[U-Boot] [PATCH v2 11/11] freescale: cmd: qixis: tidy up the duplicated code

[Yuan Yao]

From: Yuan Yao 

Signed-off-by: Yuan Yao 
---
 board/freescale/common/qixis.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f..de9daeb 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -211,8 +211,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_NAND);
set_rcw_src(QIXIS_RCW_SRC_NAND);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
@@ -222,8 +221,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD);
set_rcw_src(QIXIS_RCW_SRC_SD);
-   QIXIS_WRITE(rcfg_ctl, 0x20);
-   QIXIS_WRITE(rcfg_ctl, 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
@@ -233,8 +231,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD_QSPI);
set_rcw_src(QIXIS_RCW_SRC_SD);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
@@ -244,8 +241,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_QSPI);
set_rcw_src(QIXIS_RCW_SRC_QSPI);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-   qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+   qixis_bank_reset();
 #else
printf("Not implemented\n");
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 10/11] board/ls2080qds: add the procedure to deply QSPI image.

[Yuan Yao]

From: Yuan Yao 

Signed-off-by: Yuan Yao 
---
 board/freescale/ls2080aqds/README | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/board/freescale/ls2080aqds/README 
b/board/freescale/ls2080aqds/README
index 6ddad92..21e8c7b 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -227,3 +227,38 @@ DPMAC14 -> PHY4-P1
 DPMAC15 -> PHY4-P2
 DPMAC16 -> PHY4-P3
 
+
+Booting from QSPI
+---
+Booting from QSPI requires two images, RCW and u-boot-dtb.bin.
+The difference between QSPI boot RCW image and NOR boot image is the PBI
+command sequence. Below is the setting for PBI commands for QDS which boot
+on QSPI flash device.
+
+1) CCSR 4-byte write to 0x00e00404, data=0x
+2) CCSR 4-byte write to 0x00e00400, data=0x2001
+The above two commands set bootloc register to 0x_2001 where
+the u-boot code will be running in QSPI flash.
+
+RCW image should be written to the beginning of QSPI flash device.
+Example of using u-boot command
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 0 +
+SF: 65536 bytes @ 0x0 Erased: OK
+=> sf write  0 
+SF: 164 bytes @ 0x0 Written: OK
+
+To get the QSPI image, build u-boot with QSPI config, for example,
+ls2080aqds_qspi_defconfig. The image needed is u-boot-dtb.bin.
+The u-boot image should be written to 0x1.
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 
32 MiB
+=> sf erase 1 +
+SF: 589824 bytes @ 0x1 Erased: OK
+=> sf write  1 
+SF: 580966 bytes @ 0x1 Written: OK
+
+With these two images in QSPI flash device, the board can boot from QSPI.
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 08/11] ls2080aqds_nand_defconfig: Enable QSPI & its dependence

[Yuan Yao]

From: Yuan Yao 

The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao 
---
 configs/ls2080aqds_nand_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/ls2080aqds_nand_defconfig 
b/configs/ls2080aqds_nand_defconfig
index b7d64f6..3a970b0 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -2,6 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS2080AQDS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 07/11] configs: ls2080a: Increase load image len in NAND boot

[Yuan Yao]

From: Yuan Yao 

Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.

Signed-off-by: Yuan Yao 
---
 include/configs/ls2080a_common.h | 2 +-
 include/configs/ls2080aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 82af464..8048753 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -305,7 +305,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index ee51348..eaca55c 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -240,7 +240,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SPL_PAD_TO  0x2
 #define CONFIG_SYS_NAND_U_BOOT_OFFS(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT   CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0   CONFIG_SYS_NOR0_CSPR_EARLY
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 05/11] dm: dts: ls2080aqds: Add QSPI dts node

[Yuan Yao]

From: Yuan Yao 

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao 
---
 arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
 arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -51,3 +52,16 @@
reg = <2>;
};
 };
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs256s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "QuadSPI", "QuadSPI-memory";
+   num-cs = <4>;
+   };
 };
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 04/11] configs: ls2080aqds: Enable QSPI flash support

[Yuan Yao]

From: Yuan Yao 

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao 
---
 include/configs/ls2080aqds.h | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 3edb0b9..3cba10a 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -292,11 +292,22 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT  0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #endif
 
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
 /*
  * MMC
  */
-- 
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[U-Boot] [PATCH v2 01/11] armv8: ls2080aqds: Select QSPI CLK div via SCFG

[Yuan Yao]

From: Yuan Yao 

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao 
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 board/freescale/ls2080aqds/ls2080aqds.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..e5acae8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -101,6 +101,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
 #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1)  /* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index aa256a2..6e73829 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -25,6 +25,7 @@
 
 #define PIN_MUX_SEL_SDHC   0x00
 #define PIN_MUX_SEL_DSPI   0x0a
+#define SCFG_QSPICLKCTRL_DIV_20(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -218,6 +219,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+   /* input clk: 1/2 platform clk, output: input/20 */
+   out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
 }
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 00/11] armv8: ls2080aqds: Enable QSPI boot support

[Yuan Yao]

From: Yuan Yao 

This series add support for QSPI boot on LS2080AQDS.

Yuan Yao (11):
  armv8: ls2080aqds: Select QSPI CLK div via SCFG
  configs: ls2080a_common: Remove duplicate NOR configs
  configs: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
  configs: ls2080aqds: Enable QSPI flash support
  dm: dts: ls2080aqds: Add QSPI dts node
  armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
  configs: ls2080a: Increase load image len in NAND boot
  ls2080aqds_nand_defconfig: Enable QSPI & its dependence
  armv8: ls2080aqds: Enable QSPI boot support
Changed in v2:
 merged the patch:
 0009-armv8-ls2080aqds-Enable-QSPI-boot-support.patch
 0010-ls2080aqds-Enable-support-for-boot-from-QSPI.patch
 0012-LS2080QDS-QSPI-boot-fix-issues.patch
 in this patch.
  board/ls2080qds: add the procedure to deply QSPI image.
New add in v2.
  freescale: cmd: qixis: tidy up the duplicated code

 arch/arm/dts/fsl-ls2080a-qds.dts   | 14 +++
 arch/arm/dts/fsl-ls2080a.dtsi  | 10 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  4 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  3 ++
 board/freescale/common/qixis.c | 12 ++
 board/freescale/ls2080aqds/README  | 35 ++
 board/freescale/ls2080aqds/ls2080aqds.c| 16 
 common/board_f.c   |  6 +--
 configs/ls2080aqds_nand_defconfig  |  9 +
 configs/ls2080aqds_qspi_defconfig  | 10 +
 include/configs/ls2080a_common.h   | 11 ++
 include/configs/ls2080a_simu.h |  7 
 include/configs/ls2080aqds.h   | 43 +-
 13 files changed, 159 insertions(+), 21 deletions(-)
 create mode 100644 configs/ls2080aqds_qspi_defconfig

-- 
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[U-Boot] [PATCH v2 02/11] configs: ls2080a_common: Remove duplicate NOR configs

[Yuan Yao]

From: Yuan Yao 

The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao 
---
 include/configs/ls2080a_common.h | 7 ---
 include/configs/ls2080a_simu.h   | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 64b82e8..82af464 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -148,13 +148,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS0xC000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY  0x800
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 2c2ce7b..6a59afe 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -38,6 +38,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT   (0x0)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 09/12] armv8: ls2080aqds: Enable QSPI boot support

[Yao Yuan]

On 03/04/2016 12:49 AM, York Sun wrote:
> On 03/02/2016 06:30 PM, Yao Yuan wrote:
> > On 03/03/2016 12:52 AM, York Sun wrote:
> >> On 03/02/2016 02:41 AM, Yuan Yao wrote:
> >>> From: Yuan Yao 
> >>>
> >>> This patch adds QSPI boot support for LS2080AQDS board.
> >>> The QSPI boot image need to be programmed into the QSPI flash first.
> >>> Then the booting will start from QSPI memory space.
> >>>
> >>> Signed-off-by: Yuan Yao 
> >>> ---
> >>
> >> Please update the README file to include procedure to deply QSPI image.
> >>
> >> York
> >
> > Hi York,
> >
> > Thanks for your review.
> > So where should I put the README file?
> >
> 
> board/freescale/ls2080aqds/README
> 
> York

Hi York,

Do you know is there any example exist in uboot that I can take reference?
Or is there any format and content requirement for the procedure to deply QSPI 
image?

Thanks.
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Re: [U-Boot] [PATCH 1/8] fdtgrep: Improve error handling with invalid device tree

[Simon Glass]

Hi Masahiro,

On 6 March 2016 at 20:07, Masahiro Yamada  wrote:
> Hi Simon,
>
>
> 2016-03-07 11:45 GMT+09:00 Simon Glass :
>> This tool requires that the aliases node be the first node in the tree. But
>> when it is not, it does not handle things gracefully. In fact it crashes.
>>
>> Fix this, and add a more helpful error message.
>>
>> Signed-off-by: Simon Glass 
>> Reported-by: Masahiro Yamada 
>
>
> I think this patch would diplay a clearer hint,
> but would not solve the root cause.
>
>
>
> fdtgrep still crashes with the following DTS:

Crashes?

>
>
> / {
> model = "UniPhier PH1-LD20 Reference Board";
> compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
>
> memory {
> device_type = "memory";
> reg = <0 0x8000 0 0xc000>;
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
>
> aliases {
> serial0 = 
> serial1 = 
> serial2 = 
> serial3 = 
> i2c0 = 
> i2c1 = 
> i2c2 = 
> i2c3 = 
> i2c4 = 
> i2c5 = 
> i2c6 = 
> };
> };
>
>
> Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT
> /aliases node must come before all other nodes
> Error: FDT_ERR_BADMAGIC

You mean it gives an error?

>
>
>
>
>
> But, fdtgrep can accept the following:
>
> / {
> model = "UniPhier PH1-LD20 Reference Board";
> compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
>
> aliases {
> serial0 = 
> serial1 = 
> serial2 = 
> serial3 = 
> i2c0 = 
> i2c1 = 
> i2c2 = 
> i2c3 = 
> i2c4 = 
> i2c5 = 
> i2c6 = 
> };
>
> memory {
> device_type = "memory";
> reg = <0 0x8000 0 0xc000>;
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
> };
>
>
>
> Should I really move the "aliases" node?
> I do not think this restriction is reasonable.

Agreed. Given that it now sorts the regions I'm not sure why that
restriction is still there, actually.

Looking a bit closer, it is really checking that the aliases node
isn't last. It could probably work around it by using
fdt_size_dt_structs() when node_end is -ve.

Regards,
Simon
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Re: [U-Boot] [PATCH] rockchip: rk3288: correct sdram setting

[Chris Zhong]

Hi Simon

On 2016年03月07日 10:39, Simon Glass wrote:

Hi Chris,

On 29 February 2016 at 19:29, Chris Zhong  wrote:

Hi Simon


On 03/01/2016 10:04 AM, Simon Glass wrote:

Hi Chris,

On 29 February 2016 at 05:16, Chris Zhong  wrote:

The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2,
and it expects uboot to store the value using a same protocol. But now
the ddr setting value is different with DMC, so if you enable the DMC,
system would crash in kernel. Correct the sdram setting here, according
to the requirements of kernel.

[0]
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/
chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c

Signed-off-by: Chris Zhong 
---

   arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 42 -
   arch/arm/mach-rockchip/rk3288/sdram_rk3288.c| 61
+++--
   2 files changed, 48 insertions(+), 55 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
index fccabcd..f2e3130 100644
--- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
@@ -459,26 +459,26 @@ enum {
* [3:2] bw_ch0
* [1:0] dbw_ch0
   */
-#define SYS_REG_DDRTYPE_SHIFT  13
-#define SYS_REG_DDRTYPE_MASK   7
-#define SYS_REG_NUM_CH_SHIFT   12
-#define SYS_REG_NUM_CH_MASK1
-#define SYS_REG_ROW_3_4_SHIFT(ch)  (30 + (ch))
-#define SYS_REG_ROW_3_4_MASK   1
-#define SYS_REG_CHINFO_SHIFT(ch)   (28 + (ch))
-#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
-#define SYS_REG_RANK_MASK  1
-#define SYS_REG_COL_SHIFT(ch)  (9 + (ch) * 16)
-#define SYS_REG_COL_MASK   3
-#define SYS_REG_BK_SHIFT(ch)   (8 + (ch) * 16)
-#define SYS_REG_BK_MASK1
-#define SYS_REG_CS0_ROW_SHIFT(ch)  (6 + (ch) * 16)
-#define SYS_REG_CS0_ROW_MASK   3
-#define SYS_REG_CS1_ROW_SHIFT(ch)  (4 + (ch) * 16)
-#define SYS_REG_CS1_ROW_MASK   3
-#define SYS_REG_BW_SHIFT(ch)   (2 + (ch) * 16)
-#define SYS_REG_BW_MASK3
-#define SYS_REG_DBW_SHIFT(ch)  ((ch) * 16)
-#define SYS_REG_DBW_MASK   3
+#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
+#define SYS_REG_DEC_ROW_3_4(n, ch) ((n >> (30 + ch)) & 0x1)
+#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
+#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
+#define SYS_REG_ENC_NUM_CH(n)  (((n) - 1) << 12)
+#define SYS_REG_DEC_NUM_CH(n)  (1 + ((n >> 12) & 0x1))
+#define SYS_REG_ENC_RANK(n, ch)(((n) - 1) << (11 + ((ch)
* 16)))
+#define SYS_REG_DEC_RANK(n, ch)(1 + ((n >> (11 + 16 *
ch)) & 0x1))
+#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16)))
+#define SYS_REG_DEC_COL(n, ch) (9 + ((n >> (9 + 16 * ch)) &
0x3))
+#define SYS_REG_ENC_BK(n, ch)  (((n) == 3 ? 0 : 1) \
+   << (8 + ((ch) * 16)))
+#define SYS_REG_DEC_BK(n, ch)  (3 - ((n >> (8 + 16 * ch)) &
0x1))
+#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + ((ch) * 16)))
+#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + ((n >> (6 + 16 * ch)) &
0x3))
+#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + ((ch) * 16)))
+#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + ((n >> (4 + 16 * ch)) &
0x3))
+#define SYS_REG_ENC_BW(n, ch)  ((2 >> (n)) << (2 + ((ch) * 16)))
+#define SYS_REG_DEC_BW(n, ch)  (2 >> ((n >> (2 + 16 * ch)) &
0x3))
+#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16)))
+#define SYS_REG_DEC_DBW(n, ch) (2 >> ((n >> (0 + 16 * ch)) &
0x3))

Are the above shift/masks actually wrong? I'm not keen on this style
of packing and unpacking registers since it is really hard to read and
it's not obvious that pack and unpack work the same way.

Actually, I copy these code from coreboot[0], can we just keep the code
consistent with it?

I'm really not keen on that style. It is really hard to read.

So please can you fix the bug without changing the code style?

Actually the mask I set up for rockchip is wrong also. It should be:

#define SYS_REG_DDRTYPE_SHIFT  13
#define SYS_REG_DDRTYPE_MASK   (7 << SYS_REG_DDRTYPE_SHIFT)

I'll take a look at fixing these.

Okay, I'll send a new patch today using a better style, read the definition
is not easy.



[0]https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/
firmware-veyron-6588.B/src/soc/rockchip/rk3288/sdram.c



   #endif
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index e9e2211..4db39ec 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -551,27 +551,27 @@ static void dram_cfg_rbc(const struct chan_info
*chan, u32 chnum,
   static void 

[U-Boot] [PATCH 51/69] x86: broadwell: Add a few microcode files

[Simon Glass]

Add two microcode files for broadwell.

Signed-off-by: Simon Glass 
---

 arch/x86/dts/microcode/m7240651_001c.dtsi | 1328 +
 arch/x86/dts/microcode/mc0306d4_0018.dtsi |  944 ++
 2 files changed, 2272 insertions(+)
 create mode 100644 arch/x86/dts/microcode/m7240651_001c.dtsi
 create mode 100644 arch/x86/dts/microcode/mc0306d4_0018.dtsi

diff --git a/arch/x86/dts/microcode/m7240651_001c.dtsi 
b/arch/x86/dts/microcode/m7240651_001c.dtsi
new file mode 100644
index 000..ab96017
--- /dev/null
+++ b/arch/x86/dts/microcode/m7240651_001c.dtsi
@@ -0,0 +1,1328 @@
+/*
+ * Copyright (c) <1995-2015>, Intel Corporation.
+ * All rights reserved.
+ * Redistribution. Redistribution and use in binary form, without 
modification, are
+ * permitted provided that the following conditions are met:
+ * .Redistributions must reproduce the above copyright notice and the 
following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ * .Neither the name of Intel Corporation nor the names of its suppliers 
may be used
+ * to endorse or promote products derived from this software without specific 
prior
+ * written permission.
+ * .No reverse engineering, decompilation, or disassembly of this software 
is
+ * permitted.
+ * ."Binary form" includes any format commonly used for electronic 
conveyance
+ * which is a reversible, bit-exact translation of binary representation to 
ASCII or
+ * ISO text, for example, "uuencode."
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date: Wed Jan 7 17:15:10 CST 2015
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x1c>;
+intel,date-code = <0x7032014>;
+intel,processor-signature = <0x40651>;
+intel,checksum = <0x4f9aa4c4>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x72>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+   0x0100  0x1c00  0x14200307  0x51060400
+   0xc4a49a4f  0x0100  0x7200  0xd04f
+   0x0050  0x  0x  0x
+   0x  0xa100  0x01000200  0x1c00
+   0x0200  0x3113  0x02071420  0x3113
+   0x0100  0x51060400  0x  0x
+   0x  0x  0x  0x
+   0x  0x  0x  0x
+   0x  0x  0x  0x
+   0x36358054  0x2a09425b  0x907d339f  0xe56a8e53
+   0x877c79ee  0xe74bb340  0x4ada5820  0x1f5b6602
+   0xa30893a1  0xb7c4195b  0x5b421b4a  0xf6746a7d
+   0x93416281  0x0596553a  0x0b287554  0x589d31e7
+   0xa74c6248  0x30f07a50  0x6ad9323b  0x68401630
+   0xf5d28452  0x15295b72  0x80923cf6  0x42c1b744
+   0xb3a77ce6  0xe763f1d6  0x3c1ff5cd  0xa180d141
+   0xb13139cc  0xa944a5f7  0x7df76b7f  0x5fa445fc
+   0x365898f0  0x2e7e2d65  0xf3b12403  0x8c54b924
+   0xa5e7ca7b  0x79bfdedc  0x22590127  0x06c6830c
+   0xb7ee2c3d  0xc8eec561  0xc699686b  0x3105503e
+   0x44fa8bf0  0xf4a804b3  0x13f7e8ce  0x86c71229
+   0x4cc3e6fa  0x602929a5  0x89e3637d  0x017a25aa
+   0x5450b21f  0x76c63f96  0xd39fcb5b  0xa469f358
+   0xb2bee3f6  0xb05e8ba5  0xa4ebc733  0x668bfe37
+   0x03447100  0x4e0cfdf0  0x962912aa  0x84b1559a
+   0x07152000  0x3a6efbc9  0xc860ab11  0x846eff80
+   0xddab7ac3  0x7531c20f  0x348cb1b0  0x6c80ecf1
+   0x1100  0x8e6aec93  0x0e9ee5e7  0x63a85483
+   0x70cc3265  0x6e1f946b  0x15b0efe6  0x72063a81
+   0x34a1d64b  0x2eaed2e7  0x17fd01b8  0xb10d73c6
+   0xc670afff  0x563a9699  0x48242b55  0x4f24da06
+   0x9470dbbd  0x43bd1bc4   

Re: [U-Boot] [PATCH 1/8] fdtgrep: Improve error handling with invalid device tree

[Masahiro Yamada]

Hi Simon,


2016-03-07 11:45 GMT+09:00 Simon Glass :
> This tool requires that the aliases node be the first node in the tree. But
> when it is not, it does not handle things gracefully. In fact it crashes.
>
> Fix this, and add a more helpful error message.
>
> Signed-off-by: Simon Glass 
> Reported-by: Masahiro Yamada 


I think this patch would diplay a clearer hint,
but would not solve the root cause.



fdtgrep still crashes with the following DTS:


/ {
model = "UniPhier PH1-LD20 Reference Board";
compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";

memory {
device_type = "memory";
reg = <0 0x8000 0 0xc000>;
};

chosen {
stdout-path = "serial0:115200n8";
};

aliases {
serial0 = 
serial1 = 
serial2 = 
serial3 = 
i2c0 = 
i2c1 = 
i2c2 = 
i2c3 = 
i2c4 = 
i2c5 = 
i2c6 = 
};
};


Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT
/aliases node must come before all other nodes
Error: FDT_ERR_BADMAGIC





But, fdtgrep can accept the following:

/ {
model = "UniPhier PH1-LD20 Reference Board";
compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";

aliases {
serial0 = 
serial1 = 
serial2 = 
serial3 = 
i2c0 = 
i2c1 = 
i2c2 = 
i2c3 = 
i2c4 = 
i2c5 = 
i2c6 = 
};

memory {
device_type = "memory";
reg = <0 0x8000 0 0xc000>;
};

chosen {
stdout-path = "serial0:115200n8";
};
};



Should I really move the "aliases" node?
I do not think this restriction is reasonable.


-- 
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH 56/69] x86: broadwell: Add an LPC driver

[Simon Glass]

Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/broadwell/Makefile   |  1 +
 arch/x86/cpu/broadwell/lpc.c  | 77 +++
 arch/x86/include/asm/arch-broadwell/lpc.h | 32 +
 3 files changed, 110 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/lpc.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/lpc.h

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 39bf733..3054a89 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -6,6 +6,7 @@
 
 obj-y += cpu.o
 obj-y += iobp.o
+obj-y += lpc.o
 obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
diff --git a/arch/x86/cpu/broadwell/lpc.c b/arch/x86/cpu/broadwell/lpc.c
new file mode 100644
index 000..ee3ac18
--- /dev/null
+++ b/arch/x86/cpu/broadwell/lpc.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot broadwell support
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static void set_spi_speed(void)
+{
+   u32 fdod;
+   u8 ssfc;
+
+   /* Observe SPI Descriptor Component Section 0 */
+   writel(0x1000, SPI_REG(SPIBAR_FDOC));
+
+   /* Extract the Write/Erase SPI Frequency from descriptor */
+   fdod = readl(SPI_REG(SPIBAR_FDOD));
+   fdod >>= 24;
+   fdod &= 7;
+
+   /* Set Software Sequence frequency to match */
+   ssfc = readb(SPI_REG(SPIBAR_SSFC + 2));
+   ssfc &= ~7;
+   ssfc |= fdod;
+   writeb(ssfc, SPI_REG(SPIBAR_SSFC + 2));
+}
+
+static int broadwell_lpc_early_init(struct udevice *dev)
+{
+   set_spi_speed();
+
+   return 0;
+}
+
+static int lpc_init_extra(struct udevice *dev)
+{
+   return 0;
+}
+
+static int broadwell_lpc_probe(struct udevice *dev)
+{
+   int ret;
+
+   if (!(gd->flags & GD_FLG_RELOC)) {
+   ret = lpc_common_early_init(dev);
+   if (ret) {
+   debug("%s: lpc_early_init() failed\n", __func__);
+   return ret;
+   }
+
+   return broadwell_lpc_early_init(dev);
+   }
+
+   return lpc_init_extra(dev);
+}
+
+static const struct udevice_id broadwell_lpc_ids[] = {
+   { .compatible = "intel,broadwell-lpc" },
+   { }
+};
+
+U_BOOT_DRIVER(broadwell_lpc_drv) = {
+   .name   = "lpc",
+   .id = UCLASS_LPC,
+   .of_match   = broadwell_lpc_ids,
+   .probe  = broadwell_lpc_probe,
+};
diff --git a/arch/x86/include/asm/arch-broadwell/lpc.h 
b/arch/x86/include/asm/arch-broadwell/lpc.h
new file mode 100644
index 000..c6b54b0
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/lpc.h
@@ -0,0 +1,32 @@
+/*
+ * From coreboot soc/intel/broadwell/include/soc/lpc.h
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _asm_arch_lpc_h
+#define _asm_arch_lpc_h
+
+#define GEN_PMCON_10xa0
+#define  SMI_LOCK  (1 << 4)
+#define GEN_PMCON_20xa2
+#define  SYSTEM_RESET_STS  (1 << 4)
+#define  THERMTRIP_STS (1 << 3)
+#define  SYSPWR_FLR(1 << 1)
+#define  PWROK_FLR (1 << 0)
+#define GEN_PMCON_30xa4
+#define  SUS_PWR_FLR   (1 << 14)
+#define  GEN_RST_STS   (1 << 9)
+#define  RTC_BATTERY_DEAD  (1 << 2)
+#define  PWR_FLR   (1 << 1)
+#define  SLEEP_AFTER_POWER_FAIL(1 << 0)
+#define GEN_PMCON_LOCK 0xa6
+#define  SLP_STR_POL_LOCK  (1 << 2)
+#define  ACPI_BASE_LOCK(1 << 1)
+#define PMIR   0xac
+#define  PMIR_CF9LOCK  (1 << 31)
+#define  PMIR_CF9GR(1 << 20)
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 40/69] x86: Record the CPU details when starting each core

[Simon Glass]

As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/intel_common/microcode_intel.c | 2 +-
 arch/x86/cpu/mp_init.c  | 5 +
 arch/x86/include/asm/microcode.h| 9 +
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/intel_common/microcode_intel.c 
b/arch/x86/cpu/intel_common/microcode_intel.c
index 3054fab..26b1316 100644
--- a/arch/x86/cpu/intel_common/microcode_intel.c
+++ b/arch/x86/cpu/intel_common/microcode_intel.c
@@ -64,7 +64,7 @@ static int microcode_decode_node(const void *blob, int node,
return 0;
 }
 
-static inline uint32_t microcode_read_rev(void)
+int microcode_read_rev(void)
 {
/*
 * Some Intel CPUs can be very finicky about the CPUID sequence used.
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index ca47e9e..94ddbbb 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -560,12 +561,16 @@ int mp_init(struct mp_params *p)
 
 int mp_init_cpu(struct udevice *cpu, void *unused)
 {
+   struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
+
/*
 * Multiple APs are brought up simultaneously and they may get the same
 * seq num in the uclass_resolve_seq() during device_probe(). To avoid
 * this, set req_seq to the reg number in the device tree in advance.
 */
cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1);
+   plat->ucode_version = microcode_read_rev();
+   plat->device_id = cpuid_eax(1);
 
return device_probe(cpu);
 }
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 67f32cc..0478935 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -18,6 +18,15 @@
  * not updates were found, -EINVAL if an update was invalid
  */
 int microcode_update_intel(void);
+
+/**
+ * microcode_read_rev() - Read the microcode version
+ *
+ * This reads the microcode version of the currently running CPU
+ *
+ * @return microcode version number
+ */
+int microcode_read_rev(void);
 #endif /* __ASSEMBLY__ */
 
 #endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 63/69] x86: broadwell: Add video support

[Simon Glass]

Add a video driver for Intel's broadwell integrated graphics controller.
This uses a binary blob for most init, with the driver just performing a few
basic tasks.

This driver supports VESA as the mode-setting mechanism. Since most boards
don't support driver model yet with VESA, a special case is added to the
Kconfig for broadwell. Eventually all boards will use driver model and this
can be removed.

Signed-off-by: Simon Glass 
---

 drivers/video/Kconfig |  14 +-
 drivers/video/Makefile|   2 +
 drivers/video/broadwell_igd.c | 797 ++
 drivers/video/i915_reg.h  | 362 +++
 4 files changed, 1174 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/broadwell_igd.c
 create mode 100644 drivers/video/i915_reg.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ff4179f..8361a71 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -112,7 +112,7 @@ config VIDEO_VESA
 
 config FRAMEBUFFER_SET_VESA_MODE
bool "Set framebuffer graphics resolution"
-   depends on VIDEO_VESA
+   depends on VIDEO_VESA || VIDEO_BROADWELL_IGD
help
  Set VESA/native framebuffer mode (needed for bootsplash and graphical
  framebuffer console)
@@ -362,6 +362,18 @@ config DISPLAY
   The devices provide a simple interface to start up the display,
   read display information and enable it.
 
+config VIDEO_BROADWELL_IGD
+   bool "Enable Intel Broadwell integrated graphics device"
+   depends on X86
+   help
+ This enabled support for integrated graphics on Intel broadwell
+ devices. Initialisation is mostly performed by a VGA boot ROM, with
+ some setup handled by U-Boot itself. The graphics adaptor works as
+ a VESA device and supports LCD panels, eDP and LVDS outputs.
+ Configuration of most aspects of device operation is performed using
+ a special tool which configures the VGA ROM, but the graphics
+ resolution can be selected in U-Boot.
+
 config VIDEO_ROCKCHIP
bool "Enable Rockchip video support"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9b635fc..2fd0891 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -19,6 +19,8 @@ obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o
 obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
 endif
 
+obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
+
 obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
 obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c
new file mode 100644
index 000..ce4f296
--- /dev/null
+++ b/drivers/video/broadwell_igd.c
@@ -0,0 +1,797 @@
+/*
+ * From coreboot src/soc/intel/broadwell/igd.c
+ *
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "i915_reg.h"
+
+struct broadwell_igd_priv {
+   GraphicDevice ctfb;
+   u8 *regs;
+};
+
+struct broadwell_igd_plat {
+   u32 dp_hotplug[3];
+
+   int port_select;
+   int power_up_delay;
+   int power_backlight_on_delay;
+   int power_down_delay;
+   int power_backlight_off_delay;
+   int power_cycle_delay;
+   int cpu_backlight;
+   int pch_backlight;
+   int cdclk;
+   int pre_graphics_delay;
+};
+
+#define GT_RETRY   1000
+#define GT_CDCLK_337   0
+#define GT_CDCLK_450   1
+#define GT_CDCLK_540   2
+#define GT_CDCLK_675   3
+
+u32 board_map_oprom_vendev(u32 vendev)
+{
+   return SA_IGD_OPROM_VENDEV;
+}
+
+static int poll32(u8 *addr, uint mask, uint value)
+{
+   ulong start;
+
+   start = get_timer(0);
+   debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
+   while ((readl(addr) & mask) != value) {
+   if (get_timer(start) > GT_RETRY) {
+   debug("poll32: timeout: %x\n", readl(addr));
+   return -ETIMEDOUT;
+   }
+   }
+
+   return 0;
+}
+
+static int haswell_early_init(struct udevice *dev)
+{
+   struct broadwell_igd_priv *priv = dev_get_priv(dev);
+   u8 *regs = priv->regs;
+   int ret;
+
+   /* Enable Force Wake */
+   writel(0x0020, regs + 0xa180);
+   writel(0x00010001, regs + 0xa188);
+   ret = poll32(regs + 0x130044, 1, 1);
+   if (ret)
+   goto err;
+
+   /* Enable Counters */
+   setbits_le32(regs + 0xa248, 0x0016);
+
+   /* GFXPAUSE settings */
+   writel(0x00070020, regs + 0xa000);
+
+   /* ECO Settings */
+   clrsetbits_le32(regs + 0xa180, ~0xff3f, 0x1500);
+
+   /* Enable DOP Clock Gating 

[U-Boot] [PATCH 31/69] x86: Add common SDRAM-init code

[Simon Glass]

The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/intel_common/Makefile   |   1 +
 arch/x86/cpu/intel_common/sdram_common.c | 271 +++
 arch/x86/include/asm/sdram_common.h  |  56 +++
 3 files changed, 328 insertions(+)
 create mode 100644 arch/x86/cpu/intel_common/sdram_common.c
 create mode 100644 arch/x86/include/asm/sdram_common.h

diff --git a/arch/x86/cpu/intel_common/Makefile 
b/arch/x86/cpu/intel_common/Makefile
index 066b7b5..808f38e 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -13,3 +13,4 @@ obj-y += microcode_intel.o
 endif
 obj-y += pch_common.o
 obj-$(CONFIG_HAVE_MRC) += report_platform.o
+obj-$(CONFIG_HAVE_MRC) += sdram_common.o
diff --git a/arch/x86/cpu/intel_common/sdram_common.c 
b/arch/x86/cpu/intel_common/sdram_common.c
new file mode 100644
index 000..5e23028
--- /dev/null
+++ b/arch/x86/cpu/intel_common/sdram_common.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const char *const ecc_decoder[] = {
+   "inactive",
+   "active on IO",
+   "disabled on IO",
+   "active"
+};
+
+ulong sdram_common_board_get_usable_ram_top(ulong total_size)
+{
+   struct memory_info *info = >arch.meminfo;
+   uintptr_t dest_addr = 0;
+   struct memory_area *largest = NULL;
+   int i;
+
+   /* Find largest area of memory below 4GB */
+
+   for (i = 0; i < info->num_areas; i++) {
+   struct memory_area *area = >area[i];
+
+   if (area->start >= 1ULL << 32)
+   continue;
+   if (!largest || area->size > largest->size)
+   largest = area;
+   }
+
+   /* If no suitable area was found, return an error. */
+   assert(largest);
+   if (!largest || largest->size < (2 << 20))
+   panic("No available memory found for relocation");
+
+   dest_addr = largest->start + largest->size;
+
+   return (ulong)dest_addr;
+}
+
+void sdram_common_dram_init_banksize(void)
+{
+   struct memory_info *info = >arch.meminfo;
+   int num_banks;
+   int i;
+
+   for (i = 0, num_banks = 0; i < info->num_areas; i++) {
+   struct memory_area *area = >area[i];
+
+   if (area->start >= 1ULL << 32)
+   continue;
+   gd->bd->bi_dram[num_banks].start = area->start;
+   gd->bd->bi_dram[num_banks].size = area->size;
+   num_banks++;
+   }
+}
+
+int sdram_add_memory_area(struct memory_info *info, uint64_t start,
+ uint64_t end)
+{
+   struct memory_area *ptr;
+
+   if (info->num_areas == CONFIG_NR_DRAM_BANKS)
+   return -ENOSPC;
+
+   ptr = >area[info->num_areas];
+   ptr->start = start;
+   ptr->size = end - start;
+   info->total_memory += ptr->size;
+   if (ptr->start < (1ULL << 32))
+   info->total_32bit_memory += ptr->size;
+   debug("%d: memory %llx size %llx, total now %llx / %llx\n",
+ info->num_areas, ptr->start, ptr->size,
+ info->total_32bit_memory, info->total_memory);
+   info->num_areas++;
+
+   return 0;
+}
+
+/*
+ * Dump in the log memory controller configuration as read from the memory
+ * controller registers.
+ */
+void report_memory_config(void)
+{
+   u32 addr_decoder_common, addr_decode_ch[2];
+   int i;
+
+   addr_decoder_common = readl(MCHBAR_REG(0x5000));
+   addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
+   addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
+
+   debug("memcfg DDR3 clock %d MHz\n",
+ (readl(MCHBAR_REG(0x5e04)) * 1 * 2 + 50) / 100);
+   debug("memcfg channel assignment: A: %d, B % d, C % d\n",
+ addr_decoder_common & 3,
+ (addr_decoder_common >> 2) & 3,
+ (addr_decoder_common >> 4) & 3);
+
+   for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+   u32 ch_conf = addr_decode_ch[i];
+   debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+   debug("   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
+   debug("   enhanced interleave mode %s\n",
+ ((ch_conf >> 22) & 1) ? "on" : "off");
+   debug("   rank interleave %s\n",
+ ((ch_conf >> 21) & 1) ? "on" : "off");
+   debug("   DIMMA %d MB width x%d %s rank%s\n",
+ ((ch_conf >> 0) & 0xff) * 256,
+ ((ch_conf >> 19) & 1) ? 16 : 8,
+ ((ch_conf >> 17) & 1) ? 

[U-Boot] [PATCH 49/69] x86: dts: Update the pinctrl binding a little

[Simon Glass]

Make a few minor updates to make the meaning clearer.

Signed-off-by: Simon Glass 
---

 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt 
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
index be5d51c..22d3bec 100644
--- a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -8,17 +8,18 @@ The PINCTRL master node requires the following properties:
 
 Pin nodes must be children of the pinctrl master node and can
 contain the following properties:
-- pad-offset- (required) offset in the IOBASE for the pin to 
configured.
-- gpio-offset   - (required) offset in the GPIOBASE for the pin to 
configured and
-   also the bit shift in this register.
-- mode-gpio- (optional) standalone property to force the 
pin into GPIO mode.
-- mode-func- (optional) function number to assign to the 
pin. if 'mode-gpio'
-   is set, this property will be ignored.
+- pad-offset   - (required) offset in the IOBASE for the pin to configure
+- gpio-offset  - (required) 2 cells
+   - offset in the GPIOBASE for the pin to configure
+   - the bit shift in this register (4 = bit 4)
+- mode-gpio- (optional) standalone property to force the pin into GPIO mode
+- mode-func- (optional) function number to assign to the pin. If
+   'mode-gpio' is set, this property will be ignored.
 in case of 'mode-gpio' property set:
-- output-value - (optional) this set the default output value of the 
GPIO.
-- direction - (optional) this set the direction of the gpio.
-- pull-str  - (optional) this set the pull strength of the pin.
-- pull-assign   - (optional) this set the pull assignement (up/down) of 
the pin.
+- output-value - (optional) this set the default output value of the GPIO
+- direction- (optional) this set the direction of the gpio
+- pull-str - (optional) this set the pull strength of the pin
+- pull-assign  - (optional) this set the pull assignement (up/down) of the pin
 - invert- (optional) this input pin is inverted
 
 Example:
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 52/69] x86: broadwell: Add a PCH driver

[Simon Glass]

Add a driver for the broadwell low-power platform controller hub.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/broadwell/Makefile   |   2 +
 arch/x86/cpu/broadwell/iobp.c | 144 
 arch/x86/cpu/broadwell/pch.c  | 540 ++
 arch/x86/include/asm/arch-broadwell/pch.h | 153 +
 4 files changed, 839 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/iobp.c
 create mode 100644 arch/x86/cpu/broadwell/pch.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/pch.h

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index c7ef630..128829a 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -5,3 +5,5 @@
 #
 
 obj-y += cpu.o
+obj-y += iobp.o
+obj-y += pch.o
diff --git a/arch/x86/cpu/broadwell/iobp.c b/arch/x86/cpu/broadwell/iobp.c
new file mode 100644
index 000..5eed849
--- /dev/null
+++ b/arch/x86/cpu/broadwell/iobp.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * Modified from coreboot
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define IOBP_RETRY 1000
+
+/* IO Buffer Programming */
+#define IOBPIRI0x2330
+#define IOBPD  0x2334
+#define IOBPS  0x2338
+#define  IOBPS_READY   0x0001
+#define  IOBPS_TX_MASK 0x0006
+#define  IOBPS_MASK 0xff00
+#define  IOBPS_READ 0x0600
+#define  IOBPS_WRITE   0x0700
+#define IOBPU  0x233a
+#define  IOBPU_MAGIC   0xf000
+#define  IOBP_PCICFG_READ  0x0400
+#define  IOBP_PCICFG_WRITE 0x0500
+
+static inline int iobp_poll(void)
+{
+   unsigned try;
+
+   for (try = IOBP_RETRY; try > 0; try--) {
+   u16 status = readw(RCB_REG(IOBPS));
+   if ((status & IOBPS_READY) == 0)
+   return 1;
+   udelay(10);
+   }
+
+   printf("IOBP: timeout waiting for transaction to complete\n");
+   return 0;
+}
+
+int pch_iobp_trans_start(u32 address, int op)
+{
+   if (!iobp_poll())
+   return 0;
+
+   /* Set the address */
+   writel(address, RCB_REG(IOBPIRI));
+
+   /* READ OPCODE */
+   clrsetbits_le16(RCB_REG(IOBPS), IOBPS_MASK, op);
+
+   return 1;
+}
+
+int pch_iobp_trans_finish(void)
+{
+   u16 status;
+
+   /* Undocumented magic */
+   writew(IOBPU_MAGIC, RCB_REG(IOBPU));
+
+   /* Set ready bit */
+   setbits_le16(RCB_REG(IOBPS), IOBPS_READY);
+
+   if (!iobp_poll())
+   return 1;
+
+   /* Check for successful transaction */
+   status = readw(RCB_REG(IOBPS));
+   if (status & IOBPS_TX_MASK)
+   return 1;
+
+   return 0;
+}
+
+u32 pch_iobp_read(u32 address)
+{
+   if (!pch_iobp_trans_start(address, IOBPS_READ))
+   return 0;
+   if (pch_iobp_trans_finish()) {
+   printf("IOBP: read 0x%08x failed\n", address);
+   return 0;
+   }
+
+   /* Read IOBP data */
+   return readl(RCB_REG(IOBPD));
+}
+
+int pch_iobp_write(u32 address, u32 data)
+{
+   if (!pch_iobp_trans_start(address, IOBPS_WRITE))
+   return -EIO;
+
+   writel(data, RCB_REG(IOBPD));
+
+   if (pch_iobp_trans_finish()) {
+   printf("IOBP: write 0x%08x failed\n", address);
+   return -EIO;
+   }
+
+   return 0;
+}
+
+int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+   u32 data = pch_iobp_read(address);
+
+   /* Update the data */
+   data &= andvalue;
+   data |= orvalue;
+
+   return pch_iobp_write(address, data);
+}
+
+int pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
+{
+   if (!data || !resp)
+   return 0;
+
+   *resp = -1;
+   if (!iobp_poll())
+   return -EIO;
+
+   writel(addr, RCB_REG(IOBPIRI));
+   clrsetbits_le16(RCB_REG(IOBPS), 0xff00, op_code);
+   writew(IOBPU_MAGIC | route_id, RCB_REG(IOBPU));
+
+   writel(*data, RCB_REG(IOBPD));
+   /* Set IOBPS[0] to trigger IOBP transaction*/
+   setbits_le16(RCB_REG(IOBPS), 1);
+
+   if (!iobp_poll())
+   return -EIO;
+
+   *resp = (readw(RCB_REG(IOBPS)) & IOBPS_TX_MASK) >> 1;
+   *data = readl(RCB_REG(IOBPD));
+
+   return 0;
+}
diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
new file mode 100644
index 000..8f9bee6
--- /dev/null
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -0,0 +1,540 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define BIOS_CTRL  0xdc
+
+bool cpu_is_ult(void)
+{
+   u32 fm = cpu_get_family_model();
+
+   return fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT;

[U-Boot] [PATCH 67/69] x86: Add a function to set the IOAPIC ID

[Simon Glass]

Add a function to set the ID in the IOAPIC.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/ioapic.c | 16 
 arch/x86/include/asm/ioapic.h |  2 ++
 2 files changed, 18 insertions(+)

diff --git a/arch/x86/cpu/ioapic.c b/arch/x86/cpu/ioapic.c
index 112a9c6..d15e86c 100644
--- a/arch/x86/cpu/ioapic.c
+++ b/arch/x86/cpu/ioapic.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 
 u32 io_apic_read(u32 reg)
 {
@@ -19,3 +20,18 @@ void io_apic_write(u32 reg, u32 val)
writel(reg, IO_APIC_INDEX);
writel(val, IO_APIC_DATA);
 }
+
+void io_apic_set_id(int ioapic_id)
+{
+   int bsp_lapicid = lapicid();
+
+   debug("IOAPIC: Initialising IOAPIC at %08x\n", IO_APIC_ADDR);
+   debug("IOAPIC: Bootstrap Processor Local APIC = %#02x\n", bsp_lapicid);
+
+   if (ioapic_id) {
+   debug("IOAPIC: ID = 0x%02x\n", ioapic_id);
+   /* Set IOAPIC ID if it has been specified */
+   io_apic_write(0x00, (io_apic_read(0x00) & 0xf0ff) |
+ (ioapic_id << 24));
+   }
+}
diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h
index 77c443e..2feed86 100644
--- a/arch/x86/include/asm/ioapic.h
+++ b/arch/x86/include/asm/ioapic.h
@@ -39,4 +39,6 @@ u32 io_apic_read(u32 reg);
  */
 void io_apic_write(u32 reg, u32 val);
 
+void io_apic_set_id(int ioapic_id);
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 34/69] x86: Add a script to aid code conversion from coreboot

[Simon Glass]

It is useful to automate the process of converting code from coreboot a
little. Add a sed script which performs some common transformations.

Signed-off-by: Simon Glass 
---

 doc/README.x86   |  9 +
 scripts/coreboot.sed | 17 +
 2 files changed, 26 insertions(+)
 create mode 100644 scripts/coreboot.sed

diff --git a/doc/README.x86 b/doc/README.x86
index d3fea5d..a3f45c7 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -812,6 +812,15 @@ PCIe root port's configuration registers will cause system 
hang while it is
 held in reset. For more details, check how they are implemented by the Intel
 Galileo board support codes in board/intel/galileo/galileo.c.
 
+coreboot:
+
+See scripts/coreboot.sed which can assist with porting coreboot code into
+U-Boot drivers. It will not resolve all build errors, but will perform common
+transformations. Remember to add attribution to coreboot for new files added
+to U-Boot. This should go at the top of each file and list the coreboot
+filename where the code originated.
+
+
 TODO List
 -
 - Audio
diff --git a/scripts/coreboot.sed b/scripts/coreboot.sed
new file mode 100644
index 000..42e1f3a
--- /dev/null
+++ b/scripts/coreboot.sed
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Script to convert coreboot code to something similar to what U-Boot uses
+# sed -f coreboot.sed 
+# Remember to add attribution to coreboot for new files added to U-Boot.
+s/REG_RES_WRITE32(\(.*\), \(.*\), \(.*\)),/writel(\3, base + \2);/
+s/REG_RES_POLL32(\(.*\), \(.*\), \(.*\), \(.*\), \(.*\)),/ret = poll32(base + 
\2, \3, \4, \5);/
+s/REG_RES_OR32(\(.*\), \(.*\), \(.*\)),/setbits_le32(base + \2, \3);/
+s/REG_RES_RMW32(\(.*\), \(.*\), \(.*\), \(.*\)),/clrsetbits_le32(base + \2, 
~\3, \4);/
+/REG_SCRIPT_END/d
+s/read32/readl/
+s/write32(\(.*\), \(.*\))/writel(\2, \1)/
+s/conf->/plat->/
+s/static const struct reg_script \(.*\)_script\[\] = {/static int \1(struct 
udevice *dev)/
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 22/69] x86: Move common CPU code to its own place

[Simon Glass]

Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/intel_common/Makefile|   1 +
 arch/x86/cpu/intel_common/cpu_common.c| 111 ++
 arch/x86/cpu/ivybridge/cpu.c  |  82 ++
 arch/x86/include/asm/arch-ivybridge/pch.h |   2 -
 arch/x86/include/asm/cpu_common.h |  35 ++
 arch/x86/include/asm/intel_regs.h |   9 +++
 6 files changed, 162 insertions(+), 78 deletions(-)
 create mode 100644 arch/x86/cpu/intel_common/cpu_common.c
 create mode 100644 arch/x86/include/asm/cpu_common.h

diff --git a/arch/x86/cpu/intel_common/Makefile 
b/arch/x86/cpu/intel_common/Makefile
index 36c150d..e9a2b29 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -5,6 +5,7 @@
 #
 
 obj-$(CONFIG_HAVE_MRC) += car.o
+obj-y += cpu_common.o
 obj-y += lpc_common.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode_intel.o
diff --git a/arch/x86/cpu/intel_common/cpu_common.c 
b/arch/x86/cpu/intel_common/cpu_common.c
new file mode 100644
index 000..1210943
--- /dev/null
+++ b/arch/x86/cpu/intel_common/cpu_common.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int report_bist_failure(void)
+{
+   if (gd->arch.bist != 0) {
+   post_code(POST_BIST_FAILURE);
+   printf("BIST failed: %08x\n", gd->arch.bist);
+   return -EFAULT;
+   }
+
+   return 0;
+}
+
+int cpu_common_init(void)
+{
+   struct udevice *dev, *lpc;
+   int ret;
+
+   /* Halt if there was a built in self test failure */
+   ret = report_bist_failure();
+   if (ret)
+   return ret;
+
+   enable_lapic();
+
+   ret = microcode_update_intel();
+   if (ret && ret != -EEXIST)
+   return ret;
+
+   /* Enable upper 128bytes of CMOS */
+   writel(1 << 2, RCB_REG(RC));
+
+   /* Early chipset init required before RAM init can work */
+   uclass_first_device(UCLASS_NORTHBRIDGE, );
+
+   ret = uclass_first_device(UCLASS_LPC, );
+   if (ret)
+   return ret;
+   if (!lpc)
+   return -ENODEV;
+
+   /* Cause the SATA device to do its early init */
+   uclass_first_device(UCLASS_DISK, );
+
+   return 0;
+}
+
+int cpu_set_flex_ratio_to_tdp_nominal(void)
+{
+   msr_t flex_ratio, msr;
+   u8 nominal_ratio;
+
+   /* Check for Flex Ratio support */
+   flex_ratio = msr_read(MSR_FLEX_RATIO);
+   if (!(flex_ratio.lo & FLEX_RATIO_EN))
+   return -EINVAL;
+
+   /* Check for >0 configurable TDPs */
+   msr = msr_read(MSR_PLATFORM_INFO);
+   if (((msr.hi >> 1) & 3) == 0)
+   return -EINVAL;
+
+   /* Use nominal TDP ratio for flex ratio */
+   msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+   nominal_ratio = msr.lo & 0xff;
+
+   /* See if flex ratio is already set to nominal TDP ratio */
+   if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+   return 0;
+
+   /* Set flex ratio to nominal TDP ratio */
+   flex_ratio.lo &= ~0xff00;
+   flex_ratio.lo |= nominal_ratio << 8;
+   flex_ratio.lo |= FLEX_RATIO_LOCK;
+   msr_write(MSR_FLEX_RATIO, flex_ratio);
+
+   /* Set flex ratio in soft reset data register bits 11:6 */
+   clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
+   (nominal_ratio & 0x3f) << 6);
+
+   debug("CPU: Soft reset to set up flex ratio\n");
+
+   /* Set soft reset control to use register value */
+   setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
+
+   /* Issue warm reset, will be "CPU only" due to soft reset data */
+   outb(0x0, PORT_RESET);
+   outb(SYS_RST | RST_CPU, PORT_RESET);
+   cpu_hlt();
+
+   /* Not reached */
+   return -EINVAL;
+}
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index f847a2f..b8234ae 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -34,51 +35,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int set_flex_ratio_to_tdp_nominal(void)
 {
-   msr_t flex_ratio, msr;
-   u8 nominal_ratio;
-
/* Minimum CPU revision for configurable TDP support */
if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
return -EINVAL;
 
-   /* Check for Flex Ratio support */
-   flex_ratio = msr_read(MSR_FLEX_RATIO);
-   if (!(flex_ratio.lo & FLEX_RATIO_EN))
-   return -EINVAL;
-
-   /* Check for >0 configurable TDPs */
-   msr = msr_read(MSR_PLATFORM_INFO);
-   if (((msr.hi >> 1) 

[U-Boot] [PATCH 55/69] x86: broadwell: Add a northbridge driver

[Simon Glass]

Add a driver for the broadwell northbridge. This sets up the location of
several blocks of registers.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/broadwell/Makefile  |  1 +
 arch/x86/cpu/broadwell/northbridge.c | 59 
 2 files changed, 60 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/northbridge.c

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index d422a1c..39bf733 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -6,6 +6,7 @@
 
 obj-y += cpu.o
 obj-y += iobp.o
+obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
 obj-y += sata.o
diff --git a/arch/x86/cpu/broadwell/northbridge.c 
b/arch/x86/cpu/broadwell/northbridge.c
new file mode 100644
index 000..aa64808
--- /dev/null
+++ b/arch/x86/cpu/broadwell/northbridge.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2011 The Chromium Authors
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int broadwell_northbridge_early_init(struct udevice *dev)
+{
+   /* Move earlier? */
+   dm_pci_write_config32(dev, PCIEXBAR + 4, 0);
+   /* 64MiB - 0-63 buses */
+   dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1);
+
+   dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
+   dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1);
+   dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1);
+   writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR);
+   writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR);
+
+   /* Set C-F to access RAM on both reads and writes */
+   dm_pci_write_config8(dev, PAM0, 0x30);
+   dm_pci_write_config8(dev, PAM1, 0x33);
+   dm_pci_write_config8(dev, PAM2, 0x33);
+   dm_pci_write_config8(dev, PAM3, 0x33);
+   dm_pci_write_config8(dev, PAM4, 0x33);
+   dm_pci_write_config8(dev, PAM5, 0x33);
+   dm_pci_write_config8(dev, PAM6, 0x33);
+
+   /* Device enable: IGD and Mini-HD */
+   dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
+
+   return 0;
+}
+
+static int broadwell_northbridge_probe(struct udevice *dev)
+{
+   if (!(gd->flags & GD_FLG_RELOC))
+   return broadwell_northbridge_early_init(dev);
+
+   return 0;
+}
+
+static const struct udevice_id broadwell_northbridge_ids[] = {
+   { .compatible = "intel,broadwell-northbridge" },
+   { }
+};
+
+U_BOOT_DRIVER(broadwell_northbridge_drv) = {
+   .name   = "broadwell_northbridge",
+   .id = UCLASS_NORTHBRIDGE,
+   .of_match   = broadwell_northbridge_ids,
+   .probe  = broadwell_northbridge_probe,
+};
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 7/8] buildman: Allow the toolchain architecture to be specified

[Simon Glass]

At present the architecture is deduced from the toolchain filename. Allow it
to be specified by the caller.

Signed-off-by: Simon Glass 
---

 tools/buildman/toolchain.py | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 1874d73..7bcc0af 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -54,7 +54,8 @@ class Toolchain:
 component of the filename. E.g. arm-linux-gcc becomes arm
 priority: Toolchain priority (0=highest, 20=lowest)
 """
-def __init__(self, fname, test, verbose=False, priority=PRIORITY_CALC):
+def __init__(self, fname, test, verbose=False, priority=PRIORITY_CALC,
+ arch=None):
 """Create a new toolchain object.
 
 Args:
@@ -75,7 +76,10 @@ class Toolchain:
 
 # The architecture is the first part of the name
 pos = self.cross.find('-')
-self.arch = self.cross[:pos] if pos != -1 else 'sandbox'
+if arch:
+self.arch = arch
+else:
+self.arch = self.cross[:pos] if pos != -1 else 'sandbox'
 
 env = self.MakeEnvironment(False)
 
@@ -92,7 +96,8 @@ class Toolchain:
 if verbose:
 print 'Tool chain test: ',
 if self.ok:
-print 'OK, priority %d' % self.priority
+print "OK, arch='%s', priority %d" % (self.arch,
+  self.priority)
 else:
 print 'BAD'
 print 'Command: ', cmd
@@ -179,7 +184,8 @@ class Toolchains:
 def GetSettings(self):
   self.paths += self.GetPathList()
 
-def Add(self, fname, test=True, verbose=False, priority=PRIORITY_CALC):
+def Add(self, fname, test=True, verbose=False, priority=PRIORITY_CALC,
+arch=None):
 """Add a toolchain to our list
 
 We select the given toolchain as our preferred one for its
@@ -189,8 +195,9 @@ class Toolchains:
 fname: Filename of toolchain's gcc driver
 test: True to run the toolchain to test it
 priority: Priority to use for this toolchain
+arch: Toolchain architecture, or None if not known
 """
-toolchain = Toolchain(fname, test, verbose, priority)
+toolchain = Toolchain(fname, test, verbose, priority, arch)
 add_it = toolchain.ok
 if toolchain.arch in self.toolchains:
 add_it = (toolchain.priority <
-- 
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[U-Boot] [PATCH 8/8] buildman: Add a way to specific a full toolchain prefix

[Simon Glass]

At present buildman allows you to specify the directory containing the
toolchain, but not the actual toolchain prefix. If there are multiple
toolchains in a single directory, this can be inconvenient.

Add a new 'toolchain-prefix' setting to the settings file, which allows
the full prefix (or path to the C compiler) to be specified.

Update the documentation to match.

Suggested-by: Stephen Warren 
Reported-by: Joe Hershberger 
Signed-off-by: Simon Glass 
---

 tools/buildman/README   | 287 +++-
 tools/buildman/toolchain.py |  17 ++-
 2 files changed, 194 insertions(+), 110 deletions(-)

diff --git a/tools/buildman/README b/tools/buildman/README
index 6f41008..19ec3f5 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -169,6 +169,19 @@ Make sure the tags (here root: rest: and eldk:) are unique.
 The toolchain-alias section indicates that the i386 toolchain should be used
 to build x86 commits.
 
+Note that you can also specific exactly toolchain prefixes if you like:
+
+[toolchain-prefix]
+arm: /opt/arm-eabi-4.6/bin/arm-eabi-
+
+or even:
+
+[toolchain-prefix]
+arm: /opt/arm-eabi-4.6/bin/arm-eabi-gcc
+
+This tells buildman that you want to use this exact toolchain for the arm
+architecture. This will override any toolchains found by searching using the
+[toolchain] settings.
 
 3. Make sure you have the require Python pre-requisites
 
@@ -185,124 +198,180 @@ Run this check to make sure that you have a toolchain 
for every architecture.
 
 $ ./tools/buildman/buildman --list-tool-chains
 Scanning for tool chains
+   - scanning prefix '/opt/gcc-4.6.3-nolibc/x86_64-linux/bin/x86_64-linux-'
+Tool chain test:  OK, arch='x86', priority 1
+   - scanning prefix '/opt/arm-eabi-4.6/bin/arm-eabi-'
+Tool chain test:  OK, arch='arm', priority 1
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/i386-linux'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/i386-linux/.'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/i386-linux/bin'
+ - found '/toolchains/gcc-4.9.0-nolibc/i386-linux/bin/i386-linux-gcc'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/i386-linux/usr/bin'
+Tool chain test:  OK, arch='i386', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/aarch64-linux'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/aarch64-linux/.'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/aarch64-linux/bin'
+ - found 
'/toolchains/gcc-4.9.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/aarch64-linux/usr/bin'
+Tool chain test:  OK, arch='aarch64', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/microblaze-linux'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/microblaze-linux/.'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/microblaze-linux/bin'
+ - found 
'/toolchains/gcc-4.9.0-nolibc/microblaze-linux/bin/microblaze-linux-gcc'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/microblaze-linux/usr/bin'
+Tool chain test:  OK, arch='microblaze', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/mips64-linux'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/mips64-linux/.'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/mips64-linux/bin'
+ - found 
'/toolchains/gcc-4.9.0-nolibc/mips64-linux/bin/mips64-linux-gcc'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/mips64-linux/usr/bin'
+Tool chain test:  OK, arch='mips64', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/sparc64-linux'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/sparc64-linux/.'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/sparc64-linux/bin'
+ - found 
'/toolchains/gcc-4.9.0-nolibc/sparc64-linux/bin/sparc64-linux-gcc'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/sparc64-linux/usr/bin'
+Tool chain test:  OK, arch='sparc64', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/.'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/bin'
+ - found 
'/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/bin/arm-unknown-linux-gnueabi-gcc'
+  - looking in 
'/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/usr/bin'
+Tool chain test:  OK, arch='arm', priority 3
+Toolchain 
'/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/bin/arm-unknown-linux-gnueabi-gcc'
 at priority 3 will be ignored because another toolchain for arch 'arm' has 
priority 1
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/sparc-linux'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/sparc-linux/.'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/sparc-linux/bin'
+ - found '/toolchains/gcc-4.9.0-nolibc/sparc-linux/bin/sparc-linux-gcc'
+  - looking in '/toolchains/gcc-4.9.0-nolibc/sparc-linux/usr/bin'
+Tool chain test:  OK, arch='sparc', priority 4
+   - 

[U-Boot] [PATCH 5/8] buildman: Allow branch names which conflict with directories

[Simon Glass]

At present if you try to use buildman with the branch 'test' it will
complain that it is unsure whether you mean the branch or the directory.
This is a feature of the 'git log' command that buildman uses. Fix it
by resolving the ambiguity.

Signed-off-by: Simon Glass 
---

 tools/patman/gitutil.py | 5 +
 1 file changed, 5 insertions(+)

diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index 5f1b4f6..e088bae 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -44,6 +44,11 @@ def LogCmd(commit_range, git_dir=None, oneline=False, 
reverse=False,
 cmd.append('-n%d' % count)
 if commit_range:
 cmd.append(commit_range)
+
+# Add this in case we have a branch with the same name as a directory.
+# This avoids messages like this, for example:
+#   fatal: ambiguous argument 'test': both revision and filename
+cmd.append('--')
 return cmd
 
 def CountCommitsToBranch():
-- 
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[U-Boot] [PATCH 6/8] buildman: Allow the toolchain priority to be specified

[Simon Glass]

At present the priority of a toolchain is calculated from its filename based
on hard-coded rules. Allow it to be specified by the caller. We will use
this in a later patch. Also display the priority and provide a message when
it is overriden by another toolchain of higher priority.

Signed-off-by: Simon Glass 
---

 tools/buildman/toolchain.py | 30 ++
 1 file changed, 22 insertions(+), 8 deletions(-)

diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 5e77fed..1874d73 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -14,6 +14,8 @@ import urllib2
 import bsettings
 import command
 
+PRIORITY_CALC = 0
+
 # Simple class to collect links from a page
 class MyHTMLParser(HTMLParser):
 def __init__(self, arch):
@@ -50,14 +52,17 @@ class Toolchain:
 cross: Cross compile string, e.g. 'arm-linux-'
 arch: Architecture of toolchain as determined from the first
 component of the filename. E.g. arm-linux-gcc becomes arm
+priority: Toolchain priority (0=highest, 20=lowest)
 """
-def __init__(self, fname, test, verbose=False):
+def __init__(self, fname, test, verbose=False, priority=PRIORITY_CALC):
 """Create a new toolchain object.
 
 Args:
 fname: Filename of the gcc component
 test: True to run the toolchain to test it
 verbose: True to print out the information
+priority: Priority to use for this toolchain, or PRIORITY_CALC to
+calculate it
 """
 self.gcc = fname
 self.path = os.path.dirname(fname)
@@ -76,6 +81,10 @@ class Toolchain:
 
 # As a basic sanity check, run the C compiler with --version
 cmd = [fname, '--version']
+if priority == PRIORITY_CALC:
+self.priority = self.GetPriority(fname)
+else:
+self.priority = priority
 if test:
 result = command.RunPipe([cmd], capture=True, env=env,
  raise_on_error=False)
@@ -83,7 +92,7 @@ class Toolchain:
 if verbose:
 print 'Tool chain test: ',
 if self.ok:
-print 'OK'
+print 'OK, priority %d' % self.priority
 else:
 print 'BAD'
 print 'Command: ', cmd
@@ -91,7 +100,6 @@ class Toolchain:
 print result.stderr
 else:
 self.ok = True
-self.priority = self.GetPriority(fname)
 
 def GetPriority(self, fname):
 """Return the priority of the toolchain.
@@ -102,15 +110,15 @@ class Toolchain:
 Args:
 fname: Filename of toolchain
 Returns:
-Priority of toolchain, 0=highest, 20=lowest.
+Priority of toolchain, PRIORITY_CALC=highest, 20=lowest.
 """
 priority_list = ['-elf', '-unknown-linux-gnu', '-linux',
 '-none-linux-gnueabi', '-uclinux', '-none-eabi',
 '-gentoo-linux-gnu', '-linux-gnueabi', '-le-linux', '-uclinux']
 for prio in range(len(priority_list)):
 if priority_list[prio] in fname:
-return prio
-return prio
+return PRIORITY_CALC + prio
+return PRIORITY_CALC + prio
 
 def MakeEnvironment(self, full_path):
 """Returns an environment for using the toolchain.
@@ -171,7 +179,7 @@ class Toolchains:
 def GetSettings(self):
   self.paths += self.GetPathList()
 
-def Add(self, fname, test=True, verbose=False):
+def Add(self, fname, test=True, verbose=False, priority=PRIORITY_CALC):
 """Add a toolchain to our list
 
 We select the given toolchain as our preferred one for its
@@ -180,14 +188,20 @@ class Toolchains:
 Args:
 fname: Filename of toolchain's gcc driver
 test: True to run the toolchain to test it
+priority: Priority to use for this toolchain
 """
-toolchain = Toolchain(fname, test, verbose)
+toolchain = Toolchain(fname, test, verbose, priority)
 add_it = toolchain.ok
 if toolchain.arch in self.toolchains:
 add_it = (toolchain.priority <
 self.toolchains[toolchain.arch].priority)
 if add_it:
 self.toolchains[toolchain.arch] = toolchain
+elif verbose:
+print ("Toolchain '%s' at priority %d will be ignored because "
+   "another toolchain for arch '%s' has priority %d" %
+   (toolchain.gcc, toolchain.priority, toolchain.arch,
+self.toolchains[toolchain.arch].priority))
 
 def ScanPath(self, path, verbose):
 """Scan a path for a valid toolchain
-- 
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[U-Boot] [PATCH 4/8] buildman: Fix up a few code inconsistencies in toolchain.py

[Simon Glass]

Normally we use a single quote for strings unless there is a reason not to
(such as an embedded single quote). Fix a few counter-examples in this file.
Also add a missing function-argument comment.

Signed-off-by: Simon Glass 
---

 tools/buildman/toolchain.py | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index e33e105..5e77fed 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -57,6 +57,7 @@ class Toolchain:
 Args:
 fname: Filename of the gcc component
 test: True to run the toolchain to test it
+verbose: True to print out the information
 """
 self.gcc = fname
 self.path = os.path.dirname(fname)
@@ -155,8 +156,8 @@ class Toolchains:
 """
 toolchains = bsettings.GetItems('toolchain')
 if not toolchains:
-print ("Warning: No tool chains - please add a [toolchain] section"
- " to your buildman config file %s. See README for details" %
+print ('Warning: No tool chains - please add a [toolchain] section'
+ ' to your buildman config file %s. See README for details' %
  bsettings.config_fname)
 
 paths = []
@@ -367,14 +368,14 @@ class Toolchains:
 Full path to the downloaded archive file in that directory,
 or None if there was an error while downloading
 """
-print "Downloading: %s" % url
+print 'Downloading: %s' % url
 leaf = url.split('/')[-1]
 tmpdir = tempfile.mkdtemp('.buildman')
 response = urllib2.urlopen(url)
 fname = os.path.join(tmpdir, leaf)
 fd = open(fname, 'wb')
 meta = response.info()
-size = int(meta.getheaders("Content-Length")[0])
+size = int(meta.getheaders('Content-Length')[0])
 done = 0
 block_size = 1 << 16
 status = ''
@@ -388,7 +389,7 @@ class Toolchains:
 
 done += len(buffer)
 fd.write(buffer)
-status = r"%10d MiB  [%3d%%]" % (done / 1024 / 1024,
+status = r'%10d MiB  [%3d%%]' % (done / 1024 / 1024,
  done * 100 / size)
 status = status + chr(8) * (len(status) + 1)
 print status,
-- 
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[U-Boot] [PATCH 2/8] patman: Add a missing space in GetMetaDataForList()

[Simon Glass]

Fix this nit to keep the code consistent.

Signed-off-by: Simon Glass 
---

 tools/patman/patchstream.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 6d3c41f..27d031e 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -376,7 +376,7 @@ def GetMetaDataForList(commit_range, git_dir=None, 
count=None,
 if not series:
 series = Series()
 series.allow_overwrite = allow_overwrite
-params = gitutil.LogCmd(commit_range,reverse=True, count=count,
+params = gitutil.LogCmd(commit_range, reverse=True, count=count,
 git_dir=git_dir)
 stdout = command.RunPipe([params], capture=True).stdout
 ps = PatchStream(series, is_log=True)
-- 
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[U-Boot] [PATCH 3/8] buildman: patman: Fix -H when installed as a symlink

[Simon Glass]

It is convenient to install symlinks to buildman and patman in the search
patch, such as /usr/local/bin. But when this is done, the -H option fails to
work because it looks in the directory containing the symlink instead of its
target. Fix this.

Signed-off-by: Simon Glass 
---

 tools/buildman/control.py | 3 ++-
 tools/patman/patman.py| 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 8b3cd30..c2c54bf 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -101,7 +101,8 @@ def DoBuildman(options, args, toolchains=None, 
make_func=None, boards=None,
 pager = os.getenv('PAGER')
 if not pager:
 pager = 'more'
-fname = os.path.join(os.path.dirname(sys.argv[0]), 'README')
+fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
+ 'README')
 command.Run(pager, fname)
 return 0
 
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index d05c5ff..fe50eb4 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -117,7 +117,8 @@ elif options.full_help:
 pager = os.getenv('PAGER')
 if not pager:
 pager = 'more'
-fname = os.path.join(os.path.dirname(sys.argv[0]), 'README')
+fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
+ 'README')
 command.Run(pager, fname)
 
 # Process commits, produce patches files, check them, email them
-- 
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[U-Boot] [PATCH 1/8] fdtgrep: Improve error handling with invalid device tree

[Simon Glass]

This tool requires that the aliases node be the first node in the tree. But
when it is not, it does not handle things gracefully. In fact it crashes.

Fix this, and add a more helpful error message.

Signed-off-by: Simon Glass 
Reported-by: Masahiro Yamada 
---

 tools/fdtgrep.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c
index 67aa41a..8d3fef4 100644
--- a/tools/fdtgrep.c
+++ b/tools/fdtgrep.c
@@ -660,6 +660,8 @@ static int fdtgrep_find_regions(const void *fdt,
if (!ret)
count++;
}
+   if (ret && ret != -FDT_ERR_NOTFOUND)
+   return ret;
 
/* Find all the aliases and add those regions back in */
if (disp->add_aliases && count < max_regions) {
@@ -667,7 +669,11 @@ static int fdtgrep_find_regions(const void *fdt,
 
new_count = fdt_add_alias_regions(fdt, region, count,
  max_regions, );
-   if (new_count <= max_regions) {
+   if (new_count == -FDT_ERR_NOTFOUND) {
+   /* No alias node found */
+   } else if (new_count < 0) {
+   return new_count;
+   } else if (new_count <= max_regions) {
/*
* The alias regions will now be at the end of the list.
* Sort the regions by offset to get things into the
@@ -679,9 +685,6 @@ static int fdtgrep_find_regions(const void *fdt,
}
}
 
-   if (ret != -FDT_ERR_NOTFOUND)
-   return ret;
-
return count;
 }
 
@@ -807,6 +810,9 @@ static int do_fdtgrep(struct display_info *disp, const char 
*filename)
disp->flags);
if (count < 0) {
report_error("fdt_find_regions", count);
+   if (count == -FDT_ERR_BADLAYOUT)
+   fprintf(stderr,
+   "/aliases node must come before all 
other nodes\n");
return -1;
}
if (count <= max_regions)
-- 
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[U-Boot] [PATCH 57/69] x86: broadwell: Add reference code support

[Simon Glass]

Broadwell needs a special binary blob to set up the PCH. Add code to run
this on start-up.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/broadwell/Makefile  |   1 +
 arch/x86/cpu/broadwell/refcode.c | 108 +++
 2 files changed, 109 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/refcode.c

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 3054a89..a542fef 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -10,4 +10,5 @@ obj-y += lpc.o
 obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
+obj-y += refcode.o
 obj-y += sata.o
diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c
new file mode 100644
index 000..8c1d99c
--- /dev/null
+++ b/arch/x86/cpu/broadwell/refcode.c
@@ -0,0 +1,108 @@
+/*
+ * Read a coreboot rmodule and execute it.
+ * The rmodule_header struct is from coreboot.
+ *
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+
+#define RMODULE_MAGIC  0xf8fe
+#define RMODULE_VERSION_1  1
+
+/*
+ * All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.
+ */
+struct rmodule_header {
+   uint16_t magic;
+   uint8_t  version;
+   uint8_t  type;
+   /* The payload represents the program's loadable code and data. */
+   uint32_t payload_begin_offset;
+   uint32_t payload_end_offset;
+   /* Begin and of relocation information about the program module. */
+   uint32_t relocations_begin_offset;
+   uint32_t relocations_end_offset;
+   /* The starting address of the linked program. This address is vital
+* for determining relocation offsets as the relocation info and other
+* symbols (bss, entry point) need this value as a basis to calculate
+* the offsets.
+*/
+   uint32_t module_link_start_address;
+   /* The module_program_size is the size of memory used while running
+* the program. The program is assumed to consume a contiguous amount
+* of memory. */
+   uint32_t module_program_size;
+   /* This is program's execution entry point. */
+   uint32_t module_entry_point;
+   /* Optional parameter structure that can be used to pass data into
+* the module. */
+   uint32_t parameters_begin;
+   uint32_t parameters_end;
+   /* BSS section information so the loader can clear the bss. */
+   uint32_t bss_begin;
+   uint32_t bss_end;
+   /* Add some room for growth. */
+   uint32_t padding[4];
+} __packed;
+
+int cpu_run_reference_code(void)
+{
+   struct pei_data _pei_data __aligned(8);
+   struct pei_data *pei_data = &_pei_data;
+   asmlinkage int (*func)(void *);
+   struct rmodule_header *hdr;
+   char *src, *dest;
+   int ret, dummy;
+   int size;
+
+   hdr = (struct rmodule_header *)CONFIG_X86_REFCODE_ADDR;
+   debug("Extracting code from rmodule at %p\n", hdr);
+   if (hdr->magic != RMODULE_MAGIC) {
+   debug("Invalid rmodule magic\n");
+   return -EINVAL;
+   }
+   if (hdr->module_link_start_address != 0) {
+   debug("Link start address must be 0\n");
+   return -EPERM;
+   }
+   if (hdr->module_entry_point != 0) {
+   debug("Entry point must be 0\n");
+   return -EPERM;
+   }
+
+   memset(pei_data, '\0', sizeof(struct pei_data));
+   broadwell_fill_pei_data(pei_data);
+   mainboard_fill_pei_data(pei_data);
+   pei_data->saved_data = (void *)
+
+   src = (char *)hdr + hdr->payload_begin_offset;
+   dest = (char *)CONFIG_X86_REFCODE_RUN_ADDR;
+
+   size = hdr->payload_end_offset - hdr->payload_begin_offset;
+   debug("Copying refcode from %p to %p, size %x\n", src, dest, size);
+   memcpy(dest, src, size);
+
+   size = hdr->bss_end - hdr->bss_begin;
+   debug("Zeroing BSS at %p, size %x\n", dest + hdr->bss_begin, size);
+   memset(dest + hdr->bss_begin, '\0', size);
+
+   func = (asmlinkage int (*)(void *))dest;
+   debug("Running reference code at %p\n", func);
+#ifdef DEBUG
+   print_buffer(CONFIG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0);
+#endif
+   ret = func(pei_data);
+   if (ret != 0) {
+   debug("Reference code returned %d\n", ret);
+   return -EL2HLT;
+   }
+   debug("Refereence code completed\n");
+
+   return 0;
+}
-- 
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[U-Boot] [PATCH 65/69] x86: Use white on black for the console on chromebooks

[Simon Glass]

This is a little easier on the eyes, particularly when the backlight is set
to maximum.

Signed-off-by: Simon Glass 
---

 include/configs/x86-chromebook.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index 057d4be..ae969b9 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -51,6 +51,8 @@
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_OFFSET  0x003f8000
 
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
-- 
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[U-Boot] [PATCH 29/69] x86: dts: link: Add board ID GPIOs

[Simon Glass]

At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.

Signed-off-by: Simon Glass 
---

 arch/x86/dts/chromebook_link.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 12f315e..a702ea9 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -74,6 +74,8 @@
northbridge@0,0 {
reg = <0x 0 0 0 0>;
compatible = "intel,bd82x6x-northbridge";
+   board-id-gpios = <_b 9 0>, <_b 10 0>,
+   <_b 11 0>, <_a 10 0>;
u-boot,dm-pre-reloc;
spd {
compatible = "memory-spd";
-- 
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[U-Boot] [PATCH 21/69] x86: Add some more common MSR indexes

[Simon Glass]

Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/ivybridge/model_206ax.c  |  5 +--
 arch/x86/include/asm/arch-ivybridge/model_206ax.h | 17 --
 arch/x86/include/asm/msr-index.h  | 41 ++-
 3 files changed, 43 insertions(+), 20 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c 
b/arch/x86/cpu/ivybridge/model_206ax.c
index 9654600..950132a 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -363,7 +364,7 @@ static void set_max_ratio(void)
msr = msr_read(MSR_PLATFORM_INFO);
perf_ctl.lo = msr.lo & 0xff00;
}
-   msr_write(IA32_PERF_CTL, perf_ctl);
+   msr_write(MSR_IA32_PERF_CTL, perf_ctl);
 
debug("model_x06ax: frequency set to %d\n",
  ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
@@ -455,7 +456,7 @@ static int model_206ax_get_info(struct udevice *dev, struct 
cpu_info *info)
 {
msr_t msr;
 
-   msr = msr_read(IA32_PERF_CTL);
+   msr = msr_read(MSR_IA32_PERF_CTL);
info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 100;
info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
 
diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h 
b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
index d2f9006..22f7929 100644
--- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h
+++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
@@ -15,13 +15,9 @@
 #define  CPUID_VMX (1 << 5)
 #define  CPUID_SMX (1 << 6)
 #define MSR_FEATURE_CONFIG 0x13c
-#define MSR_FLEX_RATIO 0x194
-#define  FLEX_RATIO_LOCK   (1 << 20)
-#define  FLEX_RATIO_EN (1 << 16)
 #define IA32_PLATFORM_DCA_CAP  0x1f8
 #define IA32_MISC_ENABLE   0x1a0
 #define MSR_TEMPERATURE_TARGET 0x1a2
-#define IA32_PERF_CTL  0x199
 #define IA32_THERM_INTERRUPT   0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS   0x1b0
 #define  ENERGY_POLICY_PERFORMANCE 0
@@ -31,12 +27,8 @@
 #define MSR_LT_LOCK_MEMORY 0x2e7
 #define IA32_MC0_STATUS0x401
 
-#define MSR_PIC_MSG_CONTROL0x2e
-#define  PLATFORM_INFO_SET_TDP (1 << 29)
-
 #define MSR_MISC_PWR_MGMT  0x1aa
 #define  MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
-#define MSR_TURBO_RATIO_LIMIT  0x1ad
 
 #define MSR_PKGC3_IRTL 0x60a
 #define MSR_PKGC6_IRTL 0x60b
@@ -50,13 +42,6 @@
 #define  IRTL_33554432_NS  (5 << 10)
 #define  IRTL_RESPONSE_MASK(0x3ff)
 
-/* long duration in low dword, short duration in high dword */
-#define  PKG_POWER_LIMIT_MASK  0x7fff
-#define  PKG_POWER_LIMIT_EN(1 << 15)
-#define  PKG_POWER_LIMIT_CLAMP (1 << 16)
-#define  PKG_POWER_LIMIT_TIME_SHIFT17
-#define  PKG_POWER_LIMIT_TIME_MASK 0x7f
-
 #define MSR_PP0_CURRENT_CONFIG 0x601
 #define  PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
 #define MSR_PP1_CURRENT_CONFIG 0x602
@@ -65,11 +50,9 @@
 #define MSR_PKG_POWER_SKU  0x614
 
 #define IVB_CONFIG_TDP_MIN_CPUID   0x306a2
-#define MSR_CONFIG_TDP_NOMINAL 0x648
 #define MSR_CONFIG_TDP_LEVEL1  0x649
 #define MSR_CONFIG_TDP_LEVEL2  0x64a
 #define MSR_CONFIG_TDP_CONTROL 0x64b
-#define MSR_TURBO_ACTIVATION_RATIO 0x64c
 
 /* P-state configuration */
 #define PSS_MAX_ENTRIES8
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 38dbb31..b2a03f4 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -41,6 +41,9 @@
 #define EFER_FFXSR (1<<_EFER_FFXSR)
 
 /* Intel MSRs. Some also available on other CPUs */
+#define MSR_PIC_MSG_CONTROL0x2e
+#define  PLATFORM_INFO_SET_TDP (1 << 29)
+
 #define MSR_IA32_PERFCTR0  0x00c1
 #define MSR_IA32_PERFCTR1  0x00c2
 #define MSR_FSB_FREQ   0x00cd
@@ -73,14 +76,27 @@
 #define MSR_IA32_MCG_STATUS0x017a
 #define MSR_IA32_MCG_CTL   0x017b
 
+#define MSR_FLEX_RATIO 0x194
+#define  FLEX_RATIO_LOCK   (1 << 20)
+#define  FLEX_RATIO_EN (1 << 16)
+
 #define MSR_IA32_MISC_ENABLES  0x01a0
+#define MSR_TEMPERATURE_TARGET 0x1a2
 #define MSR_OFFCORE_RSP_0  0x01a6
 #define MSR_OFFCORE_RSP_1  0x01a7
+#define MSR_MISC_PWR_MGMT  0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
 #define MSR_NHM_TURBO_RATIO_LIMIT  0x01ad
 

[U-Boot] [PATCH 28/69] x86: dts: link: Move SPD info into the memory controller

[Simon Glass]

The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.

As a first step, move the information.

Signed-off-by: Simon Glass 
---

 arch/x86/dts/chromebook_link.dts | 221 +++
 1 file changed, 110 insertions(+), 111 deletions(-)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index e203139..12f315e 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -62,117 +62,6 @@
intel,duplicate-por;
};
 
-   spd {
-   compatible = "memory-spd";
-   #address-cells = <1>;
-   #size-cells = <0>;
-   elpida_4Gb_1600_x16 {
-   reg = <0>;
-   data = [92 10 0b 03 04 19 02 02
-   03 52 01 08 0a 00 fe 00
-   69 78 69 3c 69 11 18 81
-   20 08 3c 3c 01 40 83 81
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 0f 11 42 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 02 fe 00
-   11 52 00 00 00 07 7f 37
-   45 42 4a 32 30 55 47 36
-   45 42 55 30 2d 47 4e 2d
-   46 20 30 20 02 fe 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00];
-   };
-   samsung_4Gb_1600_1.35v_x16 {
-   reg = <1>;
-   data = [92 11 0b 03 04 19 02 02
-   03 11 01 08 0a 00 fe 00
-   69 78 69 3c 69 11 18 81
-   f0 0a 3c 3c 01 40 83 01
-   00 80 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 0f 11 02 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 80 ce 01
-   00 00 00 00 00 00 6a 04
-   4d 34 37 31 42 35 36 37
-   34 42 48 30 2d 59 4b 30
-   20 20 00 00 80 ce 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00
-   00 00 00 00 00 00 00 00];
-   };
-   micron_4Gb_1600_1.35v_x16 {
-   reg = <2>;
-   data = [92 11 0b 03 04 19 02 02
-   03 11 01 08 0a 00 fe 00
-   69 78 69 3c 69 11 18 81
-   20 08 3c 3c 01 40 83 05
-   00 00 00 00 00 00 00 00
-  

[U-Boot] [PATCH 50/69] x86: Add basic support for broadwell

[Simon Glass]

This adds the broadwell architecture, with the CPU driver and some useful
header files.

Signed-off-by: Simon Glass 
---

 arch/x86/Kconfig|   1 +
 arch/x86/cpu/Makefile   |   1 +
 arch/x86/cpu/broadwell/Kconfig  |  30 ++
 arch/x86/cpu/broadwell/Makefile |   7 +
 arch/x86/cpu/broadwell/cpu.c| 761 
 arch/x86/include/asm/arch-broadwell/cpu.h   |  48 ++
 arch/x86/include/asm/arch-broadwell/iomap.h |  53 ++
 arch/x86/include/asm/arch-broadwell/me.h| 200 
 arch/x86/include/asm/arch-broadwell/rcb.h   |  58 +++
 arch/x86/include/asm/arch-broadwell/spi.h   |  87 
 10 files changed, 1246 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/Kconfig
 create mode 100644 arch/x86/cpu/broadwell/Makefile
 create mode 100644 arch/x86/cpu/broadwell/cpu.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/cpu.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/iomap.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/me.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/rcb.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/spi.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 2544c65..4e125c7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -34,6 +34,7 @@ source "board/intel/Kconfig"
 
 # platform-specific options below
 source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/broadwell/Kconfig"
 source "arch/x86/cpu/coreboot/Kconfig"
 source "arch/x86/cpu/ivybridge/Kconfig"
 source "arch/x86/cpu/qemu/Kconfig"
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 2583809..2667e0b 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -20,6 +20,7 @@ extra-y += call32.o
 
 obj-y += intel_common/
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
+obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_EFI_APP) += efi/
 obj-$(CONFIG_QEMU) += qemu/
diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig
new file mode 100644
index 000..1ce3848
--- /dev/null
+++ b/arch/x86/cpu/broadwell/Kconfig
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2016 Google Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+config INTEL_BROADWELL
+   bool
+   select CACHE_MRC_BIN
+
+if INTEL_BROADWELL
+
+config DCACHE_RAM_BASE
+   default 0xff7c
+
+config DCACHE_RAM_SIZE
+   default 0x4
+
+config DCACHE_RAM_MRC_VAR_SIZE
+   default 0x3
+
+config CPU_SPECIFIC_OPTIONS
+   def_bool y
+   select SMM_TSEG
+   select X86_RAMTEST
+
+config SMM_TSEG_SIZE
+   hex
+   default 0x80
+
+endif
diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
new file mode 100644
index 000..c7ef630
--- /dev/null
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
new file mode 100644
index 000..3ba21aa
--- /dev/null
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -0,0 +1,761 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ *
+ * Based on code from coreboot src/soc/intel/broadwell/cpu.c
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct cpu_broadwell_priv {
+   bool ht_disabled;
+};
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+   [0]   = 0x00,
+   [1]   = 0x0a,
+   [2]   = 0x0b,
+   [3]   = 0x4b,
+   [4]   = 0x0c,
+   [5]   = 0x2c,
+   [6]   = 0x4c,
+   [7]   = 0x6c,
+   [8]   = 0x0d,
+   [10]  = 0x2d,
+   [12]  = 0x4d,
+   [14]  = 0x6d,
+   [16]  = 0x0e,
+   [20]  = 0x2e,
+   [24]  = 0x4e,
+   [28]  = 0x6e,
+   [32]  = 0x0f,
+   [40]  = 0x2f,
+   [48]  = 0x4f,
+   [56]  = 0x6f,
+   [64]  = 0x10,
+   [80]  = 0x30,
+   [96]  = 0x50,
+   [112] = 0x70,
+   [128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+   [0x00] = 0,
+   [0x0a] = 1,
+   [0x0b] = 2,
+   [0x4b] = 3,
+   [0x0c] = 4,
+   [0x2c] = 5,
+   [0x4c] = 6,
+   [0x6c] = 7,
+   [0x0d] = 8,
+   [0x2d] = 10,
+   [0x4d] = 12,
+   [0x6d] = 14,
+   [0x0e] = 16,
+   [0x2e] = 20,
+   [0x4e] = 24,
+   [0x6e] = 28,
+   [0x0f] = 32,
+   [0x2f] = 40,
+   [0x4f] = 48,
+   [0x6f] = 56,
+   [0x10] = 64,
+   [0x30] = 80,
+   [0x50] = 96,
+   [0x70] = 112,
+   [0x11] = 128,
+};
+
+int arch_cpu_init_dm(void)
+{
+   struct udevice *dev;
+   int ret;
+
+   /* Start up the LPC so we have serial */
+   ret = 

[U-Boot] [PATCH 36/69] x86: Add macros to clear and set I/O bits

[Simon Glass]

The clrsetbits_...() macros are useful for working with memory mapped I/O.
But they do not work with I/O space, as used on x86 machines.

Add some macros to provide similar features for I/O.

Signed-off-by: Simon Glass 
---

 arch/x86/include/asm/io.h | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index e0b2561..38b543d 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -254,6 +254,28 @@ __OUTS(b)
 __OUTS(w)
 __OUTS(l)
 
+/* IO space accessors */
+#define clrio(type, addr, clear) \
+   out##type(in##type(addr) & ~(clear), (addr))
+
+#define setio(type, addr, set) \
+   out##type(in##type(addr) | (set), (addr))
+
+#define clrsetio(type, addr, clear, set) \
+   out##type((in##type(addr) & ~(clear)) | (set), (addr))
+
+#define clrio_le32(addr, clear) clrio(l, addr, clear)
+#define clrio_le16(addr, clear) clrio(w, addr, clear)
+#define clrio_8(addr, clear) clrio(b, addr, clear)
+
+#define setio_le32(addr, set) setio(l, addr, set)
+#define setio_le16(addr, set) setio(w, addr, set)
+#define setio_8(addr, set) setio(b, addr, set)
+
+#define clrsetio_le32(addr, clear, set) clrsetio(l, addr, clear, set)
+#define clrsetio_le16(addr, clear, set) clrsetio(w, addr, clear, set)
+#define clrsetio_8(addr, clear, set) clrsetio(b, addr, clear, set)
+
 static inline void sync(void)
 {
 }
-- 
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[U-Boot] [PATCH 27/69] x86: link: Add required GPIO properties

[Simon Glass]

In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.

Signed-off-by: Simon Glass 
---

 arch/x86/dts/chromebook_link.dts | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index f85e55c..e203139 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -249,23 +249,29 @@
};
};
 
-   gpioa {
+   gpio_a: gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
+   #gpio-cells = <2>;
+   gpio-controller;
reg = <0 0x10>;
bank-name = "A";
};
 
-   gpiob {
+   gpio_b: gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
+   #gpio-cells = <2>;
+   gpio-controller;
reg = <0x30 0x10>;
bank-name = "B";
};
 
-   gpioc {
+   gpio_c: gpioc {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
+   #gpio-cells = <2>;
+   gpio-controller;
reg = <0x40 0x10>;
bank-name = "C";
};
-- 
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[U-Boot] [PATCH 68/69] x86: Fix a header nit in x86-chromebook.h

[Simon Glass]

There is an extra line in the comment in the header. Remove it.

Signed-off-by: Simon Glass 
---

 include/configs/x86-chromebook.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index ae969b9..c94096a 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -1,5 +1,4 @@
 /*
- *
  * Copyright (c) 2015 Google, Inc
  *
  * SPDX-License-Identifier:GPL-2.0+
-- 
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[U-Boot] [PATCH 48/69] x86: Add support for running Intel reference code

[Simon Glass]

Intel has invented yet another binary blob which firmware is required to
run. This is run after SDRAM is ready. It is linked to load at a particular
address, typically 0, but is a relocatable ELF so can be moved if required.

Add support for this in the build system. The file should be placed in the
board directory, and called refcode.elf.

Signed-off-by: Simon Glass 
---

 Makefile   | 14 +-
 arch/x86/Kconfig   | 11 +++
 arch/x86/include/asm/cpu.h | 12 
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 6bb5565..76dab6f 100644
--- a/Makefile
+++ b/Makefile
@@ -1044,6 +1044,10 @@ ifneq ($(CONFIG_HAVE_VGA_BIOS),)
 IFDTOOL_FLAGS += -w 
$(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
 endif
 
+ifneq ($(CONFIG_HAVE_REFCODE),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_REFCODE_ADDR):refcode.bin
+endif
+
 quiet_cmd_ifdtool = IFDTOOL $@
 cmd_ifdtool  = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
 ifneq ($(CONFIG_HAVE_INTEL_ME),)
@@ -1052,7 +1056,15 @@ endif
 cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
 cmd_ifdtool += mv u-boot.tmp $@
 
-u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE
+refcode.bin: $(srctree)/board/$(BOARDDIR)/refcode.bin FORCE
+   $(call if_changed,copy)
+
+quiet_cmd_ldr = LD  $@
+cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
+  $(filter-out FORCE,$^) -o $@
+
+u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
+   $(if $(CONFIG_HAVE_REFCODE),refcode.bin)
$(call if_changed,ifdtool)
 
 OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 29df78c..2544c65 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -305,6 +305,17 @@ config DCACHE_RAM_MRC_VAR_SIZE
  memory reference code and must be set correctly or the board will
  not boot.
 
+config HAVE_REFCODE
+bool "Add a Reference Code binary"
+help
+  Select this option to add a Reference Code binary to the resulting
+  U-Boot image. This is an Intel binary blob that handles system
+  initialisation, in this case the PCH and System Agent.
+
+  Note: Without this binary (on platforms that need it such as
+  broadwell) U-Boot will be missing some critical setup steps.
+  Various peripherals may fail to work.
+
 config SMP
bool "Enable Symmetric Multiprocessing"
default n
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 85386da..23ec764 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -275,4 +275,16 @@ u32 cpu_get_family_model(void);
  */
 u32 cpu_get_stepping(void);
 
+/**
+ * cpu_run_reference_code() - Run the platform reference code
+ *
+ * Some platforms require a binary blob to be executed once SDRAM is
+ * available. This is used to set up various platform features, such as the
+ * platform controller hub (PCB). This function should be implemented by the
+ * CPU-specific code.
+ *
+ * @return 0 on success, -ve on failure
+ */
+int cpu_run_reference_code(void);
+
 #endif
-- 
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[U-Boot] [PATCH 54/69] x86: broadwell: Add a SATA driver

[Simon Glass]

Add a SATA driver for broadwell. This supports connecting an SSD and the
usual U-Boot commands to read and write data.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/broadwell/Makefile |   1 +
 arch/x86/cpu/broadwell/sata.c   | 269 
 2 files changed, 270 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/sata.c

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index db60e30..d422a1c 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -8,3 +8,4 @@ obj-y += cpu.o
 obj-y += iobp.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
+obj-y += sata.o
diff --git a/arch/x86/cpu/broadwell/sata.c b/arch/x86/cpu/broadwell/sata.c
new file mode 100644
index 000..dfb8486
--- /dev/null
+++ b/arch/x86/cpu/broadwell/sata.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot src/soc/intel/broadwell/sata.c
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct sata_platdata {
+   int port_map;
+   uint port0_gen3_tx;
+   uint port1_gen3_tx;
+   uint port0_gen3_dtle;
+   uint port1_gen3_dtle;
+
+   /*
+* SATA DEVSLP Mux
+* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
+* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
+*/
+   int devslp_mux;
+
+   /*
+* DEVSLP Disable
+* 0: DEVSLP is enabled
+* 1: DEVSLP is disabled
+*/
+   int devslp_disable;
+};
+
+static void broadwell_sata_init(struct udevice *dev)
+{
+   struct sata_platdata *plat = dev_get_platdata(dev);
+   u32 reg32;
+   u8 *abar;
+   u16 reg16;
+   int port;
+
+   debug("SATA: Initializing controller in AHCI mode.\n");
+
+   /* Set timings */
+   dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
+   dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
+
+   /* for AHCI, Port Enable is managed in memory mapped space */
+   dm_pci_read_config16(dev, 0x92, );
+   reg16 &= ~0xf;
+   reg16 |= 0x8000 | plat->port_map;
+   dm_pci_write_config16(dev, 0x92, reg16);
+   udelay(2);
+
+   /* Setup register 98h */
+   dm_pci_read_config32(dev, 0x98, );
+   reg32 &= ~((1 << 31) | (1 << 30));
+   reg32 |= 1 << 23;
+   reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
+   dm_pci_write_config32(dev, 0x98, reg32);
+
+   /* Setup register 9Ch */
+   reg16 = 0;   /* Disable alternate ID */
+   reg16 = 1 << 5;  /* BWG step 12 */
+   dm_pci_write_config16(dev, 0x9c, reg16);
+
+   /* SATA Initialization register */
+   reg32 = 0x183;
+   reg32 |= (plat->port_map ^ 0xf) << 24;
+   reg32 |= (plat->devslp_mux & 1) << 15;
+   dm_pci_write_config32(dev, 0x94, reg32);
+
+   /* Initialize AHCI memory-mapped space */
+   dm_pci_read_config32(dev, PCI_BASE_ADDRESS_5, );
+   abar = (u8 *)reg32;
+   debug("ABAR: %p\n", abar);
+
+   /* CAP (HBA Capabilities) : enable power management */
+   clrsetbits_le32(abar + 0x00, 0x00020060 /* SXS+EMS+PMS */,
+   0x0c006000 /* PSC+SSC+SALP+SSS */ |
+   1 << 18); /* SAM: SATA AHCI MODE ONLY */
+
+   /* PI (Ports implemented) */
+   writel(plat->port_map, abar + 0x0c);
+   (void) readl(abar + 0x0c); /* Read back 1 */
+   (void) readl(abar + 0x0c); /* Read back 2 */
+
+   /* CAP2 (HBA Capabilities Extended)*/
+   if (plat->devslp_disable) {
+   clrbits_le32(abar + 0x24, 1 << 3);
+   } else {
+   /* Enable DEVSLP */
+   setbits_le32(abar + 0x24, 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2);
+
+   for (port = 0; port < 4; port++) {
+   if (!(plat->port_map & (1 << port)))
+   continue;
+   /* DEVSLP DSP */
+   setbits_le32(abar + 0x144 + (0x80 * port), 1 << 1);
+   }
+   }
+
+   /* Static Power Gating for unused ports */
+   reg32 = readl(RCB_REG(0x3a84));
+   /* Port 3 and 2 disabled */
+   if ((plat->port_map & ((1 << 3)|(1 << 2))) == 0)
+   reg32 |= (1 << 24) | (1 << 26);
+   /* Port 1 and 0 disabled */
+   if ((plat->port_map & ((1 << 1)|(1 << 0))) == 0)
+   reg32 |= (1 << 20) | (1 << 18);
+   writel(reg32, RCB_REG(0x3a84));
+
+   /* Set Gen3 Transmitter settings if needed */
+   if (plat->port0_gen3_tx)
+   pch_iobp_update(SATA_IOBP_SP0_SECRT88,
+   ~(SATA_SECRT88_VADJ_MASK <<
+ SATA_SECRT88_VADJ_SHIFT),
+   (plat->port0_gen3_tx &
+SATA_SECRT88_VADJ_MASK)
+   << SATA_SECRT88_VADJ_SHIFT);
+
+   if (plat->port1_gen3_tx)
+

[U-Boot] [PATCH 19/69] x86: Add the root-complex block to common intel registers

[Simon Glass]

This is similar to MCH in that it is used in various drivers. Add it to
the common header.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/ivybridge/bd82x6x.c  | 1 +
 arch/x86/cpu/ivybridge/lpc.c  | 6 --
 arch/x86/include/asm/arch-ivybridge/pch.h | 5 -
 arch/x86/include/asm/intel_regs.h | 4 
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 9972b0a..55057e0 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 9ab5ed3..26ffaa0 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -420,7 +421,7 @@ static void enable_spi_prefetch(struct udevice *pch)
 static void enable_port80_on_lpc(struct udevice *pch)
 {
/* Enable port 80 POST on LPC */
-   dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+   dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
clrbits_le32(RCB_REG(GCS), 4);
 }
 
@@ -552,7 +553,8 @@ static int bd82x6x_lpc_early_init(struct udevice *dev)
 {
/* Setting up Southbridge. In the northbridge code. */
debug("Setting up static southbridge registers\n");
-   dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+   dm_pci_write_config32(dev->parent, PCH_RCBA_BASE,
+ RCB_BASE_ADDRESS | 1);
dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
 
/* Enable ACPI BAR */
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h 
b/arch/x86/include/asm/arch-ivybridge/pch.h
index af3e8e7..628b517 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -211,11 +211,6 @@
 
 #define SMBUS_TIMEOUT  (10 * 1000 * 100)
 
-
-/* Root Complex Register Block */
-#define DEFAULT_RCBA   0xfed1c000
-#define RCB_REG(reg)   (DEFAULT_RCBA + (reg))
-
 #define PCH_RCBA_BASE  0xf0
 
 #define VCH0x  /* 32bit */
diff --git a/arch/x86/include/asm/intel_regs.h 
b/arch/x86/include/asm/intel_regs.h
index 61e0ec2..0bc2fca 100644
--- a/arch/x86/include/asm/intel_regs.h
+++ b/arch/x86/include/asm/intel_regs.h
@@ -12,4 +12,8 @@
 #define MCH_BASE_SIZE  0x8000
 #define MCHBAR_REG(reg)(MCH_BASE_ADDRESS + (reg))
 
+/* Access the Root Complex Register Block */
+#define RCB_BASE_ADDRESS   0xfed1c000
+#define RCB_REG(reg)   (RCB_BASE_ADDRESS + (reg))
+
 #endif
-- 
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[U-Boot] [PATCH 33/69] x86: dts: Drop memory SPD compatible string

[Simon Glass]

This is not needed now that the memory controller driver has the SPD data
in its own node.

Signed-off-by: Simon Glass 
---

 arch/x86/dts/chromebook_link.dts | 1 -
 include/fdtdec.h | 1 -
 lib/fdtdec.c | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index a702ea9..7ddbe43 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -78,7 +78,6 @@
<_b 11 0>, <_a 10 0>;
u-boot,dm-pre-reloc;
spd {
-   compatible = "memory-spd";
#address-cells = <1>;
#size-cells = <0>;
elpida_4Gb_1600_x16 {
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4caf3b6..eed01e0 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -152,7 +152,6 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */
COMPAT_SAMSUNG_EXYNOS_SYSMMU,   /* Exynos sysmmu */
COMPAT_INTEL_MICROCODE, /* Intel microcode update */
-   COMPAT_MEMORY_SPD,  /* Memory SPD information */
COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */
COMPAT_INTEL_MODEL_206AX,   /* Intel Model 206AX CPU */
COMPAT_INTEL_GMA,   /* Intel Graphics Media Accelerator */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index b361a25..6e89e95 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -57,7 +57,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
COMPAT(INTEL_MICROCODE, "intel,microcode"),
-   COMPAT(MEMORY_SPD, "memory-spd"),
COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
COMPAT(INTEL_GMA, "intel,gma"),
-- 
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[U-Boot] [PATCH 24/69] x86: Move Intel Management Engine code to a common place

[Simon Glass]

Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/intel_common/Makefile |   2 +
 .../cpu/{ivybridge => intel_common}/me_status.c|  20 +-
 .../{ivybridge => intel_common}/report_platform.c  |   2 +-
 arch/x86/cpu/ivybridge/Makefile|   2 -
 arch/x86/cpu/ivybridge/early_me.c  |  31 +-
 arch/x86/cpu/ivybridge/sdram.c |   3 +-
 arch/x86/include/asm/arch-ivybridge/me.h   | 333 +-
 arch/x86/include/asm/arch-ivybridge/sandybridge.h  |   2 -
 arch/x86/include/asm/me_common.h   | 372 +
 arch/x86/include/asm/report_platform.h |  19 ++
 10 files changed, 417 insertions(+), 369 deletions(-)
 rename arch/x86/cpu/{ivybridge => intel_common}/me_status.c (93%)
 rename arch/x86/cpu/{ivybridge => intel_common}/report_platform.c (98%)
 create mode 100644 arch/x86/include/asm/me_common.h
 create mode 100644 arch/x86/include/asm/report_platform.h

diff --git a/arch/x86/cpu/intel_common/Makefile 
b/arch/x86/cpu/intel_common/Makefile
index e9a2b29..50023fe 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -7,6 +7,8 @@
 obj-$(CONFIG_HAVE_MRC) += car.o
 obj-y += cpu_common.o
 obj-y += lpc_common.o
+obj-$(CONFIG_HAVE_MRC) += me_status.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode_intel.o
 endif
+obj-$(CONFIG_HAVE_MRC) += report_platform.o
diff --git a/arch/x86/cpu/ivybridge/me_status.c 
b/arch/x86/cpu/intel_common/me_status.c
similarity index 93%
rename from arch/x86/cpu/ivybridge/me_status.c
rename to arch/x86/cpu/intel_common/me_status.c
index 15cf69f..130d219 100644
--- a/arch/x86/cpu/ivybridge/me_status.c
+++ b/arch/x86/cpu/intel_common/me_status.c
@@ -128,7 +128,14 @@ static const char *const me_progress_policy_values[] = {
[0x10] = "Required VSCC values for flash parts do not match",
 };
 
-void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
+
+/**
+ * _intel_me_status() - Check Intel Management Engine status
+ *
+ * struct hfs: Firmware status
+ * struct gmes:Management engine status
+ */
+static void _intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
 {
/* Check Current States */
debug("ME: FW Partition Table  : %s\n",
@@ -193,3 +200,14 @@ void intel_me_status(struct me_hfs *hfs, struct me_gmes 
*gmes)
}
debug("\n");
 }
+
+void intel_me_status(struct udevice *me_dev)
+{
+   struct me_hfs hfs;
+   struct me_gmes gmes;
+
+   pci_read_dword_ptr(me_dev, , PCI_ME_HFS);
+   pci_read_dword_ptr(me_dev, , PCI_ME_GMES);
+
+   _intel_me_status(, );
+}
diff --git a/arch/x86/cpu/ivybridge/report_platform.c 
b/arch/x86/cpu/intel_common/report_platform.c
similarity index 98%
rename from arch/x86/cpu/ivybridge/report_platform.c
rename to arch/x86/cpu/intel_common/report_platform.c
index c78322a..05e1cf9 100644
--- a/arch/x86/cpu/ivybridge/report_platform.c
+++ b/arch/x86/cpu/intel_common/report_platform.c
@@ -9,8 +9,8 @@
 #include 
 #include 
 #include 
+#include 
 #include 
-#include 
 
 static void report_cpu_info(void)
 {
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 78006f1..9cdb07b 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -11,10 +11,8 @@ obj-y += cpu.o
 obj-y += early_me.o
 obj-y += gma.o
 obj-y += lpc.o
-obj-y += me_status.o
 obj-y += model_206ax.o
 obj-y += northbridge.o
-obj-y += report_platform.o
 obj-y += sata.o
 obj-y += sdram.o
 endif
diff --git a/arch/x86/cpu/ivybridge/early_me.c 
b/arch/x86/cpu/ivybridge/early_me.c
index b1df77d..cda96ab 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -27,35 +27,6 @@ static const char *const me_ack_values[] = {
[ME_HFS_ACK_CONTINUE]   = "Continue to boot"
 };
 
-static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
- int offset)
-{
-   u32 dword;
-
-   dm_pci_read_config32(me_dev, offset, );
-   memcpy(ptr, , sizeof(dword));
-}
-
-static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
-  int offset)
-{
-   u32 dword = 0;
-
-   memcpy(, ptr, sizeof(dword));
-   dm_pci_write_config32(me_dev, offset, dword);
-}
-
-void intel_early_me_status(struct udevice *me_dev)
-{
-   struct me_hfs hfs;
-   struct me_gmes gmes;
-
-   pci_read_dword_ptr(me_dev, , PCI_ME_HFS);
-   pci_read_dword_ptr(me_dev, , PCI_ME_GMES);
-
-   intel_me_status(, );
-}
-
 int intel_early_me_init(struct udevice *me_dev)
 {
int count;
@@ -159,7 +130,7 @@ int intel_early_me_init_done(struct udevice *dev, struct 
udevice *me_dev,
debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
 

[U-Boot] [PATCH 64/69] x86: Add a default address for reference code

[Simon Glass]

Add an address which can be used for loading and running the reference code
when needed.

Signed-off-by: Simon Glass 
---

 include/configs/x86-chromebook.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index c575dab..057d4be 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -14,6 +14,8 @@
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_X86_MRC_ADDR0xfffa
+#define CONFIG_X86_REFCODE_ADDR0xffea
+#define CONFIG_X86_REFCODE_RUN_ADDR0
 
 #define CONFIG_SCSI_DEV_LIST   \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
-- 
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[U-Boot] [PATCH 69/69] x86: Add support for the samus chromebook

[Simon Glass]

This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.

Signed-off-by: Simon Glass 
---

 arch/x86/dts/Makefile |   1 +
 arch/x86/dts/chromebook_samus.dts | 628 ++
 board/google/Kconfig  |  13 +
 board/google/chromebook_samus/Kconfig |  40 ++
 board/google/chromebook_samus/MAINTAINERS |   6 +
 board/google/chromebook_samus/Makefile|   7 +
 board/google/chromebook_samus/samus.c |  18 +
 configs/chromebook_samus_defconfig|  51 +++
 doc/README.x86|  81 
 include/configs/chromebook_samus.h|  29 ++
 include/configs/x86-chromebook.h  |   3 +-
 11 files changed, 876 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/dts/chromebook_samus.dts
 create mode 100644 board/google/chromebook_samus/Kconfig
 create mode 100644 board/google/chromebook_samus/MAINTAINERS
 create mode 100644 board/google/chromebook_samus/Makefile
 create mode 100644 board/google/chromebook_samus/samus.c
 create mode 100644 configs/chromebook_samus_defconfig
 create mode 100644 include/configs/chromebook_samus.h

diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 84feb19..fcfce95 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -5,6 +5,7 @@
 dtb-y += bayleybay.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
+   chromebook_samus.dtb \
cougarcanyon2.dtb \
crownbay.dtb \
efi.dtb \
diff --git a/arch/x86/dts/chromebook_samus.dts 
b/arch/x86/dts/chromebook_samus.dts
new file mode 100644
index 000..5dd3e57
--- /dev/null
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -0,0 +1,628 @@
+/dts-v1/;
+
+#include 
+
+/include/ "skeleton.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+   model = "Google Samus";
+   compatible = "google,samus", "intel,broadwell";
+
+   aliases {
+   spi0 = 
+   usb0 = _0;
+   usb1 = _1;
+   };
+
+   config {
+  silent_console = <0>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "intel,core-i3-gen5";
+   reg = <0>;
+   intel,apic-id = <0>;
+   intel,slow-ramp = <3>;
+   };
+
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "intel,core-i3-gen5";
+   reg = <1>;
+   intel,apic-id = <1>;
+   };
+
+   cpu@2 {
+   device_type = "cpu";
+   compatible = "intel,core-i3-gen5";
+   reg = <2>;
+   intel,apic-id = <2>;
+   };
+
+   cpu@3 {
+   device_type = "cpu";
+   compatible = "intel,core-i3-gen5";
+   reg = <3>;
+   intel,apic-id = <3>;
+   };
+
+   };
+
+   chosen {
+   stdout-path = "/serial";
+   };
+
+   keyboard {
+   intel,duplicate-por;
+   };
+
+   pch_pinctrl {
+   compatible = "intel,x86-broadwell-pinctrl";
+   u-boot,dm-pre-reloc;
+   reg = <0 0>;
+
+   /* Put this first: it is the default */
+   gpio_unused: gpio-unused {
+   mode-gpio;
+   direction = ;
+   owner = ;
+   sense-disable;
+   };
+
+   gpio_acpi_sci: acpi-sci {
+   mode-gpio;
+   direction = ;
+   invert;
+   route = ;
+   };
+
+   gpio_acpi_smi: acpi-smi {
+   mode-gpio;
+   direction = ;
+   invert;
+   route = ;
+   };
+
+   gpio_input: gpio-input {
+   mode-gpio;
+   direction = ;
+   owner = ;
+   };
+
+   gpio_input_invert: gpio-input-invert {
+   mode-gpio;
+   direction = ;
+   owner = ;
+   

[U-Boot] [PATCH 30/69] x86: gpio: Correct GPIO setup ordering

[Simon Glass]

The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.

Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.

Signed-off-by: Simon Glass 
---

 arch/x86/include/asm/gpio.h| 5 +
 drivers/gpio/intel_ich6_gpio.c | 4 +++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 403851b..40f4958 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -12,6 +12,7 @@
 struct ich6_bank_platdata {
uint16_t base_addr;
const char *bank_name;
+   int offset;
 };
 
 #define GPIO_MODE_NATIVE   0
@@ -146,6 +147,10 @@ struct pch_gpio_map {
} set3;
 };
 
+/*
+ * Deprecated functions to set up the GPIO map. The device tree should be used
+ * instead.
+ */
 int gpio_ich6_pinctrl_init(void);
 void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 527ed6d..c81d033 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -279,6 +279,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
debug("%s: Invalid register offset %d\n", __func__, offset);
return -EINVAL;
}
+   plat->offset = offset;
plat->base_addr = gpiobase + offset;
plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
  "bank-name", NULL);
@@ -293,7 +294,8 @@ static int ich6_gpio_probe(struct udevice *dev)
struct ich6_bank_priv *bank = dev_get_priv(dev);
 
if (gd->arch.gpio_map) {
-   setup_pch_gpios(plat->base_addr, gd->arch.gpio_map);
+   setup_pch_gpios(plat->base_addr - plat->offset,
+   gd->arch.gpio_map);
gd->arch.gpio_map = NULL;
}
 
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 62/69] x86: Support a chained-boot development flow

[Simon Glass]

Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.

In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong. Provide a development-only option to set up the GDT
correctly.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/start.S | 79 
 1 file changed, 79 insertions(+)

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 485868f..5fbc2b5 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -18,6 +18,13 @@
 #include 
 #include 
 
+/*
+ * Define this to boot U-Boot from a 32-bit program which sets the GDT
+ * differently. This can be used to boot directly from coreboot, for example.
+ * This is only useful for development.
+ */
+#undef LOAD_FROM_32_BIT
+
 .section .text
 .code32
 .globl _start
@@ -68,6 +75,10 @@ _start:
/* Save table pointer */
movl%ecx, %esi
 
+#ifdef LOAD_FROM_32_BIT
+   lgdtgdt_ptr2
+#endif
+
/* Load the segement registers to match the GDT loaded in start16.S */
movl$(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
movw%ax, %fs
@@ -220,3 +231,71 @@ multiboot_header:
.long   0
/* entry addr */
.long   CONFIG_SYS_TEXT_BASE
+
+#ifdef LOAD_FROM_32_BIT
+   /*
+* The following Global Descriptor Table is just enough to get us into
+* 'Flat Protected Mode' - It will be discarded as soon as the final
+* GDT is setup in a safe location in RAM
+*/
+gdt_ptr2:
+   .word   0x1f/* limit (31 bytes = 4 GDT entries - 1) */
+   .long   gdt_rom2/* base */
+
+   /* Some CPUs are picky about GDT alignment... */
+   .align  16
+.globl gdt_rom2
+gdt_rom2:
+   /*
+* The GDT table ...
+*
+*   Selector   Type
+*   0x00   NULL
+*   0x08   Unused
+*   0x10   32bit code
+*   0x18   32bit data/stack
+*/
+   /* The NULL Desciptor - Mandatory */
+   .word   0x  /* limit_low */
+   .word   0x  /* base_low */
+   .byte   0x00/* base_middle */
+   .byte   0x00/* access */
+   .byte   0x00/* flags + limit_high */
+   .byte   0x00/* base_high */
+
+   /* Unused Desciptor - (matches Linux) */
+   .word   0x  /* limit_low */
+   .word   0x  /* base_low */
+   .byte   0x00/* base_middle */
+   .byte   0x00/* access */
+   .byte   0x00/* flags + limit_high */
+   .byte   0x00/* base_high */
+
+   /*
+* The Code Segment Descriptor:
+* - Base   = 0x
+* - Size   = 4GB
+* - Access = Present, Ring 0, Exec (Code), Readable
+* - Flags  = 4kB Granularity, 32-bit
+*/
+   .word   0x  /* limit_low */
+   .word   0x  /* base_low */
+   .byte   0x00/* base_middle */
+   .byte   0x9b/* access */
+   .byte   0xcf/* flags + limit_high */
+   .byte   0x00/* base_high */
+
+   /*
+* The Data Segment Descriptor:
+* - Base   = 0x
+* - Size   = 4GB
+* - Access = Present, Ring 0, Non-Exec (Data), Writable
+* - Flags  = 4kB Granularity, 32-bit
+*/
+   .word   0x  /* limit_low */
+   .word   0x  /* base_low */
+   .byte   0x00/* base_middle */
+   .byte   0x93/* access */
+   .byte   0xcf/* flags + limit_high */
+   .byte   0x00/* base_high */
+#endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 59/69] x86: broadwell: Add support for SDRAM setup

[Simon Glass]

Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/broadwell/Makefile|   1 +
 arch/x86/cpu/broadwell/sdram.c | 307 +
 arch/x86/include/asm/arch-broadwell/pei_data.h | 177 ++
 arch/x86/include/asm/global_data.h |  24 ++
 4 files changed, 509 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/sdram.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 5a62afa..012798f 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -13,3 +13,4 @@ obj-y += pinctrl_broadwell.o
 obj-y += power_state.o
 obj-y += refcode.o
 obj-y += sata.o
+obj-y += sdram.o
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
new file mode 100644
index 000..caf6ef6
--- /dev/null
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot src/soc/intel/broadwell/romstage/raminit.c
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+   return sdram_common_board_get_usable_ram_top(total_size);
+}
+
+void dram_init_banksize(void)
+{
+   sdram_common_dram_init_banksize();
+}
+
+void broadwell_fill_pei_data(struct pei_data *pei_data)
+{
+   pei_data->pei_version = PEI_VERSION;
+   pei_data->board_type = BOARD_TYPE_ULT;
+   pei_data->pciexbar = MCFG_BASE_ADDRESS;
+   pei_data->smbusbar = SMBUS_BASE_ADDRESS;
+   pei_data->ehcibar = EARLY_EHCI_BAR;
+   pei_data->xhcibar = EARLY_XHCI_BAR;
+   pei_data->gttbar = EARLY_GTT_BAR;
+   pei_data->pmbase = ACPI_BASE_ADDRESS;
+   pei_data->gpiobase = GPIO_BASE_ADDRESS;
+   pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
+   pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
+   pei_data->tx_byte = sdram_console_tx_byte;
+   pei_data->ddr_refresh_2x = 1;
+}
+
+static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
+ uint16_t length, uint8_t enable,
+ uint8_t oc_pin, uint8_t location)
+{
+   pei_data->usb2_ports[port].length   = length;
+   pei_data->usb2_ports[port].enable   = enable;
+   pei_data->usb2_ports[port].oc_pin   = oc_pin;
+   pei_data->usb2_ports[port].location = location;
+}
+
+static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
+ uint8_t enable, uint8_t oc_pin,
+ uint8_t fixed_eq)
+{
+   pei_data->usb3_ports[port].enable   = enable;
+   pei_data->usb3_ports[port].oc_pin   = oc_pin;
+   pei_data->usb3_ports[port].fixed_eq = fixed_eq;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+   /* DQ byte map for Samus board */
+   const u8 dq_map[2][6][2] = {
+   { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+   { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
+   /* DQS CPU<>DRAM map for Samus board */
+   const u8 dqs_map[2][8] = {
+   { 2, 0, 1, 3, 6, 4, 7, 5 },
+   { 2, 1, 0, 3, 6, 5, 4, 7 } };
+
+   pei_data->ec_present = 1;
+
+   /* One installed DIMM per channel */
+   pei_data->dimm_channel0_disabled = 2;
+   pei_data->dimm_channel1_disabled = 2;
+
+   memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+   memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+
+   /* P0: HOST PORT */
+   pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
+  USB_PORT_BACK_PANEL);
+   /* P1: HOST PORT */
+   pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
+  USB_PORT_BACK_PANEL);
+   /* P2: RAIDEN */
+   pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+  USB_PORT_BACK_PANEL);
+   /* P3: SD CARD */
+   pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+  USB_PORT_INTERNAL);
+   /* P4: RAIDEN */
+   pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
+  USB_PORT_BACK_PANEL);
+   /* P5: WWAN (Disabled) */
+   pei_data_usb2_port(pei_data, 5, 0x, 0, USB_OC_PIN_SKIP,
+  USB_PORT_SKIP);
+   /* P6: CAMERA */
+   pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+ 

[U-Boot] [PATCH 23/69] x86: Rename PORT_RESET to IO_PORT_RESET

[Simon Glass]

This same name is used in USB. Add a prefix to distinguish it.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/cpu.c | 4 ++--
 arch/x86/cpu/intel_common/cpu_common.c | 4 ++--
 arch/x86/include/asm/processor.h   | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index e2aad19..8eb676c 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -469,14 +469,14 @@ void  flush_cache(unsigned long dummy1, unsigned long 
dummy2)
 __weak void reset_cpu(ulong addr)
 {
/* Do a hard reset through the chipset's reset control register */
-   outb(SYS_RST | RST_CPU, PORT_RESET);
+   outb(SYS_RST | RST_CPU, IO_PORT_RESET);
for (;;)
cpu_hlt();
 }
 
 void x86_full_reset(void)
 {
-   outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
+   outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
 }
 
 int dcache_status(void)
diff --git a/arch/x86/cpu/intel_common/cpu_common.c 
b/arch/x86/cpu/intel_common/cpu_common.c
index 1210943..93e4505 100644
--- a/arch/x86/cpu/intel_common/cpu_common.c
+++ b/arch/x86/cpu/intel_common/cpu_common.c
@@ -102,8 +102,8 @@ int cpu_set_flex_ratio_to_tdp_nominal(void)
setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
 
/* Issue warm reset, will be "CPU only" due to soft reset data */
-   outb(0x0, PORT_RESET);
-   outb(SYS_RST | RST_CPU, PORT_RESET);
+   outb(0x0, IO_PORT_RESET);
+   outb(SYS_RST | RST_CPU, IO_PORT_RESET);
cpu_hlt();
 
/* Not reached */
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 7c77b90..cefc633 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -36,7 +36,7 @@
  *
  * The naming follows Intel's naming.
  */
-#define PORT_RESET 0xcf9
+#define IO_PORT_RESET  0xcf9
 
 enum {
SYS_RST = 1 << 1,   /* 0 for soft reset, 1 for hard reset */
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 35/69] x86: Correct duplicate POST values

[Simon Glass]

Two power-on-self-test values are the same. Fix this.

Signed-off-by: Simon Glass 
---

 arch/x86/include/asm/post.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
index f49ce99..6b774bd 100644
--- a/arch/x86/include/asm/post.h
+++ b/arch/x86/include/asm/post.h
@@ -29,8 +29,8 @@
 #define POST_CPU_INFO  0x2d
 #define POST_PRE_MRC   0x2e
 #define POST_MRC   0x2f
-#define POST_DRAM  0x2f
-#define POST_LAPIC 0x30
+#define POST_DRAM  0x30
+#define POST_LAPIC 0x31
 
 #define POST_RAM_FAILURE   0xea
 #define POST_BIST_FAILURE  0xeb
-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] Weird error message on buildman

[Simon Glass]

Hi Masahiro,

On 23 February 2015 at 06:42, Simon Glass  wrote:
> Hi Masahiro,
>
> On 23 February 2015 at 05:52, Masahiro Yamada  
> wrote:
>> Hi Simon,
>>
>>
>> When I try to run Buildman against a branch named "test",
>> it fails with a weird error message.
>>
>>
>>
>> $ git branch
>> * master
>> $ git checkout -b test master
>> Switched to a new branch 'test'
>> $ echo foo >> README
>> $ git add README
>> $ git commit -m foo
>> [test f8f6569] foo
>>  1 file changed, 1 insertion(+)
>> $ tools/buildman/buildman -b test
>> Branch 'test' not found
>> $ git branch
>>   master
>> * test
>>
>>
>> Indeed, the branch "test" exists,
>> but Buildman reports "Branch "test' not found".
>>
>>
>> Could you check it out, please?
>
> Weird indeed. Thanks for the test case, will take a look.

eventually

It looks like this is because there is a directory called 'test'. I
should be able to fix it with a patch.

Regards,
Simon
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[U-Boot] [PATCH 39/69] x86: Tidy up mp_init to reduce duplication

[Simon Glass]

The timeout step is always 50us. By updating apic_wait_timeout() to print
the debug messages we can simplify the code. Also tidy up a few messages and
comments while we are here.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/mp_init.c | 79 +-
 1 file changed, 26 insertions(+), 53 deletions(-)

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index fc2fb5b..ca47e9e 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -195,7 +195,7 @@ static int save_bsp_msrs(char *start, int size)
msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
 
if ((msr_count * sizeof(struct saved_msr)) > size) {
-   printf("Cannot mirror all %d msrs.\n", msr_count);
+   printf("Cannot mirror all %d msrs\n", msr_count);
return -ENOSPC;
}
 
@@ -283,21 +283,25 @@ static int check_cpu_devices(int expected_cpus)
 }
 
 /* Returns 1 for timeout. 0 on success */
-static int apic_wait_timeout(int total_delay, int delay_step)
+static int apic_wait_timeout(int total_delay, const char *msg)
 {
int total = 0;
-   int timeout = 0;
 
+   if (!(lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY))
+   return 0;
+
+   debug("Waiting for %s...", msg);
while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
-   udelay(delay_step);
-   total += delay_step;
+   udelay(50);
+   total += 50;
if (total >= total_delay) {
-   timeout = 1;
-   break;
+   debug("timed out: aborting\n");
+   return -ETIMEDOUT;
}
}
+   debug("done\n");
 
-   return timeout;
+   return 0;
 }
 
 static int start_aps(int ap_count, atomic_t *num_aps)
@@ -320,73 +324,42 @@ static int start_aps(int ap_count, atomic_t *num_aps)
 
debug("Attempting to start %d APs\n", ap_count);
 
-   if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
-   debug("Waiting for ICR not to be busy...");
-   if (apic_wait_timeout(1000, 50)) {
-   debug("timed out. Aborting.\n");
-   return -1;
-   } else {
-   debug("done.\n");
-   }
-   }
+   if (apic_wait_timeout(1000, "ICR not to be busy"))
+   return -ETIMEDOUT;
 
/* Send INIT IPI to all but self */
lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
LAPIC_DM_INIT);
-   debug("Waiting for 10ms after sending INIT.\n");
+   debug("Waiting for 10ms after sending INIT\n");
mdelay(10);
 
/* Send 1st SIPI */
-   if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
-   debug("Waiting for ICR not to be busy...");
-   if (apic_wait_timeout(1000, 50)) {
-   debug("timed out. Aborting.\n");
-   return -1;
-   } else {
-   debug("done.\n");
-   }
-   }
+   if (apic_wait_timeout(1000, "ICR not to be busy"))
+   return -ETIMEDOUT;
 
lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
LAPIC_DM_STARTUP | sipi_vector);
-   debug("Waiting for 1st SIPI to complete...");
-   if (apic_wait_timeout(1, 50)) {
-   debug("timed out.\n");
-   return -1;
-   } else {
-   debug("done.\n");
-   }
+   if (apic_wait_timeout(1, "first SIPI to complete"))
+   return -ETIMEDOUT;
 
/* Wait for CPUs to check in up to 200 us */
wait_for_aps(num_aps, ap_count, 200, 15);
 
/* Send 2nd SIPI */
-   if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
-   debug("Waiting for ICR not to be busy...");
-   if (apic_wait_timeout(1000, 50)) {
-   debug("timed out. Aborting.\n");
-   return -1;
-   } else {
-   debug("done.\n");
-   }
-   }
+   if (apic_wait_timeout(1000, "ICR not to be busy"))
+   return -ETIMEDOUT;
 
lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
LAPIC_DM_STARTUP | sipi_vector);
-   debug("Waiting for 2nd SIPI to complete...");
-   if (apic_wait_timeout(1, 50)) {
-   debug("timed out.\n");
-   return -1;
-   } else {
-   debug("done.\n");
-   }
+   if (apic_wait_timeout(1, "second SIPI to complete"))
+   return -ETIMEDOUT;
 
/* Wait for CPUs to check in */
if (wait_for_aps(num_aps, ap_count, 1, 50)) {
-   debug("Not all APs 

Re: [U-Boot] How do I tell buildman to use a /specific/ toolchain?

[Simon Glass]

Hi Stephen,

On 4 October 2015 at 19:19, Stephen Warren  wrote:
> On 10/04/2015 10:38 AM, Simon Glass wrote:
>> Hi Stephen,
>>
>> On 3 October 2015 at 20:20, Stephen Warren  wrote:
>>> On 10/03/2015 08:30 AM, Simon Glass wrote:
 Hi Stephen,

 On 2 October 2015 at 00:27, Stephen Warren  wrote:
> On 10/01/2015 04:59 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On Wednesday, 23 September 2015, Stephen Warren 
>> wrote:
>>>
>>>
>>> Simon,
>>>
>>> I have 3 different ARM toolchains installed into /usr/bin via distro
>>> packages. How do I tell buildman which of those to use?
>>>
>>> I had originally thought that ~/.buildman's [toolchain] section 
>>> contained
>>> CROSS_COMPILE-like values, so I tried:
>>>
 [toolchain]
 root: /
 arm0-not-installed: arm-none-gnueabi-
 arm1: arm-none-eabi-
 arm2: arm-linux-gnueabihf-
 arm3: arm-linux-gnueabi-
 arch64: aarch64-linux-gnu-

 [toolchain-alias]
 arm: arm1
 aarch64: aarch64
>>>
>>>
>>>
>>> (I intended to change the "arm: arm1" line to point at arm1/2/3 based on
>>> which I wanted to use at a particular time).
>>>
>>> However, running "buildman --list-toolchains" and re-reading the docs
>>> shows me that the [toolchain] values are absolute directories that 
>>> buildman
>>> searches for files named *-gcc:
>>>
 - scanning path 'arm-none-gnueabi-'
- looking in 'arm-none-gnueabi-/.'
- looking in 'arm-none-gnueabi-/bin'
- looking in 'arm-none-gnueabi-/usr/bin'
>>>
>>>
>>>
>>> If buildman finds multiple toolchains, there doesn't seem to be a way to
>>> tell it which one to use. Am I missing something?
>>>
>>> I suppose a solution wouuld be to move the compiler binaries into
>>> different separate directories, and only list one of those directories 
>>> in
>>> ~/.buildman. However, I can't do that for distro-packaged toolchains 
>>> (well,
>>> I suppose I could manually mv everything all over the place, but that's
>>> really fragile since it'd break any time the package got upgraded or 
>>> removed
>>> and re-installed).
>>>
>>> I think it makes sense to add new syntax into ~/.buildman to specify
>>> "don't do automagical searching, just use this CROSS_COMPILE value that 
>>> I
>>> say". Does that sound reasonable? Automagic stuff makes for great 
>>> defaults,
>>> but if it can't be overridden, it sucks when you actually know what you
>>> want.
>>
>>
>> Yes I think it would be fine to add an option to use CROSS_COMPILE (of
>> course it would fail if you tried to build the board with the wrong
>> arch).
>
>
> I wasn't necessarily looking for buildman to pick up the CROSS_COMPILE
> environment variable, although that would be a simple solution for
> single-arch builds at least. My mention of CROSS_COMPILE immediately above
> was re: using values that are formatted in the same way as the 
> CROSS_COMPILE
> environment variable would be, rather than directory names, in the config
> file. In other words, the example content I showed above.
>
>> The option other option at present is -G which lets you use multiple
>> .buildman files. You could have one of these for each toolchain.
>
>
> I don't think that gets me what I want. As far as I can tell, the buildman
> config file contains a list directories to search within, yet if I have 3
> toolchains in a single directory, there's no way to select which one I 
> want
> to use, is there?
>
> In other words, a config file that contains:
>
> [toolchain]
> distro-packages: /usr/bin
>
> ... finds the following toolchains:
>
> [swarren@swarren-lx1 u-boot]$ ./tools/buildman/buildman \
> --list-tool-chains
> Scanning for tool chains
>- scanning path '/usr/bin'
>   - looking in '/usr/bin/.'
>  - found '/usr/bin/./arm-linux-gnueabi-gcc'
>  - found '/usr/bin/./arm-linux-gnueabihf-gcc'
>  - found '/usr/bin/./arm-none-eabi-gcc'
> (That's 3 AArch32 toolchains found)
>  - found '/usr/bin/./winegcc'
>  - found '/usr/bin/./aarch64-linux-gnu-gcc'
>  - found '/usr/bin/./gcc'
>  - found '/usr/bin/./c89-gcc'
>  - found '/usr/bin/./x86_64-linux-gnu-gcc'
>  - found '/usr/bin/./i586-mingw32msvc-gcc'
>  - found '/usr/bin/./c99-gcc'
>   - looking in '/usr/bin/bin'
>   - looking in '/usr/bin/usr/bin'
> Tool chain test:  OK
> Tool chain test:  OK
> Tool chain test:  OK
> Tool chain test:  OK
> 

Re: [U-Boot] buildman for sandbox

[Simon Glass]

Hi Joe,

On 7 May 2015 at 03:17, Joe Hershberger  wrote:
> Hi Simon,
>
> Is there a way to make buildman compile sandbox with a non-system tool
> chain? I've tried creating an alias from sandbox to i386 and removing
> the "root" entry. It then simply claims not to have a sandbox tool
> chain.
>
> Thanks,
> -Joe

FYI I've prepared a series that permits:

[toolchain-prefix]
sandbox = /path/to/sandbox-gcc

so you can specify this.

Regards,
Simon
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Re: [U-Boot] [PATCH] rockchip: rk3288: correct sdram setting

[Simon Glass]

Hi Chris,

On 29 February 2016 at 19:29, Chris Zhong  wrote:
> Hi Simon
>
>
> On 03/01/2016 10:04 AM, Simon Glass wrote:
>>
>> Hi Chris,
>>
>> On 29 February 2016 at 05:16, Chris Zhong  wrote:
>>>
>>> The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2,
>>> and it expects uboot to store the value using a same protocol. But now
>>> the ddr setting value is different with DMC, so if you enable the DMC,
>>> system would crash in kernel. Correct the sdram setting here, according
>>> to the requirements of kernel.
>>>
>>> [0]
>>> https://chromium.googlesource.com/chromiumos/third_party/kernel/+/
>>> chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c
>>>
>>> Signed-off-by: Chris Zhong 
>>> ---
>>>
>>>   arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 42 -
>>>   arch/arm/mach-rockchip/rk3288/sdram_rk3288.c| 61
>>> +++--
>>>   2 files changed, 48 insertions(+), 55 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
>>> b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
>>> index fccabcd..f2e3130 100644
>>> --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
>>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
>>> @@ -459,26 +459,26 @@ enum {
>>>* [3:2] bw_ch0
>>>* [1:0] dbw_ch0
>>>   */
>>> -#define SYS_REG_DDRTYPE_SHIFT  13
>>> -#define SYS_REG_DDRTYPE_MASK   7
>>> -#define SYS_REG_NUM_CH_SHIFT   12
>>> -#define SYS_REG_NUM_CH_MASK1
>>> -#define SYS_REG_ROW_3_4_SHIFT(ch)  (30 + (ch))
>>> -#define SYS_REG_ROW_3_4_MASK   1
>>> -#define SYS_REG_CHINFO_SHIFT(ch)   (28 + (ch))
>>> -#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
>>> -#define SYS_REG_RANK_MASK  1
>>> -#define SYS_REG_COL_SHIFT(ch)  (9 + (ch) * 16)
>>> -#define SYS_REG_COL_MASK   3
>>> -#define SYS_REG_BK_SHIFT(ch)   (8 + (ch) * 16)
>>> -#define SYS_REG_BK_MASK1
>>> -#define SYS_REG_CS0_ROW_SHIFT(ch)  (6 + (ch) * 16)
>>> -#define SYS_REG_CS0_ROW_MASK   3
>>> -#define SYS_REG_CS1_ROW_SHIFT(ch)  (4 + (ch) * 16)
>>> -#define SYS_REG_CS1_ROW_MASK   3
>>> -#define SYS_REG_BW_SHIFT(ch)   (2 + (ch) * 16)
>>> -#define SYS_REG_BW_MASK3
>>> -#define SYS_REG_DBW_SHIFT(ch)  ((ch) * 16)
>>> -#define SYS_REG_DBW_MASK   3
>>> +#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
>>> +#define SYS_REG_DEC_ROW_3_4(n, ch) ((n >> (30 + ch)) & 0x1)
>>> +#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
>>> +#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
>>> +#define SYS_REG_ENC_NUM_CH(n)  (((n) - 1) << 12)
>>> +#define SYS_REG_DEC_NUM_CH(n)  (1 + ((n >> 12) & 0x1))
>>> +#define SYS_REG_ENC_RANK(n, ch)(((n) - 1) << (11 + ((ch)
>>> * 16)))
>>> +#define SYS_REG_DEC_RANK(n, ch)(1 + ((n >> (11 + 16 *
>>> ch)) & 0x1))
>>> +#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16)))
>>> +#define SYS_REG_DEC_COL(n, ch) (9 + ((n >> (9 + 16 * ch)) &
>>> 0x3))
>>> +#define SYS_REG_ENC_BK(n, ch)  (((n) == 3 ? 0 : 1) \
>>> +   << (8 + ((ch) * 16)))
>>> +#define SYS_REG_DEC_BK(n, ch)  (3 - ((n >> (8 + 16 * ch)) &
>>> 0x1))
>>> +#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + ((ch) * 16)))
>>> +#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + ((n >> (6 + 16 * ch)) &
>>> 0x3))
>>> +#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + ((ch) * 16)))
>>> +#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + ((n >> (4 + 16 * ch)) &
>>> 0x3))
>>> +#define SYS_REG_ENC_BW(n, ch)  ((2 >> (n)) << (2 + ((ch) * 16)))
>>> +#define SYS_REG_DEC_BW(n, ch)  (2 >> ((n >> (2 + 16 * ch)) &
>>> 0x3))
>>> +#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16)))
>>> +#define SYS_REG_DEC_DBW(n, ch) (2 >> ((n >> (0 + 16 * ch)) &
>>> 0x3))
>>
>> Are the above shift/masks actually wrong? I'm not keen on this style
>> of packing and unpacking registers since it is really hard to read and
>> it's not obvious that pack and unpack work the same way.
>
> Actually, I copy these code from coreboot[0], can we just keep the code
> consistent with it?

I'm really not keen on that style. It is really hard to read.

So please can you fix the bug without changing the code style?

Actually the mask I set up for rockchip is wrong also. It should be:

#define SYS_REG_DDRTYPE_SHIFT  13
#define SYS_REG_DDRTYPE_MASK   (7 << SYS_REG_DDRTYPE_SHIFT)

I'll take a look at fixing these.

>
> [0]https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/
> firmware-veyron-6588.B/src/soc/rockchip/rk3288/sdram.c
>
>
>>
>>>   #endif
>>> diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
>>> b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
>>> index e9e2211..4db39ec 

Re: [U-Boot] [PATCH 1/3] drivers: block: Kconfig: set default n to CONFIG_DISK

[Simon Glass]

Hi Mugunthan,

On 2 March 2016 at 22:06, Mugunthan V N  wrote:
> When a platform is converted to support DM and when its scsi
> driver is not converted to support DM, there is a build break as
> multiple definition of scsi_init(). So select CONFIG_DISK only
> when the platform supports CONFIG_DISK.
>
> drivers/built-in.o: In function `scsi_init':
> /home/mugunthan/workspace/git/work/u-boot/dm-sata/drivers/block/disk-uclass.c:37:
>  multiple definition of `scsi_init'
> board/sunxi/built-in.o:/home/mugunthan/workspace/git/work/u-boot/dm-sata/board/sunxi/ahci.c:74:
>  first defined here
> Makefile:1171: recipe for target 'u-boot' failed
> make: *** [u-boot] Error 1
>
> Signed-off-by: Mugunthan V N 
> ---
>  drivers/block/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

This is because you are defining scsi_init() in the uclass, but I
don't think that is a great idea. Or at least it should only be
defined if DISK is enabled.

Regards,
Simon
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Re: [U-Boot] [PATCH v6 1/2] common: image-fit: Use a common function to get address

[Simon Glass]

On 29 February 2016 at 16:48, York Sun  wrote:
> FIT image supports load address and entry address. Getting these
> addresses can use a common function.
>
> Signed-off-by: York Sun 
>
> ---
>
> Changes in v6:
>   Drop patches which convert ulong to phys_addr_t
>   Revert to use original ulong
>
> Changes in v5:
>   New patch split from fixing load and entry address patch
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  common/image-fit.c |   42 +++---
>  1 file changed, 19 insertions(+), 23 deletions(-)

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Re: [U-Boot] [PATCH V2 1/2] malloc: use hidden visibility

[Simon Glass]

On 5 March 2016 at 10:30, Stephen Warren  wrote:
> When running sandbox, the following phases occur, each with different
> malloc implementations or behaviors:
>
> 1) Dynamic linker execution, using the dynamic linker's own malloc()
> implementation. This is fully functional.
>
> 2) After U-Boot's malloc symbol has been hooked into the GOT, but before
> any U-Boot code has run. This phase is entirely non-functional, since
> U-Boot's gd symbol is NULL and U-Boot's initf_malloc() and
> mem_malloc_init() have not been called.
>
> At least on Ubuntu Xenial, the dynamic linker does make both malloc() and
> free() calls during this phase. Currently these free() calls crash since
> they dereference gd, which is NULL.
>
> U-Boot itself makes no use of malloc() during this phase.
>
> 3) U-Boot execution after gd is set and initf_malloc() has been called.
> This is fully functional, albeit via a very simple malloc()
> implementation.
>
> 4) U-Boot execution after mem_malloc_init() has been called. This is fully
> functional with a complete malloc() implementation.
>
> Furthermore, if code that called malloc() during phase 1 calls free() in
> phase 3 or later, it is likely that heap corruption will occur, since
> U-Boot's malloc implementation will assume the pointer is part of its own
> heap, although it isn't. I have not actively observed this happening.
>
> To prevent phase 2 from happening, this patch makes all of U-Boot's malloc
> library public symbols have hidden visibility. This prevents them from
> being hooked into the GOT, so only code in the U-Boot binary itself
> actually calls them; any other code will call into the standard C library
> malloc(). This also avoids the "furthermore" issue mentioned above.
>
> I have seen references to this GCC pragma in blog posts from 2008, and
> RHEL5's ancient gcc appears to accept it fine, so I believe it's quite
> safe to use it without checking gcc version.
>
> Cc: Rabin Vincent 
> Signed-off-by: Stephen Warren 
> ---
> v2: A whole different approach.
> ---
>  include/malloc.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/include/malloc.h b/include/malloc.h
> index f20e4d3d2a6b..8175c75920cf 100644
> --- a/include/malloc.h
> +++ b/include/malloc.h
> @@ -914,6 +914,7 @@ int initf_malloc(void);
>  /* Simple versions which can be used when space is tight */
>  void *malloc_simple(size_t size);
>
> +#pragma GCC visibility push(hidden)
>  # if __STD_C
>
>  Void_t* mALLOc(size_t);
> @@ -945,6 +946,7 @@ int mALLOPt();
>  struct mallinfo mALLINFo();
>  # endif
>  #endif
> +#pragma GCC visibility pop
>
>  /*
>   * Begin and End of memory area for malloc(), and current "brk"
> --
> 2.7.0
>

This seems better than what we have. Thanks for digging into it.

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v6 2/2] common: image-fit: Fix load and entry addresses in FIT image

[Simon Glass]

On 29 February 2016 at 16:48, York Sun  wrote:
> FIT image supports more than 32 bits in addresses by using #address-cell
> field. Fixing 64-bit support by using this field.
>
> Signed-off-by: York Sun 
>
> ---
>
> Changes in v6:
>   Revert back to use original "ulong" instead of "phys_addr_t"
>   Abort getting image addresses if address is too long for "ulong"
>
> Changes in v5:
>   Split the common function into another patch.
>   Revise commit subject.
>   Update commit message as suggested by Simon.
>   Updated cover letter with testing report.
>
> Changes in v4:
>   Separate ulong to phys_addr_t change to another patch.
>
> Changes in v3:
>   Define PRIpa for host and target in common/image-fit.c so printf works
>   properly for 32-, 64-bit targets and host tools.
>
> Changes in v2:
>   Make a common function for both load and entry addresses.
>   Simplify calculation of addresses in a similar way as fdtdec_get_number()
>   fdtdec_get_number() is not used, or too many files need to be included
> and/or twisted for host tool
>   Continue to use %08llx for print format for load and entry addresses
> because %pa does not always work for host tool (mkimage)
>
>  common/image-fit.c |   22 +-
>  1 file changed, 17 insertions(+), 5 deletions(-)

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Re: [U-Boot] [PATCH] dm: core: make simple-bus compatible to simple-mfd

[Simon Glass]

On 29 February 2016 at 19:51, Masahiro Yamada
 wrote:
>
> Simple MFD devices can bind children without special bus configuration.
> Like Linux, let's handle "simple-mfd" in the same way as "simple-bus".
>
> Signed-off-by: Masahiro Yamada 
> ---
>
>  drivers/core/simple-bus.c | 1 +
>  1 file changed, 1 insertion(+)


Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH] rockchip: make configure_emmc() empty for Firefly-RK3288

[Simon Glass]

On 5 March 2016 at 06:32, FUKAUMI Naoki  wrote:
> on v2016.03-rc3, size of SPL image compiled by gcc 5.3.0 is too large for
> Firefly-RK3288. (it's fine for Rock2)
>
> $ gcc --version
> gcc (Ubuntu/Linaro 5.3.0-3ubuntu1~14.04) 5.3.0 20151204
> Copyright (C) 2015 Free Software Foundation, Inc.
> This is free software; see the source for copying conditions.  There is NO
> warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
>
> $ ./tools/mkimage -n rk3288 -T rksd -d spl/u-boot-spl-dtb.bin 
> u-boot-spl-dtb.img
> Warning: SPL image is too large (size 0x80d0) and will not boot
>
> to reduce size of SPL image, this patch makes configure_emmc() empty for
> Firefly-RK3288 as same as Rock2.
>
> Signed-off-by: FUKAUMI Naoki 
> ---
>  arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH V2 2/2] malloc: remove !gd handling

[Simon Glass]

On 5 March 2016 at 10:30, Stephen Warren  wrote:
> Following the previous patch, malloc() is never called before gd is set,
> so we can remove the special-case check for this condition.
>
> This reverts commit 854d2b9753e4 "dlmalloc: ensure gd is set for early
> alloc".
>
> Cc: Rabin Vincent 
> Signed-off-by: Stephen Warren 
> ---
>  common/dlmalloc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

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Re: [U-Boot] [PATCH] sandbox: Fix building with LLVM

[Simon Glass]

On 5 March 2016 at 12:07, Tom Rini  wrote:
> - The macro __BIGGEST_ALIGNMENT__ is gcc-specific.  If it is not defined
>   we'll just assume 16.  This is correct for at least the common cases
>   and LLVM does not provide an equivalent macro.
> - When linking U-Boot we're passing -T to the linker, and while gcc will
>   just pass this along with LLVM we need to be specific.
>
> Cc: Simon Glass 
> Signed-off-by: Tom Rini 
>
> ---
> I've tested this with both test/fs/fs-test.sh (and a quick kludge to
> force it to use LLVM) and test/pytest/test.py with a pre-built sandbox
> and both pass as much as with gcc does for me.
> ---
>  arch/sandbox/config.mk   |2 +-
>  arch/sandbox/include/asm/cache.h |6 ++
>  2 files changed, 7 insertions(+), 1 deletion(-)

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Re: [U-Boot] [PATCH] serial: pl01x: Add support for devices with the rate pre-configured.

[Simon Glass]

Hi Stephen,

On 5 March 2016 at 23:26, Stephen Warren  wrote:
>
> On 02/05/2016 09:19 PM, Stephen Warren wrote:
>>
>> On 02/05/2016 02:43 PM, Eric Anholt wrote:
>>>
>>> For Raspberry Pi, we had the input clock rate to the pl011 fixed in
>>> the rpi.c file, but it may be changed by firmware due to user changes
>>> to config.txt.  Since the firmware always sets up the uart (default
>>> 115200 output unless the user changes it), we can just skip our own
>>> uart init to simplify the boot process and more reliably get serial
>>> output.
>>
>>
>> Tested-by: Stephen Warren 
>> (With a 6MHz init_uart_clock and with/without init_uart_baud=9600)
>
>
> Simon/Tom, did this slip through the cracks, or are you deferring it until 
> the next release?

We haven't heard back on the review comments.

I don't really mind if we go the DT approach or this one. But this
patch needs a little rework I think.

Regards,
Simon
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[U-Boot] [PATCH 60/69] x86: broadwell: Add a GPIO driver

[Simon Glass]

Add a GPIO driver for the GPIO peripheral found on broadwell devices.

Signed-off-by: Simon Glass 
---

 drivers/gpio/Kconfig|   9 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/intel_broadwell_gpio.c | 198 
 3 files changed, 208 insertions(+)
 create mode 100644 drivers/gpio/intel_broadwell_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 845dc72..e7ec384 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -39,6 +39,15 @@ config ATMEL_PIO4
  may be dedicated as a general purpose I/O or be assigned to
  a function of an embedded peripheral.
 
+config INTEL_BROADWELL_GPIO
+   bool "Intel Broadwell GPIO driver"
+   depends on DM
+   help
+ This driver supports Broadwell U devices which have an expanded
+ GPIO feature set. The difference is large enough to merit a separate
+ driver from the common Intel ICH6 driver. It supports a total of
+ 95 GPIOs which can be configure from the device tree.
+
 config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 845a6d4..5ac381a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
 obj-$(CONFIG_AT91_GPIO)+= at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)   += atmel_pio4.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)  += intel_ich6_gpio.o
+obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
 obj-$(CONFIG_KIRKWOOD_GPIO)+= kw_gpio.o
 obj-$(CONFIG_KONA_GPIO)+= kona_gpio.o
 obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o
diff --git a/drivers/gpio/intel_broadwell_gpio.c 
b/drivers/gpio/intel_broadwell_gpio.c
new file mode 100644
index 000..06bf46b
--- /dev/null
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct broadwell_bank_priv - Private driver data
+ *
+ * @regs:  Pointer to GPIO registers
+ * @bank:  Bank number for this bank (0, 1 or 2)
+ * @offset:GPIO offset for this bank (0, 32 or 64)
+ */
+struct broadwell_bank_priv {
+   struct pch_lp_gpio_regs *regs;
+   int bank;
+   int offset;
+};
+
+static int broadwell_gpio_request(struct udevice *dev, unsigned offset,
+const char *label)
+{
+   struct broadwell_bank_priv *priv = dev_get_priv(dev);
+   struct pch_lp_gpio_regs *regs = priv->regs;
+   u32 val;
+
+   /*
+* Make sure that the GPIO pin we want isn't already in use for some
+* built-in hardware function. We have to check this for every
+* requested pin.
+*/
+   debug("%s: request bank %d offset %d: ", __func__, priv->bank, offset);
+   val = inl(>own[priv->bank]);
+   if (!(val & (1UL << offset))) {
+   debug("gpio is reserved for internal use\n");
+   return -EPERM;
+   }
+   debug("ok\n");
+
+   return 0;
+}
+
+static int broadwell_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+   struct broadwell_bank_priv *priv = dev_get_priv(dev);
+   struct pch_lp_gpio_regs *regs = priv->regs;
+
+   setio_le32(>config[priv->offset + offset], CONFA_DIR_INPUT);
+
+   return 0;
+}
+
+static int broadwell_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+   struct broadwell_bank_priv *priv = dev_get_priv(dev);
+   struct pch_lp_gpio_regs *regs = priv->regs;
+
+   return inl(>config[priv->offset + offset]) & CONFA_LEVEL_HIGH ?
+   1 : 0;
+}
+
+static int broadwell_gpio_set_value(struct udevice *dev, unsigned offset,
+   int value)
+{
+   struct broadwell_bank_priv *priv = dev_get_priv(dev);
+   struct pch_lp_gpio_regs *regs = priv->regs;
+
+   debug("%s: dev=%s, offset=%d, value=%d\n", __func__, dev->name, offset,
+ value);
+   clrsetio_le32(>config[priv->offset + offset], CONFA_OUTPUT_HIGH,
+ value ? CONFA_OUTPUT_HIGH : 0);
+
+   return 0;
+}
+
+static int broadwell_gpio_direction_output(struct udevice *dev, unsigned 
offset,
+  int value)
+{
+   struct broadwell_bank_priv *priv = dev_get_priv(dev);
+   struct pch_lp_gpio_regs *regs = priv->regs;
+
+   broadwell_gpio_set_value(dev, offset, value);
+   clrio_le32(>config[priv->offset + offset], CONFA_DIR_INPUT);
+
+   return 0;
+}
+
+static int broadwell_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+   struct broadwell_bank_priv *priv = dev_get_priv(dev);
+   struct pch_lp_gpio_regs *regs = priv->regs;
+   u32 mask = 

Re: [U-Boot] [PATCH V5] ARM: Various: Future-proof serial platdata

[Simon Glass]

On 2 March 2016 at 04:38, Adam Ford  wrote:
> A few boards still use ns16550_platdata structures, but assume the structure
> is going to be in a specific order. By explicitly naming each entry,
> this should also help 'future-proof' in the event the structure changes.
>
> Tested on the Logic PD Torpedo + Wireless.
>
> I only changed a handful of devices that used the same syntax as the Logic
> board.  Appologies if I missed one or stepped on toes.  Thanks to Derald Woods
> and Alexander Graf.
>
> Signed-off-by: Adam Ford 
>
> V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c
>
> V4: Fix subject heading
>
> V3: Remove  reg_offset out in all the structs. It was reverted out, and and if
> it did exist, it would get initialized to 0 by default.
>
> V2: I hastily copy-pasted the boards without looking at the UART number.
> This addresses 3 boards that use UART3 and not UART1.
> ---
>  arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 8 
>  board/isee/igep00x0/igep00x0.c   | 6 +++---
>  board/logicpd/omap3som/omap3logic.c  | 6 +++---
>  board/logicpd/zoom1/zoom1.c  | 6 +++---
>  board/overo/overo.c  | 6 +++---
>  board/quipos/cairo/cairo.c   | 6 +++---
>  board/ti/beagle/beagle.c | 6 +++---
>  board/timll/devkit8000/devkit8000.c  | 6 +++---
>  8 files changed, 25 insertions(+), 25 deletions(-)

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[U-Boot] [PATCH 58/69] x86: broadwell: Add power-control support

[Simon Glass]

Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/broadwell/Makefile  |   1 +
 arch/x86/cpu/broadwell/power_state.c |  89 +
 arch/x86/include/asm/arch-broadwell/pm.h | 129 +++
 3 files changed, 219 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/power_state.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/pm.h

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index a542fef..5a62afa 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -10,5 +10,6 @@ obj-y += lpc.o
 obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
+obj-y += power_state.o
 obj-y += refcode.o
 obj-y += sata.o
diff --git a/arch/x86/cpu/broadwell/power_state.c 
b/arch/x86/cpu/broadwell/power_state.c
new file mode 100644
index 000..3380323
--- /dev/null
+++ b/arch/x86/cpu/broadwell/power_state.c
@@ -0,0 +1,89 @@
+/*
+ * From coreboot src/soc/intel/broadwell/romstage/power_state.c
+ *
+ * Copyright (C) 2016 Google, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+static int prev_sleep_state(struct chipset_power_state *ps)
+{
+   /* Default to S0. */
+   int prev_sleep_state = SLEEP_STATE_S0;
+
+   if (ps->pm1_sts & WAK_STS) {
+   switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
+#if CONFIG_HAVE_ACPI_RESUME
+   case SLP_TYP_S3:
+   prev_sleep_state = SLEEP_STATE_S3;
+   break;
+#endif
+   case SLP_TYP_S5:
+   prev_sleep_state = SLEEP_STATE_S5;
+   break;
+   }
+   /* Clear SLP_TYP. */
+   outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+   }
+
+   if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
+   prev_sleep_state = SLEEP_STATE_S5;
+
+   return prev_sleep_state;
+}
+
+static void dump_power_state(struct chipset_power_state *ps)
+{
+   debug("PM1_STS:   %04x\n", ps->pm1_sts);
+   debug("PM1_EN:%04x\n", ps->pm1_en);
+   debug("PM1_CNT:   %08x\n", ps->pm1_cnt);
+   debug("TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
+
+   debug("GPE0_STS:  %08x %08x %08x %08x\n",
+ ps->gpe0_sts[0], ps->gpe0_sts[1],
+ ps->gpe0_sts[2], ps->gpe0_sts[3]);
+   debug("GPE0_EN:   %08x %08x %08x %08x\n",
+ ps->gpe0_en[0], ps->gpe0_en[1],
+ ps->gpe0_en[2], ps->gpe0_en[3]);
+
+   debug("GEN_PMCON: %04x %04x %04x\n",
+ ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
+
+   debug("Previous Sleep State: S%d\n",
+ ps->prev_sleep_state);
+}
+
+/* Fill power state structure from ACPI PM registers */
+void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps)
+{
+   ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
+   ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
+   ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+   ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
+   ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
+   ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
+   ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
+   ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
+   ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
+   ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
+   ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
+   ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
+   ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
+
+   dm_pci_read_config16(pch_dev, GEN_PMCON_1, >gen_pmcon1);
+   dm_pci_read_config16(pch_dev, GEN_PMCON_2, >gen_pmcon2);
+   dm_pci_read_config16(pch_dev, GEN_PMCON_3, >gen_pmcon3);
+
+   ps->prev_sleep_state = prev_sleep_state(ps);
+
+   dump_power_state(ps);
+}
diff --git a/arch/x86/include/asm/arch-broadwell/pm.h 
b/arch/x86/include/asm/arch-broadwell/pm.h
new file mode 100644
index 000..279dde9
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pm.h
@@ -0,0 +1,129 @@
+/*
+ * From coreboot src/soc/intel/broadwell/include/soc/pm.h
+ *
+ * Copyright (C) 2016 Google, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __asm_arch_pm_h
+#define __asm_arch_pm_h
+
+#define PM1_STS0x00
+#define  WAK_STS   (1 << 15)
+#define  PCIEXPWAK_STS (1 << 14)
+#define  PRBTNOR_STS   (1 << 11)
+#define  RTC_STS   (1 << 10)
+#define  PWRBTN_STS(1 << 8)
+#define  GBL_STS   (1 << 5)
+#define  BM_STS(1 << 4)
+#define  TMROF_STS (1 << 0)
+#define PM1_EN  

[U-Boot] [PATCH 38/69] x86: Move common MRC Kconfig options to the common file

[Simon Glass]

At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.

Signed-off-by: Simon Glass 
---

 arch/x86/Kconfig   | 39 +++
 arch/x86/cpu/ivybridge/Kconfig | 27 +--
 2 files changed, 40 insertions(+), 26 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a0bd344..29df78c 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -266,6 +266,45 @@ config ENABLE_MRC_CACHE
  to be used for speeding up boot time on future reboots and/or
  power cycles.
 
+config HAVE_MRC
+bool "Add a System Agent binary"
+   depends on !HAVE_FSP
+help
+  Select this option to add a System Agent binary to
+  the resulting U-Boot image. MRC stands for Memory Reference Code.
+  It is a binary blob which U-Boot uses to set up SDRAM.
+
+  Note: Without this binary U-Boot will not be able to set up its
+  SDRAM so will not boot.
+
+config CACHE_MRC_BIN
+   bool
+   depends on HAVE_MRC
+   default n
+
+config CACHE_MRC_SIZE_KB
+   int
+   depends on HAVE_MRC
+   default 512
+
+config DCACHE_RAM_BASE
+   hex
+   depends on HAVE_MRC
+
+config DCACHE_RAM_SIZE
+   hex
+   depends on HAVE_MRC
+   default 0x4
+
+config DCACHE_RAM_MRC_VAR_SIZE
+   hex
+   depends on HAVE_MRC
+   help
+ This is the amount of CAR (Cache as RAM) reserved for use by the
+ memory reference code. This depends on the implementation of the
+ memory reference code and must be set correctly or the board will
+ not boot.
+
 config SMP
bool "Enable Symmetric Multiprocessing"
default n
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 0819347..e23d01a 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -7,43 +7,18 @@
 
 config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
-   select CACHE_MRC_BIN
+   select CACHE_MRC_BIN if HAVE_MRC
 
 if NORTHBRIDGE_INTEL_IVYBRIDGE
 
-config CACHE_MRC_BIN
-   bool
-   default n
-
-config CACHE_MRC_SIZE_KB
-   int
-   default 512
-
 config DCACHE_RAM_BASE
-   hex
default 0xff7e
 
 config DCACHE_RAM_SIZE
-   hex
default 0x2
 
-config HAVE_MRC
-bool "Add a System Agent binary"
-help
-  Select this option to add a System Agent binary to
-  the resulting U-Boot image. MRC stands for Memory Reference Code.
-  It is a binary blob which U-Boot uses to set up SDRAM.
-
-  Note: Without this binary U-Boot will not be able to set up its
-  SDRAM so will not boot.
-
 config DCACHE_RAM_MRC_VAR_SIZE
-   hex
default 0x4000
-   help
- This is the amount of CAR (Cache as RAM) reserved for use by the
- memory reference code. This should be set to 16KB (0x4000 hex)
- so that MRC has enough space to run.
 
 config CPU_SPECIFIC_OPTIONS
def_bool y
-- 
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[U-Boot] [PATCH 66/69] x86: Update README for new developments

[Simon Glass]

Update a few points which have become out-of-date.

Signed-off-by: Simon Glass 
---

 doc/README.x86 | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/doc/README.x86 b/doc/README.x86
index a3f45c7..b87fec4 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -20,8 +20,17 @@ most of the low-level details.
 
 U-Boot also supports booting directly from x86 reset vector, without coreboot.
 In this case, known as bare mode, from the fact that it runs on the
-'bare metal', U-Boot acts like a BIOS replacement. Currently Link, QEMU x86
-targets and all Intel boards support running U-Boot 'bare metal'.
+'bare metal', U-Boot acts like a BIOS replacement. The following platforms
+are supported:
+
+   - Bayleybay
+   - Cougarcanyon 2 CRB
+   - Crown Bay CRB
+   - Galileo
+   - Link (Chromebook Pixel)
+   - Minnowboard MAX
+   - Samus (Chromebook Pixel 2015)
+   - QEMU x86
 
 As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
 Linux kernel as part of a FIT image. It also supports a compressed zImage.
@@ -371,7 +380,8 @@ options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
 
 Driver Model
 
-x86 has been converted to use driver model for serial and GPIO.
+x86 has been converted to use driver model for serial, GPIO, SPI, SPI flash,
+keyboard, real-time clock, USB. Video is in progress.
 
 Device Tree
 ---
-- 
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[U-Boot] [PATCH 61/69] x86: broadwell: Add support for high-speed I/O lane with ME

[Simon Glass]

Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/broadwell/Makefile |  1 +
 arch/x86/cpu/broadwell/me.c | 57 +
 2 files changed, 58 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/me.c

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 012798f..7edb6f6 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -7,6 +7,7 @@
 obj-y += cpu.o
 obj-y += iobp.o
 obj-y += lpc.o
+obj-y += me.o
 obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
diff --git a/arch/x86/cpu/broadwell/me.c b/arch/x86/cpu/broadwell/me.c
new file mode 100644
index 000..e03b87c
--- /dev/null
+++ b/arch/x86/cpu/broadwell/me.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ *
+ * Based on code from coreboot src/soc/intel/broadwell/me_status.c
+ */
+
+#include 
+#include 
+#include 
+
+static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int 
offset)
+{
+   u32 dword;
+
+   dm_pci_read_config32(dev, offset, );
+   memcpy(ptr, , sizeof(dword));
+}
+
+int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp,
+ uint16_t *checksump)
+{
+   int count;
+   u32 hsiover;
+   struct me_hfs hfs;
+
+   /* Query for HSIO version, overloads H_GS and HFS */
+   dm_pci_write_config32(dev, PCI_ME_H_GS,
+ ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
+
+   /* Must wait for ME acknowledgement */
+   for (count = ME_RETRY; count > 0; --count) {
+   me_read_dword_ptr(dev, , PCI_ME_HFS);
+   if (hfs.bios_msg_ack)
+   break;
+   udelay(ME_DELAY);
+   }
+   if (!count) {
+   debug("ERROR: ME failed to respond\n");
+   return -ETIMEDOUT;
+   }
+
+   /* HSIO version should be in HFS_5 */
+   dm_pci_read_config32(dev, PCI_ME_HFS5, );
+   *versionp = hsiover >> 16;
+   *checksump = hsiover & 0x;
+
+   debug("ME: HSIO Version: %d (CRC 0x%04x)\n",
+ *versionp, *checksump);
+
+   /* Reset registers to normal behavior */
+   dm_pci_write_config32(dev, PCI_ME_H_GS,
+ ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
+
+   return 0;
+}
-- 
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[U-Boot] [PATCH 53/69] x86: broadwell: Add a pinctrl driver

[Simon Glass]

GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/broadwell/Makefile|   1 +
 arch/x86/cpu/broadwell/pinctrl_broadwell.c | 278 +
 arch/x86/include/asm/arch-broadwell/gpio.h |  91 +++
 .../gpio/intel,x86-broadwell-pinctrl.txt   | 208 +++
 include/dt-bindings/gpio/x86-gpio.h|  12 +
 5 files changed, 590 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/pinctrl_broadwell.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/gpio.h
 create mode 100644 
doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 128829a..db60e30 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -7,3 +7,4 @@
 obj-y += cpu.o
 obj-y += iobp.o
 obj-y += pch.o
+obj-y += pinctrl_broadwell.o
diff --git a/arch/x86/cpu/broadwell/pinctrl_broadwell.c 
b/arch/x86/cpu/broadwell/pinctrl_broadwell.c
new file mode 100644
index 000..2a3fced
--- /dev/null
+++ b/arch/x86/cpu/broadwell/pinctrl_broadwell.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+   MAX_GPIOS   = 95,
+};
+
+#define PIRQ_SHIFT 16
+#define CONF_MASK  0x
+
+struct pin_info {
+   int node;
+   int phandle;
+   bool mode_gpio;
+   bool dir_input;
+   bool invert;
+   bool trigger_level;
+   bool output_high;
+   bool sense_disable;
+   bool owner_gpio;
+   bool route_smi;
+   bool irq_enable;
+   bool reset_rsmrst;
+   bool pirq_apic_route;
+};
+
+static int broadwell_pinctrl_read_configs(struct udevice *dev,
+ struct pin_info *conf, int max_pins)
+{
+   const void *blob = gd->fdt_blob;
+   int count = 0;
+   int node;
+
+   debug("%s: starting\n", __func__);
+   for (node = fdt_first_subnode(blob, dev->of_offset);
+node > 0;
+node = fdt_next_subnode(blob, node)) {
+   int phandle = fdt_get_phandle(blob, node);
+
+   if (!phandle)
+   continue;
+   if (count == max_pins)
+   return -ENOSPC;
+
+   /* We've found a new configuration */
+   memset(conf, '\0', sizeof(*conf));
+   conf->node = node;
+   conf->phandle = phandle;
+   conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio");
+   if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT)
+   conf->dir_input = true;
+   conf->invert = fdtdec_get_bool(blob, node, "invert");
+   if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL)
+   conf->trigger_level = true;
+   if (fdtdec_get_int(blob, node, "output-value", -1) == 1)
+   conf->output_high = true;
+   conf->sense_disable = fdtdec_get_bool(blob, node,
+ "sense-disable");
+   if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO)
+   conf->owner_gpio = true;
+   if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI)
+   conf->route_smi = true;
+   conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable");
+   conf->reset_rsmrst = fdtdec_get_bool(blob, node,
+"reset-rsmrst");
+   if (fdtdec_get_int(blob, node, "pirq-apic", -1) ==
+   PIRQ_APIC_ROUTE)
+   conf->pirq_apic_route = true;
+   debug("config: phandle=%d\n", phandle);
+   count++;
+   conf++;
+   }
+   debug("%s: Found %d configurations\n", __func__, count);
+
+   return count;
+}
+
+static int broadwell_pinctrl_lookup_phandle(struct pin_info *conf,
+   int conf_count, int phandle)
+{
+   int i;
+
+   for (i = 0; i < conf_count; i++) {
+   if (conf[i].phandle == phandle)
+   return i;
+   }
+
+   return -ENOENT;
+}
+
+static int broadwell_pinctrl_read_pins(struct udevice *dev,
+   struct pin_info *conf, int conf_count, int gpio_conf[],
+   int num_gpios)
+{
+   const void *blob = gd->fdt_blob;
+   int count = 0;
+   int node;
+
+   for 

[U-Boot] [PATCH 37/69] x86: Allow I/O functions to use pointers

[Simon Glass]

It is common with memory-mapped I/O to use the address of a structure member
to access memory, as in:

   struct some_regs {
  u32 ctrl;
  u32 data;
   }

   struct some_regs *regs = (struct some_regs *)BASE_ADDRESS;

   writel(1, >ctrl);
   writel(2, >data);

This does not currently work with inl(), outl(), etc. Add a cast to permit
this.

Signed-off-by: Simon Glass 
---

 arch/x86/include/asm/io.h | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 38b543d..d2c6e2e 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -202,7 +202,7 @@ out:
  * Talk about misusing macros..
  */
 #define __OUT1(s,x) \
-static inline void out##s(unsigned x value, unsigned short port) {
+static inline void _out##s(unsigned x value, unsigned short port) {
 
 #define __OUT2(s,s1,s2) \
 __asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
@@ -213,7 +213,7 @@ __OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); 
} \
 __OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" 
(port));}
 
 #define __IN1(s) \
-static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v;
+static inline RETURN_TYPE _in##s(unsigned short port) { RETURN_TYPE _v;
 
 #define __IN2(s,s1,s2) \
 __asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
@@ -242,10 +242,18 @@ __IN(w,"")
 __IN(l,"")
 #undef RETURN_TYPE
 
+#define inb(port)  _inb((uintptr_t)(port))
+#define inw(port)  _inw((uintptr_t)(port))
+#define inl(port)  _inl((uintptr_t)(port))
+
 __OUT(b,"b",char)
 __OUT(w,"w",short)
 __OUT(l,,int)
 
+#define outb(val, port)_outb(val, (uintptr_t)(port))
+#define outw(val, port)_outw(val, (uintptr_t)(port))
+#define outl(val, port)_outl(val, (uintptr_t)(port))
+
 __INS(b)
 __INS(w)
 __INS(l)
-- 
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[U-Boot] [PATCH 43/69] x86: Update microcode for secondary CPUs

[Simon Glass]

Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/cpu.c   | 1 +
 arch/x86/cpu/intel_common/car.S  | 2 ++
 arch/x86/cpu/mp_init.c   | 6 --
 arch/x86/include/asm/microcode.h | 3 +++
 arch/x86/lib/fsp/fsp_car.S   | 2 ++
 5 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 8eb676c..fcc1980 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S
index 81ac976..a7ae9b1 100644
--- a/arch/x86/cpu/intel_common/car.S
+++ b/arch/x86/cpu/intel_common/car.S
@@ -237,5 +237,7 @@ mtrr_table_end:
.align 4
 _dt_ucode_base_size:
/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base:/* Declared in micrcode.h */
.long   0   /* microcode base */
.long   0   /* microcode size */
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 94ddbbb..6b5886a 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -248,8 +248,10 @@ static int load_sipi_vector(atomic_t **ap_countp, int 
num_cpus)
if (!stack)
return -ENOMEM;
params->stack_top = (u32)(stack + size);
-
-   params->microcode_ptr = 0;
+#ifndef CONFIG_QEMU
+   params->microcode_ptr = ucode_base;
+   debug("Microcode at %x\n", params->microcode_ptr);
+#endif
params->msr_table_ptr = (u32)msr_save;
ret = save_bsp_msrs(msr_save, sizeof(msr_save));
if (ret < 0)
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 0478935..29bf060 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -9,6 +9,9 @@
 
 #ifndef __ASSEMBLY__
 
+/* This is a declaration for ucode_base in start.S */
+extern u32 ucode_base;
+
 /**
  * microcode_update_intel() - Apply microcode updates
  *
diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S
index 15b3751..fbe8aef 100644
--- a/arch/x86/lib/fsp/fsp_car.S
+++ b/arch/x86/lib/fsp/fsp_car.S
@@ -102,6 +102,8 @@ temp_ram_init_romstack:
 temp_ram_init_params:
 _dt_ucode_base_size:
/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base:/* Declared in micrcode.h */
.long   0   /* microcode base */
.long   0   /* microcode size */
.long   CONFIG_SYS_MONITOR_BASE /* code region base */
-- 
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[U-Boot] [PATCH 45/69] x86: Add an ICH6 pin configuration driver

[Simon Glass]

Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.

The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:

- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed

It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH

However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.

Also add an 'invert' property to support inverting the input.

Signed-off-by: Simon Glass 
---

 arch/x86/include/asm/cpu.h |   1 +
 arch/x86/lib/Makefile  |   1 +
 arch/x86/lib/pinctrl_ich6.c| 216 +
 .../gpio/intel,x86-pinctrl.txt |   1 +
 4 files changed, 219 insertions(+)
 create mode 100644 arch/x86/lib/pinctrl_ich6.c

diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 987dc65..85386da 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -54,6 +54,7 @@ enum {
X86_NONE,
X86_SYSCON_ME,  /* Intel Management Engine */
X86_SYSCON_GMA, /* Intel Graphics Media Accelerator */
+   X86_SYSCON_PINCONF, /* Intel x86 pin configuration */
 };
 
 struct cpuid_result {
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 4fc1936..1ff8533 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -22,6 +22,7 @@ obj-y += cmd_mtrr.o
 obj-y  += northbridge-uclass.o
 obj-$(CONFIG_I8259_PIC) += i8259.o
 obj-$(CONFIG_I8254_TIMER) += i8254.o
+obj-y  += pinctrl_ich6.o
 obj-y  += pirq_routing.o
 obj-y  += relocate.o
 obj-y += physmem.o
diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c
new file mode 100644
index 000..758fd87
--- /dev/null
+++ b/arch/x86/lib/pinctrl_ich6.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_USESEL_OFFSET(x)  (x)
+#define GPIO_IOSEL_OFFSET(x)   (x + 4)
+#define GPIO_LVL_OFFSET(x) ((x) ? (x) + 8 : 0xc)
+#define GPI_INV0x2c
+
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_SHIFT7
+#define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT)
+#define IOPAD_PULL_STRENGTH_SHIFT  9
+#define IOPAD_PULL_STRENGTH_MASK   (0x3 << IOPAD_PULL_STRENGTH_SHIFT)
+
+static int ich6_pinctrl_set_value(uint16_t base, unsigned offset, int value)
+{
+   if (value)
+   setio_le32(base, 1UL << offset);
+   else
+   clrio_le32(base, 1UL << offset);
+
+   return 0;
+}
+
+static int ich6_pinctrl_set_function(uint16_t base, unsigned offset, int func)
+{
+   if (func)
+   setio_le32(base, 1UL << offset);
+   else
+   clrio_le32(base, 1UL << offset);
+
+   return 0;
+}
+
+static int ich6_pinctrl_set_direction(uint16_t base, unsigned offset, int dir)
+{
+   if (!dir)
+   setio_le32(base, 1UL << offset);
+   else
+   clrio_le32(base, 1UL << offset);
+
+   return 0;
+}
+
+static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
+{
+   bool is_gpio, invert;
+   u32 gpio_offset[2];
+   int pad_offset;
+   int dir, val;
+   int ret;
+
+   /*
+* GPIO node is not mandatory, so we only do the pinmuxing if the
+* node exists.
+*/
+   ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
+  gpio_offset, 2);
+   if (!ret) {
+   /* Do we want to force the GPIO mode? */
+   is_gpio = fdtdec_get_bool(gd->fdt_blob, pin_node, "mode-gpio");
+   if (is_gpio)
+   ich6_pinctrl_set_function(GPIO_USESEL_OFFSET(gpiobase) +
+   gpio_offset[0], gpio_offset[1],
+   1);
+
+   dir = fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
+   if (dir != -1)
+   ich6_pinctrl_set_direction(GPIO_IOSEL_OFFSET(gpiobase) +
+

[U-Boot] [PATCH 46/69] x86: gpio: Allow the pinctrl driver to set up the pin config

[Simon Glass]

Rather than setting up the pin configuration in the GPIO driver, use the
new pinctrl driver to do it.

Signed-off-by: Simon Glass 
---

 configs/bayleybay_defconfig |   2 +
 configs/cougarcanyon2_defconfig |   2 +
 configs/crownbay_defconfig  |   2 +
 configs/galileo_defconfig   |   2 +
 configs/minnowmax_defconfig |   6 +-
 drivers/gpio/intel_ich6_gpio.c  | 180 ++--
 6 files changed, 17 insertions(+), 177 deletions(-)

diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 0879d1e..8e1347c 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -19,6 +19,8 @@ CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 09306bb..71028cf 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -8,6 +8,8 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_PCI=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 6bc4b8d..3c5891b 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -17,6 +17,8 @@ CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 925d3ee..b5863fc 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -13,6 +13,8 @@ CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index af6a8ec..848d5da 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -8,16 +8,18 @@ CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index c81d033..ae999af 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -32,6 +32,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -51,12 +53,6 @@ struct ich6_bank_priv {
 #define GPIO_IOSEL_OFFSET(x)   (x + 4)
 #define GPIO_LVL_OFFSET(x) (x + 8)
 
-#define IOPAD_MODE_MASK0x7
-#define IOPAD_PULL_ASSIGN_SHIFT7
-#define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT)
-#define IOPAD_PULL_STRENGTH_SHIFT  9
-#define IOPAD_PULL_STRENGTH_MASK   (0x3 << IOPAD_PULL_STRENGTH_SHIFT)
-
 /* TODO: Move this to device tree, or platform data */
 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
 {
@@ -77,23 +73,6 @@ static int _ich6_gpio_set_value(uint16_t base, unsigned 
offset, int value)
return 0;
 }
 
-static int _ich6_gpio_set_function(uint16_t base, unsigned offset, int func)
-{
-   u32 val;
-
-   if (func) {
-   val = inl(base);
-   val |= (1UL << offset);
-   outl(val, base);
-   } else {
-   val = inl(base);
-   val &= ~(1UL << offset);
-   outl(val, base);
-   }
-
-   return 0;
-}
-
 static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
 {
u32 val;
@@ -111,155 +90,8 @@ static int _ich6_gpio_set_direction(uint16_t base, 
unsigned offset, int dir)
return 0;
 }
 
-static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
-{
-   u32 gpio_offset[2];
-   int pad_offset;
-   int val;
-   int ret;
-   const void *prop;
-
-   /*
-* GPIO node is not mandatory, so we only do the
-* pinmuxing if the node exist.
-*/
-   ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
-gpio_offset, 2);
-   if (!ret) {
-   /* Do we want to force the GPIO mode? */
-   prop = fdt_getprop(gd->fdt_blob, pin_node, "mode-gpio",
- NULL);
-   if (prop)
-   _ich6_gpio_set_function(GPIO_USESEL_OFFSET
- 

[U-Boot] [PATCH 32/69] x86: ivybridge: Convert to use the common SDRAM code

[Simon Glass]

Adjust the existing implementation to use the new common SDRAM init code.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/ivybridge/sdram.c | 394 +
 1 file changed, 83 insertions(+), 311 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index af76826..3d43e71 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -40,57 +41,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CMOS_OFFSET_MRC_SEED_S3156
 #define CMOS_OFFSET_MRC_SEED_CHK   160
 
-/*
- * This function looks for the highest region of memory lower than 4GB which
- * has enough space for U-Boot where U-Boot is aligned on a page boundary.
- * It overrides the default implementation found elsewhere which simply
- * picks the end of ram, wherever that may be. The location of the stack,
- * the relocation address, and how far U-Boot is moved by relocation are
- * set in the global data structure.
- */
 ulong board_get_usable_ram_top(ulong total_size)
 {
-   struct memory_info *info = >arch.meminfo;
-   uintptr_t dest_addr = 0;
-   struct memory_area *largest = NULL;
-   int i;
-
-   /* Find largest area of memory below 4GB */
-
-   for (i = 0; i < info->num_areas; i++) {
-   struct memory_area *area = >area[i];
-
-   if (area->start >= 1ULL << 32)
-   continue;
-   if (!largest || area->size > largest->size)
-   largest = area;
-   }
-
-   /* If no suitable area was found, return an error. */
-   assert(largest);
-   if (!largest || largest->size < (2 << 20))
-   panic("No available memory found for relocation");
-
-   dest_addr = largest->start + largest->size;
-
-   return (ulong)dest_addr;
+   return sdram_common_board_get_usable_ram_top(total_size);
 }
 
 void dram_init_banksize(void)
 {
-   struct memory_info *info = >arch.meminfo;
-   int num_banks;
-   int i;
-
-   for (i = 0, num_banks = 0; i < info->num_areas; i++) {
-   struct memory_area *area = >area[i];
-
-   if (area->start >= 1ULL << 32)
-   continue;
-   gd->bd->bi_dram[num_banks].start = area->start;
-   gd->bd->bi_dram[num_banks].size = area->size;
-   num_banks++;
-   }
+   sdram_common_dram_init_banksize();
 }
 
 static int read_seed_from_cmos(struct pei_data *pei_data)
@@ -217,164 +175,10 @@ int misc_init_r(void)
return 0;
 }
 
-static const char *const ecc_decoder[] = {
-   "inactive",
-   "active on IO",
-   "disabled on IO",
-   "active"
-};
-
-/*
- * Dump in the log memory controller configuration as read from the memory
- * controller registers.
- */
-static void report_memory_config(void)
+static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev,
+  struct pei_data *pei_data)
 {
-   u32 addr_decoder_common, addr_decode_ch[2];
-   int i;
-
-   addr_decoder_common = readl(MCHBAR_REG(0x5000));
-   addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
-   addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
-
-   debug("memcfg DDR3 clock %d MHz\n",
- (readl(MCHBAR_REG(0x5e04)) * 1 * 2 + 50) / 100);
-   debug("memcfg channel assignment: A: %d, B % d, C % d\n",
- addr_decoder_common & 3,
- (addr_decoder_common >> 2) & 3,
- (addr_decoder_common >> 4) & 3);
-
-   for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
-   u32 ch_conf = addr_decode_ch[i];
-   debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
-   debug("   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
-   debug("   enhanced interleave mode %s\n",
- ((ch_conf >> 22) & 1) ? "on" : "off");
-   debug("   rank interleave %s\n",
- ((ch_conf >> 21) & 1) ? "on" : "off");
-   debug("   DIMMA %d MB width x%d %s rank%s\n",
- ((ch_conf >> 0) & 0xff) * 256,
- ((ch_conf >> 19) & 1) ? 16 : 8,
- ((ch_conf >> 17) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? "" : ", selected");
-   debug("   DIMMB %d MB width x%d %s rank%s\n",
- ((ch_conf >> 8) & 0xff) * 256,
- ((ch_conf >> 20) & 1) ? 16 : 8,
- ((ch_conf >> 18) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? ", selected" : "");
-   }
-}
-
-static void post_system_agent_init(struct pei_data *pei_data)
-{
-   /* If PCIe init is skipped, set the PEG clock gating */
-   if (!pei_data->pcie_init)
-   setbits_le32(MCHBAR_REG(0x7010), 1);
-}
-
-static 

[U-Boot] [PATCH 17/69] x86: Move microcode code to a common location

[Simon Glass]

This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/intel_common/Makefile | 3 +++
 arch/x86/cpu/intel_common/car.S| 2 +-
 arch/x86/cpu/{ivybridge => intel_common}/microcode_intel.c | 4 +++-
 arch/x86/cpu/ivybridge/Makefile| 1 -
 arch/x86/cpu/ivybridge/cpu.c   | 2 +-
 arch/x86/include/asm/{arch-ivybridge => }/microcode.h  | 0
 6 files changed, 8 insertions(+), 4 deletions(-)
 rename arch/x86/cpu/{ivybridge => intel_common}/microcode_intel.c (98%)
 rename arch/x86/include/asm/{arch-ivybridge => }/microcode.h (100%)

diff --git a/arch/x86/cpu/intel_common/Makefile 
b/arch/x86/cpu/intel_common/Makefile
index 5dd9573..bc7c3ff 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -5,3 +5,6 @@
 #
 
 obj-$(CONFIG_HAVE_MRC) += car.o
+ifndef CONFIG_TARGET_EFI
+obj-y += microcode_intel.o
+endif
diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S
index 1defabf..81ac976 100644
--- a/arch/x86/cpu/intel_common/car.S
+++ b/arch/x86/cpu/intel_common/car.S
@@ -12,12 +12,12 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 
 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c 
b/arch/x86/cpu/intel_common/microcode_intel.c
similarity index 98%
rename from arch/x86/cpu/ivybridge/microcode_intel.c
rename to arch/x86/cpu/intel_common/microcode_intel.c
index 2440a97..3054fab 100644
--- a/arch/x86/cpu/ivybridge/microcode_intel.c
+++ b/arch/x86/cpu/intel_common/microcode_intel.c
@@ -12,10 +12,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-#include 
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /**
  * struct microcode_update - standard microcode header from Intel
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index b117f0d..78006f1 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -13,7 +13,6 @@ obj-y += gma.o
 obj-y += lpc.o
 obj-y += me_status.o
 obj-y += model_206ax.o
-obj-y += microcode_intel.o
 obj-y += northbridge.o
 obj-y += report_platform.o
 obj-y += sata.o
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 948833c..c54e800 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -19,13 +19,13 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h 
b/arch/x86/include/asm/microcode.h
similarity index 100%
rename from arch/x86/include/asm/arch-ivybridge/microcode.h
rename to arch/x86/include/asm/microcode.h
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 11/69] input: i8042: Make sure the keyboard is enabled

[Simon Glass]

Add one more step into the init sequence. This fixes the keyboard on samus,
which otherwise does not work.

Signed-off-by: Simon Glass 
---

 drivers/input/i8042.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
index 661d7fd..12f8934 100644
--- a/drivers/input/i8042.c
+++ b/drivers/input/i8042.c
@@ -128,6 +128,12 @@ static int kbd_reset(int quirk)
if (kbd_cmd_read(CMD_SELF_TEST) != KBC_TEST_OK)
goto err;
 
+   if (kbd_write(I8042_DATA_REG, 0xf4) ||
+   kbd_read(I8042_DATA_REG) != KBD_ACK) {
+   debug("Keyboard enable failed ACK\n");
+   goto err;
+   }
+
/* keyboard reset */
if (kbd_write(I8042_DATA_REG, CMD_RESET_KBD) ||
kbd_read(I8042_DATA_REG) != KBD_ACK ||
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 44/69] x86: link: Add pin configuration to the device tree

[Simon Glass]

At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.

Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).

Signed-off-by: Simon Glass 
---

 arch/x86/dts/chromebook_link.dts | 151 +++
 1 file changed, 151 insertions(+)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 7ddbe43..ce0fe47 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -1,5 +1,7 @@
 /dts-v1/;
 
+#include 
+
 /include/ "skeleton.dtsi"
 /include/ "keyboard.dtsi"
 /include/ "serial.dtsi"
@@ -62,6 +64,155 @@
intel,duplicate-por;
};
 
+   pch_pinctrl {
+   compatible = "intel,x86-pinctrl";
+   u-boot,dm-pre-reloc;
+   reg = <0 0>;
+
+   gpio_a0 {
+   gpio-offset = <0 0>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_a1 {
+   gpio-offset = <0 >;
+   output-value = <1>;
+   };
+
+   gpio_a3 {
+   gpio-offset = <0 3>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_a5 {
+   gpio-offset = <0 5>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_a6 {
+   gpio-offset = <0 6>;
+   output-value = <1>;
+   };
+
+   gpio_a7 {
+   gpio-offset = <0 7>;
+   mode-gpio;
+   direction = ;
+   invert;
+   };
+
+   gpio_a8 {
+   gpio-offset = <0 8>;
+   mode-gpio;
+   direction = ;
+   invert;
+   };
+
+   gpio_a9 {
+   gpio-offset = <0 9>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_a10 {
+   u-boot,dm-pre-reloc;
+   gpio-offset = <0 10>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_a11 {
+   gpio-offset = <0 11>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_a12 {
+   gpio-offset = <0 12>;
+   mode-gpio;
+   direction = ;
+   invert;
+   };
+
+   gpio_a14 {
+   gpio-offset = <0 14>;
+   mode-gpio;
+   direction = ;
+   invert;
+   };
+
+   gpio_a15 {
+   gpio-offset = <0 15>;
+   mode-gpio;
+   direction = ;
+   invert;
+   };
+
+   gpio_a21 {
+   gpio-offset = <0 21>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_a24 {
+   gpio-offset = <0 24>;
+   mode-gpio;
+   output-value = <0>;
+   direction = ;
+   };
+
+   gpio_a28 {
+   gpio-offset = <0 28>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_b4 {
+   gpio-offset = <0x30 4>;
+   mode-gpio;
+   direction = ;
+   output-value = <1>;
+   };
+
+   gpio_b9 {
+   u-boot,dm-pre-reloc;
+   gpio-offset = <0x30 9>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_b10 {
+   u-boot,dm-pre-reloc;
+   gpio-offset = <0x30 10>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_b11 {
+   u-boot,dm-pre-reloc;
+   gpio-offset = <0x30 11>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_b25 {
+   gpio-offset = <0x30 25>;
+   mode-gpio;
+   direction = ;
+   };
+
+   gpio_b28 {
+   gpio-offset = <0x30 28>;
+   mode-gpio;
+   direction = ;
+  

[U-Boot] [PATCH 13/69] x86: Allow use of serial soon after relocation

[Simon Glass]

At present on x86 machines with use cache-as-RAM, the memory goes away just
before board_init_r() is called. This means that serial drivers are
no-longer unavailable, until initr_dm() it called, etc.

Any attempt to use printf() within this period will cause a hang.

To fix this, mark the serial devices as 'unavailable' when it is no-longer
available. Bring it back when serial_initialize() is called. This means that
the debug UART will be used instead for this period.

Signed-off-by: Simon Glass 
---

 common/board_f.c   | 7 +++
 drivers/serial/serial-uclass.c | 1 +
 2 files changed, 8 insertions(+)

diff --git a/common/board_f.c b/common/board_f.c
index 622093a..109025a 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -1096,6 +1096,13 @@ void board_init_f_r(void)
hang();
 
/*
+* The pre-relocation drivers may be using memory that has now gone
+* away. Mark serial as unavailable - this will fall back to the debug
+* UART if available.
+*/
+   gd->flags &= ~GD_FLG_SERIAL_READY;
+
+   /*
 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
 * Transfer execution from Flash to RAM by calculating the address
 * of the in-RAM copy of board_init_r() and calling it
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 1c447ff..6562be0 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -116,6 +116,7 @@ int serial_init(void)
 void serial_initialize(void)
 {
serial_find_console_or_panic();
+   gd->flags |= GD_FLG_SERIAL_READY;
 }
 
 static void _serial_putc(struct udevice *dev, char ch)
-- 
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[U-Boot] [PATCH 20/69] x86: Move common LPC code to its own place

[Simon Glass]

Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/intel_common/Makefile|   1 +
 arch/x86/cpu/intel_common/lpc_common.c| 102 ++
 arch/x86/cpu/ivybridge/bd82x6x.c  |  16 +
 arch/x86/cpu/ivybridge/lpc.c  |  73 ++---
 arch/x86/include/asm/arch-ivybridge/pch.h |   2 -
 arch/x86/include/asm/lpc_common.h |  59 +
 6 files changed, 168 insertions(+), 85 deletions(-)
 create mode 100644 arch/x86/cpu/intel_common/lpc_common.c
 create mode 100644 arch/x86/include/asm/lpc_common.h

diff --git a/arch/x86/cpu/intel_common/Makefile 
b/arch/x86/cpu/intel_common/Makefile
index bc7c3ff..36c150d 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -5,6 +5,7 @@
 #
 
 obj-$(CONFIG_HAVE_MRC) += car.o
+obj-y += lpc_common.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode_intel.o
 endif
diff --git a/arch/x86/cpu/intel_common/lpc_common.c 
b/arch/x86/cpu/intel_common/lpc_common.c
new file mode 100644
index 000..2a3b941
--- /dev/null
+++ b/arch/x86/cpu/intel_common/lpc_common.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(struct udevice *pch)
+{
+   u8 reg8;
+
+   dm_pci_read_config8(pch, 0xdc, );
+   reg8 &= ~(3 << 2);
+   reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+   dm_pci_write_config8(pch, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(struct udevice *pch)
+{
+   /* Enable port 80 POST on LPC */
+   dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
+   clrbits_le32(RCB_REG(GCS), 4);
+}
+
+/**
+ * lpc_early_init() - set up LPC serial ports and other early things
+ *
+ * @dev:   LPC device
+ * @return 0 if OK, -ve on error
+ */
+int lpc_common_early_init(struct udevice *dev)
+{
+   struct udevice *pch = dev->parent;
+   struct reg_info {
+   u32 base;
+   u32 size;
+   } values[4], *ptr;
+   int count;
+   int i;
+
+   count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+   "intel,gen-dec", (u32 *)values,
+   sizeof(values) / sizeof(u32));
+   if (count < 0)
+   return -EINVAL;
+
+   /* Set COM1/COM2 decode range */
+   dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010);
+
+   /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
+   dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ GAMEL_LPC_EN | COMA_LPC_EN);
+
+   /* Write all registers but use 0 if we run out of data */
+   count = count * sizeof(u32) / sizeof(values[0]);
+   for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
+   u32 reg = 0;
+
+   if (i < count)
+   reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
+   dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg);
+   }
+
+   enable_spi_prefetch(pch);
+
+   /* This is already done in start.S, but let's do it in C */
+   enable_port80_on_lpc(pch);
+
+   return 0;
+}
+
+int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect)
+{
+   uint8_t bios_cntl;
+
+   /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
+   dm_pci_read_config8(dev, bios_ctrl, _cntl);
+   if (protect) {
+   bios_cntl &= ~BIOS_CTRL_BIOSWE;
+   bios_cntl |= BIT(5);
+   } else {
+   bios_cntl |= BIOS_CTRL_BIOSWE;
+   bios_cntl &= ~BIT(5);
+   }
+   dm_pci_write_config8(dev, bios_ctrl, bios_cntl);
+
+   return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 55057e0..4c039ac 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -188,20 +189,7 @@ static int bd82x6x_pch_get_spi_base(struct udevice *dev, 
ulong *sbasep)
 
 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
 {
-   uint8_t bios_cntl;
-
-   /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
-   dm_pci_read_config8(dev, BIOS_CTRL, _cntl);
-   if (protect) {
-   bios_cntl &= ~BIOS_CTRL_BIOSWE;
-   bios_cntl |= BIT(5);
-   } else {
-   bios_cntl |= BIOS_CTRL_BIOSWE;
-   bios_cntl &= ~BIT(5);
-   }
-   dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
-
-   return 0;
+   return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
 }
 
 static int 

[U-Boot] [PATCH 10/69] pci: Correct a few comments and nits

[Simon Glass]

Two comments are missing a parameter and there is an extra blank line. Also
two of the region access macros are misnamed. Correct these problems.

Signed-off-by: Simon Glass 
---

 drivers/pci/pci-uclass.c | 1 -
 include/pci.h| 6 --
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 51e0e7a..b1b3642 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -291,7 +291,6 @@ int dm_pci_write_config(struct udevice *dev, int offset, 
unsigned long value,
size);
 }
 
-
 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
 {
return pci_write_config(bdf, offset, value, PCI_SIZE_32);
diff --git a/include/pci.h b/include/pci.h
index db84744..87de7ab 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1007,6 +1007,7 @@ int dm_pci_hose_probe_bus(struct udevice *bus);
  *
  * @bus:   Bus to read from
  * @bdf:   PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:Register offset to read
  * @valuep:Place to put the returned value
  * @size:  Access size
  * @return 0 if OK, -ve on error
@@ -1019,6 +1020,7 @@ int pci_bus_read_config(struct udevice *bus, pci_dev_t 
bdf, int offset,
  *
  * @bus:   Bus to write from
  * @bdf:   PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:Register offset to write
  * @value: Value to write
  * @size:  Access size
  * @return 0 if OK, -ve on error
@@ -1260,9 +1262,9 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int 
flags);
 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
 #define dm_pci_virt_to_io(dev, addr) \
-   dm_dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+   dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
-   dm_dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+   dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
 
 /**
  * dm_pci_find_device() - find a device by vendor/device ID
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 15/69] x86: cpu: Add functions to return the family and stepping

[Simon Glass]

These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/cpu.c | 10 ++
 arch/x86/include/asm/cpu.h | 14 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 8800e09..e2aad19 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -333,6 +333,16 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t 
tfms)
c->x86_model += ((tfms >> 16) & 0xF) << 4;
 }
 
+u32 cpu_get_family_model(void)
+{
+   return gd->arch.x86_device & 0x0fff0ff0;
+}
+
+u32 cpu_get_stepping(void)
+{
+   return gd->arch.x86_device & 0xf;
+}
+
 int x86_cpu_init_f(void)
 {
const u32 em_rst = ~X86_CR0_EM;
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 18b0345..987dc65 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -260,4 +260,18 @@ void cpu_call32(ulong code_seg32, ulong target, ulong 
table);
  */
 int cpu_jump_to_64bit(ulong setup_base, ulong target);
 
+/**
+ * cpu_get_family_model() - Get the family and model for the CPU
+ *
+ * @return the CPU ID masked with 0x0fff0ff0
+ */
+u32 cpu_get_family_model(void);
+
+/**
+ * cpu_get_stepping() - Get the stepping value for the CPU
+ *
+ * @return the CPU ID masked with 0xf
+ */
+u32 cpu_get_stepping(void);
+
 #endif
-- 
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[U-Boot] [PATCH 42/69] x86: Add comments to the SIPI vector

[Simon Glass]

The Intel SIPI (start-up inter-processor interrupt) vector is the entry
point for each secondary CPU (also called an AP - applications processor).
The assembler and C code are linked, so add comments to indicate this.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/sipi_vector.S  | 1 +
 arch/x86/include/asm/sipi.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/x86/cpu/sipi_vector.S b/arch/x86/cpu/sipi_vector.S
index 0c4a157..94c0f5a 100644
--- a/arch/x86/cpu/sipi_vector.S
+++ b/arch/x86/cpu/sipi_vector.S
@@ -193,6 +193,7 @@ load_msr:
mov c_handler, %esi
call*%esi
 
+   /* This matches struct sipi_param */
.align  4
 .globl sipi_params
 sipi_params:
diff --git a/arch/x86/include/asm/sipi.h b/arch/x86/include/asm/sipi.h
index 25d7d31..da91a48 100644
--- a/arch/x86/include/asm/sipi.h
+++ b/arch/x86/include/asm/sipi.h
@@ -42,6 +42,7 @@ struct __packed sipi_params_16bit {
  * struct sipi_params - 32-bit SIP entry-point parameters
  *
  * These are used by the AP init code and must be set up before the APs start.
+ * The members must match with the sipi_params layout in sipi_vector.S.
  *
  * The stack area extends down from @stack_top, with @stack_size allocated
  * for each AP.
-- 
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[U-Boot] [PATCH 09/69] pci: Add functions to update PCI configuration registers

[Simon Glass]

It is common to read a config register value, clear and set some bits, then
write back the updated value. Add functions to do this in one step, for
convenience.

Signed-off-by: Simon Glass 
---

 drivers/pci/pci-uclass.c | 57 
 include/pci.h| 23 +++
 2 files changed, 80 insertions(+)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index d01bfc1..51e0e7a 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -252,6 +252,21 @@ int pci_bus_write_config(struct udevice *bus, pci_dev_t 
bdf, int offset,
return ops->write_config(bus, bdf, offset, value, size);
 }
 
+int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
+   u32 clr, u32 set)
+{
+   ulong val;
+   int ret;
+
+   ret = pci_bus_read_config(bus, bdf, offset, , PCI_SIZE_32);
+   if (ret)
+   return ret;
+   val &= ~clr;
+   val |= set;
+
+   return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
+}
+
 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
 enum pci_size_t size)
 {
@@ -420,6 +435,48 @@ int dm_pci_read_config32(struct udevice *dev, int offset, 
u32 *valuep)
return 0;
 }
 
+int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+   u8 val;
+   int ret;
+
+   ret = dm_pci_read_config8(dev, offset, );
+   if (ret)
+   return ret;
+   val &= ~clr;
+   val |= set;
+
+   return dm_pci_write_config8(dev, offset, val);
+}
+
+int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+   u16 val;
+   int ret;
+
+   ret = dm_pci_read_config16(dev, offset, );
+   if (ret)
+   return ret;
+   val &= ~clr;
+   val |= set;
+
+   return dm_pci_write_config16(dev, offset, val);
+}
+
+int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+   u32 val;
+   int ret;
+
+   ret = dm_pci_read_config32(dev, offset, );
+   if (ret)
+   return ret;
+   val &= ~clr;
+   val |= set;
+
+   return dm_pci_write_config32(dev, offset, val);
+}
+
 static void set_vga_bridge_bits(struct udevice *dev)
 {
struct udevice *parent = dev->parent;
diff --git a/include/pci.h b/include/pci.h
index 68548b0..db84744 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1027,6 +1027,21 @@ int pci_bus_write_config(struct udevice *bus, pci_dev_t 
bdf, int offset,
 unsigned long value, enum pci_size_t size);
 
 /**
+ * pci_bus_clrset_config32() - Update a configuration value for a device
+ *
+ * The register at @offset is updated to (oldvalue & ~clr) | set.
+ *
+ * @bus:   Bus to access
+ * @bdf:   PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:Register offset to update
+ * @clr:   Bits to clear
+ * @set:   Bits to set
+ * @return 0 if OK, -ve on error
+ */
+int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
+   u32 clr, u32 set);
+
+/**
  * Driver model PCI config access functions. Use these in preference to others
  * when you have a valid device
  */
@@ -1044,6 +1059,14 @@ int dm_pci_write_config8(struct udevice *dev, int 
offset, u8 value);
 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
 
+/**
+ * These permit convenient read/modify/write on PCI configuration. The
+ * register is updated to (oldvalue & ~clr) | set.
+ */
+int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
+int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
+int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
+
 /*
  * The following functions provide access to the above without needing the
  * size parameter. We are trying to encourage the use of the 8/16/32-style
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 12/69] malloc_simple: Add a little more debugging

[Simon Glass]

Output the pointer returned by each call to malloc(). This can be useful
when debugging memory problems.

Signed-off-by: Simon Glass 
---

 common/malloc_simple.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/common/malloc_simple.c b/common/malloc_simple.c
index 479a1e4..0f6bcbc 100644
--- a/common/malloc_simple.c
+++ b/common/malloc_simple.c
@@ -19,12 +19,15 @@ void *malloc_simple(size_t bytes)
void *ptr;
 
new_ptr = gd->malloc_ptr + bytes;
-   debug("%s: size=%zx, ptr=%lx, limit=%lx\n", __func__, bytes, new_ptr,
+   debug("%s: size=%zx, ptr=%lx, limit=%lx: ", __func__, bytes, new_ptr,
  gd->malloc_limit);
-   if (new_ptr > gd->malloc_limit)
+   if (new_ptr > gd->malloc_limit) {
+   debug("space exhausted\n");
return NULL;
+   }
ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes);
gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
+   debug("%lx\n", (ulong)ptr);
 
return ptr;
 }
-- 
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[U-Boot] [PATCH 08/69] gpio: Use const where possible

[Simon Glass]

Some functions do not change the struct gpio_desc parameter. Update these to
use const so this is clear.

Signed-off-by: Simon Glass 
---

 drivers/gpio/gpio-uclass.c | 10 +-
 include/asm-generic/gpio.h | 10 +-
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index b2a2ca8..b58d4e6 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -257,7 +257,7 @@ int gpio_free(unsigned gpio)
return _dm_gpio_free(desc.dev, desc.offset);
 }
 
-static int check_reserved(struct gpio_desc *desc, const char *func)
+static int check_reserved(const struct gpio_desc *desc, const char *func)
 {
struct gpio_dev_priv *uc_priv;
 
@@ -324,7 +324,7 @@ int gpio_direction_output(unsigned gpio, int value)
desc.offset, value);
 }
 
-int dm_gpio_get_value(struct gpio_desc *desc)
+int dm_gpio_get_value(const struct gpio_desc *desc)
 {
int value;
int ret;
@@ -338,7 +338,7 @@ int dm_gpio_get_value(struct gpio_desc *desc)
return desc->flags & GPIOD_ACTIVE_LOW ? !value : value;
 }
 
-int dm_gpio_set_value(struct gpio_desc *desc, int value)
+int dm_gpio_set_value(const struct gpio_desc *desc, int value)
 {
int ret;
 
@@ -577,7 +577,7 @@ int gpio_get_values_as_int(const int *gpio_list)
return vector;
 }
 
-int dm_gpio_get_values_as_int(struct gpio_desc *desc_list, int count)
+int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count)
 {
unsigned bitmask = 1;
unsigned vector = 0;
@@ -766,7 +766,7 @@ static int gpio_renumber(struct udevice *removed_dev)
return 0;
 }
 
-int gpio_get_number(struct gpio_desc *desc)
+int gpio_get_number(const struct gpio_desc *desc)
 {
struct udevice *dev = desc->dev;
struct gpio_dev_priv *uc_priv;
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 059f339..68b5f0b 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -133,7 +133,7 @@ struct gpio_desc {
  * previously returned by gpio_request_by_name()
  * @return true if valid, false if not
  */
-static inline bool dm_gpio_is_valid(struct gpio_desc *desc)
+static inline bool dm_gpio_is_valid(const struct gpio_desc *desc)
 {
return desc->dev != NULL;
 }
@@ -369,7 +369,7 @@ int gpio_get_values_as_int(const int *gpio_list);
  * @count: Number of GPIOs
  * @return resulting integer value, or -ve on error
  */
-int dm_gpio_get_values_as_int(struct gpio_desc *desc_list, int count);
+int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count);
 
 /**
  * gpio_claim_vector() - claim a number of GPIOs for input
@@ -536,9 +536,9 @@ int gpio_free_list_nodev(struct gpio_desc *desc, int count);
  * previously returned by gpio_request_by_name()
  * @return GPIO value (0 for inactive, 1 for active) or -ve on error
  */
-int dm_gpio_get_value(struct gpio_desc *desc);
+int dm_gpio_get_value(const struct gpio_desc *desc);
 
-int dm_gpio_set_value(struct gpio_desc *desc, int value);
+int dm_gpio_set_value(const struct gpio_desc *desc, int value);
 
 /**
  * dm_gpio_set_dir() - Set the direction for a GPIO
@@ -577,6 +577,6 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong 
flags);
  * previously returned by gpio_request_by_name()
  * @return GPIO number, or -ve if not found
  */
-int gpio_get_number(struct gpio_desc *desc);
+int gpio_get_number(const struct gpio_desc *desc);
 
 #endif /* _ASM_GENERIC_GPIO_H_ */
-- 
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[U-Boot] [PATCH 25/69] x86: ivybridge: Drop sandybridge_early_init()

[Simon Glass]

This function was removed in the previous clean-up. Drop it from the header
file also.

Signed-off-by: Simon Glass 
---

 arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h 
b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index c395d53..8e0f668 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -113,6 +113,4 @@
  */
 int bridge_silicon_revision(struct udevice *dev);
 
-void sandybridge_early_init(int chipset_type);
-
 #endif
-- 
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[U-Boot] [PATCH 18/69] x86: Create a common header for Intel register access

[Simon Glass]

There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.

An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).

Add a new header file for these registers, and move MCH into it.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/ivybridge/cpu.c  |  1 +
 arch/x86/cpu/ivybridge/gma.c  |  1 +
 arch/x86/cpu/ivybridge/northbridge.c  |  5 +++--
 arch/x86/cpu/ivybridge/sdram.c|  3 ++-
 arch/x86/include/asm/arch-ivybridge/sandybridge.h |  3 ---
 arch/x86/include/asm/intel_regs.h | 15 +++
 6 files changed, 22 insertions(+), 6 deletions(-)
 create mode 100644 arch/x86/include/asm/intel_regs.h

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c54e800..f847a2f 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 3b6291e..87e06e7 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/arch/x86/cpu/ivybridge/northbridge.c 
b/arch/x86/cpu/ivybridge/northbridge.c
index a066607..f7e0bc3 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -167,8 +168,8 @@ static void sandybridge_setup_northbridge_bars(struct 
udevice *dev)
debug("Setting up static registers\n");
dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
-   dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
-   dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
+   dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
+   dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
/* 64MB - busses 0-63 */
dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
dm_pci_write_config32(dev, PCIEXBAR + 4,
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e23c422..6f45071 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -682,7 +683,7 @@ int dram_init(void)
 {
struct pei_data pei_data __aligned(8) = {
.pei_version = PEI_VERSION,
-   .mchbar = DEFAULT_MCHBAR,
+   .mchbar = MCH_BASE_ADDRESS,
.dmibar = DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_PCIE_ECAM_BASE,
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h 
b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index d137d67..59b05cc 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -38,7 +38,6 @@
 #define IED_SIZE   0x40
 
 /* Northbridge BARs */
-#define DEFAULT_MCHBAR 0xfed1  /* 16 KB */
 #define DEFAULT_DMIBAR 0xfed18000  /* 4 KB */
 #define DEFAULT_EPBAR  0xfed19000  /* 4 KB */
 #define DEFAULT_RCBABASE   0xfed1c000
@@ -97,8 +96,6 @@
 /*
  * MCHBAR
  */
-#define MCHBAR_REG(reg)(DEFAULT_MCHBAR + (reg))
-
 #define SSKPD  0x5d14  /* 16bit (scratchpad) */
 #define BIOS_RESET_CPL 0x5da8  /* 8bit */
 
diff --git a/arch/x86/include/asm/intel_regs.h 
b/arch/x86/include/asm/intel_regs.h
new file mode 100644
index 000..61e0ec2
--- /dev/null
+++ b/arch/x86/include/asm/intel_regs.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __asm_intel_regs_h
+#define __asm_intel_regs_h
+
+/* Access the memory-controller hub */
+#define MCH_BASE_ADDRESS   0xfed1
+#define MCH_BASE_SIZE  0x8000
+#define MCHBAR_REG(reg)(MCH_BASE_ADDRESS + (reg))
+
+#endif
-- 
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[U-Boot] [PATCH 14/69] x86: cpu: Make the vendor table const

[Simon Glass]

This does not need to be modified at run-time, so make it const.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6c3a748..8800e09 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -71,7 +71,7 @@ struct cpuinfo_x86 {
  * List of cpu vendor strings along with their normalized
  * id values.
  */
-static struct {
+static const struct {
int vendor;
const char *name;
 } x86_vendors[] = {
-- 
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[U-Boot] [PATCH 41/69] x86: ivybridge: Show microcode version for each code

[Simon Glass]

Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/ivybridge/model_206ax.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c 
b/arch/x86/cpu/ivybridge/model_206ax.c
index 950132a..cef4256 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -458,7 +458,8 @@ static int model_206ax_get_info(struct udevice *dev, struct 
cpu_info *info)
 
msr = msr_read(MSR_IA32_PERF_CTL);
info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 100;
-   info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
+   info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+   1 << CPU_FEAT_UCODE;
 
return 0;
 }
-- 
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[U-Boot] [PATCH 16/69] x86: Move cache-as-RAM code into a common location

[Simon Glass]

This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/Makefile  | 1 +
 arch/x86/cpu/intel_common/Makefile | 7 +++
 arch/x86/cpu/{ivybridge => intel_common}/car.S | 0
 arch/x86/cpu/ivybridge/Makefile| 1 -
 4 files changed, 8 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/cpu/intel_common/Makefile
 rename arch/x86/cpu/{ivybridge => intel_common}/car.S (100%)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 2ff2377..2583809 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -18,6 +18,7 @@ AFLAGS_call32.o := -fpic -fshort-wchar
 
 extra-y += call32.o
 
+obj-y += intel_common/
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_EFI_APP) += efi/
diff --git a/arch/x86/cpu/intel_common/Makefile 
b/arch/x86/cpu/intel_common/Makefile
new file mode 100644
index 000..5dd9573
--- /dev/null
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_HAVE_MRC) += car.o
diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/intel_common/car.S
similarity index 100%
rename from arch/x86/cpu/ivybridge/car.S
rename to arch/x86/cpu/intel_common/car.S
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 9203219..b117f0d 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -7,7 +7,6 @@
 ifdef CONFIG_HAVE_FSP
 obj-y += fsp_configs.o ivybridge.o
 else
-obj-y += car.o
 obj-y += cpu.o
 obj-y += early_me.o
 obj-y += gma.o
-- 
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[U-Boot] [PATCH 26/69] x86: Move common PCH code into a common place

[Simon Glass]

The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass 
---

 arch/x86/cpu/intel_common/Makefile|  1 +
 arch/x86/cpu/intel_common/pch_common.c| 25 ++
 arch/x86/cpu/ivybridge/cpu.c  |  1 +
 arch/x86/cpu/ivybridge/sata.c | 47 +-
 arch/x86/include/asm/arch-ivybridge/pch.h | 53 -
 arch/x86/include/asm/pch_common.h | 56 +++
 board/intel/cougarcanyon2/cougarcanyon2.c |  1 +
 7 files changed, 100 insertions(+), 84 deletions(-)
 create mode 100644 arch/x86/cpu/intel_common/pch_common.c
 create mode 100644 arch/x86/include/asm/pch_common.h

diff --git a/arch/x86/cpu/intel_common/Makefile 
b/arch/x86/cpu/intel_common/Makefile
index 50023fe..066b7b5 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_HAVE_MRC) += me_status.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode_intel.o
 endif
+obj-y += pch_common.o
 obj-$(CONFIG_HAVE_MRC) += report_platform.o
diff --git a/arch/x86/cpu/intel_common/pch_common.c 
b/arch/x86/cpu/intel_common/pch_common.c
new file mode 100644
index 000..1f05b44
--- /dev/null
+++ b/arch/x86/cpu/intel_common/pch_common.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+
+u32 pch_common_sir_read(struct udevice *dev, int idx)
+{
+   u32 data;
+
+   dm_pci_write_config32(dev, SATA_SIRI, idx);
+   dm_pci_read_config32(dev, SATA_SIRD, );
+
+   return data;
+}
+
+void pch_common_sir_write(struct udevice *dev, int idx, u32 value)
+{
+   dm_pci_write_config32(dev, SATA_SIRI, idx);
+   dm_pci_write_config32(dev, SATA_SIRD, value);
+}
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index b8234ae..78fa73a 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index a59d9ed..c2dbab8 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -9,28 +9,13 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static inline u32 sir_read(struct udevice *dev, int idx)
-{
-   u32 data;
-
-   dm_pci_write_config32(dev, SATA_SIRI, idx);
-   dm_pci_read_config32(dev, SATA_SIRD, );
-
-   return data;
-}
-
-static inline void sir_write(struct udevice *dev, int idx, u32 value)
-{
-   dm_pci_write_config32(dev, SATA_SIRI, idx);
-   dm_pci_write_config32(dev, SATA_SIRD, value);
-}
-
 static void common_sata_init(struct udevice *dev, unsigned int port_map)
 {
u32 reg32;
@@ -177,27 +162,27 @@ static void bd82x6x_sata_init(struct udevice *dev, struct 
udevice *pch)
pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
 
/* Additional Programming Requirements */
-   sir_write(dev, 0x04, 0x1600);
-   sir_write(dev, 0x28, 0xa033);
-   reg32 = sir_read(dev, 0x54);
+   pch_common_sir_write(dev, 0x04, 0x1600);
+   pch_common_sir_write(dev, 0x28, 0xa033);
+   reg32 = pch_common_sir_read(dev, 0x54);
reg32 &= 0xff00;
reg32 |= 0xaa;
-   sir_write(dev, 0x54, reg32);
-   sir_write(dev, 0x64, 0x8484);
-   reg32 = sir_read(dev, 0x68);
+   pch_common_sir_write(dev, 0x54, reg32);
+   pch_common_sir_write(dev, 0x64, 0x8484);
+   reg32 = pch_common_sir_read(dev, 0x68);
reg32 &= 0x;
reg32 |= 0x;
-   sir_write(dev, 0x68, reg32);
-   reg32 = sir_read(dev, 0x78);
+   pch_common_sir_write(dev, 0x68, reg32);
+   reg32 = pch_common_sir_read(dev, 0x78);
reg32 &= 0x;
reg32 |= 0x;
-   sir_write(dev, 0x78, reg32);
-   sir_write(dev, 0x84, 0x001c7000);
-   sir_write(dev, 0x88, 0x88338822);
-   sir_write(dev, 0xa0, 0x001c7000);
-   sir_write(dev, 0xc4, 0x0c0c0c0c);
-   sir_write(dev, 0xc8, 0x0c0c0c0c);
-   sir_write(dev, 0xd4, 0x1000);
+   pch_common_sir_write(dev, 0x78, reg32);
+   pch_common_sir_write(dev, 0x84, 0x001c7000);
+   pch_common_sir_write(dev, 0x88, 0x88338822);
+   pch_common_sir_write(dev, 0xa0, 0x001c7000);
+   pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
+   pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
+   pch_common_sir_write(dev, 0xd4, 0x1000);
 
pch_iobp_update(pch, 0xea004001, 0x3fff, 0xc000);
pch_iobp_update(pch, 0xea00408a, 0xfcff, 0x0100);
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h 
b/arch/x86/include/asm/arch-ivybridge/pch.h
index e72ff2a..4725250 100644
--- 

[U-Boot] [PATCH 06/69] cpu: Add support for microcode version and CPU ID

[Simon Glass]

Some CPUs use microcode and each core can have a different version of
microcode loaded. Also some CPUs support the concept of an integer ID used
for identification purposes. Add support for these in the CPU uclass.

Signed-off-by: Simon Glass 
---

 cmd/cpu.c | 7 +++
 include/cpu.h | 5 +
 2 files changed, 12 insertions(+)

diff --git a/cmd/cpu.c b/cmd/cpu.c
index b4af64f..bc4dc5c 100644
--- a/cmd/cpu.c
+++ b/cmd/cpu.c
@@ -14,6 +14,7 @@
 static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
"L1 cache",
"MMU",
+   "Microcode",
 };
 
 static int print_cpu_list(bool detail)
@@ -58,6 +59,12 @@ static int print_cpu_list(bool detail)
}
}
printf("\n");
+   if (info.features & (1 << CPU_FEAT_UCODE)) {
+   printf("\tMicrocode version %#x\n",
+  plat->ucode_version);
+   }
+   if (info.features & (1 << CPU_FEAT_DEVICE_ID))
+   printf("\tDevice ID %#lx\n", plat->device_id);
}
 
return 0;
diff --git a/include/cpu.h b/include/cpu.h
index bfb0db2..bda5315 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -15,15 +15,20 @@
  * device.
  *
  * @cpu_id:Platform-specific way of identifying the CPU.
+ * @ucode_version: Microcode version, if CPU_FEAT_UCODE is set
  */
 struct cpu_platdata {
int cpu_id;
+   int ucode_version;
+   ulong device_id;
 };
 
 /* CPU features - mostly just a placeholder for now */
 enum {
CPU_FEAT_L1_CACHE   = 0,/* Supports level 1 cache */
CPU_FEAT_MMU= 1,/* Supports virtual memory */
+   CPU_FEAT_UCODE  = 2,/* Requires/uses microcode */
+   CPU_FEAT_DEVICE_ID  = 3,/* Provides a device ID */
 
CPU_FEAT_COUNT,
 };
-- 
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[U-Boot] [PATCH 03/69] dhry: Correct dhrystone calculation for fast machines

[Simon Glass]

At present samus reports about 5600 DMIPS. With the default iteration count
this is OK, but if 10 million runs are performed it overflows. Fix it.

Signed-off-by: Simon Glass 
---

 lib/dhry/cmd_dhry.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/lib/dhry/cmd_dhry.c b/lib/dhry/cmd_dhry.c
index 5dc191e..d7e1e6a 100644
--- a/lib/dhry/cmd_dhry.c
+++ b/lib/dhry/cmd_dhry.c
@@ -6,11 +6,13 @@
 
 #include 
 #include 
+#include 
 #include "dhry.h"
 
 static int do_dhry(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-   ulong start, duration, dhry_per_sec, vax_mips;
+   ulong start, duration, vax_mips;
+   u64 dhry_per_sec;
int iterations = 100;
 
if (argc > 1)
@@ -19,10 +21,10 @@ static int do_dhry(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
start = get_timer(0);
dhry(iterations);
duration = get_timer(start);
-   dhry_per_sec = iterations * 1000 / duration;
+   dhry_per_sec = lldiv(iterations * 1000ULL, duration);
vax_mips = dhry_per_sec / 1757;
printf("%d iterations in %lu ms: %lu/s, %lu DMIPS\n", iterations,
-  duration, dhry_per_sec, vax_mips);
+  duration, (ulong)dhry_per_sec, vax_mips);
 
return 0;
 }
-- 
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[U-Boot] [PATCH 04/69] syscon: Avoid returning a device on failure

[Simon Glass]

If the device cannot be probed, syscon_get_by_driver_data() will still
return a useful value in its devp parameter. Ensure that it returns NULL
instead.

Signed-off-by: Simon Glass 
---

 drivers/core/syscon-uclass.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index a0666d0..e03f46a 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -38,6 +38,7 @@ int syscon_get_by_driver_data(ulong driver_data, struct 
udevice **devp)
struct uclass *uc;
int ret;
 
+   *devp = NULL;
ret = uclass_get(UCLASS_SYSCON, );
if (ret)
return ret;
-- 
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[U-Boot] [PATCH 05/69] video: Allow simple-panel to be used without regulators

[Simon Glass]

At present simple-panel requires regulator support and will not build
without it. But some panels do not have a power supply, or at least not one
that can be controlled. Update the implementation to cope with this.

Signed-off-by: Simon Glass 
---

 drivers/video/simple_panel.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index c73f242..6219300 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -38,13 +38,15 @@ static int simple_panel_ofdata_to_platdata(struct udevice 
*dev)
struct simple_panel_priv *priv = dev_get_priv(dev);
int ret;
 
-   ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
-  "power-supply", >reg);
-   if (ret) {
-   debug("%s: Warning: cnnot get power supply: ret=%d\n",
- __func__, ret);
-   if (ret != -ENOENT)
-   return ret;
+   if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+   ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+  "power-supply", >reg);
+   if (ret) {
+   debug("%s: Warning: cnnot get power supply: ret=%d\n",
+ __func__, ret);
+   if (ret != -ENOENT)
+   return ret;
+   }
}
ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
   "backlight", >backlight);
@@ -69,7 +71,7 @@ static int simple_panel_probe(struct udevice *dev)
struct simple_panel_priv *priv = dev_get_priv(dev);
int ret;
 
-   if (priv->reg) {
+   if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
debug("%s: Enable regulator '%s'\n", __func__, priv->reg->name);
ret = regulator_set_enable(priv->reg, true);
if (ret)
-- 
2.7.0.rc3.207.g0ac5344

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