Re: [U-Boot] [PATCH] dm: mmc: socfpga: fix MMC_OPS support

[Marek Vasut]

On 10/26/2016 04:03 AM, Jaehoon Chung wrote:
> Hi,
> 
> On 10/25/2016 06:13 AM, Simon Glass wrote:
>> On 24 October 2016 at 10:24, Sylvain Lesne  wrote:
>>>
>>> Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with
>>> CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at
>>> runtime.
>>>
>>> This adds the missing fields in the driver declaration.
>>>
>>> Signed-off-by: Sylvain Lesne 
> 
> Applied on u-boot-mmc. Thanks!

Cool, thanks.

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH] armv8: QSPI: Add AHB bus 16MB+ size support

[Yuan Yao]

From: Yuan Yao 

The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 37 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 include/configs/ls1012a_common.h   |  1 +
 include/configs/ls1046ardb.h   |  1 +
 5 files changed, 41 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d68eeba..18d753e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -370,6 +370,40 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_QSPI_AHB_INIT
+/* Enable 4bytes address support and fast read */
+int qspi_ahb_init(void)
+{
+   u32 *qspi_lut, lut_key, *qspi_key;
+
+   qspi_key = (void *)CONFIG_SYS_QSPI_ADDR + 0x300;
+   qspi_lut = (void *)CONFIG_SYS_QSPI_ADDR + 0x310;
+
+   lut_key = in_be32(qspi_key);
+
+   if (lut_key == 0x5af05af0) {
+   /* That means the register is BE */
+   out_be32(qspi_key, 0x5af05af0);
+   out_be32(qspi_key + 1, 0x0002);
+   out_be32(qspi_lut, 0x0820040c);
+   out_be32(qspi_lut + 1, 0x1c080c08);
+   out_be32(qspi_lut + 2, 0x2400);
+   out_be32(qspi_key, 0x5af05af0);
+   out_be32(qspi_key + 1, 0x0001);
+   } else {
+   /* That means the register is LE */
+   out_le32(qspi_key, 0x5af05af0);
+   out_le32(qspi_key + 1, 0x0002);
+   out_le32(qspi_lut, 0x0820040c);
+   out_le32(qspi_lut + 1, 0x1c080c08);
+   out_le32(qspi_lut + 2, 0x2400);
+   out_le32(qspi_key, 0x5af05af0);
+   out_le32(qspi_key + 1, 0x0001);
+   }
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -379,6 +413,9 @@ int board_late_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
 #endif
+#ifdef CONFIG_QSPI_AHB_INIT
+   qspi_ahb_init();
+#endif
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..a28b1fd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018)
 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x0040)
 #define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0053)
+#define CONFIG_SYS_QSPI_ADDR   (CONFIG_SYS_IMMR + 0x0055)
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x0056)
 #define CONFIG_SYS_FSL_CSU_ADDR(CONFIG_SYS_IMMR + 
0x0051)
 #define CONFIG_SYS_FSL_GUTS_ADDR   (CONFIG_SYS_IMMR + 0x00ee)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 7acba27..8aefc76 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR   (CONFIG_SYS_IMMR + 0x0030)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR   (CONFIG_SYS_IMMR + 0x0031)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR   (CONFIG_SYS_IMMR + 0x0037)
+#define CONFIG_SYS_QSPI_ADDR   (CONFIG_SYS_IMMR + 0x010c)
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x0114)
 #define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0124)
 #define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR + 
0x011C0500)
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 80603c9..c1e1102 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -61,6 +61,7 @@
 
 #define FSL_QSPI_FLASH_SIZE(1 << 24)
 #define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_QSPI_AHB_INIT
 
 /*
  * Environment
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 2fe8fc1..662ecb1 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -209,6 +209,7 @@
 #define FSL_QSPI_FLASH_SIZE(1 << 26)
 #define FSL_QSPI_FLASH_NUM 2
 #define CONFIG_SPI_FLASH_BAR
+#define CONFIG_QSPI_AHB_INIT
 #endif
 
 /* SATA */
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH] dm: mmc: socfpga: fix MMC_OPS support

[Jaehoon Chung]

Hi,

On 10/25/2016 06:13 AM, Simon Glass wrote:
> On 24 October 2016 at 10:24, Sylvain Lesne  wrote:
>>
>> Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with
>> CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at
>> runtime.
>>
>> This adds the missing fields in the driver declaration.
>>
>> Signed-off-by: Sylvain Lesne 

Applied on u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

>> ---
>>
>> Hi,
>>
>> I might be missing something, but with the latest master, on a
>> socfpga board, I get the following failure:
>>
>> U-Boot SPL 2016.11-rc2-00072-g869588d-dirty (Oct 24 2016 - 17:18:22)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
>> drivers/ddr/altera/sequencer.c: Calibration complete
>> Trying to boot from MMC1
>> spl: partition error
>> MMC: block number 0xx exceeds max(0xx)
>> mmc_load_image_raw_sector: mmc block read error
>> SPL: failed to boot from all boot devices
>> ### ERROR ### Please RESET the board ###
>>
>> After some digging, it seems that the socfpga_dw_mmc driver slipped
>> through the cracks during some steps of the DM conversion, so I
>> added the missing fields of the driver declaration, mimicking what's
>> done in the other dw_mmc_* drivers, and it works on my board.
>>
>> (Also, this is kind of unrelated, but it looks like the error
>> message 'MMC: block number 0xx exceeds max(0xx)' has a formatting
>> issue!)
>>
>> ---
>>  drivers/mmc/socfpga_dw_mmc.c | 2 ++
>>  1 file changed, 2 insertions(+)
> 
> 
> Reviewed-by: Simon Glass 
> 
> The formatting issue may be due to tiny-printf.
> 
> - Simon
> 
> 
> 

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Re: [U-Boot] [PATCH] mmc: sdhci: assign to clk_mul when host version is upper than SD3.0

[Jaehoon Chung]

On 10/21/2016 08:52 PM, Jaehoon Chung wrote:
> To prevent the wrong value check the SD version.
> 
> Signed-off-by: Jaehoon Chung 

Applied on u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

> ---
>  drivers/mmc/sdhci.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index 10ff57e..766e9ee 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -608,9 +608,11 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct 
> sdhci_host *host,
>* In case of Host Controller v3.00, find out whether clock
>* multiplier is supported.
>*/
> - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
> - host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
> - SDHCI_CLOCK_MUL_SHIFT;
> + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
> + caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
> + host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
> + SDHCI_CLOCK_MUL_SHIFT;
> + }
>  
>   return 0;
>  }
> 

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Re: [U-Boot] [PATCH] mmc: add the device name in debugging message for supplying vmmc

[Jaehoon Chung]

On 10/24/2016 05:51 PM, Peng Fan wrote:
> Hi Chung,
> On Mon, Oct 24, 2016 at 03:22:22PM +0900, Jaehoon Chung wrote:
>> If vmmc didn't supply, we didn't know which card didn't supply vmmc.
>> And changed from "put" to "debug".
>>
>> Signed-off-by: Jaehoon Chung 
> 
> Reviewed-by: Peng Fan 

Applied on u-boot-mmc. Thanks.

Best Regards,
Jaehoon Chung

> 
> Regards,
> Peng.
> 
>> ---
>> drivers/mmc/mmc.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
>> index 320413a..4380c7c 100644
>> --- a/drivers/mmc/mmc.c
>> +++ b/drivers/mmc/mmc.c
>> @@ -1595,7 +1595,7 @@ static int mmc_power_init(struct mmc *mmc)
>>  ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
>>_supply);
>>  if (ret) {
>> -puts("No vmmc supply\n");
>> +debug("%s: No vmmc supply\n", mmc->dev->name);
>>  return 0;
>>  }
>>
>> -- 
>> 2.10.1
>>
>> ___
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> 
> 
> 

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[U-Boot] [RFC PATCH v2 09/10] mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan

[Chris Packham]

This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.

[ Linux commit 154f50fbde539c20bbf74854461d932ebdace4d5 ]

Cc: Ezequiel García 
Signed-off-by: Chris Packham 
---

Changes in v2:
- New

 drivers/mtd/nand/pxa3xx_nand.c | 30 ++
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 432219c78831..de897ae41d1e 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1252,7 +1252,7 @@ static void pxa3xx_nand_config_tail(struct 
pxa3xx_nand_info *info)
info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
 }
 
-static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
+static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 {
struct pxa3xx_nand_platform_data *pdata = info->pdata;
uint32_t ndcr = nand_readl(info, NDCR);
@@ -1264,7 +1264,6 @@ static int pxa3xx_nand_detect_config(struct 
pxa3xx_nand_info *info)
info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
-   return 0;
 }
 
 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
@@ -1384,22 +1383,21 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
int ret;
uint16_t ecc_strength, ecc_step;
 
-   if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
-   goto KEEP_CONFIG;
-
-   ret = pxa3xx_nand_config_ident(info);
-   if (ret)
-   return ret;
-
-   ret = pxa3xx_nand_sensing(host);
-   if (ret) {
-   dev_info(>pdev->dev, "There is no chip on cs %d!\n",
-info->cs);
-
-   return ret;
+   if (pdata->keep_config) {
+   pxa3xx_nand_detect_config(info);
+   } else {
+   ret = pxa3xx_nand_config_ident(info);
+   if (ret)
+   return ret;
+   ret = pxa3xx_nand_sensing(host);
+   if (ret) {
+   dev_info(>pdev->dev,
+"There is no chip on cs %d!\n",
+info->cs);
+   return ret;
+   }
}
 
-KEEP_CONFIG:
/* Device detection must be done with ECC disabled */
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
nand_writel(info, NDECCCTRL, 0x0);
-- 
2.10.1

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[U-Boot] [RFC PATCH v2 10/10] mtd: nand: pxa3xx_nand: add support for partial chunks

[Chris Packham]

This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.

When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
this requirement, the data layout on NAND is a bit strange, with ECC
interleaved with data, at the end of each chunk.

When a 4-bits ECC configuration is used with 4 KB pages, the physical
data layout on the NAND looks like this:

| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |

So the data chunks have an equal size, 2080 bytes for each chunk,
which the driver supports properly.

When a 8-bits ECC configuration is used with 4KB pages, the physical
data layout on the NAND looks like this:

| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 
ECC | 64 spare | 30 ECC |

So, the spare area is stored in its own chunk, which has a different
size than the other chunks. Since OOB is not used by UBIFS, the initial
implementation of the driver has chosen to not support reading this
additional "spare" chunk of data.

Unfortunately, Marvell has chosen to store the BBT signature in the
OOB area. Therefore, if the driver doesn't read this spare area, Linux
has no way of finding the BBT. It thinks there is no BBT, and rewrites
one, which U-Boot does not recognize, causing compatibility problems
between the bootloader and the kernel in terms of NAND usage.

To fix this, this commit implements the support for reading a partial
last chunk. This support is currently only useful for the case of 8
bits ECC with 4 KB pages, but it will be useful in the future to
enable other configurations such as 12 bits and 16 bits ECC with 4 KB
pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
have a "last" chunk that doesn't have the same size as the other
chunks.

In order to implement reading of the last chunk, this commit:

 - Adds a number of new fields to the pxa3xx_nand_info to describe how
   many full chunks and how many chunks we have, the size of full
   chunks and partial chunks, both in terms of data area and spare
   area.

 - Fills in the step_chunk_size and step_spare_size variables to
   describe how much data and spare should be read/written for the
   current read/program step.

 - Reworks the state machine to accommodate doing the additional read
   or program step when a last partial chunk is used.

[ Linux commit c2cdace755b583bae540a9979bff1aa428181b8c ]

Cc: Thomas Petazzoni 
Signed-off-by: Chris Packham 
---

Changes in v2:
- None

 drivers/mtd/nand/pxa3xx_nand.c | 154 ++---
 1 file changed, 99 insertions(+), 55 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index de897ae41d1e..365dcaf69f3e 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -199,15 +199,44 @@ struct pxa3xx_nand_info {
int use_spare;  /* use spare ? */
int need_wait;
 
-   unsigned intdata_size;  /* data to be read from FIFO */
-   unsigned intchunk_size; /* split commands chunk size */
-   unsigned intoob_size;
+   /* Amount of real data per full chunk */
+   unsigned intchunk_size;
+
+   /* Amount of spare data per full chunk */
unsigned intspare_size;
+
+   /* Number of full chunks (i.e chunk_size + spare_size) */
+   unsigned intnfullchunks;
+
+   /*
+* Total number of chunks. If equal to nfullchunks, then there
+* are only full chunks. Otherwise, there is one last chunk of
+* size (last_chunk_size + last_spare_size)
+*/
+   unsigned intntotalchunks;
+
+   /* Amount of real data in the last chunk */
+   unsigned intlast_chunk_size;
+
+   /* Amount of spare data in the last chunk */
+   unsigned intlast_spare_size;
+
unsigned intecc_size;
unsigned intecc_err_cnt;
unsigned intmax_bitflips;
int retcode;
 
+   /*
+* Variables only valid during command
+* execution. step_chunk_size and step_spare_size is the
+* amount of real data and spare data in the current
+* chunk. cur_chunk is the current chunk being
+* read/programmed.
+*/
+   unsigned intstep_chunk_size;
+   unsigned intstep_spare_size;
+   unsigned intcur_chunk;
+
/* cached register value */
uint32_treg_ndcr;
uint32_tndtr0cs0;
@@ -432,25 +461,6 @@ static int pxa3xx_nand_init_timings(struct 

[U-Boot] [RFC PATCH v2 08/10] mtd: pxa3xx_nand: Fix initial controller configuration

[Chris Packham]

The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those that can only be set after device identification.

Therefore, the driver can't set them all at once and instead
needs to configure the first group before nand_scan_ident()
and the second group later.

Let's split pxa3xx_nand_config in two halves, and set the
parameters that depend on the device geometry once this is known.

[ Linux commit 66e8e47eae658dc884e65695a597fdda7a109448 ]

Cc: Ezequiel Garcia 
Signed-off-by: Chris Packham 
---

Changes in v2:
- New

 drivers/mtd/nand/pxa3xx_nand.c | 41 +
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 146ef096ea3f..432219c78831 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -59,7 +59,8 @@
 #define NDCR_ND_MODE   (0x3 << 21)
 #define NDCR_NAND_MODE (0x0)
 #define NDCR_CLR_PG_CNT(0x1 << 20)
-#define NDCR_STOP_ON_UNCOR (0x1 << 19)
+#define NFCV1_NDCR_ARB_CNTL(0x1 << 19)
+#define NFCV2_NDCR_STOP_ON_UNCOR   (0x1 << 19)
 #define NDCR_RD_ID_CNT_MASK(0x7 << 16)
 #define NDCR_RD_ID_CNT(x)  (((x) << 16) & NDCR_RD_ID_CNT_MASK)
 
@@ -1226,26 +1227,41 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, 
struct nand_chip *this)
return NAND_STATUS_READY;
 }
 
-static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
+static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
+{
+   struct pxa3xx_nand_platform_data *pdata = info->pdata;
+
+   /* Configure default flash values */
+   info->chunk_size = PAGE_CHUNK_SIZE;
+   info->reg_ndcr = 0x0; /* enable all interrupts */
+   info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
+   info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
+   info->reg_ndcr |= NDCR_SPARE_EN;
+
+   return 0;
+}
+
+static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
 {
struct pxa3xx_nand_host *host = info->host[info->cs];
-   struct mtd_info *mtd = nand_to_mtd(>chip);
+   struct mtd_info *mtd = nand_to_mtd(>host[info->cs]->chip);
struct nand_chip *chip = mtd_to_nand(mtd);
 
info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
-
-   return 0;
 }
 
 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 {
+   struct pxa3xx_nand_platform_data *pdata = info->pdata;
uint32_t ndcr = nand_readl(info, NDCR);
 
/* Set an initial chunk size */
info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
-   info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
+   info->reg_ndcr = ndcr &
+   ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
+   info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
return 0;
@@ -1371,8 +1387,9 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
goto KEEP_CONFIG;
 
-   /* Set a default chunk size */
-   info->chunk_size = PAGE_CHUNK_SIZE;
+   ret = pxa3xx_nand_config_ident(info);
+   if (ret)
+   return ret;
 
ret = pxa3xx_nand_sensing(host);
if (ret) {
@@ -1399,10 +1416,6 @@ KEEP_CONFIG:
}
}
 
-   ret = pxa3xx_nand_config_flash(info);
-   if (ret)
-   return ret;
-
 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
/*
 * We'll use a bad block table stored in-flash and don't
@@ -1467,6 +1480,10 @@ KEEP_CONFIG:
host->row_addr_cycles = 3;
else
host->row_addr_cycles = 2;
+
+   if (!pdata->keep_config)
+   pxa3xx_nand_config_tail(info);
+
return nand_scan_tail(mtd);
 }
 
-- 
2.10.1

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[U-Boot] [RFC PATCH v2 06/10] nand: pxa3xx: Increase READ_ID buffer and make the size static

[Chris Packham]

The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.

[ Linux commit b226eca2088004622434cbcc27c6401b64f22d7c]

Cc: Ezequiel García 
Signed-off-by: Chris Packham 
---

Changes in v2:
- New

 drivers/mtd/nand/pxa3xx_nand.c | 29 ++---
 1 file changed, 10 insertions(+), 19 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index c97d85782cb1..d1c6e010f3c0 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -110,6 +110,13 @@
 #define EXT_CMD_TYPE_LAST_RW   1 /* Last naked read/write */
 #define EXT_CMD_TYPE_MONO  0 /* Monolithic read/write */
 
+/*
+ * This should be large enough to read 'ONFI' and 'JEDEC'.
+ * Let's use 7 bytes, which is the maximum ID count supported
+ * by the controller (see NDCR_RD_ID_CNT_MASK).
+ */
+#define READ_ID_BYTES  7
+
 /* macros for registers read/write */
 #define nand_writel(info, off, val)\
writel((val), (info)->mmio_base + (off))
@@ -156,8 +163,6 @@ struct pxa3xx_nand_host {
/* calculated from pxa3xx_nand_flash data */
unsigned intcol_addr_cycles;
unsigned introw_addr_cycles;
-   size_t  read_id_bytes;
-
 };
 
 struct pxa3xx_nand_info {
@@ -856,7 +861,7 @@ static int prepare_set_command(struct pxa3xx_nand_info 
*info, int command,
break;
 
case NAND_CMD_READID:
-   info->buf_count = host->read_id_bytes;
+   info->buf_count = READ_ID_BYTES;
info->ndcb0 |= NDCB0_CMD_TYPE(3)
| NDCB0_ADDR_CYC(1)
| command;
@@ -1236,23 +1241,10 @@ static int pxa3xx_nand_config_flash(struct 
pxa3xx_nand_info *info)
 
 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 {
-   /*
-* We set 0 by hard coding here, for we don't support keep_config
-* when there is more than one chip attached to the controller
-*/
-   struct pxa3xx_nand_host *host = info->host[0];
uint32_t ndcr = nand_readl(info, NDCR);
 
-   if (ndcr & NDCR_PAGE_SZ) {
-   /* Controller's FIFO size */
-   info->chunk_size = 2048;
-   host->read_id_bytes = 4;
-   } else {
-   info->chunk_size = 512;
-   host->read_id_bytes = 2;
-   }
-
/* Set an initial chunk size */
+   info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
@@ -1282,7 +1274,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host 
*host)
/* configure default flash values */
info->reg_ndcr = 0x0; /* enable all interrupts */
info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
-   info->reg_ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
+   info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
 
/* use the common timing to make a try */
@@ -1499,7 +1491,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info 
*info)
info->host[cs] = host;
host->cs = cs;
host->info_data = info;
-   host->read_id_bytes = 4;
mtd->owner = THIS_MODULE;
 
nand_set_controller_data(chip, host);
-- 
2.10.1

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[U-Boot] [RFC PATCH v2 07/10] mtd: pxa3xx_nand: Increase the initial chunk size

[Chris Packham]

The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transfered data.

However, the initial chunk size is used in a non-splitted way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during device identification.
This includes NAND_CMD_PARAM which was recently changed to
transfer up to 2048 bytes (for the redundant parameter pages).

Thus, the initial chunk size should be 2048 as well.

On Armada 370/XP platforms (NFCv2) booted without the keep-config
devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
command:

  [..]
  pxa3xx-nand f10d.nand: This platform can't do DMA on this device
  pxa3xx-nand f10d.nand: Wait time out!!!
  nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
  nand: Micron MT29F8G08ABABAWP
  nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224

[ Linux commit c7f00c29aa846b00c70bc99ddb6b1cc7e17c47d4 ]

Cc: Ezequiel García 
Signed-off-by: Chris Packham 
---

Changes in v2:
- new patch

 drivers/mtd/nand/pxa3xx_nand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index d1c6e010f3c0..146ef096ea3f 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1372,7 +1372,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
goto KEEP_CONFIG;
 
/* Set a default chunk size */
-   info->chunk_size = 512;
+   info->chunk_size = PAGE_CHUNK_SIZE;
 
ret = pxa3xx_nand_sensing(host);
if (ret) {
-- 
2.10.1

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[U-Boot] [RFC PATCH v2 05/10] mtd: nand: pxa3xx-nand: fix random command timeouts

[Chris Packham]

When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase

[ Linux commit 21fc0ef9652f0c809dc0d3e0a67f1e1bf6ff8255 ]

Cc: Robert Jarzmik 
Signed-off-by: Chris Packham 
---

Changes in v2:
- Add reference to Linux commit sha1

 drivers/mtd/nand/pxa3xx_nand.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 4cd1297e1d59..c97d85782cb1 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -619,8 +619,14 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info 
*info)
is_ready = 1;
}
 
+   /*
+* Clear all status bit before issuing the next command, which
+* can and will alter the status bits and will deserve a new
+* interrupt on its own. This lets the controller exit the IRQ
+*/
+   nand_writel(info, NDSR, status);
+
if (status & NDSR_WRCMDREQ) {
-   nand_writel(info, NDSR, NDSR_WRCMDREQ);
status &= ~NDSR_WRCMDREQ;
info->state = STATE_CMD_HANDLE;
 
@@ -641,8 +647,6 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info 
*info)
nand_writel(info, NDCB0, info->ndcb3);
}
 
-   /* clear NDSR to let the controller exit the IRQ */
-   nand_writel(info, NDSR, status);
if (is_completed)
info->cmd_complete = 1;
if (is_ready)
-- 
2.10.1

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[U-Boot] [RFC PATCH v2 04/10] mtd: nand: pxa3xx_nand: fix early spurious interrupt

[Chris Packham]

When the nand is first probe, and upon the first command start, the
status bits should be cleared before the interrupts are unmasked.

[ Linux commit 0b14392db2e998157d924085d7913e537ec26121 ]

Cc: Robert Jarzmik 
Signed-off-by: Chris Packham 
---

Changes in v2:
- Add reference to Linux commit sha1

 drivers/mtd/nand/pxa3xx_nand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 17cbc8d3d930..4cd1297e1d59 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -477,8 +477,8 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
ndcr |= NDCR_ND_RUN;
 
/* clear status bits and run */
-   nand_writel(info, NDCR, 0);
nand_writel(info, NDSR, NDSR_MASK);
+   nand_writel(info, NDCR, 0);
nand_writel(info, NDCR, ndcr);
 }
 
-- 
2.10.1

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[U-Boot] [RFC PATCH v2 02/10] mtd: nand: pxa3xx_nand: use nand_to_mtd()

[Chris Packham]

Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the
one that is already part of struct nand_chip. This brings us in line
with current U-boot and Linux conventions.

Signed-off-by: Chris Packham 
---

Changes in v2:
- Drop irrelevant Cc from commit message

 drivers/mtd/nand/pxa3xx_nand.c | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 8d7f7a845a9d..a5b9332456ec 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -147,7 +147,6 @@ enum pxa3xx_nand_variant {
 
 struct pxa3xx_nand_host {
struct nand_chipchip;
-   struct mtd_info *mtd;
void*info_data;
 
/* page size of attached chip */
@@ -380,16 +379,17 @@ static int pxa3xx_nand_init_timings(struct 
pxa3xx_nand_host *host)
struct nand_chip *chip = >chip;
struct pxa3xx_nand_info *info = host->info_data;
const struct pxa3xx_nand_flash *f = NULL;
+   struct mtd_info *mtd = nand_to_mtd(>chip);
int mode, id, ntypes, i;
 
mode = onfi_get_async_timing_mode(chip);
if (mode == ONFI_TIMING_MODE_UNKNOWN) {
ntypes = ARRAY_SIZE(builtin_flash_types);
 
-   chip->cmdfunc(host->mtd, NAND_CMD_READID, 0x00, -1);
+   chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
 
-   id = chip->read_byte(host->mtd);
-   id |= chip->read_byte(host->mtd) << 0x8;
+   id = chip->read_byte(mtd);
+   id |= chip->read_byte(mtd) << 0x8;
 
for (i = 0; i < ntypes; i++) {
f = _flash_types[i];
@@ -682,7 +682,7 @@ static void set_command_address(struct pxa3xx_nand_info 
*info,
 static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
 {
struct pxa3xx_nand_host *host = info->host[info->cs];
-   struct mtd_info *mtd = host->mtd;
+   struct mtd_info *mtd = nand_to_mtd(>chip);
 
/* reset data and oob column point to handle data */
info->buf_start = 0;
@@ -733,7 +733,7 @@ static int prepare_set_command(struct pxa3xx_nand_info 
*info, int command,
struct mtd_info *mtd;
 
host = info->host[info->cs];
-   mtd = host->mtd;
+   mtd = nand_to_mtd(>chip);
addr_cycle = 0;
exec_cmd = 1;
 
@@ -1220,7 +1220,7 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, 
struct nand_chip *this)
 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
 {
struct pxa3xx_nand_host *host = info->host[info->cs];
-   struct mtd_info *mtd = host->mtd;
+   struct mtd_info *mtd = nand_to_mtd(>chip);
struct nand_chip *chip = mtd_to_nand(mtd);
 
info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
@@ -1272,7 +1272,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host 
*host)
const struct nand_sdr_timings *timings;
int ret;
 
-   mtd = info->host[info->cs]->mtd;
+   mtd = nand_to_mtd(>host[info->cs]->chip);
chip = mtd_to_nand(mtd);
 
/* configure default flash values */
@@ -1493,7 +1493,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info 
*info)
mtd = nand_to_mtd(chip);
host = (struct pxa3xx_nand_host *)chip;
info->host[cs] = host;
-   host->mtd = mtd;
host->cs = cs;
host->info_data = info;
host->read_id_bytes = 4;
@@ -1568,7 +1567,7 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info 
*info)
 
probe_success = 0;
for (cs = 0; cs < pdata->num_cs; cs++) {
-   struct mtd_info *mtd = info->host[cs]->mtd;
+   struct mtd_info *mtd = nand_to_mtd(>host[cs]->chip);
 
/*
 * The mtd name matches the one used in 'mtdparts' kernel
-- 
2.10.1

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[U-Boot] [RFC PATCH v2 03/10] mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()

[Chris Packham]

Since the pxa3xx_nand driver was added there has been a discrepancy in
pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min.
This brings us into line with the current Linux code.

Signed-off-by: Chris Packham 
---

Changes in v2:
- None

 drivers/mtd/nand/pxa3xx_nand.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index a5b9332456ec..17cbc8d3d930 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -345,9 +345,9 @@ static void pxa3xx_nand_set_sdr_timing(struct 
pxa3xx_nand_host *host,
u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
-   u32 tWP_min = DIV_ROUND_UP(t->tWC_min - tWH_min, 1000);
+   u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
-   u32 tRP_min = DIV_ROUND_UP(t->tRC_min - tREH_min, 1000);
+   u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
u32 tR = chip->chip_delay * 1000;
u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
-- 
2.10.1

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[U-Boot] [RFC PATCH v2 01/10] mtd: nand: pxa3xx_nand: Increase initial buffer size

[Chris Packham]

The initial buffer is used for the initial commands used to detect
a flash device (STATUS, READID and PARAM).

ONFI param page is 256 bytes, and there are three redundant copies
to be read. JEDEC param page is 512 bytes, and there are also three
redundant copies to be read. Hence this buffer should be at least
512 x 3. This commits rounds the buffer size to 2048.

[ Linux commit c16340973fcb6461474a9f811f7f3ff2f946b24c ]

Cc: Ezequiel Garcia 
Signed-off-by: Chris Packham 
---

Changes in v2:
- Add reference to Linux commit sha1.
- Remove spurious change

 drivers/mtd/nand/pxa3xx_nand.c | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index dfe8966b56b6..8d7f7a845a9d 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -26,10 +26,13 @@
 
 /*
  * Define a buffer size for the initial command that detects the flash device:
- * STATUS, READID and PARAM. The largest of these is the PARAM command,
- * needing 256 bytes.
+ * STATUS, READID and PARAM.
+ * ONFI param page is 256 bytes, and there are three redundant copies
+ * to be read. JEDEC param page is 512 bytes, and there are also three
+ * redundant copies to be read.
+ * Hence this buffer should be at least 512 x 3. Let's pick 2048.
  */
-#define INIT_BUFFER_SIZE   256
+#define INIT_BUFFER_SIZE   2048
 
 /* registers and bit definitions */
 #define NDCR   (0x00) /* Control register */
@@ -838,14 +841,14 @@ static int prepare_set_command(struct pxa3xx_nand_info 
*info, int command,
break;
 
case NAND_CMD_PARAM:
-   info->buf_count = 256;
+   info->buf_count = INIT_BUFFER_SIZE;
info->ndcb0 |= NDCB0_CMD_TYPE(0)
| NDCB0_ADDR_CYC(1)
| NDCB0_LEN_OVRD
| command;
info->ndcb1 = (column & 0xFF);
-   info->ndcb3 = 256;
-   info->data_size = 256;
+   info->ndcb3 = INIT_BUFFER_SIZE;
+   info->data_size = INIT_BUFFER_SIZE;
break;
 
case NAND_CMD_READID:
-- 
2.10.1

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[U-Boot] [RFC PATCH v2 00/10] pxa3xx_nand updates

[Chris Packham]

I'm looking into the NAND support for the db-88f6820-amc board.
There are a number of changes in the pxa3xx_nand driver in Linux that
are relevant (not specifically to this boards but to Armada boards in
general). Some of these changes are cleanups and some are actual bug
fixes.

I'd really appreciate some testing on this. This gives me enough so I
can mount and read files out of a ubifs volume created by Linux on the
DB-88F6820-AMC board but I don't have access to any other Armada boards
to test with.

Where applicable I'll Cc the author of the equivalent Linux patch. I've
had to tweak a few of them to make them fit u-boot (e.g. to handle
platform data) but they should still look pretty close to their Linux
counterparts.

Note this series is dependent on
http://lists.denx.de/pipermail/u-boot/2016-October/270967.html

Changes in v2:
- Add references to Linux commit sha1.
- Remove spurious change in 1/10
- Drop irrelevant Cc from 2/10
- 6/10 to 9/10 are new

Chris Packham (10):
  mtd: nand: pxa3xx_nand: Increase initial buffer size
  mtd: nand: pxa3xx_nand: use nand_to_mtd()
  mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()
  mtd: nand: pxa3xx_nand: fix early spurious interrupt
  mtd: nand: pxa3xx-nand: fix random command timeouts
  nand: pxa3xx: Increase READ_ID buffer and make the size static
  mtd: pxa3xx_nand: Increase the initial chunk size
  mtd: pxa3xx_nand: Fix initial controller configuration
  mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan
  mtd: nand: pxa3xx_nand: add support for partial chunks

 drivers/mtd/nand/pxa3xx_nand.c | 294 -
 1 file changed, 175 insertions(+), 119 deletions(-)

-- 
2.10.1

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[U-Boot] [PATCH] arm: mvebu: move SYS_MVEBU_PLL_CLOCK to Kconfig

[Chris Packham]

The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375,
38x and 39x.

[ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ]

Signed-off-by: Chris Packham 
---
See 
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=ae142bd99765

I've set the value for ARMADA_3700 and ARMADA_8K to 2GHz. I'm not sure
if this is correct but it is the same value that these SoCs would have
had when the value was defined in soc.h.

 arch/arm/mach-mvebu/Kconfig| 6 ++
 arch/arm/mach-mvebu/include/mach/soc.h | 3 ---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 6e8026bde253..7733936be540 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -36,6 +36,12 @@ config ARMADA_8K
bool
select ARM64
 
+# Armada PLL frequency (used for NAND clock generation)
+config SYS_MVEBU_PLL_CLOCK
+   int
+   default "20" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
+   default "10" if ARMADA_38X || ARMADA_375
+
 # Armada XP/38x SoC types...
 config MV78230
bool
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h 
b/arch/arm/mach-mvebu/include/mach/soc.h
index 731fe65ae4b4..0f69f3341be0 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -31,9 +31,6 @@
 #define CONFIG_SYS_TCLK25000   /* 250MHz */
 #endif
 
-/* Armada XP PLL frequency (used for NAND clock generation) */
-#define CONFIG_SYS_MVEBU_PLL_CLOCK 20
-
 /* SOC specific definations */
 #define INTREG_BASE0xd000
 #define INTREG_BASE_ADDR_REG   (INTREG_BASE + 0x20080)
-- 
2.10.1

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Re: [U-Boot] [RFC PATCH] lib/timer: initialize timebase_l/timebase_h

[André Przywara]

On 25/10/16 08:52, Alexander Graf wrote:

Hi Alex,

thanks for looking at this!

> 
> On 25/10/2016 02:51, Andre Przywara wrote:
>> On systems using the generic timer routines defined in lib/time.c we
>> use timebase_l and timebase_h fields from the gd to detect wraparounds
>> in our tick counter. The tick calculcation algorithm silently assumes
>> that a long is only 32 bits, which leads to wrong results when timebase_h
>> is not 0 on 64-bit systems.
>> As one possible fix lets initialize timebase_h (and timebase_l) to 0, so
>> on 64-bit systems timebase_h will never(TM) be bigger than 0 and thus
>> cannot spoil timebase_l by being ORed into it.
>>
>> This fixes occasional timeout issues on the Pine64 (and possibly other
>> ARM64 systems).

Well, not really (this fix isn't sufficient), but read on ...

>> Signed-off-by: Andre Przywara 
>> ---
>> Hi,
>>
>> I am bit puzzled what the proper fix is, this one is the easiest I could
>> come up with. Not sure if the gd should be zeroed normally (and it's just
>> broken on sunxi/arm64 because of some linker issues) or whether we really
>> forgot to initialize those fields and just got away with it.
> 
> The gd clearing happens via crt0_64.S -> board_init_f_init_reserve().
> There we should have fully cleared all memory associated with global data.

Ah,thanks for pointing to that. I was a bit clueless where to start
looking for it - "git grep gd" is obviously not a good idea ;-)

> I can't see anything obviously wrong in that code. Could you try to dump
> gd if the timer offsets are != 0 on init? Maybe we can conclude
> something from the data in it.

So I agree that this code looks sane and indeed in all my dumps it looks
like the initialization works fine.
I did some more debugging and learned that the increased timebase_h
comes from detected overflows: in fact some readings are really lower
than previous ones:
...
MMC:   SUNXI SD/MMC: 0
get_ticks() overflow: now: 118046720, tbl: 118063103, tbh: 0
get_ticks() overflow: now: 118439936, tbl: 118456318, tbh: 1
get_ticks() overflow: now: 118571008, tbl: 118587391, tbh: 2
get_ticks() overflow: now: 118734848, tbl: 118751230, tbh: 3
get_ticks() overflow: now: 119422976, tbl: 119439358, tbh: 4
get_ticks() overflow: now: 119783424, tbl: 119799807, tbh: 5
get_ticks() overflow: now: 120045568, tbl: 120061950, tbh: 6
get_ticks() overflow: now: 120406016, tbl: 120422398, tbh: 7
*** Warning - bad CRC, using default environment
..
Not sure how this actually happens - I am not aware of any such severe
hardware errata in the A53 r0p4 or the timer, also I think that would
have bitten us elsewhere already.
As ATF keeps the secondaries in WFI, U-Boot only runs on CPU0 (confirmed
by MPIDR reads).
Also U-Boot reads the physical counter, so a bogus CNTVOFF can also not
be the culprit.

So I can fix this annoying issue by using one of the other proposed
fixes (handling timebase_h only if BITS_PER_LONG < 64 or defining
get_ticks in armv8/generic_timer.c), but it would still be interesting
to find the real root cause.

Thanks,
Andre.

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Re: [U-Boot] [PATCH 4/6] x86: efi: Add EFI loader support for x86

[Alexander Graf]

On 10/08/2016 14:56, Simon Glass wrote:
> Hi Alex,
> 
> On 10 August 2016 at 05:49, Alexander Graf  wrote:
>> On 08/07/2016 01:23 AM, Simon Glass wrote:
>>>
>>> Add the required pieces to support the EFI loader on x86.
>>>
>>> Since U-Boot only builds for 32-bit on x86, only a 32-bit EFI application
>>> is supported. If a 64-bit kernel must be booted, U-Boot supports this
>>> directly using FIT (see doc/uImage.FIT/kernel.its). U-Boot can act as a
>>> payload for both 32-bit and 64-bit EFI.
>>>
>>> Signed-off-by: Simon Glass 
>>> ---
>>>
>>>   arch/x86/cpu/u-boot.lds   | 36 +++-
>>>   arch/x86/lib/Makefile |  1 +
>>>   arch/x86/lib/sections.c   | 12 
>>>   include/efi.h |  3 ++-
>>>   lib/efi_loader/efi_boottime.c |  9 +
>>>   lib/efi_loader/efi_runtime.c  |  4 
>>>   6 files changed, 63 insertions(+), 2 deletions(-)
>>>   create mode 100644 arch/x86/lib/sections.c
>>>
>>> diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
>>> index 36f59ea..cca536b 100644
>>> --- a/arch/x86/cpu/u-boot.lds
>>> +++ b/arch/x86/cpu/u-boot.lds
>>> @@ -28,7 +28,10 @@ SECTIONS
>>> }
>>> . = ALIGN(4);
>>> -   .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
>>> +   .rodata : {
>>> +   *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
>>> +   KEEP(*(.rodata.efi.init));
>>> +   }
>>> . = ALIGN(4);
>>> .data : { *(.data*) }
>>> @@ -40,6 +43,37 @@ SECTIONS
>>> .got : { *(.got*) }
>>> . = ALIGN(4);
>>> +
>>> +   .__efi_runtime_start : {
>>> +   *(.__efi_runtime_start)
>>> +   }
>>> +
>>> +   .efi_runtime : {
>>> +   *(efi_runtime_text)
>>> +   *(efi_runtime_data)
>>> +   }
>>> +
>>> +   .__efi_runtime_stop : {
>>> +   *(.__efi_runtime_stop)
>>> +   }
>>> +
>>> +   .efi_runtime_rel_start :
>>> +   {
>>> +   *(.__efi_runtime_rel_start)
>>> +   }
>>> +
>>> +   .efi_runtime_rel : {
>>> +   *(.relefi_runtime_text)
>>> +   *(.relefi_runtime_data)
>>> +   }
>>> +
>>> +   .efi_runtime_rel_stop :
>>> +   {
>>> +   *(.__efi_runtime_rel_stop)
>>> +   }
>>> +
>>> +   . = ALIGN(4);
>>> +
>>> __data_end = .;
>>> __init_end = .;
>>>   diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
>>> index e17f0bb..e46e7f1 100644
>>> --- a/arch/x86/lib/Makefile
>>> +++ b/arch/x86/lib/Makefile
>>> @@ -28,6 +28,7 @@ obj-y += pirq_routing.o
>>>   obj-y += relocate.o
>>>   obj-y += physmem.o
>>>   obj-$(CONFIG_X86_RAMTEST) += ramtest.o
>>> +obj-y  += sections.o
>>>   obj-y += sfi.o
>>>   obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
>>>   obj-y += string.o
>>> diff --git a/arch/x86/lib/sections.c b/arch/x86/lib/sections.c
>>> new file mode 100644
>>> index 000..6455e0f
>>> --- /dev/null
>>> +++ b/arch/x86/lib/sections.c
>>> @@ -0,0 +1,12 @@
>>> +/*
>>> + * Copyright 2013 Albert ARIBAUD 
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +char __efi_runtime_start[0]
>>> __attribute__((section(".__efi_runtime_start")));
>>> +char __efi_runtime_stop[0]
>>> __attribute__((section(".__efi_runtime_stop")));
>>> +char __efi_runtime_rel_start[0]
>>> +   __attribute__((section(".__efi_runtime_rel_start")));
>>> +char __efi_runtime_rel_stop[0]
>>> +   __attribute__((section(".__efi_runtime_rel_stop")));
>>> diff --git a/include/efi.h b/include/efi.h
>>> index 1dbc3b7..47b351f 100644
>>> --- a/include/efi.h
>>> +++ b/include/efi.h
>>> @@ -15,6 +15,7 @@
>>>   #ifndef _EFI_H
>>>   #define _EFI_H
>>>   +#include 
>>>   #include 
>>>   #include 
>>>   @@ -22,7 +23,7 @@
>>>   /* EFI uses the Microsoft ABI which is not the default for GCC */
>>>   #define EFIAPI __attribute__((ms_abi))
>>>   #else
>>> -#define EFIAPI
>>> +#define EFIAPI asmlinkage
>>
>>
>> Ah, this should trigger what I mentioned in my previous email. Since
>> linkage.h is now included in efi.h, we no longer have to include the header
>> in bootefi.c explicitly. How about you just move this part of the patch
>> between patches 1/6 and 2/6?
> 
> OK will take a look.
> 
>>
>>
>>>   #endif
>>> struct efi_device_path;
>>> diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
>>> index 798b566..e027bd3 100644
>>> --- a/lib/efi_loader/efi_boottime.c
>>> +++ b/lib/efi_loader/efi_boottime.c
>>> @@ -39,6 +39,7 @@ static bool efi_is_direct_boot = true;
>>>*/
>>>   static struct efi_configuration_table EFI_RUNTIME_DATA
>>> efi_conf_table[1];
>>>   +#ifdef CONFIG_ARM
>>>   /*
>>>* The "gd" pointer lives in a register on ARM and AArch64 that we
>>> declare
>>>* fixed when compiling U-Boot. However, the payload does not know about
>>> that
>>> @@ -46,16 +47,20 @@ static struct efi_configuration_table EFI_RUNTIME_DATA

Re: [U-Boot] [PATCH v4 1/2] armv8/ls1043a: fixup GIC offset according to SVR and SCFG_GIC400_ALIGN[GIC_ADDR_BIT]

[york sun]

On 10/24/2016 12:51 AM, Wenbin song wrote:
> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
> and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
> which offset will be used.
>
> The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment.
>
> If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is 
> used.
> 64K alignment is the default setting.
>
> Overriding the weekly smp_kick_all_cpus, the new impletment is able to detect
> GIC offset.

I think you meant "weak" here. :)

>
> The default GIC offset in kernel device tree is using 64K alignment, it
> need to be fixed if 4K alignment is detected.

The "default" offset in device tree is also created by us, isn't it? I 
am not against you fixing it. Don't you want to check the alignment 
first? If the device tree has 4K alignment but you run on rev 1.1, do 
you want to use 64K alignment?

>
> Signed-off-by: Wenbin Song 
> Signed-off-by: Mingkai Hu 
> ---
> Changes in v4:
>   Squash [patch 2/3 v3] with this patch.
>   Add comments on fix_gic_offest.
>   Add the descriptions of rev1.0 GIC offset.
>   Use macros to define the offset and size of GIC components.
> Changes in v3:
>   Add descriptions about smp_kick_all_cpus on commit message.
>   Rename the macros on commit message to match with them used in the 
> change.
>   Replace CONFIG_LS1043A with HAS_FEATURE_GIC4K_ALIGN.
> Changes in v2:
>   None
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  4 ++
>  arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 49 +++
>  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 55 
> ++
>  arch/arm/include/asm/arch-fsl-layerscape/config.h  | 20 +++-
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
>  5 files changed, 128 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 94ec8d5..c66c497 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -12,6 +12,7 @@ config ARCH_LS1043A
>   select SYS_FSL_DDR_VER_50
>   select SYS_FSL_ERRATUM_A010315
>   select SYS_FSL_ERRATUM_A010539
> + select HAS_FEATURE_GIC4K_ALIGN
>
>  config ARCH_LS1046A
>   bool
> @@ -135,4 +136,7 @@ config SYS_FSL_DDR4
>   help
> Enable Freescale DDR4 controller.
>
> +config HAS_FEATURE_GIC4K_ALIGN
> +   bool
> +
>  endmenu
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> index 1a8321b..ebc7863 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> @@ -126,6 +126,52 @@ void fsl_fdt_disable_usb(void *blob)
>   }
>  }
>
> +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> +/* Fixup gic node align with 4K */
> +static void fdt_fixup_gic(void *blob)
> +{
> + int offset, err;
> + u64 reg[8];
> + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> + unsigned int val;
> + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
> +
> + val = gur_in32(>svr) & 0xff;
> +
> + if (val == REV1_1) {

This is problematic. How about for future SoCs, or other than LS1043A? 
Can we just check GIC_ADDR_BIT?

> + val = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
> + if (!val)
> + return;
> + }
> +
> + offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
> + if (offset < 0) {
> + printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
> +"interrupt-controller@140", fdt_strerror(offset));
> + return;
> + }
> +
> + reg[0] = cpu_to_fdt64(GICD_BASE_4K);
> + reg[1] = cpu_to_fdt64(GICD_SIZE_4K);
> + reg[2] = cpu_to_fdt64(GICC_BASE_4K);
> + reg[3] = cpu_to_fdt64(GICC_SIZE_4K);
> + reg[4] = cpu_to_fdt64(GICH_BASE_4K);
> + reg[5] = cpu_to_fdt64(GICH_SIZE_4K);
> + reg[6] = cpu_to_fdt64(GICV_BASE_4K);
> + reg[7] = cpu_to_fdt64(GICV_SIZE_4K);
> +
> + err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
> + if (err < 0) {
> + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
> +"reg", "interrupt-controller@140",
> +fdt_strerror(err));
> + return;
> + }
> +
> + return;
> +}
> +#endif
> +
>  void ft_cpu_setup(void *blob, bd_t *bd)
>  {
>  #ifdef CONFIG_FSL_LSCH2
> @@ -170,4 +216,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
>  #endif
>   fsl_fdt_disable_usb(blob);
>
> +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> + fdt_fixup_gic(blob);
> +#endif
>  }
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
> b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> index 5d0b7a4..e2b8698 100644
> --- 

Re: [U-Boot] Loading kernel from SD card slow on MinnowBoard Turbot since v2016.09

[Raschen Josef]

Von: Jaehoon Chung [jh80.ch...@samsung.com]
Gesendet: Freitag, 21. Oktober 2016 14:11

>>>From my tests it should be somewhere between these two commits:
>> 1c62d999528da1f052cb4b07cbb540b148c52537OK
>> ceec08f50b66df0c988033842ec057a32658cfe0NOK

> Thanks for checking..Could you share which controller you use?
> I needs to check the driver codes for this...but i didn't know which driver 
> you use..
> It should be helpful to me..

Unfortunately, I have no access to the board for the next two weeks. I can only 
tell you, that the Board uses a an Intel Atom E3826 (Bay Trail) SoC. I think 
the data sheet does not say which type of MMC controller it uses. 

http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html
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Re: [U-Boot] [PATCH v2] powerpc: mpc512x: Add support for get_svr() for mpc512x devices

[york sun]

On 10/13/2016 11:36 PM, Sriram Dash wrote:
> Defines get_svr() for mpc512x devices
>
> Signed-off-by: Sriram Dash 
> Reviewed-by: Bin Meng 
> ---
> Changes in v2:
>   - cosmetic changes
>
>  arch/powerpc/cpu/mpc512x/start.S | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/powerpc/cpu/mpc512x/start.S 
> b/arch/powerpc/cpu/mpc512x/start.S
> index 471d401..dd3066e 100644
> --- a/arch/powerpc/cpu/mpc512x/start.S
> +++ b/arch/powerpc/cpu/mpc512x/start.S
> @@ -443,6 +443,11 @@ get_pvr:
>   mfspr   r3, PVR
>   blr
>
> + .globl get_svr
> +get_svr:
> + mfspr   r3, SVR
> + blr
> +
>  /*---*/
>
>  /*
>

Reviewed-by: York Sun 
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Re: [U-Boot] [PATCH v2] tpm: tpm_tis_lpc: Add support for AT97SC3204

[Simon Glass]

On 17 October 2016 at 16:17, Simon Glass  wrote:
> On 17 October 2016 at 08:24, George McCollister
>  wrote:
>> The Atmel AT97SC3204 is also TIS compliant.
>> Modify the tpm_tis_lpc driver to check for the vid/did used by the
>> Atmel AT97SC3204 and report an appropriate description.
>>
>> Signed-off-by: George McCollister 
>> ---
>>
>> Changes in v2:
>> - Reorganized didvid check to make it more consistent with the original
>>   code
>> - Return -ENODEV instead of -ENOENT when didvid doesn't match the
>>   expected value for the device
>>
>>  drivers/tpm/tpm_tis_lpc.c | 37 -
>>  1 file changed, 28 insertions(+), 9 deletions(-)
>
> Reviewed-by: Simon Glass 

Applied to u-boot-dm/next, thanks!
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Re: [U-Boot] [PATCH] sandboxfs: Fix resource leak

[Simon Glass]

On 17 October 2016 at 19:54, Simon Glass  wrote:
> On 17 October 2016 at 19:09, Tom Rini  wrote:
>> Now that we free resources in sandbox_fs_ls Coverity is letting us know
>> that in some cases we might leak.  So in case of error we should still
>> let os_dirent_free free anything that was allocated.
>>
>> Fixes: 86167089b71c ("sandbox/fs: Free memory allocated by os_dirent_ls")
>> Reported-by: Coverity (CID: 153450)
>> Cc: Stefan Brüns 
>> Cc: Simon Glass 
>> Signed-off-by: Tom Rini 
>> ---
>>  fs/sandbox/sandboxfs.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> Reviewed-by: Simon Glass 

Applied to u-boot-dm/next, thanks
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Re: [U-Boot] [PATCH] cmd/tpm_test: Fix misleading code indentation

[Simon Glass]

On 17 October 2016 at 16:17, Simon Glass  wrote:
> On 16 October 2016 at 09:13, Stefan Brüns  
> wrote:
>> GCC 6.2 reasonably complains about the current code:
>>
>> ../cmd/tpm_test.c: In function ‘do_tpmtest’:
>> ../cmd/tpm_test.c:540:3: warning: this ‘for’ clause does not guard... 
>> [-Wmisleading-indentation]
>>for (i = 0; i < argc; i++)
>>^~~
>> ../cmd/tpm_test.c:542:4: note: ...this statement, but the latter is 
>> misleadingly indented as if it is guarded by the ‘for’
>> printf("\n--\n");
>> ^~
>>
>> Signed-off-by: Stefan Brüns 
>> ---
>>  cmd/tpm_test.c | 11 +--
>>  1 file changed, 5 insertions(+), 6 deletions(-)
>
> Reviewed-by: Simon Glass 

Updated to drop the C99 variable decl.

Applied to u-boot-dm/next, thanks!
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Re: [U-Boot] [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to config.h

[york sun]

On 10/24/2016 11:55 PM, Prabhakar Kushwaha wrote:
>
>> -Original Message-
>> From: york sun
>> Sent: Monday, October 24, 2016 9:41 PM
>> To: Prabhakar Kushwaha ; u-
>> b...@lists.denx.de
>> Cc: o...@buserror.net
>> Subject: Re: [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to
>> config.h
>>
>> On 10/23/2016 07:04 AM, Prabhakar Kushwaha wrote:
>>> Hi York,
>>>
 -Original Message-
 From: york sun
 Sent: Friday, October 21, 2016 7:55 PM
 To: Prabhakar Kushwaha ; u-
 b...@lists.denx.de
 Cc: o...@buserror.net
 Subject: Re: [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to
 config.h

 On 10/20/2016 11:37 PM, Prabhakar Kushwaha wrote:
> Migration of IFC_BANK_COUNT from Kconfig to config.h avoids adding
> SoC name in Kconfig as Dependencies. It will help in having
> all SoC related defines in config.h - easy to maintain.
>

 Prabhakar,

 Why do you want to go back to config.h? I think we are going with
 Kconfig. Having everything in one config file conflicts with Kconfig.
 The former has centralized config per SoC, the latter has centralized
 config per feature.

>>>
>>> There are 2 reason for this
>>>
>>> 1) in File arch/arm/cpu/armv8/fsl-layerscape/Kconfig, "depends" row will 
>>> keep
>> on increasing with SoC.
>>> And if I add new field CONFIG_SYS_FSL_IFC_CLK_DIV, similar entry will be
>> done and it will also keep on increasing with SoC.
>>> I want to avoid it.
>>>
>>> config SYS_FSL_IFC_BANK_COUNT
>>> int "Maximum banks of Integrated flash controller"
>>> depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
>>
>> The "depends" line can be rewritten with HAS_* feature macro.
>>
>>> default 4 if ARCH_LS1043A
>>> default 4 if ARCH_LS1046A
>>> default 8 if ARCH_LS2080A
>>
>> You can simplify the "default 4" for all and only use different number
>> for others.
>>
>
> ok
>
>
>>>
>>> 2) There is no file similar to  " 
>>> arch/arm/cpu/armv8/fsl-layerscape/Kconfig" for
>> powerpc platform. So how to add new " CONFIG SYS_FSL_IFC_CLK_DIV" with
>> different values per SoC.
>>>This problem will come for defining other clocks for " armv8/fsl-lsch3:
>> consolidate the clock system initialization"
>>>
>>
>> We will convert powerpc as well.
>
> This means, IFC and clock related patches needs to wait till powerpc is 
> converted as well.
>

Maybe. If you have bandwidth, you can take it. Or you can wait for me to 
get it done. My plate is full, so it will take a while before I start.

York

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[U-Boot] [PATCH] omap3_beagle: use config_distro_bootcmd

[Guillaume GARDET]

Add support for distro_bootcmd on MMC and fall back to prior 
behavior if distro_bootcmd fails.

Tested on Beagleboad xM to boot GRUB2 (and then Linux kernel) in EFI mode 
from MMC.

Signed-off-by: Guillaume GARDET 
Cc: Tom Rini 

---
 include/configs/omap3_beagle.h | 76 --
 1 file changed, 43 insertions(+), 33 deletions(-)

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 8a69a5f..9850aa6 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -104,11 +104,52 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE 1   /* Max number of NAND */
/* devices */
 
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 0)
+
+#define CONFIG_BOOTCOMMAND \
+   "run findfdt; " \
+   "run distro_bootcmd; " \
+   "mmc dev ${mmcdev}; if mmc rescan; then " \
+   "if run userbutton; then " \
+   "setenv bootenv uEnv.txt;" \
+   "else " \
+   "setenv bootenv user.txt;" \
+   "fi;" \
+   "echo SD/MMC found on device ${mmcdev};" \
+   "if run loadbootenv; then " \
+   "echo Loaded environment from ${bootenv};" \
+   "run importbootenv;" \
+   "fi;" \
+   "if test -n $uenvcmd; then " \
+   "echo Running uenvcmd ...;" \
+   "run uenvcmd;" \
+   "fi;" \
+   "if run loadbootscript; then " \
+   "run bootscript; " \
+   "else " \
+   "if run loadimage; then " \
+   "run mmcboot;" \
+   "fi;" \
+   "fi; " \
+   "fi;" \
+   "run nandboot;" \
+   "setenv bootfile zImage;" \
+   "if run loadimage; then " \
+   "run loadfdt;" \
+   "run mmcbootz; " \
+   "fi; " \
+
+#include 
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x8020\0" \
+   "kernel_addr_r=0x8020\0" \
"rdaddr=0x8100\0" \
+   "initrd_addr_r=0x8100\0" \
"fdt_high=0x\0" \
"fdtaddr=0x80f8\0" \
+   "fdt_addr_r=0x80f8\0" \
"usbtty=cdc_acm\0" \
"bootfile=uImage\0" \
"ramdisk=ramdisk.gz\0" \
@@ -203,39 +244,8 @@
"userbutton=if gpio input 173; then run userbutton_xm; " \
"else run userbutton_nonxm; fi;\0" \
"userbutton_xm=gpio input 4;\0" \
-   "userbutton_nonxm=gpio input 7;\0"
-/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
-#define CONFIG_BOOTCOMMAND \
-   "run findfdt; " \
-   "mmc dev ${mmcdev}; if mmc rescan; then " \
-   "if run userbutton; then " \
-   "setenv bootenv uEnv.txt;" \
-   "else " \
-   "setenv bootenv user.txt;" \
-   "fi;" \
-   "echo SD/MMC found on device ${mmcdev};" \
-   "if run loadbootenv; then " \
-   "echo Loaded environment from ${bootenv};" \
-   "run importbootenv;" \
-   "fi;" \
-   "if test -n $uenvcmd; then " \
-   "echo Running uenvcmd ...;" \
-   "run uenvcmd;" \
-   "fi;" \
-   "if run loadbootscript; then " \
-   "run bootscript; " \
-   "else " \
-   "if run loadimage; then " \
-   "run mmcboot;" \
-   "fi;" \
-   "fi; " \
-   "fi;" \
-   "run nandboot;" \
-   "setenv bootfile zImage;" \
-   "if run loadimage; then " \
-   "run loadfdt;" \
-   "run mmcbootz; " \
-   "fi; " \
+   "userbutton_nonxm=gpio input 7;\0" \
+   BOOTENV
 
 /*
  * OMAP3 has 12 GP timers, they can be driven by the system clock
-- 
1.8.4.5

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Re: [U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[Priyanka Jain]

> -Original Message-
> From: york sun
> Sent: Tuesday, October 25, 2016 12:37 AM
> To: Priyanka Jain ; u-boot@lists.denx.de;
> Prabhakar Kushwaha 
> Cc: Raghav Dogra 
> Subject: Re: [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release
> secondary cores
> 
> On 10/24/2016 08:49 AM, york@nxp.com wrote:
> > On 10/24/2016 01:33 AM, Priyanka Jain wrote:
> >> NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
> >> But other new SoCs like LS2088A, LS1088A release secondary cores one
> >> by one to avoid power spike.
> >>
> >> Update code to release secondary cores based on SoC SVR Add code to
> >> release cores one by one for non LS2080A SoCs
> >>
> >> Signed-off-by: Priyanka Jain 
> >> Signed-off-by: Raghav Dogra 
> >> Signed-off-by: Prabhakar Kushwaha 
> >> ---
> >>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c |2 +-
> >>  arch/arm/cpu/armv8/fsl-layerscape/cpu.h |1 +
> >>  arch/arm/cpu/armv8/fsl-layerscape/mp.c  |   59
> >> --
> >>  3 files changed, 57 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> index ce04e48..15d157c 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> @@ -190,7 +190,7 @@ void enable_caches(void)  }  #endif
> >>
> >> -static inline u32 initiator_type(u32 cluster, int init_id)
> >> +inline u32 initiator_type(u32 cluster, int init_id)
> >>  {
> >>  struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> >>  u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> >> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> >> index 8072f3c..a05f8aa 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> >> @@ -5,4 +5,5 @@
> >>   */
> >>
> >>  int fsl_qoriq_core_to_cluster(unsigned int core);
> >> +u32 initiator_type(u32 cluster, int init_id);
> >>  u32 cpu_mask(void);
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> >> index f607c39..5cf080f 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> >> @@ -9,6 +9,8 @@
> >>  #include 
> >>  #include 
> >>  #include 
> >> +#include "cpu.h"
> >> +#include 
> >>
> >>  DECLARE_GLOBAL_DATA_PTR;
> >>
> >> @@ -22,11 +24,30 @@ phys_addr_t determine_mp_bootpg(void)
> >>  return (phys_addr_t)_boot_code;
> >>  }
> >>
> >> +#ifdef CONFIG_FSL_LSCH3
> >> +void wake_secondary_core_n(int cluster, int core, int cluster_cores)
> >> +{
> >> +struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> >> +struct ccsr_reset __iomem *rst = (void
> *)(CONFIG_SYS_FSL_RST_ADDR);
> >> +u32 mpidr = 0;
> >> +
> >> +mpidr = ((cluster << 8) | core);
> >> +gur_out32(>scratchrw[6], mpidr);
> >
> > What's the definition of each bit for scratchrw[6]? Before this patch,
> > secondary cores only check if it is zero.
> >
> >> +asm volatile("dsb st" : : : "memory");
> >> +rst->brrl |= 1 << ((cluster * cluster_cores) + core);
> >> +asm volatile("dsb st" : : : "memory");
> >> +while (gur_in32(>scratchrw[6]) != 0)
> >> +;
> >
> > Does each secondary core clear this register after it starts to run?
> >
> 
> Priyanka,
> 
> I got hold of the architect for the bootrom. I understand the story behind the
> release one-by-one now. It would be better if you can add some comments
> for scratchrw[6] for its expected behaviour.
> 
> York

Thanks for your inputs.
I will add the comments in code about scratchrcw[6]
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Re: [U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization

[Mingkai Hu]

> -Original Message-
> From: york sun
> Sent: Tuesday, October 25, 2016 12:15 AM
> To: Prabhakar Kushwaha ; Pratiyush
> Srivastava ; u-boot@lists.denx.de; Mingkai
> Hu 
> Cc: Hou Zhiqiang 
> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization
> 
> On 10/23/2016 06:59 AM, Prabhakar Kushwaha wrote:
> > Hi York,
> >
> >
> >> -Original Message-
> >> From: york sun
> >> Sent: Saturday, October 22, 2016 1:39 AM
> >> To: Prabhakar Kushwaha ; Pratiyush
> >> Srivastava ; u-boot@lists.denx.de;
> >> Mingkai Hu 
> >> Cc: Hou Zhiqiang 
> >> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization
> >>
> >> On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote:
> >>> Hi Mingkai,
> >>>
>  -Original Message-
>  From: Pratiyush Srivastava [mailto:pratiyush.srivast...@nxp.com]
>  Sent: Wednesday, October 12, 2016 5:46 PM
>  To: u-boot@lists.denx.de
>  Cc: york sun ; Prabhakar Kushwaha
>  ; Pratiyush Srivastava
>  ; Hou Zhiqiang
> >> 
>  Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization
> 
>  Clear the content to zero and the ECC error bit of OCRAM1/2.
> 
>  The OCRAM must be initialized to ZERO by the unit of 8-Byte before
>  accessing it, or else it will generate ECC error. And the IBR has
>  accessed the OCRAM before this initialization, so the ECC error
>  status bit should to be cleared.
> 
>  Signed-off-by: Pratiyush Srivastava 
>  Signed-off-by: Hou Zhiqiang 
>  Signed-off-by: Prabhakar Kushwaha 
>  ---
> >>>
> >>> This requirement is for both ls1043 and ls1088a.  was this patch
> >>> taken care
> >> during ls1043a upstreaming
> >>> If not, how it is being taken care for ls1043a.  Same approach can
> >>> be used for
> >> ls1088a
> >>>
> >>
> >> I wonder why we don't see ECC errors before this patch. We have
> >> LS1043A boots on NAND, SD.
> >>
> >
> > OCRAM has a requirement of initializing before first time "read".
> > If user reads OCRAM before **initializing**; ECC error will come.  (u-boot 
> > is
> not handling this error for now).
> >
> > I can only guess the reason of not seeing this error as OCRAM never read
> before any write.
> > Even in case of Stack, data is first written and then read.
> >
> 
> Is there a case you want to read from OCRAM before writing anything to it?
> Why don't we need to do so for SPL or LSCH3?
> 

Hi York,

For secure boot case, the bootrom uses the OCRAM as workspace but does not
Cleare the after the using, which will trigger this issue.

Thanks,
Mingkai
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Re: [U-Boot] [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A SoC

[Priyanka Jain]

> -Original Message-
> From: york sun
> Sent: Tuesday, October 25, 2016 12:33 AM
> To: Priyanka Jain ; u-boot@lists.denx.de;
> Prabhakar Kushwaha 
> Cc: Priyanka Jain 
> Subject: Re: [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A
> SoC
> 
> On 10/24/2016 01:32 AM, Priyanka Jain wrote:
> > From: Priyanka Jain 
> >
> > LS2088A is similar to LS2080A SoC with some differences like 1)Timer
> > controller offset is different 2)It has A72 cores 3)Process to release
> > secondary cores is different 4)LS2088A SoC has TZASC controller
> >
> > In preparation of using same binary for LS2088A and LS2080A as both
> > are using same development boards. code is update to detect difference
> > based on SVR at runtime
> >
> >
> > Priyanka Jain (5):
> >   armv8: lsch3: Use SVR based timer base address detection
> >   armv8: fsl-layerscape: Update TZASC registers type
> >   armv8: fsl-layerscape : Check SVR for initializing TZASC
> >   armv8: fsl-layerscape: Add NXP LS2088A SoC support
> >   armv8/fsl-lsch3: Update code to release secondary cores
> 
> Priyanka,
> 
> Does PCIe work for you? It doesn't work for my test. The same binary works
> for LS2080ARDB/LS2085ARDB. Do you have other patches? I noticed several
> internal commits related to LS2088A PCIe. Do we need them?
> 
> York

There are some additional patches for PCIe for LS2088A.
I have requested Mingkai to send those patches

--Priyanka
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Re: [U-Boot] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support

[Jagan Teki]

Hi Stefano,

On Mon, Oct 24, 2016 at 7:51 PM, Jagan Teki  wrote:
> On Mon, Oct 24, 2016 at 7:31 PM, Stefano Babic  wrote:
>> On 24/10/2016 15:15, Jagan Teki wrote:
>>> On Mon, Oct 24, 2016 at 6:04 PM, Stefano Babic  wrote:
 Hi Jagan,
>>

 Please wait, I am confused. You have sent a complete V8, but as far as I
 understand the oinly changes are reported above (Patch 14/15).

 However, even if I have not tested, this would break bisecting, because
 patch 4/23 introduces the board and building with that commit leads to
 the error. So changes should be respective in patch 4 for mmc and patch
 21 for NAND taking as reference V8.
>>>
>>> Yes, I've added 14/23 and 15/23 for new changes so the previous 14/21
>>> becomes 16/23 now and the only missing one is 21/23. So I will update
>>> this 21/23 for v9. Hope this make clear for you.
>>
>> It is ok if you feel better to send V9 - what I meant it is just that
>> entries for CONFIG_DM_MM and CONFIG_DM_MMC_OPS should be done in the
>> same patch where the defconfig is added to avoid breaking bisecting.
>
> OK, then I will send the 14/23 with squash of 14/23 and 15/23 to 16/23
> and 21/23 v9.
> Does it fine?

Sent these two patches with v9, please let me know for any issues.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization

[Calvin Johnson]

Hi York,

>-Original Message-
>From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york sun
>Sent: Monday, October 24, 2016 9:45 PM
>To: Prabhakar Kushwaha ; Pratiyush Srivastava 
>; u-
>b...@lists.denx.de; Mingkai Hu 
>Cc: Hou Zhiqiang 
>Subject: Re: [U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization
>
>On 10/23/2016 06:59 AM, Prabhakar Kushwaha wrote:
>> Hi York,
>>
>>
>>> -Original Message-
>>> From: york sun
>>> Sent: Saturday, October 22, 2016 1:39 AM
>>> To: Prabhakar Kushwaha ; Pratiyush
>>> Srivastava ; u-boot@lists.denx.de;
>>> Mingkai Hu 
>>> Cc: Hou Zhiqiang 
>>> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization
>>>
>>> On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote:
 Hi Mingkai,

> -Original Message-
> From: Pratiyush Srivastava [mailto:pratiyush.srivast...@nxp.com]
> Sent: Wednesday, October 12, 2016 5:46 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Prabhakar Kushwaha
> ; Pratiyush Srivastava
> ; Hou Zhiqiang
>>> 
> Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization
>
> Clear the content to zero and the ECC error bit of OCRAM1/2.
>
> The OCRAM must be initialized to ZERO by the unit of 8-Byte before
> accessing it, or else it will generate ECC error. And the IBR has
> accessed the OCRAM before this initialization, so the ECC error
> status bit should to be cleared.
>
> Signed-off-by: Pratiyush Srivastava 
> Signed-off-by: Hou Zhiqiang 
> Signed-off-by: Prabhakar Kushwaha 
> ---

 This requirement is for both ls1043 and ls1088a.  was this patch
 taken care
>>> during ls1043a upstreaming
 If not, how it is being taken care for ls1043a.  Same approach can
 be used for
>>> ls1088a

>>>
>>> I wonder why we don't see ECC errors before this patch. We have
>>> LS1043A boots on NAND, SD.
>>>
>>
>> OCRAM has a requirement of initializing before first time "read".
>> If user reads OCRAM before **initializing**; ECC error will come.  (u-boot 
>> is not handling this error for now).
>>
>> I can only guess the reason of not seeing this error as OCRAM never read 
>> before any write.
>> Even in case of Stack, data is first written and then read.
>>
>
>Is there a case you want to read from OCRAM before writing anything to it? Why 
>don't we need to do so for SPL or LSCH3?

This issue will be seen ONLY in secure boot. It was reproduced on LS1043A also.

Regards
Calvin
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Re: [U-Boot] [PATCH 3/5][v2] armv8: fsl-layerscape : Check SVR for initializing TZASC

[york sun]

On 10/24/2016 10:27 AM, york@nxp.com wrote:
>
> Please clarify, before this patch the code runs through this section for
> LS2080A but actually it has no effect, correct?
>

Never mind. I just realized CONFIG_FSL_TZASC_400 wasn't defined before.

York
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[U-Boot] [PATCH] Add workaround for USB PHY errata

[Suresh Gupta]

The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY

Suresh Gupta (8):
  armv8: Add workaround for USB erratum A-009008
  armv8: Add workaround for USB erratum A-009798
  armv8: Add workaround for USB erratum A-008997
  armv8: Add workaround for USB erratum A-009007
  armv7: Add workaround for USB erratum A-009008
  armv7: Add workaround for USB erratum A-009798
  armv7: Add workaround for USB erratum A-008997
  armv7: Add workaround for USB erratum A-009007

 arch/arm/cpu/armv7/ls102xa/Kconfig |  16 +++
 arch/arm/cpu/armv7/ls102xa/soc.c   |  50 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  24 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 118 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  20 
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  12 +++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h  |  19 
 7 files changed, 259 insertions(+)

-- 
1.9.3

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[U-Boot] [PATCH] armv7: Add workaround for USB erratum A-008997

[Suresh Gupta]

Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change settings required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 16 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  9 +
 3 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index f816ed1..d8a8257 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -39,6 +40,9 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
+config SYS_FSL_ERRATUM_A008997
+   bool "Workaround for USB PHY erratum A008997"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 2e64708..19eb361 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+   u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+  (u8 *)(usb_phy) + USB_PHY_TX_OVRD_DRV_LO);
+   writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+  (u8 *)(usb_phy) + USB_PHY_MPLL_OVRD_IN_HI);
+   writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+  (u8 *)(usb_phy) + USB_PHY_LEVEL_OVRD_IN);
+   writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+  (u8 *)(usb_phy) + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 void s_init(void)
 {
 }
@@ -168,6 +183,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 8cafa07..c0e4372 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,15 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PHY_BASE   0x0851
+#define USB_PHY_TX_OVRD_DRV_LO 0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI0x0024
+#define USB_PHY_LEVEL_OVRD_IN  0x002a
+#define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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Re: [U-Boot] [RFC PATCH] lib/timer: initialize timebase_l/timebase_h

[Alexander Graf]

On 25/10/2016 02:51, Andre Przywara wrote:
> On systems using the generic timer routines defined in lib/time.c we
> use timebase_l and timebase_h fields from the gd to detect wraparounds
> in our tick counter. The tick calculcation algorithm silently assumes
> that a long is only 32 bits, which leads to wrong results when timebase_h
> is not 0 on 64-bit systems.
> As one possible fix lets initialize timebase_h (and timebase_l) to 0, so
> on 64-bit systems timebase_h will never(TM) be bigger than 0 and thus
> cannot spoil timebase_l by being ORed into it.
> 
> This fixes occasional timeout issues on the Pine64 (and possibly other
> ARM64 systems).
> 
> Signed-off-by: Andre Przywara 
> ---
> Hi,
> 
> I am bit puzzled what the proper fix is, this one is the easiest I could
> come up with. Not sure if the gd should be zeroed normally (and it's just
> broken on sunxi/arm64 because of some linker issues) or whether we really
> forgot to initialize those fields and just got away with it.

The gd clearing happens via crt0_64.S -> board_init_f_init_reserve().
There we should have fully cleared all memory associated with global data.

I can't see anything obviously wrong in that code. Could you try to dump
gd if the timer offsets are != 0 on init? Maybe we can conclude
something from the data in it.


Alex
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[U-Boot] [PATCH] armv8: ls2080a: Update serdes protocol support

[Priyanka Jain]

Add serdes protocol support for
Serdes1 protocol: 0x39, 0x4B, 0x4C, 0x4D
Serdes2 protocol: 0x47, 0x57

Signed-off-by: Priyanka Jain 
---
 arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c |6 +
 board/freescale/ls2080aqds/eth.c   |  122 +++-
 2 files changed, 125 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index eaa44a7..67d605e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
@@ -34,6 +34,11 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
QSGMII_A} },
{0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+   {0x39, {SGMII8, SGMII7, SGMII6, PCIE2, SGMII4, SGMII3, SGMII2,
+   PCIE1 } },
+   {0x4B, {PCIE2, PCIE2, PCIE2, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+   {0x4C, {XFI8, XFI7, XFI6, XFI5, PCIE1, PCIE1, PCIE1, PCIE1 } },
+   {0x4D, {SGMII8, SGMII7, PCIE2, PCIE2, SGMII4, SGMII3, PCIE1, PCIE1 } },
{}
 };
 static struct serdes_config serdes2_cfg_tbl[] = {
@@ -64,6 +69,7 @@ static struct serdes_config serdes2_cfg_tbl[] = {
SATA2 } },
{0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
SATA2 } },
+   {0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } },
{}
 };
 
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 95ff68b..8618506 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -64,7 +64,7 @@ static int sgmii_riser_phy_addr[] = {
 };
 
 /* Slot2 does not have EMI connections */
-#define EMI_NONE   0x
+#define EMI_NONE   0xFF
 #define EMI1_SLOT1 0
 #define EMI1_SLOT2 1
 #define EMI1_SLOT3 2
@@ -470,7 +470,49 @@ static void initialize_dpmac_to_slot(void)
}
break;
 
+   case 0x39:
+   printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+  serdes1_prtcl);
+   if (hwconfig_f("xqsgmii", env_hwconfig)) {
+   lane_to_slot_fsm1[0] = EMI1_SLOT3;
+   lane_to_slot_fsm1[1] = EMI1_SLOT3;
+   lane_to_slot_fsm1[2] = EMI1_SLOT3;
+   lane_to_slot_fsm1[3] = EMI_NONE;
+   } else {
+   lane_to_slot_fsm1[0] = EMI_NONE;
+   lane_to_slot_fsm1[1] = EMI_NONE;
+   lane_to_slot_fsm1[2] = EMI_NONE;
+   lane_to_slot_fsm1[3] = EMI_NONE;
+   }
+   lane_to_slot_fsm1[4] = EMI1_SLOT3;
+   lane_to_slot_fsm1[5] = EMI1_SLOT3;
+   lane_to_slot_fsm1[6] = EMI1_SLOT3;
+   lane_to_slot_fsm1[7] = EMI_NONE;
+   break;
+
+   case 0x4D:
+   printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+  serdes1_prtcl);
+   if (hwconfig_f("xqsgmii", env_hwconfig)) {
+   lane_to_slot_fsm1[0] = EMI1_SLOT3;
+   lane_to_slot_fsm1[1] = EMI1_SLOT3;
+   lane_to_slot_fsm1[2] = EMI_NONE;
+   lane_to_slot_fsm1[3] = EMI_NONE;
+   } else {
+   lane_to_slot_fsm1[0] = EMI_NONE;
+   lane_to_slot_fsm1[1] = EMI_NONE;
+   lane_to_slot_fsm1[2] = EMI_NONE;
+   lane_to_slot_fsm1[3] = EMI_NONE;
+   }
+   lane_to_slot_fsm1[4] = EMI1_SLOT3;
+   lane_to_slot_fsm1[5] = EMI1_SLOT3;
+   lane_to_slot_fsm1[6] = EMI_NONE;
+   lane_to_slot_fsm1[7] = EMI_NONE;
+   break;
+
case 0x2A:
+   case 0x4B:
+   case 0x4C:
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
   serdes1_prtcl);
break;
@@ -505,6 +547,38 @@ static void initialize_dpmac_to_slot(void)
lane_to_slot_fsm2[7] = EMI1_SLOT6;
}
break;
+
+   case 0x47:
+   printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+  serdes2_prtcl);
+   lane_to_slot_fsm2[0] = EMI_NONE;
+   lane_to_slot_fsm2[1] = EMI1_SLOT5;
+   lane_to_slot_fsm2[2] = EMI1_SLOT5;
+   lane_to_slot_fsm2[3] = EMI1_SLOT5;
+
+   if (hwconfig_f("xqsgmii", env_hwconfig)) {
+   lane_to_slot_fsm2[4] = EMI_NONE;
+   lane_to_slot_fsm2[5] = EMI1_SLOT5;
+   lane_to_slot_fsm2[6] = EMI1_SLOT5;
+   lane_to_slot_fsm2[7] = EMI1_SLOT5;
+   }
+   break;
+
+   case 0x57:
+   

[U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009798

[Suresh Gupta]

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig   |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h   |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h   |  1 +
 4 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ec3e50d..c62958e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -13,6 +13,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config ARCH_LS1046A
bool
@@ -23,6 +24,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config ARCH_LS2080A
bool
@@ -33,6 +35,7 @@ config ARCH_LS2080A
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config FSL_LSCH2
bool
@@ -59,6 +62,9 @@ config SYS_FSL_ERRATUM_A010539
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 88cced1..6b18252 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -49,6 +49,25 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+   val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -215,6 +234,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+   erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -392,6 +412,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+   erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b8c9926..b72d47a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -340,6 +340,7 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR_USB2   0x07C
 #define SCFG_USB3PRM1CR_USB3   0x088
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3683b39..a4bc036 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -135,6 +135,7 @@
 #define SCFG_USB3PRM1CR0x000
 #define SCFG_USB3PRM1CR_INIT   0x27672b2a
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 #define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
-- 
1.9.3

Re: [U-Boot] [PATCH] cmd: load: align cache flush

[Stefan Roese]

On 25.10.2016 09:22, Chris Packham wrote:

Prevent cache misalignment message by ensuring that a whole cache line
is flushed.

Signed-off-by: Chris Packham 
---

 cmd/load.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/load.c b/cmd/load.c
index 65557e4f9ec3..77c3359b29b7 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@ -997,7 +997,7 @@ static ulong load_serial_ymodem(ulong offset, int mode)
xyzModem_stream_terminate(false, );


-   flush_cache(offset, size);
+   flush_cache(offset, ALIGN(size, ARCH_DMA_MINALIGN));

printf("## Total Size  = 0x%08x = %d Bytes\n", size, size);
setenv_hex("filesize", size);



Reviewed-by: Stefan Roese 

Thanks,
Stefan
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[U-Boot] [PATCH] driver: net: ldpaa_eth: Fix missing bracket issue

[Priyanka Jain]

Signed-off-by: Priyanka Jain 
---
 drivers/net/ldpaa_eth/ldpaa_eth.c |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 75b2b6b..4e61700 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -420,13 +420,14 @@ static int ldpaa_eth_open(struct eth_device *net_dev, 
bd_t *bd)
goto err_dpmac_setup;
 
 #ifdef CONFIG_PHYLIB
-   if (priv->phydev)
+   if (priv->phydev) {
err = phy_startup(priv->phydev);
if (err) {
printf("%s: Could not initialize\n",
   priv->phydev->dev->name);
goto err_dpamc_bind;
}
+   }
 #else
priv->phydev = (struct phy_device *)malloc(sizeof(struct phy_device));
memset(priv->phydev, 0, sizeof(struct phy_device));
-- 
1.7.4.1

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Re: [U-Boot] [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to config.h

[Prabhakar Kushwaha]

> -Original Message-
> From: york sun
> Sent: Monday, October 24, 2016 9:41 PM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de
> Cc: o...@buserror.net
> Subject: Re: [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to
> config.h
> 
> On 10/23/2016 07:04 AM, Prabhakar Kushwaha wrote:
> > Hi York,
> >
> >> -Original Message-
> >> From: york sun
> >> Sent: Friday, October 21, 2016 7:55 PM
> >> To: Prabhakar Kushwaha ; u-
> >> b...@lists.denx.de
> >> Cc: o...@buserror.net
> >> Subject: Re: [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to
> >> config.h
> >>
> >> On 10/20/2016 11:37 PM, Prabhakar Kushwaha wrote:
> >>> Migration of IFC_BANK_COUNT from Kconfig to config.h avoids adding
> >>> SoC name in Kconfig as Dependencies. It will help in having
> >>> all SoC related defines in config.h - easy to maintain.
> >>>
> >>
> >> Prabhakar,
> >>
> >> Why do you want to go back to config.h? I think we are going with
> >> Kconfig. Having everything in one config file conflicts with Kconfig.
> >> The former has centralized config per SoC, the latter has centralized
> >> config per feature.
> >>
> >
> > There are 2 reason for this
> >
> > 1) in File arch/arm/cpu/armv8/fsl-layerscape/Kconfig, "depends" row will 
> > keep
> on increasing with SoC.
> > And if I add new field CONFIG_SYS_FSL_IFC_CLK_DIV, similar entry will be
> done and it will also keep on increasing with SoC.
> > I want to avoid it.
> >
> > config SYS_FSL_IFC_BANK_COUNT
> > int "Maximum banks of Integrated flash controller"
> > depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
> 
> The "depends" line can be rewritten with HAS_* feature macro.
> 
> > default 4 if ARCH_LS1043A
> > default 4 if ARCH_LS1046A
> > default 8 if ARCH_LS2080A
> 
> You can simplify the "default 4" for all and only use different number
> for others.
> 

ok


> >
> > 2) There is no file similar to  " 
> > arch/arm/cpu/armv8/fsl-layerscape/Kconfig" for
> powerpc platform. So how to add new " CONFIG SYS_FSL_IFC_CLK_DIV" with
> different values per SoC.
> >This problem will come for defining other clocks for " armv8/fsl-lsch3:
> consolidate the clock system initialization"
> >
> 
> We will convert powerpc as well.

This means, IFC and clock related patches needs to wait till powerpc is 
converted as well.

-prabhakar

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[U-Boot] [PATCH] cmd: load: align cache flush

[Chris Packham]

Prevent cache misalignment message by ensuring that a whole cache line
is flushed.

Signed-off-by: Chris Packham 
---

 cmd/load.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/load.c b/cmd/load.c
index 65557e4f9ec3..77c3359b29b7 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@ -997,7 +997,7 @@ static ulong load_serial_ymodem(ulong offset, int mode)
xyzModem_stream_terminate(false, );
 
 
-   flush_cache(offset, size);
+   flush_cache(offset, ALIGN(size, ARCH_DMA_MINALIGN));
 
printf("## Total Size  = 0x%08x = %d Bytes\n", size, size);
setenv_hex("filesize", size);
-- 
2.10.1

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[U-Boot] [PATCH] armv8: Add workaround for USB erratum A-008997

[Suresh Gupta]

Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change settings required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 29 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 41 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index c62958e..a2f3237 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -14,6 +14,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
 
 config ARCH_LS1046A
bool
@@ -25,6 +26,7 @@ config ARCH_LS1046A
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
 
 config ARCH_LS2080A
bool
@@ -36,6 +38,7 @@ config ARCH_LS2080A
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
 
 config FSL_LSCH2
bool
@@ -65,6 +68,9 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
+config SYS_FSL_ERRATUM_A008997
+   bool "Workaround for USB PHY erratum A008997"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6b18252..1d0354d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -68,6 +68,33 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -235,6 +262,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -413,6 +441,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a010539();
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b72d47a..a7e36cd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -337,10 +337,14 @@ struct ccsr_gur {
 
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM2CR_USB1   0x074
 #define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM2CR_USB2   0x080
 #define SCFG_USB3PRM1CR_USB3   0x088
+#define SCFG_USB3PRM2CR_USB3   0x08c
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PCSTXSWINGFULL 0x47
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index a4bc036..cdc08ed 100644
--- 

[U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009008

[Suresh Gupta]

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.

Signed-off-by: Sriram Dash 
---
 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 
 3 files changed, 20 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 28bf778..9f0188a 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
+   select SYS_FSL_ERRATUM_A009008
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -31,6 +32,9 @@ config NUM_DDR_CONTROLLERS
 config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8..c54daee 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void)
return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 void s_init(void)
 {
 }
@@ -146,6 +156,8 @@ int arch_soc_init(void)
 */
out_be32(>eddrtqcfg, 0x63b20042);
 
+   /* Erratum */
+   erratum_a009008();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..6ea8c4b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@ struct ccsr_gur {
 #define SCFG_PMCINTECR_ETSECERRG1  0x0004
 #define SCFG_CLUSTERPMCR_WFIL2EN   0x8000
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR0x070
+#define USB_TXVREFTUNE 0x9
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u32 dpslpcr;
-- 
1.9.3

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[U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009008

[Suresh Gupta]

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 25 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 4 files changed, 38 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..ec3e50d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -12,6 +12,7 @@ config ARCH_LS1043A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
 
 config ARCH_LS1046A
bool
@@ -21,6 +22,7 @@ config ARCH_LS1046A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_SRDS_2
+   select SYS_FSL_ERRATUM_A009008
 
 config ARCH_LS2080A
bool
@@ -30,6 +32,7 @@ config ARCH_LS2080A
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_SRDS_2
+   select SYS_FSL_ERRATUM_A009008
 
 config FSL_LSCH2
bool
@@ -53,6 +56,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d68eeba..88cced1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -26,6 +26,29 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -191,6 +214,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+   erratum_a009008();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -367,6 +391,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+   erratum_a009008();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..b8c9926 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -335,6 +335,12 @@ struct ccsr_gur {
 #define SCFG_USBPWRFAULT_USB2_SHIFT2
 #define SCFG_USBPWRFAULT_USB1_SHIFT0
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM1CR_USB3   0x088
+#define USB_TXVREFTUNE 0x9
+
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 7acba27..3683b39 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -134,6 +134,7 @@
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
 #define SCFG_USB3PRM1CR_INIT   0x27672b2a
+#define USB_TXVREFTUNE  

[U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009007

[Suresh Gupta]

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 +++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 43 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  9 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  8 
 4 files changed, 66 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a2f3237..9965228 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -15,6 +15,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
 
 config ARCH_LS1046A
bool
@@ -27,6 +28,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
 
 config ARCH_LS2080A
bool
@@ -39,6 +41,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
 
 config FSL_LSCH2
bool
@@ -71,6 +74,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1d0354d..1f08b89 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -95,6 +95,47 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+/* TODO:implement the out_be16 instead of writew which is taking
+little endian style */
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY1;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (u32 __iomem *)USB_PHY2;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (u32 __iomem *)USB_PHY3;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *dcsr = (u32 __iomem *)DCSR_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_1,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -263,6 +304,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -442,6 +484,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009008();
erratum_a009798();

[U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009798

[Suresh Gupta]

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 10 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 9f0188a..f816ed1 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1021A
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -35,6 +36,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index c54daee..2e64708 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 void s_init(void)
 {
 }
@@ -158,6 +167,7 @@ int arch_soc_init(void)
 
/* Erratum */
erratum_a009008();
+   erratum_a009798();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 6ea8c4b..8cafa07 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,7 @@ struct ccsr_gur {
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009007

[Suresh Gupta]

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index d8a8257..9313c11 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -43,6 +44,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 19eb361..4754907 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+   u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c0e4372..9c4c926 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,10 +182,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI0x0024
 #define USB_PHY_LEVEL_OVRD_IN  0x002a
 #define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
+#define USB_PHY_RX_EQ_VAL_10x
+#define USB_PHY_RX_EQ_VAL_20x8000
+#define USB_PHY_RX_EQ_VAL_30x8004
+#define USB_PHY_RX_EQ_VAL_40x800C
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v9 21/23] imx6: icorem6: Add NAND support

[Jagan Teki]

From: Jagan Teki 

Add NAND support for Engicam i.CoreM6 qdl board.

Boot Log:


U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43)
Trying to boot from NAND
NAND : 512 MiB

U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530)

CPU:   Freescale i.MX6SOLO rev1.3 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 55C
Reset cause: WDOG
Model: Engicam i.CoreM6 DualLite/Solo Starter Kit
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0
icorem6qdl>

Cc: Scott Wood 
Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
Changes for v9:
- Add below configs on defconfig
  # CONFIG_BLK is not set
  # CONFIG_DM_MMC_OPS is not set

 board/engicam/icorem6/icorem6.c  | 63 
 configs/imx6qdl_icore_nand_defconfig | 37 +
 include/configs/imx6qdl_icore.h  | 25 +-
 3 files changed, 124 insertions(+), 1 deletion(-)
 create mode 100644 configs/imx6qdl_icore_nand_defconfig

diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index a370c8b..c152007 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -101,6 +101,66 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+   PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+iomux_v3_cfg_t gpmi_pads[] = {
+   IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE  | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE  | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B  | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+   IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+};
+
+static void setup_gpmi_nand(void)
+{
+   struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   /* config gpmi nand iomux */
+   SETUP_IOMUX_PADS(gpmi_pads);
+
+   /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+   clrbits_le32(_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+   /* config gpmi and bch clock to 100 MHz */
+   clrsetbits_le32(_ccm->cs2cdr,
+   MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+   MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+   MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+   MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+   MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+   MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+   /* enable ENFC_CLK_ROOT clock */
+   setbits_le32(_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+   /* enable gpmi and bch clock gating */
+   setbits_le32(_ccm->CCGR4,
+MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+   /* enable apbh clock gating */
+   setbits_le32(_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
 int board_early_init_f(void)
 {
SETUP_IOMUX_PADS(uart4_pads);
@@ -113,6 +173,9 @@ int board_init(void)
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_NAND_MXS
+   setup_gpmi_nand();
+#endif
return 0;
 }
 
diff --git a/configs/imx6qdl_icore_nand_defconfig 
b/configs/imx6qdl_icore_nand_defconfig
new file mode 100644
index 000..8ac3099
--- /dev/null
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -0,0 

[U-Boot] [PATCH v9 14/23] engicam: icorem6: Add DM_GPIO, DM_MMC support

[Jagan Teki]

From: Jagan Teki 

Add DM_GPIO, DM_MMC support for u-boot and disable for SPL.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig  |   2 +
 board/engicam/icorem6/icorem6.c | 142 ++--
 configs/imx6qdl_icore_mmc_defconfig |   2 +
 include/configs/imx6qdl_icore.h |   4 +
 4 files changed, 80 insertions(+), 70 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index e2431a8..762a581 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -100,6 +100,8 @@ config TARGET_MX6Q_ICORE
select MX6QDL
select OF_CONTROL
select DM
+   select DM_GPIO
+   select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
 
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index a23cb7e..a370c8b 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -7,8 +7,6 @@
  */
 
 #include 
-#include 
-#include 
 #include 
 #include 
 
@@ -29,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
-   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
-   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
@@ -55,70 +49,6 @@ static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-   IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
-};
-
-#ifdef CONFIG_FSL_ESDHC
-#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
-   {USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-   struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-   int ret = 0;
-
-   switch (cfg->esdhc_base) {
-   case USDHC1_BASE_ADDR:
-   ret = !gpio_get_value(USDHC1_CD_GPIO);
-   break;
-   }
-
-   return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-   int i, ret;
-
-   /*
-   * According to the board_mmc_init() the following map is done:
-   * (U-boot device node)(Physical Port)
-   * mmc0  USDHC1
-   */
-   for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-   switch (i) {
-   case 0:
-   SETUP_IOMUX_PADS(usdhc1_pads);
-   gpio_direction_input(USDHC1_CD_GPIO);
-   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-   break;
-   default:
-   printf("Warning - USDHC%d controller not supporting\n",
-  i + 1);
-   return 0;
-   }
-
-   ret = fsl_esdhc_initialize(bis, _cfg[i]);
-   if (ret) {
-   printf("Warning: failed to initialize mmc dev %d\n", i);
-   return ret;
-   }
-   }
-
-   return 0;
-}
-#endif
-
 #ifdef CONFIG_FEC_MXC
 #define ENET_PHY_RST   IMX_GPIO_NR(7, 12)
 static int setup_fec(void)
@@ -200,6 +130,78 @@ int dram_init(void)
 #include 
 #include 
 
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include 
+#include 
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
+   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+   IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 |