[U-Boot] [PATCH 0/3] Extend xhci-dwc3
From: Patrice Chotard Convert xhci-dwc3 to Driver Model Add dual role mode selection from DT Add generic PHY support Patrice Chotard (3): usb: host: xhci-dwc3: Convert driver to DM usb: host: xhci-dwc3: Add dual role mode support from DT usb: host: xhci-dwc3: Add generic PHY support drivers/usb/host/xhci-dwc3.c | 109 +++ 1 file changed, 109 insertions(+) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/3] usb: host: xhci-dwc3: Convert driver to DM
From: Patrice Chotard
Add Driver Model support with use of generic DT
compatible string "snps,dwc3"
Signed-off-by: Patrice Chotard
---
drivers/usb/host/xhci-dwc3.c | 71
1 file changed, 71 insertions(+)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 33961cd..b0b9076 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -9,9 +9,23 @@
*/
#include
+#include
+#include
+
+#include "xhci.h"
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
+struct xhci_dwc3_platdata {
+ phys_addr_t dwc3_regs;
+};
+
+struct xhci_dwc3_priv {
+ struct xhci_ctrl ctrl;
+};
+
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(&dwc3_reg->g_ctl,
@@ -97,3 +111,60 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
GFLADJ_30MHZ(val));
}
+
+static int xhci_dwc3_ofdata_to_platdata(struct udevice *dev)
+{
+ struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ u32 reg[2];
+
+ /* get the dwc3 register space base address */
+ if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "reg", reg,
+ARRAY_SIZE(reg))) {
+ debug("dwc3 node has bad/missing 'reg' property\n");
+ return -FDT_ERR_NOTFOUND;
+ }
+ plat->dwc3_regs = reg[0];
+
+ return 0;
+}
+
+static int xhci_dwc3_probe(struct udevice *dev)
+{
+ struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ struct xhci_hcor *hcor;
+ struct xhci_hccr *hccr;
+ struct dwc3 *dwc3_reg;
+
+ hccr = (struct xhci_hccr *)plat->dwc3_regs;
+ hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
+ HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+
+ dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
+
+ dwc3_core_init(dwc3_reg);
+
+ return xhci_register(dev, hccr, hcor);
+}
+
+static int xhci_dwc3_remove(struct udevice *dev)
+{
+ return xhci_deregister(dev);
+}
+
+static const struct udevice_id xhci_dwc3_ids[] = {
+ { .compatible = "snps,dwc3" },
+ { }
+};
+
+U_BOOT_DRIVER(xhci_dwc3) = {
+ .name = "xhci-dwc3",
+ .id = UCLASS_USB,
+ .of_match = xhci_dwc3_ids,
+ .ofdata_to_platdata = xhci_dwc3_ofdata_to_platdata,
+ .probe = xhci_dwc3_probe,
+ .remove = xhci_dwc3_remove,
+ .ops = &xhci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct xhci_dwc3_priv),
+ .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
--
1.9.1
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[U-Boot] [PATCH 2/3] usb: host: xhci-dwc3: Add dual role mode support from DT
From: Patrice Chotard DWC3 dual role mode is selected using DT "dr_mode" property. If not found, DWC3 controller is configured in HOST mode by default Signed-off-by: Patrice Chotard --- drivers/usb/host/xhci-dwc3.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index b0b9076..ea85834 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -15,6 +15,7 @@ #include "xhci.h" #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -134,6 +135,7 @@ static int xhci_dwc3_probe(struct udevice *dev) struct xhci_hcor *hcor; struct xhci_hccr *hccr; struct dwc3 *dwc3_reg; + enum usb_dr_mode dr_mode; hccr = (struct xhci_hccr *)plat->dwc3_regs; hcor = (struct xhci_hcor *)((phys_addr_t)hccr + @@ -143,6 +145,13 @@ static int xhci_dwc3_probe(struct udevice *dev) dwc3_core_init(dwc3_reg); + dr_mode = usb_get_dr_mode(dev_of_offset(dev)); + if (dr_mode == USB_DR_MODE_UNKNOWN) + /* by default set dual role mode to HOST */ + dr_mode = USB_DR_MODE_HOST; + + dwc3_set_mode(dwc3_reg, dr_mode); + return xhci_register(dev, hccr, hcor); } -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/3] usb: host: xhci-dwc3: Add generic PHY support
From: Patrice Chotard
Add support of generic PHY framework support
Signed-off-by: Patrice Chotard
---
drivers/usb/host/xhci-dwc3.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index ea85834..70d3946 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -10,6 +10,8 @@
#include
#include
+#include
+#include
#include
#include "xhci.h"
@@ -20,6 +22,7 @@
DECLARE_GLOBAL_DATA_PTR;
struct xhci_dwc3_platdata {
+ struct phy usb_phy;
phys_addr_t dwc3_regs;
};
@@ -136,11 +139,26 @@ static int xhci_dwc3_probe(struct udevice *dev)
struct xhci_hccr *hccr;
struct dwc3 *dwc3_reg;
enum usb_dr_mode dr_mode;
+ int ret;
hccr = (struct xhci_hccr *)plat->dwc3_regs;
hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+ ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
+ if (ret) {
+ if (ret != -ENOENT) {
+ error("Failed to get USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ } else {
+ ret = generic_phy_init(&plat->usb_phy);
+ if (ret) {
+ error("Can't init USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ }
+
dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
dwc3_core_init(dwc3_reg);
@@ -157,6 +175,17 @@ static int xhci_dwc3_probe(struct udevice *dev)
static int xhci_dwc3_remove(struct udevice *dev)
{
+ struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ if (plat->usb_phy.dev) {
+ ret = generic_phy_exit(&plat->usb_phy);
+ if (ret) {
+ error("Can't deinit USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ }
+
return xhci_deregister(dev);
}
--
1.9.1
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Re: [U-Boot] [PATCH] board_f: skip timer_init() on Coldfire archs
Hi Simon.
On 17/05/2017 03:38, Simon Glass wrote:
Hi Angelo,
On 10 May 2017 at 16:36, Angelo Dureghello wrote:
Hi Simon,
On 11/05/2017 00:03, Simon Glass wrote:
Hi Angelo,
On 10 May 2017 at 15:58, Angelo Dureghello wrote:
Coldfire arch is not happy with timer_init since interrupt handlers
are still not set at that stage, and the boot hangs silently.
Signed-off-by: Angelo Dureghello
---
common/board_f.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c
index d9431ee79a..30e588e213 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -740,7 +740,9 @@ static const init_fnc_t init_sequence_f[] = {
/* get CPU and bus clocks according to the environment variable
*/
get_clocks, /* get CPU and bus clocks (etc.) */
#endif
+#if !defined(CONFIG_M68K)
timer_init, /* initialize timer */
+#endif
#if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init,
#endif
--
2.11.0
I'm really hoping we can get rid of all arch-specific things from the
init sequence.
Yes, i have seen you unified that step for all archs, and unfortunately i
discovered the issue now only updating u-boot on my mcf5307 based board.
Is there no way that m68k can init its timer here? Or perhaps it could
be a nop function?
I checked now all the cpu/xxx/start.S. At that early stage, all the
vector handlers are set to _fault thats is just and endless loop.
In Coldfire arch, timer_init() is implemented in lib/time.c, as to
setup and start the system timer overflow interrupt. It is called later
from board_init_r(), line 863, after interrupt_init().
So, no :( unless you don't have some suggestion, i don't see any easy
way to keep that timer_init() call enabled in board_init_f().
My only ideas are:
- user driver model for timer and then call the interrupt init from
your driver's probe() method
- make timer_init() a nop for you arch
thanks, it sounds good.
Ok, i see the patch has been applied to master so we have
the things working for now.
I'll try to do the change above in the next future,
i keep it in the todo list.
Regards,
Angelo
Regards,
Simon
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Re: [U-Boot] [PATCH v2 2/2] test: py: hush: Add echo dependency
On 18.5.2017 18:27, Stephen Warren wrote:
> On 05/18/2017 01:23 AM, Michal Simek wrote:
>> Some tests depends on echo command to be present.
>
>> diff --git a/test/py/tests/test_hush_if_test.py
>> b/test/py/tests/test_hush_if_test.py
>
>> +@pytest.mark.buildconfigspec('cmd_echo')
>> @pytest.mark.parametrize('expr,result', subtests)
>> def test_hush_if_test(u_boot_console, expr, result):
>> """Test a single "if test" condition."""
>
> This change is technically correct I admit.
>
> However, there's not much point allowing test_hush_if_test_setup() and
> test_hush_if_test_teardown() to run if test_hush_if_test() doesn't run,
> so I'd be inclined to make this a file-level mark rather than a
> function-/test-level mark, just like the other mark for the dependency
> on CONFIG_HUSH_PARSER.
>
> Still, either way is OK I guess.
I choose this way because in future someone can add more tests for hush
which won't use echo. And still that two tests which runs are doing
something what can failed that's why not run them.
Anyway not a problem to mark the whole file too if syntax enables it.
Thanks,
Michal
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Re: [U-Boot] [PATCH 1/3] usb: host: xhci-dwc3: Convert driver to DM
On 05/19/2017 09:15 AM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Add Driver Model support with use of generic DT
> compatible string "snps,dwc3"
>
> Signed-off-by: Patrice Chotard
> ---
> drivers/usb/host/xhci-dwc3.c | 71
>
> 1 file changed, 71 insertions(+)
>
> diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
> index 33961cd..b0b9076 100644
> --- a/drivers/usb/host/xhci-dwc3.c
> +++ b/drivers/usb/host/xhci-dwc3.c
> @@ -9,9 +9,23 @@
> */
>
> #include
> +#include
> +#include
> +
> +#include "xhci.h"
> #include
> #include
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct xhci_dwc3_platdata {
> + phys_addr_t dwc3_regs;
> +};
Since you have DM, do you need this ?
> +struct xhci_dwc3_priv {
> + struct xhci_ctrl ctrl;
> +};
> +
> void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
> {
> clrsetbits_le32(&dwc3_reg->g_ctl,
> @@ -97,3 +111,60 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
> setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
> GFLADJ_30MHZ(val));
> }
> +
> +static int xhci_dwc3_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
> + u32 reg[2];
> +
> + /* get the dwc3 register space base address */
> + if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "reg", reg,
> + ARRAY_SIZE(reg))) {
dev_get_addr() ?
> + debug("dwc3 node has bad/missing 'reg' property\n");
> + return -FDT_ERR_NOTFOUND;
> + }
> + plat->dwc3_regs = reg[0];
> +
> + return 0;
> +}
> +
> +static int xhci_dwc3_probe(struct udevice *dev)
> +{
> + struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
> + struct xhci_hcor *hcor;
> + struct xhci_hccr *hccr;
> + struct dwc3 *dwc3_reg;
> +
> + hccr = (struct xhci_hccr *)plat->dwc3_regs;
> + hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
> + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
> +
> + dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
> +
> + dwc3_core_init(dwc3_reg);
> +
> + return xhci_register(dev, hccr, hcor);
> +}
> +
> +static int xhci_dwc3_remove(struct udevice *dev)
> +{
> + return xhci_deregister(dev);
> +}
> +
> +static const struct udevice_id xhci_dwc3_ids[] = {
> + { .compatible = "snps,dwc3" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(xhci_dwc3) = {
> + .name = "xhci-dwc3",
> + .id = UCLASS_USB,
> + .of_match = xhci_dwc3_ids,
> + .ofdata_to_platdata = xhci_dwc3_ofdata_to_platdata,
> + .probe = xhci_dwc3_probe,
> + .remove = xhci_dwc3_remove,
> + .ops = &xhci_usb_ops,
> + .priv_auto_alloc_size = sizeof(struct xhci_dwc3_priv),
> + .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
> + .flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 3/3] usb: host: xhci-dwc3: Add generic PHY support
On 05/19/2017 09:15 AM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Add support of generic PHY framework support
>
> Signed-off-by: Patrice Chotard
> ---
> drivers/usb/host/xhci-dwc3.c | 29 +
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
> index ea85834..70d3946 100644
> --- a/drivers/usb/host/xhci-dwc3.c
> +++ b/drivers/usb/host/xhci-dwc3.c
> @@ -10,6 +10,8 @@
>
> #include
> #include
> +#include
> +#include
> #include
>
> #include "xhci.h"
> @@ -20,6 +22,7 @@
> DECLARE_GLOBAL_DATA_PTR;
>
> struct xhci_dwc3_platdata {
> + struct phy usb_phy;
> phys_addr_t dwc3_regs;
> };
>
> @@ -136,11 +139,26 @@ static int xhci_dwc3_probe(struct udevice *dev)
> struct xhci_hccr *hccr;
> struct dwc3 *dwc3_reg;
> enum usb_dr_mode dr_mode;
> + int ret;
>
> hccr = (struct xhci_hccr *)plat->dwc3_regs;
> hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
> HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
>
> + ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
> + if (ret) {
> + if (ret != -ENOENT) {
> + error("Failed to get USB PHY for %s\n", dev->name);
> + return ret;
> + }
> + } else {
You can drop the else and indent here by reordering the condition.
Otherwise OK.
> + ret = generic_phy_init(&plat->usb_phy);
> + if (ret) {
> + error("Can't init USB PHY for %s\n", dev->name);
> + return ret;
> + }
> + }
> +
> dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
>
> dwc3_core_init(dwc3_reg);
> @@ -157,6 +175,17 @@ static int xhci_dwc3_probe(struct udevice *dev)
>
> static int xhci_dwc3_remove(struct udevice *dev)
> {
> + struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
> + int ret;
> +
> + if (plat->usb_phy.dev) {
> + ret = generic_phy_exit(&plat->usb_phy);
> + if (ret) {
> + error("Can't deinit USB PHY for %s\n", dev->name);
> + return ret;
> + }
> + }
> +
> return xhci_deregister(dev);
> }
>
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] litesom.c: Board stuff in SOC ?
Hi Stefano, I've added Tom to the discussion. So if we make some changes to SOM code position in u-boot tree, let's make sure we do it for all architectures the same (at least I mean chilisom code which is in arch/arm/mach-omap2/am33xx/). On 18.05.2017 17:20, Stefano Babic wrote: Hi Marcin, On 18/05/2017 16:57, Marcin Niestroj wrote: Hi Stefano, On 18.05.2017 16:28, Stefano Babic wrote: Hi Marcin, even if it was already merged (and maybe I am guilty of it because I have not noted before), it is completely crazy that a board is stored inside the SOC directory. The litesom board is in fact in ./arch/arm/cpu/armv7/mx6/litesom.c, and there is nothing that justify this. The code has just board related stuff and nothing common for all SOC. litesom is not a board, but a SOM. It does not matter, sorry. The code is not common for all boards (and if you like it, all SOMs) sharing the same SOC or SOC family. In this case, i.MX6. There is plenty of such as example in U-Boot, please check it in code. SOM support is in the boards directory and it must not be here. It will be removed. It has only RAM and eMMC memory included with the processor. Like all SOMs you find in u-boot from a lot of different vendors...just check it. litesom cannot work on it's own. It needs to be part of some board. An example board is liteboard, which support is included in board/grinn/liteboard/. Please visit [2] to visualize what the litesom device is. Thanks, nothing new. Again: the SOM is specific to a vendor and cannot be in the SOC directory. There should be then a board/grinn/common (or whatever you want) where SOM code is put. And again, not in SOC directory. The idea about creating a separate file in arch/arm/cpu/armv7/mx6/ The idea is correct, just in wrong place. There are plenty of examples doing this: ./engicam/common Ok, I see. But it was just merged, so I couldn't look at it earlier. As I understand, you want me to follow this example with litesom. I do not say that is a bad idea in general and we should not follow it. *BUT* right now these sources cannot be used when other vendor will create it's own board. They won't compile, because root Makefile has a "libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/" entry, which depends on *board* vendor. ./freescale/common There is a lot of shared code between freescale boards, but I do not see SOM example there. Could you point me one? ./compulab/common I do not see SOM code there. There is also ./compulab/cl-som-am57x directory, but it contains *board* support code, which uses CL-SOM-AM57x, not pure SOM (e.g. they configure UART and SD card, which are not SOM specific). and many others. was to be able to reuse code when new boards, that use litesom as it's core, will be added. And these boards need not to be manufactured or designed by Grinn. Right, so why are we discussing ? They belong to grinn, that means the code should be in board/, that is board/grinn. Please move it ! So if some other vendor wants to add support for it's board (which will be based on litesom), the code to initialize RAM and eMMC can be reused. They will be put code into the grimm directory. See all other vendors selling SOMs. When litesom code would be part of board/grinn/ directory, then other vendors could not easily add support for their boards without copying litesom sources. I will take care that the code will not be duplicated - not worry. Ok. Could you tell me how that would be done? That is my main concern about moving SOM sources to ./board//common. In fact I've already asked about that in both RFC for adding lite(som/board) [3] [4] and described my motivation in PATCH adding lite(som/board) [5] support in u-boot. [3] https://lists.denx.de/pipermail/u-boot/2016-August/265384.html [4] https://lists.denx.de/pipermail/u-boot/2016-September/266534.html [5] https://lists.denx.de/pipermail/u-boot/2016-September/266799.html Please move it or it will be removed, thanks ! [2] http://grinn-global.com/litesom/ I just took again the commit and I see: Moving arch/arm/mach-litesom/ to arch/arm/cpu/armv7/mx6/ was requested in [1] during discussion of chiliSOM support patches. [1] http://lists.denx.de/pipermail/u-boot/2017-January/279137.html But [1] has nothing to do with the context. I will tend to revert this patch and wait for an appropriate patch that add support for the board just like all other boards in U-Boot - as it is currently, it is wrong. Link [1] was a discussion of adding chilisom support into u-boot. The idea was the same - allow to reuse SOM code for vendors creating their own board based on our SOMs. Idea is already used in U-Boot and the SOM vendor has priority. Else code inside arch/arm/cpu/*, that must be common to all boards and *all* SOMs using those processor is becoming a mess. Please move it. I do not oppose to move SOM sources from arch/arm/cpu/*, but in my opinion we need some mechanism for reusing SO
Re: [U-Boot] litesom.c: Board stuff in SOC ?
Hi Marcin, On 19/05/2017 12:41, Marcin Niestroj wrote: > Hi Stefano, > > I've added Tom to the discussion. Of course ! > So if we make some changes to SOM > code position in u-boot tree, let's make sure we do it for all > architectures the same We have already not done in this way. We have all boards / SOM code inside bords/, the only exceptions are yours. If there is a decision to add an abstraction for SOM, we have to put coherently all SOMs that are now stored in the boards directory. What you mention are just exception - that I would like to clean up. Best regards, Stefano Babic > (at least I mean chilisom code which is in > arch/arm/mach-omap2/am33xx/ > > On 18.05.2017 17:20, Stefano Babic wrote: >> Hi Marcin, >> >> On 18/05/2017 16:57, Marcin Niestroj wrote: >>> Hi Stefano, >>> >>> On 18.05.2017 16:28, Stefano Babic wrote: Hi Marcin, even if it was already merged (and maybe I am guilty of it because I have not noted before), it is completely crazy that a board is stored inside the SOC directory. The litesom board is in fact in ./arch/arm/cpu/armv7/mx6/litesom.c, and there is nothing that justify this. The code has just board related stuff and nothing common for all SOC. >>> >>> litesom is not a board, but a SOM. >> >> It does not matter, sorry. The code is not common for all boards (and if >> you like it, all SOMs) sharing the same SOC or SOC family. In this case, >> i.MX6. >> >> There is plenty of such as example in U-Boot, please check it in code. >> SOM support is in the boards directory and it must not be here. It will >> be removed. >> >>> It has only RAM and eMMC memory >>> included with the processor. >> >> Like all SOMs you find in u-boot from a lot of different vendors...just >> check it. >> >>> litesom cannot work on it's own. It needs >>> to be part of some board. An example board is liteboard, which support >>> is included in board/grinn/liteboard/. Please visit [2] to visualize >>> what the litesom device is. >> >> Thanks, nothing new. >> >> Again: the SOM is specific to a vendor and cannot be in the SOC >> directory. There should be then a board/grinn/common (or whatever you >> want) where SOM code is put. And again, not in SOC directory. >> >>> >>> The idea about creating a separate file in arch/arm/cpu/armv7/mx6/ >> >> The idea is correct, just in wrong place. There are plenty of examples >> doing this: >> >> ./engicam/common > > Ok, I see. But it was just merged, so I couldn't look at it earlier. > As I understand, you want me to follow this example with litesom. > > I do not say that is a bad idea in general and we should not follow it. > *BUT* right now these sources cannot be used when other vendor > will create it's own board. They won't compile, because root Makefile > has a "libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/" > entry, which depends on *board* vendor. > >> ./freescale/common > > There is a lot of shared code between freescale boards, but I do not see > SOM example there. Could you point me one? > >> ./compulab/common > > I do not see SOM code there. There is also ./compulab/cl-som-am57x > directory, but it contains *board* support code, which uses > CL-SOM-AM57x, not pure SOM (e.g. they configure UART and SD card, > which are not SOM specific). > >> >> >> and many others. >> >>> was to be able to reuse code when new boards, that use litesom >>> as it's core, will be added. And these boards need not to be >>> manufactured or designed by Grinn. >> >> Right, so why are we discussing ? They belong to grinn, that means the >> code should be in board/, that is board/grinn. Please move it ! >> >>> So if some other vendor wants >>> to add support for it's board (which will be based on litesom), >>> the code to initialize RAM and eMMC can be reused. >> >> They will be put code into the grimm directory. See all other vendors >> selling SOMs. >> >>> When litesom >>> code would be part of board/grinn/ directory, then other vendors >>> could not easily add support for their boards without copying >>> litesom sources. >> >> I will take care that the code will not be duplicated - not worry. > > Ok. Could you tell me how that would be done? That is my main concern > about moving SOM sources to ./board//common. In fact I've > already asked about that in both RFC for adding lite(som/board) [3] [4] > and described my motivation in PATCH adding lite(som/board) [5] support > in u-boot. > > [3] https://lists.denx.de/pipermail/u-boot/2016-August/265384.html > [4] https://lists.denx.de/pipermail/u-boot/2016-September/266534.html > [5] https://lists.denx.de/pipermail/u-boot/2016-September/266799.html > >> >> Please move it or it will be removed, thanks ! >> >>> >>> [2] http://grinn-global.com/litesom/ >>> I just took again the commit and I see: Moving arch/arm/mach-litesom/ to arch/arm/cpu/armv7/mx6/ was requested in [1] during discussion of chiliSOM support patches. [1] http://lis
[U-Boot] [PATCH 1/3] nds32: Support AG101P serial DM.
From: rick
Support AG101P serial device tree flow.
Signed-off-by: rick
---
arch/Kconfig|1 +
arch/nds32/cpu/n1213/start.S| 10 +---
arch/nds32/dts/Makefile | 14 +++
arch/nds32/dts/ag101p.dts | 49 +++
arch/nds32/include/asm/config.h |1 +
arch/nds32/lib/bootm.c |6 +
configs/adp-ag101p_defconfig|5
include/configs/adp-ag101p.h|8 +--
8 files changed, 89 insertions(+), 5 deletions(-)
create mode 100644 arch/nds32/dts/Makefile
create mode 100644 arch/nds32/dts/ag101p.dts
diff --git a/arch/Kconfig b/arch/Kconfig
index 2528f50..1212635 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -43,6 +43,7 @@ config MIPS
config NDS32
bool "NDS32 architecture"
+ select SUPPORT_OF_CONTROL
config NIOS2
bool "Nios II architecture"
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index 99971fd..7992fd9 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -161,9 +161,13 @@ update_gp:
*/
call_board_init_f:
li $sp, CONFIG_SYS_INIT_SP_ADDR
- li $r10, GD_SIZE /* get GD size */
- sub $sp, $sp, $r10 /* GD start addr */
- move$r10, $sp
+ move$r0, $sp
+ bal board_init_f_alloc_reserve
+ move$sp, $r0
+ bal board_init_f_init_reserve
+#ifdef CONFIG_DEBUG_UART
+ bal debug_uart_init
+#endif
li $r0, 0x
#ifdef __PIC__
diff --git a/arch/nds32/dts/Makefile b/arch/nds32/dts/Makefile
new file mode 100644
index 000..2d8480b
--- /dev/null
+++ b/arch/nds32/dts/Makefile
@@ -0,0 +1,14 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts
new file mode 100644
index 000..2baa3dc
--- /dev/null
+++ b/arch/nds32/dts/ag101p.dts
@@ -0,0 +1,49 @@
+/dts-v1/;
+/ {
+ compatible = "nds32 ag101p";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ aliases {
+ uart0 = &serial0;
+ } ;
+
+ chosen {
+ /* bootargs = "console=ttyS0,38400n8
earlyprintk=uart8250-32bit,0x9960 debug bootmem_debug memblock=debug
loglevel=7"; */
+ bootargs = "console=ttyS0,38400n8
earlyprintk=uart8250-32bit,0x9960 debug loglevel=7";
+ stdout-path = "uart0:38400n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x 0x4000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "andestech,n13";
+ reg = <0>;
+ /* FIXME: to fill correct frqeuency */
+ clock-frequency = <6000>;
+ };
+ };
+
+ intc: interrupt-controller {
+ compatible = "andestech,atnointc010";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ serial0: serial@9960 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0x9960 0x1000>;
+ interrupts = <7 4>;
+ clock-frequency = <14745600>;
+ reg-shift = <2>;
+ no-loopback-test = <1>;
+ };
+
+};
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
index 054cc48..7289217 100644
--- a/arch/nds32/include/asm/config.h
+++ b/arch/nds32/include/asm/config.h
@@ -8,5 +8,6 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_LMB
#endif
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
index 8b0b28f..7999167 100644
--- a/arch/nds32/lib/bootm.c
+++ b/arch/nds32/lib/bootm.c
@@ -14,6 +14,12 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
+
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 48d08cc..2a7302f 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -1,5 +1,7 @@
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG101P=y
+CONFIG_DEFAULT_DEVICE_TREE="ag101p"
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="NDS32 # "
CONFIG_CMD_MMC=y
@@ -12,4 +14,7 @@ CONFIG_CMD_FAT=y
CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_BAUDRATE=38400
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index b42fcfa..106b591 100644
--- a/include/configs/adp-ag101p.h
[U-Boot] [PATCH 2/3] nds32: Support AG101P timer DM.
From: rick
Support AG101P timer device tree flow.
Signed-off-by: rick
---
arch/nds32/cpu/n1213/ag101/timer.c |3 +-
arch/nds32/dts/ag101p.dts |8 +++
configs/adp-ag101p_defconfig |2 +
drivers/timer/Kconfig |6 ++
drivers/timer/Makefile |1 +
drivers/timer/ag101p_timer.c | 122
6 files changed, 141 insertions(+), 1 deletion(-)
create mode 100644 drivers/timer/ag101p_timer.c
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c
b/arch/nds32/cpu/n1213/ag101/timer.c
index 758b354..0c03a10 100644
--- a/arch/nds32/cpu/n1213/ag101/timer.c
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -8,7 +8,7 @@
*
* SPDX-License-Identifier:GPL-2.0+
*/
-
+#ifndef CONFIG_TIMER
#include
#include
#include
@@ -189,3 +189,4 @@ ulong get_tbclk(void)
return CONFIG_SYS_CLK_FREQ;
#endif
}
+#endif /* CONFIG_TIMER */
diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts
index 2baa3dc..91314b5 100644
--- a/arch/nds32/dts/ag101p.dts
+++ b/arch/nds32/dts/ag101p.dts
@@ -13,6 +13,7 @@
/* bootargs = "console=ttyS0,38400n8
earlyprintk=uart8250-32bit,0x9960 debug bootmem_debug memblock=debug
loglevel=7"; */
bootargs = "console=ttyS0,38400n8
earlyprintk=uart8250-32bit,0x9960 debug loglevel=7";
stdout-path = "uart0:38400n8";
+ tick-timer = &timer0;
};
memory@0 {
@@ -46,4 +47,11 @@
no-loopback-test = <1>;
};
+ timer0: timer@9840 {
+ compatible = "andestech,attmr010";
+ reg = <0x9840 0x1000>;
+ interrupts = <19 4>;
+ clock-frequency = <1500>;
+ };
+
};
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 2a7302f..685a961 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -18,3 +18,5 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_AG101P_TIMER=y
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index e038523..356fa29 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -74,4 +74,10 @@ config ARC_TIMER
usually at least one of them exists. Either of them is supported
in U-Boot.
+config AG101P_TIMER
+ bool "Ag101p timer support"
+ depends on TIMER
+ help
+ Select this to enable a timer for Ag101p devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index bfe65fc..3dad956 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_AST_TIMER)+= ast_timer.o
obj-$(CONFIG_STI_TIMER)+= sti-timer.o
obj-$(CONFIG_ARC_TIMER)+= arc_timer.o
+obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
diff --git a/drivers/timer/ag101p_timer.c b/drivers/timer/ag101p_timer.c
new file mode 100644
index 000..163402f
--- /dev/null
+++ b/drivers/timer/ag101p_timer.c
@@ -0,0 +1,122 @@
+/*
+ * Andestech ATFTMR010 timer driver
+ *
+ * (C) Copyright 2016
+ * Rick Chen, NDS32 Software Engineering, r...@andestech.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Timer Control Register
+ */
+#define T3_UPDOWN (1 << 11)
+#define T2_UPDOWN (1 << 10)
+#define T1_UPDOWN (1 << 9)
+#define T3_OFENABLE(1 << 8)
+#define T3_CLOCK (1 << 7)
+#define T3_ENABLE (1 << 6)
+#define T2_OFENABLE(1 << 5)
+#define T2_CLOCK (1 << 4)
+#define T2_ENABLE (1 << 3)
+#define T1_OFENABLE(1 << 2)
+#define T1_CLOCK (1 << 1)
+#define T1_ENABLE (1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define T3_OVERFLOW(1 << 8)
+#define T3_MATCH2 (1 << 7)
+#define T3_MATCH1 (1 << 6)
+#define T2_OVERFLOW(1 << 5)
+#define T2_MATCH2 (1 << 4)
+#define T2_MATCH1 (1 << 3)
+#define T1_OVERFLOW(1 << 2)
+#define T1_MATCH2 (1 << 1)
+#define T1_MATCH1 (1 << 0)
+
+struct atftmr_timer_regs {
+ u32 t1_counter; /* 0x00 */
+ u32 t1_load;/* 0x04 */
+ u32 t1_match1; /* 0x08 */
+ u32 t1_match2; /* 0x0c */
+ u32 t2_counter; /* 0x10 */
+ u32 t2_load;/* 0x14 */
+ u32 t2_match1; /* 0x18 */
+ u32 t2_match2; /* 0x1c */
+ u32 t3_counter; /* 0x20 */
+ u32 t3_load;/* 0x24 */
+ u32 t3_match1; /* 0x28 */
+ u32 t3_match2; /* 0x2c */
+ u32 cr; /* 0x30 */
+ u32 int_state; /* 0x34 */
+ u32 int_mask; /* 0x38 */
+};
+
+struct atftmr_timer_platdata {
+
[U-Boot] [PATCH 3/3] nds32: Support AE3XX platform.
From: rick Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick --- arch/nds32/Kconfig |4 + arch/nds32/cpu/n1213/Makefile |1 + arch/nds32/cpu/n1213/ae3xx/Makefile| 18 ++ arch/nds32/cpu/n1213/ae3xx/cpu.c | 45 + arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S | 148 arch/nds32/cpu/n1213/ae3xx/timer.c | 16 ++ arch/nds32/cpu/n1213/ae3xx/watchdog.S | 17 ++ arch/nds32/cpu/n1213/ag101/Makefile|3 - arch/nds32/cpu/n1213/ag101/cpu.c |8 +- arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 59 +++ arch/nds32/cpu/n1213/start.S | 40 - arch/nds32/dts/Makefile|1 + arch/nds32/dts/ae3xx.dts | 65 +++ arch/nds32/include/asm/arch-ae3xx/ae3xx.h | 54 ++ arch/nds32/include/asm/bootm.h | 65 +++ arch/nds32/include/asm/cache.h | 23 ++- arch/nds32/include/asm/mach-types.h|1 + arch/nds32/lib/Makefile|1 + arch/nds32/lib/boot.c | 20 +++ arch/nds32/lib/bootm.c | 23 ++- arch/nds32/lib/cache.c | 197 + board/AndesTech/adp-ae3xx/Kconfig | 18 ++ board/AndesTech/adp-ae3xx/MAINTAINERS |6 + board/AndesTech/adp-ae3xx/Makefile |8 + board/AndesTech/adp-ae3xx/adp-ae3xx.c | 86 + board/AndesTech/adp-ag101p/adp-ag101p.c|9 +- configs/adp-ae3xx_defconfig| 25 +++ configs/adp-ag101p_defconfig |1 + drivers/timer/Kconfig | 12 +- drivers/timer/Makefile |1 + drivers/timer/ae3xx_timer.c| 117 + include/configs/adp-ae3xx.h| 260 include/configs/adp-ag101p.h | 27 ++- 33 files changed, 1265 insertions(+), 114 deletions(-) create mode 100644 arch/nds32/cpu/n1213/ae3xx/Makefile create mode 100644 arch/nds32/cpu/n1213/ae3xx/cpu.c create mode 100644 arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213/ae3xx/timer.c create mode 100644 arch/nds32/cpu/n1213/ae3xx/watchdog.S create mode 100644 arch/nds32/dts/ae3xx.dts create mode 100644 arch/nds32/include/asm/arch-ae3xx/ae3xx.h create mode 100644 arch/nds32/include/asm/bootm.h create mode 100644 arch/nds32/lib/boot.c create mode 100644 board/AndesTech/adp-ae3xx/Kconfig create mode 100644 board/AndesTech/adp-ae3xx/MAINTAINERS create mode 100644 board/AndesTech/adp-ae3xx/Makefile create mode 100644 board/AndesTech/adp-ae3xx/adp-ae3xx.c create mode 100644 configs/adp-ae3xx_defconfig create mode 100644 drivers/timer/ae3xx_timer.c create mode 100644 include/configs/adp-ae3xx.h diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index 4fcd01d..d72ff46 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -11,8 +11,12 @@ choice config TARGET_ADP_AG101P bool "Support adp-ag101p" +config TARGET_ADP_AE3XX + bool "Support adp-ae3xx" + endchoice source "board/AndesTech/adp-ag101p/Kconfig" +source "board/AndesTech/adp-ae3xx/Kconfig" endmenu diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile index 7d5ae96..3a9ada1 100644 --- a/arch/nds32/cpu/n1213/Makefile +++ b/arch/nds32/cpu/n1213/Makefile @@ -12,3 +12,4 @@ extra-y= start.o obj-$(if $(filter ag101,$(SOC)),y) += ag101/ +obj-$(if $(filter ae3xx,$(SOC)),y) += ae3xx/ diff --git a/arch/nds32/cpu/n1213/ae3xx/Makefile b/arch/nds32/cpu/n1213/ae3xx/Makefile new file mode 100644 index 000..07fa942 --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/Makefile @@ -0,0 +1,18 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation +# Macpaul Lin, Andes Technology Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cpu.o timer.o +obj-y += lowlevel_init.o + +ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG +obj-y += watchdog.o +endif diff --git a/arch/nds32/cpu/n1213/ae3xx/cpu.c b/arch/nds32/cpu/n1213/ae3xx/cpu.c new file mode 100644 index 000..26f878f --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/cpu.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +/* CPU specific code */ +#include +#include +#include +#include + +#include + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +
Re: [U-Boot] [PATCH v1 0/4] Add FIT support for falcon boot
Hi York, On 16/05/17 16:54, york sun wrote: > On 05/15/2017 10:42 PM, Lokesh Vutla wrote: >> + Andre >> >> >> On Monday 15 May 2017 09:31 PM, York Sun wrote: >>> This patch set adds FIT support for falcon boot. GZIP is enabled >>> to supported compressed image. >> >> Did you get a chance to look at Andre's "SPL: extend FIT loading >> support"[1] patch series? This series addresses similar problem in a >> more generic way. >> >> [1] >> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.mail-archive.com%2Fu-boot%40lists.denx.de%2Fmsg246692.html&data=01%7C01%7Cyork.sun%40nxp.com%7C63ec3a7e245445e2253d08d49c1e542b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=XrCyv6JBg02fwP7MEMo1hg8rVCOGnEQ741Hs0oLwZVg%3D&reserved=0 > > I only received partial patches from Andre's set. Looks like that set > should cover my changes by supporting multiple images. I was focusing on > a fast boot path for the past two months. I can rebase my patch once > Andre's set is merged. FYI: My patches have been merged into u-boot-sunxi/master[1], which is based on origin/master as of earlier this week. I take it they get merged into origin before -rc1, but meanwhile you could base on u-boot-sunxi/master. Cheers, Andre. [1] http://git.denx.de/?p=u-boot/u-boot-sunxi.git;a=shortlog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] regulator: pwm: Fix handling of missing init voltage
Since priv->init_voltage is an unsigned integer it can never be
negative. So the current code fails to detect a missing
'regulator-init-microvolt' property and instead misconfigures the
PWM device. Fix this by making the relevant members of
'struct pwm_regulator_info' signed integers.
Signed-off-by: Mark Kettenis
---
The current device tree for the Firefly-RK3399 does not have a
'regulator-init-microvolt' property for the 'vdd-log' regulator.
Without this fix U-Boot configures a voltage that is too low which
causes the Ethernet interface to drop almost all packets.
This is the same patch that I sent a couple of days ago, but was bounced
since I wasn't subscribed to the mailing list at that point. Funily enough
the message did make it into the mailing list archive. Resending to make
sure it does reach subscribers.
drivers/power/regulator/pwm_regulator.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/power/regulator/pwm_regulator.c
b/drivers/power/regulator/pwm_regulator.c
index a6c9fccd68..00a7cca7f7 100644
--- a/drivers/power/regulator/pwm_regulator.c
+++ b/drivers/power/regulator/pwm_regulator.c
@@ -32,13 +32,13 @@ struct pwm_regulator_info {
bool polarity;
struct udevice *pwm;
/* initialize voltage of regulator */
- unsigned int init_voltage;
+ int init_voltage;
/* the maximum voltage of regulator */
- unsigned int max_voltage;
+ int max_voltage;
/* the minimum voltage of regulator */
- unsigned int min_voltage;
+ int min_voltage;
/* the current voltage of regulator */
- unsigned int volt_uV;
+ int volt_uV;
};
static int pwm_regulator_enable(struct udevice *dev, bool enable)
--
2.13.0
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Re: [U-Boot] [PATCH v3 5/7] usb: host: ohci-generic: add CLOCK support
Hi Marek
On 05/18/2017 11:29 AM, Marek Vasut wrote:
> On 05/17/2017 03:34 PM, patrice.chot...@st.com wrote:
>> From: Patrice Chotard
>>
>> use list to save reference to enabled clocks in order to
>> disabled them in case of error during probe() or
>> during driver removal.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> v3: _ extract in this patch the CLOCK support add-on from previous patch 5
>> _ keep enabled clocks reference in list in order to
>>disable clocks in error path or in .remove callback
>>
>> v2: _ add error path management
>> _ add .remove callback
>>
>> drivers/usb/host/ohci-generic.c | 81
>> -
>> 1 file changed, 80 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/host/ohci-generic.c
>> b/drivers/usb/host/ohci-generic.c
>> index f3307f4..a6d89a8 100644
>> --- a/drivers/usb/host/ohci-generic.c
>> +++ b/drivers/usb/host/ohci-generic.c
>> @@ -5,6 +5,7 @@
>>*/
>>
>> #include
>> +#include
>> #include
>> #include "ohci.h"
>>
>> @@ -12,20 +13,98 @@
>> # error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
>> #endif
>>
>> +struct ohci_clock {
>> +struct clk *clk;
>> +struct list_head list;
>> +};
>> +
>> struct generic_ohci {
>> ohci_t ohci;
>> +struct list_head clks;
>> };
>>
>> +static int ohci_release_clocks(struct generic_ohci *priv)
>> +{
>> +struct ohci_clock *ohci_clock, *tmp;
>> +struct clk *clk;
>> +int ret;
>> +
>> +list_for_each_entry_safe(ohci_clock, tmp, &priv->clks, list) {
>> +clk = ohci_clock->clk;
>> +
>> +clk_request(clk->dev, clk);
>> +if (ret)
>> +return ret;
>> +
>> +clk_disable(clk);
>> +
>> +ret = clk_free(clk);
>> +if (ret)
>> +return ret;
>> +
>> +list_del(&ohci_clock->list);
>> +}
>> +return 0;
>> +}
>> +
>> static int ohci_usb_probe(struct udevice *dev)
>> {
>> struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev);
>> +struct generic_ohci *priv = dev_get_priv(dev);
>> +int i, ret;
>> +
>> +INIT_LIST_HEAD(&priv->clks);
>> +
>> +for (i = 0; ; i++) {
>> +struct ohci_clock *ohci_clock;
>> +struct clk *clk;
>> +
>> +clk = devm_kmalloc(dev, sizeof(*clk), GFP_KERNEL);
>
> Since you know how many entries the clock phandle has, you can allocate
> an array and drop this while list handling and this per-element kmalloc,
> which fragments the allocator pool.
I disagree, at this point we don't know how many entries the clock
phandle has.
But, following your idea to avoid allocator pool fragmentation, in order
to get the phandle number for array allocation, i can, for example add a
new fdt API :
int fdtdec_get_phandle_nb(const void *blob, int src_node,
const char *list_name,
const char *cells_name,
int cell_count,
int phandle_nb);
Then, with phandle_nb,, we 'll be able to allocate the right array size
for clocks and resets before populating them.
Thanks
Patrice
>
>> +if (!clk) {
>> +error("Can't allocate resource\n");
>> +goto clk_err;
>> +}
>> +
>> +ret = clk_get_by_index(dev, i, clk);
>> +if (ret < 0)
>> +break;
>> +
>> +if (clk_enable(clk)) {
>> +error("failed to enable ohci_clock %d\n", i);
>> +clk_free(clk);
>> +goto clk_err;
>> +}
>> +clk_free(clk);
>> +
>> +/*
>> + * add enabled clocks into clks list in order to be disabled
>> + * later on ohci_usb_remove() call or in error path if needed
>> + */
>> +ohci_clock = devm_kmalloc(dev, sizeof(*ohci_clock), GFP_KERNEL);
>
> Can't you just embed one structure into the other ?
>
>> +if (!ohci_clock) {
>> +error("Can't allocate resource\n");
>> +goto clk_err;
>> +}
>> +ohci_clock->clk = clk;
>> +list_add(&ohci_clock->list, &priv->clks);
>> +}
>>
>> return ohci_register(dev, regs);
>> +
>> +clk_err:
>> +return ohci_release_clocks(priv);
>> }
>>
>> static int ohci_usb_remove(struct udevice *dev)
>> {
>> -return ohci_deregister(dev);
>> +struct generic_ohci *priv = dev_get_priv(dev);
>> +int ret;
>> +
>> +ret = ohci_deregister(dev);
>> +if (ret)
>> +return ret;
>> +
>> +return ohci_release_clocks(priv);
>> }
>>
>> static const struct udevice_id ohci_usb_ids[] = {
>>
>
>
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Re: [U-Boot] [PATCH 1/3] usb: host: xhci-dwc3: Convert driver to DM
Hi Marek
On 05/19/2017 12:06 PM, Marek Vasut wrote:
> On 05/19/2017 09:15 AM, patrice.chot...@st.com wrote:
>> From: Patrice Chotard
>>
>> Add Driver Model support with use of generic DT
>> compatible string "snps,dwc3"
>>
>> Signed-off-by: Patrice Chotard
>> ---
>> drivers/usb/host/xhci-dwc3.c | 71
>>
>> 1 file changed, 71 insertions(+)
>>
>> diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
>> index 33961cd..b0b9076 100644
>> --- a/drivers/usb/host/xhci-dwc3.c
>> +++ b/drivers/usb/host/xhci-dwc3.c
>> @@ -9,9 +9,23 @@
>>*/
>>
>> #include
>> +#include
>> +#include
>> +
>> +#include "xhci.h"
>> #include
>> #include
>>
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct xhci_dwc3_platdata {
>> +phys_addr_t dwc3_regs;
>> +};
>
> Since you have DM, do you need this ?
Ah yes, effectively, i can remove that
>
>> +struct xhci_dwc3_priv {
>> +struct xhci_ctrl ctrl;
>> +};
>> +
>> void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
>> {
>> clrsetbits_le32(&dwc3_reg->g_ctl,
>> @@ -97,3 +111,60 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
>> setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
>> GFLADJ_30MHZ(val));
>> }
>> +
>> +static int xhci_dwc3_ofdata_to_platdata(struct udevice *dev)
>> +{
>> +struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
>> +u32 reg[2];
>> +
>> +/* get the dwc3 register space base address */
>> +if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "reg", reg,
>> + ARRAY_SIZE(reg))) {
>
> dev_get_addr() ?
Agree, i will fix it
Thanks
Patrice
>
>> +debug("dwc3 node has bad/missing 'reg' property\n");
>> +return -FDT_ERR_NOTFOUND;
>> +}
>> +plat->dwc3_regs = reg[0];
>> +
>> +return 0;
>> +}
>> +
>> +static int xhci_dwc3_probe(struct udevice *dev)
>> +{
>> +struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
>> +struct xhci_hcor *hcor;
>> +struct xhci_hccr *hccr;
>> +struct dwc3 *dwc3_reg;
>> +
>> +hccr = (struct xhci_hccr *)plat->dwc3_regs;
>> +hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
>> +HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
>> +
>> +dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
>> +
>> +dwc3_core_init(dwc3_reg);
>> +
>> +return xhci_register(dev, hccr, hcor);
>> +}
>> +
>> +static int xhci_dwc3_remove(struct udevice *dev)
>> +{
>> +return xhci_deregister(dev);
>> +}
>> +
>> +static const struct udevice_id xhci_dwc3_ids[] = {
>> +{ .compatible = "snps,dwc3" },
>> +{ }
>> +};
>> +
>> +U_BOOT_DRIVER(xhci_dwc3) = {
>> +.name = "xhci-dwc3",
>> +.id = UCLASS_USB,
>> +.of_match = xhci_dwc3_ids,
>> +.ofdata_to_platdata = xhci_dwc3_ofdata_to_platdata,
>> +.probe = xhci_dwc3_probe,
>> +.remove = xhci_dwc3_remove,
>> +.ops = &xhci_usb_ops,
>> +.priv_auto_alloc_size = sizeof(struct xhci_dwc3_priv),
>> +.platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
>> +.flags = DM_FLAG_ALLOC_PRIV_DMA,
>> +};
>>
>
>
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Re: [U-Boot] [PATCH v3 5/7] usb: host: ohci-generic: add CLOCK support
On 05/19/2017 01:27 PM, Patrice CHOTARD wrote:
> Hi Marek
>
> On 05/18/2017 11:29 AM, Marek Vasut wrote:
>> On 05/17/2017 03:34 PM, patrice.chot...@st.com wrote:
>>> From: Patrice Chotard
>>>
>>> use list to save reference to enabled clocks in order to
>>> disabled them in case of error during probe() or
>>> during driver removal.
>>>
>>> Signed-off-by: Patrice Chotard
>>> ---
>>>
>>> v3: _ extract in this patch the CLOCK support add-on from previous patch 5
>>> _ keep enabled clocks reference in list in order to
>>> disable clocks in error path or in .remove callback
>>>
>>> v2: _ add error path management
>>> _ add .remove callback
>>>
>>> drivers/usb/host/ohci-generic.c | 81
>>> -
>>> 1 file changed, 80 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/usb/host/ohci-generic.c
>>> b/drivers/usb/host/ohci-generic.c
>>> index f3307f4..a6d89a8 100644
>>> --- a/drivers/usb/host/ohci-generic.c
>>> +++ b/drivers/usb/host/ohci-generic.c
>>> @@ -5,6 +5,7 @@
>>>*/
>>>
>>> #include
>>> +#include
>>> #include
>>> #include "ohci.h"
>>>
>>> @@ -12,20 +13,98 @@
>>> # error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
>>> #endif
>>>
>>> +struct ohci_clock {
>>> + struct clk *clk;
>>> + struct list_head list;
>>> +};
>>> +
>>> struct generic_ohci {
>>> ohci_t ohci;
>>> + struct list_head clks;
>>> };
>>>
>>> +static int ohci_release_clocks(struct generic_ohci *priv)
>>> +{
>>> + struct ohci_clock *ohci_clock, *tmp;
>>> + struct clk *clk;
>>> + int ret;
>>> +
>>> + list_for_each_entry_safe(ohci_clock, tmp, &priv->clks, list) {
>>> + clk = ohci_clock->clk;
>>> +
>>> + clk_request(clk->dev, clk);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + clk_disable(clk);
>>> +
>>> + ret = clk_free(clk);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + list_del(&ohci_clock->list);
>>> + }
>>> + return 0;
>>> +}
>>> +
>>> static int ohci_usb_probe(struct udevice *dev)
>>> {
>>> struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev);
>>> + struct generic_ohci *priv = dev_get_priv(dev);
>>> + int i, ret;
>>> +
>>> + INIT_LIST_HEAD(&priv->clks);
>>> +
>>> + for (i = 0; ; i++) {
>>> + struct ohci_clock *ohci_clock;
>>> + struct clk *clk;
>>> +
>>> + clk = devm_kmalloc(dev, sizeof(*clk), GFP_KERNEL);
>>
>> Since you know how many entries the clock phandle has, you can allocate
>> an array and drop this while list handling and this per-element kmalloc,
>> which fragments the allocator pool.
>
> I disagree, at this point we don't know how many entries the clock
> phandle has.
I know you can do it in less then 2 mallocs, in fact in exactly 1 ,
which is already better.
> But, following your idea to avoid allocator pool fragmentation, in order
> to get the phandle number for array allocation, i can, for example add a
> new fdt API :
>
> int fdtdec_get_phandle_nb(const void *blob, int src_node,
> const char *list_name,
> const char *cells_name,
> int cell_count,
> int phandle_nb);
Uh, why ?
> Then, with phandle_nb,, we 'll be able to allocate the right array size
> for clocks and resets before populating them.
Just query the number of elements up front and then allocate the array ?
> Thanks
>
> Patrice
>
>>
>>> + if (!clk) {
>>> + error("Can't allocate resource\n");
>>> + goto clk_err;
>>> + }
>>> +
>>> + ret = clk_get_by_index(dev, i, clk);
>>> + if (ret < 0)
>>> + break;
>>> +
>>> + if (clk_enable(clk)) {
>>> + error("failed to enable ohci_clock %d\n", i);
>>> + clk_free(clk);
>>> + goto clk_err;
>>> + }
>>> + clk_free(clk);
>>> +
>>> + /*
>>> +* add enabled clocks into clks list in order to be disabled
>>> +* later on ohci_usb_remove() call or in error path if needed
>>> +*/
>>> + ohci_clock = devm_kmalloc(dev, sizeof(*ohci_clock), GFP_KERNEL);
>>
>> Can't you just embed one structure into the other ?
>>
>>> + if (!ohci_clock) {
>>> + error("Can't allocate resource\n");
>>> + goto clk_err;
>>> + }
>>> + ohci_clock->clk = clk;
>>> + list_add(&ohci_clock->list, &priv->clks);
>>> + }
>>>
>>> return ohci_register(dev, regs);
>>> +
>>> +clk_err:
>>> + return ohci_release_clocks(priv);
>>> }
>>>
>>> static int ohci_usb_remove(struct udevice *dev)
>>> {
>>> - return ohci_deregister(dev);
>>> + struct generic_ohci *priv = dev_get_priv(dev);
>>> + int ret;
>>> +
>>> + ret = ohci_deregister(dev);
Re: [U-Boot] [PATCH 3/3] usb: host: xhci-dwc3: Add generic PHY support
Hi Marek
On 05/19/2017 12:07 PM, Marek Vasut wrote:
> On 05/19/2017 09:15 AM, patrice.chot...@st.com wrote:
>> From: Patrice Chotard
>>
>> Add support of generic PHY framework support
>>
>> Signed-off-by: Patrice Chotard
>> ---
>> drivers/usb/host/xhci-dwc3.c | 29 +
>> 1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
>> index ea85834..70d3946 100644
>> --- a/drivers/usb/host/xhci-dwc3.c
>> +++ b/drivers/usb/host/xhci-dwc3.c
>> @@ -10,6 +10,8 @@
>>
>> #include
>> #include
>> +#include
>> +#include
>> #include
>>
>> #include "xhci.h"
>> @@ -20,6 +22,7 @@
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> struct xhci_dwc3_platdata {
>> +struct phy usb_phy;
>> phys_addr_t dwc3_regs;
>> };
>>
>> @@ -136,11 +139,26 @@ static int xhci_dwc3_probe(struct udevice *dev)
>> struct xhci_hccr *hccr;
>> struct dwc3 *dwc3_reg;
>> enum usb_dr_mode dr_mode;
>> +int ret;
>>
>> hccr = (struct xhci_hccr *)plat->dwc3_regs;
>> hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
>> HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
>>
>> +ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
>> +if (ret) {
>> +if (ret != -ENOENT) {
>> +error("Failed to get USB PHY for %s\n", dev->name);
>> +return ret;
>> +}
>> +} else {
>
> You can drop the else and indent here by reordering the condition.
I can't drop the "else", otherwise, in case there is no "phys" property
in DT (by example for arch/arm/dts/zynqmp.dtsi),
generic_phy_get_by_index() returns -ENOENT, we must continue without
calling generic_phy_init().
Patrice
>
> Otherwise OK.
>
>> +ret = generic_phy_init(&plat->usb_phy);
>> +if (ret) {
>> +error("Can't init USB PHY for %s\n", dev->name);
>> +return ret;
>> +}
>> +}
>> +
>> dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
>>
>> dwc3_core_init(dwc3_reg);
>> @@ -157,6 +175,17 @@ static int xhci_dwc3_probe(struct udevice *dev)
>>
>> static int xhci_dwc3_remove(struct udevice *dev)
>> {
>> +struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
>> +int ret;
>> +
>> +if (plat->usb_phy.dev) {
>> +ret = generic_phy_exit(&plat->usb_phy);
>> +if (ret) {
>> +error("Can't deinit USB PHY for %s\n", dev->name);
>> +return ret;
>> +}
>> +}
>> +
>> return xhci_deregister(dev);
>> }
>>
>>
>
>
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Re: [U-Boot] [PATCH v3 5/7] usb: host: ohci-generic: add CLOCK support
On 05/19/2017 01:51 PM, Marek Vasut wrote:
> On 05/19/2017 01:27 PM, Patrice CHOTARD wrote:
>> Hi Marek
>>
>> On 05/18/2017 11:29 AM, Marek Vasut wrote:
>>> On 05/17/2017 03:34 PM, patrice.chot...@st.com wrote:
From: Patrice Chotard
use list to save reference to enabled clocks in order to
disabled them in case of error during probe() or
during driver removal.
Signed-off-by: Patrice Chotard
---
v3:_ extract in this patch the CLOCK support add-on from previous
patch 5
_ keep enabled clocks reference in list in order to
disable clocks in error path or in .remove callback
v2:_ add error path management
_ add .remove callback
drivers/usb/host/ohci-generic.c | 81
-
1 file changed, 80 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/ohci-generic.c
b/drivers/usb/host/ohci-generic.c
index f3307f4..a6d89a8 100644
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include "ohci.h"
@@ -12,20 +13,98 @@
# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
#endif
+struct ohci_clock {
+ struct clk *clk;
+ struct list_head list;
+};
+
struct generic_ohci {
ohci_t ohci;
+ struct list_head clks;
};
+static int ohci_release_clocks(struct generic_ohci *priv)
+{
+ struct ohci_clock *ohci_clock, *tmp;
+ struct clk *clk;
+ int ret;
+
+ list_for_each_entry_safe(ohci_clock, tmp, &priv->clks, list) {
+ clk = ohci_clock->clk;
+
+ clk_request(clk->dev, clk);
+ if (ret)
+ return ret;
+
+ clk_disable(clk);
+
+ ret = clk_free(clk);
+ if (ret)
+ return ret;
+
+ list_del(&ohci_clock->list);
+ }
+ return 0;
+}
+
static int ohci_usb_probe(struct udevice *dev)
{
struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev);
+ struct generic_ohci *priv = dev_get_priv(dev);
+ int i, ret;
+
+ INIT_LIST_HEAD(&priv->clks);
+
+ for (i = 0; ; i++) {
+ struct ohci_clock *ohci_clock;
+ struct clk *clk;
+
+ clk = devm_kmalloc(dev, sizeof(*clk), GFP_KERNEL);
>>>
>>> Since you know how many entries the clock phandle has, you can allocate
>>> an array and drop this while list handling and this per-element kmalloc,
>>> which fragments the allocator pool.
>>
>> I disagree, at this point we don't know how many entries the clock
>> phandle has.
>
> I know you can do it in less then 2 mallocs, in fact in exactly 1 ,
> which is already better.
Can you elaborate ?
>
>> But, following your idea to avoid allocator pool fragmentation, in order
>> to get the phandle number for array allocation, i can, for example add a
>> new fdt API :
>>
>> int fdtdec_get_phandle_nb(const void *blob, int src_node,
>> const char *list_name,
>> const char *cells_name,
>> int cell_count,
>> int phandle_nb);
>
> Uh, why ?
>
>> Then, with phandle_nb,, we 'll be able to allocate the right array size
>> for clocks and resets before populating them.
>
> Just query the number of elements up front and then allocate the array ?
Can you indicate me with which API please ?
>
>> Thanks
>>
>> Patrice
>>
>>>
+ if (!clk) {
+ error("Can't allocate resource\n");
+ goto clk_err;
+ }
+
+ ret = clk_get_by_index(dev, i, clk);
+ if (ret < 0)
+ break;
+
+ if (clk_enable(clk)) {
+ error("failed to enable ohci_clock %d\n", i);
+ clk_free(clk);
+ goto clk_err;
+ }
+ clk_free(clk);
+
+ /*
+ * add enabled clocks into clks list in order to be disabled
+ * later on ohci_usb_remove() call or in error path if needed
+ */
+ ohci_clock = devm_kmalloc(dev, sizeof(*ohci_clock), GFP_KERNEL);
>>>
>>> Can't you just embed one structure into the other ?
>>>
+ if (!ohci_clock) {
+ error("Can't allocate resource\n");
+ goto clk_err;
+ }
+ ohci_clock->clk = clk;
+ list_add(&ohci_clock->list, &priv->clks);
+ }
return ohci_register(dev, regs);
+
+clk_err:
[U-Boot] [PATCH] mmc: sdhci-cadence: set timing mode register depending on frequency
The MMC framework in U-Boot does not support a systematic API for
timing switch like mmc_set_timing() in Linux.
U-Boot just provides a hook to change the clock frequency via
mmc_set_clock(). It is up to drivers if additional register
settings are needed.
This driver needs to set a correct timing mode into a register when
it migrates to a different speed mode. Only increasing clock frequency
could result in setup/hold timing violation.
The timing mode should be decided by checking MMC_TIMING_* like
drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not
supported by U-Boot for now. Just use mmc->clock to decide the
timing mode.
Signed-off-by: Masahiro Yamada
---
drivers/mmc/sdhci-cadence.c | 48 +
1 file changed, 48 insertions(+)
diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
index dc86d108a698..4e1c5f78a419 100644
--- a/drivers/mmc/sdhci-cadence.c
+++ b/drivers/mmc/sdhci-cadence.c
@@ -23,6 +23,18 @@
#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
+#define SDHCI_CDNS_HRS06 0x18/* eMMC control */
+#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
+#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8
+#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f
+#define SDHCI_CDNS_HRS06_MODE_MASK 0x7
+#define SDHCI_CDNS_HRS06_MODE_SD 0x0
+#define SDHCI_CDNS_HRS06_MODE_MMC_SDR0x2
+#define SDHCI_CDNS_HRS06_MODE_MMC_DDR0x3
+#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
+#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
+#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES0x6
+
/* SRS - Slot Register Set (SDHCI-compatible) */
#define SDHCI_CDNS_SRS_BASE0x200
@@ -111,6 +123,41 @@ static int sdhci_cdns_phy_init(struct sdhci_cdns_plat
*plat,
return 0;
}
+static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
+{
+ struct mmc *mmc = host->mmc;
+ struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);
+ unsigned int clock = mmc->clock;
+ u32 mode, tmp;
+
+ /*
+* REVISIT:
+* The mode should be decided by MMC_TIMING_* like Linux, but
+* U-Boot does not support timing. Use the clock frequency instead.
+*/
+ if (clock <= 2600)
+ mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
+ else if (clock <= 5200) {
+ if (mmc->ddr_mode)
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
+ else
+ mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
+ } else {
+ /* The IP supports HS200/HS400, but U-Boot does not. */
+ printf("unsupported frequency %d\n", clock);
+ return;
+ }
+
+ tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
+ tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK;
+ tmp |= mode;
+ writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
+}
+
+static const struct sdhci_ops sdhci_cdns_ops = {
+ .set_control_reg = sdhci_cdns_set_control_reg,
+};
+
static int sdhci_cdns_bind(struct udevice *dev)
{
struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
@@ -137,6 +184,7 @@ static int sdhci_cdns_probe(struct udevice *dev)
host->name = dev->name;
host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
+ host->ops = &sdhci_cdns_ops;
host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev->of_offset);
--
2.7.4
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Re: [U-Boot] litesom.c: Board stuff in SOC ?
On Fri, May 19, 2017 at 12:51:18PM +0200, Stefano Babic wrote: > Hi Marcin, > > On 19/05/2017 12:41, Marcin Niestroj wrote: > > Hi Stefano, > > > > I've added Tom to the discussion. > > Of course ! > > > So if we make some changes to SOM > > code position in u-boot tree, let's make sure we do it for all > > architectures the same > > We have already not done in this way. We have all boards / SOM code > inside bords/, the only exceptions are yours. If there is a decision to > add an abstraction for SOM, we have to put coherently all SOMs that are > now stored in the boards directory. > > What you mention are just exception - that I would like to clean up. So, we do have a problem with the layout today. The point of SOMs is that yes, you can drop them into a carrier from the same vendor (and this is true for both "3rd party" ones like litesom/chilisom/solidrun/etc and vendor ones like more recent NXP eval boards) or company X buys the SOMs and puts them in their own custom carrier (which hell, we have customers that do). In the latter case, it doesn't make sense for company X to put their board in boards/SOM-vendor/. In my mind, arch/arm/mach-omap2/am33xx/chilisom.c is the right solution and the big problem with i.MX right now is that arch/arm/imx-common and arch/arm/cpu/armv7/mx* need to get some re-organization under arch/arm/mach-imx/. And I'm not going to claim that arch/arm/mach-omap2 is best organized here, I largely moved the old omap-common to mach-omap2 and everything else into subdirs of that. I can certainly see an argument for arch/arm/mach-$X/som/ (or mach-$X/$soc/som/) instead of just putting them in arch/arm/mach-$X/ (or again, mach-$X/$soc/). Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] drivers: net: fsl-mc: Link MC boot to PHY_RESET_R
DPAA2 platforms boot the Management Complex based on the u-boot env
variable "mcinitcmd". Instead of doing this step on each platform
individually, define a single mc_env_boot function in the MC driver,
since it's semantically tied to it.
Call the function in a per-board reset_phy hook, as it gets called at a
later moment, when all board PHY devices have been initialized.
Signed-off-by: Bogdan Purcareata
Signed-off-by: Heinz Wrobel
---
v1 -> v2:
- keep the reset_phy implementation on each board; some boards might
want to do something else besides booting the MC.
board/freescale/ls2080aqds/eth.c | 13 ++---
board/freescale/ls2080ardb/eth_ls2080rdb.c | 14 --
drivers/net/fsl-mc/mc.c| 16
include/configs/ls2080a_common.h | 5 +
include/fsl-mc/fsl_mc.h| 1 +
5 files changed, 36 insertions(+), 13 deletions(-)
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 59361e9..7083224 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -834,7 +834,6 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
int board_eth_init(bd_t *bis)
{
int error;
- char *mc_boot_env_var;
#ifdef CONFIG_FSL_MC_ENET
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@@ -902,9 +901,6 @@ int board_eth_init(bd_t *bis)
}
}
- mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
- if (mc_boot_env_var)
- run_command_list(mc_boot_env_var, -1, 0);
error = cpu_eth_init(bis);
if (hwconfig_f("xqsgmii", env_hwconfig)) {
@@ -919,6 +915,9 @@ int board_eth_init(bd_t *bis)
return error;
}
-#ifdef CONFIG_FSL_MC_ENET
-
-#endif
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+ mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c
b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index ba584c8..d6ea76a 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -20,11 +20,9 @@
DECLARE_GLOBAL_DATA_PTR;
-#define MC_BOOT_ENV_VAR "mcinitcmd"
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
- char *mc_boot_env_var;
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
@@ -98,11 +96,8 @@ int board_eth_init(bd_t *bis)
}
}
- mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
- if (mc_boot_env_var)
- run_command_list(mc_boot_env_var, -1, 0);
cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
+#endif /* CONFIG_FSL_MC_ENET */
#ifdef CONFIG_PHY_AQUANTIA
/*
@@ -118,3 +113,10 @@ int board_eth_init(bd_t *bis)
#endif
return pci_eth_init(bis);
}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+ mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 9f69d75..543d08a 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -26,6 +26,7 @@
#define MC_MEM_SIZE_ENV_VAR"mcmemsize"
#define MC_BOOT_TIMEOUT_ENV_VAR"mcboottimeout"
+#define MC_BOOT_ENV_VAR"mcinitcmd"
DECLARE_GLOBAL_DATA_PTR;
static int mc_boot_status = -1;
@@ -1362,3 +1363,18 @@ U_BOOT_CMD(
"fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n"
"fsl_mc start aiop [FW_addr] - Start AIOP\n"
);
+
+void mc_env_boot(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ char *mc_boot_env_var;
+ /* The MC may only be initialized in the reset PHY function
+* because otherwise U-Boot has not yet set up all the MAC
+* address info properly. Without MAC addresses, the MC code
+* can not properly initialize the DPC.
+*/
+ mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+ if (mc_boot_env_var)
+ run_command_list(mc_boot_env_var, -1, 0);
+#endif /* CONFIG_FSL_MC_ENET */
+}
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 427f623..266ef02 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -149,6 +149,11 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x20
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x0700
+/* Define phy_reset function to boot the MC based on mcinitcmd.
+ * This happens late enough to properly fixup u-boot env MAC addresses.
+ */
+#define CONFIG_RESET_PHY_R
+
/*
* Carve out a DDR region which will not be used by u-boot/Linux
*
diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index ffe6da5..60088ec 100644
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h
@@ -61,4 +61,5 @@ u64 mc_get_dram_addr(void);
unsigned long mc_get_dram_block_size(void);
int fsl_mc_ldpaa_init(b
[U-Boot] [PATCH v2 2/2] drivers: net: fsl-mc: Include MAC addr fixup to DPL
Previous to MC v10.x, port mac address was specified via DPL. Since
newer MC versions are compatible with old style DPLs, make the u-boot
env mac addresses visible there. This applies only to DPLs that have an
older version.
DPLs use 32 bit values for specifying MAC addresses. U-boot environment
variables take precedence over the MAC addresses already visible in the
DPL/DPC.
Signed-off-by: Bogdan Purcareata
Signed-off-by: Heinz Wrobel
---
v1 -> v2:
- initialize variables to fix compiler warnings
- remove prints
drivers/net/fsl-mc/mc.c | 258
1 file changed, 195 insertions(+), 63 deletions(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 543d08a..727f24a 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -155,19 +155,142 @@ int parse_mc_firmware_fit_image(u64 mc_fw_addr,
}
#endif
-static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id,
- struct eth_device *eth_dev)
+#define MC_DT_INCREASE_SIZE64
+
+enum mc_fixup_type {
+ MC_FIXUP_DPL,
+ MC_FIXUP_DPC
+};
+
+static int mc_fixup_mac_addr(void *blob, int nodeoffset,
+const char *propname, struct eth_device *eth_dev,
+enum mc_fixup_type type)
{
- int nodeoffset, err = 0;
+ int err = 0, len = 0, size, i;
+ unsigned char env_enetaddr[ARP_HLEN];
+ unsigned int enetaddr_32[ARP_HLEN];
+ void *val = NULL;
+
+ switch (type) {
+ case MC_FIXUP_DPL:
+ /* DPL likes its addresses on 32 * ARP_HLEN bits */
+ for (i = 0; i < ARP_HLEN; i++)
+ enetaddr_32[i] = cpu_to_fdt32(eth_dev->enetaddr[i]);
+ val = enetaddr_32;
+ len = sizeof(enetaddr_32);
+ break;
+
+ case MC_FIXUP_DPC:
+ val = eth_dev->enetaddr;
+ len = ARP_HLEN;
+ break;
+ }
+
+ /* MAC address property present */
+ if (fdt_get_property(blob, nodeoffset, propname, NULL)) {
+ /* u-boot MAC addr randomly assigned - leave the present one */
+ if (!eth_getenv_enetaddr_by_index("eth", eth_dev->index,
+ env_enetaddr))
+ return err;
+ } else {
+ size = MC_DT_INCREASE_SIZE + strlen(propname) + len;
+ /* make room for mac address property */
+ err = fdt_increase_size(blob, size);
+ if (err) {
+ printf("fdt_increase_size: err=%s\n",
+ fdt_strerror(err));
+ return err;
+ }
+ }
+
+ err = fdt_setprop(blob, nodeoffset, propname, val, len);
+ if (err) {
+ printf("fdt_setprop: err=%s\n", fdt_strerror(err));
+ return err;
+ }
+
+ return err;
+}
+
+#define is_dpni(s) (s != NULL ? !strncmp(s, "dpni@", 5) : 0)
+
+const char *dpl_get_connection_endpoint(void *blob, char *endpoint)
+{
+ int connoffset = fdt_path_offset(blob, "/connections"), off;
+ const char *s1, *s2;
+
+ for (off = fdt_first_subnode(blob, connoffset);
+off >= 0;
+off = fdt_next_subnode(blob, off)) {
+ s1 = fdt_stringlist_get(blob, off, "endpoint1", 0, NULL);
+ s2 = fdt_stringlist_get(blob, off, "endpoint2", 0, NULL);
+
+ if (!s1 || !s2)
+ continue;
+
+ if (strcmp(endpoint, s1) == 0)
+ return s2;
+
+ if (strcmp(endpoint, s2) == 0)
+ return s1;
+ }
+
+ return NULL;
+}
+
+static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
+struct eth_device *eth_dev)
+{
+ int objoff = fdt_path_offset(blob, "/objects");
+ int dpmacoff = -1, dpnioff = -1;
+ const char *endpoint;
char mac_name[10];
- const char link_type_mode[] = "FIXED_LINK";
- unsigned char env_enetaddr[6];
+ int err;
+
+ sprintf(mac_name, "dpmac@%d", dpmac_id);
+ dpmacoff = fdt_subnode_offset(blob, objoff, mac_name);
+ if (dpmacoff < 0)
+ /* dpmac not defined in DPL, so skip it. */
+ return 0;
+
+ err = mc_fixup_mac_addr(blob, dpmacoff, "mac_addr", eth_dev,
+ MC_FIXUP_DPL);
+ if (err) {
+ printf("Error fixing up dpmac mac_addr in DPL\n");
+ return err;
+ }
+
+ /* now we need to figure out if there is any
+* DPNI connected to this MAC, so we walk the
+* connection list
+*/
+ endpoint = dpl_get_connection_endpoint(blob, mac_name);
+ if (!is_dpni(endpoint))
+ return 0;
+
+ /* let's see if we can fixup the DPNI as well */
+ dpnioff = fdt_subnode_offset(blob, objoff, endpoint);
+ if (dpnioff < 0)
+ /* DPNI not defined in DPL in the obj
Re: [U-Boot] litesom.c: Board stuff in SOC ?
Hi Tom, On 19/05/2017 15:39, Tom Rini wrote: > On Fri, May 19, 2017 at 12:51:18PM +0200, Stefano Babic wrote: >> Hi Marcin, >> >> On 19/05/2017 12:41, Marcin Niestroj wrote: >>> Hi Stefano, >>> >>> I've added Tom to the discussion. >> >> Of course ! >> >>> So if we make some changes to SOM >>> code position in u-boot tree, let's make sure we do it for all >>> architectures the same >> >> We have already not done in this way. We have all boards / SOM code >> inside bords/, the only exceptions are yours. If there is a decision to >> add an abstraction for SOM, we have to put coherently all SOMs that are >> now stored in the boards directory. >> >> What you mention are just exception - that I would like to clean up. > > So, we do have a problem with the layout today. Indeed, true. There is not an abstraction for SOM today. > The point of SOMs is > that yes, you can drop them into a carrier from the same vendor (and > this is true for both "3rd party" ones like > litesom/chilisom/solidrun/etc and vendor ones like more recent NXP eval > boards) or company X buys the SOMs and puts them in their own custom > carrier (which hell, we have customers that do). Right, this is the common case. > In the latter case, it > doesn't make sense for company X to put their board in > boards/SOM-vendor/. The question is how they reference to the common / SOM code. I am quite sure that the object should be part of the board library, that is at the end part of board///lib.a. > > In my mind, arch/arm/mach-omap2/am33xx/chilisom.c is the right solution > and the big problem with i.MX right now is that arch/arm/imx-common and > arch/arm/cpu/armv7/mx* need to get some re-organization under > arch/arm/mach-imx/. Sure the SOM code should be not under cpu/mx6. This is wrong. imx-common was created (as far as I can still remember) as solution to put code shared between all i.MX processors, from imx.2x up to i.MX6 or i.MX7. Code that does not belong to a single SOC. As far as I see, there is not a single solution for SOM in u-boot. In some cases (what you mention) are in mach-*, in some other cases they are under board/. Just check the number of "common" directories under boards. In most cases they are SOM, and I am sure I am still missing a lot of them. > And I'm not going to claim that arch/arm/mach-omap2 > is best organized here, I largely moved the old omap-common to > mach-omap2 and everything else into subdirs of that. Nevertheless, this is a much more sustainable solution. If imx-common is changed into mach-imx, and it contains subdirectories for the specific type, we could simplify imx-common/Makefile, that is become messy with two many filters in a way as in mach-omap2. And then, moving litesom.c in a place as arch/arm/mach-imx/som/mx6 seems much more appropriate. > I can certainly > see an argument for arch/arm/mach-$X/som/ (or mach-$X/$soc/som/) instead > of just putting them in arch/arm/mach-$X/ (or again, mach-$X/$soc/). mach-$X/$soc/som/ is my preferred choice if we vote.. :-) Best regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 01/26] dm: video: Sync display on backspace
We should sync the display (e.g. flush cache) when backspace is pressed to ensure that the character is erased correctly. Signed-off-by: Simon Glass --- drivers/video/vidconsole-uclass.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index e9a90b1b9b..b5afd72227 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -77,6 +77,7 @@ static int vidconsole_back(struct udevice *dev) if (priv->ycur < 0) priv->ycur = 0; } + video_sync(dev->parent); return 0; } -- 2.13.0.303.g4ebf302169-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 03/26] video: simple-panel: Add a little more debugging
Add some debugging to show when the backlight is enabled.
Signed-off-by: Simon Glass
---
drivers/video/simple_panel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index baa95f6a12..c0ce199c6a 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -25,8 +25,10 @@ static int simple_panel_enable_backlight(struct udevice *dev)
struct simple_panel_priv *priv = dev_get_priv(dev);
int ret;
+ debug("%s: start, backlight = '%s'\n", __func__, priv->backlight->name);
dm_gpio_set_value(&priv->enable, 1);
ret = backlight_enable(priv->backlight);
+ debug("%s: done, ret = %d\n", __func__, ret);
if (ret)
return ret;
--
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[U-Boot] [PATCH 02/26] dm: video: Update pwm_backlight to support livetree
Update this driver to support a live device tree.
Signed-off-by: Simon Glass
---
drivers/video/pwm_backlight.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index 3697f4905c..359f8fa186 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -28,11 +28,13 @@ struct pwm_backlight_priv {
static int pwm_backlight_enable(struct udevice *dev)
{
struct pwm_backlight_priv *priv = dev_get_priv(dev);
+ struct dm_regulator_uclass_platdata *plat;
uint duty_cycle;
int ret;
- debug("%s: Enable '%s', regulator '%s'\n", __func__, dev->name,
- priv->reg->name);
+ plat = dev_get_uclass_platdata(priv->reg);
+ debug("%s: Enable '%s', regulator '%s'/'%s'\n", __func__, dev->name,
+ priv->reg->name, plat->name);
ret = regulator_set_enable(priv->reg, true);
if (ret) {
debug("%s: Cannot enable regulator for PWM '%s'\n", __func__,
@@ -59,12 +61,11 @@ static int pwm_backlight_enable(struct udevice *dev)
static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
{
struct pwm_backlight_priv *priv = dev_get_priv(dev);
- struct fdtdec_phandle_args args;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
+ struct ofnode_phandle_args args;
int index, ret, count, len;
const u32 *cell;
+ debug("%s: start\n", __func__);
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret) {
@@ -79,14 +80,15 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice
*dev)
if (ret != -ENOENT)
return ret;
}
- ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
-0, 0, &args);
+ ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0,
+ &args);
if (ret) {
debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
return ret;
}
- ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
+ ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node,
+ &priv->pwm);
if (ret) {
debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
return ret;
@@ -94,8 +96,8 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice
*dev)
priv->channel = args.args[0];
priv->period_ns = args.args[1];
- index = fdtdec_get_int(blob, node, "default-brightness-level", 255);
- cell = fdt_getprop(blob, node, "brightness-levels", &len);
+ index = dev_read_u32_default(dev, "default-brightness-level", 255);
+ cell = dev_read_prop(dev, "brightness-levels", &len);
count = len / sizeof(u32);
if (cell && count > index) {
priv->default_level = fdt32_to_cpu(cell[index]);
@@ -104,6 +106,7 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice
*dev)
priv->default_level = index;
priv->max_level = 255;
}
+ debug("%s: done\n", __func__);
return 0;
--
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[U-Boot] [PATCH 08/26] dm: tegra: Convert clock_decode_periph_id() to support livetree
Adjust this to take a device as a parameter instead of a node.
Signed-off-by: Simon Glass
---
arch/arm/include/asm/arch-tegra/clock.h | 2 +-
arch/arm/mach-tegra/clock.c | 5 ++---
drivers/spi/tegra114_spi.c | 2 +-
drivers/spi/tegra20_sflash.c| 2 +-
drivers/spi/tegra20_slink.c | 2 +-
drivers/spi/tegra210_qspi.c | 2 +-
drivers/usb/host/ehci-tegra.c | 2 +-
7 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index 388afcb723..301de4a899 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -266,7 +266,7 @@ void clock_ll_start_uart(enum periph_id periph_id);
* @param node Node to look at
* @return peripheral ID, or PERIPH_ID_NONE if none
*/
-enum periph_id clock_decode_periph_id(const void *blob, int node);
+int clock_decode_periph_id(struct udevice *dev);
/**
* Checks if the oscillator bypass is enabled (XOBP bit)
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index f547942022..090dba629c 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -652,14 +652,13 @@ void clock_ll_start_uart(enum periph_id periph_id)
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-int clock_decode_periph_id(const void *blob, int node)
+int clock_decode_periph_id(struct udevice *dev)
{
enum periph_id id;
u32 cell[2];
int err;
- err = fdtdec_get_int_array(blob, node, "clocks", cell,
- ARRAY_SIZE(cell));
+ err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
if (err)
return -1;
id = clk_id_to_periph_id(cell[1]);
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 802117eb49..86b1019585 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -104,7 +104,7 @@ static int tegra114_spi_ofdata_to_platdata(struct udevice
*bus)
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 299e1b44fa..e70210d7ab 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -91,7 +91,7 @@ static int tegra20_sflash_ofdata_to_platdata(struct udevice
*bus)
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 4cbde7b22f..f242574760 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -97,7 +97,7 @@ static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index 6d0b5da261..2a35a583f5 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -100,7 +100,7 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice
*bus)
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 7dc37f045d..873bf8ecfd 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -723,7 +723,7 @@ static int fdt_decode_usb(struct udevice *dev, struct
fdt_usb *config)
config->enabled = fdtdec_get_is_enabled(blob, node);
config->has_legacy_mode = fdtdec_get_bool(blob, node,
"nvidia,has-legacy-mode");
- config->periph_id = clock_decode_periph_id(blob, node);
+ config->periph_id = clock_decode_periph_id(dev);
if (config->periph_id == PERIPH_ID_NONE) {
debug("%s: Missing/invalid peripheral ID\n", __func__);
return -EINVAL;
--
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[U-Boot] [PATCH 10/26] tegra: dts: Move stdout-path to /chosen
This property should be in the /chosen node, not /aliases.
Signed-off-by: Simon Glass
---
arch/arm/dts/tegra124-nyan-big.dts | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/tegra124-nyan-big.dts
b/arch/arm/dts/tegra124-nyan-big.dts
index 62f89d0f1a..f1c97052a8 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -8,7 +8,6 @@
aliases {
console = &uarta;
- stdout-path = &uarta;
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
@@ -26,6 +25,10 @@
usb2 = "/usb@7d004000";
};
+ chosen {
+ stdout-path = &uarta;
+ };
+
host1x@5000 {
dc@5420 {
display-timings {
--
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[U-Boot] [PATCH 12/26] dm: tegra: gpio: Convert to support livetree
Update the GPIO driver to support a live device tree.
Signed-off-by: Simon Glass
---
drivers/gpio/tegra_gpio.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index 687cd74fee..4965583158 100644
--- a/drivers/gpio/tegra_gpio.c
+++ b/drivers/gpio/tegra_gpio.c
@@ -337,11 +337,13 @@ static int gpio_tegra_bind(struct udevice *parent)
* This driver does not make use of interrupts, other than to figure
* out the number of GPIO banks
*/
- if (!fdt_getprop(gd->fdt_blob, dev_of_offset(parent), "interrupts",
-&len))
- return -EINVAL;
+ len = dev_read_size(parent, "interrupts");
+ if (len < 0)
+ return len;
bank_count = len / 3 / sizeof(u32);
- ctlr = (struct gpio_ctlr *)devfdt_get_addr(parent);
+ ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
+ if ((ulong)ctlr == FDT_ADDR_T_NONE)
+ return -EINVAL;
}
#endif
for (bank = 0; bank < bank_count; bank++) {
--
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[U-Boot] [PATCH 13/26] dm: tegra: usb: Convert to livetree
Update the Tegra EHCI driver to support a live device tree.
Signed-off-by: Simon Glass
---
drivers/usb/host/ehci-tegra.c | 34 ++
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 873bf8ecfd..1c72330b0c 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -17,7 +17,6 @@
#include
#include
#include
-#include
#include "ehci.h"
@@ -695,12 +694,11 @@ static void config_clock(const u32 timing[])
static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
{
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
const char *phy, *mode;
- config->reg = (struct usb_ctlr *)devfdt_get_addr(dev);
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ config->reg = (struct usb_ctlr *)dev_read_addr(dev);
+ debug("reg=%p\n", config->reg);
+ mode = dev_read_string(dev, "dr_mode");
if (mode) {
if (0 == strcmp(mode, "host"))
config->dr_mode = DR_MODE_HOST;
@@ -717,28 +715,24 @@ static int fdt_decode_usb(struct udevice *dev, struct
fdt_usb *config)
config->dr_mode = DR_MODE_HOST;
}
- phy = fdt_getprop(blob, node, "phy_type", NULL);
+ phy = dev_read_string(dev, "phy_type");
config->utmi = phy && 0 == strcmp("utmi", phy);
config->ulpi = phy && 0 == strcmp("ulpi", phy);
- config->enabled = fdtdec_get_is_enabled(blob, node);
- config->has_legacy_mode = fdtdec_get_bool(blob, node,
- "nvidia,has-legacy-mode");
+ config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode");
config->periph_id = clock_decode_periph_id(dev);
if (config->periph_id == PERIPH_ID_NONE) {
debug("%s: Missing/invalid peripheral ID\n", __func__);
return -EINVAL;
}
- gpio_request_by_name_nodev(offset_to_ofnode(node), "nvidia,vbus-gpio",
- 0, &config->vbus_gpio, GPIOD_IS_OUT);
- gpio_request_by_name_nodev(offset_to_ofnode(node),
- "nvidia,phy-reset-gpio", 0,
- &config->phy_reset_gpio, GPIOD_IS_OUT);
- debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
- "vbus=%d, phy_reset=%d, dr_mode=%d\n",
- config->enabled, config->has_legacy_mode, config->utmi,
- config->ulpi, config->periph_id,
- gpio_get_number(&config->vbus_gpio),
- gpio_get_number(&config->phy_reset_gpio), config->dr_mode);
+ gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio,
+GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0,
+&config->phy_reset_gpio, GPIOD_IS_OUT);
+ debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d,
phy_reset=%d, dr_mode=%d, reg=%p\n",
+ config->has_legacy_mode, config->utmi, config->ulpi,
+ config->periph_id, gpio_get_number(&config->vbus_gpio),
+ gpio_get_number(&config->phy_reset_gpio), config->dr_mode,
+ config->reg);
return 0;
}
--
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[U-Boot] [PATCH 23/26] dm: serial: Add livetree support
Add support for a live device tree to the core serial uclass.
Signed-off-by: Simon Glass
---
drivers/serial/serial-uclass.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index ede5c2c0be..976b99ce7c 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -81,9 +82,20 @@ static void serial_find_console_or_panic(void)
return;
}
} else if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
- if (!serial_check_stdout(blob, &dev)) {
- gd->cur_serial_dev = dev;
- return;
+ /* Live tree has support for stdout */
+ if (of_live_active()) {
+ struct device_node *np = of_get_stdout();
+
+ if (np && !uclass_get_device_by_ofnode(UCLASS_SERIAL,
+ np_to_ofnode(np), &dev)) {
+ gd->cur_serial_dev = dev;
+ return;
+ }
+ } else {
+ if (!serial_check_stdout(blob, &dev)) {
+ gd->cur_serial_dev = dev;
+ return;
+ }
}
}
if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) {
--
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[U-Boot] [PATCH 19/26] power: Add a GPIO driver for the as3722 PMIC
This pmic includes GPIOs which should have their own driver. Add
a driver to support these.
Signed-off-by: Simon Glass
---
drivers/power/pmic/as3722_gpio.c | 120 +++
include/power/as3722.h | 5 ++
2 files changed, 125 insertions(+)
create mode 100644 drivers/power/pmic/as3722_gpio.c
diff --git a/drivers/power/pmic/as3722_gpio.c b/drivers/power/pmic/as3722_gpio.c
new file mode 100644
index 00..d0b681ca4a
--- /dev/null
+++ b/drivers/power/pmic/as3722_gpio.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NUM_GPIOS 8
+
+int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
+ unsigned long flags)
+{
+ u8 value = 0;
+ int err;
+
+ if (flags & AS3722_GPIO_OUTPUT_VDDH)
+ value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+ if (flags & AS3722_GPIO_INVERT)
+ value |= AS3722_GPIO_CONTROL_INVERT;
+
+ err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+ if (err) {
+ error("failed to configure GPIO#%u: %d", gpio, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int as3722_gpio_set_value(struct udevice *dev, unsigned int gpio,
+int level)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ const char *l;
+ u8 value;
+ int err;
+
+ if (gpio >= NUM_GPIOS)
+ return -EINVAL;
+
+ err = pmic_reg_read(pmic, AS3722_GPIO_SIGNAL_OUT);
+ if (err < 0) {
+ error("failed to read GPIO signal out register: %d", err);
+ return err;
+ }
+ value = err;
+
+ if (level == 0) {
+ value &= ~(1 << gpio);
+ l = "low";
+ } else {
+ value |= 1 << gpio;
+ l = "high";
+ }
+
+ err = pmic_reg_write(pmic, AS3722_GPIO_SIGNAL_OUT, value);
+ if (err) {
+ error("failed to set GPIO#%u %s: %d", gpio, l, err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_gpio_direction_output(struct udevice *dev, unsigned int gpio,
+int value)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int err;
+
+ if (gpio > 7)
+ return -EINVAL;
+
+ if (value == 0)
+ value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL;
+ else
+ value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+ err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+ if (err) {
+ error("failed to configure GPIO#%u as output: %d", gpio, err);
+ return err;
+ }
+
+ err = as3722_gpio_set_value(pmic, gpio, value);
+ if (err < 0) {
+ error("failed to set GPIO#%u high: %d", gpio, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int as3722_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = NUM_GPIOS;
+ uc_priv->bank_name = "as3722_";
+
+ return 0;
+}
+
+static const struct dm_gpio_ops gpio_as3722_ops = {
+ .direction_output = as3722_gpio_direction_output,
+ .set_value = as3722_gpio_set_value,
+};
+
+U_BOOT_DRIVER(gpio_as3722) = {
+ .name = "gpio_as3722",
+ .id = UCLASS_GPIO,
+ .ops= &gpio_as3722_ops,
+ .probe = as3722_gpio_probe,
+};
diff --git a/include/power/as3722.h b/include/power/as3722.h
index 14afa0c81a..713e79840f 100644
--- a/include/power/as3722.h
+++ b/include/power/as3722.h
@@ -20,6 +20,11 @@
#define AS3722_ASIC_ID1 0x90
#define AS3722_ASIC_ID2 0x91
+#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
+#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
+
struct udevice;
int as3722_init(struct udevice **devp);
--
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[U-Boot] [PATCH 26/26] dm: tegra: nyan-big: Move to livetree
Change this board to use a live device tree after relocation. Signed-off-by: Simon Glass --- configs/nyan-big_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index a152ff6915..82be85a834 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_LIVE=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y -- 2.13.0.303.g4ebf302169-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 15/26] dm: tegra: i2c: Convert to livetree
Update the tegra i2c driver to support a live device tree.
Signed-off-by: Simon Glass
---
drivers/i2c/tegra_i2c.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 055f48153a..4163d798d5 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -365,7 +365,11 @@ static int tegra_i2c_probe(struct udevice *dev)
i2c_bus->id = dev->seq;
i2c_bus->type = dev_get_driver_data(dev);
- i2c_bus->regs = (struct i2c_ctlr *)devfdt_get_addr(dev);
+ i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
+ if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot get regs address\n", __func__);
+ return -EINVAL;
+ }
ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
if (ret) {
--
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[U-Boot] [PATCH 24/26] tegra: Show a debug message if the LCD PMIC fails to start
This error condition should have a debug() message. Add it.
Signed-off-by: Simon Glass
---
arch/arm/mach-tegra/board2.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 0291c7fb33..e0a39e1a32 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -150,8 +150,10 @@ int board_init(void)
#if defined(CONFIG_DM_VIDEO)
board_id = tegra_board_id();
err = tegra_lcd_pmic_init(board_id);
- if (err)
+ if (err) {
+ debug("Failed to set up LCD PMIC\n");
return err;
+ }
#endif
#ifdef CONFIG_TEGRA_NAND
--
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[U-Boot] [PATCH 00/26] dm: tegra: Move nyan-big to livetree
This moves an entire board to use a live device tree as an example of the impact. Nyan-big was chosen because I can easily and boot U-Boot without any media swapping, etc. Total code size impact on this board is approximately 9KB on U-Boot and 64 bytes on SPL: 27: dm: tegra: nyan-big: Move to livetree arm: (for 1/1 boards) all +9264.0 bss -16.0 data +44.0 rodata +92.0 spl/u-boot-spl:all +326.0 spl/u-boot-spl:rodata +262.0 spl/u-boot-spl:text +64.0 text +9144.0 Tegra does not use Thumb2, which would likely reduce the code size by about 25%, indicating a code-size impact of perhaps 7KB. I have not yet collected reliable detailed timing information. I will do that with the next version of this series, after comments are received. I expect that building the live tree will take a little time, and that using it will be very slightly faster. The use of livetree is controlled by a the CONFIG_OF_LIVE option. When enabled, U-Boot builds a livetree immediately after relocation and uses it from then on. This series is available at u-boot-dm/livet-working (note that some work remains for apalis-tk1, jetson-tk1, cei-tk1-som) Simon Glass (26): dm: video: Sync display on backspace dm: video: Update pwm_backlight to support livetree video: simple-panel: Add a little more debugging tegra: Fix up include file ordering tegra: spl: Enable debug UART tegra: nyan: Add a PMC syscon driver dm: tegra: Convert USB setup to livetree dm: tegra: Convert clock_decode_periph_id() to support livetree dm: video: tegra124: Convert to livetree tegra: dts: Move stdout-path to /chosen tegra: Don't set up the UART clocks again in U-Boot dm: tegra: gpio: Convert to support livetree dm: tegra: usb: Convert to livetree dm: tegra: spi: Convert to livetree dm: tegra: i2c: Convert to livetree dm: tegra: pwm: Convert to livetree dm: tegra: mmc: Convert to livetree power: Add a regulator driver for the as3722 PMIC power: Add a GPIO driver for the as3722 PMIC dm: power: Convert as3722 to driver model dm: serial: ns16550: Convert to livetree dm: serial: Separate out the core serial-device finding code dm: serial: Add livetree support tegra: Show a debug message if the LCD PMIC fails to start fdtdec: Drop old compatible values dm: tegra: nyan-big: Move to livetree arch/arm/dts/tegra124-nyan-big.dts| 5 +- arch/arm/include/asm/arch-tegra/clock.h | 2 +- arch/arm/include/asm/arch-tegra/tegra.h | 5 + arch/arm/include/asm/arch-tegra/xusb-padctl.h | 2 +- arch/arm/mach-tegra/board.c | 2 + arch/arm/mach-tegra/board2.c | 34 ++- arch/arm/mach-tegra/clock.c | 9 +- arch/arm/mach-tegra/spl.c | 4 + arch/arm/mach-tegra/tegra124/Makefile | 1 + arch/arm/mach-tegra/tegra124/pmc.c| 19 ++ arch/arm/mach-tegra/tegra124/xusb-padctl.c| 36 +++- arch/arm/mach-tegra/tegra210/xusb-padctl.c| 40 +++- arch/arm/mach-tegra/xusb-padctl-common.c | 84 arch/arm/mach-tegra/xusb-padctl-common.h | 11 +- arch/arm/mach-tegra/xusb-padctl-dummy.c | 2 +- board/nvidia/nyan-big/nyan-big.c | 22 +- configs/nyan-big_defconfig| 4 + drivers/gpio/tegra_gpio.c | 10 +- drivers/i2c/tegra_i2c.c | 6 +- drivers/mmc/tegra_mmc.c | 17 +- drivers/power/pmic/Makefile | 2 +- drivers/power/pmic/as3722.c | 292 +- drivers/power/pmic/as3722_gpio.c | 120 +++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/as3722_regulator.c| 149 + drivers/pwm/tegra_pwm.c | 2 +- drivers/serial/ns16550.c | 15 +- drivers/serial/serial-uclass.c| 92 drivers/spi/tegra114_spi.c| 15 +- drivers/spi/tegra20_sflash.c | 2 +- drivers/spi/tegra20_slink.c | 2 +- drivers/spi/tegra210_qspi.c | 2 +- drivers/usb/host/ehci-tegra.c | 36 ++-- drivers/video/pwm_backlight.c | 23 +- drivers/video/simple_panel.c | 2 + drivers/video/tegra124/display.c | 8 +- drivers/video/tegra124/dp.c | 3 +- drivers/video/tegra124/sor.c | 25 +-- drivers/video/vidconsole-uclass.c | 1 + include/fdtdec.h | 6 - include/power/as3722.h| 27 ++- lib/fdtdec.c | 6 - 43 files changed, 699 insertions(+), 456 deletions(-) create mode 100644 arch/arm/mach-tegra/tegra124/pmc.c create mode 100644 drivers/power/pmic/as3722_gpio.c create mode 100644 drivers/p
[U-Boot] [PATCH 09/26] dm: video: tegra124: Convert to livetree
Update these drivers to support a live device tree.
Signed-off-by: Simon Glass
---
drivers/video/tegra124/display.c | 8 +++-
drivers/video/tegra124/dp.c | 3 +--
drivers/video/tegra124/sor.c | 25 +++--
3 files changed, 11 insertions(+), 25 deletions(-)
diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c
index 47752b27f1..4164fa1bd9 100644
--- a/drivers/video/tegra124/display.c
+++ b/drivers/video/tegra124/display.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -334,7 +333,6 @@ static int display_init(struct udevice *dev, void *lcdbase,
{
struct display_plat *disp_uc_plat;
struct dc_ctlr *dc_ctlr;
- const void *blob = gd->fdt_blob;
struct udevice *dp_dev;
const int href_to_sync = 1, vref_to_sync = 1;
int panel_bpp = 18; /* default 18 bits per pixel */
@@ -363,9 +361,8 @@ static int display_init(struct udevice *dev, void *lcdbase,
return ret;
}
- dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev_of_offset(dev),
- "reg");
- if (fdtdec_decode_display_timing(blob, dev_of_offset(dev), 0, timing)) {
+ dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
+ if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
@@ -416,6 +413,7 @@ static int display_init(struct udevice *dev, void *lcdbase,
debug("dc: failed to update window\n");
return ret;
}
+ debug("%s: ready\n", __func__);
return 0;
}
diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c
index c38b3e5335..95d743d0f4 100644
--- a/drivers/video/tegra124/dp.c
+++ b/drivers/video/tegra124/dp.c
@@ -10,7 +10,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -1572,7 +1571,7 @@ static int tegra_dp_ofdata_to_platdata(struct udevice
*dev)
{
struct tegra_dp_plat *plat = dev_get_platdata(dev);
- plat->base = devfdt_get_addr(dev);
+ plat->base = dev_read_addr(dev);
return 0;
}
diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c
index 5e4140ff53..1f5e572bda 100644
--- a/drivers/video/tegra124/sor.c
+++ b/drivers/video/tegra124/sor.c
@@ -7,9 +7,9 @@
#include
#include
#include
-#include
#include
#include
+#include
#include
#include
#include
@@ -750,15 +750,12 @@ int tegra_dc_sor_attach(struct udevice *dc_dev, struct
udevice *dev,
const struct display_timing *timing)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
u32 reg_val;
- int node;
/* Use the first display controller */
debug("%s\n", __func__);
- node = dev_of_offset(dc_dev);
- disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
tegra_dc_sor_enable_dc(disp_ctrl);
tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
@@ -965,16 +962,13 @@ int tegra_dc_sor_detach(struct udevice *dc_dev, struct
udevice *dev)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int dc_reg_ctx[DC_REG_SAVE_SPACE];
- const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
unsigned long dc_int_mask;
- int node;
int ret;
debug("%s\n", __func__);
/* Use the first display controller */
- node = dev_of_offset(dc_dev);
- disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
/* Sleep mode */
tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
@@ -1041,18 +1035,13 @@ static int tegra_sor_set_backlight(struct udevice *dev,
int percent)
static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
- int node;
int ret;
- priv->base = (void *)fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+ priv->base = (void *)dev_read_addr(dev);
- node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
- if (node < 0) {
- debug("%s: Cannot find PMC\n", __func__);
- return -ENOENT;
- }
- priv->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
+ priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
+ if (IS_ERR(priv->pmc_base))
+ return PTR_ERR(priv->pmc_base);
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
&priv->panel);
--
2.13.0.303.g4ebf302169-goog
[U-Boot] [PATCH 25/26] fdtdec: Drop old compatible values
These are not needed now since the drivers now use driver model. Drop
them.
Signed-off-by: Simon Glass
---
include/fdtdec.h | 6 --
lib/fdtdec.c | 6 --
2 files changed, 12 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index eda2ffaf66..4a0947c626 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -119,12 +119,6 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
- COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
- COMPAT_NVIDIA_TEGRA186_SDMMC, /* Tegra186 SDMMC controller */
- COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */
- COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
- COMPAT_NVIDIA_TEGRA30_SDMMC,/* Tegra30 SDMMC controller */
- COMPAT_NVIDIA_TEGRA20_SDMMC,/* Tegra20 SDMMC controller */
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
/* Tegra124 XUSB pad controller */
COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 91503b8cb9..9818f78c51 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -33,12 +33,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
- COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
- COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
- COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
- COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
- COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
- COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
COMPAT(SMSC_LAN9215, "smsc,lan9215"),
--
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[U-Boot] [PATCH 04/26] tegra: Fix up include file ordering
Update these two files so include files in the right order. Signed-off-by: Simon Glass --- arch/arm/mach-tegra/board2.c | 22 -- arch/arm/mach-tegra/clock.c | 4 ++-- 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 84f1ee5035..943ee24e59 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -9,14 +9,8 @@ #include #include #include -#include -#include +#include #include -#include -#include -#include -#include -#include #include #include #include @@ -25,17 +19,17 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include #ifdef CONFIG_TEGRA_CLOCK_SCALING #include #endif -#include -#ifdef CONFIG_USB_EHCI_TEGRA -#include -#endif -#include #include -#include -#include #include "emc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 3bb72331a4..f547942022 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -7,6 +7,8 @@ /* Tegra SoC common clock control functions */ #include +#include +#include #include #include #include @@ -15,8 +17,6 @@ #include #include #include -#include -#include /* * This is our record of the current clock rate of each clock. We don't -- 2.13.0.303.g4ebf302169-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 16/26] dm: tegra: pwm: Convert to livetree
Update the tegra pwm driver to support a live device tree.
Signed-off-by: Simon Glass
---
drivers/pwm/tegra_pwm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c
index d93ac28c31..b8acc1583f 100644
--- a/drivers/pwm/tegra_pwm.c
+++ b/drivers/pwm/tegra_pwm.c
@@ -59,7 +59,7 @@ static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
- priv->regs = (struct pwm_ctlr *)devfdt_get_addr(dev);
+ priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
return 0;
}
--
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[U-Boot] [PATCH 05/26] tegra: spl: Enable debug UART
Enable the debug UART in SPL to allow early serial output even if the standard UART does not work (e.g. due to driver model problem). Signed-off-by: Simon Glass --- arch/arm/mach-tegra/spl.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 41c88cb2b4..189b3da026 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -7,6 +7,7 @@ * SPDX-License-Identifier:GPL-2.0+ */ #include +#include #include #include @@ -32,6 +33,9 @@ void spl_board_init(void) gpio_early_init_uart(); clock_early_init(); +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif preloader_console_init(); } -- 2.13.0.303.g4ebf302169-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/26] tegra: nyan: Add a PMC syscon driver
The PMC can be modelled as a syscon peripheral. Add a driver for this
so that it can be accessed by drivers when needed.
Signed-off-by: Simon Glass
---
arch/arm/include/asm/arch-tegra/tegra.h | 5 +
arch/arm/mach-tegra/tegra124/Makefile | 1 +
arch/arm/mach-tegra/tegra124/pmc.c | 19 +++
configs/nyan-big_defconfig | 2 ++
4 files changed, 27 insertions(+)
create mode 100644 arch/arm/mach-tegra/tegra124/pmc.c
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h
b/arch/arm/include/asm/arch-tegra/tegra.h
index 3add1b3c09..3b9711d28e 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -97,6 +97,11 @@ enum {
TEGRA_SOC_UNKNOWN = -1,
};
+/* Tegra system controller (SYSCON) devices */
+enum {
+ TEGRA_SYSCON_PMC,
+};
+
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRLNV_PA_PMC_BASE
#endif
diff --git a/arch/arm/mach-tegra/tegra124/Makefile
b/arch/arm/mach-tegra/tegra124/Makefile
index c00de6151e..d275dafdc4 100644
--- a/arch/arm/mach-tegra/tegra124/Makefile
+++ b/arch/arm/mach-tegra/tegra124/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-y += clock.o
obj-y += funcmux.o
obj-y += pinmux.o
+obj-y += pmc.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra124/pmc.c
b/arch/arm/mach-tegra/tegra124/pmc.c
new file mode 100644
index 00..be82acf11e
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra124/pmc.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+static const struct udevice_id tegra124_syscon_ids[] = {
+ { .compatible = "nvidia,tegra124-pmc", .data = TEGRA_SYSCON_PMC },
+};
+
+U_BOOT_DRIVER(syscon_tegra124) = {
+ .name = "tegra124_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = tegra124_syscon_ids,
+};
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 8345aea27b..22769bdc93 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -34,6 +34,8 @@ CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
--
2.13.0.303.g4ebf302169-goog
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[U-Boot] [PATCH 11/26] tegra: Don't set up the UART clocks again in U-Boot
The UART clocks are already set up in SPL so we don't need to do it again in U-Boot. This seems to cause a hang on Nyan. Signed-off-by: Simon Glass --- arch/arm/mach-tegra/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index b3a041b539..c478420655 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -187,7 +187,9 @@ static void setup_uarts(int uart_ids) enum periph_id id = id_for_uart[i]; funcmux_select(id, uart_configs[i]); +#ifdef CONFIG_SPL_BUILD clock_ll_start_uart(id); +#endif } } } -- 2.13.0.303.g4ebf302169-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 14/26] dm: tegra: spi: Convert to livetree
Update the tegra114 spi driver to support a live device tree.
Signed-off-by: Simon Glass
---
drivers/spi/tegra114_spi.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 86b1019585..013bc82380 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -100,10 +99,8 @@ struct tegra114_spi_priv {
static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
@@ -113,10 +110,10 @@ static int tegra114_spi_ofdata_to_platdata(struct udevice
*bus)
}
/* Use 500KHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
- 50);
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
- "spi-deactivate-delay", 0);
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+ 50);
+ plat->deactivate_delay_us = dev_read_u32_default(bus,
+ "spi-deactivate-delay", 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d,
deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
--
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[U-Boot] [PATCH 22/26] dm: serial: Separate out the core serial-device finding code
This function is quite long. Move the core code into a separate function
in preparation for adding livetree support.
Signed-off-by: Simon Glass
---
drivers/serial/serial-uclass.c | 84 ++
1 file changed, 44 insertions(+), 40 deletions(-)
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index a9c4f89e1a..ede5c2c0be 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -8,7 +8,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -27,11 +26,53 @@ static const unsigned long baudrate_table[] =
CONFIG_SYS_BAUDRATE_TABLE;
#error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN
to make this work"
#endif
+static int serial_check_stdout(const void *blob, struct udevice **devp)
+{
+ int node;
+
+ /* Check for a chosen console */
+ node = fdtdec_get_chosen_node(blob, "stdout-path");
+ if (node < 0) {
+ const char *str, *p, *name;
+
+ /*
+* Deal with things like
+* stdout-path = "serial0:115200n8";
+*
+* We need to look up the alias and then follow it to the
+* correct node.
+*/
+ str = fdtdec_get_chosen_prop(blob, "stdout-path");
+ if (str) {
+ p = strchr(str, ':');
+ name = fdt_get_alias_namelen(blob, str,
+ p ? p - str : strlen(str));
+ if (name)
+ node = fdt_path_offset(blob, name);
+ }
+ }
+ if (node < 0)
+ node = fdt_path_offset(blob, "console");
+ if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, devp))
+ return 0;
+
+ /*
+* If the console is not marked to be bound before relocation, bind it
+* anyway.
+*/
+ if (node > 0 && !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
+ devp)) {
+ if (!device_probe(*devp))
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static void serial_find_console_or_panic(void)
{
const void *blob = gd->fdt_blob;
struct udevice *dev;
- int node;
if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
uclass_first_device(UCLASS_SERIAL, &dev);
@@ -40,47 +81,10 @@ static void serial_find_console_or_panic(void)
return;
}
} else if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
- /* Check for a chosen console */
- node = fdtdec_get_chosen_node(blob, "stdout-path");
- if (node < 0) {
- const char *str, *p, *name;
-
- /*
-* Deal with things like
-* stdout-path = "serial0:115200n8";
-*
-* We need to look up the alias and then follow it to
-* the correct node.
-*/
- str = fdtdec_get_chosen_prop(blob, "stdout-path");
- if (str) {
- p = strchr(str, ':');
- name = fdt_get_alias_namelen(blob, str,
- p ? p - str : strlen(str));
- if (name)
- node = fdt_path_offset(blob, name);
- }
- }
- if (node < 0)
- node = fdt_path_offset(blob, "console");
- if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node,
- &dev)) {
+ if (!serial_check_stdout(blob, &dev)) {
gd->cur_serial_dev = dev;
return;
}
-
- /*
-* If the console is not marked to be bound before relocation,
-* bind it anyway.
-*/
- if (node > 0 &&
- !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
- &dev)) {
- if (!device_probe(dev)) {
- gd->cur_serial_dev = dev;
- return;
- }
- }
}
if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) {
/*
--
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[U-Boot] [PATCH 20/26] dm: power: Convert as3722 to driver model
Convert this PMIC driver to driver model and fix up other users. The
regulator and GPIO functions are now handled by separate drivers.
Note that this currently breaks apalis-tk1, jetson-tk1 and cei-tk1-som.
I have the middle one so will tidy that up in the next version, at least.
Signed-off-by: Simon Glass
---
arch/arm/mach-tegra/board2.c | 6 -
board/nvidia/nyan-big/nyan-big.c | 22 +--
configs/nyan-big_defconfig | 1 +
drivers/power/pmic/Makefile | 2 +-
drivers/power/pmic/as3722.c | 292 +--
include/power/as3722.h | 18 +--
6 files changed, 114 insertions(+), 227 deletions(-)
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 5aedd3ef9d..0291c7fb33 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -29,7 +29,6 @@
#ifdef CONFIG_TEGRA_CLOCK_SCALING
#include
#endif
-#include
#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -142,11 +141,6 @@ int board_init(void)
debug("Memory controller init failed: %d\n", err);
# endif
# endif /* CONFIG_TEGRA_PMU */
-#ifdef CONFIG_PMIC_AS3722
- err = as3722_init(NULL);
- if (err && err != -ENODEV)
- return err;
-#endif
#endif /* CONFIG_SYS_I2C_TEGRA */
#ifdef CONFIG_USB_EHCI_TEGRA
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index 8f68ae9fbe..54acf5418d 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -6,6 +6,7 @@
*/
#include
+#include
#include
#include
#include
@@ -46,20 +47,23 @@ int tegra_board_id(void)
int tegra_lcd_pmic_init(int board_id)
{
- struct udevice *pmic;
+ struct udevice *dev;
int ret;
- ret = as3722_get(&pmic);
- if (ret)
- return -ENOENT;
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_as3722), &dev);
+ if (ret) {
+ debug("%s: Failed to find PMIC\n", __func__);
+ return ret;
+ }
if (board_id == 0)
- as3722_write(pmic, 0x00, 0x3c);
+ pmic_reg_write(dev, 0x00, 0x3c);
else
- as3722_write(pmic, 0x00, 0x50);
- as3722_write(pmic, 0x12, 0x10);
- as3722_write(pmic, 0x0c, 0x07);
- as3722_write(pmic, 0x20, 0x10);
+ pmic_reg_write(dev, 0x00, 0x50);
+ pmic_reg_write(dev, 0x12, 0x10);
+ pmic_reg_write(dev, 0x0c, 0x07);
+ pmic_reg_write(dev, 0x20, 0x10);
return 0;
}
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 22769bdc93..a152ff6915 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f409e3a0b3..76dda2a070 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
-obj-$(CONFIG_PMIC_AS3722) += as3722.o
+obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o
obj-$(CONFIG_PMIC_MAX8997) += max8997.o
obj-$(CONFIG_PMIC_PM8916) += pm8916.o
obj-$(CONFIG_PMIC_RK8XX) += rk8xx.o
diff --git a/drivers/power/pmic/as3722.c b/drivers/power/pmic/as3722.c
index c09e1de06f..4efe8ee183 100644
--- a/drivers/power/pmic/as3722.c
+++ b/drivers/power/pmic/as3722.c
@@ -11,264 +11,168 @@
#include
#include
#include
-
+#include
#include
+#include
-#define AS3722_SD_VOLTAGE(n) (0x00 + (n))
-#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
-#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
-#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
-#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
-#define AS3722_LDO_VOLTAGE(n) (0x10 + (n))
-#define AS3722_GPIO_SIGNAL_OUT 0x20
-#define AS3722_SD_CONTROL 0x4d
-#define AS3722_LDO_CONTROL 0x4e
-#define AS3722_ASIC_ID1 0x90
-#define AS3722_DEVICE_ID 0x0c
-#define AS3722_ASIC_ID2 0x91
-
-int as3722_read(struct udevice *pmic, u8 reg, u8 *value)
-{
- int err;
-
- err = dm_i2c_read(pmic, reg, value, 1);
- if (err < 0)
- return err;
-
- return 0;
-}
+#define AS3722_NUM_OF_REGS 0x92
-int as3722_write(struct udevice *pmic, u8 reg, u8 value)
+static int as3722_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
{
- int err;
+ int ret;
- err = dm_i2c_write(pmic, reg, &value, 1);
- if (err < 0)
- return err;
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret < 0)
+ return ret;
return 0;
}
-static int as3722_read_id(struct udevice *pmi
[U-Boot] [PATCH 07/26] dm: tegra: Convert USB setup to livetree
Adjust this code to support a live device tree. This should be implemented
as a PHY driver but that is left as an exercise for the maintainer.
Signed-off-by: Simon Glass
---
arch/arm/include/asm/arch-tegra/xusb-padctl.h | 2 +-
arch/arm/mach-tegra/board2.c | 2 +-
arch/arm/mach-tegra/tegra124/xusb-padctl.c| 36 +---
arch/arm/mach-tegra/tegra210/xusb-padctl.c| 40 +
arch/arm/mach-tegra/xusb-padctl-common.c | 84 ++-
arch/arm/mach-tegra/xusb-padctl-common.h | 11 ++--
arch/arm/mach-tegra/xusb-padctl-dummy.c | 2 +-
7 files changed, 112 insertions(+), 65 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h
b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
index b4b4c8ba4d..deccdf455d 100644
--- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h
+++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
@@ -15,7 +15,7 @@ struct tegra_xusb_phy;
*/
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
-void tegra_xusb_padctl_init(const void *fdt);
+void tegra_xusb_padctl_init(void);
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 943ee24e59..5aedd3ef9d 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -164,7 +164,7 @@ int board_init(void)
pin_mux_nand();
#endif
- tegra_xusb_padctl_init(gd->fdt_blob);
+ tegra_xusb_padctl_init();
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c
b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
index 76af924b94..d326a6ae57 100644
--- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
@@ -8,6 +8,8 @@
#include
#include
+#include
+#include
#include "../xusb-padctl-common.h"
@@ -317,13 +319,33 @@ static const struct tegra_xusb_padctl_soc
tegra124_socdata = {
.num_phys = ARRAY_SIZE(tegra124_phys),
};
-void tegra_xusb_padctl_init(const void *fdt)
+void tegra_xusb_padctl_init(void)
{
- int count, nodes[1];
+ ofnode nodes[1];
+ int count = 0;
+ int ret;
+
+ debug("%s: start\n", __func__);
+ if (of_live_active()) {
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "nvidia,tegra124-xusb-padctl");
+
+ debug("np=%p\n", np);
+ if (np) {
+ nodes[0] = np_to_ofnode(np);
+ count = 1;
+ }
+ } else {
+ int node_offsets[1];
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
+ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
+ node_offsets, ARRAY_SIZE(node_offsets));
+ for (i = 0; i < count; i++)
+ nodes[i] = offset_to_ofnode(node_offsets[i]);
+ }
- count = fdtdec_find_aliases_for_id(fdt, "padctl",
- COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
- nodes, ARRAY_SIZE(nodes));
- if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra124_socdata))
- return;
+ ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata);
+ debug("%s: done, ret=%d\n", __func__, ret);
}
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index 9ec93e7c4c..fde76dda01 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -8,6 +8,8 @@
#include
#include
+#include
+#include
#include "../xusb-padctl-common.h"
@@ -421,17 +423,33 @@ static const struct tegra_xusb_padctl_soc
tegra210_socdata = {
.num_phys = ARRAY_SIZE(tegra210_phys),
};
-void tegra_xusb_padctl_init(const void *fdt)
+void tegra_xusb_padctl_init(void)
{
- int count, nodes[1];
-
- debug("> %s(fdt=%p)\n", __func__, fdt);
-
- count = fdtdec_find_aliases_for_id(fdt, "padctl",
- COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
- nodes, ARRAY_SIZE(nodes));
- if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata))
- return;
+ ofnode nodes[1];
+ int count = 0;
+ int ret;
+
+ debug("%s: start\n", __func__);
+ if (of_live_active()) {
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "nvidia,tegra210-xusb-padctl");
+
+ debug("np=%p\n", np);
+ if (np) {
+ nodes[0] = np_to_ofnode(np);
+
[U-Boot] [PATCH 17/26] dm: tegra: mmc: Convert to livetree
Update the tegra mmc driver to support a live device tree.
Signed-off-by: Simon Glass
---
drivers/mmc/tegra_mmc.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 338e42b528..9f7e7195f1 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -11,10 +11,10 @@
#include
#include
#include
+#include
#include
#include
#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -599,8 +599,7 @@ static int tegra_mmc_probe(struct udevice *dev)
cfg->name = dev->name;
- bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "bus-width", 1);
+ bus_width = dev_read_u32_default(dev, "bus-width", 1);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = 0;
@@ -621,7 +620,7 @@ static int tegra_mmc_probe(struct udevice *dev)
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- priv->reg = (void *)devfdt_get_addr(dev);
+ priv->reg = (void *)dev_read_addr(dev);
ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
if (ret) {
@@ -648,12 +647,10 @@ static int tegra_mmc_probe(struct udevice *dev)
return ret;
/* These GPIOs are optional */
- gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
-GPIOD_IS_IN);
- gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
-GPIOD_IS_IN);
- gpio_request_by_name(dev, "power-gpios", 0,
-&priv->pwr_gpio, GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
+GPIOD_IS_OUT);
if (dm_gpio_is_valid(&priv->pwr_gpio))
dm_gpio_set_value(&priv->pwr_gpio, 1);
--
2.13.0.303.g4ebf302169-goog
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[U-Boot] [PATCH 21/26] dm: serial: ns16550: Convert to livetree
Update this driver to support a live device tree.
Signed-off-by: Simon Glass
---
drivers/serial/ns16550.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 52c52c1ad1..330c5e186a 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -8,7 +8,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -395,7 +394,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
int err;
/* try Processor Local Bus device first */
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
@@ -434,11 +433,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
#endif
- plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-"reg-offset", 0);
- plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-"reg-shift", 0);
-
+ plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
+ plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
err = clk_get_by_index(dev, 0, &clk);
if (!err) {
err = clk_get_rate(&clk);
@@ -450,9 +446,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
}
if (!plat->clock)
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-"clock-frequency",
-CONFIG_SYS_NS16550_CLK);
+ plat->clock = dev_read_u32_default(dev, "clock-frequency",
+ CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("ns16550 clock not defined\n");
return -EINVAL;
--
2.13.0.303.g4ebf302169-goog
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[U-Boot] [PATCH 18/26] power: Add a regulator driver for the as3722 PMIC
This pmic includes regulators which should have their own driver. Add
a driver to support these.
Signed-off-by: Simon Glass
---
drivers/power/regulator/Kconfig| 9 ++
drivers/power/regulator/Makefile | 1 +
drivers/power/regulator/as3722_regulator.c | 149 +
include/power/as3722.h | 8 ++
4 files changed, 167 insertions(+)
create mode 100644 drivers/power/regulator/as3722_regulator.c
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index ef057e0e2f..2583a19910 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -34,6 +34,15 @@ config REGULATOR_ACT8846
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
+config REGULATOR_AS3722
+ bool "Enable driver for AS7322 regulator"
+ depends on DM_REGULATOR && PMIC_AS3722
+ help
+ Enable support for the regulator functions of the AS3722. The
+ driver implements enable/disable for step-down bucks and LDOs,
+ but does not yet support change voltages. Currently this must be
+ done using direct register writes to the PMIC.
+
config DM_REGULATOR_PFUZE100
bool "Enable Driver Model for REGULATOR PFUZE100"
depends on DM_REGULATOR && DM_PMIC_PFUZE100
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 3e01021b76..48d3735d6c 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
+obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
diff --git a/drivers/power/regulator/as3722_regulator.c
b/drivers/power/regulator/as3722_regulator.c
new file mode 100644
index 00..0122e1e389
--- /dev/null
+++ b/drivers/power/regulator/as3722_regulator.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2017 Google, Inc
+ * Written by Simon Glass
+ *
+ * Placeholder regulator driver for as3722.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int stepdown_get_value(struct udevice *dev)
+{
+ return -ENOSYS;
+}
+
+static int stepdown_set_value(struct udevice *dev, int uvolt)
+{
+ return -ENOSYS;
+}
+
+static int stepdown_set_enable(struct udevice *dev, bool enable)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int sd = dev->driver_data;
+ int ret;
+
+ ret = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
+ if (ret < 0) {
+ debug("%s: failed to write SD control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static bool stepdown_get_enable(struct udevice *dev)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int sd = dev->driver_data;
+ int ret;
+
+ ret = pmic_reg_read(pmic, AS3722_SD_CONTROL);
+ if (ret < 0) {
+ debug("%s: failed to read SD control register: %d", __func__,
+ ret);
+ return false;
+ }
+
+ return ret & (1 << sd) ? true : false;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ return -ENOSYS;
+}
+
+static int ldo_set_value(struct udevice *dev, int uvolt)
+{
+ return -ENOSYS;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int ldo = dev->driver_data;
+ int ret;
+
+ ret = pmic_clrsetbits(pmic, AS3722_LDO_CONTROL, 0, 1 << ldo);
+ if (ret < 0) {
+ debug("%s: failed to write LDO control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static bool ldo_get_enable(struct udevice *dev)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int ldo = dev->driver_data;
+ int ret;
+
+ ret = pmic_reg_read(pmic, AS3722_LDO_CONTROL);
+ if (ret < 0) {
+ debug("%s: failed to read SD control register: %d", __func__,
+ ret);
+ return false;
+ }
+
+ return ret & (1 << ldo) ? true : false;
+}
+
+static int as3722_stepdown_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ return 0;
+}
+
+static int as3722_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+
+ return 0;
+}
+
+static const struct dm_regulator_ops as3722_stepdown_ops = {
+
Re: [U-Boot] [PATCH] rockchip: doc: update latest info to document
Am Dienstag, 16. Mai 2017, 09:19:57 CEST schrieb Kever Yang: > > On 05/16/2017 02:51 AM, Heiko Stübner wrote: > > Hi Kever, > > > > Am Montag, 15. Mai 2017, 21:18:00 CEST schrieb Kever Yang: > >> - Add some rk3399 and rk3328 boards; > >> - use rkdeveloptool instead of rkflashtool; > >> - use opensource.rock-chips.com instead of wikidot; > >> - other update. > >> > >> Signed-off-by: Kever Yang > >> --- > >> > >> doc/README.rockchip | 38 -- > >> 1 file changed, 24 insertions(+), 14 deletions(-) > >> > >> diff --git a/doc/README.rockchip b/doc/README.rockchip > >> index 2d8cf9f..229db0d 100644 > >> --- a/doc/README.rockchip > >> +++ b/doc/README.rockchip > >> @@ -14,9 +14,6 @@ many Rockchip devices [1] [2]. > >> The current mainline support is experimental only and is not useful for > >> anything. It should provide a base on which to build. > >> > >> -So far only support for the RK3288 and RK3036 is provided. > >> - > >> - > >> Prerequisites > >> = > >> > >> @@ -26,17 +23,18 @@ You will need: > >> - Power connection to 5V using the supplied micro-USB power cable > >> - Separate USB serial cable attached to your computer and the Firefly > >> (connect to the micro-USB connector below the logo) > >> - - rkflashtool [3] > >> - - openssl (sudo apt-get install openssl) > >> + - rkdeveloptool [3] > > In my personal opinion, rkflashtool should stay. You can very well add > > rkdeveloptool as a second option, but rkflashtool was there first and > > also is the one that most distributions contain in their repositories. > > And both tools seem to have the same functionality. > > OK, it can leave there, but I don't know why it does not works well with > rk3399. I'd guess most likely because it is missing the soc-specific id for the rk3399 [0]. Heiko [0] https://github.com/linux-rockchip/rkflashtool/blob/master/rkflashtool.c#L103 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 01/26] dm: video: Sync display on backspace
On Fri, 19 May 2017 08:30:44 -0600 Simon Glass s...@chromium.org wrote: > We should sync the display (e.g. flush cache) when backspace is pressed > to ensure that the character is erased correctly. > > Signed-off-by: Simon Glass > --- > > drivers/video/vidconsole-uclass.c | 1 + > 1 file changed, 1 insertion(+) Acked-by: Anatolij Gustschin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 02/26] dm: video: Update pwm_backlight to support livetree
On Fri, 19 May 2017 08:30:45 -0600 Simon Glass s...@chromium.org wrote: > Update this driver to support a live device tree. > > Signed-off-by: Simon Glass > --- > > drivers/video/pwm_backlight.c | 23 +-- > 1 file changed, 13 insertions(+), 10 deletions(-) Acked-by: Anatolij Gustschin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 03/26] video: simple-panel: Add a little more debugging
On Fri, 19 May 2017 08:30:46 -0600 Simon Glass s...@chromium.org wrote: > Add some debugging to show when the backlight is enabled. > > Signed-off-by: Simon Glass > --- > > drivers/video/simple_panel.c | 2 ++ > 1 file changed, 2 insertions(+) Acked-by: Anatolij Gustschin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/8] sf: improve support of (Q)SPI flash memories
Hi all, this series of patches has been tested on u-boot-2017.03-at91 then ported to the 'master' branch of the u-boot-spi.git tree. Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers. The following tests have been passed: - QSPI0 + Macronix MX25L25673G: + probe: OK + Fast Read 1-1-4 at offset 0x1 (u-boot env): OK + Page Program 1-1-4 at offset 0x1: OK The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why... - QSPI0 + Microchip SST26 + probe: OK + Fast Read 1-1-4 at offset 0x1 (u-boot env): OK + Page Program 1-1-1 at offset 0x1: OK SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it. - QSPI0 + Adesto AT25DF321A + probe: OK + Fast Read 1-1-1 at offset 0x1 (u-boot env): OK + Page Program 1-1-1 at offset 0x1: OK - SPI0 + Adesto AT25DF321A + probe: OK + Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK + Page Program 1-1-1 at offest 0x6000: OK - SPI1 + Atmel AT45 + probe: OK + Read at offset 0: OK + Write at offset 0: OK <- I didn't try offset other than 0. During my tests, I used: - setenv/saveenv, reboot, printenv or - sf probe, sf read, sf write Best regards, Cyrille Cyrille Pitchen (8): spi: add support of SPI flash commands sf: describe all SPI flash commands with 'struct spi_flash_command' sf: select the relevant SPI flash protocol for read and write commands sf: differentiate Page Program 1-1-4 and 1-4-4 sf: add 'addr_len' member to 'struct spi_flash' sf: add new option to support SPI flash above 16MiB sf: add support to Microchip SST26 QSPI memories sf: add driver for Atmel QSPI controller drivers/mtd/spi/Kconfig | 15 +- drivers/mtd/spi/sf.c| 78 ++-- drivers/mtd/spi/sf_dataflash.c | 119 ++-- drivers/mtd/spi/sf_internal.h | 48 +++-- drivers/mtd/spi/spi_flash.c | 338 +++-- drivers/mtd/spi/spi_flash_ids.c | 5 + drivers/spi/Kconfig | 7 + drivers/spi/Makefile| 1 + drivers/spi/atmel_qspi.c| 404 drivers/spi/atmel_qspi.h| 169 + drivers/spi/spi-uclass.c| 40 drivers/spi/spi.c | 13 ++ include/spi.h | 168 + include/spi_flash.h | 6 + 14 files changed, 1222 insertions(+), 189 deletions(-) create mode 100644 drivers/spi/atmel_qspi.c create mode 100644 drivers/spi/atmel_qspi.h -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/8] spi: add support of SPI flash commands
This patch introduces 'struct spi_flash_command' and functions
spi_is_flash_command_supported() / spi_exec_flash_command().
The 'struct spi_flash_command' describes all the relevant parameters to
execute any SPI flash command:
- the instruction op code
- the number of bytes used to send the address: 0, 3 or 4 bytes
- the number of mode and wait-state clock cycles, also called dummy cycles
- the number and values of data bytes to be sent or received
- the SPI x-y-z protocol [1]
- the flash command type [2]
[1] SPI x-y-z protocol:
- x is the number of I/O lines used to send the instruction op code.
- y is the number of I/O lines used during address, mode and wait-state
clock cycles.
- z is the number of I/O lines used to send or received data.
[2] Flash command type:
The flash command type is provided to differenciate "memory"
read/write/erase operations from "flash internal register" read/write
operations. Indeed some SPI controller drivers handle those command type
in different ways.
However SPI controller drivers should not check the value of the
instruction op code to guess the actual kind of flash command to perform.
Many instruction op codes are SPI flash manufacturer specific and only
drivers/mtd/spi/spi_flash.c should have the knowledge of all of them.
Besides, more and more QSPI controllers, like those of TI and Candence,
have special way to support (Fast) Read operations using some
"memory like" area mapped into the system bus. Hence, if those drivers
choose to override the default implementation of
spi_is_flash_command_supported() so that their own functions return true
only for a "memory read" flash command type, then spi_exec_flash_command()
might be used to implement the read from the "memory like" area mapped
into the system bus.
It means that spi_exec_flash_command() could be used to supersede the
actual flash->memory_map mechanism; spi_is_flash_command_supported() /
spi_exec_flash_command() being more generic and covering more use cases.
For instance, the Atmel QSPI hardware controller uses its "memory like"
area mapped ino the system to perform not only (Fast) Read operations but
actually all other types of flash commands. Hence the regular SPI API
based on the spi_xfer() function is not suited to support the Atmel QSPI
controller.
Signed-off-by: Cyrille Pitchen
---
drivers/spi/spi-uclass.c | 40 +++
drivers/spi/spi.c| 13
include/spi.h| 168 +++
3 files changed, 221 insertions(+)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index c061c05443d4..b8092538e9b0 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -92,6 +92,30 @@ int dm_spi_xfer(struct udevice *dev, unsigned int bitlen,
return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags);
}
+bool dm_spi_is_flash_command_supported(struct udevice *dev,
+ const struct spi_flash_command *cmd)
+{
+ struct udevice *bus = dev->parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+
+ if (ops->is_flash_command_supported)
+ return ops->is_flash_command_supported(dev, cmd);
+
+ return false;
+}
+
+int dm_spi_exec_flash_command(struct udevice *dev,
+ const struct spi_flash_command *cmd)
+{
+ struct udevice *bus = dev->parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+
+ if (ops->exec_flash_command)
+ return ops->exec_flash_command(dev, cmd);
+
+ return -EINVAL;
+}
+
int spi_claim_bus(struct spi_slave *slave)
{
return dm_spi_claim_bus(slave->dev);
@@ -108,6 +132,18 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
}
+bool spi_is_flash_command_supported(struct spi_slave *slave,
+ const struct spi_flash_command *cmd)
+{
+ return dm_spi_is_flash_command_supported(slave->dev, cmd);
+}
+
+int spi_exec_flash_command(struct spi_slave *slave,
+ const struct spi_flash_command *cmd)
+{
+ return dm_spi_exec_flash_command(slave->dev, cmd);
+}
+
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static int spi_child_post_bind(struct udevice *dev)
{
@@ -147,6 +183,10 @@ static int spi_post_probe(struct udevice *bus)
ops->set_mode += gd->reloc_off;
if (ops->cs_info)
ops->cs_info += gd->reloc_off;
+ if (ops->is_flash_command_supported)
+ ops->is_flash_command_supported += gd->reloc_off;
+ if (ops->exec_flash_command)
+ ops->exec_flash_command += gd->reloc_off;
#endif
return 0;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 7d81fbd7f8f5..e47acdc9e414 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -58,3 +59,15 @@ struct spi_slave *spi_base_setup_slave_fd
[U-Boot] [PATCH 2/8] sf: describe all SPI flash commands with 'struct spi_flash_command'
Now that the SPI sub-system API has been extended with
'struct spi_flash_command' and spi_is_flash_command_supported() /
spi_exec_flash_command() functions, we update the SPI FLASH sub-system to
use this new API.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/sf.c | 78 +
drivers/mtd/spi/sf_dataflash.c | 119 +-
drivers/mtd/spi/sf_internal.h | 24 +++---
drivers/mtd/spi/spi_flash.c| 184 +++--
4 files changed, 236 insertions(+), 169 deletions(-)
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index d5e175ca..6178b0aa9824 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -9,46 +9,88 @@
#include
#include
+#include
-static int spi_flash_read_write(struct spi_slave *spi,
- const u8 *cmd, size_t cmd_len,
- const u8 *data_out, u8 *data_in,
- size_t data_len)
+#include "sf_internal.h"
+
+static void spi_flash_addr(u32 addr, u8 addr_len, u8 *cmd_buf)
{
+ u8 i;
+
+ for (i = 0; i < addr_len; i++)
+ cmd_buf[i] = addr >> ((addr_len - 1 - i) * 8);
+}
+
+static u8 spi_compute_num_dummy_bytes(enum spi_flash_protocol proto,
+ u8 num_dummy_clock_cycles)
+{
+ int shift = fls(spi_flash_protocol_get_addr_nbits(proto)) - 1;
+
+ if (shift < 0)
+ shift = 0;
+ return (num_dummy_clock_cycles << shift) >> 3;
+}
+
+static int spi_flash_exec(struct spi_flash *flash,
+ const struct spi_flash_command *cmd)
+{
+ struct spi_slave *spi = flash->spi;
+ u8 cmd_buf[SPI_FLASH_CMD_LEN];
+ size_t cmd_len, num_dummy_bytes;
unsigned long flags = SPI_XFER_BEGIN;
int ret;
- if (data_len == 0)
+ if (spi_is_flash_command_supported(spi, cmd))
+ return spi_exec_flash_command(spi, cmd);
+
+ if (cmd->data_len == 0)
flags |= SPI_XFER_END;
- ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
+ cmd_buf[0] = cmd->inst;
+ spi_flash_addr(cmd->addr, cmd->addr_len, cmd_buf + 1);
+ cmd_len = 1 + cmd->addr_len;
+
+ num_dummy_bytes = spi_compute_num_dummy_bytes(cmd->proto,
+ cmd->num_mode_cycles +
+ cmd->num_wait_states);
+ memset(cmd_buf + cmd_len, 0xff, num_dummy_bytes);
+ cmd_len += num_dummy_bytes;
+
+ ret = spi_xfer(spi, cmd_len * 8, cmd_buf, NULL, flags);
if (ret) {
debug("SF: Failed to send command (%zu bytes): %d\n",
cmd_len, ret);
- } else if (data_len != 0) {
- ret = spi_xfer(spi, data_len * 8, data_out, data_in,
- SPI_XFER_END);
+ } else if (cmd->data_len != 0) {
+ ret = spi_xfer(spi, cmd->data_len * 8,
+ cmd->tx_data, cmd->rx_data,
+ SPI_XFER_END);
if (ret)
debug("SF: Failed to transfer %zu bytes of data: %d\n",
- data_len, ret);
+ cmd->data_len, ret);
}
return ret;
}
-int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len)
+int spi_flash_cmd_read(struct spi_flash *flash,
+ const struct spi_flash_command *cmd)
{
- return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
+ return spi_flash_exec(flash, cmd);
}
-int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
+int spi_flash_cmd(struct spi_flash *flash, u8 instr, void *response, size_t
len)
{
- return spi_flash_cmd_read(spi, &cmd, 1, response, len);
+ struct spi_flash_command cmd;
+ u8 flags = (response && len) ? SPI_FCMD_READ_REG : SPI_FCMD_WRITE_REG;
+
+ spi_flash_command_init(&cmd, instr, 0, flags);
+ cmd.data_len = len;
+ cmd.rx_data = response;
+ return spi_flash_exec(flash, &cmd);
}
-int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
- const void *data, size_t data_len)
+int spi_flash_cmd_write(struct spi_flash *flash,
+ const struct spi_flash_command *cmd)
{
- return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
+ return spi_flash_exec(flash, cmd);
}
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index bcddfa07556b..b2166ad4e5ff 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -73,7 +73,7 @@ struct dataflash {
};
/* Return the status of the DataFlash device */
-static inline int dataflash_status(struct spi_slave *spi)
+static inline int dataflash_status(struct spi_flash *spi_flash)
{
[U-Boot] [PATCH 6/8] sf: add new option to support SPI flash above 16MiB
The patch provides an alternative method to support SPI flash size greater
than 16MiB (128Mib).
Indeed using the Base Address Register (BAR) is stateful. Hence, once the
BAR has been modified, if a spurious CPU reset occurs with no reset/power
off at the SPI flash side, early boot loarders may try to read from offset
0 but fails because of the new BAR value.
On the other hand, using the 4-byte address instruction set is stateless.
When supported by the SPI flash memory, it allows us to access memory data
area above 16MiB without changing the internal state of this SPI flash
memory. Then if a spirious reboot occurs, early boot loaders can still
access data from offset 0.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/Kconfig | 15 ++-
drivers/mtd/spi/sf_internal.h | 18 +
drivers/mtd/spi/spi_flash.c | 92 ---
3 files changed, 118 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 5ca0a712d84a..c11e83263b16 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -34,14 +34,27 @@ config SPI_FLASH
If unsure, say N
+choice
+ prompt "Support SPI flash above 16MiB"
+ depends on SPI_FLASH
+ optional
+
config SPI_FLASH_BAR
bool "SPI flash Bank/Extended address register support"
- depends on SPI_FLASH
help
Enable the SPI flash Bank/Extended address register support.
Bank/Extended address registers are used to access the flash
which has size > 16MiB in 3-byte addressing.
+config SPI_FLASH_4BAIS
+ bool "SPI flash 4-byte address instruction set support"
+ help
+ Convert the selected 3-byte address op codes into their associated
+ 4-byte address op codes. Using this instruction set does not change
+ the internal state of the SPI flash device.
+
+endchoice
+
if SPI_FLASH
config SPI_FLASH_ATMEL
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 8b8c951bcc55..30994f9f460c 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -27,6 +27,7 @@ enum spi_nor_option_flags {
};
#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_4B_ADDR_LEN 4
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN + 16)
#define SPI_FLASH_16MB_BOUN0x100
@@ -64,6 +65,19 @@ enum spi_nor_option_flags {
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+/* 4-byte address instruction set */
+#define CMD_READ_ARRAY_SLOW_4B 0x13
+#define CMD_READ_ARRAY_FAST_4B 0x0c
+#define CMD_READ_DUAL_OUTPUT_FAST_4B 0x3c
+#define CMD_READ_DUAL_IO_FAST_4B 0xbc
+#define CMD_READ_QUAD_OUTPUT_FAST_4B 0x6c
+#define CMD_READ_QUAD_IO_FAST_4B 0xec
+#define CMD_PAGE_PROGRAM_4B0x12
+#define CMD_PAGE_PROGRAM_1_1_4_4B 0x34
+#define CMD_PAGE_PROGRAM_1_4_4_4B 0x3e
+#define CMD_ERASE_4K_4B0x21
+#define CMD_ERASE_64K_4B 0xdc
+
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
# define CMD_BANKADDR_BRWR 0x17
@@ -133,6 +147,10 @@ struct spi_flash_info {
#define RD_QUADIO BIT(6) /* use Quad IO Read */
#define RD_DUALIO BIT(7) /* use Dual IO Read */
#define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO |
RD_DUALIO)
+#define NO_4BAIS BIT(8) /*
+* 4-byte address instruction set
+* NOT supported
+*/
};
extern const struct spi_flash_info spi_flash_ids[];
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index c5e00772f241..695c8555db3f 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -176,6 +176,67 @@ bar_end:
}
#endif
+#ifdef CONFIG_SPI_FLASH_4BAIS
+static u8 spi_flash_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
+{
+ size_t i;
+
+ for (i = 0; i < size; i++)
+ if (table[i][0] == opcode)
+ return table[i][1];
+
+ /* No conversion found, keep input op code. */
+ return opcode;
+}
+
+static u8 spi_flash_convert_3to4_read(u8 opcode)
+{
+ static const u8 spi_flash_3to4_read[][2] = {
+ {CMD_READ_ARRAY_SLOW, CMD_READ_ARRAY_SLOW_4B},
+ {CMD_READ_ARRAY_FAST, CMD_READ_ARRAY_FAST_4B},
+ {CMD_READ_DUAL_OUTPUT_FAST, CMD_READ_DUAL_OUTPUT_FAST_4B},
+ {CMD_READ_DUAL_IO_FAST, CMD_READ_DUAL_IO_FAST_4B},
+ {CMD_READ_QUAD_OUTPUT_FAST, CMD_READ_QUAD_OUTPUT_FAST_4B},
+ {CMD_READ_QUAD_IO_FAST, CMD_READ_QUAD_IO_FAST_4B},
+ };
+
+ return spi_flash_convert_opcode(opcode, spi_flash_3to4_read,
+
[U-Boot] [PATCH 5/8] sf: add 'addr_len' member to 'struct spi_flash'
This is a transitional patch to prepare the SPI FLASH sub-system to
support the 4-byte address instruction set later.
For now, flash->addr_len is always set to SPI_FLASH_3B_ADDR_LEN.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/spi_flash.c | 13 -
include/spi_flash.h | 2 ++
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index ec998166017d..c5e00772f241 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -322,7 +322,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len)
}
}
- spi_flash_command_init(&cmd, flash->erase_cmd, SPI_FLASH_3B_ADDR_LEN,
+ spi_flash_command_init(&cmd, flash->erase_cmd, flash->addr_len,
SPI_FCMD_ERASE);
while (len) {
erase_addr = offset;
@@ -377,7 +377,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
}
}
- spi_flash_command_init(&cmd, flash->write_cmd, SPI_FLASH_3B_ADDR_LEN,
+ spi_flash_command_init(&cmd, flash->write_cmd, flash->addr_len,
SPI_FCMD_WRITE);
cmd.proto = flash->write_proto;
for (actual = 0; actual < len; actual += chunk_len) {
@@ -481,7 +481,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
return 0;
}
- spi_flash_command_init(&cmd, flash->read_cmd, SPI_FLASH_3B_ADDR_LEN,
+ spi_flash_command_init(&cmd, flash->read_cmd, flash->addr_len,
SPI_FCMD_READ);
cmd.proto = flash->read_proto;
cmd.num_wait_states = flash->dummy_byte * 8;
@@ -529,7 +529,7 @@ static int sst_byte_write(struct spi_flash *flash, u32
offset, const void *buf)
int ret;
u8 sr = 0xFFu;
- spi_flash_command_init(&cmd, CMD_SST_BP, SPI_FLASH_3B_ADDR_LEN,
+ spi_flash_command_init(&cmd, CMD_SST_BP, flash->addr_len,
SPI_FCMD_WRITE);
cmd.addr = offset;
cmd.data_len = 1;
@@ -580,7 +580,7 @@ int sst_write_wp(struct spi_flash *flash, u32 offset,
size_t len,
if (ret)
goto done;
- spi_flash_command_init(&cmd, CMD_SST_AAI_WP, SPI_FLASH_3B_ADDR_LEN,
+ spi_flash_command_init(&cmd, CMD_SST_AAI_WP, flash->addr_len,
SPI_FCMD_WRITE);
cmd.addr = offset;
cmd.data_len = 2;
@@ -1103,6 +1103,9 @@ int spi_flash_scan(struct spi_flash *flash)
flash->flags |= SNOR_F_USE_FSR;
#endif
+ /* Set the address length */
+ flash->addr_len = SPI_FLASH_3B_ADDR_LEN;
+
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
ret = read_bar(flash, info);
diff --git a/include/spi_flash.h b/include/spi_flash.h
index ac2b37f0202f..9168fca8f96d 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -44,6 +44,7 @@ struct spi_slave;
* @bank_read_cmd: Bank read cmd
* @bank_write_cmd:Bank write cmd
* @bank_curr: Current flash bank
+ * @addr_len: Number of bytes for the address
* @erase_cmd: Erase cmd 4K, 32K, 64K
* @read_cmd: Read cmd - Array Fast, Extn read and quad read.
* @write_cmd: Write cmd - page and quad program.
@@ -81,6 +82,7 @@ struct spi_flash {
u8 bank_write_cmd;
u8 bank_curr;
#endif
+ u8 addr_len;
u8 erase_cmd;
u8 read_cmd;
u8 write_cmd;
--
2.7.4
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[U-Boot] [PATCH 7/8] sf: add support to Microchip SST26 QSPI memories
This patch adds support to Microchip SST26 QSPI memories.
Erase blocks are protected at power up and must be unlocked first before
being erased then programmed.
Also, the erase block sizes are not uniform. The memory layout is uniform
only for the 4K sector blocks. The 64K Block Erase (D8h) op code cannot be
used as currently done by the SPI FLASH sub-system.
The 4K Sector Erase (20h) op code should be chosen instead even if
CONFIG_SPI_FLASH_USE_4K_SECTORS is not set.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/sf_internal.h | 3 +++
drivers/mtd/spi/spi_flash.c | 33 ++---
drivers/mtd/spi/spi_flash_ids.c | 5 +
3 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 30994f9f460c..4354a2aa532f 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -104,6 +104,7 @@ enum spi_nor_option_flags {
#ifdef CONFIG_SPI_FLASH_SST
# define CMD_SST_BP0x02/* Byte Program */
# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word
Program */
+# define CMD_SST_ULBPR 0x98/* Global Block Protection Unlock */
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
@@ -151,6 +152,8 @@ struct spi_flash_info {
* 4-byte address instruction set
* NOT supported
*/
+#define SECT_4K_ONLY BIT(9) /* use only CMD_ERASE_4K */
+#define SST_ULBPR BIT(10) /* use SST unlock block protection */
};
extern const struct spi_flash_info spi_flash_ids[];
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 695c8555db3f..307e4140826b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -891,6 +891,22 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t
len)
}
#endif
+#ifdef CONFIG_SPI_FLASH_SST
+static int sst26_unlock(struct spi_flash *flash)
+{
+ struct spi_flash_command cmd;
+ int ret;
+
+ spi_flash_command_init(&cmd, CMD_SST_ULBPR, 0, SPI_FCMD_WRITE_REG);
+ ret = spi_flash_write_common(flash, &cmd);
+ if (ret) {
+ debug("SF: SST26 is still locked (read-only)\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX
static int macronix_quad_enable(struct spi_flash *flash)
@@ -920,7 +936,8 @@ static int macronix_quad_enable(struct spi_flash *flash)
}
#endif
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) ||\
+defined(CONFIG_SPI_FLASH_SST)
static int spansion_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
@@ -981,9 +998,11 @@ static int set_quad_mode(struct spi_flash *flash,
case SPI_FLASH_CFI_MFR_MACRONIX:
return macronix_quad_enable(flash);
#endif
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) ||\
+defined(CONFIG_SPI_FLASH_SST)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND:
+ case SPI_FLASH_CFI_MFR_SST:
return spansion_quad_enable(flash);
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
@@ -1040,6 +1059,11 @@ int spi_flash_scan(struct spi_flash *flash)
JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
write_sr(flash, 0);
+#ifdef CONFIG_SPI_FLASH_SST
+ if (info->flags & SST_ULBPR)
+ sst26_unlock(flash);
+#endif
+
flash->name = info->name;
flash->memory_map = spi->memory_map;
@@ -1099,7 +1123,10 @@ int spi_flash_scan(struct spi_flash *flash)
flash->erase_size = 4096 << flash->shift;
} else
#endif
- {
+ if (info->flags & SECT_4K_ONLY) {
+ flash->erase_cmd = CMD_ERASE_4K;
+ flash->erase_size = 4096 << flash->shift;
+ } else {
flash->erase_cmd = CMD_ERASE_64K;
flash->erase_size = flash->sector_size;
}
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index edca94e30cf0..3d3132bc3b22 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -146,6 +146,11 @@ const struct spi_flash_info spi_flash_ids[] = {
{"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K |
SST_WR) },
{"sst25wf040b",INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) },
{"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024,16, SECT_4K |
SST_WR) },
+ {"sst26vf016b",INFO(0xbf2641, 0x0, 4 * 1024, 512, SECT_4K_ONLY
| SST_ULBPR | RD_FULL) },
+ {"sst26vf032b",INFO(0xbf2642, 0x0, 4 * 1024, 1024, SECT_4K_ONLY
| SST_ULBPR | RD_FULL) },
+ {"
Re: [U-Boot] [PATCH 09/26] dm: video: tegra124: Convert to livetree
On Fri, 19 May 2017 08:30:52 -0600 Simon Glass s...@chromium.org wrote: > Update these drivers to support a live device tree. > > Signed-off-by: Simon Glass > --- > > drivers/video/tegra124/display.c | 8 +++- > drivers/video/tegra124/dp.c | 3 +-- > drivers/video/tegra124/sor.c | 25 +++-- > 3 files changed, 11 insertions(+), 25 deletions(-) Acked-by: Anatolij Gustschin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/8] sf: differentiate Page Program 1-1-4 and 1-4-4
This patch simply renames the ambiguous CMD_QUAD_PAGE_PROGRAM macro
into the more explicit CMD_PAGE_PROGRAM_1_1_4.
Also it defines the CMD_PAGE_PROGRAM_1_4_4 macro to the standard 38h op
code.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/sf_internal.h | 3 ++-
drivers/mtd/spi/spi_flash.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 5c551089d673..8b8c951bcc55 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -48,7 +48,8 @@ enum spi_nor_option_flags {
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_WRITE_ENABLE 0x06
-#define CMD_QUAD_PAGE_PROGRAM 0x32
+#define CMD_PAGE_PROGRAM_1_1_4 0x32
+#define CMD_PAGE_PROGRAM_1_4_4 0x38
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7e35fb9f4802..ec998166017d 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1060,7 +1060,7 @@ int spi_flash_scan(struct spi_flash *flash)
/* Look for write commands */
if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD) {
- flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
+ flash->write_cmd = CMD_PAGE_PROGRAM_1_1_4;
flash->write_proto = SPI_FPROTO_1_1_4;
} else {
/* Go for default supported write cmd */
--
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[U-Boot] [PATCH 8/8] sf: add driver for Atmel QSPI controller
This patch adds support to the Atmel Quad SPI controller.
Signed-off-by: Cyrille Pitchen
---
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/atmel_qspi.c | 404 +++
drivers/spi/atmel_qspi.h | 169
4 files changed, 581 insertions(+)
create mode 100644 drivers/spi/atmel_qspi.c
create mode 100644 drivers/spi/atmel_qspi.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f3f7dbe0897b..73f2e5c26bfb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -32,6 +32,13 @@ config ATH79_SPI
uses driver model and requires a device tree binding to operate.
please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+config ATMEL_QSPI
+ bool "Atmel QSPI driver"
+ depends on ARCH_AT91
+ help
+ Enable the Ateml Quad-SPI (QSPI) driver. This driver can only be
+ used to access SPI NOR flashes.
+
config ATMEL_SPI
bool "Atmel SPI driver"
depends on ARCH_AT91
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c090562c7732..af75fa41c82f 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -18,6 +18,7 @@ endif
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
+obj-$(CONFIG_ATMEL_QSPI) += atmel_qspi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
diff --git a/drivers/spi/atmel_qspi.c b/drivers/spi/atmel_qspi.c
new file mode 100644
index ..6c265d0a4714
--- /dev/null
+++ b/drivers/spi/atmel_qspi.c
@@ -0,0 +1,404 @@
+/*
+ * Copyright (C) 2017 Atmel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "atmel_qspi.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void atmel_qspi_memcpy_fromio(void *dst, unsigned long src, size_t len)
+{
+ u8 *d = (u8 *)dst;
+
+ while (len--) {
+ *d++ = readb(src);
+ src++;
+ }
+}
+
+static void atmel_qspi_memcpy_toio(unsigned long dst, const void *src,
+ size_t len)
+{
+ const u8 *s = (const u8 *)src;
+
+ while (len--) {
+ writeb(*s, dst);
+ dst++;
+ s++;
+ }
+}
+
+static int atmel_qspi_set_ifr_tfrtype(u8 flags, u32 *ifr)
+{
+ u32 ifr_tfrtype;
+
+ switch (flags & SPI_FCMD_TYPE) {
+ case SPI_FCMD_READ:
+ ifr_tfrtype = QSPI_IFR_TFRTYPE_READ_MEMORY;
+ break;
+
+ case SPI_FCMD_WRITE:
+ ifr_tfrtype = QSPI_IFR_TFRTYPE_WRITE_MEMORY;
+ break;
+
+ case SPI_FCMD_ERASE:
+ case SPI_FCMD_WRITE_REG:
+ ifr_tfrtype = QSPI_IFR_TFRTYPE_WRITE;
+ break;
+
+ case SPI_FCMD_READ_REG:
+ ifr_tfrtype = QSPI_IFR_TFRTYPE_READ;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ *ifr = (*ifr & ~QSPI_IFR_TFRTYPE) | ifr_tfrtype;
+ return 0;
+}
+
+static int atmel_qpsi_set_ifr_width(enum spi_flash_protocol proto, u32 *ifr)
+{
+ u32 ifr_width;
+
+ switch (proto) {
+ case SPI_FPROTO_1_1_1:
+ ifr_width = QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
+ break;
+
+ case SPI_FPROTO_1_1_2:
+ ifr_width = QSPI_IFR_WIDTH_DUAL_OUTPUT;
+ break;
+
+ case SPI_FPROTO_1_2_2:
+ ifr_width = QSPI_IFR_WIDTH_DUAL_IO;
+ break;
+
+ case SPI_FPROTO_2_2_2:
+ ifr_width = QSPI_IFR_WIDTH_DUAL_CMD;
+ break;
+
+ case SPI_FPROTO_1_1_4:
+ ifr_width = QSPI_IFR_WIDTH_QUAD_OUTPUT;
+ break;
+
+ case SPI_FPROTO_1_4_4:
+ ifr_width = QSPI_IFR_WIDTH_QUAD_IO;
+ break;
+
+ case SPI_FPROTO_4_4_4:
+ ifr_width = QSPI_IFR_WIDTH_QUAD_CMD;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ *ifr = (*ifr & ~QSPI_IFR_WIDTH) | ifr_width;
+ return 0;
+}
+
+static int atmel_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ /* This controller can only be used with SPI NOR flashes. */
+ return -EINVAL;
+}
+
+static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
+{
+ struct atmel_qspi_priv *aq = dev_get_priv(bus);
+ u32 scr, scbr, mask, new_value;
+
+ /* Compute the QSPI baudrate */
+ scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
+ if (scbr > 0)
+ scbr--;
+
+ new_value = QSPI_SCR_SCBR_(scbr);
+ mask = QSPI_SCR_SCBR;
+
+ scr = qspi_readl(aq, QSPI_SCR);
+ if ((scr & mask) == new_value)
+ return 0;
+
+ scr = (scr & ~mas
[U-Boot] [PATCH 3/8] sf: select the relevant SPI flash protocol for read and write commands
SPI controller drivers should not check the instruction op code byte to
guess which SPI x-y-z protocol is to be used for Fast Read or Page Program
operations.
Indeed, the op code values are not so reliable. For instance, the 32h op
code is generally used for Page Program 1-1-4 operations. However
Microchip SST26 memories use this 32h op code for their Page Program 1-4-4
operations. There are many other examples of those SPI flash manufacturer
quirks.
Instead, the SPI FLASH sub-system now fills the 'proto' member
of 'struct spi_flash_command' with flash->read_proto for Fast Read
operations and flash->write_proto for Page Program operations.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/spi_flash.c | 24
include/spi_flash.h | 4
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index d0634e5b28c7..7e35fb9f4802 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -379,6 +379,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
spi_flash_command_init(&cmd, flash->write_cmd, SPI_FLASH_3B_ADDR_LEN,
SPI_FCMD_WRITE);
+ cmd.proto = flash->write_proto;
for (actual = 0; actual < len; actual += chunk_len) {
write_addr = offset;
@@ -482,6 +483,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
spi_flash_command_init(&cmd, flash->read_cmd, SPI_FLASH_3B_ADDR_LEN,
SPI_FCMD_READ);
+ cmd.proto = flash->read_proto;
cmd.num_wait_states = flash->dummy_byte * 8;
while (len) {
read_addr = offset;
@@ -1045,24 +1047,30 @@ int spi_flash_scan(struct spi_flash *flash)
/* Look for read commands */
flash->read_cmd = CMD_READ_ARRAY_FAST;
- if (spi->mode & SPI_RX_SLOW)
+ flash->read_proto = SPI_FPROTO_1_1_1;
+ if (spi->mode & SPI_RX_SLOW) {
flash->read_cmd = CMD_READ_ARRAY_SLOW;
- else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
+ } else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD) {
flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
- else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
+ flash->read_proto = SPI_FPROTO_1_1_4;
+ } else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL) {
flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
+ flash->read_proto = SPI_FPROTO_1_1_2;
+ }
/* Look for write commands */
- if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
+ if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD) {
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
- else
+ flash->write_proto = SPI_FPROTO_1_1_4;
+ } else {
/* Go for default supported write cmd */
flash->write_cmd = CMD_PAGE_PROGRAM;
+ flash->write_proto = SPI_FPROTO_1_1_1;
+ }
/* Set the quad enable bit - only for quad commands */
- if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
- (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
- (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
+ if (spi_flash_protocol_get_data_nbits(flash->read_proto) == 4 ||
+ spi_flash_protocol_get_data_nbits(flash->write_proto) == 4) {
ret = set_quad_mode(flash, info);
if (ret) {
debug("SF: Fail to set QEB for %02x\n",
diff --git a/include/spi_flash.h b/include/spi_flash.h
index be2fe3f84cb9..ac2b37f0202f 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -48,6 +48,8 @@ struct spi_slave;
* @read_cmd: Read cmd - Array Fast, Extn read and quad read.
* @write_cmd: Write cmd - page and quad program.
* @dummy_byte:Dummy cycles for read operation.
+ * @read_proto:SPI x-y-z protocol for flash read ops
+ * @write_proto: SPI x-y-z protocol for flash write ops
* @memory_map:Address of read-only SPI flash access
* @flash_lock:lock a region of the SPI Flash
* @flash_unlock: unlock a region of the SPI Flash
@@ -83,6 +85,8 @@ struct spi_flash {
u8 read_cmd;
u8 write_cmd;
u8 dummy_byte;
+ enum spi_flash_protocol read_proto;
+ enum spi_flash_protocol write_proto;
void *memory_map;
--
2.7.4
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[U-Boot] [PATCH v2 0/4] sunxi: video: Add support for TV (composite) output on H3/H5
This series implements support for composite output. Driver is
implemented using DM video framework and heavily reuse code written for
older SoCs. Additionally, driver also implements plug detection.
All patches in first version were merged except the last one. Because
this version only split one patch into multiple and doesn't do any code
change, I didn't write any changelog.
Patch 1 renames tve.c to tve_common.c to better describe it's intention.
Patch 2 adds TVE base address.
Patch 3 adds support for TVE to DE2 driver.
Patch 4 finally adds TVE driver for H3 and H5.
Everything was tested on H3 (OrangePi 2) and H5 (OrangePi PC2) board.
Since this series changes video driver for old SoCs, I would kindly ask
that someone tests if everything still works as expected.
Best regards,
Jernej
Jernej Skrabec (4):
sunxi: video: Rename tve.c to tve_common.c
sunxi: Add base address for TV encoder
sunxi: video: Add support for CSC and TVE to DE2 driver
sunxi: video: Add H3/H5 TV out driver
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 10 ++
arch/arm/include/asm/arch-sunxi/display2.h | 17 +++
arch/arm/include/asm/arch-sunxi/tve.h | 17 ++-
drivers/video/sunxi/Makefile| 4 +-
drivers/video/sunxi/sunxi_de2.c | 60 ---
drivers/video/sunxi/sunxi_tve.c | 156
drivers/video/sunxi/{tve.c => tve_common.c} | 6 +-
7 files changed, 252 insertions(+), 18 deletions(-)
create mode 100644 drivers/video/sunxi/sunxi_tve.c
rename drivers/video/sunxi/{tve.c => tve_common.c} (95%)
--
2.13.0
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[U-Boot] [PATCH v2 1/4] sunxi: video: Rename tve.c to tve_common.c
In order to avoid future confusion with similary named files, rename
tve.c to tve_common.c. New name better represents the fact that this file
holds code which can be and will be shared between multiple drivers.
Signed-off-by: Jernej Skrabec
---
drivers/video/sunxi/Makefile| 2 +-
drivers/video/sunxi/{tve.c => tve_common.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/video/sunxi/{tve.c => tve_common.c} (100%)
diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile
index dbaab61b59..0d64c2021f 100644
--- a/drivers/video/sunxi/Makefile
+++ b/drivers/video/sunxi/Makefile
@@ -5,5 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve.o ../videomodes.o
+obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o
../videomodes.o
obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
diff --git a/drivers/video/sunxi/tve.c b/drivers/video/sunxi/tve_common.c
similarity index 100%
rename from drivers/video/sunxi/tve.c
rename to drivers/video/sunxi/tve_common.c
--
2.13.0
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[U-Boot] [PATCH v2 4/4] sunxi: video: Add H3/H5 TV out driver
This commit adds support for TV (composite) output.
Because there is no mechanism to select TV standard, PAL is hardcoded.
Signed-off-by: Jernej Skrabec
---
arch/arm/include/asm/arch-sunxi/tve.h | 17 +++-
drivers/video/sunxi/Makefile | 2 +-
drivers/video/sunxi/sunxi_tve.c | 156 ++
drivers/video/sunxi/tve_common.c | 6 +-
4 files changed, 176 insertions(+), 5 deletions(-)
create mode 100644 drivers/video/sunxi/sunxi_tve.c
diff --git a/arch/arm/include/asm/arch-sunxi/tve.h
b/arch/arm/include/asm/arch-sunxi/tve.h
index 41a14a68e4..ff34bbbc12 100644
--- a/arch/arm/include/asm/arch-sunxi/tve.h
+++ b/arch/arm/include/asm/arch-sunxi/tve.h
@@ -45,7 +45,9 @@ struct sunxi_tve_reg {
u32 csc_reg1; /* 0x044 */
u32 csc_reg2; /* 0x048 */
u32 csc_reg3; /* 0x04c */
- u8 res1[0xb0]; /* 0x050 */
+ u8 res1[0xa8]; /* 0x050 */
+ u32 auto_detect_cfg0; /* 0x0f8 */
+ u32 auto_detect_cfg1; /* 0x0fc */
u32 color_burst;/* 0x100 */
u32 vsync_num; /* 0x104 */
u32 notch_freq; /* 0x108 */
@@ -62,6 +64,10 @@ struct sunxi_tve_reg {
u32 slave_para; /* 0x134 */
u32 cfg1; /* 0x138 */
u32 cfg2; /* 0x13c */
+ u8 res2[0x1c4]; /* 0x140 */
+ u32 calibration;/* 0x304 */
+ u8 res3[0x4]; /* 0x308 */
+ u32 unknown3; /* 0x30c */
};
/*
@@ -79,12 +85,14 @@ struct sunxi_tve_reg {
#define SUNXI_TVE_CFG0_PAL 0x07030001
#define SUNXI_TVE_CFG0_NTSC0x0703
#define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7
-#ifdef CONFIG_MACH_SUN5I
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUNXI_H3_H5)
#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009
#else
#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008
#endif
+#define SUNXI_TVE_DAC_CFG0_DETECTION 0x433f0289
#define SUNXI_TVE_FILTER_COMPOSITE 0x0120
+#define SUNXI_TVE_CHROMA_FREQ_PAL 0x2a098acb
#define SUNXI_TVE_CHROMA_FREQ_PAL_M0x21e6efe3
#define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446
#define SUNXI_TVE_PORCH_NUM_PAL0x008a0018
@@ -105,6 +113,8 @@ struct sunxi_tve_reg {
#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3
#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d)((d) * 8)
#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8))
+#define SUNXI_TVE_AUTO_DETECT_CFG0 0x0280
+#define SUNXI_TVE_AUTO_DETECT_CFG1 0x028F00FF
#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31)
#define SUNXI_TVE_CSC_REG0 0x08440832
#define SUNXI_TVE_CSC_REG1 0x3b6dace1
@@ -124,6 +134,9 @@ struct sunxi_tve_reg {
#define SUNXI_TVE_RESYNC_NUM_PAL 0x800d000c
#define SUNXI_TVE_RESYNC_NUM_NTSC 0x000e000c
#define SUNXI_TVE_SLAVE_PARA_COMPOSITE 0x
+#define SUNXI_TVE_CALIBRATION_H3 0x02000c00
+#define SUNXI_TVE_CALIBRATION_H5 0x0285
+#define SUNXI_TVE_UNKNOWN3_H5 0x00101110
void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode);
void tvencoder_enable(struct sunxi_tve_reg * const tve);
diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile
index 0d64c2021f..e63c1d65bc 100644
--- a/drivers/video/sunxi/Makefile
+++ b/drivers/video/sunxi/Makefile
@@ -6,4 +6,4 @@
#
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o
../videomodes.o
-obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
+obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o sunxi_tve.o lcdc.o
tve_common.o ../dw_hdmi.o
diff --git a/drivers/video/sunxi/sunxi_tve.c b/drivers/video/sunxi/sunxi_tve.c
new file mode 100644
index 00..95f54bbaf7
--- /dev/null
+++ b/drivers/video/sunxi/sunxi_tve.c
@@ -0,0 +1,156 @@
+/*
+ * Allwinner TVE driver
+ *
+ * (C) Copyright 2017 Jernej Skrabec
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int sunxi_tve_get_plug_in_status(void)
+{
+ struct sunxi_tve_reg * const tve =
+ (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
+ u32 status;
+
+ status = readl(&tve->auto_detect_status) &
+ SUNXI_TVE_AUTO_DETECT_STATUS_MASK(0);
+
+ return status == SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED;
+}
+
+static int sunxi_tve_wait_for_hpd(void)
+{
+ struct sunxi_tve_reg * const tve =
+ (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
+ ulong start;
+
+ /* enable auto detection */
+ writel(SUNXI_TVE_DAC_CFG0
[U-Boot] [PATCH v2 2/4] sunxi: Add base address for TV encoder
This commit adds TVE base address for Allwinner H3 and H5 SoCs. Signed-off-by: Jernej Skrabec --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 6aa5e91ada..2419062d45 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -34,7 +34,9 @@ #define SUNXI_MS_BASE 0x01c07000 #define SUNXI_TVD_BASE 0x01c08000 #define SUNXI_CSI0_BASE0x01c09000 +#ifndef CONFIG_MACH_SUNXI_H3_H5 #define SUNXI_TVE0_BASE0x01c0a000 +#endif #define SUNXI_EMAC_BASE0x01c0b000 #define SUNXI_LCD0_BASE0x01c0C000 #define SUNXI_LCD1_BASE0x01c0d000 @@ -161,10 +163,18 @@ defined(CONFIG_MACH_SUN50I) /* module sram */ #define SUNXI_SRAM_C_BASE 0x01d0 +#ifndef CONFIG_MACH_SUN8I_H3 #define SUNXI_DE_FE0_BASE 0x01e0 +#else +#define SUNXI_TVE0_BASE0x01e0 +#endif #define SUNXI_DE_FE1_BASE 0x01e2 #define SUNXI_DE_BE0_BASE 0x01e6 +#ifndef CONFIG_MACH_SUN50I_H5 #define SUNXI_DE_BE1_BASE 0x01e4 +#else +#define SUNXI_TVE0_BASE0x01e4 +#endif #define SUNXI_MP_BASE 0x01e8 #define SUNXI_AVG_BASE 0x01ea -- 2.13.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/4] sunxi: video: Add support for CSC and TVE to DE2 driver
Extend DE2 driver with support for TVE driver, which will be added in
next commit. TVE unit expects data to be in YUV format, so CSC support
is also added here.
Note that HDMI driver has higher priority, so TV out is not probed if
HDMI monitor is detected.
Signed-off-by: Jernej Skrabec
---
arch/arm/include/asm/arch-sunxi/display2.h | 17 +
drivers/video/sunxi/sunxi_de2.c| 60 --
2 files changed, 65 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/display2.h
b/arch/arm/include/asm/arch-sunxi/display2.h
index b5875f9605..359cacd90b 100644
--- a/arch/arm/include/asm/arch-sunxi/display2.h
+++ b/arch/arm/include/asm/arch-sunxi/display2.h
@@ -90,6 +90,23 @@ struct de_ui {
u32 ovl_size;
};
+struct de_csc {
+ u32 csc_ctl;
+ u8 res[0xc];
+ u32 coef11;
+ u32 coef12;
+ u32 coef13;
+ u32 coef14;
+ u32 coef21;
+ u32 coef22;
+ u32 coef23;
+ u32 coef24;
+ u32 coef31;
+ u32 coef32;
+ u32 coef33;
+ u32 coef34;
+};
+
/*
* DE register constants.
*/
diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c
index 9a32c3a020..ee67764ac5 100644
--- a/drivers/video/sunxi/sunxi_de2.c
+++ b/drivers/video/sunxi/sunxi_de2.c
@@ -56,7 +56,7 @@ static void sunxi_de2_composer_init(void)
}
static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
- int bpp, ulong address)
+ int bpp, ulong address, bool is_composite)
{
ulong de_mux_base = (mux == 0) ?
SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
@@ -72,6 +72,9 @@ static void sunxi_de2_mode_set(int mux, const struct
display_timing *mode,
(struct de_ui *)(de_mux_base +
SUNXI_DE2_MUX_CHAN_REGS +
SUNXI_DE2_MUX_CHAN_SZ * 1);
+ struct de_csc * const de_csc_regs =
+ (struct de_csc *)(de_mux_base +
+ SUNXI_DE2_MUX_DCSC_REGS);
u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
int channel;
u32 format;
@@ -128,7 +131,27 @@ static void sunxi_de2_mode_set(int mux, const struct
display_timing *mode,
writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
- writel(0, de_mux_base + SUNXI_DE2_MUX_DCSC_REGS);
+
+ if (is_composite) {
+ /* set CSC coefficients */
+ writel(0x107, &de_csc_regs->coef11);
+ writel(0x204, &de_csc_regs->coef12);
+ writel(0x64, &de_csc_regs->coef13);
+ writel(0x4200, &de_csc_regs->coef14);
+ writel(0x1f68, &de_csc_regs->coef21);
+ writel(0x1ed6, &de_csc_regs->coef22);
+ writel(0x1c2, &de_csc_regs->coef23);
+ writel(0x20200, &de_csc_regs->coef24);
+ writel(0x1c2, &de_csc_regs->coef31);
+ writel(0x1e87, &de_csc_regs->coef32);
+ writel(0x1fb7, &de_csc_regs->coef33);
+ writel(0x20200, &de_csc_regs->coef34);
+
+ /* enable CSC unit */
+ writel(1, &de_csc_regs->csc_ctl);
+ } else {
+ writel(0, &de_csc_regs->csc_ctl);
+ }
switch (bpp) {
case 16:
@@ -153,7 +176,7 @@ static void sunxi_de2_mode_set(int mux, const struct
display_timing *mode,
static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
enum video_log2_bpp l2bpp,
- struct udevice *disp, int mux)
+ struct udevice *disp, int mux, bool is_composite)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct display_timing timing;
@@ -183,7 +206,7 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
}
sunxi_de2_composer_init();
- sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase);
+ sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
ret = display_enable(disp, 1 << l2bpp, &timing);
if (ret) {
@@ -204,7 +227,6 @@ static int sunxi_de2_probe(struct udevice *dev)
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct udevice *disp;
int ret;
- int mux;
/* Before relocation we don't need to do anything */
if (!(gd->flags & GD_FLG_RELOC))
@@ -212,17 +234,31 @@ static int sunxi_de2_probe(struct udevice *dev)
ret = uclass_find_device_by_name(UCLASS_DISPLAY,
"sunxi_dw_hdmi", &disp);
+ if (!ret) {
+ int mux;
+ if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
+ mux = 0;
+ else
+ mux = 1;
+
+ ret = sunxi_de2_
Re: [U-Boot] [PATCH] pico-imx7d: Add initial support
Hi Stefano, Jagan, I have been trying to add the dts support for this board but I could not make Ethernet, I2C and PMIC support work using dts. I am still trying to add this support but I don't know how much time it can take. I'm new to U-Boot. Can you please consider applying the original patch? Thanks in advance! Regards, Vanessa Maegima From: Vanessa Ayumi Maegima Sent: Tuesday, May 9, 2017 10:45:20 AM To: Stefano Babic Cc: Vanessa Maegima; Jagan Teki; Fabio Estevam; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH] pico-imx7d: Add initial support Hi Stefano, Jagan, On Tue, May 9, 2017 at 5:23 AM, Stefano Babic mailto:sba...@denx.de>> wrote: Hi Jagan, Vanessa, On 08/05/2017 21:49, Jagan Teki wrote: > Though the code look good and similar approach of existing boards, I'm > little concern of continue the same legacy and w/o trying new feature > like fdt. > > We've few i.MX boards which uses fdt support please refer the same. > I'm commenting below what all the code can removed ans use it with > dts. It is worth a couple og thoughts. Even if the path to a u-boot configured via fdt is clear, this should be done if this does not block other feature that are maybe important for the project - and this is known only by the board maintainer. I do not talk about this particular board - the issue is general and I remain general. For example, it looks to me that having a single binary for multiple variants of the board cannot be easy reached. There is a DTS for each variant and this means a binary for each of them. This is ok for some projects, it is not ok for some other ones. And I cannot constrain people to go into a direction when they lose features. I did quite the same approach with SPL / u-boot.imx. I understand that some projects want to stick with a single binary instead of two, it remains a decision of board maintainer. No block on my site. Last concern is related to size in SPL. imx6.Solo has just 64Kb RAM, but less are available because a part is reserved to the BootRom (or HAB, or whatever). And putting a lot of stuff inside SPL is not possible, then. After saying all this, back to the specific case. Vanessa, you are not using SPL and you have put the RAM configuration into the DCD table. Then it is everything fix and you cannot have more variants. That means your board has not the drawbacks I mentioned above. It could be a good candidate to use dts. What do you think ? Best regards, Stefano Babic I will add the dts support and send a v2. Thanks for the review! Best Regards, Vanessa Maegima ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] dts: socfpga: Add trigger-address property to QSPI device
On 5/19/2017 1:09 AM , Marek Vasut wrote:
> On 05/18/2017 08:26 PM, Rush, Jason A. wrote:
>> Add the 'cdns,trigger-address' property to the cadence QSPI device
>> node for Altera SoC devices.
>>
>> Signed-off-by: Jason A. Rush
>
> +CC Dinh, is that address correct ? I think there was some discussion.
There was some discussion on this before here:
https://lists.denx.de/pipermail/u-boot/2017-March/282882.html
> Jason, I'd rather prefer if you sent this as a series (with git
> send-email) not as a set of separate patches. Also, I'd prefer if you
> would just sync up the whole block with standard agreed-upon (linux)
> DT bindings and then ev. tweak the driver.
>
I can't use git send-email from this email account, but I can switch to my
personal gmail account which should work. I'll CC my other account and
switch to using that from now on.
I can try and sync up the DT bindings with Linux, most of the parameters
should be easy enough to convert. However, there are two bindings that
the u-boot driver defines but Linux looks them up from a table or from
querying the flash part ("page-size" and "block-size"), and one binding
Linux defines where u-boot calculates ("cdns,read-delay").
It would require significant changes to the u-boot driver to adopt these
3 bindings, would it be acceptable to align all the other DT bindings, with
the exception of those 3 bindings?
--
Regards,
Jason Rush
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Re: [U-Boot] [PATCH v1 0/4] Add FIT support for falcon boot
On 05/19/2017 02:56 AM, Andre Przywara wrote: > Hi York, > > On 16/05/17 16:54, york sun wrote: >> On 05/15/2017 10:42 PM, Lokesh Vutla wrote: >>> + Andre >>> >>> >>> On Monday 15 May 2017 09:31 PM, York Sun wrote: This patch set adds FIT support for falcon boot. GZIP is enabled to supported compressed image. >>> >>> Did you get a chance to look at Andre's "SPL: extend FIT loading >>> support"[1] patch series? This series addresses similar problem in a >>> more generic way. >>> >>> [1] >>> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.mail-archive.com%2Fu-boot%40lists.denx.de%2Fmsg246692.html&data=01%7C01%7Cyork.sun%40nxp.com%7C63ec3a7e245445e2253d08d49c1e542b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=XrCyv6JBg02fwP7MEMo1hg8rVCOGnEQ741Hs0oLwZVg%3D&reserved=0 >> >> I only received partial patches from Andre's set. Looks like that set >> should cover my changes by supporting multiple images. I was focusing on >> a fast boot path for the past two months. I can rebase my patch once >> Andre's set is merged. > > FYI: My patches have been merged into u-boot-sunxi/master[1], which is > based on origin/master as of earlier this week. > I take it they get merged into origin before -rc1, but meanwhile you > could base on u-boot-sunxi/master. > > Cheers, > Andre. > > [1] > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fgit.denx.de%2F%3Fp%3Du-boot%2Fu-boot-sunxi.git%3Ba%3Dshortlog&data=01%7C01%7Cyork.sun%40nxp.com%7C15aaad5759e8473cc8ca08d49e9d5f11%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=yjdSr%2BloxYTaLql0nI2rfeLCVS3upXK7%2BO8IapUNkNA%3D&reserved=0 > Thanks for the update. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] Kconfig: Add support for hash and sha1sum commands
Currently these (board agnostic) commands cannot be selected using menuconfig and friends. Fix this the obvious way. Signed-off-by: Daniel Thompson --- cmd/Kconfig | 27 +++ 1 file changed, 27 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index d9f7151bacdc..f459f8440346 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -338,6 +338,19 @@ config CMD_CRC32 help Compute CRC32. +config CMD_HASH + bool "hash" + default n + help + Compute a hash using any algorithm supported by hash_lookup_algo(). + +config HASH_VERIFY + bool "hash -v" + default n + depends on CMD_HASH + help + Add -v option to verify data against a hash. + config CMD_MD5SUM bool "md5sum" default n @@ -352,6 +365,20 @@ config MD5SUM_VERFIY help Add -v option to verify data against an MD5 checksum. +config CMD_SHA1SUM + bool "sha1sum" + default n + select SHA1 + help + Compute SHA1 checksum. + +config SHA1SUM_VERFIY + bool "sha1sum -v" + default n + depends on CMD_SHA1SUM + help + Add -v option to verify data against an SHA1 checksum. + config LOOPW bool "loopw" help -- 2.9.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 00/18] GPT over MTD
Thanks Maxime for the feedback, > -Original Message- > From: Maxime Ripard [mailto:maxime.rip...@free-electrons.com] > Sent: mardi 16 mai 2017 11:29 > > On Fri, May 12, 2017 at 04:09:08PM +, Patrick DELAUNAY wrote: > > Hi Maxime > > > > > From: Maxime Ripard [mailto:maxime.rip...@free-electrons.com] > > > Sent: jeudi 11 mai 2017 16:46 > > > > > > On Thu, May 11, 2017 at 09:19:16AM +, Patrick DELAUNAY wrote: > > > > Hi Maxime, > > > > > > > > > From: Maxime Ripard [mailto:maxime.rip...@free-electrons.com] > > > > > Sent: jeudi 11 mai 2017 10:20 > > > > > > > > > > Hi, > > > > > > > > > > On Thu, May 11, 2017 at 09:51:50AM +0200, Patrick Delaunay wrote: > > > > > > I have a request to support GPT over MTD to have the MTD > > > > > > informations without U-Boot > > > environment(CONFIG_ENV_IS_NOWHERE is a > > > > > > other requirement of my project to manage several board > > > > > > configuration with the same defconfig; boot from NAND or NOR > > > > > > or > > > SDCARD). > > > > > > > > > > What would happen if you have a bad block in the middle of the > > > > > primary or secondary GPT headers (or both)? > > > > > > > > > > Maxime > > > > > > > > > > > > > All Bad block are skipped > > > > => primary GPT header is located at the beginning of first good > > > > block => backup GPT header is located at the end the of last good > > > > block > > > > > > > > And gpt create will failed if the erase block command (for primary > > > > or backup GPT) produce a new bad block. > > > > > > Right, but what happens if your block becomes bad or too corrupted > > > after it's been written. > > > > > > You mention in your Drawbacks section that if you erase the block > > > and is now detected to be bad, u-boot will have to act upon it. But > > > that can happen outside of U-Boot as well, or not directly to this > > > block, by reads or writes disturb... In this case, your GPT header > > > is gone, and you have no way to recover from it. > > > > Yes, I known that it is the main issue for my proposal: the management > > of NAND bad block. But it is the same for all the binary in boot > > stage (SPL / U-Boot / U-Boot env) in NAND. > > U-Boot environment can be stored in UBI, and iirc U-Boot too. And usually > the SPLs can be stored at multiple offsets to reduce the risks. So multiple copy for fist boot stage (SPL or other) to reduce the risk And first boot stage need to handle the all NAND constraint. Then for U-Boot SPL, the more simple is to manage next stage in UBIFS volume. And for other first boot stage, multiple copy to avoid all NAND issues (bad block / read disturb) I agree that this architecture simplify the NAND management for SPL and next boot stage and allow improvement for SPL (FALCON mode). > > > For my point of view, erase should done only when GPT header need to > > updated > > > > => for first flashing / complete update of NAND => for the refresh of > > the GPT header So the NAND block becomes BAD only in this 2 cases. > > > > If a read or write disturb for GPT block occur, it should be detected > > by NAND ECC => when unrecoverable error occur for one boot the backup > > GPT header should be used PS: Perhaps need to do something in U-Boot > > to refresh primary GPT header from backup header informaiton > > Like I was saying, the issue really isn't in U-Boot itself, but when U-Boot > isn't > there anymore to deal with those issues. Yes in this case the product is dead > > The expected strategy is to read the boot partitions (all of them , > > GPT header , SPL and U-Boot) periodically outside of U-Boot and if ECC > > read are too important refresh them : > > read the partition and write it again in RAW mode (skip bad block) > > > > So if the partitioning is correctly managed (with reserve some tank of > > good block for partition refresh) The GPT can de refreshed in raw mode > > without breaking the other partition > > > > My idea is : to prepare a partionning with tank of good block > > 3 is this example : > > > > 0 => MBR + primary GPT > > 1 => tank block > > 2 => tank block > > 3 => tank block > > - MTD1 > > 4 => SPL > > 5 => tank block > > 6 => tank block > > 7 => tank block > > --MTD2 > > 8 => U-Boot 1/3 > > 9 => U-Boot 2/3 > > 10 => U-Boot 3/3 > > 11 => tank block > > 12 => tank block > > 13 => tank block > > --MTD3 > > 14 => UBI for kernel > > .. > > N-8 => last usable LBA > > -- > > N-7 => tank block > > N-6 => tank block > > N-5 => tank block > > N-4 => backup GPT > > N-3 => BBT (marked as bad) > > N-2 => BBT (marked as bad) > > N-1 => BBT (marked as bad) > > N => BBT (marked as bad) > > > > Block 0 and N-4 will be refreshed when ECC errors reach the threshold > > for any partition => refresh = read + erase + write (skip bad block) > > => if the erase command detect a bad block, the next tank block is used. > > > > 0 => Bad block (NEW) > > 1 => MBR + primary GPT > > 2 => ta
Re: [U-Boot] [PATCH 3/6] moveconfig: Tidy up the documentation and add hints
2017-05-15 20:47 GMT+09:00 Simon Glass : > @@ -169,7 +182,8 @@ Available options > > -y, --yes > Instead of prompting, automatically go ahead with all operations. This > - includes cleaning up headers and CONFIG_SYS_EXTRA_OPTIONS. > + includes cleaning up header, CONFIG_SYS_EXTRA_OPTIONS, the config > whitelist > + and the README. > I think "headers" is OK as-is. (plural) (Usually, two or more headers are cleaned up) -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] moveconfig: Support providing a path to the defconfig files
> if not matched:
> -print >> sys.stderr, "warning: %s:%d: no defconfig matched '%s'"
> % \
> - (defconfigs_file, i + 1,
> line)
> -
> +print >> sys.stderr, ("warning: %s:%d: no defconfig matched
> '%s'" %
> + (defconfigs_file, i + 1, line))
> defconfigs += matched
>
> # use set() to drop multiple matching
This hunk is an unrelated/unneeded change. Please drop.
--
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH v1 0/8] rockchip: mkimage: refactor rksd/rkspi padding calculation and add dumpimage support
Hi Philipp, Am Mittwoch, 17. Mai 2017, 12:12:51 CEST schrieb Dr. Philipp Tomsich: > What are the requirements for BACK_TO_BROM? > All I can see about how BACK_TO_BROM works is that it needs to save the > register > context on the stack for returning to the ROM, but that seems to be only half > the story. > > Assuming that the header0 structure plays into this, the only significant > change there > is that I don’t set the 'hdr->init_boot_size’ to the maximum SPL size any > longer... Which is most likely the problem. back_to_bootrom-images are concatenated with the spl in front (init_size) and when returned to the bootrom it reads the rest up to init_boot_size into the sdram. So ideally we would return that line back to RK_MAX_BOOT_SIZE (512KB). Somewhat safe value and boards not using back_to_bootrom, as this value really only affects that second stage and not the actual spl loading. I'm sadly away from my boardfarm this and next week, so testing bootloader on my rk3188 board can only happend after that, but I'm somewhat confident that this would solve the problem. Maybe Kever can test that meanwhile. Heiko > > Regards, > Philipp. > > > On 17 May 2017, at 11:50, Kever Yang wrote: > > > > Hi Philipp, > > > > This patch makes all the Rockchip SoCs with BACK_TO_BROM enabled can not > > work, > > > > does the size correct for the SPL correct? > > > > Thanks, > > - Kever > > On 04/17/2017 11:47 PM, Philipp Tomsich wrote: > >> We support booting both from SD/MMC images and SPI images on the > >> RK3399-Q7 for different use-cases (e.g. external boot in development > >> from the SD card, internal boot from MMC or SPI depending on whether > >> the SPI flash is populated on any given configuration option). > >> > >> In getting the SPI image support ready for production, we found a > >> few areas that warranted improvements: > >> - we had broken SPI bootstrap earlier in the changes introducting > >> boot0-style images for the RK3399 (this needed fixing) > >> - in fixing the broken SPI padding calculation, it became apparent > >> that it's best to refactor and document things before we make > >> the same mistake again in the future > >> - with both SD/MMC and SPI images being used for various purposes > >> by various people, the wrong image style was inadvertendly used > >> in some tests... so we support for 'dumpimage' (i.e. verify_header > >> and print_header) had to be added to quickly check the image > >> type being handled > >> > >> Note that with the refactored calculation of the image-size, we > >> don't pad the image to the maximum SPL size any longer, but pad > >> SD/MMC to the next 512 byte block (RK_BLK_SIZE) and SPI to the > >> next 2K boundary. > >> > >> > >> Philipp Tomsich (8): > >> rockchip: mkimage: rkspi: include the header sector in the SPI size > >> calculation > >> rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI > >> images > >> rockchip: mkimage: Update comments for header size > >> rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize > >> rockchip: mkimage: clarify header0 initialisation > >> rockchip: mkimage: play nice with dumpimage > >> rockchip: mkimage: remove placeholder functions from rkimage > >> rockchip: mkimage: add support for verify_header/print_header > >> > >> tools/rkcommon.c | 195 > >> ++- > >> tools/rkcommon.h | 29 - > >> tools/rkimage.c | 21 +- > >> tools/rksd.c | 47 +- > >> tools/rkspi.c| 62 +- > >> 5 files changed, 255 insertions(+), 99 deletions(-) > >> > > > > > > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 0/8] rockchip: mkimage: refactor rksd/rkspi padding calculation and add dumpimage support
Heiko, thanks for the insight into the BROM. I’ll respin this with part of the change reverted and have Kever test. Regards, Philipp. > On 19 May 2017, at 20:39, Heiko Stuebner wrote: > > Hi Philipp, > > Am Mittwoch, 17. Mai 2017, 12:12:51 CEST schrieb Dr. Philipp Tomsich: >> What are the requirements for BACK_TO_BROM? >> All I can see about how BACK_TO_BROM works is that it needs to save the >> register >> context on the stack for returning to the ROM, but that seems to be only >> half the story. >> >> Assuming that the header0 structure plays into this, the only significant >> change there >> is that I don’t set the 'hdr->init_boot_size’ to the maximum SPL size any >> longer... > > Which is most likely the problem. back_to_bootrom-images are concatenated > with the spl in front (init_size) and when returned to the bootrom it > reads the rest up to init_boot_size into the sdram. > > So ideally we would return that line back to RK_MAX_BOOT_SIZE (512KB). > Somewhat safe value and boards not using back_to_bootrom, as this value > really only affects that second stage and not the actual spl loading. > > I'm sadly away from my boardfarm this and next week, so testing bootloader > on my rk3188 board can only happend after that, but I'm somewhat > confident that this would solve the problem. Maybe Kever can test that > meanwhile. > > > Heiko > > >> >> Regards, >> Philipp. >> >>> On 17 May 2017, at 11:50, Kever Yang wrote: >>> >>> Hi Philipp, >>> >>> This patch makes all the Rockchip SoCs with BACK_TO_BROM enabled can not >>> work, >>> >>> does the size correct for the SPL correct? >>> >>> Thanks, >>> - Kever >>> On 04/17/2017 11:47 PM, Philipp Tomsich wrote: We support booting both from SD/MMC images and SPI images on the RK3399-Q7 for different use-cases (e.g. external boot in development from the SD card, internal boot from MMC or SPI depending on whether the SPI flash is populated on any given configuration option). In getting the SPI image support ready for production, we found a few areas that warranted improvements: - we had broken SPI bootstrap earlier in the changes introducting boot0-style images for the RK3399 (this needed fixing) - in fixing the broken SPI padding calculation, it became apparent that it's best to refactor and document things before we make the same mistake again in the future - with both SD/MMC and SPI images being used for various purposes by various people, the wrong image style was inadvertendly used in some tests... so we support for 'dumpimage' (i.e. verify_header and print_header) had to be added to quickly check the image type being handled Note that with the refactored calculation of the image-size, we don't pad the image to the maximum SPL size any longer, but pad SD/MMC to the next 512 byte block (RK_BLK_SIZE) and SPI to the next 2K boundary. Philipp Tomsich (8): rockchip: mkimage: rkspi: include the header sector in the SPI size calculation rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images rockchip: mkimage: Update comments for header size rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize rockchip: mkimage: clarify header0 initialisation rockchip: mkimage: play nice with dumpimage rockchip: mkimage: remove placeholder functions from rkimage rockchip: mkimage: add support for verify_header/print_header tools/rkcommon.c | 195 ++- tools/rkcommon.h | 29 - tools/rkimage.c | 21 +- tools/rksd.c | 47 +- tools/rkspi.c| 62 +- 5 files changed, 255 insertions(+), 99 deletions(-) >>> >>> >> >> >> > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 0/8] rockchip: mkimage: refactor rksd/rkspi padding calculation and add dumpimage support
Am Freitag, 19. Mai 2017, 20:44:07 CEST schrieb Dr. Philipp Tomsich: > Heiko, > > thanks for the insight into the BROM. > I’ll respin this with part of the change reverted and have Kever test. The patch is already in Simon's next branch [0], so a fixup might be better :-) Heiko [0] http://git.denx.de/?p=u-boot/u-boot-rockchip.git;a=commit;h=8c38deeabfda64ed24c867c4657cb7406375d27e > > Regards, > Philipp. > > > On 19 May 2017, at 20:39, Heiko Stuebner wrote: > > > > Hi Philipp, > > > > Am Mittwoch, 17. Mai 2017, 12:12:51 CEST schrieb Dr. Philipp Tomsich: > >> What are the requirements for BACK_TO_BROM? > >> All I can see about how BACK_TO_BROM works is that it needs to save the > >> register > >> context on the stack for returning to the ROM, but that seems to be only > >> half the story. > >> > >> Assuming that the header0 structure plays into this, the only significant > >> change there > >> is that I don’t set the 'hdr->init_boot_size’ to the maximum SPL size any > >> longer... > > > > Which is most likely the problem. back_to_bootrom-images are concatenated > > with the spl in front (init_size) and when returned to the bootrom it > > reads the rest up to init_boot_size into the sdram. > > > > So ideally we would return that line back to RK_MAX_BOOT_SIZE (512KB). > > Somewhat safe value and boards not using back_to_bootrom, as this value > > really only affects that second stage and not the actual spl loading. > > > > I'm sadly away from my boardfarm this and next week, so testing bootloader > > on my rk3188 board can only happend after that, but I'm somewhat > > confident that this would solve the problem. Maybe Kever can test that > > meanwhile. > > > > > > Heiko > > > > > >> > >> Regards, > >> Philipp. > >> > >>> On 17 May 2017, at 11:50, Kever Yang wrote: > >>> > >>> Hi Philipp, > >>> > >>> This patch makes all the Rockchip SoCs with BACK_TO_BROM enabled can not > >>> work, > >>> > >>> does the size correct for the SPL correct? > >>> > >>> Thanks, > >>> - Kever > >>> On 04/17/2017 11:47 PM, Philipp Tomsich wrote: > We support booting both from SD/MMC images and SPI images on the > RK3399-Q7 for different use-cases (e.g. external boot in development > from the SD card, internal boot from MMC or SPI depending on whether > the SPI flash is populated on any given configuration option). > > In getting the SPI image support ready for production, we found a > few areas that warranted improvements: > - we had broken SPI bootstrap earlier in the changes introducting > boot0-style images for the RK3399 (this needed fixing) > - in fixing the broken SPI padding calculation, it became apparent > that it's best to refactor and document things before we make > the same mistake again in the future > - with both SD/MMC and SPI images being used for various purposes > by various people, the wrong image style was inadvertendly used > in some tests... so we support for 'dumpimage' (i.e. verify_header > and print_header) had to be added to quickly check the image > type being handled > > Note that with the refactored calculation of the image-size, we > don't pad the image to the maximum SPL size any longer, but pad > SD/MMC to the next 512 byte block (RK_BLK_SIZE) and SPI to the > next 2K boundary. > > > Philipp Tomsich (8): > rockchip: mkimage: rkspi: include the header sector in the SPI size > calculation > rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI > images > rockchip: mkimage: Update comments for header size > rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize > rockchip: mkimage: clarify header0 initialisation > rockchip: mkimage: play nice with dumpimage > rockchip: mkimage: remove placeholder functions from rkimage > rockchip: mkimage: add support for verify_header/print_header > > tools/rkcommon.c | 195 > ++- > tools/rkcommon.h | 29 - > tools/rkimage.c | 21 +- > tools/rksd.c | 47 +- > tools/rkspi.c| 62 +- > 5 files changed, 255 insertions(+), 99 deletions(-) > > >>> > >>> > >> > >> > >> > > > > > > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2] Convert CONFIG_SPL_BOARD_INIT to Kconfig
From: Ley Foon Tan This converts the following to Kconfig: CONFIG_SPL_BOARD_INIT Signed-off-by: Ley Foon Tan [trini: Update the Kconfig logic] Signed-off-by: Tom Rini --- arch/arm/Kconfig | 5 + arch/arm/include/asm/fsl_secure_boot.h | 1 - arch/arm/mach-keystone/Kconfig | 4 arch/arm/mach-rockchip/Kconfig | 2 ++ arch/arm/mach-socfpga/Kconfig | 1 + arch/arm/mach-tegra/Kconfig| 1 + board/freescale/common/Kconfig | 1 + common/spl/Kconfig | 8 configs/a3m071_defconfig | 1 + configs/a4m2k_defconfig| 1 + configs/controlcenterdc_defconfig | 1 + configs/da850_am18xxevm_defconfig | 1 + configs/da850evm_defconfig | 1 + configs/devkit3250_defconfig | 1 + configs/edminiv2_defconfig | 1 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + configs/ipam390_defconfig | 1 + configs/m53evk_defconfig | 1 + configs/mccmon6_nor_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + configs/microblaze-generic_defconfig | 1 + configs/omapl138_lcdk_defconfig| 1 + configs/sandbox_spl_defconfig | 1 + configs/woodburn_sd_defconfig | 1 + configs/work_92105_defconfig | 1 + include/configs/a3m071.h | 1 - include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 1 - include/configs/at91sam9n12ek.h| 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/bur_am335x_common.h| 1 - include/configs/cm_t35.h | 1 - include/configs/controlcenterdc.h | 1 - include/configs/corvus.h | 1 - include/configs/da850evm.h | 1 - include/configs/devkit3250.h | 1 - include/configs/edminiv2.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/ipam390.h | 1 - include/configs/kc1.h | 1 - include/configs/m53evk.h | 1 - include/configs/ma5d4evk.h | 1 - include/configs/mccmon6.h | 1 - include/configs/mcx.h | 1 - include/configs/microblaze-generic.h | 1 - include/configs/omap3_evm.h| 1 - include/configs/omapl138_lcdk.h| 1 - include/configs/rk3188_common.h| 1 - include/configs/rk3288_common.h| 1 - include/configs/sama5d2_ptc.h | 1 - include/configs/sama5d2_xplained.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/sama5d4_xplained.h | 1 - include/configs/sama5d4ek.h| 1 - include/configs/sandbox_spl.h | 2 -- include/configs/siemens-am33x-common.h | 1 - include/configs/smartweb.h | 1 - include/configs/sniper.h | 1 - include/configs/socfpga_common.h | 3 --- include/configs/tam3517-common.h | 1 - include/configs/tao3530.h | 1 - include/configs/taurus.h | 1 - include/configs/tegra-common.h | 1 - include/configs/ti814x_evm.h | 2 -- include/configs/ti816x_evm.h | 2 -- include/configs/ti_armv7_common.h | 1 - include/configs/tricorder.h| 1 - include/configs/twister.h | 1 - include/configs/uniphier.h | 2 -- include/configs/woodburn_sd.h | 1 - include/configs/work_92105.h | 1 - include/configs/xilinx_zynqmp.h| 1 - include/configs/zynq-common.h | 1 - 76 files changed, 41 insertions(+), 56 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a17ba2c60a54..bf91e6f35100 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -281,6 +281,7 @@ choice config ARCH_AT91 bool "Atmel AT91" + select SPL_BOARD_INIT if SUPPORT_SPL config TARGET_EDB93XX bool "Support edb93xx" @@ -553,6 +554,7 @@ config ARCH_KEYSTONE config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7 + select SPL_BOARD_INIT if SPL select SUPPORT_SPL imply FIT @@ -674,6 +676,7 @@ config ARCH_ZYNQ select CPU_V7 select SUPPORT_SPL select OF_CONTROL + select SPL_BOARD_INIT if SPL select SPL_OF_CONTROL if SPL select DM select DM_ETH @@ -701,6 +704,7 @@ config ARCH_ZYNQMP select DM_SERIAL select SUPPORT_SPL select CLK + select SPL_BOARD_INIT if SPL select SPL_CLK select DM_USB if USB @@ -943,6 +947,7 @@ config ARCH_UNIPHIER select OF_CONTROL select OF_LIBFDT select PINCTRL + select SPL_BOARD_INIT if SPL select SPL_DM if SPL select SPL_LIBCOMMON_SUPPORT if SPL select SPL_LIBGENERIC_SUPPORT if SPL diff --git a/arch/arm/include/asm/fsl_secure_boo
[U-Boot] [PATCH] ARM: k2g: Fix passing main pll info for higher speeds
Main pll is marked as arm plls for higher speeds. Fix this.
Signed-off-by: Lokesh Vutla
---
board/ti/ks2_evm/board_k2g.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 21aec8f065..f0bd31d6f7 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -79,29 +79,29 @@ static struct pll_init_data
main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
[SPD400]= {MAIN_PLL, 125, 3, 2},
[SPD600]= {MAIN_PLL, 125, 2, 2},
[SPD800]= {MAIN_PLL, 250, 3, 2},
- [SPD900]= {TETRIS_PLL, 187, 2, 2},
- [SPD1000] = {TETRIS_PLL, 104, 1, 2},
+ [SPD900]= {MAIN_PLL, 187, 2, 2},
+ [SPD1000] = {MAIN_PLL, 104, 1, 2},
},
[SYSCLK_24MHz] = {
[SPD400]= {MAIN_PLL, 100, 3, 2},
[SPD600]= {MAIN_PLL, 300, 6, 2},
[SPD800]= {MAIN_PLL, 200, 3, 2},
- [SPD900]= {TETRIS_PLL, 75, 1, 2},
- [SPD1000] = {TETRIS_PLL, 250, 3, 2},
+ [SPD900]= {MAIN_PLL, 75, 1, 2},
+ [SPD1000] = {MAIN_PLL, 250, 3, 2},
},
[SYSCLK_25MHz] = {
[SPD400]= {MAIN_PLL, 32, 1, 2},
[SPD600]= {MAIN_PLL, 48, 1, 2},
[SPD800]= {MAIN_PLL, 64, 1, 2},
- [SPD900]= {TETRIS_PLL, 72, 1, 2},
- [SPD1000] = {TETRIS_PLL, 80, 1, 2},
+ [SPD900]= {MAIN_PLL, 72, 1, 2},
+ [SPD1000] = {MAIN_PLL, 80, 1, 2},
},
[SYSCLK_26MHz] = {
[SPD400]= {MAIN_PLL, 400, 13, 2},
[SPD600]= {MAIN_PLL, 230, 5, 2},
[SPD800]= {MAIN_PLL, 123, 2, 2},
- [SPD900]= {TETRIS_PLL, 69, 1, 2},
- [SPD1000] = {TETRIS_PLL, 384, 5, 2},
+ [SPD900]= {MAIN_PLL, 69, 1, 2},
+ [SPD1000] = {MAIN_PLL, 384, 5, 2},
},
};
--
2.11.0
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Re: [U-Boot] [PATCH 3/8] dm: blk: Add a function to find the next block device number
Hi Andy,
On 18 May 2017 at 10:01, wrote:
> On Wed, May 3, 2017 at 5:36 AM, Simon Glass wrote:
>> Hi Andy,
>>
>> On 24 April 2017 at 02:04, Andy Shevchenko wrote:
>>> On Mon, Apr 24, 2017 at 5:02 AM, Simon Glass wrote:
At present this code is inline. Move it into a function to allow it to
be used elsewhere.
Signed-off-by: Simon Glass
>>>
+static int blk_next_free_devnum(enum if_type if_type)
+{
+ int ret;
+
+ ret = blk_find_max_devnum(if_type);
+ if (ret == -ENODEV)
+ return 0;
>>>
+ else if (ret < 0)
>>>
>>> Useless 'else'.
>>>
+ return ret;
+ else
>>>
>>> Ditto.
I updated these when applying.
- Simon
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Re: [U-Boot] i.MX6: u-boot,dm-pre-reloc block U-Boot
Hi Jagan,
On 17 May 2017 at 11:18, Jagan Teki wrote:
> Hi Simon,
>
> On Tue, May 16, 2017 at 5:47 AM, Simon Glass wrote:
>> Hi,
>>
>> On 13 May 2017 at 10:15, Jagan Teki wrote:
>>> Hi All,
>>>
>>> On Thu, May 11, 2017 at 1:40 PM, Jagan Teki
>>> wrote:
On Thu, May 11, 2017 at 7:39 AM, Lokesh Vutla wrote:
>
>
> On 5/11/2017 12:52 AM, Jagan Teki wrote:
>> Hi Lokesh,
>>
>> On Tue, May 9, 2017 at 10:03 PM, Jagan Teki
>> wrote:
>>> On Tue, May 9, 2017 at 8:54 PM, Lokesh Vutla wrote:
On Tuesday 09 May 2017 08:37 PM, Jagan Teki wrote:
> On Tue, May 9, 2017 at 7:49 PM, Lokesh Vutla
> wrote:
>>
>>
>> On Tuesday 09 May 2017 04:35 PM, Jagan Teki wrote:
>>> Hi All,
>>>
>>> I'm trying to add SPL_OF_CONTROL for i.MX6UL, with usdhc1 and gpio1
>>> nodes are marking as "u-boot,dm-pre-reloc" like
>>
>> Did you try "u-boot,dm-spl" instead?
>
> Yes, no change.
Hmm..Ideally this should have taken effect :(
>
>>
>>
>>>
>>> --- a/arch/arm/dts/imx6ul.dtsi
>>> +++ b/arch/arm/dts/imx6ul.dtsi
>>> @@ -129,6 +129,7 @@
>>> };
>>>
>>> soc {
>>> + u-boot,dm-pre-reloc;
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>> compatible = "simple-bus";
>>> @@ -180,6 +181,7 @@
>>> };
>>>
>>> aips1: aips-bus@0200 {
>>> + u-boot,dm-pre-reloc;
>>> compatible = "fsl,aips-bus", "simple-bus";
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>> @@ -405,6 +407,7 @@
>>> };
>>>
>>> gpio1: gpio@0209c000 {
>>> + u-boot,dm-pre-reloc;
>>> compatible = "fsl,imx6ul-gpio",
>>> "fsl,imx35-gpio";
>>> reg = <0x0209c000 0x4000>;
>>> interrupts = >> IRQ_TYPE_LEVEL_HIGH>,
>>> @@ -724,6 +727,7 @@
>>> };
>>>
>>> aips2: aips-bus@0210 {
>>> + u-boot,dm-pre-reloc;
>>> compatible = "fsl,aips-bus", "simple-bus";
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>> @@ -781,6 +785,7 @@
>>> };
>>>
>>> usdhc1: usdhc@0219 {
>>> + u-boot,dm-pre-reloc;
>>> compatible = "fsl,imx6ul-usdhc",
>>> "fsl,imx6sx-usdhc";
>>> reg = <0x0219 0x4000>;
>>> interrupts = >> IRQ_TYPE_LEVEL_HIGH>;
>>>
>>> SPL is loading fine from MMC but block the U-Boot that means we
>>> can't
>>> see U-Boot log on console.
>>
>> Any chance you can try enabling early debug? Since enabling
>> pre-reloc is
>> going for a toss, I guess your malloc size is going for a toss. Can
>> you
>> try increasing initial malloc size?
>
> Yes, I've increased malloc CONFIG_SYS_MALLOC_LEN from 16M to upto 128M
> but no change.
No, try CONFIG_SYS_MALLOC_F_LEN=0x2000.
Is it possible to check where exactly is it hanged?
>>>
>>> Yes, it hangs while relocating dram[1] and I also observed the main
>>> bus nodes are are 'not found' which I haven't see before and these are
>>> marked 'u-boot,dm-spl'
>>>
>>> uclass_find_device_by_seq: 0 -1
>>> uclass_find_device_by_seq: 0 0
>>>- -1 -1 'soc'
>>>- -1 -1 'aips-bus@0200'
>>>- -1 -1 'aips-bus@0210'
>>>- not found
>>
>> Any clue, I still investigating. Look like the node seq numbers which
>> are marked as "u-boot,dm-spl" in SPL are checking before relocating in
>> U-Boot, and they seems not found.
>>
>> Interestingly I couldn't see any panic or exception, the code ends
>> board_f last line.
>
> Manfred posted a patch[1] stating a similar issue. See if it fixes it?
It's not. I think this hanged at relocation assembly relocate_code or
relocate_vectors.
>>>
>>> Any help on this, this look relocation is not possible in U-Boot with
>>> 'u-boot,dm-pre-reloc' and incidentally removing property from /soc all
>>> works fine.
>>
>> I don't have any idea based on the DM angl
Re: [U-Boot] [PATCH v2 8/9] dm: core: Add ofnode to represent device tree nodes
Hi Masahiro, On 16 May 2017 at 04:35, Masahiro Yamada wrote: > > Hi Simon, > > > 2017-05-02 0:18 GMT+09:00 Simon Glass : > > With live tree we need a struct device_node * to reference a node. With > > the existing flat tree, we need an int offset. We need to unify these into > > a single value which can represent both. > > > > Add an ofnode union for this and adjust existing code to move to this. > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v2: None > > > > drivers/core/device.c | 2 +- > > drivers/core/root.c | 2 +- > > include/dm.h | 1 + > > include/dm/device.h | 14 +-- > > include/dm/ofnode.h | 100 > > ++ > > 5 files changed, 113 insertions(+), 6 deletions(-) > > create mode 100644 include/dm/ofnode.h > When you add a new header, please make sure it is self-contained. > > You use bool for offset_toofnode() and ofnode_equal(). > So you need to include from this header. > > (or, use "int" for the return type.) I'm wondering about this problem: In general we want to minimise the size of headers included by U-Boot. For something like ofnode which is used by several header files we end up including it many times, once per header. With dm.h we avoid this since the header is only included ones (and in the correct order). What is the best solution to this? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] doc: rockchip: Add phyCORE-RK3288 RDK to board list
On 15 May 2017 at 08:19, Wadim Egorov wrote: > Signed-off-by: Wadim Egorov > --- > doc/README.rockchip | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] rockchip: pinctrl: rk3328: use gpio instead of sdmmc-pwren
On 16 May 2017 at 21:44, Kever Yang wrote: > SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may > be high active or low active, the dwmmc driver always assume > the sdmmc-pwren as high active. > > Kernel treat this pin as fixed regulator instead of a pin from > controller, and then it can set in dts file upon board schematic, > that's a good solution, we can also do this in u-boot. > > Signed-off-by: Kever Yang > --- > > drivers/pinctrl/rockchip/pinctrl_rk3328.c | 6 ++ > 1 file changed, 2 insertions(+), 4 deletions(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] Ensure device tree DTS is compiled
Hi Masahiro, On 25 April 2017 at 19:02, Masahiro Yamada wrote: > 2017-03-27 11:27 GMT+09:00 Simon Glass : >> On 15 March 2017 at 22:11, James Balean wrote: >>> Enables custom DTS files, or those not associated with a specific target, >>> to be compiled into a boot image. >>> >>> Signed-off-by: James Balean >>> Cc: Andy Shevchenko >>> Cc: Simon Glass >>> --- >>> Changes for v2: >>> - Removed trailing '/dts' from paths containing ARCH_PATH >>> >>> dts/Makefile | 13 ++--- >>> 1 file changed, 10 insertions(+), 3 deletions(-) >> >> Applied to u-boot-dm, thanks! >> ___ >> U-Boot mailing list >> U-Boot@lists.denx.de >> https://lists.denx.de/listinfo/u-boot > > > Since this patch was applied, > I see annoying "is up to date" log every time. > > > grep __rel_dyn_end | cut -f 1 -d ' '); tools/relocate-rela > u-boot-nodtb.bin 0x8400 $start $end > DTC arch/arm/dts/uniphier-ld11-ref.dtb > DTC arch/arm/dts/uniphier-ld20-ref.dtb > make[2]: `arch/arm/dts/uniphier-ld11-ref.dtb' is up to date. > SHIPPED dts/dt.dtb > CAT u-boot-dtb.bin > COPYu-boot.bin > SYM u-boot.sym > MKIMAGE u-boot.img > COPYu-boot.dtb > MKIMAGE u-boot-dtb.img > CFGCHK u-boot.cfg > > > > I could not understand what you wanted to achieve with this patch. > > Could you explain? I have not seen any followup on this thread. Feel free to send a revert if you think that is warranted. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/6] rockchip: pinctrl: rk3328: do not set io routing
On 16 May 2017 at 21:44, Kever Yang wrote: > In rk3328, some function pin may have more than one choice, and muxed > with more than one IO, for example, the UART2 controller IO, > TX and RX, have 3 choice(setting in com_iomux): > - M0 which mux with GPIO1A0/GPIO1A1 > - M1 which mux with GPIO2A0/GPIO2A1 > - usb2phy which mux with USB2.0 DP/DM pin. > > We should not decide which group to use in pinctrl driver, > for it may be different in different board, it should goes to board > file, and the pinctrl file should setting correct iomux depends on > the com_iomux value. > > Signed-off-by: Kever Yang > --- > > arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 30 > drivers/pinctrl/rockchip/pinctrl_rk3328.c | 47 > +++-- > 2 files changed, 43 insertions(+), 34 deletions(-) > Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 03/14] mmc: sti_sdhci: Use reset framework
Hi Patrice,
On 17 May 2017 at 01:14, Patrice CHOTARD wrote:
> Hi Simon
>
> On 05/17/2017 03:38 AM, Simon Glass wrote:
>> Hi Patrice,
>>
>> On 15 May 2017 at 03:21, Patrice CHOTARD wrote:
>>> Hi Simon
>>>
>>> On 05/15/2017 05:02 AM, Simon Glass wrote:
Hi Patrice,
On 10 May 2017 at 10:09, wrote:
> From: Patrice Chotard
>
> Signed-off-by: Patrice Chotard
> Reviewed-by: Jaehoon Chung
> ---
>
> v5: _ none
> v4: _ none
> v3: _ none
> v2: _ none
>
>
> drivers/mmc/sti_sdhci.c | 31 ++-
> 1 file changed, 22 insertions(+), 9 deletions(-)
>
Reviewed-by: Simon Glass
This is fine as is. But please see questions below.
> diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c
> index d6c4d67..8b1b2c0 100644
> --- a/drivers/mmc/sti_sdhci.c
> +++ b/drivers/mmc/sti_sdhci.c
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -16,6 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
> struct sti_sdhci_plat {
> struct mmc_config cfg;
> struct mmc mmc;
> + struct reset_ctl reset;
> int instance;
> };
>
> @@ -37,17 +39,19 @@ struct sti_sdhci_plat {
> * W/o these settings the SDHCI could configure and use the embedded
> controller
> * with limited features.
> */
> -static void sti_mmc_core_config(struct udevice *dev)
> +static int sti_mmc_core_config(struct udevice *dev)
> {
> struct sti_sdhci_plat *plat = dev_get_platdata(dev);
> struct sdhci_host *host = dev_get_priv(dev);
> - unsigned long *sysconf;
> + int ret;
>
> /* only MMC1 has a reset line */
> if (plat->instance) {
> - sysconf = (unsigned long *)(STIH410_SYSCONF5_BASE +
> - ST_MMC_CCONFIG_REG_5);
> - generic_set_bit(SYSCONF_MMC1_ENABLE_BIT, sysconf);
> + ret = reset_deassert(&plat->reset);
> + if (ret < 0) {
> + error("MMC1 deassert failed: %d", ret);
> + return ret;
> + }
> }
>
> writel(STI_FLASHSS_MMC_CORE_CONFIG_1,
> @@ -66,6 +70,8 @@ static void sti_mmc_core_config(struct udevice *dev)
> }
> writel(STI_FLASHSS_MMC_CORE_CONFIG4,
>host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4);
> +
> + return 0;
> }
>
> static int sti_sdhci_probe(struct udevice *dev)
> @@ -80,13 +86,20 @@ static int sti_sdhci_probe(struct udevice *dev)
> * MMC0 is wired to the SD slot,
> * MMC1 is wired on the high speed connector
> */
> -
> - if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL))
> + if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets",
> NULL)) {
> plat->instance = 1;
> - else
> + ret = reset_get_by_name(dev, "softreset", &plat->reset);
Two questions:
1. The name "softreset" is in the "resets" property, isn't it? If so,
can you use it instead of hard-coding "softreset" here?
>>>
>>> Sorry, i didn't understand what you mean by "can you use it instead of
>>> hard-coding "softreset" here"
>>
>> I am wondering if the value of the 'resets' property is 'softtreset'?
>
> "softreset" is the value of the "reset-names" property.
>
> resets = <&softreset STIH407_MMC1_SOFTRESET>;
> reset-names = "softreset";
>
> But i am thinking to simplify this part.
>
OK I see. Well, from me:
Reviewed-by: Simon Glass
> Patrice
>
>> If so, you could perhaps use that value instead of the string
>> 'softreset'.
>>
>>>
>>>
2. Can you not call reset_get_by_name() and deal with the error return
(-ENOENT I think) if there is no such reset?
> + if (ret) {
> + error("can't get reset for %s (%d)", dev->name,
> ret);
> + return ret;
> + }
> + } else {
> plat->instance = 0;
> + }
>
> - sti_mmc_core_config(dev);
> + ret = sti_mmc_core_config(dev);
> + if (ret)
> + return ret;
>
> host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
>SDHCI_QUIRK_32BIT_DMA_ADDR |
> --
> 1.9.1
>>
>> Regards,
>> Simon
>>
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Re: [U-Boot] [PATCH 6/6] rockchip: dts: rk3328-evb: add sdmmc-pwren regulator
On 16 May 2017 at 21:44, Kever Yang wrote: > Use fixed regulator for sdmmc-pwren for sdmmc power. > > Signed-off-by: Kever Yang > --- > > arch/arm/dts/rk3328-evb.dts | 8 > 1 file changed, 8 insertions(+) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] OF_PLATDATA questions on rk3399 platfrom
Hi Ziyuan,
On 8 May 2017 at 01:01, Ziyuan wrote:
> hi simon,
>
> I need to achieve emmc_phy physical address in driver, so that I can
> configure phy in different scenarios (phy register address should be
> 0xff77f780). see below:
> sdhci: sdhci@fe33 {
>
> phys = <&emmc_phy>;
> phy-names = "phy_arasan";
>
> };
>
> grf: syscon@ff77 {
> reg = <0x0 0xff77 0x0 0x1>;
>
> emmc_phy: phy@f780 {
> compatible = "rockchip,rk3399-emmc-phy";
> reg = <0xf780 0x24>;
> #phy-cells = <0>;
> status = "disabled";
> };
> };
>
> AKA, I can't use libfdt if OF_PLATDATA is enabled, so how to get it?
>
At present this is not supported. I'm not quite sure how to support
it, or at least the best way. Do you have ideas on what the C
structure should be for this?
Regards,
Simon
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Re: [U-Boot] [PATCH 5/6] rockchip: evb-rk3328: enable boot on regulator
On 16 May 2017 at 21:44, Kever Yang wrote: > Enable all the boot-on regulator in default. > > Signed-off-by: Kever Yang > --- > > board/rockchip/evb_rk3328/evb-rk3328.c | 8 +++- > 1 file changed, 7 insertions(+), 1 deletion(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 01/10] drivers: spi: allow limiting reads
On 18 May 2017 at 13:29, Álvaro Fernández Rojas wrote: > For some SPI controllers it's not possible to keep the CS active between > transfers and they are limited to a known number of bytes. > This splits spi_flash reads into different iterations in order to respect > the SPI controller limits. > > Signed-off-by: Álvaro Fernández Rojas > --- > drivers/mtd/spi/spi_flash.c | 3 +++ > include/spi.h | 3 +++ > 2 files changed, 6 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 02/10] drivers: spi: add config to consider command bytes when writting to flash
Hi Alvaro,
On 18 May 2017 at 13:29, Álvaro Fernández Rojas wrote:
> Command bytes are part of the written bytes and they should be taken into
> account when sending a spi transfer.
>
> Signed-off-by: Álvaro Fernández Rojas
> ---
> drivers/mtd/spi/spi_flash.c | 2 +-
> drivers/spi/Kconfig | 3 +++
> include/spi.h | 8 +++-
> 3 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> index e44c10f..748cc32 100644
> --- a/drivers/mtd/spi/spi_flash.c
> +++ b/drivers/mtd/spi/spi_flash.c
> @@ -380,7 +380,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
> offset,
>
> if (spi->max_write_size)
> chunk_len = min(chunk_len,
> - (size_t)spi->max_write_size);
> + spi_max_write(spi, sizeof(cmd)));
>
> spi_flash_addr(write_addr, cmd);
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index f3f7dbe..a00d401 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -13,6 +13,9 @@ config DM_SPI
> typically use driver-private data instead of extending the
> spi_slave structure.
>
> +config SPI_MAX_WRITE_CMD_BYTES
> + bool "Include command bytes when determining max write size"
Do you really need this, or can you just always do this? If you need
it, please add detailed help.
> +
> if DM_SPI
>
> config ALTERA_SPI
> diff --git a/include/spi.h b/include/spi.h
> index 75a994c..310fa4d 100644
> --- a/include/spi.h
> +++ b/include/spi.h
> @@ -63,6 +63,12 @@ struct dm_spi_slave_platdata {
>
> #endif /* CONFIG_DM_SPI */
>
> +#ifdef CONFIG_SPI_MAX_WRITE_CMD_BYTES
> +#define spi_max_write(spi, len)(spi->max_write_size - len)
> +#else
> +#define spi_max_write(spi, len)(spi->max_write_size)
> +#endif
> +
> /**
> * struct spi_slave - Representation of a SPI slave
> *
> @@ -89,7 +95,7 @@ struct dm_spi_slave_platdata {
> * @max_read_size: If non-zero, the maximum number of bytes which can
> * be read at once.
> * @max_write_size:If non-zero, the maximum number of bytes which can
> - * be written at once, excluding command bytes.
> + * be written at once.
> * @memory_map:Address of read-only SPI flash access.
> * @flags: Indication of SPI flags.
> */
> --
> 2.1.4
>
Regards,
Simon
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Re: [U-Boot] [PATCH 1/6] rockchip: pinctrl: move rk3328 grf reg definition in header file
On 16 May 2017 at 21:44, Kever Yang wrote: > > Move GRF register bit definition into GRF header file, remove > 'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning. > > Signed-off-by: Kever Yang > --- > > arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 114 + > drivers/pinctrl/rockchip/pinctrl_rk3328.c | 205 > ++-- > 2 files changed, 164 insertions(+), 155 deletions(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing
Hi Kever,
On 16 May 2017 at 21:44, Kever Yang wrote:
> In rk3328, some function pin may have more than one choice, and muxed
> with more than one IO, for example, the UART2 controller IO,
> TX and RX, have 3 choice(setting in com_iomux):
> - M0 which mux with GPIO1A0/GPIO1A1
> - M1 which mux with GPIO2A0/GPIO2A1
> - usb2phy which mux with USB2.0 DP/DM pin.
>
> We should set these IO routing in board file.
>
> Signed-off-by: Kever Yang
> ---
>
> board/rockchip/evb_rk3328/evb-rk3328.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c
> b/board/rockchip/evb_rk3328/evb-rk3328.c
> index a7895cb..d9dc782 100644
> --- a/board/rockchip/evb_rk3328/evb-rk3328.c
> +++ b/board/rockchip/evb_rk3328/evb-rk3328.c
> @@ -5,7 +5,10 @@
> */
>
> #include
> +#include
> +#include
> #include
> +#include
> #include
> #include
>
> @@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;
>
> int board_init(void)
> {
> +#define GRF_BASE 0xff10
> + struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
> +
> + /* uart2 select m1, sdcard select m1*/
> + rk_clrsetreg(&grf->com_iomux,
> +IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
> +IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
> +IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
> +
> return 0;
> }
This needs to be done via a call to some sort of driver. The above
hack is OK in SPL but not in U-Boot proper.
See my comments elsewhere about using a misc driver with an IOCTL
interface to do this sort of thing. Although here I wonder why you
cannot use pinctrl?
Regards,
Simon
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Re: [U-Boot] [PATCH 03/10] dm: spi: add BCM63xx SPI driver
On 18 May 2017 at 13:29, Álvaro Fernández Rojas wrote: > This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c > Instead of supporting both HW revisions of the controller in a single build, > support has been split by the selected config to save space. > > Signed-off-by: Álvaro Fernández Rojas > --- > drivers/spi/Kconfig | 23 +++ > drivers/spi/Makefile | 1 + > drivers/spi/bcm63xx_spi.c | 404 > ++ > 3 files changed, 428 insertions(+) > create mode 100644 drivers/spi/bcm63xx_spi.c Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
