date:20171211

On 12/11/2017 08:57 AM, Jaehoon Chung wrote:
> Hi JJ,
> 
> On 12/01/2017 01:43 AM, Jean-Jacques Hiblot wrote:
>> This series applies on top of "[PATCH v2 00/26] mmc: Add support for HS200
>> and UHS modes"
>>
>> It fixes a bug with old SD and MMC cards that support only the legacy mode.
>> This series also adresses the problem of increased code size that broke some
>> platform (openrd and omapl138_lcdk) by making more things optional.
>>
>> It also addresses other comments made on the mailing list:
>> * dump card and host capabilities in debug mode
>> * use 1-bit if the DTS property 'bus-width' is not present.
>> * recognize the "mmc-ddr-1_2v" and "mmc-hs200-1_2v" DTS properties
>> * convert mmc_of_parse to livetree
>>
> 
> Applied to u-boot-mmc. Sorry for late. Thanks!

Does that mean this thing will make it for 2018.01 or 2018.03 ?

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC 0/5] sf: Update spi-nor framework

On 12/11/2017 06:57 AM, Prabhakar Kushwaha wrote:
> SPI-NOR framework currently supports-
>  - (1-1-1, 1-1-2, 1-1-4) read protocols
>  - read latency(dummy bytes) are hardcoded with the assumption
>  that the flash would support it.
>  - No support of mode bits.
>  - No support of flash size above 128Mib
> 
> This patch set add support of 1-2-2, 1-4-4 read protocols. 
> It ports Linux commits "mtd: spi-nor: add a stateless method to support
> memory size above 128Mib" and "mtd: spi-nor: parse Serial Flash
> Discoverable Parameters (SFDP) tables". It enables 4byte address opcode
> and run time flash parameters discovery including dummy cycle and mode
> cycle.
> 
> Finally it update fsl-quadspi driver to store(set_mode) spi bus mode and
> provision for run-time LUTs creation.
> 
> Note: This patch-set is only **compliation** tested. Sending RFC to get
> early feed-back on the approach.
> 
> Prabhakar Kushwaha (5):
>   sf: Add support of 1-2-2, 1-4-4 IO READ protocols
>   sf: add method to support memory size above 128Mib
>   sf: parse Serial Flash Discoverable Parameters (SFDP) tables
>   sf: fsl_qspi: Add support of fsl_qspi_set_mode
>   sf: fsl_quadspi: Configue LUT based on padding information
> 
>  drivers/mtd/spi/sf_internal.h   | 230 +++-
>  drivers/mtd/spi/spi_flash.c | 574 
> +++-
>  drivers/spi/fsl_qspi.c  |  85 +-
>  include/spi_flash.h |   2 +
>  5 files changed, 875 insertions(+), 18 deletions(-)
> 

Could you rather port the entire SPI NOR framework from Linux 4.14 ?
That'd make more sense than porting bits and pieces on top of the
current crappy code IMO.

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v5 00/11] mmc: fixes for HS200/UHS core support

2017-12-11 Thread Jaehoon Chung

On 12/11/2017 06:33 PM, Marek Vasut wrote:
> On 12/11/2017 08:57 AM, Jaehoon Chung wrote:
>> Hi JJ,
>>
>> On 12/01/2017 01:43 AM, Jean-Jacques Hiblot wrote:
>>> This series applies on top of "[PATCH v2 00/26] mmc: Add support for HS200
>>> and UHS modes"
>>>
>>> It fixes a bug with old SD and MMC cards that support only the legacy mode.
>>> This series also adresses the problem of increased code size that broke some
>>> platform (openrd and omapl138_lcdk) by making more things optional.
>>>
>>> It also addresses other comments made on the mailing list:
>>> * dump card and host capabilities in debug mode
>>> * use 1-bit if the DTS property 'bus-width' is not present.
>>> * recognize the "mmc-ddr-1_2v" and "mmc-hs200-1_2v" DTS properties
>>> * convert mmc_of_parse to livetree
>>>
>>
>> Applied to u-boot-mmc. Sorry for late. Thanks!
> 
> Does that mean this thing will make it for 2018.01 or 2018.03 ?

If it's possible, will make it for 2018.01!
Now, i'm checking some issue about SPL size. 

Best Regards,
Jaehoon Chung

> 

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 00/20] Add FPGA driver, SDRAM driver, generic firmware loader and booting U-Boot.

From: Tien Fong Chee 

This patchset adding FPGA drivers, SDRAM drivers, and generic firmware loader.
The patchset also enable fpga loadfs to program FPGA, SPL loading U-boot and
booting to U-boot console. This version mainly resolved comments from
Lothar Waßmann in [v5].

Please note that generic firmware loader is an independent driver, which can be
used to load whatever into target location, then consumer driver would use it to
program whatever, ie. the FPGA.

This series is working on top of u-boot.git -
 http://git.denx.de/u-boot.git .

[v5]: https://www.mail-archive.com/u-boot@lists.denx.de/msg271395.html

v5 -> v6 changes:
-
- Fixed the bugs in Generic firmware loader.

Patchset history

[v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg261831.html
[v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg265192.html
[v3]: https://www.mail-archive.com/u-boot@lists.denx.de/msg266981.html
[v4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg268160.html

Tien Fong Chee (20):
  ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA
manager
  dts: Add FPGA bitstream properties to Arria 10 DTS
  arm: socfpga: Add Arria 10 SoCFPGA programming interface
  dts: Enable fpga-mgr node build for Arria 10 SPL
  fs: Enable generic filesystems interface support in SPL.
  arm: socfpga: Remove static declaration on spl_mmc_find_device
function
  common: Generic firmware loader for file system
  arm: socfpga: Fix with the correct polling on bit is set
  arm: socfpga: Add FPGA drivers for Arria 10 FPGA loadfs
  arm: socfpga: Rename the gen5 sdram driver to more specific name
  arm: socfpga: Add DRAM bank size initialization function
  arm: socfpga: Add DDR driver for Arria 10
  configs: Add DDR Kconfig support for Arria 10
  arm: socfpga: Enable SPL memory allocation
  arm: socfpga: Improve comments for Intel SoCFPGA program header
  arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10
  arm: socfpga: Adding clock frequency info for U-Boot
  arm: socfpga: Adding SoCFPGA info for both SPL and U-Boot
  arm: socfpga: Enable DDR working
  arm: socfpga: Enable SPL booting U-boot

 arch/arm/dts/socfpga_arria10.dtsi  |   6 +
 arch/arm/mach-socfpga/Kconfig  |   1 +
 arch/arm/mach-socfpga/board.c  |  18 +
 arch/arm/mach-socfpga/include/mach/boot0.h |  11 +-
 .../include/mach/fpga_manager_arria10.h|  32 +
 arch/arm/mach-socfpga/include/mach/sdram.h | 434 +---
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +
 .../include/mach/{sdram.h => sdram_gen5.h} |   6 +-
 arch/arm/mach-socfpga/misc_arria10.c   |   5 -
 arch/arm/mach-socfpga/spl.c|  49 ++
 cmd/fpga.c |   2 +-
 common/Makefile|   1 +
 common/fs_loader.c | 299 +
 common/spl/Kconfig |   8 +
 common/spl/spl_mmc.c   |   2 +-
 configs/socfpga_arria10_defconfig  |  58 +-
 doc/README.SPL |   1 +
 .../fpga/altera-socfpga-a10-fpga-mgr.txt   |  11 +
 drivers/ddr/altera/Kconfig |   2 +-
 drivers/ddr/altera/Makefile|   3 +-
 drivers/ddr/altera/sdram_arria10.c | 737 +
 drivers/ddr/altera/{sdram.c => sdram_gen5.c}   |   0
 drivers/fpga/altera.c  |  40 +-
 drivers/fpga/fpga.c|   8 +
 drivers/fpga/socfpga_arria10.c | 379 ++-
 fs/Makefile|   1 +
 include/altera.h   |   6 +
 include/configs/socfpga_common.h   |  23 +-
 include/fpga.h |   2 +
 include/fs_loader.h|  30 +
 include/spl.h  |   2 +
 31 files changed, 1713 insertions(+), 466 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
 create mode 100644 common/fs_loader.c
 create mode 100644 drivers/ddr/altera/sdram_arria10.c
 rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
 create mode 100644 include/fs_loader.h

-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 01/20] ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager

From: Tien Fong Chee 

This patch adds description on properties about location of FPGA RBFs are
stored, type and functionality of RBF used to configure FPGA.

Signed-off-by: Tien Fong Chee 
---
 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt 
b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a..47c695b 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,6 +7,14 @@ Required properties:
- The second index is for writing FPGA configuration data.
 - resets : Phandle and reset specifier for the device's reset.
 - clocks : Clocks used by the device.
+- altr,bitstream_periph : FPGA peripheral raw binary file which is used to
+  initialize FPGA IOs, PLL, IO48 and DDR.
+- altr,bitstream_core : FPGA core raw binary file contains FPGA design which is
+   used to program FPGA CRAM and ERAM.
+- altr,bitstream_devpart : Partition of flash device where bitstream files are
+  stored.
+- dev is flash device number, part is
+ flash device partition.
 
 Example:
 
@@ -16,4 +24,7 @@ Example:
   0xffcfe400 0x20>;
clocks = <&l4_mp_clk>;
resets = <&rst FPGAMGR_RESET>;
+   altr,bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
+   altr,bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
+   altr,bitstream_devpart = "0:1";
};
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 02/20] dts: Add FPGA bitstream properties to Arria 10 DTS

From: Tien Fong Chee 

These FPGA bitstream properties would help bootloader to understand
how to configure FPGA and where to look the FPGA RBF files during
booting.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/dts/socfpga_arria10.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
index 377700d..aeb2be8 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -538,6 +538,11 @@
clocks = <&l4_mp_clk>;
resets = <&rst FPGAMGR_RESET>;
reset-names = "fpgamgr";
+   altr,bitstream_periph =
+"ghrd_10as066n2.periph.rbf.mkimage";
+   altr,bitstream_core =
+"ghrd_10as066n2.core.rbf.mkimage";
+   altr,bitstream_devpart = "0:1";
};
 
i2c0: i2c@ffc02200 {
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 08/20] arm: socfpga: Fix with the correct polling on bit is set

From: Tien Fong Chee 

Commit 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")
Polling on wrong cleared bit. Fix with correct polling on bit is set.

Fixes: 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")

Signed-off-by: Tien Fong Chee 
---
 drivers/fpga/socfpga_arria10.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5c1a68a..e076bda 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -112,13 +112,14 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 
-   /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until 
de-asserted,
-* timeout at 1000ms
+   /*
+* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
+* de-asserted, timeout at 1000ms
 */
return wait_for_bit(__func__,
&fpga_manager_base->imgcfg_stat,
mask,
-   false, FPGA_TIMEOUT_MSEC, false);
+   true, FPGA_TIMEOUT_MSEC, false);
 }
 
 static int wait_for_f2s_nstatus_pin(unsigned long value)
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 05/20] fs: Enable generic filesystems interface support in SPL.

From: Tien Fong Chee 

Enable generic filesystem interface drivers(fs.c and fat/) build
for SPL. This would allow generic filesystem being used in SPL.

Signed-off-by: Tien Fong Chee 
Reviewed-by: Simon Glass 
---
 common/spl/Kconfig | 8 
 doc/README.SPL | 1 +
 fs/Makefile| 1 +
 3 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index aef0034..982c694 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -321,6 +321,14 @@ config SPL_ETH_SUPPORT
  is required since the network stack uses a number of environment
  variables. See also SPL_NET_SUPPORT.
 
+config SPL_FS_GENERIC
+   bool "Support Generic filesystems interface driver"
+   help
+ Enable support for generic filesystems interface with SPL. This
+ permits U-Boot (or Linux in Falcon mode) to be loaded from a generic
+ filesystem from within SPL. Support for the underlying block
+ device (e.g. MMC or USB) must be enabled separately.
+
 config SPL_EXT_SUPPORT
bool "Support EXT filesystems"
help
diff --git a/doc/README.SPL b/doc/README.SPL
index 3ba313c..32628a4 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -55,6 +55,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
 CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
 CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
 CONFIG_SPL_EXT_SUPPORT
+CONFIG_SPL_FS_GENERIC (fs/fs.o fat/)
 CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
 CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
 CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
diff --git a/fs/Makefile b/fs/Makefile
index 8a8175b..90e3cef 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -7,6 +7,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_FS_GENERIC) += fs.o fat/
 obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
 obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/
 else
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 07/20] common: Generic firmware loader for file system

From: Tien Fong Chee 

This is file system generic loader which can be used to load
the file image from the storage into target such as memory.
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.

Signed-off-by: Tien Fong Chee 
---
 common/Makefile |   1 +
 common/fs_loader.c  | 299 
 include/fs_loader.h |  30 ++
 3 files changed, 330 insertions(+)
 create mode 100644 common/fs_loader.c
 create mode 100644 include/fs_loader.h

diff --git a/common/Makefile b/common/Makefile
index cec506f..2934221 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -130,3 +130,4 @@ obj-$(CONFIG_CMD_DFU) += dfu.o
 obj-y += command.o
 obj-y += s_record.o
 obj-y += xyzModem.o
+obj-y += fs_loader.o
diff --git a/common/fs_loader.c b/common/fs_loader.c
new file mode 100644
index 000..269af25
--- /dev/null
+++ b/common/fs_loader.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static struct device_location default_locations[] = {
+   {
+   .name = "mmc",
+   .devpart = "0:1",
+   },
+   {
+   .name = "usb",
+   .devpart = "0:1",
+   },
+   {
+   .name = "sata",
+   .devpart = "0:1",
+   },
+};
+
+/* USB build is not supported yet in SPL */
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_USB_STORAGE
+static int init_usb(void)
+{
+   int err;
+
+   err = usb_init();
+   if (err)
+   return err;
+
+#ifndef CONFIG_DM_USB
+   err = usb_stor_scan(1) < 0 ? -ENODEV : 0;
+#endif
+
+   return err;
+}
+#else
+static int init_usb(void)
+{
+   printf("Error: Cannot load flash image: no USB support\n");
+   return -ENOSYS;
+}
+#endif
+#endif
+
+#ifdef CONFIG_SATA
+static int init_storage_sata(void)
+{
+   return sata_probe(0);
+}
+#else
+static int init_storage_sata(void)
+{
+   printf("Error: Cannot load image: no SATA support\n");
+   return -ENOSYS;
+}
+#endif
+
+#ifdef CONFIG_CMD_UBIFS
+static int mount_ubifs(struct device_location *location)
+{
+   int ret;
+   char cmd[32];
+
+   sprintf(cmd, "ubi part %s", location->mtdpart);
+
+   ret = run_command(cmd, 0);
+   if (ret)
+   return ret;
+
+   sprintf(cmd, "ubifsmount %s", location->ubivol);
+
+   ret = run_command(cmd, 0);
+
+   return ret;
+}
+
+static int umount_ubifs(void)
+{
+   return run_command("ubifsumount", 0);
+}
+#else
+static int mount_ubifs(struct device_location *location)
+{
+   printf("Error: Cannot load image: no UBIFS support\n");
+   return -ENOSYS;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT) && defined(CONFIG_SPL_BUILD)
+static int init_mmc(void)
+{
+   /* Just for the case MMC is not yet initialized */
+   struct mmc *mmc = NULL;
+   int err;
+
+   spl_mmc_find_device(&mmc, spl_boot_device());
+
+   err = mmc_init(mmc);
+   if (err) {
+   printf("spl: mmc init failed with error: %d\n", err);
+   return err;
+   }
+
+   return err;
+}
+#else
+static int init_mmc(void)
+{
+   /* Expect somewhere already initialize MMC */
+   return 0;
+}
+#endif
+
+static int select_fs_dev(struct device_location *location)
+{
+   int ret = 0;
+
+   if (!strcmp("mmc", location->name)) {
+   ret = fs_set_blk_dev("mmc", location->devpart, FS_TYPE_ANY);
+   }
+   else if (!strcmp("usb", location->name)) {
+   ret = fs_set_blk_dev("usb", location->devpart, FS_TYPE_ANY);
+   }
+   else if (!strcmp("sata", location->name)) {
+   ret = fs_set_blk_dev("sata", location->devpart, FS_TYPE_ANY);
+   }
+   else if (!strcmp("ubi", location->name)) {
+   if (location->ubivol != NULL)
+   ret = fs_set_blk_dev("ubi", NULL, FS_TYPE_UBIFS);
+   else
+   ret = -ENODEV;
+   }
+   else {
+   printf("Error: unsupported location storage.\n");
+   return -ENODEV;
+   }
+
+   if (ret)
+   printf("Error: could not access storage.\n");
+
+   return ret;
+}
+
+static int init_storage_device(struct device_location *location)
+{
+   int ret = 0;
+#ifndef CONFIG_SPL_BUILD
+   /* USB build is not supported yet in SPL */
+   if (!strcmp("usb", location->name))
+   ret = init_usb();
+#endif
+
+   if (!strcmp("mmc", location->name))
+   ret = init_mmc();
+
+   if (!strcmp("sata", location->name))
+   ret = init_storage_sata();
+
+   if (location->ubivol != NULL)
+   ret = mount_ubifs(location);
+
+   return ret;
+}
+
+static void set_storage_devpart(char *name, char *devpart)
+{
+   size_t i;
+
+   for (i

[U-Boot] [PATCH v6 04/20] dts: Enable fpga-mgr node build for Arria 10 SPL

From: Tien Fong Chee 

fpga-mgr node is required in SPL, because SPL needs information
from the node to configure FPGA in Arria 10.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/dts/socfpga_arria10.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
index aeb2be8..1848710 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -532,6 +532,7 @@
};
 
fpga_mgr: fpga-mgr@ffd03000 {
+   u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-fpga-mgr";
reg = <0xffd03000 0x100
   0xffcfe400 0x20>;
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 14/20] arm: socfpga: Enable SPL memory allocation

From: Tien Fong Chee 

Enable memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.

Signed-off-by: Tien Fong Chee 
Reviewed-by: Dinh Nguyen 
---
 include/configs/socfpga_common.h | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 31b1eda..7dcacbc 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -263,17 +263,33 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * SPL
  *
- * SRAM Memory layout:
+ * SRAM Memory layout for gen 5:
  *
  * 0x_ .. Start of SRAM
  * 0x_ .. Top of stack (grows down)
  * 0x_ .. Malloc area
  * 0x_ .. Global Data
  * 0x_FF00 .. End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_ .. Start of SRAM (bottom)
+ * 0xFFEx_ .. Top of stack (grows down to bottom)
+ * 0xFFEy_ .. Global Data
+ * 0xFFEz_ .. Malloc area (grows up to top)
+ * 0xFFE3_ .. End of SRAM (top)
  */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT_RAM_SIZE
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001
+#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_INIT_RAM_SIZE - \
+CONFIG_SYS_SPL_MALLOC_SIZE + \
+CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+#endif
 
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -303,7 +319,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * Stack setup
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP_ADDR
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_STACK   CONFIG_SYS_SPL_MALLOC_START
+#endif
 
 /* Extra Environment */
 #ifndef CONFIG_SPL_BUILD
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 17/20] arm: socfpga: Adding clock frequency info for U-Boot

From: Tien Fong Chee 

Clock frequency info is required in U-Boot because info would be erased
when transition from SPL to U-Boot.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/board.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 965f9dc..8d3b515 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -8,7 +8,9 @@
 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 
 #include 
@@ -26,6 +28,11 @@ int board_init(void)
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+#endif
+
return 0;
 }
 
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 11/20] arm: socfpga: Add DRAM bank size initialization function

From: Tien Fong Chee 

Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.

Signed-off-by: Tien Fong Chee 
Tested-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/board.c| 7 +++
 include/configs/socfpga_common.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index a41d089..965f9dc 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -29,6 +29,13 @@ int board_init(void)
return 0;
 }
 
+int dram_init_banksize(void)
+{
+   fdtdec_setup_memory_banksize();
+
+   return 0;
+}
+
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
.usb_gusbcfg= 0x1417,
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 8a7debb..31b1eda 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -43,6 +43,7 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE  PHYS_SDRAM_1_SIZE
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE   0x0840
 #else
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 13/20] configs: Add DDR Kconfig support for Arria 10

From: Tien Fong Chee 

This patch enables DDR Kconfig support for Arria 10.

Signed-off-by: Tien Fong Chee 
Reviewed-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/Kconfig | 1 +
 drivers/ddr/altera/Kconfig| 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 45e5379..3e7a68a 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -40,6 +40,7 @@ config TARGET_SOCFPGA_ARRIA5
 config TARGET_SOCFPGA_ARRIA10
bool
select SPL_BOARD_INIT if SPL
+   select ALTERA_SDRAM
 
 config TARGET_SOCFPGA_CYCLONE5
bool
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 021ec1d..2b28a97 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,5 @@
 config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
-   depends on TARGET_SOCFPGA_GEN5
+   depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
help
  Enable DDR SDRAM controller for the SoCFPGA devices.
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 09/20] arm: socfpga: Add FPGA drivers for Arria 10 FPGA loadfs

From: Tien Fong Chee 

Add FPGA drivers to support FPGA loadfs to program FPGA.
The drivers are designed based on generic firmware loader framework,
specific firmware loader handling is defined in fpga_manager_arria10.c.
These drivers can handle FPGA program operation from
loading RBF image in flash to memory and then to program FPGA.

Signed-off-by: Tien Fong Chee 
---
 .../include/mach/fpga_manager_arria10.h|  32 ++
 drivers/fpga/socfpga_arria10.c | 372 -
 include/altera.h   |   6 +
 3 files changed, 407 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..afcf7d8 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -8,6 +8,9 @@
 #ifndef _FPGA_MANAGER_ARRIA10_H_
 #define _FPGA_MANAGER_ARRIA10_H_
 
+#include 
+#include 
+
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  BIT(0)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   BIT(2)
@@ -89,11 +92,40 @@ struct socfpga_fpga_manager {
u32  imgcfg_fifo_status;
 };
 
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+enum rbf_type {unknown, periph_section, core_section};
+enum rbf_security {invalid, unencrypted, encrypted};
+
+struct rbf_info {
+   enum rbf_type section;
+   enum rbf_security security;
+};
+
+struct flash_info {
+   struct device_location dev;
+   char *filename;
+   int fstype;
+   u32 remaining;
+   u32 offset;
+   struct rbf_info rbfinfo;
+   struct image_header header;
+};
+#endif
+
 /* Functions */
 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
 int fpgamgr_program_finish(void);
 int is_fpgamgr_user_mode(void);
 int fpgamgr_wait_early_user_mode(void);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core);
+const char *get_cff_devpart(const void *fdt, int *len);
+int fs_flash_preinit(struct flash_info *flashinfo, u32 *buffer,
+u32 *buffer_sizebytes);
+int fs_flash_read(struct flash_info *flashinfo, u32 *buffer,
+ u32 *buffer_sizebytes);
+#endif
+void set_flash_devpart(char *name, char *devpart);
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index e076bda..fcdc79e 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -13,6 +13,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
 #include 
 
@@ -22,6 +28,10 @@
 #define COMPRESSION_OFFSET 229
 #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT   0x100
+#define RBF_UNENCRYPTED0xa65c
+#define RBF_ENCRYPTED  0xa65d
+#define ARRIA10RBF_PERIPH  0x0001
+#define ARRIA10RBF_CORE0x8001
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -146,7 +156,6 @@ static void fpgamgr_set_cd_ratio(unsigned long ratio)
 static int fpgamgr_verify_msel(void)
 {
u32 msel = fpgamgr_get_msel();
-
if (msel & ~BIT(0)) {
printf("Fail: read msel=%d\n", msel);
return -EPERM;
@@ -337,7 +346,6 @@ int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
 
/* Step 8 */
ret = fpgamgr_reset();
-
if (ret)
return ret;
 
@@ -434,7 +442,6 @@ int fpgamgr_program_finish(void)
 {
/* Ensure the FPGA entering config done */
int status = fpgamgr_program_poll_cd();
-
if (status) {
printf("FPGA: Poll CD failed with error code %d\n", status);
return -EPERM;
@@ -478,3 +485,362 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
 
return fpgamgr_program_finish();
 }
+
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core)
+{
+   const char *cff_filename = NULL;
+   const char *cell;
+   int nodeoffset;
+
+   nodeoffset = fdtdec_next_compatible(fdt, 0,
+COMPAT_ALTERA_SOCFPGA_FPGA0);
+   if (nodeoffset >= 0) {
+   if (core) {
+   cell = fdt_getprop(fdt,
+   nodeoffset,
+   "altr,bitstream_core",
+   len);
+   }
+   else {
+   cell = fdt_getprop(fdt, nodeoffset,
+   "altr,bitstream_periph", len);
+   }
+
+   if (cell)
+   cff_filename = cell;
+   }
+
+   return cff_filename;
+}
+
+const char *get_cff_devpart(const void *fdt, int *len)
+{
+   const char *cff_devpart = NULL;
+

[U-Boot] [PATCH v6 19/20] arm: socfpga: Enable DDR working

From: Tien Fong Chee 

SPL configures DDR by programming peripheral raw binary file
and calibrating DDR.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/spl.c   | 43 +++
 configs/socfpga_arria10_defconfig | 17 +---
 2 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index aba116d..60159b2 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -15,13 +15,19 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
+#include 
+#include 
+#include 
 #include 
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
@@ -29,6 +35,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BSIZE  4096
+#define PERIPH_RBF 0
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -197,6 +206,12 @@ void board_init_f(ulong dummy)
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 void spl_board_init(void)
 {
+   int rval = 0;
+   int len = 0;
+   u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
+   struct spl_boot_device bootdev;
+   fpga_fs_info fpga_fsinfo;
+
/* configuring the clock based on handoff */
cm_basic_init(gd->fdt_blob);
WATCHDOG_RESET();
@@ -214,6 +229,34 @@ void spl_board_init(void)
 
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
+
+   set_default_env(NULL);
+
+   bootdev.boot_device = spl_boot_device();
+
+   if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
+   fpga_fsinfo.interface = "mmc";
+   fpga_fsinfo.fstype = FS_TYPE_FAT;
+   }
+
+   fpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob,
+   &len,
+   PERIPH_RBF);
+
+   fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob,
+  &len);
+
+   if (fpga_fsinfo.dev_part)
+   env_set("FW_DEV_PART", fpga_fsinfo.dev_part);
+
+   /* Program peripheral RBF */
+   rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);
+
+   if (!rval) {
+   config_pins(gd->fdt_blob, "shared");
+
+   ddr_calibration_sequence();
+   }
 }
 
 void board_init_f(ulong dummy)
diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
index f7bcce3..f85064b 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -7,28 +7,39 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_FIT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FIT=y
 CONFIG_SPL=y
 CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_DOS_PARTITION=y
-# CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DOS_PARTITION=y
+CONFIG_SPL_FS_GENERIC=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_SPL_MMC_SUPPORT=y
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 20/20] arm: socfpga: Enable SPL booting U-boot

From: Tien Fong Chee 

Enable SPL successfully boot to U-boot.

Signed-off-by: Tien Fong Chee 
---
 configs/socfpga_arria10_defconfig | 41 ++-
 1 file changed, 36 insertions(+), 5 deletions(-)

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
index f85064b..8cecc88 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -1,16 +1,18 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_arria10"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
 CONFIG_FIT=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_SPL_FAT_SUPPORT=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
@@ -18,15 +20,23 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DOS_PARTITION=y
 CONFIG_SPL_FS_GENERIC=y
 CONFIG_CMD_FAT=y
@@ -39,7 +49,28 @@ CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="altera"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v6 07/20] common: Generic firmware loader for file system

On Isn, 2017-12-11 at 18:06 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> This is file system generic loader which can be used to load
> the file image from the storage into target such as memory.
> The consumer driver would then use this loader to program whatever,
> ie. the FPGA device.
> 
> Signed-off-by: Tien Fong Chee 
> ---
>  common/Makefile |   1 +
>  common/fs_loader.c  | 299
> 
>  include/fs_loader.h |  30 ++
>  3 files changed, 330 insertions(+)
>  create mode 100644 common/fs_loader.c
>  create mode 100644 include/fs_loader.h
> 
> diff --git a/common/Makefile b/common/Makefile
> index cec506f..2934221 100644
> --- a/common/Makefile
> +++ b/common/Makefile
> @@ -130,3 +130,4 @@ obj-$(CONFIG_CMD_DFU) += dfu.o
>  obj-y += command.o
>  obj-y += s_record.o
>  obj-y += xyzModem.o
> +obj-y += fs_loader.o
> diff --git a/common/fs_loader.c b/common/fs_loader.c
> new file mode 100644
> index 000..269af25
> --- /dev/null
> +++ b/common/fs_loader.c
> @@ -0,0 +1,299 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation 
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +static struct device_location default_locations[] = {
> + {
> + .name = "mmc",
> + .devpart = "0:1",
> + },
> + {
> + .name = "usb",
> + .devpart = "0:1",
> + },
> + {
> + .name = "sata",
> + .devpart = "0:1",
> + },
> +};
> +
> +/* USB build is not supported yet in SPL */
> +#ifndef CONFIG_SPL_BUILD
> +#ifdef CONFIG_USB_STORAGE
> +static int init_usb(void)
> +{
> + int err;
> +
> + err = usb_init();
> + if (err)
> + return err;
> +
> +#ifndef CONFIG_DM_USB
> + err = usb_stor_scan(1) < 0 ? -ENODEV : 0;
> +#endif
> +
> + return err;
> +}
> +#else
> +static int init_usb(void)
> +{
> + printf("Error: Cannot load flash image: no USB support\n");
> + return -ENOSYS;
> +}
> +#endif
> +#endif
> +
> +#ifdef CONFIG_SATA
> +static int init_storage_sata(void)
> +{
> + return sata_probe(0);
> +}
> +#else
> +static int init_storage_sata(void)
> +{
> + printf("Error: Cannot load image: no SATA support\n");
> + return -ENOSYS;
> +}
> +#endif
> +
> +#ifdef CONFIG_CMD_UBIFS
> +static int mount_ubifs(struct device_location *location)
> +{
> + int ret;
> + char cmd[32];
> +
> + sprintf(cmd, "ubi part %s", location->mtdpart);
> +
> + ret = run_command(cmd, 0);
> + if (ret)
> + return ret;
> +
> + sprintf(cmd, "ubifsmount %s", location->ubivol);
> +
> + ret = run_command(cmd, 0);
> +
> + return ret;
> +}
> +
> +static int umount_ubifs(void)
> +{
> + return run_command("ubifsumount", 0);
> +}
> +#else
> +static int mount_ubifs(struct device_location *location)
> +{
> + printf("Error: Cannot load image: no UBIFS support\n");
> + return -ENOSYS;
> +}
> +#endif
> +
> +#if defined(CONFIG_SPL_MMC_SUPPORT) && defined(CONFIG_SPL_BUILD)
> +static int init_mmc(void)
> +{
> + /* Just for the case MMC is not yet initialized */
> + struct mmc *mmc = NULL;
> + int err;
> +
> + spl_mmc_find_device(&mmc, spl_boot_device());
> +
> + err = mmc_init(mmc);
> + if (err) {
> + printf("spl: mmc init failed with error: %d\n",
> err);
> + return err;
> + }
> +
> + return err;
> +}
> +#else
> +static int init_mmc(void)
> +{
> + /* Expect somewhere already initialize MMC */
> + return 0;
> +}
> +#endif
> +
> +static int select_fs_dev(struct device_location *location)
> +{
> + int ret = 0;
> +
> + if (!strcmp("mmc", location->name)) {
> + ret = fs_set_blk_dev("mmc", location->devpart,
> FS_TYPE_ANY);
> + }
> + else if (!strcmp("usb", location->name)) {
> + ret = fs_set_blk_dev("usb", location->devpart,
> FS_TYPE_ANY);
> + }
> + else if (!strcmp("sata", location->name)) {
> + ret = fs_set_blk_dev("sata", location->devpart,
> FS_TYPE_ANY);
> + }
> + else if (!strcmp("ubi", location->name)) {
> + if (location->ubivol != NULL)
> + ret = fs_set_blk_dev("ubi", NULL,
> FS_TYPE_UBIFS);
> + else
> + ret = -ENODEV;
> + }
> + else {
> + printf("Error: unsupported location storage.\n");
> + return -ENODEV;
> + }
> +
> + if (ret)
> + printf("Error: could not access storage.\n");
> +
> + return ret;
> +}
> +
> +static int init_storage_device(struct device_location *location)
> +{
> + int ret = 0;
> +#ifndef CONFIG_SPL_BUILD
> + /* USB build is not supported yet in SPL */
> + if (!strcmp("usb", location->name))
> + ret = init_usb();
> +#endif
> +
> + if (!strcmp("mmc", location->name))
> +

[U-Boot] [PATCH v6 03/20] arm: socfpga: Add Arria 10 SoCFPGA programming interface

From: Tien Fong Chee 

Add code necessary into the FPGA driver framework in U-Boot
so it can be used via the 'fpga' command for programing Arria 10
SoCFPGA.

Signed-off-by: Tien Fong Chee 
---
 cmd/fpga.c|  2 +-
 drivers/fpga/altera.c | 40 
 drivers/fpga/fpga.c   |  8 
 include/fpga.h|  2 ++
 4 files changed, 43 insertions(+), 9 deletions(-)

diff --git a/cmd/fpga.c b/cmd/fpga.c
index ac6f504..3cb0bcd 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,
   "(Xilinx only)\n"
 #endif
 #if defined(CONFIG_CMD_FPGA_LOADFS)
-  "Load device from filesystem (FAT by default) (Xilinx only)\n"
+  "Load device from filesystem (FAT by default)\n"
   "  loadfs [dev] [address] [image size] [blocksize] \n"
   "[] \n"
 #endif
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 135a357..a03e835 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -23,25 +23,31 @@ static const struct altera_fpga {
enum altera_family  family;
const char  *name;
int (*load)(Altera_desc *, const void *, size_t);
+   int (*loadfs)(Altera_desc *, const void *, size_t, fpga_fs_info *);
int (*dump)(Altera_desc *, const void *, size_t);
int (*info)(Altera_desc *);
 } altera_fpga[] = {
 #if defined(CONFIG_FPGA_ACEX1K)
-   { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
-   { Altera_CYC2,   "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
+   { Altera_ACEX1K, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
+ACEX1K_info },
+   { Altera_CYC2,   "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
+ACEX1K_info },
 #elif defined(CONFIG_FPGA_CYCLON2)
-   { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
-   { Altera_CYC2,   "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
+   { Altera_ACEX1K, "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info },
+   { Altera_CYC2,   "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info },
 #endif
 #if defined(CONFIG_FPGA_STRATIX_II)
-   { Altera_StratixII, "StratixII", StratixII_load,
+   { Altera_StratixII, "StratixII", StratixII_load, NULL,
  StratixII_dump, StratixII_info },
 #endif
 #if defined(CONFIG_FPGA_STRATIX_V)
-   { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
+   { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL, NULL },
 #endif
-#if defined(CONFIG_FPGA_SOCFPGA)
-   { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
+#if defined(CONFIG_FPGA_SOCFPGA) && defined(CONFIG_CMD_FPGA_LOADFS)
+   { Altera_SoCFPGA, "SoC FPGA", socfpga_load, socfpga_loadfs, NULL,
+NULL },
+#elif defined(CONFIG_FPGA_SOCFPGA)
+   { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL, NULL },
 #endif
 };
 
@@ -174,3 +180,21 @@ int altera_info(Altera_desc *desc)
 
return FPGA_SUCCESS;
 }
+
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+  fpga_fs_info *fpga_fsinfo)
+{
+   const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
+
+   if (!fpga)
+   return FPGA_FAIL;
+
+   debug_cond(FPGA_DEBUG, "%s: Launching the %s FS Loader...\n",
+  __func__, fpga->name);
+   if (fpga->loadfs)
+   return fpga->loadfs(desc, buf, bsize, fpga_fsinfo);
+
+   return -EINVAL;
+}
+#endif
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index e0fb1b4..42e901e 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_no_sup((char *)__func__, "Xilinx devices");
 #endif
break;
+#if defined(CONFIG_FPGA_ALTERA)
+   case fpga_altera:
+   ret_val = altera_loadfs(desc->devdesc, buf, size,
+   fpga_fsinfo);
+#else
+   fpga_no_sup((char *)__func__, "Altera devices");
+#endif
+   break;
default:
printf("%s: Invalid or unsupported device type %d\n",
   __func__, desc->devtype);
diff --git a/include/fpga.h b/include/fpga.h
index d768fb1..8920016 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -56,8 +56,10 @@ int fpga_count(void);
 const fpga_desc *const fpga_get_desc(int devnum);
 int fpga_load(int devnum, const void *buf, size_t bsize,
  bitstream_type bstype);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
 int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
+#endif
 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
   bitstream_type bstype);
 int fpga_dump(int devnum, const void *buf, s

[U-Boot] [PATCH v6 06/20] arm: socfpga: Remove static declaration on spl_mmc_find_device function

From: Tien Fong Chee 

This patch removes the static declation on spl_mmc_find_device_function
so this function is accessible by the caller from other file. This patch
is required for later patch.

Signed-off-by: Tien Fong Chee 
---
 common/spl/spl_mmc.c | 2 +-
 include/spl.h| 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index b57e0b0..183d05a 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -114,7 +114,7 @@ static int spl_mmc_get_device_index(u32 boot_device)
return -ENODEV;
 }
 
-static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
 {
 #if CONFIG_IS_ENABLED(DM_MMC)
struct udevice *dev;
diff --git a/include/spl.h b/include/spl.h
index 308ce7b..912983a 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -10,6 +10,7 @@
 /* Platform-specific defines */
 #include 
 #include 
+#include 
 
 /* Value in r0 indicates we booted from U-Boot */
 #define UBOOT_NOT_LOADED_FROM_SPL  0x13578642
@@ -72,6 +73,7 @@ void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(const u32 boot_device);
 void spl_set_bd(void);
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
 
 /**
  * spl_set_header_raw_uboot() - Set up a standard SPL image structure
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 15/20] arm: socfpga: Improve comments for Intel SoCFPGA program header

From: Tien Fong Chee 

Adding some details about size in bytes to each section.

Signed-off-by: Tien Fong Chee 
Reviewed-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h 
b/arch/arm/mach-socfpga/include/mach/boot0.h
index d6b9435..7e8a2b1 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -14,8 +14,8 @@ _start:
.balignl 64,0xf33db33f;
 
.word   0x1337c0d3; /* SoCFPGA preloader validation word */
-   .word   0xc01df00d; /* Version, flags, length */
-   .word   0xcafec0d3; /* Checksum, zero-pad */
+   .word   0xc01df00d; /* Header length(2B),flags(1B),version(1B) */
+   .word   0xcafec0d3; /* Simple checksum(2B),spare offset(2B) */
nop;
 
b reset;/* SoCFPGA jumps here */
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 10/20] arm: socfpga: Rename the gen5 sdram driver to more specific name

From: Tien Fong Chee 

Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/sdram.h | 432 +
 .../include/mach/{sdram.h => sdram_gen5.h} |   6 +-
 drivers/ddr/altera/Makefile|   2 +-
 drivers/ddr/altera/{sdram.c => sdram_gen5.c}   |   0
 4 files changed, 7 insertions(+), 433 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
 rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index b11228f..137e073 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -8,435 +8,9 @@
 
 #ifndef __ASSEMBLY__
 
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
-#define SDR_CTRLGRP_ADDRESS(SOCFPGA_SDR_ADDRESS | 0x5000)
-
-struct socfpga_sdr_ctrl {
-   u32 ctrl_cfg;
-   u32 dram_timing1;
-   u32 dram_timing2;
-   u32 dram_timing3;
-   u32 dram_timing4;   /* 0x10 */
-   u32 lowpwr_timing;
-   u32 dram_odt;
-   u32 extratime1;
-   u32 __padding0[3];
-   u32 dram_addrw; /* 0x2c */
-   u32 dram_if_width;  /* 0x30 */
-   u32 dram_dev_width;
-   u32 dram_sts;
-   u32 dram_intr;
-   u32 sbe_count;  /* 0x40 */
-   u32 dbe_count;
-   u32 err_addr;
-   u32 drop_count;
-   u32 drop_addr;  /* 0x50 */
-   u32 lowpwr_eq;
-   u32 lowpwr_ack;
-   u32 static_cfg;
-   u32 ctrl_width; /* 0x60 */
-   u32 cport_width;
-   u32 cport_wmap;
-   u32 cport_rmap;
-   u32 rfifo_cmap; /* 0x70 */
-   u32 wfifo_cmap;
-   u32 cport_rdwr;
-   u32 port_cfg;
-   u32 fpgaport_rst;   /* 0x80 */
-   u32 __padding1;
-   u32 fifo_cfg;
-   u32 protport_default;
-   u32 prot_rule_addr; /* 0x90 */
-   u32 prot_rule_id;
-   u32 prot_rule_data;
-   u32 prot_rule_rdwr;
-   u32 __padding2[3];
-   u32 mp_priority;/* 0xac */
-   u32 mp_weight0; /* 0xb0 */
-   u32 mp_weight1;
-   u32 mp_weight2;
-   u32 mp_weight3;
-   u32 mp_pacing0; /* 0xc0 */
-   u32 mp_pacing1;
-   u32 mp_pacing2;
-   u32 mp_pacing3;
-   u32 mp_threshold0;  /* 0xd0 */
-   u32 mp_threshold1;
-   u32 mp_threshold2;
-   u32 __padding3[29];
-   u32 phy_ctrl0;  /* 0x150 */
-   u32 phy_ctrl1;
-   u32 phy_ctrl2;
-};
-
-/* SDRAM configuration structure for the SPL. */
-struct socfpga_sdram_config {
-   u32 ctrl_cfg;
-   u32 dram_timing1;
-   u32 dram_timing2;
-   u32 dram_timing3;
-   u32 dram_timing4;
-   u32 lowpwr_timing;
-   u32 dram_odt;
-   u32 extratime1;
-   u32 dram_addrw;
-   u32 dram_if_width;
-   u32 dram_dev_width;
-   u32 dram_intr;
-   u32 lowpwr_eq;
-   u32 static_cfg;
-   u32 ctrl_width;
-   u32 cport_width;
-   u32 cport_wmap;
-   u32 cport_rmap;
-   u32 rfifo_cmap;
-   u32 wfifo_cmap;
-   u32 cport_rdwr;
-   u32 port_cfg;
-   u32 fpgaport_rst;
-   u32 fifo_cfg;
-   u32 mp_priority;
-   u32 mp_weight0;
-   u32 mp_weight1;
-   u32 mp_weight2;
-   u32 mp_weight3;
-   u32 mp_pacing0;
-   u32 mp_pacing1;
-   u32 mp_pacing2;
-   u32 mp_pacing3;
-   u32 mp_threshold0;
-   u32 mp_threshold1;
-   u32 mp_threshold2;
-   u32 phy_ctrl0;
-};
-
-struct socfpga_sdram_rw_mgr_config {
-   u8  activate_0_and_1;
-   u8  activate_0_and_1_wait1;
-   u8  activate_0_and_1_wait2;
-   u8  activate_1;
-   u8  clear_dqs_enable;
-   u8  guaranteed_read;
-   u8  guaranteed_read_cont;
-   u8  guaranteed_write;
-   u8  guaranteed_write_wait0;
-   u8  guaranteed_write_wait1;
-   u8  guaranteed_write_wait2;
-   u8  guaranteed_writ

[U-Boot] [PATCH v6 16/20] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

From: Tien Fong Chee 

Enhance preloader header with both additional program length and program
entry offset attributes, which offset is relative to the start of program
header.

Signed-off-by: Tien Fong Chee 
Reviewed-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/boot0.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h 
b/arch/arm/mach-socfpga/include/mach/boot0.h
index 7e8a2b1..e6db659 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -15,6 +15,13 @@ _start:
 
.word   0x1337c0d3; /* SoCFPGA preloader validation word */
.word   0xc01df00d; /* Header length(2B),flags(1B),version(1B) */
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+   .word   0xfeedface; /* Program length(4B) */
+   .word   0xf00dcafe; /*
+* Program entry offset(4B),relative to
+* the start of program header
+*/
+#endif
.word   0xcafec0d3; /* Simple checksum(2B),spare offset(2B) */
nop;
 
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 18/20] arm: socfpga: Adding SoCFPGA info for both SPL and U-Boot

From: Tien Fong Chee 

SoC FPGA info is required in both SPL and U-Boot.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/board.c| 4 
 arch/arm/mach-socfpga/misc_arria10.c | 5 -
 arch/arm/mach-socfpga/spl.c  | 6 ++
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 8d3b515..7beb347 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -31,6 +32,9 @@ int board_init(void)
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
/* configuring the clock based on handoff */
cm_basic_init(gd->fdt_blob);
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
 #endif
 
return 0;
diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
index 9d751f6..8760ac9 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -94,11 +94,6 @@ int arch_early_init_r(void)
/* assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();
 
-   /* configuring the clock based on handoff */
-   /* TODO: Add call to cm_basic_init() */
-
-   /* Add device descriptor to FPGA device table */
-   socfpga_fpga_add();
return 0;
 }
 #else
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 71bae82..aba116d 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -208,6 +209,11 @@ void spl_board_init(void)
 
/* enable console uart printing */
preloader_console_init();
+
+   WATCHDOG_RESET();
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
 }
 
 void board_init_f(ulong dummy)
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 12/20] arm: socfpga: Add DDR driver for Arria 10

From: Tien Fong Chee 

Add DDR driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +
 drivers/ddr/altera/Makefile|   1 +
 drivers/ddr/altera/sdram_arria10.c | 737 +
 4 files changed, 742 insertions(+)
 create mode 100644 drivers/ddr/altera/sdram_arria10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index 137e073..33f830b 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -10,6 +10,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
index 1d7b7c1..e7a2503 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -8,6 +8,7 @@
 #define _SOCFPGA_SDRAM_ARRIA10_H_
 
 #ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
 
 struct socfpga_ecc_hmc {
u32 ip_rev_id;
@@ -204,6 +205,7 @@ struct socfpga_io48_mmr {
u32 niosreserve1;
u32 niosreserve2;
 };
+
 #endif /*__ASSEMBLY__*/
 
 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK0x1F00
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index ac4ab85..02f8b7c 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -10,4 +10,5 @@
 
 ifdef CONFIG_ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 endif
diff --git a/drivers/ddr/altera/sdram_arria10.c 
b/drivers/ddr/altera/sdram_arria10.c
new file mode 100644
index 000..e60a724
--- /dev/null
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -0,0 +1,737 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_mmr_init(void);
+static u64 sdram_size_calc(void);
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK   (0x1)
+
+#define ARRIA_DDR_CONFIG(A, B, C, R) \
+   (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define DDR_CONFIG_ELEMENTSARRAY_SIZE(ddr_config)
+#define DDR_REG_SEQ2CORE0xFFD0507C
+#define DDR_REG_CORE2SEQ0xFFD05078
+#define DDR_READ_LATENCY_DELAY 40
+#define DDR_SIZE_2GB_HEX   0x8000
+#define DDR_MAX_TRIES  0x0010
+
+#define IO48_MMR_DRAMSTS   0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE00xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE10xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE20xFFCFA118
+
+#define SEQ2CORE_MASK  0xF
+#define CORE2SEQ_INT_REQ   0xF
+#define SEQ2CORE_INT_RESP_BIT  3
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+   (void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+   (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
+   *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+   (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+
+/* The following are the supported configurations */
+static u32 ddr_config[] = {
+   /* Chip - Row - Bank - Column Style */
+   /* All Types */
+   ARRIA_DDR_CONFIG(0, 3, 10, 12),
+   ARRIA_DDR_CONFIG(0, 3, 10, 13),
+   ARRIA_DDR_CONFIG(0, 3, 10, 14),
+   ARRIA_DDR_CONFIG(0, 3, 10, 15),
+   ARRIA_DDR_CONFIG(0, 3, 10, 16),
+   ARRIA_DDR_CONFIG(0, 3, 10, 17),
+   /* LPDDR x16 */
+   ARRIA_DDR_CONFIG(0, 3, 11, 14),
+   ARRIA_DDR_CONFIG(0, 3, 11, 15),
+   ARRIA_DDR_CONFIG(0, 3, 11, 16),
+   ARRIA_DDR_CONFIG(0, 3, 12, 15),
+   /* DDR4 Only */
+   ARRIA_DDR_CONFIG(0, 4, 10, 14),
+   ARRIA_DDR_CONFIG(0, 4, 10, 15),
+   ARRIA_DDR_CONFIG(0, 4, 10, 16),
+   ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
+   /* Chip - Bank - Row - Column Style */
+   ARRIA_DDR_CONFIG(1, 3, 10, 12),
+   ARRIA_DDR_CONFIG(1, 3, 10, 13),
+   ARRIA_DDR_CONFIG(1, 3, 10, 14),
+   ARRIA_DDR_CONFIG(1, 3, 10, 15),
+   ARRIA_DDR_CONFIG(1, 3, 10, 16),
+   ARRIA_DDR_CONFIG(1, 3, 10, 17),
+   ARRIA_DDR_CONFIG(1, 3, 11, 14),
+   ARRIA_DDR_CONFIG(1, 3, 11, 15),
+   ARRIA_DDR_CONFIG(1, 3, 11, 16),
+   ARRIA_DDR_CONFIG(1,

Re: [U-Boot] [PATCH v6 07/20] common: Generic firmware loader for file system

On 12/11/2017 11:08 AM, Chee, Tien Fong wrote:
> On Isn, 2017-12-11 at 18:06 +0800, tien.fong.c...@intel.com wrote:
>> From: Tien Fong Chee 
>>
>> This is file system generic loader which can be used to load
>> the file image from the storage into target such as memory.
>> The consumer driver would then use this loader to program whatever,
>> ie. the FPGA device.
>>
>> Signed-off-by: Tien Fong Chee 

You should break this patch out first , get it in and then resubmit the
20 other patches so you're not saturating everyones' mailboxes.

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v6 07/20] common: Generic firmware loader for file system

On Isn, 2017-12-11 at 11:15 +0100, Marek Vasut wrote:
> On 12/11/2017 11:08 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-12-11 at 18:06 +0800, tien.fong.c...@intel.com wrote:
> > > 
> > > From: Tien Fong Chee 
> > > 
> > > This is file system generic loader which can be used to load
> > > the file image from the storage into target such as memory.
> > > The consumer driver would then use this loader to program
> > > whatever,
> > > ie. the FPGA device.
> > > 
> > > Signed-off-by: Tien Fong Chee 
> You should break this patch out first , get it in and then resubmit
> the
> 20 other patches so you're not saturating everyones' mailboxes.
> 
Okay.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 1/2] arm: socfpga: Remove static declaration on spl_mmc_find_device function

From: Tien Fong Chee 

This patch removes the static declation on spl_mmc_find_device_function
so this function is accessible by the caller from other file. This patch
is required for later patch.

Signed-off-by: Tien Fong Chee 
---
 common/spl/spl_mmc.c | 2 +-
 include/spl.h| 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index b57e0b0..183d05a 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -114,7 +114,7 @@ static int spl_mmc_get_device_index(u32 boot_device)
return -ENODEV;
 }
 
-static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
 {
 #if CONFIG_IS_ENABLED(DM_MMC)
struct udevice *dev;
diff --git a/include/spl.h b/include/spl.h
index 308ce7b..912983a 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -10,6 +10,7 @@
 /* Platform-specific defines */
 #include 
 #include 
+#include 
 
 /* Value in r0 indicates we booted from U-Boot */
 #define UBOOT_NOT_LOADED_FROM_SPL  0x13578642
@@ -72,6 +73,7 @@ void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(const u32 boot_device);
 void spl_set_bd(void);
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
 
 /**
  * spl_set_header_raw_uboot() - Set up a standard SPL image structure
-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 0/2] Generic firmware loader

From: Tien Fong Chee 

This patchset contains generic firmware loader which is very close to Linux
firmware loader but for U-Boot framework. Generic firmware loader can be used
load whatever into target location, and then consumer driver would use it to
program whatever, ie. the FPGA.

This series is working on top of u-boot-socfpga.git -
 http://git.denx.de/u-boot-socfpga.git .

Tien Fong Chee (2):
  arm: socfpga: Remove static declaration on spl_mmc_find_device
function
  common: Generic firmware loader for file system

 common/Makefile  |   1 +
 common/fs_loader.c   | 299 +++
 common/spl/spl_mmc.c |   2 +-
 include/fs_loader.h  |  30 ++
 include/spl.h|   2 +
 5 files changed, 333 insertions(+), 1 deletion(-)
 create mode 100644 common/fs_loader.c
 create mode 100644 include/fs_loader.h

-- 
2.2.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 2/2] common: Generic firmware loader for file system

From: Tien Fong Chee 

This is file system generic loader which can be used to load
the file image from the storage into target such as memory.
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.

Signed-off-by: Tien Fong Chee 
---
 common/Makefile |   1 +
 common/fs_loader.c  | 299 
 include/fs_loader.h |  30 ++
 3 files changed, 330 insertions(+)
 create mode 100644 common/fs_loader.c
 create mode 100644 include/fs_loader.h

diff --git a/common/Makefile b/common/Makefile
index cec506f..2934221 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -130,3 +130,4 @@ obj-$(CONFIG_CMD_DFU) += dfu.o
 obj-y += command.o
 obj-y += s_record.o
 obj-y += xyzModem.o
+obj-y += fs_loader.o
diff --git a/common/fs_loader.c b/common/fs_loader.c
new file mode 100644
index 000..269af25
--- /dev/null
+++ b/common/fs_loader.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static struct device_location default_locations[] = {
+   {
+   .name = "mmc",
+   .devpart = "0:1",
+   },
+   {
+   .name = "usb",
+   .devpart = "0:1",
+   },
+   {
+   .name = "sata",
+   .devpart = "0:1",
+   },
+};
+
+/* USB build is not supported yet in SPL */
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_USB_STORAGE
+static int init_usb(void)
+{
+   int err;
+
+   err = usb_init();
+   if (err)
+   return err;
+
+#ifndef CONFIG_DM_USB
+   err = usb_stor_scan(1) < 0 ? -ENODEV : 0;
+#endif
+
+   return err;
+}
+#else
+static int init_usb(void)
+{
+   printf("Error: Cannot load flash image: no USB support\n");
+   return -ENOSYS;
+}
+#endif
+#endif
+
+#ifdef CONFIG_SATA
+static int init_storage_sata(void)
+{
+   return sata_probe(0);
+}
+#else
+static int init_storage_sata(void)
+{
+   printf("Error: Cannot load image: no SATA support\n");
+   return -ENOSYS;
+}
+#endif
+
+#ifdef CONFIG_CMD_UBIFS
+static int mount_ubifs(struct device_location *location)
+{
+   int ret;
+   char cmd[32];
+
+   sprintf(cmd, "ubi part %s", location->mtdpart);
+
+   ret = run_command(cmd, 0);
+   if (ret)
+   return ret;
+
+   sprintf(cmd, "ubifsmount %s", location->ubivol);
+
+   ret = run_command(cmd, 0);
+
+   return ret;
+}
+
+static int umount_ubifs(void)
+{
+   return run_command("ubifsumount", 0);
+}
+#else
+static int mount_ubifs(struct device_location *location)
+{
+   printf("Error: Cannot load image: no UBIFS support\n");
+   return -ENOSYS;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT) && defined(CONFIG_SPL_BUILD)
+static int init_mmc(void)
+{
+   /* Just for the case MMC is not yet initialized */
+   struct mmc *mmc = NULL;
+   int err;
+
+   spl_mmc_find_device(&mmc, spl_boot_device());
+
+   err = mmc_init(mmc);
+   if (err) {
+   printf("spl: mmc init failed with error: %d\n", err);
+   return err;
+   }
+
+   return err;
+}
+#else
+static int init_mmc(void)
+{
+   /* Expect somewhere already initialize MMC */
+   return 0;
+}
+#endif
+
+static int select_fs_dev(struct device_location *location)
+{
+   int ret = 0;
+
+   if (!strcmp("mmc", location->name)) {
+   ret = fs_set_blk_dev("mmc", location->devpart, FS_TYPE_ANY);
+   }
+   else if (!strcmp("usb", location->name)) {
+   ret = fs_set_blk_dev("usb", location->devpart, FS_TYPE_ANY);
+   }
+   else if (!strcmp("sata", location->name)) {
+   ret = fs_set_blk_dev("sata", location->devpart, FS_TYPE_ANY);
+   }
+   else if (!strcmp("ubi", location->name)) {
+   if (location->ubivol != NULL)
+   ret = fs_set_blk_dev("ubi", NULL, FS_TYPE_UBIFS);
+   else
+   ret = -ENODEV;
+   }
+   else {
+   printf("Error: unsupported location storage.\n");
+   return -ENODEV;
+   }
+
+   if (ret)
+   printf("Error: could not access storage.\n");
+
+   return ret;
+}
+
+static int init_storage_device(struct device_location *location)
+{
+   int ret = 0;
+#ifndef CONFIG_SPL_BUILD
+   /* USB build is not supported yet in SPL */
+   if (!strcmp("usb", location->name))
+   ret = init_usb();
+#endif
+
+   if (!strcmp("mmc", location->name))
+   ret = init_mmc();
+
+   if (!strcmp("sata", location->name))
+   ret = init_storage_sata();
+
+   if (location->ubivol != NULL)
+   ret = mount_ubifs(location);
+
+   return ret;
+}
+
+static void set_storage_devpart(char *name, char *devpart)
+{
+   size_t i;
+
+   for (i

Re: [U-Boot] [PATCH 1/2] arm: socfpga: Remove static declaration on spl_mmc_find_device function

On 12/11/2017 11:53 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 

So the tags would imply this has a lot to do with SoCFPGA, but this is
not touching any file in the SoCFPGA. The tags are thus completely bogus.

> This patch removes the static declation on spl_mmc_find_device_function
> so this function is accessible by the caller from other file. This patch
> is required for later patch.
> 
> Signed-off-by: Tien Fong Chee 
> ---
>  common/spl/spl_mmc.c | 2 +-
>  include/spl.h| 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
> index b57e0b0..183d05a 100644
> --- a/common/spl/spl_mmc.c
> +++ b/common/spl/spl_mmc.c
> @@ -114,7 +114,7 @@ static int spl_mmc_get_device_index(u32 boot_device)
>   return -ENODEV;
>  }
>  
> -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
>  {
>  #if CONFIG_IS_ENABLED(DM_MMC)
>   struct udevice *dev;
> diff --git a/include/spl.h b/include/spl.h
> index 308ce7b..912983a 100644
> --- a/include/spl.h
> +++ b/include/spl.h
> @@ -10,6 +10,7 @@
>  /* Platform-specific defines */
>  #include 
>  #include 
> +#include 
>  
>  /* Value in r0 indicates we booted from U-Boot */
>  #define UBOOT_NOT_LOADED_FROM_SPL0x13578642
> @@ -72,6 +73,7 @@ void preloader_console_init(void);
>  u32 spl_boot_device(void);
>  u32 spl_boot_mode(const u32 boot_device);
>  void spl_set_bd(void);
> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
>  
>  /**
>   * spl_set_header_raw_uboot() - Set up a standard SPL image structure
> 


-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 2/6] efi_loader: correctly setup device paths for block devices

According to the UEFI spec the numbering of partitions has to
start with 1.

Partion number 0 is reserved for the optional device path for
the complete block device.

Signed-off-by: Heinrich Schuchardt 
---
v3
no change
v2
Do not generate optional device path with partion number 0.
---
 lib/efi_loader/efi_device_path.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 42fe6e1185..6461ea9abc 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -420,7 +420,7 @@ static void *dp_part_fill(void *buf, struct blk_desc *desc, 
int part)
if (desc->part_type == PART_TYPE_ISO) {
struct efi_device_path_cdrom_path *cddp = buf;
 
-   cddp->boot_entry = part - 1;
+   cddp->boot_entry = part;
cddp->dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
cddp->dp.sub_type = DEVICE_PATH_SUB_TYPE_CDROM_PATH;
cddp->dp.length = sizeof(*cddp);
@@ -434,7 +434,7 @@ static void *dp_part_fill(void *buf, struct blk_desc *desc, 
int part)
hddp->dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
hddp->dp.sub_type = DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH;
hddp->dp.length = sizeof(*hddp);
-   hddp->partition_number = part - 1;
+   hddp->partition_number = part;
hddp->partition_start = info.start;
hddp->partition_end = info.size;
if (desc->part_type == PART_TYPE_EFI)
-- 
2.15.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 5/6] efi_loader: create full device path for block devices

When creating the device path of a block device it has to
comprise the block device itself and should not end at
its parent.

Signed-off-by: Heinrich Schuchardt 
---
v3
new patch
---
 lib/efi_loader/efi_device_path.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 31cdd38773..492a7643e6 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -368,7 +368,14 @@ static unsigned dp_part_size(struct blk_desc *desc, int 
part)
unsigned dpsize;
 
 #ifdef CONFIG_BLK
-   dpsize = dp_size(desc->bdev->parent);
+   {
+   struct udevice *dev;
+   int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+
+   if (ret)
+   dev = desc->bdev->parent;
+   dpsize = dp_size(dev);
+   }
 #else
dpsize = sizeof(ROOT) + sizeof(struct efi_device_path_usb);
 #endif
@@ -396,7 +403,14 @@ static void *dp_part_fill(void *buf, struct blk_desc 
*desc, int part)
disk_partition_t info;
 
 #ifdef CONFIG_BLK
-   buf = dp_fill(buf, desc->bdev->parent);
+   {
+   struct udevice *dev;
+   int ret = blk_find_device(desc->if_type, desc->devnum, &dev);
+
+   if (ret)
+   dev = desc->bdev->parent;
+   buf = dp_fill(buf, dev);
+   }
 #else
/*
 * We *could* make a more accurate path, by looking at if_type
-- 
2.15.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 3/6] efi_loader: correct DeviceNodeToText for media types

When converting device nodes and paths to text we should
stick to the UEFI spec.

Signed-off-by: Heinrich Schuchardt 
---
v3
Copy from packed structure to aligned memory to avoid unaligned
memory access.
v2
no change
---
 lib/efi_loader/efi_device_path_to_text.c | 43 +++-
 1 file changed, 31 insertions(+), 12 deletions(-)

diff --git a/lib/efi_loader/efi_device_path_to_text.c 
b/lib/efi_loader/efi_device_path_to_text.c
index 7159c974d4..50d9e911c0 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -90,7 +90,7 @@ static char *dp_msging(char *s, struct efi_device_path *dp)
case DEVICE_PATH_SUB_TYPE_MSG_USB: {
struct efi_device_path_usb *udp =
(struct efi_device_path_usb *)dp;
-   s += sprintf(s, "Usb(0x%x,0x%x)", udp->parent_port_number,
+   s += sprintf(s, "USB(0x%x,0x%x)", udp->parent_port_number,
 udp->usb_interface);
break;
}
@@ -124,10 +124,10 @@ static char *dp_msging(char *s, struct efi_device_path 
*dp)
case DEVICE_PATH_SUB_TYPE_MSG_MMC: {
const char *typename =
(dp->sub_type == DEVICE_PATH_SUB_TYPE_MSG_SD) ?
-   "SDCard" : "MMC";
+   "SD" : "eMMC";
struct efi_device_path_sd_mmc_path *sddp =
(struct efi_device_path_sd_mmc_path *)dp;
-   s += sprintf(s, "%s(Slot%u)", typename, sddp->slot_number);
+   s += sprintf(s, "%s(%u)", typename, sddp->slot_number);
break;
}
default:
@@ -137,6 +137,13 @@ static char *dp_msging(char *s, struct efi_device_path *dp)
return s;
 }
 
+/*
+ * Convert a media device path node to text.
+ *
+ * @s  output buffer
+ * @dp device path node
+ * @return next unused buffer address
+ */
 static char *dp_media(char *s, struct efi_device_path *dp)
 {
switch (dp->sub_type) {
@@ -144,21 +151,33 @@ static char *dp_media(char *s, struct efi_device_path *dp)
struct efi_device_path_hard_drive_path *hddp =
(struct efi_device_path_hard_drive_path *)dp;
void *sig = hddp->partition_signature;
+   u64 start;
+   u64 end;
+
+   /* Copy from packed structure to aligned memory */
+   memcpy(&start, &hddp->partition_start, sizeof(start));
+   memcpy(&end, &hddp->partition_end, sizeof(end));
 
switch (hddp->signature_type) {
-   case SIG_TYPE_MBR:
-   s += sprintf(s, "HD(Part%d,Sig%08x)",
-hddp->partition_number,
-*(uint32_t *)sig);
+   case SIG_TYPE_MBR: {
+   u32 signature;
+
+   memcpy(&signature, sig, sizeof(signature));
+   s += sprintf(
+   s, "HD(%d,MBR,0x%08x,0x%llx,0x%llx)",
+   hddp->partition_number, signature, start, end);
break;
+   }
case SIG_TYPE_GUID:
-   s += sprintf(s, "HD(Part%d,Sig%pUl)",
-hddp->partition_number, sig);
+   s += sprintf(
+   s, "HD(%d,GPT,%pUl,0x%llx,0x%llx)",
+   hddp->partition_number, sig, start, end);
break;
default:
-   s += sprintf(s, "HD(Part%d,MBRType=%02x,SigType=%02x)",
-hddp->partition_number, hddp->partmap_type,
-hddp->signature_type);
+   s += sprintf(
+   s, "HD(%d,0x%02x,0,0x%llx,0x%llx)",
+   hddp->partition_number, hddp->partmap_type,
+   start, end);
break;
}
 
-- 
2.15.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 1/6] efi_loader: correctly determine if an MMC device is an SD-card

The SD cards and eMMC devices have different device nodes.
The current coding interpretes all MMC devices as eMMC.

Signed-off-by: Heinrich Schuchardt 
---
v3
no change
v2
no change
---
 lib/efi_loader/efi_device_path.c | 24 +---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index b4e2f933cb..42fe6e1185 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -36,6 +36,24 @@ static const struct efi_device_path_vendor ROOT = {
.guid = U_BOOT_GUID,
 };
 
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+/*
+ * Determine if an MMC device is an SD card.
+ *
+ * @desc   block device descriptor
+ * @return true if the device is an SD card
+ */
+static bool is_sd(struct blk_desc *desc)
+{
+   struct mmc *mmc = find_mmc_device(desc->devnum);
+
+   if (!mmc)
+   return false;
+
+   return IS_SD(mmc) != 0U;
+}
+#endif
+
 static void *dp_alloc(size_t sz)
 {
void *buf;
@@ -298,9 +316,9 @@ static void *dp_fill(void *buf, struct udevice *dev)
struct blk_desc *desc = mmc_get_blk_desc(mmc);
 
sddp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
-   sddp->dp.sub_type = (desc->if_type == IF_TYPE_MMC) ?
-   DEVICE_PATH_SUB_TYPE_MSG_MMC :
-   DEVICE_PATH_SUB_TYPE_MSG_SD;
+   sddp->dp.sub_type = is_sd(desc) ?
+   DEVICE_PATH_SUB_TYPE_MSG_SD :
+   DEVICE_PATH_SUB_TYPE_MSG_MMC;
sddp->dp.length   = sizeof(*sddp);
sddp->slot_number = dev->seq;
 
-- 
2.15.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 6/6] efi_loader: support device path for IDE and SCSI disks

Correctly create the device path for IDE and SCSI disks.

Support for SATA remains to be done in a future patch.

Signed-off-by: Heinrich Schuchardt 
---
v3
new patch
---
 include/efi_api.h| 15 
 lib/efi_loader/efi_device_path.c | 64 
 lib/efi_loader/efi_device_path_to_text.c | 14 +++
 3 files changed, 93 insertions(+)

diff --git a/include/efi_api.h b/include/efi_api.h
index 584016dc30..46963f2891 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -329,12 +329,27 @@ struct efi_device_path_acpi_path {
 } __packed;
 
 #define DEVICE_PATH_TYPE_MESSAGING_DEVICE  0x03
+#  define DEVICE_PATH_SUB_TYPE_MSG_ATAPI   0x01
+#  define DEVICE_PATH_SUB_TYPE_MSG_SCSI0x02
 #  define DEVICE_PATH_SUB_TYPE_MSG_USB 0x05
 #  define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR0x0b
 #  define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS   0x0f
 #  define DEVICE_PATH_SUB_TYPE_MSG_SD  0x1a
 #  define DEVICE_PATH_SUB_TYPE_MSG_MMC 0x1d
 
+struct efi_device_path_atapi {
+   struct efi_device_path dp;
+   u8 primary_secondary;
+   u8 slave_master;
+   u16 logical_unit_number;
+} __packed;
+
+struct efi_device_path_scsi {
+   struct efi_device_path dp;
+   u16 target_id;
+   u16 logical_unit_number;
+} __packed;
+
 struct efi_device_path_usb {
struct efi_device_path dp;
u8 parent_port_number;
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 492a7643e6..ed30f1cabf 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -282,6 +282,23 @@ static unsigned dp_size(struct udevice *dev)
case UCLASS_SIMPLE_BUS:
/* stop traversing parents at this point: */
return sizeof(ROOT);
+#ifdef CONFIG_BLK
+   case UCLASS_BLK:
+   switch (dev->parent->uclass->uc_drv->id) {
+#ifdef CONFIG_IDE
+   case UCLASS_IDE:
+   return dp_size(dev->parent) +
+   sizeof(struct efi_device_path_atapi);
+#endif
+#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+   case UCLASS_SCSI:
+   return dp_size(dev->parent) +
+   sizeof(struct efi_device_path_scsi);
+#endif
+   default:
+   return dp_size(dev->parent);
+   }
+#endif
case UCLASS_MMC:
return dp_size(dev->parent) +
sizeof(struct efi_device_path_sd_mmc_path);
@@ -295,6 +312,13 @@ static unsigned dp_size(struct udevice *dev)
}
 }
 
+/*
+ * Recursively build a device path.
+ *
+ * @bufpointer to the end of the device path
+ * @devdevice
+ * @return pointer to the end of the device path
+ */
 static void *dp_fill(void *buf, struct udevice *dev)
 {
if (!dev || !dev->driver)
@@ -308,6 +332,46 @@ static void *dp_fill(void *buf, struct udevice *dev)
*vdp = ROOT;
return &vdp[1];
}
+#ifdef CONFIG_BLK
+   case UCLASS_BLK:
+   switch (dev->parent->uclass->uc_drv->id) {
+#ifdef CONFIG_IDE
+   case UCLASS_IDE: {
+   struct efi_device_path_atapi *dp =
+   dp_fill(buf, dev->parent);
+   struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+   dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+   dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_ATAPI;
+   dp->dp.length = sizeof(*dp);
+   dp->logical_unit_number = desc->devnum;
+   dp->primary_secondary = IDE_BUS(desc->devnum);
+   dp->slave_master = desc->devnum %
+   (CONFIG_SYS_IDE_MAXDEVICE /
+CONFIG_SYS_IDE_MAXBUS);
+   return &dp[1];
+   }
+#endif
+#if defined(CONFIG_SCSI) && defined(CONFIG_DM_SCSI)
+   case UCLASS_SCSI: {
+   struct efi_device_path_scsi *dp =
+   dp_fill(buf, dev->parent);
+   struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+   dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+   dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_SCSI;
+   dp->dp.length = sizeof(*dp);
+   dp->logical_unit_number = desc->lun;
+   dp->target_id = desc->target;
+   return &dp[1];
+   }
+#endif
+   default:
+   printf("unhandled parent class: %s (%u)\n",
+  dev->name, dev->driver->id);
+   return dp_fill(buf, dev->parent);
+   }
+#endif
 #if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)

[U-Boot] [PATCH v3 4/6] efi_loader: comments for dp_part_fill()

Add a description for dp_part_fill().
Reword a comment in the function.

Signed-off-by: Heinrich Schuchardt 
---
v3
new patch
---
 lib/efi_loader/efi_device_path.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 6461ea9abc..31cdd38773 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -384,6 +384,13 @@ static unsigned dp_part_size(struct blk_desc *desc, int 
part)
return dpsize;
 }
 
+/*
+ * Create a device path for a block device or one of its partitions.
+ *
+ * @bufbuffer to which the device path is wirtten
+ * @desc   block device descriptor
+ * @part   partition number, 0 identifies a block device
+ */
 static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
 {
disk_partition_t info;
@@ -396,7 +403,7 @@ static void *dp_part_fill(void *buf, struct blk_desc *desc, 
int part)
 * and handling all the different cases like we do for non-
 * legacy (ie CONFIG_BLK=y) case.  But most important thing
 * is just to have a unique device-path for if_type+devnum.
-* So map things to a fictional USB device:
+* So map things to a fictitious USB device.
 */
struct efi_device_path_usb *udp;
 
-- 
2.15.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 0/6] efi_loader: correct media device paths

For each disk we need partition device path with partion number 0.
The device node texts should match the UEFI spec.

v3:
Add support for IDE and SCSI disks.
Avoid an unaligned memory access.
v2:
Do not generate optional device path with partion number
0 for the whole block device.

Heinrich Schuchardt (6):
  efi_loader: correctly determine if an MMC device is an SD-card
  efi_loader: correctly setup device paths for block devices
  efi_loader: correct DeviceNodeToText for media types
  efi_loader: comments for dp_part_fill()
  efi_loader: create full device path for block devices
  efi_loader: support device path for IDE and SCSI disks

 include/efi_api.h|  15 
 lib/efi_loader/efi_device_path.c | 119 ---
 lib/efi_loader/efi_device_path_to_text.c |  57 +++
 3 files changed, 171 insertions(+), 20 deletions(-)

-- 
2.15.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] efi_loader: helloworld.c: Explicitly use .rodata for loaded_image_guid


On 12/11/2017 09:45 AM, Alexander Graf wrote:

Commit bbf75dd9345d0b ("efi_loader: output load options in helloworld")
introduced a const variable in efi_main() called loaded_image_guid which
got populated from a constant struct.

While you would usually expect a compiler to realize that this variable
should really just be a global pointer to .rodata, gcc disagrees and instead
puts it on the stack. Unfortunately in some implementations of gcc it does
so my calling memcpy() which we do not implement in our hello world
environment.

So let's explicitly move it to a global variable which in turn puts it in
.rodata reliably and gets rid of the memcpy().

Fixes: bbf75dd9345d0b ("efi_loader: output load options in helloworld")
Reported-by: Florian Fainelli 
Signed-off-by: Alexander Graf 
---
  lib/efi_loader/helloworld.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c
index e59c24c788..b8c147d7f2 100644
--- a/lib/efi_loader/helloworld.c
+++ b/lib/efi_loader/helloworld.c
@@ -13,6 +13,8 @@
  #include 
  #include 
  
+static const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID;

+
  /*
   * Entry point of the EFI application.
   *
@@ -26,7 +28,6 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle,
struct efi_simple_text_output_protocol *con_out = systable->con_out;
struct efi_boot_services *boottime = systable->boottime;
struct efi_loaded_image *loaded_image;
-   const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID;
efi_status_t ret;
  
  	con_out->output_string(con_out, L"Hello, world!\n");



Reviewed-by: Heinrich Schuchardt 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 2/2] common: Generic firmware loader for file system

2017-12-11 Thread Lothar Waßmann

Hi,

On Mon, 11 Dec 2017 18:53:46 +0800 tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
[...}
> +/*
> + * Prepare firmware struct;
> + * return -ve if fail.
> + */
> +static int _request_firmware_prepare(struct firmware **firmware_p,
> +  const char *name, void *dbuf,
> +  size_t size, u32 offset)
> +{
> + struct firmware *firmware = NULL;
> + int ret = 0;
> +
> + *firmware_p = NULL;
>
Sigh. This is useless...
> + if (!name || name[0] == '\0')
> + ret = -EINVAL;
> +
unless you do a 'return -EINVAL' here!

> + *firmware_p = firmware = calloc(1, sizeof(*firmware));
> +
> + if (!firmware) {
> + printf("%s: calloc(struct firmware) failed\n", __func__);
> + return -ENOMEM;
> + }
> +
> + firmware->name = name;
> + firmware->data = dbuf;
> + firmware->size = size;
> + firmware->offset = offset;
> +
> + return ret;
> +}
> +


Lothar Waßmann
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 2/4] ARM: meson: add clock measurement function

Hi Benjamin,

On 3 December 2017 at 02:17, Beniamino Galvani  wrote:
> Add add a function to measure the current clock rate.
>
> Signed-off-by: Beniamino Galvani 
> ---
>  arch/arm/include/asm/arch-meson/clock.h | 34 +
>  arch/arm/mach-meson/Makefile|  2 +-
>  arch/arm/mach-meson/clock.c | 45 
> +
>  3 files changed, 80 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/include/asm/arch-meson/clock.h
>  create mode 100644 arch/arm/mach-meson/clock.c
>
> diff --git a/arch/arm/include/asm/arch-meson/clock.h 
> b/arch/arm/include/asm/arch-meson/clock.h
> new file mode 100644
> index 00..b43b23386c
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-meson/clock.h
> @@ -0,0 +1,34 @@
> +/*
> + * Copyright 2017 - Beniamino Galvani 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +#ifndef _MESON_CLOCK_H_
> +#define _MESON_CLOCK_H_
> +
> +/* CBUS clock measure registers */
> +#define MSR_CLK_DUTY   0xc1108758
> +#define MSR_CLK_REG0   0xc110875c
> +#define MSR_CLK_REG1   0xc1108760
> +#define MSR_CLK_REG2   0xc1108764
> +
> +#define CLK_GP0_PLL4
> +#define CLK_GP1_PLL5
> +#define CLK_81 7
> +#define CLK_MMC23
> +#define CLK_MOD_ETH_TX 40
> +#define CLK_MOD_ETH_RX_RMII41
> +#define CLK_FCLK_DIV5  43
> +#define CLK_SD_EMMC_CLK_C  51
> +#define CLK_SD_EMMC_CLK_B  52

Are these constants in the dt-binding file somewhere?

> +
> +/* Clock gates */
> +#define HHI_GCLK_MPEG0 0x140
> +#define HHI_GCLK_MPEG1 0x144
> +#define HHI_GCLK_MPEG2 0x148
> +#define HHI_GCLK_OTHER 0x150
> +#define HHI_GCLK_AO0x154
> +
> +ulong meson_measure_clk_rate(unsigned int clk);

Please can you add a function comment and mention error-return values also?

> +
> +#endif
> diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
> index bf49b8b1e5..e7ea4fc5b0 100644
> --- a/arch/arm/mach-meson/Makefile
> +++ b/arch/arm/mach-meson/Makefile
> @@ -4,4 +4,4 @@
>  # SPDX-License-Identifier: GPL-2.0+
>  #
>
> -obj-y += board.o sm.o
> +obj-y += board.o clock.o sm.o
> diff --git a/arch/arm/mach-meson/clock.c b/arch/arm/mach-meson/clock.c
> new file mode 100644
> index 00..73be11e90d
> --- /dev/null
> +++ b/arch/arm/mach-meson/clock.c
> @@ -0,0 +1,45 @@
> +/*
> + * (C) Copyright 2016 Beniamino Galvani 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + * Clock rate measuring.
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +ulong meson_measure_clk_rate(unsigned int clk)
> +{
> +   ulong start;
> +   ulong mhz;
> +
> +   writel(0, MSR_CLK_REG0);
> +
> +   /* Set the measurement gate to 64uS */
> +   clrsetbits_le32(MSR_CLK_REG0, 0x, 64 - 1);
> +   clrbits_le32(MSR_CLK_REG0,
> +BIT(17) |  /* disable continuous measurement */
> +BIT(18));  /* disable interrupts */
> +   clrsetbits_le32(MSR_CLK_REG0,
> +   GENMASK(20, 26),
> +   clk << 20); /* select the clock */
> +   setbits_le32(MSR_CLK_REG0,
> +BIT(19) |  /* enable the clock */
> +BIT(16));  /* enable measuring */
> +
> +   start = get_timer(0);
> +   while (readl(MSR_CLK_REG0) & BIT(31)) {
> +   if (get_timer(start) > 100) {

How long does this take to measure? Is it up to 100ms?

> +   debug("could not measure clk %u rate\n", clk);
> +   return -ETIMEDOUT;
> +   }
> +   }
> +
> +   /* Disable measuring */
> +   clrbits_le32(MSR_CLK_REG0, BIT(16));
> +
> +   mhz = ((readl(MSR_CLK_REG2) + 31) & 0xf) >> 6;
> +   return mhz * 100;
> +}
> --
> 2.14.3
>


Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 3/4] clk: add Amlogic meson clock driver

Hi Benjamin,

On 3 December 2017 at 02:17, Beniamino Galvani  wrote:
> Introduce a basic clock driver for Amlogic Meson SoCs which supports
> enabling/disabling clock gates and getting their frequency.
>
> Signed-off-by: Beniamino Galvani 
> ---
>  arch/arm/mach-meson/Kconfig |   2 +
>  drivers/clk/Makefile|   1 +
>  drivers/clk/clk_meson.c | 196 
> 
>  3 files changed, 199 insertions(+)
>  create mode 100644 drivers/clk/clk_meson.c

Reviewed-by: Simon Glass 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 4/4] meson: use the clock driver

On 3 December 2017 at 02:17, Beniamino Galvani  wrote:
> Use the clk framework to initialize clocks from drivers that need them
> instead of having hardcoded frequencies and initializations from board
> code.
>
> Signed-off-by: Beniamino Galvani 
> ---
>  arch/arm/include/asm/arch-meson/gxbb.h | 10 --
>  arch/arm/include/asm/arch-meson/i2c.h  | 11 ---
>  board/amlogic/odroid-c2/odroid-c2.c|  4 +---
>  board/amlogic/p212/p212.c  |  3 +--
>  drivers/i2c/meson_i2c.c| 20 +---
>  5 files changed, 19 insertions(+), 29 deletions(-)
>  delete mode 100644 arch/arm/include/asm/arch-meson/i2c.h

Reviewed-by: Simon Glass 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK

The DDR DRAM calibration doesn't work on T-topology sometimes, so disable it.

Signed-off-by: Marek Vasut 
Cc: Stefano Babic 
---
 board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c 
b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index bb98f39f02..57ae7f15ce 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -387,10 +387,6 @@ void board_init_f(ulong dummy)
  &dhcom6sdl_grp_ioregs);
mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
 
-   /* Perform DDR DRAM calibration */
-   udelay(100);
-   mmdc_do_dqs_calibration(&dhcom_ddr_info);
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
 
-- 
2.15.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK

Hi Marek,

On Mon, Dec 11, 2017 at 1:19 PM, Marek Vasut  wrote:
> The DDR DRAM calibration doesn't work on T-topology sometimes, so disable it.
>
> Signed-off-by: Marek Vasut 
> Cc: Stefano Babic 
> ---
>  board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 
>  1 file changed, 4 deletions(-)
>
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c 
> b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> index bb98f39f02..57ae7f15ce 100644
> --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> @@ -387,10 +387,6 @@ void board_init_f(ulong dummy)
>   &dhcom6sdl_grp_ioregs);
> mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
>
> -   /* Perform DDR DRAM calibration */
> -   udelay(100);
> -   mmdc_do_dqs_calibration(&dhcom_ddr_info);

I also observed mmdc_do_dqs_calibration() failures and after applying
this patch from Eric they were gone:
https://lists.denx.de/pipermail/u-boot/2016-November/271596.html

Does this help to solve the mmdc_do_dqs_calibration() on your case too?
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK

On 12/11/2017 04:23 PM, Fabio Estevam wrote:
> Hi Marek,

Hi!

> On Mon, Dec 11, 2017 at 1:19 PM, Marek Vasut  wrote:
>> The DDR DRAM calibration doesn't work on T-topology sometimes, so disable it.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Stefano Babic 
>> ---
>>  board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 
>>  1 file changed, 4 deletions(-)
>>
>> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c 
>> b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
>> index bb98f39f02..57ae7f15ce 100644
>> --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
>> +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
>> @@ -387,10 +387,6 @@ void board_init_f(ulong dummy)
>>   &dhcom6sdl_grp_ioregs);
>> mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
>>
>> -   /* Perform DDR DRAM calibration */
>> -   udelay(100);
>> -   mmdc_do_dqs_calibration(&dhcom_ddr_info);
> 
> I also observed mmdc_do_dqs_calibration() failures and after applying
> this patch from Eric they were gone:
> https://lists.denx.de/pipermail/u-boot/2016-November/271596.html
> 
> Does this help to solve the mmdc_do_dqs_calibration() on your case too?

Nope, I'm not getting calibration failures, I'm getting bitflips at
runtime IFF I use the calibration. The calibration itself passes just fine.

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [GIT PULL] u-boot-uniphier/master

2017-12-11 Thread Masahiro Yamada

Hi Tom,

Please pull some more fixes and trivial changes.
Thanks!



The following changes since commit 335f7b1290ce24a729a9689a1db834c743226ca8:

  Merge git://git.denx.de/u-boot-mpc85xx (2017-12-08 12:02:01 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-uniphier.git master

for you to fetch changes up to 7f8e75390b9c9b79748b2f87dd7ab45674323d58:

  ARM: uniphier: use FIELD_PREP for PLL settings (2017-12-12 00:36:12 +0900)


Dai Okamura (1):
  ARM: uniphier: fix SSCPLL init code for LD11 SoC

Masahiro Yamada (4):
  ARM: uniphier: compile pll-base-ld20.c for PXs3
  mtd: nand: denali: make NAND_DENALI unconfigurable option
  ARM: uniphier: compute SSCPLL values more precisely
  ARM: uniphier: use FIELD_PREP for PLL settings

 arch/arm/mach-uniphier/clk/Makefile|  1 +
 arch/arm/mach-uniphier/clk/pll-base-ld20.c | 15 ++-
 drivers/mtd/nand/Kconfig   |  7 +++
 3 files changed, 14 insertions(+), 9 deletions(-)


-- 
Best Regards
Masahiro Yamada
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] mx6: Add board mx6memcal for use in validating DDR

From: Eric Nelson 

This is a virtual "board" that uses configuration files and
Kconfig to define the memory layout used by a real board during
the board bring-up process.

It generates an SPL image that can be loaded using imx_usb or
SB_LOADER.exe.

When run, it will generate a set of calibration constants for
use in either or both a DCD configuration file for boards that
use u-boot.imx or struct mx6_mmdc_calibration for boards that
boot via SPL.

In essence, it is a configurable, open-source variant of the
Freescale ddr-stress tool.

https://community.nxp.com/docs/DOC-105652

File mx6memcal_defconfig configures the board for use with
mx6sabresd or mx6qsabreauto.

Signed-off-by: Eric Nelson 
Signed-off-by: Fabio Estevam 
---
This is an attempt to bring Eric's useful patch to life:
https://lists.denx.de/pipermail/u-boot/2016-November/271597.html

Changes since RFC:
- Rebased against latest U-Boot
- Removed get_imx_type() as it does not build with SPL (to be added lates).
- Include patch 2/9 into this one: 
https://lists.denx.de/pipermail/u-boot/2016-November/271596.html
,otherwise mmdc_do_dqs_calibration() always fail on my tests with mx6qsabresd
- Fixed some Coding Style issues to make checkpatch happier
 
 arch/arm/mach-imx/mx6/Kconfig |   9 +
 board/freescale/mx6memcal/Kconfig | 235 ++
 board/freescale/mx6memcal/MAINTAINERS |   7 +
 board/freescale/mx6memcal/Makefile|  13 +
 board/freescale/mx6memcal/README  |  49 
 board/freescale/mx6memcal/mx6memcal.c |  32 +++
 board/freescale/mx6memcal/spl.c   | 456 ++
 configs/mx6memcal_defconfig   |  33 +++
 include/configs/mx6memcal.h   |  59 +
 scripts/config_whitelist.txt  |   1 +
 10 files changed, 894 insertions(+)
 create mode 100644 board/freescale/mx6memcal/Kconfig
 create mode 100644 board/freescale/mx6memcal/MAINTAINERS
 create mode 100644 board/freescale/mx6memcal/Makefile
 create mode 100644 board/freescale/mx6memcal/README
 create mode 100644 board/freescale/mx6memcal/mx6memcal.c
 create mode 100644 board/freescale/mx6memcal/spl.c
 create mode 100644 configs/mx6memcal_defconfig
 create mode 100644 include/configs/mx6memcal.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index bee7eab..89bf1ae 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -202,6 +202,14 @@ config TARGET_MX6LOGICPD
select DM_REGULATOR
select OF_CONTROL
 
+config TARGET_MX6MEMCAL
+   bool "mx6memcal"
+   select SUPPORT_SPL
+   help
+ The mx6memcal board is a virtual board that can be used to validate
+ and characterize the memory layout of a new design during the initial
+ development and pre-production stages.
+
 config TARGET_MX6QARM2
bool "mx6qarm2"
 
@@ -441,6 +449,7 @@ source "board/embest/mx6boards/Kconfig"
 source "board/engicam/imx6q/Kconfig"
 source "board/engicam/imx6ul/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
+source "board/freescale/mx6memcal/Kconfig"
 source "board/freescale/mx6sabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"
diff --git a/board/freescale/mx6memcal/Kconfig 
b/board/freescale/mx6memcal/Kconfig
new file mode 100644
index 000..443804d
--- /dev/null
+++ b/board/freescale/mx6memcal/Kconfig
@@ -0,0 +1,235 @@
+if TARGET_MX6MEMCAL
+
+config SYS_BOARD
+   default "mx6memcal"
+
+config SYS_VENDOR
+   default "freescale"
+
+config SYS_CONFIG_NAME
+   default "mx6memcal"
+
+menu "mx6memcal specifics"
+choice
+   prompt "Serial console"
+   help
+ Either UART1 or UART2 will be used as the console for
+ displaying the calibration values or errors.
+
+config SERIAL_CONSOLE_UART1
+   bool "UART1"
+   help
+ Select this if your board uses UART1 for its' console.
+
+config SERIAL_CONSOLE_UART2
+   bool "UART2"
+   help
+ Select this if your board uses UART2 for its' console.
+
+endchoice
+
+choice
+   prompt "UART pads"
+   help
+ Select the RX and TX pads used for your serial console.
+ The choices below reflect the most commonly used options
+ for your UART.
+
+   config UART2_EIM_D26_27
+   bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
+   depends on SERIAL_CONSOLE_UART2
+   help
+ Choose this configuration if you're using pads
+ EIM_D26 and D27 for a console on UART2.
+ This is typical for designs that are based on the
+ NXP SABRELite.
+
+   config UART1_CSI0_DAT10_11
+   bool "UART1 on CSI0_DAT10/11 (Wand)"
+   depends on SERIAL_CONSOLE_UART1
+   help
+ Choose this configuration if you're using pads
+ CSI0_DAT10 and DAT11 for a console on UART1 as
+ is done on the i.MX6 Wand

[U-Boot] [PATCH v6 0/2] DW SPI: Get clock value from Device Tree

As discussed with Marek during the LINUX-PITER here is v4 patch:

Add option to set spi controller clock frequency via device tree
using standard clock bindings.

Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.

Get rid of clock_manager.h include in designware_spi.c as we don't use
cm_get_spi_controller_clk_hz function anymore - we use redefined
dw_spi_get_clk in SOCFPGA clock managers (clock_manager_gen5.c and
clock_manager_arria10.c) instead.

Changes v5->v6:
  * Put the clock handle into the private data

Changes v4->v5:
  * Get rid of usless ifdef in dw_spi_get_clk function

Eugeniy Paltsev (2):
  SOCFPGA: clock manager: implement dw_spi_get_clk function
  DW SPI: Get clock value from Device Tree

 arch/arm/mach-socfpga/clock_manager_arria10.c |  9 +
 arch/arm/mach-socfpga/clock_manager_gen5.c|  9 +
 drivers/spi/designware_spi.c  | 47 +--
 3 files changed, 63 insertions(+), 2 deletions(-)

-- 
2.9.3

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 1/2] SOCFPGA: clock manager: implement dw_spi_get_clk function

Implement dw_spi_get_clk function to override its weak
implementation in designware_spi.c driver.

We need this change to get rid of cm_get_spi_controller_clk_hz
function and clock_manager.h include in designware_spi.c driver.

Signed-off-by: Eugeniy Paltsev 
---
 arch/arm/mach-socfpga/clock_manager_arria10.c | 9 +
 arch/arm/mach-socfpga/clock_manager_gen5.c| 9 +
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 482b854..623a266 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -1076,6 +1077,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
return  cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
 }
 
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+   *rate = cm_get_spi_controller_clk_hz();
+
+   return 0;
+}
+
 void cm_print_clock_quick_summary(void)
 {
printf("MPU   %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c 
b/arch/arm/mach-socfpga/clock_manager_gen5.c
index 31fd510..a371d83 100644
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -509,6 +510,14 @@ unsigned int cm_get_spi_controller_clk_hz(void)
return clock;
 }
 
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+   *rate = cm_get_spi_controller_clk_hz();
+
+   return 0;
+}
+
 void cm_print_clock_quick_summary(void)
 {
printf("MPU   %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
-- 
2.9.3

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 2/2] DW SPI: Get clock value from Device Tree

Add option to set spi controller clock frequency via device tree
using standard clock bindings.

Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.

Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)

Signed-off-by: Eugeniy Paltsev 
---
 drivers/spi/designware_spi.c | 43 +--
 1 file changed, 41 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 5aa507b..a037376 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -11,6 +11,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -18,7 +19,6 @@
 #include 
 #include 
 #include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -94,6 +94,8 @@ struct dw_spi_priv {
void __iomem *regs;
unsigned int freq;  /* Default frequency */
unsigned int mode;
+   struct clk clk;
+   unsigned long bus_clk_rate;
 
int bits_per_word;
u8 cs;  /* chip select pin */
@@ -176,14 +178,51 @@ static void spi_hw_init(struct dw_spi_priv *priv)
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
 }
 
+/*
+ * We define dw_spi_get_clk function as 'weak' as some targets
+ * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
+ * and implement dw_spi_get_clk their own way in their clock manager.
+ */
+__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+   struct dw_spi_priv *priv = dev_get_priv(bus);
+   int ret;
+
+   ret = clk_get_by_index(bus, 0, &priv->clk);
+   if (ret)
+   return -EINVAL;
+
+   ret = clk_enable(&priv->clk);
+   if (ret && ret != -ENOSYS && ret != -ENOSYS && ret != -ENOTSUPP)
+   return ret;
+
+   *rate = clk_get_rate(&priv->clk);
+   if (!*rate) {
+   clk_disable(&priv->clk);
+   return -EINVAL;
+   }
+
+   debug("%s: get spi controller clk via device tree: %lu Hz\n",
+ __func__, *rate);
+
+   clk_free(&priv->clk);
+
+   return 0;
+}
+
 static int dw_spi_probe(struct udevice *bus)
 {
struct dw_spi_platdata *plat = dev_get_platdata(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
+   int ret;
 
priv->regs = plat->regs;
priv->freq = plat->frequency;
 
+   ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
+   if (ret)
+   return ret;
+
/* Currently only bits_per_word == 8 supported */
priv->bits_per_word = 8;
 
@@ -369,7 +408,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
spi_enable_chip(priv, 0);
 
/* clk_div doesn't support odd number */
-   clk_div = cm_get_spi_controller_clk_hz() / speed;
+   clk_div = priv->bus_clk_rate / speed;
clk_div = (clk_div + 1) & 0xfffe;
dw_writel(priv, DW_SPI_BAUDR, clk_div);
 
-- 
2.9.3

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v6 2/2] DW SPI: Get clock value from Device Tree

On 12/11/2017 05:18 PM, Eugeniy Paltsev wrote:
> Add option to set spi controller clock frequency via device tree
> using standard clock bindings.
> 
> Define dw_spi_get_clk function as 'weak' as some targets
> (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
> and implement dw_spi_get_clk their own way in their clock manager.
> 
> Get rid of clock_manager.h include as we don't use
> cm_get_spi_controller_clk_hz function anymore. (we use redefined
> dw_spi_get_clk in SOCFPGA clock managers instead)
> 
> Signed-off-by: Eugeniy Paltsev 
> ---
>  drivers/spi/designware_spi.c | 43 +--
>  1 file changed, 41 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> index 5aa507b..a037376 100644
> --- a/drivers/spi/designware_spi.c
> +++ b/drivers/spi/designware_spi.c
> @@ -11,6 +11,7 @@
>   */
>  
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -18,7 +19,6 @@
>  #include 
>  #include 
>  #include 
> -#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -94,6 +94,8 @@ struct dw_spi_priv {
>   void __iomem *regs;
>   unsigned int freq;  /* Default frequency */
>   unsigned int mode;
> + struct clk clk;
> + unsigned long bus_clk_rate;
>  
>   int bits_per_word;
>   u8 cs;  /* chip select pin */
> @@ -176,14 +178,51 @@ static void spi_hw_init(struct dw_spi_priv *priv)
>   debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
>  }
>  
> +/*
> + * We define dw_spi_get_clk function as 'weak' as some targets
> + * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
> + * and implement dw_spi_get_clk their own way in their clock manager.
> + */
> +__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
> +{
> + struct dw_spi_priv *priv = dev_get_priv(bus);
> + int ret;
> +
> + ret = clk_get_by_index(bus, 0, &priv->clk);
> + if (ret)
> + return -EINVAL;

if (ret)
 return ret;

> + ret = clk_enable(&priv->clk);
> + if (ret && ret != -ENOSYS && ret != -ENOSYS && ret != -ENOTSUPP)

You have ENOSYS twice in there, but you can do just if (ret) return ret
again.

> + return ret;
> +
> + *rate = clk_get_rate(&priv->clk);
> + if (!*rate) {
> + clk_disable(&priv->clk);

You didn't do clk_free() here, just implement a failpath (ie. goto
err_rate).

> + return -EINVAL;
> + }
> +
> + debug("%s: get spi controller clk via device tree: %lu Hz\n",
> +   __func__, *rate);
> +
> + clk_free(&priv->clk);

If anyone accesses priv->clk outside of this function, the code will
crash, so remove this.

> + return 0;

err_rate:
 clk_free() ...

> +}
> +
>  static int dw_spi_probe(struct udevice *bus)
>  {
>   struct dw_spi_platdata *plat = dev_get_platdata(bus);
>   struct dw_spi_priv *priv = dev_get_priv(bus);
> + int ret;
>  
>   priv->regs = plat->regs;
>   priv->freq = plat->frequency;
>  
> + ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
> + if (ret)
> + return ret;
> +
>   /* Currently only bits_per_word == 8 supported */
>   priv->bits_per_word = 8;
>  
> @@ -369,7 +408,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint 
> speed)
>   spi_enable_chip(priv, 0);
>  
>   /* clk_div doesn't support odd number */
> - clk_div = cm_get_spi_controller_clk_hz() / speed;
> + clk_div = priv->bus_clk_rate / speed;
>   clk_div = (clk_div + 1) & 0xfffe;
>   dw_writel(priv, DW_SPI_BAUDR, clk_div);
>  
> 


-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] Linux hang

2017-12-11 Thread Jan Siegmund

Am 08.12.2017 um 14:52 schrieb Anatolij Gustschin:

Hi,

On Wed, 6 Dec 2017 17:02:07 +
Siegmund, Jan jan.siegmu...@hm.edu wrote:

Hi all,
does anybody have an idea for the following problem.

* FPGA is programmed using an overlay
* FPGA writes to SDRAM via the FPGA2SDRAM-bridge
* Linux hangs and the watchdog resets the board (the FPGA stays programmed)
* After the reset and boot the FPGA is reprogrammed using the same overlay
* Now, the FPGA can write to the SDRAM without a problem

Probably because configuration of the FPGA2SDRAM-bridge is different than
other bridges. There is an important step needed, setting APPLYCFG bit in
the STATICCFG register [1]. But this must be done when the DDR interface
is idle (no DRAM transfer from ARM-core or DMA) which is not the case when
Linux is running. Therefore, if you have designs that use fpga2sdram, you
have to program the FPGA under U-Boot. U-Boot fpga command runs APPLYCFG
setting code from OCRAM.

Thanks, this has helped me a lot. But there was still something
missing. First, the FPGA needs to be programmed in U-Boot using the
'fpga' command. Then 'bridge enable' has to be called. This command
does not only get the lwHPS2FPGA, HPS2FPGA and FPGA2HPS bridges out of
reset, but also applies the SDRAM config, like you described.

Now, my SDRAM-to-FPGA interface works fine.

Regards,
Jan

Anatolij

[1]
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v6 2/2] DW SPI: Get clock value from Device Tree

On Mon, 2017-12-11 at 17:21 +0100, Marek Vasut wrote:
> On 12/11/2017 05:18 PM, Eugeniy Paltsev wrote:
> > Add option to set spi controller clock frequency via device tree
> > using standard clock bindings.
> > 
> > Define dw_spi_get_clk function as 'weak' as some targets
> > (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
> > and implement dw_spi_get_clk their own way in their clock manager.
> > 
> > Get rid of clock_manager.h include as we don't use
> > cm_get_spi_controller_clk_hz function anymore. (we use redefined
> > dw_spi_get_clk in SOCFPGA clock managers instead)
> > 
> > Signed-off-by: Eugeniy Paltsev 
> > ---
> >  drivers/spi/designware_spi.c | 43 
> > +--
> >  1 file changed, 41 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> > index 5aa507b..a037376 100644
> > --- a/drivers/spi/designware_spi.c
> > +++ b/drivers/spi/designware_spi.c
> > @@ -11,6 +11,7 @@
> >   */
> >  
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -18,7 +19,6 @@
> >  #include 
> >  #include 
> >  #include 
> > -#include 
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > @@ -94,6 +94,8 @@ struct dw_spi_priv {
> >     void __iomem *regs;
> >     unsigned int freq;  /* Default frequency */
> >     unsigned int mode;
> > +   struct clk clk;
> > +   unsigned long bus_clk_rate;
> >  
> >     int bits_per_word;
> >     u8 cs;  /* chip select pin */
> > @@ -176,14 +178,51 @@ static void spi_hw_init(struct dw_spi_priv *priv)
> >     debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
> >  }
> >  
> > +/*
> > + * We define dw_spi_get_clk function as 'weak' as some targets
> > + * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
> > + * and implement dw_spi_get_clk their own way in their clock manager.
> > + */
> > +__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
> > +{
> > +   struct dw_spi_priv *priv = dev_get_priv(bus);
> > +   int ret;
> > +
> > +   ret = clk_get_by_index(bus, 0, &priv->clk);
> > +   if (ret)
> > +   return -EINVAL;
> 
> if (ret)
>  return ret;
Ok.

> 
> > +   ret = clk_enable(&priv->clk);
> > +   if (ret && ret != -ENOSYS && ret != -ENOSYS && ret != -ENOTSUPP)
> 
> You have ENOSYS twice in there, but you can do just if (ret) return ret
> again.

The idea is to skip error if error code is -ENOSYS or -ENOTSUPP
as it is OK situation: some clock drivers don't implement .enable/.disable
callbacks so clk_enable returns -ENOSYS.
Also some clock drivers implement .enable/.disable callbacks not for all
clock IDs and return -ENOSYS or -ENOTSUPP for others.

But definitely I should remove second ENOSYS here.

> > +   return ret;
> > +
> > +   *rate = clk_get_rate(&priv->clk);
> > +   if (!*rate) {
> > +   clk_disable(&priv->clk);
> 
> You didn't do clk_free() here, just implement a failpath (ie. goto
> err_rate).
> 
> > +   return -EINVAL;
> > +   }
> > +
> > +   debug("%s: get spi controller clk via device tree: %lu Hz\n",
> > +     __func__, *rate);
> > +
> > +   clk_free(&priv->clk);
> 
> If anyone accesses priv->clk outside of this function, the code will
> crash, so remove this.
> 
> > +   return 0;
> 
> err_rate:
>  clk_free() ...

Sure, thanks.

> 
> > +}
> > +
> >  static int dw_spi_probe(struct udevice *bus)
> >  {
> >     struct dw_spi_platdata *plat = dev_get_platdata(bus);
> >     struct dw_spi_priv *priv = dev_get_priv(bus);
> > +   int ret;
> >  
> >     priv->regs = plat->regs;
> >     priv->freq = plat->frequency;
> >  
> > +   ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
> > +   if (ret)
> > +   return ret;
> > +
> >     /* Currently only bits_per_word == 8 supported */
> >     priv->bits_per_word = 8;
> >  
> > @@ -369,7 +408,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint 
> > speed)
> >     spi_enable_chip(priv, 0);
> >  
> >     /* clk_div doesn't support odd number */
> > -   clk_div = cm_get_spi_controller_clk_hz() / speed;
> > +   clk_div = priv->bus_clk_rate / speed;
> >     clk_div = (clk_div + 1) & 0xfffe;
> >     dw_writel(priv, DW_SPI_BAUDR, clk_div);
> >  
> > 
> 
> 
-- 
 Eugeniy Paltsev
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v6 2/2] DW SPI: Get clock value from Device Tree

On 12/11/2017 05:37 PM, Eugeniy Paltsev wrote:
> On Mon, 2017-12-11 at 17:21 +0100, Marek Vasut wrote:
>> On 12/11/2017 05:18 PM, Eugeniy Paltsev wrote:
>>> Add option to set spi controller clock frequency via device tree
>>> using standard clock bindings.
>>>
>>> Define dw_spi_get_clk function as 'weak' as some targets
>>> (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
>>> and implement dw_spi_get_clk their own way in their clock manager.
>>>
>>> Get rid of clock_manager.h include as we don't use
>>> cm_get_spi_controller_clk_hz function anymore. (we use redefined
>>> dw_spi_get_clk in SOCFPGA clock managers instead)
>>>
>>> Signed-off-by: Eugeniy Paltsev 
>>> ---
>>>  drivers/spi/designware_spi.c | 43 
>>> +--
>>>  1 file changed, 41 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
>>> index 5aa507b..a037376 100644
>>> --- a/drivers/spi/designware_spi.c
>>> +++ b/drivers/spi/designware_spi.c
>>> @@ -11,6 +11,7 @@
>>>   */
>>>  
>>>  #include 
>>> +#include 
>>>  #include 
>>>  #include 
>>>  #include 
>>> @@ -18,7 +19,6 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> -#include 
>>>  
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>  
>>> @@ -94,6 +94,8 @@ struct dw_spi_priv {
>>>     void __iomem *regs;
>>>     unsigned int freq;  /* Default frequency */
>>>     unsigned int mode;
>>> +   struct clk clk;
>>> +   unsigned long bus_clk_rate;
>>>  
>>>     int bits_per_word;
>>>     u8 cs;  /* chip select pin */
>>> @@ -176,14 +178,51 @@ static void spi_hw_init(struct dw_spi_priv *priv)
>>>     debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
>>>  }
>>>  
>>> +/*
>>> + * We define dw_spi_get_clk function as 'weak' as some targets
>>> + * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
>>> + * and implement dw_spi_get_clk their own way in their clock manager.
>>> + */
>>> +__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
>>> +{
>>> +   struct dw_spi_priv *priv = dev_get_priv(bus);
>>> +   int ret;
>>> +
>>> +   ret = clk_get_by_index(bus, 0, &priv->clk);
>>> +   if (ret)
>>> +   return -EINVAL;
>>
>> if (ret)
>>  return ret;
> Ok.
> 
>>
>>> +   ret = clk_enable(&priv->clk);
>>> +   if (ret && ret != -ENOSYS && ret != -ENOSYS && ret != -ENOTSUPP)
>>
>> You have ENOSYS twice in there, but you can do just if (ret) return ret
>> again.
> 
> The idea is to skip error if error code is -ENOSYS or -ENOTSUPP
> as it is OK situation: some clock drivers don't implement .enable/.disable
> callbacks so clk_enable returns -ENOSYS.
> Also some clock drivers implement .enable/.disable callbacks not for all
> clock IDs and return -ENOSYS or -ENOTSUPP for others.
> 
> But definitely I should remove second ENOSYS here.
+CC Simon, that's somewhat iffy ...

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v4 2/4] net: designware: Pad small packets

2017-12-11 Thread Joe Hershberger

On Sat, Dec 9, 2017 at 4:59 PM, Florian Fainelli  wrote:
> Make sure that we pad small packets to a minimum length of 60 bytes
> (without FCS). This is necessary to interface with Ethernet switches
> that will reject RUNT frames unless padded correctly.
>
> Signed-off-by: Florian Fainelli 

Acked-by: Joe Hershberger 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] u-boot-dm crashes early on NVIDIA Beaver, Jetson TK1

2017-12-11 Thread Stephen Warren

Simon, the latest commits in u-boot-dm/git master branch (2b64d049a061 
"power: pmic/regulator: Add basic support for TPS65910") crash on at 
least Beaver and Jetson TK1. On TK1, I added debug spew to 
lib/initcall.c, and the last function called before the crash is 
initr_serial():



U-Boot SPL 2018.01-rc1-00620-g2b64d049a061-dirty (Dec 11 2017 - 09:50:35)
Trying to boot from RAM
initcall: 801602c4


U-Boot 2018.01-rc1-00620-g2b64d049a061-dirty (Dec 11 2017 - 09:50:35 -0700)

initcall: 80123814
U-Boot code: 8011 -> 8017F6E8  BSS: -> 801C3B0C
initcall: 80113030
TEGRA124
initcall: 80123dc0
Model: NVIDIA Jetson TK1
Board: NVIDIA Jetson TK1
initcall: 8012394c
DRAM:  initcall: 80111c78
initcall: 80123ab4
Monitor len: 000B3B0C
Ram size: 8000
Ram top: 
initcall: 80123664
initcall: 80123684
TLB table from  to 4000
initcall: 8012367c
initcall: 801239bc
initcall: 801237c8
Reserving 718k for U-Boot at: fff3c000
initcall: 80123798
Reserving 37896k for malloc() at: fda3a000
initcall: 801238f8
Reserving 88 Bytes for Board Info at: fda39fa8
initcall: 801239c4
initcall: 80123764
Reserving 208 Bytes for Global Data at: fda39ed8
initcall: 801236f8
Reserving 30560 Bytes for FDT at: fda32778
initcall: 801239cc
initcall: 801239e4
initcall: 80123b20
initcall: 80111e0c
initcall: 801239f8

RAM Configuration:
Bank #0: 8000 2 GiB
Bank #1: 0 0 Bytes

DRAM:  2 GiB
initcall: 801236dc
New Stack Pointer is: fda32750
initcall: 801238b4
initcall: 801239d4
initcall: 80123844
Relocation Offset is: 7fe2c000
Relocating to fff3c000, new gd at fda39ed8, sp at fda32750
initcall: fff4fb64
initcall: fff4fb6c
initcall: 80123d54 (relocated to fff4fd54)
initcall: 80123d1c (relocated to fff4fd1c)
initcall: 80123d74 (relocated to fff4fd74)
initcall: 80123ce0 (relocated to fff4fce0)
Pre-reloc malloc() used 0x130 bytes (0 KB)
initcall: 80123634 (relocated to fff4f634)
initcall: 80123ccc (relocated to fff4fccc)
initcall: 80123d7c (relocated to fff4fd7c)
initcall: 80123cbc (relocated to fff4fcbc)
initcall: 80123d64 (relocated to fff4fd64)
initcall: 80123cb0 (relocated to fff4fcb0)
initcall: 80123c9c (relocated to fff4fc9c)
initcall: 80111d80 (relocated to fff3dd80)
initcall: 8015670c (relocated to fff8270c)
initcall: 8012c7f0 (relocated to fff587f0)
initcall: 80123c8c (relocated to fff4fc8c)

U-Boot SPL 2016.09-00263-gf50db3a323b1 (Sep 23 2016 - 16:34:07)



80123c70 l F .text  001c initr_announce
80123c8c l F .text  0010 initr_serial
80123c9c l F .text  0014 initr_dm

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] rockchip: move CONFIG_ENV_SIZE and CONFIG_ENV_OFFSET to Kconfig

2017-12-11 Thread Klaus Goger

These settings are not not user visible via a menuconfig prompt. This is
necessary to have the possibility to select new default values if
CONFIG_IS_IN_* is changed (interactively or with oldconfig). Otherwise it
will always be set to a previous value if used with a prompt.
As an example if we do a defconfig with CONFIG_IS_IN_MMC and change it to
CONFIG_IS_IN_SPI_FLASH via menuconfig, ENV_SIZE and ENV_OFFSET will not
be changed to the correct values as defconfig will already have set them
to the default values of CONFIG_IS_IN_MMC in .config.

Signed-off-by: Klaus Goger 

---

 board/theobroma-systems/puma_rk3399/Kconfig |  6 ++
 env/Kconfig | 19 +++
 include/configs/puma_rk3399.h   |  8 
 include/configs/rockchip-common.h   |  6 --
 4 files changed, 25 insertions(+), 14 deletions(-)

diff --git a/board/theobroma-systems/puma_rk3399/Kconfig 
b/board/theobroma-systems/puma_rk3399/Kconfig
index a645590d78..80b3460d4c 100644
--- a/board/theobroma-systems/puma_rk3399/Kconfig
+++ b/board/theobroma-systems/puma_rk3399/Kconfig
@@ -12,4 +12,10 @@ config SYS_CONFIG_NAME
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
 
+config ENV_SIZE
+   default 0x2000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+   default 0x3c000 if ENV_IS_IN_SPI_FLASH
+
 endif
diff --git a/env/Kconfig b/env/Kconfig
index 2477bf8530..12c6d80785 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -427,4 +427,23 @@ config ENV_UBI_VOLUME
 
 endif
 
+if ARCH_ROCKCHIP
+
+config ENV_OFFSET
+   hex
+   depends on !ENV_IS_IN_UBI
+   depends on !ENV_IS_NOWHERE
+   default 0x3f8000
+   help
+ Offset from the start of the device (or partition)
+
+config ENV_SIZE
+   hex
+   depends on !ENV_IS_NOWHERE
+   default 0x8000
+   help
+ Size of the environment storage area
+
+endif
+
 endmenu
diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h
index 39d0786266..6523a7c34a 100644
--- a/include/configs/puma_rk3399.h
+++ b/include/configs/puma_rk3399.h
@@ -9,14 +9,6 @@
 
 #include 
 
-/*
- * SPL @ 32kB for ~130kB
- * ENV @ 240KB for 8kB
- * FIT payload (ATF, U-Boot, FDT) @ 256kB
- */
-#undef CONFIG_ENV_OFFSET
-#define CONFIG_ENV_OFFSET (240 * 1024)
-
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_SYS_MMC_ENV_DEV 1
 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
diff --git a/include/configs/rockchip-common.h 
b/include/configs/rockchip-common.h
index 35d948ae29..9da6dcaf72 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -61,12 +61,6 @@
 
 #endif
 
-/*
- * Rockchip SoCs use fixed ENV 32KB@(4MB-32KB)
- */
-#define CONFIG_ENV_OFFSET  (SZ_4M - SZ_32K)
-#define CONFIG_ENV_SIZESZ_32K
-
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
 #endif /* _ROCKCHIP_COMMON_H_ */
-- 
2.11.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] u-boot-dm crashes early on NVIDIA Beaver, Jetson TK1

2017-12-11 Thread Stephen Warren


On 12/11/2017 09:55 AM, Stephen Warren wrote:
Simon, the latest commits in u-boot-dm/git master branch (2b64d049a061 
"power: pmic/regulator: Add basic support for TPS65910") crash on at 
least Beaver and Jetson TK1. On TK1, I added debug spew to 
lib/initcall.c, and the last function called before the crash is 
initr_serial():


Bisect shows this is due to the commit below. If I revert this, U-Boot 
works correctly again:



0c98340717f69a66acd4156392b6a45cc51042b3 is the first bad commit
commit 0c98340717f69a66acd4156392b6a45cc51042b3
Author: Mario Six 
Date:   Fri Nov 24 07:51:40 2017 +0100

drivers: core: Add translation in live tree case

The function dev_read_addr calls ofnode_get_addr_index in the live tree

case, which does not apply bus translations to the address read from the
device tree. This results in illegal addresses on boards that rely on
bus translations being applied.

Fix this situation by applying bus translations in the live tree case as

well.

Signed-off-by: Mario Six 

Reviewed-by: Simon Glass 

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] arm: imx: add tzic interrupt controller for imx53

2017-12-11 Thread linux-kernel-dev

From: Patrick Bruenn 

Since commit 999a78d5cf00 ("scripts/dtc: Update to upstream version 
v1.4.5-3-gb1a60033c110")
dtc warns about:
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
interrupt-parent for /soc/aips@5000/serial@53fc
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
interrupt-parent for /soc/aips@5000/ccm@53fd4000
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
interrupt-parent for /soc/aips@5000/gpio@53fe4000
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
interrupt-parent for /soc/aips@6000/sdma@63fb
arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
interrupt-parent for /soc/aips@6000/ethernet@63fec000

Fix this by adding a node for the tzic interrupt controller.
Copied from "/arch/arm/boot/dts/imx53.dts"

Signed-off-by: Patrick Bruenn 
---

 arch/arm/dts/imx53.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index 1bdf0668a5..f68e88585e 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -23,10 +23,18 @@
serial1 = &uart2;
};
 
+   tzic: tz-interrupt-controller@fffc000 {
+   compatible = "fsl,imx53-tzic", "fsl,tzic";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   reg = <0x0fffc000 0x4000>;
+   };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
+   interrupt-parent = <&tzic>;
ranges;
 
aips@5000 { /* AIPS1 */
-- 
2.11.0


___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v5] arm64: ls1012ardb: Add distro boot support

2017-12-11 Thread York Sun

On 11/30/2017 03:14 AM, Rajesh Bhagat wrote:

> --- a/include/configs/ls1012ardb.h
> +++ b/include/configs/ls1012ardb.h
> @@ -60,6 +60,49 @@
>  #define CONFIG_SYS_MEMTEST_START 0x8000
>  #define CONFIG_SYS_MEMTEST_END   0x9fff
>  
> +#undef CONFIG_EXTRA_ENV_SETTINGS
> +#define CONFIG_EXTRA_ENV_SETTINGS\

With this patch and the similar one for ls1012afrdm, does it make sense
to keep a default CONFIG_EXTRA_ENV_SETTINGS in the common file? The only
board left is QDS.

York
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] efi_loader: helloworld.c: Explicitly use .rodata for loaded_image_guid

2017-12-11 Thread Florian Fainelli



On 12/11/2017 12:45 AM, Alexander Graf wrote:
> Commit bbf75dd9345d0b ("efi_loader: output load options in helloworld")
> introduced a const variable in efi_main() called loaded_image_guid which
> got populated from a constant struct.
> 
> While you would usually expect a compiler to realize that this variable
> should really just be a global pointer to .rodata, gcc disagrees and instead
> puts it on the stack. Unfortunately in some implementations of gcc it does
> so my calling memcpy() which we do not implement in our hello world
> environment.
> 
> So let's explicitly move it to a global variable which in turn puts it in
> .rodata reliably and gets rid of the memcpy().
> 
> Fixes: bbf75dd9345d0b ("efi_loader: output load options in helloworld")
> Reported-by: Florian Fainelli 
> Signed-off-by: Alexander Graf 

Tested-by: Florian Fainelli 

Thanks Alexander!

> ---
>  lib/efi_loader/helloworld.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c
> index e59c24c788..b8c147d7f2 100644
> --- a/lib/efi_loader/helloworld.c
> +++ b/lib/efi_loader/helloworld.c
> @@ -13,6 +13,8 @@
>  #include 
>  #include 
>  
> +static const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID;
> +
>  /*
>   * Entry point of the EFI application.
>   *
> @@ -26,7 +28,6 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle,
>   struct efi_simple_text_output_protocol *con_out = systable->con_out;
>   struct efi_boot_services *boottime = systable->boottime;
>   struct efi_loaded_image *loaded_image;
> - const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID;
>   efi_status_t ret;
>  
>   con_out->output_string(con_out, L"Hello, world!\n");
> 

-- 
Florian
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 1/1] efi_loader: use wide string do define firmware vendor

As the U-Boot is compiled with -fshort-wchar we can define
the firmware vendor constant as wide string.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_boottime.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 94b7205a5e..eae141815b 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -2597,8 +2597,7 @@ static const struct efi_boot_services efi_boot_services = 
{
 };
 
 
-static uint16_t __efi_runtime_data firmware_vendor[] =
-   { 'D','a','s',' ','U','-','b','o','o','t',0 };
+static uint16_t __efi_runtime_data firmware_vendor[] = L"Das U-Boot";
 
 struct efi_system_table __efi_runtime_data systab = {
.hdr = {
-- 
2.15.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [U-Boot,1/1] mx6: wandboard: reenable SPL build

2017-12-11 Thread Vagrant Cascadian

On 2017-12-09, Heinrich Schuchardt wrote:
> The last merge from the u-boot-imx tree deleted a
> necessary line from wandboard_defconfig by mistake.
>
> This caused an error when running
>
>   make wandboard_defconfig
>   make SPL
>
> Fixes: 6e6cf015e7cd Merge git://www.denx.de/git/u-boot-imx
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Fabio Estevam 

This is essentially identical to the patch I submitted a couple days
ago, so:

Tested-By: Vagrant Cascadian 

live well,
  vagrant

> ---
>  configs/wandboard_defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
> index 4b6b9d9aaee..0e1f1f4a376 100644
> --- a/configs/wandboard_defconfig
> +++ b/configs/wandboard_defconfig
> @@ -11,6 +11,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
>  CONFIG_CMD_HDMIDETECT=y
>  CONFIG_DISTRO_DEFAULTS=y
>  CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
>  # CONFIG_CONSOLE_MUX is not set
>  CONFIG_SYS_CONSOLE_IS_IN_ENV=y
>  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] imx: Fix missing spl_sd configuration for wandboard.

Hi Vagrant,

On Wed, Dec 6, 2017 at 10:31 PM, Vagrant Cascadian  wrote:
> In commit 6e6cf015e7cdd7ca83a933320a81201972bd5e5e ("Merge
> git://www.denx.de/git/u-boot-imx") the line defining spl_sd
> configuration for wandboard was removed, which resulted in no SPL
> target being built.
>
> Add it back.
>
> Signed-off-by: Vagrant Cascadian 

Sorry, I missed this one.

Reviewed-by: Fabio Estevam 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] arm: imx: add tzic interrupt controller for imx53

On Mon, Dec 11, 2017 at 10:09 AM,   wrote:
> From: Patrick Bruenn 
>
> Since commit 999a78d5cf00 ("scripts/dtc: Update to upstream version 
> v1.4.5-3-gb1a60033c110")
> dtc warns about:
> arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
> interrupt-parent for /soc/aips@5000/serial@53fc
> arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
> interrupt-parent for /soc/aips@5000/ccm@53fd4000
> arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
> interrupt-parent for /soc/aips@5000/gpio@53fe4000
> arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
> interrupt-parent for /soc/aips@6000/sdma@63fb
> arch/arm/dts/imx53-cx9020.dtb: Warning (interrupts_property): Missing 
> interrupt-parent for /soc/aips@6000/ethernet@63fec000
>
> Fix this by adding a node for the tzic interrupt controller.
> Copied from "/arch/arm/boot/dts/imx53.dts"
>
> Signed-off-by: Patrick Bruenn 

Reviewed-by: Fabio Estevam 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] efi_loader: Setup logical_partition media information

2017-12-11 Thread Emmanuel Vadot

When adding a partition, set the logical_partition member in the media
structure as mandated by the UEFI spec.

Signed-off-by: Emmanuel Vadot 
---
 lib/efi_loader/efi_disk.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 4e457a841b..d299fc8dea 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -258,6 +258,8 @@ static void efi_disk_add_dev(const char *name,
diskobj->media.block_size = desc->blksz;
diskobj->media.io_align = desc->blksz;
diskobj->media.last_block = desc->lba - offset;
+   if (part != 0)
+   diskobj->media.logical_partition = 1;
diskobj->ops.media = &diskobj->media;
return;
 out_of_memory:
-- 
2.15.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 2/2] Move SYS_DPAA_QBMAN to Kconfig

2017-12-11 Thread Ahmed Mansour

The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to
add device tree fixups that allow deep sleep in Linux. The define was
placed in header files included by a number of boards, but was not
explicitly documented in any of the Kconfigs. A description was added
to the drivers/networking menuconfig and default selection for
current SOCs that have this part

Signed-off-by: Ahmed Mansour 

---

Changes in v3: None
Changes in v2: None

 drivers/net/Kconfig  | 22 ++
 include/configs/B4860QDS.h   |  1 -
 include/configs/P1023RDB.h   |  1 -
 include/configs/P2041RDB.h   |  1 -
 include/configs/T102xQDS.h   |  1 -
 include/configs/T102xRDB.h   |  1 -
 include/configs/T1040QDS.h   |  1 -
 include/configs/T104xRDB.h   |  1 -
 include/configs/T208xQDS.h   |  1 -
 include/configs/T208xRDB.h   |  1 -
 include/configs/T4240QDS.h   |  1 -
 include/configs/T4240RDB.h   |  1 -
 include/configs/corenet_ds.h |  1 -
 include/configs/cyrus.h  |  1 -
 include/configs/ls1043a_common.h |  2 --
 include/configs/ls1046a_common.h |  4 
 16 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 52555da..db4c176 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -365,4 +365,26 @@ config FEC2_PHY_NORXERR
  The PHY does not have a RXERR line (RMII only).
  (so program the FEC to ignore it).
 
+config SYS_DPAA_QBMAN
+   bool "Device tree fixup for QBMan on freescale SOCs"
+   depends on (ARM || PPC) && !SPL_BUILD
+   default y if ARCH_B4860 || \
+ARCH_P1023 || \
+ARCH_P2041 || \
+ARCH_T1023 || \
+ARCH_T1024 || \
+ARCH_T1040 || \
+ARCH_T1042 || \
+ARCH_T2080 || \
+ARCH_T2081 || \
+ARCH_T4240 || \
+ARCH_P4080 || \
+ARCH_P3041 || \
+ARCH_P5040 || \
+ARCH_P5020 || \
+ARCH_LS1043A || \
+ARCH_LS1046A
+   help
+ QBman fixups to allow deep sleep in DPAA 1 SOCs
+
 endif # NETDEVICES
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 661bc8b..7f9482d 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -572,7 +572,6 @@ unsigned long get_board_ddr_clk(void);
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN  /* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS25
 #define CONFIG_SYS_BMAN_MEM_BASE   0xf400
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 1b78a4f..56e3f48 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -272,7 +272,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_LOADADDR100
 
 /* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN  /* support Q/Bman */
 #define CONFIG_SYS_QMAN_MEM_BASE   0xff00
 #define CONFIG_SYS_QMAN_MEM_PHYS   CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_MEM_SIZE   0x0020
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 6008237..5f7ebe7 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -438,7 +438,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE3_IO_SIZE   0x0001  /* 64k */
 
 /* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN  /* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS10
 #define CONFIG_SYS_BMAN_MEM_BASE   0xf400
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 259e8a0..13f4c92 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -644,7 +644,6 @@ unsigned long get_board_ddr_clk(void);
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN  /* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS10
 #define CONFIG_SYS_BMAN_MEM_BASE   0xf400
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 7dee2f0..e1f2196 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -649,7 +649,6 @@ unsigned long get_board_ddr_clk(void);
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN  /* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS10
 #define CONFIG_SYS_BMAN_MEM_BASE   0xf400
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index c694e50..c186d15 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -535,7 +535,6 @@ unsigned long get_board_ddr_clk(void);
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN  /* Support Q/Bman */
 #define C

[U-Boot] [PATCH v3 1/2] drivers/misc: Share qbman init between archs

2017-12-11 Thread Ahmed Mansour

This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware

- Create new board/freescale/common/fsl_portals.c to house shared
  device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
  both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
  setup to disable interrupts on all QMan and BMan portals. It is
  needed because the interrupts are enabled by default for all portals
  including unused/uninitialised portals. When the kernel attempts to
  go to deep sleep the unused portals prevent it from doing so

Signed-off-by: Ahmed Mansour 

---

Changes in v3:
- Add freescale old copyright in new file since it is a modified copy
- Add ifdef QBMAN guard around get_qman_freq()
- Return freq_qman instead of freq_systembus. More readable and robust
- Add white space before return line in get_qman_freq()

Changes in v2:
- Add get_qman_freq() to replace get_sys_info() for readability
- Correct the copyright year in new files
- Replace !ARM with PPC to wall off PowerPC SOCs specific qman setup
- Rename portals.c -> fsl_portals.c for clarity

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|   4 +
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c|   9 +
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |  14 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  29 ++
 arch/arm/include/asm/arch-fsl-layerscape/speed.h   |   3 +
 arch/powerpc/cpu/mpc85xx/cpu_init.c|   3 +-
 arch/powerpc/cpu/mpc85xx/fdt.c |   1 +
 arch/powerpc/cpu/mpc85xx/portals.c | 281 ---
 arch/powerpc/include/asm/fsl_liodn.h   |   7 +-
 arch/powerpc/include/asm/fsl_portals.h |   4 -
 arch/powerpc/include/asm/immap_85xx.h  |  60 
 drivers/misc/Makefile  |   1 +
 drivers/misc/fsl_portals.c | 305 +
 include/configs/ls1043a_common.h   |   2 +
 include/fsl_qbman.h|  75 +
 15 files changed, 450 insertions(+), 348 deletions(-)
 create mode 100644 drivers/misc/fsl_portals.c
 create mode 100644 include/fsl_qbman.h

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d082629..3fd352f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -30,6 +30,7 @@
 #endif
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -565,6 +566,9 @@ int arch_early_init_r(void)
 #ifdef CONFIG_FMAN_ENET
fman_enet_init();
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+   setup_qbman_portals();
+#endif
return 0;
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index cae59da..382bf3d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -26,6 +26,8 @@
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include 
 #endif
+#include 
+#include 
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -415,6 +417,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_esdhc(blob, bd);
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+   fdt_fixup_bportals(blob);
+   fdt_fixup_qportals(blob);
+   do_fixup_by_compat_u32(blob, "fsl,qman",
+  "clock-frequency", get_qman_freq(), 1);
+#endif
+
 #ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 2d7775e..5f23aad 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -155,8 +155,22 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_localbus = sys_info->freq_systembus /
CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+   sys_info->freq_qman = sys_info->freq_systembus;
+#endif
 }
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void)
+{
+   struct sys_info sys_info;
+
+   get_sys_info(&sys_info);
+
+   return sys_info.freq_qman;
+}
+#endif
+
 int get_clocks(void)
 {
struct sys_info sys_info;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2561ead..1ff5cac 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -23,6 +23,8 @@
 #define CONFIG_SYS_FSL_GUTS_ADDR   (CONFIG_SYS_IMMR + 0x00ee)
 #define CONFIG_SYS_FSL_RST_ADDR(CONFIG_SYS_IMMR + 
0x00ee00b0)
 #define CONFIG_SYS_FSL_SCFG_ADDR

[U-Boot] [PATCH v3 0/2] arm: ppc: Share DPAA1 fixups between ARCHs

2017-12-11 Thread Ahmed Mansour

- Support DPAA1 QBMan device tree fixups in a shared location for both
  arm and ppc architectures
- cleanup a define from header files and add as Kconfig with auto
  selection based on SOC

Changes in v3:
- Add freescale old copyright in new file since it is a modified copy
- Add ifdef QBMAN guard around get_qman_freq()
- Return freq_qman instead of freq_systembus. More readable and robust
- Add white space before return line in get_qman_freq()

Changes in v2:
- Add get_qman_freq() to replace get_sys_info() for readability
- Correct the copyright year in new files
- Replace !ARM with PPC to wall off PowerPC SOCs specific qman setup
- Rename portals.c -> fsl_portals.c for clarity

Ahmed Mansour (2):
  drivers/misc: Share qbman init between archs
  Move SYS_DPAA_QBMAN to Kconfig

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|   4 +
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c|   9 +
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |  14 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  29 ++
 arch/arm/include/asm/arch-fsl-layerscape/speed.h   |   3 +
 arch/powerpc/cpu/mpc85xx/cpu_init.c|   3 +-
 arch/powerpc/cpu/mpc85xx/fdt.c |   1 +
 arch/powerpc/cpu/mpc85xx/portals.c | 281 ---
 arch/powerpc/include/asm/fsl_liodn.h   |   7 +-
 arch/powerpc/include/asm/fsl_portals.h |   4 -
 arch/powerpc/include/asm/immap_85xx.h  |  60 
 drivers/misc/Makefile  |   1 +
 drivers/misc/fsl_portals.c | 305 +
 drivers/net/Kconfig|  22 ++
 include/configs/B4860QDS.h |   1 -
 include/configs/P1023RDB.h |   1 -
 include/configs/P2041RDB.h |   1 -
 include/configs/T102xQDS.h |   1 -
 include/configs/T102xRDB.h |   1 -
 include/configs/T1040QDS.h |   1 -
 include/configs/T104xRDB.h |   1 -
 include/configs/T208xQDS.h |   1 -
 include/configs/T208xRDB.h |   1 -
 include/configs/T4240QDS.h |   1 -
 include/configs/T4240RDB.h |   1 -
 include/configs/corenet_ds.h   |   1 -
 include/configs/cyrus.h|   1 -
 include/configs/ls1046a_common.h   |   4 -
 include/fsl_qbman.h|  75 +
 29 files changed, 470 insertions(+), 365 deletions(-)
 create mode 100644 drivers/misc/fsl_portals.c
 create mode 100644 include/fsl_qbman.h

-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] stm32f4: Support over-drive mode in standard code path

2017-12-11 Thread Stefan Berzl


From 0d0ea4a15605080f0418d601e6539d6555266475 Mon Sep 17 00:00:00 2001
From: Stefan Berzl 
Date: Mon, 11 Dec 2017 23:41:04 +0100
Subject: [PATCH] stm32f4: Support over-drive mode in standard code path

The datasheet for the stm32f429-discovery says that the clock rate of
180 Mhz is only attainable when the system is switched to over-drive,
so I added support for that.

Signed-off-by: Stefan Berzl 
---
 arch/arm/include/asm/arch-stm32f4/stm32.h |  5 ---
 arch/arm/include/asm/arch-stm32f4/stm32_pwr.h |  4 +-
 arch/arm/mach-stm32/stm32f4/clock.c   | 55 +++
 3 files changed, 41 insertions(+), 23 deletions(-)

diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h 
b/arch/arm/include/asm/arch-stm32f4/stm32.h
index e9f3aabb6f..f5bdaeb895 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -42,11 +42,6 @@ struct stm32_u_id_regs {
u32 u_id_high;
 };
 
-struct stm32_pwr_regs {

-   u32 cr;
-   u32 csr;
-};
-
 /*
  * Registers access macros
  */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h 
b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
index bfe54698b3..9fa5a5b06a 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
@@ -16,8 +16,8 @@
 #define PWR_CSR1_ODSWRDY   BIT(17)
 
 struct stm32_pwr_regs {

-   u32 cr1;   /* power control register 1 */
-   u32 csr1;  /* power control/status register 2 */
+   u32 cr;   /* power control register */
+   u32 csr;  /* power control/status register */
 };
 
 #endif /* __STM32_PWR_H_ */

diff --git a/arch/arm/mach-stm32/stm32f4/clock.c 
b/arch/arm/mach-stm32/stm32f4/clock.c
index 774591d6a5..706d716fd2 100644
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define RCC_CR_HSION		(1 << 0)

 #define RCC_CR_HSEON   (1 << 16)
@@ -88,25 +89,31 @@
 #if (CONFIG_STM32_HSE_HZ == 800)
 #if (CONFIG_SYS_CLK_FREQ == 18000)
 /* 180 MHz */
-struct pll_psc sys_pll_psc = {
-   .pll_m = 8,
-   .pll_n = 360,
-   .pll_p = 2,
-   .pll_q = 8,
-   .ahb_psc = AHB_PSC_1,
-   .apb1_psc = APB_PSC_4,
-   .apb2_psc = APB_PSC_2
+struct stm32_clk_info stm32f4_clk_info = {
+   .sys_pll_psc = {
+   .pll_m = 8,
+   .pll_n = 360,
+   .pll_p = 2,
+   .pll_q = 8,
+   .ahb_psc = AHB_PSC_1,
+   .apb1_psc = APB_PSC_4,
+   .apb2_psc = APB_PSC_2,
+   },
+   .has_overdrive = true
 };
 #else
 /* default 168 MHz */
-struct pll_psc sys_pll_psc = {
-   .pll_m = 8,
-   .pll_n = 336,
-   .pll_p = 2,
-   .pll_q = 7,
-   .ahb_psc = AHB_PSC_1,
-   .apb1_psc = APB_PSC_4,
-   .apb2_psc = APB_PSC_2
+struct stm32_clk_info stm32f4_clk_info = {
+   .sys_pll_psc = {
+   .pll_m = 8,
+   .pll_n = 336,
+   .pll_p = 2,
+   .pll_q = 7,
+   .ahb_psc = AHB_PSC_1,
+   .apb1_psc = APB_PSC_4,
+   .apb2_psc = APB_PSC_2
+   },
+   .has_overdrive = false
 };
 #endif
 #else
@@ -116,6 +123,8 @@ struct pll_psc sys_pll_psc = {
 
 int configure_clocks(void)

 {
+   struct pll_psc sys_pll_psc = stm32f4_clk_info.sys_pll_psc;
+
/* Reset RCC configuration */
setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
@@ -151,6 +160,20 @@ int configure_clocks(void)
while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
;
 
+	if (stm32f4_clk_info.has_overdrive) {

+   /* Enable Over-drive mode */
+   setbits_le32(&STM32_PWR->cr, PWR_CR1_ODEN);
+
+   while (!(readl(&STM32_PWR->csr) & PWR_CSR1_ODRDY))
+   ;
+
+   /* Enable the Over-drive switch */
+   setbits_le32(&STM32_PWR->cr, PWR_CR1_ODSWEN);
+
+   while (!(readl(&STM32_PWR->csr) & PWR_CSR1_ODSWRDY))
+   ;
+   }
+
stm32_flash_latency_cfg(5);
clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
--
2.15.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] Swig now required to build U-Boot?

2017-12-11 Thread Tom Rini

On Fri, Dec 08, 2017 at 04:16:41PM -0800, Sergey Kubushyn wrote:
> On Fri, 8 Dec 2017, Simon Glass wrote:
> 
> >Hi Stephen,
> >
> >On 8 December 2017 at 16:28, Stephen Warren  wrote:
> >>Simon,
> >>
> >>Is it expected that the latest u-boot-dm.git master branch now requires
> >>swig? All the non-sandbox builds on my test systems are failing:
> >>
> >>  CHK include/config/uboot.release
> >>  CHK include/generated/timestamp_autogenerated.h
> >>  GEN ./Makefile
> >>  UPD include/generated/timestamp_autogenerated.h
> >>  CHK include/config.h
> >>  CFG u-boot.cfg
> >>  SHIPPED scripts/dtc/pylibfdt/libfdt.i
> >>  PYMOD   scripts/dtc/pylibfdt/_libfdt.so
> >>unable to execute 'swig': No such file or directory
> >>error: command 'swig' failed with exit status 1
> >>make[4]: *** [scripts/dtc/pylibfdt/_libfdt.so] Error 1
> >>make[3]: *** [scripts/dtc/pylibfdt] Error 2
> >>make[2]: *** [scripts/dtc] Error 2
> >>make[1]: *** [scripts] Error 2
> >>make[1]: *** Waiting for unfinished jobs
> >
> >Yes, unless we have a very recent libfdt on the system (and even then
> >I'm not sure that it is picked up). We need swig to build pylibfdt
> >which is needed for binman.
> 
> Err, would it be long before we need Java/Eclipse/Maven/younameit to just
> build U-Boot?

There is a fine line to be walked here.  On the flip side, do we want to
have to depend on N little external tools to put together a functional
image?  We can use binman to avoid some subset of that.  That said,
Simon, are we only building binman related stuff when we need binman in
the end?  Thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] Please pull ARC changes

2017-12-11 Thread Tom Rini

On Mon, Dec 11, 2017 at 08:43:12AM +, Alexey Brodkin wrote:

> Hi Tom,
> 
> Seems like I'm a little bit late as RC1 was already cut but anyways
> I think most if not all the mentioned below changes could be safely pulled.
> 
> That's because 5 of 6 patches are really just very trivial fixes
> (which I think is quite of for post-RC1 stage) and the only more significant
> change is HSDK clk driver. Still that patch was floated on the mailing list
> quite some time ago and shouldn't cause any troubles because it is by default
> is disabled, and essentially it all went through full TravisCI build so
> I don't expect any issues.
> 
> Anyways if you prefer I may exclude HSDK clk driver from this pull-request and
> resend it shortly.
> 
> The following changes since commit 335f7b1290ce24a729a9689a1db834c743226ca8:
> 
>   Merge git://git.denx.de/u-boot-mpc85xx (2017-12-08 12:02:01 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-arc.git 
> 
> for you to fetch changes up to e80dac0ab83ccb1d54e2d91b93d27b54a7f6544f:
> 
>   ARC: clk: introduce HSDK CGU clock driver (2017-12-11 11:36:23 +0300)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [GIT PULL] u-boot-uniphier/master

2017-12-11 Thread Tom Rini

On Tue, Dec 12, 2017 at 12:45:29AM +0900, Masahiro Yamada wrote:

> Hi Tom,
> 
> Please pull some more fixes and trivial changes.
> Thanks!
> 
> 
> 
> The following changes since commit 335f7b1290ce24a729a9689a1db834c743226ca8:
> 
>   Merge git://git.denx.de/u-boot-mpc85xx (2017-12-08 12:02:01 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-uniphier.git master
> 
> for you to fetch changes up to 7f8e75390b9c9b79748b2f87dd7ab45674323d58:
> 
>   ARM: uniphier: use FIELD_PREP for PLL settings (2017-12-12 00:36:12 +0900)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 0/7] Fix incorrect usage of the (FIT) DT node unit address

Hi Andre,

On 3 December 2017 at 19:05, Andre Przywara  wrote:
> The DT spec[1] demands a unit-address in a node name (name@address) to
> match the "reg" property inside that node:
> uart0: serial@1c28000 {
> reg = <0x01c28000 0x400>;
> 
> If there is no reg property in a node, there must not be a unit address
> in the node name as well (so no '@' sign at all).
>
> Newer version of the device tree compiler (dtc) will warn about violations
> of this rule:
> 
> : Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name,
> but no reg property
> 
>
> To avoid those warnings, but still keep enumerable node names, we replace
> the "@" sign with a dash ("-"), which does not have a specical meaning,
> but is a valid node name character. So the first fdt file (as referenced
> above in the warning message) would be called "fdt-1" instead.
>
> This affects mostly documenation files and some examples of FIT image
> files, but also some code which actually generates FIT images:
> - The first four patches fix documentation, example files and comments,
> they should not affect actual generated code or files.
> In places where having multiple instances of a node is normal (fdt,
> hash, signature), I simply replaced the '@' sign with the dash.
> Where one would expect only one instance (kernel, initrd), I removed the
> bogus '@1' completely, so a "kernel" just goes by just this very name.
> - Patch 5/7 fixes the usage in the Allwinner SPL FIT image files, this has
> been on the list before.
> - Patch 6/7 fixes the usage when the mkimage tool (auto-)generates FIT images.
> - The final patch 7/7 fixes the usage for the ARMv8 secure firmware image
> handling. I am a bit unsure about this one, as this seems to *look* for
> a specific node name, which sounds a bit dodgy to me. I think DT parsers
> should never rely on a certain node name, but either use references or look
> inside nodes to find a matching one. Also I am not sure who actually
> generates those FIT image files this code gets to read. Any input would
> be welcome here.
>
> Please let me know if this makes some sense or not.

I thought I read somewhere that there is a dtc option to turn off
these warnings?

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 3/5] Introduce CONFIG_ENABLE_BUG_CHECKS to disable BUG{_ON} by default

On 3 December 2017 at 20:37, Masahiro Yamada
 wrote:
> BUG() and BUG_ON() are generally used to test a condition that should
> never happen.  If it does, it is a bug.
>
> Linux always enables them, but doing so in U-Boot causes image size
> problems on some platforms.  Introduce CONFIG_ENABLE_BUG_CHECKS to
> make them no-op by default.  Platforms without image size constraint
> are free to enable this option to catch bugs easily.
>
> Likewise, silence WARN_ON() unless this option is enabled.
>
> Suggested-by: Tom Rini 
> Signed-off-by: Masahiro Yamada 
> ---
>
> Changes in v2:
>   - Newly added
>
>  include/linux/bug.h | 9 -
>  lib/Kconfig | 7 +++
>  2 files changed, 15 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 2/5] Enable CONFIG_PANIC_HANG for boards without do_reset()

On 3 December 2017 at 20:37, Masahiro Yamada
 wrote:
> Calling panic() for these boards causes build error:
>   undefined reference to `do_reset'
>
> They must compile do_reset(), or define CONFIG_PANIC_HANG.
>
> Signed-off-by: Masahiro Yamada 
> ---
>
> Changes in v2: None
>
>  configs/cl-som-imx7_defconfig | 1 +
>  configs/evb-rk3229_defconfig  | 1 +
>  configs/mccmon6_sd_defconfig  | 1 +
>  configs/opos6uldev_defconfig  | 1 +
>  4 files changed, 4 insertions(+)

Reviewed-by: Simon Glass 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] gpio/hsdk: Depend on DM_GPIO instead of simple DM

On 10 December 2017 at 10:55, Alexey Brodkin
 wrote:
> This driver really is DM GPIO one and so we need to have a correct
> dependency, because DM alone doesn't provide required for CMD_GPIO
> call and we're seeing build failures like this:
> -->8-
> cmd/built-in.o: In function 'do_gpio':
> .../cmd/gpio.c:188: undefined reference to 'gpio_request'
> ...
> -->8-
>
> Signed-off-by: Alexey Brodkin 
> Cc: Eugeniy Paltsev 
> Cc: Simon Glass 
> ---
>  drivers/gpio/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 5/5] Remove assert()

On 3 December 2017 at 20:37, Masahiro Yamada
 wrote:
> No more users of assert() except host tools.  Remove.
>
> Signed-off-by: Masahiro Yamada 
> ---
>
> Changes in v2: None
>
>  include/common.h  | 15 ---
>  lib/tiny-printf.c |  9 -
>  lib/vsprintf.c|  9 -
>  3 files changed, 33 deletions(-)

Reviewed-by: Simon Glass 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: socfpga: Remove static declaration on spl_mmc_find_device function

On Isn, 2017-12-11 at 12:03 +0100, Marek Vasut wrote:
> On 12/11/2017 11:53 AM, tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> So the tags would imply this has a lot to do with SoCFPGA, but this
> is
> not touching any file in the SoCFPGA. The tags are thus completely
> bogus.
> 
Opps...sorry, i forgot to remove the socfpga tag. I would fix it.
> > 
> > This patch removes the static declation on
> > spl_mmc_find_device_function
> > so this function is accessible by the caller from other file. This
> > patch
> > is required for later patch.
> > 
> > Signed-off-by: Tien Fong Chee 
> > ---
> >  common/spl/spl_mmc.c | 2 +-
> >  include/spl.h| 2 ++
> >  2 files changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
> > index b57e0b0..183d05a 100644
> > --- a/common/spl/spl_mmc.c
> > +++ b/common/spl/spl_mmc.c
> > @@ -114,7 +114,7 @@ static int spl_mmc_get_device_index(u32
> > boot_device)
> >     return -ENODEV;
> >  }
> >  
> > -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
> > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
> >  {
> >  #if CONFIG_IS_ENABLED(DM_MMC)
> >     struct udevice *dev;
> > diff --git a/include/spl.h b/include/spl.h
> > index 308ce7b..912983a 100644
> > --- a/include/spl.h
> > +++ b/include/spl.h
> > @@ -10,6 +10,7 @@
> >  /* Platform-specific defines */
> >  #include 
> >  #include 
> > +#include 
> >  
> >  /* Value in r0 indicates we booted from U-Boot */
> >  #define UBOOT_NOT_LOADED_FROM_SPL  0x13578642
> > @@ -72,6 +73,7 @@ void preloader_console_init(void);
> >  u32 spl_boot_device(void);
> >  u32 spl_boot_mode(const u32 boot_device);
> >  void spl_set_bd(void);
> > +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
> >  
> >  /**
> >   * spl_set_header_raw_uboot() - Set up a standard SPL image
> > structure
> > 
> 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 2/2] common: Generic firmware loader for file system

On Isn, 2017-12-11 at 13:16 +0100, Lothar Waßmann wrote:
> Hi,
> 
> On Mon, 11 Dec 2017 18:53:46 +0800 tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> > 
> [...}
> > 
> > +/*
> > + * Prepare firmware struct;
> > + * return -ve if fail.
> > + */
> > +static int _request_firmware_prepare(struct firmware **firmware_p,
> > +    const char *name, void *dbuf,
> > +    size_t size, u32 offset)
> > +{
> > +   struct firmware *firmware = NULL;
> > +   int ret = 0;
> > +
> > +   *firmware_p = NULL;
> > 
> Sigh. This is useless...
> > 
> > +   if (!name || name[0] == '\0')
> > +   ret = -EINVAL;
> > +
> unless you do a 'return -EINVAL' here!
> 
You are right, i missed to change this to return. I would fix it.
> > 
> > +   *firmware_p = firmware = calloc(1, sizeof(*firmware));
> > +
> > +   if (!firmware) {
> > +   printf("%s: calloc(struct firmware) failed\n",
> > __func__);
> > +   return -ENOMEM;
> > +   }
> > +
> > +   firmware->name = name;
> > +   firmware->data = dbuf;
> > +   firmware->size = size;
> > +   firmware->offset = offset;
> > +
> > +   return ret;
> > +}
> > +
> 
> Lothar Waßmann
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 0/7] Fix incorrect usage of the (FIT) DT node unit address

2017-12-11 Thread Masahiro Yamada

Hi Simon,


2017-12-12 13:38 GMT+09:00 Simon Glass :
> Hi Andre,
>
> On 3 December 2017 at 19:05, Andre Przywara  wrote:
>> The DT spec[1] demands a unit-address in a node name (name@address) to
>> match the "reg" property inside that node:
>> uart0: serial@1c28000 {
>> reg = <0x01c28000 0x400>;
>> 
>> If there is no reg property in a node, there must not be a unit address
>> in the node name as well (so no '@' sign at all).
>>
>> Newer version of the device tree compiler (dtc) will warn about violations
>> of this rule:
>> 
>> : Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name,
>> but no reg property
>> 
>>
>> To avoid those warnings, but still keep enumerable node names, we replace
>> the "@" sign with a dash ("-"), which does not have a specical meaning,
>> but is a valid node name character. So the first fdt file (as referenced
>> above in the warning message) would be called "fdt-1" instead.
>>
>> This affects mostly documenation files and some examples of FIT image
>> files, but also some code which actually generates FIT images:
>> - The first four patches fix documentation, example files and comments,
>> they should not affect actual generated code or files.
>> In places where having multiple instances of a node is normal (fdt,
>> hash, signature), I simply replaced the '@' sign with the dash.
>> Where one would expect only one instance (kernel, initrd), I removed the
>> bogus '@1' completely, so a "kernel" just goes by just this very name.
>> - Patch 5/7 fixes the usage in the Allwinner SPL FIT image files, this has
>> been on the list before.
>> - Patch 6/7 fixes the usage when the mkimage tool (auto-)generates FIT 
>> images.
>> - The final patch 7/7 fixes the usage for the ARMv8 secure firmware image
>> handling. I am a bit unsure about this one, as this seems to *look* for
>> a specific node name, which sounds a bit dodgy to me. I think DT parsers
>> should never rely on a certain node name, but either use references or look
>> inside nodes to find a matching one. Also I am not sure who actually
>> generates those FIT image files this code gets to read. Any input would
>> be welcome here.
>>
>> Please let me know if this makes some sense or not.
>
> I thought I read somewhere that there is a dtc option to turn off
> these warnings?
>

I think -Wno-unit_address_vs_reg is the one,
but I prefer to fix the root cause by replacing @
instead of hiding it.



-- 
Best Regards
Masahiro Yamada
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC 0/5] sf: Update spi-nor framework

2017-12-11 Thread Prabhakar Kushwaha

Hi Marek,

> -Original Message-
> From: Marek Vasut [mailto:marek.va...@gmail.com]
> Sent: Monday, December 11, 2017 3:04 PM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de
> Cc: jagannadh.t...@gmail.com; Poonam Aggrwal
> ; Suresh Gupta ;
> cyrille.pitc...@atmel.com
> Subject: Re: [RFC 0/5] sf: Update spi-nor framework
> 
> On 12/11/2017 06:57 AM, Prabhakar Kushwaha wrote:
> > SPI-NOR framework currently supports-
> >  - (1-1-1, 1-1-2, 1-1-4) read protocols
> >  - read latency(dummy bytes) are hardcoded with the assumption
> >  that the flash would support it.
> >  - No support of mode bits.
> >  - No support of flash size above 128Mib
> >
> > This patch set add support of 1-2-2, 1-4-4 read protocols.
> > It ports Linux commits "mtd: spi-nor: add a stateless method to support
> > memory size above 128Mib" and "mtd: spi-nor: parse Serial Flash
> > Discoverable Parameters (SFDP) tables". It enables 4byte address opcode
> > and run time flash parameters discovery including dummy cycle and mode
> > cycle.
> >
> > Finally it update fsl-quadspi driver to store(set_mode) spi bus mode and
> > provision for run-time LUTs creation.
> >
> > Note: This patch-set is only **compliation** tested. Sending RFC to get
> > early feed-back on the approach.
> >
> > Prabhakar Kushwaha (5):
> >   sf: Add support of 1-2-2, 1-4-4 IO READ protocols
> >   sf: add method to support memory size above 128Mib
> >   sf: parse Serial Flash Discoverable Parameters (SFDP) tables
> >   sf: fsl_qspi: Add support of fsl_qspi_set_mode
> >   sf: fsl_quadspi: Configue LUT based on padding information
> >
> >  drivers/mtd/spi/sf_internal.h   | 230 +++-
> >  drivers/mtd/spi/spi_flash.c | 574
> +++-
> >  drivers/spi/fsl_qspi.c  |  85 +-
> >  include/spi_flash.h |   2 +
> >  5 files changed, 875 insertions(+), 18 deletions(-)
> >
> 
> Could you rather port the entire SPI NOR framework from Linux 4.14 ?
> That'd make more sense than porting bits and pieces on top of the
> current crappy code IMO.

I agree with you. Linux 4.14 SPI NOR framework should be ported.
I may not able to do this because of bandwidth and lack of expertise.  
I will request Jagan (custodian) to look into this.

This RFC patch-set can easily be applied to existing and  ported Linux SPI NOR 
framework when it gets available.

For now, I think these patches(the next version) with the existing framework 
can be reviewed and accepted.
Please help to share your views.

For next version of this patch set, I will be working on testing  it to enable 
other flashes. 
It will also help Jagan during 4.14 porting.  
Jagan, your views?

--pk   




___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 00/16] sun50i: a64: add support for axp803, musb

This series deals axp803, musb and related improvements on a64
- axp803 PMIC support used by a64
- a64 musb improvements (rework by Philipp [1])
- musb support for bananapi-m64, a64-olinuxino

[1] https://patchwork.ozlabs.org/patch/729246/ 

Jagan Teki (11):
  power: sunxi: add AXP803 PMIC support
  sunxi: adjust usb bases between H3_H5 vs a64
  musb-new: sunxi: add common SUNXI_MUSB_BASE
  sunxi: usb_phy: Update a64 sunxi_usb_phy base
  arm64: allwinner: sync bananapi-m64 usb nodes from Linux
  configs: sun50i: add usb-otg support for bananapi-m64
  configs: sun50i: enable ums on bananapi-m64
  arm64: allwinner: sync a64-olinuxino usb nodes from Linux
  configs: sun50i: add usb-otg support for a64-olinuxino
  configs: sun50i: enable ums on a64-olinuxino
  configs: sun50i: Enable eMMC on a64-olinuxino

Philipp Tomsich (5):
  sunxi (sun50i): Set CONFIG_SUNXI_USB_PHYS to 2 (the A64 has 2 PHYs)
  musb-new: sunxi: a64: add support to select shared phy
  musb-new: sunxi: a64: adds support for clearing the SIDDP
  usb: sunxi: set up usb_phy_passby only for HCI
  sunxi: clock: update a64 usb clock gating and module reset bits

 arch/arm/dts/sun50i-a64-bananapi-m64.dts  |  27 +++
 arch/arm/dts/sun50i-a64-olinuxino.dts |  19 ++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |  16 +-
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h   |   6 +
 arch/arm/include/asm/arch-sunxi/usb_phy.h |   2 +
 arch/arm/mach-sunxi/Makefile  |   9 +
 arch/arm/mach-sunxi/pmic_bus.c|   9 +-
 arch/arm/mach-sunxi/rsb.c |   2 +-
 arch/arm/mach-sunxi/usb_phy.c |  24 ++-
 board/sunxi/board.c   |  40 
 configs/a64-olinuxino_defconfig   |   6 +
 configs/bananapi_m64_defconfig|   4 +
 drivers/power/Kconfig |  95 +++---
 drivers/power/Makefile|   3 +
 drivers/power/axp803.c| 260 ++
 drivers/usb/host/ehci-sunxi.c |  10 +
 drivers/usb/host/ohci-sunxi.c |  10 +
 drivers/usb/musb-new/musb_regs.h  |   3 +-
 drivers/usb/musb-new/sunxi.c  |  24 ++-
 include/axp803.h  |  68 +++
 include/axp_pmic.h|   4 +
 include/configs/sun50i.h  |   2 +-
 22 files changed, 598 insertions(+), 45 deletions(-)
 create mode 100644 drivers/power/axp803.c
 create mode 100644 include/axp803.h

-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 02/16] sunxi (sun50i): Set CONFIG_SUNXI_USB_PHYS to 2 (the A64 has 2 PHYs)

From: Philipp Tomsich 

The sun50i platform (e.g. the A64/sun50iw1p1) integrates 2 USB PHYs
which are connected as follows:
  PHY#0 is shared between the OTG controller (MUSB) [at 01C19000]
and the USB-OTG-HCI [at 01C1A000]
  PHY#1 is dedicated to USB-HCI0 [at 01C1B000] and can be bypassed
when connecting HCI0 to the HSIC interface

Note that all USB PHYs are controlled from within the OTG address
space at 01C19000.

X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich 
[jagan: rebased, fixed 80 line warning]
Signed-off-by: Jagan Teki 
Acked-by: Maxime Ripard 
---
 drivers/usb/musb-new/musb_regs.h | 3 ++-
 include/configs/sun50i.h | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h
index a3cc38e..89b5dbc 100644
--- a/drivers/usb/musb-new/musb_regs.h
+++ b/drivers/usb/musb-new/musb_regs.h
@@ -432,7 +432,8 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem 
*mbase)
 
 static inline u8 musb_read_configdata(void __iomem *mbase)
 {
-#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T
+#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T \
+   || defined CONFIG_MACH_SUN50I
/*  allwinner saves a reg, and we need to hardcode this */
return 0xde;
 #else
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
index b7b67a1..9f3a8a6 100644
--- a/include/configs/sun50i.h
+++ b/include/configs/sun50i.h
@@ -16,7 +16,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 #endif
 
-#define CONFIG_SUNXI_USB_PHYS  1
+#define CONFIG_SUNXI_USB_PHYS  2
 
 #define GICD_BASE  0x1c81000
 #define GICC_BASE  0x1c82000
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 01/16] power: sunxi: add AXP803 PMIC support

AXP803 another PMIC produced by x-powers and paired with
A64 via RSB bus.

unlike other axp chip's support in SPL this is only added
for U-Boot proper since SPL on A64 has no space to add anything.

Signed-off-by: Jagan Teki 
---
 arch/arm/mach-sunxi/Makefile   |   9 ++
 arch/arm/mach-sunxi/pmic_bus.c |   9 +-
 arch/arm/mach-sunxi/rsb.c  |   2 +-
 board/sunxi/board.c|  40 +++
 drivers/power/Kconfig  |  95 ++-
 drivers/power/Makefile |   3 +
 drivers/power/axp803.c | 260 +
 include/axp803.h   |  68 +++
 include/axp_pmic.h |   4 +
 9 files changed, 458 insertions(+), 32 deletions(-)
 create mode 100644 drivers/power/axp803.c
 create mode 100644 include/axp803.h

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 2a3c379..aedf22f 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -19,9 +19,15 @@ endif
 obj-$(CONFIG_MACH_SUN6I)   += prcm.o
 obj-$(CONFIG_MACH_SUN8I)   += prcm.o
 obj-$(CONFIG_MACH_SUN9I)   += prcm.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_MACH_SUN50I)  += prcm.o
+endif
 obj-$(CONFIG_MACH_SUN6I)   += p2wi.o
 obj-$(CONFIG_MACH_SUN8I)   += rsb.o
 obj-$(CONFIG_MACH_SUN9I)   += rsb.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_MACH_SUN50I)  += rsb.o
+endif
 obj-$(CONFIG_MACH_SUN4I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)   += clock_sun6i.o
@@ -38,6 +44,9 @@ obj-$(CONFIG_AXP152_POWER)+= pmic_bus.o
 obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP809_POWER) += pmic_bus.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_AXP803_POWER) += pmic_bus.o
+endif
 obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index f917c3e..34acd01 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -36,7 +36,8 @@ int pmic_bus_init(void)
if (!needs_init)
return 0;
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+   defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
p2wi_init();
ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -65,7 +66,8 @@ int pmic_bus_read(u8 reg, u8 *data)
return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
 #elif defined CONFIG_AXP209_POWER
return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+   defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
return p2wi_read(reg, data);
 # elif defined CONFIG_MACH_SUN8I_R40
@@ -82,7 +84,8 @@ int pmic_bus_write(u8 reg, u8 data)
return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
 #elif defined CONFIG_AXP209_POWER
return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+   defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
return p2wi_write(reg, data);
 # elif defined CONFIG_MACH_SUN8I_R40
diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c
index 6fd11f1..ea52a6f 100644
--- a/arch/arm/mach-sunxi/rsb.c
+++ b/arch/arm/mach-sunxi/rsb.c
@@ -27,7 +27,7 @@ static void rsb_cfg_io(void)
sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
-#elif defined CONFIG_MACH_SUN9I
+#elif defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index dcacdf3..158282e 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -173,6 +173,40 @@ void i2c_init_board(void)
 #endif
 }
 
+#ifdef CONFIG_AXP803_POWER
+static int axp803_init(void)
+{
+   int power_failed = 0;
+
+   power_failed = axp_init();
+
+   power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
+   power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
+   power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
+   power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
+   power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
+   power_failed |= axp_set_dcdc6(CONFIG_AXP_DCDC6_VOLT);
+
+   power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
+   pow

[U-Boot] [PATCH 05/16] musb-new: sunxi: a64: add support to select shared phy

From: Philipp Tomsich 

Allwinner a64 has a shared PHY for MUSB and USB-OTG-HCI,
so add function to select the PHY route.

Signed-off-by: Philipp Tomsich 
[jagan: reworked for remove func support]
Signed-off-by: Jagan Teki 
---
 drivers/usb/musb-new/sunxi.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 2e22497..45ddf20 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -45,6 +45,9 @@
 #define  USBC_REG_o_PHYCTL 0x0404
 #define  USBC_REG_o_PHYBIST0x0408
 #define  USBC_REG_o_PHYTUNE0x040c
+#if defined(CONFIG_MACH_SUN50I)
+#defineSUNXI_OTG_PHY_CFG   0x0420
+#endif
 
 #define  USBC_REG_o_VEND0  0x0043
 
@@ -162,6 +165,16 @@ static void USBC_ConfigFIFO_Base(void)
writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
 }
 
+#if defined(CONFIG_MACH_SUN50I)
+static void USBC_SelectPhyToDevice(__iomem void *base, bool routePHYtoOTG)
+{
+   /* The OTG and HCI0 controllers share a single PHY in the A64.
+* Select either 'to OTG' (1) or 'to HCI' (0).
+*/
+   clrsetbits_le32(base + SUNXI_OTG_PHY_CFG, 1, routePHYtoOTG ? 1 : 0);
+}
+#endif
+
 /**
  * Needed for the DFU polling magic
  
**/
@@ -267,6 +280,9 @@ static int sunxi_musb_init(struct musb *musb)
setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
 #endif
sunxi_usb_phy_init(0);
+#if defined(CONFIG_MACH_SUN50I)
+   USBC_SelectPhyToDevice(musb->mregs, true);
+#endif
 
USBC_ConfigFIFO_Base();
USBC_EnableDpDmPullUp(musb->mregs);
@@ -342,6 +358,9 @@ static int musb_usb_remove(struct udevice *dev)
musb_stop(host->host);
 
sunxi_usb_phy_exit(0);
+#if defined(CONFIG_MACH_SUN50I)
+   USBC_SelectPhyToDevice(host->host->mregs, false);
+#endif
 #ifdef CONFIG_SUNXI_GEN_SUN6I
clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
 #endif
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 12/16] configs: sun50i: enable ums on bananapi-m64

This patch enable ums through CMD_USB_MASS_STORAGE.

Signed-off-by: Jagan Teki 
---
 configs/bananapi_m64_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig
index 55feafe..d4aade5 100644
--- a/configs/bananapi_m64_defconfig
+++ b/configs/bananapi_m64_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64"
 CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 08/16] sunxi: clock: update a64 usb clock gating and module reset bits

From: Philipp Tomsich 

clock gating and module reset bits on a64 are different than H3_H5
and other allwinner family SOCs, add them on clock_sun6i.h

Signed-off-by: Philipp Tomsich 
[jagan: reowrked on entire patch]
Signed-off-by: Jagan Teki 
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d328df9..7cb9235 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -280,12 +280,24 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI2  27
 #define AHB_GATE_OFFSET_USB_EHCI1  26
 #define AHB_GATE_OFFSET_USB_EHCI0  25
+#elif defined(CONFIG_MACH_SUN50I)
+#define AHB_GATE_OFFSET_USB_OHCI0  29
+#define AHB_GATE_OFFSET_USBOTG_OHCI28
+#define AHB_GATE_OFFSET_USB_EHCI0  25
+#define AHB_GATE_OFFSET_USBOTG_EHCI24
+#define AHB_GATE_OFFSET_USBOTG 23
 #else
 #define AHB_GATE_OFFSET_USB_EHCI1  27
 #define AHB_GATE_OFFSET_USB_EHCI0  26
 #endif
-#ifndef CONFIG_MACH_SUN8I_R40
-#define AHB_GATE_OFFSET_USB0   24
+#ifdef CONFIG_MACH_SUN50I
+/*
+ * The musb-new/sunxi.c glue uses AHB_GATE_OFFSET_USB0
+ * for the MUSB OTG block, so we define it to what it expects.
+ */
+# define AHB_GATE_OFFSET_USB0  AHB_GATE_OFFSET_USBOTG
+#elif !defined(CONFIG_MACH_SUN8I_R40)
+# define AHB_GATE_OFFSET_USB0  24
 #else
 #define AHB_GATE_OFFSET_USB0   25
 #define AHB_GATE_OFFSET_SATA   24
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 11/16] configs: sun50i: add usb-otg support for bananapi-m64

USB-OTG require MUSB driver along with PHY#0 id(PH9) and/or
vbus pin through AXP_GPIO driver.

This patch add support for it.

Signed-off-by: Jagan Teki 
---
 configs/bananapi_m64_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig
index 461567f..55feafe 100644
--- a/configs/bananapi_m64_defconfig
+++ b/configs/bananapi_m64_defconfig
@@ -4,6 +4,8 @@ CONFIG_MACH_SUN50I=y
 CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_MMC0_CD_PIN="PH13"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_ID_DET="PH9"
+CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
@@ -14,4 +16,5 @@ CONFIG_SPL=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 09/16] sunxi: usb_phy: Update a64 sunxi_usb_phy base

a64 has shared PHY#0(for OTG and USB-OTG-HCI) which start at
0x01C19000 which different than other allwinner SOC, so
update the same for sunxi_usb_phy[0] base.

Signed-off-by: Jagan Teki 
---
 arch/arm/mach-sunxi/usb_phy.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index 4bc47a1..cc66446 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -63,7 +63,11 @@ static struct sunxi_usb_phy {
{
.usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
.id = 0,
+#ifdef CONFIG_MACH_SUN50I
+   .base = SUNXI_USBPHY_BASE,
+#else
.base = SUNXI_USB0_BASE,
+#endif
},
{
.usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 13/16] arm64: allwinner: sync a64-olinuxino usb nodes from Linux

Sync USB-OTG and USB-OTG-HCI nodes from Linux.

Signed-off-by: Jagan Teki 
---
 arch/arm/dts/sun50i-a64-olinuxino.dts | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts 
b/arch/arm/dts/sun50i-a64-olinuxino.dts
index 7bd4730..bd56355 100644
--- a/arch/arm/dts/sun50i-a64-olinuxino.dts
+++ b/arch/arm/dts/sun50i-a64-olinuxino.dts
@@ -66,6 +66,10 @@
};
 };
 
+&ehci0 {
+   status = "okay";
+};
+
 &mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -77,8 +81,23 @@
status = "okay";
 };
 
+&ohci0 {
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
 };
+
+&usb_otg {
+   dr_mode = "otg";
+   status = "okay";
+};
+
+&usbphy {
+   usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+   usb0_vbus_det-gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+   status = "okay";
+};
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 06/16] musb-new: sunxi: a64: adds support for clearing the SIDDP

From: Philipp Tomsich 

Allwinner a64 needs to clear the SIDDP bit from PHYCTL
register once the phy_init done.

Signed-off-by: Philipp Tomsich 
[jagan: reworked to fix multi-line comments]
Signed-off-by: Jagan Teki 
---
 arch/arm/include/asm/arch-sunxi/usb_phy.h |  1 +
 arch/arm/mach-sunxi/usb_phy.c | 11 +++
 drivers/usb/host/ehci-sunxi.c |  8 
 drivers/usb/host/ohci-sunxi.c |  8 
 drivers/usb/musb-new/sunxi.c  |  1 +
 5 files changed, 29 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h 
b/arch/arm/include/asm/arch-sunxi/usb_phy.h
index 5a9cacb..f97d415 100644
--- a/arch/arm/include/asm/arch-sunxi/usb_phy.h
+++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h
@@ -19,3 +19,4 @@ void sunxi_usb_phy_power_off(int index);
 int sunxi_usb_phy_vbus_detect(int index);
 int sunxi_usb_phy_id_detect(int index);
 void sunxi_usb_phy_enable_squelch_detect(int index, int enable);
+void sunxi_usb_phy_clear_SIDDP(void *base);
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index 2f1cad1..1bfee40 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -190,6 +190,17 @@ static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 }
 #endif
 
+#if defined(CONFIG_MACH_SUN50I)
+void sunxi_usb_phy_clear_SIDDP(void *base)
+{
+   /* We pretend that this is always at the same offset (0x410),
+* even though it is 0x410 for MUSB/OTG and OHCI, but 0x810
+* for EHCI.  The EHCI call site will have to adjust this...
+*/
+   clrbits_le32(base + SUNXI_USB_CSR, (1 << 1));
+}
+#endif
+
 static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
 {
unsigned long bits = 0;
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 6ecb7c4..c3432aa 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -61,6 +61,14 @@ static int ehci_usb_probe(struct udevice *dev)
 #endif
 
sunxi_usb_phy_init(priv->phy_index);
+#if defined(CONFIG_MACH_SUN50I)
+   /*
+* For the HCI blocks, the PHYCTL register is at 0x810, so
+* it's an extra 0x400 for the EHCI block.  This should go
+* away once the PHYs use the driver model.
+*/
+   sunxi_usb_phy_clear_SIDDP((void *)hccr + 0x400);
+#endif
sunxi_usb_phy_power_on(priv->phy_index);
 
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index 133774f..e9eeb56 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -66,6 +66,14 @@ static int ohci_usb_probe(struct udevice *dev)
 #endif
 
sunxi_usb_phy_init(priv->phy_index);
+#if defined(CONFIG_MACH_SUN50I)
+   /*
+* For the HCI blocks, the PHYCTL register is at 0x810, so it's
+* an extra 0x400 for the EHCI block.  This should go away once
+* the PHYs use the driver model.
+*/
+   sunxi_usb_phy_clear_SIDDP(regs);
+#endif
sunxi_usb_phy_power_on(priv->phy_index);
 
return ohci_register(dev, regs);
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 45ddf20..0d87582 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -281,6 +281,7 @@ static int sunxi_musb_init(struct musb *musb)
 #endif
sunxi_usb_phy_init(0);
 #if defined(CONFIG_MACH_SUN50I)
+   sunxi_usb_phy_clear_SIDDP(musb->mregs);
USBC_SelectPhyToDevice(musb->mregs, true);
 #endif
 
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 15/16] configs: sun50i: enable ums on a64-olinuxino