Re: [U-Boot] [PATCH] TCP and wget implementation v4

[Joe Hershberger]

On Fri, Jan 5, 2018 at 4:10 PM, Duncan Hare  wrote:
>> >
>> > A note on this TCP implementation. In TCP the transmitting TCP
>> > guarantees delivery of a stream, and the receiving TCP guarantees
>> > ordered of delivery of the stream. In this implementation The
>> > kernel memory buffer and the TCP sequence number is used to order
>> > the stream. for the application, and the application is the kernel
>> > itself. wget is not considered the application, and does receive
>> > packets "out of order."
>>
>> It seems like it would be possible to just store off a packet that is
>> ahead of its neighbor and not call any upper handler until the needed
>> packet arrives. Then all upper layers wouldn't need to know about the
>> reordering.
>
> There is, for u-boot a large number of buffers used on RX, in order
> to have a long work queue  of kernel data.
>
> CONFIG_SYS_RX_ETH_BUFFER 50
>
> The TCP transmit window is approximately 25 such packets, so overruns
> are eliminated.
>
> There are about 3300 kernel data packets in this test kernel, so missing
> a few, 3 to 5, has little impact on elapsed time, and they remain in the
> input buffer pool ahead of the HTTP header,
>
> The only critical order for this implementation is the TCP header.
> Without processing the TCP header we do not know the stream
> address of the first byte of kernel data. It is easy when we know this
> to map TCP stream address to kernel data offset.
>
>> >
>> > Advice on the reset buffer approach are invited. It requires an
>> > interface between the wget application to reset the buffer index.
>>
>> Between wget and what? The TCP implementation? It seems like something
>> that should be abstracted from wget.
>
> wget receives packets without intermediate ordering.
> Ordering data is a function of wget placing the kernel data at the
> correct offset, based of TCP stream location, at the correct memory
> address.
>
> wget is the agent which correctly orders data. There is no
> socket analogue, the abstraction, and a socket's linked list buffer
> reordering, which is the generally recognized reordering point for TCP
> data.
>
> Correct ordering is a primary task of this wget implementation,
> becuse the destination is a kernel image, and this choice very greatly
> simplifies the TCP stack, while reducing code complexity, and limits
> code size.
>
> Reordering would require a new piece of code similar to the fragment
> assemble piece of code in net.h, and that's an amazing, but complex,
> piece of code. My objective was to produce something as
> simple as possible.
>
> The TCP stack delivers packets in the order they come off the wire.
> Wget puts them in the correct order based on TCP sequence number to
> build the kernel image, and the TCP sequence number/ack protocol ensures
> complete delivery of a stream.

OK, it sounds like you've got a solution and a preference, so if it
makes more sense for this embedded implementation to maintain
simplicity, then so be it.

-Joe
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Re: [U-Boot] exFAT support in u-boot

[Lukasz Majewski]

Hi,

> Hi All,
> 
> As per my understanding, u-boot doesn't support exFAT.
> [ based on
> https://lists.denx.de/pipermail/u-boot/2012-March/119300.html ]

This seems to be a bit outdated.

I'm using stock SD cards in mainline u-boot.

> 
> Just want to know, is there is a way to add exFAT support to u-boot ?
> [ May be a similar way as exFAT support in Linux [
> https://github.com/relan/exfat] ]
> 
> The reason to use exFAT in u-boot is to use the same SD card for
> - data storage in multiple platforms
> - use the same SD card as a bootable one [ with out formatting ].
> 
> Please let me know.
> 
> Thanks,
> Arun
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Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH] TCP and wget implementation v4

[Duncan Hare]

> >
> > A note on this TCP implementation. In TCP the transmitting TCP
> > guarantees delivery of a stream, and the receiving TCP guarantees
> > ordered of delivery of the stream. In this implementation The
> > kernel memory buffer and the TCP sequence number is used to order
> > the stream. for the application, and the application is the kernel
> > itself. wget is not considered the application, and does receive
> > packets "out of order."  
> 
> It seems like it would be possible to just store off a packet that is
> ahead of its neighbor and not call any upper handler until the needed
> packet arrives. Then all upper layers wouldn't need to know about the
> reordering.

There is, for u-boot a large number of buffers used on RX, in order
to have a long work queue  of kernel data. 

CONFIG_SYS_RX_ETH_BUFFER 50 

The TCP transmit window is approximately 25 such packets, so overruns
are eliminated.

There are about 3300 kernel data packets in this test kernel, so missing
a few, 3 to 5, has little impact on elapsed time, and they remain in the
input buffer pool ahead of the HTTP header,

The only critical order for this implementation is the TCP header.
Without processing the TCP header we do not know the stream
address of the first byte of kernel data. It is easy when we know this
to map TCP stream address to kernel data offset.

> >
> > Advice on the reset buffer approach are invited. It requires an
> > interface between the wget application to reset the buffer index.  
> 
> Between wget and what? The TCP implementation? It seems like something
> that should be abstracted from wget.

wget receives packets without intermediate ordering.
Ordering data is a function of wget placing the kernel data at the
correct offset, based of TCP stream location, at the correct memory
address. 

wget is the agent which correctly orders data. There is no
socket analogue, the abstraction, and a socket's linked list buffer
reordering, which is the generally recognized reordering point for TCP
data.

Correct ordering is a primary task of this wget implementation,
becuse the destination is a kernel image, and this choice very greatly
simplifies the TCP stack, while reducing code complexity, and limits
code size.

Reordering would require a new piece of code similar to the fragment
assemble piece of code in net.h, and that's an amazing, but complex,
piece of code. My objective was to produce something as
simple as possible.

The TCP stack delivers packets in the order they come off the wire.
Wget puts them in the correct order based on TCP sequence number to
build the kernel image, and the TCP sequence number/ack protocol ensures
complete delivery of a stream.

  

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Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

[Marek Vasut]

On 01/05/2018 08:31 PM, Goldschmidt Simon wrote:
> On Fri, 05/01/2018 Marek Vasut wrote:
>> On 01/05/2018 04:49 PM, Goldschmidt Simon wrote:
> 
> 
> 
> OK, so I need these patches to get qspi work on socfpga:
>
> - Series "spi: cadence_spi: Adopt Linux DT bindings" (v4) from Jason Rush:
>   https://patchwork.ozlabs.org/project/uboot/list/?series=13864
> - Patch "Revert "spi: cadence_qspi_apb: Use 32 bit indirect read 
> transaction when possible" (v2)
>   https://patchwork.ozlabs.org/patch/838871/

 I've waited for ack/tested-by from marek or someone who usually worked
 on these cadence.
>>>
>>> Vignesh acked, who already did some of the last changes. But Ok, I've
>>> added Marek to the loop.
>>>
>>> Marek, do you see any problems here? Are you running QSPI on the
>>> socfpga platform anywhere?
>> I am not entirely sure what this partial thread is all about, do you
>> need some patches Acked ? Repost them including the Acks collected
>> already and CC me, I want to review them. PW link is not enough.
> 
> Marek, you were one of the people addressed in "to:" when Jason Rush
> sent "[PATCH v4 1/5] spi: cadence_spi: Sync DT bindings with Linux"
> and successors on Nov. 16th 2017.
> 
> You were also in the "to:" field when I sent "[PATCH v4 1/5] spi:
> cadence_spi: Sync DT bindings with Linux" on Nov. 17th 2017.
> 
> Should I resend them anyway?

I really dunno what to make of this sparse thread, sorry. Also, I don't
quite remember what happened in this thread on November 17th, sorry.

So maybe you should elaborate what you expect me to do ... or just
resend the patches, yes.

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH] ARM: bootm: don't assume sp is in DRAM bank 0

[Stephen Warren]

From: Stephen Warren 

arch_lmb_reserve() currently assumes that the stack pointer is within DRAM
bank 0. This is not necessarily true. Enhance the code to search through
DRAM banks until the bank that does contain SP is found, and then reserve
the tail of that bank.

Fixes: 2d1916e48bd8 ("ARM: add flat device tree support")
Signed-off-by: Stephen Warren 
---
It would be best to apply this patch before "ARM: Tegra186: search for
best RAM bank" is applied.
---
 arch/arm/lib/bootm.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 5c62d9c14406..89740657e0c5 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -47,7 +47,8 @@ static ulong get_sp(void)
 
 void arch_lmb_reserve(struct lmb *lmb)
 {
-   ulong sp;
+   ulong sp, bank_end;
+   int bank;
 
/*
 * Booting a (Linux) kernel image
@@ -63,8 +64,16 @@ void arch_lmb_reserve(struct lmb *lmb)
 
/* adjust sp by 4K to be safe */
sp -= 4096;
-   lmb_reserve(lmb, sp,
-   gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
+   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+   if (sp < gd->bd->bi_dram[bank].start)
+   continue;
+   bank_end = gd->bd->bi_dram[bank].start +
+   gd->bd->bi_dram[bank].size;
+   if (sp >= bank_end)
+   continue;
+   lmb_reserve(lmb, sp, bank_end - sp);
+   break;
+   }
 }
 
 __weak void board_quiesce_devices(void)
-- 
2.15.1

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Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

[Goldschmidt Simon]

On Fri, 05/01/2018 Marek Vasut wrote:
> On 01/05/2018 04:49 PM, Goldschmidt Simon wrote:



 OK, so I need these patches to get qspi work on socfpga:

 - Series "spi: cadence_spi: Adopt Linux DT bindings" (v4) from Jason Rush:
   https://patchwork.ozlabs.org/project/uboot/list/?series=13864
 - Patch "Revert "spi: cadence_qspi_apb: Use 32 bit indirect read 
 transaction when possible" (v2)
   https://patchwork.ozlabs.org/patch/838871/
>>>
>>> I've waited for ack/tested-by from marek or someone who usually worked
>>> on these cadence.
>>
>> Vignesh acked, who already did some of the last changes. But Ok, I've
>> added Marek to the loop.
>>
>> Marek, do you see any problems here? Are you running QSPI on the
>> socfpga platform anywhere?
> I am not entirely sure what this partial thread is all about, do you
> need some patches Acked ? Repost them including the Acks collected
> already and CC me, I want to review them. PW link is not enough.

Marek, you were one of the people addressed in "to:" when Jason Rush
sent "[PATCH v4 1/5] spi: cadence_spi: Sync DT bindings with Linux"
and successors on Nov. 16th 2017.

You were also in the "to:" field when I sent "[PATCH v4 1/5] spi:
cadence_spi: Sync DT bindings with Linux" on Nov. 17th 2017.

Should I resend them anyway?

Thanks,
Simon
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Re: [U-Boot] [PATCH 3/3] imx: mx7: psci: add system power off support

[Troy Kisky]

On 1/4/2018 10:03 PM, Anson Huang wrote:
> Add i.MX7 PSCI system power off support, linux
> kernel can use "poweroff" command to power off
> system via SNVS, PMIC power will be disabled.
> 
> Signed-off-by: Anson Huang 
> ---
>  arch/arm/mach-imx/mx7/psci-mx7.c | 18 ++
>  arch/arm/mach-imx/mx7/psci.S |  7 +++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c 
> b/arch/arm/mach-imx/mx7/psci-mx7.c
> index 66f6db6..0e515f0 100644
> --- a/arch/arm/mach-imx/mx7/psci-mx7.c
> +++ b/arch/arm/mach-imx/mx7/psci-mx7.c
> @@ -26,6 +26,12 @@
>  #define BP_SRC_A7RCR0_A7_CORE_RESET0 0
>  #define BP_SRC_A7RCR1_A7_CORE1_ENABLE1
>  
> +#define SNVS_LPCR0x38
> +#define BP_SNVS_LPCR_DP_EN   0x20
> +#define BP_SNVS_LPCR_TOP 0x40
> +
> +#define CCM_CCGR_SNVS0x4250
> +
>  static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
>  {
>   writel(enable, GPC_IPS_BASE_ADDR + offset);
> @@ -79,3 +85,15 @@ __secure void imx_system_reset(void)
>  {
>   writew(1 << 2, WDOG1_BASE_ADDR);
>  }
> +
> +__secure void imx_system_off(void)
> +{
> + u32 val;
> +
> + /* make sure SNVS clock is enabled */
> + writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
> +
> + val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
> + val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
> + writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
> +}
> diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S
> index 59f98cd..3d15016 100644
> --- a/arch/arm/mach-imx/mx7/psci.S
> +++ b/arch/arm/mach-imx/mx7/psci.S
> @@ -50,4 +50,11 @@ psci_system_reset:
>  2:   wfi
>   b 2b
>  
> +.globl psci_system_off
> +psci_system_off:
> + b   imx_system_off


Should this be "bl" for this and the previous patch ?


> +
> +3:   wfi
> + b 3b
> +
>   .popsection
> 

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Re: [U-Boot] [PATCH] TCP and wget implementation v4

[Joe Hershberger]

On Wed, Jan 3, 2018 at 5:01 PM, Duncan Hare  wrote:
>> >>>selects the LIB_RAND feature since it is required.
>> >
>> > Thanks: will be in u-boot/cmd/Kconfig
>> >
>> >>Are we lookin at a series of patches, or a concurrent set?
>> >
>> > At this time a series of three, but I'd take advice on the preferred
>> > procedure.
>>
>> Remember that the goal is to be atomic.
>>
>> You should be able to build and use U-Boot after each patch.
>>
>> Also, any changes to existing code that is not changing behavior but
>> simply making way for new functionality should be done separately.
>> Thanks
>> -Joe
>
> A note on this TCP implementation. In TCP the transmitting TCP
> guarantees delivery of a stream, and the receiving TCP guarantees
> ordered of delivery of the stream. In this implementation The
> kernel memory buffer and the TCP sequence number is used to order the stream.
> for the application, and the application is the kernel itself. wget is
> not considered the application, and does receive packets "out of order."

It seems like it would be possible to just store off a packet that is
ahead of its neighbor and not call any upper handler until the needed
packet arrives. Then all upper layers wouldn't need to know about the
reordering.

>
> This places a constraint on the incoming data stream. All
> (disordered) packets received before the HTTP header are
> ignored, which means the sending TCP will re-transmit them. This forced
> re-transmission could be avoided with a change to reprocess the
> incoming packet stream back to the first packet received, directly
> following processing the TCP header.
>
> This behavior was detected and failed downloads fixed in tests
> downloading Linux kernels from the cloud.
>
> Advice on the reset buffer approach are invited. It requires an
> interface between the wget application to reset the buffer index.

Between wget and what? The TCP implementation? It seems like something
that should be abstracted from wget.

>
> Joe Thanks, Good advice, based on that the order of 3 patches is:
>
> (1) Prepares the interfaces, no new behavior, CONFIG-TCP is introduced.
> net/Kconfig
> net/net.c
> net/ping.c
> include/net.h
>
> (2) Introduces TCP
> net/tcp.c
> net/tcp.h
> net/Makefile
>
> (3) Introduces wget, CONFIG-WGET introduced
> cmd/Kconfig
> cmd/net.c
> net/wget.c
> net/wget.h
>
>
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[U-Boot] [PATCH] board: i.MX6QDL: add Engicam i.CoreM6 1.5 QDL MIPI starter kit

[Jagan Teki]

i.CoreM6 1.5 is an another i.CoreM6 QDL cpu modules which can be connected
to EDIMM starter kit design with eMMC and MIPI-CSI interfaces suitable for
Android and video capture application.

notable features:
CPU NXP i.MX6 S/DL/D/Q, Up to 4 x Cortex-A9@800MHz
Memory  Up to 2 GB DDR3-1066
Video InterfacesUp to 1 Parallel Up to 2 LVDS HDMI 1.4
port 8 bit CSI INPUT MIPI-CSI INPUT
1 x 10/100 Ethernet interface, 2 x USB, 1 x PCIe, 1 x I2S etc

This patch adds support for Quad/Dual and DualLite/Solo SOM's on
MIPI starter kit with boot from SD and eMMC.

Signed-off-by: Jagan Teki 
---
 arch/arm/dts/Makefile|  2 ++
 arch/arm/dts/imx6dl-icore-mipi.dts   | 21 
 arch/arm/dts/imx6q-icore-mipi.dts| 21 
 arch/arm/dts/imx6qdl-icore.dtsi  | 28 +
 board/engicam/common/board.c |  5 
 configs/imx6qdl_icore_mipi_defconfig | 49 
 6 files changed, 126 insertions(+)
 create mode 100644 arch/arm/dts/imx6dl-icore-mipi.dts
 create mode 100644 arch/arm/dts/imx6q-icore-mipi.dts
 create mode 100644 configs/imx6qdl_icore_mipi_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a895c70..8515645 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -374,9 +374,11 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6sl-evk.dtb \
imx6sll-evk.dtb \
imx6dl-icore.dtb \
+   imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
imx6q-cm-fx6.dtb \
imx6q-icore.dtb \
+   imx6q-icore-mipi.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb \
imx6sx-sabreauto.dtb \
diff --git a/arch/arm/dts/imx6dl-icore-mipi.dts 
b/arch/arm/dts/imx6dl-icore-mipi.dts
new file mode 100644
index 000..3a444c0
--- /dev/null
+++ b/arch/arm/dts/imx6dl-icore-mipi.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Engicam S.r.l.
+ * Copyright (C) 2017 Amarula Solutions B.V.
+ * Author: Jagan Teki 
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+   model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit";
+   compatible = "engicam,imx6-icore", "fsl,imx6dl";
+};
+
+ {
+   u-boot,dm-spl;
+   status = "okay";
+};
diff --git a/arch/arm/dts/imx6q-icore-mipi.dts 
b/arch/arm/dts/imx6q-icore-mipi.dts
new file mode 100644
index 000..527f52c
--- /dev/null
+++ b/arch/arm/dts/imx6q-icore-mipi.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Engicam S.r.l.
+ * Copyright (C) 2017 Amarula Solutions B.V.
+ * Author: Jagan Teki 
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+   model = "Engicam i.CoreM6 Quad/Dual MIPI Starter Kit";
+   compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+ {
+   u-boot,dm-spl;
+   status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
index 06d9bc3..913dc99 100644
--- a/arch/arm/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -44,6 +44,10 @@
 #include 
 
 / {
+   aliases {
+   mmc1 = 
+   };
+
memory {
reg = <0x1000 0x8000>;
};
@@ -126,6 +130,14 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_usdhc3>;
+   no-1-8-v;
+   non-removable;
+   status = "disabled";
+};
+
  {
pinctrl_enet: enetgrp {
fsl,pins = <
@@ -219,4 +231,20 @@
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
>;
};
+
+   pinctrl_usdhc3: usdhc3grp {
+   u-boot,dm-spl;
+   fsl,pins = <
+   MX6QDL_PAD_SD3_CMD__SD3_CMD0x17059
+   MX6QDL_PAD_SD3_CLK__SD3_CLK0x10059
+   MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+   MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+   MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+   MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+   MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+   MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+   MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+   MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+   >;
+   };
 };
diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c
index f633c71..0160418 100644
--- a/board/engicam/common/board.c
+++ b/board/engicam/common/board.c
@@ -41,6 +41,11 @@ static void setenv_fdt_file(void)
env_set("fdt_file", "imx6q-icore.dtb");
else if(is_mx6dl() || is_mx6solo())
env_set("fdt_file", "imx6dl-icore.dtb");
+   } else if 

[U-Boot] [PATCH] config_whitelist: remove false-positive CONFIG options

[Masahiro Yamada]

U-Boot pulled in several core makefiles from Linux.  The following
are not used in U-Boot:

  - CONFIG_DEBUG_SECTION_MISMATCH
  - CONFIG_FTRACE_MCOUNT_RECORD
  - CONFIG_GCOV_KERNEL
  - CONFIG_GCOV_PROFILE_ALL
  - CONFIG_KASAN
  - CONFIG_MODVERSIONS

We can remove the unused code if we like. (although it will get the
scripts out of sync)

CONFIG_BOOM and CONFIG_HIS_DRIVER are just mentioned in the comment
block of scripts/basic/fixdep.c

CONFIG_SHELL is not configuration, but a variable for internal-use.
It is just a historical misnomer in Kbuild.

Signed-off-by: Masahiro Yamada 
---

 scripts/config_whitelist.txt | 9 -
 1 file changed, 9 deletions(-)

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 43a4ff0..2b07dee 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -154,7 +154,6 @@ CONFIG_BOARD_SIZE_LIMIT
 CONFIG_BOARD_TAURUS
 CONFIG_BOARD_TYPES
 CONFIG_BOOGER
-CONFIG_BOOM
 CONFIG_BOOTBLOCK
 CONFIG_BOOTCOUNT_ALEN
 CONFIG_BOOTCOUNT_AM33XX
@@ -387,7 +386,6 @@ CONFIG_DEBUG
 CONFIG_DEBUG_FS
 CONFIG_DEBUG_LED
 CONFIG_DEBUG_LOCK_ALLOC
-CONFIG_DEBUG_SECTION_MISMATCH
 CONFIG_DEBUG_SEMIHOSTING
 CONFIG_DEBUG_UART_LINFLEXUART
 CONFIG_DEBUG_WRITECOUNT
@@ -784,7 +782,6 @@ CONFIG_FTPMU010
 CONFIG_FTPMU010_BASE
 CONFIG_FTPMU010_POWER
 CONFIG_FTPWM010_BASE
-CONFIG_FTRACE_MCOUNT_RECORD
 CONFIG_FTRTC010_BASE
 CONFIG_FTRTC010_EXTCLK
 CONFIG_FTRTC010_PCLK
@@ -807,8 +804,6 @@ CONFIG_FTWDT010_BASE
 CONFIG_FTWDT010_WATCHDOG
 CONFIG_FZOTG266HD0A_BASE
 CONFIG_GATEWAYIP
-CONFIG_GCOV_KERNEL
-CONFIG_GCOV_PROFILE_ALL
 CONFIG_GICV2
 CONFIG_GICV3
 CONFIG_GLOBAL_DATA_NOT_REG10
@@ -851,7 +846,6 @@ CONFIG_HETROGENOUS_CLUSTERS
 CONFIG_HIDE_LOGO_VERSION
 CONFIG_HIGH_BATS
 CONFIG_HIKEY_GPIO
-CONFIG_HIS_DRIVER
 CONFIG_HITACHI_SX14
 CONFIG_HOSTNAME
 CONFIG_HOST_MAX_DEVICES
@@ -1091,7 +1085,6 @@ CONFIG_JFFS2_PART_SIZE
 CONFIG_JFFS2_SUMMARY
 CONFIG_JRSTARTR_JR0
 CONFIG_JTAG_CONSOLE
-CONFIG_KASAN
 CONFIG_KCLK_DIS
 CONFIG_KEEP_SERVERADDR
 CONFIG_KERNEL_OFFSET
@@ -1373,7 +1366,6 @@ CONFIG_MMC_SPI_SPEED
 CONFIG_MMC_SUNXI_SLOT
 CONFIG_MMC_TRACE
 CONFIG_MMU
-CONFIG_MODVERSIONS
 CONFIG_MONITOR_IS_IN_RAM
 CONFIG_MP
 CONFIG_MPC8308
@@ -1947,7 +1939,6 @@ CONFIG_SHARP_LM8V31
 CONFIG_SHARP_LQ035Q7DH06
 CONFIG_SHEEVA_88SV131
 CONFIG_SHEEVA_88SV331xV5
-CONFIG_SHELL
 CONFIG_SHMIN
 CONFIG_SHOW_ACTIVITY
 CONFIG_SHOW_BOOT_PROGRESS
-- 
2.7.4

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Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

[Marek Vasut]

On 01/05/2018 04:49 PM, Goldschmidt Simon wrote:
> + Marek (as Jagan wants an ack)
> 
> On 05/01/2018 Jagan Teki wrote:
>> On Fri, Jan 5, 2018 at 5:32 PM, Goldschmidt Simon wrote:
>>> + Vignesh
>>> + Jason
>>>
>>> On Wed, 03/01/2018 16:57, Goldschmidt Simon wrote:
 On Wed, 03/01/2018 14:51, Jagan Teki wrote:
>> There were already patches posted on this list by me and others, but
>> unfortunately they haven't made it into the repository, yet.
>>
>> Jagan, could you comment on the status of these fixes? I can search
>> for the patchwork items related if you want me to.
>
> 2 out of 1 of this[1] have some discussion still going is it?
>
> [1] https://patchwork.ozlabs.org/patch/838195/

 No, that series should be dropped. I don't know if I can do anything about 
 that in
 patchwork though?

 Let me check the patches from my upstreaming queue when I'm back at work
 tomorrow. I'll send a list of patchwork items I needed to get QSPI running 
 on
> <>> mach-socfpga.
>>>
>>> OK, so I need these patches to get qspi work on socfpga:
>>>
>>> - Series "spi: cadence_spi: Adopt Linux DT bindings" (v4) from Jason Rush:
>>>   https://patchwork.ozlabs.org/project/uboot/list/?series=13864
>>> - Patch "Revert "spi: cadence_qspi_apb: Use 32 bit indirect read 
>>> transaction when possible" (v2)
>>>   https://patchwork.ozlabs.org/patch/838871/
>>
>> I've waited for ack/tested-by from marek or someone who usually worked
>> on these cadence.
> 
> Vignesh acked, who already did some of the last changes. But Ok, I've
> added Marek to the loop.
> 
> Marek, do you see any problems here? Are you running QSPI on the
> socfpga platform anywhere?
I am not entirely sure what this partial thread is all about, do you
need some patches Acked ? Repost them including the Acks collected
already and CC me, I want to review them. PW link is not enough.

-- 
Best regards,
Marek Vasut
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[U-Boot] exFAT support in u-boot

[Arun Kuttiyara Varghese]

Hi All,

As per my understanding, u-boot doesn't support exFAT.
[ based on https://lists.denx.de/pipermail/u-boot/2012-March/119300.html ]

Just want to know, is there is a way to add exFAT support to u-boot ?
[ May be a similar way as exFAT support in Linux [
https://github.com/relan/exfat] ]

The reason to use exFAT in u-boot is to use the same SD card for
- data storage in multiple platforms
- use the same SD card as a bootable one [ with out formatting ].

Please let me know.

Thanks,
Arun
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Re: [U-Boot] [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction

[York Sun]

On 01/05/2018 08:22 AM, Sumit Garg wrote:
>> -Original Message-
>> From: York Sun
>> Sent: Friday, January 05, 2018 9:40 PM
>> To: Sumit Garg ; u-boot@lists.denx.de
>> Cc: Prabhakar Kushwaha ; Ruchika Gupta
>> 
>> Subject: Re: [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction
>>
>> On 01/05/2018 08:07 AM, Sumit Garg wrote:
>>
>> 
>>

 Sumit,

 PPA has been fixed to not claim OCRAM. Please rework your patch.

 York
>>>
>>> York,
>>>
>>> I have just sent reworked patches without removing dcache cache code.
>>> It's been working only with toolchain above GCC 6 that reduces SPL size.
>>
>> Thanks.
>> What do you mean "working only with toolchain above GCC 6"? Do you mean
>> the size would be too large using older toolchain?
>>
>> York
> 
> Yes for LSDK, tool-chain being used is GCC 5.4.1. Following is analysis with 
> LSDK too-chain:
> 
> SPL size for Secure boot image without dcache code:   83K
> Available max OCRAM memory size for SPL image:84K
> SPL size for Secure boot image with dcache code:  85K
> 
> So for LSDK we have remove dcache code for Secure boot to work with current 
> SPL size reduction.

If you are out of space for LSDK, go ahead to remove the dcache code.
For upstream U-Boot, I want to keep those code for falcon boot. We are
going with GCC 6 anyway.

York
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Re: [U-Boot] [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction

[Sumit Garg]

> -Original Message-
> From: York Sun
> Sent: Friday, January 05, 2018 9:40 PM
> To: Sumit Garg ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Ruchika Gupta
> 
> Subject: Re: [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction
> 
> On 01/05/2018 08:07 AM, Sumit Garg wrote:
> 
> 
> 
> >>
> >> Sumit,
> >>
> >> PPA has been fixed to not claim OCRAM. Please rework your patch.
> >>
> >> York
> >
> > York,
> >
> > I have just sent reworked patches without removing dcache cache code.
> > It's been working only with toolchain above GCC 6 that reduces SPL size.
> 
> Thanks.
> What do you mean "working only with toolchain above GCC 6"? Do you mean
> the size would be too large using older toolchain?
> 
> York

Yes for LSDK, tool-chain being used is GCC 5.4.1. Following is analysis with 
LSDK too-chain:

SPL size for Secure boot image without dcache code: 83K
Available max OCRAM memory size for SPL image:  84K
SPL size for Secure boot image with dcache code:85K

So for LSDK we have remove dcache code for Secure boot to work with current SPL 
size reduction.

-Sumit
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[U-Boot] [[PATCH v2] 7/8] sunxi: usb_phy: setup USB PHY passby for USB0 on H3/H5/A64

[Jun Nie]

From: Chen-Yu Tsai 

On newer chips, there is a pair of EHCI/OHCI USB hosts for OTG host
mode. USB PHY passby must be configured for its corresponding PHY.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/mach-sunxi/usb_phy.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index bcf5f15..4ae0a77 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -245,7 +245,12 @@ void sunxi_usb_phy_init(int index)
 
sunxi_usb_phy_config(phy);
 
-   if (phy->id != 0)
+   /*
+* Later SoCs such as the H3, H5, A64 have proper hosts for OTG.
+* As such the passby settings need to be set for them as well.
+*/
+   if (phy->id != 0 || IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5) ||
+   IS_ENABLED(CONFIG_MACH_SUN50I))
sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
 
 #ifdef CONFIG_MACH_SUN8I_A83T
-- 
1.9.1

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[U-Boot] [[PATCH v2] 8/8] sunxi: H3: set different otg base address per mode

[Jun Nie]

Set different base address per host mode or peripheral mode. Phy
configuration also depends on this address.

Signed-off-by: Jun Nie 
---
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 2419062..f45f53a 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -64,7 +64,11 @@
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 #define SUNXI_USBPHY_BASE  0x01c19000
+#ifdef CONFIG_USB_MUSB_GADGET
+#define SUNXI_USB0_BASE0x01c19000
+#else
 #define SUNXI_USB0_BASE0x01c1a000
+#endif
 #define SUNXI_USB1_BASE0x01c1b000
 #define SUNXI_USB2_BASE0x01c1c000
 #define SUNXI_USB3_BASE0x01c1d000
-- 
1.9.1

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[U-Boot] [[PATCH v2] 6/8] sunxi: usb_phy: Clear PHYCTL register before writing

[Jun Nie]

PHYCTL register offset at 0x10 need to be cleared before it's
written. Ported from below Linux patch.
  d699c1d phy: sun4i-usb: change PHYCTL register clearing code

Signed-off-by: Jun Nie 
---
 arch/arm/mach-sunxi/usb_phy.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index 2f1cad1..bcf5f15 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -156,9 +156,15 @@ __maybe_unused static void usb_phy_write(struct 
sunxi_usb_phy *phy, int addr,
 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 {
 #if defined CONFIG_MACH_SUNXI_H3_H5
-   if (phy->id == 0)
+   if (phy->id == 0) {
+#ifdef CONFIG_USB_MUSB_GADGET
+   setbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
+   writel(0, SUNXI_USB0_BASE + SUNXI_USB_CSR);
+#else
clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
 #endif
+   }
+#endif
clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
 }
 #elif defined CONFIG_MACH_SUN8I_A83T
-- 
1.9.1

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[U-Boot] [[PATCH v2] 4/8] sunxi: musb: Hack dynamic fifo support for H3 OTG

[Jun Nie]

Like other Allwinner SoC, the H3 is missing the config register
from the musb hardware block. Use a known working value for it
like other SoC.

Signed-off-by: Jun Nie 
---
 drivers/usb/musb-new/musb_regs.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h
index a3cc38e..8a357ed 100644
--- a/drivers/usb/musb-new/musb_regs.h
+++ b/drivers/usb/musb-new/musb_regs.h
@@ -432,7 +432,8 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem 
*mbase)
 
 static inline u8 musb_read_configdata(void __iomem *mbase)
 {
-#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T
+#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_A83T) || \
+   defined(CONFIG_MACH_SUNXI_H3_H5)
/*  allwinner saves a reg, and we need to hardcode this */
return 0xde;
 #else
-- 
1.9.1

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[U-Boot] [[PATCH v2] 5/8] sunxi: musb: Enable OTG device clock for H3

[Jun Nie]

Enable OTG clock and deassert reset

Signed-off-by: Jun Nie 
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 +
 drivers/usb/musb-new/sunxi.c  | 6 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 2c82d0a..624d624 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -279,6 +279,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI2  26
 #define AHB_GATE_OFFSET_USB_EHCI1  25
 #define AHB_GATE_OFFSET_USB_EHCI0  24
+#define AHB_GATE_OFFSET_OTG_DEVICE 23
 #else
 #define AHB_GATE_OFFSET_USB_OHCI1  30
 #define AHB_GATE_OFFSET_USB_OHCI0  29
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 0005c1e..ce7365b 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -264,7 +264,10 @@ static int sunxi_musb_init(struct musb *musb)
 
setbits_le32(>ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-   setbits_le32(>ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+   setbits_le32(>ahb_gate0, BIT(AHB_GATE_OFFSET_OTG_DEVICE));
+   setbits_le32(>ahb_reset0_cfg,
+BIT(AHB_GATE_OFFSET_USB0) |
+BIT(AHB_GATE_OFFSET_OTG_DEVICE));
 #endif
sunxi_usb_phy_init(0);
 
@@ -376,6 +379,7 @@ static int musb_usb_remove(struct udevice *dev)
sunxi_usb_phy_exit(0);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
clrbits_le32(>ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+   clrbits_le32(>ahb_gate0, 1 << AHB_GATE_OFFSET_OTG_DEVICE);
 #endif
clrbits_le32(>ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
 
-- 
1.9.1

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[U-Boot] [[PATCH v2] 2/8] sunxi: musb: Add fifo config for H3

[Jun Nie]

Add fifo config for H3 as H3 differ with other SoC
on ep number.

Signed-off-by: Jun Nie 
Reviewed-by: Jagan Teki 
---
 drivers/usb/musb-new/sunxi.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 7ee44ea..0005c1e 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -290,10 +290,42 @@ static const struct musb_platform_ops sunxi_musb_ops = {
.disable= sunxi_musb_disable,
 };
 
+#if defined(CONFIG_MACH_SUN8I_H3)
+static struct musb_fifo_cfg sunxi_musb_fifo_config[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
+   { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
+   { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
+   { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
+   { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
+   { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
+   { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
+   { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
+};
+#else
+static struct musb_fifo_cfg sunxi_musb_fifo_config[] = {
+   { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
+   { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
+   { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
+   { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
+   { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
+   { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
+   { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
+   { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
+   { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
+   { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
+};
+#endif
+
 static struct musb_hdrc_config musb_config = {
+   .fifo_cfg   = sunxi_musb_fifo_config,
+   .fifo_cfg_size  = ARRAY_SIZE(sunxi_musb_fifo_config),
.multipoint = 1,
.dyn_fifo   = 1,
+#if defined(CONFIG_MACH_SUN8I_H3)
.num_eps= 6,
+#else
+   .num_eps= 5,
+#endif
.ram_bits   = 11,
 };
 
-- 
1.9.1

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[U-Boot] [[PATCH v2] 1/8] sunxi: h3: Sync OTG and HCI nodes from Linux DT

[Jun Nie]

Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
or MUSB controller.

Signed-off-by: Jun Nie 
---
 arch/arm/dts/sun8i-h3.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index afa6079..d9728a7 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -218,6 +218,19 @@
#size-cells = <0>;
};
 
+   usb_otg: usb@1c19000 {
+   compatible = "allwinner,sun8i-h3-musb";
+   reg = <0x01c19000 0x400>;
+   clocks = < CLK_BUS_OTG>;
+   resets = < RST_BUS_OTG>;
+   interrupts = ;
+   interrupt-names = "mc";
+   phys = < 0>;
+   phy-names = "usb";
+   extcon = < 0>;
+   status = "disabled";
+   };
+
usbphy: phy@01c19400 {
compatible = "allwinner,sun8i-h3-usb-phy";
reg = <0x01c19400 0x2c>,
@@ -250,6 +263,25 @@
#phy-cells = <1>;
};
 
+   ehci0: usb@1c1a000 {
+   compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+   reg = <0x01c1a000 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_EHCI0>, < CLK_BUS_OHCI0>;
+   resets = < RST_BUS_EHCI0>, < RST_BUS_OHCI0>;
+   status = "disabled";
+   };
+
+   ohci0: usb@1c1a400 {
+   compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+   reg = <0x01c1a400 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_EHCI0>, < CLK_BUS_OHCI0>,
+< CLK_USB_OHCI0>;
+   resets = < RST_BUS_EHCI0>, < RST_BUS_OHCI0>;
+   status = "disabled";
+   };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
-- 
1.9.1

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[U-Boot] [[PATCH v2] 3/8] sunxi: Fix USB PHY index for H3/H5/A64

[Jun Nie]

From: Chen-Yu Tsai 

On the new chips such as H3, H5, and A64, the USB OTG controller is
paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts,
the USB PHY index count has to be reworked to start from this pair.

This patch reworks the USB clock gate and reset indices, and how the
USB host is mapped to a USB phy, for the newer chips.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 30 +--
 drivers/usb/host/ehci-sunxi.c |  9 +++-
 drivers/usb/host/ohci-sunxi.c |  9 +++-
 3 files changed, 30 insertions(+), 18 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d328df9..2c82d0a 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -270,17 +270,18 @@ struct sunxi_ccm_reg {
 #define AXI_GATE_OFFSET_DRAM   0
 
 /* ahb_gate0 offsets */
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#define AHB_GATE_OFFSET_USB_OHCI3  31
+#define AHB_GATE_OFFSET_USB_OHCI2  30
+#define AHB_GATE_OFFSET_USB_OHCI1  29
+#define AHB_GATE_OFFSET_USB_OHCI0  28
+#define AHB_GATE_OFFSET_USB_EHCI3  27
+#define AHB_GATE_OFFSET_USB_EHCI2  26
+#define AHB_GATE_OFFSET_USB_EHCI1  25
+#define AHB_GATE_OFFSET_USB_EHCI0  24
+#else
 #define AHB_GATE_OFFSET_USB_OHCI1  30
 #define AHB_GATE_OFFSET_USB_OHCI0  29
-#ifdef CONFIG_MACH_SUNXI_H3_H5
-/*
- * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
- * them 0 - 2 like they were called on older SoCs.
- */
-#define AHB_GATE_OFFSET_USB_EHCI2  27
-#define AHB_GATE_OFFSET_USB_EHCI1  26
-#define AHB_GATE_OFFSET_USB_EHCI0  25
-#else
 #define AHB_GATE_OFFSET_USB_EHCI1  27
 #define AHB_GATE_OFFSET_USB_EHCI0  26
 #endif
@@ -339,13 +340,10 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
 #ifdef CONFIG_MACH_SUNXI_H3_H5
-/*
- * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
- * them 0 - 2 like they were called on older SoCs.
- */
-#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
-#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
-#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
 #else
 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 6ecb7c4..f40228e 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -48,10 +48,17 @@ static int ehci_usb_probe(struct udevice *dev)
 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
 #endif
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+   /* Newer chips have a EHCI/OHCI host pair for OTG host mode */
+   priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST;
+#else
priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
+#endif
priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
-   priv->phy_index++; /* Non otg phys start at 1 */
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
+   priv->phy_index++; /* older chips do not have EHCI with OTG */
+#endif
 
setbits_le32(>ahb_gate0,
 priv->ahb_gate_mask | extra_ahb_gate_mask);
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index 133774f..4b8a403 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -51,11 +51,18 @@ static int ohci_usb_probe(struct udevice *dev)
extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+   /* Newer chips have a EHCI/OHCI host pair for OTG host mode */
+   priv->phy_index = ((uintptr_t)regs - (SUNXI_USB0_BASE + 0x400)) / 
BASE_DIST;
+#else
priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / 
BASE_DIST;
+#endif
priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
priv->usb_gate_mask <<= priv->phy_index;
-   priv->phy_index++; /* Non otg phys start at 1 */
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
+   priv->phy_index++; /* older chips do not have OHCI with OTG */
+#endif
 
setbits_le32(>ahb_gate0,
 priv->ahb_gate_mask | extra_ahb_gate_mask);
-- 
1.9.1

___

[U-Boot] [[PATCH v2] 0/8] sunxi: Enable OTG peripheral and host mode on H3

[Jun Nie]

Changes vs V1:
- Add two patches from Chen-Yu to enable host mode
- split USB0 base address change to separate patch
- revise OTG clock enabling patch

Chen-Yu Tsai (2):
  sunxi: Fix USB PHY index for H3/H5/A64
  sunxi: usb_phy: setup USB PHY passby for USB0 on H3/H5/A64

Jun Nie (6):
  sunxi: h3: Sync OTG and HCI nodes from Linux DT
  sunxi: musb: Add fifo config for H3
  sunxi: musb: Hack dynamic fifo support for H3 OTG
  sunxi: musb: Enable OTG device clock for H3
  sunxi: usb_phy: Clear PHYCTL register before writing
  sunxi: H3: set different otg base address per mode

 arch/arm/dts/sun8i-h3.dtsi| 32 ++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 31 +++---
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h   |  4 +++
 arch/arm/mach-sunxi/usb_phy.c | 15 +--
 drivers/usb/host/ehci-sunxi.c |  9 ++-
 drivers/usb/host/ohci-sunxi.c |  9 ++-
 drivers/usb/musb-new/musb_regs.h  |  3 ++-
 drivers/usb/musb-new/sunxi.c  | 38 ++-
 8 files changed, 119 insertions(+), 22 deletions(-)

-- 
1.9.1

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Re: [U-Boot] [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction

[York Sun]

On 01/05/2018 08:07 AM, Sumit Garg wrote:



>>
>> Sumit,
>>
>> PPA has been fixed to not claim OCRAM. Please rework your patch.
>>
>> York
>  
> York,
> 
> I have just sent reworked patches without removing dcache cache code. It's 
> been working
> only with toolchain above GCC 6 that reduces SPL size.

Thanks.
What do you mean "working only with toolchain above GCC 6"? Do you mean
the size would be too large using older toolchain?

York
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Re: [U-Boot] [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction

[Sumit Garg]

> -Original Message-
> From: York Sun
> Sent: Friday, January 05, 2018 9:26 PM
> To: Sumit Garg ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Ruchika Gupta
> 
> Subject: Re: [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction
> 
> On 08/30/2017 01:53 AM, Sumit Garg wrote:
> > < snip >
> >
>  On 08/29/2017 12:02 AM, Sumit Garg wrote:
> > Using changes in this patch we were able to reduce approx 8k size
> > of u-boot-spl.bin image. Following is breif description of changes
> > to reduce SPL size:
> > 1. Changes in board/freescale/ls1088a/Makefile to remove
> >  compilation of eth.c and cpld.c in case of SPL build.
> > 2. Changes in board/freescale/ls1088a/ls1088a.c to keep
> >  board_early_init_f funcations in case of SPL build.
> > 3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver
> >  specific macros due to which static data was being compiled in
> >  case of SPL build.
> > 4. Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is
> >  not being enabled in case of SPL image but was compiled in to
> >  add redundant code.
> >
> > Signed-off-by: Sumit Garg 
> > ---
> >
> > Dependent on ls1088 base SD boot target. Also dependent on ls1088
> > QPSI secure boot target.
> >
> >board/freescale/ls1088a/Makefile  |  4 +++-
> >board/freescale/ls1088a/ls1088a.c | 14 --
> >include/configs/ls1088a_common.h  | 20 
> >include/configs/ls1088ardb.h  | 20 
> >4 files changed, 51 insertions(+), 7 deletions(-)
> >
> > diff --git a/board/freescale/ls1088a/Makefile
> > b/board/freescale/ls1088a/Makefile
> > index bdcce9e..0e15031 100644
> > --- a/board/freescale/ls1088a/Makefile
> > +++ b/board/freescale/ls1088a/Makefile
> > @@ -5,6 +5,8 @@
> >#
> >
> >obj-y += ls1088a.o
> > +obj-y += ddr.o
> > +ifndef CONFIG_SPL_BUILD
> >obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
> >obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y +=
> > ddr.o
> > +endif
> > diff --git a/board/freescale/ls1088a/ls1088a.c
> > b/board/freescale/ls1088a/ls1088a.c
> > index 1860f9c..1c28ab4 100644
> > --- a/board/freescale/ls1088a/ls1088a.c
> > +++ b/board/freescale/ls1088a/ls1088a.c
> > @@ -24,6 +24,13 @@
> >
> >DECLARE_GLOBAL_DATA_PTR;
> >
> > +int board_early_init_f(void)
> > +{
> > +   fsl_lsch3_early_init_f();
> > +   return 0;
> > +}
> > +
> > +#if !defined(CONFIG_SPL_BUILD)
> >unsigned long long get_qixis_addr(void)
> >{
> > unsigned long long addr;
> > @@ -324,12 +331,6 @@ int board_init(void)
> > return 0;
> >}
> >
> > -int board_early_init_f(void)
> > -{
> > -   fsl_lsch3_early_init_f();
> > -   return 0;
> > -}
> > -
> >void detail_board_ddr_info(void)
> >{
> > puts("\nDDR");
> > @@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd)
> > return 0;
> >}
> >#endif
> > +#endif /* defined(CONFIG_SPL_BUILD) */
> > diff --git a/include/configs/ls1088a_common.h
> > b/include/configs/ls1088a_common.h
> > index 63b69f8..fb4c852 100644
> > --- a/include/configs/ls1088a_common.h
> > +++ b/include/configs/ls1088a_common.h
> > @@ -7,6 +7,20 @@
> >#ifndef __LS1088_COMMON_H
> >#define __LS1088_COMMON_H
> >
> > +/* SPL build */
> > +#ifdef CONFIG_SPL_BUILD
> > +#define SPL_NO_BOARDINFO
> > +#define SPL_NO_QIXIS
> > +#define SPL_NO_PCI
> > +#define SPL_NO_ENV
> > +#define SPL_NO_RTC
> > +#define SPL_NO_USB
> > +#define SPL_NO_SATA
> > +#define SPL_NO_QSPI
> > +#define SPL_NO_IFC
> > +#define CONFIG_SYS_DCACHE_OFF
> 
>  How much space can you save with data cache off? I prefer to leave
>  the cache on. Cache is used if PPA is loaded in SPL stage for boost
>  booting
> >> speed.
> 
>  York
> >>>
> >>> As we discussed earlier too, dcache was not enabled in SPL for our
> >>> layerscape
> >> platforms.
> >>
> >> That was a mistake when SPL targets were added. It should be enabled.
> >> As I said, if you load PPA in SPL, cache will be enabled for EL2. You
> >> didn't do it because booting performance is not a concern. If you
> >> enable falcon boot, this is required.
> >
> > Ok. BTW, do you think latest PPA which claims whole of OCRAM could work
> with SPL.
> > I saw crashes in SPL on ls1043ardb with latest PPA enabled in SPL upstream 
> > u-
> boot.
> 
> Sumit,
> 
> PPA has been fixed to not claim OCRAM. Please rework your patch.
> 
> York
 
York,

I have just sent reworked patches without 

Re: [U-Boot] [PATCH v2] crypto/fsl: fix BLOB encapsulation and decapsulation

[York Sun]

On 01/05/2018 05:02 AM, Clemens Gruber wrote:



> 
> York: Should I send a v3 or a fixup patch ontop of v2.

I have reset my git head. Please send v3 patch.

York

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Re: [U-Boot] Please pull u-boot-fsl-qoriq master

[York Sun]

Tom,

Please abort this PR. More review comments came in last night.

(Somehow I sent to wrong address anyway.)

York

On 01/04/2018 05:19 PM, York Sun wrote:
> Tom,
> 
> The following changes since commit ca833ca9579b29c5667ea2fa7a9d3f89f1599a94:
> 
>   Merge git://git.denx.de/u-boot-rockchip (2018-01-03 12:27:12 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-fsl-qoriq.git
> 
> for you to fetch changes up to 2080e50dd38723a50c84715b88c3493b853893ec:
> 
>   crypto/fsl: fix BLOB encapsulation and decapsulation (2018-01-04
> 17:16:56 -0800)
> 
> 
> Clemens Gruber (1):
>   crypto/fsl: fix BLOB encapsulation and decapsulation
> 
>  drivers/crypto/fsl/fsl_blob.c | 99
> ---
>  include/fsl_sec.h |  4 +-
>  2 files changed, 85 insertions(+), 18 deletions(-)
> 
> Thanks.
> 
> York
> 

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[U-Boot] [PATCH v2 3/3] ls1088ardb: Add SD Secure boot target support

[Sumit Garg]

Signed-off-by: Udit Agarwal 
Signed-off-by: Sumit Garg 
---

Changes in v2:
Rebased to top of master

 arch/arm/include/asm/fsl_secure_boot.h | 16 
 board/freescale/ls1088a/MAINTAINERS|  5 +++
 .../ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig   | 45 ++
 include/configs/ls1088a_common.h   | 15 +++-
 4 files changed, 72 insertions(+), 9 deletions(-)
 create mode 100644 configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig

diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index ec6463d..3f30470 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -26,6 +26,14 @@
 
 #define CONFIG_KEY_REVOCATION
 
+#if defined(CONFIG_FSL_LAYERSCAPE)
+/*
+ * For fsl layerscape based platforms, ESBC image Address in Header
+ * is 64 bit.
+ */
+#define CONFIG_ESBC_ADDR_64BIT
+#endif
+
 #ifndef CONFIG_SPL_BUILD
 #ifndef CONFIG_SYS_RAMBOOT
 /* The key used for verification of next level images
@@ -42,14 +50,6 @@
 
 #endif
 
-#if defined(CONFIG_FSL_LAYERSCAPE)
-/*
- * For fsl layerscape based platforms, ESBC image Address in Header
- * is 64 bit.
- */
-#define CONFIG_ESBC_ADDR_64BIT
-#endif
-
 #ifdef CONFIG_ARCH_LS2080A
 #define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xa000;"   \
diff --git a/board/freescale/ls1088a/MAINTAINERS 
b/board/freescale/ls1088a/MAINTAINERS
index de3961d..371e5db 100644
--- a/board/freescale/ls1088a/MAINTAINERS
+++ b/board/freescale/ls1088a/MAINTAINERS
@@ -27,3 +27,8 @@ M:Udit Agarwal 
 M: Vinitha Pillai-B57223 
 S: Maintained
 F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+
+LS1088ARDB_SD_SECURE_BOOT BOARD
+M: Sumit Garg 
+S: Maintained
+F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig 
b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
new file mode 100644
index 000..ba90e64
--- /dev/null
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -0,0 +1,45 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
+CONFIG_SECURE_BOOT=y
+CONFIG_SD_BOOT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_SPL_CRYPTO_SUPPORT=y
+CONFIG_SPL_HASH_SUPPORT=y
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 13b5e8b..e684884 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -254,7 +254,20 @@ unsigned long long get_qixis_addr(void);
 
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
 #define CONFIG_SYS_SPL_MALLOC_START0x8020
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN (0x10 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN 0x10
+#endif /* ifdef CONFIG_SECURE_BOOT */
+
 #endif
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
-- 
1.9.1

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[U-Boot] [PATCH v2 2/3] armv8: ls1088a: SPL size reduction

[Sumit Garg]

Using changes in this patch we were able to reduce approx 8k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1088a/Makefile to remove
   compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1088a/ls1088a.c to keep
   board_early_init_f funcations in case of SPL build.
3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver
   specific macros due to which static data was being compiled in
   case of SPL build.

Signed-off-by: Sumit Garg 
---

Changes in v2:
Removed code specific to D-Cache off. With GCC 6.2 tool-chain, able
to reduce size to 79K.

 board/freescale/ls1088a/Makefile  |  4 +++-
 board/freescale/ls1088a/ls1088a.c | 16 ++--
 include/configs/ls1088a_common.h  | 19 +++
 include/configs/ls1088ardb.h  | 20 
 4 files changed, 52 insertions(+), 7 deletions(-)

diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile
index bdcce9e..0e15031 100644
--- a/board/freescale/ls1088a/Makefile
+++ b/board/freescale/ls1088a/Makefile
@@ -5,6 +5,8 @@
 #
 
 obj-y += ls1088a.o
+obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
 obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
-obj-y += ddr.o
+endif
diff --git a/board/freescale/ls1088a/ls1088a.c 
b/board/freescale/ls1088a/ls1088a.c
index 96f183e..d12bcae 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -25,6 +25,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int board_early_init_f(void)
+{
+   fsl_lsch3_early_init_f();
+   return 0;
+}
+
+#ifdef CONFIG_FSL_QIXIS
 unsigned long long get_qixis_addr(void)
 {
unsigned long long addr;
@@ -42,7 +49,9 @@ unsigned long long get_qixis_addr(void)
 
return addr;
 }
+#endif
 
+#if !defined(CONFIG_SPL_BUILD)
 int checkboard(void)
 {
char buf[64];
@@ -342,12 +351,6 @@ int board_init(void)
return 0;
 }
 
-int board_early_init_f(void)
-{
-   fsl_lsch3_early_init_f();
-   return 0;
-}
-
 void detail_board_ddr_info(void)
 {
puts("\nDDR");
@@ -451,3 +454,4 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
 }
 #endif
+#endif /* defined(CONFIG_SPL_BUILD) */
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 6587296..13b5e8b 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -7,6 +7,19 @@
 #ifndef __LS1088_COMMON_H
 #define __LS1088_COMMON_H
 
+/* SPL build */
+#ifdef CONFIG_SPL_BUILD
+#define SPL_NO_BOARDINFO
+#define SPL_NO_QIXIS
+#define SPL_NO_PCI
+#define SPL_NO_ENV
+#define SPL_NO_RTC
+#define SPL_NO_USB
+#define SPL_NO_SATA
+#define SPL_NO_QSPI
+#define SPL_NO_IFC
+#undef CONFIG_DISPLAY_CPUINFO
+#endif
 
 #define CONFIG_REMAKE_ELF
 #define CONFIG_FSL_LAYERSCAPE
@@ -74,8 +87,10 @@
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 
+#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
 /* IFC */
 #define CONFIG_FSL_IFC
+#endif
 
 /*
  * During booting, IFC is mapped at the region of 0x3000.
@@ -172,6 +187,7 @@ unsigned long long get_qixis_addr(void);
 
 /* #define CONFIG_DISPLAY_CPUINFO */
 
+#ifndef SPL_NO_ENV
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
@@ -211,6 +227,7 @@ unsigned long long get_qixis_addr(void);
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
 #endif
+#endif
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE  512 /* Console I/O Buffer Size */
@@ -219,7 +236,9 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
+#ifndef SPL_NO_ENV
 #define CONFIG_CMDLINE_EDITING 1
+#endif
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS 64  /* max command args */
 
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 1438bec..3c6c666 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -9,7 +9,9 @@
 
 #include "ls1088a_common.h"
 
+#ifndef SPL_NO_BOARDINFO
 #define CONFIG_DISPLAY_BOARDINFO_LATE
+#endif
 
 #define CONFIG_MISC_INIT_R
 
@@ -29,7 +31,9 @@
 #endif
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_QIXIS_I2C_ACCESS
+#endif
 #define SYS_NO_FLASH
 #undef CONFIG_CMD_IMLS
 #endif
@@ -97,7 +101,11 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST{ CONFIG_SYS_FLASH_BASE }
 #endif
 #endif
+
+#ifndef SPL_NO_IFC
 #define CONFIG_NAND_FSL_IFC
+#endif
+
 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
 #define CONFIG_SYS_NAND_MAX_OOBFREE2
 
@@ -139,7 +147,10 @@
 
 #define 

[U-Boot] [PATCH v2 1/3] armv8: fsl-layerscape: SPL size reduction

[Sumit Garg]

Compile-off mp.c and libfdt.c in case of SPL build. SPL size reduces
by approx 2k.

Signed-off-by: Sumit Garg 
---

Changes in v2:
Removed code specific to D-Cache off. With GCC 6.2 tool-chain, able
to reduce size to 79K.

 arch/arm/cpu/armv8/fsl-layerscape/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 115c3fc..0cb6d4e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,8 +7,10 @@
 obj-y += cpu.o
 obj-y += lowlevel.o
 obj-y += soc.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
+endif
 obj-$(CONFIG_SPL) += spl.o
 obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
 
-- 
1.9.1

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Re: [U-Boot] [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction

[York Sun]

On 08/30/2017 01:53 AM, Sumit Garg wrote:
> < snip >
> 
 On 08/29/2017 12:02 AM, Sumit Garg wrote:
> Using changes in this patch we were able to reduce approx 8k size of
> u-boot-spl.bin image. Following is breif description of changes to
> reduce SPL size:
> 1. Changes in board/freescale/ls1088a/Makefile to remove
>  compilation of eth.c and cpld.c in case of SPL build.
> 2. Changes in board/freescale/ls1088a/ls1088a.c to keep
>  board_early_init_f funcations in case of SPL build.
> 3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver
>  specific macros due to which static data was being compiled in
>  case of SPL build.
> 4. Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is
>  not being enabled in case of SPL image but was compiled in to
>  add redundant code.
>
> Signed-off-by: Sumit Garg 
> ---
>
> Dependent on ls1088 base SD boot target. Also dependent on ls1088
> QPSI secure boot target.
>
>board/freescale/ls1088a/Makefile  |  4 +++-
>board/freescale/ls1088a/ls1088a.c | 14 --
>include/configs/ls1088a_common.h  | 20 
>include/configs/ls1088ardb.h  | 20 
>4 files changed, 51 insertions(+), 7 deletions(-)
>
> diff --git a/board/freescale/ls1088a/Makefile
> b/board/freescale/ls1088a/Makefile
> index bdcce9e..0e15031 100644
> --- a/board/freescale/ls1088a/Makefile
> +++ b/board/freescale/ls1088a/Makefile
> @@ -5,6 +5,8 @@
>#
>
>obj-y += ls1088a.o
> +obj-y += ddr.o
> +ifndef CONFIG_SPL_BUILD
>obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
>obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y +=
> ddr.o
> +endif
> diff --git a/board/freescale/ls1088a/ls1088a.c
> b/board/freescale/ls1088a/ls1088a.c
> index 1860f9c..1c28ab4 100644
> --- a/board/freescale/ls1088a/ls1088a.c
> +++ b/board/freescale/ls1088a/ls1088a.c
> @@ -24,6 +24,13 @@
>
>DECLARE_GLOBAL_DATA_PTR;
>
> +int board_early_init_f(void)
> +{
> + fsl_lsch3_early_init_f();
> + return 0;
> +}
> +
> +#if !defined(CONFIG_SPL_BUILD)
>unsigned long long get_qixis_addr(void)
>{
>   unsigned long long addr;
> @@ -324,12 +331,6 @@ int board_init(void)
>   return 0;
>}
>
> -int board_early_init_f(void)
> -{
> - fsl_lsch3_early_init_f();
> - return 0;
> -}
> -
>void detail_board_ddr_info(void)
>{
>   puts("\nDDR");
> @@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd)
>   return 0;
>}
>#endif
> +#endif /* defined(CONFIG_SPL_BUILD) */
> diff --git a/include/configs/ls1088a_common.h
> b/include/configs/ls1088a_common.h
> index 63b69f8..fb4c852 100644
> --- a/include/configs/ls1088a_common.h
> +++ b/include/configs/ls1088a_common.h
> @@ -7,6 +7,20 @@
>#ifndef __LS1088_COMMON_H
>#define __LS1088_COMMON_H
>
> +/* SPL build */
> +#ifdef CONFIG_SPL_BUILD
> +#define SPL_NO_BOARDINFO
> +#define SPL_NO_QIXIS
> +#define SPL_NO_PCI
> +#define SPL_NO_ENV
> +#define SPL_NO_RTC
> +#define SPL_NO_USB
> +#define SPL_NO_SATA
> +#define SPL_NO_QSPI
> +#define SPL_NO_IFC
> +#define CONFIG_SYS_DCACHE_OFF

 How much space can you save with data cache off? I prefer to leave
 the cache on. Cache is used if PPA is loaded in SPL stage for boost booting
>> speed.

 York
>>>
>>> As we discussed earlier too, dcache was not enabled in SPL for our 
>>> layerscape
>> platforms.
>>
>> That was a mistake when SPL targets were added. It should be enabled.
>> As I said, if you load PPA in SPL, cache will be enabled for EL2. You didn't 
>> do it
>> because booting performance is not a concern. If you enable falcon boot, 
>> this is
>> required.
>  
> Ok. BTW, do you think latest PPA which claims whole of OCRAM could work with 
> SPL.
> I saw crashes in SPL on ls1043ardb with latest PPA enabled in SPL upstream 
> u-boot.

Sumit,

PPA has been fixed to not claim OCRAM. Please rework your patch.

York
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Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

[Goldschmidt Simon]

+ Marek (as Jagan wants an ack)

On 05/01/2018 Jagan Teki wrote:
> On Fri, Jan 5, 2018 at 5:32 PM, Goldschmidt Simon wrote:
>> + Vignesh
>> + Jason
>>
>> On Wed, 03/01/2018 16:57, Goldschmidt Simon wrote:
>>> On Wed, 03/01/2018 14:51, Jagan Teki wrote:
>>> >> There were already patches posted on this list by me and others, but
>>> >> unfortunately they haven't made it into the repository, yet.
>>> >>
>>> >> Jagan, could you comment on the status of these fixes? I can search
>>> >> for the patchwork items related if you want me to.
>>> >
>>> > 2 out of 1 of this[1] have some discussion still going is it?
>>> >
>>> > [1] https://patchwork.ozlabs.org/patch/838195/
>>>
>>> No, that series should be dropped. I don't know if I can do anything about 
>>> that in
>>> patchwork though?
>>>
>>> Let me check the patches from my upstreaming queue when I'm back at work
>>> tomorrow. I'll send a list of patchwork items I needed to get QSPI running 
>>> on
<>> mach-socfpga.
>>
>> OK, so I need these patches to get qspi work on socfpga:
>>
>> - Series "spi: cadence_spi: Adopt Linux DT bindings" (v4) from Jason Rush:
>>   https://patchwork.ozlabs.org/project/uboot/list/?series=13864
>> - Patch "Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction 
>> when possible" (v2)
>>   https://patchwork.ozlabs.org/patch/838871/
> 
> I've waited for ack/tested-by from marek or someone who usually worked
> on these cadence.

Vignesh acked, who already did some of the last changes. But Ok, I've
added Marek to the loop.

Marek, do you see any problems here? Are you running QSPI on the
socfpga platform anywhere?

> 
>>
>> All patches were discussed with Vignesh in November. Could we make
>> sure these make it into 2018.03 now that we missed 2018.01?
>>
>> Aside from that, I have this patch running which ensures my QSPI (that
>> does not have a reset line) is put into 3 byte address mode that
>> U-Boot needs. This would be *very* helpful, too:
>> https://patchwork.ozlabs.org/patch/826919/
> 
> issue discussing with spi-nor changes as well, we will figure it out
> and try for best possible.

Ok, this is a different issue anyway. It is not related to socfpga
or cadence qspi. Maybe I can even trick my Linux to use 4 byte opcodes
instead of the 4 byte mode...

Thanks,
Simon
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[U-Boot] [PATCH v2 2/3] imx: introduce CONFIG_GPT_TIMER

[Stefan Agner]

From: Stefan Agner 

Introduce a new config symbol to select the i.MX
General Purpose Timer (GPT).

Signed-off-by: Stefan Agner 
Reviewed-by: Fabio Estevam 
---

Changes in v2:
- Fix Kconfig for MX5

 arch/arm/mach-imx/Kconfig | 3 +++
 arch/arm/mach-imx/Makefile| 3 ++-
 arch/arm/mach-imx/mx5/Kconfig | 1 +
 arch/arm/mach-imx/mx6/Kconfig | 1 +
 4 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 653819123c..3aec89d440 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -10,6 +10,9 @@ config ROM_UNIFIED_SECTIONS
 config SYSCOUNTER_TIMER
bool
 
+config GPT_TIMER
+   bool
+
 config IMX_RDC
bool "i.MX Resource domain controller driver"
depends on ARCH_MX6 || ARCH_MX7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d77c10e176..9322c1ce83 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -11,7 +11,8 @@ ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
 obj-y  = iomux-v3.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-obj-y  += timer.o cpu.o speed.o
+obj-y  += cpu.o speed.o
+obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index 250194b623..3ce6bcfc88 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -1,6 +1,7 @@
 if ARCH_MX5
 
 config MX5
+   select GPT_TIMER
bool
default y
 
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 752471fb72..1af60df8d8 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -9,6 +9,7 @@ config MX6_SMP
 
 config MX6
select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
+   select GPT_TIMER
bool
default y
imply CMD_FUSE
-- 
2.15.1

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[U-Boot] [PATCH v2 3/3] imx: initialize and use generic timer on i.MX 6UL/ULL

[Stefan Agner]

From: Stefan Agner 

The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM
generic timer. This change makes use of the ARM generic timer in
U-Boot.

This is crucial to make the ARM generic timers usable in Linux since
timer_init() initalizes the system counter module, which is necessary
to use the generic timers CP15 registers.

Signed-off-by: Stefan Agner 
Reviewed-by: Fabio Estevam 
---

Changes in v2: None

 arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
 arch/arm/mach-imx/Makefile   | 2 +-
 arch/arm/mach-imx/mx6/Kconfig| 4 +++-
 include/configs/mx6_common.h | 5 -
 4 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 4be7aab18a..48ce0edd06 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -291,6 +291,7 @@
 #endif
 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5)
 #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SCTR_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x6)
 #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #elif defined(CONFIG_MX6SX)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9322c1ce83..d7966cfd4a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -22,7 +22,6 @@ endif
 ifeq ($(SOC),$(filter $(SOC),mx7))
 obj-y  += cpu.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
-obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y  += cache.o init.o
@@ -31,6 +30,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 obj-$(CONFIG_SECURE_BOOT)+= hab.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7ulp))
 obj-y  += cache.o
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 1af60df8d8..86b80ca576 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -9,7 +9,7 @@ config MX6_SMP
 
 config MX6
select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
-   select GPT_TIMER
+   select GPT_TIMER if !MX6UL && !MX6ULL
bool
default y
imply CMD_FUSE
@@ -54,6 +54,7 @@ config MX6UL
select HAS_CAAM
select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
+   select SYSCOUNTER_TIMER
bool
 
 config MX6UL_LITESOM
@@ -76,6 +77,7 @@ config MX6UL_OPOS6UL
 config MX6ULL
select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
+   select SYSCOUNTER_TIMER
bool
 
 config MX6_DDRCAL
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 59e6daea62..ddc645c136 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -7,7 +7,10 @@
 #ifndef __MX6_COMMON_H
 #define __MX6_COMMON_H
 
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define CONFIG_SC_TIMER_CLK 800 /* 8Mhz */
+#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
+#else
 #ifndef CONFIG_SYS_L2CACHE_OFF
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE  L2_PL310_BASE
-- 
2.15.1

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[U-Boot] [PATCH v2 1/3] imx: move CONFIG_SYSCOUNTER_TIMER to Kconfig

[Stefan Agner]

From: Stefan Agner 

Signed-off-by: Stefan Agner 
Reviewed-by: Fabio Estevam 
---

Changes in v2: None

 arch/arm/mach-imx/Kconfig | 3 +++
 arch/arm/mach-imx/mx7/Kconfig | 1 +
 include/configs/mx7_common.h  | 1 -
 scripts/config_whitelist.txt  | 1 -
 4 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e687048b31..653819123c 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -7,6 +7,9 @@ config IMX_CONFIG
 config ROM_UNIFIED_SECTIONS
bool
 
+config SYSCOUNTER_TIMER
+   bool
+
 config IMX_RDC
bool "i.MX Resource domain controller driver"
depends on ARCH_MX6 || ARCH_MX7
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 4f8b4e138e..2a3db860bb 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -3,6 +3,7 @@ if ARCH_MX7
 config MX7
bool
select ROM_UNIFIED_SECTIONS
+   select SYSCOUNTER_TIMER
select CPU_V7_HAS_VIRT
select CPU_V7_HAS_NONSEC
select ARCH_SUPPORT_PSCI
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 16e4d95ff4..17850400c1 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -19,7 +19,6 @@
 
 /* Timer settings */
 #define CONFIG_MXC_GPT_HCLK
-#define CONFIG_SYSCOUNTER_TIMER
 #define CONFIG_SC_TIMER_CLK 800 /* 8Mhz */
 #define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
 #define CONFIG_SYS_FSL_CLK
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 43a4ff0892..5d8d907cc4 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2219,7 +2219,6 @@ CONFIG_SUPPORT_RAW_INITRD
 CONFIG_SUPPORT_VFAT
 CONFIG_SUVD3
 CONFIG_SXNI855T
-CONFIG_SYSCOUNTER_TIMER
 CONFIG_SYSFLAGS_ADDR
 CONFIG_SYSFS
 CONFIG_SYSMGR_ISWGRP_HANDOFF
-- 
2.15.1

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Re: [U-Boot] [PATCH 3/3] imx: initialize and use generic timer on i.MX 6UL/ULL

[Fabio Estevam]

On Fri, Jan 5, 2018 at 12:01 PM, Stefan Agner  wrote:

> This does not add it to MX6UL_LITESOM, it adds it to "config MX6ULL".
> diff is somewhat confusing here.

Got it! So all is well here then. Thanks
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Re: [U-Boot] [PATCH 3/3] imx: initialize and use generic timer on i.MX 6UL/ULL

[Stefan Agner]

On 2018-01-05 13:40, Fabio Estevam wrote:
> On Mon, Jan 1, 2018 at 10:43 PM, Stefan Agner  wrote:
> 
>> --- a/arch/arm/mach-imx/mx6/Kconfig
>> +++ b/arch/arm/mach-imx/mx6/Kconfig
>> @@ -9,7 +9,7 @@ config MX6_SMP
>>
>>  config MX6
>> select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
>> -   select GPT_TIMER
>> +   select GPT_TIMER if !MX6UL && !MX6ULL
>> bool
>> default y
>> imply CMD_FUSE
>> @@ -54,6 +54,7 @@ config MX6UL
>> select HAS_CAAM
>> select SYS_L2CACHE_OFF
>> select ROM_UNIFIED_SECTIONS
>> +   select SYSCOUNTER_TIMER
>> bool
>>
>>  config MX6UL_LITESOM
>> @@ -76,6 +77,7 @@ config MX6UL_OPOS6UL
>>  config MX6ULL
>> select SYS_L2CACHE_OFF
>> select ROM_UNIFIED_SECTIONS
>> +   select SYSCOUNTER_TIMER
> 
> This is not needed as MX6UL_LITESOM already selects MX6UL.

This does not add it to MX6UL_LITESOM, it adds it to "config MX6ULL".
diff is somewhat confusing here.

--
Stefan

> 
> Other than that:
> 
> Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH 2/3] imx: introduce CONFIG_GPT_TIMER

[Stefan Agner]

On 2018-01-02 01:43, Stefan Agner wrote:
> Introduce a new config symbol to select the i.MX
> General Purpose Timer (GPT).
> 
> Signed-off-by: Stefan Agner 
> ---
> 
>  arch/arm/mach-imx/Kconfig | 3 +++
>  arch/arm/mach-imx/Makefile| 3 ++-
>  arch/arm/mach-imx/mx5/Kconfig | 1 +
>  arch/arm/mach-imx/mx6/Kconfig | 1 +
>  4 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 653819123c..3aec89d440 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -10,6 +10,9 @@ config ROM_UNIFIED_SECTIONS
>  config SYSCOUNTER_TIMER
>   bool
>  
> +config GPT_TIMER
> + bool
> +
>  config IMX_RDC
>   bool "i.MX Resource domain controller driver"
>   depends on ARCH_MX6 || ARCH_MX7
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index d77c10e176..9322c1ce83 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -11,7 +11,8 @@ ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
>  obj-y= iomux-v3.o
>  endif
>  ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
> -obj-y+= timer.o cpu.o speed.o
> +obj-y+= cpu.o speed.o
> +obj-$(CONFIG_GPT_TIMER) += timer.o
>  obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
>  endif
>  ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
> diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
> index 250194b623..735cd240f1 100644
> --- a/arch/arm/mach-imx/mx5/Kconfig
> +++ b/arch/arm/mach-imx/mx5/Kconfig
> @@ -1,6 +1,7 @@
>  if ARCH_MX5
>  
>  config MX5
> + GPT_TIMER

Just realized, this does not work, select missing. Will send v2.

--
Stefan

>   bool
>   default y
>  
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
> index 752471fb72..1af60df8d8 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -9,6 +9,7 @@ config MX6_SMP
>  
>  config MX6
>   select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
> + select GPT_TIMER
>   bool
>   default y
>   imply CMD_FUSE
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[U-Boot] [PATCH v1 0/6] Add support for DM_USB for TI's DRA7 platforms

[Jean-Jacques Hiblot]

Supporting DM USB is required to support DM_ETH and USB network adapters
with the same binary.
This series adds support for DM_USB for the DRA7 family. It leverages the
work done for the STi family.

limitations:
- only USB2 Host is supported. USB2 Device can be added later.
- only DRA7 platforms, though it could be extended to other TI SOCs


Jean-Jacques Hiblot (6):
  board: ti: dra7xx-evm: turn on USB clocks in late init stage
  syscon: dm: Add a new method to get a regmap from DTS
  phy: Add a new driver for OMAP's USB2 PHYs
  usb: omap5: Add glue logic to support DM for USB host
  configs: enable DM_USB for all the platforms of the DRA7 family
  dts: dra7x: enable host on USB2 for all the platforms of the DRA7
family

 arch/arm/dts/dra7-evm-common.dtsi  |   7 ++
 arch/arm/dts/dra72-evm-common.dtsi |   4 +
 arch/arm/dts/omap5-u-boot.dtsi |   4 +
 board/ti/dra7xx/evm.c  |  19 
 configs/dra7xx_evm_defconfig   |   2 +
 configs/dra7xx_hs_evm_defconfig|   2 +
 drivers/core/syscon-uclass.c   |  23 +
 drivers/phy/Kconfig|   8 ++
 drivers/phy/Makefile   |   2 +
 drivers/phy/omap-usb2-phy.c| 186 +
 drivers/usb/host/Kconfig   |  10 ++
 drivers/usb/host/Makefile  |   1 +
 drivers/usb/host/dwc3-omap-glue.c  |  47 ++
 include/syscon.h   |  13 +++
 14 files changed, 328 insertions(+)
 create mode 100644 drivers/phy/omap-usb2-phy.c
 create mode 100644 drivers/usb/host/dwc3-omap-glue.c

-- 
1.9.1

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[U-Boot] [PATCH v1 4/6] usb: omap5: Add glue logic to support DM for USB host

[Jean-Jacques Hiblot]

The omap5 uses the dwc3. The dwc3 supports the driver model but it requires
some glue logic to load the the driver.

Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/usb/host/Kconfig  | 10 +
 drivers/usb/host/Makefile |  1 +
 drivers/usb/host/dwc3-omap-glue.c | 47 +++
 3 files changed, 58 insertions(+)
 create mode 100644 drivers/usb/host/dwc3-omap-glue.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index c79f866..82e1db2 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -79,6 +79,16 @@ config USB_XHCI_DRA7XX_INDEX
  Select the DRA7XX xHCI USB index.
  Current supported values: 0, 1.
 
+config USB_DM_XHCI_OMAP
+   bool "Support for OMAP family on-chip xHCI USB controller (DM version)"
+   depends on DM_USB
+   depends on ARCH_OMAP2PLUS
+   default y if DRA7XX
+   help
+ Enables support for the on-chip xHCI controller on TI OMAP family SoCs
+ using the Driver Model.
+ This driver provides the glue logic to probe the generic dwc3 driver.
+
 config USB_XHCI_FSL
bool "Support for NXP Layerscape on-chip xHCI USB controller"
default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 79df888..b13a564 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
 obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
 obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
+obj-$(CONFIG_USB_DM_XHCI_OMAP) += dwc3-omap-glue.o
 
 # designware
 obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/dwc3-omap-glue.c 
b/drivers/usb/host/dwc3-omap-glue.c
new file mode 100644
index 000..1110fb6
--- /dev/null
+++ b/drivers/usb/host/dwc3-omap-glue.c
@@ -0,0 +1,47 @@
+/*
+ * OMAP5 family DWC3 specific Glue layer
+ *
+ * Copyright (c) 2017
+ * Jean-Jacques Hiblot 
+ * based on dwc3-sti-glue
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int omap5_dwc3_glue_bind(struct udevice *dev)
+{
+   int dwc3_node;
+
+   /* check if one subnode is present */
+   dwc3_node = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
+   if (dwc3_node <= 0) {
+   printf("Can't find subnode for %s\n", dev->name);
+   return -ENODEV;
+   }
+   /* check if the subnode compatible string is the dwc3 one*/
+   if (fdt_node_check_compatible(gd->fdt_blob, dwc3_node,
+ "snps,dwc3") != 0) {
+   printf("Can't find dwc3 subnode for %s\n", dev->name);
+   return -ENODEV;
+   }
+
+   return dm_scan_fdt_dev(dev);
+}
+
+static const struct udevice_id omap5_dwc3_glue_ids[] = {
+   { .compatible = "ti,dwc3" },
+   { }
+};
+
+U_BOOT_DRIVER(dwc3_omap5_glue) = {
+   .name = "dwc3_omap5_glue",
+   .id = UCLASS_MISC,
+   .of_match = omap5_dwc3_glue_ids,
+   .bind = omap5_dwc3_glue_bind,
+};
-- 
1.9.1

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[U-Boot] [PATCH v1 3/6] phy: Add a new driver for OMAP's USB2 PHYs

[Jean-Jacques Hiblot]

This drivers supports the USB2 PHY found on omap5 and dra7 SOCs.

Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/phy/Kconfig |   8 ++
 drivers/phy/Makefile|   2 +
 drivers/phy/omap-usb2-phy.c | 186 
 3 files changed, 196 insertions(+)
 create mode 100644 drivers/phy/omap-usb2-phy.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 3b9a09c..dbf4e4d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -85,4 +85,12 @@ config STI_USB_PHY
  used by USB2 and USB3 Host controllers available on
  STiH407 SoC families.
 
+config OMAP_USB2_PHY
+   bool "Support OMAP's USB2 PHY"
+   depends on PHY
+   depends on SYSCON
+   help
+ Support for the OMAP's USB2 PHY.
+ This PHY is found on OMAP devices supporting USB2.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 668040b..ab7f205 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,3 +10,5 @@ obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
 obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
 obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
 obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
+
diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c
new file mode 100644
index 000..c8a87a5
--- /dev/null
+++ b/drivers/phy/omap-usb2-phy.c
@@ -0,0 +1,186 @@
+/*
+ * OMAP USB2 PHY driver
+ *
+ * Copyright (c) 2017
+ * Jean-Jacques Hiblot 
+ * based on dwc3-sti-glue
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OMAP_USB2_CALIBRATE_FALSE_DISCONNECT   BIT(0)
+
+#define OMAP_DEV_PHY_PDBIT(0)
+#define OMAP_USB2_PHY_PD   BIT(28)
+
+#define USB2PHY_DISCON_BYP_LATCH   BIT(31)
+#define USB2PHY_ANA_CONFIG1(0x4c)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct omap_usb2_phy {
+   struct regmap *pwr_regmap;
+   ulong flags;
+   void *phy_base;
+   u32 pwr_reg_offset;
+};
+
+struct usb_phy_data {
+   const char *label;
+   u8 flags;
+   u32 mask;
+   u32 power_on;
+   u32 power_off;
+};
+
+static const struct usb_phy_data omap5_usb2_data = {
+   .label = "omap5_usb2",
+   .flags = 0,
+   .mask = OMAP_DEV_PHY_PD,
+   .power_off = OMAP_DEV_PHY_PD,
+};
+
+static const struct usb_phy_data dra7x_usb2_data = {
+   .label = "dra7x_usb2",
+   .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+   .mask = OMAP_DEV_PHY_PD,
+   .power_off = OMAP_DEV_PHY_PD,
+};
+
+static const struct usb_phy_data dra7x_usb2_phy2_data = {
+   .label = "dra7x_usb2_phy2",
+   .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+   .mask = OMAP_USB2_PHY_PD,
+   .power_off = OMAP_USB2_PHY_PD,
+};
+
+static const struct udevice_id omap_usb2_id_table[] = {
+   {
+   .compatible = "ti,omap5-usb2",
+   .data = (ulong)_usb2_data,
+   },
+   {
+   .compatible = "ti,dra7x-usb2",
+   .data = (ulong)_usb2_data,
+   },
+   {
+   .compatible = "ti,dra7x-usb2-phy2",
+   .data = (ulong)_usb2_phy2_data,
+   },
+   {},
+};
+
+static int omap_usb_phy_power(struct phy *usb_phy, bool on)
+{
+   struct udevice *dev = usb_phy->dev;
+   const struct usb_phy_data *data;
+   const struct omap_usb2_phy *phy = dev_get_priv(dev);
+   u32 val;
+   int rc;
+
+   data = (const struct usb_phy_data *)dev_get_driver_data(dev);
+   if (!data)
+   return -EINVAL;
+
+   rc = regmap_read(phy->pwr_regmap, phy->pwr_reg_offset, );
+   if (rc)
+   return rc;
+   val &= ~data->mask;
+   if (on)
+   val |= data->power_on;
+   else
+   val |= data->power_off;
+   rc = regmap_write(phy->pwr_regmap, phy->pwr_reg_offset, val);
+   if (rc)
+   return rc;
+
+   return 0;
+}
+
+static int omap_usb2_phy_init(struct phy *usb_phy)
+{
+   struct udevice *dev = usb_phy->dev;
+   struct omap_usb2_phy *priv = dev_get_priv(dev);
+   u32 val;
+
+   if (priv->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
+   /*
+*
+* Reduce the sensitivity of internal PHY by enabling the
+* DISCON_BYP_LATCH of the USB2PHY_ANA_CONFIG1 register. This
+* resolves issues with certain devices which can otherwise
+* be prone to false disconnects.
+*
+*/
+   val = readl(priv->phy_base + USB2PHY_ANA_CONFIG1);
+   val |= USB2PHY_DISCON_BYP_LATCH;
+   writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1);
+   }
+
+   return omap_usb_phy_power(usb_phy, true);
+}
+
+static int omap_usb2_phy_exit(struct phy *usb_phy)
+{
+   return omap_usb_phy_power(usb_phy, false);
+}
+

[U-Boot] [PATCH v1 6/6] dts: dra7x: enable host on USB2 for all the platforms of the DRA7 family

[Jean-Jacques Hiblot]

This enables the USB2. USB1 is not enabled because it's managed by platform
code not by DM.

Signed-off-by: Jean-Jacques Hiblot 

---

 arch/arm/dts/dra7-evm-common.dtsi  | 7 +++
 arch/arm/dts/dra72-evm-common.dtsi | 4 
 arch/arm/dts/omap5-u-boot.dtsi | 4 
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/dts/dra7-evm-common.dtsi 
b/arch/arm/dts/dra7-evm-common.dtsi
index 343e95f..4b11c16 100644
--- a/arch/arm/dts/dra7-evm-common.dtsi
+++ b/arch/arm/dts/dra7-evm-common.dtsi
@@ -191,15 +191,22 @@
 
 _dwc3_1 {
extcon = <_usb1>;
+   status = "disabled";
 };
 
  {
dr_mode = "otg";
extcon = <_usb1>;
+   status = "disabled";
+};
+
+_dwc3_2 {
+   status = "okay";
 };
 
  {
dr_mode = "host";
+   status = "okay";
 };
 
  {
diff --git a/arch/arm/dts/dra72-evm-common.dtsi 
b/arch/arm/dts/dra72-evm-common.dtsi
index 2e485a1..dae3de0 100644
--- a/arch/arm/dts/dra72-evm-common.dtsi
+++ b/arch/arm/dts/dra72-evm-common.dtsi
@@ -386,19 +386,23 @@
 
 _dwc3_1 {
extcon = <_usb1>;
+   status = "disabled";
 };
 
 _dwc3_2 {
extcon = <_usb2>;
+   status = "okay";
 };
 
  {
dr_mode = "otg";
extcon = <_usb1>;
+   status = "disabled";
 };
 
  {
dr_mode = "host";
+   status = "okay";
 };
 
  {
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index bf2684c..a6a7801 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -15,6 +15,10 @@
ocp {
u-boot,dm-spl;
 
+   ocp2scp@4a08 {
+   compatible = "ti,omap-ocp2scp", "simple-bus";
+   };
+
ocp2scp@4a09 {
compatible = "ti,omap-ocp2scp", "simple-bus";
};
-- 
1.9.1

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[U-Boot] [PATCH v1 2/6] syscon: dm: Add a new method to get a regmap from DTS

[Jean-Jacques Hiblot]

syscon_regmap_lookup_by_phandle() can be used to the regmap of a syscon
device from a reference in the DTS. It operates similarly to the linux
version of the namesake function.

Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/core/syscon-uclass.c | 23 +++
 include/syscon.h | 13 +
 2 files changed, 36 insertions(+)

diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index a69937e..0c76bfc 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -45,6 +45,29 @@ static int syscon_pre_probe(struct udevice *dev)
 #endif
 }
 
+struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev,
+  const char *name)
+{
+   struct udevice *syscon;
+   struct regmap *r;
+   int err;
+
+   err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+  name, );
+   if (err) {
+   printf("unable to find syscon device\n");
+   return ERR_PTR(err);
+   }
+
+   r = syscon_get_regmap(syscon);
+   if (!r) {
+   printf("unable to find regmap\n");
+   return ERR_PTR(-ENODEV);
+   }
+
+   return r;
+}
+
 int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
 {
struct udevice *dev;
diff --git a/include/syscon.h b/include/syscon.h
index 5d52b1c..23d257a 100644
--- a/include/syscon.h
+++ b/include/syscon.h
@@ -74,6 +74,19 @@ int syscon_get_by_driver_data(ulong driver_data, struct 
udevice **devp);
 struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data);
 
 /**
+ * syscon_regmap_lookup_by_phandle() - Look up a controller by a phandle
+ *
+ * This operates by looking up the given name in the device (device
+ * tree property) of the device using the system controller.
+ *
+ * @dev:   Device using the system controller
+ * @name:  Name of property referring to the system controller
+ * @return A pointer to the regmap if found, ERR_PTR(-ve) on error
+ */
+struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev,
+  const char *name);
+
+/**
  * syscon_get_first_range() - get the first memory range from a syscon regmap
  *
  * @driver_data:   Driver data value to look up
-- 
1.9.1

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[U-Boot] [PATCH v1 5/6] configs: enable DM_USB for all the platforms of the DRA7 family

[Jean-Jacques Hiblot]

Signed-off-by: Jean-Jacques Hiblot 
---

 configs/dra7xx_evm_defconfig| 2 ++
 configs/dra7xx_hs_evm_defconfig | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 716a57b..875f501 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -48,6 +48,7 @@ CONFIG_DFU_SF=y
 CONFIG_DM_GPIO=y
 CONFIG_PCF8575_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_SPI_FLASH=y
@@ -58,6 +59,7 @@ CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_SPL_PHY=y
+CONFIG_OMAP_USB2_PHY=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_PMIC_LP873X=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index f7418c7..cdc1bfb 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -50,6 +50,7 @@ CONFIG_DFU_SF=y
 CONFIG_DM_GPIO=y
 CONFIG_PCF8575_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_SPI_FLASH=y
@@ -60,6 +61,7 @@ CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_SPL_PHY=y
+CONFIG_OMAP_USB2_PHY=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_PMIC_LP873X=y
 CONFIG_DM_REGULATOR_FIXED=y
-- 
1.9.1

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[U-Boot] [PATCH v1 1/6] board: ti: dra7xx-evm: turn on USB clocks in late init stage

[Jean-Jacques Hiblot]

For USB ports that use the Driver Model, turn on the clocks during the
late init stage.

Signed-off-by: Jean-Jacques Hiblot 
---

 board/ti/dra7xx/evm.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 6bcfa48..7f363b6 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -643,6 +643,19 @@ int dram_init_banksize(void)
return 0;
 }
 
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+static int device_okay(const char *path)
+{
+   int node;
+
+   node = fdt_path_offset(gd->fdt_blob, path);
+   if (node < 0)
+   return 0;
+
+   return fdtdec_get_is_enabled(gd->fdt_blob, node);
+}
+#endif
+
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -680,6 +693,12 @@ int board_late_init(void)
if (board_is_dra71x_evm())
palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
 #endif
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+   if (device_okay("/ocp/omap_dwc3_1@4888"))
+   enable_usb_clocks(0);
+   if (device_okay("/ocp/omap_dwc3_2@488c"))
+   enable_usb_clocks(1);
+#endif
return 0;
 }
 
-- 
1.9.1

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Re: [U-Boot] [PATCH] armv8: ls1088ardb: Put distro boot functions under CONFIG_SPL_BUILD

[Sumit Garg]

Hi Ashish,

Changes in below patch are already part of following patch already in upstream.

https://patchwork.ozlabs.org/patch/806983/

Regards,
Sumit

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Ashish
> Kumar
> Sent: Friday, January 05, 2018 5:08 PM
> To: u-boot@lists.denx.de
> Cc: Pankit Garg 
> Subject: [U-Boot] [PATCH] armv8: ls1088ardb: Put distro boot functions under
> CONFIG_SPL_BUILD
> 
> Remove distro related stuff from SPL-uboot to save on SPL size.
> 
> Signed-off-by: Ashish Kumar 
> Signed-off-by: Pankit Garg 
> ---
> 
> Size reduction is approx 5K
> depends upon
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
> work.ozlabs.org%2Fpatch%2F853615%2F=02%7C01%7Csumit.garg%40nx
> p.com%7C73fa100c2a554dda5df408d55430b3f2%7C686ea1d3bc2b4c6fa92cd99c
> 5c301635%7C0%7C0%7C636507490531835553=%2FaSTyJNHM%2BYZUvJf
> CB9NMjrJn9OU7WBVkrFkx36pYJI%3D=0
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
> work.ozlabs.org%2Fpatch%2F854402%2F=02%7C01%7Csumit.garg%40nx
> p.com%7C73fa100c2a554dda5df408d55430b3f2%7C686ea1d3bc2b4c6fa92cd99c
> 5c301635%7C0%7C0%7C636507490531835553=k8F7Yezv%2F2GA5DfcIAx
> T%2FcztGNSqZDl9YsNtHhGBqdk%3D=0
> 
>  include/configs/ls1088ardb.h | 42
> +-
>  1 file changed, 41 insertions(+), 1 deletion(-)
> 
> diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index
> ad01a99..3661065 100644
> --- a/include/configs/ls1088ardb.h
> +++ b/include/configs/ls1088ardb.h
> @@ -285,6 +285,8 @@
>  #endif
> 
>  #undef CONFIG_EXTRA_ENV_SETTINGS
> +
> +#ifndef CONFIG_SPL_BUILD
>  #define CONFIG_EXTRA_ENV_SETTINGS\
>   "BOARD=ls1088ardb\0"\
>   "hwconfig=fsl_ddr:bank_intlv=auto\0"\
> @@ -357,6 +359,43 @@
>   "$kernelhdr_addr_sd $kernelhdr_size_sd "\
>   " && esbc_validate ${kernelheader_addr_r};" \
>   "bootm $load_addr#$BOARD\0"
> +#else
> +#if defined(CONFIG_QSPI_BOOT)
> +#undef CONFIG_EXTRA_ENV_SETTINGS
> +#define CONFIG_EXTRA_ENV_SETTINGS\
> + "hwconfig=fsl_ddr:bank_intlv=auto\0"\
> + "loadaddr=0x9010\0" \
> + "kernel_addr=0x10\0"\
> + "ramdisk_addr=0x80\0"   \
> + "ramdisk_size=0x200\0"  \
> + "fdt_high=0xa000\0" \
> + "initrd_high=0x\0"  \
> + "kernel_start=0x100\0"  \
> + "kernel_load=0xa000\0"  \
> + "kernel_size=0x280\0"   \
> + "mcinitcmd=sf probe 0:0;sf read 0x8000 0xA0 0x10;"  \
> + "sf read 0x8010 0xE0 0x10;" \
> + "fsl_mc start mc 0x8000 0x8010\0"   \
> + "mcmemsize=0x7000 \0"
> +#elif defined(CONFIG_SD_BOOT)
> +#undef CONFIG_EXTRA_ENV_SETTINGS
> +#define CONFIG_EXTRA_ENV_SETTINGS   \
> + "hwconfig=fsl_ddr:bank_intlv=auto\0"\
> + "loadaddr=0x9010\0" \
> + "kernel_addr=0x800\0"\
> + "ramdisk_addr=0x80\0"   \
> + "ramdisk_size=0x200\0"  \
> + "fdt_high=0xa000\0" \
> + "initrd_high=0x\0"  \
> + "kernel_start=0x8000\0"  \
> + "kernel_load=0xa000\0"  \
> + "kernel_size=0x14000\0"   \
> + "mcinitcmd=mmcinfo;mmc read 0x8000 0x5000 0x800;"  \
> + "mmc read 0x8010 0x7000 0x800;" \
> + "fsl_mc start mc 0x8000 0x8010\0"   \
> + "mcmemsize=0x7000 \0"
> +#endif
> +#endif
> 
>  #undef CONFIG_BOOTCOMMAND
>  #if defined(CONFIG_QSPI_BOOT)
> @@ -414,14 +453,15 @@
>  #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
>  #endif
> 
> +#ifndef CONFIG_SPL_BUILD
>  #undef CONFIG_CMDLINE_EDITING
>  #include 
> -
>  #define BOOT_TARGET_DEVICES(func) \
>   func(MMC, mmc, 0) \
>   func(SCSI, scsi, 0) \
>   func(DHCP, dhcp, na)
>  #include 
> +#endif
> 
>  #include 
> 
> --
> 2.7.4
> 
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Re: [U-Boot] [PATCH 1/3] imx: move CONFIG_SYSCOUNTER_TIMER to Kconfig

[Stefano Babic]

Hi Stefan,

On 05/01/2018 11:26, Stefan Agner wrote:
> Hi Stefano,
> 
> Any chance to get this patchset still into v2018.01?

Yes !

Stefano

> IMHO it is almost a
> bug that U-Boot does not initialize the ARM architected timer
> properly...
> 
> --
> Stefan
> 
> 
> On 2018-01-02 01:43, Stefan Agner wrote:
>> Signed-off-by: Stefan Agner 
>> ---
>>
>>  arch/arm/mach-imx/Kconfig | 3 +++
>>  arch/arm/mach-imx/mx7/Kconfig | 1 +
>>  include/configs/mx7_common.h  | 1 -
>>  scripts/config_whitelist.txt  | 1 -
>>  4 files changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
>> index e687048b31..653819123c 100644
>> --- a/arch/arm/mach-imx/Kconfig
>> +++ b/arch/arm/mach-imx/Kconfig
>> @@ -7,6 +7,9 @@ config IMX_CONFIG
>>  config ROM_UNIFIED_SECTIONS
>>  bool
>>  
>> +config SYSCOUNTER_TIMER
>> +bool
>> +
>>  config IMX_RDC
>>  bool "i.MX Resource domain controller driver"
>>  depends on ARCH_MX6 || ARCH_MX7
>> diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
>> index 4f8b4e138e..2a3db860bb 100644
>> --- a/arch/arm/mach-imx/mx7/Kconfig
>> +++ b/arch/arm/mach-imx/mx7/Kconfig
>> @@ -3,6 +3,7 @@ if ARCH_MX7
>>  config MX7
>>  bool
>>  select ROM_UNIFIED_SECTIONS
>> +select SYSCOUNTER_TIMER
>>  select CPU_V7_HAS_VIRT
>>  select CPU_V7_HAS_NONSEC
>>  select ARCH_SUPPORT_PSCI
>> diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
>> index 16e4d95ff4..17850400c1 100644
>> --- a/include/configs/mx7_common.h
>> +++ b/include/configs/mx7_common.h
>> @@ -19,7 +19,6 @@
>>  
>>  /* Timer settings */
>>  #define CONFIG_MXC_GPT_HCLK
>> -#define CONFIG_SYSCOUNTER_TIMER
>>  #define CONFIG_SC_TIMER_CLK 800 /* 8Mhz */
>>  #define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
>>  #define CONFIG_SYS_FSL_CLK
>> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
>> index 43a4ff0892..5d8d907cc4 100644
>> --- a/scripts/config_whitelist.txt
>> +++ b/scripts/config_whitelist.txt
>> @@ -2219,7 +2219,6 @@ CONFIG_SUPPORT_RAW_INITRD
>>  CONFIG_SUPPORT_VFAT
>>  CONFIG_SUVD3
>>  CONFIG_SXNI855T
>> -CONFIG_SYSCOUNTER_TIMER
>>  CONFIG_SYSFLAGS_ADDR
>>  CONFIG_SYSFS
>>  CONFIG_SYSMGR_ISWGRP_HANDOFF

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [PATCH v2] crypto/fsl: fix BLOB encapsulation and decapsulation

[Sumit Garg]

> From: Clemens Gruber [mailto:clemens.gru...@pqgruber.com]
> Sent: Friday, January 05, 2018 6:32 PM
> 
> Hi Sumit, Fabio, York,
> 
> On Fri, Jan 05, 2018 at 06:47:36AM +, Sumit Garg wrote:
> > Hi Clemens, York, Fabio,
> >
> > > -Original Message-
> > > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of
> > > Fabio Estevam
> > > Sent: Friday, January 05, 2018 3:27 AM
> > > To: York Sun 
> > > Cc: Breno Matheus Lima ; u-boot@lists.denx.de;
> > > clemens.gru...@pqgruber.com; Fabio Estevam
> 
> > > Subject: [U-Boot] [PATCH v2] crypto/fsl: fix BLOB encapsulation and
> > > decapsulation
> > >
> >
> > 
> >
> > >
> > >  int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)  {
> > > - int ret, i = 0;
> > > + ALLOC_CACHE_ALIGN_BUFFER(u8, aligned_key_mod, 16);
> > > + u8 *aligned_src, *aligned_dst;
> > > + int ret, size, i = 0;
> > >   u32 *desc;
> > >
> > >   printf("\nDecapsulating blob to get data\n");
> > > - desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
> > > + desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
> > >   if (!desc) {
> > >   debug("Not enough memory for descriptor allocation\n");
> > > - return -1;
> > > + return -ENOMEM;
> > >   }
> > >
> > > - inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
> > > + aligned_src = malloc_cache_aligned(BLOB_SIZE(len));
> > > + aligned_dst = malloc_cache_aligned(len);
> >
> > Please don't use malloc here as these blob_encap and blob_decap
> commands are used to blobify or deblobify images of maximum sizes upto 32
> MB.
> >
> > But u-boot malloc pool is of size:
> >
> > /* Size of malloc() pool */
> > #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 2048 * 1024)
> >
> > So please remove malloc from this patch for source and destination images as
> it will fail for larger images.
> 
> I could use ALLOC_CACHE_ALIGN_BUFFER to store the aligned_src and _dst
> buffers on the stack instead of the malloc pool.

I don't think stack is enough to save src and dest images (max. size: approx. 
64MB).

> 
> Or would you rather remove the copying and require the caller of
> blob_encap/_decap to pass correctly aligned addresses?
> 

Yes you could put check for input src and dest addresses to be cache aligned and
print error to make user aware to pass cache aligned addresses. Also double 
copying will
be much overhead for encap or decap of images (size 32MB).

-Sumit

> York: Should I send a v3 or a fixup patch ontop of v2.
> 
> Thanks,
> Clemens
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Re: [U-Boot] [PATCH V2] imx: mx7: psci: add system reset support

[Anson Huang]

Hi, Fabio

Best Regards!
Anson Huang


> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: 2018-01-04 8:57 PM
> To: Anson Huang 
> Cc: Stefano Babic ; Fabio Estevam
> ; Albert ARIBAUD ;
> Christian Gmeiner ; Peng Fan
> ; U-Boot-Denx 
> Subject: Re: [U-Boot] [PATCH V2] imx: mx7: psci: add system reset support
> 
> Hi Anson,
> 
> On Thu, Jan 4, 2018 at 7:03 AM, Anson Huang  wrote:
> > Add i.MX7 PSCI system reset support, linux kernel now can use "reboot"
> > command to reset system.
> 
> Reading this commit message gives me the impression that the 'reboot'
> command does not work currently.
> 
> However, the 'reboot' command works provided the boards connects the
> WDOG output pin to the PMIC  due to the MX7 erratum.
> 
> What exactly are you fixing here? Please clarify.

Thanks for the comments, the current reboot command works is just
because wdog driver is enabled and when system reboot, the reboot notification
callback in wdog driver will do reset. But if wdog is disabled in dtb, the 
reboot
command will fail.

As now we use PSCI, the reboot operation will eventually call into u-boot's psci
reset callback, we should support this feature, the reboot feature in Linux 
kernel
should NOT depends on wdog's existence.

But I did notice that I miss a change to enable the psci reset feature, we 
should
Use psci 1.0 instead of 0.1, psci 0.1 only supports very limited features which 
does
NOT include system reset, power off etc..

So I re-send a patch series to do these changes, to support PSCI system reset, 
system
power off, please help review, thanks.

Anson.


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[U-Boot] [PATCH 3/3] imx: mx7: psci: add system power off support

[Anson Huang]

Add i.MX7 PSCI system power off support, linux
kernel can use "poweroff" command to power off
system via SNVS, PMIC power will be disabled.

Signed-off-by: Anson Huang 
---
 arch/arm/mach-imx/mx7/psci-mx7.c | 18 ++
 arch/arm/mach-imx/mx7/psci.S |  7 +++
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c
index 66f6db6..0e515f0 100644
--- a/arch/arm/mach-imx/mx7/psci-mx7.c
+++ b/arch/arm/mach-imx/mx7/psci-mx7.c
@@ -26,6 +26,12 @@
 #define BP_SRC_A7RCR0_A7_CORE_RESET0   0
 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE  1
 
+#define SNVS_LPCR  0x38
+#define BP_SNVS_LPCR_DP_EN 0x20
+#define BP_SNVS_LPCR_TOP   0x40
+
+#define CCM_CCGR_SNVS  0x4250
+
 static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
 {
writel(enable, GPC_IPS_BASE_ADDR + offset);
@@ -79,3 +85,15 @@ __secure void imx_system_reset(void)
 {
writew(1 << 2, WDOG1_BASE_ADDR);
 }
+
+__secure void imx_system_off(void)
+{
+   u32 val;
+
+   /* make sure SNVS clock is enabled */
+   writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
+
+   val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
+   val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
+   writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
+}
diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S
index 59f98cd..3d15016 100644
--- a/arch/arm/mach-imx/mx7/psci.S
+++ b/arch/arm/mach-imx/mx7/psci.S
@@ -50,4 +50,11 @@ psci_system_reset:
 2: wfi
b 2b
 
+.globl psci_system_off
+psci_system_off:
+   b   imx_system_off
+
+3: wfi
+   b 3b
+
.popsection
-- 
1.9.1

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[U-Boot] [PATCH 1/3] mx7_common: use psci 1.0 instead of 0.1

[Anson Huang]

Use PSCI 1.0 instead of 0.1 to support more power
management feature like system reset, power off etc..

Signed-off-by: Anson Huang 
---
 include/configs/mx7_common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 16e4d95..7861712 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -62,6 +62,8 @@
 
 #define CONFIG_ARMV7_SECURE_BASE   0x0090
 
+#define CONFIG_ARMV7_PSCI_1_0
+
 /* Secure boot (HAB) support */
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CSF_SIZE0x2000
-- 
1.9.1

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[U-Boot] [PATCH 2/3] imx: mx7: psci: add system reset support

[Anson Huang]

Add i.MX7 PSCI system reset support, linux
kernel can use "reboot" command to reset
system even wdog driver is disabled in kernel.

Signed-off-by: Anson Huang 
---
 arch/arm/mach-imx/mx7/psci-mx7.c | 5 +
 arch/arm/mach-imx/mx7/psci.S | 7 +++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c
index 7f429b0..66f6db6 100644
--- a/arch/arm/mach-imx/mx7/psci-mx7.c
+++ b/arch/arm/mach-imx/mx7/psci-mx7.c
@@ -74,3 +74,8 @@ __secure int imx_cpu_off(int cpu)
writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
return 0;
 }
+
+__secure void imx_system_reset(void)
+{
+   writew(1 << 2, WDOG1_BASE_ADDR);
+}
diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S
index fc5eb34..59f98cd 100644
--- a/arch/arm/mach-imx/mx7/psci.S
+++ b/arch/arm/mach-imx/mx7/psci.S
@@ -43,4 +43,11 @@ psci_cpu_off:
 1: wfi
b 1b
 
+.globl psci_system_reset
+psci_system_reset:
+   b   imx_system_reset
+
+2: wfi
+   b 2b
+
.popsection
-- 
1.9.1

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[U-Boot] [PATCH] drivers: pci: imx: fix enumeration logic error

[Koen Vandeputte]

By default, the subordinate is set equally to the secondary bus (1) when
the RC boots, and does not alter afterwards.

This means that theoretically, the highest bus reachable downstream is
bus 1.

Force the PCIe RC subordinate to 0xff, otherwise no downstream
devices will be detected behind bus 1 if the booting OS does not allow
enumerating a higher busnr than the subordinate value of the primary
bus.

Signed-off-by: Koen Vandeputte 
---
 drivers/pci/pcie_imx.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 2900c8d..9277af9 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -612,6 +612,17 @@ static int imx_pcie_link_up(void)
imx_pcie_regions_setup();
 
/*
+* By default, the subordinate is set equally to the secondary
+* bus (0x01) when the RC boots.
+* This means that theoretically, only bus 1 is reachable from the RC.
+* Force the PCIe RC subordinate to 0xff, otherwise no downstream
+* devices will be detected if the enumeration is applied strictly.
+*/
+   tmp = readl(MX6_DBI_ADDR + 0x18);
+   tmp |= (0xff << 16);
+   writel(tmp, MX6_DBI_ADDR + 0x18);
+
+   /*
 * FIXME: Force the PCIe RC to Gen1 operation
 * The RC must be forced into Gen1 mode before bringing the link
 * up, otherwise no downstream devices are detected. After the
-- 
2.7.4

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Re: [U-Boot] [PATCH v2] crypto/fsl: fix BLOB encapsulation and decapsulation

[Clemens Gruber]

Hi Sumit, Fabio, York,

On Fri, Jan 05, 2018 at 06:47:36AM +, Sumit Garg wrote:
> Hi Clemens, York, Fabio,
> 
> > -Original Message-
> > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Fabio
> > Estevam
> > Sent: Friday, January 05, 2018 3:27 AM
> > To: York Sun 
> > Cc: Breno Matheus Lima ; u-boot@lists.denx.de;
> > clemens.gru...@pqgruber.com; Fabio Estevam 
> > Subject: [U-Boot] [PATCH v2] crypto/fsl: fix BLOB encapsulation and
> > decapsulation
> > 
> 
> 
> 
> > 
> >  int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)  {
> > -   int ret, i = 0;
> > +   ALLOC_CACHE_ALIGN_BUFFER(u8, aligned_key_mod, 16);
> > +   u8 *aligned_src, *aligned_dst;
> > +   int ret, size, i = 0;
> > u32 *desc;
> > 
> > printf("\nDecapsulating blob to get data\n");
> > -   desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
> > +   desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
> > if (!desc) {
> > debug("Not enough memory for descriptor allocation\n");
> > -   return -1;
> > +   return -ENOMEM;
> > }
> > 
> > -   inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
> > +   aligned_src = malloc_cache_aligned(BLOB_SIZE(len));
> > +   aligned_dst = malloc_cache_aligned(len);
>  
> Please don't use malloc here as these blob_encap and blob_decap commands are 
> used to blobify or deblobify images of maximum sizes upto 32 MB.
> 
> But u-boot malloc pool is of size:
> 
> /* Size of malloc() pool */
> #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 2048 * 1024)
> 
> So please remove malloc from this patch for source and destination images as 
> it will fail for larger images.

I could use ALLOC_CACHE_ALIGN_BUFFER to store the aligned_src and _dst
buffers on the stack instead of the malloc pool.

Or would you rather remove the copying and require the caller of
blob_encap/_decap to pass correctly aligned addresses?

York: Should I send a v3 or a fixup patch ontop of v2.

Thanks,
Clemens
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Re: [U-Boot] [PATCH 3/3] imx: initialize and use generic timer on i.MX 6UL/ULL

[Fabio Estevam]

On Mon, Jan 1, 2018 at 10:43 PM, Stefan Agner  wrote:

> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -9,7 +9,7 @@ config MX6_SMP
>
>  config MX6
> select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
> -   select GPT_TIMER
> +   select GPT_TIMER if !MX6UL && !MX6ULL
> bool
> default y
> imply CMD_FUSE
> @@ -54,6 +54,7 @@ config MX6UL
> select HAS_CAAM
> select SYS_L2CACHE_OFF
> select ROM_UNIFIED_SECTIONS
> +   select SYSCOUNTER_TIMER
> bool
>
>  config MX6UL_LITESOM
> @@ -76,6 +77,7 @@ config MX6UL_OPOS6UL
>  config MX6ULL
> select SYS_L2CACHE_OFF
> select ROM_UNIFIED_SECTIONS
> +   select SYSCOUNTER_TIMER

This is not needed as MX6UL_LITESOM already selects MX6UL.

Other than that:

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH 2/3] imx: introduce CONFIG_GPT_TIMER

[Fabio Estevam]

On Mon, Jan 1, 2018 at 10:43 PM, Stefan Agner  wrote:
> Introduce a new config symbol to select the i.MX
> General Purpose Timer (GPT).
>
> Signed-off-by: Stefan Agner 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH 1/3] imx: move CONFIG_SYSCOUNTER_TIMER to Kconfig

[Fabio Estevam]

On Mon, Jan 1, 2018 at 10:43 PM, Stefan Agner  wrote:
> Signed-off-by: Stefan Agner 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

[Jagan Teki]

On Fri, Jan 5, 2018 at 5:32 PM, Goldschmidt Simon
 wrote:
> + Vignesh
> + Jason
>
> On Wed, 03/01/2018 16:57, Goldschmidt Simon wrote:
>> On Wed, 03/01/2018 14:51, Jagan Teki wrote:
>> >> There were already patches posted on this list by me and others, but
>> >> unfortunately they haven't made it into the repository, yet.
>> >>
>> >> Jagan, could you comment on the status of these fixes? I can search
>> >> for the patchwork items related if you want me to.
>> >
>> > 2 out of 1 of this[1] have some discussion still going is it?
>> >
>> > [1] https://patchwork.ozlabs.org/patch/838195/
>>
>> No, that series should be dropped. I don't know if I can do anything about 
>> that in
>> patchwork though?
>>
>> Let me check the patches from my upstreaming queue when I'm back at work
>> tomorrow. I'll send a list of patchwork items I needed to get QSPI running on
>> mach-socfpga.
>
> OK, so I need these patches to get qspi work on socfpga:
>
> - Series "spi: cadence_spi: Adopt Linux DT bindings" (v4) from Jason Rush:
>   https://patchwork.ozlabs.org/project/uboot/list/?series=13864
> - Patch "Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction 
> when possible" (v2)
>   https://patchwork.ozlabs.org/patch/838871/

I've waited for ack/tested-by from marek or someone who usually worked
on these cadence.

>
> All patches were discussed with Vignesh in November. Could we make
> sure these make it into 2018.03 now that we missed 2018.01?
>
> Aside from that, I have this patch running which ensures my QSPI (that
> does not have a reset line) is put into 3 byte address mode that
> U-Boot needs. This would be *very* helpful, too:
> https://patchwork.ozlabs.org/patch/826919/

issue discussing with spi-nor changes as well, we will figure it out
and try for best possible.
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Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

[Goldschmidt Simon]

+ Vignesh
+ Jason

On Wed, 03/01/2018 16:57, Goldschmidt Simon wrote:
> On Wed, 03/01/2018 14:51, Jagan Teki wrote:
> >> There were already patches posted on this list by me and others, but
> >> unfortunately they haven't made it into the repository, yet.
> >>
> >> Jagan, could you comment on the status of these fixes? I can search
> >> for the patchwork items related if you want me to.
> >
> > 2 out of 1 of this[1] have some discussion still going is it?
> >
> > [1] https://patchwork.ozlabs.org/patch/838195/
> 
> No, that series should be dropped. I don't know if I can do anything about 
> that in
> patchwork though?
> 
> Let me check the patches from my upstreaming queue when I'm back at work
> tomorrow. I'll send a list of patchwork items I needed to get QSPI running on
> mach-socfpga.

OK, so I need these patches to get qspi work on socfpga:

- Series "spi: cadence_spi: Adopt Linux DT bindings" (v4) from Jason Rush:
  https://patchwork.ozlabs.org/project/uboot/list/?series=13864
- Patch "Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction 
when possible" (v2)
  https://patchwork.ozlabs.org/patch/838871/

All patches were discussed with Vignesh in November. Could we make
sure these make it into 2018.03 now that we missed 2018.01?

Aside from that, I have this patch running which ensures my QSPI (that
does not have a reset line) is put into 3 byte address mode that
U-Boot needs. This would be *very* helpful, too:
https://patchwork.ozlabs.org/patch/826919/

Thanks,
Simon
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[U-Boot] FIT nand boot fail to load U-Boot proper

[Jagan Teki]

I have not debugged much on this, just to check whether the same
feature work for others or not?

SPL is unable to load U-Boot proper, which is fit formatted of two dtb
bundle, but normal U-Boot proper loads fine.

Log:

>>spl:board_init_r()
spl_early_init()
Trying to boot from NAND
: 512 MiB
nand_spl_load_image offset:0x0020 len:64 page:512
Found FIT
nand_spl_load_image offset:0x0020 len:1052 page:512
fit read sector 20, sectors=1052, dst=177ff980, count=1052
Selecting config 'imx6q-icore'firmware: 'firmware@1'
nand_spl_load_image offset:0x0020041c len:510672 page:512
image: dst=1780, offset=41c, size=7cad0
Selecting config 'imx6q-icore'fdt: 'fdt@1'
nand_spl_load_image offset:0x0027ceec len:30884 page:636
image: dst=1787cb00, offset=7ceec, size=78a4
Selecting config 'imx6q-icore'cannot find property 'loadables': -1
if entry = 0x0, load = 0x1780
entry = 0x1780, load = 0x1780
Jumping to U-Boot
loaded - jumping to U-Boot...
image entry point: 0x1780
<< hang >>

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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[U-Boot] [PATCH] armv8: ls1088ardb: Put distro boot functions under CONFIG_SPL_BUILD

[Ashish Kumar]

Remove distro related stuff from SPL-uboot to save on SPL size.

Signed-off-by: Ashish Kumar 
Signed-off-by: Pankit Garg 
---

Size reduction is approx 5K
depends upon
http://patchwork.ozlabs.org/patch/853615/
http://patchwork.ozlabs.org/patch/854402/

 include/configs/ls1088ardb.h | 42 +-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index ad01a99..3661065 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -285,6 +285,8 @@
 #endif
 
 #undef CONFIG_EXTRA_ENV_SETTINGS
+
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"BOARD=ls1088ardb\0"\
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
@@ -357,6 +359,43 @@
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0"
+#else
+#if defined(CONFIG_QSPI_BOOT)
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS  \
+   "hwconfig=fsl_ddr:bank_intlv=auto\0"\
+   "loadaddr=0x9010\0" \
+   "kernel_addr=0x10\0"\
+   "ramdisk_addr=0x80\0"   \
+   "ramdisk_size=0x200\0"  \
+   "fdt_high=0xa000\0" \
+   "initrd_high=0x\0"  \
+   "kernel_start=0x100\0"  \
+   "kernel_load=0xa000\0"  \
+   "kernel_size=0x280\0"   \
+   "mcinitcmd=sf probe 0:0;sf read 0x8000 0xA0 0x10;"  \
+   "sf read 0x8010 0xE0 0x10;" \
+   "fsl_mc start mc 0x8000 0x8010\0"   \
+   "mcmemsize=0x7000 \0"
+#elif defined(CONFIG_SD_BOOT)
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS   \
+   "hwconfig=fsl_ddr:bank_intlv=auto\0"\
+   "loadaddr=0x9010\0" \
+   "kernel_addr=0x800\0"\
+   "ramdisk_addr=0x80\0"   \
+   "ramdisk_size=0x200\0"  \
+   "fdt_high=0xa000\0" \
+   "initrd_high=0x\0"  \
+   "kernel_start=0x8000\0"  \
+   "kernel_load=0xa000\0"  \
+   "kernel_size=0x14000\0"   \
+   "mcinitcmd=mmcinfo;mmc read 0x8000 0x5000 0x800;"  \
+   "mmc read 0x8010 0x7000 0x800;" \
+   "fsl_mc start mc 0x8000 0x8010\0"   \
+   "mcmemsize=0x7000 \0"
+#endif
+#endif
 
 #undef CONFIG_BOOTCOMMAND
 #if defined(CONFIG_QSPI_BOOT)
@@ -414,14 +453,15 @@
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 #undef CONFIG_CMDLINE_EDITING
 #include 
-
 #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(SCSI, scsi, 0) \
func(DHCP, dhcp, na)
 #include 
+#endif
 
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH 3/3] xilinx: zynqmp: Add new target with only emmc enabled

[Siva Durga Prasad Paladugu]

This patch adds new target which is called as mini configuration
with only emmc functionality and other required basic features enabled.
This will be used to run in system with small footprint and needs
emmc support.

Signed-off-by: Siva Durga Prasad Paladugu 
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/zynqmp-mini-emmc.dts | 76 +++
 configs/xilinx_zynqmp_mini_emmc_defconfig | 44 ++
 include/configs/xilinx_zynqmp_mini_emmc.h | 23 ++
 4 files changed, 144 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-mini-emmc.dts
 create mode 100644 configs/xilinx_zynqmp_mini_emmc_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_mini_emmc.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f702fa1..2230190 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -147,6 +147,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb\
+   zynqmp-mini-emmc.dtb\
zynqmp-mini-nand.dtb\
zynqmp-mini-qspi-single.dtb \
zynqmp-zcu102-revA.dtb  \
diff --git a/arch/arm/dts/zynqmp-mini-emmc.dts 
b/arch/arm/dts/zynqmp-mini-emmc.dts
new file mode 100644
index 000..e659340
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-emmc.dts
@@ -0,0 +1,76 @@
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+   model = "ZynqMP MINI EMMC";
+   compatible = "xlnx,zynqmp";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   aliases {
+   serial0 = 
+   mmc0 = 
+   mmc1 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x2000>;
+   };
+
+   dcc: dcc {
+   compatible = "arm,dcc";
+   status = "disabled";
+   u-boot,dm-pre-reloc;
+   };
+
+   amba: amba {
+   compatible = "simple-bus";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   sdhci0: sdhci@ff16 {
+   u-boot,dm-pre-reloc;
+   compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+   status = "disabled";
+   reg = <0x0 0xff16 0x0 0x1000>;
+   clock-names = "clk_xin", "clk_ahb";
+   xlnx,device_id = <0>;
+   };
+
+   sdhci1: sdhci@ff17 {
+   u-boot,dm-pre-reloc;
+   compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+   status = "disabled";
+   reg = <0x0 0xff17 0x0 0x1000>;
+   clock-names = "clk_xin", "clk_ahb";
+   xlnx,device_id = <1>;
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/configs/xilinx_zynqmp_mini_emmc_defconfig 
b/configs/xilinx_zynqmp_mini_emmc_defconfig
new file mode 100644
index 000..5d854d9
--- /dev/null
+++ b/configs/xilinx_zynqmp_mini_emmc_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x1
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h 
b/include/configs/xilinx_zynqmp_mini_emmc.h
new file mode 100644
index 000..6f56cf6
--- 

[U-Boot] [PATCH 0/3] Add new targets for Xilinx ZynqMP SoC

[Siva Durga Prasad Paladugu]

This series adds new targets for Xilinx ZynqMP SoC. These
targets are mainly meant for u-boot with minimal set
of required functionality for each of flash devices
such as qspi, nand and emmc. These are used in places
where u-boot is supposed to run in memory with smaller
footprints and with dedicated flash device.

Siva Durga Prasad Paladugu (3):
  xilinx: zynqmp: Add new target with only qspi enabled
  xilinx: zynqmp: Add new target with only nand enabled
  xilinx: zynqmp: Add new target with only emmc enabled

 arch/arm/dts/Makefile |   3 +
 arch/arm/dts/zynqmp-mini-emmc.dts |  76 +
 arch/arm/dts/zynqmp-mini-nand.dts | 109 ++
 arch/arm/dts/zynqmp-mini-qspi-single.dts  |  13 
 arch/arm/dts/zynqmp-mini-qspi.dtsi|  96 ++
 configs/xilinx_zynqmp_mini_emmc_defconfig |  44 
 configs/xilinx_zynqmp_mini_nand_defconfig |  44 
 configs/xilinx_zynqmp_mini_qspi_defconfig |  56 +++
 include/configs/xilinx_zynqmp_mini.h  |  45 
 include/configs/xilinx_zynqmp_mini_emmc.h |  23 +++
 include/configs/xilinx_zynqmp_mini_nand.h |  24 +++
 include/configs/xilinx_zynqmp_mini_qspi.h |  25 +++
 12 files changed, 558 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-mini-emmc.dts
 create mode 100644 arch/arm/dts/zynqmp-mini-nand.dts
 create mode 100644 arch/arm/dts/zynqmp-mini-qspi-single.dts
 create mode 100644 arch/arm/dts/zynqmp-mini-qspi.dtsi
 create mode 100644 configs/xilinx_zynqmp_mini_emmc_defconfig
 create mode 100644 configs/xilinx_zynqmp_mini_nand_defconfig
 create mode 100644 configs/xilinx_zynqmp_mini_qspi_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_mini.h
 create mode 100644 include/configs/xilinx_zynqmp_mini_emmc.h
 create mode 100644 include/configs/xilinx_zynqmp_mini_nand.h
 create mode 100644 include/configs/xilinx_zynqmp_mini_qspi.h

-- 
2.7.4

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[U-Boot] [PATCH 2/3] xilinx: zynqmp: Add new target with only nand enabled

[Siva Durga Prasad Paladugu]

This patch adds new target which is called as mini configuration
with only nand functionality and other required basic features enabled.
This will be used to run in system with small footprint and needs
nand support.

Signed-off-by: Siva Durga Prasad Paladugu 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/zynqmp-mini-nand.dts | 109 ++
 configs/xilinx_zynqmp_mini_nand_defconfig |  44 
 include/configs/xilinx_zynqmp_mini_nand.h |  24 +++
 4 files changed, 178 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-mini-nand.dts
 create mode 100644 configs/xilinx_zynqmp_mini_nand_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_mini_nand.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5ef942e..f702fa1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -147,6 +147,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb\
+   zynqmp-mini-nand.dtb\
zynqmp-mini-qspi-single.dtb \
zynqmp-zcu102-revA.dtb  \
zynqmp-zcu102-revB.dtb  \
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts 
b/arch/arm/dts/zynqmp-mini-nand.dts
new file mode 100644
index 000..16e5f55
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -0,0 +1,109 @@
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad 
+ * Michal Simek 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+   model = "ZynqMP MINI NAND";
+   compatible = "xlnx,zynqmp";
+   #address-cells = <2>;
+   #size-cells = <1>;
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x4000>;
+   };
+
+   dcc: dcc {
+   compatible = "arm,dcc";
+   status = "disabled";
+   u-boot,dm-pre-reloc;
+   };
+
+   amba: amba {
+   compatible = "simple-bus";
+   #address-cells = <2>;
+   #size-cells = <1>;
+   ranges;
+
+   nand0: nand@ff10 {
+   compatible = "arasan,nfc-v3p10";
+   status = "okay";
+   reg = <0x0 0xff10 0x1000>;
+   clock-names = "clk_sys", "clk_flash";
+   #address-cells = <2>;
+   #size-cells = <1>;
+   arasan,has-mdma;
+   num-cs = <2>;
+
+   partition@0 {   /* for testing purpose */
+   label = "nand-fsbl-uboot";
+   reg = <0x0 0x0 0x40>;
+   };
+   partition@1 {   /* for testing purpose */
+   label = "nand-linux";
+   reg = <0x0 0x40 0x140>;
+   };
+   partition@2 {   /* for testing purpose */
+   label = "nand-device-tree";
+   reg = <0x0 0x180 0x40>;
+   };
+   partition@3 {   /* for testing purpose */
+   label = "nand-rootfs";
+   reg = <0x0 0x1C0 0x140>;
+   };
+   partition@4 {   /* for testing purpose */
+   label = "nand-bitstream";
+   reg = <0x0 0x300 0x40>;
+   };
+   partition@5 {   /* for testing purpose */
+   label = "nand-misc";
+   reg = <0x0 0x340 0xFCC0>;
+   };
+   partition@6 {   /* for testing purpose */
+   label = "nand1-fsbl-uboot";
+   reg = <0x1 0x0 0x40>;
+   };
+   partition@7 {   /* for testing purpose */
+   label = "nand1-linux";
+   reg = <0x1 0x40 0x140>;
+   };
+   partition@8 {   /* for testing purpose */
+   label = "nand1-device-tree";
+   reg = <0x1 0x180 0x40>;
+   };
+   partition@9 {   /* for testing purpose */
+   label = "nand1-rootfs";
+   reg = <0x1 0x1C0 0x140>;
+   };
+   

[U-Boot] [PATCH 1/3] xilinx: zynqmp: Add new target with only qspi enabled

[Siva Durga Prasad Paladugu]

This patch adds new target which is called as mini configuration
with only qspi enabled. This will be used to run in system with
small footprint and needs qspi support. One example of such case
is that it can run from OCM and programs qspi flash in DDR less
systems.

Signed-off-by: Siva Durga Prasad Paladugu 
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/zynqmp-mini-qspi-single.dts  | 13 +
 arch/arm/dts/zynqmp-mini-qspi.dtsi| 96 +++
 configs/xilinx_zynqmp_mini_qspi_defconfig | 56 ++
 include/configs/xilinx_zynqmp_mini.h  | 45 +++
 include/configs/xilinx_zynqmp_mini_qspi.h | 25 
 6 files changed, 236 insertions(+)
 create mode 100644 arch/arm/dts/zynqmp-mini-qspi-single.dts
 create mode 100644 arch/arm/dts/zynqmp-mini-qspi.dtsi
 create mode 100644 configs/xilinx_zynqmp_mini_qspi_defconfig
 create mode 100644 include/configs/xilinx_zynqmp_mini.h
 create mode 100644 include/configs/xilinx_zynqmp_mini_qspi.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a895c70..5ef942e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -147,6 +147,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb\
+   zynqmp-mini-qspi-single.dtb \
zynqmp-zcu102-revA.dtb  \
zynqmp-zcu102-revB.dtb  \
zynqmp-zcu102-rev1.0.dtb\
diff --git a/arch/arm/dts/zynqmp-mini-qspi-single.dts 
b/arch/arm/dts/zynqmp-mini-qspi-single.dts
new file mode 100644
index 000..c87eab3
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-single.dts
@@ -0,0 +1,13 @@
+/*
+ * Xilinx ZynqMP QSPI single DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "zynqmp-mini-qspi.dtsi"
+
+ {
+   spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dtsi 
b/arch/arm/dts/zynqmp-mini-qspi.dtsi
new file mode 100644
index 000..e4e6417
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi.dtsi
@@ -0,0 +1,96 @@
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad 
+ * Michal Simek 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+   model = "ZynqMP MINI QSPI";
+   compatible = "xlnx,zynqmp";
+   #address-cells = <2>;
+   #size-cells = <1>;
+
+   aliases {
+   serial0 = 
+   spi0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x4000>;
+   };
+
+   dcc: dcc {
+   compatible = "arm,dcc";
+   status = "disabled";
+   u-boot,dm-pre-reloc;
+   };
+
+   amba: amba {
+   compatible = "simple-bus";
+   #address-cells = <2>;
+   #size-cells = <1>;
+   ranges;
+
+   qspi: spi@ff0f {
+   compatible = "xlnx,zynqmp-qspi-1.0";
+   status = "disabled";
+   clock-names = "ref_clk", "pclk";
+   clocks = <_clk _clk>;
+   num-cs = <1>;
+   reg = <0x0 0xff0f 0x1000 0x0 0xc000 0x800>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   misc_clk: misc_clk {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <12500>;
+   };
+   };
+};
+
+ {
+   status = "okay";
+   flash@0 {
+   compatible = "n25q512a11";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x0>;
+   spi-tx-bus-width = <1>;
+   spi-rx-bus-width = <4>;
+   spi-max-frequency = <1000>;
+   partition@qspi-fsbl-uboot { /* for testing purpose */
+   label = "qspi-fsbl-uboot";
+   reg = <0x0 0x10>;
+   };
+   partition@qspi-linux { /* for testing purpose */
+   label = "qspi-linux";
+   reg = <0x10 0x50>;
+   };
+   partition@qspi-device-tree { /* for testing purpose */
+   label = "qspi-device-tree";
+   reg = <0x60 0x2>;
+   };
+   partition@qspi-rootfs { /* for testing purpose */
+   label = "qspi-rootfs";
+   reg = <0x62 0x5E>;
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
diff --git 

[U-Boot] [PATCH 06/07] db410c: add reserved-memory node to dts

[Jorge Ramirez-Ortiz]

From: Rob Clark 

If lk lights up display and populates simple-framebuffer node, it will
also setup a reserved-memory node (needed by simplefb on linux).  But
it isn't clever enough to cope when the reserved-memory node is not
present.

Signed-off-by: Rob Clark 
---
 arch/arm/dts/dragonboard410c.dts | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index b67e588..5ccfe7f 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -23,11 +23,16 @@
reg = <0 0x8000 0 0x3da0>;
};
 
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   };
+
chosen {
stdout-path = "/soc/serial@78b";
};
 
-
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
-- 
2.7.4

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[U-Boot] [PATCH 07/07] db410c: on aarch64 the fdtfile is in per-vendor subdirectory

[Jorge Ramirez-Ortiz]

From: Rob Clark 

Signed-off-by: Rob Clark 
---
 include/configs/dragonboard410c.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/dragonboard410c.h 
b/include/configs/dragonboard410c.h
index 3c5bb8a..530d667 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -92,7 +92,7 @@ REFLASH(dragonboard/u-boot.img, 8)\
"initrd_high=0x\0" \
"linux_image=Image\0" \
"kernel_addr_r=0x8100\0"\
-   "fdtfile=apq8016-sbc.dtb\0" \
+   "fdtfile=qcom/apq8016-sbc.dtb\0" \
"fdt_addr_r=0x8300\0"\
"ramdisk_addr_r=0x8400\0"\
"scriptaddr=0x9000\0"\
-- 
2.7.4

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[U-Boot] [PATCH 04/07] fdtdec: allow board to provide fdt for CONFIG_OF_SEPARATE

[Jorge Ramirez-Ortiz]

From: Rob Clark 

Similar to CONFIG_OF_BOARD, but in this case the fdt is still built by
u-boot build.  This allows the board to patch the fdt, etc.

In the specific case of dragonboard 410c, we pass the u-boot generated
fdt to the previous stage of bootloader (by embedding it in the
u-boot.img that is loaded by lk/aboot), which patches the fdt and passes
it back to u-boot.

Signed-off-by: Rob Clark 
---
 include/fdtdec.h |  3 ++-
 lib/fdtdec.c | 35 +++
 2 files changed, 25 insertions(+), 13 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 0fb3e07..4afb9ac 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -990,7 +990,8 @@ int fdtdec_setup(void);
 
 /**
  * Board-specific FDT initialization. Returns the address to a device tree 
blob.
- * Called when CONFIG_OF_BOARD is defined.
+ * Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined
+ * and the board implements it.
  */
 void *board_fdt_blob_setup(void);
 
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 30ec6b9..cc3dfd6 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1272,6 +1272,28 @@ static int uncompress_blob(const void *src, ulong 
sz_src, void **dstp)
 # endif
 #endif
 
+#if CONFIG_IS_ENABLED(OF_SEPARATE)
+/*
+ * For CONFIG_OF_SEPARATE, the board may optionally implement this to
+ * provide and/or fixup the fdt.
+ */
+__weak void *board_fdt_blob_setup(void)
+{
+   void *fdt_blob = NULL;
+#ifdef CONFIG_SPL_BUILD
+   /* FDT is at end of BSS unless it is in a different memory region */
+   if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
+   fdt_blob = (ulong *)&_image_binary_end;
+   else
+   fdt_blob = (ulong *)&__bss_end;
+#else
+   /* FDT is at end of image */
+   fdt_blob = (ulong *)&_end;
+#endif
+   return fdt_blob;
+}
+#endif
+
 int fdtdec_setup(void)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)
@@ -1285,18 +1307,7 @@ int fdtdec_setup(void)
 #  else
gd->fdt_blob = __dtb_dt_begin;
 #  endif
-# elif defined CONFIG_OF_SEPARATE
-#  ifdef CONFIG_SPL_BUILD
-   /* FDT is at end of BSS unless it is in a different memory region */
-   if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
-   gd->fdt_blob = (ulong *)&_image_binary_end;
-   else
-   gd->fdt_blob = (ulong *)&__bss_end;
-#  else
-   /* FDT is at end of image */
-   gd->fdt_blob = (ulong *)&_end;
-#  endif
-# elif defined(CONFIG_OF_BOARD)
+# elif defined(CONFIG_OF_BOARD) || defined (CONFIG_OF_SEPARATE)
/* Allow the board to override the fdt address. */
gd->fdt_blob = board_fdt_blob_setup();
 # elif defined(CONFIG_OF_HOSTFILE)
-- 
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[U-Boot] [PATCH 05/07] db410c: use the device tree parsed by the lk loader.

[Jorge Ramirez-Ortiz]

We dont need to keep copies of the properties that we are going to
fixup since we will be using the dtb provided by the firmware.

Signed-off-by: Jorge Ramirez-Ortiz 
---
 board/qualcomm/dragonboard410c/dragonboard410c.c | 71 ++--
 configs/dragonboard410c_defconfig|  1 +
 2 files changed, 44 insertions(+), 28 deletions(-)

diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c 
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 8ef4338..236160a 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -15,14 +15,22 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* pointer to the device tree ammended by the firmware */
-extern const void *fw_dtb;
+extern void *fw_dtb;
 
-static char wlan_mac[ARP_HLEN];
-static char bt_mac[ARP_HLEN];
+void *board_fdt_blob_setup(void)
+{
+   if (fdt_magic(fw_dtb) != FDT_MAGIC) {
+   printf("Firmware provided invalid dtb!\n");
+   return NULL;
+   }
+
+   return fw_dtb;
+}
 
 int dram_init(void)
 {
gd->ram_size = PHYS_SDRAM_1_SIZE;
+
return 0;
 }
 
@@ -138,36 +146,43 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-   int offset, len;
-   const char *mac;
-
-   /* take a copy of the firmware information (the user could unknownly
-  overwrite that DDR via tftp or other means)  */
-
-   offset = fdt_node_offset_by_compatible(fw_dtb, -1, "qcom,wcnss-wlan");
-   if (offset >= 0) {
-   mac = fdt_getprop(fw_dtb, offset, "local-mac-address", );
-   if (mac)
-   memcpy(wlan_mac, mac, ARP_HLEN);
-   }
-
-   offset = fdt_node_offset_by_compatible(fw_dtb, -1, "qcom,wcnss-bt");
-   if (offset >= 0) {
-   mac = fdt_getprop(fw_dtb, offset, "local-bd-address", );
-   if (mac)
-   memcpy(bt_mac, mac, ARP_HLEN);
-   }
-
return 0;
 }
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
-   do_fixup_by_compat(blob, "qcom,wcnss-wlan", "local-mac-address",
-   wlan_mac, ARP_HLEN, 1);
-
-   do_fixup_by_compat(blob, "qcom,wcnss-bt", "local-bd-address",
-   bt_mac, ARP_HLEN, 1);
+   int offset, len, i;
+   const char *mac;
+   struct {
+   const char *compatible;
+   const char *property;
+   } fix[] = {
+   [0] = {
+   /* update the kernel's dtb with wlan mac */
+   .compatible = "qcom,wcnss-wlan",
+   .property = "local-mac-address",
+   },
+   [1] = {
+   /* update the kernel's dtb with bt mac */
+   .compatible = "qcom,wcnss-bt",
+   .property = "local-bd-address",
+   },
+   };
+
+   for ( i = 0; i < sizeof(fix)/sizeof(fix[0]); i++) {
+
+   offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+   fix[i].compatible);
+   if (offset < 0)
+   continue;
+
+   mac = fdt_getprop(gd->fdt_blob, offset, fix[i].property, );
+   if (mac)
+   do_fixup_by_compat(blob,
+   fix[i].compatible,
+   fix[i].property,
+   mac, ARP_HLEN, 1);
+   }
 
return 0;
 }
diff --git a/configs/dragonboard410c_defconfig 
b/configs/dragonboard410c_defconfig
index de923ad..4389f52 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -47,3 +47,4 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_PSCI_RESET=y
+CONFIG_OF_SEPARATE=y
-- 
2.7.4

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[U-Boot] [PATCH 03/07] db410c: replace reset driver with psci

[Jorge Ramirez-Ortiz]

this should be the norm for armv8 platforms.

Signed-off-by: Jorge Ramirez-Ortiz 
---
 arch/arm/dts/dragonboard410c.dts |  5 ---
 board/qualcomm/dragonboard410c/dragonboard410c.c |  5 +++
 configs/dragonboard410c_defconfig|  2 +-
 drivers/sysreset/Makefile|  2 --
 drivers/sysreset/sysreset_snapdragon.c   | 40 
 5 files changed, 6 insertions(+), 48 deletions(-)
 delete mode 100644 drivers/sysreset/sysreset_snapdragon.c

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 25aeac4..b67e588 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -48,11 +48,6 @@
clock = < 4>;
};
 
-   restart@4ab000 {
-   compatible = "qcom,pshold";
-   reg = <0x4ab000 0x4>;
-   };
-
soc_gpios: pinctrl@100 {
compatible = "qcom,apq8016-pinctrl";
reg = <0x100 0x30>;
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c 
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 99fc91b..8ef4338 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -171,3 +171,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
return 0;
 }
+
+void reset_cpu(ulong addr)
+{
+   psci_system_reset();
+}
diff --git a/configs/dragonboard410c_defconfig 
b/configs/dragonboard410c_defconfig
index cfe9be9..de923ad 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -30,7 +30,6 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_PM8916=y
 CONFIG_MSM_SERIAL=y
 CONFIG_SPMI_MSM=y
-CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
@@ -47,3 +46,4 @@ CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_PSCI_RESET=y
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 2e9598e..000c288 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -8,10 +8,8 @@ obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
 obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
 obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
 obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
-
 obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
 obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
-obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
 obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
 obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
diff --git a/drivers/sysreset/sysreset_snapdragon.c 
b/drivers/sysreset/sysreset_snapdragon.c
deleted file mode 100644
index 9869813..000
--- a/drivers/sysreset/sysreset_snapdragon.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Qualcomm APQ8016 reset controller driver
- *
- * (C) Copyright 2015 Mateusz Kulikowski 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type)
-{
-   phys_addr_t addr = devfdt_get_addr(dev);
-   if (!addr)
-   return -EINVAL;
-   writel(0, addr);
-   return -EINPROGRESS;
-}
-
-static struct sysreset_ops msm_sysreset_ops = {
-   .request= msm_sysreset_request,
-};
-
-static const struct udevice_id msm_sysreset_ids[] = {
-   { .compatible = "qcom,pshold" },
-   { }
-};
-
-U_BOOT_DRIVER(msm_reset) = {
-   .name   = "msm_sysreset",
-   .id = UCLASS_SYSRESET,
-   .of_match   = msm_sysreset_ids,
-   .ops= _sysreset_ops,
-};
-- 
2.7.4

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[U-Boot] [PATCH 02/07] db410c: update wlan and bt mac addresses from firmware

[Jorge Ramirez-Ortiz]

The firmware that runs before u-boot modifies u-boot's device tree
adding the local-mac-address and local-bd-address properties for the
compatibles "qcom,wcnss-bt" and "qcom,wcnss-wlan".

This commit reads that firmware, retrieves the properties and fixups
the device tree that is passed to the kernel before booting.

Signed-off-by: Jorge Ramirez-Ortiz 
---
 arch/arm/dts/dragonboard410c.dts | 10 +
 board/qualcomm/dragonboard410c/Makefile  |  1 +
 board/qualcomm/dragonboard410c/dragonboard410c.c | 49 +---
 board/qualcomm/dragonboard410c/lowlevel_init.S   | 28 ++
 configs/dragonboard410c_defconfig|  3 ++
 5 files changed, 85 insertions(+), 6 deletions(-)
 create mode 100644 board/qualcomm/dragonboard410c/lowlevel_init.S

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 7746622..25aeac4 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -86,6 +86,16 @@
clock-frequency = <2>;
};
 
+   wcnss {
+   bt {
+   compatible="qcom,wcnss-bt";
+   };
+
+   wifi {
+   compatible="qcom,wcnss-wlan";
+   };
+   };
+
spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f800 0x200 0x240 0x40 0x2c0 
0x40>;
diff --git a/board/qualcomm/dragonboard410c/Makefile 
b/board/qualcomm/dragonboard410c/Makefile
index cd67808..5082383 100644
--- a/board/qualcomm/dragonboard410c/Makefile
+++ b/board/qualcomm/dragonboard410c/Makefile
@@ -5,4 +5,5 @@
 #
 
 obj-y  := dragonboard410c.o
+obj-y  += lowlevel_init.o
 extra-y += head.o
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c 
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 848e278..99fc91b 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -10,9 +10,16 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* pointer to the device tree ammended by the firmware */
+extern const void *fw_dtb;
+
+static char wlan_mac[ARP_HLEN];
+static char bt_mac[ARP_HLEN];
+
 int dram_init(void)
 {
gd->ram_size = PHYS_SDRAM_1_SIZE;
@@ -27,7 +34,6 @@ int dram_init_banksize(void)
return 0;
 }
 
-
 int board_prepare_usb(enum usb_init_type type)
 {
static struct udevice *pmic_gpio;
@@ -96,11 +102,6 @@ int board_prepare_usb(enum usb_init_type type)
return 0;
 }
 
-int board_init(void)
-{
-   return 0;
-}
-
 /* Check for vol- button - if pressed - stop autoboot */
 int misc_init_r(void)
 {
@@ -134,3 +135,39 @@ int misc_init_r(void)
 
return 0;
 }
+
+int board_init(void)
+{
+   int offset, len;
+   const char *mac;
+
+   /* take a copy of the firmware information (the user could unknownly
+  overwrite that DDR via tftp or other means)  */
+
+   offset = fdt_node_offset_by_compatible(fw_dtb, -1, "qcom,wcnss-wlan");
+   if (offset >= 0) {
+   mac = fdt_getprop(fw_dtb, offset, "local-mac-address", );
+   if (mac)
+   memcpy(wlan_mac, mac, ARP_HLEN);
+   }
+
+   offset = fdt_node_offset_by_compatible(fw_dtb, -1, "qcom,wcnss-bt");
+   if (offset >= 0) {
+   mac = fdt_getprop(fw_dtb, offset, "local-bd-address", );
+   if (mac)
+   memcpy(bt_mac, mac, ARP_HLEN);
+   }
+
+   return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+   do_fixup_by_compat(blob, "qcom,wcnss-wlan", "local-mac-address",
+   wlan_mac, ARP_HLEN, 1);
+
+   do_fixup_by_compat(blob, "qcom,wcnss-bt", "local-bd-address",
+   bt_mac, ARP_HLEN, 1);
+
+   return 0;
+}
diff --git a/board/qualcomm/dragonboard410c/lowlevel_init.S 
b/board/qualcomm/dragonboard410c/lowlevel_init.S
new file mode 100644
index 000..15b2d0c
--- /dev/null
+++ b/board/qualcomm/dragonboard410c/lowlevel_init.S
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2016
+ * Cédric Schieli 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+.align 8
+.global fw_dtb
+fw_dtb:
+   .dword 0x0
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: save ATAG/FDT address provided by the firmware at boot time
+ */
+
+.global save_boot_params
+save_boot_params:
+
+   /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+   adr x8, fw_dtb
+   str x0, [x8]
+
+   /* Returns */
+   b   save_boot_params_ret
diff --git a/configs/dragonboard410c_defconfig 
b/configs/dragonboard410c_defconfig
index b71bff7..cfe9be9 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig

[U-Boot] [PATCH 01/07] db410c: configs: increase gunzip buffer size for the kernel

[Jorge Ramirez-Ortiz]

the kernel fails to boot when it goes over the limit.

Signed-off-by: Jorge Ramirez-Ortiz 
---
 include/configs/dragonboard410c.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/dragonboard410c.h 
b/include/configs/dragonboard410c.h
index d2447b2..3c5bb8a 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -23,7 +23,7 @@
 #define CONFIG_SYS_TEXT_BASE   0x8008
 #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + 
0x7fff0)
 #define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_SDRAM_BASE + 0x8)
-#define CONFIG_SYS_BOOTM_LEN   0x100 /* 16MB max kernel size */
+#define CONFIG_SYS_BOOTM_LEN   SZ_64M
 
 /* UART */
 
-- 
2.7.4

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[U-Boot] [PATCH 03/05] db820c: add qualcomm dragonboard 820C support

[Jorge Ramirez-Ortiz]

This commit adds support for 96Boards Dragonboard820C.

The board is based on APQ8086 Qualcomm Soc, complying with the
96Boards specification.

Features
 - 4x Kyro CPU (64 bit) up to 2.15GHz
 - USB2.0
 - USB3.0
 - ISP
 - Qualcomm Hexagon DSP
 - SD 3.0 (UHS-I)
 - UFS 2.0
 - Qualcomm Adreno 530 GPU
 - GPS
 - BT 4.2
 - Wi-Fi 2.4GHz, 5GHz (802.11ac)
 - PCIe 2.0
 - MIPI-CSI, MIPI-DSI
 - I2S

U-Boot boots chained from LK (LK implements the fastboot protocol) in
64-bit mode.

For detailed build instructions see readme.txt in the board directory.

Signed-off-by: Jorge Ramirez-Ortiz 
---
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/dragonboard820c.dts   |  65 +++
 arch/arm/mach-snapdragon/Kconfig   |  10 +
 arch/arm/mach-snapdragon/Makefile  |   2 +
 arch/arm/mach-snapdragon/clock-apq8096.c   |  62 +++
 .../mach-snapdragon/include/mach/sysmap-apq8096.h  |  29 ++
 arch/arm/mach-snapdragon/sysmap-apq8096.c  |  32 ++
 board/qualcomm/dragonboard820c/Kconfig |  15 +
 board/qualcomm/dragonboard820c/MAINTAINERS |   6 +
 board/qualcomm/dragonboard820c/Makefile|   8 +
 board/qualcomm/dragonboard820c/dragonboard820c.c   | 128 ++
 board/qualcomm/dragonboard820c/head.S  |  34 ++
 board/qualcomm/dragonboard820c/readme.txt  | 463 +
 board/qualcomm/dragonboard820c/u-boot.lds  | 106 +
 configs/dragonboard820c_defconfig  |  37 ++
 include/configs/dragonboard820c.h  |  72 
 16 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/dragonboard820c.dts
 create mode 100644 arch/arm/mach-snapdragon/clock-apq8096.c
 create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
 create mode 100644 arch/arm/mach-snapdragon/sysmap-apq8096.c
 create mode 100644 board/qualcomm/dragonboard820c/Kconfig
 create mode 100644 board/qualcomm/dragonboard820c/MAINTAINERS
 create mode 100644 board/qualcomm/dragonboard820c/Makefile
 create mode 100644 board/qualcomm/dragonboard820c/dragonboard820c.c
 create mode 100644 board/qualcomm/dragonboard820c/head.S
 create mode 100644 board/qualcomm/dragonboard820c/readme.txt
 create mode 100644 board/qualcomm/dragonboard820c/u-boot.lds
 create mode 100644 configs/dragonboard820c_defconfig
 create mode 100644 include/configs/dragonboard820c.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a895c70..6d0587e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -211,7 +211,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-frdm.dtb

-dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
+dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
+dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb

 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
stm32f769-disco.dtb
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
new file mode 100644
index 000..bad5a1e
--- /dev/null
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -0,0 +1,65 @@
+/*
+ * Qualcomm APQ8096 based Dragonboard 820C board device tree source
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. DB820c";
+   compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   aliases {
+   serial0 = _uart1;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0 0x8000 0 0xc000>;
+   };
+
+   psci {
+   compatible = "arm,psci-1.0";
+   method = "smc";
+   };
+
+   soc: soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0 0 0x>;
+   compatible = "simple-bus";
+
+   gcc: clock-controller@30 {
+   compatible = "qcom,gcc-msm8996";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   #power-domain-cells = <1>;
+   reg = <0x30 0x9>;
+   };
+
+   blsp2_uart1: serial@75b {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x75b 0x1000>;
+   };
+
+   sdhc2: sdhci@74a4900 {
+compatible = "qcom,sdhci-msm-v4";
+reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+index = <0x0>;
+bus-width = <4>;
+clock = < 0>;
+  

[U-Boot] [PATCH 05/05] db820c: stop autoboot when vol- pressed

[Jorge Ramirez-Ortiz]

Signed-off-by: Jorge Ramirez-Ortiz 
---
 arch/arm/dts/dragonboard820c-uboot.dtsi  | 19 
 board/qualcomm/dragonboard820c/dragonboard820c.c | 37 +++-
 include/configs/dragonboard820c.h|  2 ++
 3 files changed, 57 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/dragonboard820c-uboot.dtsi

diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi 
b/arch/arm/dts/dragonboard820c-uboot.dtsi
new file mode 100644
index 000..167e72c
--- /dev/null
+++ b/arch/arm/dts/dragonboard820c-uboot.dtsi
@@ -0,0 +1,19 @@
+/*
+ * U-Boot addition to handle Dragonboard 820c pins
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+_pon {
+   key_vol_down {
+   gpios = <_pon 1 0>;
+   label = "key_vol_down";
+   };
+
+   key_power {
+   gpios = <_pon 0 0>;
+   label = "key_power";
+   };
+};
diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c 
b/board/qualcomm/dragonboard820c/dragonboard820c.c
index 8f40ba4..d4a20d2 100644
--- a/board/qualcomm/dragonboard820c/dragonboard820c.c
+++ b/board/qualcomm/dragonboard820c/dragonboard820c.c
@@ -1,7 +1,7 @@
 /*
  * Board init file for Dragonboard 820C
  *
- * (C) Copyright 2017 Jorge Ramirez-Ortiz   
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -126,3 +127,37 @@ void reset_cpu(ulong addr)
 {
psci_system_reset();
 }
+
+/* Check for vol- button - if pressed - stop autoboot */
+int misc_init_r(void)
+{
+   struct udevice *pon;
+   struct gpio_desc resin;
+   int node, ret;
+
+   ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8994_pon@800", );
+   if (ret < 0) {
+   printf("Failed to find PMIC pon node. Check device tree\n");
+   return 0;
+   }
+
+   node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+ "key_vol_down");
+   if (node < 0) {
+   printf("Failed to find key_vol_down node. Check device tree\n");
+   return 0;
+   }
+
+   if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+  , 0)) {
+   printf("Failed to request key_vol_down button.\n");
+   return 0;
+   }
+
+   if (dm_gpio_get_value()) {
+   env_set("bootdelay", "-1");
+   printf("Power button pressed - dropping to console.\n");
+   }
+
+   return 0;
+}
diff --git a/include/configs/dragonboard820c.h 
b/include/configs/dragonboard820c.h
index 76bcaf8..e0c3c0c 100644
--- a/include/configs/dragonboard820c.h
+++ b/include/configs/dragonboard820c.h
@@ -12,6 +12,8 @@
 #include 
 #include 
 
+#define CONFIG_MISC_INIT_R /* To stop autoboot */
+
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS   2
 
-- 
2.7.4

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[U-Boot] [PATCH 04/05] db820c: enable pmic gpios for pm8994

[Jorge Ramirez-Ortiz]

Signed-off-by: Jorge Ramirez-Ortiz 
---
 arch/arm/dts/dragonboard820c.dts  | 43 +++
 configs/dragonboard820c_defconfig |  7 +++
 drivers/gpio/pm8916_gpio.c|  7 +--
 3 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index bad5a1e..3086d60 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -61,5 +61,48 @@
 clock = < 0>;
clock-frequency = <2>;
 };
+
+   spmi@400f000 {
+   compatible = "qcom,spmi-pmic-arb";
+   reg = <0x400f800 0x200>,
+ <0x440 0x40>,
+ <0x4c0 0x40>;
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+
+   pmic0: pm8994@0 {
+   compatible = "qcom,spmi-pmic";
+   reg = <0x0 0x1>;
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+
+   pm8994_pon: pm8994_pon@800 {
+   compatible = "qcom,pm8994-pwrkey";
+   reg = <0x800 0x96>;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-bank-name="pm8994_key.";
+   };
+
+   pm8994_gpios: pm8994_gpios@c000 {
+   compatible = "qcom,pm8994-gpio";
+   reg = <0xc000 0x400>;
+   gpio-controller;
+   gpio-count = <24>;
+   #gpio-cells = <2>;
+   gpio-bank-name="pm8994.";
+   };
+   };
+
+   pmic1: pm8994@1 {
+   compatible = "qcom,spmi-pmic";
+   reg = <0x1 0x1>;
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+   };
+   };
};
+
 };
+
+#include "dragonboard820c-uboot.dtsi"
diff --git a/configs/dragonboard820c_defconfig 
b/configs/dragonboard820c_defconfig
index 788ff28..5e25e2e 100644
--- a/configs/dragonboard820c_defconfig
+++ b/configs/dragonboard820c_defconfig
@@ -23,11 +23,18 @@ CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PMIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_MSM_SERIAL=y
+CONFIG_SPMI_MSM=y
 CONFIG_MMC_SDHCI_MSM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_DM_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PM8916=y
+CONFIG_PM8916_GPIO=y
 CONFIG_CLK=y
 CONFIG_PSCI_RESET=y
 CONFIG_ENV_IS_IN_EXT4=y
diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/pm8916_gpio.c
index 9ec2a24..056b982 100644
--- a/drivers/gpio/pm8916_gpio.c
+++ b/drivers/gpio/pm8916_gpio.c
@@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define REG_STATUS_VAL_MASK0x1
 
 /* MODE_CTL */
-#define REG_CTL   0x40
+#define REG_CTL0x40
 #define REG_CTL_MODE_MASK   0x70
 #define REG_CTL_MODE_INPUT  0x00
 #define REG_CTL_MODE_INOUT  0x20
@@ -183,7 +183,7 @@ static int pm8916_gpio_probe(struct udevice *dev)
return -ENODEV;
 
reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
-   if (reg != 0x5)
+   if (reg != 0x5 && reg != 0x1)
return -ENODEV;
 
return 0;
@@ -203,6 +203,7 @@ static int pm8916_gpio_ofdata_to_platdata(struct udevice 
*dev)
 
 static const struct udevice_id pm8916_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
+   { .compatible = "qcom,pm8994-gpio" },   /* 22 GPIO's */
{ }
 };
 
@@ -278,6 +279,7 @@ static int pm8941_pwrkey_ofdata_to_platdata(struct udevice 
*dev)
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 
uc_priv->gpio_count = 2;
+   uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
if (uc_priv->bank_name == NULL)
uc_priv->bank_name = "pm8916_key";
 
@@ -286,6 +288,7 @@ static int pm8941_pwrkey_ofdata_to_platdata(struct udevice 
*dev)
 
 static const struct udevice_id pm8941_pwrkey_ids[] = {
{ .compatible = "qcom,pm8916-pwrkey" },
+   { .compatible = "qcom,pm8994-pwrkey" },
{ }
 };
 
-- 
2.7.4

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[U-Boot] [PATCH 02/05] arm: mach-snapdragon: refactor clock driver

[Jorge Ramirez-Ortiz]

In preparation to add support for the Dragonboard820c (APQ8096),
refactor the current Snapdragon clock driver.

No new functionality has been added.

Signed-off-by: Jorge Ramirez-Ortiz 
---
 arch/arm/mach-snapdragon/Makefile  |   6 +-
 arch/arm/mach-snapdragon/clock-apq8016.c   | 181 ++---
 arch/arm/mach-snapdragon/clock-snapdragon.c| 134 +++
 arch/arm/mach-snapdragon/clock-snapdragon.h|  40 +
 .../mach-snapdragon/include/mach/sysmap-apq8016.h  |  29 +++-
 5 files changed, 217 insertions(+), 173 deletions(-)
 create mode 100644 arch/arm/mach-snapdragon/clock-snapdragon.c
 create mode 100644 arch/arm/mach-snapdragon/clock-snapdragon.h

diff --git a/arch/arm/mach-snapdragon/Makefile 
b/arch/arm/mach-snapdragon/Makefile
index d82a04d..74f90dc 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -4,5 +4,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += clock-apq8016.o
-obj-y += sysmap-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
+obj-y += clock-snapdragon.o
diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c 
b/arch/arm/mach-snapdragon/clock-apq8016.c
index da05015..a242417 100644
--- a/arch/arm/mach-snapdragon/clock-apq8016.c
+++ b/arch/arm/mach-snapdragon/clock-apq8016.c
@@ -14,146 +14,12 @@
 #include 
 #include 
 #include 
+#include "clock-snapdragon.h"
 
 /* GPLL0 clock control registers */
-#define GPLL0_STATUS0x2101C
 #define GPLL0_STATUS_ACTIVE BIT(17)
-
-#define APCS_GPLL_ENA_VOTE  0x45000
 #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
 
-/* vote reg for blsp1 clock */
-#define APCS_CLOCK_BRANCH_ENA_VOTE  0x45004
-#define APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1 BIT(10)
-
-/* SDC(n) clock control registers; n=1,2 */
-
-/* block control register */
-#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
-/* cmd */
-#define SDCC_CMD_RCGR(n)((n * 0x1000) + 0x41004)
-/* cfg */
-#define SDCC_CFG_RCGR(n)((n * 0x1000) + 0x41008)
-/* m */
-#define SDCC_M(n)   ((n * 0x1000) + 0x4100C)
-/* n */
-#define SDCC_N(n)   ((n * 0x1000) + 0x41010)
-/* d */
-#define SDCC_D(n)   ((n * 0x1000) + 0x41014)
-/* branch control */
-#define SDCC_APPS_CBCR(n)   ((n * 0x1000) + 0x41018)
-#define SDCC_AHB_CBCR(n)((n * 0x1000) + 0x4101C)
-
-/* BLSP1 AHB clock (root clock for BLSP) */
-#define BLSP1_AHB_CBCR  0x1008
-
-/* Uart clock control registers */
-#define BLSP1_UART2_BCR 0x3028
-#define BLSP1_UART2_APPS_CBCR   0x302C
-#define BLSP1_UART2_APPS_CMD_RCGR   0x3034
-#define BLSP1_UART2_APPS_CFG_RCGR   0x3038
-#define BLSP1_UART2_APPS_M  0x303C
-#define BLSP1_UART2_APPS_N  0x3040
-#define BLSP1_UART2_APPS_D  0x3044
-
-/* CBCR register fields */
-#define CBCR_BRANCH_ENABLE_BIT  BIT(0)
-#define CBCR_BRANCH_OFF_BIT BIT(31)
-
-struct msm_clk_priv {
-   phys_addr_t base;
-};
-
-/* Enable clock controlled by CBC soft macro */
-static void clk_enable_cbc(phys_addr_t cbcr)
-{
-   setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
-
-   while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
-   ;
-}
-
-/* clock has 800MHz */
-static void clk_enable_gpll0(phys_addr_t base)
-{
-   if (readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE)
-   return; /* clock already enabled */
-
-   setbits_le32(base + APCS_GPLL_ENA_VOTE, APCS_GPLL_ENA_VOTE_GPLL0);
-
-   while ((readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE) == 0)
-   ;
-}
-
-#define APPS_CMD_RGCR_UPDATE BIT(0)
-
-/* Update clock command via CMD_RGCR */
-static void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
-{
-   setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
-
-   /* Wait for frequency to be updated. */
-   while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
-   ;
-}
-
-struct bcr_regs {
-   uintptr_t cfg_rcgr;
-   uintptr_t cmd_rcgr;
-   uintptr_t M;
-   uintptr_t N;
-   uintptr_t D;
-};
-
-/* RCGR_CFG register fields */
-#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
-
-/* sources */
-#define CFG_CLK_SRC_CXO   (0 << 8)
-#define CFG_CLK_SRC_GPLL0 (1 << 8)
-#define CFG_CLK_SRC_MASK  (7 << 8)
-
-/* Mask for supported fields */
-#define CFG_MASK 0x3FFF
-
-#define CFG_DIVIDER_MASK 0x1F
-
-/* root set rate for clocks with half integer and MND divider */
-static void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
-int div, int m, int n, int source)
-{
-   uint32_t cfg;
-   /* M value for MND divider. */
-   uint32_t m_val = m;
-   /* NOT(N-M) value for MND divider. */
-   uint32_t n_val = ~((n)-(m)) * !!(n);
-   /* NOT 2D value for MND divider. */
-   uint32_t d_val = ~(n);
-
-   /* Program MND values */
-   writel(m_val, base + 

[U-Boot] [PATCH 01/05] env: enable accessing the environment in an EXT4 partition

[Jorge Ramirez-Ortiz]

For example to store the environment in a file named "/uboot.env" in MMC
"0", where partition "1" contains the EXT4 filesystem, the following
configs should be added to the board's default config:

  CONFIG_ENV_IS_IN_EXT4=y
  CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1"
  CONFIG_ENV_EXT4_FILE="/uboot.env"
  CONFIG_ENV_EXT4_INTERFACE="mmc"

Signed-off-by: Jorge Ramirez-Ortiz 
---
 env/Kconfig | 39 +++
 env/env.c   |  2 ++
 env/ext4.c  | 20 ++--
 3 files changed, 51 insertions(+), 10 deletions(-)

diff --git a/env/Kconfig b/env/Kconfig
index bef6e89..692f863 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -81,6 +81,13 @@ config ENV_IS_IN_FAT
  - CONFIG_FAT_WRITE:
  This must be enabled. Otherwise it cannot save the environment file.
 
+config ENV_IS_IN_EXT4
+   bool "Environment is in a EXT4 filesystem"
+   depends on !CHAIN_OF_TRUST
+   select EXT4_WRITE
+   help
+ Define this if you want to use the EXT4 file system for the 
environment.
+
 config ENV_IS_IN_FLASH
bool "Environment in flash memory"
depends on !CHAIN_OF_TRUST
@@ -396,6 +403,38 @@ config ENV_FAT_FILE
  It's a string of the FAT file name. This file use to store the
  environment.
 
+config ENV_EXT4_INTERFACE
+   string "Name of the block device for the environment"
+   depends on ENV_IS_IN_EXT4
+   help
+ Define this to a string that is the name of the block device.
+
+config ENV_EXT4_DEVICE_AND_PART
+   string "Device and partition for where to store the environemt in EXT4"
+   depends on ENV_IS_IN_EXT4
+   help
+ Define this to a string to specify the partition of the device. It can
+ be as following:
+
+   "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
+  - "D:P": device D partition P. Error occurs if device D has no
+   partition table.
+  - "D:0": device D.
+  - "D" or "D:": device D partition 1 if device D has partition
+ table, or the whole device D if has no partition
+ table.
+  - "D:auto": first partition in device D with bootable flag set.
+  If none, first valid partition in device D. If no
+  partition table then means device D.
+
+config ENV_EXT4_FILE
+   string "Name of the EXT4 file to use for the environemnt"
+   depends on ENV_IS_IN_EXT4
+   default "uboot.env"
+   help
+ It's a string of the EXT4 file name. This file use to store the
+ environment (explicit path to the file)
+
 if ARCH_SUNXI
 
 config ENV_OFFSET
diff --git a/env/env.c b/env/env.c
index 76a5608..7455632 100644
--- a/env/env.c
+++ b/env/env.c
@@ -32,6 +32,8 @@ static enum env_location env_get_default_location(void)
return ENVL_EEPROM;
else if IS_ENABLED(CONFIG_ENV_IS_IN_FAT)
return ENVL_FAT;
+   else if IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)
+   return ENVL_EXT4;
else if IS_ENABLED(CONFIG_ENV_IS_IN_FLASH)
return ENVL_FLASH;
else if IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
diff --git a/env/ext4.c b/env/ext4.c
index 6520221..07fd061 100644
--- a/env/ext4.c
+++ b/env/ext4.c
@@ -46,8 +46,8 @@ static int env_ext4_save(void)
if (err)
return err;
 
-   part = blk_get_device_part_str(EXT4_ENV_INTERFACE,
-   EXT4_ENV_DEVICE_AND_PART,
+   part = blk_get_device_part_str(CONFIG_ENV_EXT4_INTERFACE,
+   CONFIG_ENV_EXT4_DEVICE_AND_PART,
_desc, , 1);
if (part < 0)
return 1;
@@ -57,16 +57,16 @@ static int env_ext4_save(void)
 
if (!ext4fs_mount(info.size)) {
printf("\n** Unable to use %s %s for saveenv **\n",
-  EXT4_ENV_INTERFACE, EXT4_ENV_DEVICE_AND_PART);
+  CONFIG_ENV_EXT4_INTERFACE, 
CONFIG_ENV_EXT4_DEVICE_AND_PART);
return 1;
}
 
-   err = ext4fs_write(EXT4_ENV_FILE, (void *)_new, sizeof(env_t));
+   err = ext4fs_write(CONFIG_ENV_EXT4_FILE, (void *)_new, 
sizeof(env_t));
ext4fs_close();
 
if (err == -1) {
printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
-   EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
+   CONFIG_ENV_EXT4_FILE, CONFIG_ENV_EXT4_INTERFACE, dev, 
part);
return 1;
}
 
@@ -84,8 +84,8 @@ static int env_ext4_load(void)
int err;
loff_t off;
 
-   part = blk_get_device_part_str(EXT4_ENV_INTERFACE,
-   EXT4_ENV_DEVICE_AND_PART,
+   part = blk_get_device_part_str(CONFIG_ENV_EXT4_INTERFACE,
+   

[U-Boot] [PATCH 03/03] dm: core: parse chosen node

[Jorge Ramirez-Ortiz]

From: Rob Clark 

This is the node that would contain, for example, the framebuffer setup
by an earlier stage.

Signed-off-by: Rob Clark 
---
 arch/sandbox/dts/test.dts |  7 +++
 drivers/core/root.c   | 12 
 test/dm/bus.c |  2 +-
 test/dm/test-fdt.c|  2 +-
 4 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index e67d428..3f9e788 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -478,6 +478,13 @@
wdt0: wdt@0 {
compatible = "sandbox,wdt";
};
+
+   chosen {
+   chosen-test {
+   compatible = "denx,u-boot-fdt-test";
+   reg = <9 1>;
+   };
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 976e2c4..5a1c599 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -266,6 +266,18 @@ static int dm_scan_fdt_node(struct udevice *parent, const 
void *blob,
for (offset = fdt_first_subnode(blob, offset);
 offset > 0;
 offset = fdt_next_subnode(blob, offset)) {
+
+   /* "chosen" node isn't a device itself but may contain some: */
+   if (!strcmp(fdt_get_name(blob, offset, NULL), "chosen")) {
+   pr_debug("parsing subnodes of \"chosen\"\n");
+
+   err = dm_scan_fdt_node(parent, blob, offset,
+  pre_reloc_only);
+   if (err && !ret)
+   ret = err;
+   continue;
+   }
+
if (pre_reloc_only &&
!dm_fdt_pre_reloc(blob, offset))
continue;
diff --git a/test/dm/bus.c b/test/dm/bus.c
index 7006d41..1da398a 100644
--- a/test/dm/bus.c
+++ b/test/dm/bus.c
@@ -105,7 +105,7 @@ UCLASS_DRIVER(testbus) = {
 /* Test that we can probe for children */
 static int dm_test_bus_children(struct unit_test_state *uts)
 {
-   int num_devices = 6;
+   int num_devices = 7;
struct udevice *bus;
struct uclass *uc;
 
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index dcc2ef8..920ccbf 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -167,7 +167,7 @@ int dm_check_devices(struct unit_test_state *uts, int 
num_devices)
 /* Test that FDT-based binding works correctly */
 static int dm_test_fdt(struct unit_test_state *uts)
 {
-   const int num_devices = 6;
+   const int num_devices = 7;
struct udevice *dev;
struct uclass *uc;
int ret;
-- 
2.7.4

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[U-Boot] [PATCH 02/03] poplar: configs: increase gunzip buffer size for the kernel

[Jorge Ramirez-Ortiz]

Signed-off-by: Jorge Ramirez-Ortiz 
---
 include/configs/poplar.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/poplar.h b/include/configs/poplar.h
index 1c39ed1..8a12b52 100644
--- a/include/configs/poplar.h
+++ b/include/configs/poplar.h
@@ -18,7 +18,7 @@
 #define CONFIG_NR_DRAM_BANKS   2
 
 /* SYS */
-#define CONFIG_SYS_BOOTM_LEN   0x140
+#define CONFIG_SYS_BOOTM_LEN   SZ_64M
 #define CONFIG_SYS_INIT_SP_ADDR0x20
 #define CONFIG_SYS_LOAD_ADDR   0x80
 #define CONFIG_SYS_MALLOC_LEN  SZ_32M
-- 
2.7.4

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[U-Boot] [PATCH 01/03] spmi: msm: display the PMIC Arb version (debug)

[Jorge Ramirez-Ortiz]

Signed-off-by: Jorge Ramirez-Ortiz 
---
 drivers/spmi/spmi-msm.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index c226913..e9bfbb0 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -17,6 +17,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+
+/* PMIC Arbiter configuration registers */
+#define PMIC_ARB_VERSION   0x
+#define PMIC_ARB_VERSION_V2_MIN0x2001
+
 #define ARB_CHANNEL_OFFSET(n)  (0x4 * (n))
 #define SPMI_CH_OFFSET(chnl)   ((chnl) * 0x8000)
 
@@ -148,6 +153,8 @@ static int msm_spmi_probe(struct udevice *dev)
struct udevice *parent = dev->parent;
struct msm_spmi_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
+   u32 hw_ver;
+   bool is_v1;
int i;
 
priv->arb_chnl = devfdt_get_addr(dev);
@@ -155,6 +162,12 @@ static int msm_spmi_probe(struct udevice *dev)
dev_of_offset(parent), node, "reg", 1, NULL, false);
priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
dev_of_offset(parent), node, "reg", 2, NULL, false);
+
+   hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800);
+   is_v1  = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
+
+   dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver);
+
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
priv->spmi_core == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/3] imx: move CONFIG_SYSCOUNTER_TIMER to Kconfig

[Stefan Agner]

Hi Stefano,

Any chance to get this patchset still into v2018.01? IMHO it is almost a
bug that U-Boot does not initialize the ARM architected timer
properly...

--
Stefan


On 2018-01-02 01:43, Stefan Agner wrote:
> Signed-off-by: Stefan Agner 
> ---
> 
>  arch/arm/mach-imx/Kconfig | 3 +++
>  arch/arm/mach-imx/mx7/Kconfig | 1 +
>  include/configs/mx7_common.h  | 1 -
>  scripts/config_whitelist.txt  | 1 -
>  4 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index e687048b31..653819123c 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -7,6 +7,9 @@ config IMX_CONFIG
>  config ROM_UNIFIED_SECTIONS
>   bool
>  
> +config SYSCOUNTER_TIMER
> + bool
> +
>  config IMX_RDC
>   bool "i.MX Resource domain controller driver"
>   depends on ARCH_MX6 || ARCH_MX7
> diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
> index 4f8b4e138e..2a3db860bb 100644
> --- a/arch/arm/mach-imx/mx7/Kconfig
> +++ b/arch/arm/mach-imx/mx7/Kconfig
> @@ -3,6 +3,7 @@ if ARCH_MX7
>  config MX7
>   bool
>   select ROM_UNIFIED_SECTIONS
> + select SYSCOUNTER_TIMER
>   select CPU_V7_HAS_VIRT
>   select CPU_V7_HAS_NONSEC
>   select ARCH_SUPPORT_PSCI
> diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
> index 16e4d95ff4..17850400c1 100644
> --- a/include/configs/mx7_common.h
> +++ b/include/configs/mx7_common.h
> @@ -19,7 +19,6 @@
>  
>  /* Timer settings */
>  #define CONFIG_MXC_GPT_HCLK
> -#define CONFIG_SYSCOUNTER_TIMER
>  #define CONFIG_SC_TIMER_CLK 800 /* 8Mhz */
>  #define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
>  #define CONFIG_SYS_FSL_CLK
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index 43a4ff0892..5d8d907cc4 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -2219,7 +2219,6 @@ CONFIG_SUPPORT_RAW_INITRD
>  CONFIG_SUPPORT_VFAT
>  CONFIG_SUVD3
>  CONFIG_SXNI855T
> -CONFIG_SYSCOUNTER_TIMER
>  CONFIG_SYSFLAGS_ADDR
>  CONFIG_SYSFS
>  CONFIG_SYSMGR_ISWGRP_HANDOFF
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Re: [U-Boot] [PATCH 00/11] sunxi: arm64 binary size fixes

[Jagan Teki]

On Fri, Jan 5, 2018 at 3:30 PM, Maxime Ripard
 wrote:
> On Thu, Jan 04, 2018 at 10:58:16AM +0530, Jagan Teki wrote:
>> Maxime,
>>
>> On Thu, Dec 21, 2017 at 6:10 PM, Maxime Ripard
>>  wrote:
>> > Hi,
>> >
>> > As we discussed already, this is the list of options that we will need
>> > to disable by default.
>> >
>> > I also added to the mix a size check, which even though it's not
>> > really optimal, is temporary and will be removed in a future (and
>> > hopefully close) release.
>> >
>> > Tom, is this still something we can merge for 2018.01?
>> >
>> > Thanks!
>> > Maxime
>> >
>> > Andre Heider (1):
>> >   sunxi: imply CONFIG_OF_LIBFDT_OVERLAY
>> >
>> > Maxime Ripard (10):
>> >   cmd: crc32: Disable by default on sunXi
>> >   cmd: unzip: Disable by default on sunXi
>> >   cmd: loadb: Disable by default on sunXi
>> >   cmd: loads: Disable by default on sunXi
>> >   cmd: misc: Disable by default on sunXi
>> >   video: bpp8: Disable by default on sunXi
>> >   video: bpp16: Disable by default on sunXi
>> >   net: regex: Disable by default on sunXi
>> >   Makefile: Add size check to the u-boot.itb make target
>> >   sunxi: Add limit with the MMC environment
>>
>> based on the conversation on individual patches, I think all these
>> need to change only for 64-bit sunxi boards for now and we can push
>> this for the release if all fine.
>
> As far as I'm concerned, these patches can be merged as is.

I've no issues with this series if it goes to next version, since we
have time to validate. But I'm thinking to push these asap to merge
them in coming release in two days, it would be good to untouch 32-bit
stuff at last minute.
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Re: [U-Boot] [PATCH 00/11] sunxi: arm64 binary size fixes

[Maxime Ripard]

On Thu, Jan 04, 2018 at 10:58:16AM +0530, Jagan Teki wrote:
> Maxime,
> 
> On Thu, Dec 21, 2017 at 6:10 PM, Maxime Ripard
>  wrote:
> > Hi,
> >
> > As we discussed already, this is the list of options that we will need
> > to disable by default.
> >
> > I also added to the mix a size check, which even though it's not
> > really optimal, is temporary and will be removed in a future (and
> > hopefully close) release.
> >
> > Tom, is this still something we can merge for 2018.01?
> >
> > Thanks!
> > Maxime
> >
> > Andre Heider (1):
> >   sunxi: imply CONFIG_OF_LIBFDT_OVERLAY
> >
> > Maxime Ripard (10):
> >   cmd: crc32: Disable by default on sunXi
> >   cmd: unzip: Disable by default on sunXi
> >   cmd: loadb: Disable by default on sunXi
> >   cmd: loads: Disable by default on sunXi
> >   cmd: misc: Disable by default on sunXi
> >   video: bpp8: Disable by default on sunXi
> >   video: bpp16: Disable by default on sunXi
> >   net: regex: Disable by default on sunXi
> >   Makefile: Add size check to the u-boot.itb make target
> >   sunxi: Add limit with the MMC environment
> 
> based on the conversation on individual patches, I think all these
> need to change only for 64-bit sunxi boards for now and we can push
> this for the release if all fine.

As far as I'm concerned, these patches can be merged as is.

Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [U-Boot] [PATCH 01/11] cmd: crc32: Disable by default on sunXi

[Maxime Ripard]

Hi Andre,

On Thu, Dec 21, 2017 at 02:50:29PM +, Andre Przywara wrote:
> Hi,
> 
> On 21/12/17 12:40, Maxime Ripard wrote:
> > The sunXi arm64 build has overflown, leading to the main U-boot binary
> > overwriting the environment when flashing the new image, or even worse,
> > overwriting itself when we're calling saveenv.
> > 
> > Disable this command that is not critical until we can adress the issue
> > properly.
> > 
> > Signed-off-by: Maxime Ripard 
> > ---
> >  cmd/Kconfig | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/cmd/Kconfig b/cmd/Kconfig
> > index c0332235261f..7751001819d0 100644
> > --- a/cmd/Kconfig
> > +++ b/cmd/Kconfig
> > @@ -397,6 +397,7 @@ menu "Memory commands"
> >  config CMD_CRC32
> > bool "crc32"
> > select HASH
> > +   default n if ARCH_SUNXI
> 
> Is that meant to solve issues with 32 bit boards as well? Or shall we
> use "ARCH_SUNXI && ARM64" here?
> 
> In case including 32-bit is intentional, this is:
> 
> for [PATCH 01/11] - [PATCH 04/11]:
> Reviewed-by: Andre Przywara 

This is intentional. I really want to have an experience as close as
possible on the arm and arm64 boards, and having the same commands set
is one of the things that matter to achieve that :)

> If no one shoot any of those options down, you might want to squash them
> into one patch, since they all go into the same file.

That works for me :)

> Unless you need to meet some company patch count target before the end
> of the year :-D

I guess I missed that deadline already... ;)

> P.S. Shall we mark those patches somehow, so that we can easily revert
> them later? Those commands can be useful.

That might be a good idea. Do you have a suggestion?

Maxime

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[U-Boot] [RFC PATCH] mtd: spi-nor: add rockchip sfc driver

[Andy Yan]

SFC stands for Serial Flash Controller on some
rockchip platforms such as RV1108 / RK3128.

This patch add support for it under mtd/spi-nor
framework

Signed-off-by: Andy Yan 

---

 drivers/mtd/spi-nor/Kconfig|   8 +
 drivers/mtd/spi-nor/Makefile   |   1 +
 drivers/mtd/spi-nor/rockchip_sfc.c | 432 +
 3 files changed, 441 insertions(+)
 create mode 100644 drivers/mtd/spi-nor/rockchip_sfc.c

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index fb53afb..07e9b18 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -55,6 +55,14 @@ config MTD_ZYNQ_QSPI
  Zynq QSPI IP core. This IP is used to connect the flash in
  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
 
+config MTD_ROCKCHIP_SFC
+   bool "Rockchip SFC driver"
+   depends on ARCH_ROCKCHIP
+   help
+ Enable the Rockchip SFC(Serial Flash Controller). This driver
+ can be used to access the SPI NOR flash with standard SPI,
+ dual SPI and quad SPI mode.
+
 config SPI_NOR_MISC
bool "Miscellaneous SPI NOR flash's support"
help
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index ded3bfa..2c4577f 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_MTD_M25P80)  += m25p80.o
 
 ## spi-nor drivers
 obj-$(CONFIG_MTD_ZYNQ_QSPI)+= zynq_qspinor.o
+obj-$(CONFIG_MTD_ROCKCHIP_SFC)  += rockchip_sfc.o
diff --git a/drivers/mtd/spi-nor/rockchip_sfc.c 
b/drivers/mtd/spi-nor/rockchip_sfc.c
new file mode 100644
index 000..fc880b3
--- /dev/null
+++ b/drivers/mtd/spi-nor/rockchip_sfc.c
@@ -0,0 +1,432 @@
+/*
+ * Rockchip SPI-NOR flash controller driver
+ *
+ * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+/* SFC_CTRL */
+#define SFC_DATA_WIDTH_SHIFT   12
+#define SFC_DATA_WIDTH_MASKGENMASK(13, 12)
+#define SFC_ADDR_WIDTH_SHIFT   10
+#define SFC_ADDR_WIDTH_MASKGENMASK(11, 10)
+#define SFC_CMD_WIDTH_SHIFT8
+#define SFC_CMD_WIDTH_MASK GENMASK(9, 8)
+#define SFC_DATA_SHIFT_NEGETIVEBIT(1)
+
+/* SFC_CMD */
+#define SFC_READ_DUMMY_SHIFT   8
+#define SFC_RDWR_SHIFT 12
+#define SFC_WR 1
+#define SFC_RD 0
+#define SFC_ADDR_0BITS (0 << 14)
+#define SFC_ADDR_24BITS(1 << 14)
+#define SFC_ADDR_32BITS(2 << 14)
+#define SFC_ADDR_XBITS (3 << 14)
+#define SFC_TRB_SHIFT  (16)
+#define SFC_TRB_MASK   GENMASK(29, 16)
+
+/* Dma start trigger signal. Auto cleared after write */
+#define SFC_DMA_START  BIT(0)
+
+#define SFC_RESET  BIT(0)
+
+/* SFC_FSR */
+#define SFC_RXLV_SHIFT (16)
+#define SFC_RXLV_MASK  GENMASK(20, 16)
+#define SFC_TXLV_SHIFT (8)
+#define SFC_TXLV_MASK  GENMASK(12, 8)
+#define SFC_RX_FULLBIT(3)  /* rx fifo full */
+#define SFC_RX_EMPTY   BIT(2)  /* rx fifo empty */
+#define SFC_TX_EMPTY   BIT(1)  /* tx fifo empty */
+#define SFC_TX_FULLBIT(0)  /* tx fifo full */
+
+#define SFC_BUSY   BIT(0)  /* sfc busy flag */
+
+/* SFC_RISR */
+#define DMA_FINISH_INT BIT(7)/* dma interrupt */
+#define SPI_ERR_INTBIT(6)/* Nspi error interrupt */
+#define AHB_ERR_INTBIT(5)/* Ahb bus error interrupt */
+#define TRANS_FINISH_INT   BIT(4)/* Transfer finish interrupt */
+#define TX_EMPTY_INT   BIT(3)/* Tx fifo empty interrupt */
+#define TX_OF_INT  BIT(2)/* Tx fifo overflow interrupt */
+#define RX_UF_INT  BIT(1)/* Rx fifo underflow interrupt */
+#define RX_FULL_INTBIT(0)/* Rx fifo full interrupt */
+
+#define SFC_MAX_TRB(15 * 1024)
+
+enum rockchip_sfc_if_type {
+   IF_TYPE_STD,
+   IF_TYPE_DUAL,
+   IF_TYPE_QUAD,
+};
+
+struct rockchip_sfc_regs {
+   u32 ctrl;
+   u32 imr;
+   u32 iclr;
+   u32 ftlr;
+   u32 rcvr;
+   u32 ax;
+   u32 abit;
+   u32 isr;
+   u32 fsr;
+   u32 sr;
+   u32 risr;
+   u32 reserved[21];
+   u32 dmatr;
+   u32 dmaaddr;
+   u32 reserved1[30];
+   u32 cmd;
+   u32 addr;
+   u32 data;
+};
+check_member(rockchip_sfc_regs, data, 0x108);
+
+struct rockchip_sfc {
+   struct udevice *dev;
+   struct rockchip_sfc_regs *base;
+};
+
+struct rockchip_sfc_platdata {
+   struct spi_nor spi_nor;
+};
+
+static u8 rockchip_sfc_get_if_type(struct spi_nor *nor)
+{
+   if (nor->read_opcode == SNOR_OP_READ ||
+   nor->read_opcode == SNOR_OP_READ_FAST)
+   return IF_TYPE_STD;
+   else if (nor->read_opcode == SNOR_OP_READ_1_1_2)
+   return IF_TYPE_DUAL;
+   else if 

[U-Boot] [RFC PATCH 0/1] Add Rockchip SFC driver under mtd/spi-nor framework

[Andy Yan]

Hi:
 Jagan, very glad to see the update of your SNI-NOR
series. So I send the Rockchip SFC(Serial Flash Controller)
driver base on it. Comments are appreciate.


Andy Yan (1):
  mtd: spi-nor: add rockchip sfc driver

 drivers/mtd/spi-nor/Kconfig|   8 +
 drivers/mtd/spi-nor/Makefile   |   1 +
 drivers/mtd/spi-nor/rockchip_sfc.c | 432 +
 3 files changed, 441 insertions(+)
 create mode 100644 drivers/mtd/spi-nor/rockchip_sfc.c

-- 
2.7.4


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Re: [U-Boot] [PATCH 11/11] sunxi: Add limit with the MMC environment

[Maxime Ripard]

On Fri, Dec 22, 2017 at 02:34:35PM +0530, Jagan Teki wrote:
> On Fri, Dec 22, 2017 at 2:18 PM, Maxime Ripard
>  wrote:
> > On Thu, Dec 21, 2017 at 10:52:04PM +, André Przywara wrote:
> >> Hi,
> >>
> >> On 21/12/17 12:40, Maxime Ripard wrote:
> >> > The MMC environment offset is getting very close to the end of the U-Boot
> >> > binary now. Since we want to make sure this will not overflow, add a size
> >> > limit in the board for arm64. arm32 has already that limit enforced in 
> >> > our
> >> > custom image generation.
> >> >
> >> > Signed-off-by: Maxime Ripard 
> >> > ---
> >> >  include/configs/sunxi-common.h | 10 ++
> >> >  1 file changed, 10 insertions(+)
> >> >
> >> > diff --git a/include/configs/sunxi-common.h 
> >> > b/include/configs/sunxi-common.h
> >> > index 3855c564f914..6236e129a89d 100644
> >> > --- a/include/configs/sunxi-common.h
> >> > +++ b/include/configs/sunxi-common.h
> >> > @@ -147,6 +147,16 @@
> >> >  #endif
> >> >
> >> >  #if defined(CONFIG_ENV_IS_IN_MMC)
> >> > +
> >> > +#ifdef CONFIG_ARM64
> >>
> >> Why is that? Isn't the limit applicable to all sunxi boards using MMC
> >> env? Maybe that's actually the better check (thanks for digging this up,
> >> btw)? I guess this would avoid to break compatibility with older
> >> sunxi-fel versions (those provided by distros not carrying your fix),
> >> also avoids blowing up u-boot-sunxi-with-spl.bin to 504K always?
> >>
> >> Or does this break anything on 32-bit boards?
> >
> > So there's a couple of arguments there, which are probably all a bit
> > weak, but the sum of them made me do it that way:
> >   - I tried to keep the changes as minimal as possible since it's
> > going to be fixes, in one of the late -rc's. We know that the
> > arm32 part works, so I didn't really want to disrupt that.
> >   - It's not really optimal, as the expression is used directly in the
> > Makefile and therefore any arithmetic operations can't really be
> > done. The arm32 part can, and is therefore correct in all
> > cases. Here we just bet that the user will never have changed one
> > of the values.
> 
> Based on the previous conversion, 2018.05 or future version will
> increase the u-boot partition size. Do we really need this in between
> which will anyway removed.

Yes, otherwise we might end up again in a situation where we'll allow
the compilation of a broken binary.

Maxime

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Re: [U-Boot] [PATCH 12/14] env: Mark env_get_location as weak

[Maxime Ripard]

Hi Simon,

On Thu, Dec 28, 2017 at 08:13:42PM -0700, Simon Glass wrote:
> Hi Maxime,
> 
> On 28 November 2017 at 03:24, Maxime Ripard
>  wrote:
> > Allow boards and architectures to override the default environment lookup
> > code by overriding env_get_location.
> >
> > Reviewed-by: Lukasz Majewski 
> > Signed-off-by: Maxime Ripard 
> > ---
> >  env/env.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/env/env.c b/env/env.c
> > index b4d8886e7a69..9b8b38cf3c2b 100644
> > --- a/env/env.c
> > +++ b/env/env.c
> > @@ -62,7 +62,7 @@ static enum env_location env_locations[] = {
> >
> >  static enum env_location env_load_location;
> >
> > -static enum env_location env_get_location(enum env_operation op, int prio)
> > +__weak enum env_location env_get_location(enum env_operation op, int prio)
> 
> Is it possible instead to make this deterministic, so that the board
> sets up the location during boot?

I'm not really sure what you mean here. The default implementation is
deterministic, and the board implementations should make sure that it
is if it's of any value to them.

Do you want me to add a comment to make that clearer?

Thanks!
Maxime

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Re: [U-Boot] [PATCH 03/14] env: Pass additional parameters to the env lookup function

[Maxime Ripard]

Hi Simon,

On Thu, Dec 28, 2017 at 08:13:23PM -0700, Simon Glass wrote:
> > -static struct env_driver *env_driver_lookup(void)
> > +static struct env_driver *env_driver_lookup(enum env_operation op, int 
> > prio)
> 
> Can you please document the function args? The operation of prio needs
> to be described somewhere.

Will do.

> >  {
> > -   enum env_location loc = env_get_location();
> > +   enum env_location loc = env_get_location(op, prio);
> > struct env_driver *drv;
> >
> > +   if (loc == ENVL_UNKNOWN)
> > +   return NULL;
> 
> Why is this needed? Shouldn't _env_driver_lookup() return NULL in this
> case anyway?

I just thought that making it obvious and explicit (especially when
the behaviour of _env_driver_lookup might change) would be a good
thing, but I can remove it if you want.

> > -   if (!drv)
> > -   return -ENODEV;
> > -   if (!drv->save)
> > -   return -ENOSYS;
> > -
> > -   printf("Saving Environment to %s...\n", drv->name);
> > -   ret = drv->save();
> > -   if (ret) {
> > -   debug("%s: Environment failed to save (err=%d)\n", __func__,
> > - ret);
> > -   return ret;
> > +   for (prio = 0; (drv = env_driver_lookup(ENVO_SAVE, prio)); prio++) {
> > +   int ret;
> > +
> > +   if (!drv->save)
> > +   continue;
> > +
> > +   printf("Saving Environment to %s...\n", drv->name);
> > +   ret = drv->save();
> > +   if (!ret)
> > +   return 0;
> 
> So we get no advice of error? I think it should print a message here,
> like ...failed or ...done.

This is addressed in the next patch

> Also if no driver succeeded I suggest returning one of the errors
> returned from drv-save().

And this was one of the comments made in this version, so it's going
to be addressed in the next iteration.

> > --- a/include/environment.h
> > +++ b/include/environment.h
> > @@ -215,6 +215,13 @@ enum env_location {
> > ENVL_UNKNOWN,
> >  };
> >
> 
> comment here
> 
> > +enum env_operation {
> > +   ENVO_GET_CHAR,
> 
> I think ENVOP would be a better prefix.

That works for me. Thanks!
Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [U-Boot] [PATCH 0/6] Add Bananapi Zero board with OTG supported

[Chen-Yu Tsai]

On Fri, Jan 5, 2018 at 5:20 PM, Jun Nie  wrote:
> 2018-01-05 17:06 GMT+08:00 Chen-Yu Tsai :
>> On Fri, Jan 5, 2018 at 5:04 PM, Jun Nie  wrote:

 a64 on otg have in ML[1] check if any redundant otherwise it's OK., we
 will test these and send next version.

>   sunxi: Add initial Banana-Pi Zero support

 similar patch is already in ML [2]

 [1] https://patchwork.ozlabs.org/cover/847375/
>>>
>>> This serial patches in the link does not introduce any redundant
>>> change with my USB patches. So my patches 1-5 still deserve review.
>>> Conflict should be resolve of course because some change is made in
>>> the same line.
>>>
>>> Two points for patches in the link:
>>> - SUNXI_MUSB_BASE is redefined with the patches in the link for H3
>>> configuration in my test.
>>> - Some coding style conflict with u-boot, such as USBC_SelectPhyToDevice.
>>
>> I have some similar patches here:
>>
>> https://github.com/wens/u-boot-sunxi/commits/libretech-cc
>>
>> ChenYu
>
> ChenYu,
>
> Are you patches are in review process or merge process? When do you
> expected they are merged?

So far only "musb: sunxi: Use base address from device tree" has been
sent out and was already reviewed, but pending. The rest I've not sent
as I was still trying to get it to work in peripheral mode.

Feel free to pick any of the patches if they suit your needs.

ChenYu
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Re: [U-Boot] [PATCH 0/6] Add Bananapi Zero board with OTG supported

[Jun Nie]

2018-01-05 17:06 GMT+08:00 Chen-Yu Tsai :
> On Fri, Jan 5, 2018 at 5:04 PM, Jun Nie  wrote:
>>>
>>> a64 on otg have in ML[1] check if any redundant otherwise it's OK., we
>>> will test these and send next version.
>>>
   sunxi: Add initial Banana-Pi Zero support
>>>
>>> similar patch is already in ML [2]
>>>
>>> [1] https://patchwork.ozlabs.org/cover/847375/
>>
>> This serial patches in the link does not introduce any redundant
>> change with my USB patches. So my patches 1-5 still deserve review.
>> Conflict should be resolve of course because some change is made in
>> the same line.
>>
>> Two points for patches in the link:
>> - SUNXI_MUSB_BASE is redefined with the patches in the link for H3
>> configuration in my test.
>> - Some coding style conflict with u-boot, such as USBC_SelectPhyToDevice.
>
> I have some similar patches here:
>
> https://github.com/wens/u-boot-sunxi/commits/libretech-cc
>
> ChenYu

ChenYu,

Are you patches are in review process or merge process? When do you
expected they are merged?

Jun
>
>>> [2] https://patchwork.ozlabs.org/patch/832937/
>>
>> This patch can replace my patch 6 and please ignore my patch 6.
>>
>> Jun
>>>
>>> --
>>> Jagan Teki
>>> Free Software Engineer | www.openedev.com
>>> U-Boot, Linux | Upstream Maintainer
>>> Hyderabad, India.
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Re: [U-Boot] [PATCH 2/6] sunxi: musb: Add fifo config for H3

[Jagan Teki]

On Fri, Jan 5, 2018 at 1:06 PM, Jun Nie  wrote:
> Add fifo config for H3 as H3 differ with other SoC
> on ep number.
>
> Signed-off-by: Jun Nie 
> ---

Reviewed-by: Jagan Teki 
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Re: [U-Boot] [PATCH 1/6] sunxi: h3: add usb_otg and OHCI/EHCI for usbc0 on H3

[Jagan Teki]

On Fri, Jan 5, 2018 at 1:06 PM, Jun Nie  wrote:
> Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
> or MUSB controller.

Since these nodes are from Linux, mention the similar text on commit
message and head like "syncing [o-e]hci nodes from Linux' are similar.
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Re: [U-Boot] [PATCH 0/6] Add Bananapi Zero board with OTG supported

[Chen-Yu Tsai]

On Fri, Jan 5, 2018 at 5:04 PM, Jun Nie  wrote:
>>
>> a64 on otg have in ML[1] check if any redundant otherwise it's OK., we
>> will test these and send next version.
>>
>>>   sunxi: Add initial Banana-Pi Zero support
>>
>> similar patch is already in ML [2]
>>
>> [1] https://patchwork.ozlabs.org/cover/847375/
>
> This serial patches in the link does not introduce any redundant
> change with my USB patches. So my patches 1-5 still deserve review.
> Conflict should be resolve of course because some change is made in
> the same line.
>
> Two points for patches in the link:
> - SUNXI_MUSB_BASE is redefined with the patches in the link for H3
> configuration in my test.
> - Some coding style conflict with u-boot, such as USBC_SelectPhyToDevice.

I have some similar patches here:

https://github.com/wens/u-boot-sunxi/commits/libretech-cc

ChenYu

>> [2] https://patchwork.ozlabs.org/patch/832937/
>
> This patch can replace my patch 6 and please ignore my patch 6.
>
> Jun
>>
>> --
>> Jagan Teki
>> Free Software Engineer | www.openedev.com
>> U-Boot, Linux | Upstream Maintainer
>> Hyderabad, India.
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Re: [U-Boot] [PATCH 0/6] Add Bananapi Zero board with OTG supported

[Jun Nie]

>
> a64 on otg have in ML[1] check if any redundant otherwise it's OK., we
> will test these and send next version.
>
>>   sunxi: Add initial Banana-Pi Zero support
>
> similar patch is already in ML [2]
>
> [1] https://patchwork.ozlabs.org/cover/847375/

This serial patches in the link does not introduce any redundant
change with my USB patches. So my patches 1-5 still deserve review.
Conflict should be resolve of course because some change is made in
the same line.

Two points for patches in the link:
- SUNXI_MUSB_BASE is redefined with the patches in the link for H3
configuration in my test.
- Some coding style conflict with u-boot, such as USBC_SelectPhyToDevice.

> [2] https://patchwork.ozlabs.org/patch/832937/

This patch can replace my patch 6 and please ignore my patch 6.

Jun
>
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com
> U-Boot, Linux | Upstream Maintainer
> Hyderabad, India.
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Re: [U-Boot] [PATCH 6/6] sunxi: Add initial Banana-Pi Zero support

[Jun Nie]

>> +/dts-v1/;
>> +#include "sun8i-h3.dtsi"
>> +#include "sunxi-common-regulators.dtsi"
>> +
>> +#include 
>> +#include 
>
> Where is that DT coming from?
>
> Usually, we'll just merge a DT merged in Linux.

The DT come from Linux but modified with removing necessary nodes.
>
>> +/ {
>> + model = "Banana Pi BPI-M2-Zero";
>> + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
>> +
>> + aliases {
>> + serial0 = 
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + pinctrl-names = "default";
>> +
>> + pwr_led {
>> + label = "bananapi-m2-zero:red:pwr";
>> + gpios = <_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
>> + default-state = "on";
>> + };
>> + };
>> +
>> + gpio_keys {
>> + compatible = "gpio-keys";
>> + pinctrl-names = "default";
>> +
>> + sw4 {
>> + label = "power";
>> + linux,code = ;
>> + gpios = <_pio 0 3 GPIO_ACTIVE_LOW>;
>> + };
>> + };
>> +};
>> +
>> + {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <_pins_a>;
>> + vmmc-supply = <_vcc3v3>;
>> + bus-width = <4>;
>> + /*
>> +  * In different revisions the board have different card detect
>> +  * configuration.
>> +  */
>> + broken-cd;
>> + status = "okay";
>> +};
>> +
>> + {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <_pins_a>;
>> + status = "okay";
>> +};
>> +
>> +_otg {
>> + dr_mode = "otg";
>> + status = "okay";
>> +};
>> +
>> + {
>> + usb0_id_det-gpios = <_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
>> + /* USB OTG VBUS is directly connected to 5V without any regulators */
>
> Then it cannot really do OTG, but rather only peripheral (or host, if
> the power is provided by the board).

Right, and working mode in u-boot is decided in compile time,
CONFIG_USB_MUSB_HOST.

>
>> + status = "okay";
>> +};
>> diff --git a/configs/bananapi_zero_defconfig 
>> b/configs/bananapi_zero_defconfig
>> new file mode 100644
>> index 000..9c78b21
>> --- /dev/null
>> +++ b/configs/bananapi_zero_defconfig
>> @@ -0,0 +1,17 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_SUNXI=y
>> +CONFIG_MACH_SUN8I_H3=y
>> +CONFIG_DRAM_CLK=408
>> +CONFIG_DRAM_ZQ=3881979
>> +CONFIG_DRAM_ODT_EN=y
>> +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-m2-zero"
>> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>> +CONFIG_SPL=y
>> +# CONFIG_CMD_FLASH is not set
>> +# CONFIG_CMD_FPGA is not set
>> +CONFIG_CMD_USB_MASS_STORAGE=y
>
> This shouldn't be enabled in the defconfig.

Thanks for pointing out! Is there any guidance, where DTS should come
from, what defconfig shall include, ...?  I am new to u-boot :-)

>
> The rest of the serie looks good, thanks!
> Maxime


Thanks for review!
Jun
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Re: [U-Boot] [PATCH 6/6] sunxi: Add initial Banana-Pi Zero support

[Maxime Ripard]

Hi Jun,

On Fri, Jan 05, 2018 at 03:37:01PM +0800, Jun Nie wrote:
> Banana-Pi Zero is designed for IOT development
> using the Allwinner H2+ SOC.
> 
> Key features
> - Allwinner H2+, Quad-core Cortex-A7
> - 512MB DRAM
> - microSD slot
> - Serial Debug Port
> - Combo WiFi/BT
> - HDMI
> 
> Signed-off-by: Jun Nie 
> ---
>  arch/arm/dts/Makefile   |   1 +
>  arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 113 
> 
>  configs/bananapi_zero_defconfig |  17 
>  3 files changed, 131 insertions(+)
>  create mode 100644 arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
>  create mode 100644 configs/bananapi_zero_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index a895c70..80eec7e 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -327,6 +327,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
>   sun8i-a83t-cubietruck-plus.dtb \
>   sun8i-a83t-tbs-a711.dts
>  dtb-$(CONFIG_MACH_SUN8I_H3) += \
> + sun8i-h2-plus-bananapi-m2-zero.dtb \
>   sun8i-h2-plus-orangepi-zero.dtb \
>   sun8i-h3-bananapi-m2-plus.dtb \
>   sun8i-h3-orangepi-2.dtb \
> diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts 
> b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
> new file mode 100644
> index 000..4d96c16
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
> @@ -0,0 +1,113 @@
> +/*
> + * Copyright (C) 2017 Jun Nie 
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-h3.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include 
> +#include 

Where is that DT coming from?

Usually, we'll just merge a DT merged in Linux.

> +/ {
> + model = "Banana Pi BPI-M2-Zero";
> + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
> +
> + aliases {
> + serial0 = 
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> +
> + pwr_led {
> + label = "bananapi-m2-zero:red:pwr";
> + gpios = <_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
> + default-state = "on";
> + };
> + };
> +
> + gpio_keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> +
> + sw4 {
> + label = "power";
> + linux,code = ;
> + gpios = <_pio 0 3 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins_a>;
> + vmmc-supply = <_vcc3v3>;
> + bus-width = <4>;
> + /*
> +  * In different revisions the board have different card detect
> +  * configuration.
> +  */
> + broken-cd;
> + status = "okay";
> +};
> +
> + {
> + 

Re: [U-Boot] [PATCH 0/6] Add Bananapi Zero board with OTG supported

[Jun Nie]

Thank you very much! Will check.

Jun
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