Re: [U-Boot] [PATCH 4/6] x86: tsc: Try hardware calibration first
Am Fr., 10. Aug. 2018 um 11:40 Uhr schrieb Bin Meng :
>
> At present if TSC frequency is provided in the device tree, it takes
> precedence over hardware calibration result. This swaps the order to
> try hardware calibration first and uses device tree as last resort.
>
> This can be helpful when a generic dts (eg: coreboot/efi payload) is
> supposed to work on as many hardware as possible, including emulators
> like QEMU where TSC hardware calibration sometimes fails.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/timer/tsc_timer.c | 27 ---
> 1 file changed, 16 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> index 747f190..6473de2 100644
> --- a/drivers/timer/tsc_timer.c
> +++ b/drivers/timer/tsc_timer.c
> @@ -341,16 +341,12 @@ static int tsc_timer_get_count(struct udevice *dev, u64
> *count)
> return 0;
> }
>
> -static void tsc_timer_ensure_setup(void)
> +static void tsc_timer_ensure_setup(bool stop)
> {
> if (gd->arch.tsc_base)
> return;
> gd->arch.tsc_base = rdtsc();
>
> - /*
> -* If there is no clock frequency specified in the device tree,
> -* calibrate it by ourselves.
> -*/
> if (!gd->arch.clock_rate) {
> unsigned long fast_calibrate;
>
> @@ -366,7 +362,10 @@ static void tsc_timer_ensure_setup(void)
> if (fast_calibrate)
> goto done;
>
> - panic("TSC frequency is ZERO");
> + if (stop)
> + panic("TSC frequency is ZERO");
> + else
> + return;
>
> done:
> gd->arch.clock_rate = fast_calibrate * 100;
> @@ -377,11 +376,17 @@ static int tsc_timer_probe(struct udevice *dev)
> {
> struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
>
> - if (!uc_priv->clock_rate) {
> - tsc_timer_ensure_setup();
> - uc_priv->clock_rate = gd->arch.clock_rate;
> + /* Try hardware calibration first */
> + tsc_timer_ensure_setup(false);
> + if (!gd->arch.clock_rate) {
> + /*
> +* Use the clock frequency specified in the
> +* device tree as last resort
> +*/
> + if (!uc_priv->clock_rate)
Where gets uc_priv->clock_rate set to something? DM should set zero-out
the whole uc_priv thing when bind/probe - or?
> + panic("TSC frequency is ZERO");
> } else {
> - gd->arch.tsc_base = rdtsc();
> + uc_priv->clock_rate = gd->arch.clock_rate;
> }
>
> return 0;
> @@ -394,7 +399,7 @@ unsigned long notrace timer_early_get_rate(void)
> * clock rate can only be calibrated via some hardware ways.
> Specifying
> * it in the device tree won't work for the early timer.
> */
> - tsc_timer_ensure_setup();
> + tsc_timer_ensure_setup(true);
>
> return gd->arch.clock_rate;
> }
> --
> 2.7.4
>
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Re: [U-Boot] [PATCH 5/6] x86: coreboot: Add default TSC frequency in the device tree
Am Fr., 10. Aug. 2018 um 11:39 Uhr schrieb Bin Meng :
>
> It was observed sometimes U-Boot as the coreboot payload fails to
> boot on QEMU. This is because TSC calibration fails with no valid
> frequency. This adds default TSC frequency in the device tree.
>
> Signed-off-by: Bin Meng
Reviewed-by: Christian Gmeiner
> ---
>
> arch/x86/dts/coreboot.dts | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
> index a94f781..e212f3d 100644
> --- a/arch/x86/dts/coreboot.dts
> +++ b/arch/x86/dts/coreboot.dts
> @@ -30,6 +30,10 @@
> stdout-path = "/serial";
> };
>
> + tsc-timer {
> + clock-frequency = <10>;
> + };
> +
> pci {
> compatible = "pci-x86";
> u-boot,dm-pre-reloc;
> --
> 2.7.4
>
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Re: [U-Boot] [PATCH 1/6] x86: coreboot: Add generic coreboot payload support
Am Fr., 10. Aug. 2018 um 11:37 Uhr schrieb Bin Meng :
>
> Currently building U-Boot as the coreboot payload requires user
> to change the build configuration for a specific board during
> menuconfig process. This uses the board's native device tree
> to configure the hardware. For example, the device tree provides
> PCI address range for the PCI host controller and U-Boot will
> re-program all PCI devices' BAR to be within this range. In order
> to make sure we don't mess up the hardware, we should guarantee
> the range matches what coreboot programs the chipset.
>
> But we really should make the coreboot payload support easier.
> Just like EFI payload, we can create a generic coreboot payload
> for all x86 boards as well. The payload is configured to include
> as many generic drivers as possible. All stuff that touches low
> level initialization are not allowed as such is the coreboot's
> responsibility. Platform specific drivers (like gpio, spi, etc)
> are not included.
>
> Signed-off-by: Bin Meng
I really love this generic coreboot payload thing and should simplify the
stuff I am working on ( - a generic coreboot payload with some boot logic
stuff in it).
Reviewed-by: Christian Gmeiner
> ---
>
> arch/x86/cpu/coreboot/Kconfig | 20 +--
> arch/x86/cpu/coreboot/coreboot.c | 9 +++--
> arch/x86/dts/Makefile | 1 +
> arch/x86/dts/coreboot.dts | 41
> ++
> board/coreboot/coreboot/Kconfig| 28 +++
> board/coreboot/coreboot/Makefile | 2 +-
> board/coreboot/coreboot/coreboot.c | 17 +
> .../coreboot/{coreboot_start.S => start.S} | 0
> configs/coreboot_defconfig | 18 --
> doc/README.x86 | 15
> include/configs/coreboot.h | 32 +
> 11 files changed, 116 insertions(+), 67 deletions(-)
> create mode 100644 arch/x86/dts/coreboot.dts
> create mode 100644 board/coreboot/coreboot/coreboot.c
> rename board/coreboot/coreboot/{coreboot_start.S => start.S} (100%)
> create mode 100644 include/configs/coreboot.h
>
> diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
> index 392c258..93f61f2 100644
> --- a/arch/x86/cpu/coreboot/Kconfig
> +++ b/arch/x86/cpu/coreboot/Kconfig
> @@ -3,26 +3,26 @@ if TARGET_COREBOOT
> config SYS_COREBOOT
> bool
> default y
> + imply SYS_NS16550
> + imply SCSI
> + imply SCSI_AHCI
> imply AHCI_PCI
> - imply E1000
> - imply ICH_SPI
> imply MMC
> imply MMC_PCI
> imply MMC_SDHCI
> imply MMC_SDHCI_SDMA
> - imply SCSI
> - imply SCSI_AHCI
> - imply SPI_FLASH
> - imply SYS_NS16550
> imply USB
> imply USB_EHCI_HCD
> imply USB_XHCI_HCD
> + imply USB_STORAGE
> + imply USB_KEYBOARD
> imply VIDEO_COREBOOT
> + imply E1000
> + imply ETH_DESIGNWARE
> + imply PCH_GBE
> + imply RTL8169
> imply CMD_CBFS
> imply FS_CBFS
> -
> -config CBMEM_CONSOLE
> - bool
> - default y
> + imply CBMEM_CONSOLE
>
> endif
> diff --git a/arch/x86/cpu/coreboot/coreboot.c
> b/arch/x86/cpu/coreboot/coreboot.c
> index 69025c1..a6fd3a8 100644
> --- a/arch/x86/cpu/coreboot/coreboot.c
> +++ b/arch/x86/cpu/coreboot/coreboot.c
> @@ -7,6 +7,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -75,12 +76,10 @@ int last_stage_init(void)
> if (gd->flags & GD_FLG_COLD_BOOT)
> timestamp_add_to_bootstage();
>
> - board_final_cleanup();
> + /* start usb so that usb keyboard can be used as input device */
> + usb_init();
>
> - return 0;
> -}
> + board_final_cleanup();
>
> -int misc_init_r(void)
> -{
> return 0;
> }
> diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
> index 37e4fdc..c62540f 100644
> --- a/arch/x86/dts/Makefile
> +++ b/arch/x86/dts/Makefile
> @@ -6,6 +6,7 @@ dtb-y += bayleybay.dtb \
> chromebox_panther.dtb \
> chromebook_samus.dtb \
> conga-qeval20-qa3-e3845.dtb \
> + coreboot.dtb \
> cougarcanyon2.dtb \
> crownbay.dtb \
> dfi-bt700-q7x-151.dtb \
> diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
> new file mode 100644
> index 000..a94f781
> --- /dev/null
> +++ b/arch/x86/dts/coreboot.dts
> @@ -0,0 +1,41 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng
> + *
> + * Generic coreboot payload device tree for x86 targets
> + */
> +
> +/dts-v1/;
> +
> +/include/ "skeleton.dtsi"
> +/include/ "serial.dtsi"
> +/include/ "keyboard.dtsi"
> +/include/ "reset.dtsi"
> +/include/ "rtc.dtsi"
> +/include/ "tsc_timer.dtsi"
> +
> +/ {
> + model = "coreboot x86 payload";
Re: [U-Boot] [PATCH v4 4/5] arm: socfpga: fix SPL booting from fpga OnChip RAM
Marek Vasut schrieb am Mo., 13. Aug. 2018, 22:36:
> On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
> > To boot from fpga OnChip RAM, some changes are required in SPL
> > to ensure the code is linked to the correct address (in contrast
> > to QSPI and MMC boot, FPGA boot executes SPL in place instead of
> > copying it to SRAM) and that fpga OnChip RAM stays accessible while
> > SPL runs (don't disable fpga bridges).
> >
> > This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA)
> > for socfpga gen5 boards.
> >
> > Signed-off-by: Simon Goldschmidt
> > ---
> >
> > Changes in v4: Adapted to changed previous patch
> > Changes in v3: this patch is new in v3
> > Changes in v2: None
> >
> > arch/arm/mach-socfpga/Kconfig | 12
> > arch/arm/mach-socfpga/misc_gen5.c | 11 +--
> > arch/arm/mach-socfpga/spl_gen5.c | 6 --
> > include/configs/socfpga_common.h | 5 +
> > 4 files changed, 30 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/Kconfig
> b/arch/arm/mach-socfpga/Kconfig
> > index 5c1df2cf1f..a909395aac 100644
> > --- a/arch/arm/mach-socfpga/Kconfig
> > +++ b/arch/arm/mach-socfpga/Kconfig
> > @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME
> > default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> >
> > endif
> > +
> > +if TARGET_SOCFPGA_GEN5
> > +
> > +config SPL_SOCFPGA_BOOT_FROM_FPGA
> > + bool "Allow booting SPL from FPGA OnChip RAM"
> > + default n
> > + help
> > + Boot from FPGA: this changes the linker address for SPL code to
> run
> > + from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip
> RAM
> > + stays accessible while SPL runs.
> > +
> > +endif
> > diff --git a/arch/arm/mach-socfpga/misc_gen5.c
> b/arch/arm/mach-socfpga/misc_gen5.c
> > index 429c3d6cd5..c82c3584dc 100644
> > --- a/arch/arm/mach-socfpga/misc_gen5.c
> > +++ b/arch/arm/mach-socfpga/misc_gen5.c
> > @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void)
> > setbits_le32(&scu_regs->sacr, 0xfff);
> >
> > /* Configure the L2 controller to make SDRAM start at 0 */
> > - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
> > + if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
> > + /* remap.mpuzero, keep fpga bridge enabled */
> > + writel(0x9, &nic301_regs->remap);
> > + } else {
> > + /* remap.mpuzero */
> > + writel(0x1, &nic301_regs->remap);
> > + }
> > writel(0x1, &pl310->pl310_addr_filter_start);
> > }
> >
> > @@ -209,7 +215,8 @@ int arch_early_init_r(void)
> > for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
> > iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
> >
> > - socfpga_bridges_reset(1);
> > + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> > + socfpga_bridges_reset(1);
> >
> > socfpga_sdram_remap_zero();
> >
> > diff --git a/arch/arm/mach-socfpga/spl_gen5.c
> b/arch/arm/mach-socfpga/spl_gen5.c
> > index be318cc0d9..0c7f6a8c84 100644
> > --- a/arch/arm/mach-socfpga/spl_gen5.c
> > +++ b/arch/arm/mach-socfpga/spl_gen5.c
> > @@ -93,7 +93,8 @@ void board_init_f(ulong dummy)
> > /* Put everything into reset but L4WD0. */
> > socfpga_per_reset_all();
> > /* Put FPGA bridges into reset too. */
> > - socfpga_bridges_reset(1);
> > + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> > + socfpga_bridges_reset(1);
> >
> > socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
> > socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> > @@ -163,5 +164,6 @@ void board_init_f(ulong dummy)
> > hang();
> > }
> >
> > - socfpga_bridges_reset(1);
> > + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> > + socfpga_bridges_reset(1);
> > }
> > diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_common.h
> > index d1148b838b..99c5e39086 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> > * 0xFFEz_ .. Malloc area (grows up to top)
> > * 0xFFE3_ .. End of SRAM (top)
> > */
> > +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA
> > +/* SPL executed from FPGA */
> > +#define CONFIG_SPL_TEXT_BASE 0xC000
> > +#else
> > #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
> > +#endif
> > #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
> >
> > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>
> What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on
> the previous version of the patch ?
>
D'oh! That slipped through. Sorry for reminding.
Simon
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Re: [U-Boot] [PATCH v4 2/5] arm: socfpga: fix U-Boot running from fpga OnChip RAM
Marek Vasut schrieb am Mo., 13. Aug. 2018, 22:36: > On 08/13/2018 09:34 PM, Simon Goldschmidt wrote: > > gd->env_addr points to pre-relocation address even after > > relocation. This leads to an abort in env_callback_init > > when loading the environment. > > > > Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC. > > > > Signed-off-by: Simon Goldschmidt > > --- > > > > Changes in v4: enable this fix for all socfpga, not for gen5 only > > Changes in v3: this patch is new in v3 > > Changes in v2: None > > > > include/configs/socfpga_common.h | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/include/configs/socfpga_common.h > b/include/configs/socfpga_common.h > > index 8ebf6b85fe..d1148b838b 100644 > > --- a/include/configs/socfpga_common.h > > +++ b/include/configs/socfpga_common.h > > @@ -284,6 +284,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > > #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START > > #endif > > > > +/* When U-Boot is started from FPGA, prevent gd->env_addr to point into > > Multi-line comment should have this format > /* > * foo > * bar > */ > Right, of course. I wonder why patman didn't warm me about that... > > + * FPGA OnChip RAM after relocation > > + */ > > +#define CONFIG_SYS_EXTRA_ENV_RELOC > > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE/* start > of monitor */ > > What you don't explain in the commit message is this last line. Why is > this needed ? > The code enabled by CONFIG_SYS_EXTRA_ENV_RELOC used this to calculate the relocation offset. I do think that's a bit strange, but I wouldn't change it with this patchset, or should I? Simon > > /* Extra Environment */ > > #ifndef CONFIG_SPL_BUILD > > > > > > > -- > Best regards, > Marek Vasut > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fs/fat: debug-print file read position during file_fat_read_at()
On 08/14/2018 04:35 AM, Andreas Dannenberg wrote:
> In order to make the debug print in file_fat_read_at() a tad more useful,
> show the offset the file is being read at alongside the filename.
>
> Suggested-by: Tero Kristo
> Signed-off-by: Andreas Dannenberg
> ---
>
> Small addition but helpful nevertheless as none of the other debug prints
> embedded into fat.c seems to output this info. Without that addition it
> would just tell you the same file name a couple of times when reading
> from an DTB/ITB file for example. With the offset being shown it's easier
> to correlate/debug the loading process.
>
> Oddly (and I haven't fully debugged this) but in order to really get _any_ of
> the debug() prints working in fat.c in my particulat setup, in addition to
> the usual '#define DEBUG' I also had to explicitly define _DEBUG to '1',
> something that should already be taken care of by log.c...
>
>
> fs/fat/fat.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/fs/fat/fat.c b/fs/fat/fat.c
> index 4efe8a3eda..4b722fc5ca 100644
> --- a/fs/fat/fat.c
> +++ b/fs/fat/fat.c
> @@ -1095,7 +1095,7 @@ int file_fat_read_at(const char *filename, loff_t pos,
> void *buffer,
> if (ret)
> goto out_free_both;
>
> - debug("reading %s\n", filename);
> + debug("reading %s at pos %llu\n", filename, pos);
> ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread);
>
> out_free_both:
>
This seems to duplicate
[PATCH 1/1] fat: provide position in debug message
https://lists.denx.de/pipermail/u-boot/2018-August/337850.html
The only difference is that you print a decimal number instead of a hex
number.
Using %llu is consistent with
fs/fat/fat.c:331:
debug("Read position past EOF: %llu\n", pos);
So I will withdraw my patch.
Reviewed-by: Heinrich Schuchardt
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Re: [U-Boot] [PATCH 1/1] fat: provide position in debug message
On 08/09/2018 08:37 PM, Heinrich Schuchardt wrote:
> The debug message in file_fat_read_at() is not very useful without
> indicating the position at which the file is read.
>
> Suggested-by: Tero Kristo
> Signed-off-by: Heinrich Schuchardt
> ---
> fs/fat/fat.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/fs/fat/fat.c b/fs/fat/fat.c
> index 4efe8a3eda..27004823cd 100644
> --- a/fs/fat/fat.c
> +++ b/fs/fat/fat.c
> @@ -1095,7 +1095,7 @@ int file_fat_read_at(const char *filename, loff_t pos,
> void *buffer,
> if (ret)
> goto out_free_both;
>
> - debug("reading %s\n", filename);
> + debug("reading %s at %llx\n", filename, pos);
> ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread);
>
> out_free_both:
>
Superseded by:
fs/fat: debug-print file read position during file_fat_read_at()
https://lists.denx.de/pipermail/u-boot/2018-August/338289.html
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[U-Boot] [RFC PATCH] arm: zynq: read mac address from SPI flash memory
Implement a method for reading the MAC address from an
SPI flash memory.
In particular, this method is used by the Zybo Z7 board
to read the MAC address from the OTP region in the SPI NOR
memory
Signed-off-by: Luis Araneda
---
I'm trying to implement the reading of the MAC address of
the Zybo Z7 board from the OTP region of its SPI NOR memory.
I took some ideas from Digilent's fork, but the commit was
marked as not upstremeable. That's why I'm asking for comments.
If the code can't be merged, ideas on how this can be implemented
are welcome.
Thanks,
Luis Araneda.
---
board/xilinx/zynq/board.c | 28
configs/zynq_zybo_z7_defconfig | 3 +++
drivers/misc/Kconfig | 17 +
3 files changed, 48 insertions(+)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 614d93c082..a252c38956 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -6,9 +6,12 @@
#include
#include
+#include
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -87,6 +90,31 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
printf("I2C EEPROM MAC address read failed\n");
#endif
+#if defined(CONFIG_MAC_ADDR_IN_SPI_FLASH)
+ struct spi_flash *flash;
+ struct udevice *dev;
+ int ret;
+
+ ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
+CONFIG_SF_DEFAULT_CS,
+0, 0, &dev);
+ if (ret) {
+ printf("SPI(bus:%u cs:%u) probe failed\n",
+ CONFIG_SF_DEFAULT_BUS,
+ CONFIG_SF_DEFAULT_CS);
+ return 0;
+ }
+
+ flash = dev_get_uclass_priv(dev);
+ flash->read_cmd = CONFIG_MAC_ADDR_SPI_FLASH_READ_CMD;
+
+ if (spi_flash_read_dm(dev,
+ CONFIG_MAC_ADDR_SPI_FLASH_DATA_OFFSET,
+ 6, ethaddr))
+ printf("SPI MAC address read failed\n");
+
+ device_remove(dev, DM_REMOVE_NORMAL);
+#endif
return 0;
}
diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index ad44e772aa..ca402e3231 100644
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -44,6 +44,9 @@ CONFIG_DM_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C0=y
CONFIG_ZYNQ_I2C1=y
+CONFIG_MAC_ADDR_IN_SPI_FLASH=y
+CONFIG_MAC_ADDR_SPI_FLASH_READ_CMD=0x4b
+CONFIG_MAC_ADDR_SPI_FLASH_DATA_OFFSET=0x20
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c031dfde9d..40cec81e66 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -272,6 +272,23 @@ config SYS_I2C_EEPROM_ADDR_OVERFLOW
endif
+config MAC_ADDR_IN_SPI_FLASH
+ bool "MAC address in SPI flash"
+ help
+ Read MAC address from an SPI flash memory
+
+if MAC_ADDR_IN_SPI_FLASH
+
+config MAC_ADDR_SPI_FLASH_READ_CMD
+ hex "Read command for the SPI flash memory"
+ default 0
+
+config MAC_ADDR_SPI_FLASH_DATA_OFFSET
+ hex "Offset of MAC data in SPI flash memory"
+ default 0
+
+endif
+
config GDSYS_RXAUI_CTRL
bool "Enable gdsys RXAUI control driver"
depends on MISC
--
2.18.0
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Re: [U-Boot] [PATCH] Kconfig: Migrate CONFIG_NR_DRAM_BANKS
On Tue, Aug 14, 2018 at 1:11 AM Marek Vasut wrote: > On 08/14/2018 12:00 AM, Ramon Fried wrote: > > Move CONFIG_NR_DRAM_BANKS from headers to Kconfig. > > > > Signed-off-by: Ramon Fried > > Somehow this seems to be missing a lot of cleanups in include/configs/ > ... look at moveconfig.py > Indeed, Tom said he'll handle that :) > > > --- > > Kconfig | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/Kconfig b/Kconfig > > index db0f545e45..d96e3373c1 100644 > > --- a/Kconfig > > +++ b/Kconfig > > @@ -104,6 +104,12 @@ config ENV_VARS_UBOOT_CONFIG > > - CONFIG_SYS_VENDOR > > - CONFIG_SYS_SOC > > > > +config NR_DRAM_BANKS > > + int "Number of DRAM banks" > > + default 4 > > + help > > + This defines the number of DRAM banks. > > + > > config SYS_BOOT_GET_CMDLINE > > bool "Enable kernel command line setup" > > help > > > > > -- > Best regards, > Marek Vasut > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] pci: Support parsing PCI controller DT subnodes
Hi Tom, On Tue, Aug 14, 2018 at 1:16 AM, Tom Rini wrote: > On Mon, Aug 13, 2018 at 06:07:14PM +0200, Marek Vasut wrote: >> On 08/13/2018 03:39 PM, Tom Rini wrote: >> [...] >> >> Next step is to upstream the DT >> changes to Linux kernel, then sync the changes to U-Boot to satisfy >> this obsession - using exactly the same DT as Linux. >> >>> >> >>> This is not gonna happen. >> >>> >> >>> Sorry, you're really just wasting my time with this foolishness. If >> >>> U-Boot cannot parse valid DT bindings while other OSes can, U-Boot is >> >>> broken and must be fixed. So far I only see you attacking this patch and >> >>> trying to pull in everything you can do avoid accepting this patch or >> >>> providing a better alternative. This is not a constructive discussion, >> >>> so I stop here. >> >> >> >> The fix in this patch is purely hack, period. >> > >> > Lets step back for a moment. >> > >> > First, U-Boot intends to be, in the case where a relevant DTS file >> > exists, the Linux kernel one PLUS additions we require (u-boot,dm-spl, >> > u-boot,dm-pre-reloc, but also sometimes stdout-path or properties that >> > are omitted for various reasons). >> >> Right, which doesn't apply here. None of those u-boot,... props are >> needed in this case. > > Which is why I also mentioned the non-u-boot specific props we also need > sometimes. My point is two-fold: > 1: We can and will _add_ information to the dts files that come from > Linux. > 2: Not all information that we add is U-Boot prefixed. > It would be better if we document such DT expectation somewhere. >> > Second, I've asked before (both in this thread and on IRC), and not >> > gotten an answer yet, as to how Linux goes "Oh, _this_ PCI device and >> > _this_ DT node need to be matched and populate some data >> > structures". >> >> You did get an answer to that on irc from George. Looks like >> of_pci_find_child_device() in drivers/pci/of.c > > Yeah, George said he thought that might be it but didn't have time to > confirm. > >> > Marek's patch seems to be, in short "here's where U-Boot >> > needs to wire things up". Bin has said that no, the function in >> > question is for other things. >> >> I disagree with this. It's a bind function and assigns other parameters >> of the driver instance too. >> >> > I think knowing where Linux does this >> > would be instructive to figure out where we need to have some additional >> > logic added OR we can make some cost/benefit analysis to see if it makes >> > more sense overall to add compatibles to some nodes rather than add to >> > the binary size. >> >> Adding compatible does not make any sense, the PCI ID provides that >> information. Adding compatible would only add redundancy which could >> possibly be even harmful (ie. if the controller got replaced with >> another one). > > To try and move things along rather than re-argue the same point, you're > saying that our pci_find_and_bind_driver() is the rough equivalent of > of_pci_find_child_device() or at least pci_set_of_node() (which calls > of_pci_find_child_device()). > > So, Bin, if this isn't the right place to start down this path, where > would be? Given that Linux can take a DTB and PCI bus with devices and > get things right, what would it look like for U-Boot to replicate the > same behavior? Instead of having to add explicit compatible nodes for > each PCI device, as I understand (but correct me if I'm wrong) we're > doing today. Thanks! So is this a requirement for all U-Boot driver subsystems to replicate the same Linux behavior? If yes, can we have it officially documented somewhere? Since Marek refused to take the original U-Boot option 1 to support his case, and asked U-Boot to follow Linux's practice on PCI device binding, if we go that way, here is what we can do: * Keep pci-uclass driver's post_bind() and child_post_bind() only for Sandbox configuration * Keep the call to pci_bus_find_devfn() in pci_bind_bus_devices() only for Sandbox configuration * Sandbox is special. We should limit the mechanism of matching PCI emulation device via "compatible" to sandbox only * Assign the DT node to the bound device in pci_find_and_bind_driver() if there is a valid PCI "reg" encoding for a specific PCI device in the device tree * Create DM PCI test case against the DT node assignment * Remove all compatible string in U-Boot's PCI device drivers: eg: ehci_pci_ids[], xhci_pci_ids[], etc. IOW, all PCI device drivers should only use U_BOOT_PCI_DEVICE(), aka the original U-Boot option 2 * Fork a "pci-ns16550" driver to support U_BOOT_PCI_DEVICE(), as currently PCI ns16550 device driver uses "compatible" string to do the matching, and update crownbay.dts and galileo.dts (so far I only know two boards are using PCI ns16550 serial port) * Make sure all DM PCI test cases are not broken * Document all of the above changes in doc/driver-model/pci-info.txt I am not sure if I missed anything. Simon, could you also comment on it? Regards, Bin
[U-Boot] [PATCH] fs/fat: debug-print file read position during file_fat_read_at()
In order to make the debug print in file_fat_read_at() a tad more useful,
show the offset the file is being read at alongside the filename.
Suggested-by: Tero Kristo
Signed-off-by: Andreas Dannenberg
---
Small addition but helpful nevertheless as none of the other debug prints
embedded into fat.c seems to output this info. Without that addition it
would just tell you the same file name a couple of times when reading
from an DTB/ITB file for example. With the offset being shown it's easier
to correlate/debug the loading process.
Oddly (and I haven't fully debugged this) but in order to really get _any_ of
the debug() prints working in fat.c in my particulat setup, in addition to
the usual '#define DEBUG' I also had to explicitly define _DEBUG to '1',
something that should already be taken care of by log.c...
fs/fat/fat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 4efe8a3eda..4b722fc5ca 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -1095,7 +1095,7 @@ int file_fat_read_at(const char *filename, loff_t pos,
void *buffer,
if (ret)
goto out_free_both;
- debug("reading %s\n", filename);
+ debug("reading %s at pos %llu\n", filename, pos);
ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread);
out_free_both:
--
2.15.1
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[U-Boot] [PATCH] ARM: da850evm_direct_nor_defconfig: Enable DM_SERIAL
With DM enabled, this patch enables DM_SERIAL and removes the NS16550 initialization from da850_lowlevel since the driver will take care of that itself. Signed-off-by: Adam Ford diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 95dc93a24f..8ceb1779f9 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -288,10 +288,10 @@ int arch_cpu_init(void) /* GPIO setup */ board_gpio_init(); - +#if !defined(CONFIG_DM_SERIAL) NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - +#endif /* * Fix Power and Emulation Management Register * see sprufw3a.pdf page 37 Table 24 diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index bb8fa3bd6e..baadd01c2c 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -5,7 +5,6 @@ CONFIG_TARGET_DA850EVM=y CONFIG_DA850_LOWLEVEL=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_DEFAULT_DEVICE_TREE="da850-evm" -# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="USE_NOR,DIRECT_NOR_BOOT" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -45,6 +44,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] pci: Support parsing PCI controller DT subnodes
Hi Marek,
On Mon, Aug 13, 2018 at 9:46 PM, Marek Vasut wrote:
> On 08/13/2018 04:24 AM, Bin Meng wrote:
>> Hi Marek,
>>
>> On Fri, Aug 10, 2018 at 8:38 PM, Marek Vasut wrote:
>>> On 08/10/2018 02:01 PM, Tom Rini wrote:
On Wed, Aug 08, 2018 at 09:37:25PM +0200, Marek Vasut wrote:
> On 08/08/2018 05:32 PM, Bin Meng wrote:
>> Hi Marek,
>>
>> On Wed, Aug 8, 2018 at 10:33 PM, Marek Vasut
>> wrote:
>>> On 08/08/2018 03:39 PM, Bin Meng wrote:
Hi Marek,
On Wed, Aug 8, 2018 at 9:24 PM, Marek Vasut
wrote:
> On 08/08/2018 03:14 PM, Bin Meng wrote:
>> Hi Marek,
>>
>> On Wed, Aug 8, 2018 at 9:03 PM, Marek Vasut
>> wrote:
>>> The PCI controller can have DT subnodes describing extra properties
>>> of particular PCI devices, ie. a PHY attached to an EHCI controller
>>> on a PCI bus. This patch parses those DT subnodes and assigns a node
>>> to the PCI device instance, so that the driver can extract details
>>> from that node and ie. configure the PHY using the PHY subsystem.
>>>
>>> Signed-off-by: Marek Vasut
>>> Cc: Simon Glass
>>> ---
>>> drivers/pci/pci-uclass.c | 14 ++
>>> 1 file changed, 14 insertions(+)
>>>
>>> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
>>> index 46e9c71bdf..306bea0dbf 100644
>>> --- a/drivers/pci/pci-uclass.c
>>> +++ b/drivers/pci/pci-uclass.c
>>> @@ -662,6 +662,8 @@ static int pci_find_and_bind_driver(struct
>>> udevice *parent,
>>> for (id = entry->match;
>>> id->vendor || id->subvendor || id->class_mask;
>>> id++) {
>>> + ofnode node;
>>> +
>>> if (!pci_match_one_id(id, find_id))
>>> continue;
>>>
>>> @@ -691,6 +693,18 @@ static int pci_find_and_bind_driver(struct
>>> udevice *parent,
>>> goto error;
>>> debug("%s: Match found: %s\n", __func__,
>>> drv->name);
>>> dev->driver_data = find_id->driver_data;
>>> +
>>> + dev_for_each_subnode(node, parent) {
>>> + phys_addr_t df, size;
>>> + df = ofnode_get_addr_size(node,
>>> "reg", &size);
>>> +
>>> + if (PCI_FUNC(df) == PCI_FUNC(bdf) &&
>>> + PCI_DEV(df) == PCI_DEV(bdf)) {
>>> + dev->node = node;
>>> + break;
>>> + }
>>
>> The function pci_find_and_bind_driver() is supposed to bind devices
>> that are NOT in the device tree. Adding device tree access in this
>> routine is quite odd. You can add the EHCI controller that need such
>> PHY subnodes in the device tree and there is no need to modify
>> anything I believe. If you are looking for an example, please check
>> pciuart0 in arch/x86/dts/crownbay.dts.
>
> Well this does not work for me, the EHCI PCI doesn't get a DT node
> assigned, check r8a7794.dtsi for the PCI devices I use.
>
I think that's because you don't specify a "compatible" string for
these two EHCI PCI nodes.
>>>
>>> That's perfectly fine, why should I specify it ? Linux has no problem
>>> with it either.
>>>
>>
>> Without a "compatible" string, DM does not bind any device in the
>> device tree to a driver, hence no device node created. This is not
>> Linux.
>
> DT is NOT Linux specific, it is OS-agnostic, DT describes hardware and
> hardware only. If U-Boot cannot parse DT correctly, U-Boot is broken and
> must be fixed.
>
> This is a fix. If there is a better fix, I am open to it.
DT should but isn't always OS agnostic. DTS files that reside in the
Linux Kernel are in practice is Linux-centric with the expectation that
even if you could solve a given problem with valid DTS changes you make
whatever is parsing it do additional logic instead. That,
approximately, is what your patch is doing. If you added some HW
description information to the dtsi file everything would work as
expected as your DTS is describing the hardware and U-Boot is reading
that description and figuring out what to do with it.
>>>
>>> Yes, you need additional logic to match the PCI controller subnode in DT
>>> with PCI device BFD, that's expected. You do NOT need extra compatibles,
>>> the PCI bus
[U-Boot] [PATCH] ARM: da850evm_direct_nor: Enable CONFIG_BLK
At least for now, CONFIG_BLK is working, but this variant of the da850evm doesn't need/support SPL so it's OK to enable it here. Signed-off-by: Adam Ford diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 9d6c47df50..bb8fa3bd6e 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_DM=y +CONFIG_BLK=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [ANN] U-Boot v2018.09-rc2 released
Hey all, It is release day and despite Travis-CI being really bad about network connections over the weekend, it's back to normal today at least. So I'm putting out v2018.09-rc2 now. I plan on looking at Kconfig migrations and similar things that I can size-test. I think there's still a code removal patch or two I can apply as well at this point. Things look on track for -rc3 on the 27th, -rc4 on September 3rd and then final release on September 10th. Thanks all! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 7/7] common: avb_verify: Fix division by zero in mmc_byte_io()
Compiling U-Boot with ubsan/asan libraries and running it in sandbox
may lead to below backtrace:
=> avb init 0
=> avb verify
## Android Verified Boot 2.0 version 1.1.0
read_is_device_unlocked not supported yet
common/avb_verify.c:407:31: runtime error: division by zero
AddressSanitizer:DEADLYSIGNAL
=
==9388==ERROR: AddressSanitizer: FPE on unknown address 0x004b467f \
(pc 0x004b467f bp 0x sp 0x7ffd899fe150 T0)
#0 0x4b467e in mmc_byte_io common/avb_verify.c:407
#1 0x4b4c47 in mmc_byte_io common/avb_verify.c:532
#2 0x4b4c47 in read_from_partition common/avb_verify.c:533
#3 0x69dc0d in load_and_verify_vbmeta lib/libavb/avb_slot_verify.c:560
#4 0x6a1ee6 in avb_slot_verify lib/libavb/avb_slot_verify.c:1139
#5 0x45dabd in do_avb_verify_part cmd/avb.c:245
#6 0x4af77c in cmd_call common/command.c:499
#7 0x4af77c in cmd_process common/command.c:538
#8 0x46bafc in run_pipe_real common/cli_hush.c:1677
#9 0x46bafc in run_list_real common/cli_hush.c:1875
#10 0x46c780 in run_list common/cli_hush.c:2024
#11 0x46c780 in parse_stream_outer common/cli_hush.c:3216
#12 0x46d34b in parse_file_outer common/cli_hush.c:3299
#13 0x4ad609 in cli_loop common/cli.c:217
#14 0x4625ae in main_loop common/main.c:65
#15 0x46f2d1 in run_main_loop common/board_r.c:648
#16 0x640253 in initcall_run_list lib/initcall.c:30
#17 0x46f9d0 in board_init_r common/board_r.c:879
#18 0x40539b in main arch/sandbox/cpu/start.c:321
#19 0x7fa94925f82f in __libc_start_main
(/lib/x86_64-linux-gnu/libc.so.6+0x2082f)
#20 0x408908 in _start (/srv/R/u-boot-master/u-boot+0x408908)
AddressSanitizer can not provide additional info.
SUMMARY: AddressSanitizer: FPE common/avb_verify.c:407 in mmc_byte_io
==9388==ABORTING
Signed-off-by: Eugeniu Rosca
---
common/avb_verify.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 3d2b4cbad92d..759df7bd25c0 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -402,6 +402,9 @@ static AvbIOResult mmc_byte_io(AvbOps *ops,
if (!part)
return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+ if (!part->info.blksz)
+ return AVB_IO_RESULT_ERROR_IO;
+
start_offset = calc_offset(part, offset);
while (num_bytes) {
start_sector = start_offset / part->info.blksz;
--
2.18.0
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[U-Boot] [PATCH 6/7] common: avb_verify: Fix never-occurring avb_free(ops_data)
Cppcheck (v1.85) reports w/o this patch:
[common/avb_verify.c:738] -> [common/avb_verify.c:741]: (warning) \
Either the condition 'ops' is redundant or there is possible null \
pointer dereference: ops.
Signed-off-by: Eugeniu Rosca
---
common/avb_verify.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 58cfa1aa7de8..3d2b4cbad92d 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -735,7 +735,7 @@ void avb_ops_free(AvbOps *ops)
{
struct AvbOpsData *ops_data;
- if (ops)
+ if (!ops)
return;
ops_data = ops->user_data;
--
2.18.0
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[U-Boot] [PATCH 5/7] common: avb_verify: Fix memory leaks
Cppcheck (v1.85) reports w/o this patch:
[common/avb_verify.c:351]: (error) Memory leak: part
[common/avb_verify.c:356]: (error) Memory leak: part
[common/avb_verify.c:361]: (error) Memory leak: part
[common/avb_verify.c:366]: (error) Memory leak: part
Signed-off-by: Eugeniu Rosca
---
common/avb_verify.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 9c90e1b4ae5c..58cfa1aa7de8 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -348,34 +348,37 @@ static struct mmc_part *get_partition(AvbOps *ops, const
char *partition)
part->mmc = find_mmc_device(dev_num);
if (!part->mmc) {
printf("No MMC device at slot %x\n", dev_num);
- return NULL;
+ goto err;
}
if (mmc_init(part->mmc)) {
printf("MMC initialization failed\n");
- return NULL;
+ goto err;
}
ret = mmc_switch_part(part->mmc, part_num);
if (ret)
- return NULL;
+ goto err;
mmc_blk = mmc_get_blk_desc(part->mmc);
if (!mmc_blk) {
printf("Error - failed to obtain block descriptor\n");
- return NULL;
+ goto err;
}
ret = part_get_info_by_name(mmc_blk, partition, &part->info);
if (!ret) {
printf("Can't find partition '%s'\n", partition);
- return NULL;
+ goto err;
}
part->dev_num = dev_num;
part->mmc_blk = mmc_blk;
return part;
+err:
+ free(part);
+ return NULL;
}
static AvbIOResult mmc_byte_io(AvbOps *ops,
--
2.18.0
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[U-Boot] [PATCH 3/7] common: kconfig: Mark AVB_VERIFY as dependent on PARTITION_UUIDS
Avoid below compiler [1] errors, reproduced with configuration [2]:
common/avb_verify.c: In function ‘get_unique_guid_for_partition’:
common/avb_verify.c:692:31: error: ‘disk_partition_t {aka struct
disk_partition}’ has no member named ‘uuid’
uuid_size = sizeof(part->info.uuid);
^
common/avb_verify.c:696:29: error: ‘disk_partition_t {aka struct
disk_partition}’ has no member named ‘uuid’
memcpy(guid_buf, part->info.uuid, uuid_size);
^
LD drivers/built-in.o
make[2]: *** [scripts/Makefile.build:278: common/avb_verify.o] Error 1
[1] aarch64-linux-gnu-gcc (Linaro GCC 7.2-2017.11)
[2] r8a7795_ulcb_defconfig, plus:
CONFIG_AVB_VERIFY=y
CONFIG_PARTITION_UUIDS=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_LIBAVB=y
Signed-off-by: Eugeniu Rosca
---
common/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/common/Kconfig b/common/Kconfig
index 4d7215a36086..f4a0e03b 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -640,6 +640,7 @@ config HASH
config AVB_VERIFY
bool "Build Android Verified Boot operations"
depends on LIBAVB && FASTBOOT
+ depends on PARTITION_UUIDS
help
This option enables compilation of bootloader-dependent operations,
used by Android Verified Boot 2.0 library (libavb). Includes:
--
2.18.0
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[U-Boot] [PATCH 1/7] libavb: Handle wrong hashtree_error_mode in avb_append_options()
From: Ievgen Maliarenko
Exit with AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT
when hashtree_error_mode value passed to avb_append_options()
is unknown (not from AvbHashtreeErrorMode enum).
Otherwise, default value is not handled in the
switch(hashtree_error_mode), which causes below compile warning:
lib/libavb/avb_cmdline.c: In function ‘avb_append_options’:
lib/libavb/avb_cmdline.c:354:13: warning: ‘dm_verity_mode’ may be used
uninitialized in this function [-Wmaybe-uninitialized]
new_ret = avb_replace(
^~
slot_data->cmdline, "$(ANDROID_VERITY_MODE)", dm_verity_mode);
~
lib/libavb/avb_cmdline.c:363:8: warning: ‘verity_mode’ may be used
uninitialized in this function [-Wmaybe-uninitialized]
if (!cmdline_append_option(
^~
slot_data, "androidboot.veritymode", verity_mode)) {
Signed-off-by: Ievgen Maliarenko
Signed-off-by: Eugeniu Rosca
---
lib/libavb/avb_cmdline.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/libavb/avb_cmdline.c b/lib/libavb/avb_cmdline.c
index 91a6615c740d..d24669927203 100644
--- a/lib/libavb/avb_cmdline.c
+++ b/lib/libavb/avb_cmdline.c
@@ -331,6 +331,9 @@ AvbSlotVerifyResult avb_append_options(
verity_mode = "logging";
dm_verity_mode = "ignore_corruption";
break;
+ default:
+ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT;
+goto out;
}
new_ret = avb_replace(
slot_data->cmdline, "$(ANDROID_VERITY_MODE)", dm_verity_mode);
--
2.18.0
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[U-Boot] [PATCH 2/7] common: avb_verify: Fix invalid 'for' loop condition
Fix below compiler [1] warning:
common/avb_verify.c: In function ‘avb_find_dm_args’:
common/avb_verify.c:179:30: warning: left-hand operand of comma expression has
no effect [-Wunused-value]
for (i = 0; i < AVB_MAX_ARGS, args[i]; ++i) {
[1] aarch64-linux-gnu-gcc (Linaro GCC 7.2-2017.11)
Signed-off-by: Eugeniu Rosca
---
common/avb_verify.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 20e35ade3029..e6f3f207ff6f 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -176,7 +176,7 @@ static int avb_find_dm_args(char **args, char *str)
if (!str)
return -1;
- for (i = 0; i < AVB_MAX_ARGS, args[i]; ++i) {
+ for (i = 0; i < AVB_MAX_ARGS && args[i]; ++i) {
if (strstr(args[i], str))
return i;
}
--
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[U-Boot] [PATCH 4/7] common: avb_verify: Make local data static
Fix sparse complaint:
common/avb_verify.c:14:21: warning: \
symbol 'avb_root_pub' was not declared. Should it be static?
Signed-off-by: Eugeniu Rosca
---
common/avb_verify.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index e6f3f207ff6f..9c90e1b4ae5c 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -11,7 +11,7 @@
#include
#include
-const unsigned char avb_root_pub[1032] = {
+static const unsigned char avb_root_pub[1032] = {
0x0, 0x0, 0x10, 0x0, 0x55, 0xd9, 0x4, 0xad, 0xd8, 0x4,
0xaf, 0xe3, 0xd3, 0x84, 0x6c, 0x7e, 0xd, 0x89, 0x3d, 0xc2,
0x8c, 0xd3, 0x12, 0x55, 0xe9, 0x62, 0xc9, 0xf1, 0xf, 0x5e,
--
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Re: [U-Boot] ARM: dts: stm32mp157: Add ADC DT node
On Mon, Aug 06, 2018 at 09:54:04AM +0200, Patrice Chotard wrote: > Add ADC device tree node. This allows to get analog conversions on > stm32mp157. > > Signed-off-by: Fabrice Gasnier > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 10/11] configs: stm32f469-discovery: Add DISTRO_DEFAULT support
On Fri, Aug 03, 2018 at 11:46:20AM +0200, Patrice Chotard wrote: > Add DISTRO_DEFAULT support to be able to boot on mmc > by default on boot. > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/2] ARM: dts: stm32: remove cd-inverted for stm32f769-disco
On Mon, Aug 06, 2018 at 09:38:17AM +0200, Patrice Chotard wrote: > As cd-inverted property is no more used by arm_pl180_mmci driver, > remove it. Update cd-gpios active level accordingly. > > Reported-by: Tuomas Tynkkynen > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 3/3] db410: alter WLAN/BT MAC address fixup
On Fri, Aug 03, 2018 at 04:25:37PM +0300, Ramon Fried wrote: > Change the way MAC address fixup is done: > 1. Stop using LK handed device-tree and calculate >the MAC address our own. > 2. Allow overriding the generated MACS with environment variables: >"wlanaddr" and "btaddr". > > Signed-off-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ARM: dts: stm32f4: Fix DT dtc warnings
On Mon, Aug 06, 2018 at 11:25:42AM +0200, Patrice Chotard wrote: > From: Patrick Delaunay > > This patch fix the following warnings for for stm32f429 > evaluation and discovery boards: > > unnecessary #address-cells/#size-cells without "ranges" or > child "reg" property > > Signed-off-by: Patrick Delaunay > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 2/3] snapdragon: added MAC generation functions
On Fri, Aug 03, 2018 at 04:25:36PM +0300, Ramon Fried wrote: > Add support for generation of unique MAC address > that is derived from board serial. > Algorithm for generation of MAC taken from LK. > > Signed-off-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 1/3] snapdragon: added msm_board_serial() func
On Fri, Aug 03, 2018 at 04:25:35PM +0300, Ramon Fried wrote: > This commit adds a function to get the board > serial number. > In snapdragon it's actually the eMMC serial number. > > Function added in a new file misc.c that will > include further snapdragon miscellaneous functions. > > Signed-off-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 04/11] configs: stm32f4xx: Enable ICACHE and DCACHE
On Fri, Aug 03, 2018 at 11:46:14AM +0200, Patrice Chotard wrote:
> Enable instruction and data caches.
> Fix boot_sd command as since commit d409c962169b ("armv7m: disable
> icache before linux booting"), instruction cache is automatically
> disable before linux booting. "icache off" from boot_sd command
> becomes useless, remove it.
>
> Signed-off-by: Patrice Chotard
Applied to u-boot/master, thanks!
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Re: [U-Boot] [U-Boot,1/2] tpm: sandbox: fix wrong check on pcr_map
On Sun, Aug 05, 2018 at 06:53:06PM +0200, Miquel Raynal wrote: > The second check on pcr_map in sandbox_tpm2_xfer() is wrong. It should > check for pcr_map not being empty. Instead, it is a pure copy/paste of > the first check which is redundant. > > This has been found thanks to a Coverity Scan report: > > CID 183370: Memory - illegal accesses (UNINIT) > Using uninitialized value "pcr_index". > put_unaligned_be32(tpm->pcr_extensions[pcr_index], recv); > > This is because pcr_index is initialized only if the user input is > correct, ie. at least one valid bit is set in pcr_map. > > Fix the second check and also initialize pcr_index to 0 (which is > harmless in case of error) to make Coverity Scan happy. > > Reported-by: Tom Rini > Signed-off-by: Miquel Raynal > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 06/11] configs: stm32h7xx: Migrate CONFIG_CMD_CACHE to defconfig
On Fri, Aug 03, 2018 at 11:46:16AM +0200, Patrice Chotard wrote: > Remove CONFIG_CMD_CACHE from include/configs/stm32h7xx.h > and enable it in stm32h7xx_defconfig > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] MAINTAINERS: Add more sources to Arch Snapdragon
On Fri, Aug 03, 2018 at 08:56:27PM +0300, Ramon Fried wrote: > Add scattered driver files around the source tree > that belongs to Snapdragon arch. Not sure why they > were not included in the first place. > > Signed-off-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm: bcm7445: Move config defines to bcm7445.h
On Thu, Jul 26, 2018 at 11:02:47PM -0400, Thomas Fitzsimmons wrote: > Move some configuration #defines that do not apply to other bcmstb > boards from bcmstb.h to bcm7445.h. > > Signed-off-by: Thomas Fitzsimmons Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/2] ARM: dts: stm32: remove cd-inverted for stm32f746-disco
On Mon, Aug 06, 2018 at 09:38:18AM +0200, Patrice Chotard wrote: > As cd-inverted property is no more used by arm_pl180_mmci driver, > remove it. Update cd-gpios active level accordingly. > > Reported-by: Tuomas Tynkkynen > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 3/3] db410: alter WLAN/BT MAC address fixup
On Fri, Aug 03, 2018 at 04:25:37PM +0300, Ramon Fried wrote: > Change the way MAC address fixup is done: > 1. Stop using LK handed device-tree and calculate >the MAC address our own. > 2. Allow overriding the generated MACS with environment variables: >"wlanaddr" and "btaddr". > > Signed-off-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 11/11] configs: stm32f429-evaluation: Add DISTRO_DEFAULT support
On Fri, Aug 03, 2018 at 11:46:21AM +0200, Patrice Chotard wrote: > Add DISTRO_DEFAULT support to be able to boot on mmc > by default on boot. > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 02/11] configs: stm32fxxx: Remove CONFIG_SYS_CLK_FREQ
On Fri, Aug 03, 2018 at 11:46:12AM +0200, Patrice Chotard wrote:
> Since commit aa5e3e22f4d6 ("board: stm32: switch to DM STM32 timer")
> SYS_CLK_FREQ is useless, remove it from stm32f4 and stm32f7 boards.
>
> Signed-off-by: Patrice Chotard
Applied to u-boot/master, thanks!
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Re: [U-Boot] ARM: omap3: evm: Enable CONFIG_BLK and misc. cleanup
On Sun, Aug 05, 2018 at 11:51:31PM -0500, Derald D. Woods wrote: > This commit enables CONFIG_BLK and removes USB_STORAGE which is awaiting > proper implementation for current U-Boot interfaces. Additionally the > console selection is now handled by Kconfig and no longer needs to be in > the config header. CONFIG_SYS_MALLOC_F_LEN=0x2000 was added to sync with > other boards. CONFIG_SPL_BLK and CONFIG_SPL_DM_MMC are disabled because > they currently do not allow the OMAP3-EVM (OMAP34XX) to actually boot. > > Signed-off-by: Derald D. Woods Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] db410c: add FIT support
On Fri, Aug 03, 2018 at 04:31:02PM +0300, Ramon Fried wrote: > 1. Add FIT support for DB410c defconfig. > 2. Don't overwrite bootargs (they're already >defined in Linux device tree for DB410c. > > Signed-off-by: Ramon Fried Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 03/11] configs: stm32f429-disco: Remove CONFIG_SYS_RAM_CS
On Fri, Aug 03, 2018 at 11:46:13AM +0200, Patrice Chotard wrote: > This flag is not used, remove it. > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 07/11] configs: stm32f4xx: Remove CONFIG_SYS_RAM_FREQ_DIV
On Fri, Aug 03, 2018 at 11:46:17AM +0200, Patrice Chotard wrote:
> Since commit bfea69ad2793 ("stm32f7: sdram: correct sdram
> configuration as per micron sdram"), CONFIG_SYS_RAM_FREQ_DIV
> flag is no more used, remove it.
>
> Signed-off-by: Patrice Chotard
Applied to u-boot/master, thanks!
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Re: [U-Boot] [U-Boot, v1, 05/11] configs: stm32f746-disco: Migrate CONFIG_CMD_CACHE to defconfig
On Fri, Aug 03, 2018 at 11:46:15AM +0200, Patrice Chotard wrote: > Remove CONFIG_CMD_CACHE from include/configs/stm32f746-disco.h > and enable it in stm32f746-disco_defconfig > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] MAINTAINERS: Update STM32MP fragments
On Mon, Aug 06, 2018 at 11:52:23AM +0200, Patrice Chotard wrote: > Add new drivers > Add Christophe Kerello and myself as maintainers > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 08/11] configs: stm32h743-evaluation: Add DISTRO_DEFAULT support
On Fri, Aug 03, 2018 at 11:46:18AM +0200, Patrice Chotard wrote: > Add DISTRO_DEFAULT support to be able to boot on mmc > by default on boot. > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2] stm32f7: board: Fix memory init
On Fri, Aug 03, 2018 at 01:09:55PM +0200, Patrice Chotard wrote:
> Commit 1473b12ad0b3 ("lib: fdtdec: Update ram_base to store ram start
> adddress") brings regression on STM32F7 which can't boot.
>
> Use fdtdec_setup_mem_size_base() to setup memory base and size.
> Use fdtdec_setup_memory_banksize() to setup memory bank base and size.
>
> Reported-by: Mark Olsson
> Signed-off-by: Patrice Chotard
> Cc: Mark Olsson
> Reviewed-by: Vikas Manocha
Applied to u-boot/master, thanks!
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Re: [U-Boot] [U-Boot, v1, 09/11] configs: stm32h743-discovery: Add DISTRO_DEFAULT support
On Fri, Aug 03, 2018 at 11:46:19AM +0200, Patrice Chotard wrote: > Add DISTRO_DEFAULT support to be able to boot on > mmc by default on boot. > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/2] tpm: sandbox: fix wrong assignment with a simplification
On Sun, Aug 05, 2018 at 06:53:07PM +0200, Miquel Raynal wrote: > The recv variable in sandbox_tpm2_fill_buf() is a pointer on a pointer > of a char array. It means accessing *recv is the char array pointer > itself while **recv is the first character of that array. There is no > need for such indirection here, so simplify the code. > > Simplifying things will make the last assignment right: "*recv = NULL" > is now correct. The issue has been found by the following Coverity > Scan report: > > CID 183371: Incorrect expression (UNUSED_VALUE) > Assigning value "4UL" to "*recv" here, but that stored value is > overwritten before it can be used. > 232 *recv += sizeof(rc); > 233 > 234 /* Add trailing \0 */ > 235 *recv = NULL; > > While at simplifying things, use '\0' instead of NULL when adding an > empty char at the end of the buffer. > > Reported-by: Tom Rini > Signed-off-by: Miquel Raynal > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm: bcm7445: Fix parallel make race condition
On Thu, Jul 26, 2018 at 10:55:37PM -0400, Thomas Fitzsimmons wrote: > Move the contents of prior_stage.h into bcmstb.h to prevent a build > failure when bcmstb.h is #include'ed before the asm/arch symbolic link > is present. > > Signed-off-by: Thomas Fitzsimmons Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v1, 01/11] board: stm32: use bi_dram[0].start instead of hardcoded value
On Fri, Aug 03, 2018 at 11:46:11AM +0200, Patrice Chotard wrote: > Use gd->bd->bi_dram[0].start initialized from DT instead of using > hardcoded CONFIG_SYS_SDRAM_BASE from config file. > > Remove unused CONFIG_SYS_RAM_BASE and CONFIG_SYS_SDRAM_BASE defines. > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] clk: at91: utmi: add timeout for utmi lock
On Fri, Aug 03, 2018 at 12:10:49PM +0300, Eugen Hristev wrote: > In case the slow clock is not properly configured, the UTMI clock > cannot lock the PLL, because UPLLCOUNT will "wait X slow clock cycles". > In this case U-boot will loop indefinitely. > Added a timeout in this case, to start U-boot even if UTMI clock is > not enabled, so the user can use different media if needed, or investigate. > > Signed-off-by: Eugen Hristev Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2] rsa: Fix LibreSSL before v2.7.0
On Wed, Jul 25, 2018 at 10:13:03PM -0400, nom...@palism.com wrote: > From: Caliph Nomble > > Fix LibreSSL compilation for versions before v2.7.0. > > Signed-off-by: Caliph Nomble > Reviewed-by: Jonathan Gray Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,1/1] fs: fix typo 'dumm'
On Sat, Aug 11, 2018 at 03:52:14PM +0200, Heinrich Schuchardt wrote: > %s/dumm /dummy / > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-fsl-qoriq master
On Mon, Aug 13, 2018 at 04:19:02PM +, York Sun wrote: > Tom, > > The following changes since commit 373413cce6260acdf14de762f94010b627a77a3b: > > Merge branch 'master' of git://git.denx.de/u-boot-video (2018-08-07 > 07:15:20 -0400) > > are available in the git repository at: > > git://git.denx.de/u-boot-fsl-qoriq.git > > for you to fetch changes up to 9add5a4b75a01cc5f69b9d5f6b30443f2088d7d8: > > armv8: layerscape: Enable EHCI access for LS1012A (2018-08-10 10:37:39 > -0700) > > > Tavis build log https://travis-ci.org/yorksun/u-boot/builds/414623801 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v3,1/1] avb2.0: add get_size_of_partition()
On Fri, Aug 10, 2018 at 04:59:59PM +0300, Igor Opaniuk wrote: > Implement get_size_of_partition() operation, > which is required by the latest upstream libavb [1]. > > [1] > https://android.googlesource.com/platform/external/avb/+/android-p-preview-5 > > Signed-off-by: Igor Opaniuk > Acked-by: Andrew F. Davis > Reviewed-by: Sam Protsenko Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: davinci: Full dm conversion
On Mon, Aug 13, 2018 at 5:09 PM Adam Ford wrote:
>
> On Mon, Aug 13, 2018 at 1:29 PM Simon Goldschmidt
> wrote:
> >
> > On Mon, Aug 13, 2018 at 3:46 PM Alex Kiernan wrote:
> > >
> > > On Mon, Aug 13, 2018 at 1:40 PM Adam Ford wrote:
> > > >
> > > > On Sat, Aug 11, 2018 at 3:09 PM Adam Ford wrote:
> > > > >
> > > > >
> > > > >
> > > > > On Sat, Aug 11, 2018, 1:24 PM Jagan Teki
> > > > > wrote:
> > > > >>
> > > > >> On Sat, Aug 11, 2018 at 6:12 PM, Adam Ford
> > > > >> wrote:
> > > > >> > On Fri, Aug 10, 2018 at 2:58 PM Adam Ford
> > > > >> > wrote:
> > > > >> >>
> > > > >> >> On Fri, Aug 10, 2018 at 7:42 AM Jagan Teki
> > > > >> >> wrote:
> > > > >> >> >
> > > > >> >> > On Fri, Aug 10, 2018 at 3:50 PM, Adam Ford
> > > > >> >> > wrote:
> > > > >> >> > > On Fri, Aug 10, 2018 at 12:14 AM Jagan Teki
> > > > >> >> > > wrote:
> > > > >> >> > >>
> > > > >> >> > >> On Wed, Aug 8, 2018 at 6:47 PM, Adam Ford
> > > > >> >> > >> wrote:
> > > > >> >> > >> > On Tue, Aug 7, 2018 at 1:29 AM Jagan Teki
> > > > >> >> > >> > wrote:
> > > > >> >> > >> >>
> > > > >> >> > >> >> davinci_spi now support dt along with platform data,
> > > > >> >> > >> >> respective boards need to switch into dm for the same.
> > > > >> >> > >> >>
> > > > >> >> > >> >> Cc: Adam Ford
> > > > >> >> > >> >> Cc: Vitaly Andrianov
> > > > >> >> > >> >> Cc: Stefano Babic
> > > > >> >> > >> >> Cc: Peter Howard
> > > > >> >> > >> >> Cc: Tom Rini
> > > > >> >> > >> >> Signed-off-by: Jagan Teki
> > > > >> >> > >> >> ---
> > > > >> >> > >> >> drivers/spi/Kconfig| 12 +-
> > > > >> >> > >> >> drivers/spi/davinci_spi.c | 289
> > > > >> >> > >> >> +++--
> > > > >> >> > >> >> include/dm/platform_data/spi_davinci.h | 15 ++
> > > > >> >> > >> >> 3 files changed, 97 insertions(+), 219 deletions(-)
> > > > >> >> > >> >> create mode 100644 include/dm/platform_data/spi_davinci.h
> > > > >> >> > >> >>
> > > > >> >> > >> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > > > >> >> > >> >> index d046e919b4..18ebff0231 100644
> > > > >> >> > >> >> --- a/drivers/spi/Kconfig
> > > > >> >> > >> >> +++ b/drivers/spi/Kconfig
> > > > >> >> > >> >> @@ -80,6 +80,12 @@ config CADENCE_QSPI
> > > > >> >> > >> >> used to access the SPI NOR flash on platforms
> > > > >> >> > >> >> embedding this
> > > > >> >> > >> >> Cadence IP core.
> > > > >> >> > >> >>
> > > > >> >> > >> >> +config DAVINCI_SPI
> > > > >> >> > >> >> + bool "Davinci & Keystone SPI driver"
> > > > >> >> > >> >> + depends on ARCH_DAVINCI || ARCH_KEYSTONE
> > > > >> >> > >> >> + help
> > > > >> >> > >> >> + Enable the Davinci SPI driver
> > > > >> >> > >> >> +
> > > > >> >> > >> >> config DESIGNWARE_SPI
> > > > >> >> > >> >> bool "Designware SPI driver"
> > > > >> >> > >> >> help
> > > > >> >> > >> >> @@ -281,12 +287,6 @@ config FSL_QSPI
> > > > >> >> > >> >> used to access the SPI NOR flash on platforms
> > > > >> >> > >> >> embedding this
> > > > >> >> > >> >> Freescale IP core.
> > > > >> >> > >> >>
> > > > >> >> > >> >> -config DAVINCI_SPI
> > > > >> >> > >> >> - bool "Davinci & Keystone SPI driver"
> > > > >> >> > >> >> - depends on ARCH_DAVINCI || ARCH_KEYSTONE
> > > > >> >> > >> >> - help
> > > > >> >> > >> >> - Enable the Davinci SPI driver
> > > > >> >> > >> >> -
> > > > >> >> > >> >> config SH_SPI
> > > > >> >> > >> >> bool "SuperH SPI driver"
> > > > >> >> > >> >> help
> > > > >> >> > >> >> diff --git a/drivers/spi/davinci_spi.c
> > > > >> >> > >> >> b/drivers/spi/davinci_spi.c
> > > > >> >> > >> >> index a822858323..5007e6c618 100644
> > > > >> >> > >> >> --- a/drivers/spi/davinci_spi.c
> > > > >> >> > >> >> +++ b/drivers/spi/davinci_spi.c
> > > > >> >> > >> >> @@ -14,6 +14,7 @@
> > > > >> >> > >> >> #include
> > > > >> >> > >> >> #include
> > > > >> >> > >> >> #include
> > > > >> >> > >> >> +#include
> > > > >> >> > >> >>
> > > > >> >> > >> >> /* SPIGCR0 */
> > > > >> >> > >> >> #define SPIGCR0_SPIENA_MASK0x1
> > > > >> >> > >> >> @@ -118,9 +119,6 @@ struct davinci_spi_regs {
> > > > >> >> > >> >>
> > > > >> >> > >> >> /* davinci spi slave */
> > > > >> >> > >> >> struct davinci_spi_slave {
> > > > >> >> > >> >> -#ifndef CONFIG_DM_SPI
> > > > >> >> > >> >> - struct spi_slave slave;
> > > > >> >> > >> >> -#endif
> > > > >> >> > >> >> struct davinci_spi_regs *regs;
> > > > >> >> > >> >> unsigned int freq; /* current SPI bus frequency */
> > > > >> >> > >> >> unsigned int mode; /* current SPI mode used */
> > > > >> >> > >> >> @@ -240,11 +238,43 @@ static int
> > > > >> >> > >> >> davinci_spi_read_write(struct davinci_spi_slave *ds,
> > > > >> >> > >> >> unsigned
> > > > >> >> > >> >> return 0;
> > > > >> >> > >> >> }
> > > > >> >> > >> >>
> > > > >> >> > >> >> +static int davinci_spi_set_speed(struct udevice *bus,
> > > > >> >> > >>
Re: [U-Boot] [PATCH] Kconfig: Migrate CONFIG_NR_DRAM_BANKS
On 08/14/2018 12:00 AM, Ramon Fried wrote: > Move CONFIG_NR_DRAM_BANKS from headers to Kconfig. > > Signed-off-by: Ramon Fried Somehow this seems to be missing a lot of cleanups in include/configs/ ... look at moveconfig.py > --- > Kconfig | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/Kconfig b/Kconfig > index db0f545e45..d96e3373c1 100644 > --- a/Kconfig > +++ b/Kconfig > @@ -104,6 +104,12 @@ config ENV_VARS_UBOOT_CONFIG > - CONFIG_SYS_VENDOR > - CONFIG_SYS_SOC > > +config NR_DRAM_BANKS > + int "Number of DRAM banks" > + default 4 > + help > + This defines the number of DRAM banks. > + > config SYS_BOOT_GET_CMDLINE > bool "Enable kernel command line setup" > help > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: davinci: Full dm conversion
On Mon, Aug 13, 2018 at 1:29 PM Simon Goldschmidt
wrote:
>
> On Mon, Aug 13, 2018 at 3:46 PM Alex Kiernan wrote:
> >
> > On Mon, Aug 13, 2018 at 1:40 PM Adam Ford wrote:
> > >
> > > On Sat, Aug 11, 2018 at 3:09 PM Adam Ford wrote:
> > > >
> > > >
> > > >
> > > > On Sat, Aug 11, 2018, 1:24 PM Jagan Teki
> > > > wrote:
> > > >>
> > > >> On Sat, Aug 11, 2018 at 6:12 PM, Adam Ford wrote:
> > > >> > On Fri, Aug 10, 2018 at 2:58 PM Adam Ford wrote:
> > > >> >>
> > > >> >> On Fri, Aug 10, 2018 at 7:42 AM Jagan Teki
> > > >> >> wrote:
> > > >> >> >
> > > >> >> > On Fri, Aug 10, 2018 at 3:50 PM, Adam Ford
> > > >> >> > wrote:
> > > >> >> > > On Fri, Aug 10, 2018 at 12:14 AM Jagan Teki
> > > >> >> > > wrote:
> > > >> >> > >>
> > > >> >> > >> On Wed, Aug 8, 2018 at 6:47 PM, Adam Ford
> > > >> >> > >> wrote:
> > > >> >> > >> > On Tue, Aug 7, 2018 at 1:29 AM Jagan Teki
> > > >> >> > >> > wrote:
> > > >> >> > >> >>
> > > >> >> > >> >> davinci_spi now support dt along with platform data,
> > > >> >> > >> >> respective boards need to switch into dm for the same.
> > > >> >> > >> >>
> > > >> >> > >> >> Cc: Adam Ford
> > > >> >> > >> >> Cc: Vitaly Andrianov
> > > >> >> > >> >> Cc: Stefano Babic
> > > >> >> > >> >> Cc: Peter Howard
> > > >> >> > >> >> Cc: Tom Rini
> > > >> >> > >> >> Signed-off-by: Jagan Teki
> > > >> >> > >> >> ---
> > > >> >> > >> >> drivers/spi/Kconfig| 12 +-
> > > >> >> > >> >> drivers/spi/davinci_spi.c | 289
> > > >> >> > >> >> +++--
> > > >> >> > >> >> include/dm/platform_data/spi_davinci.h | 15 ++
> > > >> >> > >> >> 3 files changed, 97 insertions(+), 219 deletions(-)
> > > >> >> > >> >> create mode 100644 include/dm/platform_data/spi_davinci.h
> > > >> >> > >> >>
> > > >> >> > >> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > > >> >> > >> >> index d046e919b4..18ebff0231 100644
> > > >> >> > >> >> --- a/drivers/spi/Kconfig
> > > >> >> > >> >> +++ b/drivers/spi/Kconfig
> > > >> >> > >> >> @@ -80,6 +80,12 @@ config CADENCE_QSPI
> > > >> >> > >> >> used to access the SPI NOR flash on platforms
> > > >> >> > >> >> embedding this
> > > >> >> > >> >> Cadence IP core.
> > > >> >> > >> >>
> > > >> >> > >> >> +config DAVINCI_SPI
> > > >> >> > >> >> + bool "Davinci & Keystone SPI driver"
> > > >> >> > >> >> + depends on ARCH_DAVINCI || ARCH_KEYSTONE
> > > >> >> > >> >> + help
> > > >> >> > >> >> + Enable the Davinci SPI driver
> > > >> >> > >> >> +
> > > >> >> > >> >> config DESIGNWARE_SPI
> > > >> >> > >> >> bool "Designware SPI driver"
> > > >> >> > >> >> help
> > > >> >> > >> >> @@ -281,12 +287,6 @@ config FSL_QSPI
> > > >> >> > >> >> used to access the SPI NOR flash on platforms
> > > >> >> > >> >> embedding this
> > > >> >> > >> >> Freescale IP core.
> > > >> >> > >> >>
> > > >> >> > >> >> -config DAVINCI_SPI
> > > >> >> > >> >> - bool "Davinci & Keystone SPI driver"
> > > >> >> > >> >> - depends on ARCH_DAVINCI || ARCH_KEYSTONE
> > > >> >> > >> >> - help
> > > >> >> > >> >> - Enable the Davinci SPI driver
> > > >> >> > >> >> -
> > > >> >> > >> >> config SH_SPI
> > > >> >> > >> >> bool "SuperH SPI driver"
> > > >> >> > >> >> help
> > > >> >> > >> >> diff --git a/drivers/spi/davinci_spi.c
> > > >> >> > >> >> b/drivers/spi/davinci_spi.c
> > > >> >> > >> >> index a822858323..5007e6c618 100644
> > > >> >> > >> >> --- a/drivers/spi/davinci_spi.c
> > > >> >> > >> >> +++ b/drivers/spi/davinci_spi.c
> > > >> >> > >> >> @@ -14,6 +14,7 @@
> > > >> >> > >> >> #include
> > > >> >> > >> >> #include
> > > >> >> > >> >> #include
> > > >> >> > >> >> +#include
> > > >> >> > >> >>
> > > >> >> > >> >> /* SPIGCR0 */
> > > >> >> > >> >> #define SPIGCR0_SPIENA_MASK0x1
> > > >> >> > >> >> @@ -118,9 +119,6 @@ struct davinci_spi_regs {
> > > >> >> > >> >>
> > > >> >> > >> >> /* davinci spi slave */
> > > >> >> > >> >> struct davinci_spi_slave {
> > > >> >> > >> >> -#ifndef CONFIG_DM_SPI
> > > >> >> > >> >> - struct spi_slave slave;
> > > >> >> > >> >> -#endif
> > > >> >> > >> >> struct davinci_spi_regs *regs;
> > > >> >> > >> >> unsigned int freq; /* current SPI bus frequency */
> > > >> >> > >> >> unsigned int mode; /* current SPI mode used */
> > > >> >> > >> >> @@ -240,11 +238,43 @@ static int
> > > >> >> > >> >> davinci_spi_read_write(struct davinci_spi_slave *ds,
> > > >> >> > >> >> unsigned
> > > >> >> > >> >> return 0;
> > > >> >> > >> >> }
> > > >> >> > >> >>
> > > >> >> > >> >> +static int davinci_spi_set_speed(struct udevice *bus, uint
> > > >> >> > >> >> max_hz)
> > > >> >> > >> >> +{
> > > >> >> > >> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> > > >> >> > >> >>
> > > >> >> > >> >> -static int __davinci_spi_claim_bus(struct
> > > >> >> > >> >> davinci_spi_slave *ds, int cs)
> > > >> >> > >> >> + debug("%s speed %u
Re: [U-Boot] [PATCH v4 5/5] malloc_simple: calloc: don't call memset if malloc failed
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote: > malloc_simple() can return 0 if out of memory. Don't call memset > from calloc() in this case but rely on the caller checking > the return value. > > Signed-off-by: Simon Goldschmidt > Reviewed-by: Marek Vasut Separate this from the patchset, this has nothing to do with socfpga . > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > common/malloc_simple.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/common/malloc_simple.c b/common/malloc_simple.c > index c14f8b59c1..871b5444bd 100644 > --- a/common/malloc_simple.c > +++ b/common/malloc_simple.c > @@ -57,7 +57,8 @@ void *calloc(size_t nmemb, size_t elem_size) > void *ptr; > > ptr = malloc(size); > - memset(ptr, '\0', size); > + if (ptr) > + memset(ptr, '\0', size); > > return ptr; > } > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/5] arm: socfpga: fix U-Boot running from fpga OnChip RAM
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote: > gd->env_addr points to pre-relocation address even after > relocation. This leads to an abort in env_callback_init > when loading the environment. > > Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC. > > Signed-off-by: Simon Goldschmidt > --- > > Changes in v4: enable this fix for all socfpga, not for gen5 only > Changes in v3: this patch is new in v3 > Changes in v2: None > > include/configs/socfpga_common.h | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/include/configs/socfpga_common.h > b/include/configs/socfpga_common.h > index 8ebf6b85fe..d1148b838b 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -284,6 +284,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START > #endif > > +/* When U-Boot is started from FPGA, prevent gd->env_addr to point into Multi-line comment should have this format /* * foo * bar */ > + * FPGA OnChip RAM after relocation > + */ > +#define CONFIG_SYS_EXTRA_ENV_RELOC > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE/* start of > monitor */ What you don't explain in the commit message is this last line. Why is this needed ? > /* Extra Environment */ > #ifndef CONFIG_SPL_BUILD > > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/5] arm: socfpga: fix SPL booting from fpga OnChip RAM
On 08/13/2018 09:34 PM, Simon Goldschmidt wrote:
> To boot from fpga OnChip RAM, some changes are required in SPL
> to ensure the code is linked to the correct address (in contrast
> to QSPI and MMC boot, FPGA boot executes SPL in place instead of
> copying it to SRAM) and that fpga OnChip RAM stays accessible while
> SPL runs (don't disable fpga bridges).
>
> This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA)
> for socfpga gen5 boards.
>
> Signed-off-by: Simon Goldschmidt
> ---
>
> Changes in v4: Adapted to changed previous patch
> Changes in v3: this patch is new in v3
> Changes in v2: None
>
> arch/arm/mach-socfpga/Kconfig | 12
> arch/arm/mach-socfpga/misc_gen5.c | 11 +--
> arch/arm/mach-socfpga/spl_gen5.c | 6 --
> include/configs/socfpga_common.h | 5 +
> 4 files changed, 30 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 5c1df2cf1f..a909395aac 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -132,3 +132,15 @@ config SYS_CONFIG_NAME
> default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>
> endif
> +
> +if TARGET_SOCFPGA_GEN5
> +
> +config SPL_SOCFPGA_BOOT_FROM_FPGA
> + bool "Allow booting SPL from FPGA OnChip RAM"
> + default n
> + help
> + Boot from FPGA: this changes the linker address for SPL code to run
> + from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAM
> + stays accessible while SPL runs.
> +
> +endif
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c
> b/arch/arm/mach-socfpga/misc_gen5.c
> index 429c3d6cd5..c82c3584dc 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void)
> setbits_le32(&scu_regs->sacr, 0xfff);
>
> /* Configure the L2 controller to make SDRAM start at 0 */
> - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
> + if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
> + /* remap.mpuzero, keep fpga bridge enabled */
> + writel(0x9, &nic301_regs->remap);
> + } else {
> + /* remap.mpuzero */
> + writel(0x1, &nic301_regs->remap);
> + }
> writel(0x1, &pl310->pl310_addr_filter_start);
> }
>
> @@ -209,7 +215,8 @@ int arch_early_init_r(void)
> for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
> iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
>
> - socfpga_bridges_reset(1);
> + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> + socfpga_bridges_reset(1);
>
> socfpga_sdram_remap_zero();
>
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c
> b/arch/arm/mach-socfpga/spl_gen5.c
> index be318cc0d9..0c7f6a8c84 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -93,7 +93,8 @@ void board_init_f(ulong dummy)
> /* Put everything into reset but L4WD0. */
> socfpga_per_reset_all();
> /* Put FPGA bridges into reset too. */
> - socfpga_bridges_reset(1);
> + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> + socfpga_bridges_reset(1);
>
> socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
> socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> @@ -163,5 +164,6 @@ void board_init_f(ulong dummy)
> hang();
> }
>
> - socfpga_bridges_reset(1);
> + if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
> + socfpga_bridges_reset(1);
> }
> diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_common.h
> index d1148b838b..99c5e39086 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> * 0xFFEz_ .. Malloc area (grows up to top)
> * 0xFFE3_ .. End of SRAM (top)
> */
> +#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA
> +/* SPL executed from FPGA */
> +#define CONFIG_SPL_TEXT_BASE 0xC000
> +#else
> #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
> +#endif
> #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
>
> #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
What about converting the SPL_TEXT_BASE to Kconfig , cfr my comment on
the previous version of the patch ?
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] fdt_support: Use CONFIG_NR_DRAM_BANKS if necessary
Hi Ramon,
> If CONFIG_NR_DRAM_BANKS is bigger than the default
> value (4) define MEMORY_BANKS_MAX as CONFIG_NR_DRAM_BANKS.
Also the Odroid XU3 uses 8 banks (but this is the fault of the board as
it has 4x512MiB probably).
I would also prefer to have the CONFIG_NR_DRAM_BANKS set to 4 (as it
was) and provide patch to convert it to Kconfig.
>
> Fixes: 2a1f4f1758b5 ("Revert "fdt_support: Use CONFIG_NR_DRAM_BANKS
> if defined"") Signed-off-by: Ramon Fried
> ---
> common/fdt_support.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/common/fdt_support.c b/common/fdt_support.c
> index 34d2bd59c4..d84f5dbade 100644
> --- a/common/fdt_support.c
> +++ b/common/fdt_support.c
> @@ -409,7 +409,11 @@ static int fdt_pack_reg(const void *fdt, void
> *buf, u64 *address, u64 *size, return p - (char *)buf;
> }
>
> +#if CONFIG_NR_DRAM_BANKS > 4
> +#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
> +#else
> #define MEMORY_BANKS_MAX 4
> +#endif
> int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int
> banks) {
> int err, nodeoffset;
Best regards,
Lukasz Majewski
--
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[U-Boot] [PATCH v4 4/5] arm: socfpga: fix SPL booting from fpga OnChip RAM
To boot from fpga OnChip RAM, some changes are required in SPL
to ensure the code is linked to the correct address (in contrast
to QSPI and MMC boot, FPGA boot executes SPL in place instead of
copying it to SRAM) and that fpga OnChip RAM stays accessible while
SPL runs (don't disable fpga bridges).
This adds a new config option (CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA)
for socfpga gen5 boards.
Signed-off-by: Simon Goldschmidt
---
Changes in v4: Adapted to changed previous patch
Changes in v3: this patch is new in v3
Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 12
arch/arm/mach-socfpga/misc_gen5.c | 11 +--
arch/arm/mach-socfpga/spl_gen5.c | 6 --
include/configs/socfpga_common.h | 5 +
4 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 5c1df2cf1f..a909395aac 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -132,3 +132,15 @@ config SYS_CONFIG_NAME
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
+
+if TARGET_SOCFPGA_GEN5
+
+config SPL_SOCFPGA_BOOT_FROM_FPGA
+ bool "Allow booting SPL from FPGA OnChip RAM"
+ default n
+ help
+ Boot from FPGA: this changes the linker address for SPL code to run
+ from FPGA OnChip memory instead of SRAM and ensures FPGA OnChip RAM
+ stays accessible while SPL runs.
+
+endif
diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
index 429c3d6cd5..c82c3584dc 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -187,7 +187,13 @@ void socfpga_sdram_remap_zero(void)
setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
- writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
+ if (CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA)) {
+ /* remap.mpuzero, keep fpga bridge enabled */
+ writel(0x9, &nic301_regs->remap);
+ } else {
+ /* remap.mpuzero */
+ writel(0x1, &nic301_regs->remap);
+ }
writel(0x1, &pl310->pl310_addr_filter_start);
}
@@ -209,7 +215,8 @@ int arch_early_init_r(void)
for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
- socfpga_bridges_reset(1);
+ if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
+ socfpga_bridges_reset(1);
socfpga_sdram_remap_zero();
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index be318cc0d9..0c7f6a8c84 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -93,7 +93,8 @@ void board_init_f(ulong dummy)
/* Put everything into reset but L4WD0. */
socfpga_per_reset_all();
/* Put FPGA bridges into reset too. */
- socfpga_bridges_reset(1);
+ if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
+ socfpga_bridges_reset(1);
socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
@@ -163,5 +164,6 @@ void board_init_f(ulong dummy)
hang();
}
- socfpga_bridges_reset(1);
+ if (!CONFIG_IS_ENABLED(SOCFPGA_BOOT_FROM_FPGA))
+ socfpga_bridges_reset(1);
}
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d1148b838b..99c5e39086 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -239,7 +239,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
* 0xFFEz_ .. Malloc area (grows up to top)
* 0xFFE3_ .. End of SRAM (top)
*/
+#if CONFIG_SPL_SOCFPGA_BOOT_FROM_FPGA
+/* SPL executed from FPGA */
+#define CONFIG_SPL_TEXT_BASE 0xC000
+#else
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
+#endif
#define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT_RAM_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
--
2.17.1
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[U-Boot] [PATCH v4 5/5] malloc_simple: calloc: don't call memset if malloc failed
malloc_simple() can return 0 if out of memory. Don't call memset from calloc() in this case but rely on the caller checking the return value. Signed-off-by: Simon Goldschmidt Reviewed-by: Marek Vasut --- Changes in v4: None Changes in v3: None Changes in v2: None common/malloc_simple.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/malloc_simple.c b/common/malloc_simple.c index c14f8b59c1..871b5444bd 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -57,7 +57,8 @@ void *calloc(size_t nmemb, size_t elem_size) void *ptr; ptr = malloc(size); - memset(ptr, '\0', size); + if (ptr) + memset(ptr, '\0', size); return ptr; } -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 3/5] arm: socfpga: gen5: combine some init code for SPL and U-Boot
Some of the code for low level system initialization in SPL's
board_init_f() and U-Boot's arch_early_init_r() is the same,
so let's combine it into a single function called from both.
Signed-off-by: Simon Goldschmidt
---
Changes in v4:
- rename socfpga_init_bus_mapping() to socfpga_sdram_remap_zero() and move
socfpga_bridges_reset(1) out of that function
Changes in v3: this patch is new in v3
Changes in v2: None
arch/arm/mach-socfpga/include/mach/misc.h | 4
arch/arm/mach-socfpga/misc_gen5.c | 29 +--
arch/arm/mach-socfpga/spl_gen5.c | 28 +-
3 files changed, 22 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index 7fe77ac8d8..218dd6b6e7 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -27,6 +27,10 @@ unsigned int shared_uart_com_port(const void *blob);
unsigned int uart_com_port(const void *blob);
#endif
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+void socfpga_sdram_remap_zero(void);
+#endif
+
void do_bridge_reset(int enable);
#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
index 848551c73f..429c3d6cd5 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -175,6 +175,22 @@ static void socfpga_nic301_slave_ns(void)
writel(0x1, &nic301_regs->sdrdata);
}
+void socfpga_sdram_remap_zero(void)
+{
+ socfpga_nic301_slave_ns();
+
+ /*
+* Private components security:
+* U-Boot : configure private timer, global timer and cpu component
+* access as non secure for kernel stage (as required by Linux)
+*/
+ setbits_le32(&scu_regs->sacr, 0xfff);
+
+ /* Configure the L2 controller to make SDRAM start at 0 */
+ writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
+ writel(0x1, &pl310->pl310_addr_filter_start);
+}
+
static u32 iswgrp_handoff[8];
int arch_early_init_r(void)
@@ -195,18 +211,7 @@ int arch_early_init_r(void)
socfpga_bridges_reset(1);
- socfpga_nic301_slave_ns();
-
- /*
-* Private components security:
-* U-Boot : configure private timer, global timer and cpu component
-* access as non secure for kernel stage (as required by Linux)
-*/
- setbits_le32(&scu_regs->sacr, 0xfff);
-
- /* Configure the L2 controller to make SDRAM start at 0 */
- writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
- writel(0x1, &pl310->pl310_addr_filter_start);
+ socfpga_sdram_remap_zero();
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 0e685f6ee5..be318cc0d9 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -5,7 +5,6 @@
#include
#include
-#include
#include
#include
#include
@@ -17,8 +16,6 @@
#include
#include
#include
-#include
-#include
#include
#include
#include
@@ -26,12 +23,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct scu_registers *scu_regs =
- (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
-static struct nic301_registers *nic301_regs =
- (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
@@ -72,16 +63,6 @@ u32 spl_boot_mode(const u32 boot_device)
}
#endif
-static void socfpga_nic301_slave_ns(void)
-{
- writel(0x1, &nic301_regs->lwhps2fpgaregs);
- writel(0x1, &nic301_regs->hps2fpgaregs);
- writel(0x1, &nic301_regs->acp);
- writel(0x1, &nic301_regs->rom);
- writel(0x1, &nic301_regs->ocram);
- writel(0x1, &nic301_regs->sdrdata);
-}
-
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -103,14 +84,7 @@ void board_init_f(ulong dummy)
memset(__bss_start, 0, __bss_end - __bss_start);
- socfpga_nic301_slave_ns();
-
- /* Configure ARM MPU SNSAC register. */
- setbits_le32(&scu_regs->sacr, 0xfff);
-
- /* Remap SDRAM to 0x0 */
- writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
- writel(0x1, &pl310->pl310_addr_filter_start);
+ socfpga_sdram_remap_zero();
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
--
2.17.1
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[U-Boot] [PATCH v4 2/5] arm: socfpga: fix U-Boot running from fpga OnChip RAM
gd->env_addr points to pre-relocation address even after relocation. This leads to an abort in env_callback_init when loading the environment. Fix this by enabling CONFIG_SYS_EXTRA_ENV_RELOC. Signed-off-by: Simon Goldschmidt --- Changes in v4: enable this fix for all socfpga, not for gen5 only Changes in v3: this patch is new in v3 Changes in v2: None include/configs/socfpga_common.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8ebf6b85fe..d1148b838b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -284,6 +284,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START #endif +/* When U-Boot is started from FPGA, prevent gd->env_addr to point into + * FPGA OnChip RAM after relocation + */ +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE/* start of monitor */ + /* Extra Environment */ #ifndef CONFIG_SPL_BUILD -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 0/5] Get socfpga gen5 SPL working again.
Socfpga gen5 SPL has been broken since moving to DM serial with v2018.07. Also, U-Boot console output has been broken since then. This series fixes this and makes some related small improvements. Changes in v4: - dropped already merged patches 1, 3 and 4 - enable the env relocatation for all socfpga, not for gen5 only - rename socfpga_init_bus_mapping() to socfpga_sdram_remap_zero() and move socfpga_bridges_reset(1) out of that function Changes in v3: - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board specific dts files since this can change per board - added patches 5-7 to boot SPL and U-Boot from fpga OnChip RAM - dropped Patch 5/6 "serial: ns16550: fix debug uart putc called before init" (this needs a more generic fix) Changes in v2: - Improved comment on patch 1 - Removing gd->malloc_base assignment at the end of board_init_f() moved to an extra patch - don't change printf() to debug() in reset_manager_gen5.c socfpga_bridges_reset() (instead make debug uart handle this) - make ns16550 debug uart handle putc being called before init - removed the assignment of gd->malloc_limit from board_init() Simon Goldschmidt (5): arm: socfpga: fix device trees to work with DM serial arm: socfpga: fix U-Boot running from fpga OnChip RAM arm: socfpga: gen5: combine some init code for SPL and U-Boot arm: socfpga: fix SPL booting from fpga OnChip RAM malloc_simple: calloc: don't call memset if malloc failed arch/arm/dts/socfpga_arria5_socdk.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts| 5 +++ .../arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_is1.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_sockit.dts | 5 +++ arch/arm/dts/socfpga_cyclone5_socrates.dts| 5 +++ arch/arm/dts/socfpga_cyclone5_sr1500.dts | 2 + arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 5 +++ arch/arm/mach-socfpga/Kconfig | 12 ++ arch/arm/mach-socfpga/include/mach/misc.h | 4 ++ arch/arm/mach-socfpga/misc_gen5.c | 38 --- arch/arm/mach-socfpga/spl_gen5.c | 34 +++-- common/malloc_simple.c| 3 +- include/configs/socfpga_common.h | 11 ++ 17 files changed, 111 insertions(+), 43 deletions(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 1/5] arm: socfpga: fix device trees to work with DM serial
Device trees need to have the serial console device available
before relocation and require a stdout-path in chosen at least
for SPL to have a console.
Signed-off-by: Simon Goldschmidt
---
Changes in v4: None
Changes in v3:
- moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board
specific dts files since this can change per board
Changes in v2: None
arch/arm/dts/socfpga_arria5_socdk.dts | 5 +
arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 5 +
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 5 +
arch/arm/dts/socfpga_cyclone5_de10_nano.dts| 5 +
arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 +
arch/arm/dts/socfpga_cyclone5_is1.dts | 5 +
arch/arm/dts/socfpga_cyclone5_socdk.dts| 5 +
arch/arm/dts/socfpga_cyclone5_sockit.dts | 5 +
arch/arm/dts/socfpga_cyclone5_socrates.dts | 5 +
arch/arm/dts/socfpga_cyclone5_sr1500.dts | 2 ++
arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 5 +
11 files changed, 52 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts
b/arch/arm/dts/socfpga_arria5_socdk.dts
index 449ba9cbb9..6f4de2f563 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
memory {
@@ -99,3 +100,7 @@
cdns,tslch-ns = <4>;
};
};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index aeb327dd5b..139a70f265 100644
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
@@ -56,3 +57,7 @@
disable-over-current;
status = "okay";
};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
index f4a98e4bb0..d504150edd 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
@@ -75,3 +76,7 @@
&usb1 {
status = "okay";
};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index 7da2d8b043..d4dd9e9bca 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -13,6 +13,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
@@ -65,3 +66,7 @@
&usb1 {
status = "okay";
};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index e6fadb4fc9..f62292284d 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
@@ -63,3 +64,7 @@
&usb1 {
status = "okay";
};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts
b/arch/arm/dts/socfpga_cyclone5_is1.dts
index aa1ce2c3e2..4e94d86114 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
memory {
@@ -102,3 +103,7 @@
&usb1 {
status = "okay";
};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 55c70abb02..c28be67bb9 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
memory {
@@ -113,3 +114,7 @@
&usb1 {
status = "okay";
};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts
b/arch/arm/dts/socfpga_cyclone5_sockit.dts
index 08d8356d80..c7a6cf2db8 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -11,6 +11,7 @@
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
aliases {
@@ -93,3 +94,7 @@
&
Re: [U-Boot] [U-Boot,6/8] efi_loader: Pass file path to payload
On 04/11/2016 04:16 PM, Alexander Graf wrote:
> The payload gets information on where it got loaded from. This includes
> the device as well as file path.
>
> So far we've treated both as the same thing and always gave it the device
> name. However, in some situations grub2 actually wants to find its loading
> path to find its configuration file.
>
> So let's split the two semantically separte bits into separate structs and
> pass the loaded file name into our payload when we load it using "load".
>
> Signed-off-by: Alexander Graf
> ---
> cmd/bootefi.c| 32 +---
> cmd/fs.c | 3 ++-
> include/efi_loader.h | 5 +++--
> 3 files changed, 30 insertions(+), 10 deletions(-)
>
> diff --git a/cmd/bootefi.c b/cmd/bootefi.c
> index 0d09aa1..adcf645 100644
> --- a/cmd/bootefi.c
> +++ b/cmd/bootefi.c
> @@ -34,17 +34,30 @@ static struct efi_device_path_file_path
> bootefi_image_path[] = {
> }
> };
>
> +static struct efi_device_path_file_path bootefi_device_path[] = {
> + {
> + .dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
> + .dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
> + .dp.length = sizeof(bootefi_image_path[0]),
> + .str = { 'b','o','o','t','e','f','i' },
> + }, {
> + .dp.type = DEVICE_PATH_TYPE_END,
> + .dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
> + .dp.length = sizeof(bootefi_image_path[0]),
> + }
> +};
> +
> static efi_status_t bootefi_open_dp(void *handle, efi_guid_t *protocol,
> void **protocol_interface, void *agent_handle,
> void *controller_handle, uint32_t attributes)
> {
> - *protocol_interface = bootefi_image_path;
> + *protocol_interface = bootefi_device_path;
> return EFI_SUCCESS;
> }
>
> /* The EFI loaded_image interface for the image executed via "bootefi" */
> static struct efi_loaded_image loaded_image_info = {
> - .device_handle = bootefi_image_path,
> + .device_handle = bootefi_device_path,
> .file_path = bootefi_image_path,
> };
>
> @@ -63,7 +76,7 @@ static struct efi_object loaded_image_info_obj = {
> {
> /*
>* When asking for the device path interface, return
> - * bootefi_image_path
> + * bootefi_device_path
>*/
> .guid = &efi_guid_device_path,
> .open = &bootefi_open_dp,
> @@ -73,11 +86,11 @@ static struct efi_object loaded_image_info_obj = {
>
> /* The EFI object struct for the device the "bootefi" image was loaded from
> */
> static struct efi_object bootefi_device_obj = {
> - .handle = bootefi_image_path,
> + .handle = bootefi_device_path,
> .protocols = {
> {
> /* When asking for the device path interface, return
> - * bootefi_image_path */
> + * bootefi_device_path */
> .guid = &efi_guid_device_path,
> .open = &bootefi_open_dp,
> }
> @@ -192,7 +205,7 @@ U_BOOT_CMD(
> bootefi_help_text
> );
>
> -void efi_set_bootdev(const char *dev, const char *devnr)
> +void efi_set_bootdev(const char *dev, const char *devnr, const char *path)
> {
> __maybe_unused struct blk_desc *desc;
> char devname[16] = { 0 }; /* dp->str is u16[16] long */
> @@ -217,7 +230,12 @@ void efi_set_bootdev(const char *dev, const char *devnr)
> if (colon)
> *colon = '\0';
>
> - /* Patch the bootefi_image_path to the target device */
> + /* Patch bootefi_device_path to the target device */
> + memset(bootefi_device_path[0].str, 0,
> sizeof(bootefi_device_path[0].str));
> + ascii2unicode(bootefi_device_path[0].str, devname);
> +
> + /* Patch bootefi_image_path to the target file path */
> memset(bootefi_image_path[0].str, 0, sizeof(bootefi_image_path[0].str));
> + snprintf(devname, sizeof(devname), "%s", path);
> ascii2unicode(bootefi_image_path[0].str, devname);
> }
> diff --git a/cmd/fs.c b/cmd/fs.c
> index be8f289..abfe5be 100644
> --- a/cmd/fs.c
> +++ b/cmd/fs.c
> @@ -27,7 +27,8 @@ U_BOOT_CMD(
> static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
> char * const argv[])
> {
> - efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "");
> + efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "",
> + (argc > 4) ? argv[4] : "");
Hi Alex,
efi_set_bootdev is used here to set both the device from which a file
was loaded and the filename used as image_path.
Why should we assume that the last file loaded is the EFI executable and
not the device tree (or any other file)?
Shouldn't we at least check that this file is an EFI executable or driver?
Best regards
Heinrich
> return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY);
>
[U-Boot] [PATCH] ARM: socfpga: Register the FPGA on A10 in SPL again
The restructuring of the SPL dropped registration of the FPGA in SPL,
readd it.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Fixes: c859f2a77d98 ("arm: socfpga: Restructure the SPL file")
---
arch/arm/mach-socfpga/spl_a10.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index fe4782c9cb..4164e4d31c 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -79,6 +80,11 @@ void spl_board_init(void)
/* enable console uart printing */
preloader_console_init();
+
+ WATCHDOG_RESET();
+
+ /* Add device descriptor to FPGA device table */
+ socfpga_fpga_add();
}
void board_init_f(ulong dummy)
--
2.16.2
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[U-Boot] [PATCH] ARM: socfpga: Enable DM ethernet on A10
Enable DM ethernet framework on Arria10, so that the designware GMAC can be probed from DT as it should be. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Ley Foon Tan --- configs/socfpga_arria10_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 4278bd06c8..2fc9e6bb1a 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -34,5 +34,7 @@ CONFIG_DWAPB_GPIO=y CONFIG_DM_MMC=y CONFIG_MTD_DEVICE=y CONFIG_MTD_PARTITIONS=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y CONFIG_SPI=y CONFIG_USE_TINY_PRINTF=y -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] Kconfig: Migrate CONFIG_NR_DRAM_BANKS
Move CONFIG_NR_DRAM_BANKS from headers to Kconfig. Signed-off-by: Ramon Fried --- Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Kconfig b/Kconfig index db0f545e45..d96e3373c1 100644 --- a/Kconfig +++ b/Kconfig @@ -104,6 +104,12 @@ config ENV_VARS_UBOOT_CONFIG - CONFIG_SYS_VENDOR - CONFIG_SYS_SOC +config NR_DRAM_BANKS + int "Number of DRAM banks" + default 4 + help + This defines the number of DRAM banks. + config SYS_BOOT_GET_CMDLINE bool "Enable kernel command line setup" help -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/3] ARM: socfpga: Remove adhoc ethernet reset and configuration
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Ley Foon Tan
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-socfpga/Kconfig| 5
arch/arm/mach-socfpga/misc_arria10.c | 49
3 files changed, 6 insertions(+), 50 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 63ec02403a..9f5eaf8591 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -772,7 +772,7 @@ config ARCH_SNAPDRAGON
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R
- select ARCH_MISC_INIT
+ select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
select ARM64 if TARGET_SOCFPGA_STRATIX10
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 63ce32ff66..80be1dc30a 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -14,6 +14,11 @@ config TARGET_SOCFPGA_ARRIA10
select DM_I2C
select DM_RESET
select SPL_DM_RESET if SPL
+ select REGMAP
+ select SPL_REGMAP if SPL
+ select SYSCON
+ select SPL_SYSCON if SPL
+ select ETH_DESIGNWARE_SOCFPGA
config TARGET_SOCFPGA_CYCLONE5
bool
diff --git a/arch/arm/mach-socfpga/misc_arria10.c
b/arch/arm/mach-socfpga/misc_arria10.c
index b59953068d..284e076ad6 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -38,48 +38,6 @@ static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void arria10_dwmac_reset(const u8 of_reset_id, const u8 phymode)
-{
- u32 reset;
-
- if (of_reset_id == EMAC0_RESET) {
- reset = SOCFPGA_RESET(EMAC0);
- } else if (of_reset_id == EMAC1_RESET) {
- reset = SOCFPGA_RESET(EMAC1);
- } else if (of_reset_id == EMAC2_RESET) {
- reset = SOCFPGA_RESET(EMAC2);
- } else {
- printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
- return;
- }
-
- clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
- phymode);
-
- /* Release the EMAC controller from reset */
- socfpga_per_reset(reset, 0);
-}
-
-static int socfpga_eth_reset(void)
-{
- /* Put all GMACs into RESET state. */
- socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
- socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
- socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1);
- return socfpga_eth_reset_common(arria10_dwmac_reset);
-};
-#else
-static int socfpga_eth_reset(void)
-{
- return 0;
-};
-#endif
-
#if defined(CONFIG_SPL_BUILD)
/*
+ * This function initializes security policies to be consistent across
@@ -143,13 +101,6 @@ int print_cpuinfo(void)
}
#endif
-#ifdef CONFIG_ARCH_MISC_INIT
-int arch_misc_init(void)
-{
- return socfpga_eth_reset();
-}
-#endif
-
void do_bridge_reset(int enable)
{
if (enable)
--
2.16.2
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[U-Boot] [PATCH 2/3] ARM: socfpga: Zap unused reset code
Remove code from the reset manager that is never called.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Ley Foon Tan
---
.../include/mach/reset_manager_arria10.h | 3 -
arch/arm/mach-socfpga/reset_manager_arria10.c | 123 -
2 files changed, 126 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 66c70128b4..6623ebee65 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -10,10 +10,7 @@
void socfpga_watchdog_disable(void);
void socfpga_reset_deassert_noc_ddr_scheduler(void);
-int socfpga_is_wdt_in_reset(void);
-void socfpga_emac_manage_reset(ulong emacbase, u32 state);
int socfpga_reset_deassert_bridges_handoff(void);
-void socfpga_reset_assert_fpga_connected_peripherals(void);
void socfpga_reset_deassert_osc1wd0(void);
int socfpga_bridges_reset(void);
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
b/arch/arm/mach-socfpga/reset_manager_arria10.c
index bcdb349752..471a3045af 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -20,59 +20,6 @@ static const struct socfpga_reset_manager
*reset_manager_base =
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
-
-static const u32 per0fpgamasks[] = {
- ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
- ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
- ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
- ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK,
- ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
- ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK,
- 0, /* i2c0 per1mod */
- 0, /* i2c1 per1mod */
- 0, /* i2c0_emac */
- 0, /* i2c1_emac */
- 0, /* i2c2_emac */
- ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
- ALT_RSTMGR_PER0MODRST_NAND_SET_MSK,
- ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
- ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK |
- ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK,
- 0, /* uart0 per1mod */
- 0, /* uart1 per1mod */
-};
-
-static const u32 per1fpgamasks[] = {
- 0, /* emac0 per0mod */
- 0, /* emac1 per0mod */
- 0, /* emac2 per0mod */
- ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK,
- ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK,
- ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */
- ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */
- ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */
- 0, /* nand per0mod */
- 0, /* qspi per0mod */
- 0, /* sdmmc per0mod */
- 0, /* spim0 per0mod */
- 0, /* spim1 per0mod */
- 0, /* spis0 per0mod */
- 0, /* spis1 per0mod */
- ALT_RSTMGR_PER1MODRST_UART0_SET_MSK,
- ALT_RSTMGR_PER1MODRST_UART1_SET_MSK,
-};
-
struct bridge_cfg {
int compat_id;
u32 mask_noc;
@@ -127,56 +74,6 @@ void socfpga_reset_deassert_noc_ddr_scheduler(void)
ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
}
-/* Check whether Watchdog in reset state? */
-int socfpga_is_wdt_in_reset(void)
-{
- u32 val;
-
- val = readl(&reset_manager_base->per1modrst);
- val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
-
- /* return 0x1 if watchdog in reset */
- return val;
-}
-
-/* emacbase: base address of emac to enable/disable reset
- * state: 0 - disable reset, !0 - enable reset
- */
-void socfpga_emac_manage_reset(ulong emacbase, u32 state)
-{
- ulong eccmask;
- ulong emacmask;
-
- switch (emacbase) {
- case SOCFPGA_EMAC0_ADDRESS:
- eccmask = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK;
- emacmask = ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK;
- break;
- case SOCFPGA_EMAC1_ADDRESS:
- eccmask = ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK;
- emacmask = ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK;
- break;
- case SOCFPGA_EMAC2_ADDRESS:
- eccmask = ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK;
- emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK;
- break;
- default:
- pr_err("emac base address unexpected! %lx", emacbase);
- hang();
- break;
- }
-
- if (state) {
- /* Enable ECC O
[U-Boot] [PATCH] ARM: socfpga: Enable DM reset framework on A10
Enable the DM reset framework and DM reset driver on Arria10 both in U-Boot and in SPL. This lets U-Boot parse reset control from DT. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Ley Foon Tan --- arch/arm/mach-socfpga/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5c1df2cf1f..368f217fc6 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10 bool select ALTERA_SDRAM select SPL_BOARD_INIT if SPL + select DM_RESET + select SPL_DM_RESET if SPL config TARGET_SOCFPGA_CYCLONE5 bool -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/5] ARM: dts: socfpga: Add i2c alias to A10 SoCDK
The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign
the I2C bus a bus number. Add the missing alias.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10_socdk.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi
b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 3f59f02577..4018a5b929 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -23,6 +23,7 @@
aliases {
ethernet0 = &gmac0;
serial0 = &uart1;
+ i2c0 = &i2c1;
};
chosen {
--
2.16.2
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[U-Boot] [PATCH] ARM: socfpga: Zap all the UART handling complexity
The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and console framework. Nuke all this comlexity, since it is just
duplicating the same functionality, badly.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
---
arch/arm/mach-socfpga/include/mach/misc.h | 6 -
.../include/mach/reset_manager_arria10.h | 1 -
arch/arm/mach-socfpga/misc_arria10.c | 127 -
arch/arm/mach-socfpga/reset_manager_arria10.c | 12 --
arch/arm/mach-socfpga/spl_a10.c| 3 -
5 files changed, 149 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index 7fe77ac8d8..8753d503e1 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -21,12 +21,6 @@ void socfpga_fpga_add(void);
static inline void socfpga_fpga_add(void) {}
#endif
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-unsigned int dedicated_uart_com_port(const void *blob);
-unsigned int shared_uart_com_port(const void *blob);
-unsigned int uart_com_port(const void *blob);
-#endif
-
void do_bridge_reset(int enable);
#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 522f714d76..66c70128b4 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -15,7 +15,6 @@ void socfpga_emac_manage_reset(ulong emacbase, u32 state);
int socfpga_reset_deassert_bridges_handoff(void);
void socfpga_reset_assert_fpga_connected_peripherals(void);
void socfpga_reset_deassert_osc1wd0(void);
-void socfpga_reset_uart(int assert);
int socfpga_bridges_reset(void);
struct socfpga_reset_manager {
diff --git a/arch/arm/mach-socfpga/misc_arria10.c
b/arch/arm/mach-socfpga/misc_arria10.c
index 80bf2f036f..b59953068d 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -127,133 +127,6 @@ int arch_early_init_r(void)
}
#endif
-/*
- * This function looking the 1st encounter UART peripheral,
- * and then return its offset of the dedicated/shared IO pin
- * mux. offset value (zero and above).
- */
-static int find_peripheral_uart(const void *blob,
- int child, const char *node_name)
-{
- int len;
- fdt_addr_t base_addr = 0;
- fdt_size_t size;
- const u32 *cell;
- u32 value, offset = 0;
-
- base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
- if (base_addr != FDT_ADDR_T_NONE) {
- cell = fdt_getprop(blob, child, "pinctrl-single,pins",
- &len);
- if (cell != NULL) {
- for (; len > 0; len -= (2 * sizeof(u32))) {
- offset = fdt32_to_cpu(*cell++);
- value = fdt32_to_cpu(*cell++);
- /* Found UART peripheral. */
- if (value == PINMUX_UART)
- return offset;
- }
- }
- }
- return -EINVAL;
-}
-
-/*
- * This function looks up the 1st encounter UART peripheral,
- * and then return its offset of the dedicated/shared IO pin
- * mux. UART peripheral is found if the offset is not in negative
- * value.
- */
-static int is_peripheral_uart_true(const void *blob,
- int node, const char *child_name)
-{
- int child, len;
- const char *node_name;
-
- child = fdt_first_subnode(blob, node);
-
- if (child < 0)
- return -EINVAL;
-
- node_name = fdt_get_name(blob, child, &len);
-
- while (node_name) {
- if (!strcmp(child_name, node_name))
- return find_peripheral_uart(blob, child, node_name);
-
- child = fdt_next_subnode(blob, child);
- if (child < 0)
- break;
-
- node_name = fdt_get_name(blob, child, &len);
- }
-
- return -1;
-}
-
-/*
- * This function looking the 1st encounter UART dedicated IO peripheral,
- * and then return based address of the 1st encounter UART dedicated
- * IO peripheral.
- */
-unsigned int dedicated_uart_com_port(const void *blob)
-{
- int node;
-
- node = fdtdec_next_compatible(blob, 0,
-COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
- if (node < 0)
- return 0;
-
- if (is_peripheral_uart_true(blob, node, "dedicated") >= 0)
- return SOCFPGA_UART1_ADDRESS;
-
- return 0;
-}
-
-/*
- * This function looking the 1st encounter UART shared IO peripheral, and then
- * return based address of the 1st encounter UART shared IO peripheral.
- */
-unsigned int shared_uart_com_port(const void *blob)
-{
- int node, ret;
-
- node
[U-Boot] [PATCH 1/3] net: designware: socfpga: Add Arria10 extras
Add wrapper around the designware MAC driver to handle the SoCFPGA
specific configuration bits. On Arria10, this is configuration of
syscon phy_intf.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Joe Hershberger
---
NOTE: This driver is not enabled on Gen5 or Stratix10 as the
implementation for its specifics is missing thus far.
The driver can be safely enabled though, as the behavior
of the plain designware mac driver will be retained.
---
drivers/net/Kconfig | 8 +++
drivers/net/Makefile| 1 +
drivers/net/dwmac_socfpga.c | 143
3 files changed, 152 insertions(+)
create mode 100644 drivers/net/dwmac_socfpga.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index f762b0898d..d86da7760e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -150,6 +150,14 @@ config ETH_DESIGNWARE
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
provide the PHY (physical media interface).
+config ETH_DESIGNWARE_SOCFPGA
+ bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC"
+ depends on DM_ETH && ETH_DESIGNWARE
+ help
+ The Altera SoCFPGA requires additional configuration of the
+ Altera system manager to correctly interface with the PHY.
+ This code handles those SoC specifics.
+
config ETHOC
bool "OpenCores 10/100 Mbps Ethernet MAC"
help
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index c1ed44e21f..48a2878071 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_TULIP) += dc2114x.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
+obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DNET) += dnet.o
obj-$(CONFIG_E1000) += e1000.o
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
new file mode 100644
index 00..08fc9677c4
--- /dev/null
+++ b/drivers/net/dwmac_socfpga.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marek Vasut
+ *
+ * Altera SoCFPGA EMAC extras
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "designware.h"
+
+#include
+
+enum dwmac_type {
+ DWMAC_SOCFPGA_GEN5 = 0,
+ DWMAC_SOCFPGA_ARRIA10,
+ DWMAC_SOCFPGA_STRATIX10,
+};
+
+struct dwmac_socfpga_platdata {
+ struct dw_eth_pdata dw_eth_pdata;
+ enum dwmac_type type;
+ void*phy_intf;
+};
+
+static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+ struct regmap *regmap;
+ struct ofnode_phandle_args args;
+ void *range;
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
+2, 0, &args);
+ if (ret) {
+ dev_err(dev, "Failed to get syscon: %d\n", ret);
+ return ret;
+ }
+
+ if (args.args_count != 2) {
+ dev_err(dev, "Invalid number of syscon args\n");
+ return -EINVAL;
+ }
+
+ regmap = syscon_node_to_regmap(args.node);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ dev_err(dev, "Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ range = regmap_get_range(regmap, 0);
+ if (!range) {
+ dev_err(dev, "Failed to get regmap range\n");
+ return -ENOMEM;
+ }
+
+ pdata->phy_intf = range + args.args[0];
+
+ /*
+* Sadly, the Altera DT bindings don't have SoC-specific compatibles,
+* so we have to guesstimate which SoC we are running on from the
+* DWMAC version. Luckily, Altera at least updated the DWMAC with
+* each SoC.
+*/
+ if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.70a"))
+ pdata->type = DWMAC_SOCFPGA_GEN5;
+
+ if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.72a"))
+ pdata->type = DWMAC_SOCFPGA_ARRIA10;
+
+ if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.74a"))
+ pdata->type = DWMAC_SOCFPGA_STRATIX10;
+
+ return designware_eth_ofdata_to_platdata(dev);
+}
+
+static int dwmac_socfpga_probe(struct udevice *dev)
+{
+ struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
+ struct reset_ctl_bulk reset_bulk;
+ int ret;
+ u8 modereg;
+
+ if (pdata->type == DWMAC_SOCFPGA_ARRIA10) {
+ switch (edata->phy_interface) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ moder
[U-Boot] [PATCH] ARM: socfpga: Enable DM I2C framework on A10
Enable the DM I2C framework on Arria10, so that the DM capable Designware I2C driver can handle the reset via DM reset framework. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Ley Foon Tan --- arch/arm/mach-socfpga/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 368f217fc6..63ce32ff66 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,6 +11,7 @@ config TARGET_SOCFPGA_ARRIA10 bool select ALTERA_SDRAM select SPL_BOARD_INIT if SPL + select DM_I2C select DM_RESET select SPL_DM_RESET if SPL -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/5] ARM: dts: socfpga: Add missing I2C resets
The I2Cx resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Ley Foon Tan --- arch/arm/dts/socfpga_arria10.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index f5f1b8db9b..05425a03fc 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -550,6 +550,8 @@ reg = <0xffc02200 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C0_RESET>; + reset-names = "i2c"; status = "disabled"; }; @@ -560,6 +562,8 @@ reg = <0xffc02300 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C1_RESET>; + reset-names = "i2c"; status = "disabled"; }; @@ -570,6 +574,8 @@ reg = <0xffc02400 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C2_RESET>; + reset-names = "i2c"; status = "disabled"; }; @@ -580,6 +586,8 @@ reg = <0xffc02500 0x100>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C3_RESET>; + reset-names = "i2c"; status = "disabled"; }; @@ -590,6 +598,8 @@ reg = <0xffc02600 0x100>; interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C4_RESET>; + reset-names = "i2c"; status = "disabled"; }; -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/5] ARM: dts: socfpga: Fix Arria10 GMAC resets
Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs to work and add GMAC2 reset and OCP resets which were missing altogether. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Ley Foon Tan --- arch/arm/dts/socfpga_arria10.dtsi | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index aafcfe9ce4..f5f1b8db9b 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -428,8 +428,8 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -448,8 +448,8 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -468,6 +468,8 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/5] ARM: dts: socfpga: Add missing UART resets
The UART0 and UART1 resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Ley Foon Tan --- arch/arm/dts/socfpga_arria10.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 51b31dc2b5..aafcfe9ce4 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -797,6 +797,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART0_RESET>; status = "disabled"; }; @@ -807,6 +808,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART1_RESET>; status = "disabled"; }; -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/5] ARM: dts: socfpga: Flag reset manager on A10 as pre-reloc
The Altera reset manager block must be available very early on, since
it controls ie. UART resets. Flag it as pre-reloc.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi
b/arch/arm/dts/socfpga_arria10.dtsi
index 2f935a21e9..51b31dc2b5 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -55,6 +55,7 @@
device_type = "soc";
interrupt-parent = <&intc>;
ranges;
+ u-boot,dm-pre-reloc;
amba {
compatible = "simple-bus";
@@ -735,6 +736,7 @@
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x100>;
altr,modrst-offset = <0x20>;
+ u-boot,dm-pre-reloc;
};
scu: snoop-control-unit@c000 {
--
2.16.2
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[U-Boot] [PATCH] fdt_support: Use CONFIG_NR_DRAM_BANKS if necessary
If CONFIG_NR_DRAM_BANKS is bigger than the default
value (4) define MEMORY_BANKS_MAX as CONFIG_NR_DRAM_BANKS.
Fixes: 2a1f4f1758b5 ("Revert "fdt_support: Use CONFIG_NR_DRAM_BANKS if
defined"")
Signed-off-by: Ramon Fried
---
common/fdt_support.c | 4
1 file changed, 4 insertions(+)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 34d2bd59c4..d84f5dbade 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -409,7 +409,11 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64
*address, u64 *size,
return p - (char *)buf;
}
+#if CONFIG_NR_DRAM_BANKS > 4
+#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
+#else
#define MEMORY_BANKS_MAX 4
+#endif
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
{
int err, nodeoffset;
--
2.18.0
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Re: [U-Boot] [PATCH] spi: davinci: Full dm conversion
On Mon, Aug 13, 2018 at 3:46 PM Alex Kiernan wrote:
>
> On Mon, Aug 13, 2018 at 1:40 PM Adam Ford wrote:
> >
> > On Sat, Aug 11, 2018 at 3:09 PM Adam Ford wrote:
> > >
> > >
> > >
> > > On Sat, Aug 11, 2018, 1:24 PM Jagan Teki
> > > wrote:
> > >>
> > >> On Sat, Aug 11, 2018 at 6:12 PM, Adam Ford wrote:
> > >> > On Fri, Aug 10, 2018 at 2:58 PM Adam Ford wrote:
> > >> >>
> > >> >> On Fri, Aug 10, 2018 at 7:42 AM Jagan Teki
> > >> >> wrote:
> > >> >> >
> > >> >> > On Fri, Aug 10, 2018 at 3:50 PM, Adam Ford
> > >> >> > wrote:
> > >> >> > > On Fri, Aug 10, 2018 at 12:14 AM Jagan Teki
> > >> >> > > wrote:
> > >> >> > >>
> > >> >> > >> On Wed, Aug 8, 2018 at 6:47 PM, Adam Ford
> > >> >> > >> wrote:
> > >> >> > >> > On Tue, Aug 7, 2018 at 1:29 AM Jagan Teki
> > >> >> > >> > wrote:
> > >> >> > >> >>
> > >> >> > >> >> davinci_spi now support dt along with platform data,
> > >> >> > >> >> respective boards need to switch into dm for the same.
> > >> >> > >> >>
> > >> >> > >> >> Cc: Adam Ford
> > >> >> > >> >> Cc: Vitaly Andrianov
> > >> >> > >> >> Cc: Stefano Babic
> > >> >> > >> >> Cc: Peter Howard
> > >> >> > >> >> Cc: Tom Rini
> > >> >> > >> >> Signed-off-by: Jagan Teki
> > >> >> > >> >> ---
> > >> >> > >> >> drivers/spi/Kconfig| 12 +-
> > >> >> > >> >> drivers/spi/davinci_spi.c | 289
> > >> >> > >> >> +++--
> > >> >> > >> >> include/dm/platform_data/spi_davinci.h | 15 ++
> > >> >> > >> >> 3 files changed, 97 insertions(+), 219 deletions(-)
> > >> >> > >> >> create mode 100644 include/dm/platform_data/spi_davinci.h
> > >> >> > >> >>
> > >> >> > >> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > >> >> > >> >> index d046e919b4..18ebff0231 100644
> > >> >> > >> >> --- a/drivers/spi/Kconfig
> > >> >> > >> >> +++ b/drivers/spi/Kconfig
> > >> >> > >> >> @@ -80,6 +80,12 @@ config CADENCE_QSPI
> > >> >> > >> >> used to access the SPI NOR flash on platforms
> > >> >> > >> >> embedding this
> > >> >> > >> >> Cadence IP core.
> > >> >> > >> >>
> > >> >> > >> >> +config DAVINCI_SPI
> > >> >> > >> >> + bool "Davinci & Keystone SPI driver"
> > >> >> > >> >> + depends on ARCH_DAVINCI || ARCH_KEYSTONE
> > >> >> > >> >> + help
> > >> >> > >> >> + Enable the Davinci SPI driver
> > >> >> > >> >> +
> > >> >> > >> >> config DESIGNWARE_SPI
> > >> >> > >> >> bool "Designware SPI driver"
> > >> >> > >> >> help
> > >> >> > >> >> @@ -281,12 +287,6 @@ config FSL_QSPI
> > >> >> > >> >> used to access the SPI NOR flash on platforms
> > >> >> > >> >> embedding this
> > >> >> > >> >> Freescale IP core.
> > >> >> > >> >>
> > >> >> > >> >> -config DAVINCI_SPI
> > >> >> > >> >> - bool "Davinci & Keystone SPI driver"
> > >> >> > >> >> - depends on ARCH_DAVINCI || ARCH_KEYSTONE
> > >> >> > >> >> - help
> > >> >> > >> >> - Enable the Davinci SPI driver
> > >> >> > >> >> -
> > >> >> > >> >> config SH_SPI
> > >> >> > >> >> bool "SuperH SPI driver"
> > >> >> > >> >> help
> > >> >> > >> >> diff --git a/drivers/spi/davinci_spi.c
> > >> >> > >> >> b/drivers/spi/davinci_spi.c
> > >> >> > >> >> index a822858323..5007e6c618 100644
> > >> >> > >> >> --- a/drivers/spi/davinci_spi.c
> > >> >> > >> >> +++ b/drivers/spi/davinci_spi.c
> > >> >> > >> >> @@ -14,6 +14,7 @@
> > >> >> > >> >> #include
> > >> >> > >> >> #include
> > >> >> > >> >> #include
> > >> >> > >> >> +#include
> > >> >> > >> >>
> > >> >> > >> >> /* SPIGCR0 */
> > >> >> > >> >> #define SPIGCR0_SPIENA_MASK0x1
> > >> >> > >> >> @@ -118,9 +119,6 @@ struct davinci_spi_regs {
> > >> >> > >> >>
> > >> >> > >> >> /* davinci spi slave */
> > >> >> > >> >> struct davinci_spi_slave {
> > >> >> > >> >> -#ifndef CONFIG_DM_SPI
> > >> >> > >> >> - struct spi_slave slave;
> > >> >> > >> >> -#endif
> > >> >> > >> >> struct davinci_spi_regs *regs;
> > >> >> > >> >> unsigned int freq; /* current SPI bus frequency */
> > >> >> > >> >> unsigned int mode; /* current SPI mode used */
> > >> >> > >> >> @@ -240,11 +238,43 @@ static int
> > >> >> > >> >> davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
> > >> >> > >> >> return 0;
> > >> >> > >> >> }
> > >> >> > >> >>
> > >> >> > >> >> +static int davinci_spi_set_speed(struct udevice *bus, uint
> > >> >> > >> >> max_hz)
> > >> >> > >> >> +{
> > >> >> > >> >> + struct davinci_spi_slave *ds = dev_get_priv(bus);
> > >> >> > >> >>
> > >> >> > >> >> -static int __davinci_spi_claim_bus(struct davinci_spi_slave
> > >> >> > >> >> *ds, int cs)
> > >> >> > >> >> + debug("%s speed %u\n", __func__, max_hz);
> > >> >> > >> >> + if (max_hz > CONFIG_SYS_SPI_CLK / 2)
> > >> >> > >> >> + return -EINVAL;
> > >> >> > >> >> +
> > >> >> > >> >> + ds->freq = max_hz;
> > >> >> > >> >> +
> > >> >> > >> >> + return 0;
> > >> >> > >> >> +}
> > >> >> > >> >> +
> > >>
[U-Boot] [PATCH] configs: sun7i: Fix to use emmc dts for OLinuXino_MICRO-eMMC
A20 OLinuXino Micro eMMC board has emmc with mmc2 slot so use proper dts, sun7i-a20-olinuxino-micro-emmc.dts Cc: Stefan Mavrodiev Cc: Hans de Goede Signed-off-by: Jagan Teki --- configs/A20-OLinuXino_MICRO-eMMC_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index f7e7cbab0a..a03c752aa6 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -8,7 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_I2C1_ENABLE=y CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro-emmc" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C_SUPPORT=y -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt_support: Use VLA instead of MEMORY_BANKS_MAX
On August 13, 2018 7:59:05 PM GMT+03:00, Tom Rini wrote: >On Mon, Aug 13, 2018 at 10:55:03PM +0300, Ramon Fried wrote: >> On Mon, Aug 13, 2018 at 7:22 PM Ramon Fried >wrote: >> >> > On August 13, 2018 7:15:14 PM GMT+03:00, Tom Rini > >> > wrote: >> > >On Mon, Aug 13, 2018 at 07:14:00PM +0300, Ramon Fried wrote: >> > >> On August 13, 2018 7:08:22 PM GMT+03:00, Tom Rini >> > > wrote: >> > >> >On Mon, Aug 13, 2018 at 09:54:30PM +0300, Ramon Fried wrote: >> > >> >> On Mon, Aug 13, 2018 at 5:52 PM Tom Rini >> > >wrote: >> > >> >> >> > >> >> > On Mon, Aug 13, 2018 at 08:20:03AM +0100, Peter Robinson >wrote: >> > >> >> > >> > >> >> > > On Sun, Aug 12, 2018 at 9:37 PM, Ramon Fried >> > >> > >> > >> >> > wrote: >> > >> >> > > > From: Ramon Fried >> > >> >> > > > >> > >> >> > > > Instead of relaying on user to configure >MEMORY_BANKS_MAX >> > >> >> > > > correctly, use VLA (variable length array) to >accommodate >> > >the >> > >> >> > > > required banks. >> > >> >> > > >> > >> >> > > With the kernel actively removing VLAs [1] does it make >sense >> > >for >> > >> >us >> > >> >> > > to use them? >> > >> >> > >> > >> >> > Agreed. >> > >> >> > >> > >> >> > Also, why is the answer NOT to go back to the way things >were >> > >with >> > >> >> > 5e5745465c94 and increase CONFIG_NR_DRAM_BANKS when needed? > It >> > >> >seems >> > >> >> > >> > >> >> The whole purpose of my patch was to enable to fixup more >banks >> > >than >> > >> >> defined in >> > >> >> CONFIG_NR_DRAM_BANKS. >> > >> >> >> > >> >> Another option would be to add >> > >> >> +#ifndef MEMORY_BANKS_MAX >> > >> >> #define MEMORY_BANKS_MAX 4 >> > >> >> +#endif >> > >> >> and let the use alter the value in include/configs if >necessary. >> > >> > >> > >> >I think for our purposes it's best to say that, as the code was >> > >> >written, >> > >> >if we need more banks to be configured at build time, they >should >> > >be. >> > >> >This may also mean that certain platforms need to bump their >default >> > >up >> > >> >in order to support the hardware you're using that shows this >issue. >> > >> >Thanks! >> > >> I'm confused. To which hardware you're referring to? Do you >still >> > >> think we should revert my patch? >> > > >> > >Yes, I think we should bring the code back to the way it was for a >long >> > >while. And I assume there was a specific piece of hardware that >> > >triggered this round of changes? >> > Yes. Dragonboards. >> > I can implement this fixup function in the snapdragon arch folder. >> > >> > Tom, a last effort to reduce code duplication. is this acceptable ? >> #if CONFIG_NR_DRAM_BANKS > 4 >> #define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS >> #else >> #define MEMORY_BANKS_MAX 4 >> #endif > >If you've got some time, can you add CONFIG_NR_DRAM_BANKS to Kconfig >and >set the default to 4 ? I'll take care of re-running moveconfig.py if >there's conflicts. This could probably go in the top-level Kconfig >file >near the malloc options. Thanks! Sure. Np -- Sent from my Android device with K-9 Mail. Please excuse my brevity. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] pci: Support parsing PCI controller DT subnodes
On Mon, Aug 13, 2018 at 06:07:14PM +0200, Marek Vasut wrote: > On 08/13/2018 03:39 PM, Tom Rini wrote: > [...] > > Next step is to upstream the DT > changes to Linux kernel, then sync the changes to U-Boot to satisfy > this obsession - using exactly the same DT as Linux. > >>> > >>> This is not gonna happen. > >>> > >>> Sorry, you're really just wasting my time with this foolishness. If > >>> U-Boot cannot parse valid DT bindings while other OSes can, U-Boot is > >>> broken and must be fixed. So far I only see you attacking this patch and > >>> trying to pull in everything you can do avoid accepting this patch or > >>> providing a better alternative. This is not a constructive discussion, > >>> so I stop here. > >> > >> The fix in this patch is purely hack, period. > > > > Lets step back for a moment. > > > > First, U-Boot intends to be, in the case where a relevant DTS file > > exists, the Linux kernel one PLUS additions we require (u-boot,dm-spl, > > u-boot,dm-pre-reloc, but also sometimes stdout-path or properties that > > are omitted for various reasons). > > Right, which doesn't apply here. None of those u-boot,... props are > needed in this case. Which is why I also mentioned the non-u-boot specific props we also need sometimes. My point is two-fold: 1: We can and will _add_ information to the dts files that come from Linux. 2: Not all information that we add is U-Boot prefixed. > > Second, I've asked before (both in this thread and on IRC), and not > > gotten an answer yet, as to how Linux goes "Oh, _this_ PCI device and > > _this_ DT node need to be matched and populate some data > > structures". > > You did get an answer to that on irc from George. Looks like > of_pci_find_child_device() in drivers/pci/of.c Yeah, George said he thought that might be it but didn't have time to confirm. > > Marek's patch seems to be, in short "here's where U-Boot > > needs to wire things up". Bin has said that no, the function in > > question is for other things. > > I disagree with this. It's a bind function and assigns other parameters > of the driver instance too. > > > I think knowing where Linux does this > > would be instructive to figure out where we need to have some additional > > logic added OR we can make some cost/benefit analysis to see if it makes > > more sense overall to add compatibles to some nodes rather than add to > > the binary size. > > Adding compatible does not make any sense, the PCI ID provides that > information. Adding compatible would only add redundancy which could > possibly be even harmful (ie. if the controller got replaced with > another one). To try and move things along rather than re-argue the same point, you're saying that our pci_find_and_bind_driver() is the rough equivalent of of_pci_find_child_device() or at least pci_set_of_node() (which calls of_pci_find_child_device()). So, Bin, if this isn't the right place to start down this path, where would be? Given that Linux can take a DTB and PCI bus with devices and get things right, what would it look like for U-Boot to replicate the same behavior? Instead of having to add explicit compatible nodes for each PCI device, as I understand (but correct me if I'm wrong) we're doing today. Thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt_support: Use VLA instead of MEMORY_BANKS_MAX
On Mon, Aug 13, 2018 at 10:55:03PM +0300, Ramon Fried wrote: > On Mon, Aug 13, 2018 at 7:22 PM Ramon Fried wrote: > > > On August 13, 2018 7:15:14 PM GMT+03:00, Tom Rini > > wrote: > > >On Mon, Aug 13, 2018 at 07:14:00PM +0300, Ramon Fried wrote: > > >> On August 13, 2018 7:08:22 PM GMT+03:00, Tom Rini > > > wrote: > > >> >On Mon, Aug 13, 2018 at 09:54:30PM +0300, Ramon Fried wrote: > > >> >> On Mon, Aug 13, 2018 at 5:52 PM Tom Rini > > >wrote: > > >> >> > > >> >> > On Mon, Aug 13, 2018 at 08:20:03AM +0100, Peter Robinson wrote: > > >> >> > > > >> >> > > On Sun, Aug 12, 2018 at 9:37 PM, Ramon Fried > > >> > > > >> >> > wrote: > > >> >> > > > From: Ramon Fried > > >> >> > > > > > >> >> > > > Instead of relaying on user to configure MEMORY_BANKS_MAX > > >> >> > > > correctly, use VLA (variable length array) to accommodate > > >the > > >> >> > > > required banks. > > >> >> > > > > >> >> > > With the kernel actively removing VLAs [1] does it make sense > > >for > > >> >us > > >> >> > > to use them? > > >> >> > > > >> >> > Agreed. > > >> >> > > > >> >> > Also, why is the answer NOT to go back to the way things were > > >with > > >> >> > 5e5745465c94 and increase CONFIG_NR_DRAM_BANKS when needed? It > > >> >seems > > >> >> > > > >> >> The whole purpose of my patch was to enable to fixup more banks > > >than > > >> >> defined in > > >> >> CONFIG_NR_DRAM_BANKS. > > >> >> > > >> >> Another option would be to add > > >> >> +#ifndef MEMORY_BANKS_MAX > > >> >> #define MEMORY_BANKS_MAX 4 > > >> >> +#endif > > >> >> and let the use alter the value in include/configs if necessary. > > >> > > > >> >I think for our purposes it's best to say that, as the code was > > >> >written, > > >> >if we need more banks to be configured at build time, they should > > >be. > > >> >This may also mean that certain platforms need to bump their default > > >up > > >> >in order to support the hardware you're using that shows this issue. > > >> >Thanks! > > >> I'm confused. To which hardware you're referring to? Do you still > > >> think we should revert my patch? > > > > > >Yes, I think we should bring the code back to the way it was for a long > > >while. And I assume there was a specific piece of hardware that > > >triggered this round of changes? > > Yes. Dragonboards. > > I can implement this fixup function in the snapdragon arch folder. > > > > Tom, a last effort to reduce code duplication. is this acceptable ? > #if CONFIG_NR_DRAM_BANKS > 4 > #define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS > #else > #define MEMORY_BANKS_MAX 4 > #endif If you've got some time, can you add CONFIG_NR_DRAM_BANKS to Kconfig and set the default to 4 ? I'll take care of re-running moveconfig.py if there's conflicts. This could probably go in the top-level Kconfig file near the malloc options. Thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt_support: Use VLA instead of MEMORY_BANKS_MAX
On Mon, Aug 13, 2018 at 7:22 PM Ramon Fried wrote: > On August 13, 2018 7:15:14 PM GMT+03:00, Tom Rini > wrote: > >On Mon, Aug 13, 2018 at 07:14:00PM +0300, Ramon Fried wrote: > >> On August 13, 2018 7:08:22 PM GMT+03:00, Tom Rini > > wrote: > >> >On Mon, Aug 13, 2018 at 09:54:30PM +0300, Ramon Fried wrote: > >> >> On Mon, Aug 13, 2018 at 5:52 PM Tom Rini > >wrote: > >> >> > >> >> > On Mon, Aug 13, 2018 at 08:20:03AM +0100, Peter Robinson wrote: > >> >> > > >> >> > > On Sun, Aug 12, 2018 at 9:37 PM, Ramon Fried > >> > > >> >> > wrote: > >> >> > > > From: Ramon Fried > >> >> > > > > >> >> > > > Instead of relaying on user to configure MEMORY_BANKS_MAX > >> >> > > > correctly, use VLA (variable length array) to accommodate > >the > >> >> > > > required banks. > >> >> > > > >> >> > > With the kernel actively removing VLAs [1] does it make sense > >for > >> >us > >> >> > > to use them? > >> >> > > >> >> > Agreed. > >> >> > > >> >> > Also, why is the answer NOT to go back to the way things were > >with > >> >> > 5e5745465c94 and increase CONFIG_NR_DRAM_BANKS when needed? It > >> >seems > >> >> > > >> >> The whole purpose of my patch was to enable to fixup more banks > >than > >> >> defined in > >> >> CONFIG_NR_DRAM_BANKS. > >> >> > >> >> Another option would be to add > >> >> +#ifndef MEMORY_BANKS_MAX > >> >> #define MEMORY_BANKS_MAX 4 > >> >> +#endif > >> >> and let the use alter the value in include/configs if necessary. > >> > > >> >I think for our purposes it's best to say that, as the code was > >> >written, > >> >if we need more banks to be configured at build time, they should > >be. > >> >This may also mean that certain platforms need to bump their default > >up > >> >in order to support the hardware you're using that shows this issue. > >> >Thanks! > >> I'm confused. To which hardware you're referring to? Do you still > >> think we should revert my patch? > > > >Yes, I think we should bring the code back to the way it was for a long > >while. And I assume there was a specific piece of hardware that > >triggered this round of changes? > Yes. Dragonboards. > I can implement this fixup function in the snapdragon arch folder. > > Tom, a last effort to reduce code duplication. is this acceptable ? #if CONFIG_NR_DRAM_BANKS > 4 #define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS #else #define MEMORY_BANKS_MAX 4 #endif -- > Sent from my Android device with K-9 Mail. Please excuse my brevity. > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] cmd: led.c: fix coding style
On Sun, Aug 12, 2018 at 03:06:03PM +0800, Akee Huang wrote: > Fix coding style according to checkpatch.pl > > Signed-off-by: Akee Huang > --- > cmd/led.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/cmd/led.c b/cmd/led.c > index fc07ca95a3..b339c98dfb 100644 > --- a/cmd/led.c > +++ b/cmd/led.c > @@ -133,10 +133,10 @@ int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char * > const argv[]) > #define BLINK "" > #endif > > -U_BOOT_CMD( > - led, 4, 1, do_led, > - "manage LEDs", > - " on|off|toggle" BLINK "\tChange LED state\n" > - "led [\tGet LED state\n" > - "led list\t\tshow a list of LEDs" > +U_BOOT_CMD(led, > +4, 1, do_led, > +"manage LEDs", > +" on|off|toggle" BLINK "\tChange LED state\n" > +"led [\tGet LED state\n" > +"led list\t\tshow a list of LEDs" > ); This is indeed a style violation. However, a quick 'git grep' shows that we really don't have consistency here. And to the extent that we do it's following the style that checkpatch.pl doesn't like and we're doing in cmd/led.c. So, in the absence of a Coccinelle (or simlar) script and proposal to get everything consistent, I don't think this patch by itself is a good idea to apply, sorry. -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/2] armv8: layerscape: move ns_dev[] define from h to c file.
On 08/10/2018 12:00 AM, Ran Wang wrote: > Since more c files will include ns_access.h, this move will fix some > compiling warnings and make it sense. > > Signed-off-by: Ran Wang > --- > Change in v4: > - Apply same move for ls102xa > > Change in v3: > - New file > This set is applied to fsl-qoriq master, awaiting upstream. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] mtd: nand: fsl_ifc: Fix handling of bitflips in erased pages
On 08/02/2018 01:03 AM, Kurt Kanzenbach wrote: > From: Darwin Dingel > > This is a fix made for the fsl_ifc_nand driver on linux kernel by > Pavel Machek and is applied to uboot. It is currently on applied on > linux-mtd. > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fpatch%2F9758117%2F&data=02%7C01%7Cyork.sun%40nxp.com%7C79aca70c61e943b59b1d08d5f84e77eb%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636687938268644852&sdata=PjrH%2FF6LyGA%2BpVjHfqQpn4qhvJKeRHG%2Fb3434wuQy3o%3D&reserved=0 > > IFC always raises ECC errors on erased pages. It is only ignored when > the buffer is checked for all 0xFF by is_blank(). The problem is a > single bitflip will cause is_blank() and then mtd_read to fail. The fix > makes use of nand_check_erased_ecc_chunk() to check for empty pages > instead of is_blank(). This also makes sure that reads are made at ECC > page size granularity to get a proper bitflip count. If the number of > bitflips does not exceed the ECC strength, the page is considered empty > and the bitflips will be corrected when data is sent to the higher > layers (e.g. ubi). > > Signed-off-by: Darwin Dingel > Cc: Pavel Machek > Cc: Scott Wood > Acked-by: Pavel Machek > [Kurt: Replaced dev_err by printf due to compiler warnings] > Tested-by: Kurt Kanzenbach > Signed-off-by: Kurt Kanzenbach > --- > drivers/mtd/nand/fsl_ifc_nand.c | 69 > +++-- > 1 file changed, 39 insertions(+), 30 deletions(-) Applied to fsl-qoriq master, awaiting upstream. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 1/8] armv8: fsl-layerscape: add missing register blocks base address defines
On 08/09/2018 05:20 AM, laurentiu.tu...@nxp.com wrote: > From: Laurentiu Tudor > > Add defines for the edma and qdma register block base addresses. > > Reviewed-by: Bharat Bhushan > Signed-off-by: Laurentiu Tudor > --- This set is applied to fsl-qoriq master, awaiting upstream. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] net: Increase ethernet name string size to 20 chars
On 08/01/2018 10:31 PM, Pankaj Bansal wrote: > The 16 char ethernet name size is inadequate to hold the name of ethernet > name "DPMAC17@rgmii-id", which is a valid name in LX2160AQDS/LX2160ARDB. > > Therefore, increase the name string size to 20 chars. > > Reported-by: Ioana Ciornei > Suggested-by: Ioana Ciocoi Radulescu > Signed-off-by: Pankaj Bansal > --- Applied to fsl-qoriq master, awaiting upstream. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] fsl/mc: Limit the ethernet name to ETH_NAME_LEN
On 08/01/2018 10:31 PM, Pankaj Bansal wrote: > The ethernet name should be within the ETH_NAME_LEN, as this > is the buffer space allocated to ethernet name. > > Otherwise, this causes buffer overflow. > > Reported-by: Ioana Ciornei > Signed-off-by: Pankaj Bansal > --- Applied to fsl-qoriq master, awaiting upstream. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio
On 09/12/2017 10:56 AM, Joakim Tjernlund wrote: > Most FSL PCIe controllers expects 333 MHz PCI reference clock. > This clock is derived from the CCB but in many cases the ref. > clock is not 333 MHz and a divisor needs to be configured. > > This adds PEX_CCB_DIV #define which can be defined for each > type of CPU/platform. > > Signed-off-by: Joakim Tjernlund > --- Applied to fsl-qoriq master, awaiting upstream. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] Board: ls1088ardb: Enable PCIe config for Secure boot defconfigs
On 07/16/2018 11:29 PM, Vinitha V Pillai wrote: > Enable PCIe config options in LS1088 SD Secure Boot defconfig > > Signed-off-by: Vinitha V Pillai > --- > > Changes in v2: > Changed the commit message and added reviewers Applied to fsl-qoriq master, awaiting upstream. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt_support: Use VLA instead of MEMORY_BANKS_MAX
On August 13, 2018 7:15:14 PM GMT+03:00, Tom Rini wrote: >On Mon, Aug 13, 2018 at 07:14:00PM +0300, Ramon Fried wrote: >> On August 13, 2018 7:08:22 PM GMT+03:00, Tom Rini > wrote: >> >On Mon, Aug 13, 2018 at 09:54:30PM +0300, Ramon Fried wrote: >> >> On Mon, Aug 13, 2018 at 5:52 PM Tom Rini >wrote: >> >> >> >> > On Mon, Aug 13, 2018 at 08:20:03AM +0100, Peter Robinson wrote: >> >> > >> >> > > On Sun, Aug 12, 2018 at 9:37 PM, Ramon Fried >> > >> >> > wrote: >> >> > > > From: Ramon Fried >> >> > > > >> >> > > > Instead of relaying on user to configure MEMORY_BANKS_MAX >> >> > > > correctly, use VLA (variable length array) to accommodate >the >> >> > > > required banks. >> >> > > >> >> > > With the kernel actively removing VLAs [1] does it make sense >for >> >us >> >> > > to use them? >> >> > >> >> > Agreed. >> >> > >> >> > Also, why is the answer NOT to go back to the way things were >with >> >> > 5e5745465c94 and increase CONFIG_NR_DRAM_BANKS when needed? It >> >seems >> >> > >> >> The whole purpose of my patch was to enable to fixup more banks >than >> >> defined in >> >> CONFIG_NR_DRAM_BANKS. >> >> >> >> Another option would be to add >> >> +#ifndef MEMORY_BANKS_MAX >> >> #define MEMORY_BANKS_MAX 4 >> >> +#endif >> >> and let the use alter the value in include/configs if necessary. >> > >> >I think for our purposes it's best to say that, as the code was >> >written, >> >if we need more banks to be configured at build time, they should >be. >> >This may also mean that certain platforms need to bump their default >up >> >in order to support the hardware you're using that shows this issue. >> >Thanks! >> I'm confused. To which hardware you're referring to? Do you still >> think we should revert my patch? > >Yes, I think we should bring the code back to the way it was for a long >while. And I assume there was a specific piece of hardware that >triggered this round of changes? Yes. Dragonboards. I can implement this fixup function in the snapdragon arch folder. -- Sent from my Android device with K-9 Mail. Please excuse my brevity. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: ls102xa: Fix RGMII phy-connection-type FDT fixup
On 07/16/2018 01:28 PM, Brendan Shanks wrote: > In ft_fixup_enet_phy_connect_type(), use strlen() instead of sizeof() on > the pointer result of phy_string_for_interface(). > sizeof() was returning the size of the pointer (4 bytes), resulting in > the phy-connection-type being set to "rgmi" rather than "rgmii-id". > > Signed-off-by: Brendan Shanks > Cc: York Sun > --- Applied to fsl-qoriq master, awaiting upstream. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
