Re: [U-Boot] [PATCH] misc: fs_loader: Replace label with DT phandle
On Sun, 2019-03-10 at 15:51 -0600, Simon Glass wrote: > Hi Tien Fong, > > On Tue, 26 Feb 2019 at 05:37, Chee, Tien Fong om> wrote: > > > > > > On Fri, 2019-02-15 at 14:35 +0800, tien.fong.c...@intel.com wrote: > > > > > > From: Tien Fong Chee > > > > > > In previously label which will be expanded to the node's full > > > path > > > was > > > used, and now replacing label with most commonly used DT phandle. > > > The > > > codes were changed accordingly to the use of DT phandle and > > > supporting > > > multiple instances. > > > > > > Signed-off-by: Tien Fong Chee > > > --- > > > doc/driver-model/fs_firmware_loader.txt | 58 > > > +-- > > > drivers/misc/fs_loader.c| 36 - > > > -- > > > 2 files changed, 62 insertions(+), 32 deletions(-) > This seems OK to me, but I think this feature needs a test. Yes, i have ran the test passed with FPGA driver. > > Regards, > Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [BUG] efi_loader: self-tests fail on qemu-x86_defconfig when compiled with GCC 8.3 and CONFIG_CC_OPTIMIZE_FOR_SIZE=y
HI Heinrich, On Mon, Mar 11, 2019 at 10:11 AM Heinrich Schuchardt wrote: > > Debian has recently (march 8th) upgraded GCC from 8.2 to 8.3. > > When I compile qemu-x86_defconfig with CONFIG_CC_OPTIMIZE_FOR_SIZE=y > some of the UEFI selftests (bootefi selftest) fail. It looks to me like > ebx is not conserved. > > With CONFIG_CC_OPTIMIZE_FOR_SIZE=n everything is fine. > Thanks for testing. Could you do some debugging to identify whether there is a bug in U-Boot, or a regression in GCC? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv4 08/12] pci: ls_pcie_g4: add Workaround for A-011577
From: Hou Zhiqiang
PCIe configuration access to non-existent function triggered
SERROR interrupt exception.
Workaround:
Disable error reporting on AXI bus during the Vendor ID read
transactions in enumeration.
This ERRATA is only for LX2160A Rev1.0 and will be fixed in Rev2.0.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
drivers/pci/pcie_layerscape_gen4.c | 8
drivers/pci/pcie_layerscape_gen4.h | 5 +
2 files changed, 13 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index 4e0d5b168e..799da2f7df 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -242,6 +242,9 @@ static int ls_pcie_g4_read_config(struct udevice *bus,
pci_dev_t bdf,
address = ls_pcie_g4_conf_address(pcie, bdf, offset);
+ if (pcie->rev == REV_1_0 && offset == PCI_VENDOR_ID)
+ lut_writel(pcie, 0x0 << PCIE_LUT_GCR_RRE, PCIE_LUT_GCR);
+
switch (size) {
case PCI_SIZE_8:
*valuep = readb(address);
@@ -257,6 +260,9 @@ static int ls_pcie_g4_read_config(struct udevice *bus,
pci_dev_t bdf,
break;
}
+ if (pcie->rev == REV_1_0 && offset == PCI_VENDOR_ID)
+ lut_writel(pcie, 0x1 << PCIE_LUT_GCR_RRE, PCIE_LUT_GCR);
+
return ret;
}
@@ -518,6 +524,8 @@ static int ls_pcie_g4_probe(struct udevice *dev)
dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg,
pcie->big_endian);
+ pcie->rev = readb(pcie->ccsr + PCI_REVISION_ID);
+
pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
diff --git a/drivers/pci/pcie_layerscape_gen4.h
b/drivers/pci/pcie_layerscape_gen4.h
index 356b49f9ce..137768cae7 100644
--- a/drivers/pci/pcie_layerscape_gen4.h
+++ b/drivers/pci/pcie_layerscape_gen4.h
@@ -11,6 +11,8 @@
#include
#include
+#define REV_1_0(0x10)
+
#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
#define CONFIG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL)
#endif
@@ -161,6 +163,8 @@
#define PCIE_LUT_LDR(n)(0x804 + (n) * 8)
#define PCIE_LUT_ENABLEBIT(31)
#define PCIE_LUT_ENTRY_COUNT 32
+#define PCIE_LUT_GCR (0x28)
+#define PCIE_LUT_GCR_RRE (0)
/* PF control registers */
#define PCIE_LTSSM_STA 0x7fc
@@ -190,6 +194,7 @@ struct ls_pcie_g4 {
int stream_id_cur;
int mode;
int sriov_support;
+ u8 rev;
};
extern struct list_head ls_pcie_g4_list;
--
2.17.1
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[U-Boot] [PATCHv4 12/12] pci: ls_pcie_g4: add Workaround for A-011452
From: Hou Zhiqiang
For PCIe controllers with SRIOV, MSIx table entries of all the VFs
are not accessible if BAR size is set to less than 8MB.
This ERRATA is only for LX2160A Rev1.0 and will be fixed in Rev2.0.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
drivers/pci/pcie_layerscape_gen4.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index b530a9979c..3792dbdf55 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -378,6 +378,11 @@ static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4
*pcie, int pf,
u32 mask_l = lower_32_bits(~(size - 1));
u32 mask_h = upper_32_bits(~(size - 1));
+ /* A-011452 workaround: set the VF BAR1 to 8MB */
+ if (pcie->rev == REV_1_0 && vf_bar && bar == 1) {
+ mask_l = lower_32_bits(~(SZ_8M - 1));
+ mask_h = upper_32_bits(~(SZ_8M - 1));
+ }
ccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos);
ccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l);
ccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);
--
2.17.1
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[U-Boot] [PATCHv4 07/12] armv8: lx2160a: enable PCIe support
From: Hou Zhiqiang Enable the PCIe Gen4 controller driver and e1000 for LX2160ARDB and LX2160AQDS boards. Signed-off-by: Hou Zhiqiang --- V4: - Add PCI command support - Enable PCIe in more LX2160A defconfigs configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 5 + configs/lx2160aqds_tfa_defconfig | 6 ++ configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 5 + configs/lx2160ardb_tfa_defconfig | 6 ++ 4 files changed, 22 insertions(+) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 58841053ec..367502da37 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -56,3 +56,8 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_PCI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index a0b86ae142..06ef830acd 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -51,3 +51,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_PCI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_E1000=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index f66882d6fa..4e972cc721 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -53,3 +53,8 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_PCI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 2dc49c7f5d..73b3b91034 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -51,3 +51,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_PCI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_E1000=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv4 11/12] pci: ls_pcie_g4: Add Workaround for A-011451
From: Hou Zhiqiang
When LAYERSCAPE Gen4 PCIe controller is sending multiple split
completions and ACK latency expires indicating that ACK should
be send at priority. But because of large number of split
completions and FC update DLLP, the controller does not give
priority to ACK transmission. This results into ACK latency
timer timeout error at the link partner and the pending TLPs
are replayed by the link partner again.
Workaround:
1. Reduce the ACK latency timeout value to a very small value.
2. Restrict the number of completions from the PCIe controller
to 1, by changing the Max Read Request Size (MRRS) of link
partner to the same value as Max Packet size (MPS).
This ERRATA is only for LX2160A Rev1.0 and will be fixed in Rev2.0.
Signed-off-by: Hou Zhiqiang
---
V4:
- V3 patch find root port wrongly, fix it in V4.
- Change to use the MPS and MRRS accessors.
drivers/pci/pci_auto.c | 35 ++
drivers/pci/pcie_layerscape_gen4.c | 8 +++
drivers/pci/pcie_layerscape_gen4.h | 4
include/pci_ids.h | 1 +
4 files changed, 48 insertions(+)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index d7237f6eee..611462d1d4 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -22,6 +22,8 @@ void dm_pciauto_setup_device(struct udevice *dev, int
bars_num,
struct pci_region *prefetch, struct pci_region *io,
bool enum_only)
{
+ struct udevice *ctrl = pci_get_controller(dev);
+ struct udevice *rp;
u32 bar_response;
pci_size_t bar_size;
u16 cmdstat = 0;
@@ -32,6 +34,8 @@ void dm_pciauto_setup_device(struct udevice *dev, int
bars_num,
struct pci_region *bar_res = NULL;
int found_mem64 = 0;
u16 class;
+ u16 vendor, dev_id;
+ u8 rev;
dm_pci_read_config16(dev, PCI_COMMAND, );
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
@@ -161,6 +165,37 @@ void dm_pciauto_setup_device(struct udevice *dev, int
bars_num,
dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
CONFIG_SYS_PCI_CACHE_LINE_SIZE);
dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
+
+ /*
+* When NXP LAYERSCAPE Gen4 PCIe controller is sending multiple split
+* completions and ACK latency expires indicating that ACK should be
+* send at priority. But because of large number of split completions
+* and FC update DLLP, the controller does not give priority to ACK
+* transmission. This results into ACK latency timer timeout error at
+* the link partner and the pending TLPs are replayed by the link
+* partner again.
+*
+* The workaround:
+* Restrict the number of completions from the PCIe controller to 1,
+* by changing the Max Read Request Size (MRRS) of link partner to the
+* same value as Max Packet size (MPS).
+*
+* So, set both the MPS and MRRS to the minimum 128B.
+*/
+ device_find_first_child(ctrl, );
+ if (!rp) {
+ debug("%s: Host: %s, RP is NULL\n", __func__, ctrl->name);
+ return;
+ }
+
+ dm_pci_read_config16(rp, PCI_VENDOR_ID, );
+ dm_pci_read_config16(rp, PCI_DEVICE_ID, _id);
+ dm_pci_read_config8(rp, PCI_REVISION_ID, );
+ if (vendor == PCI_VENDOR_ID_FREESCALE &&
+ dev_id == PCI_DEVICE_ID_LX2160A && rev == 0x10) {
+ dm_pci_set_mps(dev, 128);
+ dm_pci_set_readrq(dev, 128);
+ }
}
void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index 799da2f7df..b530a9979c 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -526,6 +526,14 @@ static int ls_pcie_g4_probe(struct udevice *dev)
pcie->rev = readb(pcie->ccsr + PCI_REVISION_ID);
+ /* Set ACK latency timeout */
+ if (pcie->rev == REV_1_0) {
+ val = ccsr_readl(pcie, GPEX_ACK_REPLAY_TO);
+ val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
+ val |= (4 << ACK_LAT_TO_VAL_SHIFT);
+ ccsr_writel(pcie, GPEX_ACK_REPLAY_TO, val);
+ }
+
pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
diff --git a/drivers/pci/pcie_layerscape_gen4.h
b/drivers/pci/pcie_layerscape_gen4.h
index 137768cae7..ebde52e49a 100644
--- a/drivers/pci/pcie_layerscape_gen4.h
+++ b/drivers/pci/pcie_layerscape_gen4.h
@@ -58,6 +58,10 @@
#define INI_VF_SHIFT 0
#define GPEX_SRIOV_VF_OFFSET_STRIDE(pf)(0x704 + (pf) * 4)
+#define GPEX_ACK_REPLAY_TO 0x438
+#define ACK_LAT_TO_VAL_SHIFT 0
+#define ACK_LAT_TO_VAL_MASK0x1fff
[U-Boot] [PATCHv4 06/12] armv8: lx2160a: add PCIe controller DT nodes
From: Hou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
arch/arm/dts/fsl-lx2160a.dtsi | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 510b070582..cac3207985 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -176,4 +176,89 @@
status = "disabled";
};
+
+ pcie@340 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x0340 0x0 0x8 /* PAB registers */
+ 0x00 0x0348 0x0 0x4 /* LUT registers */
+ 0x00 0x034c 0x0 0x4 /* PF control registers */
+ 0x80 0x 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>; /* non-prefetchable memory */
+ };
+
+ pcie@350 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x0350 0x0 0x8 /* PAB registers */
+ 0x00 0x0358 0x0 0x4 /* LUT registers */
+ 0x00 0x035c 0x0 0x4 /* PF control registers */
+ 0x88 0x 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x8200 0x0 0x4000 0x88 0x4000 0x0
0x4000>; /* non-prefetchable memory */
+ };
+
+ pcie@360 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x0360 0x0 0x8 /* PAB registers */
+ 0x00 0x0368 0x0 0x4 /* LUT registers */
+ 0x00 0x036c 0x0 0x4 /* PF control registers */
+ 0x90 0x 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x8200 0x0 0x4000 0x90 0x4000 0x0
0x4000>; /* non-prefetchable memory */
+ };
+
+ pcie@370 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x0370 0x0 0x8 /* PAB registers */
+ 0x00 0x0378 0x0 0x4 /* LUT registers */
+ 0x00 0x037c 0x0 0x4 /* PF control registers */
+ 0x98 0x 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x8200 0x0 0x4000 0x98 0x4000 0x0
0x4000>; /* non-prefetchable memory */
+ };
+
+ pcie@380 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x0380 0x0 0x8 /* PAB registers */
+ 0x00 0x0388 0x0 0x4 /* LUT registers */
+ 0x00 0x038c 0x0 0x4 /* PF control registers */
+ 0xa0 0x 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x8200 0x0 0x4000 0xa0 0x4000 0x0
0x4000>; /* non-prefetchable memory */
+ };
+
+ pcie@390 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x0390 0x0 0x8 /* PAB registers */
+ 0x00 0x0398 0x0 0x4 /* LUT registers */
+ 0x00 0x039c 0x0 0x4 /* PF control registers */
+ 0xa8 0x 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x8200 0x0 0x4000 0xa8 0x4000 0x0
0x4000>; /* non-prefetchable memory */
+ };
};
--
2.17.1
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[U-Boot] [PATCHv4 04/12] kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPAT
From: Hou Zhiqiang The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead of PCIE_LAYERSCAPE. Signed-off-by: Hou Zhiqiang --- V4: - No change arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f48481f465..d37e3678e7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -242,7 +242,7 @@ config FSL_LAYERSCAPE config FSL_PCIE_COMPAT string "PCIe compatible of Kernel DT" - depends on PCIE_LAYERSCAPE + depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4 default "fsl,ls1012a-pcie" if ARCH_LS1012A default "fsl,ls1043a-pcie" if ARCH_LS1043A default "fsl,ls1046a-pcie" if ARCH_LS1046A -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv4 09/12] dm: pci: add APIs for capability accessors
From: Hou Zhiqiang
This patch introduce a set of PCI/PCIe capability accessors,
including 16-bit and 32-bit read, write and clear_and_set
operations.
Signed-off-by: Hou Zhiqiang
---
V4:
- New patch
drivers/pci/pci-uclass.c | 153 +++
include/pci.h| 20 +
2 files changed, 173 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 824fa11907..4bb30f5d2b 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1443,6 +1443,159 @@ int dm_pci_find_ext_capability(struct udevice *dev, int
cap)
return dm_pci_find_next_ext_capability(dev, 0, cap);
}
+/**
+ * dm_pci_capability_read() - PCI capability register read
+ *
+ * @dev: PCI device to read
+ * @cap: capability code
+ * @pos: register offset
+ * @val: pointer to keep the read value
+ * @size: register width
+ *
+ * Returns 0 if OK or appropriate error value.
+ */
+int dm_pci_capability_read(struct udevice *dev, int cap, int pos,
+ ulong *val, enum pci_size_t size)
+{
+ u32 off;
+
+ switch (size) {
+ case PCI_SIZE_16:
+ if (pos & 1)
+ return -EINVAL;
+ break;
+ case PCI_SIZE_32:
+ if (pos & 3)
+ return -EINVAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ off = dm_pci_find_capability(dev, cap);
+ if (off)
+ return dm_pci_read_config(dev, off + pos, val, size);
+
+ return -EINVAL;
+}
+
+/**
+ * dm_pci_capability_write() - PCI capability register write
+ *
+ * @dev: PCI device to write
+ * @cap: capability code
+ * @pos: register offset
+ * @val: value to write
+ * @size: register width
+ *
+ * Returns 0 if OK or appropriate error value.
+ */
+int dm_pci_capability_write(struct udevice *dev, int cap, int pos,
+ ulong val, enum pci_size_t size)
+{
+ u32 off;
+
+ switch (size) {
+ case PCI_SIZE_16:
+ if (pos & 1)
+ return -EINVAL;
+ break;
+ case PCI_SIZE_32:
+ if (pos & 3)
+ return -EINVAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ off = dm_pci_find_capability(dev, cap);
+ if (off)
+ return dm_pci_write_config(dev, off + pos, val, size);
+
+ return -EINVAL;
+}
+
+int dm_pci_capability_read_word(struct udevice *dev, int cap, int pos, u16
*val)
+{
+ ulong value;
+ int ret;
+
+ ret = dm_pci_capability_read(dev, cap, pos, , PCI_SIZE_16);
+ if (ret)
+ return ret;
+ *val = value;
+
+ return 0;
+}
+
+int dm_pci_capability_write_word(struct udevice *dev, int cap, int pos, u16
val)
+{
+ return dm_pci_capability_write(dev, cap, pos, val, PCI_SIZE_16);
+}
+
+int dm_pci_capability_read_dword(struct udevice *dev, int cap,
+int pos, u32 *val)
+{
+ ulong value;
+ int ret;
+
+ return dm_pci_capability_read(dev, cap, pos, , PCI_SIZE_32);
+ if (ret)
+ return ret;
+ *val = value;
+
+ return 0;
+}
+
+int dm_pci_capability_write_dword(struct udevice *dev, int cap,
+ int pos, u32 val)
+{
+ return dm_pci_capability_write(dev, cap, pos, val, PCI_SIZE_32);
+}
+
+/**
+ * dm_pci_capability_clear_and_set() - PCI capability register update
+ *
+ * @dev: PCI device to update
+ * @cap: capability code
+ * @pos: register offset
+ * @clear: bits to clear
+ * @set: bits to set
+ * @size: register width
+ *
+ * Returns 0 if OK or appropriate error value.
+ */
+int dm_pci_capability_clear_and_set(struct udevice *dev, int cap, int pos,
+ ulong clear, ulong set,
+ enum pci_size_t size)
+{
+ int ret;
+ ulong val;
+
+ ret = dm_pci_capability_read(dev, cap, pos, , size);
+ if (!ret) {
+ val &= ~clear;
+ val |= set;
+ ret = dm_pci_capability_write(dev, cap, pos, val, size);
+ }
+
+ return ret;
+}
+
+int dm_pci_capability_clear_and_set_word(struct udevice *dev, int cap,
+int pos, u16 clear, u16 set)
+{
+ return dm_pci_capability_clear_and_set(dev, cap, pos, clear,
+ set, PCI_SIZE_16);
+}
+
+int dm_pci_capability_clear_and_set_dword(struct udevice *dev, int cap,
+ int pos, u32 clear, u32 set)
+{
+ return dm_pci_capability_clear_and_set(dev, cap, pos, clear,
+ set, PCI_SIZE_32);
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
diff --git
[U-Boot] [PATCHv4 10/12] dm: pci: add APIs for MPS and MRRS accessors
From: Hou Zhiqiang
This patch introduce APIs for getting and updating the MPS
and MRRS fields of Device capability Device control register.
Signed-off-by: Hou Zhiqiang
---
V4:
- New patch
drivers/pci/pci-uclass.c | 92
include/pci.h| 13 ++
2 files changed, 105 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 4bb30f5d2b..b2d295435a 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1596,6 +1597,97 @@ int dm_pci_capability_clear_and_set_dword(struct udevice
*dev, int cap,
set, PCI_SIZE_32);
}
+/**
+ * dm_pci_get_readrq - get PCI Express read request size
+ * @dev: PCI device to query
+ *
+ * Returns maximum memory read request in bytes
+ *or appropriate error value.
+ */
+int dm_pci_get_readrq(struct udevice *dev)
+{
+ u16 ctl;
+ int ret;
+
+ ret = dm_pci_capability_read_word(dev, PCI_CAP_ID_EXP,
+ PCI_EXP_DEVCTL, );
+ if (ret)
+ return ret;
+
+ return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
+}
+
+/**
+ * dm_pci_set_readrq - set PCI Express maximum memory read request
+ * @dev: PCI device to query
+ * @rq: maximum memory read count in bytes
+ *valid values are 128, 256, 512, 1024, 2048, 4096
+ */
+int dm_pci_set_readrq(struct udevice *dev, int rq)
+{
+ u16 val;
+
+ if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
+ return -EINVAL;
+
+ val = (ffs(rq) - 8) << 12;
+
+ return dm_pci_capability_clear_and_set_word(dev, PCI_CAP_ID_EXP,
+ PCI_EXP_DEVCTL,
+ PCI_EXP_DEVCTL_READRQ,
+ val);
+}
+
+/**
+ * dm_pci_get_mps - get PCI Express maximum payload size
+ * @dev: PCI device to query
+ *
+ * Returns maximum payload size in bytes
+ */
+int dm_pci_get_mps(struct udevice *dev)
+{
+ u16 ctl;
+ int ret;
+
+ ret = dm_pci_capability_read_word(dev, PCI_CAP_ID_EXP,
+ PCI_EXP_DEVCTL, );
+ if (ret)
+ return ret;
+
+ return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
+}
+
+/**
+ * dm_pci_set_mps - set PCI Express maximum payload size
+ * @dev: PCI device to query
+ * @mps: maximum payload size in bytes
+ *valid values are 128, 256, 512, 1024, 2048, 4096
+ */
+int dm_pci_set_mps(struct udevice *dev, int mps)
+{
+ u16 val, cap;
+ int ret;
+
+ if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
+ return -EINVAL;
+
+ ret = dm_pci_capability_read_word(dev, PCI_CAP_ID_EXP,
+ PCI_EXP_DEVCAP, );
+ if (ret)
+ return ret;
+
+ val = ffs(mps) - 8;
+ if (val > (cap & PCI_EXP_DEVCAP_PAYLOAD))
+ return -EINVAL;
+
+ val <<= 5;
+
+ return dm_pci_capability_clear_and_set_word(dev, PCI_CAP_ID_EXP,
+ PCI_EXP_DEVCTL,
+ PCI_EXP_DEVCTL_PAYLOAD,
+ val);
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
diff --git a/include/pci.h b/include/pci.h
index d7b6d9f4ff..b48df8a363 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -414,6 +414,14 @@
#define PCI_MAX_PCI_DEVICES32
#define PCI_MAX_PCI_FUNCTIONS 8
+/* PCI Express capability registers */
+#define PCI_EXP_DEVCAP 4 /* Device capabilities */
+#define PCI_EXP_DEVCAP_PAYLOAD0x0007 /* Max_Payload_Size */
+
+#define PCI_EXP_DEVCTL 8 /* Device Control */
+#define PCI_EXP_DEVCTL_PAYLOAD0x00e0 /* Max_Payload_Size */
+#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+
#define PCI_FIND_CAP_TTL 0x48
#define CAP_START_POS 0x40
@@ -1425,6 +1433,11 @@ int dm_pci_capability_clear_and_set_word(struct udevice
*dev, int cap,
int dm_pci_capability_clear_and_set_dword(struct udevice *dev, int cap,
int pos, u32 clear, u32 set);
+int dm_pci_get_readrq(struct udevice *dev);
+int dm_pci_set_readrq(struct udevice *dev, int rq);
+int dm_pci_get_mps(struct udevice *dev);
+int dm_pci_set_mps(struct udevice *dev, int mps);
+
#define dm_pci_virt_to_bus(dev, addr, flags) \
dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv4 03/12] pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs
From: Hou Zhiqiang
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Bao Xiaowei
---
V4:
- No change
drivers/pci/Kconfig| 8 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_layerscape_gen4.c | 577 +
drivers/pci/pcie_layerscape_gen4.h | 264 +
4 files changed, 850 insertions(+)
create mode 100644 drivers/pci/pcie_layerscape_gen4.c
create mode 100644 drivers/pci/pcie_layerscape_gen4.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 1521885bde..2638a5a72d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -69,6 +69,14 @@ config PCI_RCAR_GEN2
Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is
also used to access EHCI USB controller on the SoC.
+config PCIE_LAYERSCAPE_GEN4
+ bool "Layerscape Gen4 PCIe support"
+ depends on DM_PCI
+ help
+ Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or
+ several PCIe controllers. The PCIe controller can work in RC or
+ EP mode according to RCW[HOST_AGT_PEX] setting.
+
config PCI_SANDBOX
bool "Sandbox PCI support"
depends on SANDBOX && DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 4923641895..7f585aad55 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
new file mode 100644
index 00..fbe7d35911
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -0,0 +1,577 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2018 NXP
+ *
+ * PCIe Gen4 driver for NXP Layerscape SoCs
+ * Author: Hou Zhiqiang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie_layerscape_gen4.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+LIST_HEAD(ls_pcie_g4_list);
+
+static u64 bar_size[4] = {
+ PCIE_BAR0_SIZE,
+ PCIE_BAR1_SIZE,
+ PCIE_BAR2_SIZE,
+ PCIE_BAR4_SIZE
+};
+
+static int ls_pcie_g4_ltssm(struct ls_pcie_g4 *pcie)
+{
+ u32 state;
+
+ state = pf_ctrl_readl(pcie, PCIE_LTSSM_STA) & LTSSM_STATE_MASK;
+
+ return state;
+}
+
+static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)
+{
+ int ltssm;
+
+ ltssm = ls_pcie_g4_ltssm(pcie);
+ if (ltssm != LTSSM_PCIE_L0)
+ return 0;
+
+ return 1;
+}
+
+static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)
+{
+ ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);
+}
+
+static void ls_pcie_g4_cfg_set_target(struct ls_pcie_g4 *pcie, u32 target)
+{
+ ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);
+ ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
+}
+
+static int ls_pcie_g4_outbound_win_set(struct ls_pcie_g4 *pcie, int idx,
+ int type, u64 phys, u64 bus_addr,
+ pci_size_t size)
+{
+ u32 val;
+ u32 size_h, size_l;
+
+ if (idx >= PAB_WINS_NUM)
+ return -EINVAL;
+
+ size_h = upper_32_bits(~(size - 1));
+ size_l = lower_32_bits(~(size - 1));
+
+ val = ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
+ val &= ~((AXI_AMAP_CTRL_TYPE_MASK << AXI_AMAP_CTRL_TYPE_SHIFT) |
+ (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT) |
+ AXI_AMAP_CTRL_EN);
+ val |= ((type & AXI_AMAP_CTRL_TYPE_MASK) << AXI_AMAP_CTRL_TYPE_SHIFT) |
+ ((size_l >> AXI_AMAP_CTRL_SIZE_SHIFT) <<
+ AXI_AMAP_CTRL_SIZE_SHIFT) | AXI_AMAP_CTRL_EN;
+
+ ccsr_writel(pcie, PAB_AXI_AMAP_CTRL(idx), val);
+
+ ccsr_writel(pcie, PAB_AXI_AMAP_AXI_WIN(idx), lower_32_bits(phys));
+ ccsr_writel(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(idx), upper_32_bits(phys));
+ ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
+ ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
+ ccsr_writel(pcie, PAB_EXT_AXI_AMAP_SIZE(idx), size_h);
+
+ return 0;
+}
+
+static int ls_pcie_g4_rc_inbound_win_set(struct ls_pcie_g4 *pcie, int idx,
+int type, u64 phys, u64 bus_addr,
+pci_size_t size)
+{
+ u32 val;
+ pci_size_t win_size = ~(size - 1);
+
+ val = ccsr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
+
+ val &= ~(PEX_AMAP_CTRL_TYPE_MASK <<
[U-Boot] [PATCHv4 05/12] pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs
From: Hou Zhiqiang
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
drivers/pci/Makefile | 3 +-
drivers/pci/pcie_layerscape_gen4.c | 5 -
drivers/pci/pcie_layerscape_gen4_fixup.c | 249 +++
3 files changed, 251 insertions(+), 6 deletions(-)
create mode 100644 drivers/pci/pcie_layerscape_gen4_fixup.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 7f585aad55..8ee828af6d 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
-obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
+ pcie_layerscape_gen4_fixup.o
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
diff --git a/drivers/pci/pcie_layerscape_gen4.c
b/drivers/pci/pcie_layerscape_gen4.c
index fbe7d35911..4e0d5b168e 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -570,8 +570,3 @@ U_BOOT_DRIVER(pcie_layerscape_gen4) = {
.probe = ls_pcie_g4_probe,
.priv_auto_alloc_size = sizeof(struct ls_pcie_g4),
};
-
-/* No any fixup so far */
-void ft_pci_setup(void *blob, bd_t *bd)
-{
-}
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c
b/drivers/pci/pcie_layerscape_gen4_fixup.c
new file mode 100644
index 00..ceeea17f19
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2018 NXP
+ *
+ * PCIe Gen4 driver for NXP Layerscape SoCs
+ * Author: Hou Zhiqiang
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#ifdef CONFIG_OF_BOARD_SETUP
+#include
+#include
+#ifdef CONFIG_ARM
+#include
+#endif
+#include "pcie_layerscape_gen4.h"
+
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+/*
+ * Return next available LUT index.
+ */
+static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
+{
+ if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+ return pcie->next_lut_index++;
+
+ return -ENOSPC; /* LUT is full */
+}
+
+/* returns the next available streamid for pcie, -errno if failed */
+static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie)
+{
+ int stream_id = pcie->stream_id_cur;
+
+ if (stream_id > FSL_PEX_STREAM_ID_NUM)
+ return -EINVAL;
+
+ pcie->stream_id_cur++;
+
+ return stream_id | ((pcie->idx + 1) << 11);
+}
+
+/*
+ * Program a single LUT entry
+ */
+static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
+ u32 devid, u32 streamid)
+{
+ /* leave mask as all zeroes, want to match all bits */
+ lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
+ lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
+}
+
+/*
+ * An msi-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie_g4 *pcie,
+ u32 devid, u32 streamid)
+{
+ u32 *prop;
+ u32 phandle;
+ int nodeoff;
+
+#ifdef CONFIG_FSL_PCIE_COMPAT
+ nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
+ pcie->ccsr_res.start);
+#else
+#error "No CONFIG_FSL_PCIE_COMPAT defined"
+#endif
+ if (nodeoff < 0) {
+ debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
+ return;
+ }
+
+ /* get phandle to MSI controller */
+ prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
+ if (!prop) {
+ debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
+ __func__, pcie->idx);
+ return;
+ }
+ phandle = fdt32_to_cpu(*prop);
+
+ /* set one msi-map row */
+ fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
+ fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
+ fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
+ fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
+}
+
+/*
+ * An iommu-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
[U-Boot] [PATCHv4 02/12] armv8: lx2160a: add MMU table entries for PCIe
From: Hou Zhiqiang
The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 12
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 ++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 14 +-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b32f..2805e5f6f2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -257,6 +257,18 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
+#endif
+#ifdef CONFIG_ARCH_LX2160A
+ { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
+ SYS_PCIE5_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
+ SYS_PCIE6_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
#endif
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
CONFIG_SYS_FSL_WRIOP1_SIZE,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 89124cdb0e..bdeb62576c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -44,6 +44,8 @@
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x8
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x8
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x8
+#define SYS_PCIE5_PHYS_SIZE0x8
+#define SYS_PCIE6_PHYS_SIZE0x8
#endif
#define CONFIG_SYS_FSL_WRIOP1_BASE 0x43
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x1
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 9fab88ab2f..c9aa0cad71 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -167,7 +167,19 @@
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x260)
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x270)
-#ifdef CONFIG_ARCH_LS1088A
+#ifdef CONFIG_ARCH_LX2160A
+#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x280)
+#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x290)
+#endif
+
+#ifdef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x80ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x88ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x90ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x98ULL
+#define SYS_PCIE5_PHYS_ADDR0xa0ULL
+#define SYS_PCIE6_PHYS_ADDR0xa8ULL
+#elif CONFIG_ARCH_LS1088A
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x20ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x28ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x30ULL
--
2.17.1
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[U-Boot] [PATCHv4 01/12] armv8: fsl-layerscpae: correct the PCIe controllers' region size
From: Hou Zhiqiang The LS2080A has 8GB region for each PCIe controller, while the other platforms have 32GB. Signed-off-by: Hou Zhiqiang --- V4: - No change arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index d62754e045..89124cdb0e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -34,10 +34,17 @@ #define CONFIG_SYS_FSL_QBMAN_BASE 0x81800 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x800 #define CONFIG_SYS_FSL_QBMAN_SIZE_10x400 +#ifdef CONFIG_ARCH_LS2080A #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x2 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x2 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x2 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x2 +#else +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x8 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x8 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x8 +#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x8 +#endif #define CONFIG_SYS_FSL_WRIOP1_BASE 0x43 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x1 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCHv4 00/12] pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs
From: Hou Zhiqiang Add PCIe Gen4 driver for the NXP Layerscape series SoCs. Hou Zhiqiang (12): armv8: fsl-layerscpae: correct the PCIe controllers' region size armv8: lx2160a: add MMU table entries for PCIe pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPAT pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs armv8: lx2160a: add PCIe controller DT nodes armv8: lx2160a: enable PCIe support pci: ls_pcie_g4: add Workaround for A-011577 dm: pci: add APIs for capability accessors dm: pci: add APIs for MPS and MRRS accessors pci: ls_pcie_g4: Add Workaround for A-011451 pci: ls_pcie_g4: add Workaround for A-011452 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12 + arch/arm/dts/fsl-lx2160a.dtsi | 85 +++ .../arm/include/asm/arch-fsl-layerscape/cpu.h | 9 + .../asm/arch-fsl-layerscape/immap_lsch3.h | 14 +- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 5 + configs/lx2160aqds_tfa_defconfig | 6 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 5 + configs/lx2160ardb_tfa_defconfig | 6 + drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 2 + drivers/pci/pci-uclass.c | 245 drivers/pci/pci_auto.c| 35 ++ drivers/pci/pcie_layerscape_gen4.c| 593 ++ drivers/pci/pcie_layerscape_gen4.h| 273 drivers/pci/pcie_layerscape_gen4_fixup.c | 249 include/pci.h | 33 + include/pci_ids.h | 1 + 18 files changed, 1581 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/pcie_layerscape_gen4.c create mode 100644 drivers/pci/pcie_layerscape_gen4.h create mode 100644 drivers/pci/pcie_layerscape_gen4_fixup.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/2] rockchip: Drop call to rockchip_dnl_mode_check() for now【请注意，邮件由u-boot-boun...@lists.denx.de代发】【请注意，邮件由s...@google.com代发】
Hi Andy, On Wed, 6 Mar 2019 at 03:52, Andy Yan wrote: > > Hi Simon: > > On 2019/2/12 下午11:31, Simon Glass wrote: > > HI Andy, > > > > On Tue, 12 Feb 2019 at 04:05, Andy Yan wrote: > >> Hi Philipp: > >> > >> Sorry for the late reply, we just come back from the Chinese Spring > >> Festival. > >> > >> On 2019/2/1 下午6:26, Philipp Tomsich wrote: > >>> Kever, > >>> > >>> Independent of whether we revert this for the current cycle (and also > >>> independent of > >>> if I ever find the other patch you had been referring to — I couldn’t > >>> find it in my local > >>> mailing list archive) and then deprecate it for the next release > >>> (unless converted to > >>> DM), we still have a number of architectural issues that need to be > >>> addressed: > >> I still doubt is this a right work-flow for patch apply. Before we > >> apply a patch which will break many other boards , should we make > >> sure there is a solution patch applied for these boars first? > >> > >> > >>> 1.This really should be a driver under DTS control. > >>> 2.We need to not get away from configuring SOM-specific addresses via > >>> Kconfig > >>> > >>> Both these issues are technical debt that we’ve accumulated over the > >>> last 18 months > >>> and need to address for the sake of future maintainability. > >>> E.g. ‘setting an address to 0x0 via Kconfig to disable a > >>> driver/feature’ really isn’t in line > >>> with the architectural direction of U-Boot. > >>> > >> For technical side, I think CONFIG_ROCKCHIP_BOOT_MODE_REG is necessary > >> here, we will read this register from save_boot_params when we get out > >> from bootrom, the dtb is not available at this point. > > Yes this is happening very early, but I wonder why this is necessary? > > Can it be moved to later? > > > > The call to check_back_to_brom_dnl_flag() happens much later so there > > should be no problem to convert that. > > > >> On the other hand, almost rockchip based products use a recovery key to > >> enter download(upgrade)mode, this is a muti-funtion key, most of them > >> reuse with vol+- key, we would like the u-boot share > >> > >> dtb with linux kernel. To keep the linux kernel dts as clean as possible > >> ,we don't want to add another dts property to describe this key either. > >> This is why I implement function rockchip_dnl_key_pressed as __weak. > >> > > OK, but given that it is called later, it seems to me that it could > > use a driver. > > > > We can't let it called later. See the discuss here : > http://patchwork.ozlabs.org/patch/812228/ Yes I read that, and took a look myself, and certainly it does not look very easy and I take your point about potential bugs being introduced. It seems like you have tried quite hard, so I'm not going to object if you can't find a way. My main objection was that it broke other boards. Is there any way the check could be delayed enough to actually be able to read the device tree? It could call spl_early_init() quite early and then do that. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [BUG] efi_loader: self-tests fail on qemu-x86_defconfig when compiled with GCC 8.3 and CONFIG_CC_OPTIMIZE_FOR_SIZE=y
Debian has recently (march 8th) upgraded GCC from 8.2 to 8.3. When I compile qemu-x86_defconfig with CONFIG_CC_OPTIMIZE_FOR_SIZE=y some of the UEFI selftests (bootefi selftest) fail. It looks to me like ebx is not conserved. With CONFIG_CC_OPTIMIZE_FOR_SIZE=n everything is fine. Best regards Heinrich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/1] efi_loader: Fix serial console size detection
From: Matthias Brugger
Function term_read_reply tries to read from the serial console until
the end_char was read. This can hang forever if we are, for some reason,
not able to read the full response (e.g. serial buffer too small,
frame error). This patch moves the timeout detection into
term_read_reply() to assure we will make progress.
Fixes: 6bb591f704 ("efi_loader: query serial console size reliably")
Signed-off-by: Matthias Brugger
Throw missing error when an incomplete reply for the cursor position is
received.
Change type of argument of term_get_char() *s32. This renders the function
reusable in efi_cin_read_key().
Reviewed-by: Heinrich Schuchardt
---
v3
Throw missing error when an incomplete reply for the cursor
position is received.
Change type of argument of term_get_char() *s32. This renders the
function reusable in efi_cin_read_key().
v2
move timeout into term_get_char
---
lib/efi_loader/efi_console.c | 62
1 file changed, 35 insertions(+), 27 deletions(-)
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 66c33a551d5..8e0965bfc89 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -62,6 +62,21 @@ static struct simple_text_output_mode efi_con_mode = {
.cursor_visible = 1,
};
+static int term_get_char(s32 *c)
+{
+ u64 timeout;
+
+ /* Wait up to 100 ms for a character */
+ timeout = timer_get_us() + 10;
+
+ while (!tstc())
+ if (timer_get_us() > timeout)
+ return 1;
+
+ *c = getc();
+ return 0;
+}
+
/*
* Receive and parse a reply from the terminal.
*
@@ -72,34 +87,36 @@ static struct simple_text_output_mode efi_con_mode = {
*/
static int term_read_reply(int *n, int num, char end_char)
{
- char c;
+ s32 c;
int i = 0;
- c = getc();
- if (c != cESC)
+ if (term_get_char() || c != cESC)
return -1;
- c = getc();
- if (c != '[')
+
+ if (term_get_char() || c != '[')
return -1;
n[0] = 0;
while (1) {
- c = getc();
- if (c == ';') {
- i++;
- if (i >= num)
+ if (!term_get_char()) {
+ if (c == ';') {
+ i++;
+ if (i >= num)
+ return -1;
+ n[i] = 0;
+ continue;
+ } else if (c == end_char) {
+ break;
+ } else if (c > '9' || c < '0') {
return -1;
- n[i] = 0;
- continue;
- } else if (c == end_char) {
- break;
- } else if (c > '9' || c < '0') {
+ }
+
+ /* Read one more decimal position */
+ n[i] *= 10;
+ n[i] += c - '0';
+ } else {
return -1;
}
-
- /* Read one more decimal position */
- n[i] *= 10;
- n[i] += c - '0';
}
if (i != num - 1)
return -1;
@@ -196,7 +213,6 @@ static int query_console_serial(int *rows, int *cols)
{
int ret = 0;
int n[2];
- u64 timeout;
/* Empty input buffer */
while (tstc())
@@ -216,14 +232,6 @@ static int query_console_serial(int *rows, int *cols)
ESC "[999;999H" /* Move to bottom right corner */
ESC "[6n"); /* Query cursor position */
- /* Allow up to one second for a response */
- timeout = timer_get_us() + 100;
- while (!tstc())
- if (timer_get_us() > timeout) {
- ret = -1;
- goto out;
- }
-
/* Read {rows,cols} */
if (term_read_reply(n, 2, 'R')) {
ret = 1;
--
2.20.1
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[U-Boot] [PATCH v4 1/1] efi_loader: Patch non-runtime code out at ExitBootServices already
From: Alexander Graf
While discussing something compeltely different, Ard pointed out
that it might be legal to omit calling SetVirtualAddressMap altogether.
There is even a patch on the Linux Kernel Mailing List that implements
such behavior by now:
https://patchwork.kernel.org/patch/10782393/
While that sounds great, we currently rely on the SetVirtualAddressMap
call to remove all references to code that would not work outside of
boot services.
So let's patch out those bits already on the call to ExitBootServices,
so that we can successfully run even when an OS chooses to omit
any call to SetVirtualAddressMap.
Reported-by: Ard Biesheuvel
Signed-off-by: Alexander Graf
OpenBSD is not calling SetVirtualAddressMap on ARM 32 bit.
Adjust selftest: expect 'U-Boot' instead of 'resetting'.
Reviewed-by: Heinrich Schuchardt
---
v4
Adjust selftest: expect 'U-Boot' instead of 'resetting'.
(by fault sent as v2)
v3
Add link to upstream Linux patch
v2
Add missing icache invalidation
---
include/efi_loader.h | 2 ++
lib/efi_loader/efi_boottime.c | 1 +
lib/efi_loader/efi_runtime.c | 29 -
test/py/tests/test_efi_selftest.py | 4 ++--
4 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 512880ab8fb..82db7775c72 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -310,6 +310,8 @@ void efi_save_gd(void);
void efi_restore_gd(void);
/* Call this to relocate the runtime section to an address space */
void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map);
+/* Call this when we start to live in a runtime only world */
+void efi_runtime_detach(ulong offset);
/* Call this to set the current device name */
void efi_set_bootdev(const char *dev, const char *devnr, const char *path);
/* Add a new object to the object list. */
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index bd8b8a17ae7..233bca78e0a 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1967,6 +1967,7 @@ static efi_status_t EFIAPI
efi_exit_boot_services(efi_handle_t image_handle,
bootm_disable_interrupts();
/* Disable boot time services */
+ efi_runtime_detach((ulong)gd->relocaddr);
systab.con_in_handle = NULL;
systab.con_in = NULL;
systab.con_out_handle = NULL;
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 636dfdab39d..17d22d429e2 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -276,15 +276,11 @@ struct efi_runtime_detach_list_struct {
void *patchto;
};
-static const struct efi_runtime_detach_list_struct efi_runtime_detach_list[] =
{
+static struct efi_runtime_detach_list_struct efi_runtime_detach_list[] = {
{
/* do_reset is gone */
.ptr = _runtime_services.reset_system,
.patchto = efi_reset_system,
- }, {
- /* invalidate_*cache_all are gone */
- .ptr = _runtime_services.set_virtual_address_map,
- .patchto = _unimplemented,
}, {
/* RTC accessors are gone */
.ptr = _runtime_services.get_time,
@@ -328,7 +324,15 @@ static bool efi_runtime_tobedetached(void *p)
return false;
}
-static void efi_runtime_detach(ulong offset)
+/**
+ * efi_runtime_detach() - Remove any dependency on non-runtime sections
+ *
+ * This function patches all remaining code to be self-sufficient inside
+ * runtime sections. Any calls to non-runtime will be removed after this.
+ *
+ * @offset:relocaddr for pre-set_v_a_space, offset to VA after
+ */
+__efi_runtime void efi_runtime_detach(ulong offset)
{
int i;
ulong patchoff = offset - (ulong)gd->relocaddr;
@@ -344,6 +348,8 @@ static void efi_runtime_detach(ulong offset)
/* Update CRC32 */
efi_update_table_header_crc32(_runtime_services.hdr);
+
+invalidate_icache_all();
}
/* Relocate EFI runtime to uboot_reloc_base = offset */
@@ -430,19 +436,25 @@ void efi_runtime_relocate(ulong offset, struct
efi_mem_desc *map)
* @virtmap: virtual address mapping information
* Return: status code
*/
-static efi_status_t EFIAPI efi_set_virtual_address_map(
+static __efi_runtime efi_status_t EFIAPI efi_set_virtual_address_map(
unsigned long memory_map_size,
unsigned long descriptor_size,
uint32_t descriptor_version,
struct efi_mem_desc *virtmap)
{
+ static __efi_runtime_data bool is_patched;
int n = memory_map_size / descriptor_size;
int i;
int rt_code_sections = 0;
+ if (is_patched)
+ return EFI_INVALID_PARAMETER;
+
EFI_ENTRY("%lx %lx %x %p", memory_map_size, descriptor_size,
[U-Boot] [PATCH v2 1/1] efi_loader: Patch non-runtime code out at ExitBootServices already
From: Alexander Graf
While discussing something compeltely different, Ard pointed out
that it might be legal to omit calling SetVirtualAddressMap altogether.
There is even a patch on the Linux Kernel Mailing List that implements
such behavior by now:
https://patchwork.kernel.org/patch/10782393/
While that sounds great, we currently rely on the SetVirtualAddressMap
call to remove all references to code that would not work outside of
boot services.
So let's patch out those bits already on the call to ExitBootServices,
so that we can successfully run even when an OS chooses to omit
any call to SetVirtualAddressMap.
Reported-by: Ard Biesheuvel
Signed-off-by: Alexander Graf
OpenBSD is not calling SetVirtualAddressMap on ARM 32 bit.
Adjust selftest: expect 'U-Boot' instead of 'resetting'.
Reviewed-by: Heinrich Schuchardt
---
v2
Adjust selftest: expect 'U-Boot' instead of 'resetting'.
---
include/efi_loader.h | 2 ++
lib/efi_loader/efi_boottime.c | 1 +
lib/efi_loader/efi_runtime.c | 29 -
test/py/tests/test_efi_selftest.py | 4 ++--
4 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 512880ab8fb..82db7775c72 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -310,6 +310,8 @@ void efi_save_gd(void);
void efi_restore_gd(void);
/* Call this to relocate the runtime section to an address space */
void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map);
+/* Call this when we start to live in a runtime only world */
+void efi_runtime_detach(ulong offset);
/* Call this to set the current device name */
void efi_set_bootdev(const char *dev, const char *devnr, const char *path);
/* Add a new object to the object list. */
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index bd8b8a17ae7..233bca78e0a 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1967,6 +1967,7 @@ static efi_status_t EFIAPI
efi_exit_boot_services(efi_handle_t image_handle,
bootm_disable_interrupts();
/* Disable boot time services */
+ efi_runtime_detach((ulong)gd->relocaddr);
systab.con_in_handle = NULL;
systab.con_in = NULL;
systab.con_out_handle = NULL;
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 636dfdab39d..17d22d429e2 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -276,15 +276,11 @@ struct efi_runtime_detach_list_struct {
void *patchto;
};
-static const struct efi_runtime_detach_list_struct efi_runtime_detach_list[] =
{
+static struct efi_runtime_detach_list_struct efi_runtime_detach_list[] = {
{
/* do_reset is gone */
.ptr = _runtime_services.reset_system,
.patchto = efi_reset_system,
- }, {
- /* invalidate_*cache_all are gone */
- .ptr = _runtime_services.set_virtual_address_map,
- .patchto = _unimplemented,
}, {
/* RTC accessors are gone */
.ptr = _runtime_services.get_time,
@@ -328,7 +324,15 @@ static bool efi_runtime_tobedetached(void *p)
return false;
}
-static void efi_runtime_detach(ulong offset)
+/**
+ * efi_runtime_detach() - Remove any dependency on non-runtime sections
+ *
+ * This function patches all remaining code to be self-sufficient inside
+ * runtime sections. Any calls to non-runtime will be removed after this.
+ *
+ * @offset:relocaddr for pre-set_v_a_space, offset to VA after
+ */
+__efi_runtime void efi_runtime_detach(ulong offset)
{
int i;
ulong patchoff = offset - (ulong)gd->relocaddr;
@@ -344,6 +348,8 @@ static void efi_runtime_detach(ulong offset)
/* Update CRC32 */
efi_update_table_header_crc32(_runtime_services.hdr);
+
+invalidate_icache_all();
}
/* Relocate EFI runtime to uboot_reloc_base = offset */
@@ -430,19 +436,25 @@ void efi_runtime_relocate(ulong offset, struct
efi_mem_desc *map)
* @virtmap: virtual address mapping information
* Return: status code
*/
-static efi_status_t EFIAPI efi_set_virtual_address_map(
+static __efi_runtime efi_status_t EFIAPI efi_set_virtual_address_map(
unsigned long memory_map_size,
unsigned long descriptor_size,
uint32_t descriptor_version,
struct efi_mem_desc *virtmap)
{
+ static __efi_runtime_data bool is_patched;
int n = memory_map_size / descriptor_size;
int i;
int rt_code_sections = 0;
+ if (is_patched)
+ return EFI_INVALID_PARAMETER;
+
EFI_ENTRY("%lx %lx %x %p", memory_map_size, descriptor_size,
descriptor_version, virtmap);
+ is_patched = true;
+
/*
* TODO:
* Further down we are
Re: [U-Boot] [PATCH v3 1/7] cmd: part: Add 'number' sub-command
Hi Igor,
On Mon, Feb 18, 2019 at 06:21:51PM +0200, Igor Opaniuk wrote:
> From: Ruslan Trofymenko
>
> This sub-command serves for getting the partition index from
> partition name.
[..]
> CMD_PART_INFO_SIZE,
> + CMD_PART_INFO_NUMBER
IMHO 's/number/index/' (when referring to the id of a partition) would
make code and documentation more clear since 'number' can be confused
with 'count' while 'index' is unequivocal.
Feel free to ignore it though, as the terms seem to be intermixed in
various places of Linux/U-Boot (my opinion still stands).
The review comment also applies to other patches from this series:
- https://patchwork.ozlabs.org/patch/1044153/ ("[U-Boot,v3,2/7] disk:
part: Extend API to get partition info")
- https://patchwork.ozlabs.org/patch/1044162/ ("[U-Boot,v3,6/7] doc:
android: Add simple guide for A/B updates")
- https://patchwork.ozlabs.org/patch/1044160/ ("[U-Boot,v3,7/7] env:
am57xx: Implement A/B boot process")
Best regards,
Eugeniu.
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Re: [U-Boot] [PATCH 2/4] lib: fdt: Split fdtdec_setup_memory_banksize()
On Mon, 4 Mar 2019 at 20:26, Marek Vasut wrote: > > Split fdtdec_setup_memory_banksize() into fdtdec_setup_memory_banksize_fdt(), > which allows the caller to pass custom blob into the function and the > original fdtdec_setup_memory_banksize(), which uses the gd->fdt_blob. This > is useful when configuring the DRAM properties from a FDT blob fragment > passed in by the firmware. > > Signed-off-by: Marek Vasut > Cc: Nobuhiro Iwamatsu > Cc: Simon Glass > Cc: Tom Rini > --- > include/fdtdec.h | 19 +++ > lib/fdtdec.c | 18 -- > 2 files changed, 31 insertions(+), 6 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] fdtdec: Implement fdtdec_add_reserved_memory()
On Fri, 8 Mar 2019 at 13:11, Thierry Reding wrote:
>
> From: Thierry Reding
>
> This function can be used to add subnodes in the /reserved-memory node.
>
> Signed-off-by: Thierry Reding
> ---
> include/fdtdec.h | 17 +
> lib/fdtdec.c | 158 +++
> 2 files changed, 175 insertions(+)
>
I think an example would be useful, or perhaps a pointer to some docs
(perhaps DT spec?) showing how this function is used?
Reviewed-by: Simon Glass
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index 997103a87cdf..5c9108ced571 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -979,6 +979,23 @@ int fdtdec_get_max_phandle(const void *blob, uint32_t
> *maxp);
> */
> int fdtdec_set_phandle(void *blob, int node, uint32_t phandle);
>
> +/**
> + * fdtdec_add_reserved_memory() - add or find a reserved-memory node
> + *
> + * If a reserved-memory node already exists for the given carveout, a phandle
> + * for that node will be returned. Otherwise a new node will be created and a
> + * phandle corresponding to it will be returned.
> + *
> + * @param blob FDT blob
> + * @param basename base name of the node to create
> + * @param carveout information about the carveout region
> + * @param phandlep return location for the phandle of the carveout region
> + * @return 0 on success or a negative error code on failure
> + */
> +int fdtdec_add_reserved_memory(void *blob, const char *basename,
> + const struct fdt_memory *carveout,
> + uint32_t *phandlep);
> +
> /**
> * Set up the device tree ready for use
> */
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 9195a05d1129..a8b35c144ae0 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -1287,6 +1287,164 @@ int fdtdec_set_phandle(void *blob, int node, uint32_t
> phandle)
> return 0;
> }
>
> +static int fdtdec_init_reserved_memory(void *blob)
> +{
> + int na, ns, node, err;
> + fdt32_t value;
> +
> + /* inherit #address-cells and #size-cells from the root node */
> + na = fdt_address_cells(blob, 0);
> + ns = fdt_size_cells(blob, 0);
> +
> + node = fdt_add_subnode(blob, 0, "reserved-memory");
> + if (node < 0)
> + return node;
> +
> + err = fdt_setprop(blob, node, "ranges", NULL, 0);
> + if (err < 0)
> + return err;
> +
> + value = cpu_to_fdt32(na);
> +
> + err = fdt_setprop(blob, node, "#address-cells", ,
> sizeof(value));
> + if (err < 0)
> + return err;
> +
> + value = cpu_to_fdt32(ns);
> +
> + err = fdt_setprop(blob, node, "#size-cells", , sizeof(value));
> + if (err < 0)
> + return err;
> +
> + return node;
> +}
> +
> +static void fdt_addr_unpack(fdt_addr_t addr, fdt32_t *upper, fdt32_t *lower)
> +{
> +#ifdef CONFIG_PHYS_64BIT
> + *upper = addr >> 32;
> +#else
> + *upper = 0;
> +#endif
> +
> + *lower = addr;
> +}
> +
> +static void fdt_size_unpack(fdt_size_t size, fdt32_t *upper, fdt32_t *lower)
> +{
> +#ifdef CONFIG_PHYS_64BIT
> + *upper = size >> 32;
> +#else
> + *upper = 0;
> +#endif
> +
> + *lower = size;
> +}
> +
> +int fdtdec_add_reserved_memory(void *blob, const char *basename,
> + const struct fdt_memory *carveout,
> + uint32_t *phandlep)
> +{
> + fdt32_t cells[4] = {}, *ptr = cells;
> + uint32_t upper, lower, phandle;
> + int parent, node, na, ns, err;
> + char name[64];
> +
> + /* create an empty /reserved-memory node if one doesn't exist */
> + parent = fdt_path_offset(blob, "/reserved-memory");
> + if (parent < 0) {
> + parent = fdtdec_init_reserved_memory(blob);
> + if (parent < 0)
> + return parent;
> + }
> +
> + /* only 1 or 2 #address-cells and #size-cells are supported */
> + na = fdt_address_cells(blob, parent);
> + if (na < 1 || na > 2)
> + return -FDT_ERR_BADNCELLS;
> +
> + ns = fdt_address_cells(blob, parent);
> + if (ns < 1 || ns > 2)
> + return -FDT_ERR_BADNCELLS;
> +
> + /* find a matching node and return the phandle to that */
> + fdt_for_each_subnode(node, blob, parent) {
> + const char *name = fdt_get_name(blob, node, NULL);
> + phys_addr_t addr, size;
> +
> + addr = fdtdec_get_addr_size(blob, node, "reg", );
> + if (addr == FDT_ADDR_T_NONE) {
> + printf("failed to read address/size for %s\n", name);
> + continue;
> + }
> +
> + if (addr == carveout->start && (addr + size) ==
> carveout->end) {
> + *phandlep = fdt_get_phandle(blob, node);
> + return 0;
> + }
> + }
> +
> + /*
> +
Re: [U-Boot] [PATCH 1/2] syscon: update syscon_regmap_lookup_by_phandle
On Thu, 7 Mar 2019 at 01:57, Patrick Delaunay wrote:
>
> Change the function syscon_regmap_lookup_by_phandle()
> introduced by commit 6c3af1f24e4b ("syscon: dm: Add a
> new method to get a regmap from DTS") to have
> Linux-compatible syscon API.
>
> Same modification than commit e151a1c288bd ("syscon: add
> Linux-compatible syscon API") solves issue when the node
> identified by the phandle has several compatibles and is
> already bound to a dedicated driver.
>
> See Linux commit bdb0066df96e ("mfd: syscon: Decouple syscon
> interface from platform devices").
>
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/sandbox/dts/test.dts| 3 +-
> drivers/core/syscon-uclass.c | 83
> +++-
> test/dm/syscon.c | 7
> 3 files changed, 68 insertions(+), 25 deletions(-)
>
Reviewed-by: Simon Glass
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Re: [U-Boot] [U-Boot-DM] pre-reloc fdt scan for non-top-level nodes
Hi Viktor, On Wed, 6 Mar 2019 at 13:26, Simon Glass wrote: > > (We don't use the -dm mailing list...perhaps it should be deleted?) > > On Wed, 27 Feb 2019 at 09:22, viktor babrian wrote: >> >> Hi, >> >> as far as I understood, the pre-reloc device binding of drivers having >> DM_FLAG_PRE_RELOC flag set is only performed for top-level devices - >> at least that is what I experience. Is this intentional? What is the >> concept there? Well if the top-level node doesn't have it, then it doesn't look at that node (and in fact in SPL it is removed from the DT during compilation) so does not get to check child nodes. >> I am trying to use a spi slave display that is by default described as >> a node under root/soc/spiX. We have the device working under Linux. I >> understand these displays are not supported as is in u-boot so I >> ported some Linux code and made some minor mods in the video uclass. >> Still I do not have memory reserved for the frame-buffer and debugging >> shows that it is because bind() is not invoked pre-reloc. And it is >> not invoked because dm_extended_scan_fdt() parses top-level nodes >> only. >> I wonder if that pre-reloc scan is so for some purpose because a >> recursive scan would seemingly be justified in my case. >> (or am I just missing something?) See above. You can add u-boot,dm-pre-reloc to the node to make it be scanned before relocation. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] lib: fdt: Split fdtdec_setup_mem_size_base()
On Mon, 4 Mar 2019 at 20:26, Marek Vasut wrote: > > Split fdtdec_setup_mem_size_base() into fdtdec_setup_mem_size_base_fdt(), > which allows the caller to pass custom blob into the function and the > original fdtdec_setup_mem_size_base(), which uses the gd->fdt_blob. This > is useful when configuring the DRAM properties from a FDT blob fragment > passed in by the firmware. > > Signed-off-by: Marek Vasut > Cc: Nobuhiro Iwamatsu > Cc: Simon Glass > Cc: Tom Rini > --- > include/fdtdec.h | 20 > lib/fdtdec.c | 11 --- > 2 files changed, 28 insertions(+), 3 deletions(-) > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] core: ofnode: Fix ASAN-reported stack-buffer-overflow in of_get_address
On Sat, 9 Mar 2019 at 09:27, Eugeniu Rosca wrote:
>
> v2019.04-rc3 sandbox U-Boot fails to boot when compiled with
> -fsanitize=address and linked against -lasan, reporting [1].
>
> Git bisecting shows that the issue is contributed by v2019.01 commit
> 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function").
>
> The root cause seems to be the mismatch between sizeof(u64) and
> sizeof(fdt_size_t) on sandbox. Luckily, thanks to the fact that the
> size argument of both of_get_address() and fdtdec_get_addr_size_fixed()
> is optional, we can pass NULL in its place, avoiding the problem.
>
> [1] Backtrace reported by ASAN (gcc 8.1.0):
>
> $> ./u-boot -d arch/sandbox/dts/sandbox.dtb
> [..]
> =
> ==10998==ERROR: AddressSanitizer: stack-buffer-overflow on address
> 0x7ffcc2331140 at pc 0x004eeeb0 bp 0x7ffcc2330f80 sp 0x7ffcc2330f70
> WRITE of size 8 at 0x7ffcc2331140 thread T0
> #0 0x4eeeaf in of_get_address drivers/core/of_addr.c:154
> #1 0x4f7441 in ofnode_get_addr_index drivers/core/ofnode.c:263
> #2 0x5b2a78 in sb_eth_ofdata_to_platdata drivers/net/sandbox.c:422
> #3 0x4dccd8 in device_probe drivers/core/device.c:407
> #4 0x753170 in eth_initialize net/eth-uclass.c:428
> #5 0x47d9bf in initr_net common/board_r.c:557
> #6 0x6bcfa7 in initcall_run_list lib/initcall.c:30
> #7 0x47e1fe in board_init_r common/board_r.c:859
> #8 0x4060e5 in main arch/sandbox/cpu/start.c:356
> #9 0x7fb8d135482f in __libc_start_main
> (/lib/x86_64-linux-gnu/libc.so.6+0x2082f)
> #10 0x40a3a8 in _start (/path/to/u-boot/u-boot+0x40a3a8)
>
> Address 0x7ffcc2331140 is located in stack of thread T0 at offset 32 in frame
> #0 0x4f72b8 in ofnode_get_addr_index drivers/core/ofnode.c:255
>
> This frame has 3 object(s):
> [32, 36) 'size' <== Memory access at offset 32 partially overflows this
> variable
> [96, 100) 'flags'
> [160, 168) 'node'
> HINT: this may be a false positive if your program uses some custom stack
> unwind mechanism or swapcontext
> (longjmp and C++ exceptions *are* supported)
> SUMMARY: AddressSanitizer: stack-buffer-overflow drivers/core/of_addr.c:154
> in of_get_address
> Shadow bytes around the buggy address:
> 0x10001845e1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0x10001845e1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0x10001845e1f0: 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 f1 f1
> 0x10001845e200: 04 f2 f2 f2 f2 f2 f2 f2 04 f2 f2 f2 f2 f2 f2 f2
> 0x10001845e210: 04 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 00 00
> =>0x10001845e220: 00 00 00 00 f1 f1 f1 f1[04]f2 f2 f2 f2 f2 f2 f2
> 0x10001845e230: 04 f2 f2 f2 f2 f2 f2 f2 00 f2 f2 f2 f3 f3 f3 f3
> 0x10001845e240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0x10001845e250: 00 00 00 00 f1 f1 f1 f1 00 00 f2 f2 f3 f3 f3 f3
> 0x10001845e260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1
> 0x10001845e270: f1 f1 00 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00
> Shadow byte legend (one shadow byte represents 8 application bytes):
> Addressable: 00
> Partially addressable: 01 02 03 04 05 06 07
> Heap left redzone: fa
> Freed heap region: fd
> Stack left redzone: f1
> Stack mid redzone: f2
> Stack right redzone: f3
> Stack after return: f5
> Stack use after scope: f8
> Global redzone: f9
> Global init order: f6
> Poisoned by user:f7
> Container overflow: fc
> Array cookie:ac
> Intra object redzone:bb
> ASan internal: fe
> Left alloca redzone: ca
> Right alloca redzone:cb
> ==10998==ABORTING
>
> 'To' list:
> git log --since=1year drivers/core/ofnode.c | grep "\-by: .*@" | \
> sed 's/.*-by: //' | sort | uniq -c | sort -rn
> 10 Simon Glass
> 3 Mario Six
> 2 Martin Fuzzey
> 2 Marek Vasut
> 1 Tom Rini
> 1 Masahiro Yamada
> 1 Keerthy
> 1 Jens Wiklander
> 1 Bin Meng
>
> Fixes: 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function")
> Signed-off-by: Eugeniu Rosca
> ---
> drivers/core/ofnode.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass
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Re: [U-Boot] [PATCHv1 2/4] dm: cache: Create a uclass for cache controller
Hi Dinh,
On Fri, 8 Mar 2019 at 09:17, Dinh Nguyen wrote:
>
> The cache controller driver configures the cache settings that can be
> found in the device tree files.
>
> This initial revision only configures basic settings(data & instruction
> prefetch, shared-override, data & tag latency). I believe these are the
> settings that affect performance the most. Comprehensive settings can be
> done by the OS.
>
> Signed-off-by: Dinh Nguyen
> ---
> drivers/Kconfig | 2 +
> drivers/Makefile | 1 +
> drivers/cache/Kconfig| 22 ++
> drivers/cache/Makefile | 3 ++
> drivers/cache/cache-l2x0.c | 82
This looks like a driver, rather than the uclass itself, so should go
in a separate patch.
> drivers/cache/cache-uclass.c | 13 ++
> include/dm/uclass-id.h | 1 +
> 7 files changed, 124 insertions(+)
> create mode 100644 drivers/cache/Kconfig
> create mode 100644 drivers/cache/Makefile
> create mode 100644 drivers/cache/cache-l2x0.c
> create mode 100644 drivers/cache/cache-uclass.c
Also please add a sandbox cache driver and some tests in test/dm/cache.c
>
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index f24351ac4f..842201b753 100644
> --- a/drivers/Kconfig
> +++ b/drivers/Kconfig
> @@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
>
> source "drivers/bootcount/Kconfig"
>
> +source "drivers/cache/Kconfig"
> +
> source "drivers/clk/Kconfig"
>
> source "drivers/cpu/Kconfig"
> diff --git a/drivers/Makefile b/drivers/Makefile
> index a7bba3ed56..0a00096332 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
> obj-y += block/
> obj-y += board/
> obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
> +obj-y += cache/
> obj-$(CONFIG_CPU) += cpu/
> obj-y += crypto/
> obj-$(CONFIG_FASTBOOT) += fastboot/
> diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
> new file mode 100644
> index 00..d6b2b6762a
> --- /dev/null
> +++ b/drivers/cache/Kconfig
> @@ -0,0 +1,22 @@
> +#
> +# Cache controllers
> +#
> +
> +menu "Cache Controller drivers"
> +
> +config CACHE
> + bool "Enable Driver Model for Cache drivers"
> + depends on DM
> + help
> + Enable driver model for cache controllers.
Please add more documentation here. What exactly is a cache controller
(for CPU?) and what can you control with it?
Normally the uclass documentation goes in its header file. Since you
don't have one, you could put it in the uclass file. You should
mention that the settings can come from the DT and that there are no
uclass operations supported, only setting up the cache.
> +
> +config L2X0_CACHE
> + tristate "PL310 cache driver"
> + select CACHE
> + depends on ARM
> + help
> + This driver is for the PL310 cache controller commonly found on
> + ARMv7(32-bit) devices. The driver configures the cache settings
> + found in the device tree.
Again this should be in another patch.
> +
> +endmenu
> diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
> new file mode 100644
> index 00..fca37de0a8
> --- /dev/null
> +++ b/drivers/cache/Makefile
> @@ -0,0 +1,3 @@
> +
> +obj-$(CONFIG_CACHE) += cache-uclass.o
> +obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
> diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
> new file mode 100644
> index 00..cdd6ddb59b
> --- /dev/null
> +++ b/drivers/cache/cache-l2x0.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Intel Corporation
> + */
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +
> +static void l2c310_of_parse(struct udevice *dev)
> +{
> + u32 tag[3] = { 0, 0, 0 };
> + u32 saved_reg, prefetch;
> + int ret;
> + struct pl310_regs *regs = (struct pl310_regs *)devfdt_get_addr(dev);
This should normally be read (perhaps into struct l2c310_priv *) in
l2x0_ofdata_to_platdata().
However in this case you don't need the setting later, so it seems OK
to do this. Please use dev_read_...() API always (not devfdt which
doesn't work on livetree).
> +
> + /*Disable the L2 Cache */
Space after /*
> + clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
> +
> + saved_reg = readl(>pl310_aux_ctrl);
> + if (dev_read_u32(dev, "prefetch-data", ) == 0) {
I'm not sure about your error handling here. Are these properties
optional? Is there a binding file you can bring in from Linux?
If these are just optional, then this is OK, but please:
if (!dev_read...())
> + if (prefetch)
> + saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
> + else
> + saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
> + }
> +
> + if (dev_read_u32(dev, "prefetch-instr", ) == 0) {
> + if (prefetch)
> + saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
>
Re: [U-Boot] [PATCH] dm: check OF_LIVE is enabled
Hi Ibai, On Tue, 26 Feb 2019 at 02:26, Ibai Erkiaga wrote: > > Livetree implemented functions does not have conditional compilation so > check if CONFIG_IS_ENABLED prior using those functions. > > The issue does not report any error in a normal build as the toolchain > optimize the code. Using -O0 triggers the error so the patch is intended > to fix issues on a ongoing effor to build U-Boot with -O0. > > Signed-off-by: Ibai Erkiaga > --- > > drivers/core/ofnode.c | 60 > +- > drivers/serial/serial-uclass.c | 2 +- > 2 files changed, 31 insertions(+), 31 deletions(-) > This is supposed to work by using of_live_active(), which is called from ofnode_is_np(). Instead of changing all this code, is it possible to update of_live_active() somehow? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Revert "Ensure device tree DTS is compiled"
Hi Tom, Masahiro,
On Sat, 9 Mar 2019 at 10:42, Tom Rini wrote:
>
> On Sun, Mar 10, 2019 at 01:07:48AM +0900, Masahiro Yamada wrote:
> > Hi Tom,
> >
> >
> > On Sat, Mar 9, 2019 at 8:04 AM Tom Rini wrote:
> > >
> > > On Thu, Mar 07, 2019 at 11:13:52PM +0900, Masahiro Yamada wrote:
> > >
> > > > This reverts commit 27cb7300ffda7a3f1581f0f5a2d3bfe59b97ad67.
> > > >
> > > > I am not sure if I correctly understood the log of commit 27cb7300ffda
> > > > ("Ensure device tree DTS is compiled"), but the code-diff looks like
> > > > it was trying to solve the missed re-compilation when .dts was modified.
> > > >
> > > > Recently, commit 2737dfe096b6 ("kbuild: make arch-dtbs target PHONY")
> > > > fixed the issue in a more correct and more complete way.
> > > >
> > > > Anyway, since the former commit, we see a clumsy log like this:
> > > >
> > > > make[2]: 'arch/sandbox/dts/sandbox.dtb' is up to date
> > > >
> > > > So, let's revert it.
> > > >
> > > > Signed-off-by: Masahiro Yamada
> > >
> > > This causes tons of breakage like:
> > >arm: + rpi_0_w
> > > +(rpi_0_w)
> > > +(rpi_0_w) Device Tree Source is not correctly specified.
> > > +(rpi_0_w) Please define 'CONFIG_DEFAULT_DEVICE_TREE'
> > > +(rpi_0_w) or build with 'DEVICE_TREE=' argument
> > > +(rpi_0_w) make[2]: *** [arch/arm/dts/bcm2835-rpi-zero-w.dtb] Error 1
> > > +(rpi_0_w) make[1]: *** [dts] Error 2
> > > +(rpi_0_w) make: *** [sub-make] Error 2
> > >
> >
> >
> > This is because arch/arm/dts/Makefile
> > has no entry for bcm2835-rpi-zero-w.dtb.
> >
> >
> >
> >
> > The following patch should fix the error
> >
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 2a040b2..5540f1b 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -582,6 +582,7 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
> > bcm2835-rpi-b-plus.dtb \
> > bcm2835-rpi-b-rev2.dtb \
> > bcm2835-rpi-b.dtb \
> > + bcm2835-rpi-zero-w.dtb \
> > bcm2836-rpi-2-b.dtb \
> > bcm2837-rpi-3-b.dtb
> >
> >
> >
> >
> >
> > The reverted commit was hiding the issue.
> >
> > I believe DTB files should be explicitly associated
> > with CONFIG option in Makefile.
> > U-Boot used to work that way, and so does Linux.
> >
> >
> > I do not know how may boards are broken now, but
> > the right thing to do is to add dtb entries to Makefile,
> > the revert the bad commit.
>
> OK, that sounds good. But it's a non-trivial number of boards to fix,
> so it's a real series to be put on the TODO list then. Thanks for
> explaining!
If you are suggesting that we should have a separate CONFIG option for
every DT, I don't agree:
1. It adds more CONFIGs for no other purpose, or makes use of TARGET
configs which we try to avoid using
2. It reduces the testing of DT files for related builds. E.g. you can
change something in a common .dtsi file which works fine for one board
but breaks another, and you only find out when you build all the
boards.
Sorry if I have the wrong end of the stick.
Regards,
Simon
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Re: [U-Boot] [PATCH 5/6] fdtdec: Implement carveout support functions
Hi Thierry, On Fri, 8 Mar 2019 at 13:11, Thierry Reding wrote: > > From: Thierry Reding > > The fdtdec_get_carveout() and fdtdec_set_carveout() function can be used > to read a carveout from a given node or add a carveout to a given node > using the standard device tree bindings (involving reserved-memory nodes > and the memory-region property). > > Signed-off-by: Thierry Reding > --- > include/fdtdec.h | 39 ++ > lib/fdtdec.c | 85 > 2 files changed, 124 insertions(+) Reviewed-by: Simon Glass Again I worry a bit about adding flattree-only functions. Also, is there a test? Finally, I think debug() is pretty than printf() for code size. Regards, SImon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] misc: fs_loader: Replace label with DT phandle
Hi Tien Fong, On Tue, 26 Feb 2019 at 05:37, Chee, Tien Fong wrote: > > On Fri, 2019-02-15 at 14:35 +0800, tien.fong.c...@intel.com wrote: > > From: Tien Fong Chee > > > > In previously label which will be expanded to the node's full path > > was > > used, and now replacing label with most commonly used DT phandle. The > > codes were changed accordingly to the use of DT phandle and > > supporting > > multiple instances. > > > > Signed-off-by: Tien Fong Chee > > --- > > doc/driver-model/fs_firmware_loader.txt | 58 > > +-- > > drivers/misc/fs_loader.c| 36 --- > > 2 files changed, 62 insertions(+), 32 deletions(-) This seems OK to me, but I think this feature needs a test. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] x86: Make sure i8254 is setup correctly before generating beeps
On Tue, 26 Feb 2019 at 02:47, Bin Meng wrote: > > The i8254 timer control IO port (0x43) should be setup correctly > by using PIT counter 2 to generate beeps, however in U-Boot other > codes like TSC driver utilizes PIT for TSC frequency calibration > and configures the counter 2 to a different mode that does not > beep. Fix this by always ensuring the PIT counter 2 is correctly > initialized so that the i8254 beeper driver works as expected. > > Signed-off-by: Bin Meng > --- > > arch/x86/lib/i8254.c | 4 > 1 file changed, 4 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] x86: coreboot: Add the missing pc speaker node in the device tree
On Tue, 26 Feb 2019 at 02:47, Bin Meng wrote: > > This is currently missing and without it the i8254 beeper driver > won't work. > > Signed-off-by: Bin Meng > --- > > arch/x86/dts/coreboot.dts | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt: Remove duplicate code
On Fri, 1 Mar 2019 at 11:20, Thierry Reding wrote:
>
> From: Thierry Reding
>
> Commit 6d29cc7dcf2d ("fdt: Fixup only valid memory banks") ended up
> being merged twice, first as:
>
> commit 6d29cc7dcf2d35966aa0b6119fd1cbca0d21d5e6
> Author: Thierry Reding
> AuthorDate: Tue Jan 30 11:34:17 2018 +0100
> Commit: Simon Glass
> CommitDate: Sun Feb 18 12:53:38 2018 -0700
>
> fdt: Fixup only valid memory banks
>
> Memory banks with address 0 and size 0 are empty and should not be
> passed to the OS via device tree.
>
> Signed-off-by: Thierry Reding
> Acked-by: Stephen Warren
>
> and later again, though this time it was v2:
>
> commit ed5af03f9bb8905f1e94d68ab49f22d7f061d75f
> Author: Thierry Reding
> AuthorDate: Thu Feb 15 19:05:59 2018 +0100
> Commit: Tom Rini
> CommitDate: Fri Feb 23 10:40:50 2018 -0500
>
> fdt: Fixup only valid memory banks
>
> Memory banks with address 0 and size 0 are empty and should not be
> passed to the OS via device tree.
>
> Acked-by: Stephen Warren
> Signed-off-by: Thierry Reding
>
> The second version was slightly different, so the main hunk of the patch
> was applied twice. This isn't harmful because the code is idempotent,
> but it's wasteful to run the same code twice.
>
> Signed-off-by: Thierry Reding
> ---
> common/fdt_support.c | 6 --
> 1 file changed, 6 deletions(-)
Reviewed-by: Simon Glass
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Re: [U-Boot] [PATCH 4/4] x86: crownbay: Enable the beeper sound driver
On Tue, 26 Feb 2019 at 02:47, Bin Meng wrote: > > Use the i8254 sound driver to support creating simple beeps. > > Signed-off-by: Bin Meng > --- > > arch/x86/dts/crownbay.dts | 1 + > configs/crownbay_defconfig | 3 +++ > 2 files changed, 4 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] dm: Also remove interrupts property from SPL DT
On Fri, 22 Feb 2019 at 02:50, Michal Simek wrote: > > interrupt-parent property is removed already that's why there is no > reason to keep interrupts property if parent doesn't exist. > > Signed-off-by: Michal Simek > --- > > dts/Kconfig | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/6] fdtdec: Implement fdtdec_set_phandle()
Hi Thierry,
On Fri, 8 Mar 2019 at 13:11, Thierry Reding wrote:
>
> From: Thierry Reding
>
> This function can be used to set a phandle for a given node.
>
> Signed-off-by: Thierry Reding
> ---
> include/fdtdec.h | 11 +++
> lib/fdtdec.c | 16
> 2 files changed, 27 insertions(+)
This seems OK, although I think it should have a test.
But what about livetree? I think it would make more sense to add a
high-level API which can deal with livetree/flattree.
>
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index 5eb3c0c237a9..997103a87cdf 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -968,6 +968,17 @@ int fdtdec_setup_memory_banksize(void);
> */
> int fdtdec_get_max_phandle(const void *blob, uint32_t *maxp);
>
> +/**
> + * fdtdec_set_phandle() - sets the phandle of a given node
> + *
> + * @param blob FDT blob
> + * @param node offset in the FDT blob of the node whose phandle is to
> + * be set
> + * @param phandle phandle to set for the given node
> + * @return 0 on success or a negative error code on failure
> + */
> +int fdtdec_set_phandle(void *blob, int node, uint32_t phandle);
> +
> /**
> * Set up the device tree ready for use
> */
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index f2af947c106e..9195a05d1129 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -1271,6 +1271,22 @@ int fdtdec_get_max_phandle(const void *blob, uint32_t
> *maxp)
> return 0;
> }
>
> +int fdtdec_set_phandle(void *blob, int node, uint32_t phandle)
> +{
> + fdt32_t value = cpu_to_fdt32(phandle);
> + int err;
> +
> + err = fdt_setprop(blob, node, "linux,phandle", , sizeof(value));
> + if (err < 0)
> + return err;
Why set both properties?
> +
> + err = fdt_setprop(blob, node, "phandle", , sizeof(value));
> + if (err < 0)
> + return err;
> +
> + return 0;
> +}
> +
> int fdtdec_setup(void)
> {
> #if CONFIG_IS_ENABLED(OF_CONTROL)
> --
> 2.20.1
>
Regards,
SImon
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Re: [U-Boot] Pincontroller not getting initialized on imx6 in SPL with SPL_PINCTRL and OF_CONTROL
HI Adam,
On Fri, 22 Feb 2019 at 12:22, Adam Ford wrote:
>
> On Wed, Feb 20, 2019 at 11:38 AM Adam Ford wrote:
> >
> > On Wed, Feb 20, 2019 at 10:09 AM Lokesh Vutla wrote:
> > >
> > >
> > >
> > > On 2/20/2019 8:46 PM, Adam Ford wrote:
> > > > On Wed, Feb 20, 2019 at 7:49 AM Lokesh Vutla wrote:
> > > >>
> > > >> Hi Adam,
> > > >>
> > > >> On 20/02/19 7:01 PM, Adam Ford wrote:
> > > >>> I am trying to remove the manual pinmuxing code from the board file.
> > > >>> In an effort to accomplish this, I am trying to get SPL_OF_CONTROL and
> > > >>> SPL_PINCTRL to let me use the device tree(s) to initialize pin muxing.
> > > >>>
> > > >>> I have the following defined:
> > > >>>
> > > >>> CONFIG_SPL_PINCTRL=y
> > > >>> CONFIG_SPL_PINCTRL_FULL=y
> > > >>> CONFIG_SPL_PINCTRL_GENERIC=y
> > > >>> CONFIG_SPL_PINMUX=y
> > > >>>
> > > >>> along with
> > > >>> CONFIG_PINCTRL_IMX=y
> > > >>> CONFIG_PINCTRL_IMX6=y
> > > >>>
> > > >>> I put some debugging code into the imx6 pinctrl and I can see that
> > > >>> U-Boot initializes it, but that same debug message doesn't appear in
> > > >>> SPL.
> > > >>>
> > > >>> I looked through the spl build directory, and I can see the drivers
> > > >>> have been built, and the map file shows they exist, but for some
> > > >>> reason, it doesn't initalize. If I remove the UART pin-muxing from my
> > > >>> board file, the text for SPL doesn't' appear at all, so it's clear
> > > >>> pinctrl isn't setting up the proper muxing yet.
> > > >>>
> > > >>> I am trying to figure out how/where the pinctrl system gets
> > > >>> initialized in SPL, and I was hoping someone might have some insight.
> > > >>
> > > >> Pinctrl will be set as part of device_probe() call[1] for each device.
> > > >
> > > > Thanks for the quick reply. I took your suggestion and did a little
> > > > more digging.
> > > >
> > > >>
> > > >> Have you added u-boot,dm-spl for your pinctrl nodes? Try de-compiling
> > > >> spl dts
> > > >> and check if all required nodes are available.
> > > >
> > > > u-boot,dm-spl is setup in a common imx6qdl-u-boot.dtsi file. The spl
> > > > decompiled device tree show it.
> > > >
> > > > iomuxc@20e {
> > > > compatible = "fsl,imx6q-iomuxc";
> > > > reg = < 0x20e 0x4000 >;
> > > > pinctrl-names = "default";
> > > > pinctrl-0 = < 0x2b >;
> > > > u-boot,dm-spl;
> > > > phandle = < 0x21 >;
> > > >
> > > > uart1grp {
> > > > fsl,pins = < 0x2ac 0x694 0x920 0x01 0x03 0x1b0b1 0x2a8 0x690
> > > > 0x00 0x01 0x00 0x1b0b1 >;
> > > > u-boot,dm-spl;
> > > > phandle = < 0x1d >;
> > > > };
> > > > };
> > > >
> > > > With some debugging enabled during the fdtdec, I can see some chatter
> > > > and references to it, but it looks like it cannot find it.
> > > >
> > > > U-Boot SPL 2019.04-rc2-03217-g2d08aa679e-dirty (Feb 20 2019 - 08:15:13
> > > > -0600)
> > > > fdtdec_get_int_array: ranges
> > > > get_prop_check_min_len: ranges
> > > > fdtdec_get_int_array: ranges
> > > > get_prop_check_min_len: ranges
> > > > Looking for 'gpio' at 1224, name gpio@209c000
> > > >- gpio0, /soc/aips-bus@200/gpio@209c000
> > > > Found seq 0
> > > > Looking for 'pinctrl' at 1700, name iomuxc@20e
> > > >- gpio0, /soc/aips-bus@200/gpio@209c000
> > > >- mmc0, /soc/aips-bus@210/usdhc@219
> > > >- mmc1, /soc/aips-bus@210/usdhc@2194000
> > > >- serial0, /soc/aips-bus@200/spba-bus@200/serial@202
> > > > Not found
> > > > fdtdec_get_int_array: ranges
> > > > get_prop_check_min_len: ranges
> > > > Looking for 'mmc' at 2940, name usdhc@219
> > > >- gpio0, /soc/aips-bus@200/gpio@209c000
> > > >- mmc0, /soc/aips-bus@210/usdhc@219
> > > > Found seq 0
> > > > Looking for 'mmc' at 3200, name usdhc@2194000
> > > >- gpio0, /soc/aips-bus@200/gpio@209c000
> > > >- mmc0, /soc/aips-bus@210/usdhc@219
> > > >- mmc1, /soc/aips-bus@210/usdhc@2194000
> > > > Found seq 1
> > > > Trying to boot from USB SDP
> > > > SDP: initialize...
> > > > SDP: handle requests...
> > > > Downloading file of size 613070 to 0x177fffc0... done
> > > > Jumping to header at 0x177fffc0
> > > > Header Tag is not an IMX image
> > > >
> > > > What's interesting is that when looking for gpio and the two various
> > > > mmc's, the above function returns 'Found seq x' in SPL whereas the
> > > > pinctrl returns 'Not found'
> > >
> > > Okay, most likely your pinctrl driver is not ready yet.
> > > Your driver does not enables DM_FLAG_PRE_RELOC.
> > >
> > > 52 #if !CONFIG_IS_ENABLED(OF_CONTROL)
> > > 53 .flags = DM_FLAG_PRE_RELOC,
> > > 54 #endif
> > >
> > >
> > > Can you enable it and try again?
> >
> > I tried forcing the DM_FLAG_PRE_RELOC and I tried making various nodes
> > in the device tree u-boot,dm-pre-reloc instead of just u-boot,dm-spl;
> >
> > Either way I still can't get it to load.
> >
> > U-Boot SPL 2019.04-rc2-03218-gace08a038c-dirty (Feb 20 2019 - 11:30:08
> > -0600)
> >
Re: [U-Boot] [PATCH 2/6] fdtdec: Implement fdtdec_get_max_phandle()
Hi Thierry, On Fri, 8 Mar 2019 at 13:11, Thierry Reding wrote: > > From: Thierry Reding > > This function allows looking up the highest phandle value stored in a > device tree, which is useful to determine the next best phandle value > for new nodes. > > Signed-off-by: Thierry Reding > --- > include/fdtdec.h | 12 > lib/fdtdec.c | 28 > 2 files changed, 40 insertions(+) Can we use fdt_get_max_phandle() instead? If not, could you please add a bit more detail to the commit message as we might consider changing the upstream function. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] x86: Add a dtsi file for the pc speaker
On Tue, 26 Feb 2019 at 02:47, Bin Meng wrote: > > The pc speaker driven by the i8254 is generic enough to deserve > a single dtsi file to be included by boards that use it. > > Signed-off-by: Bin Meng > --- > > arch/x86/dts/pcspkr.dtsi | 5 + > 1 file changed, 5 insertions(+) > create mode 100644 arch/x86/dts/pcspkr.dtsi Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 05/13] clk: Use clk_get_by_index_tail()
On Wed, 27 Feb 2019 at 11:57, Jagan Teki wrote: > > clk_get_by_index_tail() now handle common clk get by index > code so use it from clk_get_by_indexed_prop(). > > Cc: Stephen Warren > Cc: Simon Glass > Signed-off-by: Jagan Teki > --- > Changes for v3: > - use clk_get_by_index_tail() from clk_get_by_indexed_prop() > > drivers/clk/clk-uclass.c | 24 ++-- > 1 file changed, 2 insertions(+), 22 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] dm: pinctrl: Skip gpio-controller node in pinconfig_post_bind()
On Mon, 25 Feb 2019 at 05:40, Patrice Chotard wrote: > > From: Patrick Delaunay > > Some binding define child node gpio-controller without compatible property. > This patch avoid to bind the pinconfig uclass to these node. > > For example, the binding for st,stm32-pinctrl > (./device-tree-bindings/pinctrl/st,stm32-pinctrl.txt) defines the GPIO > controller/bank node as sub-node of pincontrol (st,stm32f429-pinctrl) > but without compatible (as it is not mandatory). > > Signed-off-by: Patrick Delaunay > Signed-off-by: Patrice Chotard > --- > > Changes in v2: > - Update commit message with explanaition > > drivers/pinctrl/pinctrl-uclass.c | 3 +++ > 1 file changed, 3 insertions(+) > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] fdtdec: Add cpu_to_fdt_{addr, size}() macros
On Fri, 8 Mar 2019 at 13:11, Thierry Reding wrote: > > From: Thierry Reding > > These macros are useful for converting the endianness of variables of > type fdt_addr_t and fdt_size_t. > > Signed-off-by: Thierry Reding > --- > include/fdtdec.h | 4 > 1 file changed, 4 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ut dm pch sandbox test failures
On Tue, 26 Feb 2019 at 14:09, Tom Rini wrote: > > On Tue, Feb 26, 2019 at 12:21:53PM -0700, Stephen Warren wrote: > > On 2/25/19 4:49 PM, Stephen Warren wrote: > > >On 2/21/19 4:45 PM, Stephen Warren wrote: > > >>With the latest push to u-boot.git master branch, I'm seeing the > > >>following failures running test/py on sandbox: > > >> > > >>=> ut dm pch_base > > >>Test: dm_test_pch_base: pch.c > > >>/var/lib/jenkins/workspace/u-boot-denx_uboot-master-build/src/u-boot/test/dm/pch.c:20, > > >>dm_test_pch_base(): 0 == uclass_first_device_err(UCLASS_PCH, ): > > >>Expected 0, got -19 > > >>Test: dm_test_pch_base: pch.c (flat tree) > > >>/var/lib/jenkins/workspace/u-boot-denx_uboot-master-build/src/u-boot/test/dm/pch.c:20, > > >>dm_test_pch_base(): 0 == uclass_first_device_err(UCLASS_PCH, ): > > >>Expected 0, got -19 > > >>Failures: 2 > > >> > > >>=> ut dm pch_ioctl > > >>Test: dm_test_pch_ioctl: pch.c > > >>/var/lib/jenkins/workspace/u-boot-denx_uboot-master-build/src/u-boot/test/dm/pch.c:44, > > >>dm_test_pch_ioctl(): 0 == uclass_first_device_err(UCLASS_PCH, ): > > >>Expected 0, got -19 > > >>Test: dm_test_pch_ioctl: pch.c (flat tree) > > >>/var/lib/jenkins/workspace/u-boot-denx_uboot-master-build/src/u-boot/test/dm/pch.c:44, > > >>dm_test_pch_ioctl(): 0 == uclass_first_device_err(UCLASS_PCH, ): > > >>Expected 0, got -19 > > >>Failures: 2 > > > > > >This is some kind of incremental build problem; I deleted the build > > >results and retriggered Jenkins and everything worked fine. The exact same > > >issue and solution appeared and worked in two separate branches that I > > >test (u-boot.git master, u-boot-video.git master). Subsequently I found > > >that the following works fine: > > > > > >rm -rf build-sandbox/ > > >git checkout 888f9aa5cac4 > > >./test/py/test.py --bd sandbox --build -k test_ut > > > > > >But the following reproduces the problem: > > > > > >rm -rf build-sandbox/ > > >git checkout 97f9830849c6 > > >./test/py/test.py --bd sandbox --build -k test_ut > > >git checkout 888f9aa5cac4 > > >./test/py/test.py --bd sandbox --build -k test_ut > > > > I just sent "[PATCH 1/2] kbuild: make arch-dtbs target PHONY" to fix this. > > Thanks for figuring this out! Yes thank you Stephen. I have hit that on and off and have not looked at it. Rgards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2,11/23] spl: Add a comment to spl_set_bd()
Hi Simon,
On Wed, 20 Feb 2019 at 22:44, Simon Goldschmidt
wrote:
>
>
>
> Am Do., 21. Feb. 2019, 03:48 hat Simon Glass geschrieben:
>>
>> Hi Simon,
>>
>> On Mon, 11 Feb 2019 at 14:00, Simon Goldschmidt
>> wrote:
>> >
>> > Am 09.11.2018 um 19:43 schrieb Tom Rini:
>> > > On Tue, Oct 02, 2018 at 05:22:41AM -0600, Simon Glass wrote:
>> > >
>> > >> There is a strange feature to set global_data to a data-section variable
>> > >> early in SPL. This only works if SPL actually has access to SRAM which
>> > >> is
>> > >> not the case on x86, for eaxmple. Add a comment to this effect.
>> >
>> > Seems like I missed that one back in October.
>> >
>> > Does anyone have an idea why this variable ('static bd_t bdata') is
>> > hard-coded into section ".data"? To me this seems pretty unportable...
>> >
>> > For example, for a specific feature on socfpga (warm reboot CRC check),
>> > I would prefer to have the ".data" section empty and put 'bdata' into
>> > bss. This is currently not possible.
>> >
>> > But before sending a patch that somehow changes this behaviour, I'd like
>> > to know why this variable is put into ".data" instead of ".bss"
>>
>> BSS normally appears after data and is not actually part of the
>> u-boot-spi.bin image. If the device tree is appended to SPL then it
>> overlaps with BSS. Thus accessing BSS overwrites the DT. There are two
>> features to get around that - one is to pad out the BSS space so that:
>>
>> cat u-boot-spl-nodtb.bin u-boot-spl.dtb >u-boot-spl.bin
>>
>> places the DT after BSS.
>>
>> The other is to specify an address (typically in SDRAM) for BSS, so
>> that it is completely separate from the image.
>>
>> Note also that BSS is not always available in SPL. For example if SPL
>> is running from flash then the BSS may be mapped either to SDRAM
>> (which is not set up until later in SPL) or flash (which is not
>> writable at all). Of course the data section has the same problem.
>
>
> Ok, thanks for the insight.
>
>> Putting gd in the data section avoids one of the above problems.
>
>
> Actually it's bd here, not gd, so it's a little less widely used.
>
> And while I can follow your explanation, it convinces me even more that this
> should be configurable, not hadcoded. It wastes space in SPL binary and may
> not even work on some platforms...
Yes my comments were on gd, sorry about that.
Ideally it would default to something safe (i.e. not being in BSS or
data). The best things is probably to malloc() it, assuming that this
is enabled in SPL.
Regards,
Simon
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Re: [U-Boot] [PATCH v3 7/7] env: am57xx: Implement A/B boot process
On Mon, 18 Feb 2019 at 09:22, Igor Opaniuk wrote: > > From: Ruslan Trofymenko > > Add support for A/B boot process on AM57xx based boards: > > 1. Define 'slot_suffix' variable (using 'ab_select' command) > 2. Extend 'emmc_android_boot' boot command (add commands for A/B boot > process) > > 'ab_select' command is used to decide which slot should be used for > booting up. A/B metadata resides in 'misc' partition. > > To activate the A/B boot process, the following config options must be > set: > > CONFIG_ANDROID_AB=y > CONFIG_CMD_AB_SELECT=y > > For successful A/B boot, the corresponding A/B infrastructure must be > involved on Android side [1] (including mounting system as root), and > disk must be partitioned accordingly. > > When A/B boot is enabled, there are some known limitations currently > exist (not related to A/B patches, need to be implemented later): > > 1. The 'Verified Boot' sequence is not supported > 2. dev path to system partition (system_a or system_b) is passed via > 'bootargs' as 'root=' argument like 'root=/dev/mmcblk1p12', but > further we'll need to rework it with respect to dm-verity > requirements [2] > > In case when A/B partitions are not present in system (and A/B boot is > enabled), boot up process will be terminated and next message will be > shown: > > "boot_a(b) partition not found" > > [1] https://source.android.com/devices/tech/ota/ab > [2] https://source.android.com/devices/tech/ota/ab/ab_implement#kernel > > Signed-off-by: Ruslan Trofymenko > Signed-off-by: Igor Opaniuk > Reviewed-by: Alistair Strachan > Reviewed-by: Sam Protsenko > --- > > Changes in v3: None > > Changes in v2: > * Add changes related to command renaming (android_ab_select -> ab_select). > * Slotted sections (e.g. system_a and system_b) are added to the > default sections if CONFIG_CMD_AB_SELECT flag is defined > * Rebased on top of master > * system partitions sizes increased to 1024 MiB (to be consistent with > recent changes to boot.h file) > > include/environment/ti/boot.h | 58 > ++- > 1 file changed, 52 insertions(+), 6 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/7] cmd: Add 'ab_select' command
On Mon, 18 Feb 2019 at 09:22, Igor Opaniuk wrote: > > From: Ruslan Trofymenko > > For A/B system update support the Android boot process requires to send > 'androidboot.slot_suffix' parameter as a command line argument. This > patch implementes 'ab_select' command which allows us to obtain current > slot by processing the A/B metadata. > > The patch was extracted from commit [1] with one modification: the > separator for specifying the name of metadata partition was changed > from ';' to '#', because ';' is used for commands separation. > > [1] > https://android-review.googlesource.com/c/platform/external/u-boot/+/729880/2 > > Signed-off-by: Ruslan Trofymenko > Signed-off-by: Igor Opaniuk > Reviewed-by: Alistair Strachan > Reviewed-by: Sam Protsenko > --- > Changes in v3: None > Changes in v2: > * 'android_ab_select' command is renamed to 'ab_select' command > * command is moved to the separate 'Android support commands' menu > > cmd/Kconfig | 15 +++ > cmd/Makefile| 1 + > cmd/ab_select.c | 52 > 3 files changed, 68 insertions(+) > create mode 100644 cmd/ab_select.c Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/7] common: Implement A/B metadata
Hi Igor,
On Mon, 18 Feb 2019 at 10:22, Igor Opaniuk wrote:
>
> From: Ruslan Trofymenko
>
> This patch determines the A/B-specific bootloader message structure
> that is the basis for implementation of recovery and A/B update
> functions. A/B metadata is stored in this structure and used to decide
> which slot should we use to boot the device. Also some basic functions
> for A/B metadata manipulation are implemented (like slot selection).
>
> The patch was extracted from commits [1], [2] with some coding style
> fixes.
>
> [1]
> https://android-review.googlesource.com/c/platform/external/u-boot/+/729878/2
> [2]
> https://android-review.googlesource.com/c/platform/external/u-boot/+/729880/2
>
> Signed-off-by: Ruslan Trofymenko
> Signed-off-by: Igor Opaniuk
> Reviewed-by: Sam Protsenko
> ---
>
> Changes in v3:
> * Add multiple sanity checks
> * Fix mix. minor code formatting issues
>
> Changes in v2:
> * Function return codes are clarified
> * Some types and constants are renamed (for compactness)
> * android_bootloader_message.h is renamed to android_bl_msg.h
> * 'debug' calls are changed to 'log_debug'
> * Order of headers is changed
> * android_bl_msg.h was synced with AOSP master counterpart
>
> common/Kconfig | 10 ++
> common/Makefile | 1 +
> common/android_ab.c | 290
> +++
> include/android_ab.h | 34 ++
> include/android_bl_msg.h | 169 +++
> 5 files changed, 504 insertions(+)
> create mode 100644 common/android_ab.c
> create mode 100644 include/android_ab.h
> create mode 100644 include/android_bl_msg.h
>
Reviewed-by: Simon Glass
Minor comments below, could be addressed later.
> diff --git a/common/Kconfig b/common/Kconfig
> index 0a14bde..fc08e31 100644
> --- a/common/Kconfig
> +++ b/common/Kconfig
> @@ -767,6 +767,16 @@ config UPDATE_TFTP_MSEC_MAX
> default 100
> depends on UPDATE_TFTP
>
> +config ANDROID_AB
> + bool "Android A/B updates"
> + default n
> + help
> + If enabled, adds support for the new Android A/B update model. This
> + allows the bootloader to select which slot to boot from based on the
> + information provided by userspace via the Android boot_ctrl HAL.
> This
> + allows a bootloader to try a new version of the system but roll back
> + to previous version if the new one didn't boot all the way.
> +
> endmenu
>
> menu "Blob list"
> diff --git a/common/Makefile b/common/Makefile
> index ad390d0..dfa348c 100644
> --- a/common/Makefile
> +++ b/common/Makefile
> @@ -106,6 +106,7 @@ endif
> endif
>
> obj-y += image.o
> +obj-$(CONFIG_ANDROID_AB) += android_ab.o
> obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
> obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
> obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
> diff --git a/common/android_ab.c b/common/android_ab.c
> new file mode 100644
> index 000..3a6a52c
> --- /dev/null
> +++ b/common/android_ab.c
> @@ -0,0 +1,290 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (C) 2017 The Android Open Source Project
> + */
> +
> +#include
> +#include
> +#include
Please put common.h first.
> +#include
> +#include
> +
> +/**
> + * Compute the CRC-32 of the bootloader control struct.
> + *
> + * Only the bytes up to the crc32_le field are considered for the CRC-32
> + * calculation.
For function comments please add @abc for arg and @return for return
value in every case.
> + */
> +static uint32_t ab_control_compute_crc(struct andr_bl_control *abc)
> +{
> + return crc32(0, (void *)abc, offsetof(typeof(*abc), crc32_le));
> +}
> +
> +/**
> + * Initialize andr_bl_control to the default value.
> + *
> + * It allows us to boot all slots in order from the first one. This value
> + * should be used when the bootloader message is corrupted, but not when
> + * a valid message indicates that all slots are unbootable.
> + */
> +static int ab_control_default(struct andr_bl_control *abc)
> +{
> + int i;
> + const struct andr_slot_metadata metadata = {
> + .priority = 15,
> + .tries_remaining = 7,
> + .successful_boot = 0,
> + .verity_corrupted = 0,
> + .reserved = 0
> + };
> +
> + if (!abc)
> + return -EINVAL;
-EFAULT?
Also, does this actually happen>
> +
> + memcpy(abc->slot_suffix, "a\0\0\0", 4);
> + abc->magic = ANDROID_BOOT_CTRL_MAGIC;
> + abc->version = ANDROID_BOOT_CTRL_VERSION;
> + abc->nb_slot = ANDROID_NUM_SLOTS;
> + memset(abc->reserved0, 0, sizeof(abc->reserved0));
> + for (i = 0; i < abc->nb_slot; ++i)
> + abc->slot_info[i] = metadata;
> +
> + memset(abc->reserved1, 0, sizeof(abc->reserved1));
> + abc->crc32_le = ab_control_compute_crc(abc);
> +
> + return 0;
> +}
> +
> +/**
> + * Load the boot_control struct from disk
Re: [U-Boot] [PATCH 5/7] riscv: add support for multi-hart systems
> -Original Message- > From: U-Boot On Behalf Of Auer, Lukas > Sent: Sunday, March 10, 2019 11:42 PM > To: a...@brainfault.org > Cc: rickche...@gmail.com; bar...@tkos.co.il; s...@denx.de; > cmc...@andestech.com; greent...@andestech.com; sch...@suse.de; > pal...@sifive.com; ag...@suse.de; u-boot@lists.denx.de; > k...@andestech.com > Subject: Re: [U-Boot] [PATCH 5/7] riscv: add support for multi-hart systems > > On Sun, 2019-03-10 at 20:24 +0530, Anup Patel wrote: > > On Sun, Mar 10, 2019 at 7:28 PM Auer, Lukas > > wrote: > > > Hi Rick, > > > > > > On Thu, 2019-03-07 at 17:30 +0800, Rick Chen wrote: > > > > Hi Lukas > > > > > > > > > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de] > > > > > > Sent: Tuesday, February 12, 2019 6:14 AM > > > > > > To: u-boot@lists.denx.de > > > > > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer > > > > > > Dabbelt; Alexander Graf; Lukas Auer; Anup Patel; Rick Jian-Zhi > > > > > > Chen(陳建志); > > > > > > Baruch Siach; > > > > > > Stefan Roese > > > > > > Subject: [PATCH 5/7] riscv: add support for multi-hart systems > > > > > > > > > > > > On RISC-V, all harts boot independently. To be able to run on > > > > > > a multi-hart system, U-Boot must be extended with the > > > > > > functionality to manage all harts in the system. A new config > > > > > > option, CONFIG_MAIN_HART, is used to select the hart U-Boot > > > > > > runs on. All other harts are halted. > > > > > > U-Boot can delegate functions to them using > > > > > > smp_call_function(). > > > > > > > > > > > > Every hart has a valid pointer to the global data structure > > > > > > and a 8KiB stack by default. The stack size is set with > > > > > > CONFIG_STACK_SIZE_SHIFT. > > > > > > > > > > > > Signed-off-by: Lukas Auer > > > > > > --- > > > > > > > > > > > > arch/riscv/Kconfig | 12 + > > > > > > arch/riscv/cpu/start.S | 102 > > > > > > ++- > > > > > > arch/riscv/include/asm/csr.h | 1 + > > > > > > 3 files changed, 114 insertions(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index > > > > > > 3a51339c4d..af8d0f8d67 > > > > > > 100644 > > > > > > --- a/arch/riscv/Kconfig > > > > > > +++ b/arch/riscv/Kconfig > > > > > > @@ -140,4 +140,16 @@ config SBI_IPI > > > > > > default y if RISCV_SMODE > > > > > > depends on SMP > > > > > > > > > > > > +config MAIN_HART > > > > > > + int "Main hart in system" > > > > > > + default 0 > > > > > > + help > > > > > > + Some SoCs include harts of various sizes, some of > > > > > > which > > > > > > might not > > > > > > + be suitable for running U-Boot. CONFIG_MAIN_HART is > > > > > > used > > > > > > to select > > > > > > + the hart U-Boot runs on. > > > > > > + > > > > > > +config STACK_SIZE_SHIFT > > > > > > + int > > > > > > + default 13 > > > > > > + > > > > > > endmenu > > > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > > > > > index > > > > > > a30f6f7194..ce7230df37 100644 > > > > > > --- a/arch/riscv/cpu/start.S > > > > > > +++ b/arch/riscv/cpu/start.S > > > > > > @@ -13,6 +13,7 @@ > > > > > > #include > > > > > > #include > > > > > > #include > > > > > > +#include > > > > > > #include > > > > > > #include > > > > > > > > > > > > @@ -45,6 +46,23 @@ _start: > > > > > > /* mask all interrupts */ > > > > > > csrwMODE_PREFIX(ie), zero > > > > > > > > > > > > +#ifdef CONFIG_SMP > > > > > > + /* check if hart is within range */ > > > > > > + /* s0: hart id */ > > > > > > + li t0, CONFIG_NR_CPUS > > > > > > + bge s0, t0, hart_out_of_bounds_loop > > > > > > +#endif > > > > > > + > > > > > > +#ifdef CONFIG_SMP > > > > > > + /* set xSIE bit to receive IPIs */ #ifdef > > > > > > +CONFIG_RISCV_MMODE > > > > > > + li t0, MIE_MSIE > > > > > > +#else > > > > > > + li t0, SIE_SSIE > > > > > > +#endif > > > > > > + csrsMODE_PREFIX(ie), t0 > > > > > > +#endif > > > > > > + > > > > > > /* > > > > > > * Set stackpointer in internal/ex RAM to call board_init_f > > > > > > */ > > > > > > @@ -56,7 +74,25 @@ call_board_init_f: > > > > > > call_board_init_f_0: > > > > > > mv a0, sp > > > > > > jal board_init_f_alloc_reserve > > > > > > + > > > > > > + /* > > > > > > + * Set global data pointer here for all harts, > > > > > > uninitialized at this > > > > > > + * point. > > > > > > + */ > > > > > > + mv gp, a0 > > > > > > + > > > > > > + /* setup stack */ > > > > > > +#ifdef CONFIG_SMP > > > > > > + /* s0: hart id */ > > > > > > + sllit0, s0, CONFIG_STACK_SIZE_SHIFT > > > > > > + sub sp, a0, t0 > > > > > > +#else > > > > > > mv sp, a0 > > > > > > +#endif > > > > > > + > > > > > > + /* Continue on main hart, others branch to > > > > > > secondary_hart_loop */ > > > > > > + li t0, CONFIG_MAIN_HART > > >
Re: [U-Boot] SUNXI : CONFIG_VIDEO_SUNXI is never set
> Op 7 mrt. 2019, om 09:04 heeft Chen-Yu Tsai het volgende > geschreven: > > On Fri, Mar 1, 2019 at 11:36 PM Arjan van Vught > wrote: >> >> Version: u-boot-2018.09 >> >> This is a follow-up for : "SUNXI : setenv video-mode not working" >> >> Although I have added CONFIG_VIDEO_SUNXI=y in configs/orangepi_one_defconfig >> >> the source file sunxi_display.c is not compiled. Hence the setenv >> video-mode is not working ? > > That file is only used for DE 1.0, while the H3, which the Orange Pi > One is based > on, has DE 2.0. Is it on the roadmap adding support for DE 2.0 ? - Arjan > > ChenYu > > >> >> Please advice. >> >> Many thanks in advance, Arjan >> >> http://www.orangepi-dmx.org/allwinner-h3 >> >> ___ >> U-Boot mailing list >> U-Boot@lists.denx.de >> https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] Revert "pico-imx7d: Add LCD support"
This reverts commit 9e3c0174da842dd88f5feaffbf843ba332233897.
This commit causes the crash of U-Boot when loaded with imx-usb-loader
---
board/technexion/pico-imx7d/pico-imx7d.c | 55
configs/pico-hobbit-imx7d_defconfig | 1 -
configs/pico-imx7d_defconfig | 1 -
configs/pico-pi-imx7d_defconfig | 1 -
include/configs/pico-imx7d.h | 12 ---
5 files changed, 70 deletions(-)
diff --git a/board/technexion/pico-imx7d/pico-imx7d.c
b/board/technexion/pico-imx7d/pico-imx7d.c
index 767d13d..53e1469 100644
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -39,16 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define I2C_PAD_CTRL(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
-
-#define LCD_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
-PAD_CTL_DSE_3P3V_49OHM)
-
-#define LCD_SYNC_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
- PAD_CTL_DSE_3P3V_196OHM)
-
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
/* I2C4 for PMIC */
static struct i2c_pads_info i2c_pad_info4 = {
.scl = {
@@ -254,58 +246,11 @@ int board_early_init_f(void)
return 0;
}
-#ifdef CONFIG_VIDEO_MXS
-static iomux_v3_cfg_t const lcd_pads[] = {
- MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
- MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
- MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
- MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-void setup_lcd(void)
-{
- imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
- /* Set Brightness to high */
- gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
- /* Set LCD enable to high */
- gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
-}
-#endif
-
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#ifdef CONFIG_VIDEO_MXS
- setup_lcd();
-#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
diff --git a/configs/pico-hobbit-imx7d_defconfig
b/configs/pico-hobbit-imx7d_defconfig
index f58d517..cb4a6bf 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index 7e13923..f90d757 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index c8ac2ff..8e48ba7 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
Re: [U-Boot] [RFC 0/9] Convert Pico-Pi i.MX7D to DM
Le 10/03/2019 à 15:24, Fabio Estevam a écrit : Hi Joris, On Sat, Mar 9, 2019 at 7:21 PM Offouga Joris wrote: Hi Fabio, I revert the commit about add lcd and on u-boot master and u-boot imx i have the u-boot is flashed correctly in usb and dfu. do you agree that I send the revert of the commit? Yes, please revert it for now and resubmit your series that converts pico mx7 to DM. Ok, i send revert add lcd So the only issue now is the I2C errors? No, I have not solved the problem of the spl that can not find the u-boot-dtb.img in the emmc. I think the problem comes from the dfu_alt_info we already talked about it but the solution with raw u-boot 0x45 800 does not work do you have another idea? Thanks, Joris Offouga Thanks, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7] riscv: add support for multi-hart systems
On Sun, 2019-03-10 at 20:24 +0530, Anup Patel wrote: > On Sun, Mar 10, 2019 at 7:28 PM Auer, Lukas > wrote: > > Hi Rick, > > > > On Thu, 2019-03-07 at 17:30 +0800, Rick Chen wrote: > > > Hi Lukas > > > > > > > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de] > > > > > Sent: Tuesday, February 12, 2019 6:14 AM > > > > > To: u-boot@lists.denx.de > > > > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer > > > > > Dabbelt; > > > > > Alexander Graf; Lukas Auer; Anup Patel; Rick Jian-Zhi > > > > > Chen(陳建志); > > > > > Baruch Siach; > > > > > Stefan Roese > > > > > Subject: [PATCH 5/7] riscv: add support for multi-hart > > > > > systems > > > > > > > > > > On RISC-V, all harts boot independently. To be able to run on > > > > > a > > > > > multi-hart system, > > > > > U-Boot must be extended with the functionality to manage all > > > > > harts in the > > > > > system. A new config option, CONFIG_MAIN_HART, is used to > > > > > select > > > > > the hart > > > > > U-Boot runs on. All other harts are halted. > > > > > U-Boot can delegate functions to them using > > > > > smp_call_function(). > > > > > > > > > > Every hart has a valid pointer to the global data structure > > > > > and a > > > > > 8KiB stack by > > > > > default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. > > > > > > > > > > Signed-off-by: Lukas Auer > > > > > --- > > > > > > > > > > arch/riscv/Kconfig | 12 + > > > > > arch/riscv/cpu/start.S | 102 > > > > > ++- > > > > > arch/riscv/include/asm/csr.h | 1 + > > > > > 3 files changed, 114 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index > > > > > 3a51339c4d..af8d0f8d67 > > > > > 100644 > > > > > --- a/arch/riscv/Kconfig > > > > > +++ b/arch/riscv/Kconfig > > > > > @@ -140,4 +140,16 @@ config SBI_IPI > > > > > default y if RISCV_SMODE > > > > > depends on SMP > > > > > > > > > > +config MAIN_HART > > > > > + int "Main hart in system" > > > > > + default 0 > > > > > + help > > > > > + Some SoCs include harts of various sizes, some of > > > > > which > > > > > might not > > > > > + be suitable for running U-Boot. CONFIG_MAIN_HART is > > > > > used > > > > > to select > > > > > + the hart U-Boot runs on. > > > > > + > > > > > +config STACK_SIZE_SHIFT > > > > > + int > > > > > + default 13 > > > > > + > > > > > endmenu > > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > > > > index > > > > > a30f6f7194..ce7230df37 100644 > > > > > --- a/arch/riscv/cpu/start.S > > > > > +++ b/arch/riscv/cpu/start.S > > > > > @@ -13,6 +13,7 @@ > > > > > #include > > > > > #include > > > > > #include > > > > > +#include > > > > > #include > > > > > #include > > > > > > > > > > @@ -45,6 +46,23 @@ _start: > > > > > /* mask all interrupts */ > > > > > csrwMODE_PREFIX(ie), zero > > > > > > > > > > +#ifdef CONFIG_SMP > > > > > + /* check if hart is within range */ > > > > > + /* s0: hart id */ > > > > > + li t0, CONFIG_NR_CPUS > > > > > + bge s0, t0, hart_out_of_bounds_loop > > > > > +#endif > > > > > + > > > > > +#ifdef CONFIG_SMP > > > > > + /* set xSIE bit to receive IPIs */ > > > > > +#ifdef CONFIG_RISCV_MMODE > > > > > + li t0, MIE_MSIE > > > > > +#else > > > > > + li t0, SIE_SSIE > > > > > +#endif > > > > > + csrsMODE_PREFIX(ie), t0 > > > > > +#endif > > > > > + > > > > > /* > > > > > * Set stackpointer in internal/ex RAM to call board_init_f > > > > > */ > > > > > @@ -56,7 +74,25 @@ call_board_init_f: > > > > > call_board_init_f_0: > > > > > mv a0, sp > > > > > jal board_init_f_alloc_reserve > > > > > + > > > > > + /* > > > > > + * Set global data pointer here for all harts, > > > > > uninitialized at this > > > > > + * point. > > > > > + */ > > > > > + mv gp, a0 > > > > > + > > > > > + /* setup stack */ > > > > > +#ifdef CONFIG_SMP > > > > > + /* s0: hart id */ > > > > > + sllit0, s0, CONFIG_STACK_SIZE_SHIFT > > > > > + sub sp, a0, t0 > > > > > +#else > > > > > mv sp, a0 > > > > > +#endif > > > > > + > > > > > + /* Continue on main hart, others branch to > > > > > secondary_hart_loop */ > > > > > + li t0, CONFIG_MAIN_HART > > > > > + bne s0, t0, secondary_hart_loop > > > > > > > > > > la t0, prior_stage_fdt_address > > > > > SREGs1, 0(t0) > > > > > @@ -95,7 +131,14 @@ relocate_code: > > > > > *Set up the stack > > > > > */ > > > > > stack_setup: > > > > > +#ifdef CONFIG_SMP > > > > > + /* s0: hart id */ > > > > > + sllit0, s0, CONFIG_STACK_SIZE_SHIFT > > > > > + sub sp, s2, t0 > > > > > +#else > > > > > mv sp, s2 > > > > > +#endif > > > > > + > > > > > la t0, _start > > > > > sub t6, s4, t0 /* t6 <- relocation > >
Re: [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model
Hi Jagan,
thanks for your comments,
On Fri, Mar 08, 2019 at 11:30:56AM +0530, Jagan Teki wrote:
> On Mon, Dec 17, 2018 at 1:06 AM Angelo Dureghello wrote:
> >
> > Converting to driver model and removes non-dm code.
> >
> > Reviewed-by: Simon Glass
> > Signed-off-by: Angelo Dureghello
> > ---
> > Changes for v2:
> > - removed non DM code part
> > - add default setup of CTAR registers
> > - add DT CTAR register setup support
> > Changes for v3:
> > - changed commit head
> > - removed spi_slave reference
> > - add #ifdefs for the case OF_PLATDATA is used
> > Changes for v4:
> > - remove all internal static functions that are no more needed including
> > their code in the standard driver methods
> > - add helper macro for ctrl setup
> > - fix wrong fifo level check on spi tx
> > - move code inside same #if (avoid multiple #if on same option)
> > - removed externals and moved bus control code here
> > ---
> > drivers/spi/cf_spi.c| 539
> > include/dm/platform_data/spi_coldfire.h | 29 ++
> > 2 files changed, 401 insertions(+), 167 deletions(-)
> > create mode 100644 include/dm/platform_data/spi_coldfire.h
> >
> > diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
> > index 522631cbbf..3d02c87637 100644
> > --- a/drivers/spi/cf_spi.c
> > +++ b/drivers/spi/cf_spi.c
> > @@ -6,23 +6,31 @@
> > *
> > * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
> > * TsiChung Liew (tsi-chung.l...@freescale.com)
> > + *
> > + * Support for DM and DT, non-DM code removed.
> > + * Copyright (C) 2018 Angelo Dureghello
> > + *
> > + * TODO: fsl_dspi.c should work as a driver for the DSPI module.
> > */
> >
> > #include
> > +#include
> > +#include
> > #include
> > #include
> > +#include
> > +#include
> > #include
> > +#include
> >
> > -struct cf_spi_slave {
> > - struct spi_slave slave;
> > +struct coldfire_spi_priv {
> > + struct dspi *regs;
> > + struct gpio *gpio_regs;
> > uint baudrate;
> > + int mode;
> > int charbit;
> > };
> >
> > -extern void cfspi_port_conf(void);
> > -extern int cfspi_claim_bus(uint bus, uint cs);
> > -extern void cfspi_release_bus(uint bus, uint cs);
> > -
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > #ifndef CONFIG_SPI_IDLE_VAL
> > @@ -33,149 +41,267 @@ DECLARE_GLOBAL_DATA_PTR;
> > #endif
> > #endif
> >
> > -#if defined(CONFIG_CF_DSPI)
> > /* DSPI specific mode */
> > #define SPI_MODE_MOD 0x0020
> > #define SPI_DBLRATE0x0010
> >
> > -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
> > +#define MCF_DSPI_MAX_CTAR_REGS 8
> > +
> > +/* Default values */
> > +#define MCF_DSPI_DEFAULT_SCK_FREQ 1000
> > +#define MCF_DSPI_DEFAULT_MAX_CS4
> > +#define MCF_DSPI_DEFAULT_MODE 0
> > +
> > +#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
> > + DSPI_CTAR_PCSSCK_1CLK | \
> > + DSPI_CTAR_PASC(0) | \
> > + DSPI_CTAR_PDT(0) | \
> > + DSPI_CTAR_CSSCK(0) | \
> > + DSPI_CTAR_ASC(0) | \
> > + DSPI_CTAR_DT(1) | \
> > + DSPI_CTAR_BR(6))
> > +
> > +#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF00) | ((1 << cs) << 16))
> > +
> > +static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
> > + u32 ctrl, u16 data)
> > {
> > - return container_of(slave, struct cf_spi_slave, slave);
> > + /*
> > +* Need to check fifo level here
> > +*/
> > + while ((readl(>regs->sr) & 0xF000) >= 0x4000)
> > + ;
> > +
> > + writel(ctrl | data, >regs->tfr);
> > }
> >
> > -static void cfspi_init(void)
> > +static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
> > {
> > - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > -
> > - cfspi_port_conf(); /* port configuration */
> > + while ((readl(>regs->sr) & 0x00F0) == 0)
> > + ;
> >
> > - dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
> > - DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
> > - DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
> > - DSPI_MCR_CRXF | DSPI_MCR_CTXF;
> > + return readw(>regs->rfr);
> > +}
>
> Look like you include wait header and forgot to implement
> wait_for_bit_* logic which I commented before.
>
I tried to use it, this is why i forgot the header.
The fact is that wait_for_bit_* logic wait for one or more bit(s),
but cannot wait for one "of" more bit(s), as in the above case.
So seems cannot apply here.
> >
> > - /* Default setting in platform configuration */
> > -#ifdef CONFIG_SYS_DSPI_CTAR0
> > - dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR1
Re: [U-Boot] [U-Boot, RESEND, 1/3] ARM: dts: imx6ul-lite*: add DTS files for liteSOM and liteboard
sba...@denx.de writes: >> Import liteSOM and liteboard dts files from Linux v4.20. They will >> be used after transition to driver model and device-tree based boot. >> Signed-off-by: Marcin Niestroj > > Applied to u-boot-imx, master, thanks ! Thanks! What about patches 2 and 3? > > Best regards, > Stefano Babic -- Best regards, Marcin Niestrój ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7] riscv: add support for multi-hart systems
On Sun, Mar 10, 2019 at 7:28 PM Auer, Lukas wrote: > > Hi Rick, > > On Thu, 2019-03-07 at 17:30 +0800, Rick Chen wrote: > > Hi Lukas > > > > > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de] > > > > Sent: Tuesday, February 12, 2019 6:14 AM > > > > To: u-boot@lists.denx.de > > > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer > > > > Dabbelt; > > > > Alexander Graf; Lukas Auer; Anup Patel; Rick Jian-Zhi Chen(陳建志); > > > > Baruch Siach; > > > > Stefan Roese > > > > Subject: [PATCH 5/7] riscv: add support for multi-hart systems > > > > > > > > On RISC-V, all harts boot independently. To be able to run on a > > > > multi-hart system, > > > > U-Boot must be extended with the functionality to manage all > > > > harts in the > > > > system. A new config option, CONFIG_MAIN_HART, is used to select > > > > the hart > > > > U-Boot runs on. All other harts are halted. > > > > U-Boot can delegate functions to them using smp_call_function(). > > > > > > > > Every hart has a valid pointer to the global data structure and a > > > > 8KiB stack by > > > > default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. > > > > > > > > Signed-off-by: Lukas Auer > > > > --- > > > > > > > > arch/riscv/Kconfig | 12 + > > > > arch/riscv/cpu/start.S | 102 > > > > ++- > > > > arch/riscv/include/asm/csr.h | 1 + > > > > 3 files changed, 114 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index > > > > 3a51339c4d..af8d0f8d67 > > > > 100644 > > > > --- a/arch/riscv/Kconfig > > > > +++ b/arch/riscv/Kconfig > > > > @@ -140,4 +140,16 @@ config SBI_IPI > > > > default y if RISCV_SMODE > > > > depends on SMP > > > > > > > > +config MAIN_HART > > > > + int "Main hart in system" > > > > + default 0 > > > > + help > > > > + Some SoCs include harts of various sizes, some of which > > > > might not > > > > + be suitable for running U-Boot. CONFIG_MAIN_HART is used > > > > to select > > > > + the hart U-Boot runs on. > > > > + > > > > +config STACK_SIZE_SHIFT > > > > + int > > > > + default 13 > > > > + > > > > endmenu > > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > > > index > > > > a30f6f7194..ce7230df37 100644 > > > > --- a/arch/riscv/cpu/start.S > > > > +++ b/arch/riscv/cpu/start.S > > > > @@ -13,6 +13,7 @@ > > > > #include > > > > #include > > > > #include > > > > +#include > > > > #include > > > > #include > > > > > > > > @@ -45,6 +46,23 @@ _start: > > > > /* mask all interrupts */ > > > > csrwMODE_PREFIX(ie), zero > > > > > > > > +#ifdef CONFIG_SMP > > > > + /* check if hart is within range */ > > > > + /* s0: hart id */ > > > > + li t0, CONFIG_NR_CPUS > > > > + bge s0, t0, hart_out_of_bounds_loop > > > > +#endif > > > > + > > > > +#ifdef CONFIG_SMP > > > > + /* set xSIE bit to receive IPIs */ > > > > +#ifdef CONFIG_RISCV_MMODE > > > > + li t0, MIE_MSIE > > > > +#else > > > > + li t0, SIE_SSIE > > > > +#endif > > > > + csrsMODE_PREFIX(ie), t0 > > > > +#endif > > > > + > > > > /* > > > > * Set stackpointer in internal/ex RAM to call board_init_f > > > > */ > > > > @@ -56,7 +74,25 @@ call_board_init_f: > > > > call_board_init_f_0: > > > > mv a0, sp > > > > jal board_init_f_alloc_reserve > > > > + > > > > + /* > > > > + * Set global data pointer here for all harts, > > > > uninitialized at this > > > > + * point. > > > > + */ > > > > + mv gp, a0 > > > > + > > > > + /* setup stack */ > > > > +#ifdef CONFIG_SMP > > > > + /* s0: hart id */ > > > > + sllit0, s0, CONFIG_STACK_SIZE_SHIFT > > > > + sub sp, a0, t0 > > > > +#else > > > > mv sp, a0 > > > > +#endif > > > > + > > > > + /* Continue on main hart, others branch to > > > > secondary_hart_loop */ > > > > + li t0, CONFIG_MAIN_HART > > > > + bne s0, t0, secondary_hart_loop > > > > > > > > la t0, prior_stage_fdt_address > > > > SREGs1, 0(t0) > > > > @@ -95,7 +131,14 @@ relocate_code: > > > > *Set up the stack > > > > */ > > > > stack_setup: > > > > +#ifdef CONFIG_SMP > > > > + /* s0: hart id */ > > > > + sllit0, s0, CONFIG_STACK_SIZE_SHIFT > > > > + sub sp, s2, t0 > > > > +#else > > > > mv sp, s2 > > > > +#endif > > > > + > > > > la t0, _start > > > > sub t6, s4, t0 /* t6 <- relocation offset > > > > */ > > > > beq t0, s4, clear_bss /* skip relocation */ > > > > @@ -175,13 +218,30 @@ clear_bss: > > > > add t0, t0, t6 /* t0 <- rel __bss_start in > > > > RAM */ > > > > la t1, __bss_end /* t1 <- rel __bss_end in > > > > FLASH */ > > > > add t1, t1, t6 /* t1 <- rel __bss_end in > > > > RAM */ > > > > - beq t0, t1,
Re: [U-Boot] [PATCH v2 1/9] riscv: add infrastructure for calling functions on other harts
On Wed, 2019-03-06 at 19:20 -0800, Atish Patra wrote:
> On 3/5/19 2:54 PM, Lukas Auer wrote:
> > Harts on RISC-V boot independently, U-Boot is responsible for
> > managing
> > them. Functions are called on other harts with smp_call_function(),
> > which sends inter-processor interrupts (IPIs) to all other
> > available
> > harts. Available harts are those marked as available in the device
> > tree
> > and present in the available_harts mask stored in global data. The
> > available_harts mask is used to register all harts that have
> > entered
> > U-Boot. Functions are specified with their address and two function
> > arguments (argument 2 and 3). The first function argument is always
> > the
> > hart ID of the hart calling the function. On the other harts, the
> > IPI
> > interrupt handler handle_ipi() must be called on software
> > interrupts to
> > handle the request and call the specified function.
> >
> > Functions are stored in the ipi_data data structure. Every hart has
> > its
> > own data structure in global data. While this is not required at
> > the
> > moment (all harts are expected to boot Linux), this does allow
> > future
> > expansion, where other harts may be used for monitoring or other
> > tasks.
> >
> > Signed-off-by: Lukas Auer
> > ---
> >
> > Changes in v2:
> > - Remove unneeded quotes from NR_CPUS Kconfig entry
> > - Move memory barrier from send_ipi_many() to handle_ipi()
> > - Add check in send_ipi_many so that IPIs are only sent to
> > available
> > harts as indicated by the available_harts mask
> >
> > arch/riscv/Kconfig | 19 +
> > arch/riscv/include/asm/global_data.h | 6 ++
> > arch/riscv/include/asm/smp.h | 53
> > arch/riscv/lib/Makefile | 1 +
> > arch/riscv/lib/smp.c | 116
> > +++
> > 5 files changed, 195 insertions(+)
> > create mode 100644 arch/riscv/include/asm/smp.h
> > create mode 100644 arch/riscv/lib/smp.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 36512a8995..4d7a115569 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -120,4 +120,23 @@ config RISCV_RDTIME
> > config SYS_MALLOC_F_LEN
> > default 0x1000
> >
> > +config SMP
> > + bool "Symmetric Multi-Processing"
> > + help
> > + This enables support for systems with more than one CPU. If
> > + you say N here, U-Boot will run on single and multiprocessor
> > + machines, but will use only one CPU of a multiprocessor
> > + machine. If you say Y here, U-Boot will run on many, but not
> > + all, single processor machines.
> > +
> > +config NR_CPUS
> > + int "Maximum number of CPUs (2-32)"
> > + range 2 32
> > + depends on SMP
> > + default 8
> > + help
> > + On multiprocessor machines, U-Boot sets up a stack for each
> > CPU.
> > + Stack memory is pre-allocated. U-Boot must therefore know the
> > + maximum number of CPUs that may be present.
> > +
> > endmenu
> > diff --git a/arch/riscv/include/asm/global_data.h
> > b/arch/riscv/include/asm/global_data.h
> > index a3a342c6e1..80e3165e39 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -10,12 +10,18 @@
> > #ifndef __ASM_GBL_DATA_H
> > #define __ASM_GBL_DATA_H
> >
> > +#include
> > +
> > /* Architecture-specific global data */
> > struct arch_global_data {
> > long boot_hart; /* boot hart id */
> > #ifdef CONFIG_SIFIVE_CLINT
> > void __iomem *clint;/* clint base address */
> > #endif
> > +#ifdef CONFIG_SMP
> > + struct ipi_data ipi[CONFIG_NR_CPUS];
> > +#endif
> > + ulong available_harts;
> > };
> >
> > #include
> > diff --git a/arch/riscv/include/asm/smp.h
> > b/arch/riscv/include/asm/smp.h
> > new file mode 100644
> > index 00..bc863fdbaf
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/smp.h
> > @@ -0,0 +1,53 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2019 Fraunhofer AISEC,
> > + * Lukas Auer
> > + */
> > +
> > +#ifndef _ASM_RISCV_SMP_H
> > +#define _ASM_RISCV_SMP_H
> > +
> > +/**
> > + * struct ipi_data - Inter-processor interrupt (IPI) data
> > structure
> > + *
> > + * IPIs are used for SMP support to communicate to other harts
> > what function to
> > + * call. Functions are in the form
> > + * void (*addr)(ulong hart, ulong arg0, ulong arg1).
> > + *
> > + * The function address and the two arguments, arg0 and arg1, are
> > stored in the
> > + * IPI data structure. The hart ID is inserted by the hart
> > handling the IPI and
> > + * calling the function.
> > + *
> > + * @addr: Address of function
> > + * @arg0: First argument of function
> > + * @arg1: Second argument of function
> > + */
> > +struct ipi_data {
> > + ulong addr;
> > + ulong arg0;
> > + ulong arg1;
> > +};
> > +
> > +/**
> > + * handle_ipi() - interrupt handler for software interrupts
> > + *
> > + * The IPI interrupt
Re: [U-Boot] [RFC 0/9] Convert Pico-Pi i.MX7D to DM
Hi Joris, On Sat, Mar 9, 2019 at 7:21 PM Offouga Joris wrote: > Hi Fabio, > > I revert the commit about add lcd and on u-boot master and u-boot imx i have > the u-boot is flashed correctly in usb and dfu. > > do you agree that I send the revert of the commit? Yes, please revert it for now and resubmit your series that converts pico mx7 to DM. So the only issue now is the I2C errors? Thanks, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7] riscv: add support for multi-hart systems
Hi Rick, On Thu, 2019-03-07 at 17:30 +0800, Rick Chen wrote: > Hi Lukas > > > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de] > > > Sent: Tuesday, February 12, 2019 6:14 AM > > > To: u-boot@lists.denx.de > > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer > > > Dabbelt; > > > Alexander Graf; Lukas Auer; Anup Patel; Rick Jian-Zhi Chen(陳建志); > > > Baruch Siach; > > > Stefan Roese > > > Subject: [PATCH 5/7] riscv: add support for multi-hart systems > > > > > > On RISC-V, all harts boot independently. To be able to run on a > > > multi-hart system, > > > U-Boot must be extended with the functionality to manage all > > > harts in the > > > system. A new config option, CONFIG_MAIN_HART, is used to select > > > the hart > > > U-Boot runs on. All other harts are halted. > > > U-Boot can delegate functions to them using smp_call_function(). > > > > > > Every hart has a valid pointer to the global data structure and a > > > 8KiB stack by > > > default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. > > > > > > Signed-off-by: Lukas Auer > > > --- > > > > > > arch/riscv/Kconfig | 12 + > > > arch/riscv/cpu/start.S | 102 > > > ++- > > > arch/riscv/include/asm/csr.h | 1 + > > > 3 files changed, 114 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index > > > 3a51339c4d..af8d0f8d67 > > > 100644 > > > --- a/arch/riscv/Kconfig > > > +++ b/arch/riscv/Kconfig > > > @@ -140,4 +140,16 @@ config SBI_IPI > > > default y if RISCV_SMODE > > > depends on SMP > > > > > > +config MAIN_HART > > > + int "Main hart in system" > > > + default 0 > > > + help > > > + Some SoCs include harts of various sizes, some of which > > > might not > > > + be suitable for running U-Boot. CONFIG_MAIN_HART is used > > > to select > > > + the hart U-Boot runs on. > > > + > > > +config STACK_SIZE_SHIFT > > > + int > > > + default 13 > > > + > > > endmenu > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > > index > > > a30f6f7194..ce7230df37 100644 > > > --- a/arch/riscv/cpu/start.S > > > +++ b/arch/riscv/cpu/start.S > > > @@ -13,6 +13,7 @@ > > > #include > > > #include > > > #include > > > +#include > > > #include > > > #include > > > > > > @@ -45,6 +46,23 @@ _start: > > > /* mask all interrupts */ > > > csrwMODE_PREFIX(ie), zero > > > > > > +#ifdef CONFIG_SMP > > > + /* check if hart is within range */ > > > + /* s0: hart id */ > > > + li t0, CONFIG_NR_CPUS > > > + bge s0, t0, hart_out_of_bounds_loop > > > +#endif > > > + > > > +#ifdef CONFIG_SMP > > > + /* set xSIE bit to receive IPIs */ > > > +#ifdef CONFIG_RISCV_MMODE > > > + li t0, MIE_MSIE > > > +#else > > > + li t0, SIE_SSIE > > > +#endif > > > + csrsMODE_PREFIX(ie), t0 > > > +#endif > > > + > > > /* > > > * Set stackpointer in internal/ex RAM to call board_init_f > > > */ > > > @@ -56,7 +74,25 @@ call_board_init_f: > > > call_board_init_f_0: > > > mv a0, sp > > > jal board_init_f_alloc_reserve > > > + > > > + /* > > > + * Set global data pointer here for all harts, > > > uninitialized at this > > > + * point. > > > + */ > > > + mv gp, a0 > > > + > > > + /* setup stack */ > > > +#ifdef CONFIG_SMP > > > + /* s0: hart id */ > > > + sllit0, s0, CONFIG_STACK_SIZE_SHIFT > > > + sub sp, a0, t0 > > > +#else > > > mv sp, a0 > > > +#endif > > > + > > > + /* Continue on main hart, others branch to > > > secondary_hart_loop */ > > > + li t0, CONFIG_MAIN_HART > > > + bne s0, t0, secondary_hart_loop > > > > > > la t0, prior_stage_fdt_address > > > SREGs1, 0(t0) > > > @@ -95,7 +131,14 @@ relocate_code: > > > *Set up the stack > > > */ > > > stack_setup: > > > +#ifdef CONFIG_SMP > > > + /* s0: hart id */ > > > + sllit0, s0, CONFIG_STACK_SIZE_SHIFT > > > + sub sp, s2, t0 > > > +#else > > > mv sp, s2 > > > +#endif > > > + > > > la t0, _start > > > sub t6, s4, t0 /* t6 <- relocation offset > > > */ > > > beq t0, s4, clear_bss /* skip relocation */ > > > @@ -175,13 +218,30 @@ clear_bss: > > > add t0, t0, t6 /* t0 <- rel __bss_start in > > > RAM */ > > > la t1, __bss_end /* t1 <- rel __bss_end in > > > FLASH */ > > > add t1, t1, t6 /* t1 <- rel __bss_end in > > > RAM */ > > > - beq t0, t1, call_board_init_r > > > + beq t0, t1, relocate_secondary_harts > > > > > > clbss_l: > > > SREGzero, 0(t0) /* clear loop... */ > > > addit0, t0, REGBYTES > > > bne t0, t1, clbss_l > > > > > > +relocate_secondary_harts: > > > +#ifdef CONFIG_SMP > > > + /* send relocation IPI */ > > > + la
Re: [U-Boot] [PATCH v2 5/9] riscv: add support for multi-hart systems
On Sun, 2019-03-10 at 21:01 +0800, Bin Meng wrote: > On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer > wrote: > > On RISC-V, all harts boot independently. To be able to run on a > > multi-hart system, U-Boot must be extended with the functionality > > to > > manage all harts in the system. All harts entering U-Boot are > > registered > > in the available_harts mask stored in global data. A hart lottery > > system > > as used in the Linux kernel selects the hart U-Boot runs on. All > > other > > harts are halted. U-Boot can delegate functions to them using > > smp_call_function(). > > > > Every hart has a valid pointer to the global data structure and a > > 8KiB > > stack by default. The stack size is set with > > CONFIG_STACK_SIZE_SHIFT. > > > > Signed-off-by: Lukas Auer > > --- > > > > Changes in v2: > > - Implement hart lottery to pick main hart to run U-Boot > > - Remove CONFIG_MAIN_HART as it is not required anymore > > - Register available harts in the available_harts mask > > > > arch/riscv/Kconfig | 4 ++ > > arch/riscv/cpu/cpu.c | 9 ++- > > arch/riscv/cpu/start.S | 134 > > ++- > > arch/riscv/include/asm/csr.h | 1 + > > arch/riscv/lib/asm-offsets.c | 1 + > > 5 files changed, 147 insertions(+), 2 deletions(-) > > > > Looks quite good! > Thank you and thanks for testing and reviewing the series! Lukas ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PULL] u-boot-socfpga/master
Arria10 DRAM fixes and Gen5 cache fixes. The following changes since commit e8e3f2d2d48f97b2c79b698eccedce8f4f880993: Merge branch '2019-03-08-master-imports' (2019-03-08 18:04:13 -0500) are available in the Git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to 88c3bb49e1bf2b808cbad1fbdeda09480ae580a7: ddr: socfpga: Clean up ddr_setup() (2019-03-09 23:25:19 +0100) Dinh Nguyen (1): ARM: socfpga: fix data and tag latency values for pl310 cache controller Marek Vasut (9): ddr: socfpga: Fix IO in Arria10 DDR driver ddr: socfpga: Fix newline in debug print on A10 ARM: socfpga: Disable D cache in SPL ARM: socfpga: Drop CONFIG_SYS_NAND_BAD_BLOCK_POS ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset ARM: socfpga: Fix A10 SoCDK Kconfig ddr: socfpga: Fix EMIF clear timeout ddr: socfpga: Clean up EMIF reset ddr: socfpga: Clean up ddr_setup() arch/arm/mach-socfpga/misc.c| 4 ++-- arch/arm/mach-socfpga/spl_a10.c | 2 ++ board/altera/arria10-socdk/Kconfig | 2 +- drivers/ddr/altera/sdram_arria10.c | 107 --- include/configs/socfpga_arria10_socdk.h | 2 -- include/configs/socfpga_common.h| 9 - 6 files changed, 49 insertions(+), 77 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PULL] u-boot-sh/master
More gen2/gen3 fixes.
The following changes since commit e8e3f2d2d48f97b2c79b698eccedce8f4f880993:
Merge branch '2019-03-08-master-imports' (2019-03-08 18:04:13 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-sh.git master
for you to fetch changes up to 3a4511ce4ad9d0955066d47ef3d227fe97208f81:
ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3N (2019-03-09
17:57:04 +0100)
Eugeniu Rosca (2):
ARM: rmobile: rcar-gen3: Activate bootm_size
ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3N
Marek Vasut (2):
ARM: dts: rmobile: Force 1-bit bus width on Gen2 QSPI
ARM: rmobile: Convert Gen2 Stout, Porter, Silk to DM_SPI{,_FLASH}
arch/arm/dts/r8a7790-lager-u-boot.dts | 7 +++
arch/arm/dts/r8a7790-stout-u-boot.dts | 7 +++
arch/arm/dts/r8a7791-koelsch-u-boot.dts | 7 +++
arch/arm/dts/r8a7791-porter-u-boot.dts | 7 +++
arch/arm/dts/r8a7793-gose-u-boot.dts| 7 +++
arch/arm/dts/r8a7794-alt-u-boot.dts | 7 +++
arch/arm/dts/r8a7794-silk-u-boot.dts| 7 +++
arch/arm/dts/r8a77965-u-boot.dtsi | 99
---
configs/porter_defconfig| 2 ++
configs/silk_defconfig | 2 ++
configs/stout_defconfig | 2 ++
include/configs/rcar-gen2-common.h | 2 ++
include/configs/rcar-gen3-common.h | 1 -
13 files changed, 57 insertions(+), 100 deletions(-)
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 6/9] riscv: boot images passed to bootm on all harts
On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer wrote: > > Signed-off-by: Lukas Auer > Reviewed-by: Anup Patel > Reviewed-by: Bin Meng > --- > > Changes in v2: None > > arch/riscv/lib/bootm.c | 13 - > 1 file changed, 12 insertions(+), 1 deletion(-) > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/9] riscv: add support for multi-hart systems
On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer wrote: > > On RISC-V, all harts boot independently. To be able to run on a > multi-hart system, U-Boot must be extended with the functionality to > manage all harts in the system. All harts entering U-Boot are registered > in the available_harts mask stored in global data. A hart lottery system > as used in the Linux kernel selects the hart U-Boot runs on. All other > harts are halted. U-Boot can delegate functions to them using > smp_call_function(). > > Every hart has a valid pointer to the global data structure and a 8KiB > stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. > > Signed-off-by: Lukas Auer > --- > > Changes in v2: > - Implement hart lottery to pick main hart to run U-Boot > - Remove CONFIG_MAIN_HART as it is not required anymore > - Register available harts in the available_harts mask > > arch/riscv/Kconfig | 4 ++ > arch/riscv/cpu/cpu.c | 9 ++- > arch/riscv/cpu/start.S | 134 ++- > arch/riscv/include/asm/csr.h | 1 + > arch/riscv/lib/asm-offsets.c | 1 + > 5 files changed, 147 insertions(+), 2 deletions(-) > Looks quite good! Reviewed-by: Bin Meng Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 8/9] riscv: fu540: enable SMP
On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer wrote: > > Signed-off-by: Lukas Auer > Reviewed-by: Anup Patel > --- > > Changes in v2: > - New patch to enable SMP on the SiFive FU540, which was previously sent > independently > > board/sifive/fu540/Kconfig | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 9/9] riscv: qemu: enable SMP
On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer wrote: > > Signed-off-by: Lukas Auer > Reviewed-by: Anup Patel > Reviewed-by: Bin Meng > --- > > Changes in v2: None > > board/emulation/qemu-riscv/Kconfig | 1 + > 1 file changed, 1 insertion(+) > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/9] riscv: do not rely on hart ID passed by previous boot stage
On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer wrote: > > RISC-V U-Boot expects the hart ID to be passed to it via register a0 by > the previous boot stage. Machine mode firmware such as BBL and OpenSBI > do this when starting their payload (U-Boot) in supervisor mode. If > U-Boot is running in machine mode, this task must be handled by the boot > ROM. Explicitly populate register a0 with the hart ID from the mhartid > CSR to avoid possible problems on RISC-V processors with a boot ROM that > does not handle this task. > > Suggested-by: Rick Chen > Signed-off-by: Lukas Auer > --- > > Changes in v2: > - New patch to populate register a0 with the hart ID from the mhartid > CSR in machine-mode > > arch/riscv/cpu/start.S | 4 > 1 file changed, 4 insertions(+) > Reviewed-by: Bin Meng Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/9] riscv: implement IPI platform functions using SBI
On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer wrote: > > The supervisor binary interface (SBI) provides the necessary functions > to implement the platform IPI functions riscv_send_ipi() and > riscv_clear_ipi(). Use it to implement them. > > This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs > running in supervisor mode. Support for machine mode is already > available for CPUs that include the SiFive CLINT. > > Signed-off-by: Lukas Auer > Reviewed-by: Anup Patel > Reviewed-by: Bin Meng > --- > > Changes in v2: None > > arch/riscv/Kconfig | 5 + > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/sbi_ipi.c | 25 + > 3 files changed, 31 insertions(+) > create mode 100644 arch/riscv/lib/sbi_ipi.c > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/9] riscv: add infrastructure for calling functions on other harts
On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer wrote: > > Harts on RISC-V boot independently, U-Boot is responsible for managing > them. Functions are called on other harts with smp_call_function(), > which sends inter-processor interrupts (IPIs) to all other available > harts. Available harts are those marked as available in the device tree > and present in the available_harts mask stored in global data. The > available_harts mask is used to register all harts that have entered > U-Boot. Functions are specified with their address and two function > arguments (argument 2 and 3). The first function argument is always the > hart ID of the hart calling the function. On the other harts, the IPI > interrupt handler handle_ipi() must be called on software interrupts to > handle the request and call the specified function. > > Functions are stored in the ipi_data data structure. Every hart has its > own data structure in global data. While this is not required at the > moment (all harts are expected to boot Linux), this does allow future > expansion, where other harts may be used for monitoring or other tasks. > > Signed-off-by: Lukas Auer > --- > > Changes in v2: > - Remove unneeded quotes from NR_CPUS Kconfig entry > - Move memory barrier from send_ipi_many() to handle_ipi() > - Add check in send_ipi_many so that IPIs are only sent to available > harts as indicated by the available_harts mask > > arch/riscv/Kconfig | 19 + > arch/riscv/include/asm/global_data.h | 6 ++ > arch/riscv/include/asm/smp.h | 53 > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/smp.c | 116 +++ > 5 files changed, 195 insertions(+) > create mode 100644 arch/riscv/include/asm/smp.h > create mode 100644 arch/riscv/lib/smp.c > Reviewed-by: Bin Meng Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] common: spl_fit: Allow firmware image if no loadables
On 19-03-10 13:02:28, Marek Vasut wrote:
> On 3/10/19 12:42 PM, Abel Vesa wrote:
> > If CONFIG_SPL_OS_BOOT and FIT_IMAGE_TINY are enabled,
> > the os will not be set to anything and therefore will
> > remain as IH_OS_INVALID. What's needed here is to
> > have IH_OS_U_BOOT as default. And since using the
> > mkimage oneline command (that is, no its file), the
> > loadables can't be specified, so we allow firmware
> > as a fallback.
>
> Wouldn't it make more sense to fix the mkimage ?
>
OK then, I'll add a new option to mkimage for loadables.
> > Signed-off-by: Abel Vesa
> > Tested-by: Fabio Estevam
> > ---
> >
> > Changes since v1:
> > * added braces to get rid of the build warning
> >
> > common/spl/spl_fit.c | 10 +++---
> > 1 file changed, 7 insertions(+), 3 deletions(-)
> >
> > diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> > index db43626..bfcf71a 100644
> > --- a/common/spl/spl_fit.c
> > +++ b/common/spl/spl_fit.c
> > @@ -478,11 +478,15 @@ int spl_load_simple_fit(struct spl_image_info
> > *spl_image,
> >
> > /* Now check if there are more images for us to load */
> > for (; ; index++) {
> > - uint8_t os_type = IH_OS_INVALID;
> > + uint8_t os_type = IH_OS_U_BOOT;
>
> Does that mean invalid image type is then always handled as if it was
> U-Boot ? That looks kinda iffy.
>
Hmm, fair enough. I'll do the fix in mkimage and this change won't be necessary
then.
> > node = spl_fit_get_image_node(fit, images, "loadables", index);
> > - if (node < 0)
> > - break;
> > + if (node < 0) {
> > + node = spl_fit_get_image_node(fit, images,
> > + "firmware", index);
> > + if (node < 0)
> > + break;
> > + }
> >
> > ret = spl_load_fit_image(info, sector, fit, base_offset, node,
> > _info);
> >
>
>
> --
> Best regards,
> Marek Vasut
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[U-Boot] [PATCH 1/2] Convert CONFIG_NAND to Kconfig
This converts the following to Kconfig: CONFIG_NAND A bunch of boards have dependent NAND drivers, and CONFIG_NAND is already in Kconfig, so this patch enables that flag for a variety of boards to make their respective NAND drivers more easily convert to Kconfig Signed-off-by: Adam Ford --- configs/B4420QDS_SPIFLASH_defconfig| 1 + configs/B4420QDS_defconfig | 1 + configs/B4860QDS_SECURE_BOOT_defconfig | 1 + configs/B4860QDS_SPIFLASH_defconfig| 1 + configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/B4860QDS_defconfig | 1 + configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig| 1 + configs/BSC9131RDB_SPIFLASH_defconfig | 1 + configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK100_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_NOR_DDRCLK133_defconfig | 1 + configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig | 1 + configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig | 1 + configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig | 1 + configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig| 1 + configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig | 1 + configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig| 1 + configs/C29XPCIE_NOR_SECBOOT_defconfig | 1 + configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig| 1 + configs/C29XPCIE_SPIFLASH_defconfig| 1 + configs/C29XPCIE_defconfig | 1 + configs/CONFIG_NAND=y | 1 + configs/MPC8313ERDB_33_defconfig | 1 + configs/MPC8313ERDB_66_defconfig | 1 + configs/MPC8315ERDB_defconfig | 1 + configs/MPC837XEMDS_HOST_defconfig | 1 + configs/MPC837XEMDS_defconfig | 1 + configs/MPC8536DS_36BIT_defconfig | 1 + configs/MPC8536DS_SDCARD_defconfig | 1 + configs/MPC8536DS_SPIFLASH_defconfig | 1 + configs/MPC8536DS_defconfig| 1 + configs/MPC8569MDS_ATM_defconfig | 1 + configs/MPC8569MDS_defconfig | 1 + configs/MPC8572DS_36BIT_defconfig | 1 + configs/MPC8572DS_defconfig| 1 + configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig| 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig| 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig| 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig| 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig| 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1021RDB-PC_36BIT_defconfig
Re: [U-Boot] [PATCH v2] common: spl_fit: Allow firmware image if no loadables
On 3/10/19 12:42 PM, Abel Vesa wrote:
> If CONFIG_SPL_OS_BOOT and FIT_IMAGE_TINY are enabled,
> the os will not be set to anything and therefore will
> remain as IH_OS_INVALID. What's needed here is to
> have IH_OS_U_BOOT as default. And since using the
> mkimage oneline command (that is, no its file), the
> loadables can't be specified, so we allow firmware
> as a fallback.
Wouldn't it make more sense to fix the mkimage ?
> Signed-off-by: Abel Vesa
> Tested-by: Fabio Estevam
> ---
>
> Changes since v1:
> * added braces to get rid of the build warning
>
> common/spl/spl_fit.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index db43626..bfcf71a 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -478,11 +478,15 @@ int spl_load_simple_fit(struct spl_image_info
> *spl_image,
>
> /* Now check if there are more images for us to load */
> for (; ; index++) {
> - uint8_t os_type = IH_OS_INVALID;
> + uint8_t os_type = IH_OS_U_BOOT;
Does that mean invalid image type is then always handled as if it was
U-Boot ? That looks kinda iffy.
> node = spl_fit_get_image_node(fit, images, "loadables", index);
> - if (node < 0)
> - break;
> + if (node < 0) {
> + node = spl_fit_get_image_node(fit, images,
> + "firmware", index);
> + if (node < 0)
> + break;
> + }
>
> ret = spl_load_fit_image(info, sector, fit, base_offset, node,
>_info);
>
--
Best regards,
Marek Vasut
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[U-Boot] [PATCH v2] common: spl_fit: Allow firmware image if no loadables
If CONFIG_SPL_OS_BOOT and FIT_IMAGE_TINY are enabled,
the os will not be set to anything and therefore will
remain as IH_OS_INVALID. What's needed here is to
have IH_OS_U_BOOT as default. And since using the
mkimage oneline command (that is, no its file), the
loadables can't be specified, so we allow firmware
as a fallback.
Signed-off-by: Abel Vesa
Tested-by: Fabio Estevam
---
Changes since v1:
* added braces to get rid of the build warning
common/spl/spl_fit.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index db43626..bfcf71a 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -478,11 +478,15 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
/* Now check if there are more images for us to load */
for (; ; index++) {
- uint8_t os_type = IH_OS_INVALID;
+ uint8_t os_type = IH_OS_U_BOOT;
node = spl_fit_get_image_node(fit, images, "loadables", index);
- if (node < 0)
- break;
+ if (node < 0) {
+ node = spl_fit_get_image_node(fit, images,
+ "firmware", index);
+ if (node < 0)
+ break;
+ }
ret = spl_load_fit_image(info, sector, fit, base_offset, node,
_info);
--
2.7.4
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[U-Boot] [PATCH v3 3/3] poplar: enable Ethernet driver support
The 'phy' reset of gmac device in kernel device tree is not generic
enough for u-boot to use, so we need to overwrite the 'resets' property
as needed. With this device tree fixup and poplar_defconfig changes,
Ethernet starts working on Poplar board.
Signed-off-by: Shawn Guo
Reviewed-by: Igor Opaniuk
---
arch/arm/dts/hi3798cv200-u-boot.dtsi | 14 ++
configs/poplar_defconfig | 3 +++
2 files changed, 17 insertions(+)
diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi
b/arch/arm/dts/hi3798cv200-u-boot.dtsi
index 7844c5208c5d..2ca943f64e59 100644
--- a/arch/arm/dts/hi3798cv200-u-boot.dtsi
+++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi
@@ -8,7 +8,15 @@
* (C) Copyright 2017 Jorge Ramirez-Ortiz
*/
+#include
+
{
+ rst: reset-controller@8a22000 {
+ compatible = "hisilicon,hi3798cv200-reset";
+ reg = <0x8a22000 0x1000>;
+ #reset-cells = <3>;
+ };
+
usb2: ehci@989 {
compatible = "generic-ehci";
reg = <0x989 0x100>;
@@ -16,6 +24,12 @@
};
};
+ {
+ resets = < 0xcc 9 HISI_RESET_ACTIVE_HIGH>,
+< 0xcc 11 HISI_RESET_ACTIVE_HIGH>,
+< 0xcc 13 HISI_RESET_ACTIVE_LOW>;
+};
+
{
clock = <7500>;
status = "okay";
diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig
index 81bd3702e42a..76ab5eb70e7e 100644
--- a/configs/poplar_defconfig
+++ b/configs/poplar_defconfig
@@ -19,6 +19,9 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
+CONFIG_DM_ETH=y
+CONFIG_HIGMACV300_ETH=y
+CONFIG_RESET_HISILICON=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
--
2.18.0
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[U-Boot] [PATCH v3 1/3] reset: add reset driver for HiSilicon platform
It adds a Driver Model compatible reset driver for HiSlicon platform.
The driver implements a custom .of_xlate function, and uses .data field
as reset register offset and .id field as bit shift.
Signed-off-by: Shawn Guo
Reviewed-by: Igor Opaniuk
---
drivers/reset/Kconfig | 6 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-hisilicon.c | 111
3 files changed, 118 insertions(+)
create mode 100644 drivers/reset/reset-hisilicon.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index a81e76769604..6ec6f39c85f0 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -121,4 +121,10 @@ config RESET_SUNXI
This enables support for common reset driver for
Allwinner SoCs.
+config RESET_HISILICON
+ bool "Reset controller driver for HiSilicon SoCs"
+ depends on DM_RESET
+ help
+ Support for reset controller on HiSilicon SoCs.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 4fad7d412985..7fec75bb4923 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
diff --git a/drivers/reset/reset-hisilicon.c b/drivers/reset/reset-hisilicon.c
new file mode 100644
index ..7b0c11fbc82e
--- /dev/null
+++ b/drivers/reset/reset-hisilicon.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct hisi_reset_priv {
+ void __iomem *base;
+};
+
+static int hisi_reset_deassert(struct reset_ctl *rst)
+{
+ struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
+ u32 offset = rst->data & 0x;
+ u32 shift = rst->data >> 16;
+ int polarity = rst->id;
+ u32 val;
+
+ val = readl(priv->base + offset);
+ if (polarity == HISI_RESET_ACTIVE_HIGH)
+ val &= ~BIT(shift);
+ else
+ val |= BIT(shift);
+ writel(val, priv->base + offset);
+
+ return 0;
+}
+
+static int hisi_reset_assert(struct reset_ctl *rst)
+{
+ struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
+ u32 offset = rst->data & 0x;
+ u32 shift = rst->data >> 16;
+ int polarity = rst->id;
+ u32 val;
+
+ val = readl(priv->base + offset);
+ if (polarity == HISI_RESET_ACTIVE_HIGH)
+ val |= BIT(shift);
+ else
+ val &= ~BIT(shift);
+ writel(val, priv->base + offset);
+
+ return 0;
+}
+
+static int hisi_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int hisi_reset_request(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int hisi_reset_of_xlate(struct reset_ctl *rst,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 3) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ /*
+* Encode register offset in .data[15..0] and bit shift in
+* .data[31..16], and use .id field as polarity.
+*/
+ rst->data = (args->args[1] << 16) | (args->args[0] & 0x);
+ rst->id = args->args[2];
+
+ return 0;
+}
+
+static const struct reset_ops hisi_reset_reset_ops = {
+ .of_xlate = hisi_reset_of_xlate,
+ .request = hisi_reset_request,
+ .free = hisi_reset_free,
+ .rst_assert = hisi_reset_assert,
+ .rst_deassert = hisi_reset_deassert,
+};
+
+static const struct udevice_id hisi_reset_ids[] = {
+ { .compatible = "hisilicon,hi3798cv200-reset" },
+ { }
+};
+
+static int hisi_reset_probe(struct udevice *dev)
+{
+ struct hisi_reset_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_remap_addr(dev);
+ if (!priv->base)
+ return -ENOMEM;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(hisi_reset) = {
+ .name = "hisilicon_reset",
+ .id = UCLASS_RESET,
+ .of_match = hisi_reset_ids,
+ .ops = _reset_reset_ops,
+ .probe = hisi_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct hisi_reset_priv),
+};
--
2.18.0
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[U-Boot] [PATCH v3 2/3] net: add higmacv300 Ethernet driver for HiSilicon platform
It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon
SoCs like Hi3798CV200. It's based on a downstream U-Boot driver, but
quite a lot of code gets rewritten and cleaned up to adopt driver model
and PHY API.
Signed-off-by: Shawn Guo
---
drivers/net/Kconfig | 9 +
drivers/net/Makefile | 1 +
drivers/net/higmacv300.c | 597 +++
3 files changed, 607 insertions(+)
create mode 100644 drivers/net/higmacv300.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6a570285aac5..ad1e50c0e8ca 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -525,4 +525,13 @@ config MEDIATEK_ETH
This Driver support MediaTek Ethernet GMAC
Say Y to enable support for the MediaTek Ethernet GMAC.
+config HIGMACV300_ETH
+ bool "HiSilicon Gigabit Ethernet Controller"
+ depends on DM_ETH
+ select DM_RESET
+ select PHYLIB
+ help
+ This driver supports HIGMACV300 Ethernet controller found on
+ HiSilicon SoCs.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 51be72b0aa86..8d02a378964b 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
obj-y += mscc_eswitch/
+obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
diff --git a/drivers/net/higmacv300.c b/drivers/net/higmacv300.c
new file mode 100644
index ..1be8359133de
--- /dev/null
+++ b/drivers/net/higmacv300.c
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define STATION_ADDR_LOW 0x
+#define STATION_ADDR_HIGH 0x0004
+#define MAC_DUPLEX_HALF_CTRL 0x0008
+#define PORT_MODE 0x0040
+#define PORT_EN0x0044
+#define BIT_TX_EN BIT(2)
+#define BIT_RX_EN BIT(1)
+#define MODE_CHANGE_EN 0x01b4
+#define BIT_MODE_CHANGE_EN BIT(0)
+#define MDIO_SINGLE_CMD0x03c0
+#define BIT_MDIO_BUSY BIT(20)
+#define MDIO_READ (BIT(17) | BIT_MDIO_BUSY)
+#define MDIO_WRITE (BIT(16) | BIT_MDIO_BUSY)
+#define MDIO_SINGLE_DATA 0x03c4
+#define MDIO_RDATA_STATUS 0x03d0
+#define BIT_MDIO_RDATA_INVALID BIT(0)
+#define RX_FQ_START_ADDR 0x0500
+#define RX_FQ_DEPTH0x0504
+#define RX_FQ_WR_ADDR 0x0508
+#define RX_FQ_RD_ADDR 0x050c
+#define RX_FQ_REG_EN 0x0518
+#define RX_BQ_START_ADDR 0x0520
+#define RX_BQ_DEPTH0x0524
+#define RX_BQ_WR_ADDR 0x0528
+#define RX_BQ_RD_ADDR 0x052c
+#define RX_BQ_REG_EN 0x0538
+#define TX_BQ_START_ADDR 0x0580
+#define TX_BQ_DEPTH0x0584
+#define TX_BQ_WR_ADDR 0x0588
+#define TX_BQ_RD_ADDR 0x058c
+#define TX_BQ_REG_EN 0x0598
+#define TX_RQ_START_ADDR 0x05a0
+#define TX_RQ_DEPTH0x05a4
+#define TX_RQ_WR_ADDR 0x05a8
+#define TX_RQ_RD_ADDR 0x05ac
+#define TX_RQ_REG_EN 0x05b8
+#define BIT_START_ADDR_EN BIT(2)
+#define BIT_DEPTH_EN BIT(1)
+#define DESC_WR_RD_ENA 0x05cc
+#define BIT_RX_OUTCFF_WR BIT(3)
+#define BIT_RX_CFF_RD BIT(2)
+#define BIT_TX_OUTCFF_WR BIT(1)
+#define BIT_TX_CFF_RD BIT(0)
+#define BITS_DESC_ENA (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
+BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
+
+/* MACIF_CTRL */
+#define RGMII_SPEED_1000 0x2c
+#define RGMII_SPEED_1000x2f
+#define RGMII_SPEED_10 0x2d
+#define MII_SPEED_100 0x0f
+#define MII_SPEED_10 0x0d
+#define GMAC_SPEED_10000x05
+#define GMAC_SPEED_100 0x01
+#define GMAC_SPEED_10 0x00
+#define GMAC_FULL_DUPLEX BIT(4)
+
+#define RX_DESC_NUM64
+#define TX_DESC_NUM2
+#define DESC_SIZE 32
+#define DESC_WORD_SHIFT3
+#define DESC_BYTE_SHIFT5
+#define DESC_CNT(n)((n) >> DESC_BYTE_SHIFT)
+#define DESC_BYTE(n) ((n) << DESC_BYTE_SHIFT)
+#define DESC_VLD_FREE 0
+#define DESC_VLD_BUSY 1
+
+#define MAC_MAX_FRAME_SIZE 1600
+
+enum higmac_queue {
+ RX_FQ,
+ RX_BQ,
+
[U-Boot] [PATCH v3 0/3] Add Ethernet support for Poplar board
The series adds Ethernet support for Poplar board. It firstly creates a reset driver for HiSilicon platform, then introduces higmacv300 Ethernet driver, and finally enables Ethernet support for Poplar board. Changes for v3: - Add polarity support into reset driver, so that we can drop the hacking on gmac reset sequence from higmacv300 driver. Changes for v2: - Rename driver symbol to HIGMACV300_ETH. - Remove the use of temp variable 'addr' in higmac_recv(). - Simplify the return of function higmac_ofdata_to_platdata() and higmac_probe(). - Combine delaration and initialization for phyintf in function higmac_ofdata_to_platdata(). - Eliminate the MDIO read/write macros. - Use wait_for_bit_le32() for MDIO command completion polling. - Set up RX packet buffers in RX_FQ descriptor at initialization time, so that we do not need to allocate/free packet buffers repeatedly. - Inform GMAC that the RX descriptor is no longer in use in function higmac_free_pkt(). - Define BITS_DESC_ENA instead of using magic number 0xf. Shawn Guo (3): reset: add reset driver for HiSilicon platform net: add higmacv300 Ethernet driver for HiSilicon platform poplar: enable Ethernet driver support arch/arm/dts/hi3798cv200-u-boot.dtsi | 14 + configs/poplar_defconfig | 3 + drivers/net/Kconfig | 9 + drivers/net/Makefile | 1 + drivers/net/higmacv300.c | 597 +++ drivers/reset/Kconfig| 6 + drivers/reset/Makefile | 1 + drivers/reset/reset-hisilicon.c | 111 + 8 files changed, 742 insertions(+) create mode 100644 drivers/net/higmacv300.c create mode 100644 drivers/reset/reset-hisilicon.c -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
