Re: [U-Boot] EFIBootGuard for CIP and SecureBoot
On 26.04.19 15:46, Heinrich Schuchardt wrote: > > On 4/26/19 1:21 PM, Jan Kiszka wrote: >> On 26.04.19 12:21, Grant Likely wrote: >>> On 26/04/2019 10:49, Jan Kiszka wrote: On 26.04.19 11:07, Francois Ozog wrote: >>> [...] > Here are the guiding principles of our efforts : > 0) we want a cross architecture (x86/Arm/...), cross vendor and cross > processor model update solution > 1) untrusted world cannot update trusted world Conceptually, it can. It's a matter of validating the update by the trusted world before using it. A trusted instance can allow an untrusted one to write version 2, validate that before switching to it, and stick with version 1 if that fails. > 2) what the UEFI implementation does with the capsule is platform > specific > 3) the update capsule payload is opaque > > 1) is a "philosophy" decision. When you have a root of trust down to > the operating system. So in theory everything should be fine. But the > attack surface is such that we can't rule out hacking (and history > prove this is unfortunately a safe assumption). In addition, there may > be liability aspects related to the who does the update: the hardware > platform administrator may not be the legal entity than the operating > system administrator. For instance: > - on Packet.net could, a customer can flash up to the BL33 untrusted > firmware but that is all. > - A surveillance camera can be operated by city personnel but only law > enforcement agency can see raw video (un-blurred faces and licence > plates). This can be implemented by a derivative of OPTEE SecureMedia > Path but if you allow untrusted world to update the trusted one, city > personnel can overcome the legal restriction. > With 1) this means that even U-Boot code shall not be able/allowed to > update S-EL3 firmware (be it Trusted Firmware A or something else), > Secure EL1/0 software (OPTEE and its applications or something else). > If possible, allowing the operating system administrator to > selectively (BL33 is OK but not S-EL3) update firmware is at least > platform dependent. Hence defeats 0) > > With 2) we do not impose reboot to update. Some platform may impose > reboot or some designers will prefer reboot. We say that there is a > chain of responsibility for updates. > So it is perfectly OK to have a Linux software agent receive an update > by any mean (network, USB, serial...). The agent will pack this (or > those) into a capsule and push it to UEFI implementation. > The UEFI implementation (U-Boot or Tianocore) will then do whatever it > pleases for the update providing it complies with 1) So the UEFI > implementation can live update up to BL33 firmware. > Should the update be targeted to secure world, then the UEFI > implementation can pass it to S-EL3 for update (platform specific) > which means the update can also be live. It is a designer decision. > > With 3) we have flexibility but sometimes too much flexibility is a > problem. Alexander Graf suggested we can use a FIT object to pass > diverse objects. It is "half" opaque but I really like the idea. > The contents of individual FIT components can be blocks to be placed > at a fix location in a NOR flash or a file, no importance. > > What do everyone think about those design principles ? > UEFI and capsules can be fine for those platform that support it (and it's still a rare feature) and for stuff like boot and peripheral firmware. I don't think it's a wise, future-proof idea to use it for more. UEFI is not a very healthy ecosystem yet, and I'm personally skeptical it will evolve towards that (looking at that as both a user as well as an OEM). It's not even present in quite a few of our use cases. In some it will never be - think of safety-critical system: not affordable with such a complex approach like UEFI. >>> Can I challenge that view a bit? On the Tianocore side I agree that the >>> ecosystem isn't very healthy. That project in particular struggles with >>> what to do with board support, having decided early on that board >>> support generally doesn't need to be in the main repository. >>> >>> However, U-Boot support for the UEFI ABI is improving in leaps and >>> bounds. SUSE and Fedora both depend on U-Boot UEFI for booting on all >>> the Arm SBCs that they support, and enabling UEFI in U-Boot is just a >>> config option or two. There is a fair bit of encouragement from within >>> the project to enable UEFI by default. >> I don't disagree that this aspect is a step forward (though pulling in >> things redundant code via grub & Co is not really progress). But a Unix >> community would have probably designed a technically more elegant >> solution on a green field than the clumsy, legacy-based UEFI interfaces. >> >
Re: [U-Boot] [PATCH v2 1/1] lib/vsprintf: allow printing upper case GUIDs
On 26.04.19 19:23, Heinrich Schuchardt wrote:
> In the UEFI context GUIDs are expected to be rendered in upper case.
>
> The patch uses the formerly unused bit 1 of the parameter str_format
> of function uuid_bin_to_str() to indicate if we need upper or lower case
> output.
>
> Function uuid_string() in vsprint.c is adjusted to correctly set the bit
> depending on the print format code.
>
> %pUb: 01020304-0506-0708-090a-0b0c0d0e0f10
> %pUB: 01020304-0506-0708-090A-0B0C0D0E0F10
> %pUl: 04030201-0605-0807-090a-0b0c0d0e0f10
> %pUL: 04030201-0605-0807-090A-0B0C0D0E0F10
>
> Up to this point only a diagnostic message in mount_ubifs() using '%pUB' is
> concerned by the change. Further patches are needed to adjust the UEFI
> subsystem.
>
> A unit test is provided inside the ut_print command.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2
> add missing sprintf() statement in unit test
> ---
> include/uuid.h | 8
> lib/uuid.c | 18 --
> lib/vsprintf.c | 14 --
> test/print_ut.c | 23 +++
> 4 files changed, 47 insertions(+), 16 deletions(-)
>
> diff --git a/include/uuid.h b/include/uuid.h
> index 124bbce8a2..47d5b0d8d4 100644
> --- a/include/uuid.h
> +++ b/include/uuid.h
> @@ -16,10 +16,10 @@ struct uuid {
> unsigned char node[6];
> } __packed;
>
> -enum {
> - UUID_STR_FORMAT_STD,
> - UUID_STR_FORMAT_GUID
> -};
> +/* Bits of a bitmask specifying the output format for GUIDs */
> +#define UUID_STR_FORMAT_STD 0
> +#define UUID_STR_FORMAT_GUID 1
> +#define UUID_STR_UPPER_CASE 2
When #define'ing bitmasks, it's usually more obvious for the reader when
they're defined through shift operations:
#define ... (1<<0)
#define ... (1<<1)
etc
The rest looks great to me :)
Alex
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[U-Boot] [PATCH v6 0/3] arm64: rockchip: dts: Add rk3399 -u-boot.dtsi files
This series is a rework of v5 patch that send it in separate series[1] All these changes are creating an initial rk3399-u-boot.dtsi and rk3399 board -u-boot.dtsi files and u-boot specific dts changes like - sdram dtsi - sdmmc, u-boot,dm-pre-reloc - spi1, u-boot,dm-pre-reloc Changes for v6: - spilt the existing patch[1] into multiple patches and send as a separate series. [1] https://patchwork.ozlabs.org/patch/1091720/ Any inputs? Jagan. Jagan Teki (3): arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi files arm64: rockchip: dts: Add initial rk3399-u-boot.dtsi file arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsi arch/arm/dts/rk3399-evb-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399-evb.dts | 2 -- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 6 ++ arch/arm/dts/rk3399-ficus.dts | 1 - arch/arm/dts/rk3399-firefly-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399-firefly.dts | 2 -- arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399-gru-bob.dts | 1 - arch/arm/dts/rk3399-gru-u-boot.dtsi | 6 ++ arch/arm/dts/rk3399-gru.dtsi| 1 - arch/arm/dts/rk3399-puma-ddr1600.dts| 1 + arch/arm/dts/rk3399-puma.dtsi | 3 --- arch/arm/dts/rk3399-rock960-u-boot.dtsi | 6 ++ arch/arm/dts/rk3399-rock960.dts | 1 - arch/arm/dts/rk3399-u-boot.dtsi | 12 15 files changed, 52 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/rk3399-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-ficus-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-firefly-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-gru-bob-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-gru-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock960-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-u-boot.dtsi -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 2/3] arm64: rockchip: dts: Add initial rk3399-u-boot.dtsi file
U-Boot always managed to use Linux devicetree files with respective
bindings, but on the other hand u-boot also has it's own u-boot
specific nodes or properties example u-boot,dm-pre-reloc which
is required for SPL_OF_CONTROL to allocate particular node.
It is always better to maintain these u-boot specific nodes and
properties into seperate dts files. This would help to sync the
devicetrees directly from Linux.
This patch is adding initial rk3399-u-boot.dtsi and move sdmmc,
spi1 u-boot,dm-pre-reloc properties into it so-that the subsequent
rk3399 boards can include the same on their board dtsi files.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3399-u-boot.dtsi | 12
1 file changed, 12 insertions(+)
create mode 100644 arch/arm/dts/rk3399-u-boot.dtsi
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
new file mode 100644
index 00..0786c1193a
--- /dev/null
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&spi1 {
+ u-boot,dm-pre-reloc;
+};
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v6 1/3] arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi files
Devicetree files in RK3399 platform is synced from Linux, like other
platforms does. Apart from these u-boot in rk3399 would also require
some u-boot specific node like dmc.
dmc node has big chunk of DDR timing parameters which are specific
to specific board, and maintained with rk3399-sdram*.dtsi.
So, create board specific -u-boot.dtsi files and move these sdram dtsi
files accordingly. This would help of maintain u-boot specific changes
separately without touching Linux dts(i) files which indeed easy for
syncing from Linux between releases.
These board specific -u-boot.dtsi can be extendible to add more u-boot
specific nodes or properties in future.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 6 ++
arch/arm/dts/rk3399-evb.dts | 1 -
arch/arm/dts/rk3399-ficus-u-boot.dtsi | 6 ++
arch/arm/dts/rk3399-ficus.dts | 1 -
arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 ++
arch/arm/dts/rk3399-firefly.dts | 1 -
arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 6 ++
arch/arm/dts/rk3399-gru-bob.dts | 1 -
arch/arm/dts/rk3399-rock960-u-boot.dtsi | 6 ++
arch/arm/dts/rk3399-rock960.dts | 1 -
10 files changed, 30 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/dts/rk3399-evb-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-ficus-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-firefly-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-rock960-u-boot.dtsi
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi
b/arch/arm/dts/rk3399-evb-u-boot.dtsi
new file mode 100644
index 00..7e2c57af22
--- /dev/null
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index ce004d0d18..2366e7ed3a 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -7,7 +7,6 @@
#include
#include
#include "rk3399.dtsi"
-#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
/ {
model = "Rockchip RK3399 Evaluation Board";
diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi
b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
new file mode 100644
index 00..eab86bdb30
--- /dev/null
+++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-sdram-ddr3-1600.dtsi"
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts
index 4af0e4e383..4b2dd82b67 100644
--- a/arch/arm/dts/rk3399-ficus.dts
+++ b/arch/arm/dts/rk3399-ficus.dts
@@ -8,7 +8,6 @@
/dts-v1/;
#include "rk3399-rock960.dtsi"
-#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "96boards RK3399 Ficus";
diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi
b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
new file mode 100644
index 00..eab86bdb30
--- /dev/null
+++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-sdram-ddr3-1600.dtsi"
diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
index f90e7e88db..5d52319393 100644
--- a/arch/arm/dts/rk3399-firefly.dts
+++ b/arch/arm/dts/rk3399-firefly.dts
@@ -7,7 +7,6 @@
#include
#include
#include "rk3399.dtsi"
-#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "Firefly-RK3399 Board";
diff --git a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
new file mode 100644
index 00..9edb8cf841
--- /dev/null
+++ b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts
index 0e3d91fc28..1ee0dc0d9f 100644
--- a/arch/arm/dts/rk3399-gru-bob.dts
+++ b/arch/arm/dts/rk3399-gru-bob.dts
@@ -7,7 +7,6 @@
/dts-v1/;
#include "rk3399-gru-chromebook.dtsi"
-#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
/ {
model = "Google Bob";
diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi
b/arch/arm/dts/rk3399-rock960-u-boot.dtsi
new file mode 100644
index 00..5256f6d3f2
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts
index 25c58b4261..7e06bc97e5 100644
--- a/arch/arm/dts/rk3399-rock960.dts
+++ b/arch/arm/dts/rk3399-rock960.dts
@@ -5,7 +5,6 @@
/dts-v1/;
#include "rk3399-rock960.dtsi"
-#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
/ {
model = "96boards Rock960";
--
2.18.0.321.gffc6
[U-Boot] [PATCH v6 3/3] arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsi
Now we have
- board specific -u-boot.dtsi files for board specific u-boot
dts changes.
- soc specific rk3399-u-boot.dtsi for soc specific u-boot
dts changes.
So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi
and drop the properties which are globally available in rk3399-u-boot.dtsi
Right now rk3399-u-boot.dtsi has sdmmc, spi1 u-boot,dm-pre-reloc
property and more properties and nodes can be move further based
on the requirements.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 1 +
arch/arm/dts/rk3399-evb.dts | 1 -
arch/arm/dts/rk3399-firefly-u-boot.dtsi | 1 +
arch/arm/dts/rk3399-firefly.dts | 1 -
arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 1 +
arch/arm/dts/rk3399-gru-u-boot.dtsi | 6 ++
arch/arm/dts/rk3399-gru.dtsi| 1 -
arch/arm/dts/rk3399-puma-ddr1600.dts| 1 +
arch/arm/dts/rk3399-puma.dtsi | 3 ---
9 files changed, 10 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/dts/rk3399-gru-u-boot.dtsi
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi
b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index 7e2c57af22..20910e744b 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -3,4 +3,5 @@
* Copyright (C) 2019 Jagan Teki
*/
+#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index 2366e7ed3a..a506e8da37 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -154,7 +154,6 @@
};
&sdmmc {
- u-boot,dm-pre-reloc;
bus-width = <4>;
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi
b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
index eab86bdb30..67b63a8352 100644
--- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
@@ -3,4 +3,5 @@
* Copyright (C) 2019 Jagan Teki
*/
+#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
index 5d52319393..a4cb64f8bd 100644
--- a/arch/arm/dts/rk3399-firefly.dts
+++ b/arch/arm/dts/rk3399-firefly.dts
@@ -591,7 +591,6 @@
};
&sdmmc {
- u-boot,dm-pre-reloc;
bus-width = <4>;
status = "okay";
};
diff --git a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
index 9edb8cf841..726f396f32 100644
--- a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
@@ -3,4 +3,5 @@
* Copyright (C) 2019 Jagan Teki
*/
+#include "rk3399-gru-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi
b/arch/arm/dts/rk3399-gru-u-boot.dtsi
new file mode 100644
index 00..7bddc3acdb
--- /dev/null
+++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi
index df19263acc..8b3d90fdc6 100644
--- a/arch/arm/dts/rk3399-gru.dtsi
+++ b/arch/arm/dts/rk3399-gru.dtsi
@@ -545,7 +545,6 @@ ap_i2c_audio: &i2c8 {
&spi1 {
status = "okay";
- u-boot,dm-pre-reloc;
pinctrl-names = "default", "sleep";
pinctrl-1 = <&spi1_sleep>;
diff --git a/arch/arm/dts/rk3399-puma-ddr1600.dts
b/arch/arm/dts/rk3399-puma-ddr1600.dts
index 337e0eabb4..42763f82d0 100644
--- a/arch/arm/dts/rk3399-puma-ddr1600.dts
+++ b/arch/arm/dts/rk3399-puma-ddr1600.dts
@@ -6,5 +6,6 @@
/dts-v1/;
#include "rk3399-puma.dtsi"
+#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi
index 8304f67192..2712ab6826 100644
--- a/arch/arm/dts/rk3399-puma.dtsi
+++ b/arch/arm/dts/rk3399-puma.dtsi
@@ -492,7 +492,6 @@
};
&sdmmc {
- u-boot,dm-pre-reloc;
clock-frequency = <15000>;
max-frequency = <4000>;
supports-sd;
@@ -648,8 +647,6 @@
&spi1 {
- u-boot,dm-pre-reloc;
-
status = "okay";
#address-cells = <1>;
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v6 00/13] rockchip: Add new rk3399 boards
This is v6 patchset for New rk3399 boards support wrt previous version[1] Overall this series add support below rk3399 boards - Orangepi RK3399 - NanoPI M4 - NanoPC T4 - NanoPI NEO4 - Orangepi RK3399 - Rock PI 4 - Rockpro64 All the respective dts(i) files are synced from Linux 5.1-rc2 and few dts(i) from linux-next. SoC u-boot specific dtsi rk3399-u-boot.dtsi changes are part of another series [3]. Out of all above boards Rockpor64, Rock-PI and Nanopi NEO4 would support booting via Rockchip miniloader as of now. For booting the same with SPL NEO4 would require dynamic dram timing detection and rest require LPDDR4 code. There is WIP[2] for these dependencies and this would require big chunk of changes will effect all the rk3399 boards, so I'm planning to mark it for next MW. Changes for v6: - Include Nanopc T4 support patch - drop rk3399-u-boot.dtsi patch since it is send separately. Changes for v5: - Make all changes related to move sdmmc, spi1 u-boot,dm-pre-reloc properties into all rk3399 dts(i) files. Changes for v4: - don't include existing dts(i) sdmmc, u-boot,dm-pre-reloc into rk3399-u-boot.dtsi Changes for v3: - drop NanoPC T4 for now, since board is yet to receive. - add Rock PI-4 board. - add separate -u-boot.dtsi file for nanopi4 sdram changes. - collect Paul, Philipp and Kever Reviewed-by tags [1] https://patchwork.ozlabs.org/cover/1091712/ [2] https://github.com/amarula/u-boot-amarula/tree/rockdev-lpddr4 [3] https://patchwork.ozlabs.org/cover/1091909/ Any inputs? Jagan. Jagan Teki (13): rockchip: dts: rk3399: Sync rk3399-opp from Linux rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2 Kconfig: Add default SPL_FIT_GENERATOR for rockchip arm: rockchip: rk3399: Move common configs in Kconfig rockchip: rk3399: Add Orangepi RK3399 support rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1 rockchip: rk3399: Add Nanopi M4 board support rockchip: rk3399: Add Nanopc T4 board support rockchip: rk3399: Add Nanopi NEO4 board support rockchip: rk3399: Add Rockpro64 board support rockchip: rk3399: Add Rock PI 4 support doc: rockchip: Add global doc for rk3399 build/flash Kconfig | 1 + arch/arm/dts/Makefile | 6 + arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 + arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++ arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 + arch/arm/dts/rk3399-nanopi-m4.dts | 66 ++ arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-nanopi-neo4.dts | 50 ++ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 11 + arch/arm/dts/rk3399-nanopi4.dtsi| 703 ++ arch/arm/dts/rk3399-opp.dtsi| 133 arch/arm/dts/rk3399-orangepi-u-boot.dtsi| 7 + arch/arm/dts/rk3399-orangepi.dts| 771 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rock-pi-4.dts | 606 +++ arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rockpro64.dts | 712 ++ arch/arm/dts/rk3399.dtsi| 6 + arch/arm/mach-rockchip/Kconfig | 16 + board/rockchip/evb_rk3399/MAINTAINERS | 39 + configs/chromebook_bob_defconfig| 17 - configs/evb-rk3399_defconfig| 17 - configs/ficus-rk3399_defconfig | 17 - configs/firefly-rk3399_defconfig| 17 - configs/nanopc-t4-rk3399_defconfig | 58 ++ configs/nanopi-m4-rk3399_defconfig | 58 ++ configs/nanopi-neo4-rk3399_defconfig| 58 ++ configs/orangepi-rk3399_defconfig | 58 ++ configs/puma-rk3399_defconfig | 16 - configs/rock-pi-4-rk3399_defconfig | 58 ++ configs/rock960-rk3399_defconfig| 17 - configs/rockpro64-rk3399_defconfig | 58 ++ doc/README.rockchip | 233 +- 33 files changed, 3830 insertions(+), 102 deletions(-) create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi create mode 100644 arch/arm/dts/rk3399-opp.dtsi create mode 100644 arch/arm/dts/rk3399-orangepi-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-orangepi.dts create mode 100644 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock-pi-4.dts create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rockpro64.dts create mode 100644 co
[U-Boot] [PATCH v6 03/13] Kconfig: Add default SPL_FIT_GENERATOR for rockchip
Add default SPL_FIT_GENERATOR py script for rockchip platforms if specific target enabled SPL_LOAD_FIT. So, this would help get rid of explicitly mentioning the default SPL FIT generator in defconfigs. however some targets, like puma_rk3399 still require their own FIT generator so in those cases the default will override with defconfig defined generator. Signed-off-by: Jagan Teki Reviewed-by: Paul Kocialkowski --- Kconfig | 1 + configs/chromebook_bob_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - 6 files changed, 1 insertion(+), 5 deletions(-) diff --git a/Kconfig b/Kconfig index 305b265ed7..5679a288ec 100644 --- a/Kconfig +++ b/Kconfig @@ -424,6 +424,7 @@ config SPL_FIT_GENERATOR string ".its file generator script for U-Boot FIT image" depends on SPL_FIT default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI + default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP help Specifies a (platform specific) script file to generate the FIT source file used to build the U-Boot FIT image file. This gets diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index ce3deccb8a..04e25e1d4f 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -19,7 +19,6 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index d98535357a..49b2e2e089 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 94c565efc2..fe3b9964e8 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_SPL_STACK_R_ADDR=0x8 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 6725b48970..914304bb43 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index cb5a35f4f5..5e6778ea20 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_SPL_STACK_R_ADDR=0x8 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 01/13] rockchip: dts: rk3399: Sync rk3399-opp from Linux
Sync rk3399-opp.dtsi from Linux.
Linux commit details about the rk3399-opp.dtsi sync:
"arm64: dts: rockchip: use SPDX-License-Identifier"
(sha1: 4ee99cebd486238ac433da823b95cc5f8d8a6905)
Signed-off-by: Jagan Teki
Reviewed-by: Paul Kocialkowski
---
arch/arm/dts/rk3399-opp.dtsi | 133 +++
1 file changed, 133 insertions(+)
create mode 100644 arch/arm/dts/rk3399-opp.dtsi
diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi
new file mode 100644
index 00..d6f1095abb
--- /dev/null
+++ b/arch/arm/dts/rk3399-opp.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/ {
+ cluster0_opp: opp-table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <80>;
+ clock-latency-ns = <4>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <80>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <81600>;
+ opp-microvolt = <85>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <100800>;
+ opp-microvolt = <925000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <100>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <141600>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cluster1_opp: opp-table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <80>;
+ clock-latency-ns = <4>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <80>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <81600>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <100800>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <95>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <141600>;
+ opp-microvolt = <1025000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <160800>;
+ opp-microvolt = <110>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <120>;
+ };
+ };
+
+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <80>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <29700>;
+ opp-microvolt = <80>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <925000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <110>;
+ };
+ };
+};
+
+&cpu_l0 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l1 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l2 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l3 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_b0 {
+ operating-points-v2 = <&cluster1_opp>;
+};
+
+&cpu_b1 {
+ operating-points-v2 = <&cluster1_opp>;
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v6 04/13] arm: rockchip: rk3399: Move common configs in Kconfig
Few SPL and U-Boot proper configs are common to all rk3399 target defconfigs, move them and select it from platform kconfig. Moved configs: - SPL_ATF - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - SPL_LOAD_FIT - SPL_CLK if SPL - SPL_PINCTRL if SPL - SPL_RAM if SPL - SPL_REGMAP if SPL - SPL_SYSCON if SPL - CLK - FIT - PINCTRL - RAM - REGMAP - SYSCON - DM_PMIC - DM_REGULATOR_FIXED Signed-off-by: Jagan Teki Reviewed-by: Paul Kocialkowski --- arch/arm/mach-rockchip/Kconfig | 16 configs/chromebook_bob_defconfig | 16 configs/evb-rk3399_defconfig | 16 configs/ficus-rk3399_defconfig | 16 configs/firefly-rk3399_defconfig | 16 configs/puma-rk3399_defconfig| 16 configs/rock960-rk3399_defconfig | 16 7 files changed, 16 insertions(+), 96 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b9a026abb5..dbe7f11d39 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -132,9 +132,25 @@ config ROCKCHIP_RK3399 select ARM64 select SUPPORT_SPL select SPL + select SPL_ATF + select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_LOAD_FIT + select SPL_CLK if SPL + select SPL_PINCTRL if SPL + select SPL_RAM if SPL + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT + select CLK + select FIT + select PINCTRL + select RAM + select REGMAP + select SYSCON + select DM_PMIC + select DM_REGULATOR_FIXED select DEBUG_UART_BOARD_INIT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 04e25e1d4f..fdcbabf912 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -17,16 +17,12 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -45,12 +41,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -70,16 +60,10 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 49b2e2e089..1ba9dcba62 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SPL_STACK_R_ADDR=0x8 CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -32,12 +28,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -47,16 +37,10 @@ CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index fe3b9964e8..67c62065aa 100644 --- a/configs/ficus-rk3399_def
[U-Boot] [PATCH v6 02/13] rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2
To make successful build with dts(i) files syncing from Linux 5.1-rc2
the rk3399.dtsi would require pwm2_pin_pull_down.
So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this
node is strictly not part of any commit alone, I have mentioned
Linux 5.1-rc2 tag for future reference of where would this sync
coming from.
Signed-off-by: Jagan Teki
Reviewed-by: Paul Kocialkowski
---
arch/arm/dts/rk3399.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index b53e41b4dc..99471f6287 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -2495,6 +2495,12 @@
rockchip,pins =
<1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
};
+
+
+ pwm2_pin_pull_down: pwm2-pin-pull-down {
+ rockchip,pins =
+ <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
+ };
};
pwm3a {
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v6 06/13] rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.
Linux commit details about the rk3399-nanopi4.dtsi sync:
"arm64: dts: rockchip: Add nanopi4 bluetooth"
(sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)
Signed-off-by: Jagan Teki
Reviewed-by: Paul Kocialkowski
---
arch/arm/dts/rk3399-nanopi4.dtsi | 703 +++
1 file changed, 703 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi
new file mode 100644
index 00..d325e11728
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi4.dtsi
@@ -0,0 +1,703 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * RK3399-based FriendlyElec boards device tree source
+ *
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc3v3_sys";
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-name = "vcc5v0_sys";
+ vin-supply = <&vdd_5v>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc1v8_s3";
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v0_sd: vcc3v0-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_pwr_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ regulator-name = "vcc3v0_sd";
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vbus_typec: vbus-typec {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-name = "vbus_typec";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_key>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_gpio>;
+
+ status {
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clock-parents = <&clkin_gmac>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+
[U-Boot] [PATCH v6 05/13] rockchip: rk3399: Add Orangepi RK3399 support
Add initial support for Orangepi RK3399 board.
Specification
- Rockchip RK3399
- 2GB/4GB DDR3
- 16GB eMMC
- SD card slot
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- Mini PCIe
- Sensors, Keys etc
- DC12V-2A and DC5V-2A
Commit details about Linux DTS sync:
"arm64: dts: rockchip: Add support for the Orange Pi RK3399"
(sha1: d3e71487a790979057c0fdbf32f85033639c16e6)
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 7 +
arch/arm/dts/rk3399-orangepi.dts | 771 +++
board/rockchip/evb_rk3399/MAINTAINERS| 7 +
configs/orangepi-rk3399_defconfig| 58 ++
5 files changed, 844 insertions(+)
create mode 100644 arch/arm/dts/rk3399-orangepi-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-orangepi.dts
create mode 100644 configs/orangepi-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0e2ffdb87f..6d55b0caf8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3399-evb.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
diff --git a/arch/arm/dts/rk3399-orangepi-u-boot.dtsi
b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi
new file mode 100644
index 00..236b61d78d
--- /dev/null
+++ b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-ddr3-1333.dtsi"
diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts
new file mode 100644
index 00..cf37b96a6b
--- /dev/null
+++ b/arch/arm/dts/rk3399-orangepi.dts
@@ -0,0 +1,771 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "dt-bindings/pwm/pwm.h"
+#include "dt-bindings/input/input.h"
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Orange Pi RK3399 Board";
+ compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ button-up {
+ label = "Volume Up";
+ linux,code = ;
+ press-threshold-microvolt = <10>;
+ };
+
+ button-down {
+ label = "Volume Down";
+ linux,code = ;
+ press-threshold-microvolt = <30>;
+ };
+
+ back {
+ label = "Back";
+ linux,code = ;
+ press-threshold-microvolt = <985000>;
+ };
+
+ menu {
+ label = "Menu";
+ linux,code = ;
+ press-threshold-microvolt = <1314000>;
+ };
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = ;
+ linux,input-type = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_btn>;
+ wakeup-source;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-o
[U-Boot] [PATCH v6 09/13] rockchip: rk3399: Add Nanopc T4 board support
Add initial support for Nanopc T4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- 16GB eMMC
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: Add NanoPC-T4 IR receiver"
(sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3)
Tested-by: Daniel Gröber
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 ++
arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++
board/rockchip/evb_rk3399/MAINTAINERS | 6 ++
configs/nanopc-t4-rk3399_defconfig| 58 +++
5 files changed, 163 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts
create mode 100644 configs/nanopc-t4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d2ac26b556..e048565bb6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3399-evb.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
new file mode 100644
index 00..17201bcf41
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts
b/arch/arm/dts/rk3399-nanopc-t4.dts
new file mode 100644
index 00..84433cf02b
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopc-t4.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPC-T4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPC-T4";
+ compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
+
+ vcc12v0_sys: vcc12v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1200>;
+ regulator-min-microvolt = <1200>;
+ regulator-name = "vcc12v0_sys";
+ };
+
+ vcc5v0_host0: vcc5v0-host0 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc5v0_host0";
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "Recovery";
+ linux,code = ;
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_rx>;
+ };
+};
+
+&pinctrl {
+ ir {
+ ir_rx: ir-rx {
+ /* external pullup to VCC3V3_SYS, despite being 1.8V :/
*/
+ rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdhci {
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+&u2phy0_host {
+ phy-supply = <&vcc5v0_host0>;
+};
+
+&u2phy1_host {
+ phy-supply = <&vcc5v0_host0>;
+};
+
+&vcc5v0_sys {
+ vin-supply = <&vcc12v0_sys>;
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc12v0_sys>;
+};
+
+&vbus_typec {
+ enable-active-high;
+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_sys>;
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index ae43805a6a..5917abb9c1 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h
F: configs/evb-rk3399_defconfig
F: configs/firefly-rk3399_defconfig
+NANOPC-T4
+M: Jagan Teki
+S: Maintained
+F: configs/nanopic-t4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopic-t4-u-boot.dtsi
+
NANOPI-M4
M: Jagan Teki
S: Maintained
diff --git a/configs/nanopc-t4-rk3399_defconfig
b/configs/na
[U-Boot] [PATCH v6 07/13] rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1
sdmmc cd pin is configured as RK_FUNC_GPIO which is wrong and
indeed failed to detect the sdcard on the board with below error
Card did not respond to voltage select!
So, fix it by replacing RK_FUNC_GPIO with RK_FUNC_1 which
is already defined in rk3399.dts so make use of same like
other boards.
Add these changes in -u-boot.dtsi to make Linux sync easy for future
changes.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
new file mode 100644
index 00..20db99c0b8
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+&sdmmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+};
--
2.18.0.321.gffc6fa0e3
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 08/13] rockchip: rk3399: Add Nanopi M4 board support
Add initial support for Nanopi M4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- eMMC socket
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- USB 3.0 x4
- USB Type C power and data
- GPIO1, GPIO2 expansion ports
- DC5V/3A
Commit details of rk3399-nanopi-m4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: Refine nanopi4 differences"
(sha1: c62ffaf5026d0b7633e62b2cea8450b5543c349a)
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Reviewed-by: Philipp Tomsich
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 +++
arch/arm/dts/rk3399-nanopi-m4.dts | 66 +++
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 2 +
board/rockchip/evb_rk3399/MAINTAINERS | 6 +++
configs/nanopi-m4-rk3399_defconfig| 58
6 files changed, 140 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts
create mode 100644 configs/nanopi-m4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6d55b0caf8..d2ac26b556 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3399-evb.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-nanopi-m4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
diff --git a/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
new file mode 100644
index 00..17201bcf41
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopi-m4.dts
b/arch/arm/dts/rk3399-nanopi-m4.dts
new file mode 100644
index 00..60358ab8c7
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-m4.dts
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPi M4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi M4";
+ compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_core: vcc5v0-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_core";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
+
+ vcc5v0_usb1: vcc5v0-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb2: vcc5v0-usb2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb2";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_core>;
+};
+
+&u2phy0_host {
+ phy-supply = <&vcc5v0_usb1>;
+};
+
+&u2phy1_host {
+ phy-supply = <&vcc5v0_usb2>;
+};
+
+&vbus_typec {
+ regulator-always-on;
+ vin-supply = <&vdd_5v>;
+};
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
index 20db99c0b8..05708b6f55 100644
--- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2019 Jagan Teki
*/
+#include "rk3399-u-boot.dtsi"
+
&sdmmc {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index 07ee8ce92c..ae43805a6a 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h
F: configs/evb-rk3399_defconfig
F: configs/firefly-rk3399_defconfig
+NANOPI-M4
+M: Jagan Teki
+S: Maintained
+F: configs/nanopi-m4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+
ORANGEPI-RK3399
M: Jagan Teki
S: Maintained
diff --git a/configs/nanopi-m4-rk3399_defconfig
b/configs/nanopi-m4-rk3399_defconfig
new file mode 100644
index 00..be36a28315
--- /dev/null
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG
[U-Boot] [PATCH v6 10/13] rockchip: rk3399: Add Nanopi NEO4 board support
Add initial support for Nanopi NEO4 board.
Specification
- Rockchip RK3399
- 1GB DDR3-1866
- SD card slot
- eMMC Socket
- RTL8211E 1Gbps
- AP6212 WiFI/BT
- HDMI In/Out, DP, MIPI CSI
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 5V/3A
Commit details of rk3399-nanopi-neo4.dts sync from Linux:
"arm64: dts: rockchip: Add Nanopi NEO4 initial support"
(sha1: 092470b537f19788d957aed12d835a179b606014)
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 +++
arch/arm/dts/rk3399-nanopi-neo4.dts | 50 ++
board/rockchip/evb_rk3399/MAINTAINERS | 6 +++
configs/nanopi-neo4-rk3399_defconfig| 58 +
5 files changed, 121 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts
create mode 100644 configs/nanopi-neo4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e048565bb6..ede7da23fb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -89,6 +89,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3399-gru-bob.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
+ rk3399-nanopi-neo4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
new file mode 100644
index 00..7d22528f49
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopi-neo4.dts
b/arch/arm/dts/rk3399-nanopi-neo4.dts
new file mode 100644
index 00..195410b089
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-neo4.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Amarula Solutions B.V.
+ * Author: Jagan Teki
+ */
+
+/dts-v1/;
+
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi NEO4";
+ compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_core: vcc5v0-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_core";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
+
+ vcc5v0_usb1: vcc5v0-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_core>;
+};
+
+&u2phy0_host {
+ phy-supply = <&vcc5v0_usb1>;
+};
+
+&vbus_typec {
+ regulator-always-on;
+ vin-supply = <&vdd_5v>;
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index 5917abb9c1..ed58861820 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -18,6 +18,12 @@ S: Maintained
F: configs/nanopi-m4-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+NANOPI-NEO4
+M: Jagan Teki
+S: Maintained
+F: configs/nanopi-neo4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+
ORANGEPI-RK3399
M: Jagan Teki
S: Maintained
diff --git a/configs/nanopi-neo4-rk3399_defconfig
b/configs/nanopi-neo4-rk3399_defconfig
new file mode 100644
index 00..eb9d81ae87
--- /dev/null
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_DEBUG_UART_BASE=0xFF1A
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+C
[U-Boot] [PATCH v6 11/13] rockchip: rk3399: Add Rockpro64 board support
Add initial support for Rockpro64 board.
Specification
- Rockchip RK3399
- 2/4GB Dual-Channel LPDDR3
- SD card slot
- eMMC socket
- 128Mb SPI Flash
- Gigabit ethernet
- PCIe 4X slot
- WiFI/BT module socket
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-rockpro64.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: rockpro64 dts add usb regulator"
(sha1: 6db644c79c8d45d73b56bc389aebd85fc3679beb)
'Akash' has sent an initial patch before, so I keep him as board
maintainer and I'm co-maintainer based on our conversation.
Signed-off-by: Akash Gajjar
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 +
arch/arm/dts/rk3399-rockpro64.dts | 712 ++
board/rockchip/evb_rk3399/MAINTAINERS | 7 +
configs/rockpro64-rk3399_defconfig| 58 ++
5 files changed, 784 insertions(+)
create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-rockpro64.dts
create mode 100644 configs/rockpro64-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ede7da23fb..23a9807444 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -95,6 +95,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-rock960.dtb \
+ rk3399-rockpro64.dtb \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
new file mode 100644
index 00..7bddc3acdb
--- /dev/null
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-rockpro64.dts
b/arch/arm/dts/rk3399-rockpro64.dts
new file mode 100644
index 00..1f2394e058
--- /dev/null
+++ b/arch/arm/dts/rk3399-rockpro64.dts
@@ -0,0 +1,712 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2018 Akash Gajjar
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Pine64 RockPro64";
+ compatible = "pine64,rockpro64", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
+
+ work-led {
+ label = "work";
+ default-state = "on";
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ };
+
+ diy-led {
+ label = "diy";
+ default-state = "off";
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
[U-Boot] [PATCH v6 12/13] rockchip: rk3399: Add Rock PI 4 support
Add initial support for Rock PI 4 board.
Specification
- Rockchip RK3399
- LPDDR4
- eMMC
- SD card slot
- RTL8211E 1Gbps
- HDMI In/Out, DP, MIPI DSI/CSI
- PCIe M.2
- USB 2.0, USB-3.0
- USB C Type
Commit details of rk3399-rock-pi-4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: add ROCK Pi 4 DTS support"
(sha1: 1b5715c602fda7b812af0e190eddcce2812e5417)
Signed-off-by: Akash Gajjar
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 +
arch/arm/dts/rk3399-rock-pi-4.dts | 606 ++
board/rockchip/evb_rk3399/MAINTAINERS | 7 +
configs/rock-pi-4-rk3399_defconfig| 58 +++
5 files changed, 678 insertions(+)
create mode 100644 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-rock-pi-4.dts
create mode 100644 configs/rock-pi-4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 23a9807444..a2911fa2fd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -94,6 +94,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
+ rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
new file mode 100644
index 00..7bddc3acdb
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dts
b/arch/arm/dts/rk3399-rock-pi-4.dts
new file mode 100644
index 00..4a543f2117
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-pi-4.dts
@@ -0,0 +1,606 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar
+ * Copyright (c) 2019 Pragnesh Patel
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi 4";
+ compatible = "radxa,rockpi4", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc12v_dcin: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwr_en>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_typec: vcc5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_typec_en>;
+ regulator-name = "vcc5v0_typec";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_lan: vcc3v3-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_lan";
+ re
[U-Boot] [PATCH v3 2/4] pci_ep: add Cadence PCIe endpoint driver
Add Cadence PCIe endpoint driver supporting configuration
of header, bars and MSI for device.
Signed-off-by: Ramon Fried
---
Changes in v3: None
.../pci_endpoint/cdns,cdns-pcie-ep.txt| 18 +
drivers/pci_endpoint/Kconfig | 8 +
drivers/pci_endpoint/Makefile | 1 +
drivers/pci_endpoint/pcie-cadence-ep.c| 177 ++
drivers/pci_endpoint/pcie-cadence.h | 309 ++
5 files changed, 513 insertions(+)
create mode 100644 doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
create mode 100644 drivers/pci_endpoint/pcie-cadence-ep.c
create mode 100644 drivers/pci_endpoint/pcie-cadence.h
diff --git a/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
b/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
new file mode 100644
index 00..7705430559
--- /dev/null
+++ b/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
@@ -0,0 +1,18 @@
+* Cadence PCIe endpoint controller
+
+Required properties:
+- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
+- reg: Should contain the controller register base address.
+
+Optional properties:
+- max-functions: Maximum number of functions that can be configured (default
1).
+- cdns,max-outbound-regions: Set to maximum number of outbound regions
(default 8)
+
+Example:
+
+pcie_ep@fc00 {
+ compatible = "cdns,cdns-pcie-ep";
+ reg = <0x0 0xfc00 0x0 0x0100>;
+ cdns,max-outbound-regions = <16>;
+ max-functions = /bits/ 8 <8>;
+};
diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig
index ac4f43d1ab..e00cb75b8e 100644
--- a/drivers/pci_endpoint/Kconfig
+++ b/drivers/pci_endpoint/Kconfig
@@ -14,4 +14,12 @@ config PCI_ENDPOINT
controllers that can operate in endpoint mode (as a device
connected to PCI host or bridge).
+config PCIE_CADENCE_EP
+ bool "Cadence PCIe endpoint controller"
+ depends on PCI_ENDPOINT
+ help
+ Say Y here if you want to support the Cadence PCIe controller in
+ endpoint mode. This PCIe controller may be embedded into many
+ different vendors SoCs.
+
endmenu
diff --git a/drivers/pci_endpoint/Makefile b/drivers/pci_endpoint/Makefile
index 80a1066925..0a849deb19 100644
--- a/drivers/pci_endpoint/Makefile
+++ b/drivers/pci_endpoint/Makefile
@@ -4,3 +4,4 @@
# Ramon Fried
obj-y += pci_ep-uclass.o
+obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
diff --git a/drivers/pci_endpoint/pcie-cadence-ep.c
b/drivers/pci_endpoint/pcie-cadence-ep.c
new file mode 100644
index 00..59231d340a
--- /dev/null
+++ b/drivers/pci_endpoint/pcie-cadence-ep.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019
+ * Written by Ramon Fried
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "pcie-cadence.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int cdns_write_header(struct udevice *dev, uint fn,
+struct pci_ep_header *hdr)
+{
+ struct cdns_pcie *pcie = dev_get_priv(dev);
+
+ cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG,
+ hdr->progif_code);
+ cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
+ hdr->subclass_code |
+ hdr->baseclass_code << 8);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
+ hdr->cache_line_size);
+ cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID,
+ hdr->subsys_id);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN,
+ hdr->interrupt_pin);
+
+ /*
+* Vendor ID can only be modified from function 0, all other functions
+* use the same vendor ID as function 0.
+*/
+ if (fn == 0) {
+ /* Update the vendor IDs. */
+ u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
+CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
+
+ cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
+ }
+
+ return 0;
+}
+
+static int cdns_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
+{
+ struct cdns_pcie *pcie = dev_get_priv(dev);
+ dma_addr_t bar_phys = ep_bar->phys_addr;
+ enum pci_barno bar = ep_bar->barno;
+ int flags = ep_bar->flags;
+ u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
+ u64 sz;
+
+ /* BAR size is 2^(aperture + 7) */
+ sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
+ /*
+* roundup_pow_of_two() returns an unsigned long, which is not suited
+* for 64bit values.
+*/
+ sz = 1ULL << fls64(sz - 1);
+ aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 5
Re: [U-Boot] RSA in U-Boot
> >> I've done porting linux's pkcs7/x509 parsers and they work well > >> with my UEFI secure boot patch, but I'm still looking for other options > >> as well. > >> > >> * openssl > >> Most of existing components linked to UEFI secure boot, including > >> EDK2, shim and grub, reply on this library. Why not for U-Boot? > >> The size of U-Boot UEFI code in U-Boot is already quite big, and > >> so the size of openssl won't be a big issue. > >> * mbedTLS > >> which is maintained by ARM and used with Zephyr, I guess it should > >> have small footprint. But it currently lacks pkcs7 parser. > >> > >> Any thoughts? > > > > > > Paolo, Laszlo, Ard, if you could write a new secure boot implementation > > today, which of the options above would you pick and why so? :) > > Difficult question. Ideally you'd want a library where three aspects met: > > - widely used (so that there is a diverse community that's interested in > vulnerabilities, and fixing them too) > > - easy to cross-compile for your free-standing environment (optimally > the upstream project would support being cross-compiled and packaged > stand-alone, for that free-standing environment) > > - cares about API stability > > OpenSSL is very widely used... > ...and that's where we can stop in the list :) It's also license-incompatible with U-Boot's GPLv2 I think. I guess grub can use it because GPLv3 and Apache v2 can be combined just fine. Reusing Linux's code seems like the best match. Paolo ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 13/13] doc: rockchip: Add global doc for rk3399 build/flash
Since rockchip have an individual doc/README.rockchip, it would be better to update the same instead of maintaining it separately in board files. So, add the documentation for rk3399 - procedure to build for Rockchip miniloader and U-Boot SPL options - procedure to boot from SD for Rockchip miniloader and U-Boot SPL options - procedure to build ATF, PMU M0 firmware for puma boards - add boot logs of each option, so-that it would help for future boards porting Signed-off-by: Jagan Teki Reviewed-by: Philipp Tomsich --- doc/README.rockchip | 233 +++- 1 file changed, 232 insertions(+), 1 deletion(-) diff --git a/doc/README.rockchip b/doc/README.rockchip index ec10ebbc26..ca4d6473b0 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -88,10 +88,92 @@ One RV3188 baord is supported: For example: +1. To build RK3288 board: + CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all -(or you can use another cross compiler if you prefer) +(or you can use another cross compiler if you prefer) + +2. To build RK3399 board: + + Option 1: Package the image with Rockchip miniloader: + + - Compile U-Boot + + => cd /path/to/u-boot + => make nanopi-neo4-rk3399_defconfig + => make + => make u-boot.itb + + - Get the rkbin + + => git clone https://github.com/rockchip-linux/rkbin.git + + - Create trust.img + + => cd /path/to/rkbin + => ./tools/trust_merger RKTRUST/RK3399TRUST.ini + + - Create uboot.img + + => cd /path/to/rkbin + => ./tools/loaderimage --pack --uboot /path/to/u-boot/u-boot-dtb.bin uboot.img + + (Get trust.img and uboot.img) + + Option 2: Package the image with SPL: + + - We need the Python elftools.elf.elffile library for make_fit_atf.py to work + + => sudo apt-get install python-pyelftools + + - Export cross compiler path for aarch64 + + - Compile ATF + + For Puma board. + + => git clone git://git.theobroma-systems.com/arm-trusted-firmware.git + => cd arm-trusted-firmware + => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + + (copy bl31.bin into U-Boot root dir) + => cp build/rk3399/release/bl31/bl31.bin /path/to/u-boot/bl31-rk3399.bin + + For rest of rk3399 boards. + + => git clone https://github.com/ARM-software/arm-trusted-firmware.git + => cd arm-trusted-firmware + + (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-) + => make realclean + => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 + + (copy bl31.elf into U-Boot root dir) + => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot + + - Compile PMU M0 firmware + + This is optional for most of the rk3399 boards and required only for Puma board. + + => git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git + => cd rk3399-cortex-m0 + (export cross compiler path for Cortex-M0 PMU) + => make CROSS_COMPILE=arm-cortex_m0-eabi- + + (copy rk3399m0.bin into U-Boot root dir) + => cp rk3399m0.bin /path/to/u-boot + + - Compile U-Boot + + => cd /path/to/u-boot + => make orangepi-rk3399_defconfig + => make + => make u-boot.itb + + (Get spl/u-boot-spl-dtb.bin, u-boot.itb images and some boards would get + spl/u-boot-spl.bin since it doesn't enable CONFIG_SPL_OF_CONTROL) Writing to the board with USB = @@ -225,6 +307,153 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out truncate -s %2048 u-boot.bin cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out +Booting from an SD card on RK3399 += + +To write an image that boots from an SD card (assumed to be /dev/sdc): + +Option 1: Package the image with Rockchip miniloader: + + - Create idbloader.img + +=> cd /path/to/u-boot +=> ./tools/mkimage -n rk3399 -T rksd -d /path/to/rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin idbloader.img +=> cat /path/to/rkbin/bin/rk33/rk3399_miniloader_v1.19.bin >> idbloader.img + + - Write idbloader.img at 64 sector + +=> sudo dd if=idbloader.img of=/dev/sdc seek=64 + + - Write trust.img at 24576 + +=> sudo dd if=trust.img of=/dev/sdc seek=24576 + + - Write uboot.img at 16384 sector + +=> sudo dd if=uboot.img of=/dev/sdc seek=16384 +=> sync + +Put this SD (or micro-SD) card into your board and reset it. You should see +something like: + +DDR Version 1.20 20190314 +In +Channel 0: DDR3, 933MHz +Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB +no stride +ch 0 ddrconfig = 0x101, ddrsize = 0x20 +pmugrf_os_reg[2] = 0x10006281, stride = 0x17 +OUT +Boot1: 2019-03-14, version: 1.19 +CPUId = 0x0 +ChipType = 0x10, 239 +mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000 +mmc: ERROR: Card did not respond to voltage select! +emmc reinit +mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000 +mmc: ERROR: Card did not respon
[U-Boot] [PATCH v3 1/4] drivers: pci_ep: Introduce UCLASS_PCI_EP uclass
Introduce new UCLASS_PCI_EP class for handling PCI endpoint
devices, allowing to set various attributes of the PCI endpoint
device, such as:
* configuration space header
* BAR definitions
* outband memory mapping
* start/stop PCI link
Signed-off-by: Ramon Fried
---
Changes in v3: None
MAINTAINERS | 6 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/pci_endpoint/Kconfig | 17 ++
drivers/pci_endpoint/Makefile| 6 +
drivers/pci_endpoint/pci_ep-uclass.c | 211 ++
include/dm/uclass-id.h | 1 +
include/pci_ep.h | 414 +++
8 files changed, 658 insertions(+)
create mode 100644 drivers/pci_endpoint/Kconfig
create mode 100644 drivers/pci_endpoint/Makefile
create mode 100644 drivers/pci_endpoint/pci_ep-uclass.c
create mode 100644 include/pci_ep.h
diff --git a/MAINTAINERS b/MAINTAINERS
index b9cb686a05..9d95ef826b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -626,6 +626,12 @@ M: Simon Glass
S: Maintained
F: tools/patman/
+PCI Endpoint
+M: Ramon Fried
+S: Maintained
+F: drivers/pci_endpoint/
+F: include/pci_ep.h
+
POWER
M: Jaehoon Chung
S: Maintained
diff --git a/drivers/Kconfig b/drivers/Kconfig
index e6702eced4..258dfa19e8 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -64,6 +64,8 @@ source "drivers/nvme/Kconfig"
source "drivers/pci/Kconfig"
+source "drivers/pci_endpoint/Kconfig"
+
source "drivers/pch/Kconfig"
source "drivers/pcmcia/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..480b97ef58 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -85,6 +85,7 @@ obj-$(CONFIG_FPGA) += fpga/
obj-y += misc/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NVME) += nvme/
+obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/
obj-y += pcmcia/
obj-y += dfu/
obj-$(CONFIG_PCH) += pch/
diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig
new file mode 100644
index 00..ac4f43d1ab
--- /dev/null
+++ b/drivers/pci_endpoint/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# PCI Endpoint Support
+#
+
+menu "PCI Endpoint"
+
+config PCI_ENDPOINT
+ bool "PCI Endpoint Support"
+ depends on DM
+ help
+ Enable this configuration option to support configurable PCI
+ endpoints. This should be enabled if the platform has a PCI
+ controllers that can operate in endpoint mode (as a device
+ connected to PCI host or bridge).
+
+endmenu
diff --git a/drivers/pci_endpoint/Makefile b/drivers/pci_endpoint/Makefile
new file mode 100644
index 00..80a1066925
--- /dev/null
+++ b/drivers/pci_endpoint/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019
+# Ramon Fried
+
+obj-y += pci_ep-uclass.o
diff --git a/drivers/pci_endpoint/pci_ep-uclass.c
b/drivers/pci_endpoint/pci_ep-uclass.c
new file mode 100644
index 00..2f9c70398d
--- /dev/null
+++ b/drivers/pci_endpoint/pci_ep-uclass.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PCI Endpoint uclass
+ *
+ * Based on Linux PCI-EP driver written by
+ * Kishon Vijay Abraham I
+ *
+ * Copyright (c) 2019
+ * Written by Ramon Fried
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header
*hdr)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->write_header)
+ return -ENOSYS;
+
+ return ops->write_header(dev, fn, hdr);
+}
+
+int pci_ep_read_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->read_header)
+ return -ENOSYS;
+
+ return ops->read_header(dev, fn, hdr);
+}
+
+int pci_ep_set_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+ int flags = ep_bar->flags;
+
+ /* Some basic bar validity checks */
+ if (ep_bar->barno > BAR_5 || ep_bar < BAR_0)
+ return -EINVAL;
+
+ if ((ep_bar->barno == BAR_5 &&
+(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) ||
+ ((flags & PCI_BASE_ADDRESS_SPACE_IO) &&
+(flags & PCI_BASE_ADDRESS_IO_MASK)) ||
+ (upper_32_bits(ep_bar->size) &&
+!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
+ return -EINVAL;
+
+ if (!ops->set_bar)
+ return -ENOSYS;
+
+ return ops->set_bar(dev, func_no, ep_bar);
+}
+
+int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
+ enum pci_barno barno)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ /* Some basic bar validity checks */
+ if (barno > BAR_5 || barno < BAR_0)
+ return -EINVAL;
+
+ if (!ops->read_bar)
+
[U-Boot] [PATCH v3 4/4] test: pci_ep: add basic pci_ep tests
Add basic PCI endpoint sandbox testing.
Signed-off-by: Ramon Fried
---
Changes in v3:
- Added more testing of sandbox driver
arch/sandbox/include/asm/test.h | 8 +
test/dm/Makefile| 1 +
test/dm/pci_ep.c| 64 +
3 files changed, 73 insertions(+)
create mode 100644 test/dm/pci_ep.c
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index fc52f47f82..cfb30cb376 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -185,4 +185,12 @@ int sandbox_get_beep_frequency(struct udevice *dev);
*/
int sandbox_get_pch_spi_protect(struct udevice *dev);
+/**
+ * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count
+ *
+ * @dev: Device to check
+ * @return irq count
+ */
+int sandbox_get_pci_ep_irq_count(struct udevice *dev);
+
#endif
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 49857c5092..fe36f8df47 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -30,6 +30,7 @@ obj-y += ofnode.o
obj-$(CONFIG_OSD) += osd.o
obj-$(CONFIG_DM_VIDEO) += panel.o
obj-$(CONFIG_DM_PCI) += pci.o
+obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o
obj-$(CONFIG_PCH) += pch.o
obj-$(CONFIG_PHY) += phy.o
obj-$(CONFIG_POWER_DOMAIN) += power-domain.o
diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c
new file mode 100644
index 00..101f861751
--- /dev/null
+++ b/test/dm/pci_ep.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Ramon Fried
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Test that sandbox PCI EP works correctly */
+static int dm_test_pci_ep_base(struct unit_test_state *uts)
+{
+ struct udevice *bus;
+ struct pci_bar tmp_bar;
+ struct pci_ep_header tmp_header;
+ int i;
+
+ struct pci_ep_header ep_header = {
+ .vendorid = 0x1234,
+ .deviceid = 0x2020,
+ .revid = 1,
+ .interrupt_pin = PCI_INTERRUPT_INTA,
+ };
+
+ struct pci_bar bar = {
+ .phys_addr = 0x8000,
+ .size = 0x10,
+ .barno = BAR_0,
+ .flags = PCI_BASE_ADDRESS_MEM_TYPE_64 |
+ PCI_BASE_ADDRESS_MEM_PREFETCH,
+ };
+
+ ut_assertok(uclass_get_device(UCLASS_PCI_EP, 0, &bus));
+ ut_assertnonnull(bus);
+
+ ut_assertok(pci_ep_write_header(bus, 0, &ep_header));
+ ut_assertok(pci_ep_read_header(bus, 0, &tmp_header));
+ ut_asserteq_mem(&tmp_header, &ep_header, sizeof(ep_header));
+
+ ut_assertok(pci_ep_set_msi(bus, 0, 4));
+ ut_asserteq(pci_ep_get_msi(bus, 0), 4);
+
+ ut_assertok(pci_ep_set_msix(bus, 0, 360));
+ ut_asserteq(pci_ep_get_msix(bus, 0), 360);
+
+ ut_assertok(pci_ep_set_bar(bus, 0, &bar));
+
+ ut_assertok(pci_ep_read_bar(bus, 0, &tmp_bar, BAR_0));
+ ut_asserteq_mem(&tmp_bar, &bar, sizeof(bar));
+
+ for (i = 0; i < 10; i++)
+ ut_assertok(pci_ep_raise_irq(bus, 0, 1, PCI_EP_IRQ_LEGACY));
+
+ ut_asserteq(sandbox_get_pci_ep_irq_count(bus), 10);
+ return 0;
+}
+
+DM_TEST(dm_test_pci_ep_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
--
2.21.0
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 0/4] Add Cadence PCIe endpoint driver with new uclass
This patchset adds support for new uclass, UCLASS_PCI_EP allowing new set of PCI endpoint drivers. Included in the patch is also a driver for Cadence PCIe endpoint. Changes in V2: - Removed "pci.h: add missing maskbit" as it was already merged by Simon. - Added PCI endpoint sandbox driver - Added testing for sandbox driver - Addressed issues raised by Simon in UCLASS_PCI_EP class implementation Changes in v3: - Added function to read bar config - Fixed a bug in set MSI implementation (missing -1) - Elaborate a bit more in comments - Added MAINTAINER entry for PCI Endpoint - Added more description to commit message and kmsg - Removed some unused functionality that can't be tested. - Removed entries from sandbox config and added implies and select to arch/Kconfig sandbox entry. - Added more testing of sandbox driver Ramon Fried (4): drivers: pci_ep: Introduce UCLASS_PCI_EP uclass pci_ep: add Cadence PCIe endpoint driver pci_ep: add pci endpoint sandbox driver test: pci_ep: add basic pci_ep tests MAINTAINERS | 6 + arch/Kconfig | 2 + arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/test.h | 8 + .../pci_endpoint/cdns,cdns-pcie-ep.txt| 18 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/pci_endpoint/Kconfig | 34 ++ drivers/pci_endpoint/Makefile | 8 + drivers/pci_endpoint/pci_ep-uclass.c | 211 + drivers/pci_endpoint/pcie-cadence-ep.c| 177 drivers/pci_endpoint/pcie-cadence.h | 309 + drivers/pci_endpoint/sandbox-pci_ep.c | 182 include/dm/uclass-id.h| 1 + include/pci_ep.h | 414 ++ test/dm/Makefile | 1 + test/dm/pci_ep.c | 64 +++ 17 files changed, 1442 insertions(+) create mode 100644 doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt create mode 100644 drivers/pci_endpoint/Kconfig create mode 100644 drivers/pci_endpoint/Makefile create mode 100644 drivers/pci_endpoint/pci_ep-uclass.c create mode 100644 drivers/pci_endpoint/pcie-cadence-ep.c create mode 100644 drivers/pci_endpoint/pcie-cadence.h create mode 100644 drivers/pci_endpoint/sandbox-pci_ep.c create mode 100644 include/pci_ep.h create mode 100644 test/dm/pci_ep.c -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/4] pci_ep: add pci endpoint sandbox driver
Add a dummy PCI endpoint for sandbox.
Supporting only a single function, it allows setting
and reading header configuration.
Signed-off-by: Ramon Fried
---
Changes in v3:
- Added more description to commit message and kmsg
- Removed some unused functionality that can't be
tested.
- Removed entries from sandbox config and added implies and select
to arch/Kconfig sandbox entry.
arch/Kconfig | 2 +
arch/sandbox/dts/test.dts | 4 +
drivers/pci_endpoint/Kconfig | 9 ++
drivers/pci_endpoint/Makefile | 1 +
drivers/pci_endpoint/sandbox-pci_ep.c | 182 ++
5 files changed, 198 insertions(+)
create mode 100644 drivers/pci_endpoint/sandbox-pci_ep.c
diff --git a/arch/Kconfig b/arch/Kconfig
index 2f3d07c13a..379255c12c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -89,6 +89,7 @@ config SANDBOX
select DM_SPI_FLASH
select HAVE_BLOCK_DEVICE
select LZO
+ select PCI_ENDPOINT
select SPI
select SUPPORT_OF_CONTROL
imply BITREVERSE
@@ -118,6 +119,7 @@ config SANDBOX
imply VIRTIO_BLK
imply VIRTIO_NET
imply DM_SOUND
+ imply PCI_SANDBOX_EP
imply PCH
config SH
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 8b2d6451c6..001dc302ed 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -475,6 +475,10 @@
};
};
+ pci_ep: pci_ep {
+ compatible = "sandbox,pci_ep";
+ };
+
probing {
compatible = "simple-bus";
test1 {
diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig
index e00cb75b8e..19cfa0aafb 100644
--- a/drivers/pci_endpoint/Kconfig
+++ b/drivers/pci_endpoint/Kconfig
@@ -22,4 +22,13 @@ config PCIE_CADENCE_EP
endpoint mode. This PCIe controller may be embedded into many
different vendors SoCs.
+config PCI_SANDBOX_EP
+ bool "Sandbox PCIe endpoint controller"
+ depends on PCI_ENDPOINT
+ help
+ Say Y here if you want to support the Sandbox PCIe controller in
+ endpoint mode.
+ The sandbox driver act as a dummy driver which stores and
+ retrieves PCIe endpoint configuration as is.
+
endmenu
diff --git a/drivers/pci_endpoint/Makefile b/drivers/pci_endpoint/Makefile
index 0a849deb19..3cd987259d 100644
--- a/drivers/pci_endpoint/Makefile
+++ b/drivers/pci_endpoint/Makefile
@@ -5,3 +5,4 @@
obj-y += pci_ep-uclass.o
obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
+obj-$(CONFIG_PCI_SANDBOX_EP) += sandbox-pci_ep.o
diff --git a/drivers/pci_endpoint/sandbox-pci_ep.c
b/drivers/pci_endpoint/sandbox-pci_ep.c
new file mode 100644
index 00..0258433d8f
--- /dev/null
+++ b/drivers/pci_endpoint/sandbox-pci_ep.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Ramon Fried
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct sandbox_pci_ep_priv - private data for driver
+ * @hdr: Stores the EP device header
+ * @msix: required MSIx count;
+ * @msi: required MSI count;
+ */
+struct sandbox_pci_ep_priv {
+ struct pci_ep_header hdr;
+ struct pci_bar bars[6];
+ int msix;
+ int msi;
+ int irq_count;
+};
+
+/* Method exported for testing purposes */
+int sandbox_get_pci_ep_irq_count(struct udevice *dev)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ return priv->irq_count;
+}
+
+static const struct udevice_id sandbox_pci_ep_ids[] = {
+ { .compatible = "sandbox,pci_ep" },
+ { }
+};
+
+static int sandbox_write_header(struct udevice *dev, uint fn,
+ struct pci_ep_header *hdr)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ memcpy(&priv->hdr, hdr, sizeof(*hdr));
+
+ return 0;
+}
+
+static int sandbox_read_header(struct udevice *dev, uint fn,
+ struct pci_ep_header *hdr)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ memcpy(hdr, &priv->hdr, sizeof(*hdr));
+
+ return 0;
+}
+
+static int sandbox_set_bar(struct udevice *dev, uint fn,
+ struct pci_bar *ep_bar)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+ int bar_idx;
+
+ if (fn > 0)
+ return -ENODEV;
+
+ bar_idx = ep_bar->barno;
+
+ memcpy(&priv->bars[bar_idx], ep_bar, sizeof(*ep_bar));
+
+ return 0;
+}
+
+static int sandbox_read_bar(struct udevice *dev, uint fn,
+ struct pci_bar *ep_bar, enum pci_barno barno)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+ int bar_idx;
+
+ if (fn > 0)
+ return -ENODEV;
+
+ bar_idx = ep_bar->barno;
+
+ memcpy(ep_bar,
Re: [U-Boot] [PATCH 4/4] Update defconfig for minized.
pá 26. 4. 2019 v 7:11 odesílatel Philip Balister napsal: > On 04/25/2019 05:33 PM, Michal Simek wrote: > > On 17. 04. 19 19:46, Philip Balister wrote: > >> Signed-off-by: Philip Balister > >> --- > >> configs/zynq_minized_defconfig | 16 +--- > >> 1 file changed, 5 insertions(+), 11 deletions(-) > >> > >> diff --git a/configs/zynq_minized_defconfig > b/configs/zynq_minized_defconfig > >> index d61659f785..6c56b9b9b9 100644 > >> --- a/configs/zynq_minized_defconfig > >> +++ b/configs/zynq_minized_defconfig > >> @@ -1,4 +1,5 @@ > >> CONFIG_ARM=y > >> +CONFIG_SYS_CONFIG_NAME="zynq_minized" > > > > this is here because of 3/4 > > Yes. Should we be looking at cleaning up the default zynq environment? > yes. > > > > >> CONFIG_ARCH_ZYNQ=y > >> CONFIG_SYS_TEXT_BASE=0x400 > >> CONFIG_SPL=y > >> @@ -12,9 +13,9 @@ CONFIG_FIT_SIGNATURE=y > >> CONFIG_FIT_VERBOSE=y > >> CONFIG_SPL_STACK_R=y > >> CONFIG_SPL_OS_BOOT=y > >> +CONFIG_SPL_SPI_LOAD=y > >> CONFIG_SYS_PROMPT="Zynq> " > >> -CONFIG_CMD_THOR_DOWNLOAD=y > >> -CONFIG_CMD_DFU=y > >> +# CONFIG_CMD_ELF is not set > > > > What's the reason? > > I'm not a DFU expert. The time I saw it used, the board needed to be a > USB device. The minized only supports USB host. The micro usb connectors > are for serial/jtag and an extra power supply. > ok. Then dfu can be removed. I was more curious about disabling CMD_ELF then dfu. > > As I recall DFU has a maximum payload size that is smaller then the > available emmc. This can be really confusing to uncover. > > > > >> # CONFIG_CMD_FLASH is not set > >> CONFIG_CMD_FPGA_LOADBP=y > >> CONFIG_CMD_FPGA_LOADFS=y > >> @@ -25,15 +26,12 @@ CONFIG_CMD_MMC=y > >> CONFIG_CMD_SF=y > >> CONFIG_CMD_USB=y > >> # CONFIG_CMD_SETEXPR is not set > >> -CONFIG_CMD_TFTPPUT=y > >> CONFIG_CMD_CACHE=y > >> CONFIG_CMD_EXT4_WRITE=y > >> CONFIG_DEFAULT_DEVICE_TREE="zynq-minized" > >> CONFIG_ENV_IS_IN_SPI_FLASH=y > >> -CONFIG_NET_RANDOM_ETHADDR=y > >> +# CONFIG_NET is not set > > > > If there is usb host you maybe need this for usb to ethernet convertors. > > > > There is USB host. Do many people use usb ethernet convertors with u-boot? > if board has no ethernet port then ethernet convertors are the way to go. I use that a lot with ultra96. > > >> CONFIG_SPL_DM_SEQ_ALIAS=y > >> -CONFIG_DFU_MMC=y > >> -CONFIG_DFU_RAM=y > >> CONFIG_FPGA_XILINX=y > >> CONFIG_FPGA_ZYNQPL=y > >> CONFIG_DM_GPIO=y > >> @@ -44,11 +42,6 @@ CONFIG_SF_DEFAULT_SPEED=3000 > >> CONFIG_SPI_FLASH_SPANSION=y > >> CONFIG_SPI_FLASH_STMICRO=y > >> CONFIG_SPI_FLASH_WINBOND=y > >> -CONFIG_PHY_MARVELL=y > >> -CONFIG_PHY_REALTEK=y > >> -CONFIG_PHY_XILINX=y > >> -CONFIG_MII=y > >> -CONFIG_ZYNQ_GEM=y > > > > if there is no physical port we can remove this. > > > > OK > > >> CONFIG_DEBUG_UART_ZYNQ=y > >> CONFIG_ZYNQ_SERIAL=y > >> CONFIG_ZYNQ_QSPI=y > >> @@ -63,3 +56,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 > >> CONFIG_CI_UDC=y > >> CONFIG_USB_GADGET_DOWNLOAD=y > >> CONFIG_USB_FUNCTION_THOR=y > >> +CONFIG_REGEX=y > >> > > > > Don't have this board to say what it is reasonable. I see some usbs on > > pictures that's why maybe that DFU stuff can stay there too. > > > > Please put it to description in v2. > > > Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] zynq_minized: Add configuration header file for board specific environment.
pá 26. 4. 2019 v 6:59 odesílatel Philip Balister
napsal:
> On 04/25/2019 05:30 PM, Michal Simek wrote:
> > On 17. 04. 19 19:46, Philip Balister wrote:
> >> Signed-off-by: Philip Balister
> >> ---
> >> include/configs/zynq_minized.h | 54 ++
> >> 1 file changed, 54 insertions(+)
> >> create mode 100644 include/configs/zynq_minized.h
> >>
> >> diff --git a/include/configs/zynq_minized.h
> b/include/configs/zynq_minized.h
> >> new file mode 100644
> >> index 00..6d89e3da29
> >> --- /dev/null
> >> +++ b/include/configs/zynq_minized.h
> >> @@ -0,0 +1,54 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * (C) Copyright 2019 Philip Balister .
> >> + *
> >> + * Configuration settings for the MiniZed board
> >> + * See zynq-common.h for Zynq common configs
> >> + */
> >> +
> >> +#ifndef __CONFIG_ZYNQ_MINIZED_H
> >> +#define __CONFIG_ZYNQ_MINIZED_H
> >> +
> >> +#define CONFIG_EXTRA_ENV_SETTINGS \
> >> +"fit_image=fitImage\0" \
> >> +"bit_file=fpga.bit\0" \
> >> +"load_addr=0x200\0" \
> >> +"fit_size=0x80\0" \
> >> +"flash_off=0x10\0" \
> >> +"nor_flash_off=0xE210\0"\
> >> +"fdt_high=0x2000\0" \
> >> +"initrd_high=0x2000\0" \
> >> +"loadbootenv_addr=0x200\0" \
> >> +"fdt_addr_r=0x1f0\0"\
> >> +"kernel_addr_r=0x200\0" \
> >> +"ramdisk_addr_r=0x310\0"\
> >> +"bootenv=uEnv.txt\0" \
> >> +"bootenv_dev=mmc\0" \
> >> +"qspiboot=echo Copying FIT from QSPI to RAM... (Not Yet) \0" \
> >> +"mmcboot= " \
> >> +"echo Copying fpga.bit from MMC and loading FPGA... && " \
> >> +"load mmc 0:1 ${load_addr} /boot/${bit_file} && " \
> >> +"fpga loadb 0 ${load_addr} ${filesize} && " \
> >> +"echo Copying FIT from MMC to RAM... && " \
> >> +"load mmc 0:1 ${load_addr} /boot/${fit_image} && " \
> >> +"setenv bootargs root=/dev/mmcblk1p1 rootwait && " \
> >> +"bootm ${load_addr}\0" \
> >> +"usbboot=if usb start; then " \
> >> +"echo Copying fpga.bit from USB and loading FPGA... && " \
> >> +"load usb 0 ${load_addr} /boot/${bit_file} && " \
> >> +"fpga loadb 0 ${load_addr} ${filesize} && " \
> >> +"echo Copying FIT from USB to RAM... && " \
> >> +"load usb 0 ${load_addr} /boot/${fit_image} && " \
> >> +"setenv bootargs root=/dev/sda1 rootwait && " \
> >> +"bootm ${load_addr}; fi\0" \
> >> +"usbrecover=if usb start; then " \
> >> +"echo Copying fpga.bit from USB and loading FPGA... && " \
> >> +"load usb 0 ${load_addr} ${bit_file} && " \
> >> +"fpga loadb 0 ${load_addr} ${filesize} && " \
> >> +"echo Copying FIT from USB to RAM... && " \
> >> +"load usb 0 ${load_addr} ${fit_image} && " \
> >> +"bootm ${load_addr}; fi\0"
> >> +
> >> +#include
> >> +
> >> +#endif /* __CONFIG_ZYNQ_MINIZED_H */
> >>
> >
> > We are moving towards distro boot that's why if this can't be done via
> > distro boot then it should be extended. sd/mmc boot mode is handled
> > there properly that's why I have strong doubts that this is really
> > necessary.
>
> Are there any good distro boot examples or write ups? Basically, I am
> trying to make it easy for people to work with the minized. Well at
> least easy for me :)
>
Take a look at this.
https://github.com/Xilinx/u-boot-xlnx/tree/master/board/xilinx/bootscripts
There are also other bootscripts for other boards.
M
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Re: [U-Boot] [PATCH 2/4] mini-zed: Update mini-zed dts so we can use it for SPL.
pá 26. 4. 2019 v 6:18 odesílatel Philip Balister
napsal:
> On 04/25/2019 05:28 PM, Michal Simek wrote:
> > On 17. 04. 19 19:46, Philip Balister wrote:
> >> Signed-off-by: Philip Balister
> >> ---
> >> arch/arm/dts/zynq-minized.dts | 1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> diff --git a/arch/arm/dts/zynq-minized.dts
> b/arch/arm/dts/zynq-minized.dts
> >> index 525921ee7b..9ad7f090fe 100644
> >> --- a/arch/arm/dts/zynq-minized.dts
> >> +++ b/arch/arm/dts/zynq-minized.dts
> >> @@ -38,6 +38,7 @@
> >> };
> >>
> >> &qspi {
> >> +u-boot,dm-pre-reloc;
> >> status = "okay";
> >> is-dual = <0>;
> >> num-cs = <1>;
> >>
> >
> > I don't have 1/4 in my inbox but I see it on web. That ps7 config should
> > be tuned and fixed. We have converted others based on miami boards
> > that's why please do it too.
>
> What do you mean by tuned and fixed? My goal here is get to a u-boot we
> can actually boot the minized with and do some useful things.
>
Just take a look at other boards and how that init files looks like.
It is not straight copy of what xilinx tools generate. Comments are
removed. Unused functions are removed.
Coding style is fixed, etc.
Thanks,
Michal
--
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w: www.monstr.eu p: +42-0-721842854
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Re: [U-Boot] fit: Add support for printing more than one FPGA node name
On Fri, Apr 26, 2019 at 06:12:40AM +, Chee, Tien Fong wrote:
> On Mon, 2019-04-22 at 13:29 -0400, Tom Rini wrote:
> > On Wed, Feb 13, 2019 at 08:32:24PM +0800, tien.fong.c...@intel.com
> > wrote:
> >
> > >
> > > From: Tien Fong Chee
> > >
> > > This would print out all the FPGA node names setting to fpga
> > > property.
> > >
> > > Signed-off-by: Tien Fong Chee
> > > ---
> > > common/image-fit.c | 14 +++---
> > > 1 files changed, 11 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/common/image-fit.c b/common/image-fit.c
> > > index ac901e1..816e17d 100644
> > > --- a/common/image-fit.c
> > > +++ b/common/image-fit.c
> > > @@ -263,6 +263,7 @@ static void fit_conf_print(const void *fit, int
> > > noffset, const char *p)
> > > int ret;
> > > int fdt_index, loadables_index;
> > > int ndepth;
> > > + ulong count;
> > >
> > > /* Mandatory properties */
> > > ret = fit_get_desc(fit, noffset, &desc);
> > > @@ -299,9 +300,16 @@ static void fit_conf_print(const void *fit,
> > > int noffset, const char *p)
> > > printf("%s\n", uname);
> > > }
> > >
> > > - uname = fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
> > > - if (uname)
> > > - printf("%s FPGA: %s\n", p, uname);
> > > + count = fit_conf_get_prop_node_count(fit, noffset,
> > > FIT_FPGA_PROP);
> > > +
> > > + for (ndepth = 0; ndepth < count; ndepth++) {
> > > + int images_noffset =
> > > fit_conf_get_prop_node_index(fit, noffset,
> > > + FIT_FPGA_PROP,
> > > ndepth);
> > > + uname = fit_get_name(fit, images_noffset, NULL);
> > > +
> > > + if (uname)
> > > + printf("%s FPGA: %s\n", p,
> > > uname);
> > > + }
> > >
> > > /* Print out all of the specified loadables */
> > > for (loadables_index = 0;
> > While I'm fine with the conceptual change here, both
> > fit_conf_get_prop_node_count / fit_conf_get_prop_node_index are
> > defined
> > later in the file and while public functions not documented in a
> > header.
> > Can you please do a patch that does so first, as we otherwise get a
> > warning? Thanks!
> The header file in this patch https://patchwork.ozlabs.org/patch/1058289/,
> unfortunately the review taking a bit longer than what i expected.
>
> I would update you once the whole series patches are accepted.
Ah, OK, I'll hold off until the other series is complete.
--
Tom
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Re: [U-Boot] [U-Boot, 2/6] board/BuR/common: cosmetic: move 'overwrite_console' up to more related stuff
On Wed, Apr 10, 2019 at 02:13:12PM +0200, Hannes Schmelzer wrote: > Signed-off-by: Hannes Schmelzer Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 3/6] board/BuR/common: add 'brdefaulip_setup' function
On Wed, Apr 10, 2019 at 02:13:13PM +0200, Hannes Schmelzer wrote: > Many B&R boards are equipped with an I2C-EEPROM where various > information can be stored. > > Today there is only a single byte for 'board_id' used. > > We write this 'board_id' into environment for later use during boot. > > If the value != 0xFF, meaning the byte is programmed, we modify the > "brdefaultip" environment variable for setting an IP-Address based on > board_id. > > Signed-off-by: Hannes Schmelzer Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/6] board/BuR/common: prepare for compiling common into non AM33XX boards
On Wed, Apr 10, 2019 at 02:13:11PM +0200, Hannes Schmelzer wrote: > Today the BuR common stuff is only used on AM33XX boards. In future we > plan to have many other platforms than AM33XX so we have to move arch- > specific #include(s) to responsible #ifdef sections. By the way we drop > unneeded #include(s). > > Signed-off-by: Hannes Schmelzer Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 4/6] board/BuR/common: add br resetcontoller implementation
On Wed, Apr 10, 2019 at 02:13:14PM +0200, Hannes Schmelzer wrote: > On many B&R boards we have a reset-controller, responsible for very > early board-bringup (voltages, clocks, ...) and bootmode selection. > > To be ready for adding more B&R boards to source tree while avoiding > duplicate code, we add the resetcontroller implementation to the common > part of B&R boards. > > Signed-off-by: Hannes Schmelzer Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,5/6] board/BuR/brxre1: cosmetic cleanup
On Wed, Apr 10, 2019 at 02:13:15PM +0200, Hannes Schmelzer wrote: > - fixup coding style > - drop unused 'PUSH_KEY' define > > Signed-off-by: Hannes Schmelzer Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 6/6] board/BuR/brxre1: use common resetcontroller implementation
On Wed, Apr 10, 2019 at 02:13:16PM +0200, Hannes Schmelzer wrote: > The handling of regarding bootmode and early setup has been moved to > central location 'common/br_resetc.c', so use this on brxre1 board. > > Signed-off-by: Hannes Schmelzer Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,1/1] disk: part: fix typo
On Wed, Apr 10, 2019 at 06:59:26PM +0200, Heinrich Schuchardt wrote: > %g/rathen then/rather than/ > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 2/7] firmware: ti_sci: Add support for firewall management
On Fri, Apr 12, 2019 at 12:54:43PM -0400, Andrew F. Davis wrote: > TI-SCI message protocol provides support for controlling the firewall > configurations available in SoC. > > Introduce support for the set of TI-SCI message protocol APIs that > provide us with this capability of controlling firewalls. > > Signed-off-by: Andrew F. Davis > Reviewed-by: Tom Rini > Reviewed-by: Andreas Dannenberg Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] tools/Makefile: get openssl CFLAGS from pkg-config
On Thu, Apr 11, 2019 at 12:58:49AM +0200, Pierre Bourdon wrote: > Fixes building mkimage on systems where OpenSSL header files do not > live in the standard include path. > > Signed-off-by: Pierre Bourdon Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 3/7] firmware: ti_sci: Modify auth_boot TI-SCI API to match new version
On Fri, Apr 12, 2019 at 12:54:44PM -0400, Andrew F. Davis wrote: > SYSFW version 2019.01 introduces a slightly modified version of this API, > add support for it here. > > Signed-off-by: Andrew F. Davis > Reviewed-by: Tom Rini > Reviewed-by: Andreas Dannenberg Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 7/7] doc: Update info on using K3 secure devices
On Fri, Apr 12, 2019 at 12:54:48PM -0400, Andrew F. Davis wrote: > Signed-off-by: Andrew F. Davis > Reviewed-by: Tom Rini > Reviewed-by: Andreas Dannenberg Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2,1/2] at91: cleanup taurus port
On Tue, Apr 16, 2019 at 01:31:57PM +0200, Heiko Schocher wrote: > - at91sam9g20-taurus.dts: use labels > - cleanup taurus port to compile clean with > current mainline again. SPL has no serial > output anymore, so it fits into SRAM. > > Signed-off-by: Heiko Schocher This needs to be reworked now to fix some link errors, sorry! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 6/7] configs: Add configs for AM65x High Security EVM
On Fri, Apr 12, 2019 at 12:54:47PM -0400, Andrew F. Davis wrote: > Add new defconfig files for the AM65x High Security EVM. > > This defconfigs are the same as for the non-secure part, except for: > CONFIG_TI_SECURE_DEVICE option set to 'y' > CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y' > CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y' > > Signed-off-by: Andrew F. Davis > Reviewed-by: Tom Rini > Reviewed-by: Andreas Dannenberg Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 1/7] arm: K3: Avoid use of MCU_PSRAM0 before SYSFW is loaded
On Fri, Apr 12, 2019 at 12:54:42PM -0400, Andrew F. Davis wrote: > On HS devices the 512b region of reset isolated memory called > MCU_PSRAM0 is firewalled by default. Until SYSFW is loaded we > cannot use this memory. It is only used to store a single value > left at the end of SRAM by ROM that will be needed later. Save > that value to a global variable stored in the .data section. > This section is used as .bss will be cleared between saving > this value and using it. > > Signed-off-by: Andrew F. Davis > Reviewed-by: Andreas Dannenberg > Reviewed-by: Lokesh Vutla Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] fs: btrfs: fix btrfs_search_tree invalid results
On Tue, Apr 16, 2019 at 02:47:14AM +0200, Pierre Bourdon wrote: > btrfs_search_tree should return the first item in the tree that is > greater or equal to the searched item. > > The search algorithm did not properly handle the edge case where the > searched item is higher than the last item of the node but lower than > the first item of the next node. Instead of properly returning the first > item of the next node, it was returning an invalid path pointer > (pointing to a non-existent item after the last item of the node + 1). > > This fixes two issues in the btrfs driver: > - Looking for a ROOT_ITEM could fail if it was the first item of its > leaf node. > - Iterating through DIR_INDEX entries (for readdir) could fail if the > first DIR_INDEX entry was the first item of a leaf node. > > Signed-off-by: Pierre Bourdon > Cc: Marek Behun Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] cmd: pxe: Display splashscreen from extlinux.conf input
On Thu, Apr 11, 2019 at 11:13:13AM +0200, Patrice Chotard wrote: > The objective is to provide a simple way to retrieve a BMP file, > and display it as splashscreen, from extlinux.conf file input. > > For this, we take example on https://www.syslinux.org/wiki/ > index.php?title=Menu#The_advanced_menu_system > and more particularly on MENU BACKGROUND chapter. > For this, add "menu background" support in pxe command. > > As example, extlinux.conf content will look like: > > # Generic Distro Configuration file generated by OpenEmbedded > menu title Select the boot mode > TIMEOUT 20 > menu background ../splash.bmp > DEFAULT stm32mp157c-ev1-sdcard > LABEL stm32mp157c-ev1-sdcard > KERNEL /uImage > FDT /stm32mp157c-ev1.dtb > APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk > console=ttySTM0,115200 > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] fs: btrfs: fix false negatives in ROOT_ITEM search
On Sat, Apr 13, 2019 at 11:50:49PM +0200, Pierre Bourdon wrote: > ROOT_ITEMs in btrfs are referenced without knowing their actual "offset" > value. To perform these searches using only two items from the key, the > btrfs driver uses a special "btrfs_search_tree_key_type" function. > > The algorithm used by that function to transform a 3-tuple search into a > 2-tuple search was subtly broken, leading to items not being found if > they were the first in their tree node. > > This commit fixes btrfs_search_tree_key_type to properly behave in these > situations. > > Signed-off-by: Pierre Bourdon > Cc: Marek Behun Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] .gitignore: Ignore .log files
On Thu, Apr 18, 2019 at 10:46:58AM +0300, Baruch Siach wrote: > The generated flash.log file that mach-imx uses for MKIMAGEOUTPUT is not > covered by any other ignore pattern. Ignore all *.log files. > > Signed-off-by: Baruch Siach > Reviewed-by: Fabio Estevam Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] main: add new bootstage ID for entering cli loop
On Fri, Apr 12, 2019 at 12:37:03PM +0200, Heiko Schocher wrote: > adding a new bootstage ID: > BOOTSTAGE_ID_ENTER_CLI_LOOP > > Signed-off-by: Heiko Schocher Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 5/7] arm: mach-k3: Add secure device build support
On Fri, Apr 12, 2019 at 12:54:46PM -0400, Andrew F. Davis wrote: > K3 HS devices require signed binaries for boot, use the SECDEV tools > to sign the boot artifacts during build. > > Signed-off-by: Andrew F. Davis > Reviewed-by: Tom Rini > Reviewed-by: Andreas Dannenberg Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ARM: da850evm: Fix TI boot scripts for MMC
On Wed, Apr 17, 2019 at 01:24:33PM -0500, Adam Ford wrote: > The da850evm include environment/ti/mmc.h and places > DEFAULT_MMC_TI_ARGS, defined int that file, in > CONFIG_EXTRA_ENV_SETTINGS. This has been broken for some time > since neither CMD_PART nor CMD_UUID are available, so manually > changing the environmental variables was always required before > booting from MMC. With this patch, these scripts should work > again, and by default they point to mmc 0, partition 2, and > the dtb file exists in a /boot directory on partition 2. > > Signed-off-by: Adam Ford > > diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig > index 745ae2b4b1..ee39b0b1bc 100644 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ARM: da850evm: Fix broken SPI Flash
On Wed, Apr 17, 2019 at 11:21:56AM -0500, Adam Ford wrote:
> A previous patch converted a bunch of settings for CONFIG_SF_DEFAULT
> but it broke the SPI Flash which now prevents booting. This patch
> now correctly sets CONFIG_SF_DEFAULT_SPEED=3000 to match what it
> was before the conversion.
>
> Fixes: 14453fbfadc2 ("Convert CONFIG_SF_DEFAULT_* to Kconfig")
>
> Signed-off-by: Adam Ford
>
> diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
> index 4b09ba10a6..745ae2b4b1 100644
Applied to u-boot/master, thanks!
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Re: [U-Boot] fw_env: Fix double free
On Wed, Apr 17, 2019 at 04:56:54PM +0200, Björn Stenberg wrote: > addr0 is being freed twice, leading to segmentation fault > > Signed-off-by: Björn Stenberg Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] sysreset: syscon: remove POWER reset cause
On Thu, Apr 18, 2019 at 05:16:21PM +0200, Patrick Delaunay wrote: > The sysreset of 'POWER' type is a PMIC reset defined as > 'remove and restore power'. > So normally only COLD/WARN is supported by sysreset_syscon. > > This modification allows to use the function sysreset_walk(SYSRESET_POWER) > when it is supported by PMIC driver (see example in stpmic1). > > Signed-off-by: Patrick Delaunay Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: lpc32xx: Use IRAM for transmit buffer
On Wed, Apr 17, 2019 at 11:41:42AM +0200, Gregory CLEMENT wrote: > Since the introduction of the driver, some memory in IRAM is reserved for > the TX buffers. > > However there are not used but instead of it, it is the buffer provided > by the net stack which is used. As stated in the comment of the driver, > not using the IRAM buffer could cause cache issue and lower the > throughput. > > For the second argument it is less the case for transmitting buffers > because the throughput gain in IRAM is mitigated by the time to copy the > data from RAM to IRAM, but the first argument is still valid and indeed > this patch fixes issue seen with Ethernet on some boards > > Signed-off-by: Gregory CLEMENT Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-socfpga/master
On Fri, Apr 26, 2019 at 11:31:09AM +0200, Marek Vasut wrote: > The following changes since commit 3fbd2dce351ab5d40d3244f26bd713caa4f826e2: > > Merge branch '2019-04-22-master-imports' (2019-04-24 09:04:23 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-socfpga.git master > > for you to fetch changes up to bf068c7643f23c3f0936e3d1d292cc537acaf3bb: > > arm: socfpga: mailbox: Fix off-by-one error on command length checking > (2019-04-25 00:00:49 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v6, 1/1] avb: add support for named persistent values
On Tue, Apr 09, 2019 at 03:38:14PM +0200, Igor Opaniuk wrote: > AVB 2.0 spec. revision 1.1 introduces support for named persistent values > that must be tamper evident and allows AVB to store arbitrary key-value > pairs [1]. > > Introduce implementation of two additional AVB operations > read_persistent_value()/write_persistent_value() for retrieving/storing > named persistent values. > > Correspondent pull request in the OP-TEE OS project repo [2]. > > [1]: > https://android.googlesource.com/platform/external/avb/+/android-9.0.0_r22 > [2]: https://github.com/OP-TEE/optee_os/pull/2699 > > Reviewed-by: Simon Glass > Reviewed-by: Sam Protsenko > Signed-off-by: Igor Opaniuk Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3, 4/7] arm: mach-k3: Add secure device support
On Fri, Apr 12, 2019 at 12:54:45PM -0400, Andrew F. Davis wrote: > K3 devices have High Security (HS) variants along with the non-HS already > supported. Like the previous generation devices (OMAP/Keystone2) K3 > supports boot chain-of-trust by authenticating and optionally decrypting > images as they are unpacked from FIT images. Add support for this here. > > Signed-off-by: Andrew F. Davis > Reviewed-by: Tom Rini > Reviewed-by: Andreas Dannenberg Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm: lpc32xx: Fix timer initialization
On Wed, Apr 17, 2019 at 11:48:45AM +0200, Gregory CLEMENT wrote: > The match controller register is not cleared during > initialization. However, some bits of this register may reset the TC if > tnMRx match it. > > As we can't make any assumption about how U-Boot is launched by the first > stage bootloader (such as S1L) clearing this register ensure that the > timers work as expected. > > Signed-off-by: Gregory CLEMENT Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] fs: btrfs: fix false negatives in ROOT_ITEM search
On Sat, Apr 27, 2019 at 04:50:18PM +0200, Pierre Bourdon wrote: > Hi Tom, > > On Sat, Apr 27, 2019 at 4:46 PM Tom Rini wrote: > > On Sat, Apr 13, 2019 at 11:50:49PM +0200, Pierre Bourdon wrote: > > > ROOT_ITEMs in btrfs are referenced without knowing their actual "offset" > > > value. To perform these searches using only two items from the key, the > > > btrfs driver uses a special "btrfs_search_tree_key_type" function. > > > > > > The algorithm used by that function to transform a 3-tuple search into a > > > 2-tuple search was subtly broken, leading to items not being found if > > > they were the first in their tree node. > > > > > > This commit fixes btrfs_search_tree_key_type to properly behave in these > > > situations. > > > > > > Signed-off-by: Pierre Bourdon > > > Cc: Marek Behun > > > > Applied to u-boot/master, thanks! > > Please disregard this patch as was mentioned in a followup email on the > thread. > > https://patchwork.ozlabs.org/patch/1085991/ implements a better way of > addressing the problem and fixes a 2nd btrfs bug that was missed in > this first revision. > > Sorry for the mixup, OK, I'll take care of things, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/1] arm: dts: add missing vexpress device trees
On Sun, Apr 21, 2019 at 11:54:37PM +0200, Heinrich Schuchardt wrote: > Add the device trees for > > * vexpress_ca5x2_defconfig > * vexpress_ca9x4_defconfig > * vexpress_ca15_tc2_defconfig > > as available in Linux 5.1 rc5. > > We are using the vexpress_ca15_tc2_defconfig and vexpress_ca9x4_defconfig > for Travis testing via QEMU. > > The UEFI base Embedded Base Boot Requirements Specification (EBBR) requires > that an embedded board either provides a device tree or an ACPI table. > > All block devices are meant to be moved to the driver model. On ARM this > requires a device tree. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] fs: btrfs: fix false negatives in ROOT_ITEM search
Hi Tom, On Sat, Apr 27, 2019 at 4:46 PM Tom Rini wrote: > On Sat, Apr 13, 2019 at 11:50:49PM +0200, Pierre Bourdon wrote: > > ROOT_ITEMs in btrfs are referenced without knowing their actual "offset" > > value. To perform these searches using only two items from the key, the > > btrfs driver uses a special "btrfs_search_tree_key_type" function. > > > > The algorithm used by that function to transform a 3-tuple search into a > > 2-tuple search was subtly broken, leading to items not being found if > > they were the first in their tree node. > > > > This commit fixes btrfs_search_tree_key_type to properly behave in these > > situations. > > > > Signed-off-by: Pierre Bourdon > > Cc: Marek Behun > > Applied to u-boot/master, thanks! Please disregard this patch as was mentioned in a followup email on the thread. https://patchwork.ozlabs.org/patch/1085991/ implements a better way of addressing the problem and fixes a 2nd btrfs bug that was missed in this first revision. Sorry for the mixup, Best, -- Pierre Bourdon Software Engineer @ Zürich, Switzerland https://delroth.net/ ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] fs: fat: Build only if CONFIG_FS_FAT=y
On Mon, Apr 15, 2019 at 11:19:15AM +, Ismael Luceno Cortes wrote: > Signed-off-by: Ismael Luceno Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-marvell/master
On Fri, Apr 26, 2019 at 12:58:33PM +0200, Stefan Roese wrote: > Hi Tom, > > please pull the following Marvell and watchdog related patches: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] mtd: nand: raw: Fix CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT behavior
On Wed, Apr 17, 2019 at 11:22:05AM +0200, Gregory CLEMENT wrote:
> The purpose of "mtd: nand: raw: allow to disable unneeded ECC layouts"
> was to allow disabling the default ECC layouts if a driver is known to
> provide its own ECC layout. However, this commit did the opposite and
> disabled the default layout when it was _not_ selected.
>
> It breaks all the NAND drivers not providing their own ECC layout this
> patch fix this situation.
>
> It was tested with the lpc32xx_nand_slc driver.
>
> Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
> Reviewed-by: Miquel Raynal
> Signed-off-by: Gregory CLEMENT
> Tested-by: Eugen Hristev
Applied to u-boot/master, thanks!
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Re: [U-Boot] [U-Boot, v2, 2/2] dtb_platdata.py: prevent define generation of alias
On Tue, Apr 16, 2019 at 01:31:58PM +0200, Heiko Schocher wrote:
> generate define for an alias only if the struct is not
> created already.
>
> This prevents compilerwarning:
> PLATspl/dts/dt-platdata.o
> spl/dts/dt-platdata.c:11:46: error: missing braces around initializer
> [-Werror=missing-braces]
> static const struct dtd_simple_bus dtv_ahb = {
> ^
> spl/dts/dt-platdata.c:20:46: error: missing braces around initializer
> [-Werror=missing-braces]
> static const struct dtd_simple_bus dtv_apb = {
> ^
> cc1: all warnings being treated as errors
>
> on the at91 based taurus board. Reason is in at91sam9260.dtsi
> is defined:
>
> ahb {
> compatible = "simple-bus";
> ranges;
>
> and later:
>
> pinctrl: pinctrl@f400 {
> compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> ranges = <0xf400 0xf400 0x600>;
>
> without this patch dtoc generates:
>
> struct dtd_atmel_at91rm9200_pinctrl {
> fdt32_t atmel_mux_mask[6];
> fdt32_t ranges[3];
> fdt32_t reg[6];
> };
>
> struct dtd_simple_bus {
> boolranges;
> };
>
> "#define dtd_simple_bus dtd_atmel_at91rm9200_pinctrl"
>
> and the line with "define dtd_simple_bus..." introduces
> the warning. This define is not needed.
>
> Signed-off-by: Heiko Schocher
Applied to u-boot/master, thanks!
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Re: [U-Boot] doc: delete long-obsolete README.ARM-memory-map
On Thu, Apr 18, 2019 at 08:00:48AM -0400, Robert P. J. Day wrote: > As far back as 2011, "_armboot_start" was being described as "no > longer defined": > > commit 297f18ac0fbeef30ba1c17fe131ca75f09a6e7cf > Author: Greg Ungerer > Date: Fri Sep 9 22:23:34 2011 +1000 > >CM4000: fix broken flash base for OpenGear boards > >Use _bss_start_ofs as the size of the boot loader code+data that we want >to protect in the flash. This replaces use of the no longer defined >_armboot_start. > > diff --git a/doc/README.ARM-memory-map b/doc/README.ARM-memory-map > deleted file mode 100644 > index 1b120ac3e1..00 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] lib: uuid: Improve randomness of uuid values on RANDOM_UUID=y
On Fri, 26 Apr 2019 23:54:58 +0200
Eugeniu Rosca wrote:
> The random uuid values (enabled via CONFIG_RANDOM_UUID=y) on our
> platform are always the same. Below is consistent on each cold boot:
>
> => ### reach U-Boot prompt
> => setenv uuid_gpt_misc
> => gpt verify mmc 1 $partitions
> Verify GPT: success!
> => print uuid_gpt_misc
> uuid_gpt_misc=d117f98e-6f2c-d04b-a5b2-331a19f91cb2
> => setenv uuid_gpt_misc
> => gpt verify mmc 1 $partitions
> Verify GPT: success!
> => print uuid_gpt_misc
> uuid_gpt_misc=ad5ec4b6-2d9f-8544-9417-fe3bd1c9b1b3
>
> While the uuids do change on every 'gpt {write,verify}' command,
> the values appear to be taken from the same pool, in the same order.
>
> As a user, I expect a trully random uuid value in the above example.
> Otherwise, system/RFS designers and OS people might assume they have
> a reliable/consistent uuid passed by the bootloader, while the truth
> is U-Boot simply lacks entropy to generate a random string.
>
> Let's use get_timer() to update the seed, same as done in commit
> da384a9d7628 ("net: rename and refactor eth_rand_ethaddr() function").
>
> Signed-off-by: Eugeniu Rosca
> ---
> lib/uuid.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/lib/uuid.c b/lib/uuid.c
> index fa20ee39fc32..8a82cb234b88 100644
> --- a/lib/uuid.c
> +++ b/lib/uuid.c
> @@ -238,6 +238,8 @@ void gen_rand_uuid(unsigned char *uuid_bin)
> unsigned int *ptr = (unsigned int *)&uuid;
> int i;
>
> + srand(get_timer(0));
> +
> /* Set all fields randomly */
> for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++)
> *(ptr + i) = cpu_to_be32(rand());
Reviewed-by: Lukasz Majewski
Best regards,
Lukasz Majewski
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Re: [U-Boot] [PATCH] rockchip: make_fit_atf: Use BL31 environ variable for file location
Hi Jagan,
On Sun, 21 Apr 2019 22:42:45 +0530
Jagan Teki wrote:
> On Tue, Feb 5, 2019 at 4:24 PM Emmanuel Vadot wrote:
> >
> > Other make_fit script (like imx or sunxi) use the BL31 environment
> > variable to indicate the location of the file.
> > Also do that for rockchip so we don't need to copy the file in the source
> > directory.
> >
> > Signed-off-by: Emmanuel Vadot
> > ---
> > arch/arm/mach-rockchip/make_fit_atf.py | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-rockchip/make_fit_atf.py
> > b/arch/arm/mach-rockchip/make_fit_atf.py
> > index d1faff1957..7bf58e3dd1 100755
> > --- a/arch/arm/mach-rockchip/make_fit_atf.py
> > +++ b/arch/arm/mach-rockchip/make_fit_atf.py
> > @@ -194,7 +194,7 @@ def get_bl31_segments_info(bl31_file_name):
> >
> > def main():
> > uboot_elf="./u-boot"
> > -bl31_elf="./bl31.elf"
> > +bl31_elf=os.getenv("BL31", "./bl31.elf")
>
> Have similar change on my repo.
>
> Better through warning for non BL31 like
>
> if "BL31ELF" in os.environ:
>bl31_elf=os.getenv("BL31ELF");
>else:
> sys.exit("ERROR: Please export BL31ELF file, check
> board/rockchip/evb_rk3399/README)
I didn't error for the same reason we don't on Allwinner, CI don't
copy this file as part of the test. Yes this does result in a
non-working u-boot but the goal of thoses test is just to compile.
mksunxi_fit_atf.sh prints a warning, maybe I should just do the same ?
Phillipp, what's your view on this ?
> And BL31ELF would be proper env than BL31 since rockchip build would
> require elf and other one has bin, IMHO.
This change is fine with me.
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Re: [U-Boot] [PATCH 3/5] spi: add spi-mem driver for MediaTek MT7629 SoC
On Fri, Apr 26, 2019 at 2:53 PM Weijie Gao wrote: > > This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR > and SPI-NAND flashes. > > Cc: Jagan Teki > Signed-off-by: Weijie Gao > --- > drivers/spi/Kconfig | 9 ++ > drivers/spi/Makefile | 1 + > drivers/spi/mtk_spimem.c | 325 > +++ Do we really need spimen on the name? I prefer spi as it is, what is the notation used by Linux I think spi itself, please check it. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-sunxi/master
Hi Tom, Please pull this PR. Summary: - H6 Beelink GS1 board (Clément) - Olimex A64-Teres-I board (Jonas) - sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej) - _relaxed MMIO (Andre) - EPHY clock changes(Jagan) The following changes since commit 1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1: Merge tag 'arc-for-2019.07' of git://git.denx.de/u-boot-arc (2019-04-18 12:12:16 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to f93369fb348488298467e4efcc34ba538da77b74: sunxi: H6: use writel_relaxed for DRAM timing register accesses (2019-04-27 21:32:37 +0530) Andre Przywara (3): arm: clean up asm/io.h arm: introduce _relaxed MMIO accessors sunxi: H6: use writel_relaxed for DRAM timing register accesses Clément Péron (1): arm: dts: h6: Add Beelink GS1 initial support Jagan Teki (6): clk: Get the CLK by index without device clk: Use clk_get_by_index_tail() test/dm: clk: Add clk_get_by_index[_nodev] test reset: Get the RESET by index without device test/dm: reset: Add reset_get_by_index[_nodev] test net: sun8i_emac: Add EPHY CLK and RESET support Jonas Smedegaard (1): sun50i: a64: Add Olimex A64-Teres-I board initial support Ondrej Jirman (1): sunxi: Fix build when CONFIG_CMD_PXE or CONFIG_CMD_DHCP are disabled arch/arm/dts/Makefile | 4 +- arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi | 41 + arch/arm/dts/sun50i-a64-teres-i.dts | 270 arch/arm/dts/sun50i-h6-beelink-gs1.dts | 184 +++ arch/arm/include/asm/io.h | 164 ++--- arch/arm/mach-sunxi/dram_sun50i_h6.c| 79 board/sunxi/MAINTAINERS | 12 ++ configs/beelink_gs1_defconfig | 15 ++ configs/teres_i_defconfig | 22 +++ drivers/clk/clk-uclass.c| 75 ++-- drivers/net/sun8i_emac.c| 74 ++-- drivers/reset/reset-uclass.c| 53 -- include/clk.h | 15 ++ include/configs/sunxi-common.h | 16 +- include/reset.h | 16 ++ test/dm/clk.c | 21 +++ test/dm/reset.c | 23 +++ 17 files changed, 840 insertions(+), 244 deletions(-) create mode 100644 arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi create mode 100644 arch/arm/dts/sun50i-a64-teres-i.dts create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig create mode 100644 configs/teres_i_defconfig ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling
On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
From: Tien Fong Chee
Ensure the watchdog is reset timely on each status polling.
I would have expected a longer commit message here explaining why this
is done, and from where, where to, and why the watchdog reset has been
moved.
Anyway, I don't want to hold back this series again for this, but please
next time: write longer commit messages. Better write too much than risk
someone in the future doesn't get what or why you did things.
Thanks,
Simon
Signed-off-by: Tien Fong Chee
---
changes for v12
- Improved the commit messages.
changes for v11
- No changes.
changes for v10
- This patch was split out from [PATCH v10 5/9]
ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
---
drivers/fpga/socfpga_arria10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index b0abe1955c..9499d1a014 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
printf("nstatus == 0 while waiting for condone\n");
return -EPERM;
}
+ WATCHDOG_RESET();
}
if (i == FPGA_TIMEOUT_CNT)
@@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
printf("FPGA: Poll CD failed with error code %d\n", status);
return -EPERM;
}
- WATCHDOG_RESET();
/* Ensure the FPGA entering user mode */
status = fpgamgr_program_poll_usermode();
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Re: [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
On 19.03.19 09:50, tien.fong.c...@intel.com wrote: From: Tien Fong Chee Increasing Malloc pool size up to 0x15000 is required to support FAT in SPL . The result of calculation is come from after applying some few patches "Some few patches"? What should that mean? Either you refer to the current state or you can refer to the patchwork items. which are required for optimizing vfat and maximizing resusable of the memory pool, and then followed by the size required come from default max cluster(0x1) + others(0x2000) + additional memory for headroom(0x3000). Previous records of describing these few patches can be checked from here [v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg314511.html . Why do you refer to mail-archive.com instead of patchwork? Regards, Simon Signed-off-by: Tien Fong Chee --- changes for v12 - Improved the commit messages. changes for v11 - No changes. changes for v10 - No changes. changes for v9 - No changes. changes for v8 - Moved the FIT related configs to the patch of configuration for FPGA SoCFPGA A10 SoCDK. changes for v7 - Keep minimal configs. --- include/configs/socfpga_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 181af9b646..22533036ed 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2019 Altera Corporation */ #ifndef __CONFIG_SOCFPGA_COMMON_H__ #define __CONFIG_SOCFPGA_COMMON_H__ @@ -254,7 +254,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) /* SPL memory allocation configuration, this is for FAT implementation */ #ifndef CONFIG_SYS_SPL_MALLOC_START -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ CONFIG_SYS_SPL_MALLOC_SIZE + \ CONFIG_SYS_INIT_RAM_ADDR) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
From: Tien Fong Chee
Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.
Signed-off-by: Tien Fong Chee
---
changes for v12
- No changes.
changes for v11
- No changes.
changes for v10
-Cleaned up the codes.
-Return -EPERM when programing core on non early IO release mode. > -Using live
function to get rid of gd->
You got rid of gd-> in v10? How come I see numerous references to it below?
Regards,
Simon
-Removed @0 for fs-loader node
changes for v9
- Support data offset
- Added default DDR load address
- Squashed the image.h
- Changed to phandle
- Ensure the DDR is fully up running by checking the gd->ram
changes for v8
- Added codes to discern bitstream type based on fpga node name.
changes for v7
- Restructure the FPGA driver to support both peripheral bitstream and core
bitstream bundled into FIT image.
- Support loadable property for core bitstream. User can set loadable
in DDR for better performance. This loading would be done in one large
chunk instead of chunk by chunk loading with small memory buffer.
---
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
.../include/mach/fpga_manager_arria10.h| 39 +-
drivers/fpga/socfpga_arria10.c | 497 -
include/image.h| 4 +
4 files changed, 542 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index 998d811210..cc761967c7 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -18,6 +18,23 @@
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
+/ {
+ chosen {
+ firmware-loader = <&fs_loader0>;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc 1>;
+ };
+};
+
+&fpga_mgr {
+ u-boot,dm-pre-reloc;
+ altr,bitstream = "fit_spl_fpga.itb";
+};
+
&mmc {
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 09d13f6fd3..c5f67714aa 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -1,9 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2017 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
* All rights reserved.
*/
+#include
+#include
+#include
+
#ifndef _FPGA_MANAGER_ARRIA10_H_
#define _FPGA_MANAGER_ARRIA10_H_
@@ -51,6 +55,10 @@
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSKBIT(24)
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
+#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
+#define FPGA_SOCFPGA_A10_RBF_PERIPH0x0001
+#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
#ifndef __ASSEMBLY__
struct socfpga_fpga_manager {
@@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
u32 imgcfg_fifo_status;
};
+enum rbf_type {
+ unknown,
+ periph_section,
+ core_section
+};
+
+enum rbf_security {
+ invalid,
+ unencrypted,
+ encrypted
+};
+
+struct rbf_info {
+ enum rbf_type section;
+ enum rbf_security security;
+};
+
+struct fpga_loadfs_info {
+ fpga_fs_info *fpga_fsinfo;
+ u32 remaining;
+ u32 offset;
+ struct rbf_info rbfinfo;
+};
+
/* Functions */
int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
int fpgamgr_program_finish(void);
int is_fpgamgr_user_mode(void);
int fpgamgr_wait_early_user_mode(void);
-
+const char *get_fpga_filename(void);
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+ u32 offset);
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_ARRIA10_H_ */
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 9499d1a014..9df2c430d7 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2017 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
*/
-
#include
#include
#include
@@ -10,8 +9,11 @@
#include
#include
#include
+#include
#include
+#include
#include
+#include
#include
#include
@@ -21,6 +23,9 @@
#define COMPRESSION_OFFSET229
#define FPGA_TIMEOUT_MSEC 1000 /* tim
Re: [U-Boot] [PATCH] spi: Zap lpc32xx_ssp driver-related code
On 22.04.19 23:00, Tom Rini wrote: On Mon, Apr 22, 2019 at 11:50:22PM +0300, Vladimir Zapolskiy wrote: Hi Jagan, Tom, On 04/19/2019 09:48 AM, Jagan Teki wrote: Dropped - lpc32xx_ssp driver - CONFIG_LPC32XX_SSP, LPC32XX_SSP_TIMEOUT items Dropped due to: - no active updates - no dm conversion - multiple pings for asking dm-conversion I really don't want to rush into moaning, however let me ask you to drop the reason given above as invalid, otherwise please clarify who were the addressees of these 'multiple pings'. Indeed. Since it was only last month or so that I setup a low-traffic list for maintainers / custodians for important issues like this, [..] Wait, which list are you talking about? Should I be monitoring anything else than this one? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/2] spl: fix linker size check off-by-one errors
On 25.04.19 21:22, Simon Goldschmidt wrote: This fixes SPL linker script size checks for 3 lds files where the size checks were implemented as "x < YYY_MAX_SIZE". Fix the size checks to be "x <= YYY_MAX_SIZE" instead. After updating Ubuntu to 19.04 today, the new 8.3 gcc makes smartweb_defconfig fail compiling SPL without this because __image_copy_end==0x1000 I guess we're lucky travis uses gcc 7.3... (or, are we?) Regards, Simon Signed-off-by: Simon Goldschmidt --- Changes in v5: - added patch to fix linker size checks off-by-one error arch/arm/cpu/u-boot-spl.lds | 6 +++--- arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 4 ++-- arch/microblaze/cpu/u-boot-spl.lds | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index a2aa93a735..97899a567f 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -79,16 +79,16 @@ SECTIONS } #if defined(IMAGE_MAX_SIZE) -ASSERT(__image_copy_end - __image_copy_start < (IMAGE_MAX_SIZE), \ +ASSERT(__image_copy_end - __image_copy_start <= (IMAGE_MAX_SIZE), \ "SPL image too big"); #endif #if defined(CONFIG_SPL_BSS_MAX_SIZE) -ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \ +ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \ "SPL image BSS too big"); #endif #if defined(CONFIG_SPL_MAX_FOOTPRINT) -ASSERT(__bss_end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \ +ASSERT(__bss_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \ "SPL image plus BSS too big"); #endif diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index 3955bea23a..74f6355229 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -52,11 +52,11 @@ SECTIONS } #if defined(IMAGE_MAX_SIZE) -ASSERT(__image_copy_end - __start < (IMAGE_MAX_SIZE), \ +ASSERT(__image_copy_end - __start <= (IMAGE_MAX_SIZE), \ "SPL image too big"); #endif #if defined(CONFIG_SPL_BSS_MAX_SIZE) -ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \ +ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \ "SPL image BSS too big"); #endif diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds index 99c62b51a1..3387eb7189 100644 --- a/arch/microblaze/cpu/u-boot-spl.lds +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -57,6 +57,6 @@ SECTIONS } #if defined(CONFIG_SPL_MAX_FOOTPRINT) -ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \ +ASSERT(__end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \ "SPL image plus BSS too big"); #endif ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-sunxi/master
On Sat, Apr 27, 2019 at 09:47:21PM +0530, Jagan Teki wrote: > Hi Tom, > > Please pull this PR. > > Summary: > - H6 Beelink GS1 board (Clément) > - Olimex A64-Teres-I board (Jonas) > - sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej) > - _relaxed MMIO (Andre) NAK, this MMIO change (and readl/writel) stuff is causing tons of warnings on arm32. km_kirkwood_128m16 is the first platform of many. Thanks! > -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] DE10 Nano U-Boot v2019.04 Issues
Hello, I've attempted to build u-boot v2019.04 for the DE10 Nano board using
the following commands:
make ARCH=arm CROSS_COMPILE=${CC} distclean
make ARCH=arm CROSS_COMPILE=${CC} socfpga_de10_nano_defconfig
make ARCH=arm CROSS_COMPILE=${CC} u-boot-with-spl.sfp
It builds just fine but I'm not able to make the board load U-Boot correctly.
If I run the same commands using v2018.05 it builds and I'm able to boot the
board.
After some attempts to find the issue, I was able to compile and boot the
v2019.04 by changing the
CONFIG_DEFAULT_DEVICE_TREE=“socfpga_cyclone5_de10_nano” to
CONFIG_DEFAULT_DEVICE_TREE=“socfpga_cyclone5_de0_nano_soc” in the
socfpga_de10_nano_defconfig file.
That lead me to belive that there was an issue with the
socfpga_cyclone5_de10_nano.dts file.
After changing the socfpga_cyclone5_de10_nano.dts to be identical to the
socfpga_cyclone5_de0_nano_soc.dts I wasn't able to boot the board, making me
think that the issue is somewere else, since I'm also able to compile and boot
the board if I rename the socfpga_cyclone5_de10_nano.dts to
socfpga_cyclone5_de0_nano_soc.dts.
So would like to know if I'm missing a step in the build process or doing
something wrong?
Best regards,
Rafael Villatore
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Re: [U-Boot] [PATCH 3/5] spi: add spi-mem driver for MediaTek MT7629 SoC
On Sat, 2019-04-27 at 21:38 +0530, Jagan Teki wrote: > On Fri, Apr 26, 2019 at 2:53 PM Weijie Gao wrote: > > > > This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR > > and SPI-NAND flashes. > > > > Cc: Jagan Teki > > Signed-off-by: Weijie Gao > > --- > > drivers/spi/Kconfig | 9 ++ > > drivers/spi/Makefile | 1 + > > drivers/spi/mtk_spimem.c | 325 > > +++ > > Do we really need spimen on the name? I prefer spi as it is, what is > the notation used by Linux I think spi itself, please check it. This controller is originally designed for accessing SPI-NAND flashes. How about the name mtk-snfi, which means Serial NAND(NOR) flash interface? I'd prefer to use mtk-spi for the real generic SPI controller in the future. Best Regards, Weijie ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/2] ARM: defconfig: add Raspberry Pi 3 Model B+
Updating the bcm283x device tree sources adds the device trees for - Raspberry Pi 3 Model A+ - Raspberry Pi 3 Model B+ - Raspberry Pi Compute Module IO board rev1 - Raspberry Pi Compute Module 3 IO board V3.0 - Raspberry Pi Zero Add a defconfig file for the Raspberry Pi 3 Model B+. Heinrich Schuchardt (2): fdt: update bcm283x device tree sources to Linux 5.1-rc6 state ARM: defconfig: add Raspberry Pi 3 Model B+ arch/arm/dts/Makefile | 13 +- arch/arm/dts/bcm2835-rpi-a-plus.dts | 15 +- arch/arm/dts/bcm2835-rpi-a.dts | 9 +- arch/arm/dts/bcm2835-rpi-b-plus.dts | 15 +- arch/arm/dts/bcm2835-rpi-b-rev2.dts | 11 +- arch/arm/dts/bcm2835-rpi-b.dts | 9 +- arch/arm/dts/bcm2835-rpi-cm1-io1.dts| 88 ++ arch/arm/dts/bcm2835-rpi-cm1.dtsi | 34 arch/arm/dts/bcm2835-rpi-zero-w.dts | 123 +- arch/arm/dts/bcm2835-rpi-zero.dts | 105 arch/arm/dts/bcm2835-rpi.dtsi | 22 +-- arch/arm/dts/bcm2835.dtsi | 7 +- arch/arm/dts/bcm2836-rpi-2-b.dts| 81 - arch/arm/dts/bcm2836-rpi.dtsi | 6 + arch/arm/dts/bcm2836.dtsi | 25 +-- arch/arm/dts/bcm2837-rpi-3-a-plus.dts | 175 +++ arch/arm/dts/bcm2837-rpi-3-b-plus.dts | 178 arch/arm/dts/bcm2837-rpi-3-b.dts| 128 +- arch/arm/dts/bcm2837-rpi-cm3-io3.dts| 87 ++ arch/arm/dts/bcm2837-rpi-cm3.dtsi | 52 ++ arch/arm/dts/bcm2837.dtsi | 20 ++- arch/arm/dts/bcm283x-rpi-lan7515.dtsi | 41 + arch/arm/dts/bcm283x-rpi-smsc9512.dtsi | 1 + arch/arm/dts/bcm283x-rpi-usb-otg.dtsi | 11 ++ arch/arm/dts/bcm283x.dtsi | 57 +-- configs/rpi_3_b_plus_defconfig | 43 + include/dt-bindings/clock/bcm2835-aux.h | 10 +- include/dt-bindings/clock/bcm2835.h | 10 +- include/dt-bindings/net/microchip-lan78xx.h | 21 +++ include/dt-bindings/pinctrl/bcm2835.h | 8 +- include/dt-bindings/soc/bcm2835-pm.h| 28 +++ 31 files changed, 1333 insertions(+), 100 deletions(-) create mode 100644 arch/arm/dts/bcm2835-rpi-cm1-io1.dts create mode 100644 arch/arm/dts/bcm2835-rpi-cm1.dtsi create mode 100644 arch/arm/dts/bcm2835-rpi-zero.dts create mode 100644 arch/arm/dts/bcm2836-rpi.dtsi create mode 100644 arch/arm/dts/bcm2837-rpi-3-a-plus.dts create mode 100644 arch/arm/dts/bcm2837-rpi-3-b-plus.dts create mode 100644 arch/arm/dts/bcm2837-rpi-cm3-io3.dts create mode 100644 arch/arm/dts/bcm2837-rpi-cm3.dtsi create mode 100644 arch/arm/dts/bcm283x-rpi-lan7515.dtsi create mode 100644 arch/arm/dts/bcm283x-rpi-usb-otg.dtsi create mode 100644 configs/rpi_3_b_plus_defconfig create mode 100644 include/dt-bindings/net/microchip-lan78xx.h create mode 100644 include/dt-bindings/soc/bcm2835-pm.h -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] fdt: update bcm283x device tree sources to Linux 5.1-rc6 state
Updating the bcm283x device tree sources adds the device trees for
- Raspberry Pi 3 Model A+
- Raspberry Pi 3 Model B+
- Raspberry Pi Compute Module IO board rev1
- Raspberry Pi Compute Module 3 IO board V3.0
- Raspberry Pi Zero
Signed-off-by: Heinrich Schuchardt
---
arch/arm/dts/Makefile | 13 +-
arch/arm/dts/bcm2835-rpi-a-plus.dts | 15 +-
arch/arm/dts/bcm2835-rpi-a.dts | 9 +-
arch/arm/dts/bcm2835-rpi-b-plus.dts | 15 +-
arch/arm/dts/bcm2835-rpi-b-rev2.dts | 11 +-
arch/arm/dts/bcm2835-rpi-b.dts | 9 +-
arch/arm/dts/bcm2835-rpi-cm1-io1.dts| 88 ++
arch/arm/dts/bcm2835-rpi-cm1.dtsi | 34
arch/arm/dts/bcm2835-rpi-zero-w.dts | 123 +-
arch/arm/dts/bcm2835-rpi-zero.dts | 105
arch/arm/dts/bcm2835-rpi.dtsi | 22 +--
arch/arm/dts/bcm2835.dtsi | 7 +-
arch/arm/dts/bcm2836-rpi-2-b.dts| 81 -
arch/arm/dts/bcm2836-rpi.dtsi | 6 +
arch/arm/dts/bcm2836.dtsi | 25 +--
arch/arm/dts/bcm2837-rpi-3-a-plus.dts | 175 +++
arch/arm/dts/bcm2837-rpi-3-b-plus.dts | 178
arch/arm/dts/bcm2837-rpi-3-b.dts| 128 +-
arch/arm/dts/bcm2837-rpi-cm3-io3.dts| 87 ++
arch/arm/dts/bcm2837-rpi-cm3.dtsi | 52 ++
arch/arm/dts/bcm2837.dtsi | 20 ++-
arch/arm/dts/bcm283x-rpi-lan7515.dtsi | 41 +
arch/arm/dts/bcm283x-rpi-smsc9512.dtsi | 1 +
arch/arm/dts/bcm283x-rpi-usb-otg.dtsi | 11 ++
arch/arm/dts/bcm283x.dtsi | 57 +--
include/dt-bindings/clock/bcm2835-aux.h | 10 +-
include/dt-bindings/clock/bcm2835.h | 10 +-
include/dt-bindings/net/microchip-lan78xx.h | 21 +++
include/dt-bindings/pinctrl/bcm2835.h | 8 +-
include/dt-bindings/soc/bcm2835-pm.h| 28 +++
30 files changed, 1290 insertions(+), 100 deletions(-)
create mode 100644 arch/arm/dts/bcm2835-rpi-cm1-io1.dts
create mode 100644 arch/arm/dts/bcm2835-rpi-cm1.dtsi
create mode 100644 arch/arm/dts/bcm2835-rpi-zero.dts
create mode 100644 arch/arm/dts/bcm2836-rpi.dtsi
create mode 100644 arch/arm/dts/bcm2837-rpi-3-a-plus.dts
create mode 100644 arch/arm/dts/bcm2837-rpi-3-b-plus.dts
create mode 100644 arch/arm/dts/bcm2837-rpi-cm3-io3.dts
create mode 100644 arch/arm/dts/bcm2837-rpi-cm3.dtsi
create mode 100644 arch/arm/dts/bcm283x-rpi-lan7515.dtsi
create mode 100644 arch/arm/dts/bcm283x-rpi-usb-otg.dtsi
create mode 100644 include/dt-bindings/net/microchip-lan78xx.h
create mode 100644 include/dt-bindings/soc/bcm2835-pm.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1452fd2189..134b46f009 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -685,14 +685,19 @@ dtb-$(CONFIG_TARGET_VINCO) += \
at91-vinco.dtb
dtb-$(CONFIG_ARCH_BCM283X) += \
- bcm2835-rpi-a-plus.dtb \
bcm2835-rpi-a.dtb \
+ bcm2835-rpi-a-plus.dtb \
+ bcm2835-rpi-b.dtb \
bcm2835-rpi-b-plus.dtb \
bcm2835-rpi-b-rev2.dtb \
- bcm2835-rpi-b.dtb \
- bcm2835-rpi-zero-w.dtb \
+ bcm2835-rpi-cm1-io1.dtb \
+ bcm2835-rpi-zero.dtb \
+ bcm2835-rpi-zero-w.dtb\
bcm2836-rpi-2-b.dtb \
- bcm2837-rpi-3-b.dtb
+ bcm2837-rpi-3-a-plus.dtb \
+ bcm2837-rpi-3-b.dtb \
+ bcm2837-rpi-3-b-plus.dtb \
+ bcm2837-rpi-cm3-io3.dtb
dtb-$(CONFIG_ARCH_BCM63158) += \
bcm963158.dtb
diff --git a/arch/arm/dts/bcm2835-rpi-a-plus.dts
b/arch/arm/dts/bcm2835-rpi-a-plus.dts
index 9f866491ef..db8a6017f2 100644
--- a/arch/arm/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/dts/bcm2835-rpi-a-plus.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
@@ -9,12 +10,12 @@
leds {
act {
- gpios = <&gpio 47 0>;
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
pwr {
label = "PWR";
- gpios = <&gpio 35 0>;
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
linux,default-trigger = "default-on";
};
@@ -30,8 +31,8 @@
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
- gpio-line-names = "SDA0",
- "SCL0",
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
@@ -100,6 +101,12 @@
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
+ status = "okay";
+};
+
[U-Boot] [PATCH 2/2] ARM: defconfig: add Raspberry Pi 3 Model B+
Provide a defconfig file for the Raspberry Pi 3 Model B+. It is based on the Raspberry Pi 3 file, just changing the device tree. Signed-off-by: Heinrich Schuchardt --- configs/rpi_3_b_plus_defconfig | 43 ++ 1 file changed, 43 insertions(+) create mode 100644 configs/rpi_3_b_plus_defconfig diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig new file mode 100644 index 00..2ae7b6dcae --- /dev/null +++ b/configs/rpi_3_b_plus_defconfig @@ -0,0 +1,43 @@ +CONFIG_ARM=y +CONFIG_ARCH_BCM283X=y +CONFIG_SYS_TEXT_BASE=0x0008 +CONFIG_TARGET_RPI_3=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_BOARD_SETUP=y +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="U-Boot> " +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_FS_UUID=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus" +CONFIG_ENV_FAT_INTERFACE="mmc" +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DM_KEYBOARD=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_BCM2835=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_CONSOLE_SCROLL_LINES=10 +CONFIG_PHYS_TO_BUS=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] ARM: defconfig: add Raspberry Pi 3 Model B+
> Am 28.04.2019 um 06:46 schrieb Heinrich Schuchardt : > > Updating the bcm283x device tree sources adds the device trees for > > - Raspberry Pi 3 Model A+ > - Raspberry Pi 3 Model B+ > - Raspberry Pi Compute Module IO board rev1 > - Raspberry Pi Compute Module 3 IO board V3.0 > - Raspberry Pi Zero > > Add a defconfig file for the Raspberry Pi 3 Model B+. What's holding us back from just enabling CONFIG_OF_BOARD on the rpi configs by default by now? We could then live with only 3 configs: one per arm version (v6/v7/v8). Alex ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
