[U-Boot] [RESEND PATCH v7 10/11] rockchip: rk3399: Add Rock PI 4 support
Add initial support for Rock PI 4 board.
Specification
- Rockchip RK3399
- LPDDR4
- eMMC
- SD card slot
- RTL8211E 1Gbps
- HDMI In/Out, DP, MIPI DSI/CSI
- PCIe M.2
- USB 2.0, USB-3.0
- USB C Type
Commit details of rk3399-rock-pi-4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: add ROCK Pi 4 DTS support"
(sha1: 1b5715c602fda7b812af0e190eddcce2812e5417)
Signed-off-by: Akash Gajjar
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 +
arch/arm/dts/rk3399-rock-pi-4.dts | 606 ++
board/rockchip/evb_rk3399/MAINTAINERS | 7 +
configs/rock-pi-4-rk3399_defconfig| 59 +++
5 files changed, 679 insertions(+)
create mode 100644 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-rock-pi-4.dts
create mode 100644 configs/rock-pi-4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8522f01aca..e8826219b6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -113,6 +113,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
+ rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
new file mode 100644
index 00..7bddc3acdb
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dts
b/arch/arm/dts/rk3399-rock-pi-4.dts
new file mode 100644
index 00..4a543f2117
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-pi-4.dts
@@ -0,0 +1,606 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar
+ * Copyright (c) 2019 Pragnesh Patel
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi 4";
+ compatible = "radxa,rockpi4", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc12v_dcin: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pwr_en>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <_sys>;
+ };
+
+ vcc5v0_typec: vcc5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_typec_en>;
+ regulator-name = "vcc5v0_typec";
+ regulator-always-on;
+ vin-supply = <_sys>;
+ };
+
+ vcc_lan: vcc3v3-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_lan";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt =
[U-Boot] [RESEND PATCH v7 02/11] Kconfig: Add default SPL_FIT_GENERATOR for rockchip
Add default SPL_FIT_GENERATOR py script for rockchip platforms if specific target enabled SPL_LOAD_FIT. So, this would help get rid of explicitly mentioning the default SPL FIT generator in defconfigs. however some targets, like puma_rk3399 still require their own FIT generator so in those cases the default will override with defconfig defined generator. Reviewed-by: Paul Kocialkowski Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Kconfig | 1 + configs/chromebook_bob_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig| 1 - configs/firefly-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - 7 files changed, 1 insertion(+), 6 deletions(-) diff --git a/Kconfig b/Kconfig index 7a5491bd67..91c1082ace 100644 --- a/Kconfig +++ b/Kconfig @@ -435,6 +435,7 @@ config SPL_FIT_GENERATOR string ".its file generator script for U-Boot FIT image" depends on SPL_FIT default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI + default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP help Specifies a (platform specific) script file to generate the FIT source file used to build the U-Boot FIT image file. This gets diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index ce07a7f0ff..bd836acad5 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 5bb910e8d4..94963e4280 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 79da86b32f..926d244fbe 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 301b27e3a4..5016fb8993 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index ba13976cc6..22ddd8dce3 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 8d490be18c..48d14ef7d8 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/1] efi_loader: unload applications upon Exit()
On 5/8/19 3:08 AM, Takahiro Akashi wrote:
On Wed, May 08, 2019 at 02:59:08AM +0200, Heinrich Schuchardt wrote:
On 5/8/19 1:59 AM, Takahiro Akashi wrote:
On Tue, May 07, 2019 at 09:13:24PM +0200, Heinrich Schuchardt wrote:
Implement unloading of images in the Exit() boot services:
* unload images that are not yet started,
* unload started applications,
* unload drivers returning an error.
Signed-off-by: Heinrich Schuchardt
---
v2
Images that are no yet started can be unloaded by calling Exit().
In this case they are not the current image. Move the test for
current down in the code.
A started driver that called Exit() should still be considered a
started image. Exit cannot be called by another image afterwards,
cf. UEFI SCT 2.6 (2017), 3.5.1 Exit(), 5.1.4.5.8 - 5.1.4.5.10.
---
include/efi_loader.h | 1 +
lib/efi_loader/efi_boottime.c | 36 +--
lib/efi_loader/efi_image_loader.c | 2 ++
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 3b50cd28ef..4e4cffa799 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -234,6 +234,7 @@ struct efi_loaded_image_obj {
struct jmp_buf_data exit_jmp;
EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
struct efi_system_table *st);
+ u16 image_type;
};
/**
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 0385883ded..1ea96dab6c 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -2798,7 +2799,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
* image protocol.
*/
efi_status_t ret;
- void *info;
+ struct efi_loaded_image *loaded_image_protocol;
struct efi_loaded_image_obj *image_obj =
(struct efi_loaded_image_obj *)image_handle;
@@ -2806,13 +2807,33 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
exit_data_size, exit_data);
/* Check parameters */
- if (image_handle != current_image)
- goto out;
ret = EFI_CALL(efi_open_protocol(image_handle, _guid_loaded_image,
-, NULL, NULL,
+(void **)_image_protocol,
+NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL));
- if (ret != EFI_SUCCESS)
+ if (ret != EFI_SUCCESS) {
+ ret = EFI_INVALID_PARAMETER;
goto out;
+ }
+
+ /* Unloading of unstarted images */
+ switch (image_obj->header.type) {
+ case EFI_OBJECT_TYPE_STARTED_IMAGE:
+ break;
+ case EFI_OBJECT_TYPE_LOADED_IMAGE:
+ efi_delete_image(image_obj, loaded_image_protocol);
+ ret = EFI_SUCCESS;
+ goto out;
I think the goto usage here is in accordance with
https://www.kernel.org/doc/html/v4.10/process/coding-style.html#centralized-exiting-of-functions
+ default:
+ /* Handle does not refer to loaded image */
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ /* A started image can only be unloaded it is the last one started. */
+ if (image_handle != current_image) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
These are the lines I moved down.
Regards
Heinrich
/* Exit data is only foreseen in case of failure. */
if (exit_status != EFI_SUCCESS) {
@@ -2822,6 +2843,9 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
if (ret != EFI_SUCCESS)
EFI_PRINT("%s: out of memory\n", __func__);
}
+ if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION ||
+ exit_status != EFI_SUCCESS)
+ efi_delete_image(image_obj, loaded_image_protocol);
No change around efi_delete_image() and "goto" above?
Do you see a bug?
A diff would help me to understand what you would like to change.
You said:
For me, your code is much unreadable.
Moreover, I remember that you have said, in a review of my patch, that
we should use "goto" only in error cases.
Good point. So the check must be after handling
EFI_OBJECT_TYPE_LOADED_IMAGE.
I will revise the patch.
-Takahiro Akashi
Best regards
Heinrich
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[U-Boot] [RESEND PATCH v7 07/11] rockchip: rk3399: Add Nanopc T4 board support
Add initial support for Nanopc T4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- 16GB eMMC
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: Add NanoPC-T4 IR receiver"
(sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3)
Tested-by: Daniel Gröber
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 ++
arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++
board/rockchip/evb_rk3399/MAINTAINERS | 6 ++
configs/nanopc-t4-rk3399_defconfig| 59 +++
5 files changed, 164 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts
create mode 100644 configs/nanopc-t4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2a5bfd3fb5..adaca524c3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
new file mode 100644
index 00..17201bcf41
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts
b/arch/arm/dts/rk3399-nanopc-t4.dts
new file mode 100644
index 00..84433cf02b
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopc-t4.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPC-T4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPC-T4";
+ compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
+
+ vcc12v0_sys: vcc12v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1200>;
+ regulator-min-microvolt = <1200>;
+ regulator-name = "vcc12v0_sys";
+ };
+
+ vcc5v0_host0: vcc5v0-host0 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc5v0_host0";
+ vin-supply = <_sys>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = < 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "Recovery";
+ linux,code = ;
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = < RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_rx>;
+ };
+};
+
+ {
+ ir {
+ ir_rx: ir-rx {
+ /* external pullup to VCC3V3_SYS, despite being 1.8V :/
*/
+ rockchip,pins = <0 RK_PA6 RK_FUNC_1 _pull_none>;
+ };
+ };
+};
+
+ {
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+_host {
+ phy-supply = <_host0>;
+};
+
+_host {
+ phy-supply = <_host0>;
+};
+
+_sys {
+ vin-supply = <_sys>;
+};
+
+_sys {
+ vin-supply = <_sys>;
+};
+
+_typec {
+ enable-active-high;
+ gpios = < RK_PD2 GPIO_ACTIVE_HIGH>;
+ vin-supply = <_sys>;
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index ae43805a6a..f55c92f80c 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h
F: configs/evb-rk3399_defconfig
F: configs/firefly-rk3399_defconfig
+NANOPC-T4
+M: Jagan Teki
+S: Maintained
+F: configs/nanopc-t4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
+
NANOPI-M4
M: Jagan Teki
S: Maintained
diff --git a/configs/nanopc-t4-rk3399_defconfig
b/configs/nanopc-t4-rk3399_defconfig
new file mode 100644
index 00..d9f2137b4c
--- /dev/null
[U-Boot] [RESEND PATCH v7 09/11] rockchip: rk3399: Add Rockpro64 board support
Add initial support for Rockpro64 board.
Specification
- Rockchip RK3399
- 2/4GB Dual-Channel LPDDR3
- SD card slot
- eMMC socket
- 128Mb SPI Flash
- Gigabit ethernet
- PCIe 4X slot
- WiFI/BT module socket
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-rockpro64.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: rockpro64 dts add usb regulator"
(sha1: 6db644c79c8d45d73b56bc389aebd85fc3679beb)
'Akash' has sent an initial patch before, so I keep him as board
maintainer and I'm co-maintainer based on our conversation.
Signed-off-by: Akash Gajjar
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 +
arch/arm/dts/rk3399-rockpro64.dts | 712 ++
board/rockchip/evb_rk3399/MAINTAINERS | 7 +
configs/rockpro64-rk3399_defconfig| 59 ++
5 files changed, 785 insertions(+)
create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-rockpro64.dts
create mode 100644 configs/rockpro64-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 529c506b4d..8522f01aca 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -114,6 +114,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-rock960.dtb \
+ rk3399-rockpro64.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
new file mode 100644
index 00..7bddc3acdb
--- /dev/null
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-rockpro64.dts
b/arch/arm/dts/rk3399-rockpro64.dts
new file mode 100644
index 00..1f2394e058
--- /dev/null
+++ b/arch/arm/dts/rk3399-rockpro64.dts
@@ -0,0 +1,712 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2018 Akash Gajjar
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Pine64 RockPro64";
+ compatible = "pine64,rockpro64", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led_gpio>, <_led_gpio>;
+
+ work-led {
+ label = "work";
+ default-state = "on";
+ gpios = < RK_PB3 GPIO_ACTIVE_HIGH>;
+ };
+
+ diy-led {
+ label = "diy";
+ default-state = "off";
+ gpios = < RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = < 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <_enable_h>;
+
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt =
[U-Boot] [RESEND PATCH v7 08/11] rockchip: rk3399: Add Nanopi NEO4 board support
Add initial support for Nanopi NEO4 board.
Specification
- Rockchip RK3399
- 1GB DDR3-1866
- SD card slot
- eMMC Socket
- RTL8211E 1Gbps
- AP6212 WiFI/BT
- HDMI In/Out, DP, MIPI CSI
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 5V/3A
Commit details of rk3399-nanopi-neo4.dts sync from Linux:
"arm64: dts: rockchip: Add Nanopi NEO4 initial support"
(sha1: 092470b537f19788d957aed12d835a179b606014)
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 +++
arch/arm/dts/rk3399-nanopi-neo4.dts | 50 +
board/rockchip/evb_rk3399/MAINTAINERS | 6 +++
configs/nanopi-neo4-rk3399_defconfig| 59 +
5 files changed, 122 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts
create mode 100644 configs/nanopi-neo4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index adaca524c3..529c506b4d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-gru-bob.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
+ rk3399-nanopi-neo4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
new file mode 100644
index 00..7d22528f49
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopi-neo4.dts
b/arch/arm/dts/rk3399-nanopi-neo4.dts
new file mode 100644
index 00..195410b089
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-neo4.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Amarula Solutions B.V.
+ * Author: Jagan Teki
+ */
+
+/dts-v1/;
+
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi NEO4";
+ compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_core: vcc5v0-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_core";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_5v>;
+ };
+
+ vcc5v0_usb1: vcc5v0-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_sys>;
+ };
+};
+
+_sys {
+ vin-supply = <_core>;
+};
+
+_host {
+ phy-supply = <_usb1>;
+};
+
+_typec {
+ regulator-always-on;
+ vin-supply = <_5v>;
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index f55c92f80c..1f51f65160 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -18,6 +18,12 @@ S: Maintained
F: configs/nanopi-m4-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+NANOPI-NEO4
+M: Jagan Teki
+S: Maintained
+F: configs/nanopi-neo4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+
ORANGEPI-RK3399
M: Jagan Teki
S: Maintained
diff --git a/configs/nanopi-neo4-rk3399_defconfig
b/configs/nanopi-neo4-rk3399_defconfig
new file mode 100644
index 00..188656a2b4
--- /dev/null
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_DEBUG_UART_BASE=0xFF1A
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
[U-Boot] [RESEND PATCH v7 11/11] doc: rockchip: Add global doc for rk3399 build/flash
Since rockchip have an individual doc/README.rockchip, it would be better to update the same instead of maintaining it separately in board files. So, add the documentation for rk3399 - procedure to build for Rockchip miniloader and U-Boot SPL options - procedure to boot from SD for Rockchip miniloader and U-Boot SPL options - procedure to build ATF, PMU M0 firmware for puma boards - add boot logs of each option, so-that it would help for future boards porting Signed-off-by: Jagan Teki Reviewed-by: Philipp Tomsich --- doc/README.rockchip | 233 +++- 1 file changed, 232 insertions(+), 1 deletion(-) diff --git a/doc/README.rockchip b/doc/README.rockchip index ec10ebbc26..ca4d6473b0 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -88,10 +88,92 @@ One RV3188 baord is supported: For example: +1. To build RK3288 board: + CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all -(or you can use another cross compiler if you prefer) +(or you can use another cross compiler if you prefer) + +2. To build RK3399 board: + + Option 1: Package the image with Rockchip miniloader: + + - Compile U-Boot + + => cd /path/to/u-boot + => make nanopi-neo4-rk3399_defconfig + => make + => make u-boot.itb + + - Get the rkbin + + => git clone https://github.com/rockchip-linux/rkbin.git + + - Create trust.img + + => cd /path/to/rkbin + => ./tools/trust_merger RKTRUST/RK3399TRUST.ini + + - Create uboot.img + + => cd /path/to/rkbin + => ./tools/loaderimage --pack --uboot /path/to/u-boot/u-boot-dtb.bin uboot.img + + (Get trust.img and uboot.img) + + Option 2: Package the image with SPL: + + - We need the Python elftools.elf.elffile library for make_fit_atf.py to work + + => sudo apt-get install python-pyelftools + + - Export cross compiler path for aarch64 + + - Compile ATF + + For Puma board. + + => git clone git://git.theobroma-systems.com/arm-trusted-firmware.git + => cd arm-trusted-firmware + => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + + (copy bl31.bin into U-Boot root dir) + => cp build/rk3399/release/bl31/bl31.bin /path/to/u-boot/bl31-rk3399.bin + + For rest of rk3399 boards. + + => git clone https://github.com/ARM-software/arm-trusted-firmware.git + => cd arm-trusted-firmware + + (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-) + => make realclean + => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 + + (copy bl31.elf into U-Boot root dir) + => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot + + - Compile PMU M0 firmware + + This is optional for most of the rk3399 boards and required only for Puma board. + + => git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git + => cd rk3399-cortex-m0 + (export cross compiler path for Cortex-M0 PMU) + => make CROSS_COMPILE=arm-cortex_m0-eabi- + + (copy rk3399m0.bin into U-Boot root dir) + => cp rk3399m0.bin /path/to/u-boot + + - Compile U-Boot + + => cd /path/to/u-boot + => make orangepi-rk3399_defconfig + => make + => make u-boot.itb + + (Get spl/u-boot-spl-dtb.bin, u-boot.itb images and some boards would get + spl/u-boot-spl.bin since it doesn't enable CONFIG_SPL_OF_CONTROL) Writing to the board with USB = @@ -225,6 +307,153 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out truncate -s %2048 u-boot.bin cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out +Booting from an SD card on RK3399 += + +To write an image that boots from an SD card (assumed to be /dev/sdc): + +Option 1: Package the image with Rockchip miniloader: + + - Create idbloader.img + +=> cd /path/to/u-boot +=> ./tools/mkimage -n rk3399 -T rksd -d /path/to/rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin idbloader.img +=> cat /path/to/rkbin/bin/rk33/rk3399_miniloader_v1.19.bin >> idbloader.img + + - Write idbloader.img at 64 sector + +=> sudo dd if=idbloader.img of=/dev/sdc seek=64 + + - Write trust.img at 24576 + +=> sudo dd if=trust.img of=/dev/sdc seek=24576 + + - Write uboot.img at 16384 sector + +=> sudo dd if=uboot.img of=/dev/sdc seek=16384 +=> sync + +Put this SD (or micro-SD) card into your board and reset it. You should see +something like: + +DDR Version 1.20 20190314 +In +Channel 0: DDR3, 933MHz +Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB +no stride +ch 0 ddrconfig = 0x101, ddrsize = 0x20 +pmugrf_os_reg[2] = 0x10006281, stride = 0x17 +OUT +Boot1: 2019-03-14, version: 1.19 +CPUId = 0x0 +ChipType = 0x10, 239 +mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000 +mmc: ERROR: Card did not respond to voltage select! +emmc reinit +mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000 +mmc: ERROR: Card did not
[U-Boot] [RESEND PATCH v7 03/11] arm: rockchip: rk3399: Move common configs in Kconfig
Few SPL and U-Boot proper configs are common to all rk3399 target defconfigs, move them and select it from platform kconfig. Moved configs: - SPL_ATF - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - SPL_LOAD_FIT - SPL_CLK if SPL - SPL_PINCTRL if SPL - SPL_RAM if SPL - SPL_REGMAP if SPL - SPL_SYSCON if SPL - CLK - FIT - PINCTRL - RAM - REGMAP - SYSCON - DM_PMIC - DM_REGULATOR_FIXED Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig| 16 configs/chromebook_bob_defconfig | 16 configs/evb-rk3399_defconfig | 16 configs/ficus-rk3399_defconfig| 16 configs/firefly-rk3399_defconfig | 16 configs/orangepi-rk3399_defconfig | 16 configs/puma-rk3399_defconfig | 16 configs/rock960-rk3399_defconfig | 16 8 files changed, 16 insertions(+), 112 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f5c3329750..c05e3c3f48 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -156,11 +156,27 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SUPPORT_TPL select SPL + select SPL_ATF + select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_LOAD_FIT + select SPL_CLK if SPL + select SPL_PINCTRL if SPL + select SPL_RAM if SPL + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT + select CLK + select FIT + select PINCTRL + select RAM + select REGMAP + select SYSCON + select DM_PMIC + select DM_REGULATOR_FIXED select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER imply TPL_SERIAL_SUPPORT diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index bd836acad5..e61e27c992 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -17,8 +17,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -26,8 +24,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -46,12 +42,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -71,16 +61,10 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 94963e4280..f10502cb0e 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x8 CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y
[U-Boot] [RESEND PATCH v7 05/11] rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1
sdmmc cd pin is configured as RK_FUNC_GPIO which is wrong and
indeed failed to detect the sdcard on the board with below error
Card did not respond to voltage select!
So, fix it by replacing RK_FUNC_GPIO with RK_FUNC_1 which
is already defined in rk3399.dts so make use of same like
other boards.
Add these changes in -u-boot.dtsi to make Linux sync easy for future
changes.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
new file mode 100644
index 00..20db99c0b8
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_bus4 _clk _cmd _cd>;
+};
--
2.18.0.321.gffc6fa0e3
___
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[U-Boot] [RESEND PATCH v7 06/11] rockchip: rk3399: Add Nanopi M4 board support
Add initial support for Nanopi M4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- eMMC socket
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- USB 3.0 x4
- USB Type C power and data
- GPIO1, GPIO2 expansion ports
- DC5V/3A
Commit details of rk3399-nanopi-m4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: Refine nanopi4 differences"
(sha1: c62ffaf5026d0b7633e62b2cea8450b5543c349a)
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Reviewed-by: Philipp Tomsich
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 +++
arch/arm/dts/rk3399-nanopi-m4.dts | 66 +++
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 2 +
board/rockchip/evb_rk3399/MAINTAINERS | 6 +++
configs/nanopi-m4-rk3399_defconfig| 59
6 files changed, 141 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts
create mode 100644 configs/nanopi-m4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 35cbbfabd0..2a5bfd3fb5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-nanopi-m4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
diff --git a/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
new file mode 100644
index 00..17201bcf41
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopi-m4.dts
b/arch/arm/dts/rk3399-nanopi-m4.dts
new file mode 100644
index 00..60358ab8c7
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-m4.dts
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPi M4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi M4";
+ compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_core: vcc5v0-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_core";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_5v>;
+ };
+
+ vcc5v0_usb1: vcc5v0-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_sys>;
+ };
+
+ vcc5v0_usb2: vcc5v0-usb2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb2";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_sys>;
+ };
+};
+
+_sys {
+ vin-supply = <_core>;
+};
+
+_host {
+ phy-supply = <_usb1>;
+};
+
+_host {
+ phy-supply = <_usb2>;
+};
+
+_typec {
+ regulator-always-on;
+ vin-supply = <_5v>;
+};
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
index 20db99c0b8..05708b6f55 100644
--- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2019 Jagan Teki
*/
+#include "rk3399-u-boot.dtsi"
+
{
pinctrl-names = "default";
pinctrl-0 = <_bus4 _clk _cmd _cd>;
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index 07ee8ce92c..ae43805a6a 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h
F: configs/evb-rk3399_defconfig
F: configs/firefly-rk3399_defconfig
+NANOPI-M4
+M: Jagan Teki
+S: Maintained
+F: configs/nanopi-m4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+
ORANGEPI-RK3399
M: Jagan Teki
S: Maintained
diff --git a/configs/nanopi-m4-rk3399_defconfig
b/configs/nanopi-m4-rk3399_defconfig
new file mode 100644
index 00..c2832788f0
--- /dev/null
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
[U-Boot] [RESEND PATCH v7 04/11] rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.
Linux commit details about the rk3399-nanopi4.dtsi sync:
"arm64: dts: rockchip: Add nanopi4 bluetooth"
(sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)
Signed-off-by: Jagan Teki
Reviewed-by: Paul Kocialkowski
Reviewed-by: Kever Yang
---
arch/arm/dts/rk3399-nanopi4.dtsi | 703 +++
1 file changed, 703 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi
new file mode 100644
index 00..d325e11728
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi4.dtsi
@@ -0,0 +1,703 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * RK3399-based FriendlyElec boards device tree source
+ *
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc3v3_sys";
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-name = "vcc5v0_sys";
+ vin-supply = <_5v>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc1v8_s3";
+ vin-supply = <_1v8>;
+ };
+
+ vcc3v0_sd: vcc3v0-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pwr_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ regulator-name = "vcc3v0_sd";
+ vin-supply = <_sys>;
+ };
+
+ vbus_typec: vbus-typec {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-name = "vbus_typec";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <_key>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_gpio>;
+
+ status {
+ gpios = < RK_PB5 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = < 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_on_h>;
+ reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+_b0 {
+ cpu-supply = <_cpu_b>;
+};
+
+_b1 {
+ cpu-supply = <_cpu_b>;
+};
+
+_l0 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l1 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l2 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l3 {
+ cpu-supply = <_cpu_l>;
+};
+
+_phy {
+ status = "okay";
+};
+
+ {
+ assigned-clock-parents = <_gmac>;
+ assigned-clocks = < SCLK_RMII_SRC>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ phy-mode = "rgmii";
+ phy-supply = <_s3>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+
[U-Boot] [RESEND PATCH v7 01/11] rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2
To make successful build with dts(i) files syncing from Linux 5.1-rc2
the rk3399.dtsi would require pwm2_pin_pull_down.
So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this
node is strictly not part of any commit alone, I have mentioned
Linux 5.1-rc2 tag for future reference of where would this sync
coming from.
Signed-off-by: Jagan Teki
Reviewed-by: Paul Kocialkowski
Reviewed-by: Kever Yang
---
arch/arm/dts/rk3399.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index b53e41b4dc..b73442ee34 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -2495,6 +2495,11 @@
rockchip,pins =
<1 RK_PC3 RK_FUNC_1 _pull_none>;
};
+
+ pwm2_pin_pull_down: pwm2-pin-pull-down {
+ rockchip,pins =
+ <1 RK_PC3 RK_FUNC_1 _pull_down>;
+ };
};
pwm3a {
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [RESEND PATCH v7 00/11] rockchip: Add new rk3399 boards
(Sorry for the noice, I have missed to send two patches from v7) This is v7 resend patchset for New rk3399 boards support wrt previous version[1] Unfortunately initial version of creating rk3399-u-boot.dtsi and orangepi rk3399 changes are merged, so this is rework on top of u-boot-rockchip/master. Overall this series add support below rk3399 boards - NanoPI M4 - NanoPC T4 - NanoPI NEO4 - Orangepi RK3399 - Rock PI 4 - Rockpro64 All the respective dts(i) files are synced from Linux 5.1-rc2 and few dts(i) from linux-next. SoC u-boot specific dtsi rk3399-u-boot.dtsi changes are part of another series [3]. Out of all above boards Rockpor64, Rock-PI and Nanopi NEO4 would support booting via Rockchip miniloader as of now. For booting the same with SPL NEO4 would require dynamic dram timing detection and rest require LPDDR4 code. There is WIP[2] for these dependencies and this would require big chunk of changes will effect all the rk3399 boards, so I'm planning to mark it for next MW. Changes for v7: - rebase on top of u-boot-rockchip/master - add SPL_TEXT_BASE on each board defconfig - rebase on required changes Changes for v6: - Include Nanopc T4 support patch - drop rk3399-u-boot.dtsi patch since it is send separately. Changes for v5: - Make all changes related to move sdmmc, spi1 u-boot,dm-pre-reloc properties into all rk3399 dts(i) files. Changes for v4: - don't include existing dts(i) sdmmc, u-boot,dm-pre-reloc into rk3399-u-boot.dtsi Changes for v3: - drop NanoPC T4 for now, since board is yet to receive. - add Rock PI-4 board. - add separate -u-boot.dtsi file for nanopi4 sdram changes. - collect Paul, Philipp and Kever Reviewed-by tags Travis-CI: https://travis-ci.org/openedev/u-boot-amarula/builds/529284236 [1] https://patchwork.ozlabs.org/cover/1096473/ [2] https://github.com/amarula/u-boot-amarula/tree/rockdev-lpddr4 [3] https://patchwork.ozlabs.org/cover/1091909/ Any inputs? Jagan. Jagan Teki (11): rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2 Kconfig: Add default SPL_FIT_GENERATOR for rockchip arm: rockchip: rk3399: Move common configs in Kconfig rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1 rockchip: rk3399: Add Nanopi M4 board support rockchip: rk3399: Add Nanopc T4 board support rockchip: rk3399: Add Nanopi NEO4 board support rockchip: rk3399: Add Rockpro64 board support rockchip: rk3399: Add Rock PI 4 support doc: rockchip: Add global doc for rk3399 build/flash Kconfig | 1 + arch/arm/dts/Makefile | 5 + arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 + arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++ arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 + arch/arm/dts/rk3399-nanopi-m4.dts | 66 ++ arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-nanopi-neo4.dts | 50 ++ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 11 + arch/arm/dts/rk3399-nanopi4.dtsi| 703 +++ arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rock-pi-4.dts | 606 + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rockpro64.dts | 712 arch/arm/dts/rk3399.dtsi| 5 + arch/arm/mach-rockchip/Kconfig | 16 + board/rockchip/evb_rk3399/MAINTAINERS | 32 + configs/chromebook_bob_defconfig| 17 - configs/evb-rk3399_defconfig| 17 - configs/ficus-rk3399_defconfig | 17 - configs/firefly-rk3399_defconfig| 17 - configs/nanopc-t4-rk3399_defconfig | 59 ++ configs/nanopi-m4-rk3399_defconfig | 59 ++ configs/nanopi-neo4-rk3399_defconfig| 59 ++ configs/orangepi-rk3399_defconfig | 17 - configs/puma-rk3399_defconfig | 16 - configs/rock-pi-4-rk3399_defconfig | 59 ++ configs/rock960-rk3399_defconfig| 17 - configs/rockpro64-rk3399_defconfig | 59 ++ doc/README.rockchip | 233 ++- 30 files changed, 2857 insertions(+), 119 deletions(-) create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi create mode 100644 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock-pi-4.dts create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rockpro64.dts create mode 100644
Re: [U-Boot] [PATCH] bouncebuf: add feature to support buffer only available in DRAM
Hi Kever,
> Subject: [PATCH] bouncebuf: add feature to support buffer only available in
> DRAM
>
> Some DMA which inside peripheral controller can only access space in DRAM
> area, the target address outside DRAM is not available.
> eg. Rockchip MMC contrller's internal DMA can only access DRAM area.
>
> Add Kconfig option and driver for people who need it.
>
> Signed-off-by: Kever Yang
> ---
>
> common/bouncebuf.c | 9 +
> drivers/mmc/Kconfig | 6 ++
> 2 files changed, 15 insertions(+)
>
> diff --git a/common/bouncebuf.c b/common/bouncebuf.c index
> a7098e2caf..7ff2f488a4 100644
> --- a/common/bouncebuf.c
> +++ b/common/bouncebuf.c
> @@ -10,6 +10,8 @@
> #include
> #include
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> static int addr_aligned(struct bounce_buffer *state) {
> const ulong align_mask = ARCH_DMA_MINALIGN - 1; @@ -26,6 +28,13
> @@ static int addr_aligned(struct bounce_buffer *state)
> return 0;
> }
>
> +#ifdef MMC_BUF_IN_DRAM
> + if (((ulong)state->user_buffer < CONFIG_SYS_SDRAM_BASE) ||
> + ((ulong)state->user_buffer > gd->ram_top)) {
> + debug("Not support buffer address %p\n", state->user_buffer);
> + return 0;
> + }
> +#endif
> /* Aligned */
> return 1;
> }
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index
> c23299ea96..e852ee6175 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -671,6 +671,12 @@ config FSL_ESDHC
> This selects support for the eSDHC (enhanced secure digital host
> controller) found on numerous Freescale/NXP SoCs.
>
> +config MMC_BUF_IN_DRAM
> + bool "Only buffer in DRAM is available"
> + help
> + This selects support those controller whose internal DMA can only
> + access SDRAM spaces and other spaces are not available.
> +
I think introduce a new GEN_BB_FORCE flags might be better, no need to
introduce new kconfig entry, and it will be easier for others to use, if
there are other controllers has same limitation.
Regards,
Peng.
> endmenu
>
> config SYS_FSL_ERRATUM_ESDHC111
> --
> 2.20.1
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Re: [U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL
Hi Simon, On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote: > > Hi Bin, > > On Tue, 7 May 2019 at 21:33, Bin Meng wrote: > > > > Hi Simon, > > > > On Tue, May 7, 2019 at 6:07 PM Bin Meng wrote: > > > > > > Hi Simon, > > > > > > On Fri, May 3, 2019 at 12:52 AM Simon Glass wrote: > > > > > > > > At present SPL is used on 64-bit platforms, to allow SPL to be built as > > > > a 32-bit program and U-Boot proper to be built as 64-bit. > > > > > > > > However it is useful to be able to use SPL on any x86 platform, where > > > > U-Boot needs to be updated in the field. Then SPL can select which > > > > U-Boot > > > > to run (A or B) and most of the code can be updated. Similarly, using > > > > TPL > > > > allows both SPL and U-Boot to be updated. This is the best approach, > > > > since > > > > it means that all of U-Boot proper as well as SPL (in particular SDRAM > > > > init) can be updated in the field. This provides for the smallest > > > > possible > > > > amount of read-only (non-updateable) code: just the TPL code. > > > > > > > > This series contains a number of changes to allow x86 boards to use TPL, > > > > SPL and U-Boot proper. As a test, it is enabled for samus with a new > > > > chromebook_samus_tpl board. > > > > > > > > Changes in v3: > > > > - Rebase to x86/master > > > > - Use acpi_s3.h header for constants (and tidy up header order) > > > > - Fix multi-line comment format > > > > - Remove unneeded pch-reset node > > > > - Drop unnecessary change to chromebook_link_defconfig > > > > > > > > > > I applied 14 patches and left 4 below that have open questions: > > > http://patchwork.ozlabs.org/project/uboot/list/?series=105795 > > > > > > In the meantime, it looks that travis-ci complained some failures in > > > my last run for the applied patches. I will redo the travis-ci and let > > > you know the results. > > > > Travis-ci reported qemu-x86 is broken. I figured out the issue was due > > to the sysreset-x86 driver added platdata_auto_alloc_size that > > requires more memory. I will send a patch soon. > > OK thank you. I have sent v4 now. After applying "Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"" patch, qemu-x86 boots again :) So it looks that I don't need send the patch to increase the malloc memory for QEMU, at least for now. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/4] x86: samus: Add a target to boot through TPL
On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote: > > Add a version of samus which supports booting from TPL to SPL and then > to U-Boot. This allows TPL to select from an A or B SPL to support > verified boot with field upgrade. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: > - Sort defconfig and adjust it to build after rebase on maste > > board/google/Kconfig | 8 +++ > board/google/chromebook_samus/Kconfig | 14 +++- > board/google/chromebook_samus/MAINTAINERS | 7 ++ > configs/chromebook_samus_tpl_defconfig| 82 +++ > include/configs/chromebook_samus.h| 2 + > 5 files changed, 111 insertions(+), 2 deletions(-) > create mode 100644 configs/chromebook_samus_tpl_defconfig > applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/4] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote: > > This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. > > Unfortunately this has a dramatic impact on the pre-relocation memory > used on x86 platforms (increasing it by 2KB) since it increases the > overhead for each PCI device from 220 bytes to 412 bytes. > > The offending line is in UCLASS_DRIVER(pci): > > .per_device_auto_alloc_size = sizeof(struct pci_controller), > > This means that all PCI devices have the controller struct associated > with them. The solution is to move the regions[] member out of the array, > makes its size dynamic, or split UCLASS_PCI into controllers and > non-controllers, as the comment suggests. > > For now, revert the commit to get things running again. > > Reviewed-by: Bin Meng > Signed-off-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > include/pci.h | 6 +- > 1 file changed, 1 insertion(+), 5 deletions(-) > applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/4] x86: samus: Update device tree for verified boot
On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote: > > Add nvdata drivers for the TPM and RTC as used on samus. These are needed > for Chromium OS verified boot on samus. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/x86/dts/chromebook_samus.dts | 22 +- > 1 file changed, 21 insertions(+), 1 deletion(-) > applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/4] x86: samus: Update device tree for SPL
On Wed, May 8, 2019 at 12:40 PM Bin Meng wrote: > > On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote: > > > > Add tags to allow required nodes to be present in SPL / TPL. > > > > Signed-off-by: Simon Glass > > > > --- > > > > Changes in v4: > > - Update commit message to not mention the sysreset driver. > > - Drop change to SPI flash memory-map property > > > > Changes in v3: > > - Remove unneeded pch-reset node > > > > Changes in v2: None > > > > arch/x86/dts/chromebook_samus.dts | 31 --- > > 1 file changed, 28 insertions(+), 3 deletions(-) > > > > Reviewed-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/4] x86: samus: Update device tree for SPL
On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote: > > Add tags to allow required nodes to be present in SPL / TPL. > > Signed-off-by: Simon Glass > > --- > > Changes in v4: > - Update commit message to not mention the sysreset driver. > - Drop change to SPI flash memory-map property > > Changes in v3: > - Remove unneeded pch-reset node > > Changes in v2: None > > arch/x86/dts/chromebook_samus.dts | 31 --- > 1 file changed, 28 insertions(+), 3 deletions(-) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 00/13] System Firmware Loader for TI K3 family SoCs
On Tue, 2019-05-07 at 22:00 +0200, Simon Goldschmidt wrote:
>
> On 07.05.19 19:25, Andreas Dannenberg wrote:
> >
[...]
> >
> > While I also have a working solution based on the existing FS
> > loader
> > framework this has its own challenges, namely by its very nature
> > only
> > addressing a subset of our use cases (no eMMC/SD RAW boot support
> > for
> > example),
IMO, it's actually not that hard to enhance RAW support, i think
minimal changes are required. I have attached the patches about an
example of loading RAW from QSPI that i have done locally last few week
ago.
> > being heavier on resource usage (needing to use ENV to pass
> > parameters),
ENV is optional, you can use DTS. For example loading FPGA bitstream
from QSPI RAW:
/* DTS */
/ {
+ aliases {
+ spi0 =
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ sfconfig = <0 0 1 3>;
+ };
+};
+
+_mgr {
+ u-boot,dm-pre-reloc;
+ firmware-loader = <_loader0>;
+ altr,bitstream = "30";
+};
> > and not addressing the need to probe the boot peripheral.
You can add more different probing method in function called
"fs_loader_probe". Current fs_loader supports block(sdmmc, emmc, etc...)
probing, and with
the patches attached support QSPI probing.
Another idea come to mind, we can use fs_loader for loading FIT boot
image into RAM, and boot from RAM with existing SPL loader framework,
but i'm not sure this implementation fit to your use case?
> > This particular framework works well for use cases requiring to
> > load
> > firmware from FS-based media once DDR is up and U-Boot is in a more
> > "initialized" state but it is not a one-fits all solution for very
> > early use in SPL board_init_f() accross different boot modes.
> And would it be an option to improve the loader (maybe dropping the
> "fs"
> from its name)? I think it's an "fs" loader because its idea has
> been
> copied from Linux. I think in U-Boot, it's more common to have things
> at
> a raw offset instead of a file system. Just thinking...
Current fs_loader only support filesystem, and i agree that it made
sense to remove the "fs" once it supports the RAW offset as well.
Thanks.
Regards,
TF
>
> And the current state of that fs_loader is like it is because it
> fits
> its single user (socfpga stratix 10), I think.
>
> Anyway, even if you do need yet another loader, would it make sense
> to
> create a common file instead of adding this in your arch/mach?
>
> Regards,
> Simon
>
> >
> >
> > Andreas Dannenberg (10):
> > mmc: k3_arasan: Allow driver to probe without PDs specified
> > spl: Allow skipping clearing BSS during relocation
> > spl: Make image loader infrastructure more universal
> > arm: K3: Introduce System Firmware loader framework
> > armV7R: K3: am654: Allow using SPL BSS pre-relocation
> > armv7R: K3: am654: Use full malloc implementation in SPL
> > armV7R: K3: am654: Load SYSFW binary and config from boot media
> > configs: am65x_evm_r5: All sysfw to be loaded via MMC
> > configs: am65x_hs_evm_r5: All sysfw to be loaded via MMC
> > configs: am65x_hs_evm: Add Support for eMMC boot
> >
> > Faiz Abbas (2):
> > configs: am65x_evm: Add Support for eMMC boot
> > am65x: README: Add eMMC layout and flash instructions
> >
> > Lokesh Vutla (1):
> > armv7R: dts: k3: am654: Update mmc nodes for loading sysfw
> >
> > arch/arm/dts/k3-am654-r5-base-board.dts | 18 ++
> > arch/arm/lib/crt0.S | 3 +
> > arch/arm/mach-k3/Kconfig | 40 +++
> > arch/arm/mach-k3/Makefile| 1 +
> > arch/arm/mach-k3/am6_init.c | 34 ++-
> > arch/arm/mach-k3/include/mach/sysfw-loader.h | 12 +
> > arch/arm/mach-k3/sysfw-loader.c | 263
> > +++
> > board/ti/am65x/Kconfig | 1 +
> > board/ti/am65x/README| 52
> > common/spl/Kconfig | 13 +
> > common/spl/spl_fit.c | 14 +
> > common/spl/spl_mmc.c | 76 --
> > configs/am65x_evm_a53_defconfig | 2 +
> > configs/am65x_evm_r5_defconfig | 7 +-
> > configs/am65x_hs_evm_a53_defconfig | 2 +
> > configs/am65x_hs_evm_r5_defconfig| 7 +-
> > drivers/mmc/k3_arsan_sdhci.c | 16 +-
> > include/configs/am65x_evm.h | 30 ++-
> > include/spl.h| 26 ++
> > 19 files changed, 577 insertions(+), 40 deletions(-)
> > create mode 100644 arch/arm/mach-k3/include/mach/sysfw-loader.h
> > create mode 100644 arch/arm/mach-k3/sysfw-loader.c
> > From ff0fa68b8141fa7c83b3b42e7d6cf5a6bc27c980 Mon Sep 17 00:00:00 2001
From: Tien Fong Chee
Date: Mon, 15 Apr 2019 14:02:44 +0800
Subject:
Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> >
> >
> >
> > On 07.05.19 21:41, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > >
> > > > > According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page
> > > > > 175
> > > > > (Chapter 5, FPGA Manager, data register) and Arria10
> > > > > datasheet
> > > > > rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager,
> > > > > img_data_w
> > > > > register), the FPGA data register must be written with writes
> > > > > with
> > > > > non-incrementing address.
> > > > >
> > > > > The current code increments the address in 32-byte bursts.
> > > > > Fix the
> > > > > code so it does not increment the address and writes the
> > > > > register
> > > > > repeatedly instead. >
> > > > > Signed-off-by: Marek Vasut
> > > > > Cc: Chin Liang See
> > > > > Cc: Dinh Nguyen
> > > > > Cc: Simon Goldschmidt
> > > > > Cc: Tien Fong Chee
> > > > > ---
> > > > > drivers/fpga/socfpga.c | 3 +--
> > > > > 1 file changed, 1 insertion(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> > > > > index 685957626b..6ecea771ce 100644
> > > > > --- a/drivers/fpga/socfpga.c
> > > > > +++ b/drivers/fpga/socfpga.c
> > > > > @@ -55,8 +55,7 @@ void fpgamgr_program_write(const void
> > > > > *rbf_data,
> > > > > size_t rbf_size)
> > > > > " cmp %2, #0\n"
> > > > > " beq 2f\n"
> > > > > "1: ldmia %0!, {r0-r7}\n"
> > > > > - " stmia %1!, {r0-r7}\n"
> > > > > - " sub %1, #32\n"
> > > > > + " stmia %1, {r0-r7}\n"
> > > > Iirc, stmia without the "!" still stores the registers to
> > > > different
> > > > addresses, it just does not change %1 any more if you leave
> > > > away the
> > > > "!"? So this would save on opcode, but not change anything?
> > > Uh oh, you're right. Do we have a bigger problem here then ? Or
> > > is the
> > > socfpga ignoring the bottom 5 bits of this register address ?
> > Well, bitsream programming works for me very well (we're loading
> > all our
> > FGPAs in U-Boot from a FIT image), so maybe it's the documentation
> > that
> > has a problem?
> That could indeed be, maybe someone on the CC list can take a look
> into
> it and crosscheck it with internal docs ?
sure. let me check.
Thanks for finding.
>
___
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Re: [U-Boot] [PATCH] configs: stratix10: Enable CONFIG_SPI_FLASH_USE_4K_SECTORS
On 5/8/19 5:07 AM, Ley Foon Tan wrote: > Fix SPI flash environment erase size error. > > CONFIG_ENV_SECT_SIZE is set to 4KB. Enable CONFIG_SPI_FLASH_USE_4K_SECTORS > to allow erase one environment sector. > > Fix error below: > > SOCFPGA_STRATIX10 # saveenv > Saving Environment to SPI Flash... > SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 > MiB > Erasing SPI flash...SF: Erase offset/length not multiple of erase size > Failed (-22) > > Signed-off-by: Ley Foon Tan > --- > configs/socfpga_stratix10_defconfig | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/configs/socfpga_stratix10_defconfig > b/configs/socfpga_stratix10_defconfig > index 73a1231d46..4be85d53ab 100644 > --- a/configs/socfpga_stratix10_defconfig > +++ b/configs/socfpga_stratix10_defconfig > @@ -41,7 +41,6 @@ CONFIG_SPI_FLASH=y > CONFIG_SF_DEFAULT_MODE=0x2003 > CONFIG_SPI_FLASH_SPANSION=y > CONFIG_SPI_FLASH_STMICRO=y > -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > CONFIG_PHY_MICREL=y > CONFIG_PHY_MICREL_KSZ90X1=y > CONFIG_DM_ETH=y > Applied, thanks. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v7 08/11] rockchip: rk3399: Add Nanopi NEO4 board support
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Add initial support for Nanopi NEO4 board.
>
> Specification
> - Rockchip RK3399
> - 1GB DDR3-1866
> - SD card slot
> - eMMC Socket
> - RTL8211E 1Gbps
> - AP6212 WiFI/BT
> - HDMI In/Out, DP, MIPI CSI
> - USB 3.0, 2.0
> - USB Type C power and data
> - GPIO expansion ports
> - DC 5V/3A
>
> Commit details of rk3399-nanopi-neo4.dts sync from Linux:
> "arm64: dts: rockchip: Add Nanopi NEO4 initial support"
> (sha1: 092470b537f19788d957aed12d835a179b606014)
>
> Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 +++
> arch/arm/dts/rk3399-nanopi-neo4.dts | 50 +
> board/rockchip/evb_rk3399/MAINTAINERS | 6 +++
> configs/nanopi-neo4-rk3399_defconfig| 59 +
> 5 files changed, 122 insertions(+)
> create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts
> create mode 100644 configs/nanopi-neo4-rk3399_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index adaca524c3..529c506b4d 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
> rk3399-gru-bob.dtb \
> rk3399-nanopc-t4.dtb \
> rk3399-nanopi-m4.dtb \
> + rk3399-nanopi-neo4.dtb \
> rk3399-orangepi.dtb \
> rk3399-puma-ddr1333.dtb \
> rk3399-puma-ddr1600.dtb \
> diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
> b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
> new file mode 100644
> index 00..7d22528f49
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> +#include "rk3399-nanopi4-u-boot.dtsi"
> diff --git a/arch/arm/dts/rk3399-nanopi-neo4.dts
> b/arch/arm/dts/rk3399-nanopi-neo4.dts
> new file mode 100644
> index 00..195410b089
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-nanopi-neo4.dts
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Amarula Solutions B.V.
> + * Author: Jagan Teki
> + */
> +
> +/dts-v1/;
> +
> +#include "rk3399-nanopi4.dtsi"
> +
> +/ {
> + model = "FriendlyARM NanoPi NEO4";
> + compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399";
> +
> + vdd_5v: vdd-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_5v";
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vcc5v0_core: vcc5v0-core {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_core";
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <_5v>;
> + };
> +
> + vcc5v0_usb1: vcc5v0-usb1 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_usb1";
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <_sys>;
> + };
> +};
> +
> +_sys {
> + vin-supply = <_core>;
> +};
> +
> +_host {
> + phy-supply = <_usb1>;
> +};
> +
> +_typec {
> + regulator-always-on;
> + vin-supply = <_5v>;
> +};
> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
> b/board/rockchip/evb_rk3399/MAINTAINERS
> index f55c92f80c..1f51f65160 100644
> --- a/board/rockchip/evb_rk3399/MAINTAINERS
> +++ b/board/rockchip/evb_rk3399/MAINTAINERS
> @@ -18,6 +18,12 @@ S: Maintained
> F: configs/nanopi-m4-rk3399_defconfig
> F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
>
> +NANOPI-NEO4
> +M: Jagan Teki
> +S: Maintained
> +F: configs/nanopi-neo4-rk3399_defconfig
> +F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
> +
> ORANGEPI-RK3399
> M: Jagan Teki
> S: Maintained
> diff --git a/configs/nanopi-neo4-rk3399_defconfig
> b/configs/nanopi-neo4-rk3399_defconfig
> new file mode 100644
> index 00..188656a2b4
> --- /dev/null
> +++ b/configs/nanopi-neo4-rk3399_defconfig
> @@ -0,0 +1,59 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_TEXT_BASE=0x0020
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x4000
> +CONFIG_ROCKCHIP_RK3399=y
> +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
> +CONFIG_DEBUG_UART_BASE=0xFF1A
> +CONFIG_DEBUG_UART_CLOCK=2400
> +CONFIG_SPL_STACK_R_ADDR=0x8
> +CONFIG_DEBUG_UART=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_TEXT_BASE=0xff8c2000
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_TIME=y
>
Re: [U-Boot] [PATCH v7 09/11] rockchip: rk3399: Add Rockpro64 board support
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Add initial support for Rockpro64 board.
>
> Specification
> - Rockchip RK3399
> - 2/4GB Dual-Channel LPDDR3
> - SD card slot
> - eMMC socket
> - 128Mb SPI Flash
> - Gigabit ethernet
> - PCIe 4X slot
> - WiFI/BT module socket
> - HDMI In/Out, DP, MIPI DSI/CSI, eDP
> - USB 3.0, 2.0
> - USB Type C power and data
> - GPIO expansion ports
> - DC 12V/2A
>
> Commit details of rk3399-rockpro64.dts sync from Linux 5.1-rc2:
> "arm64: dts: rockchip: rockpro64 dts add usb regulator"
> (sha1: 6db644c79c8d45d73b56bc389aebd85fc3679beb)
>
> 'Akash' has sent an initial patch before, so I keep him as board
> maintainer and I'm co-maintainer based on our conversation.
>
> Signed-off-by: Akash Gajjar
> Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 +
> arch/arm/dts/rk3399-rockpro64.dts | 712 ++
> board/rockchip/evb_rk3399/MAINTAINERS | 7 +
> configs/rockpro64-rk3399_defconfig| 59 ++
> 5 files changed, 785 insertions(+)
> create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3399-rockpro64.dts
> create mode 100644 configs/rockpro64-rk3399_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 529c506b4d..8522f01aca 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -114,6 +114,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
> rk3399-puma-ddr1600.dtb \
> rk3399-puma-ddr1866.dtb \
> rk3399-rock960.dtb \
> + rk3399-rockpro64.dtb
>
> dtb-$(CONFIG_ROCKCHIP_RV1108) += \
> rv1108-elgin-r1.dtb \
> diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
> b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
> new file mode 100644
> index 00..7bddc3acdb
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> +#include "rk3399-u-boot.dtsi"
> diff --git a/arch/arm/dts/rk3399-rockpro64.dts
> b/arch/arm/dts/rk3399-rockpro64.dts
> new file mode 100644
> index 00..1f2394e058
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-rockpro64.dts
> @@ -0,0 +1,712 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
> + * Copyright (c) 2018 Akash Gajjar
> + */
> +
> +/dts-v1/;
> +#include
> +#include
> +#include "rk3399.dtsi"
> +#include "rk3399-opp.dtsi"
> +
> +/ {
> + model = "Pine64 RockPro64";
> + compatible = "pine64,rockpro64", "rockchip,rk3399";
> +
> + chosen {
> + stdout-path = "serial2:150n8";
> + };
> +
> + clkin_gmac: external-gmac-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <12500>;
> + clock-output-names = "clkin_gmac";
> + #clock-cells = <0>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + autorepeat;
> + pinctrl-names = "default";
> + pinctrl-0 = <>;
> +
> + power {
> + debounce-interval = <100>;
> + gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
> + label = "GPIO Key Power";
> + linux,code = ;
> + wakeup-source;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <_led_gpio>, <_led_gpio>;
> +
> + work-led {
> + label = "work";
> + default-state = "on";
> + gpios = < RK_PB3 GPIO_ACTIVE_HIGH>;
> + };
> +
> + diy-led {
> + label = "diy";
> + default-state = "off";
> + gpios = < RK_PA2 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + sdio_pwrseq: sdio-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + clocks = < 1>;
> + clock-names = "ext_clock";
> + pinctrl-names = "default";
> + pinctrl-0 = <_enable_h>;
> +
> + /*
> + * On the module itself this is one of these (depending
> + * on the actual card populated):
> + * - SDIO_RESET_L_WL_REG_ON
> + * - PDN (power down when low)
> + */
> + reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
> + };
> +
> + vcc12v_dcin: vcc12v-dcin {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc12v_dcin";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1200>;
> + regulator-max-microvolt = <1200>;
> + };
> +
> + /* switched by pmic_sleep */
> + vcc1v8_s3:
Re: [U-Boot] [PATCH v7 07/11] rockchip: rk3399: Add Nanopc T4 board support
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Add initial support for Nanopc T4 board.
>
> Specification
> - Rockchip RK3399
> - Dual-Channel 4GB LPDDR3-1866
> - SD card slot
> - 16GB eMMC
> - RTL8211E 1Gbps
> - AP6356S WiFI/BT
> - HDMI In/Out, DP, MIPI DSI/CSI, eDP
> - USB 3.0, 2.0
> - USB Type C power and data
> - GPIO expansion ports
> - DC 12V/2A
>
> Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2:
> "arm64: dts: rockchip: Add NanoPC-T4 IR receiver"
> (sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3)
>
> Tested-by: Daniel Gröber
> Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 ++
> arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++
> board/rockchip/evb_rk3399/MAINTAINERS | 6 ++
> configs/nanopc-t4-rk3399_defconfig| 59 +++
> 5 files changed, 164 insertions(+)
> create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts
> create mode 100644 configs/nanopc-t4-rk3399_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 2a5bfd3fb5..adaca524c3 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
> rk3399-ficus.dtb \
> rk3399-firefly.dtb \
> rk3399-gru-bob.dtb \
> + rk3399-nanopc-t4.dtb \
> rk3399-nanopi-m4.dtb \
> rk3399-orangepi.dtb \
> rk3399-puma-ddr1333.dtb \
> diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
> b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
> new file mode 100644
> index 00..17201bcf41
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
> @@ -0,0 +1,7 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> +#include "rk3399-nanopi4-u-boot.dtsi"
> +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
> diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts
> b/arch/arm/dts/rk3399-nanopc-t4.dts
> new file mode 100644
> index 00..84433cf02b
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-nanopc-t4.dts
> @@ -0,0 +1,91 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * FriendlyElec NanoPC-T4 board device tree source
> + *
> + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
> + * (http://www.friendlyarm.com)
> + *
> + * Copyright (c) 2018 Collabora Ltd.
> + */
> +
> +/dts-v1/;
> +#include "rk3399-nanopi4.dtsi"
> +
> +/ {
> + model = "FriendlyElec NanoPC-T4";
> + compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
> +
> + vcc12v0_sys: vcc12v0-sys {
> + compatible = "regulator-fixed";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <1200>;
> + regulator-min-microvolt = <1200>;
> + regulator-name = "vcc12v0_sys";
> + };
> +
> + vcc5v0_host0: vcc5v0-host0 {
> + compatible = "regulator-fixed";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-name = "vcc5v0_host0";
> + vin-supply = <_sys>;
> + };
> +
> + adc-keys {
> + compatible = "adc-keys";
> + io-channels = < 1>;
> + io-channel-names = "buttons";
> + keyup-threshold-microvolt = <180>;
> + poll-interval = <100>;
> +
> + recovery {
> + label = "Recovery";
> + linux,code = ;
> + press-threshold-microvolt = <18000>;
> + };
> + };
> +
> + ir-receiver {
> + compatible = "gpio-ir-receiver";
> + gpios = < RK_PA6 GPIO_ACTIVE_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_rx>;
> + };
> +};
> +
> + {
> + ir {
> + ir_rx: ir-rx {
> + /* external pullup to VCC3V3_SYS, despite being 1.8V :/
> */
> + rockchip,pins = <0 RK_PA6 RK_FUNC_1 _pull_none>;
> + };
> + };
> +};
> +
> + {
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
> +};
> +
> +_host {
> + phy-supply = <_host0>;
> +};
> +
> +_host {
> + phy-supply = <_host0>;
> +};
> +
> +_sys {
> + vin-supply = <_sys>;
> +};
> +
> +_sys {
> + vin-supply = <_sys>;
> +};
> +
> +_typec {
> + enable-active-high;
> + gpios = < RK_PD2 GPIO_ACTIVE_HIGH>;
> + vin-supply = <_sys>;
> +};
> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
> b/board/rockchip/evb_rk3399/MAINTAINERS
> index ae43805a6a..f55c92f80c 100644
> --- a/board/rockchip/evb_rk3399/MAINTAINERS
> +++ b/board/rockchip/evb_rk3399/MAINTAINERS
> @@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h
> F: configs/evb-rk3399_defconfig
> F: configs/firefly-rk3399_defconfig
>
> +NANOPC-T4
> +M: Jagan Teki
> +S: Maintained
> +F:
Re: [U-Boot] [PATCH v7 05/11] rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> sdmmc cd pin is configured as RK_FUNC_GPIO which is wrong and
> indeed failed to detect the sdcard on the board with below error
>
> Card did not respond to voltage select!
>
> So, fix it by replacing RK_FUNC_GPIO with RK_FUNC_1 which
> is already defined in rk3399.dts so make use of same like
> other boards.
>
> Add these changes in -u-boot.dtsi to make Linux sync easy for future
> changes.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
> arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 9 +
> 1 file changed, 9 insertions(+)
> create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
>
> diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
> b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
> new file mode 100644
> index 00..20db99c0b8
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_bus4 _clk _cmd _cd>;
> +};
___
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U-Boot@lists.denx.de
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Re: [U-Boot] [PATCH v7 04/11] rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.
>
> Linux commit details about the rk3399-nanopi4.dtsi sync:
> "arm64: dts: rockchip: Add nanopi4 bluetooth"
> (sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)
>
> Signed-off-by: Jagan Teki
> Reviewed-by: Paul Kocialkowski
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
> arch/arm/dts/rk3399-nanopi4.dtsi | 703 +++
> 1 file changed, 703 insertions(+)
> create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi
>
> diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi
> b/arch/arm/dts/rk3399-nanopi4.dtsi
> new file mode 100644
> index 00..d325e11728
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-nanopi4.dtsi
> @@ -0,0 +1,703 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * RK3399-based FriendlyElec boards device tree source
> + *
> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
> + * (http://www.friendlyarm.com)
> + *
> + * Copyright (c) 2018 Collabora Ltd.
> + * Copyright (c) 2019 Arm Ltd.
> + */
> +
> +/dts-v1/;
> +#include
> +#include "rk3399.dtsi"
> +#include "rk3399-opp.dtsi"
> +
> +/ {
> + chosen {
> + stdout-path = "serial2:150n8";
> + };
> +
> + clkin_gmac: external-gmac-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <12500>;
> + clock-output-names = "clkin_gmac";
> + #clock-cells = <0>;
> + };
> +
> + vcc3v3_sys: vcc3v3-sys {
> + compatible = "regulator-fixed";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-name = "vcc3v3_sys";
> + };
> +
> + vcc5v0_sys: vcc5v0-sys {
> + compatible = "regulator-fixed";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <500>;
> + regulator-max-microvolt = <500>;
> + regulator-name = "vcc5v0_sys";
> + vin-supply = <_5v>;
> + };
> +
> + /* switched by pmic_sleep */
> + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
> + compatible = "regulator-fixed";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + regulator-name = "vcc1v8_s3";
> + vin-supply = <_1v8>;
> + };
> +
> + vcc3v0_sd: vcc3v0-sd {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = < RK_PA1 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_pwr_h>;
> + regulator-always-on;
> + regulator-min-microvolt = <300>;
> + regulator-max-microvolt = <300>;
> + regulator-name = "vcc3v0_sd";
> + vin-supply = <_sys>;
> + };
> +
> + vbus_typec: vbus-typec {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <500>;
> + regulator-max-microvolt = <500>;
> + regulator-name = "vbus_typec";
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + autorepeat;
> + pinctrl-names = "default";
> + pinctrl-0 = <_key>;
> +
> + power {
> + debounce-interval = <100>;
> + gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
> + label = "GPIO Key Power";
> + linux,code = ;
> + wakeup-source;
> + };
> + };
> +
> + leds: gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <_gpio>;
> +
> + status {
> + gpios = < RK_PB5 GPIO_ACTIVE_HIGH>;
> + label = "status_led";
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +
> + sdio_pwrseq: sdio-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + clocks = < 1>;
> + clock-names = "ext_clock";
> + pinctrl-names = "default";
> + pinctrl-0 = <_reg_on_h>;
> + reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +_b0 {
> + cpu-supply = <_cpu_b>;
> +};
> +
> +_b1 {
> + cpu-supply = <_cpu_b>;
> +};
> +
> +_l0 {
> + cpu-supply = <_cpu_l>;
> +};
> +
> +_l1 {
> + cpu-supply = <_cpu_l>;
> +};
> +
> +_l2 {
> + cpu-supply = <_cpu_l>;
> +};
> +
> +_l3 {
> + cpu-supply = <_cpu_l>;
> +};
> +
> +_phy {
> + status = "okay";
> +};
> +
> + {
> + assigned-clock-parents = <_gmac>;
> + assigned-clocks = < SCLK_RMII_SRC>;
> + clock_in_out = "input";
>
Re: [U-Boot] [PATCH v7 03/11] arm: rockchip: rk3399: Move common configs in Kconfig
On 05/08/2019 02:36 AM, Jagan Teki wrote: > Few SPL and U-Boot proper configs are common to all rk3399 target > defconfigs, move them and select it from platform kconfig. > > Moved configs: > - SPL_ATF > - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF > - SPL_LOAD_FIT > - SPL_CLK if SPL > - SPL_PINCTRL if SPL > - SPL_RAM if SPL > - SPL_REGMAP if SPL > - SPL_SYSCON if SPL > - CLK > - FIT > - PINCTRL > - RAM > - REGMAP > - SYSCON > - DM_PMIC > - DM_REGULATOR_FIXED > > Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever > --- > arch/arm/mach-rockchip/Kconfig| 16 > configs/chromebook_bob_defconfig | 16 > configs/evb-rk3399_defconfig | 16 > configs/ficus-rk3399_defconfig| 16 > configs/firefly-rk3399_defconfig | 16 > configs/orangepi-rk3399_defconfig | 16 > configs/puma-rk3399_defconfig | 16 > configs/rock960-rk3399_defconfig | 16 > 8 files changed, 16 insertions(+), 112 deletions(-) > > diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig > index f5c3329750..c05e3c3f48 100644 > --- a/arch/arm/mach-rockchip/Kconfig > +++ b/arch/arm/mach-rockchip/Kconfig > @@ -156,11 +156,27 @@ config ROCKCHIP_RK3399 > select SUPPORT_SPL > select SUPPORT_TPL > select SPL > + select SPL_ATF > + select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF > + select SPL_LOAD_FIT > + select SPL_CLK if SPL > + select SPL_PINCTRL if SPL > + select SPL_RAM if SPL > + select SPL_REGMAP if SPL > + select SPL_SYSCON if SPL > select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL > select TPL_NEEDS_SEPARATE_STACK if TPL > select SPL_SEPARATE_BSS > select SPL_SERIAL_SUPPORT > select SPL_DRIVERS_MISC_SUPPORT > + select CLK > + select FIT > + select PINCTRL > + select RAM > + select REGMAP > + select SYSCON > + select DM_PMIC > + select DM_REGULATOR_FIXED > select BOARD_LATE_INIT > select ROCKCHIP_BROM_HELPER > imply TPL_SERIAL_SUPPORT > diff --git a/configs/chromebook_bob_defconfig > b/configs/chromebook_bob_defconfig > index bd836acad5..e61e27c992 100644 > --- a/configs/chromebook_bob_defconfig > +++ b/configs/chromebook_bob_defconfig > @@ -17,8 +17,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 > CONFIG_SPL_SPI_FLASH_SUPPORT=y > CONFIG_SPL_SPI_SUPPORT=y > CONFIG_DEBUG_UART=y > -CONFIG_FIT=y > -CONFIG_SPL_LOAD_FIT=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > @@ -26,8 +24,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 > CONFIG_SPL_STACK_R=y > CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 > CONFIG_SPL_SPI_LOAD=y > -CONFIG_SPL_ATF=y > -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > CONFIG_CMD_BOOTZ=y > CONFIG_CMD_GPIO=y > CONFIG_CMD_GPT=y > @@ -46,12 +42,6 @@ CONFIG_SPL_OF_CONTROL=y > CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" > CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names > interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" > CONFIG_ENV_IS_IN_MMC=y > -CONFIG_REGMAP=y > -CONFIG_SPL_REGMAP=y > -CONFIG_SYSCON=y > -CONFIG_SPL_SYSCON=y > -CONFIG_CLK=y > -CONFIG_SPL_CLK=y > CONFIG_ROCKCHIP_GPIO=y > CONFIG_I2C_CROS_EC_TUNNEL=y > CONFIG_SYS_I2C_ROCKCHIP=y > @@ -71,16 +61,10 @@ CONFIG_SPI_FLASH_GIGADEVICE=y > CONFIG_DM_ETH=y > CONFIG_ETH_DESIGNWARE=y > CONFIG_GMAC_ROCKCHIP=y > -CONFIG_PINCTRL=y > -CONFIG_SPL_PINCTRL=y > -CONFIG_DM_PMIC=y > CONFIG_PMIC_RK8XX=y > CONFIG_REGULATOR_PWM=y > -CONFIG_DM_REGULATOR_FIXED=y > CONFIG_REGULATOR_RK8XX=y > CONFIG_PWM_ROCKCHIP=y > -CONFIG_RAM=y > -CONFIG_SPL_RAM=y > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_ROCKCHIP_SPI=y > CONFIG_SYSRESET=y > diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig > index 94963e4280..f10502cb0e 100644 > --- a/configs/evb-rk3399_defconfig > +++ b/configs/evb-rk3399_defconfig > @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x8 > CONFIG_DEBUG_UART_BASE=0xFF1A > CONFIG_DEBUG_UART_CLOCK=2400 > CONFIG_DEBUG_UART=y > -CONFIG_FIT=y > -CONFIG_SPL_LOAD_FIT=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > CONFIG_SPL_STACK_R=y > CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1 > -CONFIG_SPL_ATF=y > -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > CONFIG_TPL=y > CONFIG_CMD_BOOTZ=y > CONFIG_CMD_GPT=y > @@ -33,12 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" > CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names > interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" > CONFIG_ENV_IS_IN_MMC=y > CONFIG_NET_RANDOM_ETHADDR=y > -CONFIG_REGMAP=y > -CONFIG_SPL_REGMAP=y > -CONFIG_SYSCON=y > -CONFIG_SPL_SYSCON=y > -CONFIG_CLK=y > -CONFIG_SPL_CLK=y > CONFIG_ROCKCHIP_GPIO=y > CONFIG_SYS_I2C_ROCKCHIP=y > CONFIG_MMC_DW=y > @@
Re: [U-Boot] [PATCH v7 02/11] Kconfig: Add default SPL_FIT_GENERATOR for rockchip
On 05/08/2019 02:36 AM, Jagan Teki wrote: > Add default SPL_FIT_GENERATOR py script for rockchip platforms if > specific target enabled SPL_LOAD_FIT. > > So, this would help get rid of explicitly mentioning the default > SPL FIT generator in defconfigs. however some targets, like puma_rk3399 > still require their own FIT generator so in those cases the default will > override with defconfig defined generator. > > Reviewed-by: Paul Kocialkowski > Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever > --- > Kconfig | 1 + > configs/chromebook_bob_defconfig | 1 - > configs/evb-rk3399_defconfig | 1 - > configs/ficus-rk3399_defconfig| 1 - > configs/firefly-rk3399_defconfig | 1 - > configs/orangepi-rk3399_defconfig | 1 - > configs/rock960-rk3399_defconfig | 1 - > 7 files changed, 1 insertion(+), 6 deletions(-) > > diff --git a/Kconfig b/Kconfig > index 7a5491bd67..91c1082ace 100644 > --- a/Kconfig > +++ b/Kconfig > @@ -435,6 +435,7 @@ config SPL_FIT_GENERATOR > string ".its file generator script for U-Boot FIT image" > depends on SPL_FIT > default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI > + default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && > ARCH_ROCKCHIP > help > Specifies a (platform specific) script file to generate the FIT > source file used to build the U-Boot FIT image file. This gets > diff --git a/configs/chromebook_bob_defconfig > b/configs/chromebook_bob_defconfig > index ce07a7f0ff..bd836acad5 100644 > --- a/configs/chromebook_bob_defconfig > +++ b/configs/chromebook_bob_defconfig > @@ -19,7 +19,6 @@ CONFIG_SPL_SPI_SUPPORT=y > CONFIG_DEBUG_UART=y > CONFIG_FIT=y > CONFIG_SPL_LOAD_FIT=y > -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig > index 5bb910e8d4..94963e4280 100644 > --- a/configs/evb-rk3399_defconfig > +++ b/configs/evb-rk3399_defconfig > @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 > CONFIG_DEBUG_UART=y > CONFIG_FIT=y > CONFIG_SPL_LOAD_FIT=y > -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig > index 79da86b32f..926d244fbe 100644 > --- a/configs/ficus-rk3399_defconfig > +++ b/configs/ficus-rk3399_defconfig > @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 > CONFIG_DEBUG_UART=y > CONFIG_FIT=y > CONFIG_SPL_LOAD_FIT=y > -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > CONFIG_SPL_TEXT_BASE=0xff8c2000 > diff --git a/configs/firefly-rk3399_defconfig > b/configs/firefly-rk3399_defconfig > index 301b27e3a4..5016fb8993 100644 > --- a/configs/firefly-rk3399_defconfig > +++ b/configs/firefly-rk3399_defconfig > @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 > CONFIG_DEBUG_UART=y > CONFIG_FIT=y > CONFIG_SPL_LOAD_FIT=y > -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > diff --git a/configs/orangepi-rk3399_defconfig > b/configs/orangepi-rk3399_defconfig > index ba13976cc6..22ddd8dce3 100644 > --- a/configs/orangepi-rk3399_defconfig > +++ b/configs/orangepi-rk3399_defconfig > @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y > CONFIG_NR_DRAM_BANKS=1 > CONFIG_FIT=y > CONFIG_SPL_LOAD_FIT=y > -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > diff --git a/configs/rock960-rk3399_defconfig > b/configs/rock960-rk3399_defconfig > index 8d490be18c..48d14ef7d8 100644 > --- a/configs/rock960-rk3399_defconfig > +++ b/configs/rock960-rk3399_defconfig > @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 > CONFIG_DEBUG_UART=y > CONFIG_FIT=y > CONFIG_SPL_LOAD_FIT=y > -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v7 01/11] rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> To make successful build with dts(i) files syncing from Linux 5.1-rc2
> the rk3399.dtsi would require pwm2_pin_pull_down.
>
> So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this
> node is strictly not part of any commit alone, I have mentioned
> Linux 5.1-rc2 tag for future reference of where would this sync
> coming from.
>
> Signed-off-by: Jagan Teki
> Reviewed-by: Paul Kocialkowski
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
> arch/arm/dts/rk3399.dtsi | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
> index b53e41b4dc..b73442ee34 100644
> --- a/arch/arm/dts/rk3399.dtsi
> +++ b/arch/arm/dts/rk3399.dtsi
> @@ -2495,6 +2495,11 @@
> rockchip,pins =
> <1 RK_PC3 RK_FUNC_1 _pull_none>;
> };
> +
> + pwm2_pin_pull_down: pwm2-pin-pull-down {
> + rockchip,pins =
> + <1 RK_PC3 RK_FUNC_1 _pull_down>;
> + };
> };
>
> pwm3a {
___
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Re: [U-Boot] [PATCH] rockchip: rk3399: orangepi: Add SPL_TEXT_BASE
On 05/08/2019 02:24 AM, Jagan Teki wrote: > CONFIG_SPL_TEXT_BASE was available in configs/rk3399_common.h > when the OrangePI rk3399 board supported during first > version patch. > > But, later below change which move this config into Kconfig and > same has been merged in mainline tree. > "configs: move CONFIG_SPL_TEXT_BASE to Kconfig" > (sha1: f89d6133eef2e068f9c33853b6584d7fcbfa9d2e) > > Unfortunately, the maintainer applied the initial version patch, > instead of looking for next version changes. > > Fix it by adding SPL_TEXT_BASE in orangepi-rk3399 defconfig. > > Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever > --- > configs/orangepi-rk3399_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/orangepi-rk3399_defconfig > b/configs/orangepi-rk3399_defconfig > index cdccf221b5..ba13976cc6 100644 > --- a/configs/orangepi-rk3399_defconfig > +++ b/configs/orangepi-rk3399_defconfig > @@ -17,6 +17,7 @@ > CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_SPL_TEXT_BASE=0xff8c2000 > CONFIG_SPL_STACK_R=y > CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 > CONFIG_SPL_ATF=y ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 4/4] x86: samus: Add a target to boot through TPL
Add a version of samus which supports booting from TPL to SPL and then to U-Boot. This allows TPL to select from an A or B SPL to support verified boot with field upgrade. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: None Changes in v3: None Changes in v2: - Sort defconfig and adjust it to build after rebase on maste board/google/Kconfig | 8 +++ board/google/chromebook_samus/Kconfig | 14 +++- board/google/chromebook_samus/MAINTAINERS | 7 ++ configs/chromebook_samus_tpl_defconfig| 82 +++ include/configs/chromebook_samus.h| 2 + 5 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 configs/chromebook_samus_tpl_defconfig diff --git a/board/google/Kconfig b/board/google/Kconfig index d98a5e818fc..679a0f10239 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -52,6 +52,14 @@ config TARGET_CHROMEBOOK_SAMUS Chrome OS EC connected on LPC, and it provides a 2560x1700 high resolution touch-enabled LCD display. +config TARGET_CHROMEBOOK_SAMUS_TPL + bool "Chromebook samus booting from TPL" + help + This is a version of Samus which boots into TPL, then to SPL and + U-Boot proper. This is useful where verified boot must select + between different A/B versions of SPL/U-Boot, to allow upgrading of + almost all U-Boot code in the field. + endchoice source "board/google/chromebook_link/Kconfig" diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig index afbfe53deb4..90c23cba1be 100644 --- a/board/google/chromebook_samus/Kconfig +++ b/board/google/chromebook_samus/Kconfig @@ -1,4 +1,4 @@ -if TARGET_CHROMEBOOK_SAMUS +if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL config SYS_BOARD default "chromebook_samus" @@ -10,7 +10,8 @@ config SYS_SOC default "broadwell" config SYS_CONFIG_NAME - default "chromebook_samus" + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL config SYS_TEXT_BASE default 0xffe0 @@ -39,3 +40,12 @@ config SYS_CAR_SIZE default 0x4 endif + +if TARGET_CHROMEBOOK_SAMUS_TPL + +config BOARD_SPECIFIC_OPTIONS_TPL # dummy + def_bool y + select SPL + select TPL + +endif diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS index 5500e46b408..ca4b16500af 100644 --- a/board/google/chromebook_samus/MAINTAINERS +++ b/board/google/chromebook_samus/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/google/chromebook_samus/ F: include/configs/chromebook_samus.h F: configs/chromebook_samus_defconfig + +CHROMEBOOK SAMUS TPL BOARD +M: Simon Glass +S: Maintained +F: board/google/chromebook_samus/ +F: include/configs/chromebook_samus.h +F: configs/chromebook_samus_tpl_defconfig diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig new file mode 100644 index 000..6ebfaa83a19 --- /dev/null +++ b/configs/chromebook_samus_tpl_defconfig @@ -0,0 +1,82 @@ +CONFIG_X86=y +CONFIG_SYS_TEXT_BASE=0xffed +CONFIG_SYS_MALLOC_F_LEN=0x1a00 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_VENDOR_GOOGLE=y +CONFIG_TARGET_CHROMEBOOK_SAMUS_TPL=y +CONFIG_DEBUG_UART=y +CONFIG_HAVE_MRC=y +CONFIG_HAVE_REFCODE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_MISC_INIT_R=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_SIZE=0x1000 +CONFIG_BLOBLIST_ADDR=0xff7c +CONFIG_HANDOFF=y +CONFIG_SPL_TEXT_BASE=0xffe7 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_PCI=y +CONFIG_SPL_PCH_SUPPORT=y +CONFIG_TPL_PCI=y +CONFIG_TPL_PCH_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_PART=y +CONFIG_CMD_SATA=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +# CONFIG_SPL_MAC_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus" +# CONFIG_NET is not set +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_TPL_MISC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y +CONFIG_SYS_NS16550=y +CONFIG_SOUND=y +CONFIG_SOUND_I8254=y
Re: [U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL
Hi Bin, On Tue, 7 May 2019 at 21:33, Bin Meng wrote: > > Hi Simon, > > On Tue, May 7, 2019 at 6:07 PM Bin Meng wrote: > > > > Hi Simon, > > > > On Fri, May 3, 2019 at 12:52 AM Simon Glass wrote: > > > > > > At present SPL is used on 64-bit platforms, to allow SPL to be built as > > > a 32-bit program and U-Boot proper to be built as 64-bit. > > > > > > However it is useful to be able to use SPL on any x86 platform, where > > > U-Boot needs to be updated in the field. Then SPL can select which U-Boot > > > to run (A or B) and most of the code can be updated. Similarly, using TPL > > > allows both SPL and U-Boot to be updated. This is the best approach, since > > > it means that all of U-Boot proper as well as SPL (in particular SDRAM > > > init) can be updated in the field. This provides for the smallest possible > > > amount of read-only (non-updateable) code: just the TPL code. > > > > > > This series contains a number of changes to allow x86 boards to use TPL, > > > SPL and U-Boot proper. As a test, it is enabled for samus with a new > > > chromebook_samus_tpl board. > > > > > > Changes in v3: > > > - Rebase to x86/master > > > - Use acpi_s3.h header for constants (and tidy up header order) > > > - Fix multi-line comment format > > > - Remove unneeded pch-reset node > > > - Drop unnecessary change to chromebook_link_defconfig > > > > > > > I applied 14 patches and left 4 below that have open questions: > > http://patchwork.ozlabs.org/project/uboot/list/?series=105795 > > > > In the meantime, it looks that travis-ci complained some failures in > > my last run for the applied patches. I will redo the travis-ci and let > > you know the results. > > Travis-ci reported qemu-x86 is broken. I figured out the issue was due > to the sysreset-x86 driver added platdata_auto_alloc_size that > requires more memory. I will send a patch soon. OK thank you. I have sent v4 now. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 1/4] x86: samus: Update device tree for SPL
Add tags to allow required nodes to be present in SPL / TPL.
Signed-off-by: Simon Glass
---
Changes in v4:
- Update commit message to not mention the sysreset driver.
- Drop change to SPI flash memory-map property
Changes in v3:
- Remove unneeded pch-reset node
Changes in v2: None
arch/x86/dts/chromebook_samus.dts | 31 ---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/arch/x86/dts/chromebook_samus.dts
b/arch/x86/dts/chromebook_samus.dts
index 35211ed81b1..c4207af48a7 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -17,6 +17,7 @@
spi0 =
usb0 = _0;
usb1 = _1;
+ cros-ec0 = _ec;
};
config {
@@ -73,6 +74,7 @@
/* Put this first: it is the default */
gpio_unused: gpio-unused {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
owner = ;
@@ -80,6 +82,7 @@
};
gpio_acpi_sci: acpi-sci {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
invert;
@@ -87,6 +90,7 @@
};
gpio_acpi_smi: acpi-smi {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
invert;
@@ -94,12 +98,14 @@
};
gpio_input: gpio-input {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
owner = ;
};
gpio_input_invert: gpio-input-invert {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
owner = ;
@@ -107,9 +113,11 @@
};
gpio_native: gpio-native {
+ u-boot,dm-pre-reloc;
};
gpio_out_high: gpio-out-high {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
output-value = <1>;
@@ -118,6 +126,7 @@
};
gpio_out_low: gpio-out-low {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
output-value = <0>;
@@ -126,6 +135,7 @@
};
gpio_pirq: gpio-pirq {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
owner = ;
@@ -133,6 +143,7 @@
};
soc_gpio@0 {
+ u-boot,dm-pre-reloc;
config =
<0 _unused 0>, /* unused */
<1 _unused 0>, /* unused */
@@ -250,8 +261,10 @@
spd {
#address-cells = <1>;
#size-cells = <0>;
+ u-boot,dm-pre-reloc;
samsung_4 {
reg = <6>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -291,6 +304,7 @@
* columns 10, density 4096 mb, x32
*/
reg = <8>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -326,6 +340,7 @@
};
samsung_8 {
reg = <10>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -365,6 +380,7 @@
* columns 11, density 4096 mb, x16
*/
reg = <12>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
[U-Boot] [PATCH v4 3/4] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Reviewed-by: Bin Meng Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None include/pci.h | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/pci.h b/include/pci.h index 066238a9c3c..508f7bca81c 100644 --- a/include/pci.h +++ b/include/pci.h @@ -546,11 +546,7 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); -#ifdef CONFIG_NR_DRAM_BANKS -#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7) -#else -#define MAX_PCI_REGIONS 7 -#endif +#define MAX_PCI_REGIONS7 #define INDIRECT_TYPE_NO_PCIE_LINK 1 -- 2.21.0.1020.gf2820cf01a-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 2/4] x86: samus: Update device tree for verified boot
Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/dts/chromebook_samus.dts | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/chromebook_samus.dts
b/arch/x86/dts/chromebook_samus.dts
index c4207af48a7..772ea5c91be 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -9,6 +9,12 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#ifdef CONFIG_CHROMEOS
+#include "chromeos-x86.dtsi"
+#include "flashmap-x86-ro.dtsi"
+#include "flashmap-8mb-rw.dtsi"
+#endif
+
/ {
model = "Google Samus";
compatible = "google,samus", "intel,broadwell";
@@ -581,7 +587,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
- spi-flash@0 {
+ fwstore_spi: spi-flash@0 {
u-boot,dm-pre-reloc;
#size-cells = <1>;
#address-cells = <1>;
@@ -670,6 +676,10 @@
u-boot,dm-pre-reloc;
reg = <0xfed4 0x5000>;
compatible = "infineon,slb9635lpc";
+ secdata {
+ u-boot,dm-pre-reloc;
+ compatible = "google,tpm-secdata";
+ };
};
microcode {
@@ -693,3 +703,13 @@
};
};
+
+ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nvdata {
+ u-boot,dm-pre-reloc;
+ compatible = "google,cmos-nvdata";
+ reg = <0x26>;
+ };
+};
--
2.21.0.1020.gf2820cf01a-goog
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Re: [U-Boot] [PATCH v7 4/4] arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsi【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips....@lists.infradead.org代发】
On 05/08/2019 02:21 AM, Jagan Teki wrote:
> Now we have
> - board specific -u-boot.dtsi files for board specific u-boot
> dts changes.
> - soc specific rk3399-u-boot.dtsi for soc specific u-boot
> dts changes.
>
> So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi
> and drop the properties which are globally available in rk3399-u-boot.dtsi
>
> Right now rk3399-u-boot.dtsi has sdmmc, spi1 u-boot,dm-pre-reloc
> property and more properties and nodes can be move further based
> on the requirements.
>
> This would fix, the -u-boot.dtsi inclusion for evb, firefly, puma
> boards that was accidentally merged on below commit.
> "rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi"
> (sha1: e05b4a4fa84b65a0c8873e8f34721741fe2bc09d)
>
> Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
> arch/arm/dts/rk3399-evb-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-firefly-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 1 +
> arch/arm/dts/rk3399-gru-u-boot.dtsi | 6 ++
> arch/arm/dts/rk3399-gru.dtsi| 1 -
> arch/arm/dts/rk3399-puma-ddr1600.dts| 1 +
> arch/arm/dts/rk3399-puma.dtsi | 2 --
> 7 files changed, 10 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/dts/rk3399-gru-u-boot.dtsi
>
> diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi
> b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> index 7e2c57af22..20910e744b 100644
> --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> @@ -3,4 +3,5 @@
> * Copyright (C) 2019 Jagan Teki
> */
>
> +#include "rk3399-u-boot.dtsi"
> #include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
> diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi
> b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
> index eab86bdb30..67b63a8352 100644
> --- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
> @@ -3,4 +3,5 @@
> * Copyright (C) 2019 Jagan Teki
> */
>
> +#include "rk3399-u-boot.dtsi"
> #include "rk3399-sdram-ddr3-1600.dtsi"
> diff --git a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
> b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
> index 9edb8cf841..726f396f32 100644
> --- a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
> @@ -3,4 +3,5 @@
> * Copyright (C) 2019 Jagan Teki
> */
>
> +#include "rk3399-gru-u-boot.dtsi"
> #include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
> diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi
> b/arch/arm/dts/rk3399-gru-u-boot.dtsi
> new file mode 100644
> index 00..7bddc3acdb
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> +#include "rk3399-u-boot.dtsi"
> diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi
> index 4cdb4320b7..ca0fc391b2 100644
> --- a/arch/arm/dts/rk3399-gru.dtsi
> +++ b/arch/arm/dts/rk3399-gru.dtsi
> @@ -545,7 +545,6 @@ ap_i2c_audio: {
>
> {
> status = "okay";
> - u-boot,dm-pre-reloc;
>
> pinctrl-names = "default", "sleep";
> pinctrl-1 = <_sleep>;
> diff --git a/arch/arm/dts/rk3399-puma-ddr1600.dts
> b/arch/arm/dts/rk3399-puma-ddr1600.dts
> index 337e0eabb4..42763f82d0 100644
> --- a/arch/arm/dts/rk3399-puma-ddr1600.dts
> +++ b/arch/arm/dts/rk3399-puma-ddr1600.dts
> @@ -6,5 +6,6 @@
> /dts-v1/;
>
> #include "rk3399-puma.dtsi"
> +#include "rk3399-u-boot.dtsi"
> #include "rk3399-sdram-ddr3-1600.dtsi"
>
> diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi
> index 319a610022..897e0bda85 100644
> --- a/arch/arm/dts/rk3399-puma.dtsi
> +++ b/arch/arm/dts/rk3399-puma.dtsi
> @@ -647,8 +647,6 @@
>
>
> {
> - u-boot,dm-pre-reloc;
> -
> status = "okay";
>
> #address-cells = <1>;
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[U-Boot] [PATCH v4 0/4] x86: Add support for booting from TPL
At present SPL is used on 64-bit platforms, to allow SPL to be built as a 32-bit program and U-Boot proper to be built as 64-bit. However it is useful to be able to use SPL on any x86 platform, where U-Boot needs to be updated in the field. Then SPL can select which U-Boot to run (A or B) and most of the code can be updated. Similarly, using TPL allows both SPL and U-Boot to be updated. This is the best approach, since it means that all of U-Boot proper as well as SPL (in particular SDRAM init) can be updated in the field. This provides for the smallest possible amount of read-only (non-updateable) code: just the TPL code. This series contains a number of changes to allow x86 boards to use TPL, SPL and U-Boot proper. As a test, it is enabled for samus with a new chromebook_samus_tpl board. Changes in v4: - Update commit message to not mention the sysreset driver. - Drop change to SPI flash memory-map property Changes in v3: - Remove unneeded pch-reset node Changes in v2: - Sort defconfig and adjust it to build after rebase on maste Simon Glass (4): x86: samus: Update device tree for SPL x86: samus: Update device tree for verified boot Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" x86: samus: Add a target to boot through TPL arch/x86/dts/chromebook_samus.dts | 53 +-- board/google/Kconfig | 8 +++ board/google/chromebook_samus/Kconfig | 14 +++- board/google/chromebook_samus/MAINTAINERS | 7 ++ configs/chromebook_samus_tpl_defconfig| 82 +++ include/configs/chromebook_samus.h| 2 + include/pci.h | 6 +- 7 files changed, 161 insertions(+), 11 deletions(-) create mode 100644 configs/chromebook_samus_tpl_defconfig -- 2.21.0.1020.gf2820cf01a-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v7 2/4] arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi files【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips....@lists.infradead.org代发】
On 05/08/2019 02:21 AM, Jagan Teki wrote:
> Devicetree files in RK3399 platform is synced from Linux, like other
> platforms does. Apart from these u-boot in rk3399 would also require
> some u-boot specific node like dmc.
>
> dmc node has big chunk of DDR timing parameters which are specific
> to specific board, and maintained with rk3399-sdram*.dtsi.
>
> So, create board specific -u-boot.dtsi files and move these sdram dtsi
> files accordingly. This would help of maintain u-boot specific changes
> separately without touching Linux dts(i) files which indeed easy for
> syncing from Linux between releases.
>
> These board specific -u-boot.dtsi can be extendible to add more u-boot
> specific nodes or properties in future.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
> arch/arm/dts/rk3399-evb-u-boot.dtsi | 6 ++
> arch/arm/dts/rk3399-evb.dts | 1 -
> arch/arm/dts/rk3399-ficus-u-boot.dtsi | 6 ++
> arch/arm/dts/rk3399-ficus.dts | 1 -
> arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 ++
> arch/arm/dts/rk3399-firefly.dts | 1 -
> arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 6 ++
> arch/arm/dts/rk3399-gru-bob.dts | 1 -
> arch/arm/dts/rk3399-rock960-u-boot.dtsi | 6 ++
> arch/arm/dts/rk3399-rock960.dts | 1 -
> 10 files changed, 30 insertions(+), 5 deletions(-)
> create mode 100644 arch/arm/dts/rk3399-evb-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3399-ficus-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3399-firefly-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3399-rock960-u-boot.dtsi
>
> diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi
> b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> new file mode 100644
> index 00..7e2c57af22
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> +#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
> diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
> index 9162f3dd50..a506e8da37 100644
> --- a/arch/arm/dts/rk3399-evb.dts
> +++ b/arch/arm/dts/rk3399-evb.dts
> @@ -7,7 +7,6 @@
> #include
> #include
> #include "rk3399.dtsi"
> -#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
>
> / {
> model = "Rockchip RK3399 Evaluation Board";
> diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi
> b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
> new file mode 100644
> index 00..eab86bdb30
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> +#include "rk3399-sdram-ddr3-1600.dtsi"
> diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts
> index 4af0e4e383..4b2dd82b67 100644
> --- a/arch/arm/dts/rk3399-ficus.dts
> +++ b/arch/arm/dts/rk3399-ficus.dts
> @@ -8,7 +8,6 @@
>
> /dts-v1/;
> #include "rk3399-rock960.dtsi"
> -#include "rk3399-sdram-ddr3-1600.dtsi"
>
> / {
> model = "96boards RK3399 Ficus";
> diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi
> b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
> new file mode 100644
> index 00..eab86bdb30
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> +#include "rk3399-sdram-ddr3-1600.dtsi"
> diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
> index 46f2ffaf8d..a4cb64f8bd 100644
> --- a/arch/arm/dts/rk3399-firefly.dts
> +++ b/arch/arm/dts/rk3399-firefly.dts
> @@ -7,7 +7,6 @@
> #include
> #include
> #include "rk3399.dtsi"
> -#include "rk3399-sdram-ddr3-1600.dtsi"
>
> / {
> model = "Firefly-RK3399 Board";
> diff --git a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
> b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
> new file mode 100644
> index 00..9edb8cf841
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
> diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts
> index 0e3d91fc28..1ee0dc0d9f 100644
> --- a/arch/arm/dts/rk3399-gru-bob.dts
> +++ b/arch/arm/dts/rk3399-gru-bob.dts
> @@ -7,7 +7,6 @@
>
> /dts-v1/;
> #include "rk3399-gru-chromebook.dtsi"
> -#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
>
> / {
> model = "Google Bob";
> diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi
> b/arch/arm/dts/rk3399-rock960-u-boot.dtsi
> new file mode 100644
> index 00..5256f6d3f2
> --- /dev/null
> +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Jagan Teki
> + */
> +
> +#include
Re: [U-Boot] [PATCH v7 3/4] rockchip: dts: rk3399-u-boot: Add u-boot, dm-pre-reloc for spi1【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips....@lists.infradead.org代发】
On 05/08/2019 02:21 AM, Jagan Teki wrote:
> Add u-boot,dm-pre-reloc property for spi1, so-that the
> subsequent rk3399 boards which boot from SPI.
>
> This help to separate the u-boot specific properties away
> from base dts files so-that the Linux sync become easy and
> meaningful.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
> arch/arm/dts/rk3399-u-boot.dtsi | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
> index f533ed95eb..0786c1193a 100644
> --- a/arch/arm/dts/rk3399-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-u-boot.dtsi
> @@ -6,3 +6,7 @@
> {
> u-boot,dm-pre-reloc;
> };
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
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Re: [U-Boot] [PATCH v7 1/4] dts: Makefile: Build rockchip dtbs based on SoC types
On 05/08/2019 02:21 AM, Jagan Teki wrote: > - Sometimes u-boot specific dtsi files are included > automatically which would build for entire rockchip SoC, > even-though the respective dtsi should used it for specific > family of rockchip SoC. > - Sometimes u-boot specific dts nodes or properties can use > config macros from respective rockchip family include/configs > files, example CONFIG_SPL_PAD_TO. > > So, it's better to compile the dtbs based on the respective > rockchip family types rather than rockchip itself to avoid > compilation issues. > > This patch organize the existing dtb's based on the rockchip > family types. > > Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever > --- > arch/arm/dts/Makefile | 35 ++- > 1 file changed, 26 insertions(+), 9 deletions(-) > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 8e082f2840..35cbbfabd0 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -65,16 +65,23 @@ dtb-$(CONFIG_KIRKWOOD) += \ > dtb-$(CONFIG_ARCH_OWL) += \ > bubblegum_96.dtb > > -dtb-$(CONFIG_ARCH_ROCKCHIP) += \ > - rk3036-sdk.dtb \ > - rk3128-evb.dtb \ > - rk3188-radxarock.dtb \ > - rk3229-evb.dtb \ > +dtb-$(CONFIG_ROCKCHIP_RK3036) += \ > + rk3036-sdk.dtb > + > +dtb-$(CONFIG_ROCKCHIP_RK3128) += \ > + rk3128-evb.dtb > + > +dtb-$(CONFIG_ROCKCHIP_RK3188) += \ > + rk3188-radxarock.dtb > + > +dtb-$(CONFIG_ROCKCHIP_RK322X) += \ > + rk3229-evb.dtb > + > +dtb-$(CONFIG_ROCKCHIP_RK3288) += \ > rk3288-evb.dtb \ > rk3288-fennec.dtb \ > rk3288-firefly.dtb \ > rk3288-miqi.dtb \ > - rk3399-orangepi.dtb \ > rk3288-phycore-rdk.dtb \ > rk3288-popmetal.dtb \ > rk3288-rock2-square.dtb \ > @@ -83,22 +90,32 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ > rk3288-veyron-mickey.dtb \ > rk3288-veyron-minnie.dtb \ > rk3288-veyron-speedy.dtb \ > - rk3288-vyasa.dtb \ > - rk3328-evb.dtb \ > - rk3399-ficus.dtb \ > + rk3288-vyasa.dtb > + > +dtb-$(CONFIG_ROCKCHIP_RK3328) += \ > + rk3328-evb.dtb > + > +dtb-$(CONFIG_ROCKCHIP_RK3368) += \ > rk3368-lion.dtb \ > rk3368-sheep.dtb \ > rk3368-geekbox.dtb \ > rk3368-px5-evb.dtb \ > + > +dtb-$(CONFIG_ROCKCHIP_RK3399) += \ > rk3399-evb.dtb \ > + rk3399-ficus.dtb \ > rk3399-firefly.dtb \ > rk3399-gru-bob.dtb \ > + rk3399-orangepi.dtb \ > rk3399-puma-ddr1333.dtb \ > rk3399-puma-ddr1600.dtb \ > rk3399-puma-ddr1866.dtb \ > rk3399-rock960.dtb \ > + > +dtb-$(CONFIG_ROCKCHIP_RV1108) += \ > rv1108-elgin-r1.dtb \ > rv1108-evb.dtb > + > dtb-$(CONFIG_ARCH_MESON) += \ > meson-gxbb-nanopi-k2.dtb \ > meson-gxbb-odroidc2.dtb \ ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL
Hi Simon, On Tue, May 7, 2019 at 6:07 PM Bin Meng wrote: > > Hi Simon, > > On Fri, May 3, 2019 at 12:52 AM Simon Glass wrote: > > > > At present SPL is used on 64-bit platforms, to allow SPL to be built as > > a 32-bit program and U-Boot proper to be built as 64-bit. > > > > However it is useful to be able to use SPL on any x86 platform, where > > U-Boot needs to be updated in the field. Then SPL can select which U-Boot > > to run (A or B) and most of the code can be updated. Similarly, using TPL > > allows both SPL and U-Boot to be updated. This is the best approach, since > > it means that all of U-Boot proper as well as SPL (in particular SDRAM > > init) can be updated in the field. This provides for the smallest possible > > amount of read-only (non-updateable) code: just the TPL code. > > > > This series contains a number of changes to allow x86 boards to use TPL, > > SPL and U-Boot proper. As a test, it is enabled for samus with a new > > chromebook_samus_tpl board. > > > > Changes in v3: > > - Rebase to x86/master > > - Use acpi_s3.h header for constants (and tidy up header order) > > - Fix multi-line comment format > > - Remove unneeded pch-reset node > > - Drop unnecessary change to chromebook_link_defconfig > > > > I applied 14 patches and left 4 below that have open questions: > http://patchwork.ozlabs.org/project/uboot/list/?series=105795 > > In the meantime, it looks that travis-ci complained some failures in > my last run for the applied patches. I will redo the travis-ci and let > you know the results. Travis-ci reported qemu-x86 is broken. I figured out the issue was due to the sysreset-x86 driver added platdata_auto_alloc_size that requires more memory. I will send a patch soon. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 45/50] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
Hi Simon, On Wed, May 8, 2019 at 11:04 AM Simon Glass wrote: > > Hi Bin, > > On Tue, 7 May 2019 at 03:28, Bin Meng wrote: > > > > Hi Simon, Thierry, > > > > On Fri, May 3, 2019 at 12:22 AM Simon Glass wrote: > > > > > > Hi Thierry, > > > > > > On Thu, 2 May 2019 at 03:25, Thierry Reding wrote: > > > > > > > > On Thu, May 02, 2019 at 12:09:49AM +0800, Bin Meng wrote: > > > > > +Thierry > > > > > > > > > > On Fri, Apr 26, 2019 at 12:00 PM Simon Glass > > > > > wrote: > > > > > > > > > > > > This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. > > > > > > > > > > > > Unfortunately this has a dramatic impact on the pre-relocation > > > > > > memory > > > > > > used on x86 platforms (increasing it by 2KB) since it increases the > > > > > > overhead for each PCI device from 220 bytes to 412 bytes. > > > > > > > > > > > > The offending line is in UCLASS_DRIVER(pci): > > > > > > > > > > > > .per_device_auto_alloc_size = sizeof(struct pci_controller), > > > > > > > > > > > > This means that all PCI devices have the controller struct > > > > > > associated > > > > > > with them. The solution is to move the regions[] member out of the > > > > > > array, > > > > > > makes its size dynamic, or split UCLASS_PCI into controllers and > > > > > > non-controllers, as the comment suggests. > > > > > > > > > > > > For now, revert the commit to get things running again. > > > > > > > > > > > > Signed-off-by: Simon Glass > > > > > > --- > > > > > > > > > > > > Changes in v2: None > > > > > > > > > > > > include/pci.h | 6 +- > > > > > > 1 file changed, 1 insertion(+), 5 deletions(-) > > > > > > > > > > > > > > > > Reviewed-by: Bin Meng > > > > > > > > Ugh... so we're trading one regression for another? Can we not live with > > > > the 2 KiB increase on x86 until this has been properly fixed? Currently > > > > this will cause Jetson TX2 to crash if it starts using PCI. > > > > > > Unfortunately this breaks several boards since we are out of memory. > > > > > > I think this needs a better solution to reduce the memory usage down > > > to sensible levels. This is something I should have considered when > > > implementing the PCI uclass, but unfortunately I did not. > > > > > > > Could you please suggest whether I should apply this revert patch for now? > > I suggest a temporary revert since this breaks some x86 boards. > > I think the real fix is to reduce the memory used by PCI devices. > Thierry, do you have time to look at this? OK, I will apply this patch then. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] configs: stratix10: Enable CONFIG_SPI_FLASH_USE_4K_SECTORS
Fix SPI flash environment erase size error. CONFIG_ENV_SECT_SIZE is set to 4KB. Enable CONFIG_SPI_FLASH_USE_4K_SECTORS to allow erase one environment sector. Fix error below: SOCFPGA_STRATIX10 # saveenv Saving Environment to SPI Flash... SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB Erasing SPI flash...SF: Erase offset/length not multiple of erase size Failed (-22) Signed-off-by: Ley Foon Tan --- configs/socfpga_stratix10_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 73a1231d46..4be85d53ab 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -41,7 +41,6 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y -- 2.19.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 45/50] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
Hi Bin, On Tue, 7 May 2019 at 03:28, Bin Meng wrote: > > Hi Simon, Thierry, > > On Fri, May 3, 2019 at 12:22 AM Simon Glass wrote: > > > > Hi Thierry, > > > > On Thu, 2 May 2019 at 03:25, Thierry Reding wrote: > > > > > > On Thu, May 02, 2019 at 12:09:49AM +0800, Bin Meng wrote: > > > > +Thierry > > > > > > > > On Fri, Apr 26, 2019 at 12:00 PM Simon Glass wrote: > > > > > > > > > > This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. > > > > > > > > > > Unfortunately this has a dramatic impact on the pre-relocation memory > > > > > used on x86 platforms (increasing it by 2KB) since it increases the > > > > > overhead for each PCI device from 220 bytes to 412 bytes. > > > > > > > > > > The offending line is in UCLASS_DRIVER(pci): > > > > > > > > > > .per_device_auto_alloc_size = sizeof(struct pci_controller), > > > > > > > > > > This means that all PCI devices have the controller struct associated > > > > > with them. The solution is to move the regions[] member out of the > > > > > array, > > > > > makes its size dynamic, or split UCLASS_PCI into controllers and > > > > > non-controllers, as the comment suggests. > > > > > > > > > > For now, revert the commit to get things running again. > > > > > > > > > > Signed-off-by: Simon Glass > > > > > --- > > > > > > > > > > Changes in v2: None > > > > > > > > > > include/pci.h | 6 +- > > > > > 1 file changed, 1 insertion(+), 5 deletions(-) > > > > > > > > > > > > > Reviewed-by: Bin Meng > > > > > > Ugh... so we're trading one regression for another? Can we not live with > > > the 2 KiB increase on x86 until this has been properly fixed? Currently > > > this will cause Jetson TX2 to crash if it starts using PCI. > > > > Unfortunately this breaks several boards since we are out of memory. > > > > I think this needs a better solution to reduce the memory usage down > > to sensible levels. This is something I should have considered when > > implementing the PCI uclass, but unfortunately I did not. > > > > Could you please suggest whether I should apply this revert patch for now? I suggest a temporary revert since this breaks some x86 boards. I think the real fix is to reduce the memory used by PCI devices. Thierry, do you have time to look at this? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: socfpga: stratix10: Fix SPI flash ENV_SECT_SIZE
On 5/8/19 4:42 AM, Ley Foon Tan wrote: > On Tue, May 7, 2019 at 9:04 PM Marek Vasut wrote: >> >> On 5/7/19 8:01 AM, Ley Foon Tan wrote: >>> Fix SPI flash environment erase size error. >>> >>> Erase size of flash mt25qu02g on Stratix 10 should be 64KB. >>> >>> SOCFPGA_STRATIX10 # saveenv >>> Saving Environment to SPI Flash... >>> SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total >>> 256 MiB >>> Erasing SPI flash...SF: Erase offset/length not multiple of erase size >>> Failed (-22) >>> >>> Signed-off-by: Ley Foon Tan >>> --- >>> include/configs/socfpga_stratix10_socdk.h | 4 ++-- >>> 1 file changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/include/configs/socfpga_stratix10_socdk.h >>> b/include/configs/socfpga_stratix10_socdk.h >>> index 12e77c0a90..16cd918cd3 100644 >>> --- a/include/configs/socfpga_stratix10_socdk.h >>> +++ b/include/configs/socfpga_stratix10_socdk.h >>> @@ -66,8 +66,8 @@ >>> #undef CONFIG_ENV_OFFSET >>> #undef CONFIG_ENV_SIZE >>> #define CONFIG_ENV_OFFSET0x71 >>> -#define CONFIG_ENV_SIZE (4 * 1024) >>> -#define CONFIG_ENV_SECT_SIZE (4 * 1024) >>> +#define CONFIG_ENV_SIZE (64 * 1024) >>> +#define CONFIG_ENV_SECT_SIZE (64 * 1024) >>> #endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ >>> >>> #ifndef CONFIG_SPL_BUILD >>> >> Can CONFIG_SPI_FLASH_USE_4K_SECTORS help instead ? > You are right, CONFIG_SPI_FLASH_USE_4K_SECTORS can fix this error too. > Will drop this patch and send another patch to enable > CONFIG_SPI_FLASH_USE_4K_SECTORS. :) -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: socfpga: stratix10: Fix SPI flash ENV_SECT_SIZE
On Tue, May 7, 2019 at 9:04 PM Marek Vasut wrote: > > On 5/7/19 8:01 AM, Ley Foon Tan wrote: > > Fix SPI flash environment erase size error. > > > > Erase size of flash mt25qu02g on Stratix 10 should be 64KB. > > > > SOCFPGA_STRATIX10 # saveenv > > Saving Environment to SPI Flash... > > SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total > > 256 MiB > > Erasing SPI flash...SF: Erase offset/length not multiple of erase size > > Failed (-22) > > > > Signed-off-by: Ley Foon Tan > > --- > > include/configs/socfpga_stratix10_socdk.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/include/configs/socfpga_stratix10_socdk.h > > b/include/configs/socfpga_stratix10_socdk.h > > index 12e77c0a90..16cd918cd3 100644 > > --- a/include/configs/socfpga_stratix10_socdk.h > > +++ b/include/configs/socfpga_stratix10_socdk.h > > @@ -66,8 +66,8 @@ > > #undef CONFIG_ENV_OFFSET > > #undef CONFIG_ENV_SIZE > > #define CONFIG_ENV_OFFSET0x71 > > -#define CONFIG_ENV_SIZE (4 * 1024) > > -#define CONFIG_ENV_SECT_SIZE (4 * 1024) > > +#define CONFIG_ENV_SIZE (64 * 1024) > > +#define CONFIG_ENV_SECT_SIZE (64 * 1024) > > #endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ > > > > #ifndef CONFIG_SPL_BUILD > > > Can CONFIG_SPI_FLASH_USE_4K_SECTORS help instead ? You are right, CONFIG_SPI_FLASH_USE_4K_SECTORS can fix this error too. Will drop this patch and send another patch to enable CONFIG_SPI_FLASH_USE_4K_SECTORS. Thanks. Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] imx: mkimage_fit_atf: Fix DTC warnings
Hi Fabio,
> Subject: [PATCH] imx: mkimage_fit_atf: Fix DTC warnings
>
> When generating the flash.bin binary the following DTC warnings are seen:
>
> u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1 has
> a unit name, but no reg property
> u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@1 has a
> unit name, but no reg property
> u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1 has a
> unit name, but no reg property
> u-boot.itb.tmp: Warning (unit_address_vs_reg): Node
> /configurations/config@1 has a unit name, but no reg property
>
>
> Fix them by removing the meaningless @1 entries.
>
> Signed-off-by: Fabio Estevam
> ---
> arch/arm/mach-imx/mkimage_fit_atf.sh | 26 +-
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh
> b/arch/arm/mach-imx/mkimage_fit_atf.sh
> index 38c9858e84..fc9342543a 100755
> --- a/arch/arm/mach-imx/mkimage_fit_atf.sh
> +++ b/arch/arm/mach-imx/mkimage_fit_atf.sh
> @@ -53,7 +53,7 @@ cat << __HEADER_EOF
> description = "Configuration to load ATF before U-Boot";
>
> images {
> - uboot@1 {
> + uboot {
> description = "U-Boot (64-bit)";
> data = /incbin/("$BL33");
> type = "standalone";
> @@ -61,7 +61,7 @@ cat << __HEADER_EOF
> compression = "none";
> load = <$BL33_LOAD_ADDR>;
> };
> - atf@1 {
> + atf {
> description = "ARM Trusted Firmware";
> data = /incbin/("$BL31");
> type = "firmware";
> @@ -74,7 +74,7 @@ __HEADER_EOF
>
> if [ -f $BL32 ]; then
> cat << __HEADER_EOF
> - tee@1 {
> + tee {
> description = "TEE firmware";
> data = /incbin/("$BL32");
> type = "firmware";
> @@ -90,7 +90,7 @@ cnt=1
> for dtname in $*
> do
> cat << __FDT_IMAGE_EOF
> - fdt@$cnt {
> + fdt {
This is not correct. The file is expected to add more than one fdt files.
Regards,
Peng.
> description = "$(basename $dtname .dtb)";
> data = /incbin/("$dtname");
> type = "flat_dt";
> @@ -103,7 +103,7 @@ done
> cat << __CONF_HEADER_EOF
> };
> configurations {
> - default = "config@1";
> + default = "config";
>
> __CONF_HEADER_EOF
>
> @@ -112,20 +112,20 @@ for dtname in $*
> do
> if [ -f $BL32 ]; then
> cat << __CONF_SECTION_EOF
> - config@$cnt {
> + config {
> description = "$(basename $dtname .dtb)";
> - firmware = "uboot@1";
> - loadables = "atf@1", "tee@1";
> - fdt = "fdt@$cnt";
> + firmware = "uboot";
> + loadables = "atf", "tee";
> + fdt = "fdt";
> };
> __CONF_SECTION_EOF
> else
> cat << __CONF_SECTION1_EOF
> - config@$cnt {
> + config {
> description = "$(basename $dtname .dtb)";
> - firmware = "uboot@1";
> - loadables = "atf@1";
> - fdt = "fdt@$cnt";
> + firmware = "uboot";
> + loadables = "atf";
> + fdt = "fdt";
> };
> __CONF_SECTION1_EOF
> fi
> --
> 2.17.1
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Re: [U-Boot] [PATCH] Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue"
Hi Lukasz,
> Subject: [PATCH] Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting
> issue"
>
> This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6, which
> causes the imx53 HSC to hang as the eMMC is not working properly anymore.
>
> The exact error message:
> MMC write: dev # 0, block # 2, count 927 ... mmc write failed
> 0 blocks written: ERROR
>
> imx53 is not using the DDR mode.
>
> Debugging of pre_div and div generation showed that those values are
> generated in a way, which is not matching the ones from working setup.
>
> As the original patch was performing code refactoring, let's revert this
> change,
> so all imx53 boards would work again.
Could you share what is the clock value for your board?
Thanks,
Peng.
>
> Signed-off-by: Lukasz Majewski
> ---
> drivers/mmc/fsl_esdhc.c | 23 +--
> 1 file changed, 5 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> 1b7de74a72..377b2673a3 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -621,31 +621,18 @@ static void set_sysctl(struct fsl_esdhc_priv *priv,
> struct mmc *mmc, uint clock) #else
> int pre_div = 2;
> #endif
> + int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
> int sdhc_clk = priv->sdhc_clk;
> uint clk;
>
> - /*
> - * For ddr mode, usdhc need to enable DDR mode first, after select
> - * this DDR mode, usdhc will automatically divide the usdhc clock
> - */
> - if (mmc->ddr_mode) {
> - writel(readl(>mixctrl) | MIX_CTRL_DDREN, >mixctrl);
> - sdhc_clk >>= 1;
> - }
> -
> if (clock < mmc->cfg->f_min)
> clock = mmc->cfg->f_min;
>
> - if (sdhc_clk / 16 > clock) {
> - for (; pre_div < 256; pre_div *= 2)
> - if ((sdhc_clk / pre_div) <= (clock * 16))
> - break;
> - } else
> - pre_div = 1;
> + while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
> + pre_div *= 2;
>
> - for (div = 1; div <= 16; div++)
> - if ((sdhc_clk / (div * pre_div)) <= clock)
> - break;
> + while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
> + div++;
>
> pre_div >>= 1;
> div -= 1;
> --
> 2.11.0
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Re: [U-Boot] [PATCH v2 1/1] efi_loader: unload applications upon Exit()
On Wed, May 08, 2019 at 02:59:08AM +0200, Heinrich Schuchardt wrote:
> On 5/8/19 1:59 AM, Takahiro Akashi wrote:
> >On Tue, May 07, 2019 at 09:13:24PM +0200, Heinrich Schuchardt wrote:
> >>Implement unloading of images in the Exit() boot services:
> >>
> >>* unload images that are not yet started,
> >>* unload started applications,
> >>* unload drivers returning an error.
> >>
> >>Signed-off-by: Heinrich Schuchardt
> >>---
> >>v2
> >>Images that are no yet started can be unloaded by calling Exit().
> >>In this case they are not the current image. Move the test for
> >>current down in the code.
> >>
> >>A started driver that called Exit() should still be considered a
> >>started image. Exit cannot be called by another image afterwards,
> >>cf. UEFI SCT 2.6 (2017), 3.5.1 Exit(), 5.1.4.5.8 - 5.1.4.5.10.
> >>---
> >> include/efi_loader.h | 1 +
> >> lib/efi_loader/efi_boottime.c | 36 +--
> >> lib/efi_loader/efi_image_loader.c | 2 ++
> >> 3 files changed, 33 insertions(+), 6 deletions(-)
> >>
> >>diff --git a/include/efi_loader.h b/include/efi_loader.h
> >>index 3b50cd28ef..4e4cffa799 100644
> >>--- a/include/efi_loader.h
> >>+++ b/include/efi_loader.h
> >>@@ -234,6 +234,7 @@ struct efi_loaded_image_obj {
> >>struct jmp_buf_data exit_jmp;
> >>EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
> >> struct efi_system_table *st);
> >>+ u16 image_type;
> >> };
> >>
> >> /**
> >>diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
> >>index 0385883ded..1ea96dab6c 100644
> >>--- a/lib/efi_loader/efi_boottime.c
> >>+++ b/lib/efi_loader/efi_boottime.c
> >>@@ -13,6 +13,7 @@
> >> #include
> >> #include
> >> #include
> >>+#include
> >> #include
> >>
> >> DECLARE_GLOBAL_DATA_PTR;
> >>@@ -2798,7 +2799,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
> >>image_handle,
> >> * image protocol.
> >> */
> >>efi_status_t ret;
> >>- void *info;
> >>+ struct efi_loaded_image *loaded_image_protocol;
> >>struct efi_loaded_image_obj *image_obj =
> >>(struct efi_loaded_image_obj *)image_handle;
> >>
> >>@@ -2806,13 +2807,33 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
> >>image_handle,
> >> exit_data_size, exit_data);
> >>
> >>/* Check parameters */
> >>- if (image_handle != current_image)
> >>- goto out;
> >>ret = EFI_CALL(efi_open_protocol(image_handle, _guid_loaded_image,
> >>-, NULL, NULL,
> >>+(void **)_image_protocol,
> >>+NULL, NULL,
> >> EFI_OPEN_PROTOCOL_GET_PROTOCOL));
> >>- if (ret != EFI_SUCCESS)
> >>+ if (ret != EFI_SUCCESS) {
> >>+ ret = EFI_INVALID_PARAMETER;
> >>goto out;
> >>+ }
> >>+
> >>+ /* Unloading of unstarted images */
> >>+ switch (image_obj->header.type) {
> >>+ case EFI_OBJECT_TYPE_STARTED_IMAGE:
> >>+ break;
> >>+ case EFI_OBJECT_TYPE_LOADED_IMAGE:
> >>+ efi_delete_image(image_obj, loaded_image_protocol);
> >>+ ret = EFI_SUCCESS;
> >>+ goto out;
> >>+ default:
> >>+ /* Handle does not refer to loaded image */
> >>+ ret = EFI_INVALID_PARAMETER;
> >>+ goto out;
> >>+ }
> >>+ /* A started image can only be unloaded it is the last one started. */
> >>+ if (image_handle != current_image) {
> >>+ ret = EFI_INVALID_PARAMETER;
> >>+ goto out;
> >>+ }
> >>
> >>/* Exit data is only foreseen in case of failure. */
> >>if (exit_status != EFI_SUCCESS) {
> >>@@ -2822,6 +2843,9 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
> >>image_handle,
> >>if (ret != EFI_SUCCESS)
> >>EFI_PRINT("%s: out of memory\n", __func__);
> >>}
> >>+ if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION ||
> >>+ exit_status != EFI_SUCCESS)
> >>+ efi_delete_image(image_obj, loaded_image_protocol);
> >
> >No change around efi_delete_image() and "goto" above?
> >
>
> Do you see a bug?
>
> A diff would help me to understand what you would like to change.
You said:
>> For me, your code is much unreadable.
>> Moreover, I remember that you have said, in a review of my patch, that
>> we should use "goto" only in error cases.
>
>Good point. So the check must be after handling
>EFI_OBJECT_TYPE_LOADED_IMAGE.
>
>I will revise the patch.
-Takahiro Akashi
> Best regards
>
> Heinrich
>
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Re: [U-Boot] [PATCH v2 1/1] efi_loader: unload applications upon Exit()
On 5/8/19 1:59 AM, Takahiro Akashi wrote:
On Tue, May 07, 2019 at 09:13:24PM +0200, Heinrich Schuchardt wrote:
Implement unloading of images in the Exit() boot services:
* unload images that are not yet started,
* unload started applications,
* unload drivers returning an error.
Signed-off-by: Heinrich Schuchardt
---
v2
Images that are no yet started can be unloaded by calling Exit().
In this case they are not the current image. Move the test for
current down in the code.
A started driver that called Exit() should still be considered a
started image. Exit cannot be called by another image afterwards,
cf. UEFI SCT 2.6 (2017), 3.5.1 Exit(), 5.1.4.5.8 - 5.1.4.5.10.
---
include/efi_loader.h | 1 +
lib/efi_loader/efi_boottime.c | 36 +--
lib/efi_loader/efi_image_loader.c | 2 ++
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 3b50cd28ef..4e4cffa799 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -234,6 +234,7 @@ struct efi_loaded_image_obj {
struct jmp_buf_data exit_jmp;
EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
struct efi_system_table *st);
+ u16 image_type;
};
/**
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 0385883ded..1ea96dab6c 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -2798,7 +2799,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
* image protocol.
*/
efi_status_t ret;
- void *info;
+ struct efi_loaded_image *loaded_image_protocol;
struct efi_loaded_image_obj *image_obj =
(struct efi_loaded_image_obj *)image_handle;
@@ -2806,13 +2807,33 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
exit_data_size, exit_data);
/* Check parameters */
- if (image_handle != current_image)
- goto out;
ret = EFI_CALL(efi_open_protocol(image_handle, _guid_loaded_image,
-, NULL, NULL,
+(void **)_image_protocol,
+NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL));
- if (ret != EFI_SUCCESS)
+ if (ret != EFI_SUCCESS) {
+ ret = EFI_INVALID_PARAMETER;
goto out;
+ }
+
+ /* Unloading of unstarted images */
+ switch (image_obj->header.type) {
+ case EFI_OBJECT_TYPE_STARTED_IMAGE:
+ break;
+ case EFI_OBJECT_TYPE_LOADED_IMAGE:
+ efi_delete_image(image_obj, loaded_image_protocol);
+ ret = EFI_SUCCESS;
+ goto out;
+ default:
+ /* Handle does not refer to loaded image */
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ /* A started image can only be unloaded it is the last one started. */
+ if (image_handle != current_image) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
/* Exit data is only foreseen in case of failure. */
if (exit_status != EFI_SUCCESS) {
@@ -2822,6 +2843,9 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
if (ret != EFI_SUCCESS)
EFI_PRINT("%s: out of memory\n", __func__);
}
+ if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION ||
+ exit_status != EFI_SUCCESS)
+ efi_delete_image(image_obj, loaded_image_protocol);
No change around efi_delete_image() and "goto" above?
Do you see a bug?
A diff would help me to understand what you would like to change.
Best regards
Heinrich
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Re: [U-Boot] [PATCH v2 1/1] efi_loader: optional data in load options are binary
On 5/8/19 1:56 AM, Takahiro Akashi wrote: On Tue, May 07, 2019 at 06:54:45PM +0200, Heinrich Schuchardt wrote: On 5/7/19 9:30 AM, Takahiro Akashi wrote: On Tue, May 07, 2019 at 09:12:56AM +0200, Heinrich Schuchardt wrote: On 5/7/19 8:16 AM, Takahiro Akashi wrote: On Tue, May 07, 2019 at 08:04:26AM +0200, Heinrich Schuchardt wrote: On 5/7/19 7:16 AM, Heinrich Schuchardt wrote: On 5/7/19 3:53 AM, Takahiro Akashi wrote: On Tue, Apr 30, 2019 at 08:11:15AM +0200, Heinrich Schuchardt wrote: The field boot OptionalData in structure _EFI_LOAD_OPTIONS is for binary data. When we use `efidebug boot add` we should convert the 5th argument from UTF-8 to UTF-16 before putting it into the Boot variable. While optional_data holds u8 string in calling efi_serialize_load_option(), it holds u16 string in leaving from efi_deserialize_load_option(). We should handle it in a consistent way if you want to keep optional_data as "const u8." When communicating with Linux optional data may contain a u16 string. But I cannot see were our coding is inconsistent. I don't get your point. Do you want to allow 'u8 *' variable to hold u16 string?# Yes, optional data may contain anything, in the case of Linux the command line parameters as an u16 string. Other operating systems may use the field in other ways, e.g. store an ASCII string. The problem is that with your patch optional_data is *always* converted to utf-16 as far as we use efidebug. My efidebug is not for linux only. optional_data treated is not treated as u16 in efidebug: With your patch, efi_serialize_load_option() always convert a given argument to utf-16 and then the resulting variable contains u16 string as optional_data. On the other hand, efi_deserialize_load_option() does *not* convert an encoded optional_data in a variable to utf-8. When we use efi_serialize_load_option() we know that it is either an UTF-8 string in the bootargs variable or UTF-8 command line parameter for the `efi boot add` command. Currently we do not foresee adding binary data. So we can simply convert the UTF-8 input to UTF-16 as will be needed when passing the boot option to the operating system. (A patch for the boot manager still to be delivered.) But this is not the only way that Boot variables can be set: * An EFI application may be used to set an arbitrary binary string. * In future an operating system could put some binary data into the load option. So it is not safe to convert the load option into UTF-8 for display. That is why I chose to use print_hex_dump() for output. If your boot option only contains ASCII letters it is still legible: => efi boot add f000 lable scsi 0:1 binary.efi 'my favorite option' => efi boot dump BootF000: attributes: A-- (0x0001) label: lable file_path: /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/Scsi(0,0)/HD(1,MBR,0x90381b6c,0x800,0x3fffe)/binary.efi data: : 6d 00 79 00 20 00 66 00 61 00 76 00 6f 00 72 00 m.y. .f.a.v.o.r. 0010: 69 00 74 00 65 00 20 00 6f 00 70 00 74 00 69 00 i.t.e. .o.p.t.i. 0020: 6f 00 6e 00 00 00o.n... Best regards Heinrich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/1] efi_loader: unload applications upon Exit()
On Tue, May 07, 2019 at 09:13:24PM +0200, Heinrich Schuchardt wrote:
> Implement unloading of images in the Exit() boot services:
>
> * unload images that are not yet started,
> * unload started applications,
> * unload drivers returning an error.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2
> Images that are no yet started can be unloaded by calling Exit().
> In this case they are not the current image. Move the test for
> current down in the code.
>
> A started driver that called Exit() should still be considered a
> started image. Exit cannot be called by another image afterwards,
> cf. UEFI SCT 2.6 (2017), 3.5.1 Exit(), 5.1.4.5.8 - 5.1.4.5.10.
> ---
> include/efi_loader.h | 1 +
> lib/efi_loader/efi_boottime.c | 36 +--
> lib/efi_loader/efi_image_loader.c | 2 ++
> 3 files changed, 33 insertions(+), 6 deletions(-)
>
> diff --git a/include/efi_loader.h b/include/efi_loader.h
> index 3b50cd28ef..4e4cffa799 100644
> --- a/include/efi_loader.h
> +++ b/include/efi_loader.h
> @@ -234,6 +234,7 @@ struct efi_loaded_image_obj {
> struct jmp_buf_data exit_jmp;
> EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
>struct efi_system_table *st);
> + u16 image_type;
> };
>
> /**
> diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
> index 0385883ded..1ea96dab6c 100644
> --- a/lib/efi_loader/efi_boottime.c
> +++ b/lib/efi_loader/efi_boottime.c
> @@ -13,6 +13,7 @@
> #include
> #include
> #include
> +#include
> #include
>
> DECLARE_GLOBAL_DATA_PTR;
> @@ -2798,7 +2799,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
> image_handle,
>* image protocol.
>*/
> efi_status_t ret;
> - void *info;
> + struct efi_loaded_image *loaded_image_protocol;
> struct efi_loaded_image_obj *image_obj =
> (struct efi_loaded_image_obj *)image_handle;
>
> @@ -2806,13 +2807,33 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
> image_handle,
> exit_data_size, exit_data);
>
> /* Check parameters */
> - if (image_handle != current_image)
> - goto out;
> ret = EFI_CALL(efi_open_protocol(image_handle, _guid_loaded_image,
> - , NULL, NULL,
> + (void **)_image_protocol,
> + NULL, NULL,
>EFI_OPEN_PROTOCOL_GET_PROTOCOL));
> - if (ret != EFI_SUCCESS)
> + if (ret != EFI_SUCCESS) {
> + ret = EFI_INVALID_PARAMETER;
> goto out;
> + }
> +
> + /* Unloading of unstarted images */
> + switch (image_obj->header.type) {
> + case EFI_OBJECT_TYPE_STARTED_IMAGE:
> + break;
> + case EFI_OBJECT_TYPE_LOADED_IMAGE:
> + efi_delete_image(image_obj, loaded_image_protocol);
> + ret = EFI_SUCCESS;
> + goto out;
> + default:
> + /* Handle does not refer to loaded image */
> + ret = EFI_INVALID_PARAMETER;
> + goto out;
> + }
> + /* A started image can only be unloaded it is the last one started. */
> + if (image_handle != current_image) {
> + ret = EFI_INVALID_PARAMETER;
> + goto out;
> + }
>
> /* Exit data is only foreseen in case of failure. */
> if (exit_status != EFI_SUCCESS) {
> @@ -2822,6 +2843,9 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
> image_handle,
> if (ret != EFI_SUCCESS)
> EFI_PRINT("%s: out of memory\n", __func__);
> }
> + if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION ||
> + exit_status != EFI_SUCCESS)
> + efi_delete_image(image_obj, loaded_image_protocol);
No change around efi_delete_image() and "goto" above?
-Takahiro Akashi
> /* Make sure entry/exit counts for EFI world cross-overs match */
> EFI_EXIT(exit_status);
> @@ -2837,7 +2861,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
> image_handle,
>
> panic("EFI application exited");
> out:
> - return EFI_EXIT(EFI_INVALID_PARAMETER);
> + return EFI_EXIT(ret);
> }
>
> /**
> diff --git a/lib/efi_loader/efi_image_loader.c
> b/lib/efi_loader/efi_image_loader.c
> index f8092b6202..13541cfa7a 100644
> --- a/lib/efi_loader/efi_image_loader.c
> +++ b/lib/efi_loader/efi_image_loader.c
> @@ -273,6 +273,7 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj
> *handle, void *efi,
> IMAGE_OPTIONAL_HEADER64 *opt = >OptionalHeader;
> image_base = opt->ImageBase;
> efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
> + handle->image_type = opt->Subsystem;
> efi_reloc = efi_alloc(virt_size,
> loaded_image_info->image_code_type);
>
Re: [U-Boot] [PATCH v2 1/1] efi_loader: optional data in load options are binary
On Tue, May 07, 2019 at 06:54:45PM +0200, Heinrich Schuchardt wrote:
> On 5/7/19 9:30 AM, Takahiro Akashi wrote:
> >On Tue, May 07, 2019 at 09:12:56AM +0200, Heinrich Schuchardt wrote:
> >>On 5/7/19 8:16 AM, Takahiro Akashi wrote:
> >>>On Tue, May 07, 2019 at 08:04:26AM +0200, Heinrich Schuchardt wrote:
> On 5/7/19 7:16 AM, Heinrich Schuchardt wrote:
> >On 5/7/19 3:53 AM, Takahiro Akashi wrote:
> >>On Tue, Apr 30, 2019 at 08:11:15AM +0200, Heinrich Schuchardt wrote:
> >>>The field boot OptionalData in structure _EFI_LOAD_OPTIONS is for
> >>>binary
> >>>data.
> >>>
> >>>When we use `efidebug boot add` we should convert the 5th argument from
> >>>UTF-8 to UTF-16 before putting it into the Boot variable.
> >>
> >>While optional_data holds u8 string in calling
> >>efi_serialize_load_option(),
> >>it holds u16 string in leaving from efi_deserialize_load_option().
> >>We should handle it in a consistent way if you want to keep
> >>optional_data
> >>as "const u8."
>
> When communicating with Linux optional data may contain a u16 string.
> But I cannot see were our coding is inconsistent.
> >>>
> >>>I don't get your point.
> >>>Do you want to allow 'u8 *' variable to hold u16 string?#
> >>
> >>Yes, optional data may contain anything, in the case of Linux the
> >>command line parameters as an u16 string.
> >>
> >>Other operating systems may use the field in other ways, e.g. store an
> >>ASCII string.
> >
> >The problem is that with your patch optional_data is *always* converted
> >to utf-16 as far as we use efidebug.
> >My efidebug is not for linux only.
>
> optional_data treated is not treated as u16 in efidebug:
With your patch,
efi_serialize_load_option() always convert a given argument to
utf-16 and then the resulting variable contains u16 string as
optional_data. On the other hand, efi_deserialize_load_option()
does *not* convert an encoded optional_data in a variable to utf-8.
See what I mean?
-Takahiro Akashi
> include/hexdump.h:
> void print_hex_dump(const char *prefix_str, int prefix_type,
> int rowsize, int groupsize, const void *buf,
> size_t len, bool ascii);
>
> include/efi_loader:
> struct efi_load_option {
> u32 attributes;
> u16 file_path_length;
> u16 *label;
> struct efi_device_path *file_path;
> const u8 *optional_data;
> };
>
> cmd/efidebug.c
> print_hex_dump("", DUMP_PREFIX_OFFSET, 16, 1,
> lo.optional_data, size + (u8 *)data -
> (u8 *)lo.optional_data, true);
>
> Best regards
>
> Heinrich
>
> >
> >-Takahiro Akashi
> >
> >
> >>Regards
> >>
> >>Heinrich
> >>
> >>>
> >>>-Takahiro Akashi
> >>>
> Regards
>
> Heinrich
>
> >
> >The patch is already merged so I will have to create a follow up patch.
> >
> >The UEFI spec has EFI_LOAD_OPTION.OptionalData as UINT8. So an odd
> >number of bytes is a possibility.
> >
> >Best regards
> >
> >Heinrich
> >
> >>
> >>Thanks,
> >>-Takahiro Akashi
> >>
> >>>When printing boot variables with `efidebug boot dump` we should
> >>>support
> >>>the OptionalData being arbitrary binary data. So let's dump the data as
> >>>hexadecimal values.
> >>>
> >>>Here is an example session protocol:
> >>>
> >>>=> efidebug boot add 00a1 label1 scsi 0:1 doit1 'my option'
> >>>=> efidebug boot add 00a2 label2 scsi 0:1 doit2
> >>>=> efidebug boot dump
> >>>Boot00A0:
> >>> attributes: A-- (0x0001)
> >>> label: label1
> >>> file_path: .../HD(1,MBR,0xeac4e18b,0x800,0x3fffe)/doit1
> >>> data:
> >>> : 6d 00 79 00 20 00 6f 00 70 00 74 00 69 00 6f 00 m.y.
> >>>.o.p.t.i.o.
> >>> 0010: 6e 00 00 00 n...
> >>>Boot00A1:
> >>> attributes: A-- (0x0001)
> >>> label: label2
> >>> file_path: .../HD(1,MBR,0xeac4e18b,0x800,0x3fffe)/doit2
> >>> data:
> >>>
> >>>Signed-off-by: Heinrich Schuchardt
> >>>---
> >>>v2:
> >>> remove statement without effect in efi_serialize_load_option()
> >>>---
> >>> cmd/efidebug.c | 27 +--
> >>> include/efi_loader.h | 2 +-
> >>> lib/efi_loader/efi_bootmgr.c | 15 ---
> >>> 3 files changed, 26 insertions(+), 18 deletions(-)
> >>>
> >>>diff --git a/cmd/efidebug.c b/cmd/efidebug.c
> >>>index efe4ea873e..c4ac9dd634 100644
> >>>--- a/cmd/efidebug.c
> >>>+++ b/cmd/efidebug.c
> >>>@@ -11,6 +11,7 @@
> >>> #include
> >>> #include
> >>> #include
> >>>+#include
> >>> #include
> >>> #include
> >>> #include
> >>>@@ -545,7 +546,10 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int
> >>>flag,
> >>> + sizeof(struct
[U-Boot] Pull request: u-boot-net.git master
Hi Tom, The following changes since commit 8d7f06bbbef16f172cd5e9c4923cdcebe16b8980: I rebased on your master and built for BB Black. DHCP seems to work fine. MLO also now fits again. Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-05-07 09:38:00 -0400) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to 8d0c6858455e89b089222a08d55ff711681ca011: net: phy: micrel: Find Micrel PHY node correctly (2019-05-07 14:51:55 -0500) Carlo Caione (4): net: phy: Add generic helpers to access MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Switch to generic helpers when accessing the registers net: phy: realtek: Introduce quirk to mark RXC not stoppable James Byrne (2): net: phy: micrel: Use correct skew values on KSZ9021 net: phy: micrel: Find Micrel PHY node correctly Murali Karicheri (2): ARM: k2g-gp-evm: update to rgmii pinmux configuration ARM: k2g-ice: Add pinmux support for rgmii interface Pankaj Bansal (1): drivers: net: ldpaa_eth: fix resource leak Siva Durga Prasad Paladugu (2): net: phy: Reloc next and prev pointers inside phy_drivers net: phy: Fix return value check phy_probe Valentin-catalin Neacsu (1): net: phy: aquantia: Set only autoneg on in register 4.c441 Vladimir Oltean (6): net: phy: ar803x: Address packet drops at low traffic rate due to SmartEEE feature net: phy: ar803x: Make RGMII Tx delays actually configurable for AR8035 net: phy: ar803x: Use common functions for RGMII internal delays net: phy: ar803x: Clarify the configuration of the CLK_25M output pin net: phy: ar803x: Explicitly disable RGMII delays net: phy: ar803x: Clarify the intention of ar8021_config arch/arm/dts/sama5d3xcm.dtsi| 32 +++--- arch/arm/dts/sama5d3xcm_cmp.dtsi| 32 +++--- arch/arm/dts/socfpga_arria5_socdk.dts | 4 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 4 +- arch/arm/dts/socfpga_cyclone5_socdk.dts | 4 +- arch/arm/dts/socfpga_cyclone5_sockit.dts| 4 +- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 4 +- board/ti/ks2_evm/mux-k2g.h | 36 +++ cmd/mdio.c | 27 +++-- doc/device-tree-bindings/net/micrel-ksz90x1.txt | 27 + drivers/net/ldpaa_eth/ldpaa_eth.c | 1 + drivers/net/phy/Kconfig | 41 drivers/net/phy/aquantia.c | 7 +- drivers/net/phy/atheros.c | 128 --- drivers/net/phy/micrel_ksz90x1.c| 24 - drivers/net/phy/phy.c | 21 +++- drivers/net/phy/realtek.c | 19 drivers/net/phy/ti.c| 130 +--- include/phy.h | 70 + 19 files changed, 394 insertions(+), 221 deletions(-) Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] pico-imx7d: remove unused 'script' variable
Hi Pierre-Jean, On Tue, May 7, 2019 at 6:55 PM Pierre-Jean Texier wrote: > > Since the pico-pi uses the distroboot, > this commit remove the 'script' variable (cf boot_scripts). > > Signed-off-by: Pierre-Jean Texier Yes, we should better remove it: Reviewed-by: Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] pico-imx7d: remove unused 'script' variable
Since the pico-pi uses the distroboot, this commit remove the 'script' variable (cf boot_scripts). Signed-off-by: Pierre-Jean Texier --- include/configs/pico-imx7d.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 365a598..a6838b3 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -61,7 +61,6 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ "image=zImage\0" \ "splashpos=m,m\0" \ "console=ttymxc4\0" \ -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] mx6sl: hab: Fix pu_irom_mmu_enabled address
Hi Breno, On Tue, May 7, 2019 at 5:19 PM Breno Matheus Lima wrote: > > According to hab.c code we have to notify the ROM code if the MMU is > enabled or not. This is achieved by setting the "pu_irom_mmu_enabled" > to 0x1. > > The current address in hab.c code is wrong for i.MX6SL, according to ROM > map file the correct address is 0x00901c60. > > As we are writing in the wrong address the ROM code is not flushing the > caches when needed, and the following HAB event is observed in certain > scenarios: > > - HAB Event 1 - > event data: > 0xdb 0x00 0x14 0x41 0x33 0x18 0xc0 0x00 > 0xca 0x00 0x0c 0x00 0x01 0xc5 0x00 0x00 > 0x00 0x00 0x07 0xe4 > > STS = HAB_FAILURE (0x33) > RSN = HAB_INV_SIGNATURE (0x18) > CTX = HAB_CTX_COMMAND (0xC0) > ENG = HAB_ENG_ANY (0x00) > > Update MX6SL_PU_IROM_MMU_EN_VAR to address this issue. > > Reported-by: Frank Zhang > Signed-off-by: Breno Lima > Reviewed-by: Ye Li Thanks for the fix. Reviewed-by: Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] mx6sl: hab: Fix pu_irom_mmu_enabled address
According to hab.c code we have to notify the ROM code if the MMU is enabled or not. This is achieved by setting the "pu_irom_mmu_enabled" to 0x1. The current address in hab.c code is wrong for i.MX6SL, according to ROM map file the correct address is 0x00901c60. As we are writing in the wrong address the ROM code is not flushing the caches when needed, and the following HAB event is observed in certain scenarios: - HAB Event 1 - event data: 0xdb 0x00 0x14 0x41 0x33 0x18 0xc0 0x00 0xca 0x00 0x0c 0x00 0x01 0xc5 0x00 0x00 0x00 0x00 0x07 0xe4 STS = HAB_FAILURE (0x33) RSN = HAB_INV_SIGNATURE (0x18) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) Update MX6SL_PU_IROM_MMU_EN_VAR to address this issue. Reported-by: Frank Zhang Signed-off-by: Breno Lima Reviewed-by: Ye Li --- arch/arm/mach-imx/hab.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d42a15e877..24d16299e8 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -17,7 +17,7 @@ #define ALIGN_SIZE 0x1000 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 -#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 +#define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60 #define IS_HAB_ENABLED_BIT \ (is_soc_type(MXC_SOC_MX7ULP) ? 0x8000 : \ (is_soc_type(MXC_SOC_MX7) ? 0x200 : 0x2)) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 00/13] System Firmware Loader for TI K3 family SoCs
On 07.05.19 19:25, Andreas Dannenberg wrote: TI K3 SoCs like the AM654x devices are fundamentally dependent on a firmware called SYSFW (System Firmware) being loaded into the dedicated DMSC (Device Management and Security Controller) processor to provide various services via TISCI (Texas Instruments System Control Interface) to manage device aspects such as core bringup, power, clocks, security, and so on across the entire SoC. Currently public U-Boot does not boot on an actual AM654x EVM due to the missing loading and startup of SYSFW, with this being the only piece missing preventing a successful boot from SD/MMC-type media. This gap is addressed with this patch series. Note that the loading and starting of SYSFW is done in the context of board_init_f() in SPL which poses some unique challenges due to the very constrained nature of this environment (minimal amount of SRAM, no DDR yet available). In order to be as lean as possible on resource use an approach was chosen that extends the existing SPL loader framework to be usable beyond the usual "loading U-Boot" use case. While this patch series only makes changes to the MMC/SD card loader framework to support eMMC/MMC/SD FS- and sector/partition-based RAW boot at this time we have this solution in production today but extended to SPI/OSPI and Y-Modem without any issues. While I also have a working solution based on the existing FS loader framework this has its own challenges, namely by its very nature only addressing a subset of our use cases (no eMMC/SD RAW boot support for example), being heavier on resource usage (needing to use ENV to pass parameters), and not addressing the need to probe the boot peripheral. This particular framework works well for use cases requiring to load firmware from FS-based media once DDR is up and U-Boot is in a more "initialized" state but it is not a one-fits all solution for very early use in SPL board_init_f() accross different boot modes. And would it be an option to improve the loader (maybe dropping the "fs" from its name)? I think it's an "fs" loader because its idea has been copied from Linux. I think in U-Boot, it's more common to have things at a raw offset instead of a file system. Just thinking... And the current state of that fs_loader is like it is because it fits its single user (socfpga stratix 10), I think. Anyway, even if you do need yet another loader, would it make sense to create a common file instead of adding this in your arch/mach? Regards, Simon Andreas Dannenberg (10): mmc: k3_arasan: Allow driver to probe without PDs specified spl: Allow skipping clearing BSS during relocation spl: Make image loader infrastructure more universal arm: K3: Introduce System Firmware loader framework armV7R: K3: am654: Allow using SPL BSS pre-relocation armv7R: K3: am654: Use full malloc implementation in SPL armV7R: K3: am654: Load SYSFW binary and config from boot media configs: am65x_evm_r5: All sysfw to be loaded via MMC configs: am65x_hs_evm_r5: All sysfw to be loaded via MMC configs: am65x_hs_evm: Add Support for eMMC boot Faiz Abbas (2): configs: am65x_evm: Add Support for eMMC boot am65x: README: Add eMMC layout and flash instructions Lokesh Vutla (1): armv7R: dts: k3: am654: Update mmc nodes for loading sysfw arch/arm/dts/k3-am654-r5-base-board.dts | 18 ++ arch/arm/lib/crt0.S | 3 + arch/arm/mach-k3/Kconfig | 40 +++ arch/arm/mach-k3/Makefile| 1 + arch/arm/mach-k3/am6_init.c | 34 ++- arch/arm/mach-k3/include/mach/sysfw-loader.h | 12 + arch/arm/mach-k3/sysfw-loader.c | 263 +++ board/ti/am65x/Kconfig | 1 + board/ti/am65x/README| 52 common/spl/Kconfig | 13 + common/spl/spl_fit.c | 14 + common/spl/spl_mmc.c | 76 -- configs/am65x_evm_a53_defconfig | 2 + configs/am65x_evm_r5_defconfig | 7 +- configs/am65x_hs_evm_a53_defconfig | 2 + configs/am65x_hs_evm_r5_defconfig| 7 +- drivers/mmc/k3_arsan_sdhci.c | 16 +- include/configs/am65x_evm.h | 30 ++- include/spl.h| 26 ++ 19 files changed, 577 insertions(+), 40 deletions(-) create mode 100644 arch/arm/mach-k3/include/mach/sysfw-loader.h create mode 100644 arch/arm/mach-k3/sysfw-loader.c ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
>
>
> On 07.05.19 21:41, Marek Vasut wrote:
>> On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
>>>
>>>
>>> On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
register), the FPGA data register must be written with writes with
non-incrementing address.
The current code increments the address in 32-byte bursts. Fix the
code so it does not increment the address and writes the register
repeatedly instead. >
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
drivers/fpga/socfpga.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 685957626b..6ecea771ce 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -55,8 +55,7 @@ void fpgamgr_program_write(const void *rbf_data,
size_t rbf_size)
" cmp %2, #0\n"
" beq 2f\n"
"1: ldmia %0!, {r0-r7}\n"
- " stmia %1!, {r0-r7}\n"
- " sub %1, #32\n"
+ " stmia %1, {r0-r7}\n"
>>>
>>> Iirc, stmia without the "!" still stores the registers to different
>>> addresses, it just does not change %1 any more if you leave away the
>>> "!"? So this would save on opcode, but not change anything?
>>
>> Uh oh, you're right. Do we have a bigger problem here then ? Or is the
>> socfpga ignoring the bottom 5 bits of this register address ?
>
> Well, bitsream programming works for me very well (we're loading all our
> FGPAs in U-Boot from a FIT image), so maybe it's the documentation that
> has a problem?
That could indeed be, maybe someone on the CC list can take a look into
it and crosscheck it with internal docs ?
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On 07.05.19 21:41, Marek Vasut wrote:
On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
register), the FPGA data register must be written with writes with
non-incrementing address.
The current code increments the address in 32-byte bursts. Fix the
code so it does not increment the address and writes the register
repeatedly instead. >
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
drivers/fpga/socfpga.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 685957626b..6ecea771ce 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -55,8 +55,7 @@ void fpgamgr_program_write(const void *rbf_data,
size_t rbf_size)
" cmp %2, #0\n"
" beq 2f\n"
"1: ldmia %0!, {r0-r7}\n"
- " stmia %1!, {r0-r7}\n"
- " sub %1, #32\n"
+ " stmia %1, {r0-r7}\n"
Iirc, stmia without the "!" still stores the registers to different
addresses, it just does not change %1 any more if you leave away the
"!"? So this would save on opcode, but not change anything?
Uh oh, you're right. Do we have a bigger problem here then ? Or is the
socfpga ignoring the bottom 5 bits of this register address ?
Well, bitsream programming works for me very well (we're loading all our
FGPAs in U-Boot from a FIT image), so maybe it's the documentation that
has a problem?
Regards,
Simon
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Re: [U-Boot] [PATCH 2/2] ARM: socfpga: Clear PL310 early in SPL
On 5/7/19 9:42 PM, Simon Goldschmidt wrote: > > > On 07.05.19 21:20, Marek Vasut wrote: >> On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux >> will result in stale data in PL310 L2 cache controller. Even if the L2 >> cache controller is disabled via the CTRL register CTRL_EN bit, those >> data can interfere with operation of devices using DMA, like e.g. the >> DWMMC controller. This can in turn cause e.g. SPL to fail reading data >> from SD/MMC. > > I bet this is copy & paste from the gen5 patch? It should probably say > "On SoCFPGA A10 systems"? Nice find, fixed. > Other than that: > Reviewed-by: Simon Goldschmidt Thanks -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] ARM: socfpga: Clear PL310 early in SPL
On 07.05.19 21:20, Marek Vasut wrote: On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC. I bet this is copy & paste from the gen5 patch? It should probably say "On SoCFPGA A10 systems"? Other than that: Reviewed-by: Simon Goldschmidt The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller. This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again. The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- arch/arm/mach-socfpga/spl_a10.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index c8e73d47c0..8eb856f3d8 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -81,6 +81,7 @@ void board_init_f(ulong dummy) socfpga_init_security_policies(); socfpga_sdram_remap_zero(); + socfpga_pl310_clear(); /* Assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all(); ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
register), the FPGA data register must be written with writes with
non-incrementing address.
The current code increments the address in 32-byte bursts. Fix the
code so it does not increment the address and writes the register
repeatedly instead. >
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
drivers/fpga/socfpga.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 685957626b..6ecea771ce 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -55,8 +55,7 @@ void fpgamgr_program_write(const void *rbf_data, size_t
rbf_size)
" cmp %2, #0\n"
" beq 2f\n"
"1:ldmia %0!,{r0-r7}\n"
- " stmia %1!,{r0-r7}\n"
- " sub %1, #32\n"
+ " stmia %1, {r0-r7}\n"
Iirc, stmia without the "!" still stores the registers to different
addresses, it just does not change %1 any more if you leave away the
"!"? So this would save on opcode, but not change anything?
Regards,
Simon
" subs%2, #1\n"
" bne 1b\n"
"2:cmp %3, #0\n"
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Re: [U-Boot] [PATCH 1/2] ARM: socfpga: Pull PL310 clearing into common code
On 07.05.19 21:20, Marek Vasut wrote:
Pull the PL310 clearing code into common code, so it can be reused
by Arria10.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
Reviewed-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
arch/arm/mach-socfpga/misc.c | 54 +++
arch/arm/mach-socfpga/spl_gen5.c | 54 ---
3 files changed, 55 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index c3ca8cdf3b..27d0b6a370 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void);
#endif
void do_bridge_reset(int enable, unsigned int mask);
+void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index d887f0201f..410d5a8b49 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -46,6 +46,60 @@ int dram_init(void)
return 0;
}
+void socfpga_pl310_clear(void)
+{
+ u32 mask = 0xff, ena = 0;
+
+ icache_enable();
+
+ /* Disable the L2 cache */
+ clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+ writel(0x0, >pl310_tag_latency_ctrl);
+ writel(0x10, >pl310_data_latency_ctrl);
+
+ /* enable BRESP, instruction and data prefetch, full line of zeroes */
+ setbits_le32(>pl310_aux_ctrl,
+L310_AUX_CTRL_DATA_PREFETCH_MASK |
+L310_AUX_CTRL_INST_PREFETCH_MASK |
+L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ /* Enable the L2 cache */
+ ena = readl(>pl310_ctrl);
+ ena |= L2X0_CTRL_EN;
+
+ /*
+* Invalidate the PL310 L2 cache. Keep the invalidation code
+* entirely in L1 I-cache to avoid any bus traffic through
+* the L2.
+*/
+ asm volatile(
+ ".align5 \n"
+ " b 3f \n"
+ "1:str %1, [%4]\n"
+ " dsb \n"
+ " isb \n"
+ " str %0, [%2]\n"
+ " dsb \n"
+ " isb \n"
+ "2:ldr %0, [%2]\n"
+ " cmp %0, #0 \n"
+ " bne 2b \n"
+ " str %0, [%3]\n"
+ " dsb \n"
+ " isb \n"
+ " b 4f \n"
+ "3:b 1b \n"
+ "4:nop \n"
+ : "+r"(mask), "+r"(ena)
+ : "r"(>pl310_inv_way),
+ "r"(>pl310_cache_sync), "r"(>pl310_ctrl)
+ : "memory", "cc");
+
+ /* Disable the L2 cache */
+ clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index bd2a9fe5ae..65ecba1a31 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -63,60 +63,6 @@ u32 spl_boot_mode(const u32 boot_device)
}
#endif
-static void socfpga_pl310_clear(void)
-{
- u32 mask = 0xff, ena = 0;
-
- icache_enable();
-
- /* Disable the L2 cache */
- clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x111, >pl310_tag_latency_ctrl);
- writel(0x121, >pl310_data_latency_ctrl);
-
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
-
- /* Enable the L2 cache */
- ena = readl(>pl310_ctrl);
- ena |= L2X0_CTRL_EN;
-
- /*
-* Invalidate the PL310 L2 cache. Keep the invalidation code
-* entirely in L1 I-cache to avoid any bus traffic through
-* the L2.
-*/
- asm volatile(
- ".align5 \n"
- " b 3f \n"
- "1:str %1, [%4]\n"
- " dsb \n"
- " isb \n"
- " str %0, [%2]\n"
- " dsb \n"
- " isb \n"
- "2:ldr %0, [%2]\n"
- " cmp %0, #0 \n"
- " bne 2b \n"
- " str %0, [%3]\n"
- " dsb \n"
-
Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
>
>
> On 07.05.19 21:19, Marek Vasut wrote:
>> According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
>> (Chapter 5, FPGA Manager, data register) and Arria10 datasheet
>> rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
>> register), the FPGA data register must be written with writes with
>> non-incrementing address.
>>
>> The current code increments the address in 32-byte bursts. Fix the
>> code so it does not increment the address and writes the register
>> repeatedly instead. >
>> Signed-off-by: Marek Vasut
>> Cc: Chin Liang See
>> Cc: Dinh Nguyen
>> Cc: Simon Goldschmidt
>> Cc: Tien Fong Chee
>> ---
>> drivers/fpga/socfpga.c | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
>> index 685957626b..6ecea771ce 100644
>> --- a/drivers/fpga/socfpga.c
>> +++ b/drivers/fpga/socfpga.c
>> @@ -55,8 +55,7 @@ void fpgamgr_program_write(const void *rbf_data,
>> size_t rbf_size)
>> " cmp %2, #0\n"
>> " beq 2f\n"
>> "1: ldmia %0!, {r0-r7}\n"
>> - " stmia %1!, {r0-r7}\n"
>> - " sub %1, #32\n"
>> + " stmia %1, {r0-r7}\n"
>
> Iirc, stmia without the "!" still stores the registers to different
> addresses, it just does not change %1 any more if you leave away the
> "!"? So this would save on opcode, but not change anything?
Uh oh, you're right. Do we have a bigger problem here then ? Or is the
socfpga ignoring the bottom 5 bits of this register address ?
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/2] ARM: dts: socfpga: Factor out U-Boot specifics from A10 handoff files
On 5/7/19 9:28 PM, Simon Goldschmidt wrote: > > > On 07.05.19 21:18, Marek Vasut wrote: >> Pull out the u-boot,dm-pre-reloc from >> socfpga_arria10_socdk_sdmmc_handoff.dtsi >> into separate dtsi header file to make it easier to patch in custom >> handoff >> dtsi files, without having to manually add the U-Boot bits. Shuffle >> the include >> clauses in the A10 DT files to make it obvious what gets included >> where without >> having to follow confusing long chain of includes, i.e. board DT file >> includes >> everything it needs. >> >> Signed-off-by: Marek Vasut >> Cc: Chin Liang See >> Cc: Dinh Nguyen >> Cc: Simon Goldschmidt >> Cc: Tien Fong Chee > > Reviewed-by: Simon Goldschmidt > > Just being curious: the remaining "*_handoff.dtsi", is this now the > unmodified output of Quartus (or whatever)? Yes -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: dts: socfpga: Factor out U-Boot specifics from A10 handoff files
On 07.05.19 21:18, Marek Vasut wrote:
Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi
into separate dtsi header file to make it easier to patch in custom handoff
dtsi files, without having to manually add the U-Boot bits. Shuffle the include
clauses in the A10 DT files to make it obvious what gets included where without
having to follow confusing long chain of includes, i.e. board DT file includes
everything it needs.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
Reviewed-by: Simon Goldschmidt
Just being curious: the remaining "*_handoff.dtsi", is this now the
unmodified output of Quartus (or whatever)?
Regards,
Simon
---
.../dts/socfpga_arria10_handoff_u-boot.dtsi | 67 +++
arch/arm/dts/socfpga_arria10_socdk.dtsi | 3 +-
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 2 +
.../socfpga_arria10_socdk_sdmmc_handoff.dtsi | 17 -
4 files changed, 71 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
new file mode 100644
index 00..39a8d9a3e7
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/ {
+ chosen {
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ u-boot,dm-pre-reloc;
+
+ altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clock_manager@0xffd04000 {
+ u-boot,dm-pre-reloc;
+
+ mainpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ perpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ pinmux@0xffd07000 {
+ u-boot,dm-pre-reloc;
+
+ shared {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpga {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ noc@0xffd1 {
+ u-boot,dm-pre-reloc;
+
+ firewall {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi
b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 42e888548e..6e5578d7bd 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -14,7 +14,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see
Re: [U-Boot] [PATCH] arm: socfpga: Re-add support for Aries MCV SoM and MCVEVK board
On 07.05.19 21:14, Wolfgang Grandegger wrote:
Am 07.05.19 um 13:37 schrieb Simon Goldschmidt:
On Tue, May 7, 2019 at 9:41 AM Wolfgang Grandegger
wrote:
Am 06.05.19 um 22:16 schrieb Simon Goldschmidt:
Am 06.05.2019 um 17:45 schrieb Wolfgang Grandegger:
Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK baseboard. The board can boot from eMMC.
Ethernet and USB is supported.
The Aries Embedded boards have been removed with commit 03b54997d568
("board/aries: Remove"). I will now take care of them.
Signed-off-by: Wolfgang Grandegger
CC: Marek Vasut
CC: Simon Goldschmidt
---
.travis.yml | 2 +-
arch/arm/dts/Makefile| 1 +
arch/arm/dts/socfpga_cyclone5_mcv.dtsi | 22 +
arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi | 38 ++
arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 81 +++
arch/arm/mach-socfpga/Kconfig| 7 +
board/aries/mcvevk/MAINTAINERS | 6 +
board/aries/mcvevk/Makefile | 7 +
board/aries/mcvevk/qts/iocsr_config.h| 659
+++
board/aries/mcvevk/qts/pinmux_config.h | 218
board/aries/mcvevk/qts/pll_config.h | 84 +++
board/aries/mcvevk/qts/sdram_config.h| 343
These files are always a mystery. Would you be able to provide
(long-lived) link to a simplistic quartus project so that everyone can
regenerate these?
I'll try to provide such a quartus project for the socrates board, and
I'd be very happy if the original Intel dev boards could do so as well!
There is a Quartus example project for that module/board here:
https://github.com/ARIES-Embedded/mcv
Cool. And is this a permanent link that we could add to some kind
of documentation for this board in the U-Boot sources? That would
ensure U-Boot maintainers can find it in the future...
I will check with the author!
BTW: My patch works fine on top of v2019.04 but the boot hangs without
console output with the latest HEAD. The problems start with commit:
ede6e7b reset: socfpga: add reset handling for old kernels
Then I get:
U-Boot SPL 2019.04-00508-g03b5c7e-dirty (May 07 2019 - 21:03:52 +0200)
### ERROR ### Please RESET the board ###
Any idea how to fix that?
No, sorry, I don't have an idea right now. Are you sure you're not
missing any of the "u-boot,dm-pre-reloc" tags?
And you're absolutely sure this very commit produces this error?
Regards,
Simon
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Re: [U-Boot] [PATCH 04/13] arm: K3: Introduce System Firmware loader framework
On 07.05.19 21:17, Andreas Dannenberg wrote: Hi Simon, On Tue, May 07, 2019 at 08:16:07PM +0200, Simon Goldschmidt wrote: On 07.05.19 19:25, Andreas Dannenberg wrote: Introduce a framework that allows loading the System Firmware (SYSFW) binary as well as the associated configuration data from an image tree blob named "sysfw.itb" from an FS-based MMC boot media or from an MMC RAW mode partition or sector. To simplify the handling of and loading from the different boot media we tap into the existing U-Boot SPL framework usually used for loading U-Boot by building on an earlier commit that exposes some of that functionality. Note that this initial implementation only supports FS and RAW-based eMMC/SD card boot. Signed-off-by: Andreas Dannenberg Signed-off-by: Lokesh Vutla Without having a too deep understanding of this, all this stuff looks like it would be similar to drivers/misc/fs_loader.c? Could it build on top of that? Yes and no. Can you please review the associated cover letter, it addresses this very question which I expected to get raised. Ah, ok. Indeed I seemed to skip those lines when reading the cover letter, sorry. Regards, Simon Thanks, Andreas Regards, Simon --- arch/arm/mach-k3/Kconfig | 40 +++ arch/arm/mach-k3/Makefile| 1 + arch/arm/mach-k3/include/mach/sysfw-loader.h | 12 + arch/arm/mach-k3/sysfw-loader.c | 263 +++ 4 files changed, 316 insertions(+) create mode 100644 arch/arm/mach-k3/include/mach/sysfw-loader.h create mode 100644 arch/arm/mach-k3/sysfw-loader.c diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index e677a2e01b..f1731dda58 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -58,6 +58,46 @@ config SYS_K3_BOOT_CORE_ID int default 16 +config K3_LOAD_SYSFW + bool + depends on SPL + default n + +config K3_SYSFW_IMAGE_NAME + string "File name of SYSFW firmware and configuration blob" + depends on K3_LOAD_SYSFW + default "sysfw.itb" + help + Filename of the combined System Firmware and configuration image tree + blob to be loaded when booting from a filesystem. + +config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT + hex "MMC sector to load SYSFW firmware and configuration blob from" + depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + default 0x3600 + help + Address on the MMC to load the combined System Firmware and + configuration image tree blob from, when the MMC is being used + in raw mode. Units: MMC sectors (1 sector = 512 bytes). + +config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART + hex "MMC partition to load SYSFW firmware and configuration blob from" + depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + default 2 + help + Partition on the MMC to the combined System Firmware and configuration + image tree blob from, when the MMC is being used in raw mode. + +config K3_SYSFW_IMAGE_SIZE_MAX + int "Amount of memory dynamically allocated for loading SYSFW blob" + depends on K3_LOAD_SYSFW + default 269000 + help + Amount of memory reserved through dynamic allocation at runtime for + loading the combined System Firmware and configuration image tree + blob. Keep it as tight as possible, as this directly affects the + overall SPL memory footprint. + config SYS_K3_SPL_ATF bool "Start Cortex-A from SPL" depends on SPL && CPU_V7R diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 0c3a4f7db1..6c895400c2 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_TI_SECURE_DEVICE) += security.o +obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o obj-y += common.o diff --git a/arch/arm/mach-k3/include/mach/sysfw-loader.h b/arch/arm/mach-k3/include/mach/sysfw-loader.h new file mode 100644 index 00..36eb265348 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/sysfw-loader.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Andreas Dannenberg + */ + +#ifndef _SYSFW_LOADER_H_ +#define _SYSFW_LOADER_H_ + +void k3_sysfw_loader(void (*config_pm_done_callback)(void)); + +#endif diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c new file mode 100644 index 00..a66c27 --- /dev/null +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * K3: System Firmware Loader + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Andreas Dannenberg + */ + +#include +#include +#include
[U-Boot] [PATCH 2/2] ARM: socfpga: Clear PL310 early in SPL
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC. The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller. This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again. The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- arch/arm/mach-socfpga/spl_a10.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index c8e73d47c0..8eb856f3d8 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -81,6 +81,7 @@ void board_init_f(ulong dummy) socfpga_init_security_policies(); socfpga_sdram_remap_zero(); + socfpga_pl310_clear(); /* Assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all(); -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] ARM: socfpga: Pull PL310 clearing into common code
Pull the PL310 clearing code into common code, so it can be reused
by Arria10.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
arch/arm/mach-socfpga/misc.c | 54 +++
arch/arm/mach-socfpga/spl_gen5.c | 54 ---
3 files changed, 55 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index c3ca8cdf3b..27d0b6a370 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void);
#endif
void do_bridge_reset(int enable, unsigned int mask);
+void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index d887f0201f..410d5a8b49 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -46,6 +46,60 @@ int dram_init(void)
return 0;
}
+void socfpga_pl310_clear(void)
+{
+ u32 mask = 0xff, ena = 0;
+
+ icache_enable();
+
+ /* Disable the L2 cache */
+ clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+ writel(0x0, >pl310_tag_latency_ctrl);
+ writel(0x10, >pl310_data_latency_ctrl);
+
+ /* enable BRESP, instruction and data prefetch, full line of zeroes */
+ setbits_le32(>pl310_aux_ctrl,
+L310_AUX_CTRL_DATA_PREFETCH_MASK |
+L310_AUX_CTRL_INST_PREFETCH_MASK |
+L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ /* Enable the L2 cache */
+ ena = readl(>pl310_ctrl);
+ ena |= L2X0_CTRL_EN;
+
+ /*
+* Invalidate the PL310 L2 cache. Keep the invalidation code
+* entirely in L1 I-cache to avoid any bus traffic through
+* the L2.
+*/
+ asm volatile(
+ ".align 5 \n"
+ " b 3f \n"
+ "1: str %1, [%4]\n"
+ " dsb \n"
+ " isb \n"
+ " str %0, [%2]\n"
+ " dsb \n"
+ " isb \n"
+ "2: ldr %0, [%2]\n"
+ " cmp %0, #0 \n"
+ " bne 2b \n"
+ " str %0, [%3]\n"
+ " dsb \n"
+ " isb \n"
+ " b 4f \n"
+ "3: b 1b \n"
+ "4: nop \n"
+ : "+r"(mask), "+r"(ena)
+ : "r"(>pl310_inv_way),
+ "r"(>pl310_cache_sync), "r"(>pl310_ctrl)
+ : "memory", "cc");
+
+ /* Disable the L2 cache */
+ clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index bd2a9fe5ae..65ecba1a31 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -63,60 +63,6 @@ u32 spl_boot_mode(const u32 boot_device)
}
#endif
-static void socfpga_pl310_clear(void)
-{
- u32 mask = 0xff, ena = 0;
-
- icache_enable();
-
- /* Disable the L2 cache */
- clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x111, >pl310_tag_latency_ctrl);
- writel(0x121, >pl310_data_latency_ctrl);
-
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
-
- /* Enable the L2 cache */
- ena = readl(>pl310_ctrl);
- ena |= L2X0_CTRL_EN;
-
- /*
-* Invalidate the PL310 L2 cache. Keep the invalidation code
-* entirely in L1 I-cache to avoid any bus traffic through
-* the L2.
-*/
- asm volatile(
- ".align 5 \n"
- " b 3f \n"
- "1: str %1, [%4]\n"
- " dsb \n"
- " isb \n"
- " str %0, [%2]\n"
- " dsb \n"
- " isb \n"
- "2: ldr %0, [%2]\n"
- " cmp %0, #0 \n"
- " bne 2b \n"
- " str %0, [%3]\n"
- " dsb \n"
- "
[U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
register), the FPGA data register must be written with writes with
non-incrementing address.
The current code increments the address in 32-byte bursts. Fix the
code so it does not increment the address and writes the register
repeatedly instead.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
drivers/fpga/socfpga.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 685957626b..6ecea771ce 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -55,8 +55,7 @@ void fpgamgr_program_write(const void *rbf_data, size_t
rbf_size)
" cmp %2, #0\n"
" beq 2f\n"
"1: ldmia %0!,{r0-r7}\n"
- " stmia %1!,{r0-r7}\n"
- " sub %1, #32\n"
+ " stmia %1, {r0-r7}\n"
" subs%2, #1\n"
" bne 1b\n"
"2: cmp %3, #0\n"
--
2.20.1
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[U-Boot] [PATCH 2/2] ARM: dts: socfpga: Keep FPGA bridge entries in SPL DT
Keep the FPGA bridge entries in SPL DT to let do_bridge_reset() toggle
the bridges on/off as needed according to the handoff file.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
.../dts/socfpga_arria10_handoff_u-boot.dtsi | 24 +++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
index 39a8d9a3e7..ef215230c2 100644
--- a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -64,4 +64,28 @@
u-boot,dm-pre-reloc;
};
};
+
+ fpgabridge@0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@2 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@3 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@4 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@5 {
+ u-boot,dm-pre-reloc;
+ };
};
--
2.20.1
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[U-Boot] [PATCH 1/2] ARM: dts: socfpga: Factor out U-Boot specifics from A10 handoff files
Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi
into separate dtsi header file to make it easier to patch in custom handoff
dtsi files, without having to manually add the U-Boot bits. Shuffle the include
clauses in the A10 DT files to make it obvious what gets included where without
having to follow confusing long chain of includes, i.e. board DT file includes
everything it needs.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
.../dts/socfpga_arria10_handoff_u-boot.dtsi | 67 +++
arch/arm/dts/socfpga_arria10_socdk.dtsi | 3 +-
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 2 +
.../socfpga_arria10_socdk_sdmmc_handoff.dtsi | 17 -
4 files changed, 71 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
new file mode 100644
index 00..39a8d9a3e7
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/ {
+ chosen {
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ u-boot,dm-pre-reloc;
+
+ altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clock_manager@0xffd04000 {
+ u-boot,dm-pre-reloc;
+
+ mainpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ perpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ pinmux@0xffd07000 {
+ u-boot,dm-pre-reloc;
+
+ shared {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpga {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ noc@0xffd1 {
+ u-boot,dm-pre-reloc;
+
+ firewall {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi
b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 42e888548e..6e5578d7bd 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -14,7 +14,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see
[U-Boot] [PATCH] spl: Set spl_image->fdt_addr pointer for full fitImage configuration
Set the spl_image->fdt_addr pointer both for simple fitImage configuration
as well as full fitImage configuration, to let spl_perform_fixups() access
the DT and perform modifications to it if necessary.
Signed-off-by: Marek Vasut
Cc: Tom Rini
---
common/spl/spl.c | 4 +++-
include/spl.h| 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 0a6a47c202..4ddeff9b51 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -195,10 +195,12 @@ static int spl_load_fit_image(struct spl_image_info
*spl_image,
#ifdef CONFIG_SPL_FIT_SIGNATURE
images.verify = 1;
#endif
- fit_image_load(, (ulong)header,
+ ret = fit_image_load(, (ulong)header,
_uname_fdt, _uname_config,
IH_ARCH_DEFAULT, IH_TYPE_FLATDT, -1,
FIT_LOAD_OPTIONAL, _data, _len);
+ if (ret >= 0)
+ spl_image->fdt_addr = (void *)dt_data;
conf_noffset = fit_conf_get_node((const void *)header,
fit_uname_config);
diff --git a/include/spl.h b/include/spl.h
index f09909e189..a9aaef345f 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -67,7 +67,7 @@ struct spl_image_info {
u8 os;
uintptr_t load_addr;
uintptr_t entry_point;
-#if CONFIG_IS_ENABLED(LOAD_FIT)
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
void *fdt_addr;
#endif
u32 boot_device;
--
2.20.1
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Re: [U-Boot] [PATCH 04/13] arm: K3: Introduce System Firmware loader framework
Hi Simon, On Tue, May 07, 2019 at 08:16:07PM +0200, Simon Goldschmidt wrote: > > > On 07.05.19 19:25, Andreas Dannenberg wrote: > > Introduce a framework that allows loading the System Firmware (SYSFW) > > binary as well as the associated configuration data from an image tree > > blob named "sysfw.itb" from an FS-based MMC boot media or from an MMC > > RAW mode partition or sector. > > > > To simplify the handling of and loading from the different boot media > > we tap into the existing U-Boot SPL framework usually used for loading > > U-Boot by building on an earlier commit that exposes some of that > > functionality. > > > > Note that this initial implementation only supports FS and RAW-based > > eMMC/SD card boot. > > > > Signed-off-by: Andreas Dannenberg > > Signed-off-by: Lokesh Vutla > > Without having a too deep understanding of this, all this stuff looks like > it would be similar to drivers/misc/fs_loader.c? > > Could it build on top of that? Yes and no. Can you please review the associated cover letter, it addresses this very question which I expected to get raised. Thanks, Andreas > > Regards, > Simon > > > --- > > arch/arm/mach-k3/Kconfig | 40 +++ > > arch/arm/mach-k3/Makefile| 1 + > > arch/arm/mach-k3/include/mach/sysfw-loader.h | 12 + > > arch/arm/mach-k3/sysfw-loader.c | 263 +++ > > 4 files changed, 316 insertions(+) > > create mode 100644 arch/arm/mach-k3/include/mach/sysfw-loader.h > > create mode 100644 arch/arm/mach-k3/sysfw-loader.c > > > > diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig > > index e677a2e01b..f1731dda58 100644 > > --- a/arch/arm/mach-k3/Kconfig > > +++ b/arch/arm/mach-k3/Kconfig > > @@ -58,6 +58,46 @@ config SYS_K3_BOOT_CORE_ID > > int > > default 16 > > +config K3_LOAD_SYSFW > > + bool > > + depends on SPL > > + default n > > + > > +config K3_SYSFW_IMAGE_NAME > > + string "File name of SYSFW firmware and configuration blob" > > + depends on K3_LOAD_SYSFW > > + default "sysfw.itb" > > + help > > + Filename of the combined System Firmware and configuration image tree > > + blob to be loaded when booting from a filesystem. > > + > > +config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT > > + hex "MMC sector to load SYSFW firmware and configuration blob from" > > + depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR > > + default 0x3600 > > + help > > + Address on the MMC to load the combined System Firmware and > > + configuration image tree blob from, when the MMC is being used > > + in raw mode. Units: MMC sectors (1 sector = 512 bytes). > > + > > +config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART > > + hex "MMC partition to load SYSFW firmware and configuration blob from" > > + depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION > > + default 2 > > + help > > + Partition on the MMC to the combined System Firmware and configuration > > + image tree blob from, when the MMC is being used in raw mode. > > + > > +config K3_SYSFW_IMAGE_SIZE_MAX > > + int "Amount of memory dynamically allocated for loading SYSFW blob" > > + depends on K3_LOAD_SYSFW > > + default 269000 > > + help > > + Amount of memory reserved through dynamic allocation at runtime for > > + loading the combined System Firmware and configuration image tree > > + blob. Keep it as tight as possible, as this directly affects the > > + overall SPL memory footprint. > > + > > config SYS_K3_SPL_ATF > > bool "Start Cortex-A from SPL" > > depends on SPL && CPU_V7R > > diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile > > index 0c3a4f7db1..6c895400c2 100644 > > --- a/arch/arm/mach-k3/Makefile > > +++ b/arch/arm/mach-k3/Makefile > > @@ -7,4 +7,5 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o > > obj-$(CONFIG_ARM64) += arm64-mmu.o > > obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o > > obj-$(CONFIG_TI_SECURE_DEVICE) += security.o > > +obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o > > obj-y += common.o > > diff --git a/arch/arm/mach-k3/include/mach/sysfw-loader.h > > b/arch/arm/mach-k3/include/mach/sysfw-loader.h > > new file mode 100644 > > index 00..36eb265348 > > --- /dev/null > > +++ b/arch/arm/mach-k3/include/mach/sysfw-loader.h > > @@ -0,0 +1,12 @@ > > +/* SPDX-License-Identifier: GPL-2.0+ */ > > +/* > > + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ > > + * Andreas Dannenberg > > + */ > > + > > +#ifndef _SYSFW_LOADER_H_ > > +#define _SYSFW_LOADER_H_ > > + > > +void k3_sysfw_loader(void (*config_pm_done_callback)(void)); > > + > > +#endif > > diff --git a/arch/arm/mach-k3/sysfw-loader.c > > b/arch/arm/mach-k3/sysfw-loader.c > > new file mode 100644 > > index 00..a66c27 > > --- /dev/null > > +++ b/arch/arm/mach-k3/sysfw-loader.c > > @@ -0,0 +1,263 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * K3: System
[U-Boot] [PATCH v2 1/1] efi_loader: unload applications upon Exit()
Implement unloading of images in the Exit() boot services:
* unload images that are not yet started,
* unload started applications,
* unload drivers returning an error.
Signed-off-by: Heinrich Schuchardt
---
v2
Images that are no yet started can be unloaded by calling Exit().
In this case they are not the current image. Move the test for
current down in the code.
A started driver that called Exit() should still be considered a
started image. Exit cannot be called by another image afterwards,
cf. UEFI SCT 2.6 (2017), 3.5.1 Exit(), 5.1.4.5.8 - 5.1.4.5.10.
---
include/efi_loader.h | 1 +
lib/efi_loader/efi_boottime.c | 36 +--
lib/efi_loader/efi_image_loader.c | 2 ++
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 3b50cd28ef..4e4cffa799 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -234,6 +234,7 @@ struct efi_loaded_image_obj {
struct jmp_buf_data exit_jmp;
EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
struct efi_system_table *st);
+ u16 image_type;
};
/**
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 0385883ded..1ea96dab6c 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -2798,7 +2799,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
* image protocol.
*/
efi_status_t ret;
- void *info;
+ struct efi_loaded_image *loaded_image_protocol;
struct efi_loaded_image_obj *image_obj =
(struct efi_loaded_image_obj *)image_handle;
@@ -2806,13 +2807,33 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
exit_data_size, exit_data);
/* Check parameters */
- if (image_handle != current_image)
- goto out;
ret = EFI_CALL(efi_open_protocol(image_handle, _guid_loaded_image,
-, NULL, NULL,
+(void **)_image_protocol,
+NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL));
- if (ret != EFI_SUCCESS)
+ if (ret != EFI_SUCCESS) {
+ ret = EFI_INVALID_PARAMETER;
goto out;
+ }
+
+ /* Unloading of unstarted images */
+ switch (image_obj->header.type) {
+ case EFI_OBJECT_TYPE_STARTED_IMAGE:
+ break;
+ case EFI_OBJECT_TYPE_LOADED_IMAGE:
+ efi_delete_image(image_obj, loaded_image_protocol);
+ ret = EFI_SUCCESS;
+ goto out;
+ default:
+ /* Handle does not refer to loaded image */
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ /* A started image can only be unloaded it is the last one started. */
+ if (image_handle != current_image) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
/* Exit data is only foreseen in case of failure. */
if (exit_status != EFI_SUCCESS) {
@@ -2822,6 +2843,9 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
if (ret != EFI_SUCCESS)
EFI_PRINT("%s: out of memory\n", __func__);
}
+ if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION ||
+ exit_status != EFI_SUCCESS)
+ efi_delete_image(image_obj, loaded_image_protocol);
/* Make sure entry/exit counts for EFI world cross-overs match */
EFI_EXIT(exit_status);
@@ -2837,7 +2861,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t
image_handle,
panic("EFI application exited");
out:
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ return EFI_EXIT(ret);
}
/**
diff --git a/lib/efi_loader/efi_image_loader.c
b/lib/efi_loader/efi_image_loader.c
index f8092b6202..13541cfa7a 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -273,6 +273,7 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj
*handle, void *efi,
IMAGE_OPTIONAL_HEADER64 *opt = >OptionalHeader;
image_base = opt->ImageBase;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
+ handle->image_type = opt->Subsystem;
efi_reloc = efi_alloc(virt_size,
loaded_image_info->image_code_type);
if (!efi_reloc) {
@@ -288,6 +289,7 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj
*handle, void *efi,
IMAGE_OPTIONAL_HEADER32 *opt = >OptionalHeader;
image_base = opt->ImageBase;
Re: [U-Boot] [PATCH] arm: socfpga: Re-add support for Aries MCV SoM and MCVEVK board
Am 07.05.19 um 13:37 schrieb Simon Goldschmidt:
> On Tue, May 7, 2019 at 9:41 AM Wolfgang Grandegger
> wrote:
>>
>>
>>
>> Am 06.05.19 um 22:16 schrieb Simon Goldschmidt:
>>> Am 06.05.2019 um 17:45 schrieb Wolfgang Grandegger:
Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK baseboard. The board can boot from eMMC.
Ethernet and USB is supported.
The Aries Embedded boards have been removed with commit 03b54997d568
("board/aries: Remove"). I will now take care of them.
Signed-off-by: Wolfgang Grandegger
CC: Marek Vasut
CC: Simon Goldschmidt
---
.travis.yml | 2 +-
arch/arm/dts/Makefile| 1 +
arch/arm/dts/socfpga_cyclone5_mcv.dtsi | 22 +
arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi | 38 ++
arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 81 +++
arch/arm/mach-socfpga/Kconfig| 7 +
board/aries/mcvevk/MAINTAINERS | 6 +
board/aries/mcvevk/Makefile | 7 +
board/aries/mcvevk/qts/iocsr_config.h| 659
+++
board/aries/mcvevk/qts/pinmux_config.h | 218
board/aries/mcvevk/qts/pll_config.h | 84 +++
board/aries/mcvevk/qts/sdram_config.h| 343
>>>
>>> These files are always a mystery. Would you be able to provide
>>> (long-lived) link to a simplistic quartus project so that everyone can
>>> regenerate these?
>>>
>>> I'll try to provide such a quartus project for the socrates board, and
>>> I'd be very happy if the original Intel dev boards could do so as well!
>>
>> There is a Quartus example project for that module/board here:
>>
>> https://github.com/ARIES-Embedded/mcv
>
> Cool. And is this a permanent link that we could add to some kind
> of documentation for this board in the U-Boot sources? That would
> ensure U-Boot maintainers can find it in the future...
I will check with the author!
BTW: My patch works fine on top of v2019.04 but the boot hangs without
console output with the latest HEAD. The problems start with commit:
ede6e7b reset: socfpga: add reset handling for old kernels
Then I get:
U-Boot SPL 2019.04-00508-g03b5c7e-dirty (May 07 2019 - 21:03:52 +0200)
### ERROR ### Please RESET the board ###
Any idea how to fix that?
Wolfgang
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[U-Boot] [PATCH v3 4/6] rockchip: rk3399: Get bl31.elf via BL31
Right now rockchip platform need to copy bl31.elf into u-boot
source directory to make use of building u-boot.itb.
So, add environment variable BL31 like Allwinner SoC so-that the
bl31.elf would available via BL31.
If the builds are not exporting BL31 env, the make_fit_atf.py
explicitly create dummy bl31.elf in u-boot root directory to
satisfy travis builds and it will show the warning on console as
WARNING: BL31 file bl31.elf NOT found, resulting binary is non-functional
WARNING: Please read Building section in doc/README.rockchip
Note, that the dummy bl31 files were created during not exporting
BL31 case would be removed via clean target in Makefile.
Signed-off-by: Jagan Teki
---
Makefile | 2 +-
arch/arm/mach-rockchip/make_fit_atf.py | 11 ++-
doc/README.rockchip| 4 ++--
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/Makefile b/Makefile
index 64c7976f7e..c5078b95b7 100644
--- a/Makefile
+++ b/Makefile
@@ -1814,7 +1814,7 @@ clean: $(clean-dirs)
-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f \
- bl31_*.bin image.map
+ bl31.c bl31.elf bl31_*.bin image.map
# mrproper - Delete all generated files, including .config
#
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py
b/arch/arm/mach-rockchip/make_fit_atf.py
index d1faff1957..327875d87b 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -10,6 +10,7 @@ usage: $0 [ [ bl31.c")
+os.system("${CROSS_COMPILE}gcc -c bl31.c -o bl31.elf")
+bl31_elf="./bl31.elf"
+logging.basicConfig(format='%(levelname)s:%(message)s',
level=logging.DEBUG)
+logging.warning(' BL31 file bl31.elf NOT found, resulting binary is
non-functional')
+logging.warning(' Please read Building section in doc/README.rockchip')
opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h")
for opt, val in opts:
diff --git a/doc/README.rockchip b/doc/README.rockchip
index ca4d6473b0..98a3824e2c 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -149,8 +149,8 @@ For example:
=> make realclean
=> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
- (copy bl31.elf into U-Boot root dir)
- => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot
+ (export bl31.elf)
+ => export
BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
- Compile PMU M0 firmware
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v3 5/6] board: puma: Get bl31.bin via BL31 and rk3399m0.bin via PMUM0
Right now puma rk3399 board need to copy bl31-rk3399.bin and
rk3399m0.bin into u-boot source directory to make use of building
u-boot.itb.
So, add environment variable
- BL31 for bl31.bin (instead of bl31-rk3399.bin to compatible with other
platform BL31 env)
- PMUM0 for rk3399m0.bin
If the builds are not exporting BL31, PMUM0 env, the fit_spl_atf.sh will
notify with warning about which document to refer for more information
like this:
WARNING: BL31 file bl31.bin NOT found, resulting binary is non-functional
Please read Building section in doc/README.rockchip
WARNING: PMUM0 file rk3399m0.bin NOT found, resulting binary is non-functional
Please read Building section in doc/README.rockchip
Signed-off-by: Jagan Teki
---
.../puma_rk3399/fit_spl_atf.its | 58
.../puma_rk3399/fit_spl_atf.sh| 94 +++
configs/puma-rk3399_defconfig | 2 +-
doc/README.rockchip | 8 +-
4 files changed, 99 insertions(+), 63 deletions(-)
delete mode 100644 board/theobroma-systems/puma_rk3399/fit_spl_atf.its
create mode 100755 board/theobroma-systems/puma_rk3399/fit_spl_atf.sh
diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
deleted file mode 100644
index 530f059f3d..00
--- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR X11 */
-/*
- * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
- *
- * Minimal dts for a SPL FIT image payload.
- */
-
-/dts-v1/;
-
-/ {
- description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware,
DTB";
- #address-cells = <1>;
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- data = /incbin/("../../../u-boot-nodtb.bin");
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <0x0020>;
- };
- atf {
- description = "ARM Trusted Firmware";
- data = /incbin/("../../../bl31-rk3399.bin");
- type = "firmware";
- arch = "arm64";
- os = "arm-trusted-firmware";
- compression = "none";
- load = <0x1000>;
- entry = <0x1000>;
- };
- pmu {
- description = "Cortex-M0 firmware";
- data = /incbin/("../../../rk3399m0.bin");
- type = "pmu-firmware";
- compression = "none";
- load = <0x18>;
-};
- fdt {
- description = "RK3399-Q7 (Puma) flat device-tree";
- data = /incbin/("../../../u-boot.dtb");
- type = "flat_dt";
- compression = "none";
- };
- };
-
- configurations {
- default = "conf";
- conf {
- description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
- firmware = "atf";
- loadables = "uboot", "pmu";
- fdt = "fdt";
- };
- };
-};
diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh
b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh
new file mode 100755
index 00..420e7daf4c
--- /dev/null
+++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh
@@ -0,0 +1,94 @@
+#!/bin/sh
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Jagan Teki
+#
+# Based on the board/sunxi/mksunxi_fit_atf.sh
+#
+# Script to generate FIT image source for 64-bit puma boards with
+# U-Boot proper, ATF, PMU firmware and devicetree.
+#
+# usage: $0 [ [&2
+ echo "Please read Building section in doc/README.rockchip" >&2
+ BL31=/dev/null
+fi
+
+[ -z "$PMUM0" ] && PMUM0="rk3399m0.bin"
+
+if [ ! -f $PMUM0 ]; then
+ echo "WARNING: PMUM0 file $PMUM0 NOT found, resulting binary is
non-functional" >&2
+ echo "Please read Building section in doc/README.rockchip" >&2
+ PMUM0=/dev/null
+fi
+
+cat << __HEADER_EOF
+/* SPDX-License-Identifier: GPL-2.0+ OR X11 */
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * Minimal dts for a SPL FIT image payload.
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware,
DTB";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ data = /incbin/("u-boot-nodtb.bin");
+ type = "standalone";
+ arch = "arm64";
+
[U-Boot] [PATCH v3 6/6] Kconfig: Add u-boot.itb BUILD_TARGET for Rockchip
Add u-boot.itb BUILD_TARGET for Rockchip platform when SPL_LOAD_FIT is being used. This can get rid of building itb explicitly with 'make u-boot.itb' so, from now all required images will build just by make. Signed-off-by: Jagan Teki --- Kconfig | 2 +- doc/README.rockchip | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/Kconfig b/Kconfig index 91c1082ace..6bcff29659 100644 --- a/Kconfig +++ b/Kconfig @@ -240,7 +240,7 @@ config BUILD_TARGET default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-elf.srec" if RCAR_GEN3 - default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI + default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI) default "u-boot.kwb" if KIRKWOOD default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT help diff --git a/doc/README.rockchip b/doc/README.rockchip index 88a4593392..c4e5f83da7 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -103,7 +103,6 @@ For example: => cd /path/to/u-boot => make nanopi-neo4-rk3399_defconfig => make - => make u-boot.itb - Get the rkbin @@ -170,7 +169,6 @@ For example: => cd /path/to/u-boot => make orangepi-rk3399_defconfig => make - => make u-boot.itb (Get spl/u-boot-spl-dtb.bin, u-boot.itb images and some boards would get spl/u-boot-spl.bin since it doesn't enable CONFIG_SPL_OF_CONTROL) -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/6] travis.yml: Add pyelftools install entry
Currently rockchip platform is using explicit 'make u-boot.itb' for building u-boot.itb but if we enable CONFIG_BUILD_TARGET as 'u-boot.itb' then the resulting u-boot.itb directly will create by make. But, that indeed make travis build fail since it require python-pyelftools host package. So add pyelftools install entry as 'pip install pyelftools', this would create pyelftools on travis host which are required to build rk3399 itb. Signed-off-by: Jagan Teki --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index 8bd49ef1a5..94b795ef21 100644 --- a/.travis.yml +++ b/.travis.yml @@ -50,6 +50,7 @@ install: - . /tmp/venv/bin/activate - pip install pytest==2.8.7 - pip install python-subunit + - pip install pyelftools - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - mkdir ~/grub2-arm -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 2/6] Makefile: clean bl31_*.bin
Rockchip platform has its python script that would generate various bl31_*bin for creating u-boot.itb file by taking bl31.elf as input. These bl31_*.bin files are generated in u-boot root directory and have no rule to clean it up. so add support for it by adding in command entry of clean target in Makefile. Signed-off-by: Jagan Teki --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index de11446ed3..64c7976f7e 100644 --- a/Makefile +++ b/Makefile @@ -1814,7 +1814,7 @@ clean: $(clean-dirs) -o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \ -o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \ -type f -print | xargs rm -f \ - image.map + bl31_*.bin image.map # mrproper - Delete all generated files, including .config # -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/6] Makefile: clean image.map
binman tools for creating single image build will create image.map at the end, which has information about binman image node details. current u-boot, is unable to clean this image.map so add a command entry in clean target in Makefile. Signed-off-by: Jagan Teki --- Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d6a6ef19ab..de11446ed3 100644 --- a/Makefile +++ b/Makefile @@ -1813,7 +1813,8 @@ clean: $(clean-dirs) -o -name modules.builtin -o -name '.tmp_*.o.*' \ -o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \ -o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \ - -type f -print | xargs rm -f + -type f -print | xargs rm -f \ + image.map # mrproper - Delete all generated files, including .config # -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 0/6] rockchip: rk3399: Make u-boot.itb as BUILD_TARGET
RK3399 TPL changes are merged recently which I was thinking of waiting for next MW. so this series skip binman changes from previous version[1] and have only BUILD_TARGET changes. BINMAN changes would need another rework, where we need to consider the TPL image as well and that would send separately. CHanges for v3: - skip binman changes - rebase on u-boot-rockchip/master [1] https://patchwork.ozlabs.org/cover/1092198/ Jagan Teki (6): Makefile: clean image.map Makefile: clean bl31_*.bin travis.yml: Add pyelftools install entry rockchip: rk3399: Get bl31.elf via BL31 board: puma: Get bl31.bin via BL31 and rk3399m0.bin via PMUM0 Kconfig: Add u-boot.itb BUILD_TARGET for Rockchip .travis.yml | 1 + Kconfig | 2 +- Makefile | 3 +- arch/arm/mach-rockchip/make_fit_atf.py| 11 ++- .../puma_rk3399/fit_spl_atf.its | 58 .../puma_rk3399/fit_spl_atf.sh| 94 +++ configs/puma-rk3399_defconfig | 2 +- doc/README.rockchip | 14 ++- 8 files changed, 115 insertions(+), 70 deletions(-) delete mode 100644 board/theobroma-systems/puma_rk3399/fit_spl_atf.its create mode 100755 board/theobroma-systems/puma_rk3399/fit_spl_atf.sh -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v7 08/11] rockchip: rk3399: Add Nanopi NEO4 board support
Add initial support for Nanopi NEO4 board.
Specification
- Rockchip RK3399
- 1GB DDR3-1866
- SD card slot
- eMMC Socket
- RTL8211E 1Gbps
- AP6212 WiFI/BT
- HDMI In/Out, DP, MIPI CSI
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 5V/3A
Commit details of rk3399-nanopi-neo4.dts sync from Linux:
"arm64: dts: rockchip: Add Nanopi NEO4 initial support"
(sha1: 092470b537f19788d957aed12d835a179b606014)
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 +++
arch/arm/dts/rk3399-nanopi-neo4.dts | 50 +
board/rockchip/evb_rk3399/MAINTAINERS | 6 +++
configs/nanopi-neo4-rk3399_defconfig| 59 +
5 files changed, 122 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts
create mode 100644 configs/nanopi-neo4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index adaca524c3..529c506b4d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-gru-bob.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
+ rk3399-nanopi-neo4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
new file mode 100644
index 00..7d22528f49
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopi-neo4.dts
b/arch/arm/dts/rk3399-nanopi-neo4.dts
new file mode 100644
index 00..195410b089
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-neo4.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Amarula Solutions B.V.
+ * Author: Jagan Teki
+ */
+
+/dts-v1/;
+
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi NEO4";
+ compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_core: vcc5v0-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_core";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_5v>;
+ };
+
+ vcc5v0_usb1: vcc5v0-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_sys>;
+ };
+};
+
+_sys {
+ vin-supply = <_core>;
+};
+
+_host {
+ phy-supply = <_usb1>;
+};
+
+_typec {
+ regulator-always-on;
+ vin-supply = <_5v>;
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index f55c92f80c..1f51f65160 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -18,6 +18,12 @@ S: Maintained
F: configs/nanopi-m4-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+NANOPI-NEO4
+M: Jagan Teki
+S: Maintained
+F: configs/nanopi-neo4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+
ORANGEPI-RK3399
M: Jagan Teki
S: Maintained
diff --git a/configs/nanopi-neo4-rk3399_defconfig
b/configs/nanopi-neo4-rk3399_defconfig
new file mode 100644
index 00..188656a2b4
--- /dev/null
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_DEBUG_UART_BASE=0xFF1A
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
[U-Boot] [PATCH v7 07/11] rockchip: rk3399: Add Nanopc T4 board support
Add initial support for Nanopc T4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- 16GB eMMC
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: Add NanoPC-T4 IR receiver"
(sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3)
Tested-by: Daniel Gröber
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 ++
arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++
board/rockchip/evb_rk3399/MAINTAINERS | 6 ++
configs/nanopc-t4-rk3399_defconfig| 59 +++
5 files changed, 164 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts
create mode 100644 configs/nanopc-t4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2a5bfd3fb5..adaca524c3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
new file mode 100644
index 00..17201bcf41
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts
b/arch/arm/dts/rk3399-nanopc-t4.dts
new file mode 100644
index 00..84433cf02b
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopc-t4.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPC-T4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPC-T4";
+ compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
+
+ vcc12v0_sys: vcc12v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1200>;
+ regulator-min-microvolt = <1200>;
+ regulator-name = "vcc12v0_sys";
+ };
+
+ vcc5v0_host0: vcc5v0-host0 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc5v0_host0";
+ vin-supply = <_sys>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = < 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "Recovery";
+ linux,code = ;
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = < RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_rx>;
+ };
+};
+
+ {
+ ir {
+ ir_rx: ir-rx {
+ /* external pullup to VCC3V3_SYS, despite being 1.8V :/
*/
+ rockchip,pins = <0 RK_PA6 RK_FUNC_1 _pull_none>;
+ };
+ };
+};
+
+ {
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+_host {
+ phy-supply = <_host0>;
+};
+
+_host {
+ phy-supply = <_host0>;
+};
+
+_sys {
+ vin-supply = <_sys>;
+};
+
+_sys {
+ vin-supply = <_sys>;
+};
+
+_typec {
+ enable-active-high;
+ gpios = < RK_PD2 GPIO_ACTIVE_HIGH>;
+ vin-supply = <_sys>;
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index ae43805a6a..f55c92f80c 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h
F: configs/evb-rk3399_defconfig
F: configs/firefly-rk3399_defconfig
+NANOPC-T4
+M: Jagan Teki
+S: Maintained
+F: configs/nanopc-t4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
+
NANOPI-M4
M: Jagan Teki
S: Maintained
diff --git a/configs/nanopc-t4-rk3399_defconfig
b/configs/nanopc-t4-rk3399_defconfig
new file mode 100644
index 00..d9f2137b4c
--- /dev/null
+++
[U-Boot] [PATCH v7 05/11] rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1
sdmmc cd pin is configured as RK_FUNC_GPIO which is wrong and
indeed failed to detect the sdcard on the board with below error
Card did not respond to voltage select!
So, fix it by replacing RK_FUNC_GPIO with RK_FUNC_1 which
is already defined in rk3399.dts so make use of same like
other boards.
Add these changes in -u-boot.dtsi to make Linux sync easy for future
changes.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
new file mode 100644
index 00..20db99c0b8
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_bus4 _clk _cmd _cd>;
+};
--
2.18.0.321.gffc6fa0e3
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v7 06/11] rockchip: rk3399: Add Nanopi M4 board support
Add initial support for Nanopi M4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- eMMC socket
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- USB 3.0 x4
- USB Type C power and data
- GPIO1, GPIO2 expansion ports
- DC5V/3A
Commit details of rk3399-nanopi-m4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: Refine nanopi4 differences"
(sha1: c62ffaf5026d0b7633e62b2cea8450b5543c349a)
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Reviewed-by: Philipp Tomsich
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 +++
arch/arm/dts/rk3399-nanopi-m4.dts | 66 +++
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 2 +
board/rockchip/evb_rk3399/MAINTAINERS | 6 +++
configs/nanopi-m4-rk3399_defconfig| 59
6 files changed, 141 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts
create mode 100644 configs/nanopi-m4-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 35cbbfabd0..2a5bfd3fb5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-nanopi-m4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
diff --git a/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
new file mode 100644
index 00..17201bcf41
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopi-m4.dts
b/arch/arm/dts/rk3399-nanopi-m4.dts
new file mode 100644
index 00..60358ab8c7
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-m4.dts
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPi M4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi M4";
+ compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_core: vcc5v0-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_core";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_5v>;
+ };
+
+ vcc5v0_usb1: vcc5v0-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_sys>;
+ };
+
+ vcc5v0_usb2: vcc5v0-usb2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb2";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_sys>;
+ };
+};
+
+_sys {
+ vin-supply = <_core>;
+};
+
+_host {
+ phy-supply = <_usb1>;
+};
+
+_host {
+ phy-supply = <_usb2>;
+};
+
+_typec {
+ regulator-always-on;
+ vin-supply = <_5v>;
+};
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
index 20db99c0b8..05708b6f55 100644
--- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2019 Jagan Teki
*/
+#include "rk3399-u-boot.dtsi"
+
{
pinctrl-names = "default";
pinctrl-0 = <_bus4 _clk _cmd _cd>;
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS
b/board/rockchip/evb_rk3399/MAINTAINERS
index 07ee8ce92c..ae43805a6a 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h
F: configs/evb-rk3399_defconfig
F: configs/firefly-rk3399_defconfig
+NANOPI-M4
+M: Jagan Teki
+S: Maintained
+F: configs/nanopi-m4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+
ORANGEPI-RK3399
M: Jagan Teki
S: Maintained
diff --git a/configs/nanopi-m4-rk3399_defconfig
b/configs/nanopi-m4-rk3399_defconfig
new file mode 100644
index 00..c2832788f0
--- /dev/null
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
[U-Boot] [PATCH v7 03/11] arm: rockchip: rk3399: Move common configs in Kconfig
Few SPL and U-Boot proper configs are common to all rk3399 target defconfigs, move them and select it from platform kconfig. Moved configs: - SPL_ATF - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - SPL_LOAD_FIT - SPL_CLK if SPL - SPL_PINCTRL if SPL - SPL_RAM if SPL - SPL_REGMAP if SPL - SPL_SYSCON if SPL - CLK - FIT - PINCTRL - RAM - REGMAP - SYSCON - DM_PMIC - DM_REGULATOR_FIXED Signed-off-by: Jagan Teki --- arch/arm/mach-rockchip/Kconfig| 16 configs/chromebook_bob_defconfig | 16 configs/evb-rk3399_defconfig | 16 configs/ficus-rk3399_defconfig| 16 configs/firefly-rk3399_defconfig | 16 configs/orangepi-rk3399_defconfig | 16 configs/puma-rk3399_defconfig | 16 configs/rock960-rk3399_defconfig | 16 8 files changed, 16 insertions(+), 112 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f5c3329750..c05e3c3f48 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -156,11 +156,27 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SUPPORT_TPL select SPL + select SPL_ATF + select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_LOAD_FIT + select SPL_CLK if SPL + select SPL_PINCTRL if SPL + select SPL_RAM if SPL + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT + select CLK + select FIT + select PINCTRL + select RAM + select REGMAP + select SYSCON + select DM_PMIC + select DM_REGULATOR_FIXED select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER imply TPL_SERIAL_SUPPORT diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index bd836acad5..e61e27c992 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -17,8 +17,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -26,8 +24,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -46,12 +42,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -71,16 +61,10 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 94963e4280..f10502cb0e 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x8 CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y
[U-Boot] [PATCH v7 02/11] Kconfig: Add default SPL_FIT_GENERATOR for rockchip
Add default SPL_FIT_GENERATOR py script for rockchip platforms if specific target enabled SPL_LOAD_FIT. So, this would help get rid of explicitly mentioning the default SPL FIT generator in defconfigs. however some targets, like puma_rk3399 still require their own FIT generator so in those cases the default will override with defconfig defined generator. Reviewed-by: Paul Kocialkowski Signed-off-by: Jagan Teki --- Kconfig | 1 + configs/chromebook_bob_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig| 1 - configs/firefly-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - 7 files changed, 1 insertion(+), 6 deletions(-) diff --git a/Kconfig b/Kconfig index 7a5491bd67..91c1082ace 100644 --- a/Kconfig +++ b/Kconfig @@ -435,6 +435,7 @@ config SPL_FIT_GENERATOR string ".its file generator script for U-Boot FIT image" depends on SPL_FIT default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI + default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP help Specifies a (platform specific) script file to generate the FIT source file used to build the U-Boot FIT image file. This gets diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index ce07a7f0ff..bd836acad5 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 5bb910e8d4..94963e4280 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 79da86b32f..926d244fbe 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 301b27e3a4..5016fb8993 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index ba13976cc6..22ddd8dce3 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 8d490be18c..48d14ef7d8 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v7 01/11] rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2
To make successful build with dts(i) files syncing from Linux 5.1-rc2
the rk3399.dtsi would require pwm2_pin_pull_down.
So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this
node is strictly not part of any commit alone, I have mentioned
Linux 5.1-rc2 tag for future reference of where would this sync
coming from.
Signed-off-by: Jagan Teki
Reviewed-by: Paul Kocialkowski
---
arch/arm/dts/rk3399.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index b53e41b4dc..b73442ee34 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -2495,6 +2495,11 @@
rockchip,pins =
<1 RK_PC3 RK_FUNC_1 _pull_none>;
};
+
+ pwm2_pin_pull_down: pwm2-pin-pull-down {
+ rockchip,pins =
+ <1 RK_PC3 RK_FUNC_1 _pull_down>;
+ };
};
pwm3a {
--
2.18.0.321.gffc6fa0e3
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v7 04/11] rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.
Linux commit details about the rk3399-nanopi4.dtsi sync:
"arm64: dts: rockchip: Add nanopi4 bluetooth"
(sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)
Signed-off-by: Jagan Teki
Reviewed-by: Paul Kocialkowski
---
arch/arm/dts/rk3399-nanopi4.dtsi | 703 +++
1 file changed, 703 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi
diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi
new file mode 100644
index 00..d325e11728
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi4.dtsi
@@ -0,0 +1,703 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * RK3399-based FriendlyElec boards device tree source
+ *
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc3v3_sys";
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-name = "vcc5v0_sys";
+ vin-supply = <_5v>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc1v8_s3";
+ vin-supply = <_1v8>;
+ };
+
+ vcc3v0_sd: vcc3v0-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pwr_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ regulator-name = "vcc3v0_sd";
+ vin-supply = <_sys>;
+ };
+
+ vbus_typec: vbus-typec {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-name = "vbus_typec";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <_key>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_gpio>;
+
+ status {
+ gpios = < RK_PB5 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = < 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_on_h>;
+ reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+_b0 {
+ cpu-supply = <_cpu_b>;
+};
+
+_b1 {
+ cpu-supply = <_cpu_b>;
+};
+
+_l0 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l1 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l2 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l3 {
+ cpu-supply = <_cpu_l>;
+};
+
+_phy {
+ status = "okay";
+};
+
+ {
+ assigned-clock-parents = <_gmac>;
+ assigned-clocks = < SCLK_RMII_SRC>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ phy-mode = "rgmii";
+ phy-supply = <_s3>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ snps,reset-gpio = < RK_PB7
[U-Boot] [PATCH v7 09/11] rockchip: rk3399: Add Rockpro64 board support
Add initial support for Rockpro64 board.
Specification
- Rockchip RK3399
- 2/4GB Dual-Channel LPDDR3
- SD card slot
- eMMC socket
- 128Mb SPI Flash
- Gigabit ethernet
- PCIe 4X slot
- WiFI/BT module socket
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-rockpro64.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: rockpro64 dts add usb regulator"
(sha1: 6db644c79c8d45d73b56bc389aebd85fc3679beb)
'Akash' has sent an initial patch before, so I keep him as board
maintainer and I'm co-maintainer based on our conversation.
Signed-off-by: Akash Gajjar
Signed-off-by: Jagan Teki
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 +
arch/arm/dts/rk3399-rockpro64.dts | 712 ++
board/rockchip/evb_rk3399/MAINTAINERS | 7 +
configs/rockpro64-rk3399_defconfig| 59 ++
5 files changed, 785 insertions(+)
create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-rockpro64.dts
create mode 100644 configs/rockpro64-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 529c506b4d..8522f01aca 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -114,6 +114,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-rock960.dtb \
+ rk3399-rockpro64.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
new file mode 100644
index 00..7bddc3acdb
--- /dev/null
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-rockpro64.dts
b/arch/arm/dts/rk3399-rockpro64.dts
new file mode 100644
index 00..1f2394e058
--- /dev/null
+++ b/arch/arm/dts/rk3399-rockpro64.dts
@@ -0,0 +1,712 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2018 Akash Gajjar
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Pine64 RockPro64";
+ compatible = "pine64,rockpro64", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led_gpio>, <_led_gpio>;
+
+ work-led {
+ label = "work";
+ default-state = "on";
+ gpios = < RK_PB3 GPIO_ACTIVE_HIGH>;
+ };
+
+ diy-led {
+ label = "diy";
+ default-state = "off";
+ gpios = < RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = < 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <_enable_h>;
+
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+
[U-Boot] [PATCH v7 00/11] rockchip: Add new rk3399 boards
This is v7 patchset for New rk3399 boards support wrt previous version[1] Unfortunately initial version of creating rk3399-u-boot.dtsi and orangepi rk3399 changes are merged, so this is rework on top of u-boot-rockchip/master. Overall this series add support below rk3399 boards - NanoPI M4 - NanoPC T4 - NanoPI NEO4 - Orangepi RK3399 - Rock PI 4 - Rockpro64 All the respective dts(i) files are synced from Linux 5.1-rc2 and few dts(i) from linux-next. SoC u-boot specific dtsi rk3399-u-boot.dtsi changes are part of another series [3]. Out of all above boards Rockpor64, Rock-PI and Nanopi NEO4 would support booting via Rockchip miniloader as of now. For booting the same with SPL NEO4 would require dynamic dram timing detection and rest require LPDDR4 code. There is WIP[2] for these dependencies and this would require big chunk of changes will effect all the rk3399 boards, so I'm planning to mark it for next MW. Changes for v7: - rebase on top of u-boot-rockchip/master - add SPL_TEXT_BASE on each board defconfig - rebase on required changes Changes for v6: - Include Nanopc T4 support patch - drop rk3399-u-boot.dtsi patch since it is send separately. Changes for v5: - Make all changes related to move sdmmc, spi1 u-boot,dm-pre-reloc properties into all rk3399 dts(i) files. Changes for v4: - don't include existing dts(i) sdmmc, u-boot,dm-pre-reloc into rk3399-u-boot.dtsi Changes for v3: - drop NanoPC T4 for now, since board is yet to receive. - add Rock PI-4 board. - add separate -u-boot.dtsi file for nanopi4 sdram changes. - collect Paul, Philipp and Kever Reviewed-by tags Travis-CI: https://travis-ci.org/openedev/u-boot-amarula/builds/529284236 [1] https://patchwork.ozlabs.org/cover/1091914/ [2] https://github.com/amarula/u-boot-amarula/tree/rockdev-lpddr4 [3] https://patchwork.ozlabs.org/cover/1091909/ Any inputs? Jagan. Jagan Teki (11): rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2 Kconfig: Add default SPL_FIT_GENERATOR for rockchip arm: rockchip: rk3399: Move common configs in Kconfig rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1 rockchip: rk3399: Add Nanopi M4 board support rockchip: rk3399: Add Nanopc T4 board support rockchip: rk3399: Add Nanopi NEO4 board support rockchip: rk3399: Add Rockpro64 board support rockchip: rk3399: Add Rock PI 4 support doc: rockchip: Add global doc for rk3399 build/flash Kconfig | 1 + arch/arm/dts/Makefile | 5 + arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 + arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++ arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 + arch/arm/dts/rk3399-nanopi-m4.dts | 66 ++ arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-nanopi-neo4.dts | 50 ++ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 11 + arch/arm/dts/rk3399-nanopi4.dtsi| 703 +++ arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rock-pi-4.dts | 606 + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rockpro64.dts | 712 arch/arm/dts/rk3399.dtsi| 5 + arch/arm/mach-rockchip/Kconfig | 16 + board/rockchip/evb_rk3399/MAINTAINERS | 32 + configs/chromebook_bob_defconfig| 17 - configs/evb-rk3399_defconfig| 17 - configs/ficus-rk3399_defconfig | 17 - configs/firefly-rk3399_defconfig| 17 - configs/nanopc-t4-rk3399_defconfig | 59 ++ configs/nanopi-m4-rk3399_defconfig | 59 ++ configs/nanopi-neo4-rk3399_defconfig| 59 ++ configs/orangepi-rk3399_defconfig | 17 - configs/puma-rk3399_defconfig | 16 - configs/rock-pi-4-rk3399_defconfig | 59 ++ configs/rock960-rk3399_defconfig| 17 - configs/rockpro64-rk3399_defconfig | 59 ++ doc/README.rockchip | 233 ++- 30 files changed, 2857 insertions(+), 119 deletions(-) create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi create mode 100644 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock-pi-4.dts create mode 100644 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rockpro64.dts create mode 100644 configs/nanopc-t4-rk3399_defconfig create mode 100644 configs/nanopi-m4-rk3399_defconfig
[U-Boot] [PATCH] rockchip: rk3399: orangepi: Add SPL_TEXT_BASE
CONFIG_SPL_TEXT_BASE was available in configs/rk3399_common.h when the OrangePI rk3399 board supported during first version patch. But, later below change which move this config into Kconfig and same has been merged in mainline tree. "configs: move CONFIG_SPL_TEXT_BASE to Kconfig" (sha1: f89d6133eef2e068f9c33853b6584d7fcbfa9d2e) Unfortunately, the maintainer applied the initial version patch, instead of looking for next version changes. Fix it by adding SPL_TEXT_BASE in orangepi-rk3399 defconfig. Signed-off-by: Jagan Teki --- configs/orangepi-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index cdccf221b5..ba13976cc6 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_ATF=y -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v7 0/4] arm64: rockchip: dts: Add rk3399 -u-boot.dtsi files
Unfortunately initial version of creating rk3399-u-boot.dtsi has been merged, so this series is rework of previous v6 set[1] on top of u-boot-rockchip/master All these changes are updating rk3399-u-boot.dtsi and rk3399 board -u-boot.dtsi files and u-boot specific dts changes like - sdram dtsi - sdmmc, u-boot,dm-pre-reloc - spi1, u-boot,dm-pre-reloc Changes for v7: - rebase on u-boot-rockchip/master - recreate patches based on v1 series merge - add patch for dtb build based on SoC type Changes for v6: - spilt the existing patch[2] into multiple patches and send as a separate series. [2] https://patchwork.ozlabs.org/patch/1091720/ [1] https://patchwork.ozlabs.org/cover/1091909/ Any inputs? Jagan. Jagan Teki (4): dts: Makefile: Build rockchip dtbs based on SoC types arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi files rockchip: dts: rk3399-u-boot: Add u-boot,dm-pre-reloc for spi1 arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsi arch/arm/dts/Makefile | 35 ++--- arch/arm/dts/rk3399-evb-u-boot.dtsi | 7 + arch/arm/dts/rk3399-evb.dts | 1 - arch/arm/dts/rk3399-ficus-u-boot.dtsi | 6 + arch/arm/dts/rk3399-ficus.dts | 1 - arch/arm/dts/rk3399-firefly-u-boot.dtsi | 7 + arch/arm/dts/rk3399-firefly.dts | 1 - arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 7 + arch/arm/dts/rk3399-gru-bob.dts | 1 - arch/arm/dts/rk3399-gru-u-boot.dtsi | 6 + arch/arm/dts/rk3399-gru.dtsi| 1 - arch/arm/dts/rk3399-puma-ddr1600.dts| 1 + arch/arm/dts/rk3399-puma.dtsi | 2 -- arch/arm/dts/rk3399-rock960-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rock960.dts | 1 - arch/arm/dts/rk3399-u-boot.dtsi | 4 +++ 16 files changed, 70 insertions(+), 17 deletions(-) create mode 100644 arch/arm/dts/rk3399-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-ficus-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-firefly-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-gru-bob-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-gru-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock960-u-boot.dtsi -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
