Re: [U-Boot] [PATCH] arm: ti: boot: Increase system partition size
On 11/12/18 9:50 PM, Sam Protsenko wrote: > Android code base is growing, so since Android "Pie" the size of > system.img grew up to be about 740 MiB. Let's increase system.img to > 1 GiB to accommodate for those changes and leave some margin for future > changes. We don't want to make it more than 1 GiB, because we should > keep userdata partition big enough (for user files, like media etc.), > and eMMC size on BeagleBoard-X15 is only 3.5 GiB. > > Signed-off-by: Sam Protsenko Reviewed-by: Lokesh Vutla Thanks and regards, Lokesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: ti: boot: Remove legacy Android partitions
On 05/01/19 1:39 AM, Sam Protsenko wrote: > Remove unused Android partitions: > - efs, crypto, cache: we don't use it anymore (images are not built > in AOSP > - ipu1, ipu2: IPU firmware is now a part of vendor image and doesn't > reside as a separate partition > > While at it, rename "reserved" partition to "uboot-env", as it's > actually stores U-Boot environment. > > Signed-off-by: Sam Protsenko Reviewed-by: Lokesh Vutla Thanks and regards, Lokesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] env: ti: Increase boot partition
On 02/07/19 11:26 PM, Sam Protsenko wrote: > linux-mainline with multi_v7_defconfig + Android configs takes more > space than regular TI Android kernel. Let's increase boot partition > twice, so that boot_fit.img (with new zImage in it) can fit into "boot" > partition. > > Signed-off-by: Sam Protsenko Reviewed-by: Lokesh Vutla Thanks and regards, Lokesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] arm: am57xx: Allow bootm to load larger kernels
On 02/07/19 11:26 PM, Sam Protsenko wrote: > linux-mainline with multi_v7_defconfig + Android configs takes more > space than regular TI Android kernel and bootm will fail to load it. > Let's increase max kernel size up to 64 MiB to make it possible to run > such kernel. > > Signed-off-by: Sam Protsenko Reviewed-by: Lokesh Vutla Thanks and regards, Lokesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: mach-keystone: Use appended original image size in image processing
On 13/07/19 1:03 AM, Andrew F. Davis wrote:
> When an image is signed/encrypted on K2 devices the image may get padded
> to meet alignment requirements for the signature/encryption type. The
> original size is appended as 4 bytes little-endian to the end of the
> final image.
>
> Normally the trailing extra bytes are ignored and so restoring the
> exact original size is not important. In the case of initrd the
> original size is important as the kernel uses it to look for
> additional filesystem data and can do the wrong thing when the
> size is not correct.
>
> Read off the original size and report it back from the image post
> processing stage.
>
> Signed-off-by: Andrew F. Davis
> ---
> arch/arm/mach-keystone/mon.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
> index 51af028590..b7ffe277c1 100644
> --- a/arch/arm/mach-keystone/mon.c
> +++ b/arch/arm/mach-keystone/mon.c
> @@ -105,6 +105,7 @@ void board_fit_image_post_process(void **p_image, size_t
> *p_size)
> {
> int result = 0;
> void *image = *p_image;
> + uint8_t *size_image = image + (*p_size - 4);
>
> if (strncmp(image + KS2_HS_SEC_TAG_OFFSET, "KEYS", 4)) {
> printf("No signature found in image!\n");
> @@ -120,9 +121,12 @@ void board_fit_image_post_process(void **p_image, size_t
> *p_size)
> /*
>* Overwrite the image headers after authentication
>* and decryption. Update size to reflect removal
> - * of header.
> + * of header and restore original file size.
>*/
> - *p_size -= KS2_HS_SEC_HEADER_LEN;
> + *p_size = *(size_image+0) << 0 |
> + *(size_image+1) << 8 |
> + *(size_image+2) << 16 |
> + *(size_image+3) << 24;
Instead use get_unaligned_le32(size)?
Thanks and regards,
Lokesh
> memcpy(image, image + KS2_HS_SEC_HEADER_LEN, *p_size);
>
> /*
>
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Re: [U-Boot] [PATCH v2] net/macb: increase RX buffer size for GEM
On Tue, Jul 16, 2019 at 2:25 AM Joe Hershberger wrote: > > On Sun, Jul 14, 2019 at 10:25 AM Ramon Fried wrote: > > > > Macb Ethernet controller requires a RX buffer of 128 bytes. It is > > highly sub-optimal for Gigabit-capable GEM that is able to use > > a bigger DMA buffer. Change this constant and associated macros > > with data stored in the private structure. > > RX DMA buffer size has to be multiple of 64 bytes as indicated in > > DMA Configuration Register specification. > > > > Signed-off-by: Ramon Fried > > Is there a dependency here that you don't mention? This doesn't apply cleanly. > It should be applied on my earlier macb patches. Thanks, Ramon > Thanks, > -Joe > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] net: macb: sync header definitions as taken from Linux
On Mon, Jul 15, 2019 at 11:48 PM Joe Hershberger wrote: > > On Mon, Jul 15, 2019 at 3:26 PM Ramon Fried wrote: > > > > On Mon, Jul 15, 2019 at 11:19 PM Ramon Fried wrote: > > > > > > On Mon, Jul 15, 2019 at 9:31 PM Joe Hershberger > > > wrote: > > > > > > > > On Tue, Jun 11, 2019 at 10:51 AM Ramon Fried > > > > wrote: > > > > > > > > > > Few registers and bits were added by Cadence and > > > > > they were not updated in the headers. > > > > > Take the latest definitions as defined in Linux > > > > > header (5.1) that also includes some comments > > > > > about existing registers. > > > > > > > > > > One register was improperly named (UR), fix that. > > > > > > > > This is breaking the build. "UR" is still referred to in > > > > drivers/net/macb.c line 805. > > > > > > > > Did you build test this? > > > Well of course, but apparently I screwed this one in rebasing, prior to > > > submit. > > > Didn't run buildman afterwards. sorry. > > > Will issue a revised patchset. > > > Sorry. > > > Ramon. > > Actually, now that I look at this. it looks fine. the patch replaces > > the line you mentioned: > > https://patchwork.ozlabs.org/patch/1114041/ > > Can take a look ? > > It addresses some of them, but not the ones a few lines below. Just cherry-picked to a brand new master branch. there are no UR left on the file and it compiles correctly. Did you apply something else beforehand ? > > > > > > > > > > > > > > > Signed-off-by: Ramon Fried > > ___ > > U-Boot mailing list > > U-Boot@lists.denx.de > > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3] spl: kconfig: separate sysreset and firmware drivers from misc
On 16/07/19 1:06 AM, Simon Goldschmidt wrote: > This adds separate kconfig options for drivers/sysreset and > drivers/firmware. > > Up to now, CONFIG_SPL_DRIVERS_MISC_SUPPORT added drivers/misc to SPL > build but also added drivers/firmware and drivers/sysreset at the same > time. > > Since that is confusing, this patch uses CONFIG_SPL_SYSRESET for > drivers/sysreset and adds CONFIG_SPL_FIRMWARE for > drivers/firmware (and accordingly for the TPL options). > > CONFIG_SPL_DRIVERS_MISC_SUPPORT stays for including drivers/misc into > the SPL build (and accordingly for TPL) since there are boards using > non-DM (non UCLASS_MISC) files from drivers/misc. Such boards don't > have CONFIG_SPL_MISC enabled, so cannot use this to include > drivers/misc into the SPL build. > > Signed-off-by: Simon Goldschmidt > --- > > Changes in v3: > - Revert to keeping CONFIG_SPL_DRIVERS_MISC_SUPPORT as there are boards > that need to include drivers/misc without UCLASS_MISC being enabled > - Only CONFIG_SPL_FIRMWARE is added as new config symbol. To ensure no > arch Kconfig files need to be changed, add dependencies to ensure this > is enabled where required. > > Changes in v2: > - adapt config names to match the non-SPL config options: > - changed CONFIG_SPL_SYSRESET_SUPPORT to CONFIG_SPL_SYSRESET > - changed CONFIG_SPL_DRIVERS_FIRMWARE_SUPPORT to CONFIG_SPL_FIRMWARE > - changed CONFIG_SPL_DRIVERS_MISC_SUPPORT to CONFIG_SPL_MISC > > configs/evb-rk3036_defconfig | 1 + > configs/kylin-rk3036_defconfig | 1 + > configs/sandbox_spl_defconfig | 1 + > drivers/Makefile | 7 ++- > drivers/firmware/Kconfig | 7 ++- > drivers/sysreset/Kconfig | 1 + > 6 files changed, 16 insertions(+), 2 deletions(-) > > diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig > index 5e6bb54551..0eb7384340 100644 > --- a/configs/evb-rk3036_defconfig > +++ b/configs/evb-rk3036_defconfig > @@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y > CONFIG_SF_DEFAULT_SPEED=2000 > CONFIG_PINCTRL=y > # CONFIG_SPL_DM_SERIAL is not set > +# CONFIG_SPL_SYSRESET is not set > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_SYSRESET=y > CONFIG_USB=y > diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig > index 921af0d476..a76ae9d326 100644 > --- a/configs/kylin-rk3036_defconfig > +++ b/configs/kylin-rk3036_defconfig > @@ -49,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=2000 > CONFIG_PINCTRL=y > CONFIG_DM_REGULATOR_FIXED=y > # CONFIG_SPL_DM_SERIAL is not set > +# CONFIG_SPL_SYSRESET is not set > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_SYSRESET=y > CONFIG_USB=y > diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig > index 27034cfaa9..5b7dae9be6 100644 > --- a/configs/sandbox_spl_defconfig > +++ b/configs/sandbox_spl_defconfig > @@ -3,6 +3,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y > CONFIG_SPL_LIBGENERIC_SUPPORT=y > CONFIG_SPL_SERIAL_SUPPORT=y > CONFIG_SPL_DRIVERS_MISC_SUPPORT=y > +CONFIG_SPL_FIRMWARE=y > CONFIG_NR_DRAM_BANKS=1 > CONFIG_SPL=y > CONFIG_BOOTSTAGE_STASH_ADDR=0x0 > diff --git a/drivers/Makefile b/drivers/Makefile > index 603aa98590..1f225bc2ca 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -4,7 +4,6 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ > obj-$(CONFIG_$(SPL_TPL_)DM) += core/ > obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ > obj-$(CONFIG_$(SPL_TPL_)GPIO_SUPPORT) += gpio/ > -obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ why can't the following be added instead of adding SPL and TPL options separately? obj-$(CONFIG_$(SPL_TPL_)FIRMWARE) += firmware/ obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/ Thanks and regards, Lokesh > obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/ > obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ > obj-$(CONFIG_$(SPL_TPL_)LED) += led/ > @@ -58,6 +57,9 @@ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ > obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/ > obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/ > obj-$(CONFIG_SPL_THERMAL) += thermal/ > +obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/ > +obj-$(CONFIG_SPL_SYSRESET) += sysreset/ > +obj-$(CONFIG_SPL_FIRMWARE) +=firmware/ > > endif > endif > @@ -65,6 +67,9 @@ endif > ifdef CONFIG_TPL_BUILD > > obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ > +obj-$(CONFIG_TPL_DRIVERS_MISC_SUPPORT) += misc/ > +obj-$(CONFIG_TPL_SYSRESET) += sysreset/ > +obj-$(CONFIG_TPL_FIRMWARE) += firmware/ > > endif > > diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig > index 7d8f161b26..873bc8c796 100644 > --- a/drivers/firmware/Kconfig > +++ b/drivers/firmware/Kconfig > @@ -1,9 +1,13 @@ > config FIRMWARE > bool "Enable Firmware driver support" > > +config SPL_FIRMWARE > + bool "Enable Firmware driver support in SPL" > + depends on FIRMWARE > + > config SPL_ARM_PSCI_FW > bool > - select FIRMWARE > + select SPL_FIRMWARE > > config ARM_PSCI_FW > bool > @@ -13,6 +17,7 @@ config TI_SCI_PROTOCOL > tristate "TI System Control
[U-Boot] [PATCH v4 4/4] doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers
This patch removes SiFive SPI driver and MMC SPI drive from the TODO
list in SiFive FU540 README.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
doc/README.sifive-fu540 | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/doc/README.sifive-fu540 b/doc/README.sifive-fu540
index 33e03dc861..944ba1c8a0 100644
--- a/doc/README.sifive-fu540
+++ b/doc/README.sifive-fu540
@@ -13,9 +13,7 @@ The support for following drivers are already enabled:
3. Cadence MACB ethernet driver for networking support.
TODO:
-1. SPI host driver is still missing.
-2. SPI MMC driver does not compile and needs a re-write using U-Boot DM.
-2. U-Boot expects the serial console device entry to be present under /chosen
+1. U-Boot expects the serial console device entry to be present under /chosen
DT node. Example:
chosen {
stdout-path = "/soc/serial@1001:115200";
--
2.17.1
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[U-Boot] [PATCH v4 3/4] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
From: Bhargav Shah This patch enables SiFive SPI and MMC SPI drivers for the SiFive Unleashed board. Signed-off-by: Bhargav Shah Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- board/sifive/fu540/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index f46437901d..662c379b1b 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -38,6 +38,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply PHY_LIB imply PHY_MSCC imply SIFIVE_SERIAL + imply SPI + imply SIFIVE_SPI + imply MMC + imply MMC_SPI + imply MMC_BROKEN_CD + imply CMD_MMC imply SMP endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 2/4] spi: Add SiFive SPI driver
From: Bhargav Shah This patch adds SiFive SPI driver. The driver is 100% DM driver and it determines input clock using clk framework. The SiFive SPI block is found on SiFive FU540 SOC and is used to access flash and MMC devices on SiFive Unleashed board. This driver implementation is inspired from the Linux SiFive SPI driver available in Linux-5.2 or higher and SiFive FSBL sources. Signed-off-by: Bhargav Shah Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-sifive.c | 361 +++ 3 files changed, 370 insertions(+) create mode 100644 drivers/spi/spi-sifive.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index eb32f082fe..2712bad310 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -224,6 +224,14 @@ config SANDBOX_SPI }; }; +config SIFIVE_SPI + bool "SiFive SPI driver" + help + This driver supports the SiFive SPI IP. If unsure say N. + Enable the SiFive SPI controller driver. + + The SiFive SPI controller driver is found on various SiFive SoCs. + config SPI_SUNXI bool "Allwinner SoC SPI controllers" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8be9a4baa2..09a9d3697e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o +obj-$(CONFIG_SIFIVE_SPI) += spi-sifive.o obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c new file mode 100644 index 00..78eed78650 --- /dev/null +++ b/drivers/spi/spi-sifive.c @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 SiFive, Inc. + * Copyright 2019 Bhargav Shah + * + * SiFive SPI controller driver (master mode only) + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SIFIVE_SPI_MAX_CS 32 + +#define SIFIVE_SPI_DEFAULT_DEPTH 8 +#define SIFIVE_SPI_DEFAULT_BITS8 + +/* register offsets */ +#define SIFIVE_SPI_REG_SCKDIV0x00 /* Serial clock divisor */ +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ +#define SIFIVE_SPI_REG_CSMODE0x18 /* Chip select mode */ +#define SIFIVE_SPI_REG_DELAY00x28 /* Delay control 0 */ +#define SIFIVE_SPI_REG_DELAY10x2c /* Delay control 1 */ +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ +#define SIFIVE_SPI_REG_TXDATA0x48 /* Tx FIFO data */ +#define SIFIVE_SPI_REG_RXDATA0x4c /* Rx FIFO data */ +#define SIFIVE_SPI_REG_TXMARK0x50 /* Tx FIFO watermark */ +#define SIFIVE_SPI_REG_RXMARK0x54 /* Rx FIFO watermark */ +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */ +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */ +#define SIFIVE_SPI_REG_IE0x70 /* Interrupt Enable Register */ +#define SIFIVE_SPI_REG_IP0x74 /* Interrupt Pendings Register */ + +/* sckdiv bits */ +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU + +/* sckmode bits */ +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) +#define SIFIVE_SPI_SCKMODE_POL BIT(1) +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ + SIFIVE_SPI_SCKMODE_POL) + +/* csmode bits */ +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U + +/* delay0 bits */ +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) + +/* delay1 bits */ +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU +#define SIFIVE_SPI_DELAY1_INTERXFR(x)((u32)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) + +/* fmt bits */ +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U +#define SIFIVE_SPI_FMT_PROTO_DUAL1U +#define SIFIVE_SPI_FMT_PROTO_QUAD2U +#define SIFIVE_SPI_FMT_PROTO_MASK3U +#define SIFIVE_SPI_FMT_ENDIANBIT(2) +#define SIFIVE_SPI_FMT_DIR BIT(3) +#define SIFIVE_SPI_FMT_LEN(x)((u32)(x) << 16) +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16) + +/* txdata bits */ +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_TXDATA_FULL BIT(31) +
[U-Boot] [PATCH v4 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags
Most DM based SPI host controller drivers use SPI_XFER_BEGIN and SPI_XFER_END flags to enable/disable slave chip select. This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when MMC command is send at start and pass SPI_XFER_END flag using a dummy transfer (of bitlen = 0) at the end of MMC command. Suggested-by: Jagan Teki Signed-off-by: Anup Patel --- drivers/mmc/mmc_spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index f3d687ae80..350812a04b 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev, cmdo[4] = cmdarg >> 8; cmdo[5] = cmdarg; cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01; - ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0); + ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN); if (ret) return ret; @@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd, } done: + dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + dm_spi_release_bus(dev); return ret; -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 0/4] SiFive SPI MMC Support
This patchset adds: 1. SiFive SPI driver 2. New MMC SPI driver based on DM_MMC and DM_SPI 3. Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board With this patch series, we can now load files from SD card on SiFive Unleashed board. Many thanks to Bhargav for porting SiFive SPI driver and updating MMC SPI driver for us. These patches can be also found in riscv_unleashed_mmc_spi_v4 branch of: https//github.com/avpatel/u-boot.git Changes since v3: - Removed PATCH2, PATCH3, and PATCH4 because these are already merged - Added separate patch to use SPI_XFER_xyz flags in MMC_SPI driver - Use readl/writel directly instead of sifive_spi_read/sifi_spi_write - Use SPI_XFER_xyz flags to enable/disable chipselect - Remove unused callback sifive_spi_cs_info() Changes since v2: - Minor fixes in PATCH1 which adds SiFive SPI driver - Removed CONFIG_MMC_SPI_xyz from scripts/config_whitelist.txt - Removed cmd/mmc_spi and all its refrences as separate patch - Removed DM_SPI and DM_MMC from SiFive FU540 Kconfig Changes since v1: - Make response matching part belongs to mmc_spi_sendcmd() - Match response to zero for SEND_STATUS (CMD13) - Add separate patch for updating SiFive FU540 Documentation Anup Patel (2): mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers Bhargav Shah (2): spi: Add SiFive SPI driver riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers board/sifive/fu540/Kconfig | 6 + doc/README.sifive-fu540| 4 +- drivers/mmc/mmc_spi.c | 4 +- drivers/spi/Kconfig| 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-sifive.c | 361 + 6 files changed, 380 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/spi-sifive.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1] ddr, fsl: add DM_I2C support
add DM_I2C support for this driver.
Signed-off-by: Heiko Schocher
---
Did not fixed checkpatch warning:
CHECK: Prefer kernel type 'u8' over 'uint8_t'
+ uint8_t buf = 0;
Travis build, see:
https://travis-ci.org/hsdenx/u-boot-test/builds/558858904
drivers/ddr/fsl/main.c | 88 --
1 file changed, 77 insertions(+), 11 deletions(-)
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index e1f69a1d25..cb19d0f0ff 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -10,6 +10,7 @@
*/
#include
+#include
#include
#include
#include
@@ -82,17 +83,82 @@ u8
spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
#endif
+#if defined(CONFIG_DM_I2C)
+#define DEV_TYPE struct udevice
+#else
+/* Local udevice */
+struct ludevice {
+ u8 chip;
+};
+
+#define DEV_TYPE struct ludevice
+
+#endif
+
#define SPD_SPA0_ADDRESS 0x36
#define SPD_SPA1_ADDRESS 0x37
-static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr,
+ int alen, uint8_t *buf, int len)
{
int ret;
+
+#ifdef CONFIG_DM_I2C
+ ret = dm_i2c_read(dev, 0, buf, len);
+#else
+ ret = i2c_read(dev->chip, addr, alen, buf, len);
+#endif
+
+ return ret;
+}
+
#ifdef CONFIG_SYS_FSL_DDR4
- uint8_t dummy = 0;
+static int ddr_i2c_dummy_write(unsigned int chip_addr)
+{
+ uint8_t buf = 0;
+
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ CONFIG_SYS_SPD_BUS_NUM);
+ return ret;
+ }
+
+ return dm_i2c_write(dev, 0, buf, 1);
+#else
+ return i2c_write(chip_addr, 0, 1, &buf, 1);
#endif
+ return 0;
+}
+#endif
+
+static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret;
+ DEV_TYPE *dev;
+
+#if defined(CONFIG_DM_I2C)
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ CONFIG_SYS_SPD_BUS_NUM);
+ return;
+ }
+#else /* Non DM I2C support - will be removed */
+ struct ludevice ldev = {
+ .chip = i2c_address,
+ };
+ dev = &ldev;
+
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+#endif
#ifdef CONFIG_SYS_FSL_DDR4
/*
@@ -101,18 +167,18 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8
i2c_address)
* To access the upper 256 bytes, we need to set EE page address to 1
* See Jedec standar No. 21-C for detail
*/
- i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
- ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
+ ddr_i2c_dummy_write(SPD_SPA0_ADDRESS);
+ ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256);
if (!ret) {
- i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
- ret = i2c_read(i2c_address, 0, 1,
- (uchar *)((ulong)spd + 256),
- min(256,
- (int)sizeof(generic_spd_eeprom_t) - 256));
+ ddr_i2c_dummy_write(SPD_SPA1_ADDRESS);
+ ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256),
+ min(256,
+ (int)sizeof(generic_spd_eeprom_t)
+ - 256));
}
#else
- ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
- sizeof(generic_spd_eeprom_t));
+ ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
#endif
if (ret) {
--
2.21.0
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1] pci: add DM based mpc85xx driver
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge
Signed-off-by: Heiko Schocher
---
Travis build, see:
https://travis-ci.org/hsdenx/u-boot-test/builds/558855544
MAINTAINERS | 5 ++
drivers/pci/Kconfig | 7 ++
drivers/pci/Makefile | 1 +
drivers/pci/pci_mpc85xx.c | 132 ++
4 files changed, 145 insertions(+)
create mode 100644 drivers/pci/pci_mpc85xx.c
diff --git a/MAINTAINERS b/MAINTAINERS
index e91684191f..01faa67a6d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -639,6 +639,11 @@ S: Maintained
F: drivers/pci_endpoint/
F: include/pci_ep.h
+PCI MPC85xx
+M: Heiko Schocher
+S: Maintained
+F: drivers/pci/pci_mpc85xx.c
+
POWER
M: Jaehoon Chung
S: Maintained
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 3fe38f7315..88db0067b4 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -68,6 +68,13 @@ config PCIE_FSL
PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
This driver does not support SRIO_PCIE_BOOT feature.
+config PCI_MPC85XX
+ bool "MPC85XX PowerPC PCI support"
+ depends on DM_PCI
+ help
+ Say Y here if you want to enable PCI controller support on FSL
+ PowerPC MPC85xx SoC.
+
config PCI_RCAR_GEN2
bool "Renesas RCar Gen2 PCIe driver"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index b5ebd50c85..929f119fb3 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
+obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c
new file mode 100644
index 00..c0d35f7f2c
--- /dev/null
+++ b/drivers/pci/pci_mpc85xx.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019
+ * Heiko Schocher, DENX Software Engineering, h...@denx.de.
+ *
+ */
+#include
+#include
+#include
+#include
+
+struct mpc85xx_pci_priv {
+ void __iomem*cfg_addr;
+ void __iomem*cfg_data;
+};
+
+static int mpc85xx_pci_dm_read_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong *value,
+ enum pci_size_t size)
+{
+ struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+ u32 addr;
+
+ addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x8000;
+ out_be32(priv->cfg_addr, addr);
+ sync();
+ *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
+
+ return 0;
+}
+
+static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+ u32 addr;
+
+ addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x8000;
+ out_be32(priv->cfg_addr, addr);
+ sync();
+ out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
+
+ return 0;
+}
+
+static int mpc85xx_pci_dm_probe(struct udevice *dev)
+{
+ struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+ struct pci_region *io;
+ struct pci_region *mem;
+ struct pci_region *pre;
+ int ret;
+ ccsr_pcix_t *pcix;
+
+ ret = pci_get_regions(dev, &io, &mem, &pre);
+ if (ret != 2) {
+ printf("%s: wrong count of regions %d only 2 allowed\n",
+ __func__, ret);
+ return -EINVAL;
+ }
+
+ pcix = priv->cfg_addr;
+ /* BAR 1: memory */
+ out_be32(&pcix->potar1, (mem->bus_start >> 12) & 0x000f);
+ out_be32(&pcix->potear1, 0);
+ out_be32(&pcix->powbar1, (mem->phys_start >> 12) & 0x000f);
+ out_be32(&pcix->powbear1, 0);
+ out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
+POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
+
+ /* BAR 1: IO */
+ out_be32(&pcix->potar2, (io->bus_start >> 12) & 0x000f);
+ out_be32(&pcix->potear2, 0);
+ out_be32(&pcix->powbar2, (io->phys_start >> 12) & 0x000f);
+ out_be32(&pcix->powbear2, 0);
+ out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
+POWAR_IO_WRITE | (__ilog2(io->size) - 1)));
+
+ out_be32(&pcix->pitar1, 0);
+ out_be32(&pcix->piwbar1, 0);
+ out_be32(&pcix->piwar1, (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
+PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G));
+
+ out_be32(&pcix->powar3, 0);
+ out_be32(&pcix->powar4, 0);
[U-Boot] [PATCH v1 3/3] rtc, rx8025: add DM support
add DM support for this RTC driver.
Signed-off-by: Heiko Schocher
---
drivers/rtc/rx8025.c | 154 +--
1 file changed, 135 insertions(+), 19 deletions(-)
diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c
index b3826e950d..e717dcbbfe 100644
--- a/drivers/rtc/rx8025.c
+++ b/drivers/rtc/rx8025.c
@@ -10,8 +10,9 @@
#include
#include
-#include
+#include
#include
+#include
/*-*/
#undef DEBUG_RTC
@@ -27,6 +28,18 @@
# define CONFIG_SYS_I2C_RTC_ADDR 0x32
#endif
+#ifdef CONFIG_DM_RTC
+#define DEV_TYPE struct udevice
+#else
+/* Local udevice */
+struct ludevice {
+ u8 chip;
+};
+
+#define DEV_TYPE struct ludevice
+
+#endif
+
/*
* RTC register addresses
*/
@@ -68,21 +81,35 @@
*/
/* static uchar rtc_read (uchar reg); */
+#ifdef CONFIG_DM_RTC
+/*
+ * on mpc85xx based board with DM and offset len 1
+ * accessing rtc works fine. May we can drop this ?
+ */
+#define rtc_read(reg) buf[(reg) & 0xf]
+#else
#define rtc_read(reg) buf[((reg) + 1) & 0xf]
+#endif
-static void rtc_write(uchar reg, uchar val);
+static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val);
/*
* Get the current time from the RTC
*/
-int rtc_get(struct rtc_time *tmp)
+static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year, ctl2;
uchar buf[16];
- if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
+#ifdef CONFIG_DM_RTC
+ if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
+#else
+ if (i2c_read(dev->chip, 0, 0, buf, 16)) {
+#endif
printf("Error reading from RTC\n");
+ return -EIO;
+ }
sec = rtc_read(RTC_SEC_REG_ADDR);
min = rtc_read(RTC_MIN_REG_ADDR);
@@ -138,7 +165,7 @@ int rtc_get(struct rtc_time *tmp)
/*
* Set the RTC
*/
-int rtc_set(struct rtc_time *tmp)
+static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp)
{
DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
@@ -147,44 +174,133 @@ int rtc_set(struct rtc_time *tmp)
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
- rtc_write(RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
- rtc_write(RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
- rtc_write(RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday));
- rtc_write(RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
- rtc_write(RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
- rtc_write(RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
- rtc_write(RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
+ if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100)))
+ return -EIO;
- rtc_write(RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
+ if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon)))
+ return -EIO;
- return 0;
+ if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday)))
+ return -EIO;
+
+ if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday)))
+ return -EIO;
+
+ if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour)))
+ return -EIO;
+
+ if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min)))
+ return -EIO;
+
+ if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec)))
+ return -EIO;
+
+ return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
}
/*
* Reset the RTC
*/
-void rtc_reset(void)
+static int rx8025_rtc_reset(DEV_TYPE *dev)
{
uchar buf[16];
uchar ctl2;
- if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
+#ifdef CONFIG_DM_RTC
+ if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
+#else
+ if (i2c_read(dev->chip, 0, 0, buf, 16)) {
+#endif
printf("Error reading from RTC\n");
+ return -EIO;
+ }
ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
- rtc_write(RTC_CTL2_REG_ADDR, ctl2);
+
+ return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2);
}
/*
* Helper functions
*/
-static void rtc_write(uchar reg, uchar val)
+static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val)
{
uchar buf[2];
buf[0] = reg << 4;
buf[1] = val;
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 2) != 0)
+
+#ifdef CONFIG_DM_RTC
+ if (dm_i2c_write(dev, 0, buf, 2)) {
+#else
+ if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) {
+#endif
printf("Error writing to RTC\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_DM_RTC
+static int rx8025_probe(struct udevice *dev)
+{
+ uchar buf[16];
+ int ret = 0;
+
+
[U-Boot] [PATCH v1 2/3] rtc, rx8025: fix Coding Style
fix Coding Style for this driver.
Signed-off-by: Heiko Schocher
---
drivers/rtc/rx8025.c | 58 ++--
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c
index 7bd9f8b42a..b3826e950d 100644
--- a/drivers/rtc/rx8025.c
+++ b/drivers/rtc/rx8025.c
@@ -70,12 +70,12 @@
/* static uchar rtc_read (uchar reg); */
#define rtc_read(reg) buf[((reg) + 1) & 0xf]
-static void rtc_write (uchar reg, uchar val);
+static void rtc_write(uchar reg, uchar val);
/*
* Get the current time from the RTC
*/
-int rtc_get (struct rtc_time *tmp)
+int rtc_get(struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year, ctl2;
@@ -92,9 +92,9 @@ int rtc_get (struct rtc_time *tmp)
mon = rtc_read(RTC_MON_REG_ADDR);
year = rtc_read(RTC_YR_REG_ADDR);
- DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
- "hr: %02x min: %02x sec: %02x\n",
- year, mon, mday, wday, hour, min, sec);
+ DEBUGR("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
+ "hr: %02x min: %02x sec: %02x\n",
+ year, mon, mday, wday, hour, min, sec);
/* dump status */
ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
@@ -113,13 +113,14 @@ int rtc_get (struct rtc_time *tmp)
rel = -1;
}
- tmp->tm_sec = bcd2bin (sec & 0x7F);
- tmp->tm_min = bcd2bin (min & 0x7F);
+ tmp->tm_sec = bcd2bin(sec & 0x7F);
+ tmp->tm_min = bcd2bin(min & 0x7F);
if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412)
- tmp->tm_hour = bcd2bin (hour & 0x3F);
+ tmp->tm_hour = bcd2bin(hour & 0x3F);
else
- tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 +
+ tmp->tm_hour = bcd2bin(hour & 0x1F) % 12 +
((hour & 0x20) ? 12 : 0);
+
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
@@ -127,9 +128,9 @@ int rtc_get (struct rtc_time *tmp)
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
- DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ DEBUGR("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return rel;
}
@@ -137,24 +138,24 @@ int rtc_get (struct rtc_time *tmp)
/*
* Set the RTC
*/
-int rtc_set (struct rtc_time *tmp)
+int rtc_set(struct rtc_time *tmp)
{
- DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
- rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
- rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
- rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
- rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
- rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
- rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
- rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
+ rtc_write(RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
+ rtc_write(RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
+ rtc_write(RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday));
+ rtc_write(RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
+ rtc_write(RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
+ rtc_write(RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
+ rtc_write(RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
- rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
+ rtc_write(RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
return 0;
}
@@ -162,29 +163,28 @@ int rtc_set (struct rtc_time *tmp)
/*
* Reset the RTC
*/
-void rtc_reset (void)
+void rtc_reset(void)
{
uchar buf[16];
uchar ctl2;
- if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0,0, buf, 16))
+ if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
printf("Error reading from RTC\n");
ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
- rtc_write (RTC_CTL2_REG_ADDR, ctl2);
+ rtc_write(RTC_CTL2_REG_ADDR, ctl2);
}
/*
* Helper functions
*/
-static void rtc
[U-Boot] [PATCH v1 1/3] rtc: move RTC_RX8025 to Kconfig
move RTC_RX8025 to Kconfig and fixup board configs. Signed-off-by: Heiko Schocher --- configs/caddy2_defconfig | 1 + configs/socrates_defconfig | 1 + configs/vme8349_defconfig| 1 + drivers/rtc/Kconfig | 5 + include/configs/caddy2.h | 1 - include/configs/socrates.h | 1 - include/configs/vme8349.h| 1 - scripts/config_whitelist.txt | 1 - 8 files changed, 8 insertions(+), 4 deletions(-) diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 33253b1332..51c37e2e1a 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -111,6 +111,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y CONFIG_E1000=y +CONFIG_RTC_RX8025=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 2d5e158871..1dadc122cf 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -37,6 +37,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_RTC_RX8025=y CONFIG_SYS_NS16550=y CONFIG_USB=y # CONFIG_USB_EHCI_HCD is not set diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 77c7904a2c..f6b9eb6c2c 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -114,6 +114,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y +CONFIG_RTC_RX8025=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 532e94d337..023bcac286 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -86,6 +86,11 @@ config RTC_RX8010SJ help Support for Epson RX8010SJ Real Time Clock devices. +config RTC_RX8025 + bool "Enable RX8025 driver" + help + Support for Epson RX8025 Real Time Clock devices. + config RTC_PL031 bool "Enable ARM AMBA PL031 RTC driver" help diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 15ac17985f..89deeac4e7 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -225,7 +225,6 @@ */ #define CONFIG_SYS_RTC_BUS_NUM 0x01 #define CONFIG_SYS_I2C_RTC_ADDR0x32 -#define CONFIG_RTC_RX8025 /* Pass Ethernet MAC to VxWorks */ #define CONFIG_SYS_VXWORKS_MAC_PTR 0x43f0 diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 3f84fabdb6..7d266d1bcd 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -187,7 +187,6 @@ #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 /* I2C RTC */ -#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ #define CONFIG_SYS_I2C_RTC_ADDR0x32/* at address 0x32 */ /* I2C W83782G HW-Monitoring IC */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 1c3430d849..a4f2af4962 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -225,7 +225,6 @@ */ #define CONFIG_SYS_RTC_BUS_NUM 0x01 #define CONFIG_SYS_I2C_RTC_ADDR0x32 -#define CONFIG_RTC_RX8025 /* Pass Ethernet MAC to VxWorks */ #define CONFIG_SYS_VXWORKS_MAC_PTR 0x43f0 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2c9cfb450d..4ffc4bb9ec 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1559,7 +1559,6 @@ CONFIG_RTC_MCP79411 CONFIG_RTC_MXS CONFIG_RTC_PCF8563 CONFIG_RTC_PT7C4338 -CONFIG_RTC_RX8025 CONFIG_RUN_FROM_DDR0 CONFIG_RUN_FROM_DDR1 CONFIG_RUN_FROM_IRAM_ONLY -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 0/3] rtc, dm: add DM/Kconfig support for RTC_RX8025 driver
add DM and Kconfig support for RTC_RX8025 driver. Based on mainline commit: 6070ef409c - Merge branch '2019-07-12-master-imports' Travis build: https://travis-ci.org/hsdenx/u-boot-test/builds/558787565 Heiko Schocher (3): rtc: move RTC_RX8025 to Kconfig rtc, rx8025: fix Coding Style rtc, rx8025: add DM support configs/caddy2_defconfig | 1 + configs/socrates_defconfig | 1 + configs/vme8349_defconfig| 1 + drivers/rtc/Kconfig | 5 + drivers/rtc/rx8025.c | 180 --- include/configs/caddy2.h | 1 - include/configs/socrates.h | 1 - include/configs/vme8349.h| 1 - scripts/config_whitelist.txt | 1 - 9 files changed, 156 insertions(+), 36 deletions(-) -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-mmc
On Tue, Jul 16, 2019 at 02:03:02AM +, Peng Fan wrote: > Hi Tom, > > > Subject: Re: Please pull u-boot-mmc > > > > On Mon, Jul 15, 2019 at 07:21:24AM +, Peng Fan wrote: > > > > > Hi Tom, > > > > > > Please pull u-boot-mmc, > > > CI build: https://travis-ci.org/MrVan/u-boot/builds/558716778 > > > > Note that I see a general small bit of SPL growth here. Can we do something > > about it? i.e. this from libretech_all_h3_cc_h5: > > Could you please share how to the comparation? Do you have a script? Just one of the many features of buildman. My wrapper around it is: #!/bin/bash if [ $# -ne 1 -a $# -ne 2 ];then echo "Usage: $0 MACHINE [BRANCH]" exit 1 fi if [ ! -z $2 ]; then B=$2 else B=`git rev-parse --abbrev-ref HEAD` fi export SOURCE_DATE_EPOCH=`date +%s` ./tools/buildman/buildman -o /tmp/$1 -b $B --step 0 -SBCdevlk $1 ./tools/buildman/buildman -o /tmp/$1 -b $B --step 0 -SsBdevlk $1 rm -rf /tmp/$1 -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/2] arm: qemu: fix failure if booting from TF-A
Hi Albert, Tuomas, Ping. Can you review this patch, please? -Takahiro Akashi On Wed, Jul 03, 2019 at 10:44:38AM +0900, AKASHI Takahiro wrote: > With this patch, hang-up of U-Boot, as described in patch#2, will be fixed > if it is loaded and started from TF-A. > > Changes in v2 (July 3, 2019) > * add patch#1 (preparatory patch) > * remove a reference to unnecessary patch in the commit message > > AKASHI Takahiro (2): > arm: move CONFIG_TFABOOT to generic Kconfig > arm: qemu: fix failure in flash initialization if booting from TF-A > > arch/arm/Kconfig | 29 +++ > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 -- > include/configs/qemu-arm.h| 5 > 3 files changed, 34 insertions(+), 7 deletions(-) > > -- > 2.21.0 > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [EXT] Re: [PATCH v4] rtc: Add DM support to ds3231
Hi, Lukasz Majewski
> -Original Message-
> From: Lukasz Majewski
> Sent: 2019年6月21日 19:33
> To: Chuanhua Han
> Cc: Prabhakar Kushwaha ;
> u-boot@lists.denx.de
> Subject: [EXT] Re: [PATCH v4] rtc: Add DM support to ds3231
>
> On Fri, 21 Jun 2019 16:21:53 +0800
> Chuanhua Han wrote:
>
> > Add an implementation of the ds3231 driver that uses the driver model
> > i2c APIs.
> >
> > Signed-off-by: Chuanhua Han
> > ---
> > Changes in v4:
> > - Delete the original 'rel' variable in the ds3231_rtc_get function,
> > return 0 successfully, and return -EINVAL directly when the RTC
> > oscillator is stopped.
> > Changes in v3:
> > - Update copyright information.
> > Changes in v2:
> > - Replace "#ifndef CONFIG_DM_RTC" with "#if
> > !CONFIG_IS_ENABLED(DM_RTC)".
> >
> > drivers/rtc/ds3231.c | 107
> > +++ 1 file changed, 107
> > insertions(+)
> >
> > diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index
> > 9352ff87a2..79b026af4b 100644
> > --- a/drivers/rtc/ds3231.c
> > +++ b/drivers/rtc/ds3231.c
> > @@ -2,6 +2,9 @@
> > /*
> > * (C) Copyright 2006
> > * Markus Klotzbuecher, m...@denx.de
> > + *
> > + * (C) Copyright 2019 NXP
> > + * Chuanhua Han
> > */
> >
> > /*
> > @@ -13,6 +16,7 @@
> >
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -50,6 +54,7 @@
> > #define RTC_STAT_BIT_EN32KHZ 0x8 /* Enable 32KHz
> > Output */
> >
> > +#if !CONFIG_IS_ENABLED(DM_RTC)
> > static uchar rtc_read (uchar reg);
> > static void rtc_write (uchar reg, uchar val);
> >
> > @@ -164,3 +169,105 @@ static void rtc_write (uchar reg, uchar val) {
> > i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); }
> > +#else
> > +static int ds3231_rtc_get(struct udevice *dev, struct rtc_time *tmp)
> > +{
> > + uchar sec, min, hour, mday, wday, mon_cent, year, status;
> > +
> > + status = dm_i2c_reg_read(dev, RTC_STAT_REG_ADDR);
> > + sec = dm_i2c_reg_read(dev, RTC_SEC_REG_ADDR);
> > + min = dm_i2c_reg_read(dev, RTC_MIN_REG_ADDR);
> > + hour = dm_i2c_reg_read(dev, RTC_HR_REG_ADDR);
> > + wday = dm_i2c_reg_read(dev, RTC_DAY_REG_ADDR);
> > + mday = dm_i2c_reg_read(dev, RTC_DATE_REG_ADDR);
> > + mon_cent = dm_i2c_reg_read(dev, RTC_MON_REG_ADDR);
> > + year = dm_i2c_reg_read(dev, RTC_YR_REG_ADDR);
> > +
> > + if (status & RTC_STAT_BIT_OSF) {
> > + printf("### Warning: RTC oscillator has stopped\n");
> > + /* clear the OSF flag */
> > + dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR,
> > +dm_i2c_reg_read(dev,
> > RTC_STAT_REG_ADDR)
> > + & ~RTC_STAT_BIT_OSF);
> > + return -EINVAL;
> > + }
> > +
> > + tmp->tm_sec = bcd2bin(sec & 0x7F);
> > + tmp->tm_min = bcd2bin(min & 0x7F);
> > + tmp->tm_hour = bcd2bin(hour & 0x3F);
> > + tmp->tm_mday = bcd2bin(mday & 0x3F);
> > + tmp->tm_mon = bcd2bin(mon_cent & 0x1F);
> > + tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 2000 :
> > 1900);
> > + tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
> > + tmp->tm_yday = 0;
> > + tmp->tm_isdst = 0;
> > +
> > + debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME:
> > %2d:%02d:%02d\n",
> > + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
> > + tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
> > +
> > + return 0;
> > +}
> > +
> > +static int ds3231_rtc_set(struct udevice *dev, const struct rtc_time
> > *tmp) +{
> > + uchar century;
> > +
> > + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME:
> > %2d:%02d:%02d\n",
> > + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
> > + tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
> > +
> > + dm_i2c_reg_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year
> > % 100)); +
> > + century = (tmp->tm_year >= 2000) ? 0x80 : 0;
> > + dm_i2c_reg_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon)
> > | century); +
> > + dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday
> 1));
> > + dm_i2c_reg_write(dev, RTC_DATE_REG_ADDR,
> > bin2bcd(tmp->tm_mday));
> > + dm_i2c_reg_write(dev, RTC_HR_REG_ADDR,
> > bin2bcd(tmp->tm_hour));
> > + dm_i2c_reg_write(dev, RTC_MIN_REG_ADDR,
> > bin2bcd(tmp->tm_min));
> > + dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
> > bin2bcd(tmp->tm_sec)); +
> > + return 0;
> > +}
> > +
> > +static int ds3231_rtc_reset(struct udevice *dev) {
> > + int ret;
> > +
> > + ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
> > + RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static int ds3231_probe(struct udevice *dev) {
> > + i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
> > + DM_I2C_CHIP_WR_ADDRESS);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct rtc_ops ds3231_rtc_ops = {
> > + .get = ds3231_rtc_get,
> > + .set = ds3231_rtc_set,
> > + .reset = ds3231_rtc_reset,
> > +};
>
Re: [U-Boot] [PATCH v4 0/6] Add spi-mem driver for MediaTek MT7629 SoC
On Mon, 2019-07-15 at 12:59 +0530, Jagan Teki wrote: > On Wed, Jul 10, 2019 at 8:51 AM Weijie Gao wrote: > > > > Since u-boot has added the spi-mem framework and replaced the spi-nor > > framework, > > the mtk_qspi is no longer compatible with the new spi-nor driver. > > > > This patch series add a new spi-mem driver to replace the mtk_qspi driver, > > with one patch to fix watchdog not feeding during spi operation. > > > > Weijie Gao (6): > > mtd: spi-nor: add watchdog reset to flash operation loops > > spi: remove obsolete mtk_qspi driver > > spi: add spi-mem driver for MediaTek MT7629 SoC > > arm: dts: change MT7629 to use spi-mem rather than qspi > > configs: mt7629_rfb: change MTK_QSPI to MTK_SNFI_SPI > > MAINTAINERS: change spi driver entry > > What is v4 change log? I wouldn't find it on individual patches? Oh, I forgot to write this to cover letter. But I have written change log to "spi: add spi-mem driver for MediaTek MT7629 SoC". There is only one change in this patch: remove chip select checking. I think this should be implemented in spi-uclass. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] mx6: Allow configuring the NoC registers on i.MX6QP
> Subject: [PATCH 4/4] mx6: Allow configuring the NoC registers on i.MX6QP
>
> The NoC registers on i.MX6QP needs to be configured, otherwise some
> usecases in the kernel behave incorrectly, such as rotation and resize.
>
> Currently the NoC registers are not configured in the kernel, so configure
> them
> in U-Boot like it is done in the NXP U-Boot tree.
>
> Signed-off-by: Fabio Estevam
> ---
> arch/arm/mach-imx/mx6/soc.c | 32
>
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
> index e80f1d484b..8de42408c7 100644
> --- a/arch/arm/mach-imx/mx6/soc.c
> +++ b/arch/arm/mach-imx/mx6/soc.c
> @@ -365,6 +365,35 @@ static void init_bandgap(void)
> }
> }
>
> +static void noc_setup(void)
> +{
> + enable_ipu_clock();
> +
> + writel(0x8201, 0xbb0608);
> + /* Bypass IPU1 QoS generator */
> + writel(0x0002, 0x00bb048c);
> + /* Bypass IPU2 QoS generator */
> + writel(0x0002, 0x00bb050c);
> + /* Bandwidth THR for of PRE0 */
> + writel(0x0200, 0x00bb0690);
> + /* Bandwidth THR for of PRE1 */
> + writel(0x0200, 0x00bb0710);
> + /* Bandwidth THR for of PRE2 */
> + writel(0x0200, 0x00bb0790);
> + /* Bandwidth THR for of PRE3 */
> + writel(0x0200, 0x00bb0810);
> + /* Saturation THR for of PRE0 */
> + writel(0x0010, 0x00bb0694);
> + /* Saturation THR for of PRE1 */
> + writel(0x0010, 0x00bb0714);
> + /* Saturation THR for of PRE2 */
> + writel(0x0010, 0x00bb0794);
> + /* Saturation THR for of PRE */
> + writel(0x0010, 0x00bb0814);
> +
> + disable_ipu_clock();
> +}
> +
> int arch_cpu_init(void)
> {
> struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> @@ -442,6 +471,9 @@ int arch_cpu_init(void)
>
> init_src();
>
> + if (is_mx6dqp())
> + noc_setup();
> +
> return 0;
> }
Reviewed-by: Peng Fan
>
> --
> 2.17.1
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Re: [U-Boot] [PATCH 3/4] mx6: clock: Introduce disable_ipu_clock()
> Subject: [PATCH 3/4] mx6: clock: Introduce disable_ipu_clock()
>
> Introduce disable_ipu_clock(). This is done in preparation for configuring the
> NoC registers on i.MX6QP in SPL.
>
> Afer the NoC registers are set the IPU clocks can be disabled.
>
> Signed-off-by: Fabio Estevam
> ---
> arch/arm/include/asm/arch-mx6/clock.h | 1 +
> arch/arm/mach-imx/mx6/clock.c | 12
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-mx6/clock.h
> b/arch/arm/include/asm/arch-mx6/clock.h
> index a9481a5fea..f7760541a4 100644
> --- a/arch/arm/include/asm/arch-mx6/clock.h
> +++ b/arch/arm/include/asm/arch-mx6/clock.h
> @@ -71,6 +71,7 @@ int enable_pcie_clock(void); int
> enable_i2c_clk(unsigned char enable, unsigned i2c_num); int
> enable_spi_clk(unsigned char enable, unsigned spi_num); void
> enable_ipu_clock(void);
> +void disable_ipu_clock(void);
> int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void
> enable_enet_clk(unsigned char enable); int enable_lcdif_clock(u32
> base_addr, bool enable); diff --git a/arch/arm/mach-imx/mx6/clock.c
> b/arch/arm/mach-imx/mx6/clock.c index 9951f79106..e1e21e37a8 100644
> --- a/arch/arm/mach-imx/mx6/clock.c
> +++ b/arch/arm/mach-imx/mx6/clock.c
> @@ -1287,6 +1287,18 @@ void enable_ipu_clock(void)
> setbits_le32(&mxc_ccm->CCGR3,
> MXC_CCM_CCGR3_IPU2_IPU_MASK);
> }
> }
> +
> +void disable_ipu_clock(void)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
> *)CCM_BASE_ADDR;
> +
> + clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
> +
> + if (is_mx6dqp()) {
> + clrbits_le32(&mxc_ccm->CCGR6,
> MXC_CCM_CCGR6_PRG_CLK0_MASK);
> + clrbits_le32(&mxc_ccm->CCGR3,
> MXC_CCM_CCGR3_IPU2_IPU_MASK);
> + }
> +}
> #endif
Reviewed-by: Peng Fan
>
> #ifndef CONFIG_SPL_BUILD
> --
> 2.17.1
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Re: [U-Boot] [PATCH 1/4] mx6: clock: Allow enable_ipu_clock() to be built for SPL code
> Subject: [PATCH 1/4] mx6: clock: Allow enable_ipu_clock() to be built for SPL
> code
>
> Allow enable_ipu_clock() to be built for SPL code. This is done in preparation
> for configuring the NoC registers on i.MX6QP in SPL.
>
> Signed-off-by: Fabio Estevam
> ---
> arch/arm/mach-imx/mx6/clock.c | 32
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mx6/clock.c
> b/arch/arm/mach-imx/mx6/clock.c index 366a4e3c6b..5af1ae7cf3 100644
> --- a/arch/arm/mach-imx/mx6/clock.c
> +++ b/arch/arm/mach-imx/mx6/clock.c
> @@ -1275,6 +1275,22 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
> return 0;
> }
>
> +#ifndef CONFIG_MX6SX
> +void enable_ipu_clock(void)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
> *)CCM_BASE_ADDR;
> + int reg;
> + reg = readl(&mxc_ccm->CCGR3);
> + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
> + writel(reg, &mxc_ccm->CCGR3);
> +
> + if (is_mx6dqp()) {
> + setbits_le32(&mxc_ccm->CCGR6,
> MXC_CCM_CCGR6_PRG_CLK0_MASK);
> + setbits_le32(&mxc_ccm->CCGR3,
> MXC_CCM_CCGR3_IPU2_IPU_MASK);
> + }
> +}
> +#endif
> +
> #ifndef CONFIG_SPL_BUILD
> /*
> * Dump some core clockes.
> @@ -1311,22 +1327,6 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int
> flag, int argc, char * const argv[])
> return 0;
> }
>
> -#ifndef CONFIG_MX6SX
> -void enable_ipu_clock(void)
> -{
> - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
> *)CCM_BASE_ADDR;
> - int reg;
> - reg = readl(&mxc_ccm->CCGR3);
> - reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
> - writel(reg, &mxc_ccm->CCGR3);
> -
> - if (is_mx6dqp()) {
> - setbits_le32(&mxc_ccm->CCGR6,
> MXC_CCM_CCGR6_PRG_CLK0_MASK);
> - setbits_le32(&mxc_ccm->CCGR3,
> MXC_CCM_CCGR3_IPU2_IPU_MASK);
> - }
> -}
> -#endif
> -
> #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) ||
> defined(CONFIG_MX6DL) || \
> defined(CONFIG_MX6S)
> static void disable_ldb_di_clock_sources(void)
Reviewed-by: Peng Fan
> --
> 2.17.1
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Re: [U-Boot] [PATCH 2/4] mx6: clock: Use setbits_le32()
> Subject: [PATCH 2/4] mx6: clock: Use setbits_le32()
>
> The code can be made simpler by using setbits_le32(), so switch to it.
>
> Signed-off-by: Fabio Estevam
> ---
> arch/arm/mach-imx/mx6/clock.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mx6/clock.c
> b/arch/arm/mach-imx/mx6/clock.c index 5af1ae7cf3..9951f79106 100644
> --- a/arch/arm/mach-imx/mx6/clock.c
> +++ b/arch/arm/mach-imx/mx6/clock.c
> @@ -1279,10 +1279,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
> void enable_ipu_clock(void) {
> struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
> *)CCM_BASE_ADDR;
> - int reg;
> - reg = readl(&mxc_ccm->CCGR3);
> - reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
> - writel(reg, &mxc_ccm->CCGR3);
> +
> + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
>
> if (is_mx6dqp()) {
> setbits_le32(&mxc_ccm->CCGR6,
> MXC_CCM_CCGR6_PRG_CLK0_MASK);
Reviewed-by: Peng Fan
> --
> 2.17.1
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Re: [U-Boot] Please pull u-boot-mmc
Hi Tom, > Subject: Re: Please pull u-boot-mmc > > On Mon, Jul 15, 2019 at 07:21:24AM +, Peng Fan wrote: > > > Hi Tom, > > > > Please pull u-boot-mmc, > > CI build: https://travis-ci.org/MrVan/u-boot/builds/558716778 > > Note that I see a general small bit of SPL growth here. Can we do something > about it? i.e. this from libretech_all_h3_cc_h5: Could you please share how to the comparation? Do you have a script? Thanks, Peng. >spl-u-boot-spl: add: 0/0, grow: 5/-2 bytes: 260/-104 (156) > function old > new delta > static.__mmc_switch108 > 248+140 > mmc_startup_v4 > 516 572 +56 > mmc_init > 22722304 +32 > mmc_switch_part > 120 148 +28 > static.mmc_set_card_speed 156 > 160 +4 > mmc_switch > 12 4 -8 > mmc_send_status > 212 116 -96 > > Applied to u-boot/master, thanks! > > -- > Tom ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/8] net: tsec: Fix offset of MDIO registers for DM_ETH
Hi Vladimir,
On Tue, Jul 16, 2019 at 6:00 AM Vladimir Oltean wrote:
>
> Hi Joe,
>
> On Mon, 15 Jul 2019 at 21:00, Joe Hershberger wrote:
> >
> > On Sun, Jun 23, 2019 at 12:51 PM Vladimir Oltean wrote:
> > >
> > > By convention, the eTSEC MDIO controller nodes are defined in DT at
> > > 0x2d24000 and 0x2d5, but actually U-boot does not touch the
> > > interrupt portion of the register map (MDIO_IEVENTM, MDIO_IMASKM,
> > > MDIO_EMAPM).
> > >
> > > That leaves only the MDIO bus registers (MDIO_MIIMCFG, MDIO_MIIMCOM,
> > > MDIO_MIIMADD, MDIO_MIIMADD, MDIO_MIIMCON, MDIO_MIIMSTAT) which start at
> > > the 0x520 offset.
> > >
> > > So shift the DT-defined register map by the offset of MDIO_MIIMCFG when
> > > mapping the MDIO bus registers.
> > >
> > > Signed-off-by: Vladimir Oltean
> >
> > Acked-by: Joe Hershberger
> >
> > > ---
> > > drivers/net/tsec.c | 13 +++--
> > > include/tsec.h | 4 +++-
> > > 2 files changed, 10 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
> > > index 53eb5470f4c8..576398676af7 100644
> > > --- a/drivers/net/tsec.c
> > > +++ b/drivers/net/tsec.c
> > > @@ -801,6 +801,7 @@ int tsec_probe(struct udevice *dev)
> > > u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
> > > ofnode parent;
> > > const char *phy_mode;
> > > + fdt_addr_t reg;
> > > int ret;
> > >
> > > pdata->iobase = (phys_addr_t)dev_read_addr(dev);
> > > @@ -817,15 +818,15 @@ int tsec_probe(struct udevice *dev)
> > > }
> > >
> > > parent = ofnode_get_parent(phandle_args.node);
> > > - if (ofnode_valid(parent)) {
> > > - int reg = ofnode_get_addr_index(parent, 0);
> > > -
> > > - priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
> > > - } else {
> > > - debug("No parent node for PHY?\n");
> > > + if (!ofnode_valid(parent)) {
> > > + printf("No parent node for PHY?\n");
> > > return -ENOENT;
> > > }
> > >
> > > + reg = ofnode_get_addr_index(parent, 0);
> > > + priv->phyregs_sgmii = (struct tsec_mii_mng *)
> > > + (reg + TSEC_MDIO_REGS_OFFSET);
> >
> > I'm surprised not to see a .dts change in this patch as well or some
> > other consumer of this phyregs_sgmii member.
> >
>
> This surprises me as well, to be honest.
> Actually Bin Meng's patchset to convert the TSEC driver to DM never
> got completely merged. I suppose the LS1021A-TWR conversion was sort
> of mechanical and probably not tested on hardware, otherwise I can't
Actually I did test the LS1021A-TWR TSEC DM conversion patch when I
submitted it before. I vaguely remember the reason why it was not
merged was because DM ETH depended on DM PCI conversion and at that
time, DM PCI conversion on LS1021A was not ready.
> explain. There is no DT patch because this portion of the code never
> worked. The DM version of the TSEC driver had no (upstream?) users.
Regards,
Bin
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Re: [U-Boot] [PATCH v2] net/macb: increase RX buffer size for GEM
On Sun, Jul 14, 2019 at 10:25 AM Ramon Fried wrote:
>
> Macb Ethernet controller requires a RX buffer of 128 bytes. It is
> highly sub-optimal for Gigabit-capable GEM that is able to use
> a bigger DMA buffer. Change this constant and associated macros
> with data stored in the private structure.
> RX DMA buffer size has to be multiple of 64 bytes as indicated in
> DMA Configuration Register specification.
>
> Signed-off-by: Ramon Fried
Is there a dependency here that you don't mention? This doesn't apply cleanly.
Thanks,
-Joe
> ---
> v2: Fix multi-line comment style
> drivers/net/macb.c | 30 ++
> 1 file changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> index c072f99d8f..3c8b9722b3 100644
> --- a/drivers/net/macb.c
> +++ b/drivers/net/macb.c
> @@ -45,10 +45,17 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -#define MACB_RX_BUFFER_SIZE4096
> -#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
> +/*
> + * These buffer sizes must be power of 2 and divisible
> + * by RX_BUFFER_MULTIPLE
> + */
> +#define MACB_RX_BUFFER_SIZE128
> +#define GEM_RX_BUFFER_SIZE 2048
> #define RX_BUFFER_MULTIPLE 64
> +
> +#define MACB_RX_RING_SIZE 32
> #define MACB_TX_RING_SIZE 16
> +
> #define MACB_TX_TIMEOUT1000
> #define MACB_AUTONEG_TIMEOUT 500
>
> @@ -95,6 +102,7 @@ struct macb_device {
> void*tx_buffer;
> struct macb_dma_desc*rx_ring;
> struct macb_dma_desc*tx_ring;
> + size_t rx_buffer_size;
>
> unsigned long rx_buffer_dma;
> unsigned long rx_ring_dma;
> @@ -395,15 +403,16 @@ static int _macb_recv(struct macb_device *macb, uchar
> **packetp)
> }
>
> if (status & MACB_BIT(RX_EOF)) {
> - buffer = macb->rx_buffer + 128 * macb->rx_tail;
> + buffer = macb->rx_buffer +
> + macb->rx_buffer_size * macb->rx_tail;
> length = status & RXBUF_FRMLEN_MASK;
>
> macb_invalidate_rx_buffer(macb);
> if (macb->wrapped) {
> unsigned int headlen, taillen;
>
> - headlen = 128 * (MACB_RX_RING_SIZE
> -- macb->rx_tail);
> + headlen = macb->rx_buffer_size *
> + (MACB_RX_RING_SIZE - macb->rx_tail);
> taillen = length - headlen;
> memcpy((void *)net_rx_packets[0],
>buffer, headlen);
> @@ -701,7 +710,7 @@ static void gmac_configure_dma(struct macb_device *macb)
> u32 buffer_size;
> u32 dmacfg;
>
> - buffer_size = 128 / RX_BUFFER_MULTIPLE;
> + buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
> dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
> dmacfg |= GEM_BF(RXBS, buffer_size);
>
> @@ -746,7 +755,7 @@ static int _macb_init(struct macb_device *macb, const
> char *name)
> paddr |= MACB_BIT(RX_WRAP);
> macb->rx_ring[i].addr = paddr;
> macb->rx_ring[i].ctrl = 0;
> - paddr += 128;
> + paddr += macb->rx_buffer_size;
> }
> macb_flush_ring_desc(macb, RX);
> macb_flush_rx_buffer(macb);
> @@ -957,8 +966,13 @@ static void _macb_eth_initialize(struct macb_device
> *macb)
> int id = 0; /* This is not used by functions we call */
> u32 ncfgr;
>
> + if (macb_is_gem(macb))
> + macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
> + else
> + macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
> +
> /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
> - macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
> + macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
> MACB_RX_RING_SIZE,
> &macb->rx_buffer_dma);
> macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
>&macb->rx_ring_dma);
> --
> 2.22.0
>
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[U-Boot] [PATCH v2 1/2] flash: Script to create a flash image from u-boot
This creates an empty flash image and places u-boot at the start of it.
It will be used by the ASPEED Qemu tests which boot u-boot from an
emaulated flash device.
Signed-off-by: Joel Stanley
---
bin/flash.create_image_32mb | 9 +
1 file changed, 9 insertions(+)
create mode 100755 bin/flash.create_image_32mb
diff --git a/bin/flash.create_image_32mb b/bin/flash.create_image_32mb
new file mode 100755
index ..8c2770d50e2b
--- /dev/null
+++ b/bin/flash.create_image_32mb
@@ -0,0 +1,9 @@
+# Copyright 2019 IBM Corp.
+# Joel Stanley
+# SPDX-License-Identifier: GPL-2.0+
+
+# TODO: Work out a better temp directory
+FLASH_IMG="${U_BOOT_BUILD_DIR}"/flash.img
+
+dd if=/dev/zero of="${FLASH_IMG}" count=32 bs=1M
+dd if="${U_BOOT_BUILD_DIR}"/u-boot.bin of="${FLASH_IMG}" conv=notrunc
--
2.20.1
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[U-Boot] [PATCH v2 2/2] travis: Add ASPEED AST2500 EVB Qemu
Signed-off-by: Joel Stanley
---
bin/travis-ci/conf.evb-ast2500_qemu | 11 +++
py/travis-ci/u_boot_boardenv_evb-ast2500_qemu.py | 7 +++
2 files changed, 18 insertions(+)
create mode 100644 bin/travis-ci/conf.evb-ast2500_qemu
create mode 100644 py/travis-ci/u_boot_boardenv_evb-ast2500_qemu.py
diff --git a/bin/travis-ci/conf.evb-ast2500_qemu
b/bin/travis-ci/conf.evb-ast2500_qemu
new file mode 100644
index ..41406fe38112
--- /dev/null
+++ b/bin/travis-ci/conf.evb-ast2500_qemu
@@ -0,0 +1,11 @@
+# Copyright 2019 IBM Corp.
+# Joel Stanley
+# SPDX-License-Identifier: GPL-2.0+
+
+console_impl=qemu
+qemu_machine="ast2500-evb"
+qemu_binary="qemu-system-arm"
+qemu_extra_args="-nographic -m 512M -serial mon:stdio -net nic,model=ftgmac100
-net user,id=net0,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
+qemu_kernel_args="-drive file=${U_BOOT_BUILD_DIR}/flash.img,format=raw,if=mtd"
+reset_impl=none
+flash_impl=create_image_32mb
diff --git a/py/travis-ci/u_boot_boardenv_evb-ast2500_qemu.py
b/py/travis-ci/u_boot_boardenv_evb-ast2500_qemu.py
new file mode 100644
index ..9a10a56e15dc
--- /dev/null
+++ b/py/travis-ci/u_boot_boardenv_evb-ast2500_qemu.py
@@ -0,0 +1,7 @@
+import travis_tftp
+
+env__spl_skipped = True
+
+env__net_dhcp_server = True
+
+env__net_tftp_readable_file = travis_tftp.file2env('u-boot')
--
2.20.1
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[U-Boot] [PATCH v2 0/2] uboot-test-hooks: aspeed ast2500 support
Hi Stephen, Here is support for the aspeed machine. The qemu setup is a bit different in that we load u-boot from an emulated flash device, so I've included a script that does this. v2 is a resend to include the u-boot list. I'll send out patches for the u-boot travis setup. I've given it a spin and it appears to work: https://travis-ci.com/shenki/u-boot/builds/117772801 Joel Stanley (2): flash: Script to create a flash image from u-boot travis: Add ASPEED AST2500 EVB Qemu bin/flash.create_image_32mb | 9 + bin/travis-ci/conf.evb-ast2500_qemu | 11 +++ py/travis-ci/u_boot_boardenv_evb-ast2500_qemu.py | 7 +++ 3 files changed, 27 insertions(+) create mode 100755 bin/flash.create_image_32mb create mode 100644 bin/travis-ci/conf.evb-ast2500_qemu create mode 100644 py/travis-ci/u_boot_boardenv_evb-ast2500_qemu.py -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/7] net: fec_mxc: Update driver to use full clks for iMX8
Hi Ye,
On Wed, Jul 3, 2019 at 4:52 AM Ye Li wrote:
>
> Add support for more clocks used by iMX8 from DTB:
> ref_clock, tx_2x_clock, ahb_clock
> And update get clock rate interface to support multiple fec ports.
It seems the feature to support multiple ports should be independent
of adding the extra needed clocks. I think they should be two separate
patches.
Thanks,
-Joe
>
> Signed-off-by: Ye Li
> ---
> Changes in v2:
> - None
>
> drivers/net/fec_mxc.c | 47 ++-
> drivers/net/fec_mxc.h | 1 +
> 2 files changed, 39 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index d7c0809..6d485f1 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -6,7 +6,6 @@
> * (C) Copyright 2007 Pengutronix, Sascha Hauer
> * (C) Copyright 2007 Pengutronix, Juergen Beisert
> */
> -
> #include
> #include
> #include
> @@ -132,9 +131,9 @@ static int fec_get_clk_rate(void *udev, int idx)
>
> dev = udev;
> if (!dev) {
> - ret = uclass_get_device(UCLASS_ETH, idx, &dev);
> + ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
> if (ret < 0) {
> - debug("Can't get FEC udev: %d\n", ret);
> + debug("Can't get FEC udev%d: %d\n", idx, ret);
> return ret;
> }
> }
> @@ -149,7 +148,7 @@ static int fec_get_clk_rate(void *udev, int idx)
> #endif
> }
>
> -static void fec_mii_setspeed(struct ethernet_regs *eth)
> +static void fec_mii_setspeed(struct ethernet_regs *eth, int idx)
> {
> /*
> * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
> @@ -171,7 +170,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth)
> u32 hold;
> int ret;
>
> - ret = fec_get_clk_rate(NULL, 0);
> + ret = fec_get_clk_rate(NULL, idx);
> if (ret < 0) {
> printf("Can't find FEC0 clk rate: %d\n", ret);
> return;
> @@ -593,7 +592,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
> fec_reg_setup(fec);
>
> if (fec->xcv_type != SEVENWIRE)
> - fec_mii_setspeed(fec->bus->priv);
> + fec_mii_setspeed(fec->bus->priv, fec->dev_id);
>
> /* Set Opcode/Pause Duration Register */
> writel(0x00010020, &fec->eth->op_pause);/* FIXME 0x0020;
> */
> @@ -1073,7 +1072,7 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int
> dev_id)
> free(bus);
> return NULL;
> }
> - fec_mii_setspeed(eth);
> + fec_mii_setspeed(eth, dev_id);
> return bus;
> }
>
> @@ -1142,7 +1141,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t
> base_addr,
> fec_set_dev_name(edev->name, dev_id);
> fec->dev_id = (dev_id == -1) ? 0 : dev_id;
> fec->bus = bus;
> - fec_mii_setspeed(bus->priv);
> + fec_mii_setspeed(bus->priv, fec->dev_id);
> #ifdef CONFIG_PHYLIB
> fec->phydev = phydev;
> phy_connect_dev(phydev, edev);
> @@ -1324,6 +1323,7 @@ static int fecmxc_probe(struct udevice *dev)
> int ret;
>
> if (IS_ENABLED(CONFIG_IMX8)) {
> + struct clk ref_clk, clk_2x_txclk;
> ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
> if (ret < 0) {
> debug("Can't get FEC ipg clk: %d\n", ret);
> @@ -1335,6 +1335,35 @@ static int fecmxc_probe(struct udevice *dev)
> return ret;
> }
>
> + ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
> + if (ret < 0) {
> + debug("Can't get FEC ahb clk: %d\n", ret);
> + return ret;
> + }
> + ret = clk_enable(&priv->ahb_clk);
> + if (ret < 0) {
> + debug("Can't enable FEC ahb clk: %d\n", ret);
> + return ret;
> + }
> +
> + ret = clk_get_by_name(dev, "enet_clk_ref", &ref_clk);
> + if (ret >= 0) {
> + ret = clk_enable(&ref_clk);
> + if (ret < 0) {
> + debug("Can't enable FEC ref clk: %d\n", ret);
> + return ret;
> + }
> + }
> +
> + ret = clk_get_by_name(dev, "enet_2x_txclk", &clk_2x_txclk);
> + if (ret >= 0) {
> + ret = clk_enable(&clk_2x_txclk);
> + if (ret < 0) {
> + debug("Can't enable FEC 2x_tx clk: %d\n",
> ret);
> + return ret;
> + }
> + }
> +
> priv->clk_rate = clk_get_rate(&priv->ipg_clk);
> }
>
> @@ -1368,7 +1397,6 @@ static int fecmxc_probe(struct udevice *dev)
> }
>
>
Re: [U-Boot] [PATCH v3] drivers: net: phy: Ignore PHY ID 0 during PHY probing
On Fri, Jul 5, 2019 at 4:29 AM Alex Marginean wrote: > > Current code fails to probe some C45 PHYs that also respond to C22 reads. > This is the case for PHYs like Aquantia AQR112, Marvell 88X2242 (as > previously posted on the u-boot list). > If the PHY ID reads all 0s just ignore it and try the next devad. > > Signed-off-by: Alex Marginean > Reviewed-By: Ramon Fried > Reviewed-by: Bin Meng Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-mmc
On Mon, Jul 15, 2019 at 07:21:24AM +, Peng Fan wrote: > Hi Tom, > > Please pull u-boot-mmc, > CI build: https://travis-ci.org/MrVan/u-boot/builds/558716778 Note that I see a general small bit of SPL growth here. Can we do something about it? i.e. this from libretech_all_h3_cc_h5: spl-u-boot-spl: add: 0/0, grow: 5/-2 bytes: 260/-104 (156) function old new delta static.__mmc_switch108 248+140 mmc_startup_v4 516 572 +56 mmc_init 22722304 +32 mmc_switch_part120 148 +28 static.mmc_set_card_speed 156 160 +4 mmc_switch 12 4 -8 mmc_send_status212 116 -96 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: macb: Add support for 1000-baseX
Hi Radu, https://patchwork.ozlabs.org/patch/832/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defs
Hi Keerthy, https://patchwork.ozlabs.org/patch/1129508/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: macb: Fixed reading MII_LPA register
Hi Radu, https://patchwork.ozlabs.org/patch/831/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: introduce MDIO DM class for MDIO devices
Hi Alex, https://patchwork.ozlabs.org/patch/1109368/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] test: dm: add MDIO test
Hi Alex, https://patchwork.ozlabs.org/patch/1109369/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] configs: am65x_evm_a53: enable networking
Hi Keerthy, https://patchwork.ozlabs.org/patch/1129507/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm64: dts: ti: k3-am65: add mcu cpsw node
Hi Keerthy, https://patchwork.ozlabs.org/patch/1129509/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver
Hi Keerthy, https://patchwork.ozlabs.org/patch/1129506/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addr
Hi Keerthy, https://patchwork.ozlabs.org/patch/1129505/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: mscc: refactor mscc_miim
Hi Horatiu, https://patchwork.ozlabs.org/patch/1112638/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: ti: Fix clock output DT property
Hi Trent, https://patchwork.ozlabs.org/patch/1098253/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: cortina: Use block layer to read from mmc
Hi Yinbo, https://patchwork.ozlabs.org/patch/1113517/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] cmd: mii: Add the standard 1000BASE-T registers
Hi Trent, https://patchwork.ozlabs.org/patch/1097646/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: ti: Use default values for tx/rx delay and fifo size
Hi Trent, https://patchwork.ozlabs.org/patch/1097657/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: mscc: serval: Remove delay when serdes is configured
Hi Horatiu, https://patchwork.ozlabs.org/patch/1104383/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] cmd: mii: Refactor some of the MII reg dump code
Hi Trent, https://patchwork.ozlabs.org/patch/1097645/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-net.git master
Hi Tom, These patches passed travis [1] and are ready for master. Thanks, -Joe [1] - https://travis-ci.org/jhershbe/u-boot/builds/559064493 The following changes since commit a9a3a37f92b072a56693ad665ab4c5cc73028d16: Merge tag 'u-boot-stm32-20190712' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm (2019-07-14 09:09:49 -0400) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to 0dc97fc3d8cd8c4154f63c9ea74f5e73ee48fa6c: net: macb: Add support for 1000-baseX (2019-07-15 13:32:26 -0500) Alex Marginean (2): net: introduce MDIO DM class for MDIO devices test: dm: add MDIO test Grygorii Strashko (3): arm64: dts: ti: k3-am65: add mcu cpsw node arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defs configs: am65x_evm_a53: enable networking Horatiu Vultur (2): net: mscc: serval: Remove delay when serdes is configured net: mscc: refactor mscc_miim Keerthy (2): driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addr net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver Radu Pirea (2): net: macb: Fixed reading MII_LPA register net: macb: Add support for 1000-baseX Trent Piepho (4): cmd: mii: Refactor some of the MII reg dump code cmd: mii: Add the standard 1000BASE-T registers net: phy: ti: Use default values for tx/rx delay and fifo size net: phy: ti: Fix clock output DT property Yinbo Zhu (1): net: phy: cortina: Use block layer to read from mmc arch/Kconfig | 2 + arch/arm/dts/k3-am65.dtsi| 2 + arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 170 ++ arch/sandbox/dts/test.dts| 4 + cmd/mdio.c | 5 + cmd/mii.c| 189 --- configs/am65x_evm_a53_defconfig | 6 + drivers/net/Kconfig | 23 + drivers/net/Makefile | 1 + drivers/net/macb.c | 8 +- drivers/net/mdio_sandbox.c | 92 drivers/net/mscc_eswitch/Makefile| 10 +- drivers/net/mscc_eswitch/jr2_switch.c| 119 +--- drivers/net/mscc_eswitch/luton_switch.c | 101 +--- drivers/net/mscc_eswitch/mscc_miim.c | 28 + drivers/net/mscc_eswitch/mscc_miim.h | 14 +- drivers/net/mscc_eswitch/ocelot_switch.c | 104 +--- drivers/net/mscc_eswitch/serval_switch.c | 103 +--- drivers/net/mscc_eswitch/servalt_switch.c| 102 +--- drivers/net/phy/cortina.c| 5 + drivers/net/phy/ti.c | 16 +- drivers/net/ti/Kconfig | 8 + drivers/net/ti/Makefile | 1 + drivers/net/ti/am65-cpsw-nuss.c | 792 +++ drivers/net/ti/cpsw_mdio.c | 4 +- drivers/net/ti/cpsw_mdio.h | 2 +- include/dm/uclass-id.h | 1 + include/miiphy.h | 49 ++ net/Makefile | 1 + net/mdio-uclass.c| 115 test/dm/Makefile | 1 + test/dm/mdio.c | 53 ++ 32 files changed, 1506 insertions(+), 625 deletions(-) create mode 100644 drivers/net/mdio_sandbox.c create mode 100644 drivers/net/ti/am65-cpsw-nuss.c create mode 100644 net/mdio-uclass.c create mode 100644 test/dm/mdio.c Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 8/8] Add support for the NXP LS1021A-TSN board
On Tue, 16 Jul 2019 at 01:20, Joe Hershberger wrote:
>
> On Mon, Jul 15, 2019 at 4:57 PM Vladimir Oltean wrote:
> >
> > Hi Joe,
> >
> > On Mon, 15 Jul 2019 at 22:17, Joe Hershberger
> > wrote:
> > >
> > > On Sun, Jun 23, 2019 at 12:53 PM Vladimir Oltean
> > > wrote:
> > > >
> > > > From: Jianchao Wang
> > > >
> > > > The LS1021A-TSN is a development board built by VVDN/Argonboards in
> > > > partnership with NXP.
> > > >
> > > > It features the LS1021A SoC and the first-generation SJA1105T Ethernet
> > > > switch for prototyping implementations of a subset of IEEE 802.1 TSN
> > > > standards.
> > > >
> > > > Supported boot media: microSD card (via SPL), QSPI flash.
> > > >
> > > > Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which
> > > > is 64 MB in size and has an erase sector size of 256KB (therefore,
> > > > flashing the RCW would erase part of U-boot).
> > > >
> > > > Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which
> > > > is only 32 MB in size but has an erase sector size of 64KB (therefore
> > > > the RCW image can be flashed without erasing U-boot).
> > > >
> > > > To avoid the problems above, the U-boot base address has been selected
> > > > at 0x10 (the start of the 5th 256KB erase sector), which works for
> > > > all board revisions. Actually 0x4 would have been enough, but
> > > > 0x10 is common for all Layerscape devices.
> > > >
> > > > eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but
> > > > SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is
> > > > disabled.
> > > >
> > > > Signed-off-by: Xiaoliang Yang
> > > > Signed-off-by: Mingkai Hu
> > > > Signed-off-by: Jianchao Wang
> > > > Signed-off-by: Changming Huang
> > > >
> > > > [Vladimir] Code taken from https://github.com/openil/u-boot (which
> > > > itself is mostly copied from ls1021a-iot) and adapted with the following
> > > > changes:
> > > >
> > > > - Add a008850 errata workaround
> > > > - Converted eTSEC, MMC to DM to avoid all build warnings
> > > > - Plugged in distro boot feature, including support for extlinux.conf
> > > > - Added defconfig for QSPI boot
> > > > - Added the board/freescale/ls1021atsn/README.rst for initial setup
> > > >
> > > > Signed-off-by: Vladimir Oltean
> > > > ---
>
> [ ... ]
>
> > > > +int board_early_init_f(void)
> > > > +{
> > > > + struct ccsr_scfg *scfg = (struct ccsr_scfg
> > > > *)CONFIG_SYS_FSL_SCFG_ADDR;
> > > > +
> > > > +#ifdef CONFIG_TSEC_ENET
> > > > + /* Clear BD & FR bits for big endian BD's and frame data (aka
> > > > set
> > >
> > > Nit: Multi-line comment format. I'm curious why checkpatch.pl doesn't
> > > catch this sometimes.
> > >
> >
> > What seems to be the problem with this? Do you prefer to see a first
> > line with just " /* "?
>
> Yes. See [1] and [2]. I tried to make the intent more clear at [2].
>
> [1] -
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst#n543
> [2] - http://www.denx.de/wiki/U-Boot/CodingStyle
>
Oh, I wasn't aware that the coding style for the Linux net-next
mailing list is the exception rather than the rule. Thanks for letting
me know.
> >
> > > > +* correct eTSEC endianness). This is crucial in ensuring that
> > > > it does
> > > > +* not report Data Parity Errors in its RX/TX FIFOs when
> > > > attempting to
> > > > +* send traffic.
> > > > +*/
> > > > + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
> > > > + /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
> > > > + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
> > > > +#endif
> > > > +
> > > > +#ifdef CONFIG_FSL_IFC
> > > > + init_early_memctl_regs();
> > > > +#endif
> > > > +
> > > > + arch_soc_init();
> > > > +
> > > > +#if defined(CONFIG_DEEP_SLEEP)
> > > > + if (is_warm_boot()) {
> > > > + timer_init();
> > > > + dram_init();
> > > > + }
> > > > +#endif
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +#ifdef CONFIG_SPL_BUILD
> > > > +void board_init_f(ulong dummy)
> > > > +{
> > > > + void (*second_uboot)(void);
> > > > +
> > > > + /* Clear the BSS */
> > > > + memset(__bss_start, 0, __bss_end - __bss_start);
> > > > +
> > > > + get_clocks();
> > > > +
> > > > +#if defined(CONFIG_DEEP_SLEEP)
> > > > + if (is_warm_boot())
> > > > + fsl_dp_disable_console();
> > > > +#endif
> > > > +
> > > > + preloader_console_init();
> > > > +
> > > > + dram_init();
> > > > +
> > > > + /* Allow OCRAM access permission as R/W */
> > > > +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
> > > > + enable_layerscape_ns_access();
> > > > + enable_layerscape_ns_access();
> > > > +#endif
> > > > +
> > > > + /*
> > > > +* if it is woken up from deep sleep, then jump to second
> > > > +* stage uboot and continue e
Re: [U-Boot] [PATCH 8/8] Add support for the NXP LS1021A-TSN board
On Mon, Jul 15, 2019 at 4:57 PM Vladimir Oltean wrote:
>
> Hi Joe,
>
> On Mon, 15 Jul 2019 at 22:17, Joe Hershberger wrote:
> >
> > On Sun, Jun 23, 2019 at 12:53 PM Vladimir Oltean wrote:
> > >
> > > From: Jianchao Wang
> > >
> > > The LS1021A-TSN is a development board built by VVDN/Argonboards in
> > > partnership with NXP.
> > >
> > > It features the LS1021A SoC and the first-generation SJA1105T Ethernet
> > > switch for prototyping implementations of a subset of IEEE 802.1 TSN
> > > standards.
> > >
> > > Supported boot media: microSD card (via SPL), QSPI flash.
> > >
> > > Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which
> > > is 64 MB in size and has an erase sector size of 256KB (therefore,
> > > flashing the RCW would erase part of U-boot).
> > >
> > > Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which
> > > is only 32 MB in size but has an erase sector size of 64KB (therefore
> > > the RCW image can be flashed without erasing U-boot).
> > >
> > > To avoid the problems above, the U-boot base address has been selected
> > > at 0x10 (the start of the 5th 256KB erase sector), which works for
> > > all board revisions. Actually 0x4 would have been enough, but
> > > 0x10 is common for all Layerscape devices.
> > >
> > > eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but
> > > SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is
> > > disabled.
> > >
> > > Signed-off-by: Xiaoliang Yang
> > > Signed-off-by: Mingkai Hu
> > > Signed-off-by: Jianchao Wang
> > > Signed-off-by: Changming Huang
> > >
> > > [Vladimir] Code taken from https://github.com/openil/u-boot (which
> > > itself is mostly copied from ls1021a-iot) and adapted with the following
> > > changes:
> > >
> > > - Add a008850 errata workaround
> > > - Converted eTSEC, MMC to DM to avoid all build warnings
> > > - Plugged in distro boot feature, including support for extlinux.conf
> > > - Added defconfig for QSPI boot
> > > - Added the board/freescale/ls1021atsn/README.rst for initial setup
> > >
> > > Signed-off-by: Vladimir Oltean
> > > ---
[ ... ]
> > > +int board_early_init_f(void)
> > > +{
> > > + struct ccsr_scfg *scfg = (struct ccsr_scfg
> > > *)CONFIG_SYS_FSL_SCFG_ADDR;
> > > +
> > > +#ifdef CONFIG_TSEC_ENET
> > > + /* Clear BD & FR bits for big endian BD's and frame data (aka set
> >
> > Nit: Multi-line comment format. I'm curious why checkpatch.pl doesn't
> > catch this sometimes.
> >
>
> What seems to be the problem with this? Do you prefer to see a first
> line with just " /* "?
Yes. See [1] and [2]. I tried to make the intent more clear at [2].
[1] -
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst#n543
[2] - http://www.denx.de/wiki/U-Boot/CodingStyle
>
> > > +* correct eTSEC endianness). This is crucial in ensuring that it
> > > does
> > > +* not report Data Parity Errors in its RX/TX FIFOs when
> > > attempting to
> > > +* send traffic.
> > > +*/
> > > + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
> > > + /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
> > > + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
> > > +#endif
> > > +
> > > +#ifdef CONFIG_FSL_IFC
> > > + init_early_memctl_regs();
> > > +#endif
> > > +
> > > + arch_soc_init();
> > > +
> > > +#if defined(CONFIG_DEEP_SLEEP)
> > > + if (is_warm_boot()) {
> > > + timer_init();
> > > + dram_init();
> > > + }
> > > +#endif
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +#ifdef CONFIG_SPL_BUILD
> > > +void board_init_f(ulong dummy)
> > > +{
> > > + void (*second_uboot)(void);
> > > +
> > > + /* Clear the BSS */
> > > + memset(__bss_start, 0, __bss_end - __bss_start);
> > > +
> > > + get_clocks();
> > > +
> > > +#if defined(CONFIG_DEEP_SLEEP)
> > > + if (is_warm_boot())
> > > + fsl_dp_disable_console();
> > > +#endif
> > > +
> > > + preloader_console_init();
> > > +
> > > + dram_init();
> > > +
> > > + /* Allow OCRAM access permission as R/W */
> > > +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
> > > + enable_layerscape_ns_access();
> > > + enable_layerscape_ns_access();
> > > +#endif
> > > +
> > > + /*
> > > +* if it is woken up from deep sleep, then jump to second
> > > +* stage uboot and continue executing without recopying
> >
> > U-Boot
> >
> > > +* it from SD since it has already been reserved in memory
> > > +* in last boot.
> > > +*/
> > > + if (is_warm_boot()) {
> > > + second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
> > > + second_uboot();
> > > + }
> > > +
> > > + board_init_r(NULL, 0);
> > > +}
> > > +#endif
> > > +
> > > +int board_init(void)
> > > +{
> > > +#ifndef CONFIG_SYS_FSL_NO_SERDE
Re: [U-Boot] [PATCH 2/8] net: tsec: Fix offset of MDIO registers for DM_ETH
Hi Joe,
On Mon, 15 Jul 2019 at 21:00, Joe Hershberger wrote:
>
> On Sun, Jun 23, 2019 at 12:51 PM Vladimir Oltean wrote:
> >
> > By convention, the eTSEC MDIO controller nodes are defined in DT at
> > 0x2d24000 and 0x2d5, but actually U-boot does not touch the
> > interrupt portion of the register map (MDIO_IEVENTM, MDIO_IMASKM,
> > MDIO_EMAPM).
> >
> > That leaves only the MDIO bus registers (MDIO_MIIMCFG, MDIO_MIIMCOM,
> > MDIO_MIIMADD, MDIO_MIIMADD, MDIO_MIIMCON, MDIO_MIIMSTAT) which start at
> > the 0x520 offset.
> >
> > So shift the DT-defined register map by the offset of MDIO_MIIMCFG when
> > mapping the MDIO bus registers.
> >
> > Signed-off-by: Vladimir Oltean
>
> Acked-by: Joe Hershberger
>
> > ---
> > drivers/net/tsec.c | 13 +++--
> > include/tsec.h | 4 +++-
> > 2 files changed, 10 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
> > index 53eb5470f4c8..576398676af7 100644
> > --- a/drivers/net/tsec.c
> > +++ b/drivers/net/tsec.c
> > @@ -801,6 +801,7 @@ int tsec_probe(struct udevice *dev)
> > u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
> > ofnode parent;
> > const char *phy_mode;
> > + fdt_addr_t reg;
> > int ret;
> >
> > pdata->iobase = (phys_addr_t)dev_read_addr(dev);
> > @@ -817,15 +818,15 @@ int tsec_probe(struct udevice *dev)
> > }
> >
> > parent = ofnode_get_parent(phandle_args.node);
> > - if (ofnode_valid(parent)) {
> > - int reg = ofnode_get_addr_index(parent, 0);
> > -
> > - priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
> > - } else {
> > - debug("No parent node for PHY?\n");
> > + if (!ofnode_valid(parent)) {
> > + printf("No parent node for PHY?\n");
> > return -ENOENT;
> > }
> >
> > + reg = ofnode_get_addr_index(parent, 0);
> > + priv->phyregs_sgmii = (struct tsec_mii_mng *)
> > + (reg + TSEC_MDIO_REGS_OFFSET);
>
> I'm surprised not to see a .dts change in this patch as well or some
> other consumer of this phyregs_sgmii member.
>
This surprises me as well, to be honest.
Actually Bin Meng's patchset to convert the TSEC driver to DM never
got completely merged. I suppose the LS1021A-TWR conversion was sort
of mechanical and probably not tested on hardware, otherwise I can't
explain. There is no DT patch because this portion of the code never
worked. The DM version of the TSEC driver had no (upstream?) users.
>
> > +
> > ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
> > &phandle_args);
> > if (ret == 0)
> > diff --git a/include/tsec.h b/include/tsec.h
> > index e90095121bdd..b17fa957df5b 100644
> > --- a/include/tsec.h
> > +++ b/include/tsec.h
> > @@ -17,6 +17,8 @@
> > #include
> > #include
> >
> > +#define TSEC_MDIO_REGS_OFFSET 0x520
> > +
> > #ifndef CONFIG_DM_ETH
> >
> > #ifdef CONFIG_ARCH_LS1021A
> > @@ -27,7 +29,7 @@
> > #define TSEC_MDIO_OFFSET 0x01000
> > #endif
> >
> > -#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
> > +#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET)
> >
> > #define TSEC_GET_REGS(num, offset) \
> > (struct tsec __iomem *)\
> > --
> > 2.17.1
> >
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
Thanks,
-Vladimir
___
U-Boot mailing list
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Re: [U-Boot] [PATCH 8/8] Add support for the NXP LS1021A-TSN board
Hi Joe, On Mon, 15 Jul 2019 at 22:17, Joe Hershberger wrote: > > On Sun, Jun 23, 2019 at 12:53 PM Vladimir Oltean wrote: > > > > From: Jianchao Wang > > > > The LS1021A-TSN is a development board built by VVDN/Argonboards in > > partnership with NXP. > > > > It features the LS1021A SoC and the first-generation SJA1105T Ethernet > > switch for prototyping implementations of a subset of IEEE 802.1 TSN > > standards. > > > > Supported boot media: microSD card (via SPL), QSPI flash. > > > > Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which > > is 64 MB in size and has an erase sector size of 256KB (therefore, > > flashing the RCW would erase part of U-boot). > > > > Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which > > is only 32 MB in size but has an erase sector size of 64KB (therefore > > the RCW image can be flashed without erasing U-boot). > > > > To avoid the problems above, the U-boot base address has been selected > > at 0x10 (the start of the 5th 256KB erase sector), which works for > > all board revisions. Actually 0x4 would have been enough, but > > 0x10 is common for all Layerscape devices. > > > > eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but > > SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is > > disabled. > > > > Signed-off-by: Xiaoliang Yang > > Signed-off-by: Mingkai Hu > > Signed-off-by: Jianchao Wang > > Signed-off-by: Changming Huang > > > > [Vladimir] Code taken from https://github.com/openil/u-boot (which > > itself is mostly copied from ls1021a-iot) and adapted with the following > > changes: > > > > - Add a008850 errata workaround > > - Converted eTSEC, MMC to DM to avoid all build warnings > > - Plugged in distro boot feature, including support for extlinux.conf > > - Added defconfig for QSPI boot > > - Added the board/freescale/ls1021atsn/README.rst for initial setup > > > > Signed-off-by: Vladimir Oltean > > --- > > arch/arm/Kconfig | 14 + > > arch/arm/dts/Makefile | 2 +- > > arch/arm/dts/ls1021a-tsn.dts | 77 > > board/freescale/ls1021atsn/Kconfig| 18 + > > board/freescale/ls1021atsn/MAINTAINERS| 8 + > > board/freescale/ls1021atsn/Makefile | 3 + > > board/freescale/ls1021atsn/README.rst | 96 + > > board/freescale/ls1021atsn/ls1021atsn.c | 291 +++ > > board/freescale/ls1021atsn/ls102xa_pbi.cfg| 15 + > > board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg | 8 + > > configs/ls1021atsn_qspi_defconfig | 76 > > configs/ls1021atsn_sdcard_defconfig | 85 + > > include/configs/ls1021atsn.h | 346 ++ > > 13 files changed, 1038 insertions(+), 1 deletion(-) > > create mode 100644 arch/arm/dts/ls1021a-tsn.dts > > create mode 100644 board/freescale/ls1021atsn/Kconfig > > create mode 100644 board/freescale/ls1021atsn/MAINTAINERS > > create mode 100644 board/freescale/ls1021atsn/Makefile > > create mode 100644 board/freescale/ls1021atsn/README.rst > > create mode 100644 board/freescale/ls1021atsn/ls1021atsn.c > > create mode 100644 board/freescale/ls1021atsn/ls102xa_pbi.cfg > > create mode 100644 board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg > > create mode 100644 configs/ls1021atsn_qspi_defconfig > > create mode 100644 configs/ls1021atsn_sdcard_defconfig > > create mode 100644 include/configs/ls1021atsn.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 01ff57cf1bec..5edac7ea2bd5 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -1327,6 +1327,19 @@ config TARGET_LS1021ATWR > > select SUPPORT_SPL > > imply SCSI > > > > +config TARGET_LS1021ATSN > > + bool "Support ls1021atsn" > > + select ARCH_LS1021A > > + select ARCH_SUPPORT_PSCI > > + select BOARD_EARLY_INIT_F > > + select BOARD_LATE_INIT > > + select CPU_V7A > > + select CPU_V7_HAS_NONSEC > > + select CPU_V7_HAS_VIRT > > + select LS1_DEEP_SLEEP > > + select SUPPORT_SPL > > + imply SCSI > > + > > config TARGET_LS1021AIOT > > bool "Support ls1021aiot" > > select ARCH_LS1021A > > @@ -1693,6 +1706,7 @@ source "board/freescale/ls1028a/Kconfig" > > source "board/freescale/ls1021aqds/Kconfig" > > source "board/freescale/ls1043aqds/Kconfig" > > source "board/freescale/ls1021atwr/Kconfig" > > +source "board/freescale/ls1021atsn/Kconfig" > > source "board/freescale/ls1021aiot/Kconfig" > > source "board/freescale/ls1046aqds/Kconfig" > > source "board/freescale/ls1043ardb/Kconfig" > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > > index 528fb909d5b0..28590b0c5530 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -325,7 +325,7 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb > > dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ > >
Re: [U-Boot] [PATCH v1 2/2] ARM: dts: imx6ull-colibri: pre-reloc for uart pinmux modes
Hi Igor,
On Mon, Jul 15, 2019 at 11:19 AM Igor Opaniuk wrote:
> diff --git a/arch/arm/dts/imx6ull-colibri.dts
> b/arch/arm/dts/imx6ull-colibri.dts
> index 6c847ab792..8cc67a1fa7 100644
> --- a/arch/arm/dts/imx6ull-colibri.dts
> +++ b/arch/arm/dts/imx6ull-colibri.dts
> @@ -458,6 +458,7 @@
> };
>
> pinctrl_uart1: uart1-grp {
> + u-boot,dm-pre-reloc;
Shouldn't this U-Boot specific property go to
arch/arm/dts/imx6ull-colibri-uboot.dtsi instead?
This way you could keep arch/arm/dts/imx6ull-colibri.dts in sync with Linux.
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Re: [U-Boot] [PATCH 1/6] net: macb: sync header definitions as taken from Linux
On Mon, Jul 15, 2019 at 3:26 PM Ramon Fried wrote: > > On Mon, Jul 15, 2019 at 11:19 PM Ramon Fried wrote: > > > > On Mon, Jul 15, 2019 at 9:31 PM Joe Hershberger > > wrote: > > > > > > On Tue, Jun 11, 2019 at 10:51 AM Ramon Fried wrote: > > > > > > > > Few registers and bits were added by Cadence and > > > > they were not updated in the headers. > > > > Take the latest definitions as defined in Linux > > > > header (5.1) that also includes some comments > > > > about existing registers. > > > > > > > > One register was improperly named (UR), fix that. > > > > > > This is breaking the build. "UR" is still referred to in > > > drivers/net/macb.c line 805. > > > > > > Did you build test this? > > Well of course, but apparently I screwed this one in rebasing, prior to > > submit. > > Didn't run buildman afterwards. sorry. > > Will issue a revised patchset. > > Sorry. > > Ramon. > Actually, now that I look at this. it looks fine. the patch replaces > the line you mentioned: > https://patchwork.ozlabs.org/patch/1114041/ > Can take a look ? It addresses some of them, but not the ones a few lines below. > > > > > > > > > > > Signed-off-by: Ramon Fried > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] net: macb: sync header definitions as taken from Linux
On Mon, Jul 15, 2019 at 11:19 PM Ramon Fried wrote: > > On Mon, Jul 15, 2019 at 9:31 PM Joe Hershberger > wrote: > > > > On Tue, Jun 11, 2019 at 10:51 AM Ramon Fried wrote: > > > > > > Few registers and bits were added by Cadence and > > > they were not updated in the headers. > > > Take the latest definitions as defined in Linux > > > header (5.1) that also includes some comments > > > about existing registers. > > > > > > One register was improperly named (UR), fix that. > > > > This is breaking the build. "UR" is still referred to in > > drivers/net/macb.c line 805. > > > > Did you build test this? > Well of course, but apparently I screwed this one in rebasing, prior to > submit. > Didn't run buildman afterwards. sorry. > Will issue a revised patchset. > Sorry. > Ramon. Actually, now that I look at this. it looks fine. the patch replaces the line you mentioned: https://patchwork.ozlabs.org/patch/1114041/ Can take a look ? > > > > > > > > Signed-off-by: Ramon Fried ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] net: macb: sync header definitions as taken from Linux
On Mon, Jul 15, 2019 at 9:31 PM Joe Hershberger wrote: > > On Tue, Jun 11, 2019 at 10:51 AM Ramon Fried wrote: > > > > Few registers and bits were added by Cadence and > > they were not updated in the headers. > > Take the latest definitions as defined in Linux > > header (5.1) that also includes some comments > > about existing registers. > > > > One register was improperly named (UR), fix that. > > This is breaking the build. "UR" is still referred to in > drivers/net/macb.c line 805. > > Did you build test this? Well of course, but apparently I screwed this one in rebasing, prior to submit. Didn't run buildman afterwards. sorry. Will issue a revised patchset. Sorry. Ramon. > > > > > Signed-off-by: Ramon Fried ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] test.py failure in test_ut[ut_dm_pci_ep_base]
On Mon, Jul 15, 2019 at 6:25 PM Tom Rini wrote: > On Mon, Jul 15, 2019 at 09:14:03AM -0600, Stephen Warren wrote: > > Running test.py on sandbox now fails test_ut[ut_dm_pci_ep_base] with: > > > > => ut dm pci_ep_base > > Test: dm_test_pci_ep_base: pci_ep.c > > [Errno 5] Input/output error > > > > I believe that last line is printed by the test harness; presumably the > > sandbox process crashed, but I haven't checked that. > > > > I imagine this was introduced by commit "test: pci_ep: add basic pci_ep > > tests". > > > > I do see later commit "test: Disable pci_ep test for now" by Tom, but for > > some reason the test is still running after that; my test system last > built > > a9a3a37f92b0 and there's still a failure. > > To be clear, my commit only removes it from sandbox from travis runs and > a similar '-k not pci' would be needed in other hooks. Ramon is working > on the problem now. > Hi, here's the fix. sorry for that one (my uninitialized memory was zeros :) ) https://patchwork.ozlabs.org/patch/1132255/ > -- > Tom > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] drivers: net: driver for MDIO muxes controlled over I2C
On Fri, Jul 12, 2019 at 9:21 AM Alex Marginean wrote: > > This driver is used for MDIO muxes driven over I2C. This is currently > used on Freescale LS1028A QDS board, on which the physical MDIO MUX is > controlled by an on-board FPGA which in turn is configured through I2C. > > Signed-off-by: Alex Marginean > --- > > Depends on https://patchwork.ozlabs.org/project/uboot/list/?series=119124 Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] pci_ep: fix wrong addressing to barno
barno was mistakely readed from the target structure,
resulting in undefined behavious depending on the previous memory
content. fix that.
Fixes: bb413337826e ("pci_ep: add pci endpoint sandbox driver")
Signed-off-by: Ramon Fried
---
drivers/pci_endpoint/sandbox-pci_ep.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/pci_endpoint/sandbox-pci_ep.c
b/drivers/pci_endpoint/sandbox-pci_ep.c
index 0258433d8f..ca8871fc36 100644
--- a/drivers/pci_endpoint/sandbox-pci_ep.c
+++ b/drivers/pci_endpoint/sandbox-pci_ep.c
@@ -88,9 +88,7 @@ static int sandbox_read_bar(struct udevice *dev, uint fn,
if (fn > 0)
return -ENODEV;
- bar_idx = ep_bar->barno;
-
- memcpy(ep_bar, &priv->bars[bar_idx], sizeof(*ep_bar));
+ memcpy(ep_bar, &priv->bars[barno], sizeof(*ep_bar));
return 0;
}
--
2.22.0
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[U-Boot] [PATCH] net: designware: use 'phy_connect' instead of open coded
Using 'phy_connect' instead of 'phy_find_by_mask' and 'phy_connect_dev'
both deduplicates code and adds support for 'fixed-link'.
Signed-off-by: Simon Goldschmidt
---
drivers/net/designware.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 2c5d9560c5..e08f459cf4 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -480,18 +480,16 @@ static int _dw_free_pkt(struct dw_eth_dev *priv)
static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
struct phy_device *phydev;
- int mask = 0x, ret;
+ int phy_addr = -1, ret;
#ifdef CONFIG_PHY_ADDR
- mask = 1 << CONFIG_PHY_ADDR;
+ phy_addr = CONFIG_PHY_ADDR;
#endif
- phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+ phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev);
-
phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
ret = phy_set_supported(phydev, priv->max_speed);
--
2.20.1
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[U-Boot] [PATCH v4 3/4] sysreset: socfpga: stratix10: add sysreset driver
This adds a UCLASS_SYSRESET sysreset driver for socfgpa stratix10.
Signed-off-by: Simon Goldschmidt
---
Changes in v4:
- adapt MAINTAINERS to the new file
Changes in v3:
- moved socfpga stratix sysreset driver to extra patch
Changes in v2: None
MAINTAINERS | 2 +-
drivers/sysreset/Kconfig| 7 ++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_socfpga_s10.c | 29 +
4 files changed, 38 insertions(+), 1 deletion(-)
create mode 100644 drivers/sysreset/sysreset_socfpga_s10.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 8031cc92f5..495510863f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -94,7 +94,7 @@ M:Simon Goldschmidt
S: Maintainted
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git
F: arch/arm/mach-socfpga/
-F: drivers/sysreset/sysreset_socfpga.c
+F: drivers/sysreset/sysreset_socfpga*
ARM AMLOGIC SOC SUPPORT
M: Neil Armstrong
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 4ca635742f..90c41ab44d 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -62,6 +62,13 @@ config SYSRESET_SOCFPGA
This enables the system reset driver support for Intel SOCFPGA SoCs
(Cyclone 5, Arria 5 and Arria 10).
+config SYSRESET_SOCFPGA_S10
+ bool "Enable support for Intel SOCFPGA Stratix 10"
+ depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10
+ help
+ This enables the system reset driver support for Intel SOCFPGA
+ Stratix SoCs.
+
config SYSRESET_TI_SCI
bool "TI System Control Interface (TI SCI) system reset driver"
depends on TI_SCI_PROTOCOL
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 180e46301d..cf01492295 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
+obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
diff --git a/drivers/sysreset/sysreset_socfpga_s10.c
b/drivers/sysreset/sysreset_socfpga_s10.c
new file mode 100644
index 00..9837aadf64
--- /dev/null
+++ b/drivers/sysreset/sysreset_socfpga_s10.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Pepperl+Fuchs
+ * Simon Goldschmidt
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static int socfpga_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+ mbox_reset_cold();
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops socfpga_sysreset = {
+ .request = socfpga_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_socfpga) = {
+ .id = UCLASS_SYSRESET,
+ .name = "socfpga_sysreset",
+ .ops= &socfpga_sysreset,
+};
--
2.20.1
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[U-Boot] [PATCH v4 2/4] sysreset: socfpga: gen5: add sysreset driver
This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5.
Signed-off-by: Simon Goldschmidt
---
Changes in v4:
- change BIT() instead of open coded shift
- add drivers/sysreset/sysreset_socfpga.c to MAINTAINERS
Changes in v3:
- moved socfpga gen5 sysreset driver to extra patch
Changes in v2: None
MAINTAINERS | 1 +
drivers/sysreset/Kconfig| 7
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_socfpga.c | 56 +
4 files changed, 65 insertions(+)
create mode 100644 drivers/sysreset/sysreset_socfpga.c
diff --git a/MAINTAINERS b/MAINTAINERS
index bc67c49965..8031cc92f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -94,6 +94,7 @@ M:Simon Goldschmidt
S: Maintainted
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git
F: arch/arm/mach-socfpga/
+F: drivers/sysreset/sysreset_socfpga.c
ARM AMLOGIC SOC SUPPORT
M: Neil Armstrong
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index a69b74cee2..4ca635742f 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -55,6 +55,13 @@ config SYSRESET_PSCI
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
+config SYSRESET_SOCFPGA
+ bool "Enable support for Intel SOCFPGA family"
+ depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 ||
TARGET_SOCFPGA_ARRIA10)
+ help
+ This enables the system reset driver support for Intel SOCFPGA SoCs
+ (Cyclone 5, Arria 5 and Arria 10).
+
config SYSRESET_TI_SCI
bool "TI System Control Interface (TI SCI) system reset driver"
depends on TI_SCI_PROTOCOL
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 8e1c845dfe..180e46301d 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
diff --git a/drivers/sysreset/sysreset_socfpga.c
b/drivers/sysreset/sysreset_socfpga.c
new file mode 100644
index 00..d6c26a5b23
--- /dev/null
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Pepperl+Fuchs
+ * Simon Goldschmidt
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct socfpga_sysreset_data {
+ struct socfpga_reset_manager *rstmgr_base;
+};
+
+static int socfpga_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ struct socfpga_sysreset_data *data = dev_get_priv(dev);
+
+ switch (type) {
+ case SYSRESET_WARM:
+ writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+ &data->rstmgr_base->ctrl);
+ break;
+ case SYSRESET_COLD:
+ writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
+ &data->rstmgr_base->ctrl);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+ return -EINPROGRESS;
+}
+
+static int socfpga_sysreset_probe(struct udevice *dev)
+{
+ struct socfpga_sysreset_data *data = dev_get_priv(dev);
+
+ data->rstmgr_base = devfdt_get_addr_ptr(dev);
+ return 0;
+}
+
+static struct sysreset_ops socfpga_sysreset = {
+ .request = socfpga_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_socfpga) = {
+ .id = UCLASS_SYSRESET,
+ .name = "socfpga_sysreset",
+ .priv_auto_alloc_size = sizeof(struct socfpga_sysreset_data),
+ .ops= &socfpga_sysreset,
+ .probe = socfpga_sysreset_probe,
+};
--
2.20.1
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[U-Boot] [PATCH v4 4/4] sysreset: add support for socfpga sysreset
This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga
to a UCLASS_SYSRESET based dm driver.
A side effect is that gen5 and a10 can now select between cold and warm
reset.
Signed-off-by: Simon Goldschmidt
---
Changes in v4:
- adapt to patch that separates drivers/sysreset from drivers/misc
for SPL: select SPL_SYSRESET, not SPL_DRIVERS_MISC_SUPPORT
Changes in v3:
- this patch enables the new drivers and drops the ad-hoc code
Changes in v2:
- adapt to patch that separates drivers/sysreset from drivers/misc
for SPL: select SPL_SYSRESET_SUPPORT, not SPL_DRIVERS_MISC_SUPPORT
- separate gen5/a10 driver from s10 driver
- as sysreset is a function of rstmgr, bind the sysreset drivers
from rstmgr to get the base address instead of hardcoding it
arch/arm/Kconfig | 4 +++
arch/arm/mach-socfpga/Makefile| 1 -
arch/arm/mach-socfpga/reset_manager.c | 41 ---
drivers/reset/reset-socfpga.c | 19 +
4 files changed, 23 insertions(+), 42 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/reset_manager.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ab9cbe832..d1da98e111 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -894,10 +894,14 @@ config ARCH_SOCFPGA
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
select SPL_SERIAL_SUPPORT
+ select SPL_SYSRESET
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
select SYS_NS16550
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+ select SYSRESET
+ select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+ select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e66720447f..fc1181cb27 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,7 +8,6 @@
obj-y += board.o
obj-y += clock_manager.o
obj-y += misc.o
-obj-y += reset_manager.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o
diff --git a/arch/arm/mach-socfpga/reset_manager.c
b/arch/arm/mach-socfpga/reset_manager.c
deleted file mode 100644
index e0a01ed07a..00
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Altera Corporation
- */
-
-
-#include
-#include
-#include
-
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
-#endif
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
- /* request a warm reset */
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
- puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
- mbox_reset_cold();
-#else
- writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
- &reset_manager_base->ctrl);
-#endif
- /*
-* infinite loop here as watchdog will trigger and reset
-* the processor
-*/
- while (1)
- ;
-}
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index ee4cbcb02f..822a3fe265 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -14,6 +14,7 @@
#include
#include
+#include
#include
#include
#include
@@ -130,6 +131,23 @@ static int socfpga_reset_remove(struct udevice *dev)
return 0;
}
+static int socfpga_reset_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *sys_child;
+
+ /*
+* The sysreset driver does not have a device node, so bind it here.
+* Bind it to the node, too, so that it can get its base address.
+*/
+ ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
+dev->node, &sys_child);
+ if (ret)
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+
+ return 0;
+}
+
static const struct udevice_id socfpga_reset_match[] = {
{ .compatible = "altr,rst-mgr" },
{ /* sentinel */ },
@@ -139,6 +157,7 @@ U_BOOT_DRIVER(socfpga_reset) = {
.name = "socfpga-reset",
.id = UCLASS_RESET,
.of_match = socfpga_reset_match,
+ .bind = socfpga_reset_bind,
.probe = socfpga_reset_probe,
.priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
.ops = &socfpga_reset_ops,
--
2.20.1
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[U-Boot] [PATCH v4 1/4] arm: socfpga: rst: add register definition for cold reset
This adds a define for the bit in rstmgr's ctrl regiser that issues a cold reset (we had a define for the warm reset bit only) in preparation for a proper sysrese driver. Signed-off-by: Simon Goldschmidt Series changes: 2 - separate this patch to the register descriptions from the actual sysreset driver patch --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/mach-socfpga/include/mach/reset_manager.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 42beaecdd6..6ad037e325 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -11,6 +11,7 @@ void reset_cpu(ulong addr); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); +#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 /* -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3] spl: kconfig: separate sysreset and firmware drivers from misc
This adds separate kconfig options for drivers/sysreset and drivers/firmware. Up to now, CONFIG_SPL_DRIVERS_MISC_SUPPORT added drivers/misc to SPL build but also added drivers/firmware and drivers/sysreset at the same time. Since that is confusing, this patch uses CONFIG_SPL_SYSRESET for drivers/sysreset and adds CONFIG_SPL_FIRMWARE for drivers/firmware (and accordingly for the TPL options). CONFIG_SPL_DRIVERS_MISC_SUPPORT stays for including drivers/misc into the SPL build (and accordingly for TPL) since there are boards using non-DM (non UCLASS_MISC) files from drivers/misc. Such boards don't have CONFIG_SPL_MISC enabled, so cannot use this to include drivers/misc into the SPL build. Signed-off-by: Simon Goldschmidt --- Changes in v3: - Revert to keeping CONFIG_SPL_DRIVERS_MISC_SUPPORT as there are boards that need to include drivers/misc without UCLASS_MISC being enabled - Only CONFIG_SPL_FIRMWARE is added as new config symbol. To ensure no arch Kconfig files need to be changed, add dependencies to ensure this is enabled where required. Changes in v2: - adapt config names to match the non-SPL config options: - changed CONFIG_SPL_SYSRESET_SUPPORT to CONFIG_SPL_SYSRESET - changed CONFIG_SPL_DRIVERS_FIRMWARE_SUPPORT to CONFIG_SPL_FIRMWARE - changed CONFIG_SPL_DRIVERS_MISC_SUPPORT to CONFIG_SPL_MISC configs/evb-rk3036_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/Makefile | 7 ++- drivers/firmware/Kconfig | 7 ++- drivers/sysreset/Kconfig | 1 + 6 files changed, 16 insertions(+), 2 deletions(-) diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 5e6bb54551..0eb7384340 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_PINCTRL=y # CONFIG_SPL_DM_SERIAL is not set +# CONFIG_SPL_SYSRESET is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 921af0d476..a76ae9d326 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -49,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set +# CONFIG_SPL_SYSRESET is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 27034cfaa9..5b7dae9be6 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -3,6 +3,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_FIRMWARE=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_BOOTSTAGE_STASH_ADDR=0x0 diff --git a/drivers/Makefile b/drivers/Makefile index 603aa98590..1f225bc2ca 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -4,7 +4,6 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ obj-$(CONFIG_$(SPL_TPL_)GPIO_SUPPORT) += gpio/ -obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/ obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ obj-$(CONFIG_$(SPL_TPL_)LED) += led/ @@ -58,6 +57,9 @@ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/ obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/ obj-$(CONFIG_SPL_THERMAL) += thermal/ +obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/ +obj-$(CONFIG_SPL_SYSRESET) += sysreset/ +obj-$(CONFIG_SPL_FIRMWARE) +=firmware/ endif endif @@ -65,6 +67,9 @@ endif ifdef CONFIG_TPL_BUILD obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ +obj-$(CONFIG_TPL_DRIVERS_MISC_SUPPORT) += misc/ +obj-$(CONFIG_TPL_SYSRESET) += sysreset/ +obj-$(CONFIG_TPL_FIRMWARE) += firmware/ endif diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 7d8f161b26..873bc8c796 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -1,9 +1,13 @@ config FIRMWARE bool "Enable Firmware driver support" +config SPL_FIRMWARE + bool "Enable Firmware driver support in SPL" + depends on FIRMWARE + config SPL_ARM_PSCI_FW bool - select FIRMWARE + select SPL_FIRMWARE config ARM_PSCI_FW bool @@ -13,6 +17,7 @@ config TI_SCI_PROTOCOL tristate "TI System Control Interface (TISCI) Message Protocol" depends on K3_SEC_PROXY select FIRMWARE + select SPL_FIRMWARE if SPL help TI System Control Interface (TISCI) Message Protocol is used to manage compute systems such as ARM, DSP etc with the system controller in diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 30aed2c4c1..a69b74cee2 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -50,6 +50,7 @@ config SYSRESET_MICROB
Re: [U-Boot] [PATCH] env: ti: boot: Use ttyS2 instead of ttyO2
On 7/12/19 1:38 PM, Sam Protsenko wrote: > ttyO2 console enables legacy CONFIG_SERIAL_OMAP driver in kernel. > Nowadays it's preferred to use the generic CONFIG_SERIAL_8250_OMAP > driver, which being enabled via ttyS2 console. Both drivers are enabled > in multi_v7_defconfig and in omap2plus_defconfig, for compatibility > reasons. Let's switch to ttyS2 console, to be sure that standard 8250 > serial driver is used. > > Similar behavior can be also achieved by enabling > CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP option in kernel, but it's better not > to rely on that, as it can be disabled or removed after transitional > period. > > Right now on DRA7/AM57x platforms the 8250-omap driver is being probed > first, and omap-serial driver is only probed if the first one failed. > It can be seen from uart3 definition in arch/arm/boot/dts/dra7-l4.dtsi: > > compatible = "ti,dra742-uart", "ti,omap4-uart"; > > So the kernel already uses 8250 driver. This change basically allows > kernel developers to throw away the omap-serial driver and associated > compatibility options. Similar discussions [1,2] have started several > years ago, so it should be safe to do that now. > > [1] https://patchwork.kernel.org/patch/6198471/ > [2] > http://processors.wiki.ti.com/index.php/Sitara_Linux_UART_-_Switching_to_8250_Driver > > Signed-off-by: Sam Protsenko > --- > Changes in v2: > - use ttyS also in AM57x EVM and in DRA7xx EVM configs > > include/configs/am57xx_evm.h | 2 +- > include/configs/dra7xx_evm.h | 4 ++-- > include/environment/ti/boot.h | 2 +- > 3 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h > index 45fd21878c..e181b30564 100644 > --- a/include/configs/am57xx_evm.h > +++ b/include/configs/am57xx_evm.h > @@ -24,7 +24,7 @@ > > #define CONFIG_SYS_BOOTM_LEN SZ_64M > > -#define CONSOLEDEV "ttyO2" > +#define CONSOLEDEV "ttyS2" > #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has > UART0 */ > #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ > #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ > diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h > index 9c8141de2e..7ec6e691c7 100644 > --- a/include/configs/dra7xx_evm.h > +++ b/include/configs/dra7xx_evm.h > @@ -26,9 +26,9 @@ > #endif > > #if (CONFIG_CONS_INDEX == 1) This CONFIG_CONS_INDEX is not enabled for this platform, meaning the non-default console is chosen by default, it's not caused by this patch but while you are here could you fix that up? Just set: #define CONSOLEDEV "ttyS0" and drop all the #ifdef stuff, makes things a bit more clean. (and prevents a conflict with a patch I was going to send for the same) Andrew > -#define CONSOLEDEV "ttyO0" > +#define CONSOLEDEV "ttyS0" > #elif (CONFIG_CONS_INDEX == 3) > -#define CONSOLEDEV "ttyO2" > +#define CONSOLEDEV "ttyS2" > #endif > #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has > UART0 */ > #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ > diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h > index 01b2981c5b..22206b9467 100644 > --- a/include/environment/ti/boot.h > +++ b/include/environment/ti/boot.h > @@ -10,7 +10,7 @@ > #define __TI_BOOT_H > > #ifndef CONSOLEDEV > -#define CONSOLEDEV "ttyO2" > +#define CONSOLEDEV "ttyS2" > #endif > > #define VBMETA_PART_SIZE (64 * 1024) > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/2] pinctrl: nxp: mx6: DM_FLAG_PRE_RELOC by default
Hi Igor,
On Mon, Jul 15, 2019 at 11:20 AM Igor Opaniuk wrote:
>
> From: Igor Opaniuk
>
> For Colibri iMX6ULL we have to set pinmux configuration ASAP (ideally
> before relocation) to get serial console working. Without this we miss
> almost the half of output (U-boot version, CPU defails, Reset cause,
> DRAM details etc.).
>
> To achieve this we need to force pinctrl-mx6 to get probed before
> relocation. Setting pinmux configuration for UART before was done
> in board_early_init_f().
>
> Fixes: cd69e8ef9b ("colibri-imx6ull: migrate pinctrl and regulators to
> dtb/dm")
> Signed-off-by: Igor Opaniuk
> ---
>
> drivers/pinctrl/nxp/pinctrl-imx6.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c
> b/drivers/pinctrl/nxp/pinctrl-imx6.c
> index 0c1e7a9c05..aafa3057ad 100644
> --- a/drivers/pinctrl/nxp/pinctrl-imx6.c
> +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
> @@ -49,7 +49,5 @@ U_BOOT_DRIVER(imx6_pinctrl) = {
> .remove = imx_pinctrl_remove,
> .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
> .ops = &imx_pinctrl_ops,
> -#if !CONFIG_IS_ENABLED(OF_CONTROL)
> .flags = DM_FLAG_PRE_RELOC,
> -#endif
It seems that this is not i.MX6 specific (maybe not even i.MX
specific. I noticed this issue on i.MX7 too).
Could this be handled in the drivers/pinctrl core instead?
Just wanted to see if we can get a more generic solution for this issue.
Thanks
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Re: [U-Boot] [PATCH 8/8] Add support for the NXP LS1021A-TSN board
On Sun, Jun 23, 2019 at 12:53 PM Vladimir Oltean wrote: > > From: Jianchao Wang > > The LS1021A-TSN is a development board built by VVDN/Argonboards in > partnership with NXP. > > It features the LS1021A SoC and the first-generation SJA1105T Ethernet > switch for prototyping implementations of a subset of IEEE 802.1 TSN > standards. > > Supported boot media: microSD card (via SPL), QSPI flash. > > Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which > is 64 MB in size and has an erase sector size of 256KB (therefore, > flashing the RCW would erase part of U-boot). > > Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which > is only 32 MB in size but has an erase sector size of 64KB (therefore > the RCW image can be flashed without erasing U-boot). > > To avoid the problems above, the U-boot base address has been selected > at 0x10 (the start of the 5th 256KB erase sector), which works for > all board revisions. Actually 0x4 would have been enough, but > 0x10 is common for all Layerscape devices. > > eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but > SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is > disabled. > > Signed-off-by: Xiaoliang Yang > Signed-off-by: Mingkai Hu > Signed-off-by: Jianchao Wang > Signed-off-by: Changming Huang > > [Vladimir] Code taken from https://github.com/openil/u-boot (which > itself is mostly copied from ls1021a-iot) and adapted with the following > changes: > > - Add a008850 errata workaround > - Converted eTSEC, MMC to DM to avoid all build warnings > - Plugged in distro boot feature, including support for extlinux.conf > - Added defconfig for QSPI boot > - Added the board/freescale/ls1021atsn/README.rst for initial setup > > Signed-off-by: Vladimir Oltean > --- > arch/arm/Kconfig | 14 + > arch/arm/dts/Makefile | 2 +- > arch/arm/dts/ls1021a-tsn.dts | 77 > board/freescale/ls1021atsn/Kconfig| 18 + > board/freescale/ls1021atsn/MAINTAINERS| 8 + > board/freescale/ls1021atsn/Makefile | 3 + > board/freescale/ls1021atsn/README.rst | 96 + > board/freescale/ls1021atsn/ls1021atsn.c | 291 +++ > board/freescale/ls1021atsn/ls102xa_pbi.cfg| 15 + > board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg | 8 + > configs/ls1021atsn_qspi_defconfig | 76 > configs/ls1021atsn_sdcard_defconfig | 85 + > include/configs/ls1021atsn.h | 346 ++ > 13 files changed, 1038 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/ls1021a-tsn.dts > create mode 100644 board/freescale/ls1021atsn/Kconfig > create mode 100644 board/freescale/ls1021atsn/MAINTAINERS > create mode 100644 board/freescale/ls1021atsn/Makefile > create mode 100644 board/freescale/ls1021atsn/README.rst > create mode 100644 board/freescale/ls1021atsn/ls1021atsn.c > create mode 100644 board/freescale/ls1021atsn/ls102xa_pbi.cfg > create mode 100644 board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg > create mode 100644 configs/ls1021atsn_qspi_defconfig > create mode 100644 configs/ls1021atsn_sdcard_defconfig > create mode 100644 include/configs/ls1021atsn.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 01ff57cf1bec..5edac7ea2bd5 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1327,6 +1327,19 @@ config TARGET_LS1021ATWR > select SUPPORT_SPL > imply SCSI > > +config TARGET_LS1021ATSN > + bool "Support ls1021atsn" > + select ARCH_LS1021A > + select ARCH_SUPPORT_PSCI > + select BOARD_EARLY_INIT_F > + select BOARD_LATE_INIT > + select CPU_V7A > + select CPU_V7_HAS_NONSEC > + select CPU_V7_HAS_VIRT > + select LS1_DEEP_SLEEP > + select SUPPORT_SPL > + imply SCSI > + > config TARGET_LS1021AIOT > bool "Support ls1021aiot" > select ARCH_LS1021A > @@ -1693,6 +1706,7 @@ source "board/freescale/ls1028a/Kconfig" > source "board/freescale/ls1021aqds/Kconfig" > source "board/freescale/ls1043aqds/Kconfig" > source "board/freescale/ls1021atwr/Kconfig" > +source "board/freescale/ls1021atsn/Kconfig" > source "board/freescale/ls1021aiot/Kconfig" > source "board/freescale/ls1046aqds/Kconfig" > source "board/freescale/ls1043ardb/Kconfig" > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 528fb909d5b0..28590b0c5530 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -325,7 +325,7 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb > dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ > ls1021a-qds-lpuart.dtb \ > ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ > - ls1021a-iot-duart.dtb > + ls1021a-iot-duart.dtb ls1021a-tsn.dtb > dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ > fsl-ls2080a-rdb.dtb \ > fsl-ls2081a-rdb.dtb \ > diff --g
[U-Boot] [PATCH] ARM: dts: Logic PD SOM-LV and Torpedo Boards: Resync DTS
Re-sync all Logic PD OMAP35 and AM/DM37 boards with Kernel
5.2.1
Signed-off-by: Adam Ford
diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
index 32d0dc371f..f7a841a288 100644
--- a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
+++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
index 2428373952..a604d92221 100644
--- a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
+++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
diff --git a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi
b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi
index 4990ed90dc..100396f6c2 100644
--- a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi
+++ b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/ {
gpio_keys {
@@ -153,7 +149,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;/* gpio_126 */
- cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */
+ cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */
vmmc-supply = <&vmmc1>;
bus-width = <4>;
cap-power-off-card;
diff --git a/arch/arm/dts/logicpd-som-lv.dtsi b/arch/arm/dts/logicpd-som-lv.dtsi
index 98b682a808..5563ee54c9 100644
--- a/arch/arm/dts/logicpd-som-lv.dtsi
+++ b/arch/arm/dts/logicpd-som-lv.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
#include
diff --git a/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts
b/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts
index d7cb659656..7675bc3fa8 100644
--- a/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts
+++ b/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
index c39cf2ca54..18c27e8505 100644
--- a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
+++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
diff --git a/arch/arm/dts/logicpd-torpedo-baseboard.dtsi
b/arch/arm/dts/logicpd-torpedo-baseboard.dtsi
index 86c5644f55..642e809e75 100644
--- a/arch/arm/dts/logicpd-torpedo-baseboard.dtsi
+++ b/arch/arm/dts/logicpd-torpedo-baseboard.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/ {
gpio_keys {
diff --git a/arch/arm/dts/logicpd-torpedo-som.dtsi
b/arch/arm/dts/logicpd-torpedo-som.dtsi
index 7d2302e870..3fdd0a72f8 100644
--- a/arch/arm/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/dts/logicpd-torpedo-som.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
#include
--
2.17.1
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Re: [U-Boot] [PATCH v2 8/9] configs: ls1021atwr: Fix distro_bootcmd for QSPI boot
On Sat, Jul 13, 2019 at 7:22 PM Vladimir Oltean wrote: > > Due to a typo, "run qspi_bootcmd" and "env exists secureboot" got > concatenated instead of being separated by a semicolon. > > Signed-off-by: Vladimir Oltean > Reviewed-by: Bin Meng Reviewed-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] net/macb: increase RX buffer size for GEM
On Sun, Jul 14, 2019 at 10:25 AM Ramon Fried wrote: > > Macb Ethernet controller requires a RX buffer of 128 bytes. It is > highly sub-optimal for Gigabit-capable GEM that is able to use > a bigger DMA buffer. Change this constant and associated macros > with data stored in the private structure. > RX DMA buffer size has to be multiple of 64 bytes as indicated in > DMA Configuration Register specification. > > Signed-off-by: Ramon Fried Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 18/18] rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board. Since sdram rk3399 support dynamic stride and rank detection it can able to detect 1GB ddr eventough the timings are meant for dual channel, 2GB size. Bootchain after and before this change are: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper This certainly fix the second channel data training initialization since we have dynamic rank, stride where second channel capabilities are clear or memset to 0. Signed-off-by: Jagan Teki --- arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi index 7d22528f49..eb0aca4758 100644 --- a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi @@ -4,3 +4,4 @@ */ #include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-ddr3-1866.dtsi" -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 17/18] ram: rk3399: Enable sdram debug functions
This would help to debug the sdram base parameters while
debugging existing chip or while supporting new sdram type.
It require explicit enablement of CONFIG_RAM_ROCKCHIP_DEBUG
for showing the debug prints.
Signed-off-by: Jagan Teki
---
drivers/ram/rockchip/sdram_rk3399.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index b83955f94e..9a60c24135 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1251,6 +1251,8 @@ static unsigned char calculate_stride(struct
rk3399_sdram_params *params)
}
}
+ sdram_print_stride(stride);
+
return stride;
}
@@ -1357,11 +1359,14 @@ static int sdram_init(struct dram_info *dram,
debug("Channel ");
debug(channel ? "1: " : "0: ");
+ sdram_print_ddr_info(cap_info, ¶ms->base);
+
set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
}
if (params->base.num_channels == 0) {
printf("%s: ", __func__);
+ sdram_print_dram_type(params->base.dramtype);
printf(" - %dMHz failed!\n", params->base.ddr_freq);
return -EINVAL;
}
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v3 10/18] ram: rockchip: Add debug sdram driver
Add sdram driver to handle debug across rockchip SoCs.
This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
.../include/asm/arch-rockchip/sdram_common.h | 9 +
drivers/ram/rockchip/Kconfig | 9 +
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_debug.c| 34 +++
4 files changed, 53 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram_debug.c
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h
b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 7ac25af327..171b233f95 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -92,4 +92,13 @@ size_t rockchip_sdram_size(phys_addr_t reg);
/* Called by U-Boot board_init_r for Rockchip SoCs */
int dram_init(void);
+
+#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
+inline void sdram_print_dram_type(unsigned char dramtype)
+{
+}
+#else
+void sdram_print_dram_type(unsigned char dramtype);
+#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
+
#endif
diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index 995cb487b8..151ffb684d 100644
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -7,6 +7,15 @@ config RAM_ROCKCHIP
if RAM_ROCKCHIP
+config RAM_ROCKCHIP_DEBUG
+ bool "Rockchip ram drivers debugging"
+ help
+ This enables debugging ram driver API's for the platforms
+ based on Rockchip SoCs.
+
+ This is an option for developers to understand the ram drivers
+ initialization, configurations and etc.
+
config RAM_RK3399
bool "Ram driver for Rockchip RK3399"
default ROCKCHIP_RK3399
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 07d4b62a9d..feb1f82d00 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -3,6 +3,7 @@
# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
#
+obj-$(CONFIG_RAM_ROCKCHIP_DEBUG) += sdram_debug.o
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
diff --git a/drivers/ram/rockchip/sdram_debug.c
b/drivers/ram/rockchip/sdram_debug.c
new file mode 100644
index 00..c13e140fa5
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2019 Amarula Solutions.
+ * Author: Jagan Teki
+ */
+
+#include
+#include
+#include
+
+void sdram_print_dram_type(unsigned char dramtype)
+{
+ switch (dramtype) {
+ case DDR3:
+ printascii("DDR3");
+ break;
+ case DDR4:
+ printascii("DDR4");
+ break;
+ case LPDDR2:
+ printascii("LPDDR2");
+ break;
+ case LPDDR3:
+ printascii("LPDDR3");
+ break;
+ case LPDDR4:
+ printascii("LPDDR4");
+ break;
+ default:
+ printascii("Unknown Device");
+ break;
+ }
+}
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v3 11/18] ram: rockchip: debug: Add sdram_print_ddr_info
Add sdram ddr info print support, this would help to
observe the sdram base parameters.
Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
.../include/asm/arch-rockchip/sdram_common.h | 7
drivers/ram/rockchip/sdram_debug.c| 40 +++
2 files changed, 47 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h
b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 171b233f95..cfbb511843 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -97,8 +97,15 @@ int dram_init(void);
inline void sdram_print_dram_type(unsigned char dramtype)
{
}
+
+inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+struct sdram_base_params *base)
+{
+}
#else
void sdram_print_dram_type(unsigned char dramtype);
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base);
#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
#endif
diff --git a/drivers/ram/rockchip/sdram_debug.c
b/drivers/ram/rockchip/sdram_debug.c
index c13e140fa5..69a6f94a73 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -32,3 +32,43 @@ void sdram_print_dram_type(unsigned char dramtype)
break;
}
}
+
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base)
+{
+ u32 bg;
+
+ bg = (cap_info->dbw == 0) ? 2 : 1;
+
+ sdram_print_dram_type(base->dramtype);
+
+ printascii(", ");
+ printdec(base->ddr_freq);
+ printascii("MHz\n");
+
+ printascii("BW=");
+ printdec(8 << cap_info->bw);
+
+ printascii(" Col=");
+ printdec(cap_info->col);
+
+ printascii(" Bk=");
+ printdec(0x1 << cap_info->bk);
+ if (base->dramtype == DDR4) {
+ printascii(" BG=");
+ printdec(1 << bg);
+ }
+
+ printascii(" CS0 Row=");
+ printdec(cap_info->cs0_row);
+ if (cap_info->rank > 1) {
+ printascii(" CS1 Row=");
+ printdec(cap_info->cs1_row);
+ }
+
+ printascii(" CS=");
+ printdec(cap_info->rank);
+
+ printascii(" Die BW=");
+ printdec(8 << cap_info->dbw);
+}
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v3 16/18] ram: rk3399: Add rank detection support
Right now the rk3399 sdram driver assume that the board
has configured with 2 channels, so any possibility to
enable single channel on the same driver will encounter
channel #1 data training failure.
Log:
U-Boot TPL board init
sdram_init: data training failed
rk3399_dmc_init DRAM init failed -5
So, add an algorithm that can capable to compute the active
or configured rank with associated channel like
a) do rank loop to compute the active rank, with associated
channel numbers
b) then, succeed the data training only for configured channel
c) preserve the rank for given channel
d) do channel loop for setting the active channel
e) if given rank is zero or inactive on the specific channel,
clear the timings for the associated channel
f) finally, return error if number of channels is zero
Tested in NanoPI-NEO4 since it support single channel sdram
configuration.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
drivers/ram/rockchip/sdram_rk3399.c | 110 ++--
1 file changed, 86 insertions(+), 24 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index 8bbacb5275..b83955f94e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1254,13 +1254,52 @@ static unsigned char calculate_stride(struct
rk3399_sdram_params *params)
return stride;
}
+static void clear_channel_params(struct rk3399_sdram_params *params, u8
channel)
+{
+ params->ch[channel].cap_info.rank = 0;
+ params->ch[channel].cap_info.col = 0;
+ params->ch[channel].cap_info.bk = 0;
+ params->ch[channel].cap_info.bw = 32;
+ params->ch[channel].cap_info.dbw = 32;
+ params->ch[channel].cap_info.row_3_4 = 0;
+ params->ch[channel].cap_info.cs0_row = 0;
+ params->ch[channel].cap_info.cs1_row = 0;
+ params->ch[channel].cap_info.ddrconfig = 0;
+}
+
+static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params
*params)
+{
+ int channel;
+ int ret;
+
+ for (channel = 0; channel < 2; channel++) {
+ const struct chan_info *chan = &dram->chan[channel];
+ struct rk3399_cru *cru = dram->cru;
+ struct rk3399_ddr_publ_regs *publ = chan->publ;
+
+ phy_pctrl_reset(cru, channel);
+ phy_dll_bypass_set(publ, params->base.ddr_freq);
+
+ ret = pctl_cfg(dram, chan, channel, params);
+ if (ret < 0) {
+ printf("%s: pctl config failed\n", __func__);
+ return ret;
+ }
+
+ /* start to trigger initialization */
+ pctl_start(dram, channel);
+ }
+
+ return 0;
+}
+
static int sdram_init(struct dram_info *dram,
struct rk3399_sdram_params *params)
{
unsigned char dramtype = params->base.dramtype;
unsigned int ddr_freq = params->base.ddr_freq;
- struct rk3399_cru *cru = dram->cru;
- int channel;
+ u32 training_flag = PI_READ_GATE_TRAINING;
+ int channel, ch, rank;
int ret;
debug("Starting SDRAM initialization...\n");
@@ -1272,36 +1311,59 @@ static int sdram_init(struct dram_info *dram,
return -E2BIG;
}
- for (channel = 0; channel < 2; channel++) {
- const struct chan_info *chan = &dram->chan[channel];
- struct rk3399_ddr_publ_regs *publ = chan->publ;
+ for (ch = 0; ch < 2; ch++) {
+ params->ch[ch].cap_info.rank = 2;
+ for (rank = 2; rank != 0; rank--) {
+ ret = pctl_init(dram, params);
+ if (ret < 0) {
+ printf("%s: pctl init failed\n", __func__);
+ return ret;
+ }
- phy_pctrl_reset(cru, channel);
- phy_dll_bypass_set(publ, ddr_freq);
+ /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
+ if (dramtype == LPDDR3)
+ udelay(10);
- if (channel >= params->base.num_channels)
- continue;
+ params->ch[ch].cap_info.rank = rank;
- ret = pctl_cfg(dram, chan, channel, params);
- if (ret < 0) {
- printf("%s: pctl config failed\n", __func__);
- return ret;
- }
+ /*
+* LPDDR3 CA training msut be trigger before
+* other training.
+* DDR3 is not have CA training.
+*/
+ if (params->base.dramtype == LPDDR3)
+ training_flag |= PI_CA_TRAINING;
- /* start to trigger initialization */
- pctl_start(dram, channel);
+ if (!(data_trai
[U-Boot] [PATCH v3 12/18] ram: rockchip: debug: Get the cs capacity
Add code to get the channel capacity, this would help to
print the capacity of specific channel.
Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
drivers/ram/rockchip/sdram_debug.c | 46 +-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_debug.c
b/drivers/ram/rockchip/sdram_debug.c
index 69a6f94a73..19e9225c12 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -33,10 +33,46 @@ void sdram_print_dram_type(unsigned char dramtype)
}
}
+/**
+ * cs = 0, cs0
+ * cs = 1, cs1
+ * cs => 2, cs0+cs1
+ * note: it didn't consider about row_3_4
+ */
+u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type)
+{
+ u32 bg;
+ u64 cap[2];
+
+ if (dram_type == DDR4)
+ /* DDR4 8bit dram BG = 2(4bank groups),
+* 16bit dram BG = 1 (2 bank groups)
+*/
+ bg = (cap_info->dbw == 0) ? 2 : 1;
+ else
+ bg = 0;
+
+ cap[0] = 1llu << (cap_info->bw + cap_info->col +
+bg + cap_info->bk + cap_info->cs0_row);
+
+ if (cap_info->rank == 2)
+ cap[1] = 1llu << (cap_info->bw + cap_info->col +
+bg + cap_info->bk + cap_info->cs1_row);
+ else
+ cap[1] = 0;
+
+ if (cs == 0)
+ return cap[0];
+ else if (cs == 1)
+ return cap[1];
+ else
+ return (cap[0] + cap[1]);
+}
+
void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base)
{
- u32 bg;
+ u32 bg, cap;
bg = (cap_info->dbw == 0) ? 2 : 1;
@@ -71,4 +107,12 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
printascii(" Die BW=");
printdec(8 << cap_info->dbw);
+
+ cap = sdram_get_cs_cap(cap_info, 3, base->dramtype);
+ if (cap_info->row_3_4)
+ cap = cap * 3 / 4;
+
+ printascii(" Size=");
+ printdec(cap >> 20);
+ printascii("MB\n");
}
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v3 07/18] ram: rk3399: Add pctl start support
Add support for pctl start for both channel 0, 1 control
and phy registers.
This would also handle pwrup_srefresh_exit init based
on the channel number.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
drivers/ram/rockchip/sdram_rk3399.c | 75 +
1 file changed, 55 insertions(+), 20 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index 6e944cafd9..084c949728 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -49,10 +49,11 @@ struct chan_info {
struct dram_info {
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
- u32 pwrup_srefresh_exit;
+ u32 pwrup_srefresh_exit[2];
struct chan_info chan[2];
struct clk ddr_clk;
struct rk3399_cru *cru;
+ struct rk3399_grf_regs *grf;
struct rk3399_pmucru *pmucru;
struct rk3399_pmusgrf_regs *pmusgrf;
struct rk3399_ddr_cic_regs *cic;
@@ -73,6 +74,11 @@ struct rockchip_dmc_plat {
struct regmap *map;
};
+static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
+{
+ return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
+}
+
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
@@ -328,6 +334,48 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
}
+static void pctl_start(struct dram_info *dram, u8 channel)
+{
+ const struct chan_info *chan = &dram->chan[channel];
+ u32 *denali_ctl = chan->pctl->denali_ctl;
+ u32 *denali_phy = chan->publ->denali_phy;
+ u32 *ddrc0_con = get_ddrc0_con(dram, channel);
+ u32 count = 0;
+ u32 byte, tmp;
+
+ writel(0x0100, &ddrc0_con);
+
+ clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
+
+ while (!(readl(&denali_ctl[203]) & (1 << 3))) {
+ if (count > 1000) {
+ printf("%s: Failed to init pctl for channel %d\n",
+ __func__, channel);
+ while (1)
+ ;
+ }
+
+ udelay(1);
+ count++;
+ }
+
+ writel(0x01000100, &ddrc0_con);
+
+ for (byte = 0; byte < 4; byte++) {
+ tmp = 0x820;
+ writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
+ writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
+
+ clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0x, tmp);
+ }
+
+ clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
+ dram->pwrup_srefresh_exit[channel]);
+}
+
static int phy_io_config(const struct chan_info *chan,
const struct rk3399_sdram_params *params)
{
@@ -498,7 +546,6 @@ static int pctl_cfg(struct dram_info *dram, const struct
chan_info *chan,
const u32 *params_phy = params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
int ret;
- const ulong timeout_ms = 200;
/*
* work around controller bug:
@@ -518,8 +565,8 @@ static int pctl_cfg(struct dram_info *dram, const struct
chan_info *chan,
writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
- dram->pwrup_srefresh_exit = readl(&denali_ctl[68]) &
- PWRUP_SREFRESH_EXIT;
+ dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
+PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
/* PHY_DLL_RST_EN */
@@ -580,22 +627,6 @@ static int pctl_cfg(struct dram_info *dram, const struct
chan_info *chan,
if (ret)
return ret;
- /* PHY_DLL_RST_EN */
- clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
-
- /* Waiting for PHY and DRAM init complete */
- tmp = get_timer(0);
- do {
- if (get_timer(tmp) > timeout_ms) {
- pr_err("DRAM (%s): phy failed to lock within %ld ms\n",
- __func__, timeout_ms);
- return -ETIME;
- }
- } while (!(readl(&denali_ctl[203]) & (1 << 3)));
- debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
-
- clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
- dram->pwrup_srefresh_exit);
return 0;
}
@@ -1186,6 +1217,9 @@ static int sdram_init(struct dram_info *dram,
return ret;
}
+ /* start to trig
Re: [U-Boot] [PATCH 1/6] net: macb: sync header definitions as taken from Linux
On Tue, Jun 11, 2019 at 10:51 AM Ramon Fried wrote: > > Few registers and bits were added by Cadence and > they were not updated in the headers. > Take the latest definitions as defined in Linux > header (5.1) that also includes some comments > about existing registers. > > One register was improperly named (UR), fix that. This is breaking the build. "UR" is still referred to in drivers/net/macb.c line 805. Did you build test this? > > Signed-off-by: Ramon Fried ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 03/18] ram: rk3399: Use rank mask in ca data training
Add rank_mask based on the rank number, this would keep
the ca data training loop based on the desired rank mask
value instead of looping for all values.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
drivers/ram/rockchip/sdram_rk3399.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index fe26144f27..b98df20fa5 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -626,11 +626,17 @@ static int data_training_ca(const struct chan_info *chan,
u32 channel,
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_err = 0;
u32 rank = params->ch[channel].cap_info.rank;
+ u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x3f7c, (&denali_pi[175]));
- for (i = 0; i < rank; i++) {
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
+
+ for (i = 0; i < 4; i++) {
+ if (!(rank_mask & (1 << i)))
+ continue;
+
select_per_cs_training_index(chan, i);
/* PI_100 PI_CALVL_EN:RW:8:2 */
--
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[U-Boot] [PATCH v3 06/18] ram: rk3399: Move pwrup_srefresh_exit to dram_info
Add pwrup_srefresh_exit to be part of dram_info so-that
the it can help to support pwrup_srefresh_exit in individual
channels while starting pctl in future.
No functionality change.
Signed-off-by: Jagan Teki
---
drivers/ram/rockchip/sdram_rk3399.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index a5da985e1a..6e944cafd9 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -49,6 +49,7 @@ struct chan_info {
struct dram_info {
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ u32 pwrup_srefresh_exit;
struct chan_info chan[2];
struct clk ddr_clk;
struct rk3399_cru *cru;
@@ -487,8 +488,8 @@ static int phy_io_config(const struct chan_info *chan,
return 0;
}
-static int pctl_cfg(const struct chan_info *chan, u32 channel,
- const struct rk3399_sdram_params *params)
+static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
+ u32 channel, const struct rk3399_sdram_params *params)
{
u32 *denali_ctl = chan->pctl->denali_ctl;
u32 *denali_pi = chan->pi->denali_pi;
@@ -496,7 +497,6 @@ static int pctl_cfg(const struct chan_info *chan, u32
channel,
const u32 *params_ctl = params->pctl_regs.denali_ctl;
const u32 *params_phy = params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
- u32 pwrup_srefresh_exit;
int ret;
const ulong timeout_ms = 200;
@@ -518,7 +518,8 @@ static int pctl_cfg(const struct chan_info *chan, u32
channel,
writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
- pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
+ dram->pwrup_srefresh_exit = readl(&denali_ctl[68]) &
+ PWRUP_SREFRESH_EXIT;
clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
/* PHY_DLL_RST_EN */
@@ -594,7 +595,7 @@ static int pctl_cfg(const struct chan_info *chan, u32
channel,
debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
- pwrup_srefresh_exit);
+ dram->pwrup_srefresh_exit);
return 0;
}
@@ -1179,7 +1180,7 @@ static int sdram_init(struct dram_info *dram,
if (channel >= params->base.num_channels)
continue;
- ret = pctl_cfg(chan, channel, params);
+ ret = pctl_cfg(dram, chan, channel, params);
if (ret < 0) {
printf("%s: pctl config failed\n", __func__);
return ret;
--
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[U-Boot] [PATCH v3 14/18] ram: rk3399: Compute stride for 2 channels
stride value from sdram timings can be computed dynamically
based on the determined capacity for the given channel.
Right now these stride values are taken as part of sdram timings
via dtsi, but it possible to use same timings dtsi for given
frequency even though the configured board sdram do support
single channel with different size by dynamically detect the
stride value.
Example, NanoPi NEO4 do have DDR3-1866, but with single channel
and 1GB size with dynamic stride detection it is possible to
use existing rk3399-sdram-ddr3-1866.dtsi whose stride,
number of channels and capacity it support is d efferent.
So, add initial support to calculate the stride value for
2 channels sdram, which is available by default on existing
boards.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
drivers/ram/rockchip/sdram_rk3399.c | 71 -
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index 084c949728..c626ef602c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1183,8 +1183,75 @@ static int switch_to_phy_index1(struct dram_info *dram,
return 0;
}
+static unsigned char calculate_stride(struct rk3399_sdram_params *params)
+{
+ unsigned int stride = params->base.stride;
+ unsigned int channel, chinfo = 0;
+ unsigned int ch_cap[2] = {0, 0};
+ u64 cap;
+
+ for (channel = 0; channel < 2; channel++) {
+ unsigned int cs0_cap = 0;
+ unsigned int cs1_cap = 0;
+ struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info;
+
+ if (cap_info->col == 0)
+ continue;
+
+ cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
+cap_info->bk + cap_info->bw - 20));
+ if (cap_info->rank > 1)
+ cs1_cap = cs0_cap >> (cap_info->cs0_row
+ - cap_info->cs1_row);
+ if (cap_info->row_3_4) {
+ cs0_cap = cs0_cap * 3 / 4;
+ cs1_cap = cs1_cap * 3 / 4;
+ }
+ ch_cap[channel] = cs0_cap + cs1_cap;
+ chinfo |= 1 << channel;
+ }
+
+ /* stride calculation for 2 channels, default gstride type is 256B */
+ if (ch_cap[0] == ch_cap[1]) {
+ cap = ch_cap[0] + ch_cap[1];
+ switch (cap) {
+ /* 512MB */
+ case 512:
+ stride = 0;
+ break;
+ /* 1GB */
+ case 1024:
+ stride = 0x5;
+ break;
+ /*
+* 768MB + 768MB same as total 2GB memory
+* useful space: 0-768MB 1GB-1792MB
+*/
+ case 1536:
+ /* 2GB */
+ case 2048:
+ stride = 0x9;
+ break;
+ /* 1536MB + 1536MB */
+ case 3072:
+ stride = 0x11;
+ break;
+ /* 4GB */
+ case 4096:
+ stride = 0xD;
+ break;
+ default:
+ printf("%s: Unable to calculate stride for ", __func__);
+ print_size((cap * (1 << 20)), " capacity\n");
+ break;
+ }
+ }
+
+ return stride;
+}
+
static int sdram_init(struct dram_info *dram,
- const struct rk3399_sdram_params *params)
+ struct rk3399_sdram_params *params)
{
unsigned char dramtype = params->base.dramtype;
unsigned int ddr_freq = params->base.ddr_freq;
@@ -1232,6 +1299,8 @@ static int sdram_init(struct dram_info *dram,
set_ddrconfig(chan, params, channel,
params->ch[channel].cap_info.ddrconfig);
}
+
+ params->base.stride = calculate_stride(params);
dram_all_config(dram, params);
switch_to_phy_index1(dram, params);
--
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[U-Boot] [PATCH v3 15/18] ram: rk3399: Compute stride for 1 channel a
Add stride computation for the sdram which support
single channel a
This configuration available in NanoPi NEO4 and the
same can work with existing rk3399-sdram-ddr3-1866.dtsi
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
drivers/ram/rockchip/sdram_rk3399.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index c626ef602c..8bbacb5275 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1211,6 +1211,10 @@ static unsigned char calculate_stride(struct
rk3399_sdram_params *params)
chinfo |= 1 << channel;
}
+ /* stride calculation for 1 channel */
+ if (params->base.num_channels == 1 && chinfo & 1)
+ return 0x17;/* channel a */
+
/* stride calculation for 2 channels, default gstride type is 256B */
if (ch_cap[0] == ch_cap[1]) {
cap = ch_cap[0] + ch_cap[1];
--
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[U-Boot] [PATCH v3 01/18] ram: rk3399: Handle data training return types
data trainings calls like ca, wl, rg, rl, wdql have proper
return types with -EIO and the return type missed to handle
in data_training function.
This patch, add proper return type checks along with useful
debug statement on each data training calls.
Incidentally this would help to prevent the sdram initialization
hang for single channel dram and when the code is trying to
initialize second channel with proper return type of relevant
data training call might failed.
Signed-off-by: Jagan Teki
---
drivers/ram/rockchip/sdram_rk3399.c | 50 ++---
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index 492b0975dd..e9c0fdf2d4 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -887,6 +887,7 @@ static int data_training(const struct chan_info *chan, u32
channel,
u32 training_flag)
{
u32 *denali_phy = chan->publ->denali_phy;
+ int ret;
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
setbits_le32(&denali_phy[927], (1 << 22));
@@ -907,24 +908,49 @@ static int data_training(const struct chan_info *chan,
u32 channel,
}
/* ca training(LPDDR4,LPDDR3 support) */
- if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING)
- data_training_ca(chan, channel, params);
+ if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
+ ret = data_training_ca(chan, channel, params);
+ if (ret < 0) {
+ debug("%s: data training ca failed\n", __func__);
+ return ret;
+ }
+ }
/* write leveling(LPDDR4,LPDDR3,DDR3 support) */
- if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING)
- data_training_wl(chan, channel, params);
+ if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
+ ret = data_training_wl(chan, channel, params);
+ if (ret < 0) {
+ debug("%s: data training wl failed\n", __func__);
+ return ret;
+ }
+ }
/* read gate training(LPDDR4,LPDDR3,DDR3 support) */
- if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING)
- data_training_rg(chan, channel, params);
+ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
+ ret = data_training_rg(chan, channel, params);
+ if (ret < 0) {
+ debug("%s: data training rg failed\n", __func__);
+ return ret;
+ }
+ }
/* read leveling(LPDDR4,LPDDR3,DDR3 support) */
- if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING)
- data_training_rl(chan, channel, params);
+ if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
+ ret = data_training_rl(chan, channel, params);
+ if (ret < 0) {
+ debug("%s: data training rl failed\n", __func__);
+ return ret;
+ }
+ }
/* wdq leveling(LPDDR4 support) */
- if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING)
- data_training_wdql(chan, channel, params);
+ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
+ ret = data_training_wdql(chan, channel, params);
+ if (ret < 0) {
+ debug("%s: data training wdql failed\n", __func__);
+ return ret;
+ }
+ }
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
clrbits_le32(&denali_phy[927], (1 << 22));
@@ -1062,7 +1088,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
ret = data_training(&dram->chan[channel], channel,
params, PI_FULL_TRAINING);
- if (ret) {
+ if (ret < 0) {
debug("index1 training failed\n");
return ret;
}
@@ -1108,7 +1134,7 @@ static int sdram_init(struct dram_info *dram,
udelay(10);
if (data_training(chan, channel, params, PI_FULL_TRAINING)) {
- printf("SDRAM initialization failed, reset\n");
+ printf("%s: data training failed\n", __func__);
return -EIO;
}
--
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[U-Boot] [PATCH v3 02/18] ram: rk3399: Clear PI_175 interrupts in data training
Clear the PI_175 interrupts before processing actual
data training in all relevant calls.
This would help to clear interrupt from previous training.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
drivers/ram/rockchip/sdram_rk3399.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index e9c0fdf2d4..fe26144f27 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -627,6 +627,9 @@ static int data_training_ca(const struct chan_info *chan,
u32 channel,
u32 obs_0, obs_1, obs_2, obs_err = 0;
u32 rank = params->ch[channel].cap_info.rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x3f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -681,6 +684,9 @@ static int data_training_wl(const struct chan_info *chan,
u32 channel,
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
u32 rank = params->ch[channel].cap_info.rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x3f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -740,6 +746,9 @@ static int data_training_rg(const struct chan_info *chan,
u32 channel,
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
u32 rank = params->ch[channel].cap_info.rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x3f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -799,6 +808,9 @@ static int data_training_rl(const struct chan_info *chan,
u32 channel,
u32 i, tmp;
u32 rank = params->ch[channel].cap_info.rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x3f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -844,6 +856,9 @@ static int data_training_wdql(const struct chan_info *chan,
u32 channel,
u32 i, tmp;
u32 rank = params->ch[channel].cap_info.rank;
+ /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+ writel(0x3f7c, (&denali_pi[175]));
+
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
--
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[U-Boot] [PATCH v3 13/18] ram: rk3399: debug: Add sdram_print_stride
Add code to print the channel stride, this would help to
print the stride of associated channel.
Here is sample print on LPDDR4, 50MHz.
256B stride
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
.../include/asm/arch-rockchip/sdram_common.h | 5
drivers/ram/rockchip/sdram_debug.c| 29 +++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h
b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index cfbb511843..b7549f5d8a 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -102,10 +102,15 @@ inline void sdram_print_ddr_info(struct sdram_cap_info
*cap_info,
struct sdram_base_params *base)
{
}
+
+inline void sdram_print_stride(unsigned int stride)
+{
+}
#else
void sdram_print_dram_type(unsigned char dramtype);
void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base);
+void sdram_print_stride(unsigned int stride);
#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
#endif
diff --git a/drivers/ram/rockchip/sdram_debug.c
b/drivers/ram/rockchip/sdram_debug.c
index 19e9225c12..9cf662675b 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -116,3 +116,32 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
printdec(cap >> 20);
printascii("MB\n");
}
+
+void sdram_print_stride(unsigned int stride)
+{
+ switch (stride) {
+ case 0xc:
+ printf("128B stride\n");
+ break;
+ case 5:
+ case 9:
+ case 0xd:
+ case 0x11:
+ case 0x19:
+ printf("256B stride\n");
+ break;
+ case 0xa:
+ case 0xe:
+ case 0x12:
+ printf("512B stride\n");
+ break;
+ case 0xf:
+ printf("4K stride\n");
+ break;
+ case 0x1f:
+ printf("32MB + 256B stride\n");
+ break;
+ default:
+ printf("no stride\n");
+ }
+}
--
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[U-Boot] [PATCH v3 08/18] ram: rockchip: Add initial Kconfig
Right now sdram drivers in rockchip SoC are built based on the SoC configs which may not be an adequate solutions while adding common or debug driver. So, add meaningful Kconfig options start with rk3399. Signed-off-by: Jagan Teki --- drivers/ram/Kconfig | 1 + drivers/ram/rockchip/Kconfig | 17 + drivers/ram/rockchip/Makefile | 2 +- 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 drivers/ram/rockchip/Kconfig diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index fbf7d7b20f..568d8f2c6a 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -54,4 +54,5 @@ config K3_AM654_DDRSS config add support for the initialization of the external SDRAM devices connected to DDR subsystem. +source "drivers/ram/rockchip/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig new file mode 100644 index 00..995cb487b8 --- /dev/null +++ b/drivers/ram/rockchip/Kconfig @@ -0,0 +1,17 @@ +config RAM_ROCKCHIP + bool "Ram drivers support for Rockchip SoCs" + depends on RAM && ARCH_ROCKCHIP + default y + help + This enables support for ram drivers Rockchip SoCs. + +if RAM_ROCKCHIP + +config RAM_RK3399 + bool "Ram driver for Rockchip RK3399" + default ROCKCHIP_RK3399 + help + This enables ram drivers support for the platforms based on + Rockchip RK3399 SoC. + +endif # RAM_ROCKCHIP diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index 5df196066d..07d4b62a9d 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -9,4 +9,4 @@ obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o -obj-$(CONFIG_ROCKCHIP_RK3399) = sdram_rk3399.o +obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 09/18] debug_uart: Add printdec
Add printdec, this would help to print an
output a decimalism value.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
include/debug_uart.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/debug_uart.h b/include/debug_uart.h
index 34e8b2fc81..cd70ae1a04 100644
--- a/include/debug_uart.h
+++ b/include/debug_uart.h
@@ -104,6 +104,13 @@ void printhex4(uint value);
*/
void printhex8(uint value);
+/**
+ * printdec() - Output a decimalism value
+ *
+ * @value: Value to output
+ */
+void printdec(uint value);
+
#ifdef CONFIG_DEBUG_UART_ANNOUNCE
#define _DEBUG_UART_ANNOUNCE printascii(" ");
#else
@@ -170,6 +177,18 @@ void printhex8(uint value);
{ \
printhex(value, 8); \
} \
+\
+ void printdec(uint value) \
+ { \
+ if (value > 10) { \
+ printdec(value / 10); \
+ value %= 10; \
+ } else if (value == 10) { \
+ _debug_uart_putc('1'); \
+ value = 0; \
+ } \
+ _debug_uart_putc('0' + value); \
+ } \
\
void debug_uart_init(void) \
{ \
--
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[U-Boot] [PATCH v3 04/18] ram: rk3399: Use rank mask in wdql data training
Add rank_mask based on the rank number, this would keep
the wdql data training loop based on the desired rank mask
value instead of looping for all values.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
drivers/ram/rockchip/sdram_rk3399.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index b98df20fa5..16bd9427a6 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -861,11 +861,17 @@ static int data_training_wdql(const struct chan_info
*chan, u32 channel,
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
u32 rank = params->ch[channel].cap_info.rank;
+ u32 rank_mask;
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
writel(0x3f7c, (&denali_pi[175]));
- for (i = 0; i < rank; i++) {
+ rank_mask = (rank == 1) ? 0x1 : 0x3;
+
+ for (i = 0; i < 4; i++) {
+ if (!(rank_mask & (1 << i)))
+ continue;
+
select_per_cs_training_index(chan, i);
/*
--
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[U-Boot] [PATCH v3 05/18] ram: rk3399: Add phy pctrl reset support
Add support for phy pctrl reset support for both channel 0, 1.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
drivers/ram/rockchip/sdram_rk3399.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index 16bd9427a6..a5da985e1a 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -35,6 +35,10 @@
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
+#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
+ ((n) << (8 + (ch) * 4)))
+#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
+ ((n) << (9 + (ch) * 4)))
struct chan_info {
struct rk3399_ddr_pctl_regs *pctl;
struct rk3399_ddr_pi_regs *pi;
@@ -79,6 +83,29 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
}
}
+static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
+ u32 phy)
+{
+ channel &= 0x1;
+ ctl &= 0x1;
+ phy &= 0x1;
+ writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
+ CRU_SFTRST_DDR_PHY(channel, phy),
+ &cru->softrst_con[4]);
+}
+
+static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
+{
+ rkclk_ddr_reset(cru, channel, 1, 1);
+ udelay(10);
+
+ rkclk_ddr_reset(cru, channel, 1, 0);
+ udelay(10);
+
+ rkclk_ddr_reset(cru, channel, 0, 0);
+ udelay(10);
+}
+
static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
u32 freq)
{
@@ -1129,6 +1156,7 @@ static int sdram_init(struct dram_info *dram,
{
unsigned char dramtype = params->base.dramtype;
unsigned int ddr_freq = params->base.ddr_freq;
+ struct rk3399_cru *cru = dram->cru;
int channel;
int ret;
@@ -1145,6 +1173,7 @@ static int sdram_init(struct dram_info *dram,
const struct chan_info *chan = &dram->chan[channel];
struct rk3399_ddr_publ_regs *publ = chan->publ;
+ phy_pctrl_reset(cru, channel);
phy_dll_bypass_set(publ, ddr_freq);
if (channel >= params->base.num_channels)
--
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[U-Boot] [PATCH v3 00/18] ram: rk3399: Add rank detection
This is v3, version of dynamic rank detection changes from previous lpddr4 changes[1]. rank detection would required for probing single channel ddr configuration like NanoPi NEO4. Changes for v3: - rebase in master - order them in proper way [1] https://patchwork.ozlabs.org/cover/1116734/ Any inputs? Jagan. Jagan Teki (18): ram: rk3399: Handle data training return types ram: rk3399: Clear PI_175 interrupts in data training ram: rk3399: Use rank mask in ca data training ram: rk3399: Use rank mask in wdql data training ram: rk3399: Add phy pctrl reset support ram: rk3399: Move pwrup_srefresh_exit to dram_info ram: rk3399: Add pctl start support ram: rockchip: Add initial Kconfig debug_uart: Add printdec ram: rockchip: Add debug sdram driver ram: rockchip: debug: Add sdram_print_ddr_info ram: rockchip: debug: Get the cs capacity ram: rk3399: debug: Add sdram_print_stride ram: rk3399: Compute stride for 2 channels ram: rk3399: Compute stride for 1 channel a ram: rk3399: Add rank detection support ram: rk3399: Enable sdram debug functions rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 + .../include/asm/arch-rockchip/sdram_common.h | 21 + drivers/ram/Kconfig | 1 + drivers/ram/rockchip/Kconfig | 26 ++ drivers/ram/rockchip/Makefile | 3 +- drivers/ram/rockchip/sdram_debug.c| 147 +++ drivers/ram/rockchip/sdram_rk3399.c | 366 +++--- include/debug_uart.h | 19 + 8 files changed, 529 insertions(+), 55 deletions(-) create mode 100644 drivers/ram/rockchip/Kconfig create mode 100644 drivers/ram/rockchip/sdram_debug.c -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 14/15] arm: include: rockchip: Add DDR4 enum
Add DDR4 enum number in common header.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
---
arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h
b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 55abcdae77..7ac25af327 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -7,6 +7,7 @@
#define _ASM_ARCH_SDRAM_COMMON_H
enum {
+ DDR4 = 0,
DDR3 = 0x3,
LPDDR2 = 0x5,
LPDDR3 = 0x6,
--
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[U-Boot] [PATCH v3 15/15] clk: rockchip: rk3399: Fix check patch warnings and checks
- CHECK: spaces preferred around that '*'
- CHECK: spaces preferred around that '/'
- CHECK: space preferred before that '|'
- WARNING: macros should not use a trailing semicolon
- CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv'
- CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC'
- CHECK: Unnecessary parentheses around 'parent->dev == clk->dev'
- WARNING: line over 80 characters
- CHECK: Prefer kernel type 'u8' over 'uint8_t'
- Add proper macro definitions arrangements
Note: there are still line over 80 characters and other warnings but
fixing those making code look unreadable, so I kept it as it is.
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/clk_rk3399.c | 68 ++-
1 file changed, 31 insertions(+), 37 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index aa6a8ad1c9..5d1ad94e85 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -38,8 +38,8 @@ struct pll_div {
};
#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-#define DIV_TO_RATE(input_rate, div)((input_rate) / ((div) + 1))
+ ((input_rate) / (output_rate) - 1)
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
.refdiv = _refdiv,\
@@ -53,15 +53,15 @@ static const struct pll_div cpll_init_cfg =
PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
#endif
-static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
-static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
+static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1,
1);
+static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
static const struct pll_div *apll_l_cfgs[] = {
[APLL_L_1600_MHZ] = &apll_l_1600_cfg,
[APLL_L_600_MHZ] = &apll_l_600_cfg,
};
-static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
+static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
static const struct pll_div *apll_b_cfgs[] = {
[APLL_B_600_MHZ] = &apll_b_600_cfg,
};
@@ -393,7 +393,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
fref_khz = ref_khz / refdiv;
fbdiv = vco_khz / fref_khz;
- if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
+ if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
continue;
diff_khz = vco_khz - fbdiv * fref_khz;
if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
@@ -409,7 +409,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
div->fbdiv = fbdiv;
}
- if (best_diff_khz > 4 * (MHz/KHz)) {
+ if (best_diff_khz > 4 * (MHz / KHz)) {
printf("%s: Failed to match output frequency %u, "
"difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
best_diff_khz * KHz);
@@ -489,28 +489,21 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
}
#define I2C_CLK_REG_MASK(bus) \
- (I2C_DIV_CON_MASK << \
- CLK_I2C ##bus## _DIV_CON_SHIFT | \
- CLK_I2C_PLL_SEL_MASK << \
- CLK_I2C ##bus## _PLL_SEL_SHIFT)
+ (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
+CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
#define I2C_CLK_REG_VALUE(bus, clk_div) \
- ((clk_div - 1) << \
- CLK_I2C ##bus## _DIV_CON_SHIFT | \
- CLK_I2C_PLL_SEL_GPLL << \
- CLK_I2C ##bus## _PLL_SEL_SHIFT)
+ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
+CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
#define I2C_CLK_DIV_VALUE(con, bus) \
- (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
- I2C_DIV_CON_MASK;
+ ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
#define I2C_PMUCLK_REG_MASK(bus) \
- (I2C_DIV_CON_MASK << \
-CLK_I2C ##bus## _DIV_CON_SHIFT)
+ (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
- ((clk_div - 1) << \
- CLK_I2C ##bus## _DIV_CON_SHIFT)
+ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
{
@@ -597,9 +590,9 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru,
ulong clk_id, uint hz)
*/
struct spi_clkreg {
- uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
- uint8_t div_shift
[U-Boot] [PATCH v3 10/15] ram: rockchip: rk3399: Add cap_info structure
Group common ddr attributes like
- rank
- col
- bk
- bw
- dbw
- row_3_4
- cs0_row
- cs1_row
- ddrconfig
into a common cap_info structure for more code readability and extend
if possible based on the new features.
Signed-off-by: Jagan Teki
---
.../include/asm/arch-rockchip/sdram_rk3399.h | 6 +-
drivers/ram/rockchip/sdram_rk3399.c | 73 ++-
2 files changed, 45 insertions(+), 34 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index c6a260bad8..683093d4ca 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -71,7 +71,7 @@ struct rk3399_ddr_cic_regs {
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
-struct rk3399_sdram_channel {
+struct sdram_cap_info {
unsigned int rank;
/* dram column number, 0 means this channel is invalid */
unsigned int col;
@@ -89,6 +89,10 @@ struct rk3399_sdram_channel {
unsigned int cs0_row;
unsigned int cs1_row;
unsigned int ddrconfig;
+};
+
+struct rk3399_sdram_channel {
+ struct sdram_cap_info cap_info;
struct rk3399_msch_timings noc_timings;
};
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index 043b27737d..492b0975dd 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -121,35 +121,36 @@ static void set_memory_map(const struct chan_info *chan,
u32 channel,
u32 row;
/* Get row number from ddrconfig setting */
- if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)
+ if (sdram_ch->cap_info.ddrconfig < 2 ||
+ sdram_ch->cap_info.ddrconfig == 4)
row = 16;
- else if (sdram_ch->ddrconfig == 3)
+ else if (sdram_ch->cap_info.ddrconfig == 3)
row = 14;
else
row = 15;
- cs_map = (sdram_ch->rank > 1) ? 3 : 1;
- reduc = (sdram_ch->bw == 2) ? 0 : 1;
+ cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
+ reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
/* Set the dram configuration to ctrl */
- clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
+ clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
- ((3 - sdram_ch->bk) << 16) |
+ ((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
cs_map | (reduc << 16));
/* PI_199 PI_COL_DIFF:RW:0:4 */
- clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
+ clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
/* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
- ((3 - sdram_ch->bk) << 16) |
+ ((3 - sdram_ch->cap_info.bk) << 16) |
((16 - row) << 24));
/* PI_41 PI_CS_MAP:RW:24:4 */
clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
- if (sdram_ch->rank == 1 && params->base.dramtype == DDR3)
+ if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
writel(0x2EC7, &denali_pi[34]);
}
@@ -624,7 +625,7 @@ static int data_training_ca(const struct chan_info *chan,
u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_err = 0;
- u32 rank = params->ch[channel].rank;
+ u32 rank = params->ch[channel].cap_info.rank;
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -678,7 +679,7 @@ static int data_training_wl(const struct chan_info *chan,
u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
- u32 rank = params->ch[channel].rank;
+ u32 rank = params->ch[channel].cap_info.rank;
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -737,7 +738,7 @@ static int data_training_rg(const struct chan_info *chan,
u32 channel,
u32 *denali_phy = chan->publ->denali_phy;
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
- u32 rank = params->ch[channel].rank;
+ u32 rank = params->ch[channel].cap_info.rank;
for (i = 0; i < rank; i++) {
select_per_cs_training_index(chan, i);
@@ -796,7 +797,7 @@ static int data_training_rl(const struct chan_info *chan,
u32 channel,
{
u32 *denali_pi = chan->pi->denali_pi;
u32 i, tmp;
- u32 rank = params->ch[channel].rank;
+ u32 rank = params->ch[channel].cap_info.rank;
for (i = 0; i < rank; i++) {
[U-Boot] [PATCH v3 04/15] ram: rk3399: Handle pctl_cfg return type
Add proper return type handling of pctl_cfg with
meaningful print statement.
Signed-off-by: Jagan Teki
---
drivers/ram/rockchip/sdram_rk3399.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index c918c2e588..de5d8c1b5f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1063,6 +1063,7 @@ static int sdram_init(struct dram_info *dram,
unsigned char dramtype = params->base.dramtype;
unsigned int ddr_freq = params->base.ddr_freq;
int channel;
+ int ret;
debug("Starting SDRAM initialization...\n");
@@ -1082,9 +1083,10 @@ static int sdram_init(struct dram_info *dram,
if (channel >= params->base.num_channels)
continue;
- if (pctl_cfg(chan, channel, params) != 0) {
- printf("pctl_cfg fail, reset\n");
- return -EIO;
+ ret = pctl_cfg(chan, channel, params);
+ if (ret < 0) {
+ printf("%s: pctl config failed\n", __func__);
+ return ret;
}
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
--
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