[U-Boot] [PATCH 1/5] arm: k3: Add support for printing CPUINFO
Add support for printing CPU info for all K3 devices.
Signed-off-by: Lokesh Vutla
---
arch/arm/mach-k3/common.c| 43
arch/arm/mach-k3/common.h| 15 +
arch/arm/mach-k3/include/mach/hardware.h | 24 +
3 files changed, 82 insertions(+)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 3e36d90ace..7339d7398d 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -14,6 +14,22 @@
#include
#include
#include
+#include
+#include
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static const char soc_name[K3_MAX + 1][SOC_NAME_MAX_LENGTH] = {
+ [AM654] = "AM654",
+ [J721E] = "J721E",
+ [K3_MAX] = "UNKNOWN"
+};
+
+static const char soc_revision[REV_PG_MAX + 1][SOC_REVISION_MAX_LENGTH] = {
+ [REV_PG1_0] = "1.0",
+ [REV_PG2_0] = "2.0",
+ [REV_PG_MAX] = "NULL"
+};
+#endif
struct ti_sci_handle *get_ti_sci_handle(void)
{
@@ -144,3 +160,30 @@ void reset_cpu(ulong ignored)
{
}
#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ k3_soc_rev rev;
+ k3_soc soc;
+
+ soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) &
+ DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT;
+ rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
+ JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
+
+ printf("SoC: ");
+ if (soc > K3_MAX || !soc_name[soc])
+ printf("Unknown Silicon %d ", soc);
+ else
+ printf("%s ", soc_name[soc]);
+
+ printf("PG ");
+ if (rev > REV_PG_MAX)
+ printf("Unknown revision %d\n", rev);
+ else
+ printf("%s\n", soc_revision[rev]);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index ac7e80d9af..9f8fbb1241 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -8,4 +8,19 @@
#include
+#define SOC_NAME_MAX_LENGTH10
+#define SOC_REVISION_MAX_LENGTH5
+
+typedef enum {
+ AM654 = 2,
+ J721E = 4,
+ K3_MAX
+} k3_soc;
+
+typedef enum {
+ REV_PG1_0,
+ REV_PG2_0,
+ REV_PG_MAX
+} k3_soc_rev;
+
void setup_k3_mpu_regions(void);
diff --git a/arch/arm/mach-k3/include/mach/hardware.h
b/arch/arm/mach-k3/include/mach/hardware.h
index 4e629822aa..b888dbf0b2 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -13,4 +13,28 @@
#ifdef CONFIG_SOC_K3_J721E
#include "j721e_hardware.h"
#endif
+
+/* Assuming these addresses and definitions stay common across K3 devices */
+#define CTRLMMR_WKUP_JTAG_DEVICE_ID0x4318
+#define DEVICE_ID_FAMILY_SHIFT 26
+#define DEVICE_ID_FAMILY_MASK (0x3f << 26)
+#define DEVICE_ID_BASE_SHIFT 11
+#define DEVICE_ID_BASE_MASK(0x1fff << 11)
+#define DEVICE_ID_SPEED_SHIFT 6
+#define DEVICE_ID_SPEED_MASK (0x1f << 6)
+#define DEVICE_ID_TEMP_SHIFT 3
+#define DEVICE_ID_TEMP_MASK(0x7 << 3)
+
+#define CTRLMMR_WKUP_JTAG_ID 0x4314
+#define JTAG_ID_VARIANT_SHIFT 28
+#define JTAG_ID_VARIANT_MASK (0xf << 28)
+#define JTAG_ID_PARTNO_SHIFT 12
+#define JTAG_ID_PARTNO_MASK(0x7ff << 1)
+
+#define CTRLMMR_WKUP_DIE_ID0 0x4320
+#define CTRLMMR_WKUP_DIE_ID1 0x4324
+#define CTRLMMR_WKUP_DIE_ID2 0x4328
+#define CTRLMMR_WKUP_DIE_ID3 0x432c
+#define CTRLMMR_WKUP_BOOTCFG 0x4334
+
#endif /* _ASM_ARCH_HARDWARE_H_ */
--
2.23.0
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[U-Boot] [PATCH 5/5] arm: k3: Use driver_name to get ti_sci handle
Use the driver name to get ti_sci handle rather than relying
on just the FIRMWARE uclass.
Signed-off-by: Lokesh Vutla
---
arch/arm/mach-k3/common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 7339d7398d..32712e5883 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -36,7 +36,8 @@ struct ti_sci_handle *get_ti_sci_handle(void)
struct udevice *dev;
int ret;
- ret = uclass_get_device(UCLASS_FIRMWARE, 0, &dev);
+ ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
+ DM_GET_DRIVER(ti_sci), &dev);
if (ret)
panic("Failed to get SYSFW (%d)\n", ret);
--
2.23.0
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[U-Boot] [PATCH 4/5] configs: am65x_evm_a53: Enable DISPLAY_CPUINFO
Enable CONFIG_DISPLAY_CPUINFO so that cpuinfo is printed during boot.
Signed-off-by: Lokesh Vutla
---
configs/am65x_evm_a53_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 17065a3813..cb7140a574 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -19,7 +19,6 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
--
2.23.0
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[U-Boot] [PATCH 2/5] board: am65x: Print board name and version during boot
Print the board name and ver along with the DT Model.
While at it print the ver for all the detected daughter cards.
Signed-off-by: Lokesh Vutla
---
board/ti/am65x/evm.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index e01adcd642..4de1eb4de0 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -116,6 +116,19 @@ int do_board_detect(void)
return ret;
}
+int checkboard(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ if (do_board_detect())
+ /* EEPROM not populated */
+ printf("Board: %s ver %s\n", "AM6-COMPROCEVM", "E3");
+ else
+ printf("Board: %s ver %s\n", ep->name, ep->version);
+
+ return 0;
+}
+
static void setup_board_eeprom_env(void)
{
char *name = "am65x";
@@ -261,7 +274,7 @@ static int probe_daughtercards(void)
if (strncmp(ep.name, cards[i].card_name, sizeof(ep.name)))
continue;
- printf("detected %s\n", cards[i].card_name);
+ printf("Detected: %s ver %s\n", ep.name, ep.version);
/*
* Populate any MAC addresses from daughtercard into the U-Boot
--
2.23.0
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[U-Boot] [PATCH 3/5] configs: j721e_evm_a72: Enable DISPLAY_CPUINFO
Enable CONFIG_DISPLAY_CPUINFO so that cpuinfo is printed during boot.
Signed-off-by: Lokesh Vutla
---
configs/j721e_evm_a72_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 46667da36e..cc8f99d21d 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -20,7 +20,6 @@ CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
--
2.23.0
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[U-Boot] [PATCH 0/5] arm: k3: Print cpu and board names during boot
This series adds support for printing CPU name and board name for all k3 devices. Also a misc update for getting tisci handle Lokesh Vutla (5): arm: k3: Add support for printing CPUINFO board: am65x: Print board name and version during boot configs: j721e_evm_a72: Enable DISPLAY_CPUINFO configs: am65x_evm_a53: Enable DISPLAY_CPUINFO arm: k3: Use driver_name to get ti_sci handle arch/arm/mach-k3/common.c| 46 +++- arch/arm/mach-k3/common.h| 15 arch/arm/mach-k3/include/mach/hardware.h | 24 + board/ti/am65x/evm.c | 15 +++- configs/am65x_evm_a53_defconfig | 1 - configs/j721e_evm_a72_defconfig | 1 - 6 files changed, 98 insertions(+), 4 deletions(-) -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] armv8: ls1028a: disable multimedia feature when not supported
Ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a.
Both ls1027a and ls1017a personalities are lower functionality version
which doesn't support the multimedia subsystems, like LCD, GPU.
To disable multimedia feature on non-multimedia version, set the status
property to disabled in dts nodes.
Signed-off-by: Tang Yuantian
---
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 19917b207a..ef0e2095a6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -401,6 +401,24 @@ void fdt_fixup_remove_jr(void *blob)
}
#endif
+static void fdt_disable_multimedia(void *blob, unsigned int svr)
+{
+ int off;
+
+ if (!((svr >> 10) & 0x1))
+ return;
+
+ /* Disable eDP/LCD node */
+ off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
+ if (off != -FDT_ERR_NOTFOUND)
+ fdt_status_disabled(blob, off);
+
+ /* Disable GPU node */
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
+ if (off != -FDT_ERR_NOTFOUND)
+ fdt_status_disabled(blob, off);
+}
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -462,4 +480,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
fdt_fixup_msi(blob);
#endif
+#ifdef CONFIG_ARCH_LS1028A
+ fdt_disable_multimedia(blob, svr);
+#endif
}
--
2.17.1
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Re: [U-Boot] rk3288 (Tinkerboard) not booting【请注意，邮件由u-boot-boun...@lists.denx.de代发】
Hi On Wed, Sep 25, 2019 at 8:19 PM Alexander von Gluck IV wrote: > > Just rounding this one out.. I was definitely looking at the wrong uart. After > moving to uart2, things are working as expected (minus hdmi output from > u-boot) This can be enabled, but it's not the default on tinker Michael > > Thanks! > > -- Alex > > September 23, 2019 9:27 AM, "Alexander von Gluck IV" > wrote: > > ACK! I'm on UART1. Mix that with video potentially not working > > in u-boot and I think I have my answer. > > > > I'll test this afternoon. > > > > (PS, since the Tinker is supposed to be "Raspberry Pi like", why would > > u-boot present on UART2 on it while the Raspberry Pi u-boot uses UART1?) > > > > Thanks for the help! > > > > -- Alex > > > > September 23, 2019 9:19 AM, "Jonathan Gray" wrote: > > > >> On Mon, Sep 23, 2019 at 01:55:32PM +, Alexander von Gluck IV wrote: > >> > >>> Oh, a difference: > >>> > >>> $ tools/mkimage -n rk3288 -T rksd -d tpl/u-boot-tpl.bin idbloader.img && \ > >>> cat spl/u-boot-spl-dtb.bin >> idbloader.img > >>> > >>> I'm using the idbloader.img that u-boot automatically spits out. > >>> > >>> $ tools/mkimage -n rk3288 -T rksd -d tpl/u-boot-tpl.bin > >>> idbloader-manual.img > >>> Image Type: Rockchip RK32 (SD/MMC) boot image > >>> Data Size: 20480 bytes > >>> $ cat spl/u-boot-spl-dtb.bin >> idbloader-manual.img > >>> > >>> However.. the generated idbloader-manual.img from the commands above is > >>> identical to idbloader.img > >>> that u-boot produces compared with md5sum. > >>> > >>> Are you writing the following? > >>> > >>> sudo dd if=idbloader.img of=/dev/sdd seek=64 > >>> sudo dd if=u-boot-dtb.img of=/dev/sdd seek=16384 > >> > >> those files/offsets yes > >> > >>> (where /dev/sdd is a MicroSD card) > >>> > >>> These should be enough to get into u-boot at startup... correct? > >> > >> yes > >> > >> I am using uart2 > >> https://www.asus.com/us/Single-Board-Computer/Tinker-Board > >> 32 UART2TX_PWM3 > >> 33 UART2RX_PWM2 > >> and 30 for ground > >> > >>> I'm not missing some requirement of u-boot.bin on a FAT32 partition or > >>> something? > >> > >> the tpl/spl and u-boot proper are at raw offsets in this case > >> > >>> -- Alex > >>> > >>> September 23, 2019 8:31 AM, "Jonathan Gray" wrote: > >>> > >>> On Mon, Sep 23, 2019 at 01:06:35PM +, Alexander von Gluck IV wrote: > >>> > >>> Ok, looking for differences now.. > >>> > >>> * Older Tinker Board? (I'm not using the Tinker Board S) > >>> > >>> yes, the original one > >>> > >>> * Same steps? > >>> > >>> along the lines of > >>> > >>> gmake CROSS_COMPILE="arm-none-eabi-" tinker-rk3288_defconfig > >>> gmake CROSS_COMPILE="arm-none-eabi-" all > >>> tools/mkimage -n rk3288 -T rksd -d tpl/u-boot-tpl.bin idbloader.img && \ > >>> cat spl/u-boot-spl-dtb.bin >> idbloader.img > >>> > >>> * Same config? tinker-rk3288_defconfig? > >>> > >>> yes > >>> > >>> * Uart 115200? > >>> > >>> yes > >>> > >>> * Any HDMI Video output? > >>> > >>> no hdmi connected only serial > >>> > >>> * GCC version? > >>> > >>> gcc-linaro-6.3.2017.02 binutils 2.27 arm-none-eabi target > >>> > >>> September 23, 2019 12:34 AM, "Jonathan Gray" wrote: > >>> > >>> On Mon, Sep 23, 2019 at 01:17:40AM +, Alexander von Gluck IV wrote: > >>> > >>> Hello! > >>> > >>> There is no uart output and no video with u-boot master. > >>> The board works as expected booting the Asus Armbian image on an SD. > >>> > >>> At this point i'd be happy to get some u-boot uart output :-) > >>> > >>> -- Alex > >>> > >>> uart output works here with the latest master > >>> (780a17e814503f71d1b51d578b32bc9c89933183) > >>> > >>> U-Boot TPL 2019.10-rc3-00401-ge23a6e5c43 (Sep 23 2019 - 15:13:20) > >>> Trying to boot from BOOTROM > >>> Returning to boot ROM... > >>> > >>> U-Boot SPL 2019.10-rc3-00401-ge23a6e5c43 (Sep 23 2019 - 15:13:20 +1000) > >>> Trying to boot from MMC1 > >>> > >>> U-Boot 2019.10-rc3-00401-ge23a6e5c43 (Sep 23 2019 - 15:13:20 +1000) > >>> > >>> Model: Tinker-RK3288 > >>> DRAM: 2 GiB > >>> MMC: dwmmc@ff0c: 1 > >>> Loading Environment from MMC... *** Warning - bad CRC, using default > >>> environment > >>> > >>> In: serial > >>> Out: serial > >>> Err: serial > >>> Model: Tinker-RK3288 > >>> rockchip_dnl_key_pressed: adc_channel_single_shot fail! > >>> Net: eth0: ethernet@ff29 > >>> Hit any key to stop autoboot: 0 > >>> switch to partitions #0, OK > >>> mmc1 is current device > >>> Scanning mmc 1:1... > >>> Found EFI removable media binary efi/boot/bootarm.efi > >>> libfdt fdt_check_header(): FDT_ERR_BADMAGIC > >>> Scanning disk dw...@ff0c.blk... > >>> Found 3 disks > >>> BootOrder not defined > >>> EFI boot manager: Cannot load any image > >>> 88176 bytes read in 9 ms (9.3 MiB/s) > >>> libfdt fdt_check_header(): FDT_ERR_BADMAGIC > >>> OpenBSD/armv7 BOOTARM 1.6 > >>> > >>> boot> > >>> ___ > >>> U-Boot mailing list > >>> U-Boot@lists.denx.de > >>> https://lists.denx.de/listinfo/u-boot > > > > _
Re: [U-Boot] [EXT] Re: Issues with driver binding and probing
Hi Simon,
On Wednesday, September 25, 2019 8:40:48 PM PDT Bin Meng wrote:
> External Email
>
> --
> +Simon
>
> Hi Aaron,
>
> On Thu, Sep 26, 2019 at 11:10 AM Aaron Williams
wrote:
> > Hi all,
> >
> > I have an issue where I have a nexus driver and a sub serial driver on top
> > of it. The base nexus driver is getting bound and probed properly,
> > however the serial drivers (pci-console) below it are not.
> >
> > My device tree looks something like this:
> > pci-console-nexus@0x0300 {
> >
> > /* Remote PCI console buffer location */
> > compatible = "marvell,pci-console-nexus";
>
> Is this a PCI controller node?
>
No, actually it points to a location in memory which is shared by a PCI host
with the software. It is a software only structure with no actual hardware
behind it. We use this as a serial console across the PCI bus, but it's just
shared memory. There is a nexus device then multiple consoles underneath it.
U-Boot will initialize the data structures (if needed) and claim one of the
consoles while it is use. The data structures may or may not already be
initialized by earlier bootloaders or the ATF. The ATF may also claim one of
the consoles.
> > status = "okay";
> > #address-cells = <2>;
> > #size-cells = <1>;
> > skip-init;
> > num-consoles = <8>;
> > reg = <0 0x0300 0 0x4>;
> > ranges = <0 0 0 0x3000100 0x4000>,
> >
> > <1 0 0 0x3004100 0x4000>,
> > <2 0 0 0x3008100 0x4000>,
> > <3 0 0 0x300c100 0x4000>,
> > <4 0 0 0x3010100 0x4000>,
> > <5 0 0 0x3014100 0x4000>,
> > <6 0 0 0x3018100 0x4000>,
> > <7 0 0 0x301c100 0x4000>;
> >
> > console@0 {
> >
> > compatible = "marvell,pci-console";
>
> If this is a PCI device, it can be handled by the PCI codes.
>
> > status = "okay";
> > reg = <0 0 0x4000>;
> > tx-buffer-size = <0x2f80>;
> > rx-buffer-size = <0x1000>;
> >
> > };
> >
> > ...
> >
> > console@7 {
> >
> > compatible = "marvell,pci-console";
> > status = "okay";
> > reg = <7 0 0x4000>;
> > tx-buffer-size = <0x2f80>;
> > rx-buffer-size = <0x1000>;
> >
> > };
> >
> > };
> >
> > When U-Boot binds the drivers it sees and binds pci-console-nexus but it
> > never even attempts to go any deeper in the device tree. Both drivers are
> > used. The nexus datastructure is a shared resouce that can be used by
> > ATF.
> >
> > I added a bind function in the nexus driver that basically does:
> > dev_for_each_subnode(node, parent) {
> >
> > ret = device_bind_driver_to_node(parent, DRIVER_NAME,
> >
> > ofnode_get_name(node), node,
> > &dev);
> >
> > get_uclass(UCLASS_SERIAL, &uc);
> > dev->uclass = uic;
> >
> > }
> >
> > With this I see the consoles in the dm tree and uclass list, but the
> > sequences don't seem to be getting set.
> >
> > What I notice when I type dm uclass is:
> > uclass 60: serial
> > - * serial@87e02800 @ 7fbeb3360, seq 0, (req 0)
> > - serial@87e02900 @ 7fbeb3430, seq -1, (req 1)
> > - console@0 @ 7fbeb3660
> > - console@1 @ 7fbeb3780
> > - console@2 @ 7fbeb38a0
> > - console@3 @ 7fbeb39c0
> > - console@4 @ 7fbeb3ae0
> > - console@5 @ 7fbeb3c00
> > - console@6 @ 7fbeb3d20
> > - console@7 @ 7fbeb3e40
> > - * pci-bootcmd@0x03fff000 @ 7fbeb3f60, seq 1, (req -1)
> >
> > Does anyone have any ideas on how I should properly handle this? It seems
> > that whatever I'm doing is overly complicated and I'm missing something
> > for the DM layer to not go deeper into the tree past the nexus layer.
> >
> > static const struct udevice_id octeontx_pcie_console_nexus_serial_id[] = {
> >
> > { .compatible = "marvell,pci-console-nexus", },
> > { },
> >
> > };
> >
> > U_BOOT_DRIVER(octeontx_pcie_console_nexus) = {
> >
> > .name = DRIVER_NAME "-nexus",
> > .id = UCLASS_MISC,
> > .flags = DM_FLAG_PRE_RELOC,
> > .of_match = of_match_ptr(octeontx_pcie_console_nexus_serial_id),
> > .ofdata_to_platdata =
> >
> > octeontx_pcie_console_nexus_ofdata_to_platdata,
> >
> >
Re: [U-Boot] [U-BOOT PATCH v1 0/2] add gpio support for HiFive Unleashed A00 board.
Hi Bin, On Thu, Sep 26, 2019 at 7:26 AM Bin Meng wrote: > > Hi Sagar, > > On Thu, Sep 26, 2019 at 1:54 AM Sagar Kadam wrote: > > > > Hi Bin, > > > > On Wed, Sep 18, 2019 at 1:23 PM Bin Meng wrote: > > > > > > Hi Sagar, > > > > > > On Tue, Sep 10, 2019 at 11:44 PM Sagar Shrikant Kadam > > > wrote: > > > > > > > > U-Boot currently is missing GPIO support for FU540-C000 SoC which is > > > > mounted on HiFive Unleashed A00 board. This patch is intended to add DM > > > > based GPIO controller driver in order to access GPIO pins within the SoC > > > > using GPIO command in U-Boot. More details on the GPIO controller within > > > > the SoC can be found at[1] > > > > > > > > The driver is based above master branch of u-boot-riscv.git and > > > > provides a > > > > method to configure Input/Output mode of the GPIO pin along with an > > > > option > > > > to set or clear state of the GPIO pin. The patch is available in > > > > dev/sagark/gpio_v3 branch here[2]. > > > > > > > > GPIO device node added to the mainline bound device tree for HiFive > > > > Unleashed is available in dev/sagark/mlv5.3-rc5 branch of repo here[3]. > > > > > > > > This implementation is ported from linux driver submitted for review > > > > at [4]. > > > > > > > > More details of GPIO pin routing on J1 header is available in schematic > > > > document[5] > > > > > > > > [1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf > > > > [2] https://github.com/sagsifive/u-boot > > > > [3] https://github.com/sagsifive/riscv-linux-hifive/ > > > > [4] https://lkml.org/lkml/2018/10/9/1103 > > > > [5] > > > > https://static.dev.sifive.com/dev-kits/hifive-unleashed/hifive-unleashed-a00-schematics.pdf > > > > > > > > Driver Testing: > > > > #Set GPIO1 high. > > > > =>gpio set 1 > > > > Can be confirmed by probing pin No #24 on J1 Header or memory dump of > > > > gpio register space viz: #md 0x1006 > > > > > > > > #Set GPIO1 low > > > > =>gpio clear 0 > > > > > > > > #Toggle GPIO1 > > > > =>gpio toggle 1 #Toggle value of GPIO1 > > > > =>gpio toggle 1 #Toggle value of GPIO1 > > > > > > > > #Configure pin as input > > > > =>gpio input 3 #Configure gpio line 3 as input. > > > > > > > > #Error check > > > > =>gpio set 16 #Not a valid GPIO number for FU540-C000 > > > > GPIO: '16' not found > > > > Command 'gpio' failed: Error -22 > > > > > > > > > > I tested this: > > > > > > => gpio status -a > > > Bank gpio@1006: > > > gpio@10060: unknown > > > gpio@10061: unknown > > > gpio@10062: unknown > > > gpio@10063: unknown > > > gpio@10064: unknown > > > gpio@10065: unknown > > > gpio@10066: unknown > > > gpio@10067: unknown > > > gpio@10068: unknown > > > gpio@10069: unknown > > > gpio@100610: unknown > > > gpio@100611: unknown > > > gpio@100612: unknown > > > gpio@100613: unknown > > > gpio@100614: unknown > > > gpio@100615: unknown > > > > > > The status is "unknown" for all gpio pins, which is wrong. It should > > > be either input or output. > > > > Thank you for your suggestions. > > The get_function operation is missing for this driver and so the > > status is unknown. > > I will implement it and send a revised version. Thanks for catching this. > > Please correct me if I am wrong, what I do see is that the gpio command > > uses the bank name appended before the GPIO number. So the bank_name > > as assigned in the driver probe function gets prefixed to the pin number and > > so it shows: > > gpio@10060 > > gpio@10061 > > and so on. > > I see that few driver's updates the uc_priv->bank_name in probe function > > with '_' as the separator between bank_name and pin number and so > > #gpio status -a will show it as : > > > > Bank : > > _0: input : 1 [] > > _1: input : 1 [] > > and so on > > > > eg: In the current case here it will show as > > Bank gpio@1006_: > > gpio@1006_0 > > gpio@1006_1 and so on. > > > > Please let me know if this implementation is ok. > > > > > > Also the gpio pin name is weird. I think we should use "0, 1, 2 ..." > > > > > The current implementation of the gpio_get_status function includes > > the base_name > > to the pin description. Truncating it here can help to get pin numbers > > as just numbers > > "0,1,2". I will also include this if needed? > > > > I think _0 is fine. Thanks! > Thanks, I will roll out the next patch with necessary changes. BR, Sagar > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Issues with driver binding and probing
+Simon
Hi Aaron,
On Thu, Sep 26, 2019 at 11:10 AM Aaron Williams wrote:
>
> Hi all,
>
> I have an issue where I have a nexus driver and a sub serial driver on top of
> it. The base nexus driver is getting bound and probed properly, however the
> serial drivers (pci-console) below it are not.
>
> My device tree looks something like this:
>
> pci-console-nexus@0x0300 {
> /* Remote PCI console buffer location */
> compatible = "marvell,pci-console-nexus";
Is this a PCI controller node?
> status = "okay";
> #address-cells = <2>;
> #size-cells = <1>;
> skip-init;
> num-consoles = <8>;
> reg = <0 0x0300 0 0x4>;
> ranges = <0 0 0 0x3000100 0x4000>,
> <1 0 0 0x3004100 0x4000>,
> <2 0 0 0x3008100 0x4000>,
> <3 0 0 0x300c100 0x4000>,
> <4 0 0 0x3010100 0x4000>,
> <5 0 0 0x3014100 0x4000>,
> <6 0 0 0x3018100 0x4000>,
> <7 0 0 0x301c100 0x4000>;
> console@0 {
> compatible = "marvell,pci-console";
If this is a PCI device, it can be handled by the PCI codes.
> status = "okay";
> reg = <0 0 0x4000>;
> tx-buffer-size = <0x2f80>;
> rx-buffer-size = <0x1000>;
> };
> ...
> console@7 {
> compatible = "marvell,pci-console";
> status = "okay";
> reg = <7 0 0x4000>;
> tx-buffer-size = <0x2f80>;
> rx-buffer-size = <0x1000>;
> };
> };
>
> When U-Boot binds the drivers it sees and binds pci-console-nexus but it never
> even attempts to go any deeper in the device tree. Both drivers are used. The
> nexus datastructure is a shared resouce that can be used by ATF.
>
> I added a bind function in the nexus driver that basically does:
> dev_for_each_subnode(node, parent) {
> ret = device_bind_driver_to_node(parent, DRIVER_NAME,
> ofnode_get_name(node), node,
> &dev);
> get_uclass(UCLASS_SERIAL, &uc);
> dev->uclass = uic;
> }
>
> With this I see the consoles in the dm tree and uclass list, but the sequences
> don't seem to be getting set.
>
> What I notice when I type dm uclass is:
> uclass 60: serial
> - * serial@87e02800 @ 7fbeb3360, seq 0, (req 0)
> - serial@87e02900 @ 7fbeb3430, seq -1, (req 1)
> - console@0 @ 7fbeb3660
> - console@1 @ 7fbeb3780
> - console@2 @ 7fbeb38a0
> - console@3 @ 7fbeb39c0
> - console@4 @ 7fbeb3ae0
> - console@5 @ 7fbeb3c00
> - console@6 @ 7fbeb3d20
> - console@7 @ 7fbeb3e40
> - * pci-bootcmd@0x03fff000 @ 7fbeb3f60, seq 1, (req -1)
>
> Does anyone have any ideas on how I should properly handle this? It seems that
> whatever I'm doing is overly complicated and I'm missing something for the DM
> layer to not go deeper into the tree past the nexus layer.
>
> static const struct udevice_id octeontx_pcie_console_nexus_serial_id[] = {
> { .compatible = "marvell,pci-console-nexus", },
> { },
> };
>
> U_BOOT_DRIVER(octeontx_pcie_console_nexus) = {
> .name = DRIVER_NAME "-nexus",
> .id = UCLASS_MISC,
> .flags = DM_FLAG_PRE_RELOC,
> .of_match = of_match_ptr(octeontx_pcie_console_nexus_serial_id),
> .ofdata_to_platdata =
> octeontx_pcie_console_nexus_ofdata_to_platdata,
> .platdata_auto_alloc_size =
> sizeof(struct octeontx_pcie_console_plat_data),
> .bind = octeontx_pcie_console_nexus_bind,
> .probe = octeontx_pcie_console_nexus_probe,
> .priv_auto_alloc_size =
> sizeof(struct octeontx_pcie_console_nexus_priv),
> };
>
> static const struct dm_serial_ops octeontx_pcie_console_ops = {
> .setbrg = octeontx_pcie_console_setbrg,
> .getc = octeontx_pcie_console_getc,
> .putc = octeontx_pcie_console_putc,
> .pending = octeontx_pcie_console_pending,
> .clear = octeontx_pcie_console_clear,
> };
>
> static const struct udevice_id octeontx_pcie_console_serial_id[] = {
> { .compatible = "marvell,pci-console", },
> { },
> };
>
> U_BOOT_DRIVER(octeontx_pcie_console) = {
> .name = DRIVER_NAME,
> .id = UCLASS_SERIAL,
> .ops = &octeontx_pcie_console_ops,
> .of_match = of_match_ptr(octeontx_pcie_console_serial_id),
> .probe = octeontx_pcie_console_probe,
> .ofdata_to_platdata = octeontx_pcie_console_ofdata_to_platdata,
> .remove = octeontx_pcie_console_remove,
> .priv_auto_alloc_size = siz
Re: [U-Boot] [EXT] Re: [RFC 1/3] scsi: ata: Add DM SCSI interface to support None AHCI sata driver
Hi Robert, Thanks very much for your comments, please see my comments inline. >-Original Message- >From: Robert Hancock >Sent: 2019年9月25日 23:50 >To: Peng Ma ; s...@chromium.org; Prabhakar X >; ja...@openedev.com; >bmeng...@gmail.com; Andy Tang >Cc: andre.przyw...@arm.com; michal.si...@xilinx.com; >u-boot@lists.denx.de; sm...@web.de; s...@denx.de >Subject: [EXT] Re: [U-Boot] [RFC 1/3] scsi: ata: Add DM SCSI interface to >support None AHCI sata driver > >Caution: EXT Email > >On 2019-09-25 3:54 a.m., Peng Ma wrote: >> In driver/ata. If the sata driver support AHCI mode, there will >> provides a complete set of SCSI interface. If the sata is not support >> AHCI >> mode(NONE_AHCI) there will not provides the SCSI interface. >> >> This patch is to support SCSI interface for None AHCI sata such as >> fsl_sata.c sil_sata.c etc. > >The patch rationale seems strange - SATA controllers don't inherently provide a >SCSI interface regardless of whether they are AHCI or not. In the Linux kernel, >SATA devices are supported using the SCSI layer via SCSI to ATA translation, >which is a standardized mapping, largely in order to reuse a bunch of code - >and U-Boot could choose to do the same >- but AHCI controllers are handled the same way as all other SATA controllers >in >that regard by Linux, so I'm not sure why that distinction is being made here. > [Peng Ma] For Linux: If the sata controller fallow AHCI: Vendor_init > ahci_platform_init_host(struct ata_port_operations ahci_ops) ---> ata_host_register > ata_scsi_add_hosts .. If the sata controller not fallow AHCI: Vendor_init(struct ata_port_operations sata_xxx _ops) > ata_host_register > ata_scsi_add_hosts .. For U-boot: If the sata controller fallow AHCI: The devices: UCLASS_BLK>UCLASS_SCSI>UCLASS_AHCI(just call ata interface) The drivers: Vendor_init > ahci_probe_scsi(struct scsi_ops scsi_ops) then the devices will bind(ahci_bind_scsi) the driver during uboot init. If the sata controller not fallow AHCI: Not Support: We shold support for None AHCI sata with scsi interface like as follows: The devices: UCLASS_BLK>UCLASS_SCSI>UCLASS_NONE_AHCI The drivers: Vendor_init (struct scsi_ops scsi_ops) then the devices will bind(ata_bind_scsi) the driver during uboot init. Note: On U-boot the The ATA lib just provide some common interface. Best Regards, Peng >> >> Signed-off-by: Peng Ma >> --- >> drivers/ata/Kconfig | 17 +++- >> drivers/ata/Makefile | 2 + >> drivers/ata/ata-uclass.c | 16 >> drivers/ata/ata.c| 244 >+++ >> drivers/ata/sata.c | 2 +- >> drivers/ata/scsi_ata.h | 43 + >> include/dm/uclass-id.h | 1 + >> 7 files changed, 323 insertions(+), 2 deletions(-) create mode >> 100644 drivers/ata/ata-uclass.c create mode 100644 drivers/ata/ata.c >> create mode 100644 drivers/ata/scsi_ata.h >> >> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index >> 87636ae..3d6db2e 100644 >> --- a/drivers/ata/Kconfig >> +++ b/drivers/ata/Kconfig >> @@ -7,6 +7,13 @@ config AHCI >> operations at present. The block device interface has not been >converted >> to driver model. >> >> +config NONE_AHCI >> + bool "Support None AHCI SATA controllers with driver model" >> + depends on DM >> + help >> + This enables a uclass for disk controllers in U-Boot. such as AHCI. >> It >> + support None AHCI sata with DM mode >> + >> config SATA >> bool "Support SATA controllers" >> select HAVE_BLOCK_DEVICE >> @@ -32,6 +39,15 @@ config SCSI_AHCI >> help >> Enable this to allow interfacing SATA devices via the SCSI layer. >> >> +config SCSI_NONE_AHCI >> + bool "Enable SCSI interface to None AHCI SATA devices" >> + select LIBATA >> + select SCSI >> + select DM_SCSI >> + help >> + Enable this to allow interfacing None AHCI SATA devices via the DM >> + SCSI layer. >> + >> menu "SATA/SCSI device support" >> >> config AHCI_PCI >> @@ -49,7 +65,6 @@ config SATA_CEVA >> ZynqMP. Support up to 2 external devices. Complient with SATA >3.1 and >> AHCI 1.3 specifications with hot-plug detect feature. >> >> - >> config DWC_AHCI >> bool "Enable Synopsys DWC AHCI driver support" >> select SCSI_AHCI >> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index >> 6e03384..cddbdc8 100644 >> --- a/drivers/ata/Makefile >> +++ b/drivers/ata/Makefile >> @@ -6,8 +6,10 @@ >> obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o >> obj-$(CONFIG_FSL_AHCI) += fsl_ahci.o >> obj-$(CONFIG_AHCI) += ahci-uclass.o >> +obj-$(CONFIG_NONE_AHCI) += ata-uclass.o >> obj-$(CONFIG_AHCI_PCI) += ahci-pci.o >> obj-$(CONFIG_SCSI_AHCI) += ahci.o >> +obj-$(CONFIG_SCSI_NONE_AHCI) += ata.o >> obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o >> obj-$(CONFIG_FSL_SATA) += fsl_sata.o >> obj-$(CONFIG_LIBATA) += lib
[U-Boot] Issues with driver binding and probing
Hi all,
I have an issue where I have a nexus driver and a sub serial driver on top of
it. The base nexus driver is getting bound and probed properly, however the
serial drivers (pci-console) below it are not.
My device tree looks something like this:
pci-console-nexus@0x0300 {
/* Remote PCI console buffer location */
compatible = "marvell,pci-console-nexus";
status = "okay";
#address-cells = <2>;
#size-cells = <1>;
skip-init;
num-consoles = <8>;
reg = <0 0x0300 0 0x4>;
ranges = <0 0 0 0x3000100 0x4000>,
<1 0 0 0x3004100 0x4000>,
<2 0 0 0x3008100 0x4000>,
<3 0 0 0x300c100 0x4000>,
<4 0 0 0x3010100 0x4000>,
<5 0 0 0x3014100 0x4000>,
<6 0 0 0x3018100 0x4000>,
<7 0 0 0x301c100 0x4000>;
console@0 {
compatible = "marvell,pci-console";
status = "okay";
reg = <0 0 0x4000>;
tx-buffer-size = <0x2f80>;
rx-buffer-size = <0x1000>;
};
...
console@7 {
compatible = "marvell,pci-console";
status = "okay";
reg = <7 0 0x4000>;
tx-buffer-size = <0x2f80>;
rx-buffer-size = <0x1000>;
};
};
When U-Boot binds the drivers it sees and binds pci-console-nexus but it never
even attempts to go any deeper in the device tree. Both drivers are used. The
nexus datastructure is a shared resouce that can be used by ATF.
I added a bind function in the nexus driver that basically does:
dev_for_each_subnode(node, parent) {
ret = device_bind_driver_to_node(parent, DRIVER_NAME,
ofnode_get_name(node), node,
&dev);
get_uclass(UCLASS_SERIAL, &uc);
dev->uclass = uic;
}
With this I see the consoles in the dm tree and uclass list, but the sequences
don't seem to be getting set.
What I notice when I type dm uclass is:
uclass 60: serial
- * serial@87e02800 @ 7fbeb3360, seq 0, (req 0)
- serial@87e02900 @ 7fbeb3430, seq -1, (req 1)
- console@0 @ 7fbeb3660
- console@1 @ 7fbeb3780
- console@2 @ 7fbeb38a0
- console@3 @ 7fbeb39c0
- console@4 @ 7fbeb3ae0
- console@5 @ 7fbeb3c00
- console@6 @ 7fbeb3d20
- console@7 @ 7fbeb3e40
- * pci-bootcmd@0x03fff000 @ 7fbeb3f60, seq 1, (req -1)
Does anyone have any ideas on how I should properly handle this? It seems that
whatever I'm doing is overly complicated and I'm missing something for the DM
layer to not go deeper into the tree past the nexus layer.
static const struct udevice_id octeontx_pcie_console_nexus_serial_id[] = {
{ .compatible = "marvell,pci-console-nexus", },
{ },
};
U_BOOT_DRIVER(octeontx_pcie_console_nexus) = {
.name = DRIVER_NAME "-nexus",
.id = UCLASS_MISC,
.flags = DM_FLAG_PRE_RELOC,
.of_match = of_match_ptr(octeontx_pcie_console_nexus_serial_id),
.ofdata_to_platdata =
octeontx_pcie_console_nexus_ofdata_to_platdata,
.platdata_auto_alloc_size =
sizeof(struct octeontx_pcie_console_plat_data),
.bind = octeontx_pcie_console_nexus_bind,
.probe = octeontx_pcie_console_nexus_probe,
.priv_auto_alloc_size =
sizeof(struct octeontx_pcie_console_nexus_priv),
};
static const struct dm_serial_ops octeontx_pcie_console_ops = {
.setbrg = octeontx_pcie_console_setbrg,
.getc = octeontx_pcie_console_getc,
.putc = octeontx_pcie_console_putc,
.pending = octeontx_pcie_console_pending,
.clear = octeontx_pcie_console_clear,
};
static const struct udevice_id octeontx_pcie_console_serial_id[] = {
{ .compatible = "marvell,pci-console", },
{ },
};
U_BOOT_DRIVER(octeontx_pcie_console) = {
.name = DRIVER_NAME,
.id = UCLASS_SERIAL,
.ops = &octeontx_pcie_console_ops,
.of_match = of_match_ptr(octeontx_pcie_console_serial_id),
.probe = octeontx_pcie_console_probe,
.ofdata_to_platdata = octeontx_pcie_console_ofdata_to_platdata,
.remove = octeontx_pcie_console_remove,
.priv_auto_alloc_size = sizeof(struct octeontx_pcie_console_priv),
.platdata_auto_alloc_size =
sizeof(struct octeontx_pcie_console_plat_data),
.flags = DM_FLAG_OS_PREPARE | DM_FLAG_PRE_RELOC,
};
-Aaron
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Re: [U-Boot] [PATCH] Support raw initrd for qemu riscv64 targets.
On 2019-09-26, Bin Meng wrote: > On Thu, Sep 26, 2019 at 8:57 AM Vagrant Cascadian wrote: >> On 2019-07-15, Vagrant Cascadian wrote: >> > This allows booting an initrd without headers generated by mkimage, >> > which is generally needed when using distro_bootcmd with >> > extlinux-style boot menus. >> > >> > Signed-off-by: Vagrant Cascadian >> > --- >> > >> > configs/qemu-riscv64_defconfig | 1 + >> > configs/qemu-riscv64_smode_defconfig | 1 + >> > 2 files changed, 2 insertions(+) >> > >> > diff --git a/configs/qemu-riscv64_defconfig >> > b/configs/qemu-riscv64_defconfig >> > index 19a5849226..c0c893a90c 100644 >> > --- a/configs/qemu-riscv64_defconfig >> > +++ b/configs/qemu-riscv64_defconfig >> > @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y >> > CONFIG_DISPLAY_BOARDINFO=y >> > # CONFIG_CMD_MII is not set >> > CONFIG_OF_PRIOR_STAGE=y >> > +CONFIG_SUPPORT_RAW_INITRD=y >> > diff --git a/configs/qemu-riscv64_smode_defconfig >> > b/configs/qemu-riscv64_smode_defconfig >> > index 74743a5ebe..ef7d358daa 100644 >> > --- a/configs/qemu-riscv64_smode_defconfig >> > +++ b/configs/qemu-riscv64_smode_defconfig >> > @@ -9,3 +9,4 @@ CONFIG_DISPLAY_CPUINFO=y >> > CONFIG_DISPLAY_BOARDINFO=y >> > # CONFIG_CMD_MII is not set >> > CONFIG_OF_PRIOR_STAGE=y >> > +CONFIG_SUPPORT_RAW_INITRD=y > > Isn't this already selected by DISTRO_DEFAULTS? You're right; it must be leftovers on my end from very old patch series. No need to add this patch, sorry for the noise! live well, vagrant signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Support raw initrd for qemu riscv64 targets.
Hi Vagrant, On Thu, Sep 26, 2019 at 8:57 AM Vagrant Cascadian wrote: > > Haven't heard any comment on this; is there someone better to CC? > Sorry I missed this. > Would be really nice if it could be considered for v2019.10. > > Thanks! > > live well, > vagrant > > On 2019-07-15, Vagrant Cascadian wrote: > > This allows booting an initrd without headers generated by mkimage, > > which is generally needed when using distro_bootcmd with > > extlinux-style boot menus. > > > > Signed-off-by: Vagrant Cascadian > > --- > > > > configs/qemu-riscv64_defconfig | 1 + > > configs/qemu-riscv64_smode_defconfig | 1 + > > 2 files changed, 2 insertions(+) > > > > diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig > > index 19a5849226..c0c893a90c 100644 > > --- a/configs/qemu-riscv64_defconfig > > +++ b/configs/qemu-riscv64_defconfig > > @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y > > CONFIG_DISPLAY_BOARDINFO=y > > # CONFIG_CMD_MII is not set > > CONFIG_OF_PRIOR_STAGE=y > > +CONFIG_SUPPORT_RAW_INITRD=y > > diff --git a/configs/qemu-riscv64_smode_defconfig > > b/configs/qemu-riscv64_smode_defconfig > > index 74743a5ebe..ef7d358daa 100644 > > --- a/configs/qemu-riscv64_smode_defconfig > > +++ b/configs/qemu-riscv64_smode_defconfig > > @@ -9,3 +9,4 @@ CONFIG_DISPLAY_CPUINFO=y > > CONFIG_DISPLAY_BOARDINFO=y > > # CONFIG_CMD_MII is not set > > CONFIG_OF_PRIOR_STAGE=y > > +CONFIG_SUPPORT_RAW_INITRD=y Isn't this already selected by DISTRO_DEFAULTS? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-BOOT PATCH v1 0/2] add gpio support for HiFive Unleashed A00 board.
Hi Sagar, On Thu, Sep 26, 2019 at 1:54 AM Sagar Kadam wrote: > > Hi Bin, > > On Wed, Sep 18, 2019 at 1:23 PM Bin Meng wrote: > > > > Hi Sagar, > > > > On Tue, Sep 10, 2019 at 11:44 PM Sagar Shrikant Kadam > > wrote: > > > > > > U-Boot currently is missing GPIO support for FU540-C000 SoC which is > > > mounted on HiFive Unleashed A00 board. This patch is intended to add DM > > > based GPIO controller driver in order to access GPIO pins within the SoC > > > using GPIO command in U-Boot. More details on the GPIO controller within > > > the SoC can be found at[1] > > > > > > The driver is based above master branch of u-boot-riscv.git and provides a > > > method to configure Input/Output mode of the GPIO pin along with an option > > > to set or clear state of the GPIO pin. The patch is available in > > > dev/sagark/gpio_v3 branch here[2]. > > > > > > GPIO device node added to the mainline bound device tree for HiFive > > > Unleashed is available in dev/sagark/mlv5.3-rc5 branch of repo here[3]. > > > > > > This implementation is ported from linux driver submitted for review > > > at [4]. > > > > > > More details of GPIO pin routing on J1 header is available in schematic > > > document[5] > > > > > > [1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf > > > [2] https://github.com/sagsifive/u-boot > > > [3] https://github.com/sagsifive/riscv-linux-hifive/ > > > [4] https://lkml.org/lkml/2018/10/9/1103 > > > [5] > > > https://static.dev.sifive.com/dev-kits/hifive-unleashed/hifive-unleashed-a00-schematics.pdf > > > > > > Driver Testing: > > > #Set GPIO1 high. > > > =>gpio set 1 > > > Can be confirmed by probing pin No #24 on J1 Header or memory dump of > > > gpio register space viz: #md 0x1006 > > > > > > #Set GPIO1 low > > > =>gpio clear 0 > > > > > > #Toggle GPIO1 > > > =>gpio toggle 1 #Toggle value of GPIO1 > > > =>gpio toggle 1 #Toggle value of GPIO1 > > > > > > #Configure pin as input > > > =>gpio input 3 #Configure gpio line 3 as input. > > > > > > #Error check > > > =>gpio set 16 #Not a valid GPIO number for FU540-C000 > > > GPIO: '16' not found > > > Command 'gpio' failed: Error -22 > > > > > > > I tested this: > > > > => gpio status -a > > Bank gpio@1006: > > gpio@10060: unknown > > gpio@10061: unknown > > gpio@10062: unknown > > gpio@10063: unknown > > gpio@10064: unknown > > gpio@10065: unknown > > gpio@10066: unknown > > gpio@10067: unknown > > gpio@10068: unknown > > gpio@10069: unknown > > gpio@100610: unknown > > gpio@100611: unknown > > gpio@100612: unknown > > gpio@100613: unknown > > gpio@100614: unknown > > gpio@100615: unknown > > > > The status is "unknown" for all gpio pins, which is wrong. It should > > be either input or output. > > Thank you for your suggestions. > The get_function operation is missing for this driver and so the > status is unknown. > I will implement it and send a revised version. Thanks for catching this. > Please correct me if I am wrong, what I do see is that the gpio command > uses the bank name appended before the GPIO number. So the bank_name > as assigned in the driver probe function gets prefixed to the pin number and > so it shows: > gpio@10060 > gpio@10061 > and so on. > I see that few driver's updates the uc_priv->bank_name in probe function > with '_' as the separator between bank_name and pin number and so > #gpio status -a will show it as : > > Bank : > _0: input : 1 [] > _1: input : 1 [] > and so on > > eg: In the current case here it will show as > Bank gpio@1006_: > gpio@1006_0 > gpio@1006_1 and so on. > > Please let me know if this implementation is ok. > > > > Also the gpio pin name is weird. I think we should use "0, 1, 2 ..." > > > The current implementation of the gpio_get_status function includes > the base_name > to the pin description. Truncating it here can help to get pin numbers > as just numbers > "0,1,2". I will also include this if needed? > I think _0 is fine. Thanks! Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] qemu-riscv64_smode, sifive-fu540: fix extlinux (define preboot)
On 2019-08-21, David Abdurachmanov wrote:
> Commit 37304aaf60bf92a5dc3ef222ba520698bd862a44 removed preboot
> commands in RISC-V targets and broke extlinux support as reported
> by Fu Wei .
>
> The patch finishes migration of CONFIG_USE_PREBOOT and CONFIG_REBOOT
> to Kconfig.
Tested using qemu-riscv64_smode and it fixes extlinux booting. Thanks!
Please CC me on future updates to the patch series.
Tested-by: Vagrant Cascadian
live well,
vagrant
> Signed-off-by: David Abdurachmanov
> ---
> configs/qemu-riscv64_smode_defconfig | 2 ++
> configs/sifive_fu540_defconfig | 2 ++
> include/configs/sifive-fu540.h | 4
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/configs/qemu-riscv64_smode_defconfig
> b/configs/qemu-riscv64_smode_defconfig
> index 74743a5ebe..2e1f7fa91f 100644
> --- a/configs/qemu-riscv64_smode_defconfig
> +++ b/configs/qemu-riscv64_smode_defconfig
> @@ -9,3 +9,5 @@ CONFIG_DISPLAY_CPUINFO=y
> CONFIG_DISPLAY_BOARDINFO=y
> # CONFIG_CMD_MII is not set
> CONFIG_OF_PRIOR_STAGE=y
> +CONFIG_USE_PREBOOT=y
> +CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr
> ${fdtcontroladdr};"
> diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
> index 48865e5f11..a852579309 100644
> --- a/configs/sifive_fu540_defconfig
> +++ b/configs/sifive_fu540_defconfig
> @@ -9,3 +9,5 @@ CONFIG_MISC_INIT_R=y
> CONFIG_DISPLAY_CPUINFO=y
> CONFIG_DISPLAY_BOARDINFO=y
> CONFIG_OF_PRIOR_STAGE=y
> +CONFIG_USE_PREBOOT=y
> +CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr
> ${fdtcontroladdr};"
> diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
> index 858b7a7da1..ba4aa0652c 100644
> --- a/include/configs/sifive-fu540.h
> +++ b/include/configs/sifive-fu540.h
> @@ -40,8 +40,4 @@
> "ramdisk_addr_r=0x8830\0" \
> BOOTENV
>
> -#define CONFIG_PREBOOT \
> - "setenv fdt_addr ${fdtcontroladdr};" \
> - "fdt addr ${fdtcontroladdr};"
> -
> #endif /* __CONFIG_H */
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Re: [U-Boot] [PATCH] Support raw initrd for qemu riscv64 targets.
Haven't heard any comment on this; is there someone better to CC? Would be really nice if it could be considered for v2019.10. Thanks! live well, vagrant On 2019-07-15, Vagrant Cascadian wrote: > This allows booting an initrd without headers generated by mkimage, > which is generally needed when using distro_bootcmd with > extlinux-style boot menus. > > Signed-off-by: Vagrant Cascadian > --- > > configs/qemu-riscv64_defconfig | 1 + > configs/qemu-riscv64_smode_defconfig | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig > index 19a5849226..c0c893a90c 100644 > --- a/configs/qemu-riscv64_defconfig > +++ b/configs/qemu-riscv64_defconfig > @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y > CONFIG_DISPLAY_BOARDINFO=y > # CONFIG_CMD_MII is not set > CONFIG_OF_PRIOR_STAGE=y > +CONFIG_SUPPORT_RAW_INITRD=y > diff --git a/configs/qemu-riscv64_smode_defconfig > b/configs/qemu-riscv64_smode_defconfig > index 74743a5ebe..ef7d358daa 100644 > --- a/configs/qemu-riscv64_smode_defconfig > +++ b/configs/qemu-riscv64_smode_defconfig > @@ -9,3 +9,4 @@ CONFIG_DISPLAY_CPUINFO=y > CONFIG_DISPLAY_BOARDINFO=y > # CONFIG_CMD_MII is not set > CONFIG_OF_PRIOR_STAGE=y > +CONFIG_SUPPORT_RAW_INITRD=y > -- > 2.20.1 signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] ARM: i.MX6: TARGET_NITROGEN6X: add 'select MX6QDL'
This fixes commit <91435cd40d30> "ARM: i.MX6: exclude the ARM errata from i.MX6 UP system" for nitrogen6x. The above commit removed the errata for the board since MX6Q/MXDL/MX6S is selected via CONFIG_SYS_EXTRA_OPTIONS This restores the errata configs. Signed-off-by: Troy Kisky --- Note: marsboard, mx6qarm2, seem to have same problem. --- arch/arm/mach-imx/mx6/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 01f0121beb..2c2edaa093 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -412,6 +412,7 @@ config TARGET_NITROGEN6X imply USB_ETHER_MCS7830 imply USB_ETHER_SMSC95XX imply USB_HOST_ETHER + select MX6QDL config TARGET_OPOS6ULDEV bool "Armadeus OPOS6ULDev board" -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 4/4] ci: add envtools support
On Mon, Aug 26, 2019 at 01:06:18PM +0200, Pierre-Jean Texier wrote: > This commit add envtools suppport to CI to verify if there > is no build issues. > > Signed-off-by: Pierre-Jean Texier > Acked-by: Heiko Schocher > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/4] fw_env: fix build error
On Mon, Aug 26, 2019 at 01:06:16PM +0200, Pierre-Jean Texier wrote:
> The following error appears:
>
> tools/env/fw_env.c:1149:25: error: lvalue required as unary ‘&’ operand
> rc = write(fd, &ENV_REDUND_OBSOLETE, sizeof(ENV_REDUND_OBSOLETE));
>
> Fixes: d3716dd ("env: Rename the redundancy flags")
>
> Signed-off-by: Pierre-Jean Texier
> Tested-by: Joris Offouga
> Tested-by: Heiko Schocher
> Suggested-by: Heiko Schocher
> Acked-by: Joe Hershberger
Applied to u-boot/master, thanks!
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Re: [U-Boot] [PATCH v2 3/4] env: add missing header file
On Mon, Aug 26, 2019 at 01:06:17PM +0200, Pierre-Jean Texier wrote:
> Since commit af95f20 ("env: Create a new file for environment functions"),
> a new header file exists.
>
> So, this commit add a missing header file.
>
> Fixes:
>
> include/env.h:158:1: error: unknown type name ‘ulong’; did you mean ‘long’?
> ulong env_get_ulong(const char *name, int base, ulong default_val);
> ^
> long
> include/env.h:158:49: error: unknown type name ‘ulong’; did you mean ‘long’?
> ulong env_get_ulong(const char *name, int base, ulong default_val);
>
> Signed-off-by: Pierre-Jean Texier
> Tested-by: Joris Offouga
> Tested-by: Heiko Schocher
> Acked-by: Joe Hershberger
Applied to u-boot/master, thanks!
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Re: [U-Boot] [PATCH v2 1/4] fw_env: remove duplicated definitions
On Mon, Aug 26, 2019 at 01:06:15PM +0200, Pierre-Jean Texier wrote:
> Since commit d3716dd ("env: Rename the redundancy flags"), the
> definitions of ENV_REDUND_OBSOLETE & ENV_REDUND_ACTIVE was moved
> to env.h.
>
> Fixes:
>
> tools/env/fw_env.c:122:22: error: ‘ENV_REDUND_ACTIVE’ redeclared as different
> kind of symbol
> static unsigned char ENV_REDUND_ACTIVE = 1;
> ^
> In file included from tools/env/fw_env.c:13:
> include/env.h:63:2: note: previous definition of ‘ENV_REDUND_ACTIVE’ was here
> ENV_REDUND_ACTIVE = 1,
> ^
> tools/env/fw_env.c:127:22: error: ‘ENV_REDUND_OBSOLETE’ redeclared as
> different kind of symbol
> static unsigned char ENV_REDUND_OBSOLETE;
> ^~~
> In file included from tools/env/fw_env.c:13:
> include/env.h:62:2: note: previous definition of ‘ENV_REDUND_OBSOLETE’ was
> here
> ENV_REDUND_OBSOLETE = 0,
>
> Signed-off-by: Pierre-Jean Texier
> Tested-by: Joris Offouga
> Tested-by: Heiko Schocher
> Acked-by: Joe Hershberger
Applied to u-boot/master, thanks!
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Re: [U-Boot] [PATCH] rockchip: misc: read the correct number of bytes from the efuse
> On 25.09.2019, at 20:40, Heiko Stuebner wrote:
>
> Originally the cpuid var the value gets read into was defined as
>u8 cpuid[RK3399_CPUID_LEN];
> hence the sizeof(cpuid) would return the correct the correct number
> of array elements.
>
> With the move to a separate function cpuid becomes a pointer and
> sizeof(cpuid) hence returns the pointer size - 8 in the arm64 case.
>
> We do have the actual id length available as function param so use
> it for actual amount of bytes to read.
>
> Fixes: 04825384999f ("rockchip: rk3399: derive ethaddr from cpuid")
> Signed-off-by: Heiko Stuebner
Reviewed-by: Philipp Tomsich
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Re: [U-Boot] [PATCH v2 8/9] spl: Introduce SPL_DM_GPIO Kconfig define
On Wed, Sep 25, 2019 at 02:42:03PM -0600, Simon Glass wrote: > Hi Lukasz, > > On Tue, 17 Sep 2019 at 15:06, Lukasz Majewski wrote: > > > > On Tue, 17 Sep 2019 14:19:33 -0500 > > Adam Ford wrote: > > > > > On Tue, Sep 17, 2019 at 1:34 PM Simon Glass wrote: > > > > > > > > Hi Lukasz, > > > > > > > > On Tue, 17 Sep 2019 at 00:22, Lukasz Majewski > > > > wrote: > > > > > > > > > > Hi Simon, > > > > > > > > > > > On Sun, 18 Aug 2019 at 19:30, Peng Fan > > > > > > wrote: > > > > > > > > > > > > > > > Subject: [PATCH v2 8/9] spl: Introduce SPL_DM_GPIO Kconfig > > > > > > > > define > > > > > > > > > > > > > > > > This define indicates if DM_GPIO shall be supported in SPL. > > > > > > > > This allows proper operation of DM converted GPIO drivers > > > > > > > > in SPL, which use #if !CONFIG_IS_ENABLED(DM_GPIO) to also > > > > > > > > support not yet DM/DTS converted boards. > > > > > > > > > > > > > > Many of the drivers list the SPL_DM options under their respective > > > heading. For example, SPL_DM_USB is under the USB menu right next to > > > the option to select CONFIG_DM_USB. > > > If we're going to add the option to separate DM_GPIO from SPL_DM_GPIO, > > > I would suggest following that pattern and place it in the GPIO menu > > > so they are next to each other and make the dependency obvious. > > > > For the current patch I've followed the pattern and added SPL_DM_GPIO > > to the "spl" submenu of menuconfig. > > > > And as I've written in the other mail - I think that SPL_DM_GPIO shall > > depend on DM_GPIO. > > > > Considering the above - shall I place SPL_DM_GPIO next to DM_GPIO > > section or to the "spl" submenu? > > That makes sense to me. At some point we should change them all. > > +Tom Rini for comment too Should we get consistent? Yes. One of our not yet solved well enough problems is what are we going to do about SPL/TPL, image size and conflicting requirements. For now I think having these options be in the spl menu makes some future shuffling easier to do. -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 8/9] spl: Introduce SPL_DM_GPIO Kconfig define
Hi Lukasz, On Tue, 17 Sep 2019 at 15:06, Lukasz Majewski wrote: > > On Tue, 17 Sep 2019 14:19:33 -0500 > Adam Ford wrote: > > > On Tue, Sep 17, 2019 at 1:34 PM Simon Glass wrote: > > > > > > Hi Lukasz, > > > > > > On Tue, 17 Sep 2019 at 00:22, Lukasz Majewski > > > wrote: > > > > > > > > Hi Simon, > > > > > > > > > On Sun, 18 Aug 2019 at 19:30, Peng Fan > > > > > wrote: > > > > > > > > > > > > > Subject: [PATCH v2 8/9] spl: Introduce SPL_DM_GPIO Kconfig > > > > > > > define > > > > > > > > > > > > > > This define indicates if DM_GPIO shall be supported in SPL. > > > > > > > This allows proper operation of DM converted GPIO drivers > > > > > > > in SPL, which use #if !CONFIG_IS_ENABLED(DM_GPIO) to also > > > > > > > support not yet DM/DTS converted boards. > > > > > > > > > > > Many of the drivers list the SPL_DM options under their respective > > heading. For example, SPL_DM_USB is under the USB menu right next to > > the option to select CONFIG_DM_USB. > > If we're going to add the option to separate DM_GPIO from SPL_DM_GPIO, > > I would suggest following that pattern and place it in the GPIO menu > > so they are next to each other and make the dependency obvious. > > For the current patch I've followed the pattern and added SPL_DM_GPIO > to the "spl" submenu of menuconfig. > > And as I've written in the other mail - I think that SPL_DM_GPIO shall > depend on DM_GPIO. > > Considering the above - shall I place SPL_DM_GPIO next to DM_GPIO > section or to the "spl" submenu? That makes sense to me. At some point we should change them all. +Tom Rini for comment too Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC 05/15] include: image.h: export hash algorithm helper functions
On Tue, 17 Sep 2019 at 19:23, AKASHI Takahiro
wrote:
>
> This commit allows us to use common/image-sig.c even if CONFIG_FIT
> is disabled but CONFIG_EFI_LOADER is enabled.
>
> Signed-off-by: AKASHI Takahiro
> ---
> include/image.h | 15 +--
> 1 file changed, 9 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass
BTW I think it should be possible to remove these things in the header
file now. Please see below.
>
> diff --git a/include/image.h b/include/image.h
> index 685f5181c829..c9fe1d8eaed8 100644
> --- a/include/image.h
> +++ b/include/image.h
> @@ -53,7 +53,7 @@ struct fdt_region;
>
> #endif /* USE_HOSTCC */
>
> -#if IMAGE_ENABLE_FIT
> +#if IMAGE_ENABLE_FIT || defined(CONFIG_EFI_SECURE_BOOT)
> #include
> #include
> #include
> @@ -86,13 +86,14 @@ struct fdt_region;
> #endif
>
> #if defined(CONFIG_FIT_ENABLE_SHA256_SUPPORT) || \
> - defined(CONFIG_SPL_SHA256_SUPPORT)
> + defined(CONFIG_SPL_SHA256_SUPPORT) || \
> + defined(CONFIG_EFI_SECURE_BOOT)
> #define IMAGE_ENABLE_SHA2561
> #else
> #define IMAGE_ENABLE_SHA2560
> #endif
We can probably use (in the C file):
if (IS_ENABLED(CONFIG_...) || IS_ENABLED(CONFIG_...) ...
>
> -#endif /* IMAGE_ENABLE_FIT */
> +#endif /* IMAGE_ENABLE_FIT || defined(CONFIG_EFI_SECURE_BOOT) */
>
> #ifdef CONFIG_SYS_BOOT_GET_CMDLINE
> # define IMAGE_BOOT_GET_CMDLINE1
> @@ -1085,6 +1086,7 @@ int fit_conf_get_prop_node(const void *fit, int noffset,
>
> int fit_check_ramdisk(const void *fit, int os_noffset,
> uint8_t arch, int verify);
> +#endif /* IMAGE_ENABLE_FIT */
>
> int calculate_hash(const void *data, int data_len, const char *algo,
> uint8_t *value, int *value_len);
> @@ -1143,7 +1145,6 @@ struct image_sign_info {
> const char *require_keys; /* Value for 'required' property */
> const char *engine_id; /* Engine to use for signing */
> };
> -#endif /* Allow struct image_region to always be defined for rsa.h */
>
> /* A part of an image, used for hashing */
> struct image_region {
> @@ -1151,7 +1152,7 @@ struct image_region {
> int size;
> };
>
> -#if IMAGE_ENABLE_FIT
> +#if IMAGE_ENABLE_FIT || defined(CONFIG_EFI_SECURE_BOOT)
>
> #if IMAGE_ENABLE_VERIFY
> # include
> @@ -1252,7 +1253,9 @@ struct crypto_algo *image_get_crypto_algo(const char
> *full_name);
> * @return pointer to algorithm information, or NULL if not found
> */
> struct padding_algo *image_get_padding_algo(const char *name);
> +#endif /* IMAGE_ENABLE_FIT || defined(CONFIG_EFI_SECURE_BOOT) */
>
> +#if IMAGE_ENABLE_FIT
> /**
> * fit_image_verify_required_sigs() - Verify signatures marked as 'required'
> *
> @@ -1328,7 +1331,7 @@ static inline int fit_image_check_target_arch(const
> void *fdt, int node)
> #define fit_unsupported(msg)
> #define fit_unsupported_reset(msg)
> #endif /* CONFIG_FIT_VERBOSE */
> -#endif /* CONFIG_FIT */
> +#endif /* IMAGE_ENABLE_FIT */
>
> #if defined(CONFIG_ANDROID_BOOT_IMAGE)
> struct andr_img_hdr;
> --
> 2.21.0
>
Regards,
Simon
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Re: [U-Boot] [RFC 04/15] include: image.h: add key info to image_sign_info
Hi AKASHI,
On Tue, 17 Sep 2019 at 19:23, AKASHI Takahiro
wrote:
>
> For FIT verification, all the properties of a public key come from
> "control fdt" pointed to by fdt_blob. In UEFI secure boot, on the other
> hand, a public key is located and retrieved from dedicated signature
> database stored as UEFI variables.
>
> Added two fields may hold values of a public key if fdt_blob is NULL, and
> will be used in rsa_verify_with_pkey() to verify a signature in UEFI
> sub-system.
>
> Signed-off-by: AKASHI Takahiro
> ---
> include/image.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/image.h b/include/image.h
> index 97b6a82d9754..685f5181c829 100644
> --- a/include/image.h
> +++ b/include/image.h
> @@ -1136,6 +1136,8 @@ struct image_sign_info {
> struct checksum_algo *checksum; /* Checksum algorithm information */
> struct padding_algo *padding; /* Padding algorithm information */
> struct crypto_algo *crypto; /* Crypto algorithm information */
> + const void *key;
> + int keylen;
Please do add comments.
Also if these only relate to EFI they should have efi_ prefix and
probably an #ifdef.
> const void *fdt_blob; /* FDT containing public keys */
> int required_keynode; /* Node offset of key to use: -1=any
> */
> const char *require_keys; /* Value for 'required' property */
> --
> 2.21.0
>
Regards,
Simon
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[U-Boot] [PATCH] initcall.h: initcall_run_list(): Improve debug output
From: Ovidiu Panait
Existing debug output is mixed with the function name:
initcall_run_list() initcall: 25263initcall_run_list() (relocated to 425263)
Turn it to:
initcall_run_list() initcall: 25263 (relocated to 425263)
Signed-off-by: Ovidiu Panait
---
include/initcall.h | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/include/initcall.h b/include/initcall.h
index 78d15afe69..b5acdd01bd 100644
--- a/include/initcall.h
+++ b/include/initcall.h
@@ -30,11 +30,13 @@ static inline int initcall_run_list(const init_fnc_t
init_sequence[])
#ifdef CONFIG_EFI_APP
reloc_ofs = (unsigned long)image_base;
#endif
- debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs);
if (reloc_ofs)
- debug(" (relocated to %p)\n", (char *)*init_fnc_ptr);
+ debug("initcall: %p (relocated to %p)\n",
+ (char *)*init_fnc_ptr - reloc_ofs,
+ (char *)*init_fnc_ptr);
else
- debug("\n");
+ debug("initcall: %p\n", (char *)*init_fnc_ptr -
reloc_ofs);
+
ret = (*init_fnc_ptr)();
if (ret) {
printf("initcall sequence %p failed at call %p
(err=%d)\n",
--
2.20.1
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Re: [U-Boot] [PATCH 3/7] cmd: bootimg: Add bootimg command
Hi Sam, On Tue, 24 Sep 2019 at 11:41, Sam Protsenko wrote: > > Hi Igor, > > On Mon, Sep 23, 2019 at 11:36 PM Igor Opaniuk wrote: > > > > Hi Simon, > > > > On Fri, Sep 20, 2019 at 8:45 PM Simon Glass wrote: > > > > > > Hi, > > > > > > On Thu, 19 Sep 2019 at 12:28, Sam Protsenko > > > wrote: > > > > > > > > This command can be used to extract fields and image payloads from > > > > Android Boot Image. It can be used for example to implement boot flow > > > > where dtb is taken from boot.img (as v2 incorporated dtb inside of > > > > boot.img). Using this command, one can obtain needed dtb file from > > > > boot.img in scripting manner, and then apply needed dtbo's (from "dtbo" > > > > partition) on top of that, providing then the resulting image to bootm > > > > command in order to boot the Android. > > > > > > > > Also right now this command has the sub-command to get an address and > > > > size of recovery dtbo from recovery image. It can be further parsed > > > > using > > > > 'dtimg' command and merged into dtb file (for non-A/B devices only, see > > > > [1,2] for details). > > > > > > > > [1] https://source.android.com/devices/bootloader/boot-image-header > > > > [2] https://source.android.com/devices/architecture/dto/partitions > > > > > > > > Signed-off-by: Sam Protsenko > > > > --- > > > > cmd/Kconfig | 8 +++ > > > > cmd/Makefile | 1 + > > > > cmd/bootimg.c | 177 ++ > > > > 3 files changed, 186 insertions(+) > > > > create mode 100644 cmd/bootimg.c > > > > > > > > > Shouldn't this be a subcommand of avb? > > > > I think there is some misunderstanding here, as avb > > is used only for signature verification/roll-back protection, other > > aspects of booting Android (parsing android boot image) are > > handled by other commands (for instance, bootm). > > > > Howewer, I think (IMHO) that `bootimg` isn't a good choice for the > > command name , which major functionality is manipulating > > dtb/dtbos. > > > > Actually, 'bootimg' manipulates only Android boot image, but new > Android Boot Image v2 happen to have DTB field. For DTBO files in > Android we already have 'dtimg' command. > > Simon, > > This command is not connected with AVB. It's only needed to obtain > Android Boot Image payloads. We can't integrate its functionality in > 'bootm' command, because we would need to merge some DTBO files (from > 'dtbo' partition) into DTB file obtained from boot image. And bootm > command can't possibly know which DTBO files vendor would like to use > (e.g. different DTBOs for different boards). That's why I came up with > 'bootimg' command. OK, so can we say this is specific to Android. So perhaps 'boota' ? Minor point - boom allows passing an image address rather than requiring loadaddr to be set. > > Actually I think that we should think about implementing > 'boot_android' next. Because the boot script is becoming quite > cluttered. But we should have those tiny commands anyway, as it's > convenient for development and provides a more flexible way to boot > Android. Agreed on both counts. > > I'm having presentation today at Linaro Connect, highlighting new > Android boot scheme. Slides will be available at [1]. The Android boot > flow becomes more and more extensive, so I think it's time to start > discussion between community, Google and vendors w.r.t. this topic. > One point we should bring up is the possibility to use FIT image > instead of bunch of Android images. I hope this is discussable. That sounds like a good idea. > > But for now I think we should stick to established Android boot > architecture, as it was published at [2] and mandatory for new devices > launching with Android 10. OK. Let's make sure to add sandbox tests for new functionality too. - SImon > > Thanks! > > [1] https://connect.linaro.org/resources/san19/san19-217/ > [2] https://source.android.com/devices/bootloader > > > > > > > Regards, > > > Simon > > > > > > > > -- > > Best regards - Freundliche Grüsse - Meilleures salutations > > > > Igor Opaniuk > > > > mailto: igor.opan...@gmail.com > > skype: igor.opanyuk > > +380 (93) 836 40 67 > > http://ua.linkedin.com/in/iopaniuk ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] rockchip: misc: read the correct number of bytes from the efuse
Originally the cpuid var the value gets read into was defined as
u8 cpuid[RK3399_CPUID_LEN];
hence the sizeof(cpuid) would return the correct the correct number
of array elements.
With the move to a separate function cpuid becomes a pointer and
sizeof(cpuid) hence returns the pointer size - 8 in the arm64 case.
We do have the actual id length available as function param so use
it for actual amount of bytes to read.
Fixes: 04825384999f ("rockchip: rk3399: derive ethaddr from cpuid")
Signed-off-by: Heiko Stuebner
---
arch/arm/mach-rockchip/misc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c
index 4423b296b1..bed4317f7e 100644
--- a/arch/arm/mach-rockchip/misc.c
+++ b/arch/arm/mach-rockchip/misc.c
@@ -75,7 +75,7 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
}
/* read the cpu_id range from the efuses */
- ret = misc_read(dev, cpuid_offset, cpuid, sizeof(cpuid));
+ ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length);
if (ret) {
debug("%s: reading cpuid from the efuses failed\n",
__func__);
--
2.23.0
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Re: [U-Boot] rk3288 (Tinkerboard) not booting【请注意，邮件由u-boot-boun...@lists.denx.de代发】
Just rounding this one out.. I was definitely looking at the wrong uart. After moving to uart2, things are working as expected (minus hdmi output from u-boot) Thanks! -- Alex September 23, 2019 9:27 AM, "Alexander von Gluck IV" wrote: > ACK! I'm on UART1. Mix that with video potentially not working > in u-boot and I think I have my answer. > > I'll test this afternoon. > > (PS, since the Tinker is supposed to be "Raspberry Pi like", why would > u-boot present on UART2 on it while the Raspberry Pi u-boot uses UART1?) > > Thanks for the help! > > -- Alex > > September 23, 2019 9:19 AM, "Jonathan Gray" wrote: > >> On Mon, Sep 23, 2019 at 01:55:32PM +, Alexander von Gluck IV wrote: >> >>> Oh, a difference: >>> >>> $ tools/mkimage -n rk3288 -T rksd -d tpl/u-boot-tpl.bin idbloader.img && \ >>> cat spl/u-boot-spl-dtb.bin >> idbloader.img >>> >>> I'm using the idbloader.img that u-boot automatically spits out. >>> >>> $ tools/mkimage -n rk3288 -T rksd -d tpl/u-boot-tpl.bin idbloader-manual.img >>> Image Type: Rockchip RK32 (SD/MMC) boot image >>> Data Size: 20480 bytes >>> $ cat spl/u-boot-spl-dtb.bin >> idbloader-manual.img >>> >>> However.. the generated idbloader-manual.img from the commands above is >>> identical to idbloader.img >>> that u-boot produces compared with md5sum. >>> >>> Are you writing the following? >>> >>> sudo dd if=idbloader.img of=/dev/sdd seek=64 >>> sudo dd if=u-boot-dtb.img of=/dev/sdd seek=16384 >> >> those files/offsets yes >> >>> (where /dev/sdd is a MicroSD card) >>> >>> These should be enough to get into u-boot at startup... correct? >> >> yes >> >> I am using uart2 >> https://www.asus.com/us/Single-Board-Computer/Tinker-Board >> 32 UART2TX_PWM3 >> 33 UART2RX_PWM2 >> and 30 for ground >> >>> I'm not missing some requirement of u-boot.bin on a FAT32 partition or >>> something? >> >> the tpl/spl and u-boot proper are at raw offsets in this case >> >>> -- Alex >>> >>> September 23, 2019 8:31 AM, "Jonathan Gray" wrote: >>> >>> On Mon, Sep 23, 2019 at 01:06:35PM +, Alexander von Gluck IV wrote: >>> >>> Ok, looking for differences now.. >>> >>> * Older Tinker Board? (I'm not using the Tinker Board S) >>> >>> yes, the original one >>> >>> * Same steps? >>> >>> along the lines of >>> >>> gmake CROSS_COMPILE="arm-none-eabi-" tinker-rk3288_defconfig >>> gmake CROSS_COMPILE="arm-none-eabi-" all >>> tools/mkimage -n rk3288 -T rksd -d tpl/u-boot-tpl.bin idbloader.img && \ >>> cat spl/u-boot-spl-dtb.bin >> idbloader.img >>> >>> * Same config? tinker-rk3288_defconfig? >>> >>> yes >>> >>> * Uart 115200? >>> >>> yes >>> >>> * Any HDMI Video output? >>> >>> no hdmi connected only serial >>> >>> * GCC version? >>> >>> gcc-linaro-6.3.2017.02 binutils 2.27 arm-none-eabi target >>> >>> September 23, 2019 12:34 AM, "Jonathan Gray" wrote: >>> >>> On Mon, Sep 23, 2019 at 01:17:40AM +, Alexander von Gluck IV wrote: >>> >>> Hello! >>> >>> There is no uart output and no video with u-boot master. >>> The board works as expected booting the Asus Armbian image on an SD. >>> >>> At this point i'd be happy to get some u-boot uart output :-) >>> >>> -- Alex >>> >>> uart output works here with the latest master >>> (780a17e814503f71d1b51d578b32bc9c89933183) >>> >>> U-Boot TPL 2019.10-rc3-00401-ge23a6e5c43 (Sep 23 2019 - 15:13:20) >>> Trying to boot from BOOTROM >>> Returning to boot ROM... >>> >>> U-Boot SPL 2019.10-rc3-00401-ge23a6e5c43 (Sep 23 2019 - 15:13:20 +1000) >>> Trying to boot from MMC1 >>> >>> U-Boot 2019.10-rc3-00401-ge23a6e5c43 (Sep 23 2019 - 15:13:20 +1000) >>> >>> Model: Tinker-RK3288 >>> DRAM: 2 GiB >>> MMC: dwmmc@ff0c: 1 >>> Loading Environment from MMC... *** Warning - bad CRC, using default >>> environment >>> >>> In: serial >>> Out: serial >>> Err: serial >>> Model: Tinker-RK3288 >>> rockchip_dnl_key_pressed: adc_channel_single_shot fail! >>> Net: eth0: ethernet@ff29 >>> Hit any key to stop autoboot: 0 >>> switch to partitions #0, OK >>> mmc1 is current device >>> Scanning mmc 1:1... >>> Found EFI removable media binary efi/boot/bootarm.efi >>> libfdt fdt_check_header(): FDT_ERR_BADMAGIC >>> Scanning disk dw...@ff0c.blk... >>> Found 3 disks >>> BootOrder not defined >>> EFI boot manager: Cannot load any image >>> 88176 bytes read in 9 ms (9.3 MiB/s) >>> libfdt fdt_check_header(): FDT_ERR_BADMAGIC >>> OpenBSD/armv7 BOOTARM 1.6 >>> >>> boot> >>> ___ >>> U-Boot mailing list >>> U-Boot@lists.denx.de >>> https://lists.denx.de/listinfo/u-boot > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-BOOT PATCH v1 1/2] gpio: fu540: add support for DM based gpio driver for FU540-SoC
Hi Bin,
On Wed, Sep 18, 2019 at 3:09 PM Bin Meng wrote:
>
> Hi Sagar,
>
> On Tue, Sep 10, 2019 at 11:44 PM Sagar Shrikant Kadam
> wrote:
> >
> > This patch adds a DM based driver model for gpio controller present in
> > FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO
> > bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and
> > GPIO15 are routed to the J1 header on the board.
> >
> > This implementation is ported from linux based gpio driver submitted
> > for review by Wesley W. Terpstra and/or Atish Patra
> > (many thanks !!). The linux driver can be referred
> > here [1]
> >
> > [1]: https://lkml.org/lkml/2018/10/9/1103
> >
> > Signed-off-by: Sagar Shrikant Kadam
> > ---
> > arch/riscv/include/asm/arch-generic/gpio.h | 35 +++
> > arch/riscv/include/asm/gpio.h | 6 ++
> > drivers/gpio/Kconfig | 8 ++
> > drivers/gpio/Makefile | 1 +
> > drivers/gpio/sifive-gpio.c | 143
> > +
> > 5 files changed, 193 insertions(+)
> > create mode 100644 arch/riscv/include/asm/arch-generic/gpio.h
> > create mode 100644 arch/riscv/include/asm/gpio.h
> > create mode 100644 drivers/gpio/sifive-gpio.c
> >
> > diff --git a/arch/riscv/include/asm/arch-generic/gpio.h
> > b/arch/riscv/include/asm/arch-generic/gpio.h
> > new file mode 100644
> > index 000..7287298
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/arch-generic/gpio.h
> > @@ -0,0 +1,35 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2019 SiFive, Inc.
> > + */
> > +
> > +#ifndef _GPIO_FU540_H
>
> _GPIO_SIFIVE_H
>
> > +#define _GPIO_FU540_H
> > +
> > +#define GPIO_INPUT_VAL 0x00
> > +#define GPIO_INPUT_EN 0x04
> > +#define GPIO_OUTPUT_EN 0x08
> > +#define GPIO_OUTPUT_VAL0x0C
> > +#define GPIO_RISE_IE 0x18
> > +#define GPIO_RISE_IP 0x1C
> > +#define GPIO_FALL_IE 0x20
> > +#define GPIO_FALL_IP 0x24
> > +#define GPIO_HIGH_IE 0x28
> > +#define GPIO_HIGH_IP 0x2C
> > +#define GPIO_LOW_IE0x30
> > +#define GPIO_LOW_IP0x34
> > +#define GPIO_OUTPUT_XOR0x40
> > +
> > +#define NR_GPIOS 16
> > +
> > +enum gpio_state {
> > + LOW,
> > + HIGH
> > +};
> > +
> > +/* Details about a GPIO bank */
> > +struct fu540_gpio_platdata {
>
> sifive_gpio_platdata
>
Ok.
> > + void *base; /* address of registers in physical memory */
> > +};
> > +
> > +#endif /* _GPIO_FU540_H */
> > diff --git a/arch/riscv/include/asm/gpio.h b/arch/riscv/include/asm/gpio.h
> > new file mode 100644
> > index 000..008d756
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/gpio.h
> > @@ -0,0 +1,6 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2018 SiFive, Inc.
> > + */
> > +
> > +#include
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> > index f2dabb5..ec48f26 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -285,6 +285,14 @@ config STM32_GPIO
> > usable on many stm32 families like stm32f4/f7/h7 and stm32mp1.
> > Tested on STM32F7.
> >
> > +config SIFIVE_GPIO
> > + bool "SiFive FU540 GPIO driver"
>
> just "SiFive GPIO driver"?
>
Ok. Will exclude FU540 from above.
> > + depends on DM_GPIO
> > + help
> > + Device model driver for GPIO controller present in FU540 SoC. This
>
> present in SiFive FU540 SoC
>
> > + driver enables GPIO interface on HiFive Unleashed A00 board a
> > board
>
> remove "a board"
OK.
>
> > + from SiFive Inc. having FU540-C000 SoC.
>
> remove this line
>
Ok
> > +
> > config MVEBU_GPIO
> > bool "Marvell MVEBU GPIO driver"
> > depends on DM_GPIO && ARCH_MVEBU
> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> > index 4a8aa0f..ccc49e2 100644
> > --- a/drivers/gpio/Makefile
> > +++ b/drivers/gpio/Makefile
> > @@ -61,3 +61,4 @@ obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
> > obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
> > obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
> > obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
> > +obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
> > diff --git a/drivers/gpio/sifive-gpio.c b/drivers/gpio/sifive-gpio.c
> > new file mode 100644
> > index 000..4bf8acf
> > --- /dev/null
> > +++ b/drivers/gpio/sifive-gpio.c
> > @@ -0,0 +1,143 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * SiFive GPIO driver
> > + *
> > + * Copyright (C) 2019 SiFive, Inc.
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +static int fu540_gpio_probe(struct udevice *dev)
>
> Please rename all function names to have "sifive_" prefix.
>
Ok. I will update with all of the above changes and resend a v2.
Thanks & BR,
Sagar Kadam
> > +{
> > + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> > +
> > + uc_priv->bank_name = dev->name;
> > +
> > + /*
> > +*
Re: [U-Boot] [U-BOOT PATCH v1 0/2] add gpio support for HiFive Unleashed A00 board.
Hi Bin, On Wed, Sep 18, 2019 at 1:23 PM Bin Meng wrote: > > Hi Sagar, > > On Tue, Sep 10, 2019 at 11:44 PM Sagar Shrikant Kadam > wrote: > > > > U-Boot currently is missing GPIO support for FU540-C000 SoC which is > > mounted on HiFive Unleashed A00 board. This patch is intended to add DM > > based GPIO controller driver in order to access GPIO pins within the SoC > > using GPIO command in U-Boot. More details on the GPIO controller within > > the SoC can be found at[1] > > > > The driver is based above master branch of u-boot-riscv.git and provides a > > method to configure Input/Output mode of the GPIO pin along with an option > > to set or clear state of the GPIO pin. The patch is available in > > dev/sagark/gpio_v3 branch here[2]. > > > > GPIO device node added to the mainline bound device tree for HiFive > > Unleashed is available in dev/sagark/mlv5.3-rc5 branch of repo here[3]. > > > > This implementation is ported from linux driver submitted for review > > at [4]. > > > > More details of GPIO pin routing on J1 header is available in schematic > > document[5] > > > > [1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf > > [2] https://github.com/sagsifive/u-boot > > [3] https://github.com/sagsifive/riscv-linux-hifive/ > > [4] https://lkml.org/lkml/2018/10/9/1103 > > [5] > > https://static.dev.sifive.com/dev-kits/hifive-unleashed/hifive-unleashed-a00-schematics.pdf > > > > Driver Testing: > > #Set GPIO1 high. > > =>gpio set 1 > > Can be confirmed by probing pin No #24 on J1 Header or memory dump of > > gpio register space viz: #md 0x1006 > > > > #Set GPIO1 low > > =>gpio clear 0 > > > > #Toggle GPIO1 > > =>gpio toggle 1 #Toggle value of GPIO1 > > =>gpio toggle 1 #Toggle value of GPIO1 > > > > #Configure pin as input > > =>gpio input 3 #Configure gpio line 3 as input. > > > > #Error check > > =>gpio set 16 #Not a valid GPIO number for FU540-C000 > > GPIO: '16' not found > > Command 'gpio' failed: Error -22 > > > > I tested this: > > => gpio status -a > Bank gpio@1006: > gpio@10060: unknown > gpio@10061: unknown > gpio@10062: unknown > gpio@10063: unknown > gpio@10064: unknown > gpio@10065: unknown > gpio@10066: unknown > gpio@10067: unknown > gpio@10068: unknown > gpio@10069: unknown > gpio@100610: unknown > gpio@100611: unknown > gpio@100612: unknown > gpio@100613: unknown > gpio@100614: unknown > gpio@100615: unknown > > The status is "unknown" for all gpio pins, which is wrong. It should > be either input or output. Thank you for your suggestions. The get_function operation is missing for this driver and so the status is unknown. I will implement it and send a revised version. Thanks for catching this. Please correct me if I am wrong, what I do see is that the gpio command uses the bank name appended before the GPIO number. So the bank_name as assigned in the driver probe function gets prefixed to the pin number and so it shows: gpio@10060 gpio@10061 and so on. I see that few driver's updates the uc_priv->bank_name in probe function with '_' as the separator between bank_name and pin number and so #gpio status -a will show it as : Bank : _0: input : 1 [] _1: input : 1 [] and so on eg: In the current case here it will show as Bank gpio@1006_: gpio@1006_0 gpio@1006_1 and so on. Please let me know if this implementation is ok. > > Also the gpio pin name is weird. I think we should use "0, 1, 2 ..." > The current implementation of the gpio_get_status function includes the base_name to the pin description. Truncating it here can help to get pin numbers as just numbers "0,1,2". I will also include this if needed? Thanks & BR, Sagar Kadam > Regards, > Bin > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 002/126] dm: core: Correct low cell in ofnode_read_pci_addr()
On 9/25/19 8:55 AM, Simon Glass wrote: This reads the low cell of the PCI address from the wrong cell. Fix it. Also fix the function that this code came from. Fixes: 9e51204527 (dm: core: Add operations on device tree references) Fixes: 4ea5243a3a (fdt: fix fdtdec_get_pci_addr() for CONFIG_PHYS_64BIT) Signed-off-by: Simon Glass --- I can't work out why the existing code is correct, but I suppose it might be for some obscure reason that needs a comment. The original patch is here: http://patchwork.ozlabs.org/patch/525853/ This makes sense. I am not sure how the original code worked; I can only assume the mid/low values were always both set to 0, or unused, or something? Tested-by: Stephen Warren ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 125/126] x86: Add chromebook_coral
Add support for coral which is a range of apollolake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: Simon Glass
---
arch/x86/dts/Makefile | 1 +
arch/x86/dts/chromebook_coral.dts | 298 ++
board/google/Kconfig | 15 ++
board/google/chromebook_coral/Kconfig | 43
board/google/chromebook_coral/MAINTAINERS | 6 +
board/google/chromebook_coral/Makefile| 5 +
board/google/chromebook_coral/coral.c | 18 ++
configs/chromebook_coral_defconfig| 95 +++
doc/board/google/chromebook_coral.rst | 25 ++
include/configs/chromebook_coral.h| 29 +++
10 files changed, 535 insertions(+)
create mode 100644 arch/x86/dts/chromebook_coral.dts
create mode 100644 board/google/chromebook_coral/Kconfig
create mode 100644 board/google/chromebook_coral/MAINTAINERS
create mode 100644 board/google/chromebook_coral/Makefile
create mode 100644 board/google/chromebook_coral/coral.c
create mode 100644 configs/chromebook_coral_defconfig
create mode 100644 doc/board/google/chromebook_coral.rst
create mode 100644 include/configs/chromebook_coral.h
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index d4bdf62be6d..be209aaaf8f 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -2,6 +2,7 @@
dtb-y += bayleybay.dtb \
cherryhill.dtb \
+ chromebook_coral.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
chromebook_samus.dtb \
diff --git a/arch/x86/dts/chromebook_coral.dts
b/arch/x86/dts/chromebook_coral.dts
new file mode 100644
index 000..8f50ce2f94d
--- /dev/null
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -0,0 +1,298 @@
+/dts-v1/;
+
+#include
+
+/include/ "skeleton.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+#ifdef CONFIG_CHROMEOS
+#include "chromeos-x86.dtsi"
+#include "flashmap-x86-ro.dtsi"
+#include "flashmap-16mb-rw.dtsi"
+#endif
+
+#include
+#include
+#include
+#include
+
+/ {
+ model = "Google Coral";
+ compatible = "google,coral", "intel,apollolake";
+
+ aliases {
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = &serial;
+ };
+
+ cpus {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "intel,apl-cpu";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "intel,apl-cpu";
+ reg = <1>;
+ intel,apic-id = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "intel,apl-cpu";
+ reg = <2>;
+ intel,apic-id = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "intel,apl-cpu";
+ reg = <3>;
+ intel,apic-id = <3>;
+ };
+
+ };
+
+ keyboard {
+ intel,duplicate-por;
+ };
+
+ pci {
+ compatible = "pci-x86";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ ranges = <0x0200 0x0 0xc000 0xe000 0 0x1000
+ 0x4200 0x0 0xb000 0xd000 0 0x1000
+ 0x0100 0x0 0x1000 0x1000 0 0xefff>;
+
+ host_bridge: host-bridge@0,0 {
+ u-boot,dm-pre-reloc;
+ reg = <0x 0 0 0 0>;
+ compatible = "intel,apl-hostbridge";
+ pciex-region-size = <0x1000>;
+ };
+
+ punit@0,1 {
+ u-boot,dm-pre-reloc;
+ reg = <0x0800 0 0 0 0>;
+ compatible = "intel,apl-punit";
+ };
+
+ p2sb: p2sb@d,0 {
+ u-boot,dm-pre-reloc;
+ reg = <0x02006810 0 0 0 0>;
+ compatible = "intel,apl-p2sb";
+ early-regs = ;
+
+ gpio_n: n {
+ compatible = "intel,apl-gpio";
+ intel,p2sb-port-id = ;
+ };
+
+ nw {
+ u-boot,dm-pre-reloc;
+ compatible = "intel,apl-gpio";
+ intel,
Re: [U-Boot] [RFC 1/3] scsi: ata: Add DM SCSI interface to support None AHCI sata driver
On 2019-09-25 3:54 a.m., Peng Ma wrote:
> In driver/ata. If the sata driver support AHCI mode, there will provides
> a complete set of SCSI interface. If the sata is not support AHCI
> mode(NONE_AHCI) there will not provides the SCSI interface.
>
> This patch is to support SCSI interface for None AHCI sata such as fsl_sata.c
> sil_sata.c etc.
The patch rationale seems strange - SATA controllers don't inherently
provide a SCSI interface regardless of whether they are AHCI or not. In
the Linux kernel, SATA devices are supported using the SCSI layer via
SCSI to ATA translation, which is a standardized mapping, largely in
order to reuse a bunch of code - and U-Boot could choose to do the same
- but AHCI controllers are handled the same way as all other SATA
controllers in that regard by Linux, so I'm not sure why that
distinction is being made here.
>
> Signed-off-by: Peng Ma
> ---
> drivers/ata/Kconfig | 17 +++-
> drivers/ata/Makefile | 2 +
> drivers/ata/ata-uclass.c | 16
> drivers/ata/ata.c| 244
> +++
> drivers/ata/sata.c | 2 +-
> drivers/ata/scsi_ata.h | 43 +
> include/dm/uclass-id.h | 1 +
> 7 files changed, 323 insertions(+), 2 deletions(-)
> create mode 100644 drivers/ata/ata-uclass.c
> create mode 100644 drivers/ata/ata.c
> create mode 100644 drivers/ata/scsi_ata.h
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 87636ae..3d6db2e 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -7,6 +7,13 @@ config AHCI
> operations at present. The block device interface has not been
> converted
> to driver model.
>
> +config NONE_AHCI
> + bool "Support None AHCI SATA controllers with driver model"
> + depends on DM
> + help
> + This enables a uclass for disk controllers in U-Boot. such as AHCI. It
> + support None AHCI sata with DM mode
> +
> config SATA
> bool "Support SATA controllers"
> select HAVE_BLOCK_DEVICE
> @@ -32,6 +39,15 @@ config SCSI_AHCI
> help
> Enable this to allow interfacing SATA devices via the SCSI layer.
>
> +config SCSI_NONE_AHCI
> + bool "Enable SCSI interface to None AHCI SATA devices"
> + select LIBATA
> + select SCSI
> + select DM_SCSI
> + help
> + Enable this to allow interfacing None AHCI SATA devices via the DM
> + SCSI layer.
> +
> menu "SATA/SCSI device support"
>
> config AHCI_PCI
> @@ -49,7 +65,6 @@ config SATA_CEVA
> ZynqMP. Support up to 2 external devices. Complient with SATA 3.1 and
> AHCI 1.3 specifications with hot-plug detect feature.
>
> -
> config DWC_AHCI
> bool "Enable Synopsys DWC AHCI driver support"
> select SCSI_AHCI
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 6e03384..cddbdc8 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -6,8 +6,10 @@
> obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
> obj-$(CONFIG_FSL_AHCI) += fsl_ahci.o
> obj-$(CONFIG_AHCI) += ahci-uclass.o
> +obj-$(CONFIG_NONE_AHCI) += ata-uclass.o
> obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
> obj-$(CONFIG_SCSI_AHCI) += ahci.o
> +obj-$(CONFIG_SCSI_NONE_AHCI) += ata.o
> obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
> obj-$(CONFIG_FSL_SATA) += fsl_sata.o
> obj-$(CONFIG_LIBATA) += libata.o
> diff --git a/drivers/ata/ata-uclass.c b/drivers/ata/ata-uclass.c
> new file mode 100644
> index 000..e2cc499
> --- /dev/null
> +++ b/drivers/ata/ata-uclass.c
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 NXP, Inc
> + * Written by Peng Ma
> + */
> +
> +#include
> +#include
> +#include
> +#include "scsi_ata.h"
> +
> +UCLASS_DRIVER(ata) = {
> + .id = UCLASS_NONE_AHCI,
> + .name = "ata",
> + .per_device_auto_alloc_size = sizeof(struct ata_uc_priv),
> +};
> diff --git a/drivers/ata/ata.c b/drivers/ata/ata.c
> new file mode 100644
> index 000..bdb7403
> --- /dev/null
> +++ b/drivers/ata/ata.c
> @@ -0,0 +1,244 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) NXP, Inc. 2019.
> + * Author: Peng Ma
> + *
> + * with the reference on libata and none ahci drvier in kernel
> + *
> + * This driver provides a DM SCSI interface to None AHCI SATA.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "scsi_ata.h"
> +
> +int ata_bind_scsi(struct udevice *ata_dev, struct udevice **devp)
> +{
> + int ret;
> + struct udevice *dev;
> +
> + ret = device_bind_driver(ata_dev, "ata_scsi", "ata_scsi", &dev);
> + if (ret)
> + return ret;
> + *devp = dev;
> +
> + return 0;
> +}
> +
> +static int scsi_exec_internal(struct udevice *dev, struct scsi_cmd *pccb,
> + bool is_write)
> +{
> + u32 temp;
> + u16 blocks = 0;
> + int ret = -ENODEV;
> + lbaint_t start = 0;
> + u8 port
[U-Boot] [PATCH 123/126] x86: apollolake: Add Kconfig and Makefile
Add basic plumbing to allow apollolake support to be used. Signed-off-by: Simon Glass --- arch/x86/Kconfig| 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/apollolake/Kconfig | 68 + 3 files changed, 70 insertions(+) create mode 100644 arch/x86/cpu/apollolake/Kconfig diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9d01801ff13..e0e1f617ffd 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -106,6 +106,7 @@ source "board/google/Kconfig" source "board/intel/Kconfig" # platform-specific options below +source "arch/x86/cpu/apollolake/Kconfig" source "arch/x86/cpu/baytrail/Kconfig" source "arch/x86/cpu/braswell/Kconfig" source "arch/x86/cpu/broadwell/Kconfig" diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index b6a010ea320..4c151f8c94d 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -41,6 +41,7 @@ extra-y += call32.o endif obj-y += intel_common/ +obj-$(CONFIG_INTEL_APOLLOLAKE) += apollolake/ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_INTEL_BRASWELL) += braswell/ obj-$(CONFIG_INTEL_BROADWELL) += broadwell/ diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig new file mode 100644 index 000..dc78577ed03 --- /dev/null +++ b/arch/x86/cpu/apollolake/Kconfig @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2019 Google LLC +# + +config INTEL_APOLLOLAKE + bool + select FSP_VERSION2 + select HAVE_FSP + select ARCH_MISC_INIT + select USE_CAR + select INTEL_PMC + select TPL_X86_TSC_TIMER_NATIVE + select SPL_PCH_SUPPORT + select TPL_PCH_SUPPORT + select PCH_SUPPORT + select P2SB + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply SCSI + imply SCSI_AHCI + imply SPI_FLASH + imply USB + imply USB_EHCI_HCD + imply TPL + imply SPL + imply TPL_X86_16BIT_INIT + imply TPL_OF_PLATDATA + imply ITSS + imply POWER_MGR + +if INTEL_APOLLOLAKE + +config DCACHE_RAM_BASE + default 0xfef0 + +config DCACHE_RAM_SIZE + default 0xc + +config DCACHE_RAM_MRC_VAR_SIZE + default 0xb + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMM_TSEG + select X86_RAMTEST + +config SMM_TSEG_SIZE + hex + default 0x80 + +config MMCONF_BASE_ADDRESS + hex + default 0xe000 + +config INTEL_GPIO_DUAL_ROUTE_SUPPORT + def_bool y + +config INTEL_GPIO_PADCFG_PADTOL + def_bool n + +config INTEL_GPIO_IOSTANDBY + def_bool y + +config TPL_SIZE_LIMIT + default 0x7800 + +endif -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 122/126] x86: apollolake: Add P2SB driver
Adds a driver for the apollolake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/p2sb.c | 167 +++
2 files changed, 168 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/p2sb.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index f6b8caafd33..973f552cc7f 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -15,6 +15,7 @@ obj-y += gpio.o
obj-y += hostbridge.o
obj-y += itss.o
obj-y += lpc.o
+obj-y += p2sb.o
obj-y += pch.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c
new file mode 100644
index 000..5bb093361f8
--- /dev/null
+++ b/arch/x86/cpu/apollolake/p2sb.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Primary-to-Sideband Bridge
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_P2SB
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct p2sb_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_p2sb dtplat;
+#endif
+ ulong mmio_base;
+ pci_dev_t bdf;
+};
+
+/* PCI config space registers */
+#define HPTC_OFFSET0x60
+#define HPTC_ADDR_ENABLE_BIT (1 << 7)
+
+/* High Performance Event Timer Configuration */
+#define P2SB_HPTC 0x60
+#define P2SB_HPTC_ADDRESS_ENABLE (1 << 7)
+
+/*
+ * ADDRESS_SELECTENCODING_RANGE
+ * 0 0xfed0 - 0xfed0 03ff
+ * 1 0xfed0 1000 - 0xfed0 13ff
+ * 2 0xfed0 2000 - 0xfed0 23ff
+ * 3 0xfed0 3000 - 0xfed0 33ff
+ */
+#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
+
+/*
+ * apl_p2sb_early_init() - Enable decoding for HPET range
+ *
+ * This is needed for FspMemoryInit to store and retrieve a global data
+ * pointer
+ *
+ * @dev: P2SB device
+ * @return 0 if OK, -ve on error
+ */
+static int apl_p2sb_early_init(struct udevice *dev)
+{
+ struct p2sb_platdata *plat = dev_get_platdata(dev);
+ pci_dev_t pdev = plat->bdf;
+
+ /*
+* Enable decoding for HPET memory address range.
+* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
+* the High Performance Timer memory address range
+* selected by bits 1:0
+*/
+ pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
+PCI_SIZE_8);
+
+ /* Enable PCR Base address in PCH */
+ pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
+PCI_SIZE_32);
+ pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
+
+ /* Enable P2SB MSE */
+ pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
+PCI_COMMAND_MEMORY, PCI_SIZE_8);
+
+ return 0;
+}
+
+static int apl_p2sb_spl_init(struct udevice *dev)
+{
+ /* Enable decoding for HPET. Needed for FSP global pointer storage */
+ dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
+ P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
+
+ return 0;
+}
+
+int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
+ struct p2sb_platdata *plat = dev_get_platdata(dev);
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ int ret;
+
+ if (spl_phase() == PHASE_TPL) {
+ u32 base[2];
+
+ /* TPL sets up the initial BAR */
+ ret = dev_read_u32_array(dev, "early-regs", base,
+ARRAY_SIZE(base));
+ if (ret)
+ return log_msg_ret("Missing/short early-regs", ret);
+ plat->mmio_base = base[0];
+ plat->bdf = pci_x86_get_devfn(dev);
+ if (plat->bdf < 0)
+ return log_msg_ret("Cannot get p2sb PCI address",
+ plat->bdf);
+ } else {
+ plat->mmio_base = dev_read_addr_pci(dev);
+ /* Don't set BDF since it should not be used */
+ if (plat->mmio_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ }
+#else
+ plat->mmio_base = plat->dtplat.early_regs[0];
+ plat->bdf = pci_x86_ofplat_get_devfn(plat->dtplat.reg[0]);
+#endif
+ upriv->mmio_base = plat->mmio_base;
+ debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base);
+
+ return 0;
+}
+
+static int apl_p2sb_probe(struct udevice *dev)
+{
+ if (spl_phase() == PHASE_TPL)
+ return apl_p2sb
[U-Boot] [PATCH 126/126] RFC: x86: coral: Add binary MRC data
Add some pre-computed binary MRC data so that memory init does not take
nearly 30 seconds to run on the first boot.
At present every time U-Boot is flashed, coral takes nearly 30 seconds to
boot the first time. Add an initial MRC cache to speed this up. This is
somewhat dangerous since the data is taken from just one board, so your
mileage may vary.
This patch should not be applied.
Signed-off-by: Simon Glass
---
arch/x86/dts/u-boot.dtsi | 11 +++
board/google/chromebook_coral/rw-mrc-cache | Bin 0 -> 65536 bytes
board/google/chromebook_coral/rw-var-mrc-cache | Bin 0 -> 4096 bytes
3 files changed, 11 insertions(+)
create mode 100644 board/google/chromebook_coral/rw-mrc-cache
create mode 100644 board/google/chromebook_coral/rw-var-mrc-cache
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index d9a4ca1184e..bf623ba0a57 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -134,6 +134,17 @@
#endif
fdtmap {
};
+ rw-mrc-cache {
+ type = "blob";
+ offset = <0xff3e>;
+ size = <0x1>;
+ filename = "board/google/chromebook_coral/rw-mrc-cache";
+ };
+ rw-var-mrc-cache {
+ type = "blob";
+ size = <0x1000>;
+ filename = "board/google/chromebook_coral/rw-var-mrc-cache";
+ };
#ifdef CONFIG_HAVE_CMC
intel-cmc {
filename = CONFIG_CMC_FILE;
diff --git a/board/google/chromebook_coral/rw-mrc-cache
b/board/google/chromebook_coral/rw-mrc-cache
new file mode 100644
index
..931f7e251c46e03640d46756d5cb2915ec7efef4
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zooysQ0y~WWC+BzCFUJ0o011!)36KB@kN^pg011!)36Q{K6IhbTdGqA^W|Qw`5`M5W
z1gEq-JRgranQS_hD-`q7rI|`y=H=&RTb*{Z+c0*Um193Sue0(#;X%=h@}VWUM}Zc6
zrD;Q=dTr3CH%|tCH?zFaQ`GQv4SZ!o>tEKC`YrbCug4zCy{Xi{6cQi-5+DH*AOR8}
z0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq
z5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5*Skg
F{{cmnsVo2h
literal 0
HcmV?d1
diff --git a/board/google/chromebook_coral/rw-var-mrc-cache
b/board/google/chromebook_coral/rw-var-mrc-cache
new file mode 100644
index
..73183cdd778ba152dfc5f6f516f879454dbf2faf
GIT binary patch
literal 4096
zcmeYba(0nmU|@K)8%O{_^HQ&!VyE@*KzIxcmOqcVfY|?sDe#5*zxy4;$KL+SUv=~B
z>4f>;ZTlxMdzgCvKg|DfryxH5_m`tmanltinE$6a`?i7D!`1(z{u&K|(GVC7fzc2c
Y4S~@R7!85Z5Eu=C(GVC7fsqmd0PQ=I{Qv*}
literal 0
HcmV?d1
--
2.23.0.444.g18eeb5a265-goog
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 124/126] x86: apollolake: Add FSP structures
These are mostly specific to a particular SoC. Add the definitions for
apollolake.
Signed-off-by: Simon Glass
---
.../asm/arch-apollolake/fsp/fsp_configs.h | 13 ++
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 127 ++
.../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 ++
3 files changed, 151 insertions(+)
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h
diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h
b/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h
new file mode 100644
index 000..46e54e39994
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
+#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
+
+#endif
diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
new file mode 100644
index 000..a132d7f7b28
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef__ASM_ARCH_FSP_M_UDP_H
+#define__ASM_ARCH_FSP_M_UDP_H
+
+#define FSP_DRAM_CHANNELS 4
+
+struct __packed fsp_upd_header {
+ u64 signature;
+ u8 revision;
+ u8 reserved[23];
+};
+
+struct __packed fspm_arch_upd {
+ u8 revision;
+ u8 reserved[3];
+ void*nvs_buffer_ptr;
+ void*stack_base;
+ u32 stack_size;
+ u32 boot_loader_tolum_size;
+ u32 boot_mode;
+ u8 reserved1[8];
+};
+
+struct __packed fsp_ram_channel {
+ u8 rank_enable;
+ u8 device_width;
+ u8 dram_density;
+ u8 option;
+ u8 odt_config;
+ u8 tristate_clk1;
+ u8 mode2_n;
+ u8 odt_levels;
+};
+
+struct __packed fsp_m_config {
+ u32 serial_debug_port_address;
+ u8 serial_debug_port_type;
+ u8 serial_debug_port_device;
+ u8 serial_debug_port_stride_size;
+ u8 mrc_fast_boot;
+ u8 igd;
+ u8 igd_dvmt50_pre_alloc;
+ u8 igd_aperture_size;
+ u8 gtt_size;
+ u8 primary_video_adaptor;
+ u8 package;
+ u8 profile;
+ u8 memory_down;
+
+ u8 ddr3_l_page_size;
+ u8 ddr3_lasr;
+ u8 scrambler_support;
+ u8 interleaved_mode;
+ u16 channel_hash_mask;
+ u16 slice_hash_mask;
+ u8 channels_slices_enable;
+ u8 min_ref_rate2x_enable;
+ u8 dual_rank_support_enable;
+ u8 rmt_mode;
+ u16 memory_size_limit;
+ u16 low_memory_max_value;
+
+ u16 high_memory_max_value;
+ u8 disable_fast_boot;
+ u8 dimm0_spd_address;
+ u8 dimm1_spd_address;
+ struct fsp_ram_channel chan[FSP_DRAM_CHANNELS];
+ u8 rmt_check_run;
+ u16 rmt_margin_check_scale_high_threshold;
+ u8 ch_bit_swizzling[FSP_DRAM_CHANNELS][32];
+ u32 msg_level_mask;
+ u8 unused_upd_space0[4];
+
+ u8 pre_mem_gpio_table_pin_num[4];
+ u32 pre_mem_gpio_table_ptr;
+ u8 pre_mem_gpio_table_entry_num;
+ u8 enhance_port8xh_decoding;
+ u8 spd_write_enable;
+ u8 mrc_data_saving;
+ u32 oem_loading_base;
+
+ u8 oem_file_name[16];
+
+ void*mrc_boot_data_ptr;
+ u8 e_mmc_trace_len;
+ u8 skip_cse_rbp;
+ u8 npk_en;
+ u8 fw_trace_en;
+ u8 fw_trace_destination;
+ u8 recover_dump;
+ u8 msc0_wrap;
+ u8 msc1_wrap;
+ u32 msc0_size;
+
+ u32 msc1_size;
+ u8 pti_mode;
+ u8 pti_training;
+ u8 pti_speed;
+ u8 punit_mlvl;
+
+ u8 pmc_mlvl;
+ u8 sw_trace_en;
+ u8 periodic_retraining_disable;
+ u8 enable_reset_system;
+
+ u8 enable_s3_heci2;
+ u8 unused_upd_space1[3];
+
+ void*variable_nvs_buffer_ptr;
+ u8 reserved_fspm_upd[12];
+};
+
+/** Fsp M UPD Configuration */
+struct __packed fspm_upd {
+ struct fsp_upd_header header;
+ struct fspm_arch_upd arch;
+ struct fsp_m_config config;
+ u8 unused_upd_space2[158];
+ u16 upd_terminator;
+};
+
+#endif
d
[U-Boot] [PATCH 119/126] x86: apollolake: Add SPL loaders
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 2 +
arch/x86/cpu/apollolake/spl.c| 122 +++
2 files changed, 124 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/spl.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 42ba6ce9957..ba7e93c2f66 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,7 +2,9 @@
#
# Copyright (c) 2016 Google, Inc
+obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += systemagent.o
+
ifndef CONFIG_TPL_BUILD
obj-y += punit.o
endif
diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c
new file mode 100644
index 000..56fb34559f4
--- /dev/null
+++ b/arch/x86/cpu/apollolake/spl.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+/*
+ * We need to read well past the end of the region in order for execution from
+ * the loaded data to work. It is not clear why.
+ */
+#define SAFETY_MARGIN 0x4000
+
+binman_sym_declare(ulong, u_boot_spl, image_pos);
+binman_sym_declare(ulong, u_boot_spl, size);
+/* U-Boot image_pos is declared by common/spl/spl.c */
+binman_sym_declare(ulong, u_boot_any, size);
+
+static ulong get_image_pos(void)
+{
+ return spl_phase() == PHASE_TPL ?
+ binman_sym(ulong, u_boot_spl, image_pos) :
+ binman_sym(ulong, u_boot_any, image_pos);
+}
+
+static ulong get_image_size(void)
+{
+ return spl_phase() == PHASE_TPL ?
+ binman_sym(ulong, u_boot_spl, size) :
+ binman_sym(ulong, u_boot_any, size);
+}
+
+/* This reads the next phase from mapped SPI flash */
+static int rom_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ ulong spl_pos = get_image_pos();
+ ulong spl_size = get_image_size();
+ ulong map_base;
+ size_t map_size;
+ uint map_offset;
+ int ret;
+
+ spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
+ spl_image->entry_point = spl_phase() == PHASE_TPL ?
+ CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
+ spl_image->load_addr = spl_image->entry_point;
+ spl_image->os = IH_OS_U_BOOT;
+ spl_image->name = "U-Boot";
+ debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
+ ret = fast_spi_get_bios_mmap(&map_base, &map_size, &map_offset);
+ if (ret)
+ return ret;
+ spl_pos += map_base & ~0xff00;
+ debug(", base %lx, pos %lx\n", map_base, spl_pos);
+ memcpy((void *)spl_image->load_addr, (void *)spl_pos,
+ spl_size + SAFETY_MARGIN);
+
+ return 0;
+}
+SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
+
+#if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
+
+/* This uses a SPI flash device to read the next phase */
+static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ ulong spl_pos = get_image_pos();
+ ulong spl_size = get_image_size();
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
+ if (ret)
+ return ret;
+
+ spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
+ spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
+ spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
+ spl_image->os = IH_OS_U_BOOT;
+ spl_image->name = "U-Boot";
+ spl_pos &= ~0xff00;
+ debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
+ ret = spi_flash_read_dm(dev, spl_pos, spl_size + SAFETY_MARGIN,
+ (void *)spl_image->load_addr);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI,
+ spl_fast_spi_load_image);
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ bool use_spi_flash = BOOT_FROM_FAST_SPI_FLASH;
+
+ if (use_spi_flash) {
+ spl_boot_list[0] = BOOT_DEVICE_FAST_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP;
+ } else {
+ spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
+ spl_boot_list[1] = BOOT_DEVICE_FAST_SPI;
+ }
+}
+
+#else
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
+}
+#endif
--
2.23.0.444.g18eeb5a265-goog
___
U-Boot mailing list
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[U-Boot] [PATCH 121/126] x86: apollolake: Add SPL/TPL init
Add code to init the system both in TPL and SPL. Each phase has its own
procedure.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/cpu_spl.c | 272 ++
2 files changed, 273 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index c0b79ae2861..f6b8caafd33 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,6 +2,7 @@
#
# Copyright (c) 2016 Google, Inc
+obj-$(CONFIG_SPL_BUILD) += cpu_spl.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += systemagent.o
diff --git a/arch/x86/cpu/apollolake/cpu_spl.c
b/arch/x86/cpu/apollolake/cpu_spl.c
new file mode 100644
index 000..70724ba2dd2
--- /dev/null
+++ b/arch/x86/cpu/apollolake/cpu_spl.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Portions taken from coreboot
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Define this here to avoid referencing any drivers for the debug UART 1 */
+#define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0)
+
+static void pch_uart_init(void)
+{
+ /*
+* Set up the pinmux so that the UART rx/tx signals are connected
+* outside the SoC.
+*
+* There are about 500 lines of code required to program the GPIO
+* configuration for the UARTs. But it boils down to four writes, and
+* for the debug UART we want the minimum possible amount of code before
+* the UART is running. So just add the magic writes here. See
+* apl_gpio_early_init() for the full horror.
+*/
+ if (PCI_FUNC(PCH_DEV_UART) == 1) {
+ writel(0x4402, 0xd0c50650);
+ writel(0x3c47, 0xd0c50654);
+ writel(0x4400, 0xd0c50658);
+ writel(0x3c48, 0xd0c5065c);
+ } else { /* UART2 */
+ writel(0x4402, 0xd0c50670);
+ writel(0x3c4b, 0xd0c50674);
+ writel(0x4400, 0xd0c50678);
+ writel(0x3c4c, 0xd0c5067c);
+ }
+
+ apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
+}
+
+static void p2sb_enable_bar(ulong bar)
+{
+ /* Enable PCR Base address in PCH */
+ pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
+PCI_SIZE_32);
+ pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
+
+ /* Enable P2SB MSE */
+ pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
+PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
+PCI_SIZE_8);
+}
+
+/*
+ * init_for_uart() - Init the debug UART ready for use
+ *
+ * This is the minimum init needed to get the UART running. It avoids any
+ * drivers or complex code, so that the UART is running as soon as possible.
+ */
+static void init_for_uart(void)
+{
+ p2sb_enable_bar(IOMAP_P2SB_BAR);
+ pch_uart_init();
+}
+
+static int fast_spi_cache_bios_region(struct udevice *sf)
+{
+ ulong map_base;
+ size_t map_size;
+ u32 offset;
+ uintptr_t base;
+ int ret;
+
+ ret = spi_flash_get_mmap(sf, &map_base, &map_size, &offset);
+ if (ret)
+ return ret;
+
+ base = (4ULL << 30) - map_size;
+ mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
+ log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
+
+ return 0;
+}
+
+static void enable_pm_timer_emulation(struct udevice *pmc)
+{
+ struct power_mgr_upriv *upriv = dev_get_uclass_priv(pmc);
+ msr_t msr;
+
+ /*
+* The derived frequency is calculated as follows:
+*(CTC_FREQ * msr[63:32]) >> 32 = target frequency.
+*
+* Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is
+* used.
+*/
+ msr.hi = (3579545ULL << 32) / CTC_FREQ;
+
+ /* Set PM1 timer IO port and enable */
+ msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR);
+ debug("PM timer %x %x\n", msr.hi, msr.lo);
+ msr_write(MSR_EMULATE_PM_TIMER, msr);
+}
+
+static void google_chromeec_ioport_range(uint *out_basep, uint *out_sizep)
+{
+ uint base;
+ uint size;
+
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
+ base = MEC_EMI_BASE;
+ size = MEC_EMI_SIZE;
+ } else {
+ base = EC_HOST_CMD_REGION0;
+ size = 2 * EC_HOST_CMD_REGION_SIZE;
+ /* Make sure MEMMAP region follows host cmd region */
+ assert(base + size == EC_LPC_ADDR_MEMMAP);
+ size += EC_MEM
[U-Boot] [PATCH 120/126] x86: apollolake: Add a CPU driver
Add a bare-bones CPU driver so that CPUs can be probed.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/cpu.c | 51 ++
arch/x86/include/asm/arch-apollolake/cpu.h | 21 +
3 files changed, 73 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/cpu.c
create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index ba7e93c2f66..c0b79ae2861 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += systemagent.o
ifndef CONFIG_TPL_BUILD
+obj-y += cpu.o
obj-y += punit.o
endif
diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
new file mode 100644
index 000..f248623eb49
--- /dev/null
+++ b/arch/x86/cpu/apollolake/cpu.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct cpu_apollolake_priv {
+};
+
+static int apollolake_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
+}
+
+static int apollolake_get_count(struct udevice *dev)
+{
+ return 4;
+}
+
+static int cpu_x86_apollolake_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct cpu_ops cpu_x86_apollolake_ops = {
+ .get_desc = cpu_x86_get_desc,
+ .get_info = apollolake_get_info,
+ .get_count = apollolake_get_count,
+ .get_vendor = cpu_x86_get_vendor,
+};
+
+static const struct udevice_id cpu_x86_apollolake_ids[] = {
+ { .compatible = "intel,apl-cpu" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_apollolake_drv) = {
+ .name = "cpu_x86_apollolake",
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_apollolake_ids,
+ .bind = cpu_x86_bind,
+ .probe = cpu_x86_apollolake_probe,
+ .ops= &cpu_x86_apollolake_ops,
+ .priv_auto_alloc_size = sizeof(struct cpu_apollolake_priv),
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/arch/x86/include/asm/arch-apollolake/cpu.h
b/arch/x86/include/asm/arch-apollolake/cpu.h
new file mode 100644
index 000..2c5f9138ead
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/cpu.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ASM_ARCH_CPU_H
+#define __ASM_ARCH_CPU_H
+
+/* Common Timer Copy (CTC) frequency - 19.2MHz */
+#define CTC_FREQ 1920
+
+/* Set to true to use the fast SPI driver to boot, instead of mapped SPI */
+#define BOOT_FROM_FAST_SPI_FLASH false
+
+/*
+ * We need to read well past the end of the region in order for execution from
+ * the loaded data to work. It is not clear why.
+ */
+#define SAFETY_MARGIN 0x4000
+
+#endif /* __ASM_ARCH_CPU_H */
--
2.23.0.444.g18eeb5a265-goog
___
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[U-Boot] [PATCH 118/126] x86: apollolake: Add PUNIT driver
Add a driver for the apollolake power unit. It is modelled as a syscon
driver since it only needs to be probed.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 3 +
arch/x86/cpu/apollolake/punit.c | 121 +++
2 files changed, 124 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/punit.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 2760c88c153..42ba6ce9957 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -3,6 +3,9 @@
# Copyright (c) 2016 Google, Inc
obj-$(CONFIG_SPL_BUILD) += systemagent.o
+ifndef CONFIG_TPL_BUILD
+obj-y += punit.o
+endif
obj-y += gpio.o
obj-y += hostbridge.o
diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c
new file mode 100644
index 000..1bdc33aad71
--- /dev/null
+++ b/arch/x86/cpu/apollolake/punit.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct apl_punit_platdata - platform data for punit
+ *
+ * @pciex_region_size: BAR length in bytes
+ */
+struct apl_punit_platdata {
+ pci_dev_t bdf;
+};
+
+/*
+ * Punit Initialization code. This all isn't documented, but
+ * this is the recipe.
+ */
+static int punit_init(struct udevice *dev)
+{
+ struct apl_punit_platdata *plat = dev_get_platdata(dev);
+ struct udevice *cpu;
+ u32 reg;
+ ulong start;
+ int ret;
+
+ /* Thermal throttle activation offset */
+ ret = uclass_first_device_err(UCLASS_CPU, &cpu);
+ if (ret)
+ return log_msg_ret("Cannot find CPU", ret);
+ cpu_configure_thermal_target(cpu);
+
+ /*
+* Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
+* Enable all cores here.
+*/
+ writel(0, MCHBAR_REG(CORE_DISABLE_MASK));
+
+ /* P-Unit bring up */
+ reg = readl(MCHBAR_REG(BIOS_RESET_CPL));
+ if (reg == 0x) {
+ /* P-unit not found */
+ debug("Punit MMIO not available\n");
+ return -ENOENT;
+ }
+
+ /* Set Punit interrupt pin IPIN offset 3D */
+ pci_x86_write_config(plat->bdf, PCI_INTERRUPT_PIN, 0x2, PCI_SIZE_8);
+
+ /* Set PUINT IRQ to 24 and INTPIN LOCK */
+ writel(PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
+ PUINT_THERMAL_DEVICE_IRQ_LOCK,
+ MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ));
+
+ if (!IS_ENABLED(SOC_INTEL_GLK))
+ clrsetbits_le32(MCHBAR_REG(0x7818), 0x1fe0, 0x220);
+
+ /* Stage0 BIOS Reset Complete (RST_CPL) */
+ enable_bios_reset_cpl();
+
+ /*
+* Poll for bit 8 to check if PCODE has completed its action in response
+* to BIOS Reset complete. We wait here till 1 ms for the bit to get
+* set.
+*/
+ start = get_timer(0);
+ while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) {
+ if (get_timer(start) > 1) {
+ debug("PCODE Init Done timeout\n");
+ return -ETIMEDOUT;
+ }
+ udelay(100);
+ }
+ debug("PUNIT init complete\n");
+
+ return 0;
+}
+
+static int apl_punit_probe(struct udevice *dev)
+{
+ if (spl_phase() == PHASE_SPL)
+ return punit_init(dev);
+
+ return 0;
+}
+
+static int apl_punit_ofdata_to_platdata(struct udevice *dev)
+{
+ struct apl_punit_platdata *plat = dev_get_platdata(dev);
+ int root;
+
+ root = pci_x86_get_devfn(dev);
+ if (root < 0)
+ return log_msg_ret("Cannot get host-bridge PCI address", root);
+ plat->bdf = root;
+
+ return 0;
+}
+
+static const struct udevice_id apl_syscon_ids[] = {
+ { .compatible = "intel,apl-punit", .data = X86_SYSCON_PUNIT },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_intel_punit) = {
+ .name = "intel_punit_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = apl_syscon_ids,
+ .ofdata_to_platdata = apl_punit_ofdata_to_platdata,
+ .probe = apl_punit_probe,
+};
--
2.23.0.444.g18eeb5a265-goog
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[U-Boot] [PATCH 115/126] x86: apollolake: Add ITSS driver
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile| 1 +
arch/x86/cpu/apollolake/itss.c | 129
arch/x86/include/asm/arch-apollolake/itss.h | 43 +++
3 files changed, 173 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/itss.c
create mode 100644 arch/x86/include/asm/arch-apollolake/itss.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 13113fadc79..5b7b6489bb0 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -6,5 +6,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += gpio.o
obj-y += hostbridge.o
+obj-y += itss.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/itss.c b/arch/x86/cpu/apollolake/itss.c
new file mode 100644
index 000..40d2480451d
--- /dev/null
+++ b/arch/x86/cpu/apollolake/itss.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Something to do with Interrupts, but I don't know what ITSS stands for
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017 Siemens AG
+ * Copyright 2019 Google LLC
+ *
+ * Taken from coreboot itss.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct apl_itss_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_intel_apl_itss dtplat;
+#endif
+};
+
+/* struct pmc_route - Routing for PMC to GPIO */
+struct pmc_route {
+ u32 pmc;
+ u32 gpio;
+};
+
+struct apl_itss_priv {
+ struct pmc_route *route;
+ uint route_count;
+};
+
+static int apl_set_irq_polarity(struct udevice *dev, uint irq, bool active_low)
+{
+ u32 mask;
+ uint reg;
+
+ if (irq > ITSS_MAX_IRQ)
+ return -EINVAL;
+
+ reg = PCR_ITSS_IPC0_CONF + sizeof(uint32_t) * (irq / IRQS_PER_IPC);
+ mask = 1 << (irq % IRQS_PER_IPC);
+
+ pcr_clrsetbits32(dev, reg, mask, active_low ? mask : 0);
+
+ return 0;
+}
+
+static int apl_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
+{
+ struct apl_itss_priv *priv = dev_get_priv(dev);
+ struct pmc_route *route;
+ int i;
+
+ for (i = 0, route = priv->route; i < priv->route_count; i++, route++) {
+ if (pmc_gpe_num == route->pmc)
+ return route->gpio;
+ }
+
+ return -ENOENT;
+}
+
+static int apl_itss_ofdata_to_platdata(struct udevice *dev)
+{
+ struct apl_itss_priv *priv = dev_get_priv(dev);
+ int ret;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct apl_itss_platdata *plat = dev_get_platdata(dev);
+ struct dtd_intel_apl_itss *dtplat = &plat->dtplat;
+
+ /*
+* It would be nice to do this in the bind() method, but with
+* of-platdata binding happens in the order that DM finds things in the
+* linker list (i.e. alphabetical order by driver name). So the GPIO
+* device may well be bound before its parent (p2sb), and this call
+* will fail if p2sb is not bound yet.
+*
+* TODO(s...@chromium.org): Add a parent pointer to child devices in
dtoc
+*/
+ ret = p2sb_set_port_id(dev, dtplat->intel_p2sb_port_id);
+ if (ret)
+ return log_msg_ret("Could not set port id", ret);
+ priv->route = (struct pmc_route *)dtplat->intel_pmc_routes;
+ priv->route_count = ARRAY_SIZE(dtplat->intel_pmc_routes) /
+sizeof(struct pmc_route);
+#else
+ int size;
+
+ size = dev_read_size(dev, "intel,pmc-routes");
+ if (size < 0)
+ return size;
+ priv->route = malloc(size);
+ if (!priv->route)
+ return -ENOMEM;
+ ret = dev_read_u32_array(dev, "intel,pmc-routes", (u32 *)priv->route,
+size / sizeof(fdt32_t));
+ if (ret)
+ return log_msg_ret("Cannot read pmc-routes", ret);
+ priv->route_count = size / sizeof(struct pmc_route);
+#endif
+
+ return 0;
+}
+
+static const struct itss_ops apl_itss_ops = {
+ .route_pmc_gpio_gpe = apl_route_pmc_gpio_gpe,
+ .set_irq_polarity = apl_set_irq_polarity,
+};
+
+static const struct udevice_id apl_itss_ids[] = {
+ { .compatible = "intel,apl-itss"},
+ { }
+};
+
+U_BOOT_DRIVER(apl_itss_drv) = {
+ .name = "intel_apl_itss",
+ .id = UCLASS_ITSS,
+ .of_match = apl_itss_ids,
+ .ops= &apl_itss_ops,
+ .ofdata_to_platdata = apl_itss_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct apl_itss_platdata),
+ .priv_auto_alloc_size = sizeof(struct apl_itss_priv),
+};
diff --git a/arch/x86/include/asm/arch-apollolake/itss.h
b/arch/x86/include/as
[U-Boot] [PATCH 114/126] x86: apollolake: Add hostbridge driver
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/hostbridge.c | 127 +++
2 files changed, 128 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/hostbridge.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 5d5fc0b5949..13113fadc79 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -5,5 +5,6 @@
obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += gpio.o
+obj-y += hostbridge.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/hostbridge.c
b/arch/x86/cpu/apollolake/hostbridge.c
new file mode 100644
index 000..5b3cd6d292a
--- /dev/null
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct apl_hostbridge_platdata - platform data for hostbridge
+ *
+ * @pciex_region_size: BAR length in bytes
+ * @bdf: Bus/device/function of hostbridge
+ */
+struct apl_hostbridge_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_hostbridge dtplat;
+#endif
+ uint pciex_region_size;
+ pci_dev_t bdf;
+};
+
+enum {
+ PCIEXBAR= 0x60,
+ PCIEXBAR_LENGTH_256MB = 0,
+ PCIEXBAR_LENGTH_128MB,
+ PCIEXBAR_LENGTH_64MB,
+
+ PCIEXBAR_PCIEXBAREN = 1 << 0,
+
+ TSEG= 0xb8, /* TSEG base */
+};
+
+static int apl_hostbridge_early_init(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ u32 region_size;
+ u32 reg;
+ ulong base;
+
+ /* Set up the MCHBAR */
+ pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32);
+ base = MCH_BASE_ADDRESS;
+ pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32);
+
+ /*
+* The PCIEXBAR is assumed to live in the memory mapped IO space under
+* 4GiB
+*/
+ pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32);
+
+ switch (plat->pciex_region_size >> 20) {
+ default:
+ case 256:
+ region_size = PCIEXBAR_LENGTH_256MB;
+ break;
+ case 128:
+ region_size = PCIEXBAR_LENGTH_128MB;
+ break;
+ case 64:
+ region_size = PCIEXBAR_LENGTH_64MB;
+ break;
+ }
+
+ reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1)
+ | PCIEXBAR_PCIEXBAREN;
+ pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32);
+
+ /*
+* TSEG defines the base of SMM range. BIOS determines the base
+* of TSEG memory which must be at or below Graphics base of GTT
+* Stolen memory, hence its better to clear TSEG register early
+* to avoid power on default non-zero value (if any).
+*/
+ pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32);
+
+ return 0;
+}
+
+static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ int root;
+
+ /* Get length of PCI Express Region */
+ plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size",
+ 256 << 20);
+
+ root = pci_x86_get_devfn(dev);
+ if (root < 0)
+ return log_msg_ret("Cannot get host-bridge PCI address", root);
+ plat->bdf = root;
+#else
+ plat->pciex_region_size = plat->dtplat.pciex_region_size;
+ plat->bdf = pci_x86_ofplat_get_devfn(plat->dtplat.reg[0]);
+#endif
+
+ return 0;
+}
+
+static int apl_hostbridge_probe(struct udevice *dev)
+{
+ if (spl_phase() == PHASE_TPL)
+ return apl_hostbridge_early_init(dev);
+
+ return 0;
+}
+
+static const struct udevice_id apl_hostbridge_ids[] = {
+ { .compatible = "intel,apl-hostbridge" },
+ { }
+};
+
+U_BOOT_DRIVER(apl_hostbridge_drv) = {
+ .name = "intel_apl_hostbridge",
+ .id = UCLASS_NORTHBRIDGE,
+ .of_match = apl_hostbridge_ids,
+ .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata,
+ .probe = apl_hostbridge_probe,
+ .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata),
+};
--
2.23.0.444.g18eeb5a265-goog
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[U-Boot] [PATCH 111/126] x86: apollolake: Add GPIO driver
Add a driver for the apollolake GPIOs. It also handles pinctrl since this
is not very well separated on x86.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/gpio.c| 742 ++
arch/x86/include/asm/arch-apollolake/gpio.h | 156
.../include/asm/arch-apollolake/gpio_apl.h| 491
.../include/asm/arch-apollolake/gpio_defs.h | 398 ++
5 files changed, 1788 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/gpio.c
create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h
create mode 100644 arch/x86/include/asm/arch-apollolake/gpio_apl.h
create mode 100644 arch/x86/include/asm/arch-apollolake/gpio_defs.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index af7c4396619..f985018228a 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,5 +2,6 @@
#
# Copyright (c) 2016 Google, Inc
+obj-y += gpio.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/gpio.c b/arch/x86/cpu/apollolake/gpio.c
new file mode 100644
index 000..e16c06a0e2d
--- /dev/null
+++ b/arch/x86/cpu/apollolake/gpio.c
@@ -0,0 +1,742 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * Taken partly from coreboot gpio.c
+ */
+
+#define LOG_CATEGORY UCLASS_GPIO
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct apl_gpio_platdata - platform data for each device
+ *
+ * @dtplat: of-platdata data from C struct
+ * @num_cfgs: Number of configuration words for each pad
+ * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
+ * @early_pads_count: Number of pads to process
+ * @comm: Pad community for this device
+ */
+struct apl_gpio_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_intel_apl_gpio dtplat;
+#endif
+ int num_cfgs;
+ u32 *early_pads;
+ int early_pads_count;
+ const struct pad_community *comm;
+};
+
+/** struct apl_gpio_priv - private data for each device
+ *
+ * @itss: ITSS device (for interrupt handling)
+ * @itss_pol_cfg: Use to program Interrupt Polarity Control (IPCx) register
+ * Each bit represents IRQx Active High Polarity Disable configuration:
+ * when set to 1, the interrupt polarity associated with IRQx is inverted
+ * to appear as Active Low to IOAPIC and vice versa
+ */
+struct apl_gpio_priv {
+ struct udevice *itss;
+ bool itss_pol_cfg;
+};
+
+#define GPIO_DWx_SIZE(x) (sizeof(u32) * (x))
+#define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DWx_SIZE(dw_num))
+#define PAD_CFG0_OFFSET(x) PAD_CFG_OFFSET(x, 0)
+#define PAD_CFG1_OFFSET(x) PAD_CFG_OFFSET(x, 1)
+
+#define MISCCFG_GPE0_DW0_SHIFT 8
+#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
+#define MISCCFG_GPE0_DW1_SHIFT 12
+#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
+#define MISCCFG_GPE0_DW2_SHIFT 16
+#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
+
+#define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 + \
+ ((group) * sizeof(u32)))
+#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \
+ ((group) * sizeof(u32)))
+
+static const struct reset_mapping rst_map[] = {
+ { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+static const struct pad_group apl_community_n_groups[] = {
+ INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31), /* NORTH 0 */
+ INTEL_GPP(N_OFFSET, GPIO_32, JTAG_TRST_B), /* NORTH 1 */
+ INTEL_GPP(N_OFFSET, JTAG_TMS, SVID0_CLK), /* NORTH 2 */
+};
+
+static const struct pad_group apl_community_w_groups[] = {
+ INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1),/* WEST 0 */
+ INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */
+};
+
+static const struct pad_group apl_community_sw_groups[] = {
+ INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB),/* SOUTHWEST 0 */
+ INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB), /* SOUTHWEST 1 */
+};
+
+static const struct pad_group apl_community_nw_groups[] = {
+ INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B), /* NORTHWEST 0 */
+ INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106),/* NORTHWEST 1 */
+ INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123), /* NORTHWEST 2 */
+};
+
+/* TODO(s...@chromium.org): Consider moving this to device tree */
+static const struct pad_community apl_gpio_communities[] = {
+ {
+ .port = PID_GPIO_N,
+ .first_pad = N_OFFSET,
+ .last_pad = SVID0_CLK,
+ .num_gp
[U-Boot] [PATCH 116/126] x86: apollolake: Add LPC driver
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/lpc.c | 155 +
arch/x86/include/asm/arch-apollolake/lpc.h | 61
3 files changed, 217 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/lpc.c
create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 5b7b6489bb0..2bee6b6eb0d 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -7,5 +7,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += gpio.o
obj-y += hostbridge.o
obj-y += itss.o
+obj-y += lpc.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c
new file mode 100644
index 000..b528c4dc471
--- /dev/null
+++ b/arch/x86/cpu/apollolake/lpc.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ *
+ * From coreboot apollolake support lpc.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * TODO(s...@chromium.org): Move this to device tree
+static const struct pad_config lpc_gpios[] = {
+ PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
+};
+*/
+void lpc_configure_pads(void)
+{
+/* gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios)); */
+}
+
+void lpc_enable_fixed_io_ranges(uint io_enables)
+{
+ pci_x86_clrset_config(PCH_DEV_LPC, LPC_IO_ENABLES, 0, io_enables,
+ PCI_SIZE_16);
+}
+
+/*
+ * Find the first unused IO window.
+ * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ...
+ */
+static int find_unused_pmio_window(void)
+{
+ int i;
+ ulong lgir;
+
+ for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
+ pci_x86_read_config(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),
+ &lgir, PCI_SIZE_32);
+
+ if (!(lgir & LPC_LGIR_EN))
+ return i;
+ }
+
+ return -1;
+}
+
+int lpc_open_pmio_window(uint base, uint size)
+{
+ int i, lgir_reg_num;
+ u32 lgir_reg_offset, lgir, window_size, alignment;
+ ulong bridged_size, bridge_base;
+ ulong reg;
+
+ log_debug("LPC: Trying to open IO window from %x size %x\n", base,
+ size);
+
+ bridged_size = 0;
+ bridge_base = base;
+
+ while (bridged_size < size) {
+ /* Each IO range register can only open a 256-byte window */
+ window_size = min(size, (uint)LPC_LGIR_MAX_WINDOW_SIZE);
+
+ /* Window size must be a power of two for the AMASK to work */
+ alignment = 1UL << (order_base_2(window_size));
+ window_size = ALIGN(window_size, alignment);
+
+ /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18] */
+ lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
+ lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
+
+ /* Skip programming if same range already programmed */
+ for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
+ pci_x86_read_config(PCH_DEV_LPC,
+ LPC_GENERIC_IO_RANGE(i), ®,
+ PCI_SIZE_32);
+ if (lgir == reg)
+ return -EALREADY;
+ }
+
+ lgir_reg_num = find_unused_pmio_window();
+ if (lgir_reg_num < 0) {
+ log_err("LPC: Cannot open IO window: %lx size %lx\n",
+ bridge_base, size - bridged_size);
+ log_err("No more IO windows\n");
+
+ return -ENOSPC;
+ }
+ lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
+
+ pci_x86_write_config(PCH_DEV_LPC, lgir_reg_offset, lgir,
+PCI_SIZE_32);
+
+ log_debug("LPC: Opened IO window LGIR%d: base %lx size %x\n",
+ lgir_reg_num, bridge_base, window_size);
+
+ bridged_size += window_size;
+ bridge_base += window_size;
+ }
+
+ return 0;
+}
+
+void lpc_io_setup_comm_a_b(void)
+{
+ /* ComA Range 3F8h-3FFh [2:0] */
+ u16 com_ranges = LPC_IOD_C
[U-Boot] [PATCH 117/126] x86: apollolake: Add PCH driver
Add a driver for the apollolake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/pch.c | 29 ++
arch/x86/include/asm/arch-apollolake/pch.h | 9 +++
3 files changed, 39 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/pch.c
create mode 100644 arch/x86/include/asm/arch-apollolake/pch.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 2bee6b6eb0d..2760c88c153 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -8,5 +8,6 @@ obj-y += gpio.o
obj-y += hostbridge.o
obj-y += itss.o
obj-y += lpc.o
+obj-y += pch.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c
new file mode 100644
index 000..a51198f3d83
--- /dev/null
+++ b/arch/x86/cpu/apollolake/pch.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+
+static int apl_pch_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct pch_ops apl_pch_ops = {
+};
+
+static const struct udevice_id apl_pch_ids[] = {
+ { .compatible = "intel,apl-pch" },
+ { }
+};
+
+U_BOOT_DRIVER(apl_pch) = {
+ .name = "apl_pch",
+ .id = UCLASS_PCH,
+ .of_match = apl_pch_ids,
+ .probe = apl_pch_probe,
+ .ops= &apl_pch_ops,
+};
diff --git a/arch/x86/include/asm/arch-apollolake/pch.h
b/arch/x86/include/asm/arch-apollolake/pch.h
new file mode 100644
index 000..7f19903a3fe
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/pch.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ASM_ARCH_PCH_H
+#define __ASM_ARCH_PCH_H
+
+#endif /* __ASM_ARCH_PCH_H */
--
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[U-Boot] [PATCH 113/126] x86: apollolake: Add systemagent driver
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 2 ++
arch/x86/cpu/apollolake/systemagent.c | 19
.../include/asm/arch-apollolake/systemagent.h | 31 +++
3 files changed, 52 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/systemagent.c
create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index f985018228a..5d5fc0b5949 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,6 +2,8 @@
#
# Copyright (c) 2016 Google, Inc
+obj-$(CONFIG_SPL_BUILD) += systemagent.o
+
obj-y += gpio.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/systemagent.c
b/arch/x86/cpu/apollolake/systemagent.c
new file mode 100644
index 000..3a41b329c3d
--- /dev/null
+++ b/arch/x86/cpu/apollolake/systemagent.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Take from coreboot project file of the same name
+ */
+
+#include
+#include
+#include
+#include
+
+void enable_bios_reset_cpl(void)
+{
+ /*
+* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
+* that BIOS has initialised memory and power management
+*/
+ setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);
+}
diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h
b/arch/x86/include/asm/arch-apollolake/systemagent.h
new file mode 100644
index 000..5983e4e6302
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/systemagent.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Take from coreboot project file of the same name
+ */
+
+#ifndef __ARCH_SYSTEMAGENT_H
+#define __ARCH_SYSTEMAGENT_H
+
+/* Device 0:0.0 PCI configuration space */
+#define MCHBAR 0x48
+
+/* RAPL Package Power Limit register under MCHBAR */
+#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
+#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER0x18
+#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x8000
+#define BIOS_RESET_CPL 0x7078
+#define PCODE_INIT_DONE BIT(8)
+#define MCHBAR_RAPL_PPL0x70A8
+#define CORE_DISABLE_MASK 0x7168
+#define CAPID0_A 0xE4
+#define VTD_DISABLE BIT(23)
+#define DEFVTBAR 0x6c80
+#define GFXVTBAR 0x6c88
+#define VTBAR_ENABLED0x01
+#define VTBAR_MASK 0xfff000ull
+#define VTBAR_SIZE 0x1000
+
+void enable_bios_reset_cpl(void);
+
+#endif
--
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[U-Boot] [PATCH 109/126] x86: apollolake: Add PMC driver
Add a driver for the apollolake SoC. It supports the basic operations and
can use device tree or of-platdata.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile | 5 +
arch/x86/cpu/apollolake/pmc.c | 216 +
arch/x86/include/asm/arch-apollolake/pm.h | 19 ++
drivers/power/power_mgr/power-mgr-uclass.c | 51 +
4 files changed, 291 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/Makefile
create mode 100644 arch/x86/cpu/apollolake/pmc.c
create mode 100644 arch/x86/include/asm/arch-apollolake/pm.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
new file mode 100644
index 000..5d98a5a6db2
--- /dev/null
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2016 Google, Inc
+
+obj-y += pmc.o
diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c
new file mode 100644
index 000..4d27bb69ea5
--- /dev/null
+++ b/arch/x86/cpu/apollolake/pmc.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot pmclib.c, pmc.c and pmutil.c
+ */
+
+#define LOG_CATEGORY UCLASS_POWER_MGR
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define GPIO_GPE_CFG 0x1050
+
+/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
+#define PRSTS 0x1000
+#define GEN_PMCON1 0x1020
+#define COLD_BOOT_STS BIT(27)
+#define COLD_RESET_STSBIT(26)
+#define WARM_RESET_STSBIT(25)
+#define GLOBAL_RESET_STS BIT(24)
+#define SRS BIT(20)
+#define MS4V BIT(18)
+#define RPS BIT(2)
+#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \
+WARM_RESET_STS | GLOBAL_RESET_STS | \
+SRS | MS4V)
+#define GEN_PMCON2 0x1024
+#define GEN_PMCON3 0x1028
+
+/* Offset of TCO registers from ACPI base I/O address */
+#define TCO_REG_OFFSET 0x60
+#define TCO1_STS 0x64
+#define DMISCI_STS BIT(9)
+#define BOOT_STS BIT(18)
+#define TCO2_STS 0x66
+#define TCO1_CNT 0x68
+#define TCO_LOCK BIT(12)
+#define TCO2_CNT 0x6a
+
+enum {
+ ETR = 0x1048,
+ CF9_LOCK= 1UL << 31,
+ CF9_GLB_RST = 1 << 20,
+};
+
+struct apl_pmc_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_pmc dtplat;
+#endif
+ pci_dev_t bdf;
+};
+
+static int apl_pmc_fill_power_state(struct udevice *dev)
+{
+ struct power_mgr_upriv *upriv = dev_get_uclass_priv(dev);
+
+ upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS);
+ upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS);
+
+ upriv->prsts = readl(upriv->pmc_bar0 + PRSTS);
+ upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1);
+ upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2);
+ upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3);
+
+ return 0;
+}
+
+static int apl_prev_sleep_state(struct udevice *dev, int prev_sleep_state)
+{
+ struct power_mgr_upriv *upriv = dev_get_uclass_priv(dev);
+
+ /* WAK_STS bit will not be set when waking from G3 state */
+ if (!(upriv->pm1_sts & WAK_STS) &&
+ (upriv->gen_pmcon1 & COLD_BOOT_STS))
+ prev_sleep_state = ACPI_S5;
+
+ return prev_sleep_state;
+}
+
+static int apl_disable_tco(struct udevice *dev)
+{
+ struct power_mgr_upriv *upriv = dev_get_uclass_priv(dev);
+
+ pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET);
+
+ return 0;
+}
+
+static int apl_global_reset_set_enable(struct udevice *dev, bool enable)
+{
+ struct power_mgr_upriv *upriv = dev_get_uclass_priv(dev);
+
+ if (enable)
+ setbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
+ else
+ clrbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
+
+ return 0;
+}
+
+int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
+{
+ struct power_mgr_upriv *upriv = dev_get_uclass_priv(dev);
+ struct apl_pmc_platdata *plat = dev_get_platdata(dev);
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ u32 base[6];
+ int size;
+ int ret;
+
+ ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
+ if (ret)
+ return log_msg_ret("Missing/short early-regs", ret);
+ upriv->pmc_bar0 = (void *)base[0];
+ upriv->pmc_bar2 = (void *)base[2];
+ upriv->acpi_base = base[4];
+
+ /* Since PCI is not enabled, we must get the BDF manually */
+ plat->bdf = pci_x86_get_devfn(dev);
+ if (plat->bdf < 0)
+ return log_msg_ret("Cannot get PMC PCI address", plat->bdf);
+
+ /* Get the dwX values for pmc gpe settings */
+
[U-Boot] [PATCH 103/126] x86: Add an option to control the position of U-Boot
The existing work-around for positioning U-Boot in the ROM when it
actually runs from RAM still exists and there is not obvious way to change
this.
Add a proper Kconfig option to handle this case. This also adds a new bool
property to indicate whether CONFIG_SYS_TEXT_BASE exists.
Signed-off-by: Simon Glass
---
Kconfig| 9 ++---
arch/x86/Kconfig | 5 +
arch/x86/dts/u-boot.dtsi | 18 +++---
configs/chromebook_samus_tpl_defconfig | 1 +
4 files changed, 15 insertions(+), 18 deletions(-)
diff --git a/Kconfig b/Kconfig
index 1f0904f7045..f772d4fbe9f 100644
--- a/Kconfig
+++ b/Kconfig
@@ -529,9 +529,14 @@ config SYS_EXTRA_OPTIONS
configuration to Kconfig. Since this option will be removed sometime,
new boards should not use this option.
-config SYS_TEXT_BASE
+config HAS_SYS_TEXT_BASE
+ bool
depends on !NIOS2 && !XTENSA
depends on !EFI_APP
+ default y
+
+config SYS_TEXT_BASE
+ depends on HAS_SYS_TEXT_BASE
default 0x8080 if ARCH_OMAP2PLUS || ARCH_K3
default 0x4a00 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
default 0x2a00 if ARCH_SUNXI && MACH_SUN9I
@@ -540,8 +545,6 @@ config SYS_TEXT_BASE
help
The address in memory that U-Boot will be running from, initially.
-
-
config SYS_CLK_FREQ
depends on ARC || ARCH_SUNXI || MPC83xx
int "CPU clock frequency"
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index fce3c1d92a3..02c116caeb7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -891,4 +891,9 @@ config CACHE_QOS_SIZE_PER_BIT
depends on INTEL_CAR_CQOS
default 0x2 # 128 KB
+config X86_OFFSET_U_BOOT
+ hex "Offset of U-Boot in ROM image"
+ depends on HAS_SYS_TEXT_BASE
+ default SYS_TEXT_BASE
+
endmenu
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 189be2196cb..f33f276b90d 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -54,7 +54,7 @@
u-boot-spl-dtb {
};
u-boot {
- offset = ;
+ offset = ;
};
#elif defined(CONFIG_SPL)
u-boot-spl-with-ucode-ptr {
@@ -64,23 +64,11 @@
type = "u-boot-dtb-with-ucode";
};
u-boot {
- /*
-* TODO(s...@chromium.org):
-* Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
-* for boards with textbase in SDRAM we cannot do this. Just use
-* an assumed-valid value (1MB before the end of flash) here so
-* that we can actually build an image for coreboot, etc.
-* We need a better solution, perhaps a separate Kconfig.
-*/
-#if CONFIG_SYS_TEXT_BASE == 0x111
- offset = <0xfff0>;
-#else
- offset = ;
-#endif
+ offset = ;
};
#else
u-boot-with-ucode-ptr {
- offset = ;
+ offset = ;
};
#endif
#ifdef CONFIG_HAVE_MICROCODE
diff --git a/configs/chromebook_samus_tpl_defconfig
b/configs/chromebook_samus_tpl_defconfig
index 28f23cfe125..c7f125eaa40 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -13,6 +13,7 @@ CONFIG_HAVE_REFCODE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_SPL_TEXT_BASE=0xffe7
+CONFIG_X86_OFFSET_U_BOOT=0xfff0
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SHOW_BOOT_PROGRESS=y
--
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[U-Boot] [PATCH 110/126] x86: apollolake: Add UART driver
Add a driver for the apollolake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/Makefile| 1 +
arch/x86/cpu/apollolake/uart.c | 157
arch/x86/include/asm/arch-apollolake/uart.h | 17 +++
3 files changed, 175 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/uart.c
create mode 100644 arch/x86/include/asm/arch-apollolake/uart.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 5d98a5a6db2..af7c4396619 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -3,3 +3,4 @@
# Copyright (c) 2016 Google, Inc
obj-y += pmc.o
+obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/uart.c b/arch/x86/cpu/apollolake/uart.c
new file mode 100644
index 000..d4ce8312bcc
--- /dev/null
+++ b/arch/x86/cpu/apollolake/uart.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Special driver to handle of-platdata
+ *
+ * Copyright 2019 Google LLC
+ *
+ * Some code from coreboot lpss.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Low-power Subsystem (LPSS) clock register */
+enum {
+ LPSS_CLOCK_CTL_REG = 0x200,
+ LPSS_CNT_CLOCK_EN = 1,
+ LPSS_CNT_CLK_UPDATE = 1U << 31,
+ LPSS_CLOCK_DIV_N_SHIFT = 16,
+ LPSS_CLOCK_DIV_N_MASK = 0x7fff << LPSS_CLOCK_DIV_N_SHIFT,
+ LPSS_CLOCK_DIV_M_SHIFT = 1,
+ LPSS_CLOCK_DIV_M_MASK = 0x7fff << LPSS_CLOCK_DIV_M_SHIFT,
+
+ LPSS_RESET_CTL_REG = 0x204,
+
+ /* These set the UART input clock speed */
+ LPSS_UART_CLK_M_VAL = 0x25a,
+ LPSS_UART_CLK_N_VAL = 0x7fff,
+};
+
+/*
+ * Bit 1:0 controls LPSS controller reset.
+ *
+ * 00 ->LPSS Host Controller is in reset (Reset Asserted)
+ * 01/10 ->Reserved
+ * 11 ->LPSS Host Controller is NOT at reset (Reset Released)
+ */
+#define LPSS_CNT_RST_RELEASE 3
+
+/* Take controller out of reset */
+static void lpss_reset_release(void *regs)
+{
+ writel(LPSS_CNT_RST_RELEASE, regs + LPSS_RESET_CTL_REG);
+}
+
+static void lpss_clk_update(void *regs, u32 clk_m_val, u32 clk_n_val)
+{
+ u32 clk_sel;
+
+ clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT |
+clk_m_val << LPSS_CLOCK_DIV_M_SHIFT;
+ clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN;
+
+ writel(clk_sel, regs + LPSS_CLOCK_CTL_REG);
+}
+
+static void uart_lpss_init(void *regs)
+{
+ /* Take UART out of reset */
+ lpss_reset_release(regs);
+
+ /* Set M and N divisor inputs and enable clock */
+ lpss_clk_update(regs, LPSS_UART_CLK_M_VAL, LPSS_UART_CLK_N_VAL);
+}
+
+void apl_uart_init(pci_dev_t bdf, ulong base)
+{
+ /* Set UART base address */
+ pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32);
+
+ /* Enable memory access and bus master */
+ pci_x86_write_config(bdf, PCI_COMMAND, PCI_COMMAND_MEMORY |
+PCI_COMMAND_MASTER, PCI_SIZE_32);
+
+ uart_lpss_init((void *)base);
+}
+
+/*
+ * This driver uses its own compatible string but almost everything else from
+ * the standard ns16550 driver. This allows us to provide an of-platdata
+ * implementation, since the platdata produced by of-platdata does not match
+ * struct ns16550_platdata.
+ *
+ * When running with of-platdata (generally TPL), the platdata is converted to
+ * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
+ * proper), we use ns16550's ofdata_to_platdata routine.
+ */
+
+static int apl_ns16550_probe(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev_get_platdata(dev);
+
+ if (!CONFIG_IS_ENABLED(PCI))
+ apl_uart_init(plat->bdf, plat->base);
+
+ return ns16550_serial_probe(dev);
+}
+
+static int apl_ns16550_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ns16550_platdata *plat;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_ns16550 *dtplat = dev_get_platdata(dev);
+
+ /*
+* Convert our platdata to the ns16550's platdata, so we can just use
+* that driver
+*/
+ plat = malloc(sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+ plat->base = dtplat->early_regs[0];
+ plat->reg_width = 1;
+ plat->reg_shift = dtplat->reg_shift;
+ plat->reg_offset = 0;
+ plat->clock = dtplat->clock_frequency;
+ plat->fcr = UART_FCR_DEFVAL;
+ plat->bdf = pci_x86_ofplat_get_devfn(dtplat->reg[0]);
+ dev->platdata = plat;
+#else
+ int ret;
+
+ ret = ns16550_serial_ofdata_to_platdata(dev);
+ if (ret)
+ return ret;
+ if (!CONFIG_IS_ENABLED(OF_TRANSLATE)) {
+ /*
+* Without address translation we cannot get correct PCI
+* address, so just read the BAR man
[U-Boot] [PATCH 097/126] x86: Add support for newer CAR schemes
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. Signed-off-by: Simon Glass --- arch/x86/Kconfig| 16 + arch/x86/cpu/intel_common/Kconfig | 18 + arch/x86/cpu/intel_common/Makefile | 8 + arch/x86/cpu/intel_common/car2.S| 490 arch/x86/cpu/intel_common/car2_uninit.S | 87 + 5 files changed, 619 insertions(+) create mode 100644 arch/x86/cpu/intel_common/Kconfig create mode 100644 arch/x86/cpu/intel_common/car2.S create mode 100644 arch/x86/cpu/intel_common/car2_uninit.S diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 556e26080de..e34c71ec4cb 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -876,4 +876,20 @@ config HIGH_TABLE_SIZE Increse it if the default size does not fit the board's needs. This is most likely due to a large ACPI DSDT table is used. +config INTEL_CAR_CQOS + bool "Support Intel Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up a portion of L2 cache for + CAR and use the remainder for actual caching. + +# +# Each bit in QOS mask controls this many bytes. This is calculated as: +# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS +# +config CACHE_QOS_SIZE_PER_BIT + hex + depends on INTEL_CAR_CQOS + default 0x2 # 128 KB + endmenu diff --git a/arch/x86/cpu/intel_common/Kconfig b/arch/x86/cpu/intel_common/Kconfig new file mode 100644 index 000..a4f46b1108b --- /dev/null +++ b/arch/x86/cpu/intel_common/Kconfig @@ -0,0 +1,18 @@ +config INTEL_PMC + bool "Intel Power-management Controller" + select POWER_MGR + help + Enable support for the common Intel power-management controller which + provides features including checking whether the system started from + resume, powering off the system and enabling/disabling the reset + mechanism. + +config SPL_INTEL_PMC + bool "Intel Power-management Controller in SPL" + default y if SPL && INTEL_PMC + select SPL_POWER_MGR + help + Enable support for the common Intel power-management controller which + provides features including checking whether the system started from + resume, powering off the system and enabling/disabling the reset + mechanism. diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 2de567dd9fe..f620747a7d2 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -8,6 +8,14 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o endif + +ifdef CONFIG_FSP_VERSION2 +obj-$(CONFIG_TPL_BUILD) += car2.o +ifndef CONFIG_SPL_BUILD +obj-y += car2_uninit.o +endif +endif + obj-y += cpu.o obj-$(CONFIG_SPI_FLASH_INTEL_FAST) += fast_spi.o obj-y += lpc.o diff --git a/arch/x86/cpu/intel_common/car2.S b/arch/x86/cpu/intel_common/car2.S new file mode 100644 index 000..ac07fe5ea6a --- /dev/null +++ b/arch/x86/cpu/intel_common/car2.S @@ -0,0 +1,490 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +#define KiB 1024 + +.global car_init +car_init: + post_code(0x20) + + /* +* Use the MTRR default type MSR as a proxy for detecting INIT#. +* Reset the system if any known bits are set in that MSR. That is +* an indication of the CPU not being properly reset. +*/ +check_for_clean_reset: + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax + cmp $0, %eax + jz no_reset + /* perform warm reset */ + movw$0xcf9, %dx + movb$0x06, %al + outb%al, %dx + +no_reset: + post_code(0x21) + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + post_code(0x22) + + /* Figure put how many MTRRs w
[U-Boot] [PATCH 094/126] x86: Add FSP2 base support
Add support for some important configuration options and FSP memory init.
The memory init uses swizzle tables from the device tree.
Note that support for the FSP_S binary is not yet included.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig | 41 ++-
arch/x86/include/asm/fsp2/fsp_api.h | 38 +++
arch/x86/include/asm/fsp2/fsp_internal.h | 16 ++
arch/x86/lib/fsp2/Makefile | 7 +
arch/x86/lib/fsp2/fsp_dram.c | 73 +
arch/x86/lib/fsp2/fsp_meminit.c | 344 +++
arch/x86/lib/fsp2/fsp_support.c | 109 +++
7 files changed, 627 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/include/asm/fsp2/fsp_api.h
create mode 100644 arch/x86/include/asm/fsp2/fsp_internal.h
create mode 100644 arch/x86/lib/fsp2/Makefile
create mode 100644 arch/x86/lib/fsp2/fsp_dram.c
create mode 100644 arch/x86/lib/fsp2/fsp_meminit.c
create mode 100644 arch/x86/lib/fsp2/fsp_support.c
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0de3f6ed7da..49b5f0f4ebd 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -331,7 +331,7 @@ config X86_RAMTEST
config FLASH_DESCRIPTOR_FILE
string "Flash descriptor binary filename"
- depends on HAVE_INTEL_ME
+ depends on HAVE_INTEL_ME || FSP_VERSION2
default "descriptor.bin"
help
The filename of the file to use as flash descriptor in the
@@ -416,6 +416,45 @@ config FSP_ADDR
The default base address of 0xfffc indicates that the binary must
be located at offset 0xc from the beginning of a 1MB flash device.
+if FSP_VERSION2
+
+config FSP_FILE_T
+ string "Firmware-Support-Package binary filename (Temp RAM)"
+ default "fsp_t.bin"
+ help
+ The filename of the file to use for the temporary-RAM init phase from
+ the Firmware-Support-Package binary. Put this in the board directory.
+ It is used to set up an initial area of RAM which can be used for the
+ stack and other purposes, while bringing up the main system DRAM.
+
+config FSP_ADDR_T
+ hex "Firmware-Support-Package binary location (Temp RAM)"
+ default 0x8000
+ help
+ FSP is not Position-Independent Code (PIC) and FSP components have to
+ be rebased if placed at a location which is different from the
+ perferred base address specified during the FSP build. Use Intel's
+ Binary Configuration Tool (BCT) to do the rebase.
+
+config FSP_FILE_M
+ string "Firmware-Support-Package binary filename (Memory Init)"
+ default "fsp_m.bin"
+ help
+ The filename of the file to use for the RAM init phase from the
+ Firmware Support Package binary. Put this in the board directory.
+ It is used to set up an initial area of RAM which can be used for the
+ stack and other purposes, while bringing up the main system DRAM.
+
+config IFWI_INPUT_FILE
+ string "Filename containing FIT (Firmware Interface Table) with IFWI"
+ default "fitimage.bin"
+ help
+ The IFWI is obtained by running a tool on this file to extract the
+ IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
+ microcode and other internal items.
+
+endif
+
config FSP_TEMP_RAM_ADDR
hex
depends on FSP_VERSION1
diff --git a/arch/x86/include/asm/fsp2/fsp_api.h
b/arch/x86/include/asm/fsp2/fsp_api.h
new file mode 100644
index 000..3e41ecbede8
--- /dev/null
+++ b/arch/x86/include/asm/fsp2/fsp_api.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2015-2016 Intel Corp.
+ * (Written by Andrey Petrov for Intel Corp.)
+ * (Written by Alexandru Gagniuc for Intel
Corp.)
+ * Mostly taken from coreboot fsp2_0/memory_init.c
+ */
+
+#ifndef __ASM_FSP_API_H
+#define __ASM_FSP_API_H
+
+struct fspm_upd;
+struct hob_header;
+
+enum fsp_boot_mode {
+ FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00,
+ FSP_BOOT_WITH_MINIMAL_CONFIGURATION = 0x01,
+ FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES = 0x02,
+ FSP_BOOT_ON_S4_RESUME = 0x05,
+ FSP_BOOT_ON_S3_RESUME = 0x11,
+ FSP_BOOT_ON_FLASH_UPDATE = 0x12,
+ FSP_BOOT_IN_RECOVERY_MODE = 0x20
+};
+
+/**
+ * fsp_memory_init() - Init the SDRAM
+ *
+ * @s3wake: true if we are booting from resume, so cannot reinit the mememory
+ * from scatch since we will lose its contents
+ * @use_spi_flash: true to use the fast SPI driver to read FSP, otherwise use
+ * mapped SPI
+ */
+int fsp_memory_init(bool s3wake, bool use_spi_flash);
+
+typedef asmlinkage int (*fsp_memory_init_func)(struct fspm_upd *params,
+ struct hob_header **hobp);
+
+#endif
diff --git a/arch/x86/include/asm/fsp2/fsp_internal.h
b/arch/x86/include/asm/fsp2/fsp_internal.h
new file mode 100644
index 000..c69c90a931d
--- /dev/null
+++ b/arch/x86/include/asm/fsp2/fsp_internal.h
@@ -0,0 +1,
[U-Boot] [PATCH 089/126] x86: Set up the MTRR for SDRAM
Set up MTRRs for the FST SDRAM regions to improve performance. Signed-off-by: Simon Glass --- arch/x86/lib/fsp/fsp_dram.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 9161af65b98..4a87516f422 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -8,6 +8,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -70,6 +71,8 @@ int dram_init_banksize(void) gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].size = low_end; + mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end); + return 0; } -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 086/126] x86: Add mrccache support for a 'variable' cache
Add support for a second cache type, for apollolake.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/mrccache.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h
index b81e2b2fb6a..0917cf24704 100644
--- a/arch/x86/include/asm/mrccache.h
+++ b/arch/x86/include/asm/mrccache.h
@@ -30,6 +30,7 @@ struct mrc_region {
/* Types of MRC data */
enum mrc_type_t {
MRC_TYPE_NORMAL,
+ MRC_TYPE_VAR,
MRC_TYPE_COUNT,
};
--
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[U-Boot] [PATCH 096/126] x86: Add an option to include a FIT
Many Intel SoCs require a FIT in order to boot properly. Add an option to
include this and enable it by default.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig | 9 +
arch/x86/dts/u-boot.dtsi | 6 ++
2 files changed, 15 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 49b5f0f4ebd..556e26080de 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -222,6 +222,15 @@ config SYS_X86_START16
depends on X86_RESET_VECTOR
default 0xf800
+config X86_HAS_FIT
+ bool
+ default y
+ help
+ Enable inclusion of an Intel Firmware Interface Table (FIT) into the
+ image. This table is supposed to point to microcode and the like. So
+ far it is just a fixed table with the minimum set of headers, so that
+ it is actually present.
+
config X86_LOAD_FROM_32_BIT
bool "Boot from a 32-bit program"
help
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 0e87b88e105..049f47c9ffd 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -82,6 +82,12 @@
u-boot-ucode {
align = <16>;
};
+#ifdef CONFIG_X86_HAS_FIT
+ intel-fit {
+ };
+ intel-fit-ptr {
+ };
+#endif
#ifdef CONFIG_HAVE_MRC
intel-mrc {
offset = ;
--
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[U-Boot] [PATCH 112/126] x86: apollolake: Add defintions for the Intel Fast SPI interface
Provide definitions for using this device on apollolake. They should
perhaps be moved into a more generic place.
Signed-off-by: Simon Glass
---
.../include/asm/arch-apollolake/fast_spi.h| 176 ++
1 file changed, 176 insertions(+)
create mode 100644 arch/x86/include/asm/arch-apollolake/fast_spi.h
diff --git a/arch/x86/include/asm/arch-apollolake/fast_spi.h
b/arch/x86/include/asm/arch-apollolake/fast_spi.h
new file mode 100644
index 000..ebae1f87ebf
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/fast_spi.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H
+#define SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H
+
+/* PCI configuration registers */
+
+#define SPIDVID_OFFSET 0x0
+#define SPIBAR_BIOS_CONTROL0xdc
+
+/* Bit definitions for BIOS_CONTROL */
+#define SPIBAR_BIOS_CONTROL_WPDBIT(0)
+#define SPIBAR_BIOS_CONTROL_LOCK_ENABLEBIT(1)
+#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE BIT(2)
+#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLEBIT(3)
+#define SPIBAR_BIOS_CONTROL_EISS BIT(5)
+#define SPIBAR_BIOS_CONTROL_BILD BIT(7)
+
+/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
+struct fast_spi_regs {
+ u32 bfp;
+ u32 hsfsts_ctl;
+ u32 faddr;
+ u32 dlock;
+
+ u32 fdata[0x10];
+
+ u8 spare[0x84 - 0x50];
+ u32 fpr[8];
+ u16 preop;
+ u16 optype;
+ u32 opmenu_lower;
+ u32 opmenu_upper;
+
+ u32 space2;
+ u32 fdoc;
+ u32 fdod;
+ u32 spare3[4];
+ u32 ptinx;
+ u32 ptdata;
+};
+check_member(fast_spi_regs, ptdata, 0xd0);
+
+/* Bit definitions for BFPREG (0x00) register */
+#define SPIBAR_BFPREG_PRB_MASK 0x7fff
+#define SPIBAR_BFPREG_PRL_SHIFT16
+#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
+#define SPIBAR_BFPREG_SBRS BIT(31)
+
+/* Bit definitions for HSFSTS_CTL (0x04) register */
+#define SPIBAR_HSFSTS_FDBC_MASK(0x3f << 24)
+#define SPIBAR_HSFSTS_FDBC(n) (((n) << 24) & SPIBAR_HSFSTS_FDBC_MASK)
+#define SPIBAR_HSFSTS_WET BIT(21)
+#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17)
+#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) \
+ & SPIBAR_HSFSTS_FCYCLE_MASK)
+/* Supported flash cycle types */
+#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0)
+#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2)
+#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3)
+#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4)
+#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8)
+
+#define SPIBAR_HSFSTS_FGO BIT(16)
+#define SPIBAR_HSFSTS_FLOCKDN BIT(15)
+#define SPIBAR_HSFSTS_FDV BIT(14)
+#define SPIBAR_HSFSTS_FDOPSS BIT(13)
+#define SPIBAR_HSFSTS_WRSDIS BIT(11)
+#define SPIBAR_HSFSTS_SAF_CE BIT(8)
+#define SPIBAR_HSFSTS_SAF_ACTIVE BIT(7)
+#define SPIBAR_HSFSTS_SAF_LE BIT(6)
+#define SPIBAR_HSFSTS_SCIP BIT(5)
+#define SPIBAR_HSFSTS_SAF_DLE BIT(4)
+#define SPIBAR_HSFSTS_SAF_ERRORBIT(3)
+#define SPIBAR_HSFSTS_AEL BIT(2)
+#define SPIBAR_HSFSTS_FCERRBIT(1)
+#define SPIBAR_HSFSTS_FDONEBIT(0)
+#define SPIBAR_HSFSTS_W1C_BITS 0xff
+
+#define WPSR_MASK_SRP0_BIT 0x80
+
+/* Bit definitions for FADDR (0x08) register */
+#define SPIBAR_FADDR_MASK 0x7FF
+
+/* Bit definitions for DLOCK (0x0C) register */
+#define SPIBAR_DLOCK_PR0LOCKDN BIT(8)
+#define SPIBAR_DLOCK_PR1LOCKDN BIT(9)
+#define SPIBAR_DLOCK_PR2LOCKDN BIT(10)
+#define SPIBAR_DLOCK_PR3LOCKDN BIT(11)
+#define SPIBAR_DLOCK_PR4LOCKDN BIT(12)
+
+/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
+#define SPIBAR_FDATA_FIFO_SIZE 0x40
+
+/* Bit definitions for FDOC (0xB4) register */
+#define SPIBAR_FDOC_COMPONENT BIT(12)
+#define SPIBAR_FDOC_FDSI_1 BIT(2)
+
+/* Flash Descriptor Component Section - Component 0 Density Bit Settings */
+#define FLCOMP_C0DEN_MASK 0xF
+#define FLCOMP_C0DEN_8MB 4
+#define FLCOMP_C0DEN_16MB 5
+#define FLCOMP_C0DEN_32MB
[U-Boot] [PATCH 078/126] x86: Define the SPL image start
Define this symbol so that we can use binman symbols correctly.
Signed-off-by: Simon Glass
---
arch/x86/cpu/u-boot-spl.lds | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds
index c1e9bfbf66f..e6c22895b35 100644
--- a/arch/x86/cpu/u-boot-spl.lds
+++ b/arch/x86/cpu/u-boot-spl.lds
@@ -17,7 +17,10 @@ SECTIONS
. = IMAGE_TEXT_BASE;/* Location of bootcode in flash */
__text_start = .;
- .text : { *(.text*); }
+ .text : {
+ __image_copy_start = .;
+ *(.text*);
+ }
. = ALIGN(4);
--
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[U-Boot] [PATCH 098/126] x86: Drop RESET_BASE
Since x86 users binman now, we don't need this compile-time define. Signed-off-by: Simon Glass --- arch/x86/cpu/config.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 22416f39b6e..e5a393a1c81 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -10,7 +10,6 @@ LDPPFLAGS += -DRESET_SEG_START=$(CONFIG_RESET_SEG_START) LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE) LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC) LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) -LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)" ifdef CONFIG_X86_64 ifndef CONFIG_SPL_BUILD -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 093/126] x86: Allow interrupt to happen once
At present the interrupt table is included in all phases of U-Boot. Allow it to be omitted, e.g. in TPL, to reduce size. Signed-off-by: Simon Glass --- arch/x86/cpu/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 6296b55ff8a..b6a010ea320 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -53,7 +53,7 @@ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-$(CONFIG_APIC) += lapic.o ioapic.o -obj-y += irq.o +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += mp_init.o endif -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 105/126] x86: Reduce resetvec size
At present this produces a 16-byte file. It is intended to start 16 bytes before the end of ROM and pads with zeroes to readh the end. But binman sometimes wants to add an image-header at the very end of ROM. Furthermore binman automatically pads the data if it is finishes early. Drop the padding in resetvec and let binman handle it. Signed-off-by: Simon Glass --- arch/x86/cpu/resetvec.S | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/x86/cpu/resetvec.S b/arch/x86/cpu/resetvec.S index a52225d5ee9..cf972738b31 100644 --- a/arch/x86/cpu/resetvec.S +++ b/arch/x86/cpu/resetvec.S @@ -16,6 +16,3 @@ reset_vector: cli cld jmp start16 - - .org 0xf - nop -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 080/126] x86: Add a function to find the size of an mrccache record
Move the code to determine the size of a cache record into a function so
we can use it elsewhere in this file.
Signed-off-by: Simon Glass
---
arch/x86/lib/mrccache.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index be107627b80..33bb52039bd 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -17,19 +17,20 @@
DECLARE_GLOBAL_DATA_PTR;
+static uint mrc_block_size(uint data_size)
+{
+ uint mrc_size = sizeof(struct mrc_data_container) + data_size;
+
+ return ALIGN(mrc_size, MRC_DATA_ALIGN);
+}
+
static struct mrc_data_container *next_mrc_block(
struct mrc_data_container *cache)
{
/* MRC data blocks are aligned within the region */
- u32 mrc_size = sizeof(*cache) + cache->data_size;
u8 *region_ptr = (u8 *)cache;
- if (mrc_size & (MRC_DATA_ALIGN - 1UL)) {
- mrc_size &= ~(MRC_DATA_ALIGN - 1UL);
- mrc_size += MRC_DATA_ALIGN;
- }
-
- region_ptr += mrc_size;
+ region_ptr += mrc_block_size(cache->data_size);
return (struct mrc_data_container *)region_ptr;
}
--
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[U-Boot] [PATCH 085/126] x86: Update mrccache to support multiple caches
With apollolake we need to support a normal cache, which almost never
changes and a much smaller 'variable' cache which changes every time.
Update the code to add a cache type, use an array for the caches and use a
for loop to iterate over the caches.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/sdram.c | 8 ++-
arch/x86/cpu/ivybridge/sdram.c | 8 ++-
arch/x86/cpu/quark/dram.c | 8 ++-
arch/x86/include/asm/global_data.h | 21 +--
arch/x86/include/asm/mrccache.h| 11 +++-
arch/x86/lib/fsp/fsp_common.c | 2 +-
arch/x86/lib/fsp1/fsp_dram.c | 8 ++-
arch/x86/lib/mrccache.c| 93 --
8 files changed, 109 insertions(+), 50 deletions(-)
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index b31d78c092a..107c04691b0 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -82,7 +82,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data)
struct mrc_region entry;
int ret;
- ret = mrccache_get_region(NULL, &entry);
+ ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
if (ret)
return ret;
mrc_cache = mrccache_find_current(&entry);
@@ -168,12 +168,14 @@ int dram_init(void)
pei_data->data_to_save);
/* S3 resume: don't save scrambler seed or MRC data */
if (pei_data->boot_mode != SLEEP_STATE_S3) {
+ struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
+
/*
* This will be copied to SDRAM in reserve_arch(), then written
* to SPI flash in mrccache_save()
*/
- gd->arch.mrc_output = (char *)pei_data->data_to_save;
- gd->arch.mrc_output_len = pei_data->data_to_save_size;
+ mrc->buf = (char *)pei_data->data_to_save;
+ mrc->len = pei_data->data_to_save_size;
}
gd->arch.pei_meminfo = pei_data->meminfo;
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 8a58d0383d5..8b0340e 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -115,7 +115,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data)
ret = read_seed_from_cmos(pei_data);
if (ret)
return ret;
- ret = mrccache_get_region(NULL, &entry);
+ ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
if (ret)
return ret;
mrc_cache = mrccache_find_current(&entry);
@@ -537,12 +537,14 @@ int dram_init(void)
/* S3 resume: don't save scrambler seed or MRC data */
if (pei_data->boot_mode != PEI_BOOT_RESUME) {
+ struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
+
/*
* This will be copied to SDRAM in reserve_arch(), then written
* to SPI flash in mrccache_save()
*/
- gd->arch.mrc_output = (char *)pei_data->mrc_output;
- gd->arch.mrc_output_len = pei_data->mrc_output_len;
+ mrc->buf = (char *)pei_data->mrc_output;
+ mrc->len = pei_data->mrc_output_len;
ret = write_seeds_to_cmos(pei_data);
if (ret)
debug("Failed to write seeds to CMOS: %d\n", ret);
diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c
index 51f9659ab15..3994355112b 100644
--- a/arch/x86/cpu/quark/dram.c
+++ b/arch/x86/cpu/quark/dram.c
@@ -22,7 +22,7 @@ static __maybe_unused int prepare_mrc_cache(struct mrc_params
*mrc_params)
struct mrc_region entry;
int ret;
- ret = mrccache_get_region(NULL, &entry);
+ ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
if (ret)
return ret;
@@ -152,9 +152,11 @@ int dram_init(void)
#ifdef CONFIG_ENABLE_MRC_CACHE
cache = malloc(sizeof(struct mrc_timings));
if (cache) {
+ struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
+
memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
- gd->arch.mrc_output = cache;
- gd->arch.mrc_output_len = sizeof(struct mrc_timings);
+ mrc->buf = cache;
+ mrc->len = sizeof(struct mrc_timings);
}
#endif
diff --git a/arch/x86/include/asm/global_data.h
b/arch/x86/include/asm/global_data.h
index c5faac5c901..2475b3427e1 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -67,6 +67,21 @@ struct mtrr_request {
uint64_t size;
};
+/**
+ * struct mrc_output - holds the MRC data
+ *
+ * @buf: MRC training data to save for the next boot. This is set to point to
+ * the raw data after SDRAM init is complete. Then mrccache_setup()
+ * turns it into a proper cache record with a checksum
+ * @len: Length of @buf
+ * @cache: Resulting cache record
+ */
+st
[U-Boot] [PATCH 095/126] x86: Don't include the BIOS emulator in TPL
We don't generally have enough space to run this, so don't build it into TPL. This helps reduce the size of TPL. Signed-off-by: Simon Glass --- arch/x86/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index ca0ca1066b0..5cd45874803 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -4,9 +4,11 @@ # Wolfgang Denk, DENX Software Engineering, w...@denx.de. ifndef CONFIG_X86_64 +ifndef CONFIG_TPL_BUILD obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o +endif obj-y += string.o endif ifndef CONFIG_SPL_BUILD -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 081/126] x86: Correct mrccache find_next_mrc_cache() calculation
This should take account of the end of the new cache record since a record
cannot extend beyond the end of the flash region. This problem was not
seen before due to the alignment of the relatively small amount of MRC
data.
But with apollolake the MRC data is about 45KB, even if most of it is
zeroes.
Fix this bug and update the parameter name to be less confusing.
Signed-off-by: Simon Glass
---
arch/x86/lib/mrccache.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 33bb52039bd..e286bdf1b30 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -86,15 +86,16 @@ struct mrc_data_container *mrccache_find_current(struct
mrc_region *entry)
* @return next cache entry if found, NULL if we got to the end
*/
static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry,
- struct mrc_data_container *cache)
+ struct mrc_data_container *prev)
{
+ struct mrc_data_container *cache;
ulong base_addr, end_addr;
base_addr = entry->base + entry->offset;
end_addr = base_addr + entry->length;
- cache = next_mrc_block(cache);
- if ((ulong)cache >= end_addr) {
+ cache = next_mrc_block(prev);
+ if ((ulong)cache + mrc_block_size(prev->data_size) > end_addr) {
/* Crossed the boundary */
cache = NULL;
debug("%s: no available entries found\n", __func__);
--
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[U-Boot] [PATCH 106/126] x86: Add an fdtmap and image-header
Add these entries to the ROM so that we can list the contents of an image
with 'binman ls'. The image-header is not essential but does speed up
access.
Signed-off-by: Simon Glass
---
arch/x86/dts/u-boot.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 8fc5146f26c..f2fb4c2abaa 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -125,6 +125,8 @@
filename = CONFIG_FSP_FILE_M;
};
#endif
+ fdtmap {
+ };
#ifdef CONFIG_HAVE_CMC
intel-cmc {
filename = CONFIG_CMC_FILE;
@@ -170,5 +172,8 @@
offset = ;
};
#endif
+ image-header {
+ location = "end";
+ };
};
#endif
--
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[U-Boot] [PATCH 083/126] x86: Add a new global_data member for the cache record
At present we reuse the mrc_output char * to also point to the cache
record after it has been set up. This is confusing and doesn't save much
data space.
Add a new mrc_cache member instead.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/global_data.h | 2 ++
arch/x86/lib/mrccache.c| 11 +--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/global_data.h
b/arch/x86/include/asm/global_data.h
index 17a4d344913..c5faac5c901 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -10,6 +10,7 @@
#ifndef __ASSEMBLY__
#include
+#include
enum pei_boot_mode_t {
PEI_BOOT_NONE = 0,
@@ -92,6 +93,7 @@ struct arch_global_data {
/* MRC training data to save for the next boot */
char *mrc_output;
unsigned int mrc_output_len;
+ struct mrc_data_container *mrc_cache;
ulong table;/* Table pointer from previous loader */
int turbo_state;/* Current turbo state */
struct irq_routing_table *pirq_routing_table;
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 296dd5e54f7..9a3e5fffa45 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -179,8 +179,7 @@ static void mrccache_setup(void *data)
cache->reserved = 0;
memcpy(cache->data, gd->arch.mrc_output, cache->data_size);
- /* gd->arch.mrc_output now points to the container */
- gd->arch.mrc_output = (char *)cache;
+ gd->arch.mrc_cache = cache;
}
int mrccache_reserve(void)
@@ -242,7 +241,7 @@ int mrccache_get_region(struct udevice **devp, struct
mrc_region *entry)
int mrccache_save(void)
{
- struct mrc_data_container *data;
+ struct mrc_data_container *cache;
struct mrc_region entry;
struct udevice *sf;
int ret;
@@ -258,10 +257,10 @@ int mrccache_save(void)
ret = device_probe(sf);
if (ret)
goto err_entry;
- data = (struct mrc_data_container *)gd->arch.mrc_output;
- ret = mrccache_update(sf, &entry, data);
+ cache = gd->arch.mrc_cache;
+ ret = mrccache_update(sf, &entry, cache);
if (!ret) {
- debug("Saved MRC data with checksum %04x\n", data->checksum);
+ debug("Saved MRC data with checksum %04x\n", cache->checksum);
} else if (ret == -EEXIST) {
debug("MRC data is the same as last time, skipping save\n");
ret = 0;
--
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[U-Boot] [PATCH 091/126] x86: Don't imply TPL_OF_LIBFDT
This option pulls in libfdt and therefore precludes getting the full code-size savings of op-platdata. Drop it since it will be enabled anyway if needed. Signed-off-by: Simon Glass --- arch/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index 0374139fa89..b6f244d7c1b 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -203,7 +203,6 @@ config X86 imply SPL_SYSCON # TPL imply TPL_DM - imply TPL_OF_LIBFDT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_GPIO_SUPPORT imply TPL_LIBCOMMON_SUPPORT -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 087/126] x86: Move fsp_prepare_mrc_cache() to fsp1 directory
This function needs to be different for FSP2, so move the existing
function into the fsp1 directory. Since it is only called from one file,
drop it from the header file.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/fsp/fsp_support.h | 7 ---
arch/x86/lib/fsp/fsp_common.c | 20
arch/x86/lib/fsp1/fsp_common.c | 20
3 files changed, 20 insertions(+), 27 deletions(-)
diff --git a/arch/x86/include/asm/fsp/fsp_support.h
b/arch/x86/include/asm/fsp/fsp_support.h
index 2424bc1f5f9..d3eee6c0c11 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -146,13 +146,6 @@ int fsp_init_phase_pci(void);
*/
int fsp_scan_for_ram_size(void);
-/**
- * fsp_prepare_mrc_cache() - Find the DRAM training data from the MRC cache
- *
- * @return pointer to data, or NULL if no cache or no data found in the cache
- */
-void *fsp_prepare_mrc_cache(void);
-
/**
* fsp_notify() - FSP notification wrapper function
*
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index c1c30ce0eb6..6b7a614e929 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -57,26 +57,6 @@ void board_final_cleanup(void)
debug("OK\n");
}
-void *fsp_prepare_mrc_cache(void)
-{
- struct mrc_data_container *cache;
- struct mrc_region entry;
- int ret;
-
- ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
- if (ret)
- return NULL;
-
- cache = mrccache_find_current(&entry);
- if (!cache)
- return NULL;
-
- debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
- cache->data, cache->data_size, cache->checksum);
-
- return cache->data;
-}
-
#ifdef CONFIG_HAVE_ACPI_RESUME
int fsp_save_s3_stack(void)
{
diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c
index e8066d8de39..ec9c218778d 100644
--- a/arch/x86/lib/fsp1/fsp_common.c
+++ b/arch/x86/lib/fsp1/fsp_common.c
@@ -18,6 +18,26 @@
DECLARE_GLOBAL_DATA_PTR;
+static void *fsp_prepare_mrc_cache(void)
+{
+ struct mrc_data_container *cache;
+ struct mrc_region entry;
+ int ret;
+
+ ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
+ if (ret)
+ return NULL;
+
+ cache = mrccache_find_current(&entry);
+ if (!cache)
+ return NULL;
+
+ debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
+ cache->data, cache->data_size, cache->checksum);
+
+ return cache->data;
+}
+
int arch_fsp_init(void)
{
void *nvs;
--
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[U-Boot] [PATCH 107/126] x86: Don't repeat microcode in U-Boot if not needed
At present if SPL sets up the microcode then it is still included in
U-Boot as well. This is wasteful as microcode is large. Adjust the logic
in the image to prevent this.
Signed-off-by: Simon Glass
---
arch/x86/dts/u-boot.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index f2fb4c2abaa..d9a4ca1184e 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -67,9 +67,16 @@
offset = ;
};
#else
+# ifdef CONFIG_SPL
+ u-boot {
+ offset = ;
+ };
+# else
+ /* If there is no SPL then we need to put microcode in U-Boot */
u-boot-with-ucode-ptr {
offset = ;
};
+# endif
#endif
#ifdef CONFIG_HAVE_MICROCODE
u-boot-dtb-with-ucode {
--
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[U-Boot] [PATCH 084/126] x86: Tidy up error handling in mrccache_save()
This function is a bit confusing at present due to the error handling.
Update it to remove the goto, returning errors as they happen.
While we are here, use hex for the data size since this is the norm in
U-Boot.
Signed-off-by: Simon Glass
---
arch/x86/lib/mrccache.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 9a3e5fffa45..0208696c834 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -248,28 +248,23 @@ int mrccache_save(void)
if (!gd->arch.mrc_output_len)
return 0;
- debug("Saving %d bytes of MRC output data to SPI flash\n",
+ debug("Saving %#x bytes of MRC output data to SPI flash\n",
gd->arch.mrc_output_len);
ret = mrccache_get_region(&sf, &entry);
if (ret)
- goto err_entry;
+ return log_msg_ret("Cannot get region", ret);
ret = device_probe(sf);
if (ret)
- goto err_entry;
+ return log_msg_ret("Cannot probe device", ret);
cache = gd->arch.mrc_cache;
ret = mrccache_update(sf, &entry, cache);
- if (!ret) {
+ if (!ret)
debug("Saved MRC data with checksum %04x\n", cache->checksum);
- } else if (ret == -EEXIST) {
+ else if (ret == -EEXIST)
debug("MRC data is the same as last time, skipping save\n");
- ret = 0;
- }
-err_entry:
- if (ret)
- debug("%s: Failed: %d\n", __func__, ret);
- return ret;
+ return 0;
}
int mrccache_spl_save(void)
--
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[U-Boot] [PATCH 077/126] sandbox: Add a test for ITSS
Add a simple sandbox test for this uclass.
Signed-off-by: Simon Glass
---
arch/sandbox/dts/test.dts | 4
configs/sandbox_defconfig | 3 ++-
drivers/misc/Makefile | 1 +
drivers/misc/itss_sandbox.c | 44 +
test/dm/Makefile| 1 +
test/dm/itss.c | 29
6 files changed, 81 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/itss_sandbox.c
create mode 100644 test/dm/itss.c
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index cd4409b7aea..ea435f16247 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -345,6 +345,10 @@
vss-microvolts = <0>;
};
+ itss {
+ compatible = "sandbox,itss";
+ };
+
lcd {
u-boot,dm-pre-reloc;
compatible = "sandbox,lcd-sdl";
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 6f4d8449290..a1104b03433 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -129,6 +129,8 @@ CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_LPC=y
CONFIG_CROS_EC_SANDBOX=y
CONFIG_CROS_EC_SPI=y
+CONFIG_ITSS=y
+CONFIG_P2SB=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
CONFIG_I2C_EEPROM=y
@@ -149,7 +151,6 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
-CONFIG_P2SB=y
CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f715d6d6df5..83fbd193657 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
obj-$(CONFIG_ITSS) += itss-uclass.o
+obj-$(CONFIG_SANDBOX) += itss_sandbox.o
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
diff --git a/drivers/misc/itss_sandbox.c b/drivers/misc/itss_sandbox.c
new file mode 100644
index 000..993106ffdc2
--- /dev/null
+++ b/drivers/misc/itss_sandbox.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sandbox driver for itss
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+
+static int sandbox_set_irq_polarity(struct udevice *dev, uint irq,
+ bool active_low)
+{
+ if (irq > 10)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int sandbox_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
+{
+ if (pmc_gpe_num > 10)
+ return -ENOENT;
+
+ return pmc_gpe_num + 1;
+}
+
+static const struct itss_ops sandbox_itss_ops = {
+ .route_pmc_gpio_gpe = sandbox_route_pmc_gpio_gpe,
+ .set_irq_polarity = sandbox_set_irq_polarity,
+};
+
+static const struct udevice_id sandbox_itss_ids[] = {
+ { .compatible = "sandbox,itss"},
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_itss_drv) = {
+ .name = "sandbox_itss",
+ .id = UCLASS_ITSS,
+ .of_match = sandbox_itss_ids,
+ .ops= &sandbox_itss_ops,
+};
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 52a2392a8e9..3868b5d4aa9 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o
obj-$(CONFIG_DM_I2C) += i2c.o
obj-$(CONFIG_SOUND) += i2s.o
+obj-$(CONFIG_ITSS) += itss.o
obj-$(CONFIG_LED) += led.o
obj-$(CONFIG_DM_MAILBOX) += mailbox.o
obj-$(CONFIG_DM_MMC) += mmc.o
diff --git a/test/dm/itss.c b/test/dm/itss.c
new file mode 100644
index 000..1ca1aeba9f4
--- /dev/null
+++ b/test/dm/itss.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for ITSS uclass
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/* Base test of the ITSS uclass */
+static int dm_test_itss_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_first_device_err(UCLASS_ITSS, &dev));
+
+ ut_asserteq(5, itss_route_pmc_gpio_gpe(dev, 4));
+ ut_asserteq(-ENOENT, itss_route_pmc_gpio_gpe(dev, 14));
+
+ ut_assertok(itss_set_irq_polarity(dev, 4, true));
+ ut_asserteq(-EINVAL, itss_set_irq_polarity(dev, 14, true));
+
+ return 0;
+}
+DM_TEST(dm_test_itss_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
--
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[U-Boot] [PATCH 099/126] x86: Drop RESET_SEG_SIZE
This is not used anywhere now, so drop it. Signed-off-by: Simon Glass --- arch/x86/Kconfig | 5 - arch/x86/cpu/config.mk | 1 - 2 files changed, 6 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e34c71ec4cb..e797612e30e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -207,11 +207,6 @@ config RESET_SEG_START depends on X86_RESET_VECTOR default 0x -config RESET_SEG_SIZE - hex - depends on X86_RESET_VECTOR - default 0x1 - config RESET_VEC_LOC hex depends on X86_RESET_VECTOR diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index e5a393a1c81..8f9814c0ae7 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -7,7 +7,6 @@ CROSS_COMPILE ?= i386-linux- # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! LDPPFLAGS += -DRESET_SEG_START=$(CONFIG_RESET_SEG_START) -LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE) LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC) LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 090/126] x86: Update Kconfig options for FSP1
Many of the Kconfig options do not apply to FSP2. Update them to use the FSP_VERSION1 condition instead. Signed-off-by: Simon Glass --- arch/x86/Kconfig | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 47bf28c434f..0de3f6ed7da 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -397,7 +397,7 @@ endchoice config FSP_FILE string "Firmware Support Package binary filename" - depends on HAVE_FSP + depends on FSP_VERSION1 default "fsp.bin" help The filename of the file to use as Firmware Support Package binary @@ -405,7 +405,7 @@ config FSP_FILE config FSP_ADDR hex "Firmware Support Package binary location" - depends on HAVE_FSP + depends on FSP_VERSION1 default 0xfffc help FSP is not Position Independent Code (PIC) and the whole FSP has to @@ -418,7 +418,7 @@ config FSP_ADDR config FSP_TEMP_RAM_ADDR hex - depends on HAVE_FSP + depends on FSP_VERSION1 default 0x200 help Stack top address which is used in fsp_init() after DRAM is ready and @@ -426,14 +426,14 @@ config FSP_TEMP_RAM_ADDR config FSP_SYS_MALLOC_F_LEN hex - depends on HAVE_FSP + depends on FSP_VERSION1 default 0x10 help Additional size of malloc() pool before relocation. config FSP_USE_UPD bool - depends on HAVE_FSP + depends on FSP_VERSION1 default y help Most FSPs use UPD data region for some FSP customization. But there @@ -442,7 +442,7 @@ config FSP_USE_UPD config FSP_BROKEN_HOB bool - depends on HAVE_FSP + depends on FSP_VERSION1 help Indicate some buggy FSPs that does not report memory used by FSP itself as reserved in the resource descriptor HOB. Select this to @@ -600,7 +600,7 @@ config VGA_BIOS_ADDR config HAVE_VBT bool "Add a Video BIOS Table (VBT) image" - depends on HAVE_FSP + depends on FSP_VERSION1 help Select this option if you have a Video BIOS Table (VBT) image that you would like to add to your ROM. This is normally required if you -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 102/126] x86: Update .dtsi file for FSP2
Include the IFWI section and the FSP-M binary. The FSP-T binary is not
currently used, as CAR is set up manually.
Also drop the FSP binary as this relates only to FSP1.
Signed-off-by: Simon Glass
---
arch/x86/dts/u-boot.dtsi | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 35129d0510b..189be2196cb 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -104,12 +104,39 @@
offset = ;
};
#endif
-#ifdef CONFIG_HAVE_FSP
+#ifdef CONFIG_FSP_VERSION1
intel-fsp {
filename = CONFIG_FSP_FILE;
offset = ;
};
#endif
+#ifdef CONFIG_FSP_VERSION2
+ intel-descriptor {
+ filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+ };
+ intel-ifwi {
+ filename = CONFIG_IFWI_INPUT_FILE;
+ convert-fit;
+
+ section {
+ size = <0x8000>;
+ ifwi-replace;
+ ifwi-subpart = "IBBP";
+ ifwi-entry = "IBBL";
+ u-boot-tpl {
+ };
+ x86-start16-tpl {
+ offset = <0x7800>;
+ };
+ x86-reset16-tpl {
+ offset = <0x7ff0>;
+ };
+ };
+ };
+ intel-fsp-m {
+ filename = CONFIG_FSP_FILE_M;
+ };
+#endif
#ifdef CONFIG_HAVE_CMC
intel-cmc {
filename = CONFIG_CMC_FILE;
--
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[U-Boot] [PATCH 108/126] x86: apollolake: Add basic IO addresses
Add some fixed IO and mmap addresses for use in the device tree and with some early-init code. Signed-off-by: Simon Glass --- arch/x86/include/asm/arch-apollolake/iomap.h | 28 1 file changed, 28 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/iomap.h diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h new file mode 100644 index 000..200c76a8eef --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Take from coreboot project file of the same name + */ + +#ifndef __ARCH_IOMAP_H +#define __ARCH_IOMAP_H + +#define TCO_BASE_ADDRESS (ACPI_BASE_ADDRESS + 0x60) +#define TCO_BASE_SIZE 0x20 + +#define R_ACPI_PM1_TMR 0x8 + +/* Put p2sb at 0xd000 in TPL */ +#define IOMAP_P2SB_BAR 0xd000 + +#define IOMAP_SPI_BASE 0xfe01 +/* + * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial + * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE. + */ +#define PCH_DEV_UART PCI_BDF(0, 0x18, 2) + +#define PCH_DEV_LPCPCI_BDF(0, 0x1f, 0) +#define PCH_DEV_SPIPCI_BDF(0, 0x0d, 2) + +#endif -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 104/126] x86: Add an option to control the position of SPL
For apollolake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
Add a Kconfig option for the ROM position.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig | 5 +
arch/x86/dts/u-boot.dtsi | 4 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 02c116caeb7..9d01801ff13 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -896,4 +896,9 @@ config X86_OFFSET_U_BOOT
depends on HAS_SYS_TEXT_BASE
default SYS_TEXT_BASE
+config X86_OFFSET_SPL
+ hex "Offset of SPL in ROM image"
+ depends on X86
+ default SPL_TEXT_BASE
+
endmenu
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index f33f276b90d..8fc5146f26c 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -49,7 +49,7 @@
u-boot-tpl-dtb {
};
u-boot-spl {
- offset = ;
+ offset = ;
};
u-boot-spl-dtb {
};
@@ -58,7 +58,7 @@
};
#elif defined(CONFIG_SPL)
u-boot-spl-with-ucode-ptr {
- offset = ;
+ offset = ;
};
u-boot-dtb-with-ucode2 {
type = "u-boot-dtb-with-ucode";
--
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[U-Boot] [PATCH 101/126] x86: Use fsp command with FSP1
The current 'fsp' command only works with FSP1. Update it to avoid trying to build it with FSP2. Signed-off-by: Simon Glass --- cmd/x86/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/x86/Makefile b/cmd/x86/Makefile index 144b1cf5abe..c50ddccef57 100644 --- a/cmd/x86/Makefile +++ b/cmd/x86/Makefile @@ -3,4 +3,4 @@ obj-y += mtrr.o obj-$(CONFIG_CMD_EXCEPTION) += exception.o obj-$(CONFIG_USE_HOB) += hob.o -obj-$(CONFIG_HAVE_FSP) += fsp.o +obj-$(CONFIG_FSP_VERSION1) += fsp.o -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 079/126] x86: Reduce mrccache record alignment size
At present the records are 4KB in size. This is unnecessarily large when
the SPI-flash erase size is 256 bytes. Reduce it so it will be more
efficient with Apollolake's 24-byte variable-data record.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/mrccache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h
index 40fda856ff4..abf58182237 100644
--- a/arch/x86/include/asm/mrccache.h
+++ b/arch/x86/include/asm/mrccache.h
@@ -7,7 +7,7 @@
#ifndef _ASM_MRCCACHE_H
#define _ASM_MRCCACHE_H
-#define MRC_DATA_ALIGN 0x1000
+#define MRC_DATA_ALIGN 0x100
#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \
('C' << 16) | ('D'<<24))
--
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[U-Boot] [PATCH 092/126] x86: Allow removal of standard PCH drivers
These drivers are not needed on all platforms. While they are small, it is useful in TPL to drop then. Add Kconfig control to allow this. Signed-off-by: Simon Glass --- drivers/pch/Kconfig | 18 ++ drivers/pch/Makefile | 4 ++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/pch/Kconfig b/drivers/pch/Kconfig index 18f006de24c..a02a1b857cc 100644 --- a/drivers/pch/Kconfig +++ b/drivers/pch/Kconfig @@ -7,3 +7,21 @@ config PCH northbridge / southbridge architecture that was previously used. The PCH allows for higher performance since the memory functions are handled in the CPU. + +config X86_PCH7 + bool "Add support for Intel PCH7" + default y if X86 + help + Enable this if your SoC uses Platform Controller Hub 7 (PCH7). This + dates from about 2011 and is used on queensbay, for example. The + PCH proides access to the GPIO and SPI base addresses, among other + functions. + +config X86_PCH9 + bool "Add support for Intel PCH9" + default y if X86 + help + Enable this if your SoC uses Platform Controller Hub 9 (PCH9). This + dates from about 2015 and is used on queensbay, for example. The + PCH proides access to the GPIO and SPI base addresses, among other + functions. diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile index 8ea6b7852ac..d5de3e48be1 100644 --- a/drivers/pch/Makefile +++ b/drivers/pch/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += pch-uclass.o -obj-y += pch7.o -obj-y += pch9.o +obj-$(CONFIG_X86_PCH7) += pch7.o +obj-$(CONFIG_X86_PCH9) += pch9.o obj-$(CONFIG_SANDBOX) += sandbox_pch.o -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 076/126] x86: Add a uclass for ITSS
This models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. It is something
to do with interrupts.
It supports two operations.
Signed-off-by: Simon Glass
---
drivers/misc/Kconfig | 9 ++
drivers/misc/Makefile | 1 +
drivers/misc/itss-uclass.c | 34 +++
include/dm/uclass-id.h | 1 +
include/itss.h | 56 ++
5 files changed, 101 insertions(+)
create mode 100644 drivers/misc/itss-uclass.c
create mode 100644 include/itss.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 74055a35516..62c9e1089db 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -194,6 +194,15 @@ config FSL_SEC_MON
Security Monitor can be transitioned on any security failures,
like software violations or hardware security violations.
+config ITSS
+ bool "Intel ITSS Interrupt controller"
+ depends on X86 || SANDBOX
+ help
+ This enabled support for the Intel ITSS, a type of interrupt
+ controller. It is present on apollolake and some other SoCs. The
+ device has its own uclass since there are several operations
+ involved.
+
config JZ4780_EFUSE
bool "Ingenic JZ4780 eFUSE support"
depends on ARCH_JZ47XX
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 90ef92806b9..f715d6d6df5 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
+obj-$(CONFIG_ITSS) += itss-uclass.o
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
diff --git a/drivers/misc/itss-uclass.c b/drivers/misc/itss-uclass.c
new file mode 100644
index 000..664865cec3f
--- /dev/null
+++ b/drivers/misc/itss-uclass.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ITSS is a type of interrupt controller used on recent Intel SoC.
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+
+int itss_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
+{
+ const struct itss_ops *ops = itss_get_ops(dev);
+
+ if (!ops->route_pmc_gpio_gpe)
+ return -ENOSYS;
+
+ return ops->route_pmc_gpio_gpe(dev, pmc_gpe_num);
+}
+
+int itss_set_irq_polarity(struct udevice *dev, uint irq, bool active_low)
+{
+ const struct itss_ops *ops = itss_get_ops(dev);
+
+ if (!ops->set_irq_polarity)
+ return -ENOSYS;
+
+ return ops->set_irq_polarity(dev, irq, active_low);
+}
+
+UCLASS_DRIVER(itss) = {
+ .id = UCLASS_ITSS,
+ .name = "itss",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 496570ff47d..892c746940d 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -54,6 +54,7 @@ enum uclass_id {
UCLASS_I2S, /* I2S bus */
UCLASS_IDE, /* IDE device */
UCLASS_IRQ, /* Interrupt controller */
+ UCLASS_ITSS,/* Intel interrupt thingy */
UCLASS_KEYBOARD,/* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
UCLASS_LPC, /* x86 'low pin count' interface */
diff --git a/include/itss.h b/include/itss.h
new file mode 100644
index 000..1a282cbac56
--- /dev/null
+++ b/include/itss.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ITSS is a type of interrupt controller used on recent Intel SoC.
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ITSS_H
+#define __ITSS_H
+
+/**
+ * struct itss_ops - Operations for the ITSS
+ */
+struct itss_ops {
+ /**
+* route_pmc_gpio_gpe() - Get the GPIO for an event
+*
+* @dev: ITSS device
+* @pmc_gpe_num: Event number to check
+* @returns GPIO for the event, or -ENOENT if none
+*/
+ int (*route_pmc_gpio_gpe)(struct udevice *dev, uint pmc_gpe_num);
+
+ /**
+* set_irq_polarity() - Set the IRQ polarity
+*
+* @dev: ITSS device
+* @irq: Interrupt number to set
+* @active_low: true if active low, false for active high
+* @return 0 if OK, -EINVAL if @irq is invalid
+*/
+ int (*set_irq_polarity)(struct udevice *dev, uint irq, bool active_low);
+};
+
+#define itss_get_ops(dev) ((struct itss_ops *)(dev)->driver->ops)
+
+/**
+ * itss_route_pmc_gpio_gpe() - Get the GPIO for an event
+ *
+ * @dev: ITSS device
+ * @pmc_gpe_num: Event number to check
+ * @returns GPIO for the event, or -ENOENT if none
+ */
+int itss_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num);
+
+/**
+ * set_irq_polarity() - Set the IRQ polarity
+ *
+ * @dev: ITSS device
+ * @irq: Interrupt number to set
+ * @active_low: t
[U-Boot] [PATCH 088/126] x86: Set the DRAM banks to reflect real location
At present with fsp a single DRAM bank is added which extends to the
whole size of memory. However there is typically only 2GB of memory
available below the 4GB boundary, and this is what is used by U-Boot while
running in 32-bit mode.
Scan the tables to set the banks correct. The first bank is set to memory
below 4GB, and the rest of memory is put into subsequent banks.
Signed-off-by: Simon Glass
---
arch/x86/lib/fsp/fsp_dram.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 38cc25839ec..9161af65b98 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -37,8 +37,38 @@ int fsp_scan_for_ram_size(void)
int dram_init_banksize(void)
{
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
+ phys_addr_t low_end;
+ uint bank;
+
+ low_end = 0;
+ for (bank = 1, hdr = gd->arch.hob_list;
+bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
+hdr = get_next_hob(hdr)) {
+ if (hdr->type != HOB_TYPE_RES_DESC)
+ continue;
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type != RES_SYS_MEM &&
+ res_desc->type != RES_MEM_RESERVED)
+ continue;
+ if (res_desc->phys_start < (1ULL << 32)) {
+ low_end = max(low_end,
+ res_desc->phys_start + res_desc->len);
+ continue;
+ }
+
+ gd->bd->bi_dram[bank].start = res_desc->phys_start;
+ gd->bd->bi_dram[bank].size = res_desc->len;
+ mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
+res_desc->len);
+ log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
+ gd->bd->bi_dram[bank].size);
+ }
+
+ /* Add the memory below 4GB */
gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->bd->bi_dram[0].size = low_end;
return 0;
}
--
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[U-Boot] [PATCH 082/126] x86: Adjust mrccache_get_region() to use livetree
Change the algorithm to first find the flash device then read the
properties using the livetree API. With this change the device is not
probed so this needs to be done in mrccache_save().
Signed-off-by: Simon Glass
---
arch/x86/lib/mrccache.c | 59 ++---
1 file changed, 31 insertions(+), 28 deletions(-)
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index e286bdf1b30..296dd5e54f7 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -14,6 +14,8 @@
#include
#include
#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -197,45 +199,43 @@ int mrccache_reserve(void)
int mrccache_get_region(struct udevice **devp, struct mrc_region *entry)
{
- const void *blob = gd->fdt_blob;
- int node, mrc_node;
+ struct udevice *dev;
+ ofnode mrc_node;
+ ulong map_base;
+ size_t map_size;
+ u32 offset;
u32 reg[2];
int ret;
/* Find the flash chip within the SPI controller node */
- node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
- if (node < 0) {
- debug("%s: Cannot find SPI flash\n", __func__);
- return -ENOENT;
- }
-
- if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) {
- debug("%s: Cannot find memory map\n", __func__);
- return -EINVAL;
+ ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
+ if (ret)
+ return log_msg_ret("Cannot find SPI flash\n", ret);
+ ret = spi_flash_get_mmap(dev, &map_base, &map_size, &offset);
+ if (!ret) {
+ entry->base = map_base;
+ } else {
+ ret = dev_read_u32_array(dev, "memory-map", reg, 2);
+ if (ret)
+ return log_msg_ret("Cannot find memory map\n", ret);
+ entry->base = reg[0];
}
- entry->base = reg[0];
/* Find the place where we put the MRC cache */
- mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache");
- if (mrc_node < 0) {
- debug("%s: Cannot find node\n", __func__);
- return -EPERM;
- }
+ mrc_node = dev_read_subnode(dev, "rw-mrc-cache");
+ if (!ofnode_valid(mrc_node))
+ return log_msg_ret("Cannot find node", -EPERM);
- if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) {
- debug("%s: Cannot find address\n", __func__);
- return -EINVAL;
- }
+ ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2);
+ if (ret)
+ return log_msg_ret("Cannot find address", ret);
entry->offset = reg[0];
entry->length = reg[1];
- if (devp) {
- ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
-devp);
- debug("ret = %d\n", ret);
- if (ret)
- return ret;
- }
+ if (devp)
+ *devp = dev;
+ debug("MRC cache in '%s', offset %x, len %x, base %x\n",
+ dev->name, entry->offset, entry->length, entry->base);
return 0;
}
@@ -253,6 +253,9 @@ int mrccache_save(void)
gd->arch.mrc_output_len);
ret = mrccache_get_region(&sf, &entry);
+ if (ret)
+ goto err_entry;
+ ret = device_probe(sf);
if (ret)
goto err_entry;
data = (struct mrc_data_container *)gd->arch.mrc_output;
--
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[U-Boot] [PATCH 100/126] x86: Disable microcode section for FSP2
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig | 4
arch/x86/dts/u-boot.dtsi | 11 +++
2 files changed, 15 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e797612e30e..fce3c1d92a3 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -580,6 +580,10 @@ config HAVE_REFCODE
broadwell) U-Boot will be missing some critical setup steps.
Various peripherals may fail to work.
+config HAVE_MICROCODE
+ bool
+ default y if !FSP_VERSION2
+
config SMP
bool "Enable Symmetric Multiprocessing"
default n
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 049f47c9ffd..35129d0510b 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -37,9 +37,15 @@
};
#endif
#ifdef CONFIG_TPL
+#ifdef CONFIG_HAVE_MICROCODE
u-boot-tpl-with-ucode-ptr {
offset = ;
};
+#else
+ u-boot-tpl {
+ offset = <0x>;
+ };
+#endif
u-boot-tpl-dtb {
};
u-boot-spl {
@@ -77,11 +83,16 @@
offset = ;
};
#endif
+#ifdef CONFIG_HAVE_MICROCODE
u-boot-dtb-with-ucode {
};
u-boot-ucode {
align = <16>;
};
+#else
+ u-boot-dtb {
+ };
+#endif
#ifdef CONFIG_X86_HAS_FIT
intel-fit {
};
--
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[U-Boot] [PATCH 075/126] sandbox: Add PCI driver and test for p2sb
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.
Signed-off-by: Simon Glass
---
arch/sandbox/cpu/state.c| 1 +
arch/sandbox/dts/test.dts | 13 ++
arch/sandbox/include/asm/test.h | 10 ++
drivers/misc/Makefile | 2 +
drivers/misc/p2sb_emul.c| 272
drivers/misc/p2sb_sandbox.c | 44 ++
drivers/misc/sandbox_adder.c| 60 +++
test/dm/Makefile| 1 +
test/dm/p2sb.c | 28
9 files changed, 431 insertions(+)
create mode 100644 drivers/misc/p2sb_emul.c
create mode 100644 drivers/misc/p2sb_sandbox.c
create mode 100644 drivers/misc/sandbox_adder.c
create mode 100644 test/dm/p2sb.c
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index dee5fde4f73..cd46e000f5e 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -356,6 +356,7 @@ void state_reset_for_test(struct sandbox_state *state)
/* No reset yet, so mark it as such. Always allow power reset */
state->last_sysreset = SYSRESET_COUNT;
state->sysreset_allowed[SYSRESET_POWER_OFF] = true;
+ state->allow_memio = false;
memset(&state->wdt, '\0', sizeof(state->wdt));
memset(state->spi, '\0', sizeof(state->spi));
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 9b72c2f279c..cd4409b7aea 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -461,6 +461,16 @@
0x0100f810 0 0 0 0>;
sandbox,emul = <&swap_case_emul1>;
};
+ p2sb-pci@2,0 {
+ compatible = "sandbox,p2sb";
+ reg = <0x02001010 0 0 0 0>;
+ sandbox,emul = <&p2sb_emul>;
+
+ adder {
+ intel,p2sb-port-id = <3>;
+ compatible = "sandbox,adder";
+ };
+ };
pci@1e,0 {
compatible = "sandbox,pmc";
reg = <0xf000 0 0 0 0>;
@@ -489,6 +499,9 @@
compatible = "sandbox,swap-case";
use-ea;
};
+ p2sb_emul: emul@2,0 {
+ compatible = "sandbox,p2sb-emul";
+ };
pmc_emul1e: emul@1e,0 {
compatible = "sandbox,pmc-emul";
};
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index 7f9e7fc26f5..77fff529e19 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -14,6 +14,7 @@
#define SANDBOX_PCI_VENDOR_ID 0x1234
#define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678
#define SANDBOX_PCI_PMC_EMUL_ID0x5677
+#define SANDBOX_PCI_P2SB_EMUL_ID 0x5676
#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
@@ -214,4 +215,13 @@ int sandbox_get_pci_ep_irq_count(struct udevice *dev);
*/
uint sandbox_pci_read_bar(u32 barval, int type, uint size);
+/**
+ * sandbox_set_enable_memio() - Enable memory-mapped I/O read/write
+ *
+ * Normally readl(), writel() and the like are nops on sandbox. If this
function
+ * is called with true, those function do real memory accesses. This is useful
+ * for certain tests.
+ */
+void sandbox_set_enable_memio(bool enable);
+
#endif
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 840d9fa5e39..90ef92806b9 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o
ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_SANDBOX) += sandbox_adder.o
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
obj-$(CONFIG_SANDBOX) += swap_case.o
@@ -50,6 +51,7 @@ obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
obj-$(CONFIG_P2SB) += p2sb-uclass.o
+obj-$(CONFIG_SANDBOX) += p2sb_sandbox.o p2sb_emul.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
obj-$(CONFIG_QFW) += qfw.o
diff --git a/drivers/misc/p2sb_emul.c b/drivers/misc/p2sb_emul.c
new file mode 100644
index 000..c51db143495
--- /dev/null
+++ b/drivers/misc/p2sb_emul.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PCI emulation device for an x86 Primary-to-Sideband bus
+ *
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass
+ */
+
+#define LOG_CATEGORY UCLASS_MISC
+#define LOG_DEBUG
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct p2sb_emul_platdata - platform data for this device
+ *
+ * @command: Current PCI command valu
[U-Boot] [PATCH 073/126] trace: Remove the const from write functions
The write functions do actually change the contents of memory so it is not
correct to use 'const'. Remove it.
Signed-off-by: Simon Glass
---
common/iotrace.c | 6 +++---
include/iotrace.h | 13 ++---
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/common/iotrace.c b/common/iotrace.c
index 49bee3c92a0..5b92fabc76e 100644
--- a/common/iotrace.c
+++ b/common/iotrace.c
@@ -86,7 +86,7 @@ u32 iotrace_readl(const void *ptr)
return v;
}
-void iotrace_writel(ulong value, const void *ptr)
+void iotrace_writel(ulong value, void *ptr)
{
add_record(IOT_32 | IOT_WRITE, ptr, value);
writel(value, ptr);
@@ -102,7 +102,7 @@ u16 iotrace_readw(const void *ptr)
return v;
}
-void iotrace_writew(ulong value, const void *ptr)
+void iotrace_writew(ulong value, void *ptr)
{
add_record(IOT_16 | IOT_WRITE, ptr, value);
writew(value, ptr);
@@ -118,7 +118,7 @@ u8 iotrace_readb(const void *ptr)
return v;
}
-void iotrace_writeb(ulong value, const void *ptr)
+void iotrace_writeb(ulong value, void *ptr)
{
add_record(IOT_8 | IOT_WRITE, ptr, value);
writeb(value, ptr);
diff --git a/include/iotrace.h b/include/iotrace.h
index be1d2753e19..380da1fbc2c 100644
--- a/include/iotrace.h
+++ b/include/iotrace.h
@@ -49,30 +49,29 @@ struct iotrace_record {
#define readl(addr)iotrace_readl((const void *)(addr))
#undef writel
-#define writel(val, addr) iotrace_writel(val, (const void *)(addr))
+#define writel(val, addr) iotrace_writel(val, (void *)(addr))
#undef readw
#define readw(addr)iotrace_readw((const void *)(addr))
#undef writew
-#define writew(val, addr) iotrace_writew(val, (const void *)(addr))
+#define writew(val, addr) iotrace_writew(val, (void *)(addr))
#undef readb
#define readb(addr)iotrace_readb((const void *)(uintptr_t)addr)
#undef writeb
-#define writeb(val, addr) \
- iotrace_writeb(val, (const void *)(uintptr_t)addr)
+#define writeb(val, addr) iotrace_writeb(val, (void *)(uintptr_t)addr)
#endif
/* Tracing functions which mirror their io.h counterparts */
u32 iotrace_readl(const void *ptr);
-void iotrace_writel(ulong value, const void *ptr);
+void iotrace_writel(ulong value, void *ptr);
u16 iotrace_readw(const void *ptr);
-void iotrace_writew(ulong value, const void *ptr);
+void iotrace_writew(ulong value, void *ptr);
u8 iotrace_readb(const void *ptr);
-void iotrace_writeb(ulong value, const void *ptr);
+void iotrace_writeb(ulong value, void *ptr);
/**
* iotrace_reset_checksum() - Reset the iotrace checksum
--
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[U-Boot] [PATCH 074/126] pci: Add support for p2sb uclass
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.
This adds a uclass and enables it for sandbox.
Signed-off-by: Simon Glass
---
configs/sandbox_defconfig | 1 +
configs/sandbox_spl_defconfig | 1 +
drivers/misc/Kconfig | 33 ++
drivers/misc/Makefile | 1 +
drivers/misc/p2sb-uclass.c| 199 ++
include/dm/uclass-id.h| 1 +
include/p2sb.h| 127 ++
7 files changed, 363 insertions(+)
create mode 100644 drivers/misc/p2sb-uclass.c
create mode 100644 include/p2sb.h
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index f77b9e8a7d1..6f4d8449290 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -149,6 +149,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
+CONFIG_P2SB=y
CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 409b8a38d5e..c49e05ec319 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -135,6 +135,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
+CONFIG_P2SB=y
CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 8037b6ee2d7..74055a35516 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -217,6 +217,39 @@ config NUVOTON_NCT6102D
disable the legacy UART, the watchdog or other devices
in the Nuvoton Super IO chips on X86 platforms.
+config P2SB
+ bool "Intel Primary-to-Sideband Bus"
+ depends on X86 || SANDBOX
+ help
+ This enables support for the Intel Primary-to-Sideband bus,
+ abbreviated to P2SB. The P2SB is used to access various peripherals
+ such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
+ space. The space is segmented into different channels and peripherals
+ are accessed by device-specific means within those channels. Devices
+ should be added in the device tree as subnodes of the P2SB. A
+ Peripheral Channel Register? (PCR) API is provided to access those
+ devices - see pcr_readl(), etc.
+
+config SPL_P2SB
+ bool "Intel Primary-to-Sideband Bus in SPL"
+ depends on SPL && (X86 || SANDBOX)
+ help
+ The Primary-to-Sideband bus is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
+config TPL_P2SB
+ bool "Intel Primary-to-Sideband Bus in TPL"
+ depends on TPL && (X86 || SANDBOX)
+ help
+ The Primary-to-Sideband bus is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
config PWRSEQ
bool "Enable power-sequencing drivers"
depends on DM
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 0001d105bae..840d9fa5e39 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
+obj-$(CONFIG_P2SB) += p2sb-uclass.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
obj-$(CONFIG_QFW) += qfw.o
diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c
new file mode 100644
index 000..7915eb5c3ed
--- /dev/null
+++ b/drivers/misc/p2sb-uclass.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Uclass for Primary-to-sideband bus, used to access various peripherals
+ *
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PCR_COMMON_IOSF_1_01
+
+static void *_pcr_reg_address(struct udevice *dev, uint offset)
+{
+ struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct udevice *p2sb = dev_get_parent(dev);
+ struct p2sb_uc_priv *upriv = dev_get_uclass_priv(p2sb);
+ uintptr_t reg_addr;
+
+ /* Create an address based off of port id and offset */
+ reg_addr = upriv->mmio_base;
+ reg_addr += pplat-
[U-Boot] [PATCH 072/126] x86: power: Add a 'pmc' command
Add a simple command to show information about the PMC.
Signed-off-by: Simon Glass
---
arch/Kconfig | 1 +
cmd/Kconfig | 8 ++
cmd/Makefile | 1 +
cmd/pmc.c| 81
4 files changed, 91 insertions(+)
create mode 100644 cmd/pmc.c
diff --git a/arch/Kconfig b/arch/Kconfig
index e22d62f9290..0374139fa89 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -134,6 +134,7 @@ config SANDBOX
imply DM_MDIO
imply DM_MDIO_MUX
imply POWER_MGR
+ imply CMD_PMC
imply POWER_MGR_SANDBOX
config SH
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 98647f58b7a..eaad9e52578 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -225,6 +225,14 @@ config CMD_LICENSE
help
Print GPL license text
+config CMD_PMC
+ bool "pmc"
+ help
+ Provides access to the Intel Power-Management Controller (PMC) so
+ that its state can be examined. This does not currently support
+ changing the state but it is still useful for debugging and seeing
+ what is going on.
+
config CMD_REGINFO
bool "reginfo"
depends on PPC
diff --git a/cmd/Makefile b/cmd/Makefile
index ac843b4b16a..8151ba8741f 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -108,6 +108,7 @@ ifdef CONFIG_PCI
obj-$(CONFIG_CMD_PCI) += pci.o
endif
obj-$(CONFIG_CMD_PINMUX) += pinmux.o
+obj-$(CONFIG_CMD_PMC) += pmc.o
obj-$(CONFIG_CMD_PXE) += pxe.o
obj-$(CONFIG_CMD_WOL) += wol.o
obj-$(CONFIG_CMD_QFW) += qfw.o
diff --git a/cmd/pmc.c b/cmd/pmc.c
new file mode 100644
index 000..704e8e86534
--- /dev/null
+++ b/cmd/pmc.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel PMC command
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+
+static int get_pmc_dev(struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_POWER_MGR, &dev);
+ if (ret) {
+ printf("Could not find device (err=%d)\n", ret);
+ return ret;
+ }
+ ret = pmc_init(dev);
+ if (ret) {
+ printf("Could not init device (err=%d)\n", ret);
+ return ret;
+ }
+ *devp = dev;
+
+ return 0;
+}
+
+static int do_pcm_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const
argv[])
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = get_pmc_dev(&dev);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static int do_pcm_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const
argv[])
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = get_pmc_dev(&dev);
+ if (ret)
+ return CMD_RET_FAILURE;
+ pmc_dump_info(dev);
+
+ return 0;
+}
+
+static cmd_tbl_t cmd_pmc_sub[] = {
+ U_BOOT_CMD_MKENT(init, 0, 1, do_pcm_init, "", ""),
+ U_BOOT_CMD_MKENT(info, 0, 1, do_pcm_info, "", ""),
+};
+
+static int do_pmc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const cmd_tbl_t *cp;
+
+ if (argc < 2) /* no subcommand */
+ return cmd_usage(cmdtp);
+
+ cp = find_cmd_tbl(argv[1], &cmd_pmc_sub[0], ARRAY_SIZE(cmd_pmc_sub));
+ if (!cp)
+ return CMD_RET_USAGE;
+
+ return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+ pmc, 2, 1, do_pmc, "Power-management controller info",
+ "info - read state and show info about the PMC\n"
+ "pcm init - read state from the PMC\n"
+ );
--
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[U-Boot] [PATCH 071/126] x86: sandbox: Add a PMC emulator and test
Add a simple PMC for sandbox to permit tests to run.
Signed-off-by: Simon Glass
---
Makefile | 3 +-
arch/Kconfig | 2 +
arch/sandbox/dts/sandbox.dtsi | 14 ++
arch/sandbox/dts/test.dts | 14 ++
arch/sandbox/include/asm/test.h| 1 +
drivers/Makefile | 2 +
drivers/power/power_mgr/Kconfig| 9 ++
drivers/power/power_mgr/Makefile | 2 +-
drivers/power/power_mgr/pmc_emul.c | 246 +
drivers/power/power_mgr/sandbox.c | 97
test/dm/Makefile | 1 +
test/dm/pmc.c | 33
12 files changed, 422 insertions(+), 2 deletions(-)
create mode 100644 drivers/power/power_mgr/pmc_emul.c
create mode 100644 drivers/power/power_mgr/sandbox.c
create mode 100644 test/dm/pmc.c
diff --git a/Makefile b/Makefile
index 43961af590f..f008d13d02a 100644
--- a/Makefile
+++ b/Makefile
@@ -725,7 +725,8 @@ libs-y += drivers/power/ \
drivers/power/mfd/ \
drivers/power/pmic/ \
drivers/power/battery/ \
- drivers/power/regulator/
+ drivers/power/regulator/ \
+ drivers/power/power_mgr/
libs-y += drivers/spi/
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
diff --git a/arch/Kconfig b/arch/Kconfig
index 141e48bc439..e22d62f9290 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -133,6 +133,8 @@ config SANDBOX
imply PHYLIB
imply DM_MDIO
imply DM_MDIO_MUX
+ imply POWER_MGR
+ imply POWER_MGR_SANDBOX
config SH
bool "SuperH architecture"
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index f09bc70b0da..7bf144f5326 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -100,6 +100,17 @@
};
pci-controller {
+ pci@1e,0 {
+ compatible = "sandbox,pmc";
+ reg = <0xf000 0 0 0 0>;
+ sandbox,emul = <&pmc_emul>;
+ gpe0-dwx-mask = <0xf>;
+ gpe0-dwx-shift-base = <4>;
+ gpe0-dw = <6 7 9>;
+ gpe0-sts = <0x20>;
+ gpe0-en = <0x30>;
+ };
+
pci@1f,0 {
compatible = "pci-generic";
reg = <0xf800 0 0 0 0>;
@@ -109,6 +120,9 @@
emul {
compatible = "sandbox,pci-emul-parent";
+ pmc_emul: emul@1e,0 {
+ compatible = "sandbox,pmc-emul";
+ };
swap_case_emul: emul@1f,0 {
compatible = "sandbox,swap-case";
};
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 8733e0d7e19..9b72c2f279c 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -461,6 +461,17 @@
0x0100f810 0 0 0 0>;
sandbox,emul = <&swap_case_emul1>;
};
+ pci@1e,0 {
+ compatible = "sandbox,pmc";
+ reg = <0xf000 0 0 0 0>;
+ sandbox,emul = <&pmc_emul1e>;
+ acpi-base = <0x400>;
+ gpe0-dwx-mask = <0xf>;
+ gpe0-dwx-shift-base = <4>;
+ gpe0-dw = <6 7 9>;
+ gpe0-sts = <0x20>;
+ gpe0-en = <0x30>;
+ };
pci@1f,0 {
compatible = "pci-generic";
/* BAR1 is at 0x10, using FDT_PCI_SPACE_IO */
@@ -478,6 +489,9 @@
compatible = "sandbox,swap-case";
use-ea;
};
+ pmc_emul1e: emul@1e,0 {
+ compatible = "sandbox,pmc-emul";
+ };
swap_case_emul1f: emul@1f,0 {
compatible = "sandbox,swap-case";
};
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index cd2b9e3155d..7f9e7fc26f5 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -13,6 +13,7 @@
#define SANDBOX_PCI_VENDOR_ID 0x1234
#define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678
+#define SANDBOX_PCI_PMC_EMUL_ID0x5677
#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
diff --git a/drivers/Makefile b/drivers/Makefile
index a4bb5e4975c..b2e081e6cc8 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
+obj-$(CONFIG_SPL_POWER_MGR) += power/power_mgr/
obj-$(CONFIG_SPL_POWER_DOM
[U-Boot] [PATCH 070/126] x86: power: Add a PMC uclass
Intel x86 SoCs have a power manager/controller which handles several
power-related aspects of the platform. Add a uclass for this, with a few
useful operations.
Signed-off-by: Simon Glass
---
drivers/power/Kconfig | 2 +
drivers/power/power_mgr/Kconfig| 25 +++
drivers/power/power_mgr/Makefile | 6 +
drivers/power/power_mgr/power-mgr-uclass.c | 191 +
include/dm/uclass-id.h | 1 +
include/power/power_mgr.h | 177 +++
6 files changed, 402 insertions(+)
create mode 100644 drivers/power/power_mgr/Kconfig
create mode 100644 drivers/power/power_mgr/Makefile
create mode 100644 drivers/power/power_mgr/power-mgr-uclass.c
create mode 100644 include/power/power_mgr.h
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 9495dca33b9..1cb3f6d5e25 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -4,6 +4,8 @@ source "drivers/power/domain/Kconfig"
source "drivers/power/pmic/Kconfig"
+source "drivers/power/power_mgr/Kconfig"
+
source "drivers/power/regulator/Kconfig"
choice
diff --git a/drivers/power/power_mgr/Kconfig b/drivers/power/power_mgr/Kconfig
new file mode 100644
index 000..2731518462f
--- /dev/null
+++ b/drivers/power/power_mgr/Kconfig
@@ -0,0 +1,25 @@
+config POWER_MGR
+ bool "Power Manager (x86 PMC) support"
+ help
+ Enable support for an x86-style power-management controller which
+ provides features including checking whether the system started from
+ resume, powering off the system and enabling/disabling the reset
+ mechanism.
+
+config SPL_POWER_MGR
+ bool "Power Manager (x86 PMC) support in SPL"
+ default y if POWER_MGR
+ help
+ Enable support for an x86-style power-management controller which
+ provides features including checking whether the system started from
+ resume, powering off the system and enabling/disabling the reset
+ mechanism.
+
+config TPL_POWER_MGR
+ bool "Power Manager (x86 PMC) support in TPL"
+ default y if POWER_MGR
+ help
+ Enable support for an x86-style power-management controller which
+ provides features including checking whether the system started from
+ resume, powering off the system and enabling/disabling the reset
+ mechanism.
diff --git a/drivers/power/power_mgr/Makefile b/drivers/power/power_mgr/Makefile
new file mode 100644
index 000..87542f5248a
--- /dev/null
+++ b/drivers/power/power_mgr/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-$(CONFIG_$(SPL_TPL_)POWER_MGR) += power-mgr-uclass.o
+
diff --git a/drivers/power/power_mgr/power-mgr-uclass.c
b/drivers/power/power_mgr/power-mgr-uclass.c
new file mode 100644
index 000..0d73caf8cf6
--- /dev/null
+++ b/drivers/power/power_mgr/power-mgr-uclass.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_POWER_MGR
+
+#include
+#include
+#include
+#include
+#include
+#ifdef CONFIG_CREATE_ARCH_SYMLINK
+#include
+#endif
+#include
+
+enum {
+ PM1_STS = 0x00,
+ PM1_EN = 0x02,
+ PM1_CNT = 0x04,
+
+ GPE0_STS= 0x20,
+ GPE0_EN = 0x30,
+};
+
+struct tco_regs {
+ u32 tco_rld;
+ u32 tco_sts;
+ u32 tco1_cnt;
+ u32 tco_tmr;
+};
+
+enum {
+ TCO_STS_TIMEOUT = 1 << 3,
+ TCO_STS_SECOND_TO_STS = 1 << 17,
+ TCO1_CNT_HLT= 1 << 11,
+};
+
+static void pmc_fill_pm_reg_info(struct udevice *dev)
+{
+ struct power_mgr_upriv *upriv = dev_get_uclass_priv(dev);
+ int i;
+
+ upriv->pm1_sts = inw(upriv->acpi_base + PM1_STS);
+ upriv->pm1_en = inw(upriv->acpi_base + PM1_EN);
+ upriv->pm1_cnt = inw(upriv->acpi_base + PM1_CNT);
+
+ log_debug("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
+ upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
+
+ for (i = 0; i < GPE0_REG_MAX; i++) {
+ upriv->gpe0_sts[i] = inl(upriv->acpi_base + GPE0_STS + i * 4);
+ upriv->gpe0_en[i] = inl(upriv->acpi_base + GPE0_EN + i * 4);
+ log_debug("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
+ upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
+ }
+}
+
+int pmc_disable_tco_base(ulong tco_base)
+{
+ struct tco_regs *regs = (struct tco_regs *)tco_base;
+
+ debug("tco_base %lx = %x\n", (ulong)®s->tco1_cnt, TCO1_CNT_HLT);
+ setio_32(®s->tco1_cnt, TCO1_CNT_HLT);
+
+ return 0;
+}
+
+int pmc_init(struct udevice *dev)
+{
+ const struct power_mgr_ops *ops = power_mgr_get_ops(dev);
+ int ret;
+
+ pmc_fill_pm_reg_info(dev);
+ if (!ops->init)
+ return -ENOSYS;
+
+ ret = ops->init(dev);
+ if (ret)
+
[U-Boot] [PATCH 065/126] x86: Use mtrr_commit() with FSP2
With FSP2 we use MTRRs in U-Boot proper even though the 32-bit init
happens in TPL. Enable this, using a variable to try to make the
conditions more palatable.
Signed-off-by: Simon Glass
---
arch/x86/lib/init_helpers.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 4774a9bdb78..3e3a11ac2fa 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -12,15 +12,23 @@ DECLARE_GLOBAL_DATA_PTR;
int init_cache_f_r(void)
{
-#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) && \
- !defined(CONFIG_SYS_SLIMBOOTLOADER)
+ bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
+IS_ENABLED(CONFIG_FSP_VERSION2);
int ret;
- ret = mtrr_commit(false);
- /* If MTRR MSR is not implemented by the processor, just ignore it */
- if (ret && ret != -ENOSYS)
- return ret;
-#endif
+ do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
+ !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
+
+ if (do_mtrr) {
+ ret = mtrr_commit(false);
+ /*
+* If MTRR MSR is not implemented by the processor, just ignore
+* it
+*/
+ if (ret && ret != -ENOSYS)
+ return ret;
+ }
+
/* Initialise the CPU cache(s) */
return init_cache();
}
--
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[U-Boot] [PATCH 069/126] sandbox: pci: Remember the device being emulated
Add a field to the PCI emulator per-device data which records which device
is being emulated. This is useful when the emulator needs to check the
device for something.
Signed-off-by: Simon Glass
---
drivers/pci/pci-emul-uclass.c | 32 +---
include/pci.h | 20
2 files changed, 45 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/pci-emul-uclass.c b/drivers/pci/pci-emul-uclass.c
index 6e6172836a4..589fb539031 100644
--- a/drivers/pci/pci-emul-uclass.c
+++ b/drivers/pci/pci-emul-uclass.c
@@ -18,6 +18,7 @@ struct sandbox_pci_emul_priv {
int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
struct udevice **containerp, struct udevice **emulp)
{
+ struct pci_emul_uc_priv *upriv;
struct udevice *dev;
int ret;
@@ -30,17 +31,33 @@ int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t
find_devfn,
}
*containerp = dev;
- /*
-* TODO(s...@chromium.org): This code needs a comment as I'm not sure
-* why UCLASS_PCI_GENERIC devices end up being their own emulators. I
-* left this code as is.
-*/
ret = uclass_get_device_by_phandle(UCLASS_PCI_EMUL, dev, "sandbox,emul",
emulp);
- if (ret && device_get_uclass_id(dev) != UCLASS_PCI_GENERIC)
+ if (!ret) {
+ upriv = dev_get_uclass_priv(*emulp);
+
+ upriv->client = dev;
+ } else if (device_get_uclass_id(dev) != UCLASS_PCI_GENERIC) {
+ /*
+* TODO(s...@chromium.org): This code needs a comment as I'm not
+* sure why non-UCLASS_PCI_GENERIC devices end up being their
+* own emulators. I left this code as is.
+*/
*emulp = dev;
+ }
+
+ return 0;
+}
- return *emulp ? 0 : -ENODEV;
+int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp)
+{
+ struct pci_emul_uc_priv *upriv = dev_get_uclass_priv(emul);
+
+ if (!upriv->client)
+ return -ENOENT;
+ *devp = upriv->client;
+
+ return 0;
}
uint sandbox_pci_read_bar(u32 barval, int type, uint size)
@@ -89,6 +106,7 @@ UCLASS_DRIVER(pci_emul) = {
.post_probe = sandbox_pci_emul_post_probe,
.pre_remove = sandbox_pci_emul_pre_remove,
.priv_auto_alloc_size = sizeof(struct sandbox_pci_emul_priv),
+ .per_device_auto_alloc_size = sizeof(struct pci_emul_uc_priv),
};
/*
diff --git a/include/pci.h b/include/pci.h
index 8aa6636cfbf..ff59ac0e695 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1490,6 +1490,17 @@ int dm_pci_find_device(unsigned int vendor, unsigned int
device, int index,
*/
int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
+/**
+ * struct pci_emul_uc_priv - holds info about an emulator device
+ *
+ * There is always at most one emulator per client
+ *
+ * @client: Client device if any, else NULL
+ */
+struct pci_emul_uc_priv {
+ struct udevice *client;
+};
+
/**
* struct dm_pci_emul_ops - PCI device emulator operations
*/
@@ -1592,6 +1603,15 @@ struct dm_pci_emul_ops {
int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
struct udevice **containerp, struct udevice **emulp);
+/**
+ * sandbox_pci_get_client() - Find the client for an emulation device
+ *
+ * @emul: Emulation device to check
+ * @devp: Returns the client device emulated by this device
+ * @return 0 if OK, -ENOENT if the device has no client yet
+ */
+int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
+
/**
* pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device
*
--
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[U-Boot] [PATCH 064/126] x86: cpu: Don't include the cpu driver in TPL
We don't need this driver very early in boot and it adds code size. Drop it. Signed-off-by: Simon Glass --- arch/x86/cpu/Makefile | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 3f1f62da2b1..6296b55ff8a 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -26,7 +26,10 @@ endif extra-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += resetvec.o start16.o -obj-y += cpu.o cpu_x86.o +obj-y += cpu.o +ifndef CONFIG_TPL_BUILD +obj-y += cpu_x86.o +endif ifndef CONFIG_$(SPL_)X86_64 AFLAGS_REMOVE_call32.o := -mregparm=3 \ -- 2.23.0.444.g18eeb5a265-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 067/126] x86: Panic when SPL or TPL fail
At present when these fail to boot there is no message, just a hang. Add a
panic so it is obvious that something when wrong.
Signed-off-by: Simon Glass
---
arch/x86/lib/spl.c | 2 +-
arch/x86/lib/tpl.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index db1ce67a590..e1e2d4fa0d5 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -153,7 +153,7 @@ void board_init_f(ulong flags)
ret = x86_spl_init();
if (ret) {
debug("Error %d\n", ret);
- hang();
+ panic("x86_spl_init fail");
}
#ifdef CONFIG_TPL
gd->bd = malloc(sizeof(*gd->bd));
diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c
index cfefa78045e..d70f590541c 100644
--- a/arch/x86/lib/tpl.c
+++ b/arch/x86/lib/tpl.c
@@ -55,7 +55,7 @@ void board_init_f(ulong flags)
ret = x86_tpl_init();
if (ret) {
debug("Error %d\n", ret);
- hang();
+ panic("x86_tpl_init fail");
}
/* Uninit CAR and jump to board_init_f_r() */
--
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[U-Boot] [PATCH 068/126] x86: tpl: Add a fake PCI bus
In TPL we try to minimise code size so do not include the PCI subsystem.
We can use fixed BARs and drivers can directly program the devices that
they need.
However we do need to bind the devices on the PCI bus and without PCI this
does not ordinarily happen. As a work-around, define a fake PCI bus which
does this binding, but no other PCI operations. This is a convenient way
to ensure that we can use the same device tree for TPL, SPL and U-Boot
proper:
TPL- CONFIG_TPL_PCI is not set (manual mode, fake PCI bus)
SPL- CONFIG_SPL_PCI is set (manual mode but with real PCI bus)
U-Boot - CONFIG_PCI is set (full auto-config after relocation)
Signed-off-by: Simon Glass
---
arch/x86/lib/tpl.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c
index d70f590541c..f8075568a2c 100644
--- a/arch/x86/lib/tpl.c
+++ b/arch/x86/lib/tpl.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
#include
@@ -115,3 +116,27 @@ void spl_board_init(void)
{
preloader_console_init();
}
+
+#if !CONFIG_IS_ENABLED(PCI)
+/*
+ * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough
+ * to bind the devices on the PCI bus, some of which have early-regs properties
+ * providing fixed BARs. Individual drivers program these BARs themselves so
+ * that they can access the devices. The BARs are allocated statically in the
+ * device tree.
+ *
+ * Once SPL is running it enables PCI properly, but does not auto-assign BARs
+ * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
+ * the autoallocation (after relocation).
+ */
+static const struct udevice_id tpl_fake_pci_ids[] = {
+ { .compatible = "pci-x86" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_x86) = {
+ .name = "pci_x86",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = tpl_fake_pci_ids,
+};
+#endif
--
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[U-Boot] [PATCH 066/126] x86: spl: Support init of a PUNIT
The x86 power unit handles power management. Support initing this device
which is modelled as a new type of system controller since there are no
operations needed.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/cpu.h | 1 +
arch/x86/lib/spl.c | 40 ++
2 files changed, 41 insertions(+)
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index feee0f915f6..21a05dab7de 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -55,6 +55,7 @@ enum {
X86_SYSCON_PINCONF, /* Intel x86 pin configuration */
X86_SYSCON_PMU, /* Power Management Unit */
X86_SYSCON_SCU, /* System Controller Unit */
+ X86_SYSCON_PUNIT, /* Power unit */
};
struct cpuid_result {
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 2baac913837..db1ce67a590 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -5,11 +5,15 @@
#include
#include
+#include
#include
#include
+#include
#include
+#include
#include
#include
+#include
#include
#include
#include
@@ -21,6 +25,32 @@ __weak int arch_cpu_init_dm(void)
return 0;
}
+#ifdef CONFIG_TPL
+
+static int set_max_freq(void)
+{
+ if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
+ /*
+* Burst Mode has been factory-configured as disabled and is not
+* available in this physical processor package
+*/
+ debug("Burst Mode is factory-disabled\n");
+ return -ENOENT;
+ }
+
+ /* Enable burst mode */
+ cpu_set_burst_mode(true);
+
+ /* Enable speed step */
+ cpu_set_eist(true);
+
+ /* Set P-State ratio */
+ cpu_set_p_state_to_turbo_ratio();
+
+ return 0;
+}
+#endif
+
static int x86_spl_init(void)
{
#ifndef CONFIG_TPL
@@ -31,6 +61,8 @@ static int x86_spl_init(void)
* place it immediately below CONFIG_SYS_TEXT_BASE.
*/
char *ptr = (char *)0x11;
+#else
+ struct udevice *punit;
#endif
int ret;
@@ -101,6 +133,14 @@ static int x86_spl_init(void)
return ret;
}
mtrr_commit(true);
+#else
+ ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
+ if (ret)
+ debug("Could not find PUNIT (err-%d)\n", ret);
+
+ ret = set_max_freq();
+ if (ret)
+ debug("Failed to set CPU frequency (err=%d)\n", ret);
#endif
return 0;
--
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[U-Boot] [PATCH 062/126] x86: Add a function to set variable MTRRs
Normally U-Boot handles MTRRs through an add/commit process which
overwrites all MTRRs. But in very early boot it is not desirable to clear
the existing MTRRs since they may be in use and it can cause a hang.
Add a new mtrr_set_next_var() function which sets up the next available
MTRR to the required region.
Signed-off-by: Simon Glass
---
arch/x86/cpu/mtrr.c | 38 +
arch/x86/include/asm/mtrr.h | 12
2 files changed, 50 insertions(+)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 6218d149e30..1a7c292fa8b 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -112,3 +112,41 @@ int mtrr_add_request(int type, uint64_t start, uint64_t
size)
return 0;
}
+
+static int get_var_mtrr_count(void)
+{
+ return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
+}
+
+static int get_free_var_mtrr(void)
+{
+ struct msr_t maskm;
+ int vcnt;
+ int i;
+
+ vcnt = get_var_mtrr_count();
+
+ /* Identify the first var mtrr which is not valid */
+ for (i = 0; i < vcnt; i++) {
+ maskm = msr_read(MTRR_PHYS_MASK_MSR(i));
+ if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
+ return i;
+ }
+
+ /* No free var mtrr */
+ return -ENOSPC;
+}
+
+int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
+{
+ int mtrr;
+
+ mtrr = get_free_var_mtrr();
+ if (mtrr < 0)
+ return mtrr;
+
+ set_var_mtrr(mtrr, MTRR_TYPE_WRPROT, start, size);
+ debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size);
+
+ return 0;
+}
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 6f29e75ce65..672617256e9 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -117,6 +117,18 @@ int mtrr_add_request(int type, uint64_t start, uint64_t
size);
*/
int mtrr_commit(bool do_caches);
+/**
+ * mtrr_set_next_var() - set up a variable MTRR
+ *
+ * This finds the first free variable MTRR and sets to the given area
+ *
+ * @type: Requested type (MTRR_TYPE_)
+ * @start: Start address
+ * @size: Size
+ * @return 0 on success, -ENOSPC if there are no more MTRRs
+ */
+int mtrr_set_next_var(uint type, uint64_t base, uint64_t size);
+
#endif
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
--
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