Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Bin
>
> Hi Rick,
>
> On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > It will work fine due to hart 0 always will be main
> > hart coincidentally. When develop SPL flow, I try to
> > force other harts to be main hart. And it will go
> > wrong in sending IPI flow. So fix it.
>
> Fix what? Does this commit contain 2 fixes, or just 1 fix?
Yes, it include two fixs. But they will cause one negative result
that only hart 0 can send ipi to other harts.
>
> >
> > Having this fix, any hart can be main hart in U-Boot SPL
> > theoretically, but it still fail somewhere. After dig in
> > and found there is an assumption that hart 0 shall be
> > main hart in OpenSbi.
>
> So does this mean there is a bug in OpenSBI too?
I am not sure if it is a bug. Maybe it is a compatible issue.
There is a limitation that only hart 0 can be main hart in OpenSBI.
But any hart can be main hart in U-Boot.
In general case, hart 0 will be main and it is fine when U-Boot jump ot OpenSBI.
But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI from U-Boot,
It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
but hart 0 still in U-Boot SPL.
>
> >
> > After some work-arounds, it can pass the verifications
> > that any hart can be main hart and boots U-Boot SPL ->
> > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> >
>
> It's a bit hard for me to understand what was described here in the
> commit message. Maybe you need rewrite something.
OK. I will rewrite this commit message.
>
> > Signed-off-by: Rick Chen
> > Cc: KC Lin
> > Cc: Alan Kao
> > ---
> > arch/riscv/lib/andes_plic.c | 11 +++
> > 1 file changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > index 28568e4..42394b9 100644
> > --- a/arch/riscv/lib/andes_plic.c
> > +++ b/arch/riscv/lib/andes_plic.c
> > @@ -19,7 +19,7 @@
> > #include
> >
> > /* pending register */
> > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + (hart) *
> > 8)
> > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + ((hart) /
> > 4) * 4)
> > /* enable register */
> > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > /* claim register */
> > @@ -46,7 +46,7 @@ static int init_plic(void);
> >
> > static int enable_ipi(int hart)
> > {
> > - int en;
> > + unsigned int en;
>
> Is this for some compiler warning fix?
No, it is not a warning fix. It is a bug fix.
I hope en can be 0x80808080 instead of 0x80808080,
or it will cause IPI sending errors.
Thanks
Rick
>
> >
> > en = ENABLE_HART_IPI >> hart;
> > writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
> > @@ -94,10 +94,13 @@ static int init_plic(void)
> >
> > int riscv_send_ipi(int hart)
> > {
> > + unsigned int ipi;
> > +
> > PLIC_BASE_GET();
> >
> > - writel(SEND_IPI_TO_HART(hart),
> > - (void __iomem *)PENDING_REG(gd->arch.plic,
> > gd->arch.boot_hart));
> > + ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
> > + writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
> > + gd->arch.boot_hart));
> >
> > return 0;
> > }
> > --
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 3/8] riscv: ax25-ae350: Use generic memory size setup
Hi Bin Bin Meng 於 2019年10月29日 週二 下午10:42寫道： > > Hi Rick, > > On Fri, Oct 25, 2019 at 2:17 PM Andes wrote: > > > > From: Rick Chen > > > > To get memory size from device tree instead of > > get_ram_size(). This can avoid memory access fault > > Could you please explain a little more about why get_ram_size() causes > PMP access fault? OpenSBI will configure pmpcfg and pmpaddr for memory protection in specific range. When get_ram_size() try to store or load memory address, it will appear access fault exception. Thanks Rick > > > in U-Boot proper after PMP configurations in OpenSbi. > > > > Signed-off-by: Rick Chen > > Cc: KC Lin > > Cc: Alan Kao > > --- > > board/AndesTech/ax25-ae350/ax25-ae350.c | 21 ++--- > > 1 file changed, 2 insertions(+), 19 deletions(-) > > > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/8] riscv: ax25-ae350: add SPL configuration
Hi Bin
> Hi Rick,
>
> On Fri, Oct 25, 2019 at 2:17 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > This patch provides four configurations
> > which can support U-Boot SPL to boot from
> > RAM or FLASH and then boot FIT image
> > including OpenSBI FW_DYNAMIC firmware
> > and U-Boot proper images from RAM or
> > MMC boot devices.
> >
> > With ae350_rv[32|64]_spl_defconfigs:
> >
> > U-Boot SPL will be loaded by gdb or FSBL
> > and runs in RAM in machine mode and then
> > load FIT image from RAM device on AE350.
> >
> > With ae350_rv[32|64]_spl_xip_defconfigs:
> >
> > U-Boot SPL can be burned into SPI flash
> > and run in flash in machine mode and then
> > load FIT image from SPI flash or MMC device
> > on AE350.
> >
>
> Could you please rewrite the commit message so that every line has
> about 70 characters?
OK. I will rewrite it.
>
> > Signed-off-by: Rick Chen
> > Cc: KC Lin
> > Cc: Alan Kao
> > ---
> > board/AndesTech/ax25-ae350/Kconfig | 10 +
> > board/AndesTech/ax25-ae350/MAINTAINERS | 4
> > board/AndesTech/ax25-ae350/ax25-ae350.c | 27 ++
> > configs/ae350_rv32_spl_defconfig| 37 ++
> > configs/ae350_rv32_spl_xip_defconfig| 39
> >
> > configs/ae350_rv64_spl_defconfig| 38
> > +++
> > configs/ae350_rv64_spl_xip_defconfig| 40
> > +
> > include/configs/ax25-ae350.h| 17 ++
> > 8 files changed, 212 insertions(+)
> > create mode 100644 configs/ae350_rv32_spl_defconfig
> > create mode 100644 configs/ae350_rv32_spl_xip_defconfig
> > create mode 100644 configs/ae350_rv64_spl_defconfig
> > create mode 100644 configs/ae350_rv64_spl_xip_defconfig
> >
> > diff --git a/board/AndesTech/ax25-ae350/Kconfig
> > b/board/AndesTech/ax25-ae350/Kconfig
> > index 5e682b6..2e1e2bb 100644
> > --- a/board/AndesTech/ax25-ae350/Kconfig
> > +++ b/board/AndesTech/ax25-ae350/Kconfig
> > @@ -21,9 +21,19 @@ config ENV_SIZE
> > config ENV_OFFSET
> > default 0x14 if ENV_IS_IN_SPI_FLASH
> >
> > +config SPL_TEXT_BASE
> > + default 0x
> > +
> > +config SPL_OPENSBI_LOAD_ADDR
> > + default 0x0100
> > +
> > config BOARD_SPECIFIC_OPTIONS # dummy
> > def_bool y
> > select RISCV_NDS
> > + select SUPPORT_SPL
> > + imply SYS_NS16550
>
> Is there any 16550 on the AX25 boards? If not, please remove. If yes,
> this should be a separate patch with DTS changes.
Yes, it needs SYS_NS16550, but it has been declared in ae350_XXX_defconfig.
It is duplicate declaration here. I will remove it.
>
> > imply SMP
> > + imply SPL_RAM_SUPPORT
> > + imply SPL_RAM_DEVICE
> >
> > endif
> > diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS
> > b/board/AndesTech/ax25-ae350/MAINTAINERS
> > index feed5d1..eebee16 100644
> > --- a/board/AndesTech/ax25-ae350/MAINTAINERS
> > +++ b/board/AndesTech/ax25-ae350/MAINTAINERS
> > @@ -7,3 +7,7 @@ F: configs/ae350_rv32_defconfig
> > F: configs/ae350_rv64_defconfig
> > F: configs/ae350_rv32_xip_defconfig
> > F: configs/ae350_rv64_xip_defconfig
> > +F: configs/ae350_rv32_spl_defconfig
> > +F: configs/ae350_rv64_spl_defconfig
> > +F: configs/ae350_rv32_spl_xip_defconfig
> > +F: configs/ae350_rv64_spl_xip_defconfig
>
> Could you please update the doc/board/AndesTech/ax25-ae350.rst to add
> descriptions about all these different configurations of the same
> board?
OK. I will update doc/board/AndesTech/ax25-ae350.rst.
Thanks
Rick
>
> > diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
> > b/board/AndesTech/ax25-ae350/ax25-ae350.c
> > index b43eebb..b0164a9 100644
> > --- a/board/AndesTech/ax25-ae350/ax25-ae350.c
> > +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
> > @@ -12,6 +12,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -110,3 +111,29 @@ int board_early_init_f(void)
> > return 0;
> > }
> > #endif
> > +
> > +#ifdef CONFIG_SPL
> > +void board_boot_order(u32 *spl_boot_list)
> > +{
> > + u8 i;
> > + u32 boot_devices[] = {
> > +#ifdef CONFIG_SPL_RAM_SUPPORT
> > + BOOT_DEVICE_RAM,
> > +#endif
> > +#ifdef CONFIG_SPL_MMC_SUPPORT
> > + BOOT_DEVICE_MMC1,
> > +#endif
> > + };
> > +
> > + for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
> > + spl_boot_list[i] = boot_devices[i];
> > +}
> > +#endif
> > +
> > +#ifdef CONFIG_SPL_LOAD_FIT
> > +int board_fit_config_name_match(const char *name)
> > +{
> > + /* boot using first FIT config */
> > + return 0;
> > +}
> > +#endif
> > diff --git a/configs/ae350_rv32_spl_defconfig
> > b/configs/ae350_rv32_spl_defconfig
> > new file mode 100644
> > index 000..53055b7
> > --- /dev/null
> > +++ b/configs/ae350_rv32_spl_defconfig
> > @@ -0,0 +1,37 @@
> > +CONFIG_RISCV=y
> > +CONFIG_SPL=y
> >
Re: [U-Boot] [PATCH v2 16/41] i2c: add support for offset overflow in to address
Hi Robert, On Wed, 23 Oct 2019 at 12:22, Robert Beckett wrote: > > Some devices (2 wire eeproms for example) use some bits from the chip > address to represent the high bits of the offset instead of or as well > as using multiple bytes for the offset, effectively stealing chip > addresses on the bus. > > Add a chip offset mask that can be set for any i2c chip which gets > filled with the offset overflow during offset setup. > > Signed-off-by: Robert Beckett > Signed-off-by: Ian Ray > --- > drivers/i2c/i2c-uclass.c | 34 +++--- > include/i2c.h| 33 + > 2 files changed, 60 insertions(+), 7 deletions(-) This is v2 but I don't see a change log? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 3/4] drivers: mux: mmio-based syscon mux controller
On Wed, 2 Oct 2019 at 06:47, Jean-Jacques Hiblot wrote: > > This adds a driver for mmio-based syscon multiplexers controlled by > bitfields in a syscon register range. > This is heavily based on the linux mmio-mux driver. > > Signed-off-by: Jean-Jacques Hiblot > --- > > drivers/mux/Kconfig | 15 + > drivers/mux/Makefile | 1 + > drivers/mux/mmio.c | 155 +++ > 3 files changed, 171 insertions(+) > create mode 100644 drivers/mux/mmio.c Reviewed-by: Simon Glass So much memory allocation! But I suppose it is unavoidable. No way to use DM's auto-alloc? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2 2/4] aes: add support of aes192 and aes256
On Tue, 29 Oct 2019 at 11:29, Philippe Reynes wrote: > > Until now, we only support aes128. This commit add the support > of aes192 and aes256. > > Signed-off-by: Philippe Reynes > --- > cmd/aes.c | 38 +- > include/uboot_aes.h | 34 +++ > lib/aes.c | 77 > + > 3 files changed, 103 insertions(+), 46 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [EXTERNAL] Re: Need help with verified u-boot on Tegra TX2
Hi Rayees, On Wed, 23 Oct 2019 at 18:51, Rayees Shamsuddin wrote: > > Hi Simon, > > I got the ramdisk loading problem sorted out by modifying values of > initrd_high and fdt_high > setenv initrd_high 82F4EFFF; setenv fdt_high 824F > > This resulted in: >ramdisk load start = 0x82a0, ramdisk load end = 0x82f4eaa2 > ## device tree at 920989cc ... 920ec99e (len=356307 [0x56FD3]) >Loading Device Tree to 824a9000, end 824fffd2 ... OK > > Thanks for all your guidance and pointers. OK that's great! Hopefully vboot is doing the right thing now... Regards, SImon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/4] dm: board: complete the initialization of the muxes in initr_dm()
Hi Jean-Jacques, On Wed, 2 Oct 2019 at 06:47, Jean-Jacques Hiblot wrote: > > This will probe the multiplexer devices that have a "u-boot,mux-autoprobe" > property. As a consequence they will be put in their idle state. > > Signed-off-by: Jean-Jacques Hiblot > --- > > common/board_r.c | 2 ++ > 1 file changed, 2 insertions(+) I worry this should happen later, or lazily, since at present we don't actually probe any devices at this point, right? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 5/5] test: clk: test clock self assignment
On Mon, 30 Sep 2019 at 06:29, Jean-Jacques Hiblot wrote: > > Make sure that the clock self-assignment works by having a clock of > clk-sbox be configured automatically when clk-sbox is probed. > > Signed-off-by: Jean-Jacques Hiblot > > --- > > arch/sandbox/dts/test.dts | 2 ++ > drivers/clk/clk_sandbox.c | 22 ++ > test/dm/clk.c | 4 ++-- > 3 files changed, 26 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 4/5] drivers: clk: Fix using assigned-clocks in the node of the clock it sets up
Hi Jean-Jacques,
On Mon, 30 Sep 2019 at 06:29, Jean-Jacques Hiblot wrote:
>
> This fixes the case where assigned-clocks is used to define a clock
> defaults inside this same clock's node. This is used sometimes to setup a
> default parents and/or rate for a clock.
>
> example:
> muxed_clock: muxed_clock {
> clocks = <_provider 0>, <_provider 1>;
> #clock-cells = <0>;
> assigned-clocks = <_clock>;
> assigned-clock-parents = <_provider 1>;
> };
>
> It doesn't work in u-boot because the assigned-clocks are setup *before*
U-Boot
> the clock is probed. (clk_set_parent() will likely crash or fail if called
> before the device probe function)
> Making it work by handling "assigned-clocks" in 2 steps: first before the
> clk device is probed, and then after the clk device is probed.
>
> Signed-off-by: Jean-Jacques Hiblot
> ---
>
> drivers/clk/clk-uclass.c | 48 +++-
> drivers/core/device.c| 2 +-
> include/clk.h| 7 --
> 3 files changed, 48 insertions(+), 9 deletions(-)
Reviewed-by: Simon Glass
+Stephen Warren who is the expert here
>
> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> index e7ec6347de..75d618a47b 100644
> --- a/drivers/clk/clk-uclass.c
> +++ b/drivers/clk/clk-uclass.c
> @@ -178,7 +178,7 @@ bulk_get_err:
> return ret;
> }
>
> -static int clk_set_default_parents(struct udevice *dev)
> +static int clk_set_default_parents(struct udevice *dev, int stage)
> {
> struct clk clk, parent_clk;
> int index;
> @@ -214,8 +214,18 @@ static int clk_set_default_parents(struct udevice *dev)
> return ret;
> }
>
> - ret = clk_set_parent(, _clk);
> + /* This is clk provider device trying to reparent itself
/*
* This ...
> +* It cannot be done right now but need to wait after the
> +* device is probed
> +*/
> + if (stage == 0 && clk.dev == dev)
> + continue;
> +
> + if (stage > 0 && clk.dev != dev)
> + /* do not setup twice the parent clocks */
> + continue;
>
> + ret = clk_set_parent(, _clk);
> /*
> * Not all drivers may support clock-reparenting (as of now).
> * Ignore errors due to this.
> @@ -233,7 +243,7 @@ static int clk_set_default_parents(struct udevice *dev)
> return 0;
> }
>
> -static int clk_set_default_rates(struct udevice *dev)
> +static int clk_set_default_rates(struct udevice *dev, int stage)
> {
> struct clk clk;
> int index;
> @@ -268,7 +278,19 @@ static int clk_set_default_rates(struct udevice *dev)
> continue;
> }
>
> + /* This is clk provider device trying to program itself
> +* It cannot be done right now but need to wait after the
> +* device is probed
> +*/
wait until after?
Regards,
Simon
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Re: [U-Boot] [PATCH v1 1/3] drivers: reset: Handle gracefully NULL pointers
Hi Jean-Jacques, On Mon, 30 Sep 2019 at 08:31, Jean-Jacques Hiblot wrote: > > Prepare the way for a managed reset API by handling NULL pointers without > crashing nor failing. > > Signed-off-by: Jean-Jacques Hiblot > --- > > drivers/reset/reset-uclass.c | 30 +- > 1 file changed, 17 insertions(+), 13 deletions(-) Same comment here about code size / Kconfig option. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] sandbox: use correct type reading /proc/self/maps
On Sat, 26 Oct 2019 at 15:17, Heinrich Schuchardt wrote: > > Compiling arch/sandbox/cpu/os.c results in an error > > ../arch/sandbox/cpu/os.c: In function ‘os_find_text_base’: > ../arch/sandbox/cpu/os.c:823:12: error: cast to pointer from > integer of different size [-Werror=int-to-pointer-cast] > 823 | base = (void *)addr; > |^ > cc1: all warnings being treated as errors > > The size of void* differs from that of unsigned long long on 32bit > systems. > > Signed-off-by: Heinrich Schuchardt > --- > arch/sandbox/cpu/os.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/4] drivers: Add a new framework for multiplexer devices
Hi Jean-Jacques,
On Wed, 2 Oct 2019 at 06:47, Jean-Jacques Hiblot wrote:
>
> Add a new subsystem that handles multiplexer controllers. The API is the
> same as in Linux.
>
> Signed-off-by: Jean-Jacques Hiblot
> ---
>
> drivers/Kconfig | 2 +
> drivers/Makefile | 1 +
> drivers/mux/Kconfig | 7 +
> drivers/mux/Makefile | 6 +
> drivers/mux/mux-uclass.c | 296 ++
> include/dm/uclass-id.h| 1 +
> include/dt-bindings/mux/mux.h | 17 ++
> include/mux-internal.h| 80 +
> include/mux.h | 114 +
> 9 files changed, 524 insertions(+)
> create mode 100644 drivers/mux/Kconfig
> create mode 100644 drivers/mux/Makefile
> create mode 100644 drivers/mux/mux-uclass.c
> create mode 100644 include/dt-bindings/mux/mux.h
> create mode 100644 include/mux-internal.h
> create mode 100644 include/mux.h
>
I feel this needs more documentation. What is a multiplexer?
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index 350acf81f3..5334974ad4 100644
> --- a/drivers/Kconfig
> +++ b/drivers/Kconfig
> @@ -60,6 +60,8 @@ source "drivers/mmc/Kconfig"
>
> source "drivers/mtd/Kconfig"
>
> +source "drivers/mux/Kconfig"
> +
> source "drivers/net/Kconfig"
>
> source "drivers/nvme/Kconfig"
> diff --git a/drivers/Makefile b/drivers/Makefile
> index a4bb5e4975..f4d71f3b3c 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/
> obj-$(CONFIG_$(SPL_TPL_)LED) += led/
> obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/
> obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += mtd/nand/raw/
> +obj-$(CONFIG_$(SPl_)MULTIPLEXER) += mux/
SPL?
> obj-$(CONFIG_$(SPL_TPL_)PCH_SUPPORT) += pch/
> obj-$(CONFIG_$(SPL_TPL_)PCI) += pci/
> obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/
> diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig
> new file mode 100644
> index 00..ad0199c058
> --- /dev/null
> +++ b/drivers/mux/Kconfig
> @@ -0,0 +1,7 @@
> +menu "Multiplexer drivers"
> +
> +config MULTIPLEXER
> + bool "Multiplexer Support"
> + depends on DM
> +
> +endmenu
> diff --git a/drivers/mux/Makefile b/drivers/mux/Makefile
> new file mode 100644
> index 00..351e4363d3
> --- /dev/null
> +++ b/drivers/mux/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# (C) Copyright 2019
> +# Jean-Jacques Hiblot
> +
> +obj-$(CONFIG_$(SPL_)MULTIPLEXER) += mux-uclass.o
> diff --git a/drivers/mux/mux-uclass.c b/drivers/mux/mux-uclass.c
> new file mode 100644
> index 00..58998af29c
> --- /dev/null
> +++ b/drivers/mux/mux-uclass.c
> @@ -0,0 +1,296 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Multiplexer subsystem
> + *
> + * Based on the linux multiplexer framework
> + *
> + * Copyright (C) 2017 Axentia Technologies AB
> + * Author: Peter Rosin
> + *
> + * Copyright (C) 2017-2018 Texas Instruments Incorporated -
> http://www.ti.com/
> + * Jean-Jacques Hiblot
> + */
> +
> +#include
> +#include
should go above the dm/device-internal
> +#include
> +#include
Shouldn't need this
> +#include
Shouldn't need this
> +#include
> +#include
> +#include
Shouldn't need this
> +#include
> +
> +/*
> + * The idle-as-is "state" is not an actual state that may be selected, it
> + * only implies that the state should not be changed. So, use that state
> + * as indication that the cached state of the multiplexer is unknown.
> + */
> +#define MUX_CACHE_UNKNOWN MUX_IDLE_AS_IS
> +
> +static inline const struct mux_control_ops *mux_dev_ops(struct udevice *dev)
> +{
> + return (const struct mux_control_ops *)dev->driver->ops;
> +}
> +
> +static int mux_control_set(struct mux_control *mux, int state)
> +{
> + int ret = mux_dev_ops(mux->dev)->set(mux, state);
> +
> + mux->cached_state = ret < 0 ? MUX_CACHE_UNKNOWN : state;
> +
> + return ret;
> +}
> +
> +unsigned int mux_control_states(struct mux_control *mux)
> +{
> + return mux->states;
> +}
> +
> +static int __mux_control_select(struct mux_control *mux, int state)
> +{
> + int ret;
> +
> + if (WARN_ON(state < 0 || state >= mux->states))
> + return -EINVAL;
> +
> + if (mux->cached_state == state)
> + return 0;
> +
> + ret = mux_control_set(mux, state);
> + if (ret >= 0)
> + return 0;
> +
> + /* The mux update failed, try to revert if appropriate... */
> + if (mux->idle_state != MUX_IDLE_AS_IS)
> + mux_control_set(mux, mux->idle_state);
> +
> + return ret;
> +}
> +
> +int mux_control_select(struct mux_control *mux, unsigned int state)
> +{
> + int ret;
> +
> + if (mux->in_use)
> + return -EBUSY;
> +
> + ret = __mux_control_select(mux, state);
> +
> + if (ret < 0)
> + return ret;
> +
> + mux->in_use = true;
> +
> + return 0;
> +}
> +
> +int mux_control_deselect(struct mux_control
Re: [U-Boot] [PATCH v2 1/2] rockchip: make_fit_atf.py: allow inclusion of a tee binary
Hi Kever, On Tue, 22 Oct 2019 at 03:45, Kever Yang wrote: > > Add Jagan. > > Hi Simon, > > > On 2019/10/22 上午7:46, Simon Glass wrote: > > Hi, > > > > On Mon, 14 Oct 2019 at 03:07, Kever Yang wrote: > >> > >> On 2019/10/7 上午2:10, Heiko Stuebner wrote: > >>> A trusted execution environment should also get loaded as loadable from > >>> a fit image, so add the possibility to present a tee.elf to > >>> make_fit_atf.py > >>> that then gets included as additional loadable into the generated its. > >>> > >>> For ease of integration the additional loadable is created as atf_(x+1) > >>> after all others to re-use core generation loops. > >>> > >>> Tested against the combinations of 1-part-atf and multi-part-atf each > >>> time with and without a tee binary present. > >>> > >>> Signed-off-by: Heiko Stuebner > >> Reviewed-by: Kever Yang > >> > >> > >> Thanks, > >> - Kever > >>> --- > >>> changes in v2: none > >>> > >>>arch/arm/mach-rockchip/make_fit_atf.py | 52 +++--- > >>>1 file changed, 46 insertions(+), 6 deletions(-) > > I see there is an effort to move this to binman. To me that is a much > > more productive approach! > > > Do you mean the patch set from Jagan for rockchip platform to using binman? > > That patch is actually using the output of the u-boot.itb which is based > on this script. > > > > > Is there a feature or example missing in binman that you need to get > > this over the hump? > > > I think Heiko and you has a discussion about this in previous version > thread. > The U-Boot project build output is: tpl.bin, spl.bin, u-boot.bin > For rockchip platform, package needs: > - pack tpl.bin+spl.bin with mkimage -rksd/rkspi into idbloader.img > - get ATF binaries from bl31.bin/optee.bin with a script > - generate u-boot.its to describe the u-boot.itb > - pack u-boot.bin and ATF/OPTEE binaries into u-boot.itb with mkimage -f > u-boot.its > > Does the binman mainly target for pack the idbloader.img+u-boot.itb? I actually think binman could handle all of that. Is there something I could do that would help with that? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] tpm / measured boot in u-boot
Hi Stuart, On Mon, 28 Oct 2019 at 17:27, Stuart Yoder wrote: > > I saw Simon's write-up here: https://lwn.net/Articles/571031/, which > references TPM > and trusted boot support using the TPM. > > I've started looking at the TPM support code in u-boot, and am trying > to understand > it. Before getting too far I wanted to check if there were any > pointers anyone might > have around any documentation or material that provides more detail on what > the > u-boot TPM support does and does not do. I didn't see any .txt files in > u-boot. > > The supports seems oriented around using commands and scripts to > measure images. One > specific thing I'm interested is how the u-boot script itself that takes the > TPM > measurements is protected against tampering. Actually verified boot does not use the TPM at all. What do you want the TPM to do? If you want measured boot then you would need to call measure / extend before/after loading each stage. > > Also, it doesn't look like TCG compliant event logs are supported. OK, might need to be added. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2 3/4] tegra20: crypto: update code to use new aes api
On Tue, 29 Oct 2019 at 11:29, Philippe Reynes wrote: > > This commit update tge driver crypto for tegra20 > to use the new aes api. > > Signed-off-by: Philippe Reynes > --- > arch/arm/mach-tegra/tegra20/crypto.c | 41 > +++- > 1 file changed, 22 insertions(+), 19 deletions(-) Reviewed-by: Simon Glass > > Changelog: > v2: > - add a really simple commit text ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2 4/4] pytest: aes: add test for aes192 and aes256
Hi Philippe, On Tue, 29 Oct 2019 at 11:29, Philippe Reynes wrote: > > This commit update the aes tests to check the > aes192 and aes256. > > Signed-off-by: Philippe Reynes > --- > test/py/tests/test_aes.py | 118 > +++--- > 1 file changed, 91 insertions(+), 27 deletions(-) Any way we could write these tests in C? > > Changelog: > v2: > - add a really simple commit text > - re-write the test with the new version of test for aes128 > - add a test to check that results of aes128/192/256 are differents Regards, SImon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] remoteproc: elf_loader: Add elf resource table load support
Hi Fabien, On Tue, 22 Oct 2019 at 03:08, Fabien DESSENNE wrote: > > Hi Simon, > > > On 22/10/2019 1:47 AM, Simon Glass wrote: > > Hi Fabien, > > > > On Wed, 9 Oct 2019 at 09:36, Fabien Dessenne wrote: > >> Add rproc_elf_load_rsc_table(), which searches for a resource table in > >> an elf64/elf32 image, and if found, copies it to device memory. > >> Add also the elf32 and elf64 variants of this API. > >> Add a test for this. > >> > >> Signed-off-by: Fabien Dessenne > >> --- > >> drivers/remoteproc/rproc-elf-loader.c | 269 > >> ++ > >> include/remoteproc.h | 70 + > >> test/dm/remoteproc.c | 91 ++-- > >> 3 files changed, 419 insertions(+), 11 deletions(-) > >> > > If you are putting stuff in the image, should you use binman to build > > the image, then find the contents using the binman tables? > > > The "resource table" may be located anywhere, there is no strict rule > defining where it is expected to be. > > Nevertheless the Linux remoteproc[1] and OpenAmp (running RTOS) [2] > frameworks expect the resource table to be stored in a dedicated ELF > section. Both of them run some ELF scanning to find out this section. > > The proposed patch is for the "ELF section" variant of the resource table. > Other variants like binman packing may be proposed as well, both > implementations can coexist alongside. So why not use binman to pack the image and find the components? This is U-Boot, after all. > > BR > > Fabien > > [1] https://www.kernel.org/doc/Documentation/remoteproc.txt > [2] > https://github.com/OpenAMP/open-amp/blob/master/lib/remoteproc/elf_loader.c > > > > > Scanning the image for a table seems a bit horrible. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] test/py: hush_if_test: Add tests to cover octal/hex values
Hi Michal, On Thu, 24 Oct 2019 at 00:51, Michal Simek wrote: > > On 22. 10. 19 17:54, Stephen Warren wrote: > > On 10/21/19 5:46 PM, Simon Glass wrote: > >> Hi Stephen, > >> > >> On Mon, 21 Oct 2019 at 17:04, Stephen Warren > >> wrote: > >>> > >>> On 10/21/19 4:53 PM, Simon Glass wrote: > Hi Michal, > > On Tue, 15 Oct 2019 at 00:09, Michal Simek > wrote: > > > > Hi Simon, > > > > On 11. 10. 19 17:53, Simon Glass wrote: > >> Hi Michal, > >> > >> On Fri, 11 Oct 2019 at 01:50, Michal Simek > >> wrote: > >>> > >>> On 10. 10. 19 19:06, Simon Glass wrote: > Hi Michal, > > On Thu, 10 Oct 2019 at 05:44, Michal Simek > wrote: > > > > Extend test suite to cover also automatic octal/hex > > converstions which > > haven't been implemented in past. > > > > Signed-off-by: Michal Simek > > --- > > > > Depends on > > https://lists.denx.de/pipermail/u-boot/2019-September/383309.html > > > > There are of course other tests which we can run but not sure > > if make sense > > to have there all combinations. The most interesting are mixed > > tests which > > are failing before patch above is applied. > > Definitely please let me know if you want to add any other test. > > --- > >test/py/tests/test_hush_if_test.py | 27 > > +++ > >1 file changed, 27 insertions(+) > > > > I worry that these tests might be very slow since it requires a > lot of > interaction with U-Boot over a pipe. Is it possible to put them > in C > code instead, e.g. cmd_ut? > >>> > >>> I have of course running it on my HW and it is quite fast. It is > >>> just 16 > >>> more simple tests. And if this breaks gitlab/travis CI loops then we > >>> have bigger problem. > >> > >> I mean running these tests on sandbox. The interactions with the > >> sandbox command line are quite slow I think. > > > > > > I am not sharing this concern. > > > > Before: > > [u-boot]$ time ./test/py/test.py --bd sandbox -s -k hush >/dev/null > > > > real0m2,403s > > user0m1,263s > > sys 0m0,299s > > > > After > > [u-boot]$ time ./test/py/test.py --bd sandbox -s -k hush >/dev/null > > > > real0m2,864s > > user0m1,563s > > sys 0m0,305s > > > > And if 0.4s on testing will cause issues somewhere else we have > > different kind of problem. > > +Stephen Warren > > I originally mentioned this concern to Stephen we the test setup was > created. At present even 'make qcheck' takes over a minute. Adding > half a second to this every time we add a new test is not going to > lead to a good place. > > Stephen made some improvements to speed things up, and suggested that > the problem would not bear out. The alternative was presumably to > build U-Boot into a Python module to avoid the comms overhead. But we > didn't go that path. > > So I think we should only use Python when the tests cannot be > written in C. > >>> > >>> I don't really see any concern with the addition of a couple extra > >>> seconds of test. Clearly I'd rather see the test written in Python and > >>> using external interfaces (i.e. the shell) where they test features > >>> accessible through those interfaces, since that allows them to be > >>> validated on all platforms, rather than only in sandbox. I feel that > >> > >> But cmd_ut.c works fine on non-sandbox platforms. I'm asking that we > >> do the same approach here. > >> > >> We can use run_command() and run_command_list() > > > > In that case, I'd agree it's fine to use that approach since presumably > > those functions run through the standard shell parsing code. But I still > > wouldn't want to prevent anyone from invoking stuff from test/py myself, > > even if you might:-) > > Ok. Would be good to get any outcome of this discussion regarding this > one patch. Right now this is what I have and I have tested it. The patch > which adds this functionality is already in the tree. > > I expect that the same logic can be applied to all tests in this file > that's why I think that would be the best to add TODO to this file to > let everybody know what should happen with these tests and how it should > be converted. Yes please add a TODO, but I don't want to add more tests here for someone to convert! I just timed it - 2.5 seconds to run the hush tests, 22 seconds to run the whole test suite - so these tests take 10% of the time! As you mention they run instantly when done in C. I run these tests a lot - the total time for 'make qcheck' is about 75s for me and I run it a lot, so am actively looking to reduce this
Re: [U-Boot] [PATCH v1 1/5] regmap: Fix potential overflow in regmap_update_bits()
On Fri, 27 Sep 2019 at 07:22, Jean-Jacques Hiblot wrote: > > Mask the value to write so that it cannot affect the bits outside of the > mask > > Signed-off-by: Jean-Jacques Hiblot > --- > > drivers/core/regmap.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass It would be encouraging to see a test updated to catch this problem. Hmmm actually I just remembered I fixed this - see u-boot-dm/master Sorry, it looks like your patch was first, but mine does add a test :-) > > diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c > index d1d12eef38..e9e55c9d16 100644 > --- a/drivers/core/regmap.c > +++ b/drivers/core/regmap.c > @@ -462,5 +462,5 @@ int regmap_update_bits(struct regmap *map, uint offset, > uint mask, uint val) > > reg &= ~mask; > > - return regmap_write(map, offset, reg | val); > + return regmap_write(map, offset, reg | (val & mask)); > } > -- > 2.17.1 > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] patman: fix some typos in comments
On Sun, 27 Oct 2019 at 10:55, Anatolij Gustschin wrote: > > s/Subprocress/Subprocess/ > s/easiler/easier/ > s/repositiory/repository/ > s/rangem/range/ > s/Retruns/Returns/ > > Signed-off-by: Anatolij Gustschin > --- > tools/patman/cros_subprocess.py | 4 ++-- > tools/patman/gitutil.py | 4 ++-- > tools/patman/terminal.py| 2 +- > 3 files changed, 5 insertions(+), 5 deletions(-) > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/3] drivers: reset: Add a managed API to get reset controllers from the DT
On Mon, 30 Sep 2019 at 10:15, Jean-Jacques Hiblot wrote: > > Add managed functions to get a reset_ctl from the device-tree, based on a > name or an index. > Also add a managed functions to get a reset_ctl_bulk (array of reset_ctl) > from the device-tree. > > When the device is unbound, the reset controllers are automatically > released and the data structure is freed. > > Signed-off-by: Jean-Jacques Hiblot > --- > > drivers/reset/reset-uclass.c | 116 +- > include/reset.h | 135 ++- > 2 files changed, 247 insertions(+), 4 deletions(-) Reviewed-by: Simon Glass I really don't like these ERR_PTR returns. I suppose they make the code easier to port, and we can be sure that pointers will not be in the last 4KB of address space? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 3/5] test: clk: Update tests to also check the managed API
On Mon, 30 Sep 2019 at 06:29, Jean-Jacques Hiblot wrote: > > Add a few more clocks the clk_sandbox clock provider and get them using > the managed API. > Make sure they are released when the device is removed. > > Signed-off-by: Jean-Jacques Hiblot > --- > > arch/sandbox/dts/test.dts | 6 ++-- > arch/sandbox/include/asm/clk.h | 33 + > drivers/clk/clk_sandbox.c | 34 ++ > drivers/clk/clk_sandbox_test.c | 66 +- > test/dm/clk.c | 36 ++- > 5 files changed, 163 insertions(+), 12 deletions(-) +Stephen Warren Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/4] fdtdec: only create phandle if caller wants it in fdtdec_add_reserved_memory()
On Tue, 22 Oct 2019 at 13:04, Heiko Stuebner wrote: > > From: Heiko Stuebner > > The phandlep pointer returning the phandle to the caller is optional > and if it is not set when calling fdtdec_add_reserved_memory() it is > highly likely that the caller is not interested in a phandle to the > created reserved-memory area and really just wants that area added. > > So just don't create a phandle in that case. > > Signed-off-by: Heiko Stuebner > --- > changes in v2: > - update function comment > > include/fdtdec.h | 2 +- > lib/fdtdec.c | 16 +--- > 2 files changed, 10 insertions(+), 8 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 5/5] test: dm: Add tests for regmap managed API and regmap fields
On Fri, 27 Sep 2019 at 07:22, Jean-Jacques Hiblot wrote: > > The tests rely on a dummy driver to allocate and initialize the regmap > and the regmap fields using the managed API. > The first test checks that the read/write callbacks are used. > The second test checks if regmap fields behave properly (mask and shift > are ok) by peeking into the regmap. > > Signed-off-by: Jean-Jacques Hiblot > > --- > > arch/sandbox/dts/test.dts | 13 +++ > test/dm/regmap.c | 189 ++ > 2 files changed, 202 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/5] drivers: clk: Add a managed API to get clocks from the device-tree
On Mon, 30 Sep 2019 at 06:29, Jean-Jacques Hiblot wrote: > > Add devm_clk_get(), devm_clk_get_optional() to get clocks from the > device-tree. The clocks is automatically released and the data structure > freed when the device is unbound. > Also add devm_clk_put() to release the clock and free the data structure > manually. > > Signed-off-by: Jean-Jacques Hiblot > --- > > drivers/clk/clk-uclass.c | 48 > include/clk.h| 44 > 2 files changed, 92 insertions(+) Reviewed-by: Simon Glass +Stephen Warren ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 03/13] dm: core: add ofnode function to iterate on node property
On Wed, 23 Oct 2019 at 07:45, Patrick Delaunay wrote:
>
> Add functions to iterate on all property with livetree
> - ofnode_get_first_property
> - ofnode_get_next_property
> - ofnode_get_property_by_prop
>
> For example:
> for (prop = ofnode_get_first_property(dev_ofnode(dev));
> prop;
> prop = ofnode_get_next_property(dev_ofnode(dev),prop))
> {
> value = ofnode_get_property_by_prop(dev_ofnode(dev), prop,
> , );
>
> }
>
> Signed-off-by: Patrick Delaunay
> ---
>
> drivers/core/of_access.c | 32
> drivers/core/ofnode.c| 45
> include/dm/of_access.h | 40 +++
> include/dm/ofnode.h | 39 +-
> 4 files changed, 155 insertions(+), 1 deletion(-)
Please can you add the dev_read() interface too? Also need to support
CONFIG_DM_DEV_READ_INLINE in read.h
[..]
> diff --git a/include/dm/of_access.h b/include/dm/of_access.h
> index 13fedb7cf5..0418782aa2 100644
> --- a/include/dm/of_access.h
> +++ b/include/dm/of_access.h
> @@ -103,6 +103,46 @@ struct property *of_find_property(const struct
> device_node *np,
> const void *of_get_property(const struct device_node *np, const char *name,
> int *lenp);
>
> +/**
> + * of_get_first_property()- get to the pointer of the first property
> + *
> + * Get pointer to the first property of the node, it is used to iterate
> + * and read all the property with of_get_next_property_by_prop().
> + *
> + * @p: Pointer to device node
np
> + * @return pointer to property or NULL if not found
> + */
> +const struct property *of_get_first_property(const struct device_node *np);
> +
> +/**
> + * of_get_next_property() - get to the pointer of the next property
> + *
> + * Get pointer to the next property of the node, it is used to iterate
> + * and read all the property with of_get_property_by_prop().
> + *
> + * @p: Pointer to device node
np
> + * @property: pointer of the current property
> + * @return pointer to next property or NULL if not found
> + */
> +const struct property *of_get_next_property(const struct device_node *np,
> + const struct property *property);
> +
> +/**
> + * of_get_property_by_prop() - get a property value of a node property
> + *
> + * Get value for the property identified by node and property pointer.
> + *
> + * @node: node to read
> + * @property: pointer of the property to read
> + * @propname: place to property name on success
This can be NULL so please document that
> + * @lenp: place to put length on success
This can be NULL so please document that
> + * @return pointer to property value or NULL if error
> + */
> +const void *of_get_property_by_prop(const struct device_node *np,
> + const struct property *property,
> + const char **name,
> + int *lenp);
> +
> /**
> * of_device_is_compatible() - Check if the node matches given constraints
> * @device: pointer to node
> diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
> index 5c4cbf0998..08d684cea0 100644
> --- a/include/dm/ofnode.h
> +++ b/include/dm/ofnode.h
> @@ -543,7 +543,7 @@ int ofnode_decode_display_timing(ofnode node, int index,
> struct display_timing *config);
>
> /**
> - * ofnode_get_property()- - get a pointer to the value of a node property
> + * ofnode_get_property() - get a pointer to the value of a node property
> *
> * @node: node to read
> * @propname: property to read
> @@ -552,6 +552,43 @@ int ofnode_decode_display_timing(ofnode node, int index,
> */
> const void *ofnode_get_property(ofnode node, const char *propname, int
> *lenp);
>
> +/**
> + * ofnode_get_first_property()- get to the pointer of the first property
> + *
> + * Get pointer to the first property of the node, it is used to iterate
> + * and read all the property with ofnode_get_property_by_prop().
> + *
> + * @node: node to read
> + * @return pointer or offset to property, used to iterate, or NULL
> + */
> +const void *ofnode_get_first_property(ofnode node);
> +
> +/**
> + * ofnode_get_next_property() - get to the pointer of the next property
> + *
> + * Get pointer to the next property of the node, it is used to iterate
> + * and read all the property with ofnode_get_property_by_prop().
> + *
> + * @node: node to read
> + * @property: pointer or offset of the current property
> + * @return pointer or offset to next property or NULL
> + */
> +const void *ofnode_get_next_property(ofnode node, const void *property);
> +
> +/**
> + * ofnode_get_property_by_prop() - get a pointer to the value of a node
> property
> + *
> + * Get value for the property identified by node and property.
> + *
> + * @node: node to read
> + * @property: pointer or offset of the property to read
Perhaps you
Re: [U-Boot] [PATCH v1 2/5] regmap: Add devm_regmap_init()
Hi Jean-Jacques,
On Fri, 27 Sep 2019 at 07:22, Jean-Jacques Hiblot wrote:
>
> Most of new linux drivers are using managed-API to allocate resources. To
> ease porting drivers from linux to u-boot, introduce devm_regmap_init() as
U-Boot
Please always spell it that way.
> a managed API to get a regmap from the device tree.
>
> Signed-off-by: Jean-Jacques Hiblot
> ---
>
> drivers/core/regmap.c | 26 ++
> include/regmap.h | 19 +++
> 2 files changed, 45 insertions(+)
Reviewed-by: Simon Glass
Nit below
>
> diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
> index e9e55c9d16..f69ff6d12f 100644
> --- a/drivers/core/regmap.c
> +++ b/drivers/core/regmap.c
> @@ -219,6 +219,32 @@ int regmap_init_mem(ofnode node, struct regmap **mapp)
>
> return 0;
> }
> +
> +static void devm_regmap_release(struct udevice *dev, void *res)
> +{
> + regmap_uninit(*(struct regmap **)res);
> +}
> +
> +struct regmap *devm_regmap_init(struct udevice *dev,
> + const struct regmap_bus *bus,
> + void *bus_context,
> + const struct regmap_config *config)
> +{
> + int rc;
> + struct regmap **mapp;
> +
> + mapp = devres_alloc(devm_regmap_release, sizeof(struct regmap *),
> + __GFP_ZERO);
> + if (unlikely(!mapp))
> + return ERR_PTR(-ENOMEM);
> +
> + rc = regmap_init_mem(dev_ofnode(dev), mapp);
> + if (rc)
> + return ERR_PTR(rc);
> +
> + devres_add(dev, mapp);
> + return *mapp;
> +}
> #endif
>
> void *regmap_get_range(struct regmap *map, unsigned int range_num)
> diff --git a/include/regmap.h b/include/regmap.h
> index 0854200a9c..63a362d86d 100644
> --- a/include/regmap.h
> +++ b/include/regmap.h
> @@ -73,6 +73,9 @@ struct regmap_range {
> ulong size;
> };
>
> +struct regmap_bus;
> +struct regmap_config;
> +
> /**
> * struct regmap - a way of accessing hardware/bus registers
> *
> @@ -332,6 +335,22 @@ int regmap_init_mem_platdata(struct udevice *dev,
> fdt_val_t *reg, int count,
>
> int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index);
>
> +/**
> + * devm_regmap_init() - Initialise register map (device managed)
> + *
> + * @dev: Device that will be interacted with
> + * @bus: Bus-specific callbacks to use with device (IGNORED)
> + * @bus_context: Data passed to bus-specific callbacks (IGNORED)
> + * @config: Configuration for register map (IGNORED)
> + *
@return
> + * The return value will be an ERR_PTR() on error or a valid pointer to
> + * a struct regmap.
> + * The structure is automatically freed when the device is unbound
> + */
> +struct regmap *devm_regmap_init(struct udevice *dev,
> + const struct regmap_bus *bus,
> + void *bus_context,
> + const struct regmap_config *config);
> /**
> * regmap_get_range() - Obtain the base memory address of a regmap range
> *
> --
> 2.17.1
>
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Re: [U-Boot] [PATCH v1 2/3] lib: rsa: generate additional parameters for public key
Hi AKASHI, > > > > > > > > There is precedent for this. It's just that I'm not sure the code is > > > > complicated enough to worry about keeping the comment-free > > > > single-char-variable style? > > > > > > > > +Tom Rini I assume you are OK with this? > > > > > > When we import code from another project that we expect to re-sync we do > > > what we need to do to keep the overall re-sync pain down, even we we > > > otherwise may disagree on style points. > > > > OK ta. > > Thank you for your understanding. > Yes, this patch is small but if I had to modify my "import x509/pkcs7 > parsers from linux" patch, it would be quite painful. Reviewed-by: Simon Glass > > -Takahiro Akashi > > > > Regards, > > Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 4/4] tests: add OP-TEE test suite
On Tue, 22 Oct 2019 at 13:04, Heiko Stuebner wrote: > > From: Heiko Stuebner > > OP-TEE can get supplied with a devicetree and will then insert > its firmware node and reserved-memory sections into it. > As this devicetree often is not the one supplied to a later > loaded kernel, a previous commit added functionality to transfer > these nodes onto that new devicetree. > > To make sure this functionality stays intact, also add a test > for the transfer functionality. > > Signed-off-by: Heiko Stuebner > --- > Makefile | 1 + > include/test/optee.h | 14 +++ > include/test/suites.h | 1 + > test/Kconfig | 1 + > test/cmd_ut.c | 6 ++ > test/optee/Kconfig | 7 ++ > test/optee/Makefile| 13 +++ > test/optee/cmd_ut_optee.c | 143 + > test/optee/test-optee-base.dts | 13 +++ > test/optee/test-optee-no-optee.dts | 13 +++ > test/optee/test-optee-optee.dts| 32 +++ > 11 files changed, 244 insertions(+) > create mode 100644 include/test/optee.h > create mode 100644 test/optee/Kconfig > create mode 100644 test/optee/Makefile > create mode 100644 test/optee/cmd_ut_optee.c > create mode 100644 test/optee/test-optee-base.dts > create mode 100644 test/optee/test-optee-no-optee.dts > create mode 100644 test/optee/test-optee-optee.dts Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 02/13] dm: pinctrl: convert pinctrl-single to livetree
Hi Patrick,
On Wed, 23 Oct 2019 at 07:45, Patrick Delaunay wrote:
>
> Convert 'pinctrl-single' using livetree functions
> - ofnode_get_property
> - ofnode_read_u32_default
> - ofnode_read_u32_array
> - ofnode_read_bool
> - dev_read_addr
> and get rid of DECLARE_GLOBAL_DATA_PTR.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> drivers/pinctrl/pinctrl-single.c | 33 +++-
> 1 file changed, 15 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-single.c
> b/drivers/pinctrl/pinctrl-single.c
> index 1dfc97dcea..67429d6995 100644
> --- a/drivers/pinctrl/pinctrl-single.c
> +++ b/drivers/pinctrl/pinctrl-single.c
> @@ -9,8 +9,6 @@
> #include
> #include
>
> -DECLARE_GLOBAL_DATA_PTR;
> -
> struct single_pdata {
> fdt_addr_t base;/* first configuration register */
> int offset; /* index of last configuration register */
> @@ -117,13 +115,12 @@ static int single_configure_bits(struct udevice *dev,
> static int single_set_state(struct udevice *dev,
> struct udevice *config)
> {
> - const void *fdt = gd->fdt_blob;
> const struct single_fdt_pin_cfg *prop;
> const struct single_fdt_bits_cfg *prop_bits;
> int len;
>
> - prop = fdt_getprop(fdt, dev_of_offset(config), "pinctrl-single,pins",
> - );
> + prop = ofnode_get_property(dev_ofnode(dev), "pinctrl-single,pins",
> + );
dev_read_prop()
Similarly below
>
> if (prop) {
> dev_dbg(dev, "configuring pins for %s\n", config->name);
> @@ -136,9 +133,9 @@ static int single_set_state(struct udevice *dev,
> }
>
> /* pinctrl-single,pins not found so check for pinctrl-single,bits */
> - prop_bits = fdt_getprop(fdt, dev_of_offset(config),
> - "pinctrl-single,bits",
> - );
> + prop_bits = ofnode_get_property(dev_ofnode(dev),
> + "pinctrl-single,bits",
> + );
> if (prop_bits) {
> dev_dbg(dev, "configuring pins for %s\n", config->name);
> if (len % sizeof(struct single_fdt_bits_cfg)) {
> @@ -160,27 +157,27 @@ static int single_ofdata_to_platdata(struct udevice
> *dev)
> int res;
> struct single_pdata *pdata = dev->platdata;
>
> - pdata->width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
> - "pinctrl-single,register-width", 0);
> + pdata->width = ofnode_read_u32_default(dev_ofnode(dev),
> +
> "pinctrl-single,register-width",
> + 0);
>
> - res = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
> - "reg", of_reg, 2);
> + res = ofnode_read_u32_array(dev_ofnode(dev), "reg", of_reg, 2);
> if (res)
> return res;
> pdata->offset = of_reg[1] - pdata->width / 8;
>
> - addr = devfdt_get_addr(dev);
> + addr = dev_read_addr(dev);
> if (addr == FDT_ADDR_T_NONE) {
> dev_dbg(dev, "no valid base register address\n");
> return -EINVAL;
> }
> pdata->base = addr;
>
> - pdata->mask = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
> -"pinctrl-single,function-mask",
> -0x);
> - pdata->bits_per_mux = fdtdec_get_bool(gd->fdt_blob,
> dev_of_offset(dev),
> - "pinctrl-single,bit-per-mux");
> + pdata->mask = ofnode_read_u32_default(dev_ofnode(dev),
> + "pinctrl-single,function-mask",
> + 0x);
> + pdata->bits_per_mux = ofnode_read_bool(dev_ofnode(dev),
> + "pinctrl-single,bit-per-mux");
>
> return 0;
> }
> --
> 2.17.1
Regards,
Simon
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Re: [U-Boot] [PATCH 04/13] dm: pinctrl: migrate pinctrl-generic to livetree
Hi Patrick, On Wed, 23 Oct 2019 at 07:45, Patrick Delaunay wrote: > > Migrate pinctrl-generic to livetree: > - ofnode_get_first_property > - ofnode_get_next_property > - ofnode_get_property_by_prop > - ofnode_read_string_count > - ofnode_read_string_index > and get rid of DECLARE_GLOBAL_DATA_PTR. > > This solve parsing issue during test in sandbox for pin > configuration (OF_LIVE is activated in sandbox_defconfig > and sub node are not correctly parsed in > pinctrl_generic_set_state_subnode with fdt lib API). > > Signed-off-by: Patrick Delaunay > --- > > drivers/pinctrl/pinctrl-generic.c | 36 +++ > 1 file changed, 17 insertions(+), 19 deletions(-) > It looks like this should use dev_read_...() too. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] dts: Kconfig: Fix help for SPL_OF_CONTROL
On Tue, 22 Oct 2019 at 08:50, Walter Lozano wrote: > > As initially this feature was implemented as a negative CONFIG and > later it was redesigned to be positive the help text should be > updated to reflect this change. > > This commit updates the help text to match the current implementation. > > Signed-off-by: Walter Lozano > --- > dts/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2 1/4] aes: add a define for the size of a block
On Tue, 29 Oct 2019 at 11:29, Philippe Reynes wrote: > > In the code, we use the size of the key for the > size of the block. It's true when the key is 128 bits, > but it become false for key of 192 bits and 256 bits. > So to prepare the support of aes192 and 256, > we introduce a constant for the iaes block size. > > Signed-off-by: Philippe Reynes > --- > cmd/aes.c | 2 +- > include/uboot_aes.h | 5 +++-- > lib/aes.c | 34 +- > 3 files changed, 21 insertions(+), 20 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] blk: set log2blksz in blk_create_device()
Hi Heinrich, On Fri, 25 Oct 2019 at 04:15, Heinrich Schuchardt wrote: > > The ext4 file system requires log2blksz to be set. So when setting the > block size on the block descriptor we should fill this field too. > > This fixes a problem with EFI block devices providing ext4 partitions, cf. > https://lists.denx.de/pipermail/u-boot/2019-October/387702.html. > > Signed-off-by: Heinrich Schuchardt > --- > drivers/block/blk-uclass.c | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Simon Glass But I wonder if blk_create_device() should change to take log2blksz as its parameter and calculate blksz? > diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c > index e8f58b3f5e..ca8978f0e1 100644 > --- a/drivers/block/blk-uclass.c > +++ b/drivers/block/blk-uclass.c > @@ -580,6 +580,7 @@ int blk_create_device(struct udevice *parent, const char > *drv_name, > desc = dev_get_uclass_platdata(dev); > desc->if_type = if_type; > desc->blksz = blksz; > + desc->log2blksz = LOG2(desc->blksz); > desc->lba = lba; > desc->part_type = PART_TYPE_UNKNOWN; > desc->bdev = dev; > -- > 2.23.0 > Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 09/13] test: dm: update test for pins configuration in pinctrl node
On Wed, 23 Oct 2019 at 07:45, Patrick Delaunay wrote: > > Add test for "pins" configuration in gpio uclass with set_state() ops > and test for generic parsing of pinconf_param array). > > set_state() is called by: > - pinctrl_generic_set_state > |- pinctrl_generic_set_state_subnode > > Signed-off-by: Patrick Delaunay > --- > > arch/sandbox/dts/test.dts | 25 + > drivers/pinctrl/pinctrl-sandbox.c | 14 +- > test/py/tests/test_pinmux.py | 28 ++-- > 3 files changed, 56 insertions(+), 11 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 4/5] regmap: Add support for regmap fields
On Fri, 27 Sep 2019 at 07:22, Jean-Jacques Hiblot wrote: > > A regmap field is an abstraction available in Linux. It provides to access > bitfields in a regmap without having to worry about shifts and masks. > > Signed-off-by: Jean-Jacques Hiblot > --- > > drivers/core/regmap.c | 77 ++ > include/regmap.h | 108 ++ > 2 files changed, 185 insertions(+) > Reviewed-by: Simon Glass But this does need tests. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Confusion about "u-boot/doc/uImage.FIT/signature.txt"
Hi Lang,
On Tue, 22 Oct 2019 at 20:23, Lang Yu wrote:
>
> Hi, sjg,
>
>
>
> I'm YuLang, a software engineer in Hesai Tech. I really appreciate your
> contribution to secure boot. But I'm confused with your explanation about
> signature with FIT image in "u-boot/doc/uImage.FIT/signature.txt". As
> following，
>
>
> / {
> images {
> kernel@1 {
> data =
> hash@1 {
> algo = "sha1";
> value = <...kernel hash 1...>
> };
> };
> kernel@2 {
> data =
> hash@1 {
> algo = "sha1";
> value = <...kernel hash 2...>
> };
> };
> fdt@1 {
> data = ;
> hash@1 {
> algo = "sha1";
> value = <...fdt hash 1...>
> };
> };
> fdt@2 {
> data = ;
> hash@1 {
> algo = "sha1";
> value = <...fdt hash 2...>
> };
> };
> };
> configurations {
> default = "conf@1";
> conf@1 {
> kernel = "kernel@1";
> fdt = "fdt@1";
> signature@1 {
> algo = "sha1,rsa2048";
> value = <...conf 1 signature...>;
> };
> };
> conf@2 {
> kernel = "kernel@2";
> fdt = "fdt@2";
> signature@1 {
> algo = "sha1,rsa2048";
> value = <...conf 1 signature...>;
> };
> };
> };
> };
>
>
> You can see that we have added hashes for all images (since they are no
> longer signed), and a signature to each configuration. In the above example,
> mkimage will sign configurations/conf@1, the kernel and fdt that are
> pointed to by the configuration (/images/kernel@1, /images/kernel@1/hash@1,
> /images/fdt@1, /images/fdt@1/hash@1) and the root structure of the image
> (so that it isn't possible to add or remove root nodes). The signature is
> written into /configurations/conf@1/signature@1/value. It can easily be
> verified later even if the FIT has been signed with other keys in the
> meantime.
>
>
>
> But what a signature to each configuration really means ?
>
>
> 1. rsa2048-privatekey(sha1(kernel data + fdt data))
>
>
> 2. rsa2048-privatekey(sha1(kernel hash+kernel hash))
>
>
> 3
>
>
> Could you give a clear explanation? Many thanks
This is explained in signature.txt, just above the 'verification' heading:
> In the above example,
mkimage will sign configurations/conf-1, the kernel and fdt that are
pointed to by the configuration (/images/kernel-1, /images/kernel-1/hash-1,
/images/fdt-1, /images/fdt-1/hash-1) and the root structure of the image
(so that it isn't possible to add or remove root nodes). The signature is
written into /configurations/conf-1/signature-1/value. It can easily be
verified later even if the FIT has been signed with other keys in the
meantime.
Regards,
SImon
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Re: [U-Boot] [PATCH v1 3/5] regmap: Allow providing read/write callbacks through struct regmap_config
Hi Jean-Jacques, On Fri, 27 Sep 2019 at 07:22, Jean-Jacques Hiblot wrote: > > Some linux drivers provide their own read/write functions to access data > from/of the regmap. Adding support for it. > > Signed-off-by: Jean-Jacques Hiblot > --- > > drivers/core/regmap.c | 12 > include/regmap.h | 26 +++--- > 2 files changed, 35 insertions(+), 3 deletions(-) This increases code size in SPL so should probably be controlled by a Kconfig. Also I wonder if regmap should become a uclass if we are adding operations to it? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 08/13] pinctrl: sandbox: Add mux information in get_pin_muxing
On Wed, 23 Oct 2019 at 07:45, Patrick Delaunay wrote: > > Add param information in pin information output. > This update prepare unitary test for pin configuration > in pinctrl node. > > Signed-off-by: Patrick Delaunay > --- > > drivers/pinctrl/pinctrl-sandbox.c | 30 ++ > 1 file changed, 30 insertions(+) > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/4] fdtdec: protect against another NULL phandlep in fdtdec_add_reserved_memory()
On Tue, 22 Oct 2019 at 13:04, Heiko Stuebner wrote:
>
> From: Heiko Stuebner
>
> The change adding fdtdec_add_reserved_memory() already protected the added
> phandle against the phandlep being NULL - making the phandlep var optional.
>
> But in the early code checking for an already existing carveout this check
> was not done and thus the phandle assignment could run into trouble,
> so add a check there as well, which makes the function still return
> successfully if a matching region is found, even though no-one wants to
> work with the phandle.
>
> Fixes: c9222a08b3f7 ("fdtdec: Implement fdtdec_add_reserved_memory()")
> Signed-off-by: Heiko Stuebner
> ---
> changes in v2:
> - add comment about phandlep allowed to be NULL
>
> include/fdtdec.h | 1 +
> lib/fdtdec.c | 3 ++-
> 2 files changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass
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Re: [U-Boot] [PATCH 11/13] gpio: sandbox: cleanup binding support
On Wed, 23 Oct 2019 at 07:45, Patrick Delaunay wrote: > > Cleanup binding support, use the generic binding by default > (test u-class gpio_xlate_offs_flags function) and add > specific binding for added value. > > Signed-off-by: Patrick Delaunay > --- > > arch/sandbox/dts/test.dts | 14 ++ > drivers/gpio/sandbox.c | 13 - > include/dt-bindings/gpio/sandbox-gpio.h | 24 > 3 files changed, 42 insertions(+), 9 deletions(-) > create mode 100644 include/dt-bindings/gpio/sandbox-gpio.h Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/5] drivers: clk: Handle gracefully NULL pointers
Hi Jean-Jacques, On Mon, 30 Sep 2019 at 06:29, Jean-Jacques Hiblot wrote: > > Prepare the way for a managed CLK API by handling NULL pointers without > crashing nor failing. > > Signed-off-by: Jean-Jacques Hiblot > --- > > drivers/clk/clk-uclass.c | 43 +--- > include/clk.h| 2 +- > 2 files changed, 37 insertions(+), 8 deletions(-) This increases code size so can we make it a Kconfig option? Why is someone calling these functions with NULL? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 06/13] gpio: add support for new flags on gpio configuration
Hi Patrick, On Wed, 23 Oct 2019 at 07:45, Patrick Delaunay wrote: > > This commit manages the flags that can be used in GPIO specifiers to > indicate if a pull-up resistor or pull-down resistor should be > enabled for output GPIO and the Open Drain/Open Source configuration > for input GPIO. > > It is managed in driver with a new ops in gpio uclass set_config. > > These flags are already support in Linux kernel in gpiolib. > > Signed-off-by: Patrick Delaunay > --- > > drivers/gpio/gpio-uclass.c | 62 +- > include/asm-generic/gpio.h | 56 ++ > 2 files changed, 117 insertions(+), 1 deletion(-) > To me this seems like a pretty annoying interface. The uclass has to call the driver multiple times with each enum and the driver may end up reprogramming the pins multiple times to get it right. Normally we want to program things correctly once, before enabling the function. On the other handle I think what you have is better than adding new methods like set_open_drain(). But overall I think it would be better to define a new struct like gpio_config that holds some flags and perhaps a few other things. Then the uclass can set up that struct and call the driver once with it, to set up the pin. It could include input/output too, so that if set_config() is defined, the uclass uses that instead of direction_output(), etc. What do you think? Also we should update the sandbox driver to include tests for new methods. It looks like you have done pinctrl but not this? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 13/13] test: pinmux: add pincontrol-gpio for pin configuration
On Wed, 23 Oct 2019 at 07:45, Patrick Delaunay wrote: > > Add a simple pincontrol associated to the sandbox gpio driver, > that allow to check pin configuration check with the > command pinmux. > > The pinux test is also updated to test behavior with 2 pincontrols. > > Example to check LED pin configuration: > > => pinmux list > | Device| Driver| Parent > | pinctrl-gpio | sandbox_pinctrl_gpio | root_driver > | pinctrl | sandbox_pinctrl | root_driver > > => pinmux dev pinctrl-gpio > > => pinmux status > > a0: gpio input . > a1: gpio input . > a2: gpio input . > a3: gpio input . > a4: gpio input . > a5: gpio output drive-pull-push > a6: gpio output drive-pull-push > ... > > Serie-cc: Heiko Schocher > > Signed-off-by: Patrick Delaunay > > --- > > arch/sandbox/dts/test.dts| 48 + > drivers/gpio/sandbox.c | 193 +++ > test/py/tests/test_pinmux.py | 10 ++ > 3 files changed, 229 insertions(+), 22 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 10/13] gpio: sandbox: cleanup flag support
On Wed, 23 Oct 2019 at 07:45, Patrick Delaunay wrote: > > Replace the GPIOF_ defines of gpio UCLASS (they are not bitfields but > enum gpio_func_t = State of a GPIO, as reported by get_function()) > by GPIO_FLAG to access to the bitfield 'flags' of struct gpio_state. > > This patch avoid confusion between sandbox and gpio UCLASS defines. > > Signed-off-by: Patrick Delaunay > --- > > drivers/gpio/sandbox.c | 26 +- > 1 file changed, 13 insertions(+), 13 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 01/13] pinctrol: dm: remove the function pinctrl_decode_pin_config
On Wed, 23 Oct 2019 at 07:44, Patrick Delaunay wrote: > > Remove the pinctrl_decode_pin_config() API, because this > function is unused and not compatible with livetree > (it uses fdtdec_get_bool instead of ofnode API). > > Signed-off-by: Patrick Delaunay > --- > > drivers/pinctrl/pinctrl-uclass.c | 12 > include/dm/pinctrl.h | 13 - > 2 files changed, 25 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/8] cmd: bootimg: Add bootimg command
Hi Sam, On Wed, 23 Oct 2019 at 08:34, Sam Protsenko wrote: > > This command can be used to extract fields and image payloads from > Android Boot Image. It can be used for example to implement boot flow > where dtb is taken from boot.img (as v2 incorporated dtb inside of > boot.img). Using this command, one can obtain needed dtb file from > boot.img in scripting manner, and then apply needed dtbo's (from "dtbo" > partition) on top of that, providing then the resulting image to bootm > command in order to boot the Android. > > Also right now this command has the sub-command to get an address and > size of recovery dtbo from recovery image. It can be further parsed using > 'dtimg' command and merged into dtb file (for non-A/B devices only, see > [1,2] for details). > > [1] https://source.android.com/devices/bootloader/boot-image-header > [2] https://source.android.com/devices/architecture/dto/partitions > > Signed-off-by: Sam Protsenko > --- > Changes in v2: > - add "set_addr" sub-command > - provide mem mappings for sandbox > - rebase on top of master > > cmd/Kconfig | 8 ++ > cmd/Makefile | 1 + > cmd/bootimg.c | 210 ++ > 3 files changed, 219 insertions(+) > create mode 100644 cmd/bootimg.c Sorry I still think this name 'bootimg' is confusing. How would anyone know that it is specific to Android? How about abootimg? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 03/15] buildman: Convert to Python 3
Hi Tom, On Thu, 24 Oct 2019 at 19:04, Simon Glass wrote: > > Convert buildman to Python 3 and make it use that, to meet the 2020 > deadline. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > tools/buildman/board.py | 7 +-- > tools/buildman/bsettings.py | 20 +++ > tools/buildman/builder.py | 45 > tools/buildman/builderthread.py | 24 - > tools/buildman/buildman.py | 10 ++-- > tools/buildman/control.py | 40 +++--- > tools/buildman/func_test.py | 16 +++--- > tools/buildman/test.py | 22 > tools/buildman/toolchain.py | 93 + > 9 files changed, 139 insertions(+), 138 deletions(-) I am a bit mystified by this: https://gitlab.denx.de/u-boot/custodians/u-boot-dm/-/jobs/25186 It runs locally and I cannot see why it is not using unicode. Are there instructions on how to get to the same Python version as gitlab? I fear a steep learning curve coming. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/8] riscv: ax25: add SPL support
Hi Bin > > Hi Rick, > > On Fri, Oct 25, 2019 at 2:17 PM Andes wrote: > > > > From: Rick Chen > > > > The U-Boot SPL will boot in M mode and load the > > FIT image which include OpenSbi and U-Boot proper > > nits: OpenSBI OK > > > images. After loading progress, it will jump to > > OpenSbi first and then U-Boot proper which will > > ditto OK > > > run in S mode. > > > > Signed-off-by: Rick Chen > > Cc: KC Lin > > Cc: Alan Kao > > --- > > arch/riscv/cpu/ax25/Kconfig | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig > > index d411a79..8d8d71d 100644 > > --- a/arch/riscv/cpu/ax25/Kconfig > > +++ b/arch/riscv/cpu/ax25/Kconfig > > @@ -6,7 +6,9 @@ config RISCV_NDS > > imply RISCV_TIMER > > imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) > > imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) > > - imply V5L2_CACHE > > Why this is removed? Without CACHE_SUPPORT, the compiling will fail while enable V5l2_CACHE. That is why I remove it. I hope it can be enable manually. Because it will enlarge U-Boot SPL size. Thanks Rick > > > + imply SPL_CPU_SUPPORT > > + imply SPL_OPENSBI > > + imply SPL_LOAD_FIT > > help > > Run U-Boot on AndeStar V5 platforms and use some specific features > > which are provided by Andes Technology AndeStar V5 families. > > -- > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/5] tools: buildman: Remove useless mkdir() in Make() in test.py
Hi Bin, On Tue, 29 Oct 2019 at 07:56, Bin Meng wrote: > > Hi Simon, > > On Tue, Oct 29, 2019 at 11:37 AM Simon Glass wrote: > > > > Hi Bin, > > > > On Mon, 28 Oct 2019 at 08:25, Bin Meng wrote: > > > > > > In the 'Make' function, the codes tries to create a directory > > > if current stage is 'build'. But the directory isn't used at > > > all anywhere. > > > > > > Signed-off-by: Bin Meng > > > > > > --- > > > > > > Changes in v2: > > > - remove the unneeded debug codes > > > > > > tools/buildman/test.py | 8 > > > 1 file changed, 8 deletions(-) > > > > Can you check this works OK when there is no output dir at all? E.g. > > > > -o /path/to/a/deep/non-existent/dir > > If I understand the codes correctly the "O=" in args[] does not > come from "-o /path/to/a/deep/non-existent/dir" but from the > builderthread with some hardcoded values. The removed codes here seem > to do something not very useful. That's fine, and TBH if we hit a problem later due to this we should add a unit test to cover it. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Please pull u-boot-dm
Hi Tom, Test results here: https://gitlab.denx.de/u-boot/custodians/u-boot-dm/pipelines/1131 The following changes since commit ffc379b42c85466e1dd4c8fee8268801f26d2ab8: Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips (2019-10-25 20:07:24 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-29oct19 for you to fetch changes up to d60ae4c59df55c08dc96202ff58fed21ab3afb7d: fdt: Fix alignment issue when reading 64-bits properties from fdt (2019-10-27 13:01:53 -0600) Fix for patman with email addresses containing commas Bootstage improvements for TPL, SPL Various sandbox and dm improvements and fixes Dmitry Torokhov (1): patman: separate emails in CC list with NULs Jean-Jacques Hiblot (2): test: regmap: check the values read from the regmap fdt: Fix alignment issue when reading 64-bits properties from fdt Kever Yang (1): dm: core: Update log method for uclass_find_device_by_seq Simon Glass (14): sandbox: test: Show hex values on failure sandbox: Drop 'const' from sandbox_write() sandbox: test: Add a prototype for sandbox_set_enable_memio() dm: regmap: Fix mask in regmap_update_bits() tiny-printf: Reduce size by removing ctype tiny-printf: Add print_grouped_ull() tiny-printf: Reorder code to support %p bloblist: Reserve an aligned base bootstage: Store the next ID in the stash bootstage: Fix counting of entries in stash bootstage: Avoid conflicts between stash/unstash bootstage: Correct relocation algorithm bootstage: Mark the start/end of TPL and SPL separately bootstage: Allow SPL to obtain bootstage info from TPL arch/sandbox/cpu/cpu.c | 3 +-- arch/sandbox/include/asm/io.h | 11 +- arch/sandbox/include/asm/test.h | 11 ++ common/board_f.c| 2 ++ common/board_r.c| 1 - common/bootstage.c | 53 ++ common/fdt_support.c| 2 +- common/spl/spl.c| 23 drivers/core/ofnode.c | 2 +- drivers/core/regmap.c | 2 +- drivers/core/uclass.c | 11 ++ include/bootstage.h | 2 ++ include/linux/libfdt_env.h | 1 + include/regmap.h| 3 ++- include/test/ut.h | 3 ++- lib/fdtdec.c| 2 +- lib/tiny-printf.c | 29 +++-- test/dm/regmap.c| 19 ++--- tools/patman/func_test.py | 4 ++-- tools/patman/patman.py | 2 +- tools/patman/series.py | 4 ++-- 21 files changed, 135 insertions(+), 55 deletions(-) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5] dm: regmap: Fix mask in regmap_update_bits()
On 12/10/2019 00:16, Simon Glass wrote: > This function assumes that the 'val' parameter has no masked bits set. > This is not defined by the function prototype though. Fix the function to > mask the value and update the documentation. > > Signed-off-by: Simon Glass > --- > > drivers/core/regmap.c | 2 +- > include/regmap.h | 3 ++- > 2 files changed, 3 insertions(+), 2 deletions(-) > Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] sandbox: test: Show hex values on failure
On Sat, Oct 12, 2019 at 6:28 AM Simon Glass wrote: > > Quite a few tests use addresses or hex values for comparisons. Add hex > output for test failures, e.g.: > >0x55ca22fa == reg: Expected 0x55ca22fa (1439310586), > got 0x55ea22fb (1441407739) > > Signed-off-by: Simon Glass > --- > > include/test/ut.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 03/10] tiny-printf: Reorder code to support %p
With a bit of code reordering we can support %p using the existing code for ulong. Move the %p code up and adjust the logic accordingly. Signed-off-by: Simon Glass --- Changes in v2: - Add a new patch to support %p without DEBUG lib/tiny-printf.c | 30 +- 1 file changed, 17 insertions(+), 13 deletions(-) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 09/10] bootstage: Mark the start/end of TPL and SPL separately
At present bootstage in TPL and SPL use the same ID so it is not possible to see the timing of each. Separate out the IDs and use the correct one depending on which phase we are at. Example output: Timer summary in microseconds (14 records): MarkElapsed Stage 0 0 reset 224,787224,787 TPL 282,248 57,461 end TPL 341,067 58,819 SPL 925,436584,369 end SPL 931,710 6,274 board_init_f 1,035,482103,772 board_init_r 1,387,852352,370 main_loop 1,387,911 59 id=175 Accumulated time: 196 dm_r 8,300 dm_spl 14,139 dm_f 229,121 fsp-m 262,992 fsp-s Signed-off-by: Simon Glass --- Changes in v2: None common/spl/spl.c| 9 ++--- include/bootstage.h | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/5] sandbox: test: Add a prototype for sandbox_set_enable_memio()
On Sat, Oct 12, 2019 at 6:22 AM Simon Glass wrote: > > This function needs a prototype so that tests can use it. Add one. > > Signed-off-by: Simon Glass > --- > > arch/sandbox/include/asm/test.h | 11 +++ > 1 file changed, 11 insertions(+) > Reviewed-by: Bin Meng Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] test: regmap: check the values read from the regmap
On Sat, Oct 12, 2019 at 6:28 AM Simon Glass wrote: > > From: Jean-Jacques Hiblot > > The test did reads after writes but didn't check the value. > It probably was because the sandbox didn't implement the writeX/readX > functions. > > Signed-off-by: Jean-Jacques Hiblot > Updated to use sandbox_set_enable_memio(): > Signed-off-by: Simon Glass > --- > > test/dm/regmap.c | 19 --- > 1 file changed, 16 insertions(+), 3 deletions(-) > Reviewed-by: Bin Meng Tested-by: Bin Meng Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/10] bootstage: Fix counting of entries in stash
The current code searches for empty records but these not existing with bootstage now. This used to be needed when bootstage records were stored in a spare array. Drop the unnecessary code and fix a code-style nit at the same time. Signed-off-by: Simon Glass --- Changes in v2: None common/bootstage.c | 12 ++-- 1 file changed, 2 insertions(+), 10 deletions(-) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 10/10] bootstage: Allow SPL to obtain bootstage info from TPL
It is possible to enable bootstage in TPL. TPL can stash the info for SPL. But at present this information is then lost because SPL does not read from the stash. Add support for SPL not being the first phase to enable bootstage. Signed-off-by: Simon Glass --- Changes in v2: - Adjust SPL logic to avoid failing if TPL does not provide bootstage data - Add a new patch to support %p without DEBUG in tiny-printf common/spl/spl.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 04/10] bloblist: Reserve an aligned base
Make sure that the bloblist starts on an aligned boundary. This protects against one of the early allocating causing the alignment to be lost. Signed-off-by: Simon Glass --- Changes in v2: None common/board_f.c | 1 + 1 file changed, 1 insertion(+) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] sandbox: Drop 'const' from sandbox_write()
Hi Simon, On Sat, Oct 12, 2019 at 6:22 AM Simon Glass wrote: > > This function writes to its address so the address should not be declared > as const. Fix it. > > Signed-off-by: Simon Glass > --- > > arch/sandbox/cpu/cpu.c| 3 +-- > arch/sandbox/include/asm/io.h | 11 +-- > 2 files changed, 6 insertions(+), 8 deletions(-) > It looks I did something wrong when testing the previous patch :) I remember adding const was to fix build warning somewhere else. Anyway the changes look good to me. But I suspect we need give it a full build to see whether it generates warning somewhere. Reviewed-by: Bin Meng Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 07/10] bootstage: Avoid conflicts between stash/unstash
At present there is a single shared address for bootstage data in both TPL and SPL. If SPL unstashs TPL bootstage info and then stashes it again to pass it to U-Boot, the new stash overwrites the strings of the old stash. Fix this by duplicating the strings into the malloc() region. This should be a small code. Fix the header-file order at the same time. This problem doesn't happen at the next stage (SPL->U-Boot) since U-Boot relocates the boostage data. Signed-off-by: Simon Glass --- Changes in v2: None common/bootstage.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 05/10] bootstage: Store the next ID in the stash
When stashing bootstage info, store the next ID so that it can be used when the stash is restored. This avoids the ID starting at zero and potentially overwriting existing entries. Signed-off-by: Simon Glass --- Changes in v2: None common/bootstage.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 08/10] bootstage: Correct relocation algorithm
At present bootstage relocation assumes that it is possible to point back to memory available before relocation, so it does not relocate the strings. However this is not the case on some platforms, such as x86 which uses the cache as RAM and loses access to this when the cache is enabled. Move the relocation step to before U-Boot relocates, expand the allocated region to include space for the strings and relocate the strings at the same time as the bootstage records. This ensures that bootstage data can remain accessible from TPL through SPL to U-Boot before/after relocation. Signed-off-by: Simon Glass --- Changes in v2: None common/board_f.c | 1 + common/board_r.c | 1 - common/bootstage.c | 25 ++--- 3 files changed, 23 insertions(+), 4 deletions(-) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/10] tiny-printf: Reduce size by removing ctype
The ctype array is brought into the image, adding 256 bytes, when it is unlikely to be needed. The extra code for %p is only present when DEBUG is defined, so let's drop ctype as well unless DEBUG is defined. Signed-off-by: Simon Glass --- Changes in v2: None lib/tiny-printf.c | 7 +++ 1 file changed, 7 insertions(+) Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 02/10] tiny-printf: Add print_grouped_ull()
On 22.10.19 01:26, Simon Glass wrote: > This function is used in the bootstage report which may be trigged in TPL > or TPL. Add a very basic implication of this function so that it builds. > There is no attempt to get the formatting right, since this would add too > much code size. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > lib/tiny-printf.c | 6 ++ > 1 file changed, 6 insertions(+) > Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] patman: separate emails in CC list with NULs
On Mon, 21 Oct 2019 at 21:10, Dmitry Torokhov wrote: > > There is a contributor in Linux kernel with a comma in their name, which > confuses patman and results in invalid to- or cc- addresses on some > patches. To avoid this, let's use \0 as a separator when generating cc > file. > > Signed-off-by: Dmitry Torokhov > --- > > Changes in v2: > - updated test cases so that 'patman --test' passes > > tools/patman/func_test.py | 4 ++-- > tools/patman/patman.py| 2 +- > tools/patman/series.py| 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Simon Glass Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] fdt: Fix alignment issue when reading 64-bits properties from fdt
On Tue, 22 Oct 2019 at 02:05, Jean-Jacques Hiblot wrote: > > The FDT specification [0] gives a requirement of aligning properties on > 32-bits. Make sure that the compiler is aware of this constraint when > accessing 64-bits properties. > > [0]: > https://github.com/devicetree-org/devicetree-specification/blob/master/source/flattened-format.rst > > Signed-off-by: Jean-Jacques Hiblot > --- > > Here is a portion of the disassembly of ofnode_read_u64(). It show the effect > of the patch on ARM64. > > with the classic fdt64_t type. GCC emits LDR (load register) > 34: 54000109b.ls54 // b.plast > 38: f940ldr x0, [x0] > 3c: dac00c00rev x0, x0 > > with the unaligned_fdt64_t type. GCC emits LDP (Load Pair of registers) > 34: 54000129b.ls58 // b.plast > 38: 2941ldp w1, w0, [x0] > 3c: aa008020orr x0, x1, x0, lsl #32 > 40: dac00c00rev x0, x0 > > > common/fdt_support.c | 2 +- > drivers/core/ofnode.c | 2 +- > include/linux/libfdt_env.h | 1 + > lib/fdtdec.c | 2 +- > 4 files changed, 4 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass No change log? Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] dm: core: Update log method for uclass_find_device_by_seq
On Tue, 22 Oct 2019 at 01:40, Kever Yang wrote: > > Use log() insted of debug() for uclass_find_device_by_seq function, > since this print is very much and we can filter it out with log() > interface. > > Signed-off-by: Kever Yang > --- > > Changes in v2: > - use log_debug() instead of log() > > drivers/core/uclass.c | 11 +++ > 1 file changed, 7 insertions(+), 4 deletions(-) Reviewed-by: Simon Glass Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 23/29] drivers: mmc: add MMC controller driver for OcteonTX
From: Suneel Garapati
Adds support for MMC controllers found on OcteonTX or
OcteonTX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
---
drivers/mmc/Kconfig |9 +
drivers/mmc/Makefile |1 +
drivers/mmc/octeontx_hsmmc.c | 3233 ++
drivers/mmc/octeontx_hsmmc.h | 191 ++
4 files changed, 3434 insertions(+)
create mode 100644 drivers/mmc/octeontx_hsmmc.c
create mode 100644 drivers/mmc/octeontx_hsmmc.h
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 85fd1906bd..0a224bd1de 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -287,6 +287,15 @@ config MMC_PCI
This selects PCI-based MMC controllers.
If you have an MMC controller on a PCI bus, say Y here.
+config MMC_OCTEONTX
+ bool "Marvell OcteonTX Multimedia Card Interface support"
+ depends on (ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ depends on DM_MMC
+ help
+ This selects the OcteonTX Multimedia card Interface.
+ If you have an OcteonTX/TX2 board with a Multimedia Card slot,
+ say Y here.
+
If unsure, say N.
config MMC_OMAP_HS
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 9c1f8e56e2..67d6833502 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
obj-$(CONFIG_MMC_MXC) += mxcmmc.o
obj-$(CONFIG_MMC_MXS) += mxsmmc.o
+obj-$(CONFIG_MMC_OCTEONTX) += octeontx_hsmmc.o
obj-$(CONFIG_MMC_PCI) += pci_mmc.o
obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c
new file mode 100644
index 00..79129db576
--- /dev/null
+++ b/drivers/mmc/octeontx_hsmmc.c
@@ -0,0 +1,3233 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 201i9 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include/* for ctrlc */
+#include "octeontx_hsmmc.h"
+
+#define PCI_DEVICE_ID_OCTEONTX_EMMC0xA010
+
+#define MMC_TIMEOUT_SHORT 20 /* in ms */
+#define MMC_TIMEOUT_LONG 1000
+#define MMC_TIMEOUT_ERASE 1
+
+#define MMC_DEFAULT_DATA_IN_TAP10
+#define MMC_DEFAULT_CMD_IN_TAP 10
+#define MMC_DEFAULT_CMD_OUT_TAP39
+#define MMC_DEFAULT_DATA_OUT_TAP 39
+#define MMC_DEFAULT_HS200_CMD_IN_TAP 24
+#define MMC_DEFAULT_HS200_DATA_IN_TAP 24
+#define MMC_DEFAULT_HS200_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
+#define MMC_DEFAULT_HS200_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
+#define MMC_DEFAULT_SD_UHS_SDR104_CMD_OUT_TAP MMC_DEFAULT_HS200_CMD_OUT_TAP
+#define MMC_DEFAULT_SD_UHS_SDR104_DATA_OUT_TAP MMC_DEFAULT_HS200_DATA_OUT_TAP
+#define MMC_LEGACY_DEFAULT_CMD_OUT_TAP 39
+#define MMC_LEGACY_DEFAULT_DATA_OUT_TAP39
+#define MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP 63
+#define MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP 63
+#define MMC_HS_CMD_OUT_TAP 32
+#define MMC_HS_DATA_OUT_TAP32
+#define MMC_SD_HS_CMD_OUT_TAP 26
+#define MMC_SD_HS_DATA_OUT_TAP 26
+#define MMC_SD_UHS_SDR25_CMD_OUT_TAP 26
+#define MMC_SD_UHS_SDR25_DATA_OUT_TAP 26
+#define MMC_SD_UHS_SDR50_CMD_OUT_TAP 26
+#define MMC_SD_UHS_SDR50_DATA_OUT_TAP 26
+#define MMC_DEFAULT_TAP_DELAY 4
+
+static void octeontx_mmc_switch_to(struct mmc *mmc);
+static int octeontx_mmc_configure_delay(struct mmc *mmc);
+#ifdef MMC_SUPPORTS_TUNING
+static void octeontx_mmc_set_timing(struct mmc *mmc);
+#endif
+static void set_wdog(struct mmc *mmc, u64 us);
+static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch);
+static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+struct mmc_data *data);
+#ifndef CONFIG_ARCH_OCTEONTX
+static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay);
+static int octeontx_mmc_calibrate_delay(struct mmc *mmc);
+#endif
+static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc);
+static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc);
+
+static bool host_probed;
+
+/**
+ * Get the slot data structure from a MMC data structure
+ */
+static inline struct octeontx_mmc_slot *mmc_to_slot(struct mmc *mmc)
+{
+ return container_of(mmc, struct octeontx_mmc_slot, mmc);
+}
+
+static inline struct octeontx_mmc_host *mmc_to_host(struct mmc *mmc)
+{
+ return mmc_to_slot(mmc)->host;
+}
+
+static inline struct octeontx_mmc_slot *dev_to_mmc_slot(struct udevice *dev)
[U-Boot] [RFC PATCH 27/29] drivers: watchdog: add reset support for OcteonTX
From: Suneel Garapati
Adds support for Core 0 poke on OcteonTX and OcteonTX2
platforms.
Signed-off-by: Suneel Garapati
---
drivers/watchdog/Kconfig| 10 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/octeontx_wdt.c | 76 +
3 files changed, 87 insertions(+)
create mode 100644 drivers/watchdog/octeontx_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 8c16d69d33..61357a7f0a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -121,6 +121,16 @@ config WDT_MTK
The watchdog timer is stopped when initialized.
It performs full SoC reset.
+config WDT_OCTEONTX
+ bool "OcteonTX core watchdog support"
+ depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ default y if WDT && ARCH_OCTEONTX || ARCH_OCTEONTX2
+ imply WATCHDOG
+ help
+ This enables OcteonTX watchdog driver, which can be
+ found on OcteonTX/TX2 chipsets and inline with driver model.
+ Only supports watchdog reset.
+
config WDT_OMAP3
bool "TI OMAP watchdog timer support"
depends on WDT && ARCH_OMAP2PLUS
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 955caef815..66b20b0e98 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c
new file mode 100644
index 00..9362ad99bf
--- /dev/null
+++ b/drivers/watchdog/octeontx_wdt.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CORE0_POKE_OFFSET 0x5
+
+#if CONFIG_IS_ENABLED(ARCH_OCTEONTX)
+#define REG_BASE 0x8440
+#elif CONFIG_IS_ENABLED(ARCH_OCTEONTX2)
+#define REG_BASE 0x8020
+#endif
+
+struct octeontx_wdt {
+ void __iomem *reg;
+};
+
+static struct udevice *wdt_dev;
+
+static int octeontx_wdt_reset(struct udevice *dev)
+{
+ struct octeontx_wdt *priv;
+ u64 poke_reg;
+
+ if (dev) {
+ priv = dev_get_priv(dev);
+ poke_reg = ((u64)priv->reg & ~0xfULL) | CORE0_POKE_OFFSET;
+ } else {
+ poke_reg = REG_BASE + CORE0_POKE_OFFSET;
+ }
+ writeq(~0ULL, poke_reg);
+
+ return 0;
+}
+
+static int octeontx_wdt_probe(struct udevice *dev)
+{
+ struct octeontx_wdt *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ priv->reg = (void __iomem *)addr;
+ wdt_dev = dev;
+
+ return 0;
+}
+
+static const struct wdt_ops octeontx_wdt_ops = {
+ .reset = octeontx_wdt_reset,
+};
+
+static const struct udevice_id octeontx_wdt_ids[] = {
+ { .compatible = "arm,sbsa-gwdt" },
+ {}
+};
+
+U_BOOT_DRIVER(wdt_octeontx) = {
+ .name = "wdt_octeontx",
+ .id = UCLASS_WDT,
+ .of_match = octeontx_wdt_ids,
+ .ops = _wdt_ops,
+ .priv_auto_alloc_size = sizeof(struct octeontx_wdt),
+ .probe = octeontx_wdt_probe,
+};
--
2.23.0
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Re: [U-Boot] [EXT] Re: [RFC/RESEND 01/22] arm: introduce ARCH_THUNDERX
Thanks Tim, sent the series. Regards, Suneel On Tue, Oct 29, 2019 at 12:11 PM Tim Harvey wrote: > > On Sun, Oct 27, 2019 at 10:34 PM Suneel Garapati > wrote: > > > > Hi Matthias, > > > > Thanks for your patience. Sorry for the delay. > > > > I will post the patch-set tomorrow. > > > > Suneel, > > I haven't seen anything yet but I'm happy to test this on our Newport > boards running on CN8020/CN8030. We've been waiting quite a while. > > Is there some hold-up with posting a series? Post early and often as people > say! > > I know Aaron has posted some info and questions regarding Octeon > support but I assume you're working on OcteonTX (thunderx) which > perhaps doesn't have that much overlap? > > Regards, > > Tim ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 20/29] drivers: i2c: add I2C controller driver for OcteonTX
From: Suneel Garapati
Adds support for I2C controllers found on OcteonTX or
OcteonTX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
---
drivers/i2c/Kconfig| 7 +
drivers/i2c/Makefile | 1 +
drivers/i2c/octeontx_i2c.c | 968 +
3 files changed, 976 insertions(+)
create mode 100644 drivers/i2c/octeontx_i2c.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 03d2fed341..eb47454e76 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -366,6 +366,13 @@ config SYS_I2C_SANDBOX
bus. Devices can be attached to the bus using the device tree
which specifies the driver to use. See sandbox.dts as an example.
+config SYS_I2C_OCTEONTX
+ bool "OcteonTX I2C driver"
+ depends on (ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
+ default y
+ help
+Enable I2C support for OcteonTX/TX2 line of processors.
+
config SYS_I2C_S3C24X0
bool "Samsung I2C driver"
depends on ARCH_EXYNOS4 && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index c2f75d8755..e2ae95e770 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
+obj-$(CONFIG_SYS_I2C_OCTEONTX) += octeontx_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o
diff --git a/drivers/i2c/octeontx_i2c.c b/drivers/i2c/octeontx_i2c.c
new file mode 100644
index 00..b74424a75f
--- /dev/null
+++ b/drivers/i2c/octeontx_i2c.c
@@ -0,0 +1,968 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#if defined(CONFIG_ARCH_OCTEONTX)
+# define TWSI_THP 24
+#else
+# define TWSI_THP 3
+#endif
+
+/**
+ * Slave address to use for Thunder when accessed by another master
+ */
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SLAVE_ADDR
+# define CONFIG_SYS_I2C_OCTEONTX_SLAVE_ADDR0x77
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_0
+# ifdef CONFIG_SYS_I2C_SPEED
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_0 CONFIG_SYS_I2C_SPEED
+# else
+# define CONFIG_SYS_I2C_SPEED 10
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_0 CONFIG_SYS_I2C_SPEED
+# endif
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_1
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_1 CONFIG_SYS_I2C_OCTEONTX_SPEED_0
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_2
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_2 CONFIG_SYS_I2C_OCTEONTX_SPEED_1
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_3
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_3 CONFIG_SYS_I2C_OCTEONTX_SPEED_2
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_4
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_4 CONFIG_SYS_I2C_OCTEONTX_SPEED_3
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_5
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_5 CONFIG_SYS_I2C_OCTEONTX_SPEED_4
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_6
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_6 CONFIG_SYS_I2C_OCTEONTX_SPEED_5
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_7
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_7 CONFIG_SYS_I2C_OCTEONTX_SPEED_6
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_8
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_8 CONFIG_SYS_I2C_OCTEONTX_SPEED_7
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_9
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_9 CONFIG_SYS_I2C_OCTEONTX_SPEED_8
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_10
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_10 CONFIG_SYS_I2C_OCTEONTX_SPEED_9
+#endif
+
+#ifndef CONFIG_SYS_I2C_OCTEONTX_SPEED_11
+# define CONFIG_SYS_I2C_OCTEONTX_SPEED_11 CONFIG_SYS_I2C_OCTEONTX_SPEED_10
+#endif
+
+#define TWSI_SW_TWSI 0x1000
+#define TWSI_TWSI_SW 0x1008
+#define TWSI_INT 0x1010
+#define TWSI_SW_TWSI_EXT 0x1018
+
+union twsx_sw_twsi {
+ u64 u;
+ struct {
+ u64 data:32;
+ u64 eop_ia:3;
+ u64 ia:5;
+ u64 addr:10;
+ u64 scr:2;
+ u64 size:3;
+ u64 sovr:1;
+ u64 r:1;
+ u64 op:4;
+ u64 eia:1;
+ u64 slonly:1;
+ u64 v:1;
+ } s;
+};
+
+union twsx_sw_twsi_ext {
+ u64 u;
+ struct {
+ u64 data:32;
+ u64 ia:8;
+ u64 rsvd:24;
+ } s;
+};
+
+union twsx_int {
+ u64 u;
+ struct {
+ u64 st_int:1; /** TWSX_SW_TWSI register update int */
+ u64 ts_int:1; /** TWSX_TWSI_SW register update int */
+ u64 core_int:1; /** TWSI core interrupt, ignored
[U-Boot] [RFC PATCH 28/29] octeontx: Add support for OcteonTX SoC platforms
From: Suneel Garapati This patch adds support for all OcteonTX 81xx/83xx boards from Marvell. For 81xx boards, use octeontx_81xx_defconfig and for 83xx boards, use octeontx_83xx_defconfig. Signed-off-by: Suneel Garapati --- arch/arm/Kconfig | 9 + arch/arm/Makefile | 1 + arch/arm/mach-octeontx/Kconfig | 23 +++ arch/arm/mach-octeontx/Makefile| 9 + arch/arm/mach-octeontx/clock.c | 35 arch/arm/mach-octeontx/cpu.c | 76 +++ arch/arm/mach-octeontx/lowlevel_init.S | 33 +++ board/Marvell/octeontx/Kconfig | 14 ++ board/Marvell/octeontx/MAINTAINERS | 9 + board/Marvell/octeontx/Makefile| 9 + board/Marvell/octeontx/board-fdt.c | 271 + board/Marvell/octeontx/board.c | 137 + board/Marvell/octeontx/smc.c | 30 +++ board/Marvell/octeontx/soc-utils.c | 53 + configs/octeontx_81xx_defconfig| 133 configs/octeontx_83xx_defconfig| 130 include/configs/octeontx_common.h | 98 + 17 files changed, 1070 insertions(+) create mode 100644 arch/arm/mach-octeontx/Kconfig create mode 100644 arch/arm/mach-octeontx/Makefile create mode 100644 arch/arm/mach-octeontx/clock.c create mode 100644 arch/arm/mach-octeontx/cpu.c create mode 100644 arch/arm/mach-octeontx/lowlevel_init.S create mode 100644 board/Marvell/octeontx/Kconfig create mode 100644 board/Marvell/octeontx/MAINTAINERS create mode 100644 board/Marvell/octeontx/Makefile create mode 100644 board/Marvell/octeontx/board-fdt.c create mode 100644 board/Marvell/octeontx/board.c create mode 100644 board/Marvell/octeontx/smc.c create mode 100644 board/Marvell/octeontx/soc-utils.c create mode 100644 configs/octeontx_81xx_defconfig create mode 100644 configs/octeontx_83xx_defconfig create mode 100644 include/configs/octeontx_common.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 629c5e8c2d..ebe180ad90 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1618,6 +1618,13 @@ config ARCH_ROCKCHIP imply TPL_SYSRESET imply USB_FUNCTION_FASTBOOT +config ARCH_OCTEONTX + bool "Support OcteonTX SoCs" + select DM + select ARM64 + select OF_CONTROL + select BOARD_LATE_INIT + select SYS_CACHE_SHIFT_7 config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 @@ -1695,6 +1702,7 @@ source "arch/arm/cpu/arm926ejs/lpc32xx/Kconfig" source "arch/arm/mach-mvebu/Kconfig" +source "arch/arm/mach-octeontx/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig" source "arch/arm/mach-imx/mx2/Kconfig" @@ -1772,6 +1780,7 @@ source "board/bosch/guardian/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" +source "board/Marvell/octeontx/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5384981c17..271ada99e8 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -79,6 +79,7 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_STM32)+= stm32 machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_TEGRA)+= tegra +machine-$(CONFIG_ARCH_OCTEONTX)+= octeontx machine-$(CONFIG_ARCH_UNIPHIER)+= uniphier machine-$(CONFIG_ARCH_ZYNQ)+= zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp diff --git a/arch/arm/mach-octeontx/Kconfig b/arch/arm/mach-octeontx/Kconfig new file mode 100644 index 00..28ecf9821f --- /dev/null +++ b/arch/arm/mach-octeontx/Kconfig @@ -0,0 +1,23 @@ +if ARCH_OCTEONTX + +choice + prompt "OcteonTX board select" + optional + +config TARGET_OCTEONTX_81XX + bool "Marvell OcteonTX CN81XX" + +config TARGET_OCTEONTX_83XX + bool "Marvell OcteonTX CN83XX" + +endchoice + +config SYS_SOC + string + default "octeontx" + +config SYS_PCI_64BIT + bool + default y + +endif diff --git a/arch/arm/mach-octeontx/Makefile b/arch/arm/mach-octeontx/Makefile new file mode 100644 index 00..20cb48ad92 --- /dev/null +++ b/arch/arm/mach-octeontx/Makefile @@ -0,0 +1,9 @@ +#/* SPDX-License-Identifier:GPL-2.0 +# * +# * Copyright (C) 2018 Marvell International Ltd. +# * +# * https://spdx.org/licenses +# */ + +obj-y += lowlevel_init.o clock.o cpu.o + diff --git a/arch/arm/mach-octeontx/clock.c b/arch/arm/mach-octeontx/clock.c new file mode 100644 index 00..9da21077ec --- /dev/null +++ b/arch/arm/mach-octeontx/clock.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier:GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include + +/** + * Returns the I/O clock speed
[U-Boot] [RFC PATCH 17/29] drivers: ata: ahci: add BAR index quirk for OcteonTX
From: Suneel Garapati
For SATA controller found on OcteonTX SoC's, use
non-standard PCI BAR0 instead of BAR5.
Signed-off-by: Suneel Garapati
---
drivers/ata/ahci.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 5f929700c0..f8fd2043e3 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1193,10 +1193,17 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong
base)
int ahci_probe_scsi_pci(struct udevice *ahci_dev)
{
ulong base;
+ u16 vendor, device;
base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
PCI_REGION_MEM);
+ dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, );
+ dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, );
+
+ if (vendor == 0x177d && device == 0xa01c)
+ base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
+PCI_REGION_MEM);
return ahci_probe_scsi(ahci_dev, base);
}
#endif
--
2.23.0
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[U-Boot] [RFC PATCH 15/29] drivers: ata: ahci: update max id if it is more than available ports
From: Suneel Garapati After check for maximum between max id and available ports, also check if available port count is less than max id and update. Signed-off-by: Suneel Garapati --- drivers/ata/ahci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 21a89eba5a..ca075b58bc 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -1177,6 +1177,9 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base) */ uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports, uc_plat->max_id); + /* If port count is less than max_id, update max_id */ + if (uc_priv->n_ports < uc_plat->max_id) + uc_plat->max_id = uc_priv->n_ports; return 0; } -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 16/29] drivers: ata: ahci: fill upper 32bit buffer address in sg descriptor
From: Suneel Garapati For platforms that support 64bit physical address, fill upper 32bit of buffer address in scatter-gather descriptor. This is needed for platforms with more than 4GB DRAM. Signed-off-by: Suneel Garapati --- drivers/ata/ahci.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index ca075b58bc..5f929700c0 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -506,6 +506,11 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, ahci_sg->addr = cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); ahci_sg->addr_hi = 0; +#ifdef CONFIG_PHYS_64BIT + ahci_sg->addr_hi = + cpu_to_le32((u32)(((u64)(buf + i * MAX_DATA_BYTE_COUNT) + >> 16) >> 16)); +#endif ahci_sg->flags_size = cpu_to_le32(0x3f & (buf_len < MAX_DATA_BYTE_COUNT ? (buf_len - 1) -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 29/29] octeontx2: Add support for OcteonTX2 SoC platforms
From: Suneel Garapati This patch adds support for all OcteonTX2 96xx/95xx boards from Marvell. For 96xx boards, use octeontx_96xx_defconfig and for 95xx boards, use octeontx_95xx_defconfig. Signed-off-by: Suneel Garapati --- arch/arm/Kconfig| 13 ++ arch/arm/Makefile | 1 + arch/arm/mach-octeontx2/Kconfig | 23 +++ arch/arm/mach-octeontx2/Makefile| 9 + arch/arm/mach-octeontx2/clock.c | 35 arch/arm/mach-octeontx2/config.mk | 4 + arch/arm/mach-octeontx2/cpu.c | 72 arch/arm/mach-octeontx2/lowlevel_init.S | 33 board/Marvell/octeontx2/Kconfig | 15 ++ board/Marvell/octeontx2/MAINTAINERS | 9 + board/Marvell/octeontx2/Makefile| 9 + board/Marvell/octeontx2/board-fdt.c | 155 board/Marvell/octeontx2/board.c | 232 board/Marvell/octeontx2/smc.c | 62 +++ board/Marvell/octeontx2/soc-utils.c | 49 + configs/octeontx2_95xx_defconfig| 105 +++ configs/octeontx2_96xx_defconfig| 131 + include/configs/octeontx2_95xx.h| 80 include/configs/octeontx2_96xx.h| 90 + 19 files changed, 1127 insertions(+) create mode 100644 arch/arm/mach-octeontx2/Kconfig create mode 100644 arch/arm/mach-octeontx2/Makefile create mode 100644 arch/arm/mach-octeontx2/clock.c create mode 100644 arch/arm/mach-octeontx2/config.mk create mode 100644 arch/arm/mach-octeontx2/cpu.c create mode 100644 arch/arm/mach-octeontx2/lowlevel_init.S create mode 100644 board/Marvell/octeontx2/Kconfig create mode 100644 board/Marvell/octeontx2/MAINTAINERS create mode 100644 board/Marvell/octeontx2/Makefile create mode 100644 board/Marvell/octeontx2/board-fdt.c create mode 100644 board/Marvell/octeontx2/board.c create mode 100644 board/Marvell/octeontx2/smc.c create mode 100644 board/Marvell/octeontx2/soc-utils.c create mode 100644 configs/octeontx2_95xx_defconfig create mode 100644 configs/octeontx2_96xx_defconfig create mode 100644 include/configs/octeontx2_95xx.h create mode 100644 include/configs/octeontx2_96xx.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ebe180ad90..2b43e2459e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1625,6 +1625,15 @@ config ARCH_OCTEONTX select OF_CONTROL select BOARD_LATE_INIT select SYS_CACHE_SHIFT_7 + +config ARCH_OCTEONTX2 + bool "Support OcteonTX2 SoCs" + select DM + select ARM64 + select OF_CONTROL + select BOARD_LATE_INIT + select SYS_CACHE_SHIFT_7 + config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 @@ -1703,6 +1712,9 @@ source "arch/arm/cpu/arm926ejs/lpc32xx/Kconfig" source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/mach-octeontx/Kconfig" + +source "arch/arm/mach-octeontx2/Kconfig" + source "arch/arm/cpu/armv7/ls102xa/Kconfig" source "arch/arm/mach-imx/mx2/Kconfig" @@ -1781,6 +1793,7 @@ source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/Marvell/octeontx/Kconfig" +source "board/Marvell/octeontx2/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 271ada99e8..80c7c61061 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -80,6 +80,7 @@ machine-$(CONFIG_STM32) += stm32 machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_TEGRA)+= tegra machine-$(CONFIG_ARCH_OCTEONTX)+= octeontx +machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2 machine-$(CONFIG_ARCH_UNIPHIER)+= uniphier machine-$(CONFIG_ARCH_ZYNQ)+= zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp diff --git a/arch/arm/mach-octeontx2/Kconfig b/arch/arm/mach-octeontx2/Kconfig new file mode 100644 index 00..8e5cb0f638 --- /dev/null +++ b/arch/arm/mach-octeontx2/Kconfig @@ -0,0 +1,23 @@ +if ARCH_OCTEONTX2 + +choice + prompt "OcteonTX2 board select" + optional + +config TARGET_OCTEONTX2_95XX + bool "Marvell OcteonTX2 CN95XX" + +config TARGET_OCTEONTX2_96XX + bool "Marvell OcteonTX2 CN96XX" + +endchoice + +config SYS_SOC + string + default "octeontx2" + +config SYS_PCI_64BIT + bool + default y + +endif diff --git a/arch/arm/mach-octeontx2/Makefile b/arch/arm/mach-octeontx2/Makefile new file mode 100644 index 00..c3192343dd --- /dev/null +++ b/arch/arm/mach-octeontx2/Makefile @@ -0,0 +1,9 @@ +#/* +# * Copyright (C) 2018 Marvell International Ltd. +# * +# * SPDX-License-Identifier:GPL-2.0 +# * https://spdx.org/licenses +# */ + +obj-y += lowlevel_init.o clock.o cpu.o + diff --git a/arch/arm/mach-octeontx2/clock.c
[U-Boot] [RFC PATCH 09/29] drivers: pci-uclass: add VF map_bar support for Enhanced Allocation
From: Suneel Garapati
Makes dm_pci_map_bar API available for Virtual function PCI devices
based on SR-IOV capability which support Enhanced Allocation.
Signed-off-by: Suneel Garapati
---
drivers/pci/pci-uclass.c | 46 +++-
include/pci.h| 3 +++
2 files changed, 44 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 3be49c7115..f9823231b1 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1359,13 +1359,19 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev,
phys_addr_t phys_addr,
}
static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
- int ea_off)
+ int ea_off, struct pci_child_platdata *pdata)
{
int ea_cnt, i, entry_size;
int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
u32 ea_entry;
phys_addr_t addr;
+ /* In case of Virtual Function devices, device is Physical function,
+* so pdata will point to required VF specific data.
+*/
+ if (pdata->is_virtfn)
+ bar_id += PCI_EA_BEI_VF_BAR0;
+
/* EA capability structure header */
dm_pci_read_config32(dev, ea_off, _entry);
ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
@@ -1388,6 +1394,26 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int
bar, int flags,
addr |= ((u64)ea_entry) << 32;
}
+ /* In case of Virtual Function devices using BAR
+* base and size, add offset for VFn BAR(1, 2, 3...n)
+*/
+ if (pdata->is_virtfn) {
+ size_t sz;
+
+ /* MaxOffset, 1st DW */
+ dm_pci_read_config32(dev, ea_off + 8, _entry);
+ sz = ea_entry & PCI_EA_FIELD_MASK;
+ /* Fill up lower 2 bits */
+ sz |= (~PCI_EA_FIELD_MASK);
+ if (ea_entry & PCI_EA_IS_64) {
+ /* MaxOffset 2nd DW */
+ dm_pci_read_config32(dev, ea_off + 16,
+_entry);
+ sz |= ((u64)ea_entry) << 32;
+ }
+ addr += (pdata->virtid - 1) * (sz + 1);
+ }
+
/* size ignored for now */
return map_physmem(addr, 0, flags);
}
@@ -1400,17 +1426,27 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int
flags)
pci_addr_t pci_bus_addr;
u32 bar_response;
int ea_off;
+ struct udevice *udev = dev;
+ struct pci_child_platdata *pdata = dev_get_parent_platdata(dev);
+
+ /* In case of Virtual Function devices, use PF udevice
+* as EA capability is defined in Physical Function
+*/
+ if (pdata->is_virtfn)
+ udev = pdata->pfdev;
/*
* if the function supports Enhanced Allocation use that instead of
* BARs
+* Incase of virtual functions, pdata will help read VF BEI
+* and EA entry size.
*/
- ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
+ ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
if (ea_off)
- return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
+ return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
/* read BAR address */
- dm_pci_read_config32(dev, bar, _response);
+ dm_pci_read_config32(udev, bar, _response);
pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
/*
@@ -1419,7 +1455,7 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int
flags)
* linear mapping. In the future, this could read the BAR size
* and pass that as the size if needed.
*/
- return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
+ return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
}
static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
diff --git a/include/pci.h b/include/pci.h
index 1343d0e9fb..27819e86f5 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -465,6 +465,9 @@
#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
#define PCI_EA_ES 0x0007 /* Entry Size */
#define PCI_EA_BEI0x00f0 /* BAR Equivalent Indicator */
+/* 9-14 map to VF BARs 0-5 respectively */
+#define PCI_EA_BEI_VF_BAR09
+#define PCI_EA_BEI_VF_BAR514
/* Base, MaxOffset registers */
/* bit 0 is reserved */
#define PCI_EA_IS_64 0x0002 /* 64-bit field flag */
--
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[U-Boot] [RFC PATCH 24/29] drivers: mtd: nand: add NAND controller driver for OcteonTX
From: Suneel Garapati
Adds support for NAND controllers found on OcteonTX or
OcteonTX2 SoC platforms. Also includes driver to support
Hardware ECC using BCH HW engine found on these platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
---
drivers/mtd/nand/raw/Kconfig | 16 +
drivers/mtd/nand/raw/Makefile|2 +
drivers/mtd/nand/raw/octeontx_bch.c | 424
drivers/mtd/nand/raw/octeontx_bch.h | 142 ++
drivers/mtd/nand/raw/octeontx_bch_regs.h | 169 ++
drivers/mtd/nand/raw/octeontx_nand.c | 2261 ++
6 files changed, 3014 insertions(+)
create mode 100644 drivers/mtd/nand/raw/octeontx_bch.c
create mode 100644 drivers/mtd/nand/raw/octeontx_bch.h
create mode 100644 drivers/mtd/nand/raw/octeontx_bch_regs.h
create mode 100644 drivers/mtd/nand/raw/octeontx_nand.c
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 2000826c79..a173636116 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -292,6 +292,22 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
This flag prevent U-boot reconfigure NAND flash controller and reuse
the NAND timing from 1st stage bootloader.
+config NAND_OCTEONTX
+ bool "Support for OcteonTX NAND controller"
+ select SYS_NAND_SELF_INIT
+ imply CMD_NAND
+ help
+This enables Nand flash controller hardware found on the OcteonTX
+processors.
+
+config NAND_OCTEONTX_HW_ECC
+ bool "Support Hardware ECC for OcteonTX NAND controller"
+ depends on NAND_OCTEONTX
+ default y
+ help
+This enables Hardware BCH engine found on the OcteonTX processors to
+support ECC for NAND flash controller.
+
config NAND_STM32_FMC2
bool "Support for NAND controller on STM32MP SoCs"
depends on ARCH_STM32MP
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 9337f6482e..24c51b6924 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -58,6 +58,8 @@ obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o
+obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o
+obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
diff --git a/drivers/mtd/nand/raw/octeontx_bch.c
b/drivers/mtd/nand/raw/octeontx_bch.c
new file mode 100644
index 00..db6c948320
--- /dev/null
+++ b/drivers/mtd/nand/raw/octeontx_bch.c
@@ -0,0 +1,424 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "octeontx_bch.h"
+
+#ifdef DEBUG
+# undef CONFIG_LOGLEVEL
+# define CONFIG_LOGLEVEL 8
+#endif
+
+LIST_HEAD(octeontx_bch_devices);
+static unsigned int num_vfs = BCH_NR_VF;
+static void *bch_pf;
+static void *bch_vf;
+static void *token;
+static bool bch_pf_initialized;
+static bool bch_vf_initialized;
+
+static int pci_enable_sriov(struct udevice *dev, int nr_virtfn)
+{
+ int ret;
+
+ ret = pci_sriov_init(dev, nr_virtfn);
+ if (ret)
+ printf("%s(%s): pci_sriov_init returned %d\n", __func__,
+ dev->name, ret);
+ return ret;
+}
+
+void *octeontx_bch_getv(void)
+{
+ if (!bch_vf)
+ return NULL;
+ if (bch_vf_initialized && bch_pf_initialized)
+ return bch_vf;
+ else
+ return NULL;
+}
+
+void octeontx_bch_putv(void *token)
+{
+ bch_vf_initialized = !!token;
+ bch_vf = token;
+}
+
+void *octeontx_bch_getp(void)
+{
+ return token;
+}
+
+void octeontx_bch_putp(void *token)
+{
+ bch_pf = token;
+ bch_pf_initialized = !!token;
+}
+
+static int do_bch_init(struct bch_device *bch)
+{
+ return 0;
+}
+
+static void bch_reset(struct bch_device *bch)
+{
+ writeq(1, bch->reg_base + BCH_CTL);
+ mdelay(2);
+}
+
+static void bch_disable(struct bch_device *bch)
+{
+ writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C);
+ writeq(~0ull, bch->reg_base + BCH_ERR_INT);
+ bch_reset(bch);
+}
+
+static u32 bch_check_bist_status(struct bch_device *bch)
+{
+ return readq(bch->reg_base + BCH_BIST_RESULT);
+}
+
+static int bch_device_init(struct bch_device *bch)
+{
+ u64 bist;
+ int rc;
+
+ debug("%s: Resetting...\n", __func__);
+ /* Reset the PF when probed first */
+ bch_reset(bch);
+
+ debug("%s: Checking BIST...\n", __func__);
+ /* Check BIST status */
+ bist = (u64)bch_check_bist_status(bch);
+ if (bist)
[U-Boot] [RFC PATCH 22/29] drivers: mmc: remove static qualifier on mmc_power_init
From: Suneel Garapati
For platforms with multiple slot support like OcteonTX,
this is invoked per slot.
Signed-off-by: Suneel Garapati
---
drivers/mmc/mmc.c | 2 +-
include/mmc.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f683b52ead..68d6c0d658 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2640,7 +2640,7 @@ __weak void board_mmc_power_init(void)
}
#endif
-static int mmc_power_init(struct mmc *mmc)
+int mmc_power_init(struct mmc *mmc)
{
#if CONFIG_IS_ENABLED(DM_MMC)
#if CONFIG_IS_ENABLED(DM_REGULATOR)
diff --git a/include/mmc.h b/include/mmc.h
index 1a9efe4c38..360bc0e225 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -713,6 +713,7 @@ int mmc_unbind(struct udevice *dev);
int mmc_initialize(bd_t *bis);
int mmc_init_device(int num);
int mmc_init(struct mmc *mmc);
+int mmc_power_init(struct mmc *mmc);
int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
--
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[U-Boot] [RFC PATCH 21/29] drivers: spi: add SPI controller driver for OcteonTX
From: Suneel Garapati
Adds support for SPI controllers found on OcteonTX or
OcteonTX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
---
drivers/spi/Kconfig| 6 +
drivers/spi/Makefile | 1 +
drivers/spi/octeontx_spi.c | 750 +
3 files changed, 757 insertions(+)
create mode 100644 drivers/spi/octeontx_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b8ca2bdedd..e521f10015 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -175,6 +175,12 @@ config MVEBU_A3700_SPI
used to access the SPI NOR flash on platforms embedding this
Marvell IP core.
+config OCTEONTX_SPI
+ bool "OcteonTX SPI driver"
+ help
+ Enable the OcteonTX SPI driver. This driver can be used to
+ access the SPI NOR flash on OcteonTX or OcteonTX2 SoC platforms.
+
config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ae4f2958f8..296eb11da8 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
+obj-$(CONFIG_OCTEONTX_SPI) += octeontx_spi.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
diff --git a/drivers/spi/octeontx_spi.c b/drivers/spi/octeontx_spi.c
new file mode 100644
index 00..1fb4989349
--- /dev/null
+++ b/drivers/spi/octeontx_spi.c
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#if defined(CONFIG_ARCH_OCTEONTX2)
+#include
+#include
+#define USE_TBI_CLK
+#endif
+
+#define OCTEONTX_SPI_MAX_BYTES 9
+#define OCTEONTX_SPI_MAX_CLOCK_HZ 5000
+
+#define OCTEONTX2_TBI_CLK 1
+
+#define OCTEONTX_SPI_NUM_CS4
+
+#define OCTEONTX_SPI_CS_VALID(cs) ((cs) < OCTEONTX_SPI_NUM_CS)
+
+#define MPI_CFG0x1000
+#define MPI_STS0x1008
+#define MPI_TX 0x1010
+#define MPI_XMIT 0x1018
+#define MPI_WIDE_DAT 0x1040
+#define MPI_IO_CTL 0x1048
+#define MPI_DAT(X) (0x1080 + ((X) << 3))
+#define MPI_WIDE_BUF(X)(0x1800 + ((X) << 3))
+#define MPI_CYA_CFG0x2000
+#define MPI_CLKEN 0x2080
+
+union mpi_cfg {
+ u64 u;
+ struct mpi_cfg_s {
+ /** MPI/SPI enable, 0 = pins are tristated, 1 = pins driven */
+ u64 enable :1;
+ /**
+* Clock idle low/clock invert
+* 0 = SPI_CLK idles high, first transition is high-to-low.
+* This correspondes to SPI Block Guide options CPOL = 1,
+* CPHA = 0.
+* 1 = SPI_CLK idles low, first transition is low-to-high. This
+* corresponds to SPI Block Guide options CPOL = 0,
+* CPHA = 0.
+*/
+ u64 idlelo :1;
+ /**
+* Clock control.
+* 0 = Clock idles to value given by IDLELO after completion of
+* MPI/SPI transaction.
+* 1 = Clock never idles, requires SPI_CSn_L
+* deassertion/assertion between commands.
+*/
+ u64 clk_cont:1;
+ /**
+* Wire-or DO and DI.
+* 0 = SPI_DO and SPI_DI are separate wires (SPI). SPI_DO pin
+* is always driven.
+* 1 = SPI_DO/DI is all from SPI_DO pin (MPI). SPI_DO pin is
+* tristated when not transmitting. If WIREOR = 1, SPI_DI
+* pin is not used by the MPI/SPI engine.
+*/
+ u64 wireor :1;
+ /** 0 = shift MSB first, 1 = shift LSB first */
+ u64 lsbfirst:1;
+ u64 cs_sticky :1; /** cs sticky bit */
+ u64 rsvd:1; /** Reserved */
+ /**
+* SPI_CSn_L high. 1 = SPI_CSn_L is asserted high,
+* 0 = SPI_CS_n asserted low.
+*/
+ u64 cshi:1;
+ /**
+* When set, guarantees idle coprocessor-clock cycles between
+* commands.
+*/
+ u64 idleclks:2;
+ /**
+* Tristate TX. Set to 1 to tristate SPI_DO when not
+*
[U-Boot] [RFC PATCH 18/29] drivers: pci: add PCI controller driver for OcteonTX
From: Suneel Garapati
Adds support for PCI ECAM/PEM controllers found on OcteonTX
or OcteonTX2 SoC platforms.
Signed-off-by: Suneel Garapati
---
drivers/pci/Kconfig| 8 +
drivers/pci/Makefile | 1 +
drivers/pci/pci_octeontx.c | 538 +
3 files changed, 547 insertions(+)
create mode 100644 drivers/pci/pci_octeontx.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 752439afcf..e865a06749 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -115,6 +115,14 @@ config PCI_TEGRA
with a total of 5 lanes. Some boards require this for Ethernet
support to work (e.g. beaver, jetson-tk1).
+config PCI_OCTEONTX
+ bool "OcteonTX PCI support"
+ depends on (ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ help
+ Enable support for the OcteonTX/TX2 SoC family ECAM/PEM controllers.
+ These controllers provide PCI configuration access to all on-board
+ peripherals so it should only be disabled for testing purposes
+
config PCI_XILINX
bool "Xilinx AXI Bridge for PCI Express"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index b1d3dc8610..7119d8bcb2 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -40,3 +40,4 @@ obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
diff --git a/drivers/pci/pci_octeontx.c b/drivers/pci/pci_octeontx.c
new file mode 100644
index 00..d754f98bbd
--- /dev/null
+++ b/drivers/pci/pci_octeontx.c
@@ -0,0 +1,538 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#if defined(CONFIG_ARCH_OCTEONTX2)
+
+#define PEM_CFG_WR 0x18
+#define PEM_CFG_RD 0x20
+
+#define PCIERC_RASDP_DE_ME 0x440
+#define PCIERC_RASDP_EP_CTL0x420
+#define PCIERC_RAS_EINJ_EN 0x348
+#define PCIERC_RAS_EINJ_CTL6PE 0x3A4
+#define PCIERC_RAS_EINJ_CTL6_CMPP0 0x364
+#define PCIERC_RAS_EINJ_CTL6_CMPV0 0x374
+#define PCIERC_RAS_EINJ_CTL6_CHGP1 0x388
+#define PCIERC_RAS_EINJ_CTL6_CHGV1 0x398
+
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct octeontx_pci {
+ unsigned int type;
+
+ struct fdt_resource cfg;
+ struct fdt_resource bus;
+#if defined(CONFIG_ARCH_OCTEONTX2)
+ struct fdt_resource pem;
+#endif
+};
+
+static int pci_octeontx_ecam_read_config(struct udevice *bus, pci_dev_t bdf,
+uint offset, ulong *valuep,
+enum pci_size_t size)
+{
+ struct octeontx_pci *pcie = (void *)dev_get_priv(bus);
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
+ uintptr_t address;
+ u32 b, d, f;
+
+ b = PCI_BUS(bdf) + pcie->bus.start - hose->first_busno;
+ d = PCI_DEV(bdf);
+ f = PCI_FUNC(bdf);
+
+ address = (b << 20) | (d << 15) | (f << 12) | offset;
+
+ address += pcie->cfg.start;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = readb(address);
+ break;
+ case PCI_SIZE_16:
+ *valuep = readw(address);
+ break;
+ case PCI_SIZE_32:
+ *valuep = readl(address);
+ break;
+ };
+
+ debug("%02x.%02x.%02x: u%d %x -> %lx\n",
+ b, d, f, size, offset, *valuep);
+ return 0;
+}
+
+static int pci_octeontx_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong valuep,
+ enum pci_size_t size)
+{
+ struct octeontx_pci *pcie = (void *)dev_get_priv(bus);
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
+ uintptr_t address;
+ u32 b, d, f;
+
+ b = PCI_BUS(bdf) + pcie->bus.start - hose->first_busno;
+ d = PCI_DEV(bdf);
+ f = PCI_FUNC(bdf);
+
+ address = (b << 20) | (d << 15) | (f << 12) | offset;
+
+ address += pcie->cfg.start;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ writeb(valuep, address);
+ break;
+ case PCI_SIZE_16:
+ writew(valuep, address);
+ break;
+ case PCI_SIZE_32:
+ writel(valuep, address);
+ break;
+ };
+
+ debug("%02x.%02x.%02x: u%d %x <- %lx\n",
+ b, d, f, size, offset, valuep);
+ return 0;
+}
+
+static int pci_octeontx_pem_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct octeontx_pci *pcie = (void *)dev_get_priv(bus);
+ struct
[U-Boot] [RFC PATCH 19/29] drivers: gpio: add GPIO controller driver for OcteonTX
From: Suneel Garapati
Adds support for GPIO controllers found on OcteonTX or
OcteonTX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
---
drivers/gpio/Kconfig | 7 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/octeontx_gpio.c | 218 +++
3 files changed, 226 insertions(+)
create mode 100644 drivers/gpio/octeontx_gpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c1ad5d64a3..91265180d3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -276,6 +276,13 @@ config PIC32_GPIO
help
Say yes here to support Microchip PIC32 GPIOs.
+config OCTEONTX_GPIO
+ bool "OcteonTX GPIO driver"
+ depends on DM_GPIO && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ default y
+ help
+ Say yes here to support OcteonTX GPIOs.
+
config STM32_GPIO
bool "ST STM32 GPIO driver"
depends on DM_GPIO && (STM32 || ARCH_STM32MP)
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ccc49e2eb0..d7651bff4b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o
obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o
obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
+obj-$(CONFIG_OCTEONTX_GPIO)+= octeontx_gpio.o
obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
diff --git a/drivers/gpio/octeontx_gpio.c b/drivers/gpio/octeontx_gpio.c
new file mode 100644
index 00..d012044c47
--- /dev/null
+++ b/drivers/gpio/octeontx_gpio.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ *
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/** Returns the bit value to write or read based on the offset */
+#define GPIO_BIT(x)(1ULL << ((x) & 0x3f))
+
+#define GPIO_RX_DAT(0x0)
+#define GPIO_TX_SET(0x8)
+#define GPIO_TX_CLR(0x10)
+#define GPIO_CONST (0x90)
+#define GPIO_RX1_DAT (0x1400)
+#define GPIO_TX1_SET (0x1408)
+#define GPIO_TX1_CLR (0x1410)
+
+/** Returns the offset to the output register based on the offset and value */
+#define GPIO_TX_REG(offset, value) \
+ ((offset) >= 64 ? ((value) ? GPIO_TX1_SET : GPIO_TX1_CLR) : \
+ ((value) ? GPIO_TX_SET : GPIO_TX_CLR))
+
+/** Returns the offset to the input data register based on the offset */
+#define GPIO_RX_DAT_REG(offset) (((offset) >= 64) ? GPIO_RX1_DAT : GPIO_RX_DAT)
+
+/** Returns the bit configuration register based on the offset */
+#define GPIO_BIT_CFG(x)(0x400 + 8 * (x))
+#define GPIO_BIT_CFG_FN(x) (((x) >> 16) & 0x3ff)
+#define GPIO_BIT_CFG_TX_OE(x) ((x) & 0x1)
+#define GPIO_BIT_CFG_RX_DAT(x) ((x) & 0x1)
+
+/** PCI ID on NCB bus */
+#define PCI_DEVICE_ID_OCTEONTX_GPIO0xa00a
+
+union gpio_const {
+ u64 u;
+ struct {
+ u64 gpios:8;/** Number of GPIOs implemented */
+ u64 pp:8; /** Number of PP vectors */
+ u64:48; /* Reserved */
+ } s;
+};
+
+struct octeontx_gpio {
+ void __iomem *baseaddr;
+};
+
+static int octeontx_gpio_dir_input(struct udevice *dev, unsigned int offset)
+{
+ struct octeontx_gpio *gpio = dev_get_priv(dev);
+
+ debug("%s(%s, %u)\n", __func__, dev->name, offset);
+ clrbits_le64(gpio->baseaddr + GPIO_BIT_CFG(offset),
+(0x3ffUL << 16) | 4UL | 2UL | 1UL);
+ return 0;
+}
+
+static int octeontx_gpio_dir_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct octeontx_gpio *gpio = dev_get_priv(dev);
+
+ debug("%s(%s, %u, %d)\n", __func__, dev->name, offset, value);
+ writeq(GPIO_BIT(offset), gpio->baseaddr + GPIO_TX_REG(offset, value));
+
+ clrsetbits_le64(gpio->baseaddr + GPIO_BIT_CFG(offset),
+ ((0x3ffUL << 16) | 4UL), 1UL);
+ return 0;
+}
+
+static int octeontx_gpio_get_value(struct udevice *dev,
+ unsigned int offset)
+{
+ struct octeontx_gpio *gpio = dev_get_priv(dev);
+ u64 reg = readq(gpio->baseaddr + GPIO_RX_DAT_REG(offset));
+
+ debug("%s(%s, %u): value: %d\n", __func__, dev->name, offset,
+ !!(reg & GPIO_BIT(offset)));
+
+ return !!(reg & GPIO_BIT(offset));
+}
+
+static int octeontx_gpio_set_value(struct udevice *dev,
+ unsigned int offset, int value)
+{
+
[U-Boot] [RFC PATCH 13/29] arch: include: octeontx: add headers for OcteonTX
From: Suneel Garapati
Signed-off-by: Suneel Garapati
---
arch/arm/include/asm/arch-octeontx/board.h| 121 ++
arch/arm/include/asm/arch-octeontx/clock.h| 25 +
.../asm/arch-octeontx/csrs/csrs-mio_emm.h | 1193 +
.../include/asm/arch-octeontx/csrs/csrs-xcv.h | 428 ++
arch/arm/include/asm/arch-octeontx/gpio.h |6 +
arch/arm/include/asm/arch-octeontx/smc.h | 20 +
arch/arm/include/asm/arch-octeontx/soc.h | 31 +
7 files changed, 1824 insertions(+)
create mode 100644 arch/arm/include/asm/arch-octeontx/board.h
create mode 100644 arch/arm/include/asm/arch-octeontx/clock.h
create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h
create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h
create mode 100644 arch/arm/include/asm/arch-octeontx/gpio.h
create mode 100644 arch/arm/include/asm/arch-octeontx/smc.h
create mode 100644 arch/arm/include/asm/arch-octeontx/soc.h
diff --git a/arch/arm/include/asm/arch-octeontx/board.h
b/arch/arm/include/asm/arch-octeontx/board.h
new file mode 100644
index 00..99a3b71534
--- /dev/null
+++ b/arch/arm/include/asm/arch-octeontx/board.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier:GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+
+#define MAX_LMAC_PER_BGX 4
+#define LMAC_CNT MAX_LMAC_PER_BGX
+
+#if defined(CONFIG_TARGET_OCTEONTX_81XX)
+
+/** Maximum number of BGX interfaces per CPU node */
+#define MAX_BGX_PER_NODE 3
+#define OCTEONTX_XCV /* RGMII Interface */
+
+#elif defined(CONFIG_TARGET_OCTEONTX_83XX)
+
+/** Maximum number of BGX interfaces per CPU node */
+#define MAX_BGX_PER_NODE 4
+
+#endif
+
+/** Reg offsets */
+#define RST_BOOT 0x87E006001600ULL
+
+/** Structure definitions */
+
+/**
+ * Register (RSL) rst_boot
+ *
+ * RST Boot Register This register is not accessible through ROM scripts;
+ * see SCR_WRITE32_S[ADDR].
+ */
+union rst_boot {
+ u64 u;
+ struct rst_boot_s {
+ u64 rboot_pin: 1;
+ u64 rboot: 1;
+ u64 reserved_2_32: 31;
+ u64 pnr_mul : 6;
+ u64 reserved_39 : 1;
+ u64 c_mul: 7;
+ u64 reserved_47_52 : 6;
+ u64 gpio_ejtag : 1;
+ u64 mcp_jtagdis : 1;
+ u64 dis_scan : 1;
+ u64 dis_huk : 1;
+ u64 vrm_err : 1;
+ u64 jt_tstmode : 1;
+ u64 ckill_ppdis : 1;
+ u64 trusted_mode : 1;
+ u64 reserved_61_62 : 2;
+ u64 chipkill : 1;
+ } s;
+ struct rst_boot_cn81xx {
+ u64 rboot_pin: 1;
+ u64 rboot: 1;
+ u64 lboot: 10;
+ u64 lboot_ext23 : 6;
+ u64 lboot_ext45 : 6;
+ u64 lboot_jtg: 1;
+ u64 lboot_ckill : 1;
+ u64 reserved_26_29 : 4;
+ u64 lboot_oci: 3;
+ u64 pnr_mul : 6;
+ u64 reserved_39 : 1;
+ u64 c_mul: 7;
+ u64 reserved_47_54 : 8;
+ u64 dis_scan : 1;
+ u64 dis_huk : 1;
+ u64 vrm_err : 1;
+ u64 jt_tstmode : 1;
+ u64 ckill_ppdis : 1;
+ u64 trusted_mode : 1;
+ u64 ejtagdis : 1;
+ u64 jtcsrdis : 1;
+ u64 chipkill : 1;
+ } cn81xx;
+ struct rst_boot_cn83xx {
+ u64 rboot_pin: 1;
+ u64 rboot: 1;
+ u64 lboot: 10;
+ u64 lboot_ext23 : 6;
+ u64 lboot_ext45 : 6;
+ u64 lboot_jtg: 1;
+ u64 lboot_ckill : 1;
+ u64 lboot_pf_flr : 4;
+ u64 lboot_oci: 3;
+ u64 pnr_mul
[U-Boot] [RFC PATCH 10/29] drivers: pci-uclass: Add support for Alternate-RoutingID capability
From: Suneel Garapati
If ARI capability is found on device, use it to update next function
number in bus scan and also helps to skip unnecessary bdf scans.
Signed-off-by: Suneel Garapati
---
drivers/pci/pci-uclass.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index f9823231b1..b02588b552 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -773,7 +773,7 @@ int pci_bind_bus_devices(struct udevice *bus)
ulong header_type;
pci_dev_t bdf, end;
bool found_multi;
- int ret;
+ int ret, ari_off;
found_multi = false;
end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
@@ -846,6 +846,22 @@ int pci_bind_bus_devices(struct udevice *bus)
pplat->vendor = vendor;
pplat->device = device;
pplat->class = class;
+
+ ari_off = dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
+ if (ari_off) {
+ u16 ari_cap;
+
+ /* Read Next Function number in ARI Cap Register */
+ dm_pci_read_config16(dev, ari_off + 4, _cap);
+ /* Update next scan on this function number,
+* subtract 1 in BDF to satisfy loop increment.
+*/
+ if (ari_cap & 0xff00) {
+ bdf = PCI_BDF(PCI_BUS(bdf), PCI_DEV(ari_cap),
+ PCI_FUNC(ari_cap));
+ bdf = bdf - 0x100;
+ }
+ }
}
return 0;
--
2.23.0
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[U-Boot] [RFC PATCH 11/29] include: arm: asm: io: add 64bit clrbits and setbits helpers
From: Suneel Garapati Signed-off-by: Suneel Garapati --- arch/arm/include/asm/io.h | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 723f3cf497..e87887c631 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -226,6 +226,14 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define setbits_8(addr, set) setbits(8, addr, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) +#define clrbits_be64(addr, clear) clrbits(be64, addr, clear) +#define setbits_be64(addr, set) setbits(be64, addr, set) +#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) + +#define clrbits_le64(addr, clear) clrbits(le64, addr, clear) +#define setbits_le64(addr, set) setbits(le64, addr, set) +#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) + /* * Now, pick up the machine-defined IO definitions */ -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 07/29] drivers: pci-uclass: add support for Enhanced Allocation in Bridges
From: Suneel Garapati
If Enhanced Allocation capability is present in bridges, use it
to read the fixed sub-ordinate bus number.
Signed-off-by: Suneel Garapati
---
drivers/pci/pci-uclass.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index f17e83565c..51f7135723 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -599,10 +599,20 @@ int dm_pci_hose_probe_bus(struct udevice *bus)
{
int sub_bus;
int ret;
+ int ea_pos;
+ u8 reg;
debug("%s\n", __func__);
- sub_bus = pci_get_bus_max() + 1;
+ ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
+
+ if (ea_pos) {
+ dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
+ );
+ sub_bus = reg;
+ } else {
+ sub_bus = pci_get_bus_max() + 1;
+ }
debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
dm_pciauto_prescan_setup_bridge(bus, sub_bus);
@@ -612,12 +622,15 @@ int dm_pci_hose_probe_bus(struct udevice *bus)
ret);
return ret;
}
- if (sub_bus != bus->seq) {
- printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
- __func__, bus->name, bus->seq, sub_bus);
- return -EPIPE;
+
+ if (!ea_pos) {
+ if (sub_bus != bus->seq) {
+ printf("%s: Internal error, bus '%s' got seq %d,
expected %d\n",
+ __func__, bus->name, bus->seq, sub_bus);
+ return -EPIPE;
+ }
+ sub_bus = pci_get_bus_max();
}
- sub_bus = pci_get_bus_max();
dm_pciauto_postscan_setup_bridge(bus, sub_bus);
return sub_bus;
--
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[U-Boot] [RFC PATCH 06/29] drivers: pci-uclass: add multi entry support for pci regions
From: Suneel Garapati
Enable PCI memory regions to be of multiple entry. This helps to
add support for SoC's like OcteonTX/TX2 where every peripheral is
on PCI bus.
Signed-off-by: Suneel Garapati
---
drivers/pci/Kconfig | 9 +
drivers/pci/pci-uclass.c | 2 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 19e7b50046..752439afcf 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -43,6 +43,15 @@ config PCI_PNP
help
Enable PCI memory and I/O space resource allocation and assignment.
+config PCI_REGION_MULTI_ENTRY
+ bool "Enable Multiple entries of MEMORY region for PCI"
+ depends on PCI || DM_PCI
+ default n
+ help
+ Enable PCI memory regions to be of multiple entry. This helps to
+ add support for SoC's like OcteonTX/TX2 where every peripheral is
+ on PCI bus.
+
config PCIE_ECAM_GENERIC
bool "Generic ECAM-based PCI host controller support"
default n
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 007b7472c6..f17e83565c 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -902,10 +902,12 @@ static void decode_regions(struct pci_controller *hose,
ofnode parent_node,
}
pos = -1;
+#if !CONFIG_IS_ENABLED(PCI_REGION_MULTI_ENTRY)
for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == type)
pos = i;
}
+#endif
if (pos == -1)
pos = hose->region_count++;
debug(" - type=%d, pos=%d\n", type, pos);
--
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[U-Boot] [RFC PATCH 12/29] drivers: rtc: ds1337: add driver model support
From: Suneel Garapati
Add DM support to dallas 1337 RTC driver.
Signed-off-by: Suneel Garapati
---
drivers/rtc/Kconfig | 7 ++
drivers/rtc/ds1337.c | 170 +++
2 files changed, 177 insertions(+)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8778cc7b26..c31c6a3368 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -54,6 +54,13 @@ config RTC_DS1307
Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and
compatible Real Time Clock devices.
+config RTC_DS1337
+ bool "Enable DS1337 driver"
+ depends on DM_RTC
+ help
+ Support for Dallas Semiconductor (now Maxim) DS1337/39 and DS1388 and
+ compatible Real Time Clock devices.
+
config RTC_ISL1208
bool "Enable ISL1208 driver"
depends on DM_RTC
diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c
index 9b31048e97..a1c63ffa08 100644
--- a/drivers/rtc/ds1337.c
+++ b/drivers/rtc/ds1337.c
@@ -1,8 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
* (C) Copyright 2001-2008
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
* Keith Outwater, keith_outwa...@mvis.com`
+ *
*/
/*
@@ -14,6 +17,10 @@
#include
#include
#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
/*
* RTC register addresses
@@ -59,6 +66,167 @@
#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
#define RTC_STAT_BIT_OSF 0x80/* Oscillator stop flag */
+#ifdef CONFIG_DM_RTC
+
+/*
+ * Helper functions
+ */
+static uchar dm_rtc_read(struct udevice *dev, uchar reg)
+{
+ return dm_i2c_reg_read(dev, reg);
+}
+
+static void dm_rtc_write(struct udevice *dev, uchar reg, uchar val)
+{
+ dm_i2c_reg_write(dev, reg, val);
+}
+
+static int ds1337_rtc_get(struct udevice *dev, struct rtc_time *tmp)
+{
+ int rel = 0;
+ uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
+
+ control = dm_rtc_read(dev, RTC_CTL_REG_ADDR);
+ status = dm_rtc_read(dev, RTC_STAT_REG_ADDR);
+ sec = dm_rtc_read(dev, RTC_SEC_REG_ADDR);
+ min = dm_rtc_read(dev, RTC_MIN_REG_ADDR);
+ hour = dm_rtc_read(dev, RTC_HR_REG_ADDR);
+ wday = dm_rtc_read(dev, RTC_DAY_REG_ADDR);
+ mday = dm_rtc_read(dev, RTC_DATE_REG_ADDR);
+ mon_cent = dm_rtc_read(dev, RTC_MON_REG_ADDR);
+ year = dm_rtc_read(dev, RTC_YR_REG_ADDR);
+
+ /* No century bit, assume year 2000 */
+#ifdef CONFIG_RTC_DS1388
+ mon_cent |= 0x80;
+#endif
+
+ debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x",
+ year, mon_cent, mday, wday);
+ debug(" hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
+ hour, min, sec, control, status);
+
+ if (status & RTC_STAT_BIT_OSF) {
+ printf("### Warning: RTC oscillator has stopped\n");
+ /* clear the OSF flag */
+ dm_rtc_write(dev, RTC_STAT_REG_ADDR,
+dm_rtc_read(dev, RTC_STAT_REG_ADDR) &
+~RTC_STAT_BIT_OSF);
+ rel = -1;
+ }
+
+ tmp->tm_sec = bcd2bin(sec & 0x7F);
+ tmp->tm_min = bcd2bin(min & 0x7F);
+ tmp->tm_hour = bcd2bin(hour & 0x3F);
+ tmp->tm_mday = bcd2bin(mday & 0x3F);
+ tmp->tm_mon = bcd2bin(mon_cent & 0x1F);
+ tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 2100 : 2000);
+ tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
+ tmp->tm_yday = 0;
+ tmp->tm_isdst = 0;
+
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ return rel;
+}
+
+static int ds1337_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
+{
+ uchar century;
+
+ debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ if (tmp->tm_year < 2000 || tmp->tm_year > 2199)
+ return -1;
+
+ dm_rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
+
+ /* Assume 20YY as base, to fix mismatch with linux */
+ century = (tmp->tm_year >= 2100) ? 0x80 : 0;
+ dm_rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon) | century);
+
+ dm_rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
+ dm_rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
+ dm_rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
+ dm_rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
+ dm_rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
+
+ return 0;
+}
+
+/*
+ * Reset the RTC. We also enable the oscillator output on the
+ * SQW/INTB* pin and program it for 32,768 Hz output. Note that
+ *
[U-Boot] [RFC PATCH 08/29] drivers: pci-uclass: add support for Single-Root I/O Virtualizaiton
From: Suneel Garapati
If SR-IOV capability is present, use it to initialize Virtual function
(VF) PCI device instances. pci_sriov_init function will read SR-IOV
registers to create VF devices under the PF PCI device and also bind
driver if available. This function needs to be invoked from Physical
function device driver which expects VF device support, creating
minimal impact on existing framework.
Signed-off-by: Suneel Garapati
---
drivers/pci/pci-uclass.c | 113 +++
include/pci.h| 18 +++
2 files changed, 131 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 51f7135723..3be49c7115 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1535,6 +1535,119 @@ int dm_pci_flr(struct udevice *dev)
return 0;
}
+int pci_sriov_init(struct udevice *pdev, int vf_en)
+{
+ u16 vendor, device;
+ struct udevice *bus;
+ struct udevice *dev;
+ pci_dev_t bdf;
+ u16 ctrl;
+ u16 num_vfs;
+ u16 total_vf;
+ u16 vf_offset;
+ u16 vf_stride;
+ int vf, ret;
+ int pos;
+
+ pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
+ if (!pos) {
+ printf("Error: SRIOV capability not found\n");
+ return -ENOENT;
+ }
+
+ dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, );
+
+ dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, _vf);
+ if (vf_en > total_vf)
+ vf_en = total_vf;
+ dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
+
+ ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
+ dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
+
+ dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, _vfs);
+ if (num_vfs > vf_en)
+ num_vfs = vf_en;
+
+ dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, _offset);
+ dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, _stride);
+
+ dm_pci_read_config16(pdev, PCI_VENDOR_ID, );
+ dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, );
+
+ bdf = dm_pci_get_bdf(pdev);
+
+ pci_get_bus(PCI_BUS(bdf), );
+
+ if (!bus)
+ return -ENODEV;
+
+ bdf += PCI_BDF(0, 0, vf_offset);
+
+ for (vf = 0; vf < num_vfs; vf++) {
+ struct pci_child_platdata *pplat;
+ ulong class;
+
+ pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
+ , PCI_SIZE_16);
+
+ debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
+ bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
+
+ /* Find this device in the device tree */
+ ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), );
+
+ if (ret == -ENODEV) {
+ struct pci_device_id find_id;
+
+ memset(_id, 0, sizeof(find_id));
+
+ find_id.vendor = vendor;
+ find_id.device = device;
+ find_id.class = class;
+
+ ret = pci_find_and_bind_driver(bus, _id,
+ bdf, );
+
+ if (ret)
+ return ret;
+ }
+
+ /* Update the platform data */
+ pplat = dev_get_parent_platdata(dev);
+ pplat->devfn = PCI_MASK_BUS(bdf);
+ pplat->vendor = vendor;
+ pplat->device = device;
+ pplat->class = class;
+ pplat->is_virtfn = true;
+ pplat->pfdev = pdev;
+ pplat->virtid = vf * vf_stride + vf_offset;
+
+ debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
+ __func__, dev->seq, dev->name, PCI_DEV(bdf),
+ PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
+ bdf += PCI_BDF(0, 0, vf_stride);
+ }
+
+ return 0;
+}
+
+int pci_sriov_get_totalvfs(struct udevice *pdev)
+{
+ u16 total_vf;
+ int pos;
+
+ pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
+ if (!pos) {
+ printf("Error: SRIOV capability not found\n");
+ return -ENOENT;
+ }
+
+ dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, _vf);
+
+ return total_vf;
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
diff --git a/include/pci.h b/include/pci.h
index 0b14842285..1343d0e9fb 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -475,6 +475,17 @@
#define PCI_EXP_DEVCAP_FLR 0x1000 /* Function Level Reset */
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
+/* Single Root I/O Virtualization Registers */
+#define PCI_SRIOV_CAP 0x04/* SR-IOV Capabilities
[U-Boot] [RFC PATCH 03/29] fdtdec: add API to read pci bus-range property
From: Suneel Garapati
Add fdtdec_get_pci_bus_range to read bus-range property
values.
Signed-off-by: Suneel Garapati
---
include/fdtdec.h | 12
lib/fdtdec.c | 16
2 files changed, 28 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index f1e58f9732..afbd22b25a 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -441,6 +441,18 @@ int fdtdec_get_pci_vendev(const void *blob, int node,
int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr,
u32 *bar);
+/**
+ * Look at the bus range property of a device node and return the pci bus
+ * range for this node.
+ * The property must hold one fdt_pci_addr with a length.
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param res the resource structure to return the bus range
+ */
+
+int fdtdec_get_pci_bus_range(const void *blob, int node,
+struct fdt_resource *res);
+
/**
* Look up a 32-bit integer property in a node and return it. The property
* must have at least 4 bytes of data. The value of the first cell is
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 17736ce665..fb61eda1fd 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -237,6 +237,22 @@ int fdtdec_get_pci_bar32(struct udevice *dev, struct
fdt_pci_addr *addr,
return 0;
}
+
+int fdtdec_get_pci_bus_range(const void *blob, int node,
+struct fdt_resource *res)
+{
+ const u32 *values;
+ int len;
+
+ values = fdt_getprop(blob, node, "bus-range", );
+ if (!values || len < sizeof(*values) * 2)
+ return -EINVAL;
+
+ res->start = be32_to_cpup(values++);
+ res->end = be32_to_cpup(values);
+
+ return 0;
+}
#endif
uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
--
2.23.0
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[U-Boot] [RFC PATCH 02/29] include: pci: Increase max pci region limit
From: Suneel Garapati Increase MAX_PCI_REGIONS limit from 7 to 10. For some SoC's like OcteonTX/TX2 where everything is on PCI bus there is need for extra entries to support required peripherals. Signed-off-by: Suneel Garapati --- include/pci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/pci.h b/include/pci.h index ff59ac0e69..0b14842285 100644 --- a/include/pci.h +++ b/include/pci.h @@ -567,7 +567,7 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); -#define MAX_PCI_REGIONS7 +#define MAX_PCI_REGIONS10 #define INDIRECT_TYPE_NO_PCIE_LINK 1 -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 04/29] drivers: pci-uclass: fix incorrect argument in map_sysmem
From: Suneel Garapati Minor spelling correction. Signed-off-by: Suneel Garapati --- drivers/pci/pci-uclass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 896cb6b23a..848ac5a65e 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1373,7 +1373,7 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, } /* size ignored for now */ - return map_physmem(addr, flags, 0); + return map_physmem(addr, 0, flags); } return 0; @@ -1399,7 +1399,7 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) /* * Pass "0" as the length argument to pci_bus_to_virt. The arg -* isn't actualy used on any platform because u-boot assumes a static +* isn't actually used on any platform because u-boot assumes a static * linear mapping. In the future, this could read the BAR size * and pass that as the size if needed. */ -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 05/29] drivers: pci-uclass: make DT subnode parse optional
From: Suneel Garapati Parse subnode DT properties only if parent node is valid. Otherwise, assert is triggered on ofnode_valid in ofnode_first_subnode from dev_for_each_subnode. Signed-off-by: Suneel Garapati --- drivers/pci/pci-uclass.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 848ac5a65e..007b7472c6 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -675,7 +675,8 @@ static int pci_find_and_bind_driver(struct udevice *parent, find_id->vendor, find_id->device); /* Determine optional OF node */ - pci_dev_find_ofnode(parent, bdf, ); + if (ofnode_valid(dev_ofnode(parent))) + pci_dev_find_ofnode(parent, bdf, ); start = ll_entry_start(struct pci_driver_entry, pci_driver_entry); n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry); -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 01/29] include: pci_ids: add vendor ID for Cavium
From: Suneel Garapati Signed-off-by: Suneel Garapati --- include/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/pci_ids.h b/include/pci_ids.h index bd59578ccb..f8b4f28996 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2360,6 +2360,8 @@ #define PCI_DEVICE_ID_ALTIMA_AC91000x03ea #define PCI_DEVICE_ID_ALTIMA_AC10030x03eb +#define PCI_VENDOR_ID_CAVIUM 0x177d + #define PCI_VENDOR_ID_BELKIN 0x1799 #define PCI_DEVICE_ID_BELKIN_F5D7010V7 0x701f -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 00/29] arm: Introduce Marvell/Cavium OcteonTX
This series will add support for OcteonTX and OcteonTX2 processsor based platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs include support for CN96XX and CN95XX. These SoC's have peripheral drivers based on PCI ECAM. Patches [1 -10] Add requied changes to PCI framework - [6] Add support for multi-memory region range - [7] EA in bridges - [8] SR-IOV [12] Add driver model support for RTC DS1337 driver [15 - 17] AHCI changes [18 - 27] Add OcteonTX drivers [28 - 29] Add OcteonTX/TX2 board files and configurations Suneel Garapati (29): include: pci_ids: add vendor ID for Cavium include: pci: Increase max pci region limit fdtdec: add API to read pci bus-range property drivers: pci-uclass: fix incorrect argument in map_sysmem drivers: pci-uclass: make DT subnode parse optional drivers: pci-uclass: add multi entry support for pci regions drivers: pci-uclass: add support for Enhanced Allocation in Bridges drivers: pci-uclass: add support for Single-Root I/O Virtualizaiton drivers: pci-uclass: add VF map_bar support for Enhanced Allocation drivers: pci-uclass: Add support for Alternate-RoutingID capability include: arm: asm: io: add 64bit clrbits and setbits helpers drivers: rtc: ds1337: add driver model support arch: include: octeontx: add headers for OcteonTX arch: include: octeontx2: add headers for OcteonTX2 drivers: ata: ahci: update max id if it is more than available ports drivers: ata: ahci: fill upper 32bit buffer address in sg descriptor drivers: ata: ahci: add BAR index quirk for OcteonTX drivers: pci: add PCI controller driver for OcteonTX drivers: gpio: add GPIO controller driver for OcteonTX drivers: i2c: add I2C controller driver for OcteonTX drivers: spi: add SPI controller driver for OcteonTX drivers: mmc: remove static qualifier on mmc_power_init drivers: mmc: add MMC controller driver for OcteonTX drivers: mtd: nand: add NAND controller driver for OcteonTX drivers: net: add NIC controller driver for OcteonTX drivers: net: add NIC controller driver for OcteonTX2 drivers: watchdog: add reset support for OcteonTX octeontx: Add support for OcteonTX SoC platforms octeontx2: Add support for OcteonTX2 SoC platforms arch/arm/Kconfig |22 + arch/arm/Makefile | 2 + arch/arm/include/asm/arch-octeontx/board.h| 121 + arch/arm/include/asm/arch-octeontx/clock.h|25 + .../asm/arch-octeontx/csrs/csrs-mio_emm.h | 1193 ++ .../include/asm/arch-octeontx/csrs/csrs-xcv.h | 428 + arch/arm/include/asm/arch-octeontx/gpio.h | 6 + arch/arm/include/asm/arch-octeontx/smc.h |20 + arch/arm/include/asm/arch-octeontx/soc.h |31 + arch/arm/include/asm/arch-octeontx2/board.h | 123 + arch/arm/include/asm/arch-octeontx2/clock.h |24 + .../asm/arch-octeontx2/csrs/csrs-cgx.h| 7835 .../asm/arch-octeontx2/csrs/csrs-lmt.h|60 + .../asm/arch-octeontx2/csrs/csrs-mio_emm.h| 1193 ++ .../asm/arch-octeontx2/csrs/csrs-nix.h| 10482 .../asm/arch-octeontx2/csrs/csrs-npa.h| 2296 .../asm/arch-octeontx2/csrs/csrs-npc.h| 1930 +++ .../asm/arch-octeontx2/csrs/csrs-rvu.h| 2430 arch/arm/include/asm/arch-octeontx2/gpio.h| 6 + arch/arm/include/asm/arch-octeontx2/smc-id.h |32 + arch/arm/include/asm/arch-octeontx2/smc.h |18 + arch/arm/include/asm/arch-octeontx2/soc.h |31 + arch/arm/include/asm/io.h | 8 + arch/arm/mach-octeontx/Kconfig|23 + arch/arm/mach-octeontx/Makefile | 9 + arch/arm/mach-octeontx/clock.c|35 + arch/arm/mach-octeontx/cpu.c |76 + arch/arm/mach-octeontx/lowlevel_init.S|33 + arch/arm/mach-octeontx2/Kconfig |23 + arch/arm/mach-octeontx2/Makefile | 9 + arch/arm/mach-octeontx2/clock.c |35 + arch/arm/mach-octeontx2/config.mk | 4 + arch/arm/mach-octeontx2/cpu.c |72 + arch/arm/mach-octeontx2/lowlevel_init.S |33 + board/Marvell/octeontx/Kconfig|14 + board/Marvell/octeontx/MAINTAINERS| 9 + board/Marvell/octeontx/Makefile | 9 + board/Marvell/octeontx/board-fdt.c| 271 + board/Marvell/octeontx/board.c| 137 + board/Marvell/octeontx/smc.c |30 + board/Marvell/octeontx/soc-utils.c|53 + board/Marvell/octeontx2/Kconfig |15 + board/Marvell/octeontx2/MAINTAINERS | 9 + board/Marvell/octeontx2/Makefile | 9 + board/Marvell/octeontx2/board-fdt.c | 155 + board/Marvell/octeontx2/board.c | 232 +
Re: [U-Boot] [EXT] Re: [RFC/RESEND 01/22] arm: introduce ARCH_THUNDERX
On Sun, Oct 27, 2019 at 10:34 PM Suneel Garapati wrote: > > Hi Matthias, > > Thanks for your patience. Sorry for the delay. > > I will post the patch-set tomorrow. > Suneel, I haven't seen anything yet but I'm happy to test this on our Newport boards running on CN8020/CN8030. We've been waiting quite a while. Is there some hold-up with posting a series? Post early and often as people say! I know Aaron has posted some info and questions regarding Octeon support but I assume you're working on OcteonTX (thunderx) which perhaps doesn't have that much overlap? Regards, Tim ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] rtc: rx8010js: add compatible string
Add compatible string used by Linux.
Allows for simpler syncing of device trees.
Signed-off-by: Robert Beckett
---
drivers/rtc/rx8010sj.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c
index 2876692a37..82c5185e2e 100644
--- a/drivers/rtc/rx8010sj.c
+++ b/drivers/rtc/rx8010sj.c
@@ -364,6 +364,7 @@ static const struct rtc_ops rx8010sj_rtc_ops = {
static const struct udevice_id rx8010sj_rtc_ids[] = {
{ .compatible = "epson,rx8010sj-rtc" },
+ { .compatible = "epson,rx8010" },
{ }
};
--
2.20.1
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