Re: [PATCH v6 080/102] x86: Add a generic Intel pinctrl driver
On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote: > > Recent Intel SoCs share a pinctrl mechanism with many common elements. Add > an implementation of this core functionality, allowing SoC-specific > drivers to avoid adding common code. > > As well as a pinctrl driver this provides a GPIO driver based on the same > code. > > Once other SoCs use this driver we may consider moving more properties to > the device tree (e.g. the community info and pad definitions). > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Add a comment to intel_pinctrl_ops > - Drop use of GPIO_NUM_PAD_CFG_REGS > - Move Intel Kconfig pinctrl options into this patch > > Changes in v5: > - Add function to obtain ACPI gpio number > > Changes in v4: > - Add a binding file > - Split out GPIO code from the pinctrl driver > - Switch over to use pinctrl for pad init/config > > Changes in v3: None > Changes in v2: None > > arch/x86/include/asm/intel_pinctrl.h | 306 + > arch/x86/include/asm/intel_pinctrl_defs.h | 373 ++ > .../pinctrl/intel,apl-pinctrl.txt | 39 ++ > drivers/pinctrl/Kconfig | 9 + > drivers/pinctrl/Makefile | 1 + > drivers/pinctrl/intel/Kconfig | 16 + > drivers/pinctrl/intel/Makefile| 5 + > drivers/pinctrl/intel/pinctrl.c | 636 ++ > 8 files changed, 1385 insertions(+) > create mode 100644 arch/x86/include/asm/intel_pinctrl.h > create mode 100644 arch/x86/include/asm/intel_pinctrl_defs.h > create mode 100644 doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt > create mode 100644 drivers/pinctrl/intel/Kconfig > create mode 100644 drivers/pinctrl/intel/Makefile > create mode 100644 drivers/pinctrl/intel/pinctrl.c > Reviewed-by: Bin Meng
Re: [PATCH v6 081/102] x86: Add a generic Intel GPIO driver
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add a GPIO driver which uses the pinctrl driver to access the pad > information. This driver relies on the GPIO nodes being subnodes to the > pinctrl device. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Fix 'hone' typo > - Remove the * in the first line of the binding file > - Use 'north' as the node name instead of 'n' > - Use a generic compatible string intel,gpio > > Changes in v5: None > Changes in v4: None > Changes in v3: None > Changes in v2: None > > .../gpio/intel,apl-gpio.txt | 55 ++ > drivers/gpio/Kconfig | 9 + > drivers/gpio/Makefile | 1 + > drivers/gpio/intel_gpio.c | 161 ++ > 4 files changed, 226 insertions(+) > create mode 100644 doc/device-tree-bindings/gpio/intel,apl-gpio.txt > create mode 100644 drivers/gpio/intel_gpio.c > Reviewed-by: Bin Meng
Re: [PATCH v6 082/102] x86: Move qemu CPU fixup function into its own file
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > This function is specific to qemu so it seems best to keep it separate > from the generic code. > > Move it out to a new file and update the condition to use if() instead of > #ifdef > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Add back '#ifdef' line to commit message > - Drop incorrect mention of coreboot in qfw_cpu.c > > Changes in v5: > - Add a new patch to move qemu CPU fixup function into its own file > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/x86/cpu/Makefile | 1 + > arch/x86/cpu/mp_init.c | 73 +++--- > arch/x86/cpu/qfw_cpu.c | 73 ++ > include/qfw.h | 8 + > 4 files changed, 87 insertions(+), 68 deletions(-) > create mode 100644 arch/x86/cpu/qfw_cpu.c > Reviewed-by: Bin Meng
Re: [PATCH v6 084/102] x86: apl: Add PMC driver
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add a driver for the Apollo Lake SoC. It supports the basic operations and > can use device tree or of-platdata. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Use one space after #defines in pm.h > > Changes in v5: None > Changes in v4: > - Fix Makefile copyright message > - Fix incorrect mask check in pmc_gpe_init() > - Switch over to use pinctrl for pad init/config > - Tidy up header guards > - Use pci_ofplat_get_devfn() > - apollolake -> Apollo Lake > > Changes in v3: > - Use pci_get_devfn() > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile | 5 + > arch/x86/cpu/apollolake/pmc.c | 216 ++ > arch/x86/include/asm/arch-apollolake/pm.h | 19 ++ > drivers/power/acpi_pmc/acpi-pmc-uclass.c | 56 ++ > 4 files changed, 296 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/Makefile > create mode 100644 arch/x86/cpu/apollolake/pmc.c > create mode 100644 arch/x86/include/asm/arch-apollolake/pm.h > Reviewed-by: Bin Meng
Re: [PATCH v6 085/102] x86: apl: Add UART driver
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add a driver for the Apollo Lake UART. It uses the standard ns16550 device > but also sets up the input clock with LPSS and supports configuration via > of-platdata. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Drop code to handle !CONFIG_OF_TRANSLATE case > - Update comment to reference board_debug_uart_init() (its in a later patch) > > Changes in v5: None > Changes in v4: > - Add an extra comment to apl_uart_init() > - Tidy up header guards > - apollolake -> Apollo Lake > > Changes in v3: > - Use the LPSS code from a separate file > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile| 1 + > arch/x86/cpu/apollolake/uart.c | 133 > arch/x86/include/asm/arch-apollolake/uart.h | 20 +++ > 3 files changed, 154 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/uart.c > create mode 100644 arch/x86/include/asm/arch-apollolake/uart.h > Reviewed-by: Bin Meng
Re: [PATCH v6 086/102] x86: apl: Add pinctrl driver
Hi Simon, On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add a driver for the Apollo Lake pinctrl. This mostly makes use of the > common Intel pinctrl support. > > Signed-off-by: Simon Glass > --- > > Changes in v6: None It looks the comment in v5 was not addressed. See https://lists.denx.de/pipermail/u-boot/2019-December/392375.html > Changes in v5: None > Changes in v4: > - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes) > - Drop GPIO_NUM_PAD_CFG_REGS > - Switch over to use pinctrl for pad init/config > - Tidy up the header file a little > - apollolake -> Apollo Lake > > Changes in v3: > - Add various minor tidy-ups > - Fix mixed case in GPIO defines > - Rework how pads configuration is defined in TPL and SPL > - Use the IRQ uclass instead of ITSS > > Changes in v2: None > > arch/x86/include/asm/arch-apollolake/gpio.h | 490 > drivers/pinctrl/intel/Kconfig | 8 + > drivers/pinctrl/intel/Makefile | 1 + > drivers/pinctrl/intel/pinctrl_apl.c | 192 > 4 files changed, 691 insertions(+) > create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h > create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c > Regards, Bin
Re: [PATCH v6 088/102] x86: apl: Add systemagent driver
Hi Simon,
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote:
>
> This driver handles communication with the systemagent which needs to be
> told when U-Boot has completed its init.
>
> Signed-off-by: Simon Glass
>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Add a comment for enable_bios_reset_cpl()
> - Tidy up header guards
> - use GENMASK() for VTBAR_MASK
>
> Changes in v3: None
> Changes in v2: None
>
> arch/x86/cpu/apollolake/Makefile | 2 +
> arch/x86/cpu/apollolake/systemagent.c | 19 ++
> .../include/asm/arch-apollolake/systemagent.h | 37 +++
> 3 files changed, 58 insertions(+)
> create mode 100644 arch/x86/cpu/apollolake/systemagent.c
> create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h
>
> diff --git a/arch/x86/cpu/apollolake/Makefile
> b/arch/x86/cpu/apollolake/Makefile
> index fdda748ea3..3a8c2f66a3 100644
> --- a/arch/x86/cpu/apollolake/Makefile
> +++ b/arch/x86/cpu/apollolake/Makefile
> @@ -2,5 +2,7 @@
> #
> # Copyright 2019 Google LLC
>
> +obj-$(CONFIG_SPL_BUILD) += systemagent.o
> +
> obj-y += pmc.o
> obj-y += uart.o
> diff --git a/arch/x86/cpu/apollolake/systemagent.c
> b/arch/x86/cpu/apollolake/systemagent.c
> new file mode 100644
> index 00..3a41b329c3
> --- /dev/null
> +++ b/arch/x86/cpu/apollolake/systemagent.c
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 Intel Corporation.
> + * Take from coreboot project file of the same name
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +void enable_bios_reset_cpl(void)
> +{
> + /*
> +* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
> +* that BIOS has initialised memory and power management
> +*/
Could you put more comments here, like what you mentioned in the v5 comments:
"The FSP-S does not do it. If we leave this as zero then I believe the
power-aware interrupts don't work in Linux, and cpu 0 always gets the
interrupt."
> + setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);
> +}
[snip]
Regards,
Bin
Re: [PATCH v6 089/102] x86: apl: Add hostbridge driver
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > This driver models the hostbridge as a northbridge. It simply sets up the > graphics BAR. It supports of-platdata. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Fix comments for struct apl_hostbridge_platdata > > Changes in v5: None > Changes in v4: > - Avoid needing to know internals of pinctrl in this driver > - Move code to pinctrl driver > - Switch over to use pinctrl for pad init/config > > Changes in v3: > - Move pad programming into the hostbridge to reduce TPL device-tree size > - Use pci_get_devfn() > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile | 1 + > arch/x86/cpu/apollolake/hostbridge.c | 179 +++ > 2 files changed, 180 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/hostbridge.c > Reviewed-by: Bin Meng
Re: [PATCH v6 080/102] x86: Add a generic Intel pinctrl driver
On Sun, Dec 8, 2019 at 3:59 PM Bin Meng wrote: > > On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote: > > > > Recent Intel SoCs share a pinctrl mechanism with many common elements. Add > > an implementation of this core functionality, allowing SoC-specific > > drivers to avoid adding common code. > > > > As well as a pinctrl driver this provides a GPIO driver based on the same > > code. > > > > Once other SoCs use this driver we may consider moving more properties to > > the device tree (e.g. the community info and pad definitions). > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v6: > > - Add a comment to intel_pinctrl_ops > > - Drop use of GPIO_NUM_PAD_CFG_REGS > > - Move Intel Kconfig pinctrl options into this patch > > > > Changes in v5: > > - Add function to obtain ACPI gpio number > > > > Changes in v4: > > - Add a binding file > > - Split out GPIO code from the pinctrl driver > > - Switch over to use pinctrl for pad init/config > > > > Changes in v3: None > > Changes in v2: None > > > > arch/x86/include/asm/intel_pinctrl.h | 306 + > > arch/x86/include/asm/intel_pinctrl_defs.h | 373 ++ > > .../pinctrl/intel,apl-pinctrl.txt | 39 ++ > > drivers/pinctrl/Kconfig | 9 + > > drivers/pinctrl/Makefile | 1 + > > drivers/pinctrl/intel/Kconfig | 16 + > > drivers/pinctrl/intel/Makefile| 5 + > > drivers/pinctrl/intel/pinctrl.c | 636 ++ > > 8 files changed, 1385 insertions(+) > > create mode 100644 arch/x86/include/asm/intel_pinctrl.h > > create mode 100644 arch/x86/include/asm/intel_pinctrl_defs.h > > create mode 100644 doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt > > create mode 100644 drivers/pinctrl/intel/Kconfig > > create mode 100644 drivers/pinctrl/intel/Makefile > > create mode 100644 drivers/pinctrl/intel/pinctrl.c > > > > Reviewed-by: Bin Meng applied to u-boot-x86/next, thanks!
Re: [PATCH v6 082/102] x86: Move qemu CPU fixup function into its own file
On Sun, Dec 8, 2019 at 4:03 PM Bin Meng wrote: > > On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > > > This function is specific to qemu so it seems best to keep it separate > > from the generic code. > > > > Move it out to a new file and update the condition to use if() instead of > > #ifdef > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v6: > > - Add back '#ifdef' line to commit message > > - Drop incorrect mention of coreboot in qfw_cpu.c > > > > Changes in v5: > > - Add a new patch to move qemu CPU fixup function into its own file > > > > Changes in v4: None > > Changes in v3: None > > Changes in v2: None > > > > arch/x86/cpu/Makefile | 1 + > > arch/x86/cpu/mp_init.c | 73 +++--- > > arch/x86/cpu/qfw_cpu.c | 73 ++ > > include/qfw.h | 8 + > > 4 files changed, 87 insertions(+), 68 deletions(-) > > create mode 100644 arch/x86/cpu/qfw_cpu.c > > > > Reviewed-by: Bin Meng applied to u-boot-x86/next, thanks!
Re: [PATCH v6 081/102] x86: Add a generic Intel GPIO driver
On Sun, Dec 8, 2019 at 4:01 PM Bin Meng wrote: > > On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > > > Add a GPIO driver which uses the pinctrl driver to access the pad > > information. This driver relies on the GPIO nodes being subnodes to the > > pinctrl device. > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v6: > > - Fix 'hone' typo > > - Remove the * in the first line of the binding file > > - Use 'north' as the node name instead of 'n' > > - Use a generic compatible string intel,gpio > > > > Changes in v5: None > > Changes in v4: None > > Changes in v3: None > > Changes in v2: None > > > > .../gpio/intel,apl-gpio.txt | 55 ++ > > drivers/gpio/Kconfig | 9 + > > drivers/gpio/Makefile | 1 + > > drivers/gpio/intel_gpio.c | 161 ++ > > 4 files changed, 226 insertions(+) > > create mode 100644 doc/device-tree-bindings/gpio/intel,apl-gpio.txt > > create mode 100644 drivers/gpio/intel_gpio.c > > > > Reviewed-by: Bin Meng applied to u-boot-x86/next, thanks!
Re: [PATCH v6 083/102] x86: apl: Add basic IO addresses
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add some fixed IO and mmap addresses for use in the device tree and with > some early-init code. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng > > --- > > Changes in v6: None > Changes in v5: > - Add ACPI base address and size > > Changes in v4: > - Drop TCO_BASE_ADDRESS > - Tidy up header guards > > Changes in v3: None > Changes in v2: None > > arch/x86/include/asm/arch-apollolake/iomap.h | 29 > 1 file changed, 29 insertions(+) > create mode 100644 arch/x86/include/asm/arch-apollolake/iomap.h > applied to u-boot-x86/next, thanks!
Re: [PATCH v6 085/102] x86: apl: Add UART driver
On Sun, Dec 8, 2019 at 4:07 PM Bin Meng wrote: > > On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > > > Add a driver for the Apollo Lake UART. It uses the standard ns16550 device > > but also sets up the input clock with LPSS and supports configuration via > > of-platdata. > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v6: > > - Drop code to handle !CONFIG_OF_TRANSLATE case > > - Update comment to reference board_debug_uart_init() (its in a later patch) > > > > Changes in v5: None > > Changes in v4: > > - Add an extra comment to apl_uart_init() > > - Tidy up header guards > > - apollolake -> Apollo Lake > > > > Changes in v3: > > - Use the LPSS code from a separate file > > > > Changes in v2: None > > > > arch/x86/cpu/apollolake/Makefile| 1 + > > arch/x86/cpu/apollolake/uart.c | 133 > > arch/x86/include/asm/arch-apollolake/uart.h | 20 +++ > > 3 files changed, 154 insertions(+) > > create mode 100644 arch/x86/cpu/apollolake/uart.c > > create mode 100644 arch/x86/include/asm/arch-apollolake/uart.h > > > > Reviewed-by: Bin Meng applied to u-boot-x86/next, thanks!
Re: [PATCH v6 084/102] x86: apl: Add PMC driver
On Sun, Dec 8, 2019 at 4:04 PM Bin Meng wrote: > > On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > > > Add a driver for the Apollo Lake SoC. It supports the basic operations and > > can use device tree or of-platdata. > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v6: > > - Use one space after #defines in pm.h > > > > Changes in v5: None > > Changes in v4: > > - Fix Makefile copyright message > > - Fix incorrect mask check in pmc_gpe_init() > > - Switch over to use pinctrl for pad init/config > > - Tidy up header guards > > - Use pci_ofplat_get_devfn() > > - apollolake -> Apollo Lake > > > > Changes in v3: > > - Use pci_get_devfn() > > > > Changes in v2: None > > > > arch/x86/cpu/apollolake/Makefile | 5 + > > arch/x86/cpu/apollolake/pmc.c | 216 ++ > > arch/x86/include/asm/arch-apollolake/pm.h | 19 ++ > > drivers/power/acpi_pmc/acpi-pmc-uclass.c | 56 ++ > > 4 files changed, 296 insertions(+) > > create mode 100644 arch/x86/cpu/apollolake/Makefile > > create mode 100644 arch/x86/cpu/apollolake/pmc.c > > create mode 100644 arch/x86/include/asm/arch-apollolake/pm.h > > > > Reviewed-by: Bin Meng applied to u-boot-x86/next, thanks!
Re: [PATCH v6 091/102] x86: apl: Add LPC driver
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > This driver the LPC and provides a few functions to set up LPC features. > These should probably use ioctls() or perhaps, better, have specific > uclass methods. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Drop init of ComB since it is not used > - Drop lpc_configure_pads() and probe() function, add a comment about pads > > Changes in v5: None > Changes in v4: > - Add comments for exported functions > - Tidy up header guards > - Use 'Apollo Lake' > - Use BIT() macro a bit more > - Use tabs instead of spaces > > Changes in v3: > - Drop unused code in lpc_configure_pads() > - Fix value of LPC_BC_LE > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile | 1 + > arch/x86/cpu/apollolake/lpc.c | 122 + > arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++ > 3 files changed, 205 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/lpc.c > create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h > Reviewed-by: Bin Meng
Re: [PATCH v6 093/102] x86: apl: Add PUNIT driver
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a > syscon driver since it only needs to be probed. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Drop Glacier Lake code > - Drop platform data and pre-PCI code, since DM PCI is available in SPL > > Changes in v5: None > Changes in v4: > - Name this P-Unit instead of power unit, in the commit message > - apollolake -> Apollo Lake > > Changes in v3: > - Use pci_get_devfn() > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile | 3 + > arch/x86/cpu/apollolake/punit.c | 94 > 2 files changed, 97 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/punit.c > Reviewed-by: Bin Meng
Re: [PATCH v6 094/102] spl: Add methods to find the position/size of next phase
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Binman supports writing the position and size of U-Boot proper and SPL > into the previous phase of U-Boot. This allows the next phase to be easily > located and loaded. > > Add functions to return these useful values, along with symbols to allow > TPL to load SPL. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Add new patch with methods to find the position/size of next SPL phase > > Changes in v5: None > Changes in v4: None > Changes in v3: None > Changes in v2: None > > common/spl/spl.c | 20 > include/spl.h| 21 - > 2 files changed, 40 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: [PATCH v6 095/102] x86: apl: Add SPL loaders
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add loaders for SPL and TPL so that the next stage can be loaded from > memory-mapped SPI or, failing that, the Fast SPI driver. > > Signed-off-by: Simon Glass > > --- > > Changes in v6: > - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option > - Move image pos/size access functions and symbols to generic SPL code > > Changes in v5: > - Add L2 cache flush functoin > - Drop SAFETY_MARGIN > > Changes in v4: None > Changes in v3: > - Add a driver for APL SPI for TPL (using of-platdata) > - Support TPL without CONFIG_TPL_SPI_SUPPORT > - Support bootstage timing > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile | 2 + > arch/x86/cpu/apollolake/spl.c| 178 +++ > 2 files changed, 180 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/spl.c > Reviewed-by: Bin Meng
Re: [PATCH v6 096/102] x86: apl: Add a CPU driver
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add a bare-bones CPU driver so that CPUs can be probed. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Drop unnecessary priv struct and probe method > - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option > > Changes in v5: > - Add L2 cache flush function > - Drop SAFETY_MARGIN > > Changes in v4: > - Change apollolake to apl > - Tidy up header guards > > Changes in v3: > - Add two more defines for the CPU driver > - Expand comments for BOOT_FROM_FAST_SPI_FLASH > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile | 2 ++ > arch/x86/cpu/apollolake/cpu.c | 41 ++ > arch/x86/cpu/apollolake/cpu_common.c | 17 + > arch/x86/include/asm/arch-apollolake/cpu.h | 20 +++ > arch/x86/include/asm/msr-index.h | 1 + > 5 files changed, 81 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/cpu.c > create mode 100644 arch/x86/cpu/apollolake/cpu_common.c > create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h > Reviewed-by: Bin Meng
Re: [PATCH v6 097/102] x86: apl: Add SPL/TPL init
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add code to init the system both in TPL and SPL. Each phase has its own > procedure. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Change comment to apl_hostbridge_early_init_pinctrl, not apl_gpio_early_init > - Change commented-out enable_rtc_upper_bank() call to a TODO > - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option > - Rename init_for_uart() to board_debug_uart_init() > - Use SZ_4G instead of open-coded shift > > Changes in v5: None > Changes in v4: > - Switch over to use pinctrl for pad init/config > > Changes in v3: > - Adjust fast_spi_cache_bios_region() to avoid using SPI driver > - Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f() > - Fix build error when debug UART is disabled > - Init the p2sb before the northbridge since the latter so it can use GPIOs > - Move location of fast_spi.h header file > - Shorten log_msg_ret() calls since the function name is always printed > - Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size) > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile | 1 + > arch/x86/cpu/apollolake/cpu_spl.c | 271 ++ > 2 files changed, 272 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c > Reviewed-by: Bin Meng
Re: [PATCH v6 098/102] x86: apl: Add P2SB driver
Hi Simon,
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote:
>
> Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
> various child devices. It supposed both device tree and of-platdata.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Detect zero mmio address
> - Use BIT() macro bit more
> - apollolake -> Apollo Lake
>
> Changes in v3:
> - Use pci_get_devfn()
>
> Changes in v2: None
>
> arch/x86/cpu/apollolake/Makefile | 1 +
> arch/x86/cpu/apollolake/p2sb.c | 167 +++
> 2 files changed, 168 insertions(+)
> create mode 100644 arch/x86/cpu/apollolake/p2sb.c
>
> diff --git a/arch/x86/cpu/apollolake/Makefile
> b/arch/x86/cpu/apollolake/Makefile
> index edde122f75..dc6df15dab 100644
> --- a/arch/x86/cpu/apollolake/Makefile
> +++ b/arch/x86/cpu/apollolake/Makefile
> @@ -15,6 +15,7 @@ endif
> obj-y += hostbridge.o
> obj-y += itss.o
> obj-y += lpc.o
> +obj-y += p2sb.o
> obj-y += pch.o
> obj-y += pmc.o
> obj-y += uart.o
> diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c
> new file mode 100644
> index 00..0a5deaf4a0
> --- /dev/null
> +++ b/arch/x86/cpu/apollolake/p2sb.c
> @@ -0,0 +1,167 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Primary-to-Sideband Bridge
> + *
> + * Copyright 2019 Google LLC
> + */
> +
> +#define LOG_CATEGORY UCLASS_P2SB
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct p2sb_platdata {
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> + struct dtd_intel_apl_p2sb dtplat;
> +#endif
> + ulong mmio_base;
> + pci_dev_t bdf;
> +};
> +
> +/* PCI config space registers */
> +#define HPTC_OFFSET0x60
> +#define HPTC_ADDR_ENABLE_BIT BIT(7)
> +
> +/* High Performance Event Timer Configuration */
> +#define P2SB_HPTC 0x60
> +#define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
> +
> +/*
> + * ADDRESS_SELECTENCODING_RANGE
> + * 0 0xfed0 - 0xfed0 03ff
> + * 1 0xfed0 1000 - 0xfed0 13ff
> + * 2 0xfed0 2000 - 0xfed0 23ff
> + * 3 0xfed0 3000 - 0xfed0 33ff
> + */
> +#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
> +#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
> +#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
> +#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
> +
> +/*
> + * apl_p2sb_early_init() - Enable decoding for HPET range
> + *
> + * This is needed for FspMemoryInit to store and retrieve a global data
> + * pointer
Looks my comment in the v5 series was not addressed.
See https://lists.denx.de/pipermail/u-boot/2019-December/392392.html
> + *
> + * @dev: P2SB device
> + * @return 0 if OK, -ve on error
> + */
> +static int apl_p2sb_early_init(struct udevice *dev)
> +{
> + struct p2sb_platdata *plat = dev_get_platdata(dev);
> + pci_dev_t pdev = plat->bdf;
> +
> + /*
> +* Enable decoding for HPET memory address range.
> +* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
> +* the High Performance Timer memory address range
> +* selected by bits 1:0
> +*/
> + pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
> +PCI_SIZE_8);
> +
> + /* Enable PCR Base address in PCH */
> + pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
> +PCI_SIZE_32);
> + pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
> +
> + /* Enable P2SB MSE */
> + pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
> +PCI_COMMAND_MEMORY, PCI_SIZE_8);
> +
> + return 0;
> +}
> +
> +static int apl_p2sb_spl_init(struct udevice *dev)
> +{
> + /* Enable decoding for HPET. Needed for FSP global pointer storage */
> + dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
> + P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
> +
> + return 0;
> +}
> +
> +int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
> + struct p2sb_platdata *plat = dev_get_platdata(dev);
> +
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + int ret;
> +
> + if (spl_phase() == PHASE_TPL) {
> + u32 base[2];
> +
> + /* TPL sets up the initial BAR */
> + ret = dev_read_u32_array(dev, "early-regs", base,
> +ARRAY_SIZE(base));
> + if (ret)
> + return log_msg_ret("Missing/short early-regs", ret);
> + plat->mmio_base = base[0];
> + plat->bdf = pci_get_devfn(dev);
> + if (plat->bdf < 0)
> + return log_msg_ret("Cannot get p2sb PCI address",
> +
Re: [PATCH v6 099/102] x86: apl: Add Kconfig and Makefile
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > Add basic plumbing to allow Apollo Lake support to be used. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option > > Changes in v5: > - Enable SMP > > Changes in v4: > - Enable HAVE_X86_FIT > - Enable INTEL_GPIO > - Switch over to use pinctrl for pad init/config > - Use existing VBT Kconfig option > - apollolake -> Apollo Lake > > Changes in v3: > - Add MMC, video, USB configs > - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot > - Fix the incorrect value of CPU_ADDR_BITS > > Changes in v2: None > > arch/x86/Kconfig| 1 + > arch/x86/cpu/Makefile | 1 + > arch/x86/cpu/apollolake/Kconfig | 96 + > 3 files changed, 98 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/Kconfig > Reviewed-by: Bin Meng
Re: [PATCH v6 100/102] x86: apl: Add FSP structures
On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote: > > These are mostly specific to a particular SoC. Add the definitions for > Apollo Lake. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Fix FSP-M and FSP-S in comments > > Changes in v5: None > Changes in v4: > - apollolake -> Apollo Lake > > Changes in v3: > - Add VBT signature > - Add structures for FSP-S also > - Drop struct fsp_usp_header as it is now in the API file > > Changes in v2: None > > .../asm/arch-apollolake/fsp/fsp_configs.h | 14 + > .../asm/arch-apollolake/fsp/fsp_m_upd.h | 123 > .../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 ++ > .../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 + > 4 files changed, 440 insertions(+) > create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h > create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h > create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h > create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h > Reviewed-by: Bin Meng
Re: [PATCH v6 101/102] x86: apl: Add FSP support
On Sat, Dec 7, 2019 at 12:55 PM Simon Glass wrote: > > The memory and silicon init parts of the FSP need support code to work. > Add this for Apollo Lake. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Drop mention of devicetree for VTD feature > - Drop mention of ramstage > - Fix various coding style problems > - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option > - Use 'No SPI' instead of 'SPI2' as a debug message > > Changes in v5: > - Allocate the FSP-S data instead of using the stack > - Rename APOLLOLAKE_USB2_PORT_MAX > > Changes in v4: > - Adjust the comment for struct dw_i2c_speed_config > - Rename arch_fsp_s_preinit() to arch_fsps_preinit() > - Switch over to use pinctrl for pad init/config > - Tidy up mixed case in FSP code > - apollolake -> Apollo Lake > > Changes in v3: > - Add bootstage timing for reading vbt > - Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash) > - Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S > - Set boot_loader_tolum_size to 0 > - Use the IRQ uclass instead of ITSS > > Changes in v2: None > > arch/x86/cpu/apollolake/Makefile | 6 + > arch/x86/cpu/apollolake/fsp_m.c | 210 ++ > arch/x86/cpu/apollolake/fsp_s.c | 661 +++ > 3 files changed, 877 insertions(+) > create mode 100644 arch/x86/cpu/apollolake/fsp_m.c > create mode 100644 arch/x86/cpu/apollolake/fsp_s.c > Reviewed-by: Bin Meng
Re: [PATCH v6 102/102] x86: Add chromebook_coral
Hi Simon, On Sat, Dec 7, 2019 at 12:55 PM Simon Glass wrote: > > Add support for coral which is a range of Apollo Lake-based Chromebook > released in 2017. This also includes reef released in 2016, since it is > based on the same SoC. > > Signed-off-by: Simon Glass > --- > > Changes in v6: > - Add a comment about the need for board_run_command() > - Use generic gpio compatible string > > Changes in v5: > - Add gpio-controller to GPIO nodes > - Comment out GPIOs in the fsp_s node since we don't use them yet > - Correct CPU ACPI IDs > - Use a define for ACPI base address > > Changes in v4: > - Add u-boot,skip-auto-config-until-reloc property to PCI > - Drop duplicate commit 'Create a new sandbox_pci_read_bar() function' > - New GPIO driver binding > - Set up LPC pads early > - Switch over to use pinctrl for pad init/config > - Update documentation with more detailed memory map > - Use hyphen for device-tree properties > - apollolake -> Apollo Lake > > Changes in v3: > - Ad FSP-S support > - Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size > - Add Chrome OS EC support > - Add a proper SPI node and make the SPI flash node a child > - Add bootstage support > - Add more documentation > - Add spi alias in device tree > - Disable the bootcommand since it does nothing useful on coral > - Don't enable SPI flash in TPL by default > - Drop CONFIG_SPL_NET_SUPPORT > - Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs' > - Drop patch 'dm: core: Don't include ofnode functions with of-platdata' > - Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash' > - Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt' > - Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI > interface' > - Drop patch 'x86: timer: Set up the timer in timer_early_get_count()' > - Enable video and USB3 > - Reduce amount of early-pad data in TPL > - Tidy up the pad settings in the device tree > - Use a zero-based tsc timer > > Changes in v2: None > > arch/x86/dts/Makefile | 1 + > arch/x86/dts/chromebook_coral.dts | 831 ++ > board/google/Kconfig | 15 + > board/google/chromebook_coral/Kconfig | 43 ++ > board/google/chromebook_coral/MAINTAINERS | 6 + > board/google/chromebook_coral/Makefile| 5 + > board/google/chromebook_coral/coral.c | 19 + > configs/chromebook_coral_defconfig| 102 +++ > doc/board/google/chromebook_coral.rst | 241 +++ This file needs to be added in doc/board/google/index.rst > include/configs/chromebook_coral.h| 32 + > 10 files changed, 1295 insertions(+) > create mode 100644 arch/x86/dts/chromebook_coral.dts > create mode 100644 board/google/chromebook_coral/Kconfig > create mode 100644 board/google/chromebook_coral/MAINTAINERS > create mode 100644 board/google/chromebook_coral/Makefile > create mode 100644 board/google/chromebook_coral/coral.c > create mode 100644 configs/chromebook_coral_defconfig > create mode 100644 doc/board/google/chromebook_coral.rst > create mode 100644 include/configs/chromebook_coral.h > Other than that, Reviewed-by: Bin Meng Regards, Bin
Re: [PATCH v6 000/102] x86: Add initial support for apollolake
Hi Simon, On Sat, Dec 7, 2019 at 12:43 PM Simon Glass wrote: > > Apollo Lake is an Intel SoC generation aimed at relatively low-end > embedded systems. It was released in 2016 but has become more popular > recently with some embedded boards using it. > > This series adds support for Apollo Lake. As an example it adds an > implementation of chromebook_coral (a large range of Chromebooks released > in 2017). > > The series provides enough support to boot to a prompt. with LCD display, > storage, USB, EC and keyboard. > > Since this is the first time U-Boot has used FSP2 there is quite a bit of > refactoring needed. > > This series is available at u-boot-dm/coral-working > I applied the first 85 patches in the v6 series to u-boot-x86/next, except the following 2 patches: [v6,015/102] Revert "RFC: sandbox: net: Suppress the MAC-address warnings [v6,014/102] RFC: sandbox: net: Suppress the MAC-address warnings I believe this needs to be handled by Joe? The patches unfortunately break am335x_evm. Azure logs: arm: + am335x_evm +arm-linux-gnueabi-ld.bfd: u-boot-spl section `.u_boot_list' will not fit in region `.sram' +arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 8 bytes +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 +make: *** [sub-make] Error 2 GitLab logs: arm: + am335x_evm +arm-linux-gnueabi-ld.bfd: u-boot-spl section `.u_boot_list' will not fit in region `.sram' +arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 76 bytes +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 +make: *** [sub-make] Error 2 Would you please take a look, and propose a fix so that I can squash into the one that breaks this board? https://gitlab.denx.de/u-boot/custodians/u-boot-x86/-/jobs/37696 @Tom, not sure why Azure and GitLab reported different size overflowed? (8 vs 76). Is this caused by build directory path? Regards, Bin
[PATCH 1/1] efi_loader: adjust file system info
When the GetInfo() method of the EFI_FILE_PROTOCOL is called to retrieve the file system info we claim that the volume is read only and has no free space. This leads to failures in programs that check this information before writing to the volume like SCT's InstallSct.efi. Currently there is no function to determine these parameters in U-Boot. So let's return optimistic values: Return that the volume is writable. Return the volume size as free space. Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_file.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 6d3f680e56..140116ddc4 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -656,9 +656,16 @@ static efi_status_t EFIAPI efi_file_getinfo(struct efi_file_handle *file, memset(info, 0, required_size); info->size = required_size; - info->read_only = true; + /* +* TODO: We cannot determine if the volume can be written to. +*/ + info->read_only = false; info->volume_size = part.size * part.blksz; - info->free_space = 0; + /* +* TODO: We currently have no function to determine the free +* space. The volume size is the best upper bound we have. +*/ + info->free_space = info->volume_size; info->block_size = part.blksz; /* * TODO: The volume label is not available in U-Boot. -- 2.24.0
Re: [PATCH] x86: use data32 directive instead of macro for operand-size prefix
On Tue, Dec 3, 2019 at 1:32 PM Masahiro Yamada wrote: > > This file defines 'a32' and 'o32' macros to avoid magic numbers > of operand/address-size prefixing. > > GAS supports 'data32' and 'addr32' for that purpose. > > Signed-off-by: Masahiro Yamada > --- > > arch/x86/cpu/start16.S | 8 +++- > 1 file changed, 3 insertions(+), 5 deletions(-) > Reviewed-by: Bin Meng Tested-by: Bin Meng
Re: [PATCH] x86: simplify ljmp to 32-bit code
Hi Masahiro, On Tue, Dec 3, 2019 at 1:29 PM Masahiro Yamada wrote: > > You can directly specify the label as the operand for ljmp. > > This commit saves 4-byte code. > > Signed-off-by: Masahiro Yamada > --- > > arch/x86/cpu/start16.S | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S > index bcabd76741ef..7bad9f3e4d87 100644 > --- a/arch/x86/cpu/start16.S > +++ b/arch/x86/cpu/start16.S > @@ -44,10 +44,8 @@ data32 cslgdtgdt_ptr > ff: > > /* Finally restore BIST and jump to the 32-bit initialization code */ > - movw$code32start, %ax > - movw%ax, %bp > movl%ecx, %eax > -data32 cs ljmp*(%bp) > +data32 cs ljmpcode32start There should be a * before code32start, otherwise gas reportes: arch/x86/cpu/start16.S: Assembler messages: arch/x86/cpu/start16.S:48: Warning: indirect ljmp without `*' > > /* 48-bit far pointer */ > code32start: > -- Reviewed-by: Bin Meng Tested-by: Bin Meng Regards, Bin
Re: [PATCH] x86: use data32 directive instead of macro for operand-size prefix
On Sun, Dec 8, 2019 at 6:43 PM Bin Meng wrote: > > On Tue, Dec 3, 2019 at 1:32 PM Masahiro Yamada wrote: > > > > This file defines 'a32' and 'o32' macros to avoid magic numbers > > of operand/address-size prefixing. > > > > GAS supports 'data32' and 'addr32' for that purpose. > > > > Signed-off-by: Masahiro Yamada > > --- > > > > arch/x86/cpu/start16.S | 8 +++- > > 1 file changed, 3 insertions(+), 5 deletions(-) > > > > Reviewed-by: Bin Meng > Tested-by: Bin Meng applied to u-boot-x86, thanks!
Re: [PATCH] x86: simplify ljmp to 32-bit code
On Sun, Dec 8, 2019 at 6:43 PM Bin Meng wrote: > > Hi Masahiro, > > On Tue, Dec 3, 2019 at 1:29 PM Masahiro Yamada wrote: > > > > You can directly specify the label as the operand for ljmp. > > > > This commit saves 4-byte code. > > > > Signed-off-by: Masahiro Yamada > > --- > > > > arch/x86/cpu/start16.S | 4 +--- > > 1 file changed, 1 insertion(+), 3 deletions(-) > > > > diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S > > index bcabd76741ef..7bad9f3e4d87 100644 > > --- a/arch/x86/cpu/start16.S > > +++ b/arch/x86/cpu/start16.S > > @@ -44,10 +44,8 @@ data32 cslgdtgdt_ptr > > ff: > > > > /* Finally restore BIST and jump to the 32-bit initialization code > > */ > > - movw$code32start, %ax > > - movw%ax, %bp > > movl%ecx, %eax > > -data32 cs ljmp*(%bp) > > +data32 cs ljmpcode32start > > There should be a * before code32start, otherwise gas reportes: > > arch/x86/cpu/start16.S: Assembler messages: > arch/x86/cpu/start16.S:48: Warning: indirect ljmp without `*' fixed the warning by adding * before code32start > > > > > /* 48-bit far pointer */ > > code32start: > > -- > > Reviewed-by: Bin Meng > Tested-by: Bin Meng and applied to u-boot-x86, thanks!
Re: [PATCH 1/4] serial: n16550: Support run-time configuration
+Aiden
Hi Simon,
On Fri, Dec 6, 2019 at 7:04 AM Simon Glass wrote:
>
> At present this driver uses an assortment of CONFIG options to control
> how it accesses the hardware. This is painful for platforms that are
> supposed to be controlled by a device tree or a previous-stage bootloader.
>
> Add a new CONFIG option to enable fully dynamic configuration. This
> controls register spacing, size, offset and endianness.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/serial/Kconfig | 20 ++
> drivers/serial/ns16550.c | 57 ++--
> include/ns16550.h| 13 +
> 3 files changed, 82 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index d36a0108ea..50710ab998 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -598,6 +598,26 @@ config SYS_NS16550
> be used. It can be a constant or a function to get clock, eg,
> get_serial_clock().
>
> +config NS16550_DYNAMIC
> + bool "Allow NS16550 to be configured at runtime"
nits: run-time
> + default y if SYS_COREBOOT
I believe we should also turn it on for slimbootloader.
> + help
> + Enable this option to allow device-tree control of the driver.
> +
> + Normally this driver is controlled by the following options:
> +
> + CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for
> +access. If not enabled, then the UART is memory-mapped.
> + CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit
> +access should be used (instead of 8-bit)
> + CONFIG_SYS_NS16550_REG_SIZE - indicates endianness. If positive,
This is not for endianness, but for the register width.
> +big-endian access is used. If negative, little-endian is used.
> +
> + It is not good practive for a driver to be statically configured,
not a good practice
> + since it prevents the same driver being used for different types of
> + UARTs in a system. This option avoids this problem at the cost of a
> + slightly increased code size.
> +
> config INTEL_MID_SERIAL
> bool "Intel MID platform UART support"
> depends on DM_SERIAL && OF_CONTROL
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 754b6e9921..96c4471efd 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -92,19 +92,57 @@ static inline int serial_in_shift(void *addr, int shift)
> #define CONFIG_SYS_NS16550_CLK 0
> #endif
>
> +static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
> + int value)
> +{
> + if (plat->flags & NS16550_FLAG_BE) {
> + if (plat->reg_width == 1)
> + writeb(value, addr + (1 << plat->reg_shift) - 1);
> + else if (plat->flags & NS16550_FLAG_IO)
> + out_be32(addr, value);
> + else
> + writel(value, addr);
> + } else {
> + if (plat->reg_width == 1)
> + writeb(value, addr);
> + else if (plat->flags & NS16550_FLAG_IO)
> + out_le32(addr, value);
> + else
> + writel(value, addr);
> + }
> +}
> +
> +static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
> +{
> + if (plat->flags & NS16550_FLAG_BE) {
> + if (plat->reg_width == 1)
> + return readb(addr + (1 << plat->reg_shift) - 1);
> + else if (plat->flags & NS16550_FLAG_IO)
> + return in_be32(addr);
> + else
> + return readl(addr);
> + } else {
> + if (plat->reg_width == 1)
> + return readb(addr);
> + else if (plat->flags & NS16550_FLAG_IO)
> + return in_le32(addr);
> + else
> + return readl(addr);
> + }
> +}
> +
> static void ns16550_writeb(NS16550_t port, int offset, int value)
> {
> struct ns16550_platdata *plat = port->plat;
> unsigned char *addr;
>
> offset *= 1 << plat->reg_shift;
> - addr = (unsigned char *)plat->base + offset;
> + addr = (unsigned char *)plat->base + offset + plat->reg_offset;
>
> - /*
> -* As far as we know it doesn't make sense to support selection of
> -* these options at run-time, so use the existing CONFIG options.
> -*/
> - serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value);
> + if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
> + serial_out_dynamic(plat, addr, value);
> + else
> + serial_out_shift(addr, plat->reg_shift, value);
> }
>
> static int ns16550_readb(NS16550_t port, int offset)
> @@ -113,9 +151,12 @@ static int ns16550_readb(NS16550_t port,
Re: [PATCH 3/4] x86: serial: Add a coreboot serial driver
On Fri, Dec 6, 2019 at 7:04 AM Simon Glass wrote: > > Coreboot can provide information about the serial device in use on a > platform. Add a driver that uses this information to produce a working > UART. > > Signed-off-by: Simon Glass > --- > > drivers/serial/Kconfig | 11 > drivers/serial/Makefile | 1 + > drivers/serial/serial_coreboot.c | 46 > 3 files changed, 58 insertions(+) > create mode 100644 drivers/serial/serial_coreboot.c > Reviewed-by: Bin Meng
Re: [PATCH 2/4] x86: Update coreboot serial table struct
On Fri, Dec 6, 2019 at 7:04 AM Simon Glass wrote: > > Since mid 2016, coreboot has additional fields in the serial struct that > it passes down to U-Boot. Add these so we are in sync. > > Signed-off-by: Simon Glass > --- > > arch/x86/include/asm/coreboot_tables.h | 19 +++ > 1 file changed, 19 insertions(+) > Reviewed-by: Bin Meng
Re: [PATCH 4/4] x86: Move coreboot over to use the coreboot UART
On Fri, Dec 6, 2019 at 7:04 AM Simon Glass wrote: > > Use this UART to improve the compatibility of U-Boot when used as a > coreboot payload. > > Signed-off-by: Simon Glass > --- > > arch/x86/dts/coreboot.dts | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: i.MX8MM-EVK Boot failure
On Sat, Dec 7, 2019 at 12:25 PM Tom Rini wrote: > > On Sat, Dec 07, 2019 at 08:42:32AM -0600, Adam Ford wrote: > > > I am trying to run the latest master > > > > 4b19b89ca4a866b7baa642533e6dbd67cd832d27 > > with the clock patches applied for 8mm, but I am getting a boot > > failure when I follow the instructions in the README, which are also a > > bit wrong. (the firmware versions don't match, and the ./firmware > > command is missing the trailing '.bin', but it's trivial.) > > > > What comes out of the kit with DEBUG enabled is: > > > > (bunch of stuff deleted) > > > > [PMU Major message = 0x00fe] > > [PMU Major message = 0x0007] > > Training PASS > > DDRINFO: ddrphy config done > > DDRINFO:ddrphy calibration done > > DDRINFO: ddrmix config done > > >>SPL: board_init_r() > > using memory lx-lx for malloc() > > spl_init > > Normal Boot > > Trying to boot from MMC1 > > common/dlmalloc.c:792: do_check_inuse_chunk: Assertion `inuse(p)' failed. > > resetting ... > > > > The above sequence repeats again and again. I didn't put all the junk > > into the log because it looked like everything seemed OK until the > > dlmalloc failure at the end. If someone has any suggestions, I'd like > > to try the 8mm-evk with a modern U-Boot. > > I think (per the thread about fixing one of the colibri platforms) this > also needs a CONFIG_FSL_ESDHC -> CONFIG_FSL_ESDHC_IMX fix in the board > file. I am not seeing a reference to either CONFIG_FSL_ESDHC or CONFIG_FSL_ESDHC_IMX in the imx8mm_evk board files, and it appears as if the device tree and DM_SPL stuff is managing the drivers. The defconfig file is enabling CONFIG_FSL_ESDHC_IMX. It seems like a memory issue based on: common/dlmalloc.c:792: do_check_inuse_chunk: Assertion `inuse(p)' failed. adam > > -- > Tom
Re: [PATCH v6 000/102] x86: Add initial support for apollolake
On Sun, Dec 08, 2019 at 04:56:21PM +0800, Bin Meng wrote: > Hi Simon, > > On Sat, Dec 7, 2019 at 12:43 PM Simon Glass wrote: > > > > Apollo Lake is an Intel SoC generation aimed at relatively low-end > > embedded systems. It was released in 2016 but has become more popular > > recently with some embedded boards using it. > > > > This series adds support for Apollo Lake. As an example it adds an > > implementation of chromebook_coral (a large range of Chromebooks released > > in 2017). > > > > The series provides enough support to boot to a prompt. with LCD display, > > storage, USB, EC and keyboard. > > > > Since this is the first time U-Boot has used FSP2 there is quite a bit of > > refactoring needed. > > > > This series is available at u-boot-dm/coral-working > > > > I applied the first 85 patches in the v6 series to u-boot-x86/next, > except the following 2 patches: > > [v6,015/102] Revert "RFC: sandbox: net: Suppress the MAC-address warnings > [v6,014/102] RFC: sandbox: net: Suppress the MAC-address warnings > > I believe this needs to be handled by Joe? > > The patches unfortunately break am335x_evm. > > Azure logs: >arm: + am335x_evm > +arm-linux-gnueabi-ld.bfd: u-boot-spl section `.u_boot_list' will not > fit in region `.sram' > +arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 8 bytes > +make[2]: *** [spl/u-boot-spl] Error 1 > +make[1]: *** [spl/u-boot-spl] Error 2 > +make: *** [sub-make] Error 2 > > GitLab logs: >arm: + am335x_evm > +arm-linux-gnueabi-ld.bfd: u-boot-spl section `.u_boot_list' will not > fit in region `.sram' > +arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 76 bytes > +make[2]: *** [spl/u-boot-spl] Error 1 > +make[1]: *** [spl/u-boot-spl] Error 2 > +make: *** [sub-make] Error 2 > > Would you please take a look, and propose a fix so that I can squash > into the one that breaks this board? > https://gitlab.denx.de/u-boot/custodians/u-boot-x86/-/jobs/37696 > > @Tom, not sure why Azure and GitLab reported different size > overflowed? (8 vs 76). Is this caused by build directory path? Seems likely to be a path size overflow, yeah. -- Tom signature.asc Description: PGP signature
Re: [PATCH v1 2/2] treewide: Remove CONFIG_SYS_UBOOT_START from configs board files
On Fri, 6 Dec 2019 15:01:49 +0100 Patrice Chotard wrote: > As previous CONFIG_SYS_UBOOT_START is now set by default to > CONFIG_SYS_TEXT_BASE when not defined, CONFIG_SYS_UBOOT_START > can be removed from include/configs board files. > > Signed-off-by: Patrice Chotard > > --- > > include/configs/gardena-smart-gateway-at91sam.h | 1 - > include/configs/ls1046a_common.h| 1 - > include/configs/mccmon6.h | 1 - > include/configs/microblaze-generic.h| 2 -- > include/configs/mt7623.h| 1 - > include/configs/mt7629.h| 1 - > include/configs/mt8518.h| 1 - > include/configs/omap3_cairo.h | 1 - > include/configs/pumpkin.h | 1 - > include/configs/tegra-common.h | 1 - > include/configs/x600.h | 1 - > include/configs/xilinx_zynqmp_r5.h | 2 -- > include/configs/zynq-common.h | 2 -- > 13 files changed, 16 deletions(-) > > diff --git a/include/configs/gardena-smart-gateway-at91sam.h > b/include/configs/gardena-smart-gateway-at91sam.h index > 482e4714b1..f5ee65cb8a 100644 --- > a/include/configs/gardena-smart-gateway-at91sam.h +++ > b/include/configs/gardena-smart-gateway-at91sam.h @@ -64,7 +64,6 @@ > #define CONFIG_SPL_NAND_RAW_ONLY > #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4 > #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa > -#define CONFIG_SYS_UBOOT_START > CONFIG_SYS_TEXT_BASE #define > CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define > CONFIG_SYS_NAND_U_BOOT_DSTCONFIG_SYS_TEXT_BASE > diff --git a/include/configs/ls1046a_common.h > b/include/configs/ls1046a_common.h index cc8f4c0210..6543cfd868 100644 > --- a/include/configs/ls1046a_common.h > +++ b/include/configs/ls1046a_common.h > @@ -98,7 +98,6 @@ > CONFIG_SPL_BSS_MAX_SIZE) > #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10 > #define CONFIG_SYS_MONITOR_LEN 0x10 > -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE > #endif > > /* NAND SPL */ > diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h > index 045a9f7bdf..0aee1e1cf6 100644 > --- a/include/configs/mccmon6.h > +++ b/include/configs/mccmon6.h > @@ -12,7 +12,6 @@ > #define CONFIG_SPL_LIBCOMMON_SUPPORT > #include "imx6_spl.h" > > -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE > #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x8) > #define CONFIG_SYS_SPL_ARGS_ADDR 0x1800 > > diff --git a/include/configs/microblaze-generic.h > b/include/configs/microblaze-generic.h index 385b30c99b..8ca0e83c78 > 100644 --- a/include/configs/microblaze-generic.h > +++ b/include/configs/microblaze-generic.h > @@ -173,8 +173,6 @@ > /* Just for sure that there is a space for stack */ > #define CONFIG_SPL_STACK_SIZE0x100 > > -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE > - > #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ >CONFIG_SYS_INIT_RAM_ADDR - \ >CONFIG_SYS_MALLOC_F_LEN - \ > diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h > index e5182aeea8..faab0913fc 100644 > --- a/include/configs/mt7623.h > +++ b/include/configs/mt7623.h > @@ -31,7 +31,6 @@ > #define CONFIG_ENV_OVERWRITE > > /* Preloader -> Uboot */ > -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE > #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE > + SZ_2M - \ GENERATED_GBL_DATA_SIZE) > > diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h > index 4aef894c6e..6a6c2f2414 100644 > --- a/include/configs/mt7629.h > +++ b/include/configs/mt7629.h > @@ -40,7 +40,6 @@ > #define CONFIG_SYS_UBOOT_BASE(CONFIG_SPI_ADDR + > CONFIG_SPL_PAD_TO) > /* SPL -> Uboot */ > -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE > #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE > + SZ_2M - \ GENERATED_GBL_DATA_SIZE) > > diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h > index a7fe83a605..514722be99 100644 > --- a/include/configs/mt8518.h > +++ b/include/configs/mt8518.h > @@ -29,7 +29,6 @@ > #define CONFIG_SYS_BOOTM_LEN SZ_64M > > /* Uboot definition */ > -#define CONFIG_SYS_UBOOT_START > CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_INIT_SP_ADDR > (CONFIG_SYS_TEXT_BASE + \ SZ_2M - \ > GENERATED_GBL_DATA_SIZE) > diff --git a/include/configs/omap3_cairo.h > b/include/configs/omap3_cairo.h index 1b1a56d7cd..c76c81ddd5 100644 > --- a/include/configs/omap3_cairo.h > +++ b/include/configs/omap3_cairo.h > @@ -26,7 +26,6 @@ > * other needs. We use this rather than the inherited defines from > * ti_armv7_common.h for backwards compatibility. > */ > -#define CO
Re: [PATCH 06/20] clk: imx: pllv3: add disable() support
On Wed, 4 Dec 2019 18:44:25 +0100
Giulio Benetti wrote:
> Add disable() support.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/clk/imx/clk-pllv3.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index d8cbe3dd4e..9b37cd9cd9 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -54,9 +54,25 @@ static int clk_pllv3_generic_enable(struct clk
> *clk) return 0;
> }
>
> +static int clk_pllv3_generic_disable(struct clk *clk)
> +{
> + struct clk_pllv3 *pll = to_clk_pllv3(clk);
> + u32 val;
> +
> + val = readl(pll->base);
> + if (pll->powerup_set)
> + val &= ~pll->power_bit;
> + else
> + val |= pll->power_bit;
> + writel(val, pll->base);
> +
> + return 0;
> +}
> +
> static const struct clk_ops clk_pllv3_generic_ops = {
> .get_rate = clk_pllv3_generic_get_rate,
> .enable = clk_pllv3_generic_enable,
> + .disable= clk_pllv3_generic_disable,
> };
>
> struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
Reviewed-by: Lukasz Majewski
Thanks for adding this code to U-Boot.
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
pgpSnDqwLQZ5c.pgp
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Re: [PATCH 07/20] clk: imx: pllv3: add set_rate() support
On Wed, 4 Dec 2019 18:44:26 +0100
Giulio Benetti wrote:
> Add generic set_rate() support.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/clk/imx/clk-pllv3.c | 27 +++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index 9b37cd9cd9..a721dbee94 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -17,6 +17,7 @@
> #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
>
> #define BM_PLL_POWER (0x1 << 12)
> +#define BM_PLL_LOCK (0x1 << 31)
>
> struct clk_pllv3 {
> struct clk clk;
> @@ -39,6 +40,31 @@ static ulong clk_pllv3_generic_get_rate(struct clk
> *clk) return (div == 1) ? parent_rate * 22 : parent_rate * 20;
> }
>
> +static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
> +{
> + struct clk_pllv3 *pll = to_clk_pllv3(clk);
> + unsigned long parent_rate = clk_get_parent_rate(clk);
> + u32 val, div;
> +
> + if (rate == parent_rate * 22)
> + div = 1;
> + else if (rate == parent_rate * 20)
> + div = 0;
> + else
> + return -EINVAL;
> +
> + val = readl(pll->base);
> + val &= ~(pll->div_mask << pll->div_shift);
> + val |= (div << pll->div_shift);
> + writel(val, pll->base);
> +
> + /* Wait for PLL to lock */
> + while (!(readl(pll->base) & BM_PLL_LOCK))
> + ;
> +
> + return 0;
> +}
> +
> static int clk_pllv3_generic_enable(struct clk *clk)
> {
> struct clk_pllv3 *pll = to_clk_pllv3(clk);
> @@ -73,6 +99,7 @@ static const struct clk_ops clk_pllv3_generic_ops =
> { .get_rate = clk_pllv3_generic_get_rate,
> .enable = clk_pllv3_generic_enable,
> .disable= clk_pllv3_generic_disable,
> + .set_rate = clk_pllv3_generic_set_rate,
> };
>
> struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
Reviewed-by: Lukasz Majewski
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [PATCH 08/20] clk: imx: pllv3: add PLLV3_SYS support
On Wed, 4 Dec 2019 18:44:27 +0100
Giulio Benetti wrote:
> Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but
> keeping generic enable()/disable(). Add a different driver because
> ops are different respect to GENERIC/USB.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/clk/imx/clk-pllv3.c | 53
> + 1 file changed, 53 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index a721dbee94..d5087a104e 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -14,6 +14,7 @@
> #include "clk.h"
>
> #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
> +#define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
> #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
>
> #define BM_PLL_POWER (0x1 << 12)
> @@ -102,6 +103,46 @@ static const struct clk_ops
> clk_pllv3_generic_ops = { .set_rate =
> clk_pllv3_generic_set_rate, };
>
> +static ulong clk_pllv3_sys_get_rate(struct clk *clk)
> +{
> + struct clk_pllv3 *pll = to_clk_pllv3(clk);
> + unsigned long parent_rate = clk_get_parent_rate(clk);
> + u32 div = readl(pll->base) & pll->div_mask;
> +
> + return parent_rate * div / 2;
> +}
> +
> +static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
> +{
> + struct clk_pllv3 *pll = to_clk_pllv3(clk);
> + unsigned long parent_rate = clk_get_parent_rate(clk);
> + unsigned long min_rate = parent_rate * 54 / 2;
> + unsigned long max_rate = parent_rate * 108 / 2;
> + u32 val, div;
> +
> + if (rate < min_rate || rate > max_rate)
> + return -EINVAL;
> +
> + div = rate * 2 / parent_rate;
> + val = readl(pll->base);
> + val &= ~pll->div_mask;
> + val |= div;
> + writel(val, pll->base);
> +
> + /* Wait for PLL to lock */
> + while (!(readl(pll->base) & BM_PLL_LOCK))
> + ;
> +
> + return 0;
> +}
> +
> +static const struct clk_ops clk_pllv3_sys_ops = {
> + .enable = clk_pllv3_generic_enable,
> + .disable= clk_pllv3_generic_disable,
> + .get_rate = clk_pllv3_sys_get_rate,
> + .set_rate = clk_pllv3_sys_set_rate,
> +};
> +
> struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
> const char *parent_name, void __iomem
> *base, u32 div_mask)
> @@ -123,6 +164,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
> type, const char *name, pll->div_shift = 0;
> pll->powerup_set = false;
> break;
> + case IMX_PLLV3_SYS:
> + drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
> + pll->div_shift = 0;
> + pll->powerup_set = false;
> + break;
> case IMX_PLLV3_USB:
> drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
> pll->div_shift = 1;
> @@ -153,6 +199,13 @@ U_BOOT_DRIVER(clk_pllv3_generic) = {
> .flags = DM_FLAG_PRE_RELOC,
> };
>
> +U_BOOT_DRIVER(clk_pllv3_sys) = {
> + .name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
> + .id = UCLASS_CLK,
> + .ops= &clk_pllv3_sys_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> U_BOOT_DRIVER(clk_pllv3_usb) = {
> .name = UBOOT_DM_CLK_IMX_PLLV3_USB,
> .id = UCLASS_CLK,
Reviewed-by: Lukasz Majewski
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [PATCH 04/20] clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB
On Wed, 4 Dec 2019 18:44:23 +0100
Giulio Benetti wrote:
> div_mask is different for GENERIC and USB pll, so set it according.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/clk/imx/clk-pllv3.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index d1e4c3fe30..02c75c37ea 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -55,9 +55,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
> type, const char *name, switch (type) {
> case IMX_PLLV3_GENERIC:
> drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
> + pll->div_shift = 0;
> break;
> case IMX_PLLV3_USB:
> drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
> + pll->div_shift = 1;
> break;
> default:
> kfree(pll);
Reviewed-by: Lukasz Majewski
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
pgpCu3oEjLXJA.pgp
Description: OpenPGP digital signature
Re: [PATCH 03/20] clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks
On Wed, 4 Dec 2019 18:44:22 +0100
Giulio Benetti wrote:
> Better to register the 2 clock as 2 different drivers because they
> work slightly differently depending on power_bit and powerup_set bits
> coming on next patches.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/clk/imx/clk-pllv3.c | 20 +++-
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index fbb7b24d5e..d1e4c3fe30 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -13,7 +13,8 @@
> #include
> #include "clk.h"
>
> -#define UBOOT_DM_CLK_IMX_PLLV3 "imx_clk_pllv3"
> +#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
> +#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
>
> struct clk_pllv3 {
> struct clk clk;
> @@ -24,7 +25,7 @@ struct clk_pllv3 {
>
> #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
>
> -static ulong clk_pllv3_get_rate(struct clk *clk)
> +static ulong clk_pllv3_generic_get_rate(struct clk *clk)
> {
> struct clk_pllv3 *pll =
> to_clk_pllv3(dev_get_clk_ptr(clk->dev)); unsigned long parent_rate =
> clk_get_parent_rate(clk); @@ -35,7 +36,7 @@ static ulong
> clk_pllv3_get_rate(struct clk *clk) }
>
> static const struct clk_ops clk_pllv3_generic_ops = {
> - .get_rate = clk_pllv3_get_rate,
> + .get_rate = clk_pllv3_generic_get_rate,
> };
>
> struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
> @@ -53,8 +54,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
> type, const char *name,
> switch (type) {
> case IMX_PLLV3_GENERIC:
> + drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
> + break;
> case IMX_PLLV3_USB:
> - drv_name = UBOOT_DM_CLK_IMX_PLLV3;
> + drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
> break;
> default:
> kfree(pll);
> @@ -75,7 +78,14 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
> type, const char *name, }
>
> U_BOOT_DRIVER(clk_pllv3_generic) = {
> - .name = UBOOT_DM_CLK_IMX_PLLV3,
> + .name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
> + .id = UCLASS_CLK,
> + .ops= &clk_pllv3_generic_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +U_BOOT_DRIVER(clk_pllv3_usb) = {
> + .name = UBOOT_DM_CLK_IMX_PLLV3_USB,
> .id = UCLASS_CLK,
> .ops= &clk_pllv3_generic_ops,
> .flags = DM_FLAG_PRE_RELOC,
Reviewed-by: Lukasz Majewski
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [PATCH 10/20] clk: imx: pfd: add set_rate()
On Wed, 4 Dec 2019 18:44:29 +0100
Giulio Benetti wrote:
> Implement set_rate() for pfd.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/clk/imx/clk-pfd.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c
> index 188b2b3b90..4ae55f5a07 100644
> --- a/drivers/clk/imx/clk-pfd.c
> +++ b/drivers/clk/imx/clk-pfd.c
> @@ -52,8 +52,30 @@ static unsigned long clk_pfd_recalc_rate(struct
> clk *clk) return tmp;
> }
>
> +static unsigned long clk_pfd_set_rate(struct clk *clk, unsigned long
> rate) +{
> + struct clk_pfd *pfd = to_clk_pfd(clk);
> + unsigned long parent_rate = clk_get_parent_rate(clk);
> + u64 tmp = parent_rate;
> + u8 frac;
> +
> + tmp = tmp * 18 + rate / 2;
> + do_div(tmp, rate);
> + frac = tmp;
> + if (frac < 12)
> + frac = 12;
> + else if (frac > 35)
> + frac = 35;
> +
> + writel(0x3f << (pfd->idx * 8), pfd->reg + CLR);
> + writel(frac << (pfd->idx * 8), pfd->reg + SET);
> +
> + return 0;
> +}
> +
> static const struct clk_ops clk_pfd_ops = {
> .get_rate = clk_pfd_recalc_rate,
> + .set_rate = clk_pfd_set_rate,
> };
>
> struct clk *imx_clk_pfd(const char *name, const char *parent_name,
Reviewed-by: Lukasz Majewski
Best regards,
Lukasz Majewski
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [PATCH 02/20] spl: fix entry_point equal to load_addr
On Wed, 4 Dec 2019 18:44:21 +0100
Giulio Benetti wrote:
> At the moment entry_point is set to image_get_load(header) that sets
> it to "load address" instead of "entry point", assuming entry_point is
> equal to load_addr, but it's not true. Then load_addr is set to
> "entry_point - header_size", but this is wrong too since load_addr is
> not an entry point.
>
> So use image_get_ep() for entry_point assignment and image_get_load()
> for load_addr assignment.
>
> Signed-off-by: Giulio Benetti
> ---
> common/spl/spl.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/common/spl/spl.c b/common/spl/spl.c
> index d51dbe9942..24da164b43 100644
> --- a/common/spl/spl.c
> +++ b/common/spl/spl.c
> @@ -264,9 +264,9 @@ int spl_parse_image_header(struct spl_image_info
> *spl_image, spl_image->entry_point = image_get_ep(header);
> spl_image->size =
> image_get_data_size(header); } else {
> - spl_image->entry_point =
> image_get_load(header);
> + spl_image->entry_point =
> image_get_ep(header); /* Load including the header */
> - spl_image->load_addr =
> spl_image->entry_point -
> + spl_image->load_addr =
> image_get_load(header) - header_size;
> spl_image->size =
> image_get_data_size(header) + header_size;
This may not be the case - but I do recall that there was a similar
issue between u-boot.bin and u-boot.imx being loaded.
What is the format of i.MXRT?
I'm also concerned about breaking already supported in-tree boards. Why
i.MXRT needs to make this change? And why other boards don't need that
fix? (do they all have load address equal to entry point ?)
Best regards,
Lukasz Majewski
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [PATCH 11/20] clk: imx: add i.IMXRT1050 clk driver
On Wed, 4 Dec 2019 18:44:30 +0100
Giulio Benetti wrote:
> Add i.MXRT1050 clk driver support.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/clk/imx/Kconfig | 16 ++
> drivers/clk/imx/Makefile| 2 +
> drivers/clk/imx/clk-imxrt1050.c | 292
> include/dt-bindings/clock/imxrt1050-clock.h |
> 65 + 4 files changed, 375 insertions(+)
> create mode 100644 drivers/clk/imx/clk-imxrt1050.c
> create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h
>
> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
> index 0ba8bc9f63..d5738b5211 100644
> --- a/drivers/clk/imx/Kconfig
> +++ b/drivers/clk/imx/Kconfig
> @@ -52,3 +52,19 @@ config CLK_IMX8MN
> select CLK_CCF
> help
> This enables support clock driver for i.MX8MN platforms.
> +
> +config SPL_CLK_IMXRT1050
> + bool "SPL clock support for i.MXRT1050"
> + depends on ARCH_IMXRT && SPL
> + select SPL_CLK
> + select SPL_CLK_CCF
> + help
> + This enables SPL DM/DTS support for clock driver in
> i.MXRT1050 +
> +config CLK_IMXRT1050
> + bool "Clock support for i.MXRT1050"
> + depends on ARCH_IMXRT
> + select CLK
> + select CLK_CCF
> + help
> + This enables support clock driver for i.MXRT1050 platforms.
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 222c5a4e08..166cb7bb44 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -14,3 +14,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o
> clk-pll14xx.o \ clk-composite-8m.o
> obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
> clk-composite-8m.o
> +
> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
> diff --git a/drivers/clk/imx/clk-imxrt1050.c
> b/drivers/clk/imx/clk-imxrt1050.c new file mode 100644
> index 00..44ca52c013
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imxrt1050.c
> @@ -0,0 +1,292 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright(C) 2019
> + * Author(s): Giulio Benetti
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "clk.h"
> +
> +static ulong imxrt1050_clk_get_rate(struct clk *clk)
> +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu)\n", __func__, clk->id);
> +
> + ret = clk_get_by_id(clk->id, &c);
> + if (ret)
> + return ret;
> +
> + return clk_get_rate(c);
> +}
> +
> +static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
> +
> + ret = clk_get_by_id(clk->id, &c);
> + if (ret)
> + return ret;
> +
> + return clk_set_rate(c, rate);
> +}
> +
> +static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
> +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
> +
> + ret = clk_get_by_id(clk->id, &c);
> + if (ret)
> + return ret;
> +
> + if (enable)
> + ret = clk_enable(c);
> + else
> + ret = clk_disable(c);
> +
> + return ret;
> +}
> +
> +static int imxrt1050_clk_disable(struct clk *clk)
> +{
> + return __imxrt1050_clk_enable(clk, 0);
> +}
> +
> +static int imxrt1050_clk_enable(struct clk *clk)
> +{
> + return __imxrt1050_clk_enable(clk, 1);
> +}
> +
> +static struct clk_ops imxrt1050_clk_ops = {
> + .set_rate = imxrt1050_clk_set_rate,
> + .get_rate = imxrt1050_clk_get_rate,
> + .enable = imxrt1050_clk_enable,
> + .disable = imxrt1050_clk_disable,
> +};
> +
> +static const char * const pll_ref_sels[] = {"osc", "dummy", };
> +static const char * const pll1_bypass_sels[] = {"pll1_arm",
> "pll1_arm_ref_sel", }; +static const char * const pll2_bypass_sels[]
> = {"pll2_sys", "pll2_sys_ref_sel", }; +static const char * const
> pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
> +static const char * const pll5_bypass_sels[] = {"pll5_video",
> "pll5_video_ref_sel", }; + +static const char *const
> pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m",
> "arm_podf", }; +static const char *const periph_sels[] = {
> "pre_periph_sel", "todo", }; +static const char *const usdhc_sels[] =
> { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const
> lpuart_sels[] = { "pll3_80m", "osc", }; +static const char *const
> semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static
> const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
> +static const char *const lcdif_sels[] = { "pll2_sys",
> "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m",
> "pll2_pfd1_594m", "pll3_pfd1_664_62m"}; + +static int
> imxrt1050_clk_probe(struct udevice *dev) +{
> + void *base;
> +
> + /* Anatop clocks */
> + base = (void *)ANATOP_BASE_ADDR;
> +
> + clk_dm(IMXRT1050_CLK
Re: [PATCH 12/20] pinctrl: add i.MXRT driver
On Wed, 4 Dec 2019 18:44:31 +0100
Giulio Benetti wrote:
> Add i.MXRT pinctrl driver.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/pinctrl/nxp/Kconfig | 14 ++
> drivers/pinctrl/nxp/Makefile| 1 +
> drivers/pinctrl/nxp/pinctrl-imxrt.c | 40
> + 3 files changed, 55 insertions(+)
> create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c
>
> diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
> index f2e67ca231..ec55351e61 100644
> --- a/drivers/pinctrl/nxp/Kconfig
> +++ b/drivers/pinctrl/nxp/Kconfig
> @@ -99,6 +99,20 @@ config PINCTRL_MXS
> familiy, e.g. i.MX28. This feature depends on device tree
> configuration.
>
> +config PINCTRL_IMXRT
> + bool "IMXRT pinctrl driver"
> + depends on ARCH_IMXRT && PINCTRL_FULL
> + select DEVRES
> + select PINCTRL_IMX
> + help
> + Say Y here to enable the imxrt pinctrl driver
> +
> + This provides a simple pinctrl driver for i.MXRT SoC
> familiy.
> + This feature depends on device tree configuration. This
> driver
> + is different from the linux one, this is a simple
> implementation,
Could you add proper documentation entry (in ./doc/*) in which you
would point out the differences between the full blown Linux driver and
this U-Boot driver (I do guess that "only parsing 'fsl,pins'" is not
the only difference - more details are welcome).
And a bit more generic request - it is also nice to add some kind of
./doc/README.* documentation in which one can put some hints (or usage
patterns) for in-uboot boards (like during development discovered HW
issues, etc.). Such information is priceless when other community
member wants to use this code/board (and NXP is very often silence
about them :-) ).
> + only parses the 'fsl,pins' property and configure related
> + registers.
> +
> config PINCTRL_VYBRID
> bool "Vybrid (vf610) pinctrl driver"
> depends on ARCH_VF610 && PINCTRL_FULL
> diff --git a/drivers/pinctrl/nxp/Makefile
> b/drivers/pinctrl/nxp/Makefile index b86448aac9..066ca75b65 100644
> --- a/drivers/pinctrl/nxp/Makefile
> +++ b/drivers/pinctrl/nxp/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_IMX8)+=
> pinctrl-imx8.o obj-$(CONFIG_PINCTRL_IMX8M)+=
> pinctrl-imx8m.o obj-$(CONFIG_PINCTRL_MXS) +=
> pinctrl-mxs.o obj-$(CONFIG_PINCTRL_VYBRID)+=
> pinctrl-vf610.o +obj-$(CONFIG_PINCTRL_IMXRT) +=
> pinctrl-imxrt.o diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c
> b/drivers/pinctrl/nxp/pinctrl-imxrt.c new file mode 100644
> index 00..4a93941927
> --- /dev/null
> +++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include "pinctrl-imx.h"
> +
> +static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {
> + .flags = ZERO_OFFSET_VALID,
> +};
> +
> +static int imxrt_pinctrl_probe(struct udevice *dev)
> +{
> + struct imx_pinctrl_soc_info *info =
> + (struct imx_pinctrl_soc_info
> *)dev_get_driver_data(dev); +
> + return imx_pinctrl_probe(dev, info);
> +}
> +
> +static const struct udevice_id imxrt_pinctrl_match[] = {
> + { .compatible = "fsl,imxrt-iomuxc",
> + .data = (ulong)&imxrt_pinctrl_soc_info },
> + { /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(imxrt_pinctrl) = {
> + .name = "imxrt-pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = of_match_ptr(imxrt_pinctrl_match),
> + .probe = imxrt_pinctrl_probe,
> + .remove = imx_pinctrl_remove,
> + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
> + .ops = &imx_pinctrl_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
Best regards,
Lukasz Majewski
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [PATCH 13/20] ARM: dts: imxrt1050: add dtsi file
On Wed, 4 Dec 2019 18:44:32 +0100
Giulio Benetti wrote:
> Add dtsi file for i.MXRT1050.
>
> Signed-off-by: Giulio Benetti
> ---
> arch/arm/dts/imxrt1050.dtsi | 146 +++
> include/dt-bindings/pinctrl/pins-imxrt1050.h | 993
> +++ 2 files changed, 1139 insertions(+)
> create mode 100644 arch/arm/dts/imxrt1050.dtsi
> create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h
>
> diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
> new file mode 100644
> index 00..4fcca098aa
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1050.dtsi
> @@ -0,0 +1,146 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2019
> + * Author(s): Giulio Benetti
> + */
> +
> +#include "skeleton.dtsi"
> +#include "armv7-m.dtsi"
> +#include
> +#include
> +#include
> +#include
> +
> +/ {
> + aliases {
> + gpio0 = &gpio1;
> + gpio1 = &gpio2;
> + gpio2 = &gpio3;
> + gpio3 = &gpio4;
> + gpio4 = &gpio5;
> + mmc0 = &usdhc1;
> + serial0 = &lpuart1;
> + };
> +
> + clocks {
> + u-boot,dm-spl;
> +
> + osc {
> + u-boot,dm-spl;
> + compatible = "fsl,imx-osc", "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <2400>;
> + };
> + };
> +
> + soc {
> + u-boot,dm-spl;
> +
> + semc: semc@402f {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-semc";
> + reg = <0x402f 0x4000>;
> + clocks = <&clks IMXRT_CLK_SEMC>;
> + pinctrl-0 = <&pinctrl_semc>;
> + pinctrl-names = "default";
> + status = "okay";
> + };
> +
> + lpuart1: serial@40184000 {
> + compatible = "fsl,imxrt-lpuart";
> + reg = <0x40184000 0x4000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMXRT_CLK_LPUART1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> +
> + iomuxc: iomuxc@401f8000 {
> + compatible = "fsl,imxrt-iomuxc";
> + reg = <0x401f8000 0x4000>;
> + fsl,mux_mask = <0x7>;
> + };
> +
> + clks: ccm@400fc000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-ccm";
> + reg = <0x400fc000 0x4000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + };
> +
> + usdhc1: usdhc@402c {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-usdhc";
> + reg = <0x402c 0x1>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMXRT_CLK_USDHC1>;
> + clock-names = "per";
> + bus-width = <4>;
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step= <2>;
> + status = "disabled";
> + };
> +
> + gpio1: gpio@401b8000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401b8000 0x4000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio@401bc000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401bc000 0x4000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>,
> + ;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio@401c {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401c 0x4000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH>,
> + ;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio@401c4000 {
> +
Re: [PATCH 14/20] serial_lpuart: add clock enable if CONFIG_CLK is defined
On Wed, 4 Dec 2019 18:44:33 +0100
Giulio Benetti wrote:
> This driver assumes that lpuart clock is already enabled before
> probing but using DM only lpuart won't be automatically enabled so add
> clk_enable() when probing if CONFIG_CLK is defined.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/serial/serial_lpuart.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/serial/serial_lpuart.c
> b/drivers/serial/serial_lpuart.c index 4b0a964d1b..52bd2baf7d 100644
> --- a/drivers/serial/serial_lpuart.c
> +++ b/drivers/serial/serial_lpuart.c
> @@ -483,6 +483,19 @@ static int lpuart_serial_pending(struct udevice
> *dev, bool input)
> static int lpuart_serial_probe(struct udevice *dev)
> {
> +#if CONFIG_IS_ENABLED(CLK)
> + struct clk per_clk;
> + int ret;
> +
> + ret = clk_get_by_name(dev, "per", &per_clk);
> + if (ret) {
> + dev_err(dev, "Failed to get per clk: %d\n", ret);
> + return ret;
> + }
> +
> + clk_enable(&per_clk);
> +#endif
> +
I think that this change will _silently_ break all boards which do have
CONFIG_CLK enabled (for some clocks/drivers), but did not yet provided
CCF definition for lpuart clock.
Was this series checked with travis-ci?
For example:
https://travis-ci.org/lmajewski/u-boot-dfu/jobs/66547
> if (is_lpuart32(dev))
> return _lpuart32_serial_init(dev);
> else
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [PATCH 15/20] serial_lpuart: add support for i.MXRT
On Wed, 4 Dec 2019 18:44:34 +0100
Giulio Benetti wrote:
> Add i.MXRT compatible string and cpu type support to lpuart driver,
> to use little endian 32 bits configurations.
>
> Also according to RM, the Receive RX FIFO Enable (RXFE) field in
> LPUART FIFO register is bit 3, so this definition should change to
> 0x08 as done for i.MX8. It needs also to set baudrate the same way as
> i.MX8 does.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/serial/serial_lpuart.c | 15 +++
> include/fsl_lpuart.h | 3 ++-
> 2 files changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/serial/serial_lpuart.c
> b/drivers/serial/serial_lpuart.c index 52bd2baf7d..2ac4c6d56a 100644
> --- a/drivers/serial/serial_lpuart.c
> +++ b/drivers/serial/serial_lpuart.c
> @@ -49,7 +49,7 @@
> #define FIFO_RXSIZE_MASK 0x7
> #define FIFO_RXSIZE_OFF 0
> #define FIFO_TXFE0x80
> -#ifdef CONFIG_ARCH_IMX8
> +#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
> #define FIFO_RXFE0x08
> #else
> #define FIFO_RXFE0x40
> @@ -67,7 +67,8 @@ enum lpuart_devtype {
> DEV_VF610 = 1,
> DEV_LS1021A,
> DEV_MX7ULP,
> - DEV_IMX8
> + DEV_IMX8,
> + DEV_IMXRT,
> };
>
> struct lpuart_serial_platdata {
> @@ -409,7 +410,8 @@ static int _lpuart32_serial_init(struct udevice
> *dev)
> lpuart_write32(plat->flags, &base->match, 0);
>
> - if (plat->devtype == DEV_MX7ULP || plat->devtype ==
> DEV_IMX8) {
> + if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8
> ||
> + plat->devtype == DEV_IMXRT) {
> _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
> } else {
> /* provide data bits, parity, stop bit, etc */
> @@ -426,7 +428,8 @@ static int lpuart_serial_setbrg(struct udevice
> *dev, int baudrate) struct lpuart_serial_platdata *plat =
> dev_get_platdata(dev);
> if (is_lpuart32(dev)) {
> - if (plat->devtype == DEV_MX7ULP || plat->devtype ==
> DEV_IMX8)
> + if (plat->devtype == DEV_MX7ULP || plat->devtype ==
> DEV_IMX8 ||
> + plat->devtype == DEV_IMXRT)
> _lpuart32_serial_setbrg_7ulp(dev, baudrate);
> else
> _lpuart32_serial_setbrg(dev, baudrate);
> @@ -527,6 +530,8 @@ static int
> lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->devtype =
> DEV_VF610; else if (!fdt_node_check_compatible(blob, node,
> "fsl,imx8qm-lpuart")) plat->devtype = DEV_IMX8;
> + else if (!fdt_node_check_compatible(blob, node,
> "fsl,imxrt-lpuart"))
> + plat->devtype = DEV_IMXRT;
>
> return 0;
> }
> @@ -546,6 +551,8 @@ static const struct udevice_id
> lpuart_serial_ids[] = { { .compatible = "fsl,vf610-lpuart"},
> { .compatible = "fsl,imx8qm-lpuart",
> .data = LPUART_FLAG_REGMAP_32BIT_REG },
> + { .compatible = "fsl,imxrt-lpuart",
> + .data = LPUART_FLAG_REGMAP_32BIT_REG },
> { }
> };
>
> diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
> index fc517d4b7f..511fb84367 100644
> --- a/include/fsl_lpuart.h
> +++ b/include/fsl_lpuart.h
> @@ -4,7 +4,8 @@
> *
> */
>
> -#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
> +#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
> + defined(CONFIG_ARCH_IMXRT)
> struct lpuart_fsl_reg32 {
> u32 verid;
> u32 param;
Please also used buildman to check if this patch series is bisectable
(i.e. if it can be build without errors for each separate commit).
For example:
./tools/buildman/buildman.py --branch=HEAD odroid edison trats trats2
--show_errors --force-build --count=4 --output-dir=../BUILD/
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
pgpZAWglhSkaS.pgp
Description: OpenPGP digital signature
Re: [PATCH 09/20] clk: imx: pllv3: add support for PLLV3_AV type
On Wed, 4 Dec 2019 18:44:28 +0100
Giulio Benetti wrote:
> Add support for PLLV3 AV type.
>
> Signed-off-by: Giulio Benetti
> ---
> drivers/clk/imx/clk-pllv3.c | 76
> + 1 file changed, 76 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index d5087a104e..fc16416d5f 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -6,6 +6,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -16,6 +17,10 @@
> #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
> #define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
> #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
> +#define UBOOT_DM_CLK_IMX_PLLV3_AV"imx_clk_pllv3_av"
> +
> +#define PLL_NUM_OFFSET 0x10
> +#define PLL_DENOM_OFFSET 0x20
>
> #define BM_PLL_POWER (0x1 << 12)
> #define BM_PLL_LOCK (0x1 << 31)
> @@ -143,6 +148,65 @@ static const struct clk_ops clk_pllv3_sys_ops = {
> .set_rate = clk_pllv3_sys_set_rate,
> };
>
> +static ulong clk_pllv3_av_get_rate(struct clk *clk)
> +{
> + struct clk_pllv3 *pll = to_clk_pllv3(clk);
> + unsigned long parent_rate = clk_get_parent_rate(clk);
> + u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
> + u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
> + u32 div = readl(pll->base) & pll->div_mask;
> + u64 temp64 = (u64)parent_rate;
> +
> + temp64 *= mfn;
> + do_div(temp64, mfd);
> +
> + return parent_rate * div + (unsigned long)temp64;
> +}
> +
> +static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
> +{
> + struct clk_pllv3 *pll = to_clk_pllv3(clk);
> + unsigned long parent_rate = clk_get_parent_rate(clk);
> + unsigned long min_rate = parent_rate * 27;
> + unsigned long max_rate = parent_rate * 54;
> + u32 val, div;
> + u32 mfn, mfd = 100;
> + u32 max_mfd = 0x3FFF;
> + u64 temp64;
> +
> + if (rate < min_rate || rate > max_rate)
> + return -EINVAL;
> +
> + if (parent_rate <= max_mfd)
> + mfd = parent_rate;
> +
> + div = rate / parent_rate;
> + temp64 = (u64)(rate - div * parent_rate);
> + temp64 *= mfd;
> + do_div(temp64, parent_rate);
> + mfn = temp64;
> +
> + val = readl(pll->base);
> + val &= ~pll->div_mask;
> + val |= div;
> + writel(val, pll->base);
> + writel(mfn, pll->base + PLL_NUM_OFFSET);
> + writel(mfd, pll->base + PLL_DENOM_OFFSET);
> +
> + /* Wait for PLL to lock */
> + while (!(readl(pll->base) & BM_PLL_LOCK))
> + ;
> +
> + return 0;
> +}
> +
> +static const struct clk_ops clk_pllv3_av_ops = {
> + .enable = clk_pllv3_generic_enable,
> + .disable= clk_pllv3_generic_disable,
> + .get_rate = clk_pllv3_av_get_rate,
> + .set_rate = clk_pllv3_av_set_rate,
> +};
> +
> struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
> const char *parent_name, void __iomem
> *base, u32 div_mask)
> @@ -174,6 +238,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type
> type, const char *name, pll->div_shift = 1;
> pll->powerup_set = true;
> break;
> + case IMX_PLLV3_AV:
> + drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
> + pll->div_shift = 0;
> + pll->powerup_set = false;
> + break;
> default:
> kfree(pll);
> return ERR_PTR(-ENOTSUPP);
> @@ -212,3 +281,10 @@ U_BOOT_DRIVER(clk_pllv3_usb) = {
> .ops= &clk_pllv3_generic_ops,
> .flags = DM_FLAG_PRE_RELOC,
> };
> +
> +U_BOOT_DRIVER(clk_pllv3_av) = {
> + .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
> + .id = UCLASS_CLK,
> + .ops= &clk_pllv3_av_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
I don't mind about adding this new functionality, but I'm a bit
concerned about increase if the size of SPL binary (as it sets the
DM_FLAG_PRE_RELOC).
Do you have any data about increase of the final binary size?
The buildman script has options to check the difference of the final
binary (i.e. SPL) size (as provided by Tom Rini):
./tools/buildman/$ export SOURCE_DATE_EPOCH=`date +%s`
$ ./tools/buildman/buildman -o /tmp/test --step 0 -b origin/master..
--force-build -CveE
$ ./tools/buildman/buildman -o /tmp/test --step 0 -b origin/master.. -Ssdel
to get size changes between point A and point Z in a branch, and omit
--step 0 when I need to see which patch in between them caused the size
change.
If the SPL growth is too big - maybe we shall introduce some Kconfig
options to add a separate support for those PLLv3 options ?
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
pgpP9hY
Re: i.MX8MM-EVK Boot failure
On Sun, Dec 8, 2019 at 6:50 AM Adam Ford wrote: > > On Sat, Dec 7, 2019 at 12:25 PM Tom Rini wrote: > > > > On Sat, Dec 07, 2019 at 08:42:32AM -0600, Adam Ford wrote: > > > > > I am trying to run the latest master > > > > > > 4b19b89ca4a866b7baa642533e6dbd67cd832d27 > > > with the clock patches applied for 8mm, but I am getting a boot > > > failure when I follow the instructions in the README, which are also a > > > bit wrong. (the firmware versions don't match, and the ./firmware > > > command is missing the trailing '.bin', but it's trivial.) > > > > > > What comes out of the kit with DEBUG enabled is: > > > > > > (bunch of stuff deleted) > > > > > > [PMU Major message = 0x00fe] > > > [PMU Major message = 0x0007] > > > Training PASS > > > DDRINFO: ddrphy config done > > > DDRINFO:ddrphy calibration done > > > DDRINFO: ddrmix config done > > > >>SPL: board_init_r() > > > using memory lx-lx for malloc() > > > spl_init > > > Normal Boot > > > Trying to boot from MMC1 > > > common/dlmalloc.c:792: do_check_inuse_chunk: Assertion `inuse(p)' failed. > > > resetting ... > > > > > > The above sequence repeats again and again. I didn't put all the junk > > > into the log because it looked like everything seemed OK until the > > > dlmalloc failure at the end. If someone has any suggestions, I'd like > > > to try the 8mm-evk with a modern U-Boot. > > > > I think (per the thread about fixing one of the colibri platforms) this > > also needs a CONFIG_FSL_ESDHC -> CONFIG_FSL_ESDHC_IMX fix in the board > > file. > > I am not seeing a reference to either CONFIG_FSL_ESDHC or > CONFIG_FSL_ESDHC_IMX in the imx8mm_evk board files, and it appears as > if the device tree and DM_SPL stuff is managing the drivers. The > defconfig file is enabling CONFIG_FSL_ESDHC_IMX. > > It seems like a memory issue based on: >common/dlmalloc.c:792: do_check_inuse_chunk: Assertion `inuse(p)' failed. > I switched the imx8mm-evk to use CONFIG_SPL_SYS_MALLOC_SIMPLE=y, and it appears to fix one error, but I get a different one in its place. For booting from microSD, the proper USDHC controller is located at 30b5, but it's unclear to me which one it's trying to use: spl: mmc boot mode: raw blk_find_device: if_type=6, devnum=1: m...@30b5.blk, 6, 0 blk_find_device: if_type=6, devnum=1: m...@30b6.blk, 6, 1 hdr read sector 300, count=1 mkimage signature not found - ih_magic = 0 blk_find_device: if_type=6, devnum=1: m...@30b5.blk, 6, 0 blk_find_device: if_type=6, devnum=1: m...@30b6.blk, 6, 1 read 400 sectors to 4020 Jumping to U-Boot loaded - jumping to U-Boot... image entry point: 0x4020 It looks like it might be trying both or falling back to a different MMC device. The fact that it gets "mkimage signature not found - ih_magic = 0" indicates to me that maybe it's either reading from the wrong sdhc controller or the wrong address. I am still learning how the 'make flash.bin' stuff works, and/or where the u-boot raw file gets placed since it appears to be all one bundled image burned to SDHC. I think I'm making progress, but I think the original statement about memory an memory issue is interesting to me. I am not sure why simple malloc would work, but the standard malloc would fail. adam > adam > > > > > > > -- > > Tom
Please pull u-boot-x86
Hi Tom, This PR includes the following x86 changes for v2020.01. - 16-bit start up codes clean up The following changes since commit d79ae6aa3087a6434b5ecdb51d20dca20c8e1596: Merge branch '2019-12-06-master-imports' (2019-12-06 16:45:46 -0500) are available in the git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-x86 for you to fetch changes up to 90ab311a7c1ee91201c23726871d20b2287a51a5: x86: simplify ljmp to 32-bit code (2019-12-08 19:10:21 +0800) Masahiro Yamada (2): x86: use data32 directive instead of macro for operand-size prefix x86: simplify ljmp to 32-bit code arch/x86/cpu/start16.S | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) Regards, Bin
Re: i.MX8MM-EVK Boot failure
Hi Adam follow my answer On Sun, Dec 8, 2019 at 4:35 PM Adam Ford wrote: > > On Sun, Dec 8, 2019 at 6:50 AM Adam Ford wrote: > > > > On Sat, Dec 7, 2019 at 12:25 PM Tom Rini wrote: > > > > > > On Sat, Dec 07, 2019 at 08:42:32AM -0600, Adam Ford wrote: > > > > > > > I am trying to run the latest master > > > > > > > > 4b19b89ca4a866b7baa642533e6dbd67cd832d27 > > > > with the clock patches applied for 8mm, but I am getting a boot > > > > failure when I follow the instructions in the README, which are also a > > > > bit wrong. (the firmware versions don't match, and the ./firmware > > > > command is missing the trailing '.bin', but it's trivial.) > > > > > > > > What comes out of the kit with DEBUG enabled is: > > > > > > > > (bunch of stuff deleted) > > > > > > > > [PMU Major message = 0x00fe] > > > > [PMU Major message = 0x0007] > > > > Training PASS > > > > DDRINFO: ddrphy config done > > > > DDRINFO:ddrphy calibration done > > > > DDRINFO: ddrmix config done > > > > >>SPL: board_init_r() > > > > using memory lx-lx for malloc() > > > > spl_init > > > > Normal Boot > > > > Trying to boot from MMC1 > > > > common/dlmalloc.c:792: do_check_inuse_chunk: Assertion `inuse(p)' > > > > failed. > > > > resetting ... > > > > > > > > The above sequence repeats again and again. I didn't put all the junk > > > > into the log because it looked like everything seemed OK until the > > > > dlmalloc failure at the end. If someone has any suggestions, I'd like > > > > to try the 8mm-evk with a modern U-Boot. > > > > > > I think (per the thread about fixing one of the colibri platforms) this > > > also needs a CONFIG_FSL_ESDHC -> CONFIG_FSL_ESDHC_IMX fix in the board > > > file. > > > > I am not seeing a reference to either CONFIG_FSL_ESDHC or > > CONFIG_FSL_ESDHC_IMX in the imx8mm_evk board files, and it appears as > > if the device tree and DM_SPL stuff is managing the drivers. The > > defconfig file is enabling CONFIG_FSL_ESDHC_IMX. > > > > It seems like a memory issue based on: > >common/dlmalloc.c:792: do_check_inuse_chunk: Assertion `inuse(p)' failed. > > simple malloc allo on the stack. If you can see form tinker-s I give 0x30 space to it just because mmc driver use simple malloc to allocate buffer. You can easily finish it CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x30 Reason is max transfer 65000 x blk size Michael > > I switched the imx8mm-evk to use CONFIG_SPL_SYS_MALLOC_SIMPLE=y, and > it appears to fix one error, but I get a different one in its place. > > For booting from microSD, the proper USDHC controller is located at > 30b5, but it's unclear to me which one it's trying to use: > > spl: mmc boot mode: raw > blk_find_device: if_type=6, devnum=1: m...@30b5.blk, 6, 0 > blk_find_device: if_type=6, devnum=1: m...@30b6.blk, 6, 1 > hdr read sector 300, count=1 > mkimage signature not found - ih_magic = 0 > blk_find_device: if_type=6, devnum=1: m...@30b5.blk, 6, 0 > blk_find_device: if_type=6, devnum=1: m...@30b6.blk, 6, 1 > read 400 sectors to 4020 > Jumping to U-Boot > loaded - jumping to U-Boot... > image entry point: 0x4020 > > It looks like it might be trying both or falling back to a different MMC > device. > > The fact that it gets "mkimage signature not found - ih_magic = 0" > indicates to me that maybe it's either reading from the wrong sdhc > controller or the wrong address. > > I am still learning how the 'make flash.bin' stuff works, and/or where > the u-boot raw file gets placed since it appears to be all one bundled > image burned to SDHC. > > I think I'm making progress, but I think the original statement about > memory an memory issue is interesting to me. I am not sure why simple > malloc would work, but the standard malloc would fail. > > adam > > > adam > > > > > > > > > > > > -- > > > Tom -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com |
Re: Please pull u-boot-x86
On Sun, Dec 08, 2019 at 11:49:35PM +0800, Bin Meng wrote: > Hi Tom, > > This PR includes the following x86 changes for v2020.01. > > - 16-bit start up codes clean up > > The following changes since commit d79ae6aa3087a6434b5ecdb51d20dca20c8e1596: > > Merge branch '2019-12-06-master-imports' (2019-12-06 16:45:46 -0500) > > are available in the git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-x86 > > for you to fetch changes up to 90ab311a7c1ee91201c23726871d20b2287a51a5: > > x86: simplify ljmp to 32-bit code (2019-12-08 19:10:21 +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH 1/3] mx7dsabre: Remove warning about DM_SPI_FLASH
This defconfig doesn't need it. Signed-off-by: Joris Offouga --- configs/mx7dsabresd_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 2a9fdac338..3dac7136d2 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -55,9 +55,6 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_EON=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PINCTRL=y -- 2.20.1
[PATCH] pico-imx7d: Convert to DM_ETH
Signed-off-by: Joris Offouga
---
board/technexion/pico-imx7d/pico-imx7d.c | 46
configs/pico-dwarf-imx7d_defconfig | 5 +++
configs/pico-hobbit-imx7d_defconfig | 5 +++
configs/pico-imx7d_bl33_defconfig| 5 +++
configs/pico-imx7d_defconfig | 5 +++
configs/pico-nymph-imx7d_defconfig | 5 +++
configs/pico-pi-imx7d_defconfig | 5 +++
include/configs/pico-imx7d.h | 11 --
8 files changed, 30 insertions(+), 57 deletions(-)
diff --git a/board/technexion/pico-imx7d/pico-imx7d.c
b/board/technexion/pico-imx7d/pico-imx7d.c
index bcfc7d361e..b7ca2e1315 100644
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -16,7 +16,6 @@
#include
#include
#include
-#include
#include
#include
#include "../../freescale/common/pfuze.h"
@@ -26,11 +25,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-
#define I2C_PAD_CTRL(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
@@ -123,44 +117,6 @@ static iomux_v3_cfg_t const uart5_pads[] = {
};
#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
-
-static void setup_iomux_fec(void)
-{
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
- gpio_request(FEC1_RST_GPIO, "phy_rst");
- gpio_direction_output(FEC1_RST_GPIO, 0);
- udelay(500);
- gpio_set_value(FEC1_RST_GPIO, 1);
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_fec();
-
- return fecmxc_initialize_multi(bis, 0,
- CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-}
-
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
@@ -235,9 +191,7 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_DM_VIDEO
-
setup_lcd();
-
#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
diff --git a/configs/pico-dwarf-imx7d_defconfig
b/configs/pico-dwarf-imx7d_defconfig
index 94d73ee051..2437a64dd0 100644
--- a/configs/pico-dwarf-imx7d_defconfig
+++ b/configs/pico-dwarf-imx7d_defconfig
@@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
diff --git a/configs/pico-hobbit-imx7d_defconfig
b/configs/pico-hobbit-imx7d_defconfig
index ef86b0cd66..3467d4c2e4 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
diff --git a/configs/pico-imx7d_bl33_defconfig
b/configs/pico-imx7d_bl33_defconfig
index 51d3514072..49a4e1b0c1 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -50,6 +50,11 @@ CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index bf4d56ec2c..a197
[PATCH 3/3] mx7dsabre: Convert to distroboot support
Signed-off-by: Joris Offouga
---
configs/mx7dsabresd_defconfig | 13 ++---
configs/mx7dsabresd_qspi_defconfig | 14 ++---
include/configs/mx7dsabresd.h | 84 ++
3 files changed, 25 insertions(+), 86 deletions(-)
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 48aa15a199..d15de386fc 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -9,13 +9,13 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
+CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
@@ -30,17 +30,13 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -78,7 +74,6 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/mx7dsabresd_qspi_defconfig
b/configs/mx7dsabresd_qspi_defconfig
index c105560305..b2d5dc1c22 100644
--- a/configs/mx7dsabresd_qspi_defconfig
+++ b/configs/mx7dsabresd_qspi_defconfig
@@ -4,17 +4,18 @@ CONFIG_SYS_TEXT_BASE=0x8780
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC
+CONFIG_NR_DRAM_BANKS=1
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
+CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
@@ -29,17 +30,13 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -84,7 +81,6 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index f574669644..b1726b1d88 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -74,76 +74,25 @@
"image=zImage\0" \
"console=ttymxc0\0" \
"fdt_high=0x\0" \
+ "finduuid=part uuid mmc 0:1 uuid\0" \
"initrd_high=0x\0" \
- "fdt_file=imx7d-sdb.dtb\0" \
+ "fdtfile=imx7d-sdb.dtb\0" \
"fdt_addr=0x8300\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
+ "fdt_addr_r=0x8300\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "ramdisk_addr_r=0x8300\0" \
+ "ramdiskaddr=0x8300\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0"
\
- "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
- "mmcautodetect=yes\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "i
[PATCH 2/3] mx7dsabre: Enable DM_ETH
Also sync device tree with v5.5-rc1
Signed-off-by: Joris Offouga
---
arch/arm/dts/imx7d-sdb-u-boot.dtsi| 3 +
arch/arm/dts/imx7d-sdb.dts| 785 --
board/freescale/mx7dsabresd/mx7dsabresd.c | 62 --
configs/mx7dsabresd_defconfig | 6 +
configs/mx7dsabresd_qspi_defconfig| 6 +
include/configs/mx7dsabresd.h | 10 -
6 files changed, 589 insertions(+), 283 deletions(-)
create mode 100644 arch/arm/dts/imx7d-sdb-u-boot.dtsi
diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi
b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
new file mode 100644
index 00..05dd74eee1
--- /dev/null
+++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
@@ -0,0 +1,3 @@
+&fec2 {
+ status = "disable";
+};
diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts
index 76aa69a35b..8191ac7c33 100644
--- a/arch/arm/dts/imx7d-sdb.dts
+++ b/arch/arm/dts/imx7d-sdb.dts
@@ -11,253 +11,244 @@
model = "Freescale i.MX7 SabreSD Board";
compatible = "fsl,imx7d-sdb", "fsl,imx7d";
- aliases {
- spi5 = &soft_spi;
+ chosen {
+ stdout-path = &uart1;
};
- memory {
+ memory@8000 {
+ device_type = "memory";
reg = <0x8000 0x8000>;
};
- soft_spi: soft-spi {
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ wakeup-source;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ wakeup-source;
+ };
+ };
+
+ spi4 {
compatible = "spi-gpio";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1>;
- status = "okay";
- gpio-sck = <&gpio1 13 0>;
- gpio-mosi = <&gpio1 9 0>;
- cs-gpios = <&gpio1 12 0>;
+ pinctrl-0 = <&pinctrl_spi4>;
+ gpio-sck = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ gpio-mosi = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
- gpio_spi: gpio_spi@0 {
+ extended_io: gpio-expander@0 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
registers-number = <1>;
- registers-default = /bits/ 8 <0x74>; /* Enable
PERI_3V3, SENSOR_RST_B and HDMI_RST*/
spi-max-frequency = <10>;
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_usb_otg1_vbus: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_usb_otg2_vbus: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "usb_otg2_vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_sd1_vmmc: regulator
Re: [PATCH] pico-imx7d: Convert to DM_ETH
On Sun, Dec 8, 2019 at 2:03 PM Joris Offouga wrote: > > Signed-off-by: Joris Offouga Reviewed-by: Otavio Salvador -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://code.ossystems.com.br Mobile: +55 (53) 9 9981-7854 Mobile: +1 (347) 903-9750
Re: [PATCH 0/2] sandbox: enable UEFI unit tests
Hi Heinrich, On Sat, 7 Dec 2019 at 17:31, Heinrich Schuchardt wrote: > > On 11/9/19 9:39 AM, Heinrich Schuchardt wrote: > > This patch series enables the UEFI unit tests on the sandbox. > > > > The first patch add the missing compatible property in the device trees > > which is required by on of the unit tests. > > > > The real time clock unit test will fail if the sandbox is openend without > > passing a device tree (parameter -D). > > > > A separate series will enable building UEFI binaries for the sandbox and > > enable the corresponding UEFI unit tests. > > > > Heinrich Schuchardt (2): > >sandbox: add missing compatible property in device tree > >configs: sandbox: enable CONFIG_CMD_BOOTEFI_SELFTEST > > > > arch/sandbox/dts/sandbox.dts | 1 + > > arch/sandbox/dts/sandbox64.dts | 1 + > > configs/sandbox64_defconfig| 1 + > > configs/sandbox_defconfig | 1 + > > configs/sandbox_flattree_defconfig | 1 + > > configs/sandbox_spl_defconfig | 1 + > > 6 files changed, 6 insertions(+) > > > > -- > > 2.24.0.rc1 > > > > Hello Simon, > > this patch series is currently assigned to you as maintainer of the > sandbox. I hope you can add it to your next tree. Yes I'm planning to set up one up for the next release soon. Regards, Simon
[PATCH v6] imx: Add support for i.MX28 based XEA board
This patch introduces support for i.MX28 based XEA board.
This board supports DM/DTS in U-Boot proper as well as DM aware drivers
in SPL (u-boot.sb) by using OF_PLATDATA.
More detailed information regarding usage of it can be found in
./board/liebherr/xea/README file.
U-Boot SPL 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200)
Trying to boot from MMC1
MMC0: Command 8 timeout (status 0xf0344020)
mmc_load_image_raw_sector: mmc block read error
U-Boot 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200)
CPU: Freescale i.MX28 rev1.2 at 454 MHz
BOOT: SSP SPI #3, master, 3V3 NOR
Model: Liebherr (LWE) XEA i.MX28 Board
DRAM: 128 MiB
MMC: MXS MMC: 0
Loading Environment from SPI Flash... SF: Detected n25q128a13 with page size
256 Bytes, erase size 64 KiB, total 16 MiB
OK
In:serial
Out: serial
Err: serial
Net:
Warning: ethernet@800f (eth0) using random MAC address - ce:e1:9e:46:f3:a2
eth0: ethernet@800f
Hit any key to stop autoboot: 0
Signed-off-by: Lukasz Majewski
---
Changes in v6:
- Use SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG in the imx28_xea_defconfig
- Add missing #include to boards/liebherr/xea/xea.c to avoid gcc
build warning (and finally the error as all warnings are treated as
errors) for version > 6.4.x (e.g. 7.x.y).
Changes in v5:
- Define SPL_FORCE_MMC_BOOT in imx28_xea_defconfig
Changes in v4:
- Remove non needed imx28_xea_defconfig defines after introducing
SPL_DM_SPI
- Update dependencies list after introducing SPL_DM_SPI
- Fix problem with 'mtd' command
Changes in v3:
- Use Kconfig defined option (CONFIG_FS_EXT4) instead of the one defined
in xea.h
- Use Kconfig defined option (CONFIG_SYS_SPI_U_BOOT_OFFS) instead of the one
defined in xea.h
- Provide correct SDPX header for xea.h
Changes in v2:
- Adjust config to match dependent patches
- Increase malloc size to allow booting the board with GPIO DM/DTS support
- Add support for GPIO driver in SPL (with DM + OF_PLATDATA)
- Adjust spl_xea.c to support bootmode pins
- Add patches to set in Kconfig default boot HW partition for eMMC
Applied on top of -master branch:
SHA1: d79ae6aa3087a6434b5ecdb51d20dca20c8e1596
Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/jobs/66547
(No extra dependencies - everything needed is in -master now)
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/imx28-xea-u-boot.dtsi | 46 +
arch/arm/dts/imx28-xea.dts | 110 +++
arch/arm/mach-imx/mxs/Kconfig | 4 +
board/liebherr/xea/Kconfig | 24 +++
board/liebherr/xea/MAINTAINERS | 6 +
board/liebherr/xea/Makefile| 12 ++
board/liebherr/xea/README | 63 ++
board/liebherr/xea/spl_xea.c | 303 +
board/liebherr/xea/xea.c | 153 +++
configs/imx28_xea_defconfig| 108 ++
include/configs/xea.h | 196 +++
12 files changed, 1028 insertions(+)
create mode 100644 arch/arm/dts/imx28-xea-u-boot.dtsi
create mode 100644 arch/arm/dts/imx28-xea.dts
create mode 100644 board/liebherr/xea/Kconfig
create mode 100644 board/liebherr/xea/MAINTAINERS
create mode 100644 board/liebherr/xea/Makefile
create mode 100644 board/liebherr/xea/README
create mode 100644 board/liebherr/xea/spl_xea.c
create mode 100644 board/liebherr/xea/xea.c
create mode 100644 configs/imx28_xea_defconfig
create mode 100644 include/configs/xea.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3dc9c4d41c..cc39129556 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -568,6 +568,9 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-pcm052.dtb \
vf610-bk4r1.dtb
+dtb-$(CONFIG_MX28) += \
+ imx28-xea.dtb
+
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
imx53-kp.dtb \
imx53-m53menlo.dtb
diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi
b/arch/arm/dts/imx28-xea-u-boot.dtsi
new file mode 100644
index 00..cc2ced5d2d
--- /dev/null
+++ b/arch/arm/dts/imx28-xea-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019
+ * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/*
+ * The minimal augmentation DTS U-Boot file to allow eMMC driver
+ * configuration in SPL for falcon boot.
+ */
+#include "imx28-u-boot.dtsi"
+/ {
+ apb@8000 {
+ u-boot,dm-spl;
+
+ apbh@8000 {
+ u-boot,dm-spl;
+ };
+
+ apbx@8004 {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&clks {
+ u-boot,dm-spl;
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+};
+
+&ssp0 {
+ u-boot,dm-spl;
+};
+
+&ssp3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx28-xea.dts b/arch/arm/dts/imx28-xea.dts
new file mode 100644
index 00..5de6774c5a
--- /dev/null
+++ b/arch/arm/dts/imx28-x
[PATCH v2 1/4] spl: opensbi: specify main hart as preferred boot hart
OpenSBI uses a relocation lottery to determine the hart to relocate
OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart
schedules the secondary harts to enter OpenSBI before doing so itself.
One of the secondary harts will therefore always be the winner of the
relocation lottery. This is problematic if the link address ranges of
OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore
overwrite U-Boot SPL while some harts may still run it, leading to code
corruption.
Avoid this problem by specifying the main hart as the preferred boot
hart to perform the OpenSBI relocation. The main hart will be the last
hart to enter OpenSBI, relocation can therefore occur safely.
The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC
info structure. The header file include/opensbi.h is synchronized with
include/sbi/fw_dynamic.h from the OpenSBI project to update the info
structure. The header file is recent as of commit
7a13beb21326 ("firmware: Add preferred boot HART field in struct
fw_dynamic_info").
Reported-by: Rick Chen
Suggested-by: Anup Patel
Signed-off-by: Lukas Auer
Reviewed-by: Rick Chen
Tested-by: Rick Chen
Reviewed-by: Anup Patel
---
Changes in v2: None
common/spl/spl_opensbi.c | 1 +
include/opensbi.h| 18 +-
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 2345f949f0..fed41b1e66 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -70,6 +70,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image)
opensbi_info.next_addr = uboot_entry;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = SBI_SCRATCH_NO_BOOT_PRINTS;
+ opensbi_info.boot_hart = gd->arch.boot_hart;
opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point;
invalidate_icache_all();
diff --git a/include/opensbi.h b/include/opensbi.h
index 9f1d62e7dd..d812cc8ccd 100644
--- a/include/opensbi.h
+++ b/include/opensbi.h
@@ -11,7 +11,7 @@
#define FW_DYNAMIC_INFO_MAGIC_VALUE0x4942534f
/** Maximum supported info version */
-#define FW_DYNAMIC_INFO_VERSION0x1
+#define FW_DYNAMIC_INFO_VERSION0x2
/** Possible next mode values */
#define FW_DYNAMIC_INFO_NEXT_MODE_U0x0
@@ -35,6 +35,22 @@ struct fw_dynamic_info {
unsigned long next_mode;
/** Options for OpenSBI library */
unsigned long options;
+ /**
+* Preferred boot HART id
+*
+* It is possible that the previous booting stage uses same link
+* address as the FW_DYNAMIC firmware. In this case, the relocation
+* lottery mechanism can potentially overwrite the previous booting
+* stage while other HARTs are still running in the previous booting
+* stage leading to boot-time crash. To avoid this boot-time crash,
+* the previous booting stage can specify last HART that will jump
+* to the FW_DYNAMIC firmware as the preferred boot HART.
+*
+* To avoid specifying a preferred boot HART, the previous booting
+* stage can set it to -1UL which will force the FW_DYNAMIC firmware
+* to use the relocation lottery mechanism.
+*/
+ unsigned long boot_hart;
} __packed;
#endif
--
2.21.0
[PATCH v2 3/4] riscv: add option to wait for ack from secondary harts in smp functions
Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.
As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.
Signed-off-by: Lukas Auer
Reviewed-by: Rick Chen
Tested-by: Rick Chen
Reviewed-by: Anup Patel
---
Changes in v2: None
arch/riscv/cpu/start.S | 2 ++
arch/riscv/include/asm/smp.h | 3 ++-
arch/riscv/lib/bootm.c | 2 +-
arch/riscv/lib/smp.c | 31 ++-
arch/riscv/lib/spl.c | 2 +-
common/spl/spl_opensbi.c | 2 +-
6 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 0a2ce6d691..60631638dd 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -197,6 +197,7 @@ spl_secondary_hart_stack_gd_setup:
la a0, secondary_hart_relocate
mv a1, s0
mv a2, s0
+ mv a3, zero
jal smp_call_function
/* hang if relocation of secondary harts has failed */
@@ -337,6 +338,7 @@ relocate_secondary_harts:
mv a1, s2
mv a2, s3
+ mv a3, zero
jal smp_call_function
/* hang if relocation of secondary harts has failed */
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index bc863fdbaf..74de92ed13 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -46,8 +46,9 @@ void handle_ipi(ulong hart);
* @addr: Address of function
* @arg0: First argument of function
* @arg1: Second argument of function
+ * @wait: Wait for harts to acknowledge request
* @return 0 if OK, -ve on error
*/
-int smp_call_function(ulong addr, ulong arg0, ulong arg1);
+int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
#endif
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index efbd3e23e7..e96137a50c 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -99,7 +99,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
#ifdef CONFIG_SMP
ret = smp_call_function(images->ep,
- (ulong)images->ft_addr, 0);
+ (ulong)images->ft_addr, 0, 0);
if (ret)
hang();
#endif
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 188a7e34bd..17adb35730 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -44,11 +44,11 @@ extern int riscv_clear_ipi(int hart);
*/
extern int riscv_get_ipi(int hart, int *pending);
-static int send_ipi_many(struct ipi_data *ipi)
+static int send_ipi_many(struct ipi_data *ipi, int wait)
{
ofnode node, cpus;
u32 reg;
- int ret;
+ int ret, pending;
cpus = ofnode_path("/cpus");
if (!ofnode_valid(cpus)) {
@@ -91,6 +91,15 @@ static int send_ipi_many(struct ipi_data *ipi)
pr_err("Cannot send IPI to hart %d\n", reg);
return ret;
}
+
+ if (wait) {
+ pending = 1;
+ while (pending) {
+ ret = riscv_get_ipi(reg, &pending);
+ if (ret)
+ return ret;
+ }
+ }
}
return 0;
@@ -104,21 +113,25 @@ void handle_ipi(ulong hart)
if (hart >= CONFIG_NR_CPUS)
return;
+ __smp_mb();
+
+ smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
+ invalidate_icache_all();
+
+ /*
+* Clear the IPI to acknowledge the request before jumping to the
+* requested function.
+*/
ret = riscv_clear_ipi(hart);
if (ret) {
pr_err("Cannot clear IPI of hart %ld\n", hart);
return;
}
- __smp_mb();
-
- smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
- invalidate_icache_all();
-
smp_function(hart, gd->arch.ipi[hart].arg0, gd->arch.ipi[hart].arg1);
}
-int smp_call_function(ulong addr, ulong arg0, ulong arg1)
+int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait)
{
int ret = 0;
struct ipi_data ipi;
@@ -127,7 +140,7 @@ int smp_call_function(ulong addr, ulong arg0, ulong arg1)
ipi.arg0 = arg0
[PATCH v2 4/4] spl: opensbi: wait for ack from secondary harts before entering OpenSBI
At the start, OpenSBI relocates itself to its link address. If the link address ranges of U-Boot SPL and OpenSBI overlap, the relocation can lead to code corruption if a hart is still running U-Boot SPL during relocation. To avoid this problem, the main hart is specified as the preferred boot hart to perform the relocation. This fixes the code corruption problems based on the assumption that since the main hart schedules the secondary harts to enter OpenSBI, it will be the last to enter OpenSBI. However it was reported that this assumption is not always correct. To make sure the assumption always holds true, wait for all secondary harts to acknowledge the call-function request before entering OpenSBI on the main hart. Reported-by: Rick Chen Signed-off-by: Lukas Auer Reviewed-by: Rick Chen Tested-by: Rick Chen Reviewed-by: Anup Patel --- Changes in v2: None common/spl/spl_opensbi.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 58bf2468ce..6404373eca 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -76,9 +76,19 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) invalidate_icache_all(); #ifdef CONFIG_SMP + /* +* Start OpenSBI on all secondary harts and wait for acknowledgment. +* +* OpenSBI first relocates itself to its link address. This is done by +* the main hart. To make sure no hart is still running U-Boot SPL +* during relocation, we wait for all secondary harts to acknowledge +* the call-function request before entering OpenSBI on the main hart. +* Otherwise, code corruption can occur if the link address ranges of +* U-Boot SPL and OpenSBI overlap. +*/ ret = smp_call_function((ulong)spl_image->entry_point, (ulong)spl_image->fdt_addr, - (ulong)&opensbi_info, 0); + (ulong)&opensbi_info, 1); if (ret) hang(); #endif -- 2.21.0
[PATCH v2 2/4] riscv: add functions for reading the IPI status
Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).
Signed-off-by: Lukas Auer
---
Changes in v2:
- Use the pending register instead of the claim register in the Andes
PLIC implementation
arch/riscv/lib/andes_plic.c | 11 +++
arch/riscv/lib/sbi_ipi.c | 11 +++
arch/riscv/lib/sifive_clint.c | 9 +
arch/riscv/lib/smp.c | 12
4 files changed, 43 insertions(+)
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 28568e4e2b..42bda9b759 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -114,6 +114,17 @@ int riscv_clear_ipi(int hart)
return 0;
}
+int riscv_get_ipi(int hart, int *pending)
+{
+ PLIC_BASE_GET();
+
+ *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
+gd->arch.boot_hart));
+ *pending = !!(*pending & SEND_IPI_TO_HART(hart));
+
+ return 0;
+}
+
static const struct udevice_id andes_plic_ids[] = {
{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
{ }
diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
index 170346da68..9a698ce74e 100644
--- a/arch/riscv/lib/sbi_ipi.c
+++ b/arch/riscv/lib/sbi_ipi.c
@@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart)
return 0;
}
+
+int riscv_get_ipi(int hart, int *pending)
+{
+ /*
+* The SBI does not support reading the IPI status. We always return 0
+* to indicate that no IPI is pending.
+*/
+ *pending = 0;
+
+ return 0;
+}
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index d24e0d585b..d7899d16d7 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart)
return 0;
}
+int riscv_get_ipi(int hart, int *pending)
+{
+ CLINT_BASE_GET();
+
+ *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
+
+ return 0;
+}
+
static const struct udevice_id sifive_clint_ids[] = {
{ .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
{ }
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 705437862a..188a7e34bd 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -32,6 +32,18 @@ extern int riscv_send_ipi(int hart);
*/
extern int riscv_clear_ipi(int hart);
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ * 1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+extern int riscv_get_ipi(int hart, int *pending);
+
static int send_ipi_many(struct ipi_data *ipi)
{
ofnode node, cpus;
--
2.21.0
[PATCH v2 0/4] Fixes for RISC-V U-Boot SPL / OpenSBI boot flow
Rick's recent patch series, which adds support for U-Boot SPL to the Andes platform, brought several problems of the current U-Boot SPL boot flow on RISC-V to light. Discussion on the relevant parts starts at [1]. The problem showed itself in the form of code corruption. At start, OpenSBI relocates itself to its link address. This allows it to be loaded independently of the link address. In the case that the link address ranges of U-Boot SPL and OpenSBI overlap, code corruption occurs if the relocation starts while some harts are still running U-Boot SPL. This series prevents this problem by specifying the hart that performs the relocation and then making sure that it is the last hart to enter OpenSBI, allowing relocation to be completed safely. A recent version of OpenSBI is required for the changes to work. This patch series resolves the problems associated with the use case of overlapping link address ranges. However, it is still recommended to select non-overlapping ranges for U-Boot SPL and OpenSBI. [1]: https://lists.denx.de/pipermail/u-boot/2019-November/389385.html Changes in v2: - Use the pending register instead of the claim register in the Andes PLIC implementation Lukas Auer (4): spl: opensbi: specify main hart as preferred boot hart riscv: add functions for reading the IPI status riscv: add option to wait for ack from secondary harts in smp functions spl: opensbi: wait for ack from secondary harts before entering OpenSBI arch/riscv/cpu/start.S| 2 ++ arch/riscv/include/asm/smp.h | 3 ++- arch/riscv/lib/andes_plic.c | 11 + arch/riscv/lib/bootm.c| 2 +- arch/riscv/lib/sbi_ipi.c | 11 + arch/riscv/lib/sifive_clint.c | 9 arch/riscv/lib/smp.c | 43 +++ arch/riscv/lib/spl.c | 2 +- common/spl/spl_opensbi.c | 13 ++- include/opensbi.h | 18 ++- 10 files changed, 100 insertions(+), 14 deletions(-) -- 2.21.0
Re: [PATCH 0/4] Fixes for RISC-V U-Boot SPL / OpenSBI boot flow
Hi Rick, On Fri, 2019-12-06 at 16:26 +0800, Rick Chen wrote: > HI Lukas > > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de] > > Sent: Wednesday, December 04, 2019 5:40 AM > > To: u-boot@lists.denx.de > > Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas Auer; Anup Patel; > > Anup Patel; Atish Patra; Marcus Comstedt > > Subject: [PATCH 0/4] Fixes for RISC-V U-Boot SPL / OpenSBI boot flow > > > > Rick's recent patch series, which adds support for U-Boot SPL to the Andes > > platform, brought several problems of the current U-Boot SPL boot flow on > > RISC-V to light. Discussion on the relevant parts starts at [1]. > > > > The problem showed itself in the form of code corruption. At start, OpenSBI > > relocates itself to its link address. This allows it to be loaded > > independently of the link address. In the case that the link address ranges > > of U-Boot SPL and OpenSBI overlap, code corruption occurs if the relocation > > starts while some harts are still running U-Boot SPL. > > This series prevents this problem by specifying the hart that performs the > > relocation and then making sure that it is the last hart to enter OpenSBI, > > allowing relocation to be completed safely. A recent version of OpenSBI is > > required for the changes to work. > > > > This patch series resolves the problems associated with the use case of > > overlapping link address ranges. However, it is still recommended to select > > non-overlapping ranges for U-Boot SPL and OpenSBI. > > > > [1]: https://lists.denx.de/pipermail/u-boot/2019-November/389385.html > > > > > > Lukas Auer (4): > > spl: opensbi: specify main hart as preferred boot hart > > riscv: add functions for reading the IPI status > > riscv: add option to wait for ack from secondary harts in smp > > functions > > spl: opensbi: wait for ack from secondary harts before entering > > OpenSBI > > > > arch/riscv/cpu/start.S| 2 ++ > > arch/riscv/include/asm/smp.h | 3 ++- > > arch/riscv/lib/andes_plic.c | 9 > > arch/riscv/lib/bootm.c| 2 +- > > arch/riscv/lib/sbi_ipi.c | 11 + > > arch/riscv/lib/sifive_clint.c | 9 > > arch/riscv/lib/smp.c | 43 +++ > > arch/riscv/lib/spl.c | 2 +- > > common/spl/spl_opensbi.c | 13 ++- > > include/opensbi.h | 18 ++- > > 10 files changed, 98 insertions(+), 14 deletions(-) > > > > -- > > 2.21.0 > > > > LGTM. > Thanks for the review and testing of the patches! I have sent an updated version of the series. Regards, Lukas
Re: [PATCH v6 000/102] x86: Add initial support for apollolake
Hi, On Sun, 8 Dec 2019 at 06:23, Tom Rini wrote: > > On Sun, Dec 08, 2019 at 04:56:21PM +0800, Bin Meng wrote: > > Hi Simon, > > > > On Sat, Dec 7, 2019 at 12:43 PM Simon Glass wrote: > > > > > > Apollo Lake is an Intel SoC generation aimed at relatively low-end > > > embedded systems. It was released in 2016 but has become more popular > > > recently with some embedded boards using it. > > > > > > This series adds support for Apollo Lake. As an example it adds an > > > implementation of chromebook_coral (a large range of Chromebooks released > > > in 2017). > > > > > > The series provides enough support to boot to a prompt. with LCD display, > > > storage, USB, EC and keyboard. > > > > > > Since this is the first time U-Boot has used FSP2 there is quite a bit of > > > refactoring needed. > > > > > > This series is available at u-boot-dm/coral-working > > > > > > > I applied the first 85 patches in the v6 series to u-boot-x86/next, > > except the following 2 patches: > > > > [v6,015/102] Revert "RFC: sandbox: net: Suppress the MAC-address warnings > > [v6,014/102] RFC: sandbox: net: Suppress the MAC-address warnings > > > > I believe this needs to be handled by Joe? > > > > The patches unfortunately break am335x_evm. > > > > Azure logs: > >arm: + am335x_evm > > +arm-linux-gnueabi-ld.bfd: u-boot-spl section `.u_boot_list' will not > > fit in region `.sram' > > +arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 8 bytes > > +make[2]: *** [spl/u-boot-spl] Error 1 > > +make[1]: *** [spl/u-boot-spl] Error 2 > > +make: *** [sub-make] Error 2 > > > > GitLab logs: > >arm: + am335x_evm > > +arm-linux-gnueabi-ld.bfd: u-boot-spl section `.u_boot_list' will not > > fit in region `.sram' > > +arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 76 bytes > > +make[2]: *** [spl/u-boot-spl] Error 1 > > +make[1]: *** [spl/u-boot-spl] Error 2 > > +make: *** [sub-make] Error 2 > > > > Would you please take a look, and propose a fix so that I can squash > > into the one that breaks this board? > > https://gitlab.denx.de/u-boot/custodians/u-boot-x86/-/jobs/37696 > > > > @Tom, not sure why Azure and GitLab reported different size > > overflowed? (8 vs 76). Is this caused by build directory path? > > Seems likely to be a path size overflow, yeah. The use of BUG(), WARN_ON() and friends brings in __FILE__. I'll send a patch to help with that. At least with gcc 7.3 it builds OK for me. There are about 13KB of strings in SPL for this board. I hate to say it, but it seems that the gcc rodata bug has returned. For example, it brings in the compat_name[] when building SPL, even though that is not actually used. I vaguely recall that this only happens when partial linking is used, but I cannot easily change U-Boot to use archives these days. Regards, SImon
[PATCH] usb: musb-new: Drop use of BUG()
These macros use __FILE__ which inserts the full path of the object file
into U-Boot, thus increasing file size. Drop these usages.
Signed-off-by: Simon Glass
---
drivers/usb/musb-new/musb_core.c | 6 ++
drivers/usb/musb-new/musb_gadget_ep0.c | 4 +++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index afea9fbcef..238e4708a5 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -1859,7 +1859,13 @@ allocate_instance(struct device *dev,
musb->ctrl_base = mbase;
musb->nIrq = -ENODEV;
musb->config = config;
+#ifdef __UBOOT__
+ assert(musb->config->num_eps <= MUSB_C_NUM_EPS);
+ if (musb->config->num_eps > MUSB_C_NUM_EPS)
+ return NULL;
+#else
BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
+#endif
for (epnum = 0, ep = musb->endpoints;
epnum < musb->config->num_eps;
epnum++, ep++) {
diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c
b/drivers/usb/musb-new/musb_gadget_ep0.c
index 9835a2e2bf..3adabcb69f 100644
--- a/drivers/usb/musb-new/musb_gadget_ep0.c
+++ b/drivers/usb/musb-new/musb_gadget_ep0.c
@@ -882,7 +882,9 @@ finish:
default:
/* "can't happen" */
- WARN_ON(1);
+ /* WARN_ON(1); (disable since __FILE__ can be large) */
+ dev_dbg(musb->controller, "odd; unknown state %d\n",
+ musb->ep0_state);
musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
musb->ep0_state = MUSB_EP0_STAGE_IDLE;
break;
--
2.24.0.393.g34dc348eaf-goog
[PATCH v7 00/17] x86: Add initial support for apollolake
Apollo Lake is an Intel SoC generation aimed at relatively low-end embedded systems. It was released in 2016 but has become more popular recently with some embedded boards using it. This series adds support for Apollo Lake. As an example it adds an implementation of chromebook_coral (a large range of Chromebooks released in 2017). The series provides enough support to boot to a prompt. with LCD display, storage, USB, EC and keyboard. Since this is the first time U-Boot has used FSP2 there is quite a bit of refactoring needed. This series is available at u-boot-dm/coral-working Changes in v7: - Add a comment to enable_bios_reset_cpl() - Add the new documentation to the index file - Drop Glacier Lake code - Fix value of GPIO_28_IRQ - Update Kconfig to avoid using def_bool - Update comment in apl_p2sb_early_init() Changes in v6: - Add .driver_data in the designware_pci_supported array - Add a comment about VANILLA - Add a comment about the need for board_run_command() - Add new patch with methods to find the position/size of next SPL phase - Change comment to apl_hostbridge_early_init_pinctrl, not apl_gpio_early_init - Change commented-out enable_rtc_upper_bank() call to a TODO - Drop Glacier Lake code - Drop init of ComB since it is not used - Drop lpc_configure_pads() and probe() function, add a comment about pads - Drop mention of devicetree for VTD feature - Drop mention of ramstage - Drop platform data and pre-PCI code, since DM PCI is available in SPL - Drop unnecessary priv struct and probe method - Fix FSP-M and FSP-S in comments - Fix comments for struct apl_hostbridge_platdata - Fix various coding style problems - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option - Move image pos/size access functions and symbols to generic SPL code - Move lpss_reset_release() to this commit - Rename init_for_uart() to board_debug_uart_init() - Use 'No SPI' instead of 'SPI2' as a debug message - Use SZ_4G instead of open-coded shift - Use generic gpio compatible string Changes in v5: - Add L2 cache flush function - Add L2 cache flush functoin - Add gpio-controller to GPIO nodes - Allocate the FSP-S data instead of using the stack - Comment out GPIOs in the fsp_s node since we don't use them yet - Correct CPU ACPI IDs - Drop SAFETY_MARGIN - Drop unrelated change metioned by Heiko - Enable SMP - Rename APOLLOLAKE_USB2_PORT_MAX - Use a define for ACPI base address Changes in v4: - Add a comment for enable_bios_reset_cpl() - Add comments for exported functions - Add u-boot,skip-auto-config-until-reloc property to PCI - Adjust the comment for struct dw_i2c_speed_config - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes) - Avoid needing to know internals of pinctrl in this driver - Change apollolake to apl - Detect zero mmio address - Drop GPIO_NUM_PAD_CFG_REGS - Drop duplicate commit 'Create a new sandbox_pci_read_bar() function' - Enable HAVE_X86_FIT - Enable INTEL_GPIO - Move code to pinctrl driver - Name this P-Unit instead of power unit, in the commit message - New GPIO driver binding - Rename arch_fsp_s_preinit() to arch_fsps_preinit() - Set up LPC pads early - Switch over to use pinctrl for pad init/config - Tidy up header guards - Tidy up mixed case in FSP code - Tidy up the header file a little - Update SPI flash protection only in SPL - Update documentation with more detailed memory map - Use 'Apollo Lake' - Use BIT() macro a bit more - Use BIT() macro bit more - Use existing VBT Kconfig option - Use hyphen for device-tree properties - Use tabs instead of spaces - apollolake -> Apollo Lake - use GENMASK() for VTBAR_MASK Changes in v3: - Ad FSP-S support - Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size - Add Chrome OS EC support - Add MMC, video, USB configs - Add VBT signature - Add a driver for APL SPI for TPL (using of-platdata) - Add a proper SPI node and make the SPI flash node a child - Add a weak function to avoid errors on other platforms - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot - Add bootstage support - Add bootstage timing for reading vbt - Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash) - Add more documentation - Add snapshot/restore for IRQs - Add spi alias in device tree - Add structures for FSP-S also - Add two more defines for the CPU driver - Add various minor tidy-ups - Adjust fast_spi_cache_bios_region() to avoid using SPI driver - Disable the bootcommand since it does nothing useful on coral - Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S - Don't enable SPI flash in TPL by default - Drop CONFIG_SPL_NET_SUPPORT - Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f() - Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs' - Drop patch 'dm: core: Don't include ofnode functions with of-platdata' - Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash' - Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt' - Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface' - Drop patch 'x86: tim
[PATCH v7 02/17] i2c: designware: Add Apollo Lake support
For Apollo Lake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v7: None
Changes in v6:
- Add .driver_data in the designware_pci_supported array
- Add a comment about VANILLA
- Move lpss_reset_release() to this commit
Changes in v5:
- Drop unrelated change metioned by Heiko
Changes in v4:
- apollolake -> Apollo Lake
Changes in v3:
- Add a weak function to avoid errors on other platforms
Changes in v2: None
drivers/i2c/designware_i2c_pci.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
index bb1f809af3..a3586371dc 100644
--- a/drivers/i2c/designware_i2c_pci.c
+++ b/drivers/i2c/designware_i2c_pci.c
@@ -8,8 +8,14 @@
#include
#include
#include
+#include
#include "designware_i2c.h"
+enum {
+ VANILLA = 0,/* standard I2C with no tweaks */
+ INTEL_APL, /* Apollo Lake I2C */
+};
+
/* BayTrail HCNT/LCNT/SDA hold time */
static struct dw_scl_sda_cfg byt_config = {
.ss_hcnt = 0x200,
@@ -19,6 +25,9 @@ static struct dw_scl_sda_cfg byt_config = {
.sda_hold = 0x6,
};
+/* Have a weak function for now - possibly should be a new uclass */
+__weak void lpss_reset_release(void *regs);
+
static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
{
struct dw_i2c *priv = dev_get_priv(dev);
@@ -59,6 +68,15 @@ static int designware_i2c_pci_ofdata_to_platdata(struct
udevice *dev)
static int designware_i2c_pci_probe(struct udevice *dev)
{
+ struct dw_i2c *priv = dev_get_priv(dev);
+
+ if (dev_get_driver_data(dev) == INTEL_APL) {
+ /* Ensure controller is in D0 state */
+ lpss_set_power_state(dev, STATE_D0);
+
+ lpss_reset_release(priv->regs);
+ }
+
return designware_i2c_probe(dev);
}
@@ -88,6 +106,7 @@ static int designware_i2c_pci_bind(struct udevice *dev)
static const struct udevice_id designware_i2c_pci_ids[] = {
{ .compatible = "snps,designware-i2c-pci" },
+ { .compatible = "intel,apl-i2c", INTEL_APL },
{ }
};
@@ -113,6 +132,12 @@ static struct pci_device_id designware_pci_supported[] = {
{ PCI_VDEVICE(INTEL, 0x0f45) },
{ PCI_VDEVICE(INTEL, 0x0f46) },
{ PCI_VDEVICE(INTEL, 0x0f47) },
+ { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
+ { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
{},
};
--
2.24.0.393.g34dc348eaf-goog
[PATCH v7 04/17] x86: apl: Add hostbridge driver
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.
Signed-off-by: Simon Glass
---
Changes in v7: None
Changes in v6:
- Fix comments for struct apl_hostbridge_platdata
Changes in v5: None
Changes in v4:
- Avoid needing to know internals of pinctrl in this driver
- Move code to pinctrl driver
- Switch over to use pinctrl for pad init/config
Changes in v3:
- Move pad programming into the hostbridge to reduce TPL device-tree size
- Use pci_get_devfn()
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/hostbridge.c | 179 +++
2 files changed, 180 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/hostbridge.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 3a8c2f66a3..4d3c08f84e 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -4,5 +4,6 @@
obj-$(CONFIG_SPL_BUILD) += systemagent.o
+obj-y += hostbridge.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/hostbridge.c
b/arch/x86/cpu/apollolake/hostbridge.c
new file mode 100644
index 00..793853d5b5
--- /dev/null
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct apl_hostbridge_platdata - platform data for hostbridge
+ *
+ * @dtplat: Platform data for of-platdata
+ * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
+ * @early_pads_count: Number of pads to process
+ * @pciex_region_size: BAR length in bytes
+ * @bdf: Bus/device/function of hostbridge
+ */
+struct apl_hostbridge_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_hostbridge dtplat;
+#endif
+ u32 *early_pads;
+ int early_pads_count;
+ uint pciex_region_size;
+ pci_dev_t bdf;
+};
+
+enum {
+ PCIEXBAR= 0x60,
+ PCIEXBAR_LENGTH_256MB = 0,
+ PCIEXBAR_LENGTH_128MB,
+ PCIEXBAR_LENGTH_64MB,
+
+ PCIEXBAR_PCIEXBAREN = 1 << 0,
+
+ TSEG= 0xb8, /* TSEG base */
+};
+
+static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ struct udevice *pinctrl;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
+ if (ret)
+ return log_msg_ret("no hostbridge pinctrl", ret);
+
+ return pinctrl_config_pads(pinctrl, plat->early_pads,
+ plat->early_pads_count);
+}
+
+static int apl_hostbridge_early_init(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ u32 region_size;
+ ulong base;
+ u32 reg;
+ int ret;
+
+ /* Set up the MCHBAR */
+ pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32);
+ base = MCH_BASE_ADDRESS;
+ pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32);
+
+ /*
+* The PCIEXBAR is assumed to live in the memory mapped IO space under
+* 4GiB
+*/
+ pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32);
+
+ switch (plat->pciex_region_size >> 20) {
+ default:
+ case 256:
+ region_size = PCIEXBAR_LENGTH_256MB;
+ break;
+ case 128:
+ region_size = PCIEXBAR_LENGTH_128MB;
+ break;
+ case 64:
+ region_size = PCIEXBAR_LENGTH_64MB;
+ break;
+ }
+
+ reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1)
+ | PCIEXBAR_PCIEXBAREN;
+ pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32);
+
+ /*
+* TSEG defines the base of SMM range. BIOS determines the base
+* of TSEG memory which must be at or below Graphics base of GTT
+* Stolen memory, hence its better to clear TSEG register early
+* to avoid power on default non-zero value (if any).
+*/
+ pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32);
+
+ ret = apl_hostbridge_early_init_pinctrl(dev);
+ if (ret)
+ return log_msg_ret("pinctrl", ret);
+
+ return 0;
+}
+
+static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ struct udevice *pinctrl;
+ int ret;
+
+ /*
+* The host bridge holds the early pad data needed to get through TPL.
+* This is a small amount of data, enough to fit in TPL, so we keep it
+* separate from the full pad data, stored in the fsp-s subnode. That
+* subnode is not present in TPL, to save space.
+*/
+ ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
+ if (r
[PATCH v7 03/17] x86: apl: Add systemagent driver
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.
Signed-off-by: Simon Glass
---
Changes in v7:
- Add a comment to enable_bios_reset_cpl()
Changes in v6: None
Changes in v5: None
Changes in v4:
- Add a comment for enable_bios_reset_cpl()
- Tidy up header guards
- use GENMASK() for VTBAR_MASK
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 2 +
arch/x86/cpu/apollolake/systemagent.c | 23
.../include/asm/arch-apollolake/systemagent.h | 37 +++
3 files changed, 62 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/systemagent.c
create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index fdda748ea3..3a8c2f66a3 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,5 +2,7 @@
#
# Copyright 2019 Google LLC
+obj-$(CONFIG_SPL_BUILD) += systemagent.o
+
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/systemagent.c
b/arch/x86/cpu/apollolake/systemagent.c
new file mode 100644
index 00..b6bc2ba14f
--- /dev/null
+++ b/arch/x86/cpu/apollolake/systemagent.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Take from coreboot project file of the same name
+ */
+
+#include
+#include
+#include
+#include
+
+void enable_bios_reset_cpl(void)
+{
+ /*
+* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
+* that BIOS has initialised memory and power management
+*
+* The FSP-S does not do this. If we leave this as zero then I believe
+* the power-aware interrupts don't work in Linux, and CPU 0 always gets
+* the interrupt.
+*/
+ setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);
+}
diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h
b/arch/x86/include/asm/arch-apollolake/systemagent.h
new file mode 100644
index 00..206d8903fa
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/systemagent.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Take from coreboot project file of the same name
+ */
+
+#ifndef _ASM_ARCH_SYSTEMAGENT_H
+#define _ASM_ARCH_SYSTEMAGENT_H
+
+/* Device 0:0.0 PCI configuration space */
+#define MCHBAR 0x48
+
+/* RAPL Package Power Limit register under MCHBAR */
+#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
+#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER0x18
+#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x8000
+#define BIOS_RESET_CPL 0x7078
+#define PCODE_INIT_DONE BIT(8)
+#define MCHBAR_RAPL_PPL0x70A8
+#define CORE_DISABLE_MASK 0x7168
+#define CAPID0_A 0xE4
+#define VTD_DISABLE BIT(23)
+#define DEFVTBAR 0x6c80
+#define GFXVTBAR 0x6c88
+#define VTBAR_ENABLED0x01
+#define VTBAR_MASK GENMASK_ULL(39, 12)
+#define VTBAR_SIZE 0x1000
+
+/**
+ * enable_bios_reset_cpl() - Tell the system agent that memory/power are ready
+ *
+ * This should be called when U-Boot has set up the memory and power
+ * management.
+ */
+void enable_bios_reset_cpl(void);
+
+#endif
--
2.24.0.393.g34dc348eaf-goog
[PATCH v7 01/17] x86: apl: Add pinctrl driver
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass --- Changes in v7: - Drop Glacier Lake code - Fix value of GPIO_28_IRQ - Update Kconfig to avoid using def_bool Changes in v6: None Changes in v5: None Changes in v4: - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes) - Drop GPIO_NUM_PAD_CFG_REGS - Switch over to use pinctrl for pad init/config - Tidy up the header file a little - apollolake -> Apollo Lake Changes in v3: - Add various minor tidy-ups - Fix mixed case in GPIO defines - Rework how pads configuration is defined in TPL and SPL - Use the IRQ uclass instead of ITSS Changes in v2: None arch/x86/include/asm/arch-apollolake/gpio.h | 485 drivers/pinctrl/intel/Kconfig | 16 +- drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl_apl.c | 192 4 files changed, 691 insertions(+), 3 deletions(-) create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h new file mode 100644 index 00..10879c168e --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/gpio.h @@ -0,0 +1,485 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Definitions for the GPIO subsystem on Apollolake + * + * Copyright (C) 2015 - 2017 Intel Corp. + * (Written by Alexandru Gagniuc for Intel Corp.) + * + * Placed in a separate file since some of these definitions can be used from + * assembly code + * + * Taken from gpio_apl.h in coreboot + */ + +#ifndef _ASM_ARCH_GPIO_H_ +#define _ASM_ARCH_GPIO_H_ + +/* Port ids */ +#define PID_GPIO_SW0xC0 +#define PID_GPIO_S 0xC2 +#define PID_GPIO_W 0xC7 +#define PID_GPIO_NW0xC4 +#define PID_GPIO_N 0xC5 +#define PID_ITSS 0xD0 +#define PID_RTC0xD1 + +/* + * Miscellaneous Configuration register(MISCCFG). These are community-specific + * registers and are meant to house miscellaneous configuration fields per + * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent) + */ +#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */ +#define GPIO_GPE_SW_31_0 0 /* SOUTHWEST GPIO# 0 ~ 31 belong to GROUP0 */ +#define GPIO_GPE_SW_63_32 1 /* SOUTHWEST GPIO# 32 ~ 42 belong to GROUP1 */ +#define GPIO_GPE_W_31_0 2 /* WEST GPIO# 0 ~ 25 belong to GROUP2 */ +#define GPIO_GPE_NW_31_0 4 /* NORTHWEST GPIO# 0 ~ 17 belong to GROUP4 */ +#define GPIO_GPE_NW_63_32 5 /* NORTHWEST GPIO# 32 ~ 63 belong to GROUP5 */ +#define GPIO_GPE_NW_95_64 6 /* NORTHWEST GPIO# 64 ~ 76 belong to GROUP6 */ +#define GPIO_GPE_N_31_0 7 /* NORTH GPIO# 0 ~ 31 belong to GROUP7 */ +#define GPIO_GPE_N_63_32 8 /* NORTH GPIO# 32 ~ 61 belong to GROUP8 */ + +#define GPIO_MAX_NUM_PER_GROUP 32 + +/* + * Host Software Pad Ownership Register. + * The pins in the community are divided into 3 groups: + * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95 + */ +#define HOSTSW_OWN_REG_0 0x80 + +#define PAD_CFG_BASE 0x500 + +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 + +#define GPI_SMI_STS_0 0x140 +#define GPI_SMI_EN_0 0x150 + +#define NUM_N_PADS (PAD_N(SVID0_CLK) + 1) +#define NUM_NW_PADS(PAD_NW(GPIO_123) + 1) +#define NUM_W_PADS (PAD_W(SUSPWRDNACK) + 1) +#define NUM_SW_PADS(PAD_SW(LPC_FRAMEB) + 1) + +#define NUM_N_GPI_REGS \ + (ALIGN(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_NW_GPI_REGS\ + (ALIGN(NUM_NW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_W_GPI_REGS \ + (ALIGN(NUM_W_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_SW_GPI_REGS\ + (ALIGN(NUM_SW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +/* + * Total number of GPI status registers across all GPIO communities in the SOC + */ +#define NUM_GPI_STATUS_REGS(NUM_N_GPI_REGS + NUM_NW_GPI_REGS \ + + NUM_W_GPI_REGS + NUM_SW_GPI_REGS) + +/* North community pads */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_1010 +#define GPIO_1111 +#define GPIO_1212 +#define GPIO_13
Re: [PATCH v6 098/102] x86: apl: Add P2SB driver
Hi Bin,
On Sun, 8 Dec 2019 at 01:39, Bin Meng wrote:
>
> Hi Simon,
>
> On Sat, Dec 7, 2019 at 12:54 PM Simon Glass wrote:
> >
> > Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
> > various child devices. It supposed both device tree and of-platdata.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v6: None
> > Changes in v5: None
> > Changes in v4:
> > - Detect zero mmio address
> > - Use BIT() macro bit more
> > - apollolake -> Apollo Lake
> >
> > Changes in v3:
> > - Use pci_get_devfn()
> >
> > Changes in v2: None
> >
> > arch/x86/cpu/apollolake/Makefile | 1 +
> > arch/x86/cpu/apollolake/p2sb.c | 167 +++
> > 2 files changed, 168 insertions(+)
> > create mode 100644 arch/x86/cpu/apollolake/p2sb.c
> >
> > diff --git a/arch/x86/cpu/apollolake/Makefile
> > b/arch/x86/cpu/apollolake/Makefile
> > index edde122f75..dc6df15dab 100644
> > --- a/arch/x86/cpu/apollolake/Makefile
> > +++ b/arch/x86/cpu/apollolake/Makefile
> > @@ -15,6 +15,7 @@ endif
> > obj-y += hostbridge.o
> > obj-y += itss.o
> > obj-y += lpc.o
> > +obj-y += p2sb.o
> > obj-y += pch.o
> > obj-y += pmc.o
> > obj-y += uart.o
> > diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c
> > new file mode 100644
> > index 00..0a5deaf4a0
> > --- /dev/null
> > +++ b/arch/x86/cpu/apollolake/p2sb.c
> > @@ -0,0 +1,167 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Primary-to-Sideband Bridge
> > + *
> > + * Copyright 2019 Google LLC
> > + */
> > +
> > +#define LOG_CATEGORY UCLASS_P2SB
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +struct p2sb_platdata {
> > +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> > + struct dtd_intel_apl_p2sb dtplat;
> > +#endif
> > + ulong mmio_base;
> > + pci_dev_t bdf;
> > +};
> > +
> > +/* PCI config space registers */
> > +#define HPTC_OFFSET0x60
> > +#define HPTC_ADDR_ENABLE_BIT BIT(7)
> > +
> > +/* High Performance Event Timer Configuration */
> > +#define P2SB_HPTC 0x60
> > +#define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
> > +
> > +/*
> > + * ADDRESS_SELECTENCODING_RANGE
> > + * 0 0xfed0 - 0xfed0 03ff
> > + * 1 0xfed0 1000 - 0xfed0 13ff
> > + * 2 0xfed0 2000 - 0xfed0 23ff
> > + * 3 0xfed0 3000 - 0xfed0 33ff
> > + */
> > +#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
> > +#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
> > +#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
> > +#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
> > +
> > +/*
> > + * apl_p2sb_early_init() - Enable decoding for HPET range
> > + *
> > + * This is needed for FspMemoryInit to store and retrieve a global data
> > + * pointer
>
> Looks my comment in the v5 series was not addressed.
> See https://lists.denx.de/pipermail/u-boot/2019-December/392392.html
OK. I am not really sure what the FSP is doing here, but it apparently
does need HPET set up.
I'll update the comment to just say it is needed by FSP-M.
Regards,
Simon
[PATCH v7 04/17] x86: apl: Add hostbridge driver
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6:
- Fix comments for struct apl_hostbridge_platdata
Changes in v5: None
Changes in v4:
- Avoid needing to know internals of pinctrl in this driver
- Move code to pinctrl driver
- Switch over to use pinctrl for pad init/config
Changes in v3:
- Move pad programming into the hostbridge to reduce TPL device-tree size
- Use pci_get_devfn()
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/hostbridge.c | 179 +++
2 files changed, 180 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/hostbridge.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 3a8c2f66a3..4d3c08f84e 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -4,5 +4,6 @@
obj-$(CONFIG_SPL_BUILD) += systemagent.o
+obj-y += hostbridge.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/hostbridge.c
b/arch/x86/cpu/apollolake/hostbridge.c
new file mode 100644
index 00..793853d5b5
--- /dev/null
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct apl_hostbridge_platdata - platform data for hostbridge
+ *
+ * @dtplat: Platform data for of-platdata
+ * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
+ * @early_pads_count: Number of pads to process
+ * @pciex_region_size: BAR length in bytes
+ * @bdf: Bus/device/function of hostbridge
+ */
+struct apl_hostbridge_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_hostbridge dtplat;
+#endif
+ u32 *early_pads;
+ int early_pads_count;
+ uint pciex_region_size;
+ pci_dev_t bdf;
+};
+
+enum {
+ PCIEXBAR= 0x60,
+ PCIEXBAR_LENGTH_256MB = 0,
+ PCIEXBAR_LENGTH_128MB,
+ PCIEXBAR_LENGTH_64MB,
+
+ PCIEXBAR_PCIEXBAREN = 1 << 0,
+
+ TSEG= 0xb8, /* TSEG base */
+};
+
+static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ struct udevice *pinctrl;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
+ if (ret)
+ return log_msg_ret("no hostbridge pinctrl", ret);
+
+ return pinctrl_config_pads(pinctrl, plat->early_pads,
+ plat->early_pads_count);
+}
+
+static int apl_hostbridge_early_init(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ u32 region_size;
+ ulong base;
+ u32 reg;
+ int ret;
+
+ /* Set up the MCHBAR */
+ pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32);
+ base = MCH_BASE_ADDRESS;
+ pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32);
+
+ /*
+* The PCIEXBAR is assumed to live in the memory mapped IO space under
+* 4GiB
+*/
+ pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32);
+
+ switch (plat->pciex_region_size >> 20) {
+ default:
+ case 256:
+ region_size = PCIEXBAR_LENGTH_256MB;
+ break;
+ case 128:
+ region_size = PCIEXBAR_LENGTH_128MB;
+ break;
+ case 64:
+ region_size = PCIEXBAR_LENGTH_64MB;
+ break;
+ }
+
+ reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1)
+ | PCIEXBAR_PCIEXBAREN;
+ pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32);
+
+ /*
+* TSEG defines the base of SMM range. BIOS determines the base
+* of TSEG memory which must be at or below Graphics base of GTT
+* Stolen memory, hence its better to clear TSEG register early
+* to avoid power on default non-zero value (if any).
+*/
+ pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32);
+
+ ret = apl_hostbridge_early_init_pinctrl(dev);
+ if (ret)
+ return log_msg_ret("pinctrl", ret);
+
+ return 0;
+}
+
+static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
+{
+ struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ struct udevice *pinctrl;
+ int ret;
+
+ /*
+* The host bridge holds the early pad data needed to get through TPL.
+* This is a small amount of data, enough to fit in TPL, so we keep it
+* separate from the full pad data, stored in the fsp-s subnode. That
+* subnode is not present in TPL, to save space.
+*/
+ ret = uclass_first_device_err(UCLASS_PINCTRL, &
[PATCH v7 06/17] x86: apl: Add LPC driver
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6:
- Drop init of ComB since it is not used
- Drop lpc_configure_pads() and probe() function, add a comment about pads
Changes in v5: None
Changes in v4:
- Add comments for exported functions
- Tidy up header guards
- Use 'Apollo Lake'
- Use BIT() macro a bit more
- Use tabs instead of spaces
Changes in v3:
- Drop unused code in lpc_configure_pads()
- Fix value of LPC_BC_LE
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/lpc.c | 122 +
arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++
3 files changed, 205 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/lpc.c
create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 2d78368150..31045a03c1 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -6,5 +6,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += hostbridge.o
obj-y += itss.o
+obj-y += lpc.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c
new file mode 100644
index 00..45b2144fc6
--- /dev/null
+++ b/arch/x86/cpu/apollolake/lpc.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ *
+ * From coreboot Apollo Lake support lpc.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+void lpc_enable_fixed_io_ranges(uint io_enables)
+{
+ pci_x86_clrset_config(PCH_DEV_LPC, LPC_IO_ENABLES, 0, io_enables,
+ PCI_SIZE_16);
+}
+
+/*
+ * Find the first unused IO window.
+ * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ...
+ */
+static int find_unused_pmio_window(void)
+{
+ int i;
+ ulong lgir;
+
+ for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
+ pci_x86_read_config(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),
+ &lgir, PCI_SIZE_32);
+
+ if (!(lgir & LPC_LGIR_EN))
+ return i;
+ }
+
+ return -1;
+}
+
+int lpc_open_pmio_window(uint base, uint size)
+{
+ int i, lgir_reg_num;
+ u32 lgir_reg_offset, lgir, window_size, alignment;
+ ulong bridged_size, bridge_base;
+ ulong reg;
+
+ log_debug("LPC: Trying to open IO window from %x size %x\n", base,
+ size);
+
+ bridged_size = 0;
+ bridge_base = base;
+
+ while (bridged_size < size) {
+ /* Each IO range register can only open a 256-byte window */
+ window_size = min(size, (uint)LPC_LGIR_MAX_WINDOW_SIZE);
+
+ /* Window size must be a power of two for the AMASK to work */
+ alignment = 1UL << (order_base_2(window_size));
+ window_size = ALIGN(window_size, alignment);
+
+ /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18] */
+ lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
+ lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
+
+ /* Skip programming if same range already programmed */
+ for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
+ pci_x86_read_config(PCH_DEV_LPC,
+ LPC_GENERIC_IO_RANGE(i), ®,
+ PCI_SIZE_32);
+ if (lgir == reg)
+ return -EALREADY;
+ }
+
+ lgir_reg_num = find_unused_pmio_window();
+ if (lgir_reg_num < 0) {
+ log_err("LPC: Cannot open IO window: %lx size %lx\n",
+ bridge_base, size - bridged_size);
+ log_err("No more IO windows\n");
+
+ return -ENOSPC;
+ }
+ lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
+
+ pci_x86_write_config(PCH_DEV_LPC, lgir_reg_offset, lgir,
+PCI_SIZE_32);
+
+ log_debug("LPC: Opened IO window LGIR%d: base %lx size %x\n",
+ lgir_reg_num, bridge_base, window_size);
+
+ bridged_size += window_size;
+ bridge_base += window_size;
+ }
+
+ return 0;
+}
+
+void lpc_io_setup_comm_a_b(void)
+{
+ /* ComA Range 3F8h-3FFh [2:0] */
+ u16 com_ranges = LPC_IOD_COMA_RANGE;
+ u16 com_enable = LPC_IOE_COMA_EN;
+
+ /* Setup I/O Decode Range Register for LPC */
+ pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);
+ /* Enable ComA and ComB Port */
+ lpc
[PATCH v7 05/17] x86: apl: Add ITSS driver
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Tidy up header guards
Changes in v3:
- Add snapshot/restore for IRQs
- Use the IRQ uclass instead of ITSS
Changes in v2: None
arch/x86/cpu/apollolake/Makefile| 1 +
arch/x86/cpu/apollolake/itss.c | 214
arch/x86/include/asm/arch-apollolake/itss.h | 43
3 files changed, 258 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/itss.c
create mode 100644 arch/x86/include/asm/arch-apollolake/itss.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 4d3c08f84e..2d78368150 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -5,5 +5,6 @@
obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += hostbridge.o
+obj-y += itss.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/itss.c b/arch/x86/cpu/apollolake/itss.c
new file mode 100644
index 00..8789f8e6bb
--- /dev/null
+++ b/arch/x86/cpu/apollolake/itss.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Something to do with Interrupts, but I don't know what ITSS stands for
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017 Siemens AG
+ * Copyright 2019 Google LLC
+ *
+ * Taken from coreboot itss.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct apl_itss_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_intel_apl_itss dtplat;
+#endif
+};
+
+/* struct pmc_route - Routing for PMC to GPIO */
+struct pmc_route {
+ u32 pmc;
+ u32 gpio;
+};
+
+struct apl_itss_priv {
+ struct pmc_route *route;
+ uint route_count;
+ u32 irq_snapshot[NUM_IPC_REGS];
+};
+
+static int apl_set_polarity(struct udevice *dev, uint irq, bool active_low)
+{
+ u32 mask;
+ uint reg;
+
+ if (irq > ITSS_MAX_IRQ)
+ return -EINVAL;
+
+ reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * (irq / IRQS_PER_IPC);
+ mask = 1 << (irq % IRQS_PER_IPC);
+
+ pcr_clrsetbits32(dev, reg, mask, active_low ? mask : 0);
+
+ return 0;
+}
+
+#ifndef CONFIG_TPL_BUILD
+static int apl_snapshot_polarities(struct udevice *dev)
+{
+ struct apl_itss_priv *priv = dev_get_priv(dev);
+ const int start = GPIO_IRQ_START;
+ const int end = GPIO_IRQ_END;
+ int reg_start;
+ int reg_end;
+ int i;
+
+ reg_start = start / IRQS_PER_IPC;
+ reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
+
+ for (i = reg_start; i < reg_end; i++) {
+ uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
+
+ priv->irq_snapshot[i] = pcr_read32(dev, reg);
+ }
+
+ return 0;
+}
+
+static void show_polarities(struct udevice *dev, const char *msg)
+{
+ int i;
+
+ log_info("ITSS IRQ Polarities %s:\n", msg);
+ for (i = 0; i < NUM_IPC_REGS; i++) {
+ uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
+
+ log_info("IPC%d: 0x%08x\n", i, pcr_read32(dev, reg));
+ }
+}
+
+static int apl_restore_polarities(struct udevice *dev)
+{
+ struct apl_itss_priv *priv = dev_get_priv(dev);
+ const int start = GPIO_IRQ_START;
+ const int end = GPIO_IRQ_END;
+ int reg_start;
+ int reg_end;
+ int i;
+
+ show_polarities(dev, "Before");
+
+ reg_start = start / IRQS_PER_IPC;
+ reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
+
+ for (i = reg_start; i < reg_end; i++) {
+ u32 mask;
+ u16 reg;
+ int irq_start;
+ int irq_end;
+
+ irq_start = i * IRQS_PER_IPC;
+ irq_end = min(irq_start + IRQS_PER_IPC - 1, ITSS_MAX_IRQ);
+
+ if (start > irq_end)
+ continue;
+ if (end < irq_start)
+ break;
+
+ /* Track bits within the bounds of of the register */
+ irq_start = max(start, irq_start) % IRQS_PER_IPC;
+ irq_end = min(end, irq_end) % IRQS_PER_IPC;
+
+ /* Create bitmask of the inclusive range of start and end */
+ mask = (((1U << irq_end) - 1) | (1U << irq_end));
+ mask &= ~((1U << irq_start) - 1);
+
+ reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
+ pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
+ }
+
+ show_polarities(dev, "After");
+
+ return 0;
+}
+#endif
+
+static int apl_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
+{
+ struct apl_itss_priv *priv = dev_get_priv(dev);
+ struct pmc_route *route;
[PATCH v7 07/17] x86: apl: Add PCH driver
Add a driver for the Apollo Lake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Tidy up header guards
- Update SPI flash protection only in SPL
- apollolake -> Apollo Lake
Changes in v3: None
Changes in v2:
- Drop probe() function
- Implement set_spi_protect()
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/pch.c | 36 ++
arch/x86/include/asm/arch-apollolake/pch.h | 9 ++
3 files changed, 46 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/pch.c
create mode 100644 arch/x86/include/asm/arch-apollolake/pch.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 31045a03c1..36eefcbad7 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -7,5 +7,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += hostbridge.o
obj-y += itss.o
obj-y += lpc.o
+obj-y += pch.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c
new file mode 100644
index 00..1a5a985221
--- /dev/null
+++ b/arch/x86/cpu/apollolake/pch.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define BIOS_CTRL 0xdc
+
+static int apl_set_spi_protect(struct udevice *dev, bool protect)
+{
+ if (spl_phase() == PHASE_SPL)
+ return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
+
+ return 0;
+}
+
+static const struct pch_ops apl_pch_ops = {
+ .set_spi_protect = apl_set_spi_protect,
+};
+
+static const struct udevice_id apl_pch_ids[] = {
+ { .compatible = "intel,apl-pch" },
+ { }
+};
+
+U_BOOT_DRIVER(apl_pch) = {
+ .name = "apl_pch",
+ .id = UCLASS_PCH,
+ .of_match = apl_pch_ids,
+ .ops= &apl_pch_ops,
+};
diff --git a/arch/x86/include/asm/arch-apollolake/pch.h
b/arch/x86/include/asm/arch-apollolake/pch.h
new file mode 100644
index 00..bf3e1670d2
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/pch.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _ASM_ARCH_PCH_H
+#define _ASM_ARCH_PCH_H
+
+#endif /* _ASM_ARCH_PCH_H */
--
2.24.0.393.g34dc348eaf-goog
[PATCH v7 09/17] spl: Add methods to find the position/size of next phase
Binman supports writing the position and size of U-Boot proper and SPL
into the previous phase of U-Boot. This allows the next phase to be easily
located and loaded.
Add functions to return these useful values, along with symbols to allow
TPL to load SPL.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6:
- Add new patch with methods to find the position/size of next SPL phase
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
common/spl/spl.c | 20
include/spl.h| 21 -
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index d51dbe9942..c1fce62b91 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -42,6 +42,12 @@ u32 *boot_params_ptr = NULL;
/* See spl.h for information about this */
binman_sym_declare(ulong, u_boot_any, image_pos);
+binman_sym_declare(ulong, u_boot_any, size);
+
+#ifdef CONFIG_TPL
+binman_sym_declare(ulong, spl, image_pos);
+binman_sym_declare(ulong, spl, size);
+#endif
/* Define board data structure */
static bd_t bdata __attribute__ ((section(".data")));
@@ -120,6 +126,20 @@ void spl_fixup_fdt(void)
#endif
}
+ulong spl_get_image_pos(void)
+{
+ return spl_phase() == PHASE_TPL ?
+ binman_sym(ulong, spl, image_pos) :
+ binman_sym(ulong, u_boot_any, image_pos);
+}
+
+ulong spl_get_image_size(void)
+{
+ return spl_phase() == PHASE_TPL ?
+ binman_sym(ulong, spl, size) :
+ binman_sym(ulong, u_boot_any, size);
+}
+
/*
* Weak default function for board specific cleanup/preparation before
* Linux boot. Some boards/platforms might not need it, so just provide
diff --git a/include/spl.h b/include/spl.h
index 08ffddac29..02aa1ff85d 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -169,10 +169,29 @@ struct spl_load_info {
* We need to know the position of U-Boot in memory so we can jump to it. We
* allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin,
* u-boot.img), hence the '_any'. These is no checking here that the correct
- * image is found. For * example if u-boot.img is used we don't check that
+ * image is found. For example if u-boot.img is used we don't check that
* spl_parse_image_header() can parse a valid header.
+ *
+ * Similarly for SPL, so that TPL can jump to SPL.
*/
binman_sym_extern(ulong, u_boot_any, image_pos);
+binman_sym_extern(ulong, u_boot_any, size);
+binman_sym_extern(ulong, spl, image_pos);
+binman_sym_extern(ulong, spl, size);
+
+/**
+ * spl_get_image_pos() - get the image position of the next phase
+ *
+ * This returns the image position to use to load the next phase of U-Boot
+ */
+ulong spl_get_image_pos(void);
+
+/**
+ * spl_get_image_size() - get the size of the next phase
+ *
+ * This returns the size to use to load the next phase of U-Boot
+ */
+ulong spl_get_image_size(void);
/**
* spl_load_simple_fit_skip_processing() - Hook to allow skipping the FIT
--
2.24.0.393.g34dc348eaf-goog
[PATCH v7 08/17] x86: apl: Add PUNIT driver
Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a
syscon driver since it only needs to be probed.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6:
- Drop Glacier Lake code
- Drop platform data and pre-PCI code, since DM PCI is available in SPL
Changes in v5: None
Changes in v4:
- Name this P-Unit instead of power unit, in the commit message
- apollolake -> Apollo Lake
Changes in v3:
- Use pci_get_devfn()
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 3 +
arch/x86/cpu/apollolake/punit.c | 94
2 files changed, 97 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/punit.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 36eefcbad7..875d454157 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -3,6 +3,9 @@
# Copyright 2019 Google LLC
obj-$(CONFIG_SPL_BUILD) += systemagent.o
+ifndef CONFIG_TPL_BUILD
+obj-y += punit.o
+endif
obj-y += hostbridge.o
obj-y += itss.o
diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c
new file mode 100644
index 00..1a131fb0b1
--- /dev/null
+++ b/arch/x86/cpu/apollolake/punit.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * Punit Initialisation code. This all isn't documented, but
+ * this is the recipe.
+ */
+static int punit_init(struct udevice *dev)
+{
+ struct udevice *cpu;
+ u32 reg;
+ ulong start;
+ int ret;
+
+ /* Thermal throttle activation offset */
+ ret = uclass_first_device_err(UCLASS_CPU, &cpu);
+ if (ret)
+ return log_msg_ret("Cannot find CPU", ret);
+ cpu_configure_thermal_target(cpu);
+
+ /*
+* Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
+* Enable all cores here.
+*/
+ writel(0, MCHBAR_REG(CORE_DISABLE_MASK));
+
+ /* P-Unit bring up */
+ reg = readl(MCHBAR_REG(BIOS_RESET_CPL));
+ if (reg == 0x) {
+ /* P-unit not found */
+ debug("Punit MMIO not available\n");
+ return -ENOENT;
+ }
+
+ /* Set Punit interrupt pin IPIN offset 3D */
+ dm_pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x2);
+
+ /* Set PUINT IRQ to 24 and INTPIN LOCK */
+ writel(PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
+ PUINT_THERMAL_DEVICE_IRQ_LOCK,
+ MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ));
+
+ /* Stage0 BIOS Reset Complete (RST_CPL) */
+ enable_bios_reset_cpl();
+
+ /*
+* Poll for bit 8 to check if PCODE has completed its action in response
+* to BIOS Reset complete. We wait here till 1 ms for the bit to get
+* set.
+*/
+ start = get_timer(0);
+ while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) {
+ if (get_timer(start) > 1) {
+ debug("PCODE Init Done timeout\n");
+ return -ETIMEDOUT;
+ }
+ udelay(100);
+ }
+ debug("PUNIT init complete\n");
+
+ return 0;
+}
+
+static int apl_punit_probe(struct udevice *dev)
+{
+ if (spl_phase() == PHASE_SPL)
+ return punit_init(dev);
+
+ return 0;
+}
+
+static const struct udevice_id apl_syscon_ids[] = {
+ { .compatible = "intel,apl-punit", .data = X86_SYSCON_PUNIT },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_intel_punit) = {
+ .name = "intel_punit_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = apl_syscon_ids,
+ .probe = apl_punit_probe,
+};
--
2.24.0.393.g34dc348eaf-goog
[PATCH v7 10/17] x86: apl: Add SPL loaders
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6:
- Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option
- Move image pos/size access functions and symbols to generic SPL code
Changes in v5:
- Add L2 cache flush functoin
- Drop SAFETY_MARGIN
Changes in v4: None
Changes in v3:
- Add a driver for APL SPI for TPL (using of-platdata)
- Support TPL without CONFIG_TPL_SPI_SUPPORT
- Support bootstage timing
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 2 +
arch/x86/cpu/apollolake/spl.c| 178 +++
2 files changed, 180 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/spl.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 875d454157..1fde400d77 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,7 +2,9 @@
#
# Copyright 2019 Google LLC
+obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += systemagent.o
+
ifndef CONFIG_TPL_BUILD
obj-y += punit.o
endif
diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c
new file mode 100644
index 00..7ab7243311
--- /dev/null
+++ b/arch/x86/cpu/apollolake/spl.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* This reads the next phase from mapped SPI flash */
+static int rom_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ ulong spl_pos = spl_get_image_pos();
+ ulong spl_size = spl_get_image_size();
+ struct udevice *dev;
+ ulong map_base;
+ size_t map_size;
+ uint offset;
+ int ret;
+
+ spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
+ spl_image->entry_point = spl_phase() == PHASE_TPL ?
+ CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
+ spl_image->load_addr = spl_image->entry_point;
+ spl_image->os = IH_OS_U_BOOT;
+ spl_image->name = "U-Boot";
+ debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
+
+ if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
+ ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
+ if (ret)
+ return log_msg_ret("spi_flash", ret);
+ if (!dev)
+ return log_msg_ret("spi_flash dev", -ENODEV);
+ ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
+ if (ret)
+ return log_msg_ret("mmap", ret);
+ } else {
+ ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
+&offset);
+ if (ret)
+ return ret;
+ }
+ spl_pos += map_base & ~0xff00;
+ debug(", base %lx, pos %lx\n", map_base, spl_pos);
+ bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
+ memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
+ cpu_flush_l1d_to_l2();
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
+
+ return 0;
+}
+SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
+
+#if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
+
+static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
+ void *buf)
+{
+ struct spi_flash *flash = dev_get_uclass_priv(dev);
+ struct mtd_info *mtd = &flash->mtd;
+ size_t retlen;
+
+ return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
+}
+
+static int apl_flash_probe(struct udevice *dev)
+{
+ return spi_flash_std_probe(dev);
+}
+
+/*
+ * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
+ * need to allocate the parent_platdata since by the time this function is
+ * called device_bind() has already gone past that step.
+ */
+static int apl_flash_bind(struct udevice *dev)
+{
+ if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
+ struct dm_spi_slave_platdata *plat;
+ struct udevice *spi;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_SPI, &spi);
+ if (ret)
+ return ret;
+ dev->parent = spi;
+
+ plat = calloc(sizeof(*plat), 1);
+ if (!plat)
+ return -ENOMEM;
+ dev->parent_platdata = plat;
+ }
+
+ return 0;
+}
+
+static const struct dm_spi_flash_ops apl_flash_ops = {
+ .read = apl_flash_std_read,
+};
+
+static const struct udevice_id apl_flash_ids[] = {
+ { .compatible = "jedec,spi-nor" },
+ { }
+};
+
+U_BOOT_DRIVER(winbond_w25q128fw) =
[PATCH v7 11/17] x86: apl: Add a CPU driver
Add a bare-bones CPU driver so that CPUs can be probed.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6:
- Drop unnecessary priv struct and probe method
- Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option
Changes in v5:
- Add L2 cache flush function
- Drop SAFETY_MARGIN
Changes in v4:
- Change apollolake to apl
- Tidy up header guards
Changes in v3:
- Add two more defines for the CPU driver
- Expand comments for BOOT_FROM_FAST_SPI_FLASH
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 2 ++
arch/x86/cpu/apollolake/cpu.c | 41 ++
arch/x86/cpu/apollolake/cpu_common.c | 17 +
arch/x86/include/asm/arch-apollolake/cpu.h | 20 +++
arch/x86/include/asm/msr-index.h | 1 +
5 files changed, 81 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/cpu.c
create mode 100644 arch/x86/cpu/apollolake/cpu_common.c
create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 1fde400d77..37e42092ec 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -4,8 +4,10 @@
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += systemagent.o
+obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
+obj-y += cpu.o
obj-y += punit.o
endif
diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
new file mode 100644
index 00..3d05c82a5c
--- /dev/null
+++ b/arch/x86/cpu/apollolake/cpu.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static int apl_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
+}
+
+static int apl_get_count(struct udevice *dev)
+{
+ return 4;
+}
+
+static const struct cpu_ops cpu_x86_apl_ops = {
+ .get_desc = cpu_x86_get_desc,
+ .get_info = apl_get_info,
+ .get_count = apl_get_count,
+ .get_vendor = cpu_x86_get_vendor,
+};
+
+static const struct udevice_id cpu_x86_apl_ids[] = {
+ { .compatible = "intel,apl-cpu" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_apl_drv) = {
+ .name = "cpu_x86_apl",
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_apl_ids,
+ .bind = cpu_x86_bind,
+ .ops= &cpu_x86_apl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/arch/x86/cpu/apollolake/cpu_common.c
b/arch/x86/cpu/apollolake/cpu_common.c
new file mode 100644
index 00..ba6bda37bc
--- /dev/null
+++ b/arch/x86/cpu/apollolake/cpu_common.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include
+#include
+#include
+
+void cpu_flush_l1d_to_l2(void)
+{
+ struct msr_t msr;
+
+ msr = msr_read(MSR_POWER_MISC);
+ msr.lo |= FLUSH_DL1_L2;
+ msr_write(MSR_POWER_MISC, msr);
+}
diff --git a/arch/x86/include/asm/arch-apollolake/cpu.h
b/arch/x86/include/asm/arch-apollolake/cpu.h
new file mode 100644
index 00..5e906c5e7d
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/cpu.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _ASM_ARCH_CPU_H
+#define _ASM_ARCH_CPU_H
+
+/* Common Timer Copy (CTC) frequency - 19.2MHz */
+#define CTC_FREQ 1920
+
+#define MAX_PCIE_PORTS 6
+#define CLKREQ_DISABLED0xf
+
+#ifndef __ASSEMBLY__
+/* Flush L1D to L2 */
+void cpu_flush_l1d_to_l2(void);
+#endif
+
+#endif /* _ASM_ARCH_CPU_H */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 79a9369de1..246c14f815 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -70,6 +70,7 @@
#define MSR_IA32_BBL_CR_CTL0x0119
#define MSR_IA32_BBL_CR_CTL3 0x011e
#define MSR_POWER_MISC 0x0120
+#define FLUSH_DL1_L2 (1 << 8)
#define ENABLE_ULFM_AUTOCM_MASK(1 << 2)
#define ENABLE_INDP_AUTOCM_MASK(1 << 3)
--
2.24.0.393.g34dc348eaf-goog
[PATCH v7 13/17] x86: apl: Add P2SB driver
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.
Signed-off-by: Simon Glass
---
Changes in v7:
- Update comment in apl_p2sb_early_init()
Changes in v6: None
Changes in v5: None
Changes in v4:
- Detect zero mmio address
- Use BIT() macro bit more
- apollolake -> Apollo Lake
Changes in v3:
- Use pci_get_devfn()
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/p2sb.c | 166 +++
2 files changed, 167 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/p2sb.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index edde122f75..dc6df15dab 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -15,6 +15,7 @@ endif
obj-y += hostbridge.o
obj-y += itss.o
obj-y += lpc.o
+obj-y += p2sb.o
obj-y += pch.o
obj-y += pmc.o
obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c
new file mode 100644
index 00..eb27861b7a
--- /dev/null
+++ b/arch/x86/cpu/apollolake/p2sb.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Primary-to-Sideband Bridge
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_P2SB
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct p2sb_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_p2sb dtplat;
+#endif
+ ulong mmio_base;
+ pci_dev_t bdf;
+};
+
+/* PCI config space registers */
+#define HPTC_OFFSET0x60
+#define HPTC_ADDR_ENABLE_BIT BIT(7)
+
+/* High Performance Event Timer Configuration */
+#define P2SB_HPTC 0x60
+#define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
+
+/*
+ * ADDRESS_SELECTENCODING_RANGE
+ * 0 0xfed0 - 0xfed0 03ff
+ * 1 0xfed0 1000 - 0xfed0 13ff
+ * 2 0xfed0 2000 - 0xfed0 23ff
+ * 3 0xfed0 3000 - 0xfed0 33ff
+ */
+#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
+
+/*
+ * apl_p2sb_early_init() - Enable decoding for HPET range
+ *
+ * This is needed by FSP-M which uses the High Precision Event Timer.
+ *
+ * @dev: P2SB device
+ * @return 0 if OK, -ve on error
+ */
+static int apl_p2sb_early_init(struct udevice *dev)
+{
+ struct p2sb_platdata *plat = dev_get_platdata(dev);
+ pci_dev_t pdev = plat->bdf;
+
+ /*
+* Enable decoding for HPET memory address range.
+* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
+* the High Performance Timer memory address range
+* selected by bits 1:0
+*/
+ pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
+PCI_SIZE_8);
+
+ /* Enable PCR Base address in PCH */
+ pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
+PCI_SIZE_32);
+ pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
+
+ /* Enable P2SB MSE */
+ pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
+PCI_COMMAND_MEMORY, PCI_SIZE_8);
+
+ return 0;
+}
+
+static int apl_p2sb_spl_init(struct udevice *dev)
+{
+ /* Enable decoding for HPET. Needed for FSP global pointer storage */
+ dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
+ P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
+
+ return 0;
+}
+
+int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
+ struct p2sb_platdata *plat = dev_get_platdata(dev);
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ int ret;
+
+ if (spl_phase() == PHASE_TPL) {
+ u32 base[2];
+
+ /* TPL sets up the initial BAR */
+ ret = dev_read_u32_array(dev, "early-regs", base,
+ARRAY_SIZE(base));
+ if (ret)
+ return log_msg_ret("Missing/short early-regs", ret);
+ plat->mmio_base = base[0];
+ plat->bdf = pci_get_devfn(dev);
+ if (plat->bdf < 0)
+ return log_msg_ret("Cannot get p2sb PCI address",
+ plat->bdf);
+ } else {
+ plat->mmio_base = dev_read_addr_pci(dev);
+ /* Don't set BDF since it should not be used */
+ if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ }
+#else
+ plat->mmio_base = plat->dtplat.early_regs[0];
+ plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
+#endif
+ upriv->
[PATCH v7 15/17] x86: apl: Add FSP structures
These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6:
- Fix FSP-M and FSP-S in comments
Changes in v5: None
Changes in v4:
- apollolake -> Apollo Lake
Changes in v3:
- Add VBT signature
- Add structures for FSP-S also
- Drop struct fsp_usp_header as it is now in the API file
Changes in v2: None
.../asm/arch-apollolake/fsp/fsp_configs.h | 14 +
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 123
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 ++
.../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 +
4 files changed, 440 insertions(+)
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h
diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h
b/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h
new file mode 100644
index 00..9185d94b2b
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
+#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
+#define VBT_SIGNATURE 0x54425624
+
+#endif
diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
new file mode 100644
index 00..93bee5b2d1
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef__ASM_ARCH_FSP_M_UDP_H
+#define__ASM_ARCH_FSP_M_UDP_H
+
+#include
+
+#define FSP_DRAM_CHANNELS 4
+
+struct __packed fspm_arch_upd {
+ u8 revision;
+ u8 reserved[3];
+ void*nvs_buffer_ptr;
+ void*stack_base;
+ u32 stack_size;
+ u32 boot_loader_tolum_size;
+ u32 boot_mode;
+ u8 reserved1[8];
+};
+
+struct __packed fsp_ram_channel {
+ u8 rank_enable;
+ u8 device_width;
+ u8 dram_density;
+ u8 option;
+ u8 odt_config;
+ u8 tristate_clk1;
+ u8 mode2_n;
+ u8 odt_levels;
+};
+
+struct __packed fsp_m_config {
+ u32 serial_debug_port_address;
+ u8 serial_debug_port_type;
+ u8 serial_debug_port_device;
+ u8 serial_debug_port_stride_size;
+ u8 mrc_fast_boot;
+ u8 igd;
+ u8 igd_dvmt50_pre_alloc;
+ u8 igd_aperture_size;
+ u8 gtt_size;
+ u8 primary_video_adaptor;
+ u8 package;
+ u8 profile;
+ u8 memory_down;
+
+ u8 ddr3_l_page_size;
+ u8 ddr3_lasr;
+ u8 scrambler_support;
+ u8 interleaved_mode;
+ u16 channel_hash_mask;
+ u16 slice_hash_mask;
+ u8 channels_slices_enable;
+ u8 min_ref_rate2x_enable;
+ u8 dual_rank_support_enable;
+ u8 rmt_mode;
+ u16 memory_size_limit;
+ u16 low_memory_max_value;
+
+ u16 high_memory_max_value;
+ u8 disable_fast_boot;
+ u8 dimm0_spd_address;
+ u8 dimm1_spd_address;
+ struct fsp_ram_channel chan[FSP_DRAM_CHANNELS];
+ u8 rmt_check_run;
+ u16 rmt_margin_check_scale_high_threshold;
+ u8 ch_bit_swizzling[FSP_DRAM_CHANNELS][32];
+ u32 msg_level_mask;
+ u8 unused_upd_space0[4];
+
+ u8 pre_mem_gpio_table_pin_num[4];
+ u32 pre_mem_gpio_table_ptr;
+ u8 pre_mem_gpio_table_entry_num;
+ u8 enhance_port8xh_decoding;
+ u8 spd_write_enable;
+ u8 mrc_data_saving;
+ u32 oem_loading_base;
+
+ u8 oem_file_name[16];
+
+ void*mrc_boot_data_ptr;
+ u8 e_mmc_trace_len;
+ u8 skip_cse_rbp;
+ u8 npk_en;
+ u8 fw_trace_en;
+ u8 fw_trace_destination;
+ u8 recover_dump;
+ u8 msc0_wrap;
+ u8 msc1_wrap;
+ u32 msc0_size;
+
+ u32 msc1_size;
+ u8 pti_mode;
+ u8 pti_training;
+ u8 pti_speed;
+ u8 punit_mlvl;
+
+ u8 pmc_mlvl;
+ u8 sw_trace_en;
+ u8 periodic_retraining_disable;
+ u8 enable_reset_system;
+
+ u8 enable_s3_heci2;
+
[PATCH v7 16/17] x86: apl: Add FSP support
The memory and silicon init parts of the FSP need support code to work.
Add this for Apollo Lake.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6:
- Drop mention of devicetree for VTD feature
- Drop mention of ramstage
- Fix various coding style problems
- Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option
- Use 'No SPI' instead of 'SPI2' as a debug message
Changes in v5:
- Allocate the FSP-S data instead of using the stack
- Rename APOLLOLAKE_USB2_PORT_MAX
Changes in v4:
- Adjust the comment for struct dw_i2c_speed_config
- Rename arch_fsp_s_preinit() to arch_fsps_preinit()
- Switch over to use pinctrl for pad init/config
- Tidy up mixed case in FSP code
- apollolake -> Apollo Lake
Changes in v3:
- Add bootstage timing for reading vbt
- Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash)
- Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S
- Set boot_loader_tolum_size to 0
- Use the IRQ uclass instead of ITSS
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 6 +
arch/x86/cpu/apollolake/fsp_m.c | 210 ++
arch/x86/cpu/apollolake/fsp_s.c | 661 +++
3 files changed, 877 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/fsp_m.c
create mode 100644 arch/x86/cpu/apollolake/fsp_s.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index dc6df15dab..1760df54d8 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -10,6 +10,12 @@ obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
obj-y += cpu.o
obj-y += punit.o
+ifdef CONFIG_SPL_BUILD
+obj-y += fsp_m.o
+endif
+endif
+ifndef CONFIG_SPL_BUILD
+obj-y += fsp_s.o
endif
obj-y += hostbridge.o
diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c
new file mode 100644
index 00..5308af8ed4
--- /dev/null
+++ b/arch/x86/cpu/apollolake/fsp_m.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * ODT settings:
+ * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B,
+ * choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A
+ * and LOW for ODT_B, choose ODT_A_B_HIGH_LOW.
+ *
+ * Note that the enum values correspond to the interpreted UPD fields
+ * within Ch[3:0]_OdtConfig parameters.
+ */
+enum {
+ ODT_A_B_HIGH_LOW= 0 << 1,
+ ODT_A_B_HIGH_HIGH = 1 << 1,
+ N_WR_24 = 1 << 5,
+};
+
+/*
+ * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
+ * There are four physical LPDDR4 channels, each 32-bits wide. There are two
+ * logical channels using two physical channels together to form a 64-bit
+ * interface to memory for each logical channel.
+ */
+
+enum {
+ LP4_PHYS_CH0A,
+ LP4_PHYS_CH0B,
+ LP4_PHYS_CH1A,
+ LP4_PHYS_CH1B,
+
+ LP4_NUM_PHYS_CHANNELS,
+};
+
+/*
+ * The DQs within a physical channel can be bit-swizzled within each byte.
+ * Within a channel the bytes can be swapped, but the DQs need to be routed
+ * with the corresponding DQS (strobe).
+ */
+enum {
+ LP4_DQS0,
+ LP4_DQS1,
+ LP4_DQS2,
+ LP4_DQS3,
+
+ LP4_NUM_BYTE_LANES,
+ DQ_BITS_PER_DQS = 8,
+};
+
+/* Provide bit swizzling per DQS and byte swapping within a channel */
+struct lpddr4_chan_swizzle_cfg {
+ u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS];
+};
+
+struct lpddr4_swizzle_cfg {
+ struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
+};
+
+static void setup_sdram(struct fsp_m_config *cfg,
+ const struct lpddr4_swizzle_cfg *swizzle_cfg)
+{
+ const struct lpddr4_chan_swizzle_cfg *sch;
+ /* Number of bytes to copy per DQS */
+ const size_t sz = DQ_BITS_PER_DQS;
+ int chan;
+
+ cfg->memory_down = 1;
+ cfg->scrambler_support = 1;
+ cfg->channel_hash_mask = 0x36;
+ cfg->slice_hash_mask = 9;
+ cfg->interleaved_mode = 2;
+ cfg->channels_slices_enable = 0;
+ cfg->min_ref_rate2x_enable = 0;
+ cfg->dual_rank_support_enable = 1;
+
+ /* LPDDR4 is memory down so no SPD addresses */
+ cfg->dimm0_spd_address = 0;
+ cfg->dimm1_spd_address = 0;
+
+ for (chan = 0; chan < 4; chan++) {
+ struct fsp_ram_channel *ch = &cfg->chan[chan];
+
+ ch->rank_enable = 1;
+ ch->device_width = 1;
+ ch->dram_density = 2;
+ ch->option = 3;
+ ch->odt_config = ODT_A_B_HIGH_HIGH;
+ }
+
+ /*
+* CH0_DQB byte lanes in the bit swizzle configuration field are
+* not 1:1. The mapping within the swizzling field is:
+* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
+* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
+* indices [16:23] - byte lane 3 (DQS
[PATCH v7 14/17] x86: apl: Add Kconfig and Makefile
Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v7: None Changes in v6: - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option Changes in v5: - Enable SMP Changes in v4: - Enable HAVE_X86_FIT - Enable INTEL_GPIO - Switch over to use pinctrl for pad init/config - Use existing VBT Kconfig option - apollolake -> Apollo Lake Changes in v3: - Add MMC, video, USB configs - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot - Fix the incorrect value of CPU_ADDR_BITS Changes in v2: None arch/x86/Kconfig| 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/apollolake/Kconfig | 96 + 3 files changed, 98 insertions(+) create mode 100644 arch/x86/cpu/apollolake/Kconfig diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 1d08cb24fb..89b93e5de2 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -106,6 +106,7 @@ source "board/google/Kconfig" source "board/intel/Kconfig" # platform-specific options below +source "arch/x86/cpu/apollolake/Kconfig" source "arch/x86/cpu/baytrail/Kconfig" source "arch/x86/cpu/braswell/Kconfig" source "arch/x86/cpu/broadwell/Kconfig" diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 0e90a38dc5..5b40838e60 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -41,6 +41,7 @@ extra-y += call32.o endif obj-y += intel_common/ +obj-$(CONFIG_INTEL_APOLLOLAKE) += apollolake/ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_INTEL_BRASWELL) += braswell/ obj-$(CONFIG_INTEL_BROADWELL) += broadwell/ diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig new file mode 100644 index 00..fcff176c27 --- /dev/null +++ b/arch/x86/cpu/apollolake/Kconfig @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2019 Google LLC +# + +config INTEL_APOLLOLAKE + bool + select FSP_VERSION2 + select HAVE_FSP + select ARCH_MISC_INIT + select USE_CAR + select INTEL_PMC + select TPL_X86_TSC_TIMER_NATIVE + select SPL_PCH_SUPPORT + select TPL_PCH_SUPPORT + select PCH_SUPPORT + select P2SB + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply SCSI + imply SCSI_AHCI + imply SPI_FLASH + imply USB + imply USB_EHCI_HCD + imply TPL + imply SPL + imply TPL_X86_16BIT_INIT + imply TPL_OF_PLATDATA + imply ACPI_PMC + imply MMC + imply DM_MMC + imply MMC_PCI + imply MMC_SDHCI + imply CMD_MMC + imply VIDEO_FSP + imply PINCTRL_INTEL + imply PINCTRL_INTEL_APL + imply HAVE_VBT + imply HAVE_X86_FIT + imply INTEL_GPIO + imply SMP + +if INTEL_APOLLOLAKE + +config DCACHE_RAM_BASE + default 0xfef0 + +config DCACHE_RAM_SIZE + default 0xc + +config DCACHE_RAM_MRC_VAR_SIZE + default 0xb + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMM_TSEG + select X86_RAMTEST + +config SMM_TSEG_SIZE + hex + default 0x80 + +config MMCONF_BASE_ADDRESS + hex + default 0xe000 + +config TPL_SIZE_LIMIT + default 0x7800 + +config CPU_ADDR_BITS + default 39 + +config APL_SPI_FLASH_BOOT + bool "Support booting with SPI-flash driver instead memory-mapped SPI" + select TPL_SPI_FLASH_SUPPORT + select TPL_SPI_SUPPORT + help + This enables SPI and SPI flash in TPL. Without the this only + available boot method is to use memory-mapped SPI. Since this is + actually fast and produces a TPL which is 7KB smaller, memory-mapped + SPI is the default. + +config APL_BOOT_FROM_FAST_SPI_FLASH + bool "Boot using SPI flash driver" + select APL_SPI_FLASH_BOOT + help + This option is separate from APL_SPI_FLASH_BOOT since it is useful to + be able to compare booting speed with the same build. Enable this to + use the SPI-flash driver to load SPL, U-Boot and FSP-M. For technical + reasons FSP-S is currently always loaded from memory-mapped SPI. See + Apollo Lake's arch_fsp_init_r() for details about that. + +config VBT_ADDR + default 0xff3f1000 + +endif -- 2.24.0.393.g34dc348eaf-goog
[PATCH v7 12/17] x86: apl: Add SPL/TPL init
Add code to init the system both in TPL and SPL. Each phase has its own
procedure.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7: None
Changes in v6:
- Change comment to apl_hostbridge_early_init_pinctrl, not apl_gpio_early_init
- Change commented-out enable_rtc_upper_bank() call to a TODO
- Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option
- Rename init_for_uart() to board_debug_uart_init()
- Use SZ_4G instead of open-coded shift
Changes in v5: None
Changes in v4:
- Switch over to use pinctrl for pad init/config
Changes in v3:
- Adjust fast_spi_cache_bios_region() to avoid using SPI driver
- Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f()
- Fix build error when debug UART is disabled
- Init the p2sb before the northbridge since the latter so it can use GPIOs
- Move location of fast_spi.h header file
- Shorten log_msg_ret() calls since the function name is always printed
- Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size)
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/cpu_spl.c | 271 ++
2 files changed, 272 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 37e42092ec..edde122f75 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,6 +2,7 @@
#
# Copyright 2019 Google LLC
+obj-$(CONFIG_SPL_BUILD) += cpu_spl.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += cpu_common.o
diff --git a/arch/x86/cpu/apollolake/cpu_spl.c
b/arch/x86/cpu/apollolake/cpu_spl.c
new file mode 100644
index 00..8a39c3128e
--- /dev/null
+++ b/arch/x86/cpu/apollolake/cpu_spl.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Portions taken from coreboot
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Define this here to avoid referencing any drivers for the debug UART 1 */
+#define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0)
+
+static void pch_uart_init(void)
+{
+ /*
+* Set up the pinmux so that the UART rx/tx signals are connected
+* outside the SoC.
+*
+* There are about 500 lines of code required to program the GPIO
+* configuration for the UARTs. But it boils down to four writes, and
+* for the debug UART we want the minimum possible amount of code before
+* the UART is running. So just add the magic writes here. See
+* apl_hostbridge_early_init_pinctrl() for the full horror.
+*/
+ if (PCI_FUNC(PCH_DEV_UART) == 1) {
+ writel(0x4402, 0xd0c50650);
+ writel(0x3c47, 0xd0c50654);
+ writel(0x4400, 0xd0c50658);
+ writel(0x3c48, 0xd0c5065c);
+ } else { /* UART2 */
+ writel(0x4402, 0xd0c50670);
+ writel(0x3c4b, 0xd0c50674);
+ writel(0x4400, 0xd0c50678);
+ writel(0x3c4c, 0xd0c5067c);
+ }
+
+#ifdef CONFIG_DEBUG_UART
+ apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
+#endif
+}
+
+static void p2sb_enable_bar(ulong bar)
+{
+ /* Enable PCR Base address in PCH */
+ pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
+PCI_SIZE_32);
+ pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
+
+ /* Enable P2SB MSE */
+ pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
+PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
+PCI_SIZE_8);
+}
+
+/*
+ * board_debug_uart_init() - Init the debug UART ready for use
+ *
+ * This is the minimum init needed to get the UART running. It avoids any
+ * drivers or complex code, so that the UART is running as soon as possible.
+ */
+void board_debug_uart_init(void)
+{
+ p2sb_enable_bar(IOMAP_P2SB_BAR);
+ pch_uart_init();
+}
+
+static int fast_spi_cache_bios_region(void)
+{
+ uint map_size, offset;
+ ulong map_base, base;
+ int ret;
+
+ ret = fast_spi_early_init(PCH_DEV_SPI, IOMAP_SPI_BASE);
+ if (ret)
+ return log_msg_ret("early_init", ret);
+
+ ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
+&offset);
+ if (ret)
+ return log_msg_ret("get_mmap", ret);
+
+ base = SZ_4G - map_size;
+ mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
+ log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
+
+ return 0;
+}
+
+static void enable_pm_timer_emulation(struct udevice *pmc)
+{
+ struct acpi_pmc_up
[PATCH v7 17/17] x86: Add chromebook_coral
Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v7:
- Add the new documentation to the index file
Changes in v6:
- Add a comment about the need for board_run_command()
- Use generic gpio compatible string
Changes in v5:
- Add gpio-controller to GPIO nodes
- Comment out GPIOs in the fsp_s node since we don't use them yet
- Correct CPU ACPI IDs
- Use a define for ACPI base address
Changes in v4:
- Add u-boot,skip-auto-config-until-reloc property to PCI
- Drop duplicate commit 'Create a new sandbox_pci_read_bar() function'
- New GPIO driver binding
- Set up LPC pads early
- Switch over to use pinctrl for pad init/config
- Update documentation with more detailed memory map
- Use hyphen for device-tree properties
- apollolake -> Apollo Lake
Changes in v3:
- Ad FSP-S support
- Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size
- Add Chrome OS EC support
- Add a proper SPI node and make the SPI flash node a child
- Add bootstage support
- Add more documentation
- Add spi alias in device tree
- Disable the bootcommand since it does nothing useful on coral
- Don't enable SPI flash in TPL by default
- Drop CONFIG_SPL_NET_SUPPORT
- Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs'
- Drop patch 'dm: core: Don't include ofnode functions with of-platdata'
- Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash'
- Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt'
- Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface'
- Drop patch 'x86: timer: Set up the timer in timer_early_get_count()'
- Enable video and USB3
- Reduce amount of early-pad data in TPL
- Tidy up the pad settings in the device tree
- Use a zero-based tsc timer
Changes in v2: None
arch/x86/dts/Makefile | 1 +
arch/x86/dts/chromebook_coral.dts | 831 ++
board/google/Kconfig | 15 +
board/google/chromebook_coral/Kconfig | 43 ++
board/google/chromebook_coral/MAINTAINERS | 6 +
board/google/chromebook_coral/Makefile| 5 +
board/google/chromebook_coral/coral.c | 19 +
configs/chromebook_coral_defconfig| 102 +++
doc/board/google/chromebook_coral.rst | 241 +++
doc/board/google/index.rst| 1 +
include/configs/chromebook_coral.h| 32 +
11 files changed, 1296 insertions(+)
create mode 100644 arch/x86/dts/chromebook_coral.dts
create mode 100644 board/google/chromebook_coral/Kconfig
create mode 100644 board/google/chromebook_coral/MAINTAINERS
create mode 100644 board/google/chromebook_coral/Makefile
create mode 100644 board/google/chromebook_coral/coral.c
create mode 100644 configs/chromebook_coral_defconfig
create mode 100644 doc/board/google/chromebook_coral.rst
create mode 100644 include/configs/chromebook_coral.h
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index d4bdf62be6..be209aaaf8 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -2,6 +2,7 @@
dtb-y += bayleybay.dtb \
cherryhill.dtb \
+ chromebook_coral.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
chromebook_samus.dtb \
diff --git a/arch/x86/dts/chromebook_coral.dts
b/arch/x86/dts/chromebook_coral.dts
new file mode 100644
index 00..24fcbb5063
--- /dev/null
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -0,0 +1,831 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/dts-v1/;
+
+#include
+
+/include/ "skeleton.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+#ifdef CONFIG_CHROMEOS
+#include "chromeos-x86.dtsi"
+#include "flashmap-x86-ro.dtsi"
+#include "flashmap-16mb-rw.dtsi"
+#endif
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ model = "Google Coral";
+ compatible = "google,coral", "intel,apollolake";
+
+ aliases {
+ cros-ec0 = &cros_ec;
+ fsp = &fsp_s;
+ spi0 = &spi;
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = &serial;
+ };
+
+ cpus {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "intel,apl-cpu";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "intel,apl-cpu";
+ reg = <1>;
+ intel,apic-id = <2>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+
Re: [PATCH v6 000/102] x86: Add initial support for apollolake
On Sun, Dec 08, 2019 at 04:54:06PM -0700, Simon Glass wrote: > Hi, > > On Sun, 8 Dec 2019 at 06:23, Tom Rini wrote: > > > > On Sun, Dec 08, 2019 at 04:56:21PM +0800, Bin Meng wrote: > > > Hi Simon, > > > > > > On Sat, Dec 7, 2019 at 12:43 PM Simon Glass wrote: > > > > > > > > Apollo Lake is an Intel SoC generation aimed at relatively low-end > > > > embedded systems. It was released in 2016 but has become more popular > > > > recently with some embedded boards using it. > > > > > > > > This series adds support for Apollo Lake. As an example it adds an > > > > implementation of chromebook_coral (a large range of Chromebooks > > > > released > > > > in 2017). > > > > > > > > The series provides enough support to boot to a prompt. with LCD > > > > display, > > > > storage, USB, EC and keyboard. > > > > > > > > Since this is the first time U-Boot has used FSP2 there is quite a bit > > > > of > > > > refactoring needed. > > > > > > > > This series is available at u-boot-dm/coral-working > > > > > > > > > > I applied the first 85 patches in the v6 series to u-boot-x86/next, > > > except the following 2 patches: > > > > > > [v6,015/102] Revert "RFC: sandbox: net: Suppress the MAC-address warnings > > > [v6,014/102] RFC: sandbox: net: Suppress the MAC-address warnings > > > > > > I believe this needs to be handled by Joe? > > > > > > The patches unfortunately break am335x_evm. > > > > > > Azure logs: > > >arm: + am335x_evm > > > +arm-linux-gnueabi-ld.bfd: u-boot-spl section `.u_boot_list' will not > > > fit in region `.sram' > > > +arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 8 bytes > > > +make[2]: *** [spl/u-boot-spl] Error 1 > > > +make[1]: *** [spl/u-boot-spl] Error 2 > > > +make: *** [sub-make] Error 2 > > > > > > GitLab logs: > > >arm: + am335x_evm > > > +arm-linux-gnueabi-ld.bfd: u-boot-spl section `.u_boot_list' will not > > > fit in region `.sram' > > > +arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 76 bytes > > > +make[2]: *** [spl/u-boot-spl] Error 1 > > > +make[1]: *** [spl/u-boot-spl] Error 2 > > > +make: *** [sub-make] Error 2 > > > > > > Would you please take a look, and propose a fix so that I can squash > > > into the one that breaks this board? > > > https://gitlab.denx.de/u-boot/custodians/u-boot-x86/-/jobs/37696 > > > > > > @Tom, not sure why Azure and GitLab reported different size > > > overflowed? (8 vs 76). Is this caused by build directory path? > > > > Seems likely to be a path size overflow, yeah. > > The use of BUG(), WARN_ON() and friends brings in __FILE__. I'll send > a patch to help with that. > > At least with gcc 7.3 it builds OK for me. > > There are about 13KB of strings in SPL for this board. > > I hate to say it, but it seems that the gcc rodata bug has returned. > For example, it brings in the compat_name[] when building SPL, even > though that is not actually used. I vaguely recall that this only > happens when partial linking is used, but I cannot easily change > U-Boot to use archives these days. We should probably look at getting the patch I sent the other day to drop NFS from SPL when we have networking (like that board does) in as soon as feasible. -- Tom signature.asc Description: PGP signature
Re: [U-Boot] [PATCH v3 14/16] lib: crypto: add x509 parser
On Sat, Dec 07, 2019 at 05:34:07PM -0500, Tom Rini wrote: > On Sat, Dec 07, 2019 at 09:51:22PM +0100, Heinrich Schuchardt wrote: > > On 12/6/19 10:50 PM, Tom Rini wrote: > > > On Wed, Nov 13, 2019 at 09:45:00AM +0900, AKASHI Takahiro wrote: > > > > > > > Imported from linux kernel v5.3: > > > > x509.asn1 without changes > > > > x509_akid.asn1 without changes > > > > x509_parser.h without changes > > > > x509_cert_parser.c with changes marked as __UBOOT__ > > > > x509_public_key.c with changes marked as __UBOOT__ > > > > > > > > Signed-off-by: AKASHI Takahiro > > > > > > Applied to u-boot/master, thanks! > > > > > Hello Tom, > > > > this patch causes a build error for rpi_0_w_defconfig with > > CONFIG_X509_CERTIFICATE_PARSER=y: > > > > In file included from include/linux/time.h:4, > > from lib/crypto/x509_parser.h:8, > > from lib/crypto/x509_cert_parser.c:20: > > include/rtc.h:197:26: error: unknown type name ‘uchar’; did you mean > > ‘unchar’? > > void rtc_write8(int reg, uchar val); > > ^ > > unchar > > make[4]: *** [scripts/Makefile.build:279: lib/crypto/x509_cert_parser.o] > > Error 1 > > > > The error is caused by: > > > > include/linux/types.h:88:typedef unsigned char unchar; > > > > I have prepared a patch but will first run it through Gitlab: > > > > https://gitlab.denx.de/u-boot/custodians/u-boot-efi/commit/f574992867cf40f48a381f88c1ac15a47dbe1baf > > > > @Takahiro: > > I am wondering why this did not show up in your tests. Did Tom miss a patch? Thank you for catching this, Heinrich. > Only sandbox enables any of this out of the box, which is why I've taken > it at this point in the window. It's otherwise neutral and as good as > it was going to get prior to inclusion somewhere for wider testing. > Which, thanks for doing. Yeah, more strictly speaking, my x509 test is enabled by default due to "default y" if UNIT_TEST is also enabled. So if pytest is run on Travis CI, x509 test can also be exercised via pytest's ut driver, but pytest is run on limited number of architectures on Travis CI and UNIT_TEST is enabled only on sandbox for now. Thanks, -Takahiro Akashi > -- > Tom
Re: [U-Boot] [PATCH v3 05/16] include: kernel.h: include printk.h
On Fri, Dec 06, 2019 at 04:49:10PM -0500, Tom Rini wrote: > On Wed, Nov 13, 2019 at 09:44:51AM +0900, AKASHI Takahiro wrote: > > > Adding "printk.h" will help improve portability from linux kernel > > code (in my case, lib/asn1_decoder.c and others) where printf and > > pr_* variant functions are used. > > > > Signed-off-by: AKASHI Takahiro > > Applied to u-boot/master, thanks! Thank you for the merge. Heinrich pointed out a typo in the commit message (not in the code): %s/printf/printk/g Please correct it if you have a chance. Thanks, -Takahiro Akashi > -- > Tom
Re: [PATCH v2 2/4] riscv: add functions for reading the IPI status
> From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> Sent: Monday, December 09, 2019 6:29 AM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Bin Meng; Anup Patel; Lukas Auer; Anup Patel;
> Atish Patra; Daniel Schwierzeck; Simon Glass
> Subject: [PATCH v2 2/4] riscv: add functions for reading the IPI status
>
> Add the function riscv_get_ipi() for reading the pending status of IPIs.
> The supported controllers are Andes' Platform Level Interrupt Controller
> (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
> Interruptor (CLINT).
>
> Signed-off-by: Lukas Auer
> ---
>
> Changes in v2:
> - Use the pending register instead of the claim register in the Andes PLIC
> implementation
>
Reviewed-by: Rick Chen
> arch/riscv/lib/andes_plic.c | 11 +++
> arch/riscv/lib/sbi_ipi.c | 11 +++
> arch/riscv/lib/sifive_clint.c | 9 +
> arch/riscv/lib/smp.c | 12
> 4 files changed, 43 insertions(+)
>
> diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index
> 28568e4e2b..42bda9b759 100644
> --- a/arch/riscv/lib/andes_plic.c
> +++ b/arch/riscv/lib/andes_plic.c
> @@ -114,6 +114,17 @@ int riscv_clear_ipi(int hart)
> return 0;
> }
>
> +int riscv_get_ipi(int hart, int *pending) {
> + PLIC_BASE_GET();
> +
> + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
> +gd->arch.boot_hart));
> + *pending = !!(*pending & SEND_IPI_TO_HART(hart));
> +
> + return 0;
> +}
> +
> static const struct udevice_id andes_plic_ids[] = {
> { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
> { }
> diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c index
> 170346da68..9a698ce74e 100644
> --- a/arch/riscv/lib/sbi_ipi.c
> +++ b/arch/riscv/lib/sbi_ipi.c
> @@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart)
>
> return 0;
> }
> +
> +int riscv_get_ipi(int hart, int *pending) {
> + /*
> +* The SBI does not support reading the IPI status. We always return 0
> +* to indicate that no IPI is pending.
> +*/
> + *pending = 0;
> +
> + return 0;
> +}
> diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
> index d24e0d585b..d7899d16d7 100644
> --- a/arch/riscv/lib/sifive_clint.c
> +++ b/arch/riscv/lib/sifive_clint.c
> @@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart)
> return 0;
> }
>
> +int riscv_get_ipi(int hart, int *pending) {
> + CLINT_BASE_GET();
> +
> + *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
> +
> + return 0;
> +}
> +
> static const struct udevice_id sifive_clint_ids[] = {
> { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
> { }
> diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index
> 705437862a..188a7e34bd 100644
> --- a/arch/riscv/lib/smp.c
> +++ b/arch/riscv/lib/smp.c
> @@ -32,6 +32,18 @@ extern int riscv_send_ipi(int hart);
> */
> extern int riscv_clear_ipi(int hart);
>
> +/**
> + * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
> + *
> + * Platform code must provide this function.
> + *
> + * @hart: Hart ID of hart to be checked
> + * @pending: Pointer to variable with result of the check,
> + * 1 if IPI is pending, 0 otherwise
> + * @return 0 if OK, -ve on error
> + */
> +extern int riscv_get_ipi(int hart, int *pending);
> +
> static int send_ipi_many(struct ipi_data *ipi) {
> ofnode node, cpus;
> --
> 2.21.0
>
Re: [PATCH] net: nfs: Only link in NFS code outside of SPL builds
On Thu, Dec 5, 2019 at 6:36 PM Tom Rini wrote: > > While we have networking use cases within SPL we do not support loading > files via NFS at this point in time. Disable calling nfs_start() so > that the NFS related code can be garbage collected at link time. > > Cc: Joe Hershberger > Signed-off-by: Tom Rini Acked-by: Joe Hershberger
RE: [v3 1/8] rtc: pcf8563: support driver model
> Subject: RE: [v3 1/8] rtc: pcf8563: support driver model
>
>
>
> >-Original Message-
> >From: Biwen Li
> >Sent: Thursday, December 5, 2019 11:40 AM
> >To: Jagdish Gediya ; Priyanka Jain
> >; h...@denx.de; ja...@amarulasolutions.com;
> >aford...@gmail.com; Alison Wang ;
> >bhaskar.upadh...@nxp.com; feng.l...@nxp.com;
> jh80.ch...@samsung.com;
> >Pramod Kumar ; Rajesh Bhagat
> >; Ruchika Gupta ;
> >olte...@gmail.com
> >Cc: Xiaobo Xie ; Jiafei Pan ;
> >u- b...@lists.denx.de; Biwen Li
> >Subject: [v3 1/8] rtc: pcf8563: support driver model
> Please update subject to something like : rtc: pcf8563: Add driver model
> support
Okay, got it, I will update subject in v4.
> >
> >This supports driver model for pcf8563
> Please update description to something like : "Add support of driver model of
> pcf8563"
> >
> >Signed-off-by: Biwen Li
> >---
> >Changes in v3:
> > - update commit messages
> >
> >Changes in v2:
> > - none
> >
> > drivers/rtc/pcf8563.c | 107
> ++
> > 1 file changed, 107 insertions(+)
> >
> >diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index
> >a839d6cc98..44204e133e 100644
> >--- a/drivers/rtc/pcf8563.c
> >+++ b/drivers/rtc/pcf8563.c
> >@@ -12,9 +12,11 @@
> >
> As significant code changes are done, this might need change in copyright.
Got it, I will update copyright in v4.
> Please check
> > #include
> > #include
> >+#include
> > #include
> > #include
> >
> >+#if !CONFIG_IS_ENABLED(DM_RTC)
> > static uchar rtc_read (uchar reg);
> > static void rtc_write (uchar reg, uchar val);
> >
> >@@ -115,3 +117,108 @@ static void rtc_write (uchar reg, uchar val) {
> > i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); }
> >+#else
> >+static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp) {
> >+int rel = 0;
> >+uchar sec, min, hour, mday, wday, mon_cent, year;
> >+
> >+sec = dm_i2c_reg_read(dev, 0x02);
> >+min = dm_i2c_reg_read(dev, 0x03);
> >+hour= dm_i2c_reg_read(dev, 0x04);
> >+mday= dm_i2c_reg_read(dev, 0x05);
> >+wday= dm_i2c_reg_read(dev, 0x06);
> >+mon_cent = dm_i2c_reg_read(dev, 0x07);
> >+year= dm_i2c_reg_read(dev, 0x08);
> >+
> >+debug ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x
> >"
> >+ "hr: %02x min: %02x sec: %02x\n",
> >+ year, mon_cent, mday, wday,
> >+ hour, min, sec);
> >+debug ("Alarms: wday: %02x day: %02x hour: %02x min: %02x\n",
> >+ dm_i2c_reg_read(dev, 0x0C),
> >+ dm_i2c_reg_read(dev, 0x0B),
> >+ dm_i2c_reg_read(dev, 0x0A),
> >+ dm_i2c_reg_read(dev, 0x09));
> >+
> >+if (sec & 0x80) {
> >+puts ("### Warning: RTC Low Voltage - date/time not
> >reliable\n");
> >+rel = -1;
> >+}
> >+
> >+tmp->tm_sec = bcd2bin (sec & 0x7F);
> >+tmp->tm_min = bcd2bin (min & 0x7F);
> >+tmp->tm_hour = bcd2bin (hour & 0x3F);
> >+tmp->tm_mday = bcd2bin (mday & 0x3F);
> >+tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
> >+tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 1900 : 2000);
> >+tmp->tm_wday = bcd2bin (wday & 0x07);
> >+tmp->tm_yday = 0;
> >+tmp->tm_isdst = 0;
> >+
> >+debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME:
> >%2d:%02d:%02d\n",
> >+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
> >+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
> >+
> >+return rel;
> >+}
> >+
> >+static int pcf8563_rtc_set(struct udevice *dev, const struct rtc_time
> >+*tmp) {
> >+uchar century;
> >+
> >+debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME:
> >%2d:%02d:%02d\n",
> >+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
> >+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
> >+
> >+dm_i2c_reg_write(dev, 0x08, bin2bcd(tmp->tm_year % 100));
> >+
> >+century = (tmp->tm_year >= 2000) ? 0 : 0x80;
> >+dm_i2c_reg_write(dev, 0x07, bin2bcd(tmp->tm_mon) | century);
> >+
> >+dm_i2c_reg_write(dev, 0x06, bin2bcd(tmp->tm_wday));
> >+dm_i2c_reg_write(dev, 0x05, bin2bcd(tmp->tm_mday));
> >+dm_i2c_reg_write(dev, 0x04, bin2bcd(tmp->tm_hour));
> >+dm_i2c_reg_write(dev, 0x03, bin2bcd(tmp->tm_min));
> >+dm_i2c_reg_write(dev, 0x02, bin2bcd(tmp->tm_sec));
> >+
> >+return 0;
> >+}
> >+
> >+static int pcf8563_rtc_reset(struct udevice *dev) {
> >+/* clear all control & status registers */
> >+dm_i2c_reg_write(dev, 0x00, 0x00);
> >+dm_i2c_reg_write(dev, 0x01, 0x00);
> >+dm_i2c_reg_write(dev, 0x0D, 0x00);
> >+
> >+/* clear Voltage Low bit */
> >+dm_i2c_reg_write(dev, 0x02, dm_i2c_reg_read (dev, 0x02) & 0x7F);
> >+
> >+/* reset all alarms */
> >+dm_i2c_reg_write(dev, 0x09, 0x00);
> >+dm_i2c_reg_write(dev, 0x0A, 0x00);
> >+dm_i2c_reg_write(dev, 0x0B, 0x00);
> >+dm_i2c_reg_write(dev, 0x0C, 0x00);
> >+
> >+return 0;
> >+}
> >+
> >+static const struct rtc_ops pcf8563_rtc_ops = {
> >+.get = pcf8563_r
[PATCH v4 03/10] soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop
Flush caches when pushing an element to ring and invalidate caches when popping an element from ring in Exposed Ring mode. Otherwise DMA transfers don't work properly in R5 SPL (with caches enabled) where the core is not in coherency domain. Signed-off-by: Vignesh Raghavendra Reviewed-by: Grygorii Strashko --- drivers/soc/ti/k3-navss-ringacc.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index 64ebc0ba0030..f06ea29c986c 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -807,6 +808,11 @@ static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem) memcpy(elem_ptr, elem, (4 << ring->elm_size)); + flush_dcache_range((unsigned long)ring->ring_mem_virt, + ALIGN((unsigned long)ring->ring_mem_virt + +ring->size * (4 << ring->elm_size), +ARCH_DMA_MINALIGN)); + ring->windex = (ring->windex + 1) % ring->size; ring->free--; ringacc_writel(1, &ring->rt->db); @@ -823,6 +829,11 @@ static int k3_nav_ringacc_ring_pop_mem(struct k3_nav_ring *ring, void *elem) elem_ptr = k3_nav_ringacc_get_elm_addr(ring, ring->rindex); + invalidate_dcache_range((unsigned long)ring->ring_mem_virt, + ALIGN((unsigned long)ring->ring_mem_virt + + ring->size * (4 << ring->elm_size), + ARCH_DMA_MINALIGN)); + memcpy(elem, elem_ptr, (4 << ring->elm_size)); ring->rindex = (ring->rindex + 1) % ring->size; -- 2.24.0
[PATCH v4 00/10] dma: ti: k3-udma: Add support for J721e
This series adds DMA support for J721e using exist K3 UDMA driver. One main change is thati, on J721e, DMA resources such as DMA channels are shared between different entities running on different cores of the SoC. Therefore, U-Boot running on A72 core should request range of resources allocated to it from centralized resource management core (DMSC) and use only the allocated resource. First two patches adds support for dynamically querying and using allocated resources. Remaining patches fix issues when using UDMA driver on a 32 bit core like R5. Last patch adds a new compatible for J721e v4: Rebase onto latest master and fix a compliation error due to recent changes in master. v3: Address comments by Grygorii and add R-by Vignesh Raghavendra (10): lib: Import few bitmap functions from Linux dma: ti: k3-udma: Query DMA channels allocated from Resource Manager soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandle dma: ti: k3-udma: Remove coherency check for cache ops dma: ti: k3-udma: Fix debug prints during enabling MEM_TO_DEV transfers dma: ti: k3-udma: Switch to exposed ring mode dma: ti: k3-udma: Fix ring push operation for 32 bit cores dma: ti: k3-udma: Fix build warnings when building for 32 bit platforms dma: ti: k3-udma: Add new compatible to J721e drivers/dma/ti/k3-udma.c | 365 -- drivers/soc/ti/k3-navss-ringacc.c | 14 +- include/linux/bitmap.h| 133 +++ include/linux/bitops.h| 12 + 4 files changed, 404 insertions(+), 120 deletions(-) -- 2.24.0
[PATCH v4 02/10] dma: ti: k3-udma: Query DMA channels allocated from Resource Manager
On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c | 293 ---
1 file changed, 214 insertions(+), 79 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 2e64d338caaf..360f69651680 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -12,12 +12,14 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -31,6 +33,8 @@
#define RINGACC_RING_USE_PROXY (1)
#endif
+#define K3_UDMA_MAX_RFLOWS 1024
+
struct udma_chan;
enum udma_mmr {
@@ -64,10 +68,30 @@ struct udma_rflow {
int id;
};
+enum udma_rm_range {
+ RM_RANGE_TCHAN = 0,
+ RM_RANGE_RCHAN,
+ RM_RANGE_RFLOW,
+ RM_RANGE_LAST,
+};
+
+struct udma_tisci_rm {
+ const struct ti_sci_handle *tisci;
+ const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
+ u32 tisci_dev_id;
+
+ /* tisci information for PSI-L thread pairing/unpairing */
+ const struct ti_sci_rm_psil_ops *tisci_psil_ops;
+ u32 tisci_navss_dev_id;
+
+ struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
+};
+
struct udma_dev {
- struct device *dev;
+ struct udevice *dev;
void __iomem *mmrs[MMR_LAST];
+ struct udma_tisci_rm tisci_rm;
struct k3_nav_ringacc *ringacc;
u32 features;
@@ -79,6 +103,7 @@ struct udma_dev {
unsigned long *tchan_map;
unsigned long *rchan_map;
unsigned long *rflow_map;
+ unsigned long *rflow_map_reserved;
struct udma_tchan *tchans;
struct udma_rchan *rchans;
@@ -88,11 +113,6 @@ struct udma_dev {
u32 psil_base;
u32 ch_count;
- const struct ti_sci_handle *tisci;
- const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
- const struct ti_sci_rm_psil_ops *tisci_psil_ops;
- u32 tisci_dev_id;
- u32 tisci_navss_dev_id;
bool is_coherent;
};
@@ -201,19 +221,25 @@ static inline void udma_rchanrt_write(struct udma_rchan
*rchan,
static inline int udma_navss_psil_pair(struct udma_dev *ud, u32 src_thread,
u32 dst_thread)
{
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
- return ud->tisci_psil_ops->pair(ud->tisci,
- ud->tisci_navss_dev_id,
- src_thread, dst_thread);
+
+ return tisci_rm->tisci_psil_ops->pair(tisci_rm->tisci,
+ tisci_rm->tisci_navss_dev_id,
+ src_thread, dst_thread);
}
static inline int udma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
u32 dst_thread)
{
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
- return ud->tisci_psil_ops->unpair(ud->tisci,
- ud->tisci_navss_dev_id,
- src_thread, dst_thread);
+
+ return tisci_rm->tisci_psil_ops->unpair(tisci_rm->tisci,
+ tisci_rm->tisci_navss_dev_id,
+ src_thread, dst_thread);
}
static inline char *udma_get_dir_text(enum dma_direction dir)
@@ -536,6 +562,28 @@ static void udma_poll_completion(struct udma_chan *uc,
dma_addr_t *paddr)
}
}
+static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id)
+{
+ DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
+
+ if (id >= 0) {
+ if (test_bit(id, ud->rflow_map)) {
+ dev_err(ud->dev, "rflow%d is in use\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+ } else {
+ bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved,
+ ud->rflow_cnt);
+
+ id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt);
+ if (id >= ud->rflow_cnt)
+ return ERR_PTR(-ENOENT);
+ }
+
+ __set_bit(id, ud->rflow_map);
+ return &ud->rflows[id];
+}
+
#define UDMA_RESERVE_RESOURCE(res) \
static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud,\
int id) \
@@ -558,7 +606,6 @@ static struct udma_##res *__udma_reserve_##res(struct
udma_dev *ud, \
UDMA_RESERVE_RESOURCE(tchan);
UDMA_RESERVE_RESOURCE(rchan);
-UDMA_RESERVE_RESOURCE
[PATCH v4 01/10] lib: Import few bitmap functions from Linux
Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}())
and their dependencies from Linux. These are required for upcoming DMA
resource allocation support for TI's K3 SoCs.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
include/linux/bitmap.h | 133 +
include/linux/bitops.h | 12
2 files changed, 145 insertions(+)
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index fbbb67c8b24e..dae4225be549 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -5,10 +5,88 @@
#include
#include
#include
+#include
+#ifdef __LITTLE_ENDIAN
+#define BITMAP_MEM_ALIGNMENT 8
+#else
+#define BITMAP_MEM_ALIGNMENT (8 * sizeof(unsigned long))
+#endif
+#define BITMAP_MEM_MASK (BITMAP_MEM_ALIGNMENT - 1)
+
+#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1)))
+#define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1)))
#define small_const_nbits(nbits) \
(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
+static inline void
+__bitmap_or(unsigned long *dst, const unsigned long *bitmap1,
+ const unsigned long *bitmap2, unsigned int bits)
+{
+ unsigned int k;
+ unsigned int nr = BITS_TO_LONGS(bits);
+
+ for (k = 0; k < nr; k++)
+ dst[k] = bitmap1[k] | bitmap2[k];
+}
+
+static inline int
+__bitmap_weight(const unsigned long *bitmap, unsigned int bits)
+{
+ unsigned int k, lim = bits / BITS_PER_LONG;
+ int w = 0;
+
+ for (k = 0; k < lim; k++)
+ w += hweight_long(bitmap[k]);
+
+ if (bits % BITS_PER_LONG)
+ w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits));
+
+ return w;
+}
+
+static inline void
+__bitmap_set(unsigned long *map, unsigned int start, int len)
+{
+ unsigned long *p = map + BIT_WORD(start);
+ const unsigned int size = start + len;
+ int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG);
+ unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start);
+
+ while (len - bits_to_set >= 0) {
+ *p |= mask_to_set;
+ len -= bits_to_set;
+ bits_to_set = BITS_PER_LONG;
+ mask_to_set = ~0UL;
+ p++;
+ }
+ if (len) {
+ mask_to_set &= BITMAP_LAST_WORD_MASK(size);
+ *p |= mask_to_set;
+ }
+}
+
+static inline void
+__bitmap_clear(unsigned long *map, unsigned int start, int len)
+{
+ unsigned long *p = map + BIT_WORD(start);
+ const unsigned int size = start + len;
+ int bits_to_clear = BITS_PER_LONG - (start % BITS_PER_LONG);
+ unsigned long mask_to_clear = BITMAP_FIRST_WORD_MASK(start);
+
+ while (len - bits_to_clear >= 0) {
+ *p &= ~mask_to_clear;
+ len -= bits_to_clear;
+ bits_to_clear = BITS_PER_LONG;
+ mask_to_clear = ~0UL;
+ p++;
+ }
+ if (len) {
+ mask_to_clear &= BITMAP_LAST_WORD_MASK(size);
+ *p &= ~mask_to_clear;
+ }
+}
+
static inline void bitmap_zero(unsigned long *dst, int nbits)
{
if (small_const_nbits(nbits)) {
@@ -81,4 +159,59 @@ static inline unsigned long find_first_bit(const unsigned
long *addr, unsigned l
(bit) < (size);\
(bit) = find_next_bit((addr), (size), (bit) + 1))
+static inline void bitmap_fill(unsigned long *dst, unsigned int nbits)
+{
+ if (small_const_nbits(nbits)) {
+ *dst = ~0UL;
+ } else {
+ unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
+
+ memset(dst, 0xff, len);
+ }
+}
+
+static inline void bitmap_or(unsigned long *dst, const unsigned long *src1,
+const unsigned long *src2, unsigned int nbits)
+{
+ if (small_const_nbits(nbits))
+ *dst = *src1 | *src2;
+ else
+ __bitmap_or(dst, src1, src2, nbits);
+}
+
+static inline int bitmap_weight(const unsigned long *src, unsigned int nbits)
+{
+ if (small_const_nbits(nbits))
+ return hweight_long(*src & BITMAP_LAST_WORD_MASK(nbits));
+ return __bitmap_weight(src, nbits);
+}
+
+static inline void bitmap_set(unsigned long *map, unsigned int start,
+ unsigned int nbits)
+{
+ if (__builtin_constant_p(nbits) && nbits == 1)
+ __set_bit(start, map);
+ else if (__builtin_constant_p(start & BITMAP_MEM_MASK) &&
+IS_ALIGNED(start, BITMAP_MEM_ALIGNMENT) &&
+__builtin_constant_p(nbits & BITMAP_MEM_MASK) &&
+IS_ALIGNED(nbits, BITMAP_MEM_ALIGNMENT))
+ memset((char *)map + start / 8, 0xff, nbits / 8);
+ else
+ __bitmap_set(map, start, nbits);
+}
+
+static inline void bitmap_clear(unsigned long *map, unsigned int start,
+
