Re: [PATCH 6/6] rockchip: rk3328: Add support for ROC-RK3328-CC board
On 2020/3/27 下午12:41, Chen-Yu Tsai wrote:
From: Chen-Yu Tsai
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
card size development board based on the Rockchip RK3328 SoC, with:
- 1/2/4 GB DDR4 DRAM
- eMMC connector for optional module
- micro SD card slot
- 1 x USB 3.0 host port
- 2 x USB 2.0 host port
- 1 x USB 2.0 OTG port
- HDMI video output
- TRRS connector with audio and composite video output
- gigabit Ethernet
- consumer IR receiver
- debug UART pins
The ROC-RK3328-CC has the enable pin of the SD card power switch tied
to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is
muxed by default. SDMMC0_PWREN is an active high signal controlled by
the MMC controller, however the switch enable is active low, and
pulled low (enabled) by default to make things work on boot.
As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable
power to the card. The default GPIO state for the pin is pull-down and
input, which doesn't require extra configuration when paired with the
external pull-down and active low switch.
Thus we make a custom target for this board and do the muxing in its
spl_board_init() function.
The device tree file is synced from the Linux kernel next-20200324.
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 17 ++
arch/arm/dts/rk3328-roc-cc.dts | 354
arch/arm/mach-rockchip/rk3328/Kconfig | 8 +
board/firefly/roc-cc-rk3328/Kconfig | 24 ++
board/firefly/roc-cc-rk3328/MAINTAINERS | 7 +
board/firefly/roc-cc-rk3328/Makefile| 1 +
board/firefly/roc-cc-rk3328/board.c | 38 +++
configs/roc-cc-rk3328_defconfig | 97 +++
doc/README.rockchip | 4 +-
10 files changed, 550 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3328-roc-cc.dts
create mode 100644 board/firefly/roc-cc-rk3328/Kconfig
create mode 100644 board/firefly/roc-cc-rk3328/MAINTAINERS
create mode 100644 board/firefly/roc-cc-rk3328/Makefile
create mode 100644 board/firefly/roc-cc-rk3328/board.c
create mode 100644 configs/roc-cc-rk3328_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c593b2c986a..023cb010532d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -104,6 +104,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
+ rk3328-roc-cc.dtb \
rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
new file mode 100644
index ..15b67f8bbdf4
--- /dev/null
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+};
+
+&usb_host0_xhci {
+ vbus-supply = <&vcc_host1_5v>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts
new file mode 100644
index ..8d553c92182a
--- /dev/null
+++ b/arch/arm/dts/rk3328-roc-cc.dts
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Firefly roc-rk3328-cc";
+ compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-boot-on;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&grf_gpio 0 GPIO_AC
Re: [PATCH 5/6] rockchip: dts: rk3328: Sync device tree files from Linux
On 2020/3/27 下午12:41, Chen-Yu Tsai wrote:
From: Chen-Yu Tsai
This syncs rk3328 device tree files from the Linux kernel next-20200324.
The last commit to touch these files is:
b2411befed60 ("arm64: dts: add bus to rockchip amba nodenames")
Additional changes not yet in the Linux kernel include:
arm64: dts: rockchip: rk3328: drop #address-cells, #size-cells from grf
node
arm64: dts: rockchip: rk3328: drop non-existent gmac2phy pinmux options
arm64: dts: rockchip: rk3328: Replace RK805 PMIC node name with "pmic"
Changes include:
- conversion of raw pin numbers to macros
- removal of deprecated RK_FUNC_* macros
- update of device tree binding headers
- new devices
- device tree cleanups
- gmac2phy disabled in -u-boot.dtsi as it is not supported in U-boot
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3328-evb-u-boot.dtsi |5 +
arch/arm/dts/rk3328-evb.dts | 196 ++--
arch/arm/dts/rk3328-rock64.dts | 132 ++-
arch/arm/dts/rk3328.dtsi| 1420 +--
4 files changed, 1164 insertions(+), 589 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 8ba53cf8f44b..4bfa0c2330ba 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -40,6 +40,11 @@
status = "okay";
};
+&gmac2phy {
+ /* Integrated PHY unsupported by U-boot */
+ status = "broken";
+};
+
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 97bef37cf610..6abc6f4a86cf 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
@@ -11,24 +11,51 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
chosen {
- stdout-path = &uart2;
+ stdout-path = "serial2:150n8";
};
- vcc3v3_sdmmc: sdmmc-pwren {
+ dc_12v: dc-12v {
compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc_io>;
};
- vcc5v0_otg: vcc5v0-otg-drv {
+ vcc_sys: vcc-sys {
compatible = "regulator-fixed";
- enable-active-high;
- regulator-name = "vcc5v0_otg";
- gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
+ vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
@@ -39,80 +66,60 @@
};
};
-&saradc {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- disable-wp;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>,
<&sdmmc0_bus4>;
- status = "okay";
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
- supports-emmc;
- disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
-&usb_host0_ehci {
- status = "okay";
-};
+&gmac2phy {
+ phy-supply = <&v
Re: [PATCH 3/6] dt-bindings: clock: rk3328: sync from upstream Linux kernel
On 2020/3/27 下午12:41, Chen-Yu Tsai wrote:
From: Chen-Yu Tsai
This syncs the rk3328 clock header file from Linux kernel next-20200324,
to support newer hardware blocks when syncing the device tree files.
The last non-merge commit to touch it was
0dc14b013f79 ("clk: rockchip: add clock id for watchdog pclk on rk3328")
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Kever Yang
Thanks,
- Kever
---
include/dt-bindings/clock/rk3328-cru.h | 212 -
1 file changed, 106 insertions(+), 106 deletions(-)
diff --git a/include/dt-bindings/clock/rk3328-cru.h
b/include/dt-bindings/clock/rk3328-cru.h
index cde61ed8830b..555b4ff660ae 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -1,6 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Elaine
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
@@ -90,119 +91,118 @@
#define SCLK_MAC2IO_EXT 102
/* dclk gates */
-#define DCLK_LCDC 180
-#define DCLK_HDMIPHY 181
-#define HDMIPHY182
-#define USB480M183
-#define DCLK_LCDC_SRC 184
+#define DCLK_LCDC 120
+#define DCLK_HDMIPHY 121
+#define HDMIPHY122
+#define USB480M123
+#define DCLK_LCDC_SRC 124
/* aclk gates */
-#define ACLK_AXISRAM 190
-#define ACLK_VOP_PRE 191
-#define ACLK_USB3OTG 192
-#define ACLK_RGA_PRE 193
-#define ACLK_DMAC 194
-#define ACLK_GPU 195
-#define ACLK_BUS_PRE 196
-#define ACLK_PERI_PRE 197
-#define ACLK_RKVDEC_PRE198
-#define ACLK_RKVDEC199
-#define ACLK_RKVENC200
-#define ACLK_VPU_PRE 201
-#define ACLK_VIO_PRE 202
-#define ACLK_VPU 203
-#define ACLK_VIO 204
-#define ACLK_VOP 205
-#define ACLK_GMAC 206
-#define ACLK_H265 207
-#define ACLK_H264 208
-#define ACLK_MAC2PHY 209
-#define ACLK_MAC2IO210
-#define ACLK_DCF 211
-#define ACLK_TSP 212
-#define ACLK_PERI 213
-#define ACLK_RGA 214
-#define ACLK_IEP 215
-#define ACLK_CIF 216
-#define ACLK_HDCP 217
+#define ACLK_AXISRAM 130
+#define ACLK_VOP_PRE 131
+#define ACLK_USB3OTG 132
+#define ACLK_RGA_PRE 133
+#define ACLK_DMAC 134
+#define ACLK_GPU 135
+#define ACLK_BUS_PRE 136
+#define ACLK_PERI_PRE 137
+#define ACLK_RKVDEC_PRE138
+#define ACLK_RKVDEC139
+#define ACLK_RKVENC140
+#define ACLK_VPU_PRE 141
+#define ACLK_VIO_PRE 142
+#define ACLK_VPU 143
+#define ACLK_VIO 144
+#define ACLK_VOP 145
+#define ACLK_GMAC 146
+#define ACLK_H265 147
+#define ACLK_H264 148
+#define ACLK_MAC2PHY 149
+#define ACLK_MAC2IO150
+#define ACLK_DCF 151
+#define ACLK_TSP 152
+#define ACLK_PERI 153
+#define ACLK_RGA 154
+#define ACLK_IEP 155
+#define ACLK_CIF 156
+#define ACLK_HDCP 157
/* pclk gates */
-#define PCLK_GPIO0 300
-#define PCLK_GPIO1 301
-#define PCLK_GPIO2 302
-#define PCLK_GPIO3 303
-#define PCLK_GRF 304
-#define PCLK_I2C0 305
-#define PCLK_I2C1 306
-#define PCLK_I2C2 307
-#define PCLK_I2C3 308
-#define PCLK_SPI 309
-#define PCLK_UART0 310
-#define PCLK_UART1 311
-#define PCLK_UART2 312
-#define PCLK_TSADC 313
-#define PCLK_PWM 314
-#define PCLK_TIMER 315
-#define PCLK_BUS_PRE 316
-#define PCLK_PERI_PRE 317
-#define PCLK_HDMI_CTRL 318
-#define PCLK_HDMI_PHY 319
-#define PCLK_GMAC 320
-#define PCLK_H265 321
-#define PCLK_MAC2PHY 322
-#define PCLK_MAC2IO323
-#define PCLK_USB3PHY_OTG 324
-#define PCLK_USB3PHY_PIPE 325
-#define PCLK_USB3_GRF 326
-#define PCLK_USB2_GRF 327
-#define PCLK_HDMIPHY 328
-#define PCLK_DDR 329
-#define PCLK_PERI 330
-#define PCLK_HDMI 331
-#define PCLK_HDCP 332
-#define PCLK_DCF 333
-#define PCLK_SARADC334
+#define PCLK_GPIO0 200
+#define PCLK_GPIO1 201
+#define PCLK_GPIO2 202
+#define PCLK_GPI
Re: [PATCH 2/6] rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi
On 2020/3/27 下午12:41, Chen-Yu Tsai wrote:
From: Chen-Yu Tsai
The device tree file for rk3328-evb in the Linux kernel does not have
gmac2io enabled. Instead, gmac2phy is enabled, but that is not supported
in U-boot.
Move the gmac2io related nodes to rk3328-evb-u-boot.dtsi to preserve the
current functionality. When the device tree files are synced, gmac2phy
should be marked as "broken" in -u-boot.dtsi files.
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3328-evb-u-boot.dtsi | 23 +++
arch/arm/dts/rk3328-evb.dts | 23 ---
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 5679897279aa..8ba53cf8f44b 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -7,6 +7,13 @@
#include "rk3328-sdram-ddr3-666.dtsi"
/{
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
compatible = "regulator-fixed";
enable-active-high;
@@ -17,6 +24,22 @@
};
};
+&gmac2io {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index e9bc849f8c23..97bef37cf610 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -14,13 +14,6 @@
stdout-path = &uart2;
};
- gmac_clkin: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <12500>;
- clock-output-names = "gmac_clkin";
- #clock-cells = <0>;
- };
-
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -78,22 +71,6 @@
status = "okay";
};
-&gmac2io {
- phy-supply = <&vcc_phy>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 1 5>;
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_pins>;
- tx_delay = <0x26>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
&usb_host0_ehci {
status = "okay";
};
Re: [PATCH 4/6] dt-bindings: power: rk3328-power: sync from upstream Linux kernel
On 2020/3/27 下午12:41, Chen-Yu Tsai wrote:
From: Chen-Yu Tsai
This syncs the rk3328 power domain header file from Linux kernel
next-20200324, to support newer hardware blocks when syncing the
device tree files.
The last non-merge commit to touch it was
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files
with no license")
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Kever Yang
Thanks,
- Kever
---
include/dt-bindings/power/rk3328-power.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/dt-bindings/power/rk3328-power.h
diff --git a/include/dt-bindings/power/rk3328-power.h
b/include/dt-bindings/power/rk3328-power.h
new file mode 100644
index ..02e3d7fc1cce
--- /dev/null
+++ b/include/dt-bindings/power/rk3328-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__
+#define __DT_BINDINGS_POWER_RK3328_POWER_H__
+
+/**
+ * RK3328 idle id Summary.
+ */
+#define RK3328_PD_CORE 0
+#define RK3328_PD_GPU 1
+#define RK3328_PD_BUS 2
+#define RK3328_PD_MSCH 3
+#define RK3328_PD_PERI 4
+#define RK3328_PD_VIDEO5
+#define RK3328_PD_HEVC 6
+#define RK3328_PD_SYS 7
+#define RK3328_PD_VPU 8
+#define RK3328_PD_VIO 9
+
+#endif
Re: [PATCH 1/6] rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi
Hi ChenYu,
On 2020/3/27 下午12:41, Chen-Yu Tsai wrote:
From: Chen-Yu Tsai
USB 3.0 is only supported in U-boot, not in the Linux kernel where the
device tree files are ultimately synced from. While the xhci node was
moved, the external vbus regulator was not.
Move it as well.
Fixes: 2e91e2025c1b ("rockchip: rk3328: migrate u-boot node to -u-boot.dtsi")
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3328-evb-u-boot.dtsi | 11 +++
arch/arm/dts/rk3328-evb.dts | 9 -
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 4a827063c555..5679897279aa 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -6,6 +6,17 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr3-666.dtsi"
+/{
+ vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_host_xhci";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+};
+
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index a2ee838fcd6b..e9bc849f8c23 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -38,15 +38,6 @@
regulator-max-microvolt = <500>;
};
- vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
- compatible = "regulator-fixed";
- enable-active-high;
- regulator-name = "vcc5v0_host_xhci";
- gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- };
-
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
Re: [PATCH 04/16] part: detect EFI system partition
Hi Heinrich,
Heinrich Schuchardt writes:
> Up to now for MBR and GPT partitions the info field 'bootable' was set to 1
> if either the partition was an EFI system partition or the bootable flag
> was set.
>
> Turn info field 'bootable' into a bit mask with separate bits for bootable
> and EFI system partition.
>
> This will allow us to identify the EFI system partition in the UEFI
> sub-system.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> disk/part_dos.c | 10 --
> disk/part_efi.c | 12
> include/part.h | 11 ++-
> 3 files changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/disk/part_dos.c b/disk/part_dos.c
[...]
> diff --git a/include/part.h b/include/part.h
> index 0b5cf3d5e8..a63d1d0cda 100644
> --- a/include/part.h
> +++ b/include/part.h
> @@ -51,13 +51,22 @@ struct block_drvr {
> #define PART_TYPE_LEN 32
> #define MAX_SEARCH_PARTITIONS 64
>
> +#define PART_BOOTABLE1
> +#define PART_EFI_SYSTEM_PARTITION2
> +
Maybe you missed my comments on the previous version [0].
As the above defines are used as bit positions, please consider using
BIT() for clarity.
Thanks,
Punit
[0] https://lists.denx.de/pipermail/u-boot/2020-March/404081.html
> typedef struct disk_partition {
> lbaint_tstart; /* # of first block in partition*/
> lbaint_tsize; /* number of blocks in partition*/
> ulong blksz; /* block size in bytes */
> uchar name[PART_NAME_LEN];/* partition name
> */
> uchar type[PART_TYPE_LEN];/* string type description
> */
> - int bootable; /* Active/Bootable flag is set */
> + /*
> + * The bootable is a bitmask with the following fields:
> + *
> + * PART_BOOTABLEthe MBR bootable flag is set
> + * PART_EFI_SYSTEM_PARTITIONthe partition is an EFI system partition
> + */
> + int bootable;
> #if CONFIG_IS_ENABLED(PARTITION_UUIDS)
> charuuid[UUID_STR_LEN + 1]; /* filesystem UUID as string, if exists
> */
> #endif
> --
> 2.25.1
Re: [PATCH 1/3] Dockerfile: Install riscv32 toolchain from kernel.org
Hi Tom, On Fri, Mar 27, 2020 at 10:00 AM Tom Rini wrote: > > On Fri, Mar 27, 2020 at 09:57:47AM +0800, Bin Meng wrote: > > Hi Tom, > > > > On Fri, Mar 27, 2020 at 12:14 AM Tom Rini wrote: > > > > > > On Thu, Mar 26, 2020 at 09:04:52AM -0700, Bin Meng wrote: > > > > > > > This is required to build GRUB UEFI target for RISC-V 32-bit. > > > > > > > > Signed-off-by: Bin Meng > > > > > > Since we can use the 64bit toolchain for 32bit U-Boot, can we not pass > > > GRUB the right flags to use the same toolchain? Thanks! > > > > The 32-bit GRUB won't build with the 64-bit toolchain as of the > > grub-2.04 branch we are using. > > Is that something that upstream has fixed or will fix / can be fixed and > we can bump the tag we're using for? I tried the latest upstream GRUB, and it still cannot be built using riscv64 toolchain from kernel.org. Regards, Bin
Re: [PATCH 1/1] vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader.
On 3/27/20 2:39 AM, Tom Rini wrote: On Tue, Feb 25, 2020 at 06:22:16PM +0100, Kristian Amlie wrote: EFI was disabled in f95b8a4b5f64f because of the missing DTB file, and indeed, the DTB file is required to load recent versions of GRUB (2.04) correctly. Signed-off-by: Kristian Amlie Applied to u-boot/master, thanks! Since this patch is merged I get errors on Gitlab for vexpress_ca9x4: https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/jobs/69269 Filename 'lib/efi_loader/helloworld.efi'. Load address: 0x6000 Loading: *# 1.8 MiB/s done Bytes transferred = 1840 (730 hex) smc911x: MAC 52:54:00:12:34:56 => => crc32 6000 $filesize CRC32 for 6000 ... 672f ==> f5c77855 => => bootefi 6000 7[r[999;999H[6n8Scanning disks on mmc... Card did not respond to voltage select! MMC Device 1 not found MMC Device 2 not found MMC Device 3 not found Found 0 disks ERROR: need device tree Best regards Heinrich
Re: [PATCH 1/4] travis: Remove qemu-riscv64 testing
On Fri, Mar 27, 2020 at 7:31 AM Bin Meng wrote: > > On Fri, Mar 27, 2020 at 1:20 PM David Abdurachmanov > wrote: > > > > On Thu, Mar 26, 2020 at 6:06 PM Bin Meng wrote: > > > > > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > > > available on the internet, and with travis-ci we don't build GRUB > > > images like we do for azure and gitlab. > > > > There are RPM packages for GRUB in OpenSUSE and Fedora. > > > > https://build.opensuse.org/package/binaries/openSUSE:Factory:RISCV/grub2/standard > > http://fedora.riscv.rocks/koji/buildinfo?buildID=133151 > > > > I've looked at this alternatives before, it turns out there are only > riscv64 images. Do you know any riscv32 prebuilt images? I am not aware of any distribution supporting RV32 (or plans to do it). Furthermore RV32 Linux ABI is not frozen yet. OE definitely has RV32 Linux support, but it doesn't incl. RV32 GRUB2 for booting. Simply put, I don't think there are RV32 GRUB2 binaries somewhere online. > > > I have not tried them on QEMU or Unleashed yet. > > > > We should be able to boot with GRUB2 and EFI stubs to the kernel soonish. > > Regards, > Bin
Re: [PATCH 1/4] travis: Remove qemu-riscv64 testing
On Fri, Mar 27, 2020 at 1:20 PM David Abdurachmanov wrote: > > On Thu, Mar 26, 2020 at 6:06 PM Bin Meng wrote: > > > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > > available on the internet, and with travis-ci we don't build GRUB > > images like we do for azure and gitlab. > > There are RPM packages for GRUB in OpenSUSE and Fedora. > > https://build.opensuse.org/package/binaries/openSUSE:Factory:RISCV/grub2/standard > http://fedora.riscv.rocks/koji/buildinfo?buildID=133151 > I've looked at this alternatives before, it turns out there are only riscv64 images. Do you know any riscv32 prebuilt images? > I have not tried them on QEMU or Unleashed yet. > > We should be able to boot with GRUB2 and EFI stubs to the kernel soonish. Regards, Bin
[PATCH 03/16] efi_loader: eliminate EFI_CALL() for variable access
In several places of the UEFI sub-system UEFI variables as accessed via
runtime services functions. These functions require being called via
EFI_CALL() to restore the register holding the gd variable. Some code
even calls the functions via the runtime services table.
By making the functions exposing the variable runtime services wrappers for
exported functions that we can use internally we get rid of this clumsy
code.
Signed-off-by: Heinrich Schuchardt
---
cmd/efidebug.c| 63 +--
cmd/nvedit_efi.c | 18 +++---
include/efi_loader.h | 9 +++
lib/efi_loader/efi_bootmgr.c | 20 +++---
lib/efi_loader/efi_setup.c| 42 ++---
lib/efi_loader/efi_variable.c | 114 +++---
6 files changed, 168 insertions(+), 98 deletions(-)
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index c1bb76477a..f89c1d2db7 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -17,7 +17,6 @@
#include
#define BS systab.boottime
-#define RT systab.runtime
/**
* efi_get_device_handle_info() - get information of UEFI device
@@ -614,11 +613,11 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag,
goto out;
}
- ret = EFI_CALL(RT->set_variable(var_name16, &guid,
- EFI_VARIABLE_NON_VOLATILE |
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
- size, data));
+ ret = efi_set_variable_int(var_name16, &guid,
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ size, data);
if (ret != EFI_SUCCESS) {
printf("Cannot set %ls\n", var_name16);
r = CMD_RET_FAILURE;
@@ -669,7 +668,8 @@ static int do_efi_boot_rm(cmd_tbl_t *cmdtp, int flag,
p = var_name16;
utf8_utf16_strncpy(&p, var_name, 9);
- ret = EFI_CALL(RT->set_variable(var_name16, &guid, 0, 0, NULL));
+ ret = efi_set_variable_int(var_name16, &guid, 0, 0,
+ NULL);
if (ret) {
printf("Cannot remove %ls\n", var_name16);
return CMD_RET_FAILURE;
@@ -749,11 +749,11 @@ static void show_efi_boot_opt(int id)
guid = efi_global_variable_guid;
size = 0;
- ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size, NULL));
+ ret = efi_get_variable_int(var_name16, &guid, NULL, &size, NULL);
if (ret == EFI_BUFFER_TOO_SMALL) {
data = malloc(size);
- ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
- data));
+ ret = efi_get_variable_int(var_name16, &guid, NULL, &size,
+ data);
}
if (ret == EFI_SUCCESS)
show_efi_boot_opt_data(id, data, size);
@@ -808,8 +808,7 @@ static int do_efi_boot_dump(cmd_tbl_t *cmdtp, int flag,
var_name16[0] = 0;
for (;;) {
size = buf_size;
- ret = EFI_CALL(efi_get_next_variable_name(&size, var_name16,
- &guid));
+ ret = efi_get_next_variable_name_int(&size, var_name16, &guid);
if (ret == EFI_NOT_FOUND)
break;
if (ret == EFI_BUFFER_TOO_SMALL) {
@@ -820,9 +819,8 @@ static int do_efi_boot_dump(cmd_tbl_t *cmdtp, int flag,
return CMD_RET_FAILURE;
}
var_name16 = p;
- ret = EFI_CALL(efi_get_next_variable_name(&size,
- var_name16,
- &guid));
+ ret = efi_get_next_variable_name_int(&size, var_name16,
+&guid);
}
if (ret != EFI_SUCCESS) {
free(var_name16);
@@ -870,12 +868,11 @@ static int show_efi_boot_order(void)
guid = efi_global_variable_guid;
size = 0;
- ret = EFI_CALL(RT->get_variable(L"BootOrder", &guid, NULL, &size,
- NULL));
+ ret = efi_get_variable_int(L"BootOrder", &guid, NULL, &size, NULL);
if (ret == EFI_BUFFER_TOO_SMALL) {
bootorder = malloc(size);
- ret = EFI_CALL(RT->get_variable(L"BootOrder", &guid, NULL,
- &size, bootorder));
+ ret = efi_get_variable_int(L"BootOrder", &guid, NULL,
+
[PATCH 14/16] efi_loader: use memory based variable storage
Saving UEFI variable as encoded U-Boot environment variables does not allow
implement run-time support.
Use a memory buffer for storing UEFI variables.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/efi_variable.c | 584 +++--
lib/efi_loader/efi_variables_mem.c | 7 +
2 files changed, 147 insertions(+), 444 deletions(-)
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 952a0a0db7..7c39542968 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -2,152 +2,15 @@
/*
* UEFI runtime variable services
*
- * Copyright (c) 2017 Rob Clark
+ * Copyright (c) 2019 Heinrich Schuchardt
*/
#include
#include
#include
-#include
-#include
-#include
-#include
-#include
#define READ_ONLY BIT(31)
-/*
- * Mapping between EFI variables and u-boot variables:
- *
- * efi_$guid_$varname = {attributes}(type)value
- *
- * For example:
- *
- * efi_8be4df61-93ca-11d2-aa0d-00e098032b8c_OsIndicationsSupported=
- * "{ro,boot,run}(blob)"
- * efi_8be4df61-93ca-11d2-aa0d-00e098032b8c_BootOrder=
- * "(blob)0001"
- *
- * The attributes are a comma separated list of these possible
- * attributes:
- *
- * + ro - read-only
- * + boot - boot-services access
- * + run - runtime access
- *
- * NOTE: with current implementation, no variables are available after
- * ExitBootServices, and all are persisted (if possible).
- *
- * If not specified, the attributes default to "{boot}".
- *
- * The required type is one of:
- *
- * + utf8 - raw utf8 string
- * + blob - arbitrary length hex string
- *
- * Maybe a utf16 type would be useful to for a string value to be auto
- * converted to utf16?
- */
-
-#define PREFIX_LEN (strlen("efi_----_"))
-
-/**
- * efi_to_native() - convert the UEFI variable name and vendor GUID to U-Boot
- * variable name
- *
- * The U-Boot variable name is a concatenation of prefix 'efi', the hexstring
- * encoded vendor GUID, and the UTF-8 encoded UEFI variable name separated by
- * underscores, e.g. 'efi_8be4df61-93ca-11d2-aa0d-00e098032b8c_BootOrder'.
- *
- * @native:pointer to pointer to U-Boot variable name
- * @variable_name: UEFI variable name
- * @vendor:vendor GUID
- * Return: status code
- */
-static efi_status_t efi_to_native(char **native, const u16 *variable_name,
- const efi_guid_t *vendor)
-{
- size_t len;
- char *pos;
-
- len = PREFIX_LEN + utf16_utf8_strlen(variable_name) + 1;
- *native = malloc(len);
- if (!*native)
- return EFI_OUT_OF_RESOURCES;
-
- pos = *native;
- pos += sprintf(pos, "efi_%pUl_", vendor);
- utf16_utf8_strcpy(&pos, variable_name);
-
- return EFI_SUCCESS;
-}
-
-/**
- * prefix() - skip over prefix
- *
- * Skip over a prefix string.
- *
- * @str: string with prefix
- * @prefix:prefix string
- * Return: string without prefix, or NULL if prefix not found
- */
-static const char *prefix(const char *str, const char *prefix)
-{
- size_t n = strlen(prefix);
- if (!strncmp(prefix, str, n))
- return str + n;
- return NULL;
-}
-
-/**
- * parse_attr() - decode attributes part of variable value
- *
- * Convert the string encoded attributes of a UEFI variable to a bit mask.
- * TODO: Several attributes are not supported.
- *
- * @str: value of U-Boot variable
- * @attrp: pointer to UEFI attributes
- * Return: pointer to remainder of U-Boot variable value
- */
-static const char *parse_attr(const char *str, u32 *attrp)
-{
- u32 attr = 0;
- char sep = '{';
-
- if (*str != '{') {
- *attrp = EFI_VARIABLE_BOOTSERVICE_ACCESS;
- return str;
- }
-
- while (*str == sep) {
- const char *s;
-
- str++;
-
- if ((s = prefix(str, "ro"))) {
- attr |= READ_ONLY;
- } else if ((s = prefix(str, "nv"))) {
- attr |= EFI_VARIABLE_NON_VOLATILE;
- } else if ((s = prefix(str, "boot"))) {
- attr |= EFI_VARIABLE_BOOTSERVICE_ACCESS;
- } else if ((s = prefix(str, "run"))) {
- attr |= EFI_VARIABLE_RUNTIME_ACCESS;
- } else {
- printf("invalid attribute: %s\n", str);
- break;
- }
-
- str = s;
- sep = ',';
- }
-
- str++;
-
- *attrp = attr;
-
- return str;
-}
-
/**
* efi_get_variable() - retrieve value of a UEFI variable
*
@@ -167,11 +30,18 @@ efi_status_t EFIAPI efi_get_variable(u16 *variable_name,
const efi_guid_t *vendor, u32 *attributes,
efi_uintn_t *data_size, void *data)
{
+ efi_status_t ret;
+
[PATCH 09/16] efi_loader: imply FAT, FAT_WRITE
The UEFI spec requires support for the FAT file system. Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 9890144d41..e10ca05549 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -15,6 +15,8 @@ config EFI_LOADER select HAVE_BLOCK_DEVICE select REGEX imply CFB_CONSOLE_ANSI + imply FAT + imply FAT_WRITE imply USB_KEYBOARD_FN_KEYS imply VIDEO_ANSI help -- 2.25.1
[PATCH 02/16] efi_loader: only reserve memory if fdt node enabled
Sub-nodes of /reserved-memory may be disabled. In this case we should not
reserve memory in the memory map.
Reported-by: Patrick DELAUNAY
Fixes: fef907b2e440 ("efi_loader: create reservations after
ft_board_setup")
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Atish Patra
---
cmd/bootefi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 3bbe2d6a1a..aaed575505 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -199,7 +199,8 @@ static void efi_carve_out_dt_rsv(void *fdt)
* The /reserved-memory node may have children with
* a size instead of a reg property.
*/
- if (addr != FDT_ADDR_T_NONE)
+ if (addr != FDT_ADDR_T_NONE &&
+ fdtdec_get_is_enabled(fdt, subnode))
efi_reserve_memory(addr, size);
subnode = fdt_next_subnode(fdt, subnode);
}
--
2.25.1
[PATCH 13/16] efi_loader: memory buffer for variables
Saving UEFI variable as encoded U-Boot environment variables does not allow
support at runtime.
Provide functions to manage a memory buffer with UEFI variables.
Signed-off-by: Heinrich Schuchardt
---
include/efi_variable.h | 16 ++
lib/efi_loader/Makefile| 1 +
lib/efi_loader/efi_variables_mem.c | 317 +
3 files changed, 334 insertions(+)
create mode 100644 lib/efi_loader/efi_variables_mem.c
diff --git a/include/efi_variable.h b/include/efi_variable.h
index fb8294fc2e..037d268085 100644
--- a/include/efi_variable.h
+++ b/include/efi_variable.h
@@ -33,4 +33,20 @@ efi_status_t efi_var_to_file(void);
efi_status_t efi_var_from_file(void);
+void efi_var_mem_memcpy(void *dest, const void *src, size_t n);
+
+efi_status_t efi_var_mem_init(void);
+
+struct efi_var_entry *efi_var_mem_find(const efi_guid_t *guid, const u16 *name,
+ struct efi_var_entry **next);
+
+void efi_var_mem_del(struct efi_var_entry *var);
+
+efi_status_t efi_var_mem_ins(u16 *variable_name,
+const efi_guid_t *vendor, u32 attributes,
+const efi_uintn_t size1, const void *data1,
+const efi_uintn_t size2, const void *data2);
+
+u64 efi_var_mem_free(void);
+
#endif
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 621a767ab3..14b210e189 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -36,6 +36,7 @@ obj-y += efi_setup.o
obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += efi_unicode_collation.o
obj-y += efi_variable.o
obj-y += efi_variables_file.o
+obj-y += efi_variables_mem.o
obj-y += efi_watchdog.o
obj-$(CONFIG_LCD) += efi_gop.o
obj-$(CONFIG_DM_VIDEO) += efi_gop.o
diff --git a/lib/efi_loader/efi_variables_mem.c
b/lib/efi_loader/efi_variables_mem.c
new file mode 100644
index 00..f70cc65f8b
--- /dev/null
+++ b/lib/efi_loader/efi_variables_mem.c
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * File interface for UEFI variables
+ *
+ * Copyright (c) 2020, Heinrich Schuchardt
+ */
+
+#include
+#include
+#include
+#include
+
+static struct efi_var_file __efi_runtime_data *efi_var_buf;
+static struct efi_var_entry __efi_runtime_data *efi_current_var;
+
+/**
+ * memcpy() - copy memory area
+ *
+ * At runtime memcpy() is not available.
+ *
+ * @dest: destination buffer
+ * @src: source buffer
+ * @n: number of bytes to copy
+ * Return: pointer to destination buffer
+ */
+void __efi_runtime efi_var_mem_memcpy(void *dest, const void *src, size_t n)
+{
+ u8 *d = dest;
+ const u8 *s = src;
+
+ for (; n; --n)
+ *d++ = *s++;
+}
+
+/**
+ * efi_var_mem_compare() - compare GUID and name with a variable
+ *
+ * @var: variable to compare
+ * @guid: GUID to compare
+ * @name: variable name to compare
+ * @next: pointer to next variable
+ * Return: true if match
+ */
+static bool __efi_runtime
+efi_var_mem_compare(struct efi_var_entry *var, const efi_guid_t *guid,
+ const u16 *name, struct efi_var_entry **next)
+{
+ int i;
+ u8 *guid1, *guid2;
+ const u16 *data, *var_name;
+ bool match = true;
+
+ for (guid1 = (u8 *)&var->guid, guid2 = (u8 *)guid, i = 0;
+i < sizeof(efi_guid_t) && match; ++i)
+ match = (guid1[i] == guid2[i]);
+
+ for (data = var->name, var_name = name;; ++data, ++var_name) {
+ if (match)
+ match = (*data == *var_name);
+ if (!*data)
+ break;
+ }
+
+ ++data;
+
+ if (next)
+ *next = (struct efi_var_entry *)
+ ALIGN((uintptr_t)data + var->length, 8);
+
+ return match;
+}
+
+/**
+ * efi_var_mem_find() - find a variable in the list
+ *
+ * @guid: GUID of the variable
+ * @name: name of the variable
+ * @next: on exit pointer to the next variable after the found one
+ * Return: found variable
+ */
+struct efi_var_entry __efi_runtime
+*efi_var_mem_find(const efi_guid_t *guid, const u16 *name,
+ struct efi_var_entry **next)
+{
+ struct efi_var_entry *var, *last;
+
+ last = (struct efi_var_entry *)
+ ((uintptr_t)efi_var_buf + efi_var_buf->length);
+
+ if (!*name) {
+ if (next) {
+ *next = efi_var_buf->var;
+ if (*next >= last)
+ *next = NULL;
+ }
+ return NULL;
+ }
+ if (efi_current_var &&
+ efi_var_mem_compare(efi_current_var, guid, name, next)) {
+ if (next && *next >= last)
+ *next = NULL;
+ return efi_current_var;
+ }
+
+ var = efi_var_buf->var;
+ if (var < last) {
+ for (; var;) {
+ struct efi_var_entry *pos;
+
[PATCH 12/16] efi_loader: optional pointer for ConvertPointer
If the EFI_OPTIONAL_PTR is set in DebugDisposition, a NULL pointer does not
constitute an invalid parameter.
Signed-off-by: Heinrich Schuchardt
---
include/efi_api.h| 2 ++
lib/efi_loader/efi_runtime.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/include/efi_api.h b/include/efi_api.h
index 1c40ffc4f5..c56703fc5e 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -250,6 +250,8 @@ struct efi_rt_properties_table {
u32 runtime_services_supported;
};
+#define EFI_OPTIONAL_PTR 0x0001
+
struct efi_runtime_services {
struct efi_table_hdr hdr;
efi_status_t (EFIAPI *get_time)(struct efi_time *time,
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 67fa693e41..664a0422e2 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -511,6 +511,12 @@ efi_convert_pointer(efi_uintn_t debug_disposition, void
**address)
ret = EFI_INVALID_PARAMETER;
goto out;
}
+ if (!*address) {
+ if (debug_disposition & EFI_OPTIONAL_PTR)
+ return EFI_SUCCESS;
+ else
+ return EFI_INVALID_PARAMETER;
+ }
for (i = 0; i < efi_descriptor_count; i++) {
struct efi_mem_desc *map = (void *)efi_virtmap +
--
2.25.1
[PATCH 05/16] efi_loader: identify EFI system partition
For capsule updates we need to identify the EFI system partition.
Signed-off-by: Heinrich Schuchardt
---
include/efi_loader.h | 7 +++
lib/efi_loader/efi_disk.c | 20
2 files changed, 27 insertions(+)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index b1d2feab61..5890871470 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -45,6 +45,13 @@ static inline void *guidcpy(void *dst, const void *src)
/* Root node */
extern efi_handle_t efi_root;
+/* EFI system partition */
+extern struct efi_system_partition {
+ enum if_type if_type;
+ int devnum;
+ u8 part;
+} efi_system_partition;
+
int __efi_entry_check(void);
int __efi_exit_check(void);
const char *__efi_nesting(void);
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index fc0682bc48..2f752a5e99 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -13,6 +13,8 @@
#include
#include
+struct efi_system_partition efi_system_partition;
+
const efi_guid_t efi_block_io_guid = EFI_BLOCK_IO_PROTOCOL_GUID;
/**
@@ -372,6 +374,24 @@ static efi_status_t efi_disk_add_dev(
diskobj->ops.media = &diskobj->media;
if (disk)
*disk = diskobj;
+
+ /* Store first EFI system partition */
+ if (part && !efi_system_partition.if_type) {
+ int r;
+ disk_partition_t info;
+
+ r = part_get_info(desc, part, &info);
+ if (r)
+ return EFI_DEVICE_ERROR;
+ if (info.bootable & PART_EFI_SYSTEM_PARTITION) {
+ efi_system_partition.if_type = desc->if_type;
+ efi_system_partition.devnum = desc->devnum;
+ efi_system_partition.part = part;
+ EFI_PRINT("EFI system partition: %s %d:%d\n",
+ blk_get_if_type_name(desc->if_type),
+ desc->devnum, part);
+ }
+ }
return EFI_SUCCESS;
}
--
2.25.1
[PATCH 07/16] efi_loader: export initialization state
Export the UEFI sub-system initialization state. This will allow to treat
the setting of UEFI variables during and after initialization differently.
Signed-off-by: Heinrich Schuchardt
---
include/efi_loader.h | 3 +++
lib/efi_loader/efi_setup.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 5890871470..510f39fe9e 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -45,6 +45,9 @@ static inline void *guidcpy(void *dst, const void *src)
/* Root node */
extern efi_handle_t efi_root;
+/* Set to EFI_SUCCESS when initialized */
+extern efi_status_t efi_obj_list_initialized;
+
/* EFI system partition */
extern struct efi_system_partition {
enum if_type if_type;
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index d1884e4dae..f6b17b662c 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -11,7 +11,7 @@
#define OBJ_LIST_NOT_INITIALIZED 1
-static efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
+efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
/*
* Allow unaligned memory access.
--
2.25.1
[PATCH 11/16] efi_loader: export efi_convert_pointer()
We need ConvertPointer() to adjust pointers when implementing runtime
services within U-Boot.
After ExitBootServices() gd is not available anymore. So we should not use
EFI_ENTRY() and EFI_EXIT().
Signed-off-by: Heinrich Schuchardt
---
include/efi_loader.h | 3 +++
lib/efi_loader/efi_runtime.c | 8 +++-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 510f39fe9e..d17a3c5ae1 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -374,6 +374,9 @@ efi_status_t efi_root_node_register(void);
efi_status_t efi_initialize_system_table(void);
/* efi_runtime_detach() - detach unimplemented runtime functions */
void efi_runtime_detach(void);
+/* efi_convert_pointer() - convert pointer to virtual address */
+efi_status_t EFIAPI efi_convert_pointer(efi_uintn_t debug_disposition,
+ void **address);
/* Called by bootefi to make console interface available */
efi_status_t efi_console_register(void);
/* Called by bootefi to make all disk storage accessible as EFI objects */
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 6a25acbbcd..67fa693e41 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -495,15 +495,13 @@ static __efi_runtime efi_status_t EFIAPI
efi_convert_pointer_runtime(
* @address: pointer to be converted
* Return: status code
*/
-static __efi_runtime efi_status_t EFIAPI efi_convert_pointer(
- efi_uintn_t debug_disposition, void **address)
+__efi_runtime efi_status_t EFIAPI
+efi_convert_pointer(efi_uintn_t debug_disposition, void **address)
{
efi_physical_addr_t addr = (uintptr_t)*address;
efi_uintn_t i;
efi_status_t ret = EFI_NOT_FOUND;
- EFI_ENTRY("%zu %p", debug_disposition, address);
-
if (!efi_virtmap) {
ret = EFI_UNSUPPORTED;
goto out;
@@ -531,7 +529,7 @@ static __efi_runtime efi_status_t EFIAPI
efi_convert_pointer(
}
out:
- return EFI_EXIT(ret);
+ return ret;
}
static __efi_runtime void efi_relocate_runtime_table(ulong offset)
--
2.25.1
[PATCH 08/16] efi_loader: change setup sequence
If we want to restore variables from disk, we need to initialize block devices before variables. Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_setup.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index f6b17b662c..1e3e474835 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -102,6 +102,11 @@ efi_status_t efi_init_obj_list(void) /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */ switch_to_non_secure_mode(); +#ifdef CONFIG_PARTITIONS + ret = efi_disk_register(); + if (ret != EFI_SUCCESS) + goto out; +#endif /* Initialize variable services */ ret = efi_init_variables(); if (ret != EFI_SUCCESS) @@ -145,11 +150,6 @@ efi_status_t efi_init_obj_list(void) ret = efi_console_register(); if (ret != EFI_SUCCESS) goto out; -#ifdef CONFIG_PARTITIONS - ret = efi_disk_register(); - if (ret != EFI_SUCCESS) - goto out; -#endif #if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO) ret = efi_gop_register(); if (ret != EFI_SUCCESS) -- 2.25.1
[PATCH 10/16] efi_loader: UEFI variable persistence
Persist non-volatile UEFI variables in a file on the EFI system partition.
The file is written:
* whenever a non-volatile UEFI variable is changed after initialization
of the UEFI sub-system.
* upon ExitBootServices()
The file is read during the UEFI sub-system initialization to restore
non-volatile UEFI variables.
Signed-off-by: Heinrich Schuchardt
---
include/efi_variable.h | 36 +
lib/efi_loader/Kconfig | 8 +
lib/efi_loader/Makefile | 1 +
lib/efi_loader/efi_variable.c | 12 +-
lib/efi_loader/efi_variables_file.c | 235
5 files changed, 291 insertions(+), 1 deletion(-)
create mode 100644 include/efi_variable.h
create mode 100644 lib/efi_loader/efi_variables_file.c
diff --git a/include/efi_variable.h b/include/efi_variable.h
new file mode 100644
index 00..fb8294fc2e
--- /dev/null
+++ b/include/efi_variable.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * File interface for UEFI variables
+ *
+ * Copyright (c) 2020, Heinrich Schuchardt
+ */
+
+#ifndef _EFI_VARIABLE_H
+#define _EFI_VARIABLE_H
+
+#define EFI_VAR_FILE_NAME "ubootefi.var"
+
+#define EFI_VAR_BUF_SIZE 0x4000
+
+#define EFI_VAR_FILE_MAGIC 0x7261566966456255 /* UbEfiVar */
+
+struct efi_var_entry {
+ u32 length;
+ u32 attr;
+ efi_guid_t guid;
+ u16 name[0];
+};
+
+struct efi_var_file {
+ u64 reserved; /* May be overwritten by memory probing */
+ u64 magic;
+ u32 length;
+ u32 crc32;
+ struct efi_var_entry var[0];
+};
+
+efi_status_t efi_var_to_file(void);
+
+efi_status_t efi_var_from_file(void);
+
+#endif
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index e10ca05549..41705fc252 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -27,6 +27,14 @@ config EFI_LOADER
if EFI_LOADER
+config EFI_VARIABLE_FILE_STORE
+ bool "Store non-volatile UEFI variables as file"
+ depends on FAT_WRITE
+ default y
+ help
+ Select tis option if you want non-volatile UEFI variables to be stored
+ as file /ubootefi.var on the EFI system partition.
+
config EFI_GET_TIME
bool "GetTime() runtime service"
depends on DM_RTC
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 9b3b704473..621a767ab3 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -35,6 +35,7 @@ obj-y += efi_runtime.o
obj-y += efi_setup.o
obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += efi_unicode_collation.o
obj-y += efi_variable.o
+obj-y += efi_variables_file.o
obj-y += efi_watchdog.o
obj-$(CONFIG_LCD) += efi_gop.o
obj-$(CONFIG_DM_VIDEO) += efi_gop.o
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index d99ad6ddae..952a0a0db7 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
#include
@@ -604,6 +605,11 @@ efi_status_t efi_set_variable_int(u16 *variable_name,
if (env_set(native_name, val))
ret = EFI_DEVICE_ERROR;
+ /* Write non-volatile EFI variables to file */
+ if (attributes && EFI_VARIABLE_NON_VOLATILE &&
+ ret == EFI_SUCCESS && efi_obj_list_initialized == EFI_SUCCESS)
+ efi_var_to_file();
+
out:
free(native_name);
free(val);
@@ -694,6 +700,10 @@ efi_set_variable_runtime(u16 *variable_name, const
efi_guid_t *vendor,
*/
void efi_variables_boot_exit_notify(void)
{
+ /* Write non-volatile EFI variables to file */
+ efi_var_to_file();
+
+ /* Switch variable services functions to runtime version */
efi_runtime_services.get_variable = efi_get_variable_runtime;
efi_runtime_services.get_next_variable_name =
efi_get_next_variable_name_runtime;
@@ -708,5 +718,5 @@ void efi_variables_boot_exit_notify(void)
*/
efi_status_t efi_init_variables(void)
{
- return EFI_SUCCESS;
+ return efi_var_from_file();
}
diff --git a/lib/efi_loader/efi_variables_file.c
b/lib/efi_loader/efi_variables_file.c
new file mode 100644
index 00..4a918d3fde
--- /dev/null
+++ b/lib/efi_loader/efi_variables_file.c
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * File interface for UEFI variables
+ *
+ * Copyright (c) 2020, Heinrich Schuchardt
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PART_STR_LEN 10
+
+/**
+ * efi_set_blk_dev_to_system_partition() - select EFI system partition
+ *
+ * Set the EFI system partition as current block device.
+ *
+ * Return: status code
+ */
+static efi_status_t __maybe_unused efi_set_blk_dev_to_system_partition(void)
+{
+ char part_str[PART_STR_LEN];
+ int r;
+
+ if (!efi_system_partition.if_type)
+ return EFI_NOT_FOUND;
+ snprintf(part_str, PART_STR_LEN, "%u:%u",
+efi_system_part
[PATCH 00/16] efi_loader: non-volatile and runtime variables
Up to UEFI variable where stored in U-Boot environment variables. Saving UEFI variables was not possible without saving the U-Boot environment variables. With this patch series file ubootefi.var in the EFI system partition is used for saving UEFI variables. Furthermore the UEFI variables are exposed at runtime and are writable at runtime. The missing piece is transferring the variable changed at runtime back to the firmware. I will evaluate the following options: * using a fixed memory address: we could read the memory area after a reboot * using a systemd service which is called before the system goes down Many of the CCs are due to the changes in disk/part_efi.c. Here the logic to detect the EFI system partition is introduced (patch 04/16). Heinrich Schuchardt (16): cmd: efidebug: fix int to pointer cast efi_loader: only reserve memory if fdt node enabled efi_loader: eliminate EFI_CALL() for variable access part: detect EFI system partition efi_loader: identify EFI system partition efi_loader: keep attributes in efi_set_variable_int() efi_loader: export initialization state efi_loader: change setup sequence efi_loader: imply FAT, FAT_WRITE efi_loader: UEFI variable persistence efi_loader: export efi_convert_pointer() efi_loader: optional pointer for ConvertPointer efi_loader: memory buffer for variables efi_loader: use memory based variable storage efi_loader: enable UEFI variables at runtime efi_selftest: adjust runtime test for variables cmd/bootefi.c | 3 +- cmd/efidebug.c| 71 +- cmd/nvedit_efi.c | 18 +- disk/part_dos.c | 10 +- disk/part_efi.c | 12 +- include/efi_api.h | 2 + include/efi_loader.h | 22 + include/efi_variable.h| 52 ++ include/part.h| 11 +- lib/efi_loader/Kconfig| 10 + lib/efi_loader/Makefile | 2 + lib/efi_loader/efi_bootmgr.c | 20 +- lib/efi_loader/efi_disk.c | 20 + lib/efi_loader/efi_runtime.c | 20 +- lib/efi_loader/efi_setup.c| 54 +- lib/efi_loader/efi_variable.c | 635 ++ lib/efi_loader/efi_variables_file.c | 235 +++ lib/efi_loader/efi_variables_mem.c| 324 + .../efi_selftest_variables_runtime.c | 47 +- 19 files changed, 1037 insertions(+), 531 deletions(-) create mode 100644 include/efi_variable.h create mode 100644 lib/efi_loader/efi_variables_file.c create mode 100644 lib/efi_loader/efi_variables_mem.c -- 2.25.1
[PATCH 01/16] cmd: efidebug: fix int to pointer cast
On 32 bit systems fix
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
Fixes: a415d61eac26 ("cmd: map addresses to sysmem in efidebug memmap")
Signed-off-by: Heinrich Schuchardt
---
cmd/efidebug.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index bb7c13d6a1..c1bb76477a 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -489,10 +489,12 @@ static int do_efi_show_memmap(cmd_tbl_t *cmdtp, int flag,
printf("%-16s %.*llx-%.*llx", type,
EFI_PHYS_ADDR_WIDTH,
- (u64)map_to_sysmem((void *)map->physical_start),
+ (u64)map_to_sysmem((void *)(uintptr_t)
+ map->physical_start),
EFI_PHYS_ADDR_WIDTH,
- (u64)map_to_sysmem((void *)map->physical_start +
- map->num_pages * EFI_PAGE_SIZE));
+ (u64)map_to_sysmem((void *)(uintptr_t)
+ (map->physical_start +
+ map->num_pages * EFI_PAGE_SIZE)));
print_memory_attributes(map->attribute);
putc('\n');
--
2.25.1
[PATCH 04/16] part: detect EFI system partition
Up to now for MBR and GPT partitions the info field 'bootable' was set to 1
if either the partition was an EFI system partition or the bootable flag
was set.
Turn info field 'bootable' into a bit mask with separate bits for bootable
and EFI system partition.
This will allow us to identify the EFI system partition in the UEFI
sub-system.
Signed-off-by: Heinrich Schuchardt
---
disk/part_dos.c | 10 --
disk/part_efi.c | 12
include/part.h | 11 ++-
3 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 83ff40d310..0ec7f1628e 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -45,9 +45,15 @@ static inline int is_extended(int part_type)
part_type == 0x85);
}
-static inline int is_bootable(dos_partition_t *p)
+static int is_bootable(dos_partition_t *p)
{
- return (p->sys_ind == 0xef) || (p->boot_ind == 0x80);
+ int ret = 0;
+
+ if (p->sys_ind == 0xef)
+ ret |= PART_EFI_SYSTEM_PARTITION;
+ if (p->boot_ind == 0x80)
+ ret |= PART_BOOTABLE;
+ return ret;
}
static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector,
diff --git a/disk/part_efi.c b/disk/part_efi.c
index b2e157d9c1..19f1f43f4e 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -71,11 +71,15 @@ static char *print_efiname(gpt_entry *pte)
static const efi_guid_t system_guid = PARTITION_SYSTEM_GUID;
-static inline int is_bootable(gpt_entry *p)
+static int is_bootable(gpt_entry *p)
{
- return p->attributes.fields.legacy_bios_bootable ||
- !memcmp(&(p->partition_type_guid), &system_guid,
- sizeof(efi_guid_t));
+ int ret = 0;
+
+ if (!memcmp(&p->partition_type_guid, &system_guid, sizeof(efi_guid_t)))
+ ret |= PART_EFI_SYSTEM_PARTITION;
+ if (p->attributes.fields.legacy_bios_bootable)
+ ret |= PART_BOOTABLE;
+ return ret;
}
static int validate_gpt_header(gpt_header *gpt_h, lbaint_t lba,
diff --git a/include/part.h b/include/part.h
index 0b5cf3d5e8..a63d1d0cda 100644
--- a/include/part.h
+++ b/include/part.h
@@ -51,13 +51,22 @@ struct block_drvr {
#define PART_TYPE_LEN 32
#define MAX_SEARCH_PARTITIONS 64
+#define PART_BOOTABLE 1
+#define PART_EFI_SYSTEM_PARTITION 2
+
typedef struct disk_partition {
lbaint_tstart; /* # of first block in partition*/
lbaint_tsize; /* number of blocks in partition*/
ulong blksz; /* block size in bytes */
uchar name[PART_NAME_LEN];/* partition name
*/
uchar type[PART_TYPE_LEN];/* string type description
*/
- int bootable; /* Active/Bootable flag is set */
+ /*
+* The bootable is a bitmask with the following fields:
+*
+* PART_BOOTABLEthe MBR bootable flag is set
+* PART_EFI_SYSTEM_PARTITIONthe partition is an EFI system partition
+*/
+ int bootable;
#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
charuuid[UUID_STR_LEN + 1]; /* filesystem UUID as string, if exists
*/
#endif
--
2.25.1
[PATCH 06/16] efi_loader: keep attributes in efi_set_variable_int()
Do not change the value of parameter attributes in function
efi_set_variable_int(). This allows to use it later.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/efi_variable.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 4fae1fa4c7..d99ad6ddae 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -573,8 +573,8 @@ efi_status_t efi_set_variable_int(u16 *variable_name,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS);
s += sprintf(s, "{");
- while (attributes) {
- u32 attr = 1 << (ffs(attributes) - 1);
+ for (u32 attr_rem = attributes; attr_rem;) {
+ u32 attr = 1 << (ffs(attr_rem) - 1);
if (attr == EFI_VARIABLE_NON_VOLATILE)
s += sprintf(s, "nv");
@@ -583,8 +583,8 @@ efi_status_t efi_set_variable_int(u16 *variable_name,
else if (attr == EFI_VARIABLE_RUNTIME_ACCESS)
s += sprintf(s, "run");
- attributes &= ~attr;
- if (attributes)
+ attr_rem &= ~attr;
+ if (attr_rem)
s += sprintf(s, ",");
}
s += sprintf(s, "}");
--
2.25.1
Re: [PATCH 1/4] travis: Remove qemu-riscv64 testing
On Thu, Mar 26, 2020 at 6:06 PM Bin Meng wrote: > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > available on the internet, and with travis-ci we don't build GRUB > images like we do for azure and gitlab. There are RPM packages for GRUB in OpenSUSE and Fedora. https://build.opensuse.org/package/binaries/openSUSE:Factory:RISCV/grub2/standard http://fedora.riscv.rocks/koji/buildinfo?buildID=133151 I have not tried them on QEMU or Unleashed yet. We should be able to boot with GRUB2 and EFI stubs to the kernel soonish. > > Remove qemu-riscv64 testing temporarily. > > Signed-off-by: Bin Meng > --- > > .travis.yml | 7 --- > 1 file changed, 7 deletions(-) > > diff --git a/.travis.yml b/.travis.yml > index c59bd77..55b94cf 100644 > --- a/.travis.yml > +++ b/.travis.yml > @@ -481,13 +481,6 @@ matrix: >QEMU_TARGET="ppc-softmmu" >BUILDMAN="^qemu-ppce500$" >TOOLCHAIN="powerpc" > -- name: "test/py qemu-riscv64" > - env: > -- TEST_PY_BD="qemu-riscv64" > - TEST_PY_TEST_SPEC="not sleep" > - QEMU_TARGET="riscv64-softmmu" > - BUILDMAN="^qemu-riscv64$" > - TOOLCHAIN="riscv" > - name: "test/py qemu-x86" >env: > - TEST_PY_BD="qemu-x86" > -- > 2.7.4 >
[PATCH 5/6] rockchip: dts: rk3328: Sync device tree files from Linux
From: Chen-Yu Tsai
This syncs rk3328 device tree files from the Linux kernel next-20200324.
The last commit to touch these files is:
b2411befed60 ("arm64: dts: add bus to rockchip amba nodenames")
Additional changes not yet in the Linux kernel include:
arm64: dts: rockchip: rk3328: drop #address-cells, #size-cells from grf node
arm64: dts: rockchip: rk3328: drop non-existent gmac2phy pinmux options
arm64: dts: rockchip: rk3328: Replace RK805 PMIC node name with "pmic"
Changes include:
- conversion of raw pin numbers to macros
- removal of deprecated RK_FUNC_* macros
- update of device tree binding headers
- new devices
- device tree cleanups
- gmac2phy disabled in -u-boot.dtsi as it is not supported in U-boot
Signed-off-by: Chen-Yu Tsai
---
arch/arm/dts/rk3328-evb-u-boot.dtsi |5 +
arch/arm/dts/rk3328-evb.dts | 196 ++--
arch/arm/dts/rk3328-rock64.dts | 132 ++-
arch/arm/dts/rk3328.dtsi| 1420 +--
4 files changed, 1164 insertions(+), 589 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 8ba53cf8f44b..4bfa0c2330ba 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -40,6 +40,11 @@
status = "okay";
};
+&gmac2phy {
+ /* Integrated PHY unsupported by U-boot */
+ status = "broken";
+};
+
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 97bef37cf610..6abc6f4a86cf 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
@@ -11,24 +11,51 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
chosen {
- stdout-path = &uart2;
+ stdout-path = "serial2:150n8";
};
- vcc3v3_sdmmc: sdmmc-pwren {
+ dc_12v: dc-12v {
compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc_io>;
};
- vcc5v0_otg: vcc5v0-otg-drv {
+ vcc_sys: vcc-sys {
compatible = "regulator-fixed";
- enable-active-high;
- regulator-name = "vcc5v0_otg";
- gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
+ vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
@@ -39,80 +66,60 @@
};
};
-&saradc {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- disable-wp;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>,
<&sdmmc0_bus4>;
- status = "okay";
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
- supports-emmc;
- disable-wp;
non-removable;
- num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
-&usb_host0_ehci {
- status = "okay";
-};
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clo
[PATCH 2/6] rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi
From: Chen-Yu Tsai
The device tree file for rk3328-evb in the Linux kernel does not have
gmac2io enabled. Instead, gmac2phy is enabled, but that is not supported
in U-boot.
Move the gmac2io related nodes to rk3328-evb-u-boot.dtsi to preserve the
current functionality. When the device tree files are synced, gmac2phy
should be marked as "broken" in -u-boot.dtsi files.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/dts/rk3328-evb-u-boot.dtsi | 23 +++
arch/arm/dts/rk3328-evb.dts | 23 ---
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 5679897279aa..8ba53cf8f44b 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -7,6 +7,13 @@
#include "rk3328-sdram-ddr3-666.dtsi"
/{
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
compatible = "regulator-fixed";
enable-active-high;
@@ -17,6 +24,22 @@
};
};
+&gmac2io {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index e9bc849f8c23..97bef37cf610 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -14,13 +14,6 @@
stdout-path = &uart2;
};
- gmac_clkin: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <12500>;
- clock-output-names = "gmac_clkin";
- #clock-cells = <0>;
- };
-
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -78,22 +71,6 @@
status = "okay";
};
-&gmac2io {
- phy-supply = <&vcc_phy>;
- phy-mode = "rgmii";
- clock_in_out = "input";
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 1 5>;
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_pins>;
- tx_delay = <0x26>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
&usb_host0_ehci {
status = "okay";
};
--
2.25.1
[PATCH 0/6] rockchip: rk3328: sync dts and add ROC-RK3328-CC board
From: Chen-Yu Tsai
Hi everyone,
This series adds proper support for Firefly / Libre Computer ROC-RK3328-CC
single board computer.
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
card size development board based on the Rockchip RK3328 SoC, with:
- 1/2/4 GB DDR4 DRAM
- eMMC connector for optional module
- micro SD card slot
- 1 x USB 3.0 host port
- 2 x USB 2.0 host port
- 1 x USB 2.0 OTG port
- HDMI video output
- TRRS connector with audio and composite video output
- gigabit Ethernet
- consumer IR receiver
- debug UART pins
Originally I started with Loic's patches, and syncing the device tree
files from Linux. That didn't get very far, with SPL failing to detect
the SD card. Examining the schematics and internal state of GRF and
GPIOs, I realized that the logic for the SD card power enable switch
is opposite that of what the SD card controller's SDMMC0_PWREN pin
would use. Instead, directly using the GPIO is required.
Thus this series creates a special target for this board to handle
muxing this specific pin to GPIO state. The GPIO is left in input mode,
letting the external pull-down work its magic.
Along the way, there are some clean-ups of existing dts files, moving
U-boot only features to -u-boot.dtsi files, and then a wholesale sync
from Linux. Only boards already existing in U-boot are synced. DT
binding header files are synced separately as there is already one
patch floating around. The DT sync also includes clean-up changes only
recently posted, and likely won't make it in for at least a few weeks.
Please have a look, and test if possible. I cc-ed a couple people that
showed interest in this board on mailing lists recently.
Regards
ChenYu
Chen-Yu Tsai (6):
rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi
rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi
dt-bindings: clock: rk3328: sync from upstream Linux kernel
dt-bindings: power: rk3328-power: sync from upstream Linux kernel
rockchip: dts: rk3328: Sync device tree files from Linux
rockchip: rk3328: Add support for ROC-RK3328-CC board
arch/arm/dts/Makefile |1 +
arch/arm/dts/rk3328-evb-u-boot.dtsi | 39 +
arch/arm/dts/rk3328-evb.dts | 220 +--
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 17 +
.../{rk3328-rock64.dts => rk3328-roc-cc.dts} | 135 +-
arch/arm/dts/rk3328-rock64.dts| 132 +-
arch/arm/dts/rk3328.dtsi | 1420 +++--
arch/arm/mach-rockchip/rk3328/Kconfig |8 +
board/firefly/roc-cc-rk3328/Kconfig | 24 +
board/firefly/roc-cc-rk3328/MAINTAINERS |7 +
board/firefly/roc-cc-rk3328/Makefile |1 +
board/firefly/roc-cc-rk3328/board.c | 38 +
configs/roc-cc-rk3328_defconfig | 97 ++
doc/README.rockchip |4 +-
include/dt-bindings/clock/rk3328-cru.h| 212 +--
include/dt-bindings/power/rk3328-power.h | 19 +
16 files changed, 1622 insertions(+), 752 deletions(-)
create mode 100644 arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
copy arch/arm/dts/{rk3328-rock64.dts => rk3328-roc-cc.dts} (68%)
create mode 100644 board/firefly/roc-cc-rk3328/Kconfig
create mode 100644 board/firefly/roc-cc-rk3328/MAINTAINERS
create mode 100644 board/firefly/roc-cc-rk3328/Makefile
create mode 100644 board/firefly/roc-cc-rk3328/board.c
create mode 100644 configs/roc-cc-rk3328_defconfig
create mode 100644 include/dt-bindings/power/rk3328-power.h
--
2.25.1
[PATCH 3/6] dt-bindings: clock: rk3328: sync from upstream Linux kernel
From: Chen-Yu Tsai
This syncs the rk3328 clock header file from Linux kernel next-20200324,
to support newer hardware blocks when syncing the device tree files.
The last non-merge commit to touch it was
0dc14b013f79 ("clk: rockchip: add clock id for watchdog pclk on rk3328")
Signed-off-by: Chen-Yu Tsai
---
include/dt-bindings/clock/rk3328-cru.h | 212 -
1 file changed, 106 insertions(+), 106 deletions(-)
diff --git a/include/dt-bindings/clock/rk3328-cru.h
b/include/dt-bindings/clock/rk3328-cru.h
index cde61ed8830b..555b4ff660ae 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -1,6 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Elaine
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
@@ -90,119 +91,118 @@
#define SCLK_MAC2IO_EXT102
/* dclk gates */
-#define DCLK_LCDC 180
-#define DCLK_HDMIPHY 181
-#define HDMIPHY182
-#define USB480M183
-#define DCLK_LCDC_SRC 184
+#define DCLK_LCDC 120
+#define DCLK_HDMIPHY 121
+#define HDMIPHY122
+#define USB480M123
+#define DCLK_LCDC_SRC 124
/* aclk gates */
-#define ACLK_AXISRAM 190
-#define ACLK_VOP_PRE 191
-#define ACLK_USB3OTG 192
-#define ACLK_RGA_PRE 193
-#define ACLK_DMAC 194
-#define ACLK_GPU 195
-#define ACLK_BUS_PRE 196
-#define ACLK_PERI_PRE 197
-#define ACLK_RKVDEC_PRE198
-#define ACLK_RKVDEC199
-#define ACLK_RKVENC200
-#define ACLK_VPU_PRE 201
-#define ACLK_VIO_PRE 202
-#define ACLK_VPU 203
-#define ACLK_VIO 204
-#define ACLK_VOP 205
-#define ACLK_GMAC 206
-#define ACLK_H265 207
-#define ACLK_H264 208
-#define ACLK_MAC2PHY 209
-#define ACLK_MAC2IO210
-#define ACLK_DCF 211
-#define ACLK_TSP 212
-#define ACLK_PERI 213
-#define ACLK_RGA 214
-#define ACLK_IEP 215
-#define ACLK_CIF 216
-#define ACLK_HDCP 217
+#define ACLK_AXISRAM 130
+#define ACLK_VOP_PRE 131
+#define ACLK_USB3OTG 132
+#define ACLK_RGA_PRE 133
+#define ACLK_DMAC 134
+#define ACLK_GPU 135
+#define ACLK_BUS_PRE 136
+#define ACLK_PERI_PRE 137
+#define ACLK_RKVDEC_PRE138
+#define ACLK_RKVDEC139
+#define ACLK_RKVENC140
+#define ACLK_VPU_PRE 141
+#define ACLK_VIO_PRE 142
+#define ACLK_VPU 143
+#define ACLK_VIO 144
+#define ACLK_VOP 145
+#define ACLK_GMAC 146
+#define ACLK_H265 147
+#define ACLK_H264 148
+#define ACLK_MAC2PHY 149
+#define ACLK_MAC2IO150
+#define ACLK_DCF 151
+#define ACLK_TSP 152
+#define ACLK_PERI 153
+#define ACLK_RGA 154
+#define ACLK_IEP 155
+#define ACLK_CIF 156
+#define ACLK_HDCP 157
/* pclk gates */
-#define PCLK_GPIO0 300
-#define PCLK_GPIO1 301
-#define PCLK_GPIO2 302
-#define PCLK_GPIO3 303
-#define PCLK_GRF 304
-#define PCLK_I2C0 305
-#define PCLK_I2C1 306
-#define PCLK_I2C2 307
-#define PCLK_I2C3 308
-#define PCLK_SPI 309
-#define PCLK_UART0 310
-#define PCLK_UART1 311
-#define PCLK_UART2 312
-#define PCLK_TSADC 313
-#define PCLK_PWM 314
-#define PCLK_TIMER 315
-#define PCLK_BUS_PRE 316
-#define PCLK_PERI_PRE 317
-#define PCLK_HDMI_CTRL 318
-#define PCLK_HDMI_PHY 319
-#define PCLK_GMAC 320
-#define PCLK_H265 321
-#define PCLK_MAC2PHY 322
-#define PCLK_MAC2IO323
-#define PCLK_USB3PHY_OTG 324
-#define PCLK_USB3PHY_PIPE 325
-#define PCLK_USB3_GRF 326
-#define PCLK_USB2_GRF 327
-#define PCLK_HDMIPHY 328
-#define PCLK_DDR 329
-#define PCLK_PERI 330
-#define PCLK_HDMI 331
-#define PCLK_HDCP 332
-#define PCLK_DCF 333
-#define PCLK_SARADC334
+#define PCLK_GPIO0 200
+#define PCLK_GPIO1 201
+#define PCLK_GPIO2 202
+#define PCLK_GPIO3 203
+#define PCLK_GRF 204
+#define PCLK_I2C0 205
+#define PCLK_I2C1
[PATCH 6/6] rockchip: rk3328: Add support for ROC-RK3328-CC board
From: Chen-Yu Tsai
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
card size development board based on the Rockchip RK3328 SoC, with:
- 1/2/4 GB DDR4 DRAM
- eMMC connector for optional module
- micro SD card slot
- 1 x USB 3.0 host port
- 2 x USB 2.0 host port
- 1 x USB 2.0 OTG port
- HDMI video output
- TRRS connector with audio and composite video output
- gigabit Ethernet
- consumer IR receiver
- debug UART pins
The ROC-RK3328-CC has the enable pin of the SD card power switch tied
to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is
muxed by default. SDMMC0_PWREN is an active high signal controlled by
the MMC controller, however the switch enable is active low, and
pulled low (enabled) by default to make things work on boot.
As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable
power to the card. The default GPIO state for the pin is pull-down and
input, which doesn't require extra configuration when paired with the
external pull-down and active low switch.
Thus we make a custom target for this board and do the muxing in its
spl_board_init() function.
The device tree file is synced from the Linux kernel next-20200324.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 17 ++
arch/arm/dts/rk3328-roc-cc.dts | 354
arch/arm/mach-rockchip/rk3328/Kconfig | 8 +
board/firefly/roc-cc-rk3328/Kconfig | 24 ++
board/firefly/roc-cc-rk3328/MAINTAINERS | 7 +
board/firefly/roc-cc-rk3328/Makefile| 1 +
board/firefly/roc-cc-rk3328/board.c | 38 +++
configs/roc-cc-rk3328_defconfig | 97 +++
doc/README.rockchip | 4 +-
10 files changed, 550 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3328-roc-cc.dts
create mode 100644 board/firefly/roc-cc-rk3328/Kconfig
create mode 100644 board/firefly/roc-cc-rk3328/MAINTAINERS
create mode 100644 board/firefly/roc-cc-rk3328/Makefile
create mode 100644 board/firefly/roc-cc-rk3328/board.c
create mode 100644 configs/roc-cc-rk3328_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c593b2c986a..023cb010532d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -104,6 +104,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
+ rk3328-roc-cc.dtb \
rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
new file mode 100644
index ..15b67f8bbdf4
--- /dev/null
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr4-666.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+};
+
+&usb_host0_xhci {
+ vbus-supply = <&vcc_host1_5v>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts
new file mode 100644
index ..8d553c92182a
--- /dev/null
+++ b/arch/arm/dts/rk3328-roc-cc.dts
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Firefly roc-rk3328-cc";
+ compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-boot-on;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
+ states = <180 0x1
+ 330 0x0>;
+ regulator-name = "vcc
[PATCH 1/6] rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi
From: Chen-Yu Tsai
USB 3.0 is only supported in U-boot, not in the Linux kernel where the
device tree files are ultimately synced from. While the xhci node was
moved, the external vbus regulator was not.
Move it as well.
Fixes: 2e91e2025c1b ("rockchip: rk3328: migrate u-boot node to -u-boot.dtsi")
Signed-off-by: Chen-Yu Tsai
---
arch/arm/dts/rk3328-evb-u-boot.dtsi | 11 +++
arch/arm/dts/rk3328-evb.dts | 9 -
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi
b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 4a827063c555..5679897279aa 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -6,6 +6,17 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr3-666.dtsi"
+/{
+ vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_host_xhci";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+};
+
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index a2ee838fcd6b..e9bc849f8c23 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -38,15 +38,6 @@
regulator-max-microvolt = <500>;
};
- vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
- compatible = "regulator-fixed";
- enable-active-high;
- regulator-name = "vcc5v0_host_xhci";
- gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- };
-
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
--
2.25.1
[PATCH 4/6] dt-bindings: power: rk3328-power: sync from upstream Linux kernel
From: Chen-Yu Tsai
This syncs the rk3328 power domain header file from Linux kernel
next-20200324, to support newer hardware blocks when syncing the
device tree files.
The last non-merge commit to touch it was
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
files with no license")
Signed-off-by: Chen-Yu Tsai
---
include/dt-bindings/power/rk3328-power.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/dt-bindings/power/rk3328-power.h
diff --git a/include/dt-bindings/power/rk3328-power.h
b/include/dt-bindings/power/rk3328-power.h
new file mode 100644
index ..02e3d7fc1cce
--- /dev/null
+++ b/include/dt-bindings/power/rk3328-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__
+#define __DT_BINDINGS_POWER_RK3328_POWER_H__
+
+/**
+ * RK3328 idle id Summary.
+ */
+#define RK3328_PD_CORE 0
+#define RK3328_PD_GPU 1
+#define RK3328_PD_BUS 2
+#define RK3328_PD_MSCH 3
+#define RK3328_PD_PERI 4
+#define RK3328_PD_VIDEO5
+#define RK3328_PD_HEVC 6
+#define RK3328_PD_SYS 7
+#define RK3328_PD_VPU 8
+#define RK3328_PD_VIO 9
+
+#endif
--
2.25.1
[PATCH 1/1] cmd: efidebug: fix int to pointer cast
On 32 bit systems fix
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
Fixes: a415d61eac26 ("cmd: map addresses to sysmem in efidebug memmap")
Signed-off-by: Heinrich Schuchardt
---
cmd/efidebug.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index f7744bdc55..f89c1d2db7 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -488,10 +488,12 @@ static int do_efi_show_memmap(cmd_tbl_t *cmdtp, int flag,
printf("%-16s %.*llx-%.*llx", type,
EFI_PHYS_ADDR_WIDTH,
- (u64)map_to_sysmem((void *)map->physical_start),
+ (u64)map_to_sysmem((void *)(uintptr_t)
+ map->physical_start),
EFI_PHYS_ADDR_WIDTH,
- (u64)map_to_sysmem((void *)map->physical_start +
- map->num_pages * EFI_PAGE_SIZE));
+ (u64)map_to_sysmem((void *)(uintptr_t)
+ (map->physical_start +
+ map->num_pages * EFI_PAGE_SIZE)));
print_memory_attributes(map->attribute);
putc('\n');
--
2.20.1
[Patch V4 1/3] mmc: sdhci: use phys2bus macro when dma address is accessed
Use phys2bus macro when dma address is accessed.
Some targets need to use pyhs2bus macro. (e.g, RPI4)
After applied it, SDMA mode can be used.
Signed-off-by: Jaehoon Chung
Reviewed-by: Peng Fan
Reviewed-by: Minkyu Kang
---
drivers/mmc/sdhci.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 520c9f9feb..2b7493fbac 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
@@ -150,7 +151,8 @@ static void sdhci_prepare_dma(struct sdhci_host *host,
struct mmc_data *data,
mmc_get_dma_dir(data));
if (host->flags & USE_SDMA) {
- sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
+ sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
+ SDHCI_DMA_ADDRESS);
} else if (host->flags & (USE_ADMA | USE_ADMA64)) {
sdhci_prepare_adma_table(host, data);
@@ -204,7 +206,7 @@ static int sdhci_transfer_data(struct sdhci_host *host,
struct mmc_data *data)
start_addr &=
~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
- sdhci_writel(host, start_addr,
+ sdhci_writel(host,
phys_to_bus((ulong)start_addr),
SDHCI_DMA_ADDRESS);
}
}
--
2.26.0
[Patch V4 3/3] configs: rpi_4 : enable SDHCI_SDMA config
Enable SDHCI_SDMA configuration. Signed-off-by: Jaehoon Chung Reviewed-by: Peng Fan Reviewed-by: Minkyu Kang --- configs/rpi_4_32b_defconfig | 1 + configs/rpi_4_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 72cda5d949..7189914606 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -25,6 +25,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 6d148dab07..454d28ea2b 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -25,6 +25,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y -- 2.26.0
[Patch V4 0/3] Support SDMA mode on RPI4 target - 32bit
RPI4's SDHCI controller is supported SDMA mode. (Checked on kernel side) But It doesn't use on u-boot side. Then it's too slow about read/write performance. This patchset is supported SDMA mode on RPI4 target(32/64bit). - Tested on RPI4 1GB/2GB/4GB target Read/write time about 8MB file Before - Read : 1.472 seconds - Write : 4.690 seconds After - Read : 0.359 seconds - Write : 0.574 seconds This patch is based on my RFC's patches.RPI4's SDHCI controller is supported SDMA mode. (Checked on kernel side) But It doesn't use on u-boot side. Then it's too slow about read/write performance. This patchset is supported SDMA mode on RPI4 target(32bit). - I didn't test on RPI4 64bit. Read/write time about 8MB file Before - Read : 1.472 seconds - Write : 4.690 seconds After - Read : 0.359 seconds - Write : 0.574 seconds Changelog on V4 - Enable SDMA in rpi4_defconfig for 64bit Changelog on V3 - Rebased on latest u-boot-mmc Changelog on V2 - Keep printf message instead of debug - Add Peng's Reviewed-by tag Jaehoon Chung (3): mmc: sdhci: use phys2bus macro when dma address is accessed mmc: sdhci: not return error when SDMA is not supported configs: rpi_4 : enable SDHCI_SDMA config configs/rpi_4_32b_defconfig | 1 + configs/rpi_4_defconfig | 1 + drivers/mmc/sdhci.c | 13 +++-- 3 files changed, 9 insertions(+), 6 deletions(-) -- 2.26.0
[Patch V4 2/3] mmc: sdhci: not return error when SDMA is not supported
If Host controller doesn't support SDMA, it doesn't need to return
error. Because it can be worked with PIO mode.
Signed-off-by: Jaehoon Chung
Reviewed-by: Peng Fan
Reviewed-by: Minkyu Kang
---
drivers/mmc/sdhci.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 2b7493fbac..49e67fc7bd 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -741,13 +741,12 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct
sdhci_host *host,
debug("%s, caps: 0x%x\n", __func__, caps);
#ifdef CONFIG_MMC_SDHCI_SDMA
- if (!(caps & SDHCI_CAN_DO_SDMA)) {
+ if ((caps & SDHCI_CAN_DO_SDMA)) {
+ host->flags |= USE_SDMA;
+ } else {
printf("%s: Your controller doesn't support SDMA!!\n",
__func__);
- return -EINVAL;
}
-
- host->flags |= USE_SDMA;
#endif
#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
if (!(caps & SDHCI_CAN_DO_ADMA2)) {
--
2.26.0
RE: [PATCH] arm64: ls1012a: enable DM support for sata
>-Original Message- >From: U-Boot On Behalf Of Peng Ma >Sent: Friday, February 14, 2020 3:47 PM >To: bhaskar.upadh...@nxp.com; Rajesh Bhagat ; >sumit.g...@nxp.com; Priyanka Jain >Cc: Andy Tang ; u-boot@lists.denx.de; Peng Ma > >Subject: [PATCH] arm64: ls1012a: enable DM support for sata > >Enable related configs to support sata DM feature. > >Signed-off-by: Peng Ma >--- > configs/ls1012a2g5rdb_qspi_defconfig | 1 + > configs/ls1012a2g5rdb_tfa_defconfig | 1 + > configs/ls1012afrdm_qspi_defconfig | 6 ++ > configs/ls1012afrdm_tfa_defconfig| 6 ++ > configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 ++ > 5 files changed, 16 insertions(+) > >diff --git a/configs/ls1012a2g5rdb_qspi_defconfig >b/configs/ls1012a2g5rdb_qspi_defconfig >index b1cf8ef7c5..ae3805ee47 100644 >--- a/configs/ls1012a2g5rdb_qspi_defconfig >+++ b/configs/ls1012a2g5rdb_qspi_defconfig >@@ -35,6 +35,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y >CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y >CONFIG_DM=y >+CONFIG_SCSI_AHCI=y > CONFIG_SATA_CEVA=y > CONFIG_DM_I2C=y > CONFIG_DM_MMC=y >diff --git a/configs/ls1012a2g5rdb_tfa_defconfig >b/configs/ls1012a2g5rdb_tfa_defconfig >index a978580952..8e35d0fdfd 100644 >--- a/configs/ls1012a2g5rdb_tfa_defconfig >+++ b/configs/ls1012a2g5rdb_tfa_defconfig >@@ -35,6 +35,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y >CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y >CONFIG_DM=y >+CONFIG_SCSI_AHCI=y > CONFIG_SATA_CEVA=y > CONFIG_DM_I2C=y > CONFIG_DM_MMC=y >diff --git a/configs/ls1012afrdm_qspi_defconfig >b/configs/ls1012afrdm_qspi_defconfig >index 11d0cee39a..2aa29deead 100644 >--- a/configs/ls1012afrdm_qspi_defconfig >+++ b/configs/ls1012afrdm_qspi_defconfig >@@ -8,6 +8,7 @@ CONFIG_DM_GPIO=y > CONFIG_FSL_LS_PPA=y > CONFIG_QSPI_AHB_INIT=y > CONFIG_NR_DRAM_BANKS=2 >+CONFIG_AHCI=y > CONFIG_DISTRO_DEFAULTS=y > # CONFIG_SYS_MALLOC_F is not set > CONFIG_FIT_VERBOSE=y >@@ -33,8 +34,11 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y >CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y >CONFIG_DM=y >+CONFIG_SCSI_AHCI=y >+CONFIG_SATA_CEVA=y > CONFIG_DM_I2C=y > # CONFIG_MMC is not set >+CONFIG_DM_MMC=y > CONFIG_MTD=y > CONFIG_DM_SPI_FLASH=y > # CONFIG_SPI_FLASH_BAR is not set >@@ -47,6 +51,8 @@ CONFIG_DM_PCI=y > CONFIG_DM_PCI_COMPAT=y > CONFIG_PCIE_LAYERSCAPE=y > CONFIG_DM_RTC=y >+CONFIG_SCSI=y >+CONFIG_DM_SCSI=y > CONFIG_SYS_NS16550=y > CONFIG_SPI=y > CONFIG_DM_SPI=y >diff --git a/configs/ls1012afrdm_tfa_defconfig >b/configs/ls1012afrdm_tfa_defconfig >index 2818bdf0d2..30deb771f2 100644 >--- a/configs/ls1012afrdm_tfa_defconfig >+++ b/configs/ls1012afrdm_tfa_defconfig >@@ -10,6 +10,7 @@ CONFIG_QSPI_AHB_INIT=y > CONFIG_NR_DRAM_BANKS=2 > CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y > CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y >+CONFIG_AHCI=y > CONFIG_DISTRO_DEFAULTS=y > # CONFIG_SYS_MALLOC_F is not set > CONFIG_FIT_VERBOSE=y >@@ -33,8 +34,11 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y >CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y >CONFIG_DM=y >+CONFIG_SCSI_AHCI=y >+CONFIG_SATA_CEVA=y > CONFIG_DM_I2C=y > # CONFIG_MMC is not set >+CONFIG_DM_MMC=y > CONFIG_MTD=y > CONFIG_DM_SPI_FLASH=y > # CONFIG_SPI_FLASH_BAR is not set >@@ -47,6 +51,8 @@ CONFIG_DM_PCI=y > CONFIG_DM_PCI_COMPAT=y > CONFIG_PCIE_LAYERSCAPE=y > CONFIG_DM_RTC=y >+CONFIG_SCSI=y >+CONFIG_DM_SCSI=y > CONFIG_SYS_NS16550=y > CONFIG_SPI=y > CONFIG_DM_SPI=y >diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig >b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig >index 23dea4ce23..885a6e0bdf 100644 >--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig >+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig >@@ -9,6 +9,7 @@ CONFIG_QSPI_AHB_INIT=y > CONFIG_NR_DRAM_BANKS=2 > CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y > CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y >+CONFIG_AHCI=y > CONFIG_DISTRO_DEFAULTS=y > # CONFIG_SYS_MALLOC_F is not set > CONFIG_FIT_VERBOSE=y >@@ -38,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y >CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y >+CONFIG_SATA_CEVA=y > CONFIG_DM_I2C=y > CONFIG_DM_MMC=y > CONFIG_FSL_ESDHC=y >-- >2.17.1 This has below build error: Building current source for 15 boards (2 threads, 1 job per thread) aarch64: + ls1012a2g5rdb_qspi +In file included from include/config.h:6:0, + from include/common.h:16, + from lib/asm-offsets.c:14: +include/configs/ls1012a2g5rdb.h:25:0: error: "CONFIG_LIBATA" redefined [-Werror] + #define CONFIG_LIBATA + +In file included from include/linux/kconfig.h:4:0, + from :0: +include/generated/autoconf.h:153:0: note: this is the location of the previous definition + #define CONFIG_LIBATA 1 +include/configs/ls1012a2g5rdb.h:26:0: error: "CONFIG_SCSI_AHCI" redefined [-Werror] + #define CONFIG_SCSI_AHCI +include/generated/autoconf.h:55:0: note: this is the location of the previous definition + #define CONFIG_SCSI_AHCI 1 +cc1: all warnings being treated as errors +make[2]: *** [lib/asm-offsets.s] Error 1 +make[1]: *** [prepare0] Error 2 +m
Re: [PATCH v3 1/8] tool: Move ALIGN_MASK to header as common MACRO
Hi Kever,
Kever Yang writes:
> The ALIGN code is need by many files who need handle structure or image
> align, so move the macro to imagetool.h file.
>
> Signed-off-by: Kever Yang
Thanks for updating the patches.
For the series -
Reviewed-by: Punit Agrawal
Thanks,
Punit
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> include/imx8image.h | 1 -
> tools/ifwitool.c| 4 +---
> tools/imagetool.h | 3 +++
> tools/imx8mimage.c | 2 --
> tools/mksunxiboot.c | 4 +---
> 5 files changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/include/imx8image.h b/include/imx8image.h
> index 68ec9f5fcd..00c614ab6c 100644
> --- a/include/imx8image.h
> +++ b/include/imx8image.h
> @@ -11,7 +11,6 @@
> #include
> #include
> #include "imagetool.h"
> -#include "linux/kernel.h"
>
> #define __packed __attribute__((packed))
>
> diff --git a/tools/ifwitool.c b/tools/ifwitool.c
> index 543e9d4e70..b2b06cc921 100644
> --- a/tools/ifwitool.c
> +++ b/tools/ifwitool.c
> @@ -8,15 +8,13 @@
> #include
> #include
> #include
> +#include "imagetool.h"
> #include "os_support.h"
>
> #ifndef __packed
> #define __packed __attribute__((packed))
> #endif
> #define KiB 1024
> -#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a) - 1)
> -#define __ALIGN_MASK(x, mask)(((x) + (mask)) & ~(mask))
> -#define ARRAY_SIZE(x)(sizeof(x) / sizeof((x)[0]))
>
> /*
> * min()/max()/clamp() macros that also do
> diff --git a/tools/imagetool.h b/tools/imagetool.h
> index e1c778b0df..81e5cd0c5c 100644
> --- a/tools/imagetool.h
> +++ b/tools/imagetool.h
> @@ -25,6 +25,9 @@
>
> #define ARRAY_SIZE(x)(sizeof(x) / sizeof((x)[0]))
>
> +#define __ALIGN_MASK(x, mask)(((x) + (mask)) & ~(mask))
> +#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a) - 1)
> +
> #define IH_ARCH_DEFAULT IH_ARCH_INVALID
>
> /* Information about a file that needs to be placed into the FIT */
> diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
> index 2b0d946a7d..7defb13962 100644
> --- a/tools/imx8mimage.c
> +++ b/tools/imx8mimage.c
> @@ -32,8 +32,6 @@ static uint32_t rom_version = ROM_V1;
>
> #define HDMI_FW_SIZE 0x17000 /* Use Last 0x1000 for IVT and CSF */
> #define ALIGN_SIZE 0x1000
> -#define ALIGN(x,a) __ALIGN_MASK((x), (__typeof__(x))(a) - 1, a)
> -#define __ALIGN_MASK(x,mask,mask2) (((x) + (mask)) / (mask2) * (mask2))
>
> static uint32_t get_cfg_value(char *token, char *name, int linenr)
> {
> diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
> index 1c8701e75e..a18c9d98bc 100644
> --- a/tools/mksunxiboot.c
> +++ b/tools/mksunxiboot.c
> @@ -14,6 +14,7 @@
> #include
> #include
> #include
> +#include "imagetool.h"
> #include "../arch/arm/include/asm/arch-sunxi/spl.h"
>
> #define STAMP_VALUE 0x5F0A6C39
> @@ -44,9 +45,6 @@ int gen_check_sum(struct boot_file_head *head_p)
> return 0;
> }
>
> -#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1)
> -#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
> -
> #define SUNXI_SRAM_SIZE 0x8000 /* SoC with smaller size are limited
> before */
> #define SRAM_LOAD_MAX_SIZE (SUNXI_SRAM_SIZE - sizeof(struct boot_file_head))
Re: [PATCH 1/4] travis: Remove qemu-riscv64 testing
On Fri, Mar 27, 2020 at 10:19:05AM +0800, Bin Meng wrote: > Hi Tom, > > On Fri, Mar 27, 2020 at 10:01 AM Tom Rini wrote: > > > > On Fri, Mar 27, 2020 at 09:51:03AM +0800, Bin Meng wrote: > > > Hi Tom, > > > > > > On Fri, Mar 27, 2020 at 12:10 AM Tom Rini wrote: > > > > > > > > On Thu, Mar 26, 2020 at 09:05:21AM -0700, Bin Meng wrote: > > > > > > > > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > > > > > available on the internet, and with travis-ci we don't build GRUB > > > > > images like we do for azure and gitlab. > > > > > > > > > > Remove qemu-riscv64 testing temporarily. > > > > > > > > > > Signed-off-by: Bin Meng > > > > > --- > > > > > > > > > > .travis.yml | 7 --- > > > > > 1 file changed, 7 deletions(-) > > > > > > > > > > diff --git a/.travis.yml b/.travis.yml > > > > > index c59bd77..55b94cf 100644 > > > > > --- a/.travis.yml > > > > > +++ b/.travis.yml > > > > > @@ -481,13 +481,6 @@ matrix: > > > > >QEMU_TARGET="ppc-softmmu" > > > > >BUILDMAN="^qemu-ppce500$" > > > > >TOOLCHAIN="powerpc" > > > > > -- name: "test/py qemu-riscv64" > > > > > - env: > > > > > -- TEST_PY_BD="qemu-riscv64" > > > > > - TEST_PY_TEST_SPEC="not sleep" > > > > > - QEMU_TARGET="riscv64-softmmu" > > > > > - BUILDMAN="^qemu-riscv64$" > > > > > - TOOLCHAIN="riscv" > > > > > - name: "test/py qemu-x86" > > > > >env: > > > > > - TEST_PY_BD="qemu-x86" > > > > > > > > But why are we removing this? We run all of the rest of the test suites > > > > and I don't think this one test adds noticeably to the overall Travis > > > > time. Thanks! > > > > > > The reason was mentioned in the commit message. > > > > > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > > > available on the internet, and with travis-ci we don't build GRUB > > > images like we do for azure and gitlab. > > > > > > Do you want to build GRUB image in travis, like what's done in the > > > docker image used for azure/gitlab? > > > > But this isn't just for testing GRUB via UEFI, it runs our test/py suite > > too. And that's worth doing, right? > > Yes, and this testing is covered in azure/gitlab. The issue is that > whether we need build GRUB in travis. If yes, I can update the travis > scripts to sync with azure/gitlab. So you're trying to keep them all consistent in terms of what's covered. I'm not sure that's viable and we have other cases where I believe some tests aren't run in Travis but only gitlab such as the filesystem tests. -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/4] travis: Remove qemu-riscv64 testing
Hi Tom, On Fri, Mar 27, 2020 at 10:01 AM Tom Rini wrote: > > On Fri, Mar 27, 2020 at 09:51:03AM +0800, Bin Meng wrote: > > Hi Tom, > > > > On Fri, Mar 27, 2020 at 12:10 AM Tom Rini wrote: > > > > > > On Thu, Mar 26, 2020 at 09:05:21AM -0700, Bin Meng wrote: > > > > > > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > > > > available on the internet, and with travis-ci we don't build GRUB > > > > images like we do for azure and gitlab. > > > > > > > > Remove qemu-riscv64 testing temporarily. > > > > > > > > Signed-off-by: Bin Meng > > > > --- > > > > > > > > .travis.yml | 7 --- > > > > 1 file changed, 7 deletions(-) > > > > > > > > diff --git a/.travis.yml b/.travis.yml > > > > index c59bd77..55b94cf 100644 > > > > --- a/.travis.yml > > > > +++ b/.travis.yml > > > > @@ -481,13 +481,6 @@ matrix: > > > >QEMU_TARGET="ppc-softmmu" > > > >BUILDMAN="^qemu-ppce500$" > > > >TOOLCHAIN="powerpc" > > > > -- name: "test/py qemu-riscv64" > > > > - env: > > > > -- TEST_PY_BD="qemu-riscv64" > > > > - TEST_PY_TEST_SPEC="not sleep" > > > > - QEMU_TARGET="riscv64-softmmu" > > > > - BUILDMAN="^qemu-riscv64$" > > > > - TOOLCHAIN="riscv" > > > > - name: "test/py qemu-x86" > > > >env: > > > > - TEST_PY_BD="qemu-x86" > > > > > > But why are we removing this? We run all of the rest of the test suites > > > and I don't think this one test adds noticeably to the overall Travis > > > time. Thanks! > > > > The reason was mentioned in the commit message. > > > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > > available on the internet, and with travis-ci we don't build GRUB > > images like we do for azure and gitlab. > > > > Do you want to build GRUB image in travis, like what's done in the > > docker image used for azure/gitlab? > > But this isn't just for testing GRUB via UEFI, it runs our test/py suite > too. And that's worth doing, right? Yes, and this testing is covered in azure/gitlab. The issue is that whether we need build GRUB in travis. If yes, I can update the travis scripts to sync with azure/gitlab. Regards, Bin
Re: [PATCH 1/3] Dockerfile: Install riscv32 toolchain from kernel.org
On Fri, Mar 27, 2020 at 09:57:47AM +0800, Bin Meng wrote: > Hi Tom, > > On Fri, Mar 27, 2020 at 12:14 AM Tom Rini wrote: > > > > On Thu, Mar 26, 2020 at 09:04:52AM -0700, Bin Meng wrote: > > > > > This is required to build GRUB UEFI target for RISC-V 32-bit. > > > > > > Signed-off-by: Bin Meng > > > > Since we can use the 64bit toolchain for 32bit U-Boot, can we not pass > > GRUB the right flags to use the same toolchain? Thanks! > > The 32-bit GRUB won't build with the 64-bit toolchain as of the > grub-2.04 branch we are using. Is that something that upstream has fixed or will fix / can be fixed and we can bump the tag we're using for? -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/4] travis: Remove qemu-riscv64 testing
On Fri, Mar 27, 2020 at 09:51:03AM +0800, Bin Meng wrote: > Hi Tom, > > On Fri, Mar 27, 2020 at 12:10 AM Tom Rini wrote: > > > > On Thu, Mar 26, 2020 at 09:05:21AM -0700, Bin Meng wrote: > > > > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > > > available on the internet, and with travis-ci we don't build GRUB > > > images like we do for azure and gitlab. > > > > > > Remove qemu-riscv64 testing temporarily. > > > > > > Signed-off-by: Bin Meng > > > --- > > > > > > .travis.yml | 7 --- > > > 1 file changed, 7 deletions(-) > > > > > > diff --git a/.travis.yml b/.travis.yml > > > index c59bd77..55b94cf 100644 > > > --- a/.travis.yml > > > +++ b/.travis.yml > > > @@ -481,13 +481,6 @@ matrix: > > >QEMU_TARGET="ppc-softmmu" > > >BUILDMAN="^qemu-ppce500$" > > >TOOLCHAIN="powerpc" > > > -- name: "test/py qemu-riscv64" > > > - env: > > > -- TEST_PY_BD="qemu-riscv64" > > > - TEST_PY_TEST_SPEC="not sleep" > > > - QEMU_TARGET="riscv64-softmmu" > > > - BUILDMAN="^qemu-riscv64$" > > > - TOOLCHAIN="riscv" > > > - name: "test/py qemu-x86" > > >env: > > > - TEST_PY_BD="qemu-x86" > > > > But why are we removing this? We run all of the rest of the test suites > > and I don't think this one test adds noticeably to the overall Travis > > time. Thanks! > > The reason was mentioned in the commit message. > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > available on the internet, and with travis-ci we don't build GRUB > images like we do for azure and gitlab. > > Do you want to build GRUB image in travis, like what's done in the > docker image used for azure/gitlab? But this isn't just for testing GRUB via UEFI, it runs our test/py suite too. And that's worth doing, right? -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/3] Dockerfile: Install riscv32 toolchain from kernel.org
Hi Tom, On Fri, Mar 27, 2020 at 12:14 AM Tom Rini wrote: > > On Thu, Mar 26, 2020 at 09:04:52AM -0700, Bin Meng wrote: > > > This is required to build GRUB UEFI target for RISC-V 32-bit. > > > > Signed-off-by: Bin Meng > > Since we can use the 64bit toolchain for 32bit U-Boot, can we not pass > GRUB the right flags to use the same toolchain? Thanks! > The 32-bit GRUB won't build with the 64-bit toolchain as of the grub-2.04 branch we are using. Regards, Bin
Re: [PATCH 1/4] travis: Remove qemu-riscv64 testing
Hi Tom, On Fri, Mar 27, 2020 at 12:10 AM Tom Rini wrote: > > On Thu, Mar 26, 2020 at 09:05:21AM -0700, Bin Meng wrote: > > > As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 > > available on the internet, and with travis-ci we don't build GRUB > > images like we do for azure and gitlab. > > > > Remove qemu-riscv64 testing temporarily. > > > > Signed-off-by: Bin Meng > > --- > > > > .travis.yml | 7 --- > > 1 file changed, 7 deletions(-) > > > > diff --git a/.travis.yml b/.travis.yml > > index c59bd77..55b94cf 100644 > > --- a/.travis.yml > > +++ b/.travis.yml > > @@ -481,13 +481,6 @@ matrix: > >QEMU_TARGET="ppc-softmmu" > >BUILDMAN="^qemu-ppce500$" > >TOOLCHAIN="powerpc" > > -- name: "test/py qemu-riscv64" > > - env: > > -- TEST_PY_BD="qemu-riscv64" > > - TEST_PY_TEST_SPEC="not sleep" > > - QEMU_TARGET="riscv64-softmmu" > > - BUILDMAN="^qemu-riscv64$" > > - TOOLCHAIN="riscv" > > - name: "test/py qemu-x86" > >env: > > - TEST_PY_BD="qemu-x86" > > But why are we removing this? We run all of the rest of the test suites > and I don't think this one test adds noticeably to the overall Travis > time. Thanks! The reason was mentioned in the commit message. As of today there is no pre-built UEFI GRUB image for RISC-V 32/64 available on the internet, and with travis-ci we don't build GRUB images like we do for azure and gitlab. Do you want to build GRUB image in travis, like what's done in the docker image used for azure/gitlab? Regards, Bin
Re: [PULL] Pull request: u-boot-stm/next =u-boot-stm32-20200324
On Wed, Mar 25, 2020 at 08:15:01AM +, Patrick DELAUNAY wrote: > Hi Tom, > > Please pull the STM32 next related fixes for v2020.07 = u-boot-stm32-20200324 > > With the following changes: > - stm32mp: fix command stboard > - stm32mp: update kernel device tree according the part number > - stm32mp: add 800 MHz profile support = stm32mp15xd and stm32mp15xf > - stm32mp: set cp15 frequency in psci cpu on > - stm32mp: DT alignment with Linux 5.6-rc1 > - stm32mp: clk: add SPI5 support and correct CKSELR masks > - stm32mp: ram: fixes on LPDDR2/LPDDR3 support and on tuning > - stm32: i2c: allows for any bus frequency > - sti: timer: livetree and clk API conversion > > CI status: > https://gitlab.denx.de/u-boot/custodians/u-boot-stm/pipelines/2510 > > Thanks, > Patrick > > The following changes since commit 2738f0edea7d19960d692284d1f378b1a2b4c4a5: > > Merge tag 'ti-v2020.07-next' of > https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next (2020-03-17 > 11:59:58 -0400) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git > tags/u-boot-stm32-20200324 > > for you to fetch changes up to 5b5699cdc97122e08e7fd0886a9e4474ca3ccb35: > > timer: sti: use clk API to get timer clock rate (2020-03-24 14:23:35 +0100) > Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader.
On Tue, Feb 25, 2020 at 06:22:16PM +0100, Kristian Amlie wrote: > EFI was disabled in f95b8a4b5f64f because of the missing DTB file, > and indeed, the DTB file is required to load recent versions of GRUB > (2.04) correctly. > > Signed-off-by: Kristian Amlie Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Pull request: u-boot-rockchip-20200327
Hi Tom, Please pull the rockchip fixes: - Fixed for rv1108 and elgin-rv1108 board - Fix the keyboard from USB instead of CrOS EC Travis: https://travis-ci.org/keveryang/u-boot/builds/667296226 Thanks, - Kever The following changes since commit 0aadc0786e4a249cddd37efd8875f09e645be4cd: Merge tag 'efi-2020-04-rc4-5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2020-03-23 10:14:31 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20200327 for you to fetch changes up to e5a405583f5ce9576c5084a178622e2fdd49cb23: rockchip: mkimage: Use an existing macro instead of a decimal value (2020-03-26 22:58:46 +0800) Kever Yang (2): rockchip: elgin-rv1108: Use syscon API to get grf base rockchip: evb-rv1108: Use syscon API to get grf base Miquel Raynal (1): rockchip: mkimage: Use an existing macro instead of a decimal value Otavio Salvador (4): ARM: dts: Activate pullups in the console pins on rv1108-elgin-r1 elgin-rv1108: Use rk_board_late_init() for GPIO settings elgin-rv1108: Avoid adc_channel_single_shot error rv1108: Fix boot regression Peter Robinson (1): rockchip: Change keyboard input from CrOS EC keyboard to a USB keyboard arch/arm/dts/rv1108-elgin-r1.dts| 11 +++ arch/arm/dts/rv1108-u-boot.dtsi | 6 ++ board/elgin/elgin_rv1108/elgin_rv1108.c | 9 - board/rockchip/evb_rv1108/evb_rv1108.c | 7 +++ configs/elgin-rv1108_defconfig | 2 ++ configs/miqi-rk3288_defconfig | 1 + configs/roc-pc-rk3399_defconfig | 1 + configs/rock2_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + configs/tinker-s-rk3288_defconfig | 1 + include/configs/miqi_rk3288.h | 2 +- include/configs/roc-pc-rk3399.h | 2 +- include/configs/rock2.h | 2 +- include/configs/tinker_rk3288.h | 2 +- include/configs/vyasa-rk3288.h | 2 +- tools/rkcommon.c| 6 -- 16 files changed, 40 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/rv1108-u-boot.dtsi
Re: SPI driver for Raspberry Pi 4 (BMC2835)
Hi Johannes, I'm also trying to make a secure boot using an SLB9670 TPM (SPI), Yocto and a Raspberry 3, and as far as I'm documented there are no hardware SPI driver due to the fact that `start.elf` and `bootcode.bin` are being closed binaries (https://pi3g.com/2019/02/04/qa-letstrust-tpm/). However some people tried to deal with software SPI driver as a workaround, but I don't know yet if it works (@see: https://www.mail-archive.com/u-boot@lists.denx.de/msg330403.html). Hope it brings some clues, if you manage to do something keep me updated ! Have a nice day, Pierre Fontaine Le 25/03/2020 à 09:08, J. Holland a écrit : > Hi, > > does anyone know, if there is a SPI driver for Raspberry Pi 4 in U-Boot? > > I want to communicate with a TPM 2.0 via hardware SPI. So far I've > compiled > mainline U-Boot with TPM driver support. However, the SPI driver seems > to be > missing. > > The linux kernel ships the driver (drivers/spi/spi-bcm2835.c). Does > anyone know > if there is there a port for U-Boot or if anyone is currently working > on it? > > In theory, I should be able to use the soft SPI driver (since there is a > GPIO > driver), but I'd very much prefer using the hardware SPI controller. > > Many thanks! > > Best, > Johannes >
[PATCH] ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board
The AV96 is in fact an assembly of DH Electronics DHCOR SoM on top
of an AV96 reference board. Split the DTs to reflect that and make
sure to DHCOR SoM can be reused on other boards easily.
It is also highly recommended to configure the board for the DHCOM
make stm32mp15_dhcom_basic_defconfig
make DEVICE_TREE=stm32mp15xx-dhcor-avenger96
as that permits reusing the board code for the DH components, like
accessing and reading out the ethernet MAC from EEPROM.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/stm32mp157a-avenger96.dts| 393 +-
.../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 80
arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 196 +
...oot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} | 79 +---
arch/arm/dts/stm32mp15xx-dhcor.dtsi | 220 ++
doc/board/st/stm32mp1.rst | 8 +-
7 files changed, 509 insertions(+), 470 deletions(-)
create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
rename arch/arm/dts/{stm32mp157a-avenger96-u-boot.dtsi =>
stm32mp15xx-dhcor-u-boot.dtsi} (75%)
create mode 100644 arch/arm/dts/stm32mp15xx-dhcor.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c593b2c98..2564f790de 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -884,7 +884,8 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \
- stm32mp15xx-dhcom-pdk2.dtb
+ stm32mp15xx-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcor-avenger96.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts
b/arch/arm/dts/stm32mp157a-avenger96.dts
index 8e36df8787..9c165104fb 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -4,394 +4,5 @@
* Author: Manivannan Sadhasivam
*/
-/dts-v1/;
-
-#include "stm32mp157c.dtsi"
-#include "stm32mp157xac-pinctrl.dtsi"
-#include
-#include
-
-/ {
- model = "Arrow Electronics STM32MP157A Avenger96 board";
- compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
-
- aliases {
- ethernet0 = ðernet0;
- mmc0 = &sdmmc1;
- serial0 = &uart4;
- serial1 = &uart7;
- spi0 = &qspi;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@c000 {
- device_type = "memory";
- reg = <0xc000 0x4000>;
- };
-
- led {
- compatible = "gpio-leds";
- led1 {
- label = "green:user1";
- gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led2 {
- label = "green:user2";
- gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
-
- led3 {
- label = "green:user3";
- gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc1";
- default-state = "off";
- };
-
- led4 {
- label = "green:user3";
- gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- default-state = "off";
- panic-indicator;
- };
-
- led5 {
- label = "yellow:wifi";
- gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tx";
- default-state = "off";
- };
-
- led6 {
- label = "blue:bt";
- gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "bluetooth-power";
- default-state = "off";
- };
- };
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_b>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- max-speed = <1000>;
- phy-handle = <&phy0>;
- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@7 {
- reg = <7>;
- };
-
[PATCH] ARM: dts: stm32: Repair PMIC configuration on AV96
The core and vdd PMIC buck regulators were misconfigured, which caused
instability of the board and malfunction of high-speed interfaces, like
the RGMII. Furthermore, the vtt_ddr was also wrong. Configure the PMIC
correctly to repair these problems.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157a-avenger96.dts | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts
b/arch/arm/dts/stm32mp157a-avenger96.dts
index b6c984171a..8e36df8787 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -153,7 +153,7 @@
vddcore: buck1 {
regulator-name = "vddcore";
- regulator-min-microvolt = <120>;
+ regulator-min-microvolt = <80>;
regulator-max-microvolt = <135>;
regulator-always-on;
regulator-initial-mode = <0>;
@@ -171,8 +171,8 @@
vdd: buck3 {
regulator-name = "vdd";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <250>;
regulator-always-on;
st,mask_reset;
regulator-initial-mode = <0>;
@@ -206,8 +206,8 @@
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
- regulator-min-microvolt = <50>;
- regulator-max-microvolt = <75>;
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <100>;
regulator-always-on;
regulator-over-current-protection;
};
@@ -254,6 +254,7 @@
regulator-name = "vbus_otg";
interrupts = ;
interrupt-parent = <&pmic>;
+ regulator-active-discharge = <1>;
};
vbus_sw: pwr_sw2 {
--
2.25.1
[PATCH 2/2] ARM: dts: stm32: Repair ethernet operation on AV96
The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2
and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157a-avenger96.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts
b/arch/arm/dts/stm32mp157a-avenger96.dts
index 43ffbe9f9a..d0fa9af9cc 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -81,8 +81,8 @@
ðernet0 {
status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
+ pinctrl-0 = <ðernet0_rgmii_pins_b>;
+ pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii";
max-speed = <1000>;
--
2.25.1
[PATCH] ARM: dts: stm32: Add missing ethernet PHY reset on AV96
Add PHY reset GPIO on AV96 ethernet PHY.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157a-avenger96.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts
b/arch/arm/dts/stm32mp157a-avenger96.dts
index d0fa9af9cc..b6c984171a 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -87,6 +87,7 @@
phy-mode = "rgmii";
max-speed = <1000>;
phy-handle = <&phy0>;
+ phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
mdio0 {
#address-cells = <1>;
--
2.25.1
[PATCH 1/2] ARM: dts: stm32: Add alternate pinmux for ethernet RGMII
Add another mux option for DWMAC RGMII, this is used on AV96 board.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157-pinctrl.dtsi | 51
1 file changed, 51 insertions(+)
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi
b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index e25c44760e..a510e5f5de 100644
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -288,6 +288,57 @@
};
};
+ ethernet0_rgmii_pins_b: rgmii-1 {
+ pins1 {
+ pinmux = ,
/* ETH_RGMII_CLK125 */
+,
/* ETH_RGMII_GTX_CLK */
+,
/* ETH_RGMII_TXD0 */
+,
/* ETH_RGMII_TXD1 */
+,
/* ETH_RGMII_TXD2 */
+,
/* ETH_RGMII_TXD3 */
+,
/* ETH_RGMII_TX_CTL */
+;
/* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = ;
/* ETH_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = ,
/* ETH_RGMII_RXD0 */
+,
/* ETH_RGMII_RXD1 */
+,
/* ETH_RGMII_RXD2 */
+,
/* ETH_RGMII_RXD3 */
+,
/* ETH_RGMII_RX_CLK */
+;
/* ETH_RGMII_RX_CTL */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 {
+ pins1 {
+ pinmux = , /* ETH_RGMII_CLK125 */
+, /* ETH_RGMII_GTX_CLK */
+, /* ETH_RGMII_TXD0 */
+, /* ETH_RGMII_TXD1 */
+, /* ETH_RGMII_TXD2 */
+, /* ETH_RGMII_TXD3 */
+, /* ETH_RGMII_TX_CTL */
+, /* ETH_MDIO */
+, /* ETH_MDC */
+, /* ETH_RGMII_RXD0 */
+, /* ETH_RGMII_RXD1 */
+, /* ETH_RGMII_RXD2 */
+, /* ETH_RGMII_RXD3 */
+, /* ETH_RGMII_RX_CLK */
+; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
fmc_pins_a: fmc-0 {
pins1 {
pinmux = ,
/* FMC_NOE */
--
2.25.1
[PATCH v1 2/2] board: presidio-asic: Add RAW Parallel NAND support
Add Parallel NAND CA support to Cortina Access Presidio Engineering Board support Signed-off-by: Alex Nemirovsky CC: Miquel Raynal CC: Simon Glass --- configs/cortina_presidio-asic-bch16_defconfig | 35 ++ configs/cortina_presidio-asic-bch24_defconfig | 36 +++ configs/cortina_presidio-asic-bch40_defconfig | 36 +++ configs/cortina_presidio-asic-bch8_defconfig | 36 +++ include/configs/presidio_asic.h | 15 +++ 5 files changed, 158 insertions(+) create mode 100644 configs/cortina_presidio-asic-bch16_defconfig create mode 100644 configs/cortina_presidio-asic-bch24_defconfig create mode 100644 configs/cortina_presidio-asic-bch40_defconfig create mode 100644 configs/cortina_presidio-asic-bch8_defconfig diff --git a/configs/cortina_presidio-asic-bch16_defconfig b/configs/cortina_presidio-asic-bch16_defconfig new file mode 100644 index 000..57ef98f --- /dev/null +++ b/configs/cortina_presidio-asic-bch16_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +# CONFIG_SYS_ARCH_TIMER is not set +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SYS_TEXT_BASE=0x0400 +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x40 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SYS_PROMPT="G3#" +CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_CORTINA_GPIO=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_CORTINA=y +CONFIG_DM_SERIAL=y +CONFIG_CORTINA_UART=y +CONFIG_WDT=y +CONFIG_WDT_CORTINA=y diff --git a/configs/cortina_presidio-asic-bch24_defconfig b/configs/cortina_presidio-asic-bch24_defconfig new file mode 100644 index 000..d22eae7 --- /dev/null +++ b/configs/cortina_presidio-asic-bch24_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +# CONFIG_SYS_ARCH_TIMER is not set +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SYS_TEXT_BASE=0x0400 +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x40 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SYS_PROMPT="G3#" +CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_CORTINA_GPIO=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_CORTINA=y +CONFIG_NAND_CORTINA_ECC_LEVEL=4 +CONFIG_DM_SERIAL=y +CONFIG_CORTINA_UART=y +CONFIG_WDT=y +CONFIG_WDT_CORTINA=y diff --git a/configs/cortina_presidio-asic-bch40_defconfig b/configs/cortina_presidio-asic-bch40_defconfig new file mode 100644 index 000..3c39415 --- /dev/null +++ b/configs/cortina_presidio-asic-bch40_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +# CONFIG_SYS_ARCH_TIMER is not set +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SYS_TEXT_BASE=0x0400 +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x40 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SYS_PROMPT="G3#" +CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_CORTINA_GPIO=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_CORTINA=y +CONFIG_NAND_CORTINA_ECC_LEVEL=5 +CONFIG_DM_SERIAL=y +CONFIG_CORTINA_UART=y +CONFIG_WDT=y +CONFIG_WDT_CORTINA=y diff --git a/configs/cortina_presidio-asic-bch8_defconfig b/configs/cortina_presidio-asic-bch8_defconfig new file mode 100644 index 000..8cda753 --- /dev/null +++ b/configs/cortina_presidio-asic-bch8_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +# CONFIG_SYS_ARCH_TIMER is not set +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SYS_TEXT_BASE=0x0400 +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x40 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SYS_PROMPT="G3#" +CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_CORTINA_GPIO=y +# CONFIG_MMC is not
[PATCH v1 2/2] board: presidio-asic: Add RAW Parallel NAND support
Add Parallel NAND CA support to Cortina Access Presidio Engineering Board support Signed-off-by: Alex Nemirovsky --- configs/cortina_presidio-asic-bch16_defconfig | 35 ++ configs/cortina_presidio-asic-bch24_defconfig | 36 +++ configs/cortina_presidio-asic-bch40_defconfig | 36 +++ configs/cortina_presidio-asic-bch8_defconfig | 36 +++ include/configs/presidio_asic.h | 15 +++ 5 files changed, 158 insertions(+) create mode 100644 configs/cortina_presidio-asic-bch16_defconfig create mode 100644 configs/cortina_presidio-asic-bch24_defconfig create mode 100644 configs/cortina_presidio-asic-bch40_defconfig create mode 100644 configs/cortina_presidio-asic-bch8_defconfig diff --git a/configs/cortina_presidio-asic-bch16_defconfig b/configs/cortina_presidio-asic-bch16_defconfig new file mode 100644 index 000..57ef98f --- /dev/null +++ b/configs/cortina_presidio-asic-bch16_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +# CONFIG_SYS_ARCH_TIMER is not set +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SYS_TEXT_BASE=0x0400 +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x40 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SYS_PROMPT="G3#" +CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_CORTINA_GPIO=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_CORTINA=y +CONFIG_DM_SERIAL=y +CONFIG_CORTINA_UART=y +CONFIG_WDT=y +CONFIG_WDT_CORTINA=y diff --git a/configs/cortina_presidio-asic-bch24_defconfig b/configs/cortina_presidio-asic-bch24_defconfig new file mode 100644 index 000..d22eae7 --- /dev/null +++ b/configs/cortina_presidio-asic-bch24_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +# CONFIG_SYS_ARCH_TIMER is not set +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SYS_TEXT_BASE=0x0400 +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x40 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SYS_PROMPT="G3#" +CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_CORTINA_GPIO=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_CORTINA=y +CONFIG_NAND_CORTINA_ECC_LEVEL=4 +CONFIG_DM_SERIAL=y +CONFIG_CORTINA_UART=y +CONFIG_WDT=y +CONFIG_WDT_CORTINA=y diff --git a/configs/cortina_presidio-asic-bch40_defconfig b/configs/cortina_presidio-asic-bch40_defconfig new file mode 100644 index 000..3c39415 --- /dev/null +++ b/configs/cortina_presidio-asic-bch40_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +# CONFIG_SYS_ARCH_TIMER is not set +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SYS_TEXT_BASE=0x0400 +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x40 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SYS_PROMPT="G3#" +CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_CORTINA_GPIO=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_CORTINA=y +CONFIG_NAND_CORTINA_ECC_LEVEL=5 +CONFIG_DM_SERIAL=y +CONFIG_CORTINA_UART=y +CONFIG_WDT=y +CONFIG_WDT_CORTINA=y diff --git a/configs/cortina_presidio-asic-bch8_defconfig b/configs/cortina_presidio-asic-bch8_defconfig new file mode 100644 index 000..8cda753 --- /dev/null +++ b/configs/cortina_presidio-asic-bch8_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +# CONFIG_SYS_ARCH_TIMER is not set +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SYS_TEXT_BASE=0x0400 +CONFIG_ENV_SIZE=0x2 +CONFIG_ENV_OFFSET=0x40 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SYS_PROMPT="G3#" +CONFIG_CMD_NAND=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_CORTINA_GPIO=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_N
[PATCH v1 0/2] This series of patches add support for the Cortina Access
RAW NAND controller found in CA SoCs. Additionally, initial support is integrated into into the Cortina Access Presidio Engineering Board. Alex Nemirovsky (1): board: presidio-asic: Add RAW Parallel NAND support Jason Li (1): mtd: rawnand: ca_nand: add Cortina Access Parallel NAND controller support MAINTAINERS |4 + configs/cortina_presidio-asic-bch16_defconfig | 35 + configs/cortina_presidio-asic-bch24_defconfig | 36 + configs/cortina_presidio-asic-bch40_defconfig | 36 + configs/cortina_presidio-asic-bch8_defconfig | 36 + drivers/mtd/nand/raw/Kconfig | 30 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/ca_nand.c| 4914 + drivers/mtd/nand/raw/ca_nand.h| 3899 include/configs/presidio_asic.h | 15 + 10 files changed, 9006 insertions(+) create mode 100644 configs/cortina_presidio-asic-bch16_defconfig create mode 100644 configs/cortina_presidio-asic-bch24_defconfig create mode 100644 configs/cortina_presidio-asic-bch40_defconfig create mode 100644 configs/cortina_presidio-asic-bch8_defconfig create mode 100644 drivers/mtd/nand/raw/ca_nand.c create mode 100644 drivers/mtd/nand/raw/ca_nand.h -- 2.7.4
[PATCH 1/3] t210: do not enable PLLE and UPHY PLL HW PWRSEQ
From: JC Kuo
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.
Adds call to board_cleanup_before_linux to facilitate this.
Signed-off-by: JC Kuo
Signed-off-by: Tom Warren
Acked-by: Stephen Warren
---
arch/arm/cpu/armv8/cpu.c | 5 ++
arch/arm/include/asm/arch-tegra/xusb-padctl.h | 1 +
arch/arm/mach-tegra/board2.c | 6 +++
arch/arm/mach-tegra/tegra210/clock.c | 19
arch/arm/mach-tegra/tegra210/xusb-padctl.c| 68 +--
arch/arm/mach-tegra/xusb-padctl-dummy.c | 4 ++
6 files changed, 59 insertions(+), 44 deletions(-)
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index 2467e0b..3575203 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -32,6 +32,8 @@ void sdelay(unsigned long loops)
"b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
}
+void __weak board_cleanup_before_linux(void){}
+
int cleanup_before_linux(void)
{
/*
@@ -40,6 +42,9 @@ int cleanup_before_linux(void)
*
* disable interrupt and turn off caches etc ...
*/
+
+ board_cleanup_before_linux();
+
disable_interrupts();
/*
diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h
b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
index deccdf4..7e14d81 100644
--- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h
+++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
@@ -16,6 +16,7 @@ struct tegra_xusb_phy;
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
void tegra_xusb_padctl_init(void);
+void tegra_xusb_padctl_exit(void);
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index d3497a2..787ff97 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -181,6 +181,12 @@ int board_init(void)
return nvidia_board_init();
}
+void board_cleanup_before_linux(void)
+{
+ /* power down UPHY PLL */
+ tegra_xusb_padctl_exit();
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
static void __gpio_early_init(void)
{
diff --git a/arch/arm/mach-tegra/tegra210/clock.c
b/arch/arm/mach-tegra/tegra210/clock.c
index b240860..f1b25e2 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -1235,25 +1235,6 @@ int tegra_plle_enable(void)
value &= ~PLLE_SS_CNTL_INTERP_RESET;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- /* 7. Enable HW power sequencer for PLLE */
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- value &= ~PLLE_MISC_IDDQ_SWCTL;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
- value &= ~PLLE_AUX_SS_SWCTL;
- value &= ~PLLE_AUX_ENABLE_SWCTL;
- value |= PLLE_AUX_SS_SEQ_INCLUDE;
- value |= PLLE_AUX_USE_LOCKDET;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
- /* 8. Wait 1 us */
-
- udelay(1);
- value |= PLLE_AUX_SEQ_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
return 0;
}
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index ab6684f..64dc297 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy)
return tegra_xusb_padctl_disable(phy->padctl);
}
+#define XUSB_PADCTL_USB3_PAD_MUX 0x28
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
+
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
@@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
- value = readl
[PATCH 0/3] t210: miscellaneous patches
From: Tom Warren These patches change some PLL power sequencing, remove pinmuxing and GPIO init on T210, and adjust some load addresses to allow for larger kernels. JC Kuo (1): t210: do not enable PLLE and UPHY PLL HW PWRSEQ Tom Warren (2): t210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernels t210: pinmux: Remove pinmux/GPIO init from T210 boards arch/arm/cpu/armv8/cpu.c | 5 + arch/arm/include/asm/arch-tegra/xusb-padctl.h | 1 + arch/arm/mach-tegra/board2.c | 6 + arch/arm/mach-tegra/tegra210/Makefile | 3 +- arch/arm/mach-tegra/tegra210/clock.c | 19 -- arch/arm/mach-tegra/tegra210/pinmux.c | 194 -- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 68 +++-- arch/arm/mach-tegra/xusb-padctl-dummy.c| 4 + board/nvidia/e2220-1170/e2220-1170.c | 21 +- board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 276 board/nvidia/p2371-/p2371-.c | 21 +- board/nvidia/p2371-/pinmux-config-p2371-.h | 267 board/nvidia/p2371-2180/p2371-2180.c | 21 +- board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 278 - board/nvidia/p2571/p2571.c | 21 +- board/nvidia/p2571/pinmux-config-p2571.h | 242 -- include/configs/tegra210-common.h | 4 +- 17 files changed, 66 insertions(+), 1385 deletions(-) delete mode 100644 arch/arm/mach-tegra/tegra210/pinmux.c delete mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h delete mode 100644 board/nvidia/p2371-/pinmux-config-p2371-.h delete mode 100644 board/nvidia/p2371-2180/pinmux-config-p2371-2180.h delete mode 100644 board/nvidia/p2571/pinmux-config-p2571.h -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 2/3] t210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernels
From: Tom Warren The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded from extlinux.conf. Adjust the load addresses to fix this for now. Using the calculated_env addresses table from T186 U-Boot is a better fix, but it isn't working correctly on T210 U-Boot right now, so this will do until I can fix it. Signed-off-by: Tom Warren --- include/configs/tegra210-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 1c53311..1b8e94b 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,8 +46,8 @@ "scriptaddr=0x9000\0" \ "pxefile_addr_r=0x9010\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x8200\0" \ - "ramdisk_addr_r=0x8210\0" + "fdt_addr_r=0x8300\0" \ + "ramdisk_addr_r=0x8320\0" /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 3/3] t210: pinmux: Remove pinmux/GPIO init from T210 boards
From: Tom Warren
T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB
tables. Remove pinmux/GPIO init tables & code from all T210-based builds
below:
p2371-2180 aka TX1
p2371-
e2220-1170
p2571
Signed-off-by: Tom Warren
Acked-by: Stephen Warren
---
arch/arm/mach-tegra/tegra210/Makefile | 3 +-
arch/arm/mach-tegra/tegra210/pinmux.c | 194 --
board/nvidia/e2220-1170/e2220-1170.c | 21 +-
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 276
board/nvidia/p2371-/p2371-.c | 21 +-
board/nvidia/p2371-/pinmux-config-p2371-.h | 267
board/nvidia/p2371-2180/p2371-2180.c | 21 +-
board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 278 -
board/nvidia/p2571/p2571.c | 21 +-
board/nvidia/p2571/pinmux-config-p2571.h | 242 --
10 files changed, 5 insertions(+), 1339 deletions(-)
delete mode 100644 arch/arm/mach-tegra/tegra210/pinmux.c
delete mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
delete mode 100644 board/nvidia/p2371-/pinmux-config-p2371-.h
delete mode 100644 board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
delete mode 100644 board/nvidia/p2571/pinmux-config-p2571.h
diff --git a/arch/arm/mach-tegra/tegra210/Makefile
b/arch/arm/mach-tegra/tegra210/Makefile
index b6012fc..cfcba5b 100644
--- a/arch/arm/mach-tegra/tegra210/Makefile
+++ b/arch/arm/mach-tegra/tegra210/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2013-2015
+# (C) Copyright 2013-2020
# NVIDIA Corporation
#
# SPDX-License-Identifier: GPL-2.0+
@@ -7,6 +7,5 @@
obj-y += clock.o
obj-y += funcmux.o
-obj-y += pinmux.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra210/pinmux.c
b/arch/arm/mach-tegra/tegra210/pinmux.c
deleted file mode 100644
index 6158099..000
--- a/arch/arm/mach-tegra/tegra210/pinmux.c
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include
-#include
-#include
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra210_pingroups[] = {
- /* pin, f0, f1, f2,f3 */
- /* Offset 0x3000 */
- PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
- PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
- PIN_RESERVED,
- /* Offset 0x301c */
- PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
- PIN_RESERVED,
- /* Offset 0x3038 */
- PIN(PEX_L0_RST_N_PA0, PE0,RSVD1, RSVD2, RSVD3),
- PIN(PEX_L0_CLKREQ_N_PA1, PE0,RSVD1, RSVD2, RSVD3),
- PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
- PIN(PEX_L1_RST_N_PA3, PE1,RSVD1, RSVD2, RSVD3),
- PIN(PEX_L1_CLKREQ_N_PA4, PE1,RSVD1, RSVD2, RSVD3),
- PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_MOSI_PC0,SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_MISO_PC1,SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
- PIN(SPI2_MOSI_PB4,SPI2, DTV,RSVD2, RSVD3),
- PIN(SPI2_MISO_PB5,SPI2, DTV,RSVD2, RSVD3),
- PIN(SPI2_SCK_PB6, SPI2, DTV,RSVD2, RSVD3),
- PIN(SPI2_CS0_PB7, SPI2, DTV,RSVD2, RSVD3),
- PIN(SPI2_CS1_PDD0,SPI2, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_MOSI_PC7,SPI4, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_MISO_PD0,SPI4, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
- PIN(SPI4_
[PATCH 0/2] This series of patches add support for the Cortina Access
RAW NAND controller found in CA SoCs. Additionally, initial support is integrated into into the Cortina Access Presidio Engineering Board. Alex Nemirovsky (1): board: presidio-asic: Add RAW Parallel NAND support Jason Li (1): mtd: rawnand: ca_nand: add Cortina Access Parallel NAND controller support configs/cortina_presidio-asic-bch16_defconfig | 35 + configs/cortina_presidio-asic-bch24_defconfig | 36 + configs/cortina_presidio-asic-bch40_defconfig | 36 + configs/cortina_presidio-asic-bch8_defconfig | 36 + drivers/mtd/nand/raw/Kconfig | 30 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/ca_nand.c| 4914 + drivers/mtd/nand/raw/ca_nand.h| 3899 include/configs/presidio_asic.h | 15 + 9 files changed, 9002 insertions(+) create mode 100644 configs/cortina_presidio-asic-bch16_defconfig create mode 100644 configs/cortina_presidio-asic-bch24_defconfig create mode 100644 configs/cortina_presidio-asic-bch40_defconfig create mode 100644 configs/cortina_presidio-asic-bch8_defconfig create mode 100644 drivers/mtd/nand/raw/ca_nand.c create mode 100644 drivers/mtd/nand/raw/ca_nand.h -- 2.7.4
[PATCH v2 2/2] env/sf.c: honour CONFIG_SPL_SAVEENV
Deciding whether to compile the env_sf_save() function based solely on
CONFIG_SPL_BUILD is wrong: For U-Boot proper, it leads to a build
warning in case CONFIG_CMD_SAVEENV=n (because the initialization of
the .save member is guarded by CONFIG_CMD_SAVEENV, while the
env_sf_save() function is built if !CONFIG_SPL_BUILD - and even
without the CONFIG_CMD_SAVEENV guard, the env_save_ptr() macro would
just expand to NULL, with no reference to env_sf_save visible to the
compiler). And for SPL, when one selects CONFIG_SPL_SAVEENV, one
obviously expects to actually be able to save the environment.
The compiler warning can be fixed by using a " ?
env_sf_save : NULL" construction instead of a macro that just eats its
argument and expands to NULL. That way, if is false,
env_sf_save gets eliminated as dead code, but the compiler still sees
the reference to it.
For , we can use CONFIG_IS_ENABLED(SAVEENV), which is true
precisely:
- For U-Boot proper, when CONFIG_CMD_SAVEENV is set (because
CONFIG_SAVEENV is a hidden config symbol that gets set if and only
if CONFIG_CMD_SAVEENV is set).
- For SPL, when CONFIG_SPL_SAVEENV is set.
As a bonus, this also removes quite a few preprocessor conditionals.
This has been run-time tested on a mpc8309-derived board to verify
that saving the environment does indeed work in SPL with these patches
applied.
Signed-off-by: Rasmus Villemoes
---
v2: Use 'CONFIG_IS_ENABLED(SAVEENV) ? env_sf_save : NULL' directly
instead of the dropped ENV_SAVE_PTR macro and expand commit message a
bit.
env/sf.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/env/sf.c b/env/sf.c
index 5ef4055219..f41a846294 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -21,16 +21,12 @@
#include
#ifndef CONFIG_SPL_BUILD
-#define CMD_SAVEENV
#define INITENV
#endif
#ifdef CONFIG_ENV_OFFSET_REDUND
-#ifdef CMD_SAVEENV
static ulong env_offset= CONFIG_ENV_OFFSET;
static ulong env_new_offset= CONFIG_ENV_OFFSET_REDUND;
-#endif
-
#endif /* CONFIG_ENV_OFFSET_REDUND */
DECLARE_GLOBAL_DATA_PTR;
@@ -69,7 +65,6 @@ static int setup_flash_device(void)
}
#if defined(CONFIG_ENV_OFFSET_REDUND)
-#ifdef CMD_SAVEENV
static int env_sf_save(void)
{
env_t env_new;
@@ -148,7 +143,6 @@ static int env_sf_save(void)
return ret;
}
-#endif /* CMD_SAVEENV */
static int env_sf_load(void)
{
@@ -187,7 +181,6 @@ out:
return ret;
}
#else
-#ifdef CMD_SAVEENV
static int env_sf_save(void)
{
u32 saved_size, saved_offset, sector;
@@ -247,7 +240,6 @@ static int env_sf_save(void)
return ret;
}
-#endif /* CMD_SAVEENV */
static int env_sf_load(void)
{
@@ -313,9 +305,7 @@ U_BOOT_ENV_LOCATION(sf) = {
.location = ENVL_SPI_FLASH,
ENV_NAME("SPI Flash")
.load = env_sf_load,
-#ifdef CMD_SAVEENV
- .save = env_save_ptr(env_sf_save),
-#endif
+ .save = CONFIG_IS_ENABLED(SAVEENV) ? env_sf_save : NULL,
#if defined(INITENV) && (CONFIG_ENV_ADDR != 0x0)
.init = env_sf_init,
#endif
--
2.23.0
[PATCH v2 0/2] allow CONFIG_SPL_SAVEENV to work with ENV_IS_IN_SPI_FLASH
Currently, CONFIG_SPL_SAVEENV is not very well supported by the
various storage backends, as many of them contain variants of some
logic that end up not compiling the .save method when
CONFIG_SPL_BUILD.
As I need environment save support in SPL for a target that uses
ENV_IS_IN_SPI_FLASH, these patches fix env/sf.c to honour
CONFIG_SPL_SAVEENV (and fixes a build warning in the rare case where
one sets CONFIG_CMD_SAVEENV=n). In order to fix this properly and not
add to the existing maze of preprocessor directives, the first patch
adds a convenience config symbol so the existing CONFIG_IS_ENABLED()
helper can be used - which then, as a bonus, ends up reducing said maze.
Should others need to enable CONFIG_SPL_SAVEENV with one of the
remaining backends that currently ignore it, they can most likely use
a similar approach as done for sf.c here.
Difference from v1 is that patches for ext4.c and fat.c have been
dropped, as well as a patch that introduced a ENV_SAVE_PTR() macro -
and the sf.c patch consequently doesn't use that macro but just uses
'CONFIG_IS_ENABLED(SAVEENV) ? (x) : NULL' directly. Also, the series
is no longer branded as a "cleanup" - it intentionally changes the
generated code for certain configurations, but it does so in way that
happens to reduce ifdeffery.
=== testing ===
This has been run-time tested on a mpc8309-derived board to verify
that saving the environment does indeed work in SPL with these patches
applied.
As far as I can tell, the only in-tree defconfig that sets both
SPL_ENV_IS_IN_SPI_FLASH and SPL_SAVEENV is display5_defconfig, which
also happens to be the only one setting SPL_SAVEENV at all. Let's see
how these patches affect that:
# avoid differences due to different git commit or wallclock time
$ export SOURCE_DATE_EPOCH=1585252702
$ echo 'test' > .scmversion
$ export ARCH=arm
$ export CROSS_COMPILE=arm-linux-gnueabi-
$ git checkout master ; make display5_defconfig ; make -j8
$ cp u-boot u-boot.1 ; cp spl/u-boot-spl u-boot-spl.1
$ git checkout sf-spl-saveenv ; make display5_defconfig ; make -j8
$ cp u-boot u-boot.2 ; cp spl/u-boot-spl u-boot-spl.2
$ size u-boot{,-spl}.{1,2}
textdata bss dec hex filename
377468 24620 66164 468252 7251c u-boot.1
377468 24620 66164 468252 7251c u-boot.2
584112020 116 60547ec83 u-boot-spl.1
599762028 116 62120f2a8 u-boot-spl.2
So U-Boot proper is not affected (the files even yield identical
objdump -d output), while the SPL grows by the ~1.5K necessary to
implement saving the environment. Borrowing the bloat-o-meter script
from linux, we can also see the functions/data items that are now
included:
../linux/scripts/bloat-o-meter u-boot-spl.1 u-boot-spl.2
add/remove: 11/0 grow/shrink: 0/1 up/down: 1340/-24 (1316)
Function old new delta
hexport_r - 408+408
env_sf_save- 332+332
qsort - 144+144
match_entry- 124+124
env_export - 100+100
match_string - 92 +92
strstr - 64 +64
setup_flash_device - 56 +56
cmpkey - 12 +12
env_offset - 4 +4
env_new_offset - 4 +4
env_sf_load 184 160 -24
Total: Before=52986, After=54302, chg +2.48%
[The difference between 1316 and 62120-60547=1573 is most likely due
to string literals that are referenced from the above functions].
Now, to check that other storage backends are not affected, and also
that nothing (neither U-Boot or SPL) changes for ENV_IS_IN_SPI_FLASH
when CONFIG_SPL_SAVEENV=n, I have repeated the above with
am335x_shc_netboot_defconfig (MMC), pengwyn_defconfig (NAND),
mccmon6_sd_defconfig (FLASH),
ls1046ardb_qspi_spl_defconfig (SPI_FLASH):
$ for c in am335x_shc_netboot_defconfig pengwyn_defconfig mccmon6_sd_defconfig
ls1046ardb_qspi_spl_defconfig ; do
[ $c = "ls1046ardb_qspi_spl_defconfig" ] && CROSS_COMPILE=aarch64-linux-gnu-
|| CROSS_COMPILE=arm-linux-gnueabi-
for b in master sf-spl-saveenv ; do
git checkout $b ;
make $c && make -j8 ;
cp u-boot u-boot.$b && cp spl/u-boot-spl u-boot-spl.$b ;
done ;
for x in u-boot u-boot-spl ; do
diff -u <(objdump -d $x.master | sed -e '/file format/d') <(objdump -d
$x.sf-spl-saveenv | sed -e '/file format/d') > $c.$x.diff ;
done ;
done
$ ls -l *.diff
-rw-rw-r-- 1 ravi ravi 0 Mar 26 23:20 am335x_shc_netboot_defconfig.u-boot.diff
-rw-rw-r-- 1 ravi ravi 0 Mar 26 23:20
am335x_shc_netboot_defconfig.u-boot-spl.diff
-rw-rw-r-- 1 ravi ravi 0 Mar 26 23:20 ls1046ardb_qspi_spl_defconfig.u-boot.diff
-rw-rw-r-- 1 rav
[PATCH v2 1/2] env: add SAVEENV as an alias of the CMD_SAVEENV symbol
Currently, quite a few storage drivers currently do not honour SPL_SAVEENV. That is, whether or not one enables CONFIG_SPL_SAVEENV, the backend drivers do not provide the .save method. Witness env/fat.c:#ifdef CONFIG_SPL_BUILD ... env/fat.c-#else env/fat.c-# define LOADENV env/fat.c:# if defined(CONFIG_CMD_SAVEENV) env/fat.c:# define CMD_SAVEENV env/fat.c-# endif env/fat.c-#endif env/fat.c- env/fat.c:#ifdef CMD_SAVEENV env/fat.c-static int env_fat_save(void) env/flash.c:#ifndef CONFIG_SPL_BUILD env/flash.c:# if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_FLASH) env/flash.c:# define CMD_SAVEENV ... env/flash.c:#ifdef CMD_SAVEENV env/flash.c-static int env_flash_save(void) env/mmc.c:#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_SPL_BUILD) env/mmc.c-static inline int write_env(struct mmc *mmc, unsigned long size, env/nand.c:#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND) && \ env/nand.c: !defined(CONFIG_SPL_BUILD) env/nand.c:#define CMD_SAVEENV ... env/nand.c:#ifdef CMD_SAVEENV env/nand.c-/* env/nand.c- * The legacy NAND code saved the environment in the first NAND device i.e., env/nand.c- * nand_dev_desc + 0. This is also the behaviour using the new NAND code. env/nand.c- */ env/nand.c-static int writeenv(size_t offset, u_char *buf) env/sf.c:#ifndef CONFIG_SPL_BUILD env/sf.c:#define CMD_SAVEENV env/sf.c-#define INITENV env/sf.c-#endif ... env/sf.c:#ifdef CMD_SAVEENV env/sf.c-static int env_sf_save(void) In all these cases, the mere presence of CONFIG_SPL_BUILD means the save method does not get built. Now, it is currently a bit awkward to write a proper test for whether saving the environment is enabled in the current context; something like #if (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_CMD_SAVEENV)) || \ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SAVEENV)) But we already have a rather elegant mechanism that implicitly does the CONFIG_SPL_BUILD tests, namely CONFIG_IS_ENABLED(). Using that requires that the controlling config symbols follow a strict pattern: FOO for U-Boot proper, SPL_FOO for SPL. This patch introduces CONFIG_SAVEENV as an alias for CONFIG_CMD_SAVEENV. That way, the above can simply be written #if CONFIG_IS_ENABLED(SAVEENV) and moreover, CONFIG_IS_ENABLED(SAVEENV) can also be used in C code, avoiding ifdeffery and providing more compile testing. Signed-off-by: Rasmus Villemoes --- v2: Expand commit message, explain why one needs a new config symbol in order to use CONFIG_IS_ENABLED, and demonstrate how many of the storage drivers don't compile their .save method when CONFIG_SPL_BUILD. The patch itself is the same. env/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/env/Kconfig b/env/Kconfig index 0d6f559b39..969308fe6c 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -3,6 +3,9 @@ menu "Environment" config ENV_SUPPORT def_bool y +config SAVEENV + def_bool y if CMD_SAVEENV + config ENV_IS_NOWHERE bool "Environment is not stored" default y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \ -- 2.23.0
[PATCH 1/2] net: rt8169: WAR for DHCP not getting IP after kernel boot/reboot
From: Tom Warren
This is a WAR for DHCP failure after rebooting from the L4T kernel. The
r8169.c kernel driver is setting bit 19 of the rt816x HW register 0xF0,
which goes by FuncEvent and MISC in various driver source/datasheets.
That bit is called RxDv_Gated_En in the r8169.c kernel driver. Clear it
here at the end of probe to ensure that U-Boot can get an IP assigned
via DHCP.
Signed-off-by: Tom Warren
---
drivers/net/rtl8169.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 5ccdfdd..ff89e28 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -237,6 +237,9 @@ enum RTL8169_register_content {
/*_TBICSRBit*/
TBILinkOK = 0x0200,
+
+ /* FuncEvent/Misc */
+ RxDv_Gated_En = 0x8,
};
static struct {
@@ -1207,6 +1210,19 @@ static int rtl8169_eth_probe(struct udevice *dev)
return ret;
}
+ /*
+* WAR for DHCP failure after rebooting from kernel.
+* Clear RxDv_Gated_En bit which was set by kernel driver.
+* Without this, U-Boot can't get an IP via DHCP.
+* Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
+* the r8169.c kernel driver.
+*/
+
+ u32 val = RTL_R32(FuncEvent);
+ debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
+ val &= ~RxDv_Gated_En;
+ RTL_W32(FuncEvent, val);
+
return 0;
}
--
1.8.2.1.610.g562af5b
---
This email message is for the sole use of the intended recipient(s) and may
contain
confidential information. Any unauthorized review, use, disclosure or
distribution
is prohibited. If you are not the intended recipient, please contact the
sender by
reply email and destroy all copies of the original message.
---
[PATCH 2/2] tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards
From: Tom Warren This allows the user to set $serverip in the environment before executing a DHCP request. If they do, U-Boot will use that IP rather than using the IP in the DHCP response. Signed-off-by: Tom Warren Acked-by: Stephen Warren --- configs/e2220-1170_defconfig | 1 + configs/p2371-_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/p2571_defconfig | 1 + configs/p2771--000_defconfig | 1 + configs/p2771--500_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index 1639040..951ed1d 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -43,3 +43,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2371-_defconfig b/configs/p2371-_defconfig index 2070199..7081719 100644 --- a/configs/p2371-_defconfig +++ b/configs/p2371-_defconfig @@ -44,3 +44,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 8c808ae..c70217c 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -52,3 +52,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 721c5c5..43c24b8 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -44,3 +44,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2771--000_defconfig b/configs/p2771--000_defconfig index e347a77..8bf8419 100644 --- a/configs/p2771--000_defconfig +++ b/configs/p2771--000_defconfig @@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_POSITION_INDEPENDENT=y +CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/configs/p2771--500_defconfig b/configs/p2771--500_defconfig index 0803b26..1f40333 100644 --- a/configs/p2771--500_defconfig +++ b/configs/p2771--500_defconfig @@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_POSITION_INDEPENDENT=y +CONFIG_BOOTP_PREFER_SERVERIP=y -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 0/2] net: tegra: Misc network fixes
From: Tom Warren These two patches are from downstream Tegra L4T U-Boot. Tom Warren (2): net: rt8169: WAR for DHCP not getting IP after kernel boot/reboot tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards configs/e2220-1170_defconfig | 1 + configs/p2371-_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/p2571_defconfig | 1 + configs/p2771--000_defconfig | 1 + configs/p2771--500_defconfig | 1 + drivers/net/rtl8169.c| 16 7 files changed, 22 insertions(+) -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 3/3] qspi: t210: Use dev_read calls to get FDT data like base, freq
From: Tom Warren
This Tegra QSPI driver hadn't been brought up to date with how
DM drivers are fetching data from the FDT now, and was pulling
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
to work the same way it does in the tegra114 SPI driver, using
dev_read_ functions.
Signed-off-by: Tom Warren
---
Changes in v2:
- New
drivers/spi/tegra210_qspi.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index 4284ea9..466d572 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -2,7 +2,7 @@
/*
* NVIDIA Tegra210 QSPI controller driver
*
- * (C) Copyright 2015-2019 NVIDIA Corporation
+ * (C) Copyright 2015-2020 NVIDIA Corporation
*
*/
@@ -97,10 +97,8 @@ struct tegra210_qspi_priv {
static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
@@ -110,9 +108,9 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice
*bus)
}
/* Use 500KHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
50);
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ plat->deactivate_delay_us = dev_read_u32_default(bus,
"spi-deactivate-delay", 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d,
deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
--
1.8.2.1.610.g562af5b
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[PATCH 1/3] qspi: t210: Fix claim_bus's use of the wrong bus/device
From: Tom Warren
claim_bus() is passed a udevice *dev, which is the bus device's parent.
In this driver, claim_bus assumed it was the bus, which caused the
'priv' info pointer to be wrong, and periph_id was incorrect. This in
turn caused the periph clock call to assign the wrong clock (PLLM
instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
working w/this errant clock, but it was moot as QSPI wasn't active
unless you probed it, and that wasn't happening until I posted a patch
to enable env save to QSPI for Nano (coming soon).
Signed-off-by: Tom Warren
---
Changes in v2:
- None
drivers/spi/tegra210_qspi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index d82ecaa..2a77126 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -2,7 +2,8 @@
/*
* NVIDIA Tegra210 QSPI controller driver
*
- * (C) Copyright 2015 NVIDIA Corporation
+ * (C) Copyright 2015-2019 NVIDIA Corporation
+ *
*/
#include
@@ -137,8 +138,9 @@ static int tegra210_qspi_probe(struct udevice *bus)
return 0;
}
-static int tegra210_qspi_claim_bus(struct udevice *bus)
+static int tegra210_qspi_claim_bus(struct udevice *dev)
{
+ struct udevice *bus = dev->parent;
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
struct qspi_regs *regs = priv->regs;
--
1.8.2.1.610.g562af5b
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[PATCH 0/3 v2] qspi: t210: fix claim_bus and clock/tap delays
From: Tom Warren These patches fix a couple of problems encountered in the T210 QSPI driver discovered during Jetson Nano bringup, and adapt the driver to upstream DM norms. Tom Warren (3): qspi: t210: Fix claim_bus's use of the wrong bus/device qspi: t210: Fix QSPI clock and tap delays qspi: t210: Use dev_read calls to get FDT data like base, freq drivers/spi/tegra210_qspi.c | 33 +++-- 1 file changed, 19 insertions(+), 14 deletions(-) -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 2/3] qspi: t210: Fix QSPI clock and tap delays
From: Tom Warren
When claim_bus was setting the clock, it reset the QSPI controller,
which wipes out any tap delays set by previous bootloaders (nvtboot,
CBoot for example on Nano). Instead of doing that in claim_bus, which
gets called a lot, moved clock setting to probe(), and set tap delays
there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
save works reliably again.
Signed-off-by: Tom Warren
---
Changes in v2:
- None
drivers/spi/tegra210_qspi.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index 2a77126..4284ea9 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -42,10 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_CMD1_BITLEN_SHIFT 0
/* COMMAND2 */
-#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
-#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASKGENMASK(11,6)
-#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
-#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASKGENMASK(5,0)
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASKGENMASK(14,10)
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASKGENMASK(7,0)
/* TRANSFER STATUS */
#define QSPI_XFER_STS_RDY BIT(30)
@@ -127,14 +127,22 @@ static int tegra210_qspi_probe(struct udevice *bus)
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
priv->regs = (struct qspi_regs *)plat->base;
+ struct qspi_regs *regs = priv->regs;
priv->last_transaction_us = timer_get_us();
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
+ debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
priv->periph_id);
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
+ /* Set tap delays here, clock change above resets QSPI controller */
+ u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
+ (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
+ writel(reg, ®s->command2);
+ debug("%s: COMMAND2 = %08x\n", __func__, readl(®s->command2));
+
return 0;
}
@@ -144,9 +152,6 @@ static int tegra210_qspi_claim_bus(struct udevice *dev)
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
struct qspi_regs *regs = priv->regs;
- /* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
-
debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
/* Set master mode and sw controlled CS */
--
1.8.2.1.610.g562af5b
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Re: [PATCH 2/7] uart: pl011: Add proper DM clock support
On Wed, Mar 25, 2020 at 3:47 PM Andre Przywara wrote: > Even though the PL011 UART driver claims to be DM compliant, it does not > really a good job with parsing DT nodes. U-Boot seems to adhere to a > non-standard binding, either requiring to have a "skip-init" property in > the node, or to have an extra "clock" property holding the base > *frequency* value for the baud rate generator. > DTs in the U-Boot tree seem to have been hacked to match this > requirement. > > The official binding does not mention any of these properties, instead > recommends a standard "clocks" property to point to the baud base clock. > > Some boards use simple "fixed-clock" providers, which U-Boot readily > supports, so let's add some simple DM clock code to the PL011 driver to > learn the rate of the first clock, as described by the official binding. > > These clock nodes seem to be not ready very early in the boot process, > so provide a fallback value, by re-using the already existing > CONFIG_PL011_CLOCK variable. > > Signed-off-by: Andre Przywara A good start for other platforms to follow. Reviewed-by: Linus Walleij Yours, Linus Walleij
[PATCH 1/2] mmc: t210: Add autocal and tap/trim updates for SDMMC1/3
From: Tom Warren
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.
Signed-off-by: Tom Warren
---
Changes for v2:
- Added clocks.h include for TEGRA30 to fix T30 32-bit builds
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 20 +--
drivers/mmc/tegra_mmc.c | 84 ++---
2 files changed, 92 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a2b6f63..a8bfa46 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -2,7 +2,7 @@
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation
*/
#ifndef __TEGRA_MMC_H_
@@ -52,7 +52,7 @@ struct tegra_mmc {
unsigned char admaerr;/* offset 54h */
unsigned char res4[3];/* RESERVED, offset 55h-57h */
unsigned long admaaddr; /* offset 58h-5Fh */
- unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
+ unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
unsigned short slotintstatus; /* offset FCh */
unsigned short hcver; /* HOST Version */
unsigned intvenclkctl; /* _VENDOR_CLOCK_CNTRL_0,100h */
@@ -127,11 +127,23 @@ struct tegra_mmc {
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE(1 << 1)
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
#define MEMCOMP_PADCTRL_VREF 7
-#define AUTO_CAL_ENABLED (1 << 29)
+#define AUTO_CAL_ENABLE(1 << 29)
+#if defined(CONFIG_TEGRA210)
+#define AUTO_CAL_ACTIVE(1 << 31)
+#define AUTO_CAL_START (1 << 31)
+#define AUTO_CAL_PD_OFFSET (0x7D << 8)
+#define AUTO_CAL_PU_OFFSET (0 << 0)
+#define IO_TRIM_BYPASS_MASK(1 << 2)
+#define TRIM_VAL_SHIFT 24
+#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT)
+#define TAP_VAL_SHIFT 16
+#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT)
+#else
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
+#endif
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index f022e93..73ac58c 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -3,7 +3,7 @@
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang
* Jaehoon Chung
- * Portions Copyright 2011-2016 NVIDIA Corporation
+ * Portions Copyright 2011-2019 NVIDIA Corporation
*/
#include
@@ -15,6 +15,9 @@
#include
#include
#include
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
+#include
+#endif
struct tegra_mmc_plat {
struct mmc_config cfg;
@@ -30,6 +33,7 @@ struct tegra_mmc_priv {
struct gpio_desc wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
+ int mmc_id; /* peripheral id */
};
static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
@@ -446,16 +450,19 @@ static int tegra_mmc_set_ios(struct udevice *dev)
static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
{
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
u32 val;
+ u16 clk_con;
+ int timeout;
+ int id = priv->mmc_id;
- debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
+ debug("%s: sdmmc address = %p, id = %d\n", __func__,
+ priv->reg, id);
/* Set the pad drive strength for SDMMC1 or 3 only */
- if (priv->reg != (void *)0x7800 &&
- priv->reg != (void *)0x78000400) {
+ if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
- __func__);
+ __func__);
return;
}
@@ -464,11 +471,65 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv
*priv)
val |= MEMCOMP_PADCTRL_VREF;
writel(val, &priv->reg->sdmemcmppadctl);
+ /* Disable SD Clock Enable before running auto-cal as per TRM */
+ clk_con = readw(&priv->reg->clkcon);
+ debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
+ clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
+ writew(clk_con, &priv->reg->clkcon);
+
val = readl(&priv->reg->autocal
[PATCH 2/2] mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect
From: Tom Warren
According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is <= 400KHz. Note that as far as I can
tell, the other requests for clocks in the Tegra MMC driver result in
valid SD clocks.
Signed-off-by: Tom Warren
---
Changes for v2:
- None
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 +-
drivers/mmc/tegra_mmc.c | 18 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a8bfa46..70dcf4a 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -130,9 +130,9 @@ struct tegra_mmc {
/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
#define MEMCOMP_PADCTRL_VREF 7
#define AUTO_CAL_ENABLE(1 << 29)
-#if defined(CONFIG_TEGRA210)
#define AUTO_CAL_ACTIVE(1 << 31)
#define AUTO_CAL_START (1 << 31)
+#if defined(CONFIG_TEGRA210)
#define AUTO_CAL_PD_OFFSET (0x7D << 8)
#define AUTO_CAL_PU_OFFSET (0 << 0)
#define IO_TRIM_BYPASS_MASK(1 << 2)
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 73ac58c..03110ba 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -376,6 +376,24 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv
*priv, uint clock)
rate = clk_set_rate(&priv->clk, clock);
div = (rate + clock - 1) / clock;
+
+#if defined(CONFIG_TEGRA210)
+ if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 40) {
+ /* clock_adjust_periph_pll_div() chooses a 'bad' clock
+* on SDMMC1 T210, so skip it here and force a clock
+* that's been spec'd in the table in the TRM for
+* card-detect (400KHz).
+*/
+ uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
+ CLOCK_ID_PERIPH, 24727273, NULL);
+ div = 62;
+
+ debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve
%dHz card clock ...\n",
+ __func__, effective_rate, div, clock);
+ } else
+ clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
clock,
+ &div);
+#endif
debug("div = %d\n", div);
writew(0, &priv->reg->clkcon);
--
1.8.2.1.610.g562af5b
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[PATCH 0/2 v2] mmc: t210: fix autocal and 400KHz clock
From: Tom Warren These two patches contain fixes for two issues found on T210 MMC during Nano bringup. Autocal wasn't being done correctly as per the TRM, and the 375/400KHz MMC card detect clock wasn't using the correct parameters as per the TRM. Tom Warren (2): mmc: t210: Add autocal and tap/trim updates for SDMMC1/3 mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect arch/arm/include/asm/arch-tegra/tegra_mmc.h | 20 -- drivers/mmc/tegra_mmc.c | 102 +--- 2 files changed, 110 insertions(+), 12 deletions(-) -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
Re: [PATCH 1/7] arm: juno: Fix Juno address variables
On Wed, Mar 25, 2020 at 3:47 PM Andre Przywara wrote: > The U-Boot documentation explains that variables ending with "_r" hold > addresses in DRAM, while those without that ending point to flash/ROM. > The default variables for the Juno board pointing to the kernel and DTB > load addresses were not complying with this scheme: they lack the > extension, but point to DRAM. This is particularly confusing since the > Juno board features parallel NOR flash, so there *is* a memory mapped > NOR address holding a DTB, for instance. > > Fix the variables to use the proper names. On the way adjust the FDT > load address to be situated *before* the kernel, since users happened > to overwrite the DTB by the kernel clearing its .BSS section during > initialisation. > > That fixes loading debug kernels, which happened to overwrite the DTB on > certain setups. > > Signed-off-by: Andre Przywara > Reviewed-by: Liviu Dudau Makes perfect sense. Reviewed-by: Linus Walleij Yours, Linus Walleij
[PATCH 1/3] ARM: tegra: p2771-0000: enable PIE relocation
From: Vishruth U-Boot is configured to build as position independent executable. Enable relocation of RELA section required to work with different load addresses. Signed-off-by: Vishruth Signed-off-by: Tom Warren --- configs/p2771--000_defconfig | 1 + configs/p2771--500_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/p2771--000_defconfig b/configs/p2771--000_defconfig index 06f12e2..e347a77 100644 --- a/configs/p2771--000_defconfig +++ b/configs/p2771--000_defconfig @@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_POSITION_INDEPENDENT=y diff --git a/configs/p2771--500_defconfig b/configs/p2771--500_defconfig index 1a14a92..0803b26 100644 --- a/configs/p2771--500_defconfig +++ b/configs/p2771--500_defconfig @@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_POSITION_INDEPENDENT=y -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH 2/3] fdt: Fix 'system' command
From: Tom Warren
'fdt systemsetup' wasn't working, due to the fact that the 'set' command
was being parsed in do_fdt() by only testing for the leading 's' instead
of "se", which kept the "sys" test further down from executing. Changed
to test for "se" instead, now 'fdt systemsetup' works (to test the
ft_system_setup proc w/o having to boot a kernel).
Signed-off-by: Tom Warren
---
cmd/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 25a6ed4..36cc726 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -286,7 +286,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
/*
* Set the value of a property in the working_fdt.
*/
- } else if (argv[1][0] == 's') {
+ } else if (strncmp(argv[1], "se", 2) == 0) {
char *pathp;/* path */
char *prop; /* property */
int nodeoffset;/* node offset from libfdt */
--
1.8.2.1.610.g562af5b
---
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contain
confidential information. Any unauthorized review, use, disclosure or
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is prohibited. If you are not the intended recipient, please contact the
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[PATCH 3/3] ARM: tegra: p2371-2180: add I2C nodes to DT
From: Stephen Warren
This adds to the DT the I2C controllers that connect to the board ID EEPROM,
camera board EEPROM, etc. With this change, you can now probe all I2C devices
on a TX1 board.
Signed-off-by: Tom Warren
---
arch/arm/dts/tegra210-p2371-2180.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/dts/tegra210-p2371-2180.dts
b/arch/arm/dts/tegra210-p2371-2180.dts
index c2f497c..d982b5f 100644
--- a/arch/arm/dts/tegra210-p2371-2180.dts
+++ b/arch/arm/dts/tegra210-p2371-2180.dts
@@ -12,6 +12,9 @@
aliases {
i2c0 = "/i2c@7000d000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c5 = "/i2c@546c0c00";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b";
usb0 = "/usb@7d00";
@@ -33,6 +36,11 @@
};
};
+ i2c@546c0c00 {
+ status = "okay";
+ clock-frequency = <40>;
+ };
+
padctl@7009f000 {
pinctrl-0 = <&padctl_default>;
pinctrl-names = "default";
@@ -85,6 +93,16 @@
non-removable;
};
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <40>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <40>;
+ };
+
i2c@7000d000 {
status = "okay";
clock-frequency = <40>;
--
1.8.2.1.610.g562af5b
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[PATCH 0/3] Misc fixes for Tegra
From: Tom Warren These fixes originated on our downstream L4T U-Boot, and include fdt, pll and code relocation changes. Stephen Warren (1): ARM: tegra: p2371-2180: add I2C nodes to DT Tom Warren (1): fdt: Fix 'system' command Vishruth (1): ARM: tegra: p2771-: enable PIE relocation arch/arm/dts/tegra210-p2371-2180.dts | 18 ++ cmd/fdt.c| 2 +- configs/p2771--000_defconfig | 1 + configs/p2771--500_defconfig | 1 + 4 files changed, 21 insertions(+), 1 deletion(-) -- 1.8.2.1.610.g562af5b --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ---
[PATCH] mtd: spi: Add Macronix MX25U3235F device
From: Tom Warren
Add Macronix MX25U3235F flash device description.
This is a 4MiB part.
Signed-off-by: Tom Warren
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 973b6f8..abdf560 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -147,6 +147,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
+ { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
--
1.8.2.1.610.g562af5b
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distribution
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---
[PATCH] ARM: dts: stm32: Use DT alias for the configuration EEPROM
Use DT /aliases node to establish a stable phandle to the configuration
EEPROM. This permits the configuration EEPROM to be moved e.g. to a
different address or a different bus. Adjust the board code to handle
new phandle lookup.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp15xx-dhcom.dtsi | 6 +-
board/dhelectronics/dh_stm32mp1/board.c | 15 +++
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
index bed69c97b6..e5be0a79ac 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
@@ -10,6 +10,10 @@
#include
/ {
+ aliases {
+ eeprom0 = &eeprom0;
+ };
+
memory@c000 {
device_type = "memory";
reg = <0xC000 0x4000>;
@@ -187,7 +191,7 @@
};
};
- eeprom@50 {
+ eeprom0: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
diff --git a/board/dhelectronics/dh_stm32mp1/board.c
b/board/dhelectronics/dh_stm32mp1/board.c
index be55242799..0096046050 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -78,22 +78,21 @@ DECLARE_GLOBAL_DATA_PTR;
int setup_mac_address(void)
{
- struct udevice *dev;
- ofnode eeprom;
unsigned char enetaddr[6];
- int ret;
+ struct udevice *dev;
+ int off, ret;
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
if (ret)/* ethaddr is already set */
return 0;
- eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50");
- if (!ofnode_valid(eeprom)) {
- printf("Invalid hardware path to EEPROM!\n");
- return -ENODEV;
+ off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+ if (off < 0) {
+ printf("%s: No eeprom0 path offset\n", __func__);
+ return off;
}
- ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
+ ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
if (ret) {
printf("Cannot find EEPROM!\n");
return ret;
--
2.25.1
[PATCH] ARM: dts: stm32: Add configuration EEPROM on AV96
The board has an EEPROM on the same I2C bus as PMIC, at address 0x53.
The EEPROM contains the board MAC address.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157a-avenger96.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts
b/arch/arm/dts/stm32mp157a-avenger96.dts
index c8846e4180..43ffbe9f9a 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -275,6 +275,12 @@
status = "disabled";
};
};
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
};
&iwdg2 {
--
2.25.1
Re: [PATCH 2/7] uart: pl011: Add proper DM clock support
Hi Andre,
On Thu, 26 Mar 2020 at 11:06, André Przywara wrote:
>
> On 26/03/2020 16:20, Simon Glass wrote:
>
> Hi Simon,
>
> > On Wed, 25 Mar 2020 at 08:47, Andre Przywara wrote:
> >>
> >> Even though the PL011 UART driver claims to be DM compliant, it does not
> >> really a good job with parsing DT nodes. U-Boot seems to adhere to a
> >> non-standard binding, either requiring to have a "skip-init" property in
> >> the node, or to have an extra "clock" property holding the base
> >> *frequency* value for the baud rate generator.
> >> DTs in the U-Boot tree seem to have been hacked to match this
> >> requirement.
> >>
> >> The official binding does not mention any of these properties, instead
> >> recommends a standard "clocks" property to point to the baud base clock.
> >>
> >> Some boards use simple "fixed-clock" providers, which U-Boot readily
> >> supports, so let's add some simple DM clock code to the PL011 driver to
> >> learn the rate of the first clock, as described by the official binding.
> >>
> >> These clock nodes seem to be not ready very early in the boot process,
> >> so provide a fallback value, by re-using the already existing
> >> CONFIG_PL011_CLOCK variable.
> >>
> >> Signed-off-by: Andre Przywara
> >> ---
> >> drivers/serial/serial_pl01x.c | 10 +-
> >> 1 file changed, 9 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
> >> index 2a5f256184..1ab0ccadb2 100644
> >> --- a/drivers/serial/serial_pl01x.c
> >> +++ b/drivers/serial/serial_pl01x.c
> >> @@ -12,6 +12,7 @@
> >>
> >> #include
> >> #include
> >> +#include
> >> #include
> >> #include
> >> #include
> >> @@ -340,14 +341,21 @@ static const struct udevice_id pl01x_serial_id[] ={
> >> int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
> >> {
> >> struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
> >> + struct clk clk;
> >> fdt_addr_t addr;
> >> + int ret;
> >>
> >> addr = devfdt_get_addr(dev);
> >> if (addr == FDT_ADDR_T_NONE)
> >> return -EINVAL;
> >>
> >> plat->base = addr;
> >> - plat->clock = dev_read_u32_default(dev, "clock", 1);
> >> + plat->clock = dev_read_u32_default(dev, "clock",
> >> CONFIG_PL011_CLOCK);
> >
> > is this needed?
>
> This is to provide the existing behaviour as a fallback. Some SoCs have
> a complex clock providing the baud rate clock (HiKey 960, FSL LS2080a),
> which U-Boot doesn't suport. I'd rather not break them, but also don't
> really want to provide a clock driver ;-)
>
> Also this mimics the !DM_SERIAL behaviour, which sets this clock rate
> based on Kconfig, again as a fallback. I needed that because I think the
> clock driver wasn't ready that early. It's a bit hard to confirm without
> serial output ;-)
>
> So the order should be:
> - If there is a clocks property and we support that clock provider
> (fixed-clock), then use that value.
> - If not, check for a "clock" property in the DT node and use that value.
> - If there is no "clock property", use the Kconfig variable.
>
> Just written the other way around in the code.
>
> Does this make sense?
Hmm it might make more sense to migrate the boards?
Reviewed-by: Simon Glass
Regards,
Simon
Re: [PATCH] test/py: mmc: Fix 'mmc info' testcase
On Thu, 26 Mar 2020 at 11:08, Harald Seiler wrote:
>
> Commit 41e30dcf8796 ("cmd: mmc: Make Mode: printout consistent") fixed
> the layout of `mmc info` output. Reflect this change in the respective
> testcase.
>
> Also fix a typo in the documentation.
>
> Fixes: 41e30dcf8796 ("cmd: mmc: Make Mode: printout consistent")
> Signed-off-by: Harald Seiler
> ---
> test/py/tests/test_mmc_rd.py | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass
[PATCH] ARM: dts: stm32: Add QSPI NOR on AV96
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it
into the DT.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157a-avenger96.dts | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts
b/arch/arm/dts/stm32mp157a-avenger96.dts
index e7505c7596..c8846e4180 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -20,6 +20,7 @@
mmc0 = &sdmmc1;
serial0 = &uart4;
serial1 = &uart7;
+ spi0 = &qspi;
};
chosen {
@@ -286,6 +287,25 @@
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+ reg = <0x58003000 0x1000>, <0x7000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: mx66l51235l@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <10800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
&rng1 {
status = "okay";
};
--
2.25.1
[PATCH 1/2] ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7
Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157-pinctrl.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi
b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index 81a363d93d..e25c44760e 100644
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -907,6 +907,27 @@
};
};
+ sdmmc2_d47_pins_b: sdmmc2-d47-1 {
+ pins {
+ pinmux = ,
/* SDMMC2_D4 */
+,
/* SDMMC2_D5 */
+,
/* SDMMC2_D6 */
+;
/* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
+ pins {
+ pinmux = , /* SDMMC2_D4 */
+, /* SDMMC2_D5 */
+, /* SDMMC2_D6 */
+; /* SDMMC2_D7 */
+ };
+ };
+
spdifrx_pins_a: spdifrx-0 {
pins {
pinmux = ;
/* SPDIF_IN1 */
--
2.25.1
[PATCH 2/2] ARM: dts: stm32: Repair SDMMC2 operation
The eMMC uses different pinmux for the top four data lines, use such
a pinmux, otherwise it takes a very long time until the test for 8bit
operation times out. And this is the correct pinmux per schematic too.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157a-avenger96.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts
b/arch/arm/dts/stm32mp157a-avenger96.dts
index 3065593bf2..e7505c7596 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -310,7 +310,7 @@
&sdmmc2 {
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
non-removable;
no-sd;
no-sdio;
--
2.25.1
[PATCH] ARM: dts: stm32: Repair AV96 SD1 boot
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4
("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{};
became pins1{};pins2{};, however the SPL extras were not updated to reflect
that change. Fix this.
This fixes booting from SD1 X9 slot on the AV96 board.
Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4")
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
index d6dc746365..8dcd8866e8 100644
--- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
@@ -152,7 +152,10 @@
&sdmmc1_dir_pins_a {
u-boot,dm-spl;
- pins {
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
u-boot,dm-spl;
};
};
--
2.25.1
Re: [PATCH 1/3] travis-ci: Add EFI grub2 and fit image configuration for qemu-riscv64
On 3/26/20 10:05 AM, Bin Meng wrote: > This adds EFI grub2 and fit image configuration for qemu-riscv64 > target used for test. I've applied the series.
Re: [PATCH] test/py: mmc: Fix 'mmc info' testcase
On 3/26/20 11:07 AM, Harald Seiler wrote:
> Commit 41e30dcf8796 ("cmd: mmc: Make Mode: printout consistent") fixed
> the layout of `mmc info` output. Reflect this change in the respective
> testcase.
>
> Also fix a typo in the documentation.
Acked-by: Stephen Warren
I guess I don't have these tests enabled, which is why my test system
didn't catch this.
[PATCH] test/py: mmc: Fix 'mmc info' testcase
Commit 41e30dcf8796 ("cmd: mmc: Make Mode: printout consistent") fixed
the layout of `mmc info` output. Reflect this change in the respective
testcase.
Also fix a typo in the documentation.
Fixes: 41e30dcf8796 ("cmd: mmc: Make Mode: printout consistent")
Signed-off-by: Harald Seiler
---
test/py/tests/test_mmc_rd.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/test/py/tests/test_mmc_rd.py b/test/py/tests/test_mmc_rd.py
index a25aa5f6f78e..ea652f913618 100644
--- a/test/py/tests/test_mmc_rd.py
+++ b/test/py/tests/test_mmc_rd.py
@@ -56,7 +56,7 @@ env__mmc_dev_configs = (
'info_mode': ???,
'info_buswidth': ???.
},
-}
+)
# Configuration data for test_mmc_rd; defines regions of the MMC (entire
# devices, or ranges of sectors) which can be read:
@@ -210,7 +210,7 @@ def test_mmc_info(u_boot_console, env__mmc_dev_config):
assert good_response in response
good_response = "Bus Speed: %s" % info_speed
assert good_response in response
-good_response = "Mode : %s" % info_mode
+good_response = "Mode: %s" % info_mode
assert good_response in response
good_response = "Bus Width: %s" % info_buswidth
assert good_response in response
--
2.25.2
Re: [PATCH 2/7] uart: pl011: Add proper DM clock support
On 26/03/2020 16:20, Simon Glass wrote:
Hi Simon,
> On Wed, 25 Mar 2020 at 08:47, Andre Przywara wrote:
>>
>> Even though the PL011 UART driver claims to be DM compliant, it does not
>> really a good job with parsing DT nodes. U-Boot seems to adhere to a
>> non-standard binding, either requiring to have a "skip-init" property in
>> the node, or to have an extra "clock" property holding the base
>> *frequency* value for the baud rate generator.
>> DTs in the U-Boot tree seem to have been hacked to match this
>> requirement.
>>
>> The official binding does not mention any of these properties, instead
>> recommends a standard "clocks" property to point to the baud base clock.
>>
>> Some boards use simple "fixed-clock" providers, which U-Boot readily
>> supports, so let's add some simple DM clock code to the PL011 driver to
>> learn the rate of the first clock, as described by the official binding.
>>
>> These clock nodes seem to be not ready very early in the boot process,
>> so provide a fallback value, by re-using the already existing
>> CONFIG_PL011_CLOCK variable.
>>
>> Signed-off-by: Andre Przywara
>> ---
>> drivers/serial/serial_pl01x.c | 10 +-
>> 1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
>> index 2a5f256184..1ab0ccadb2 100644
>> --- a/drivers/serial/serial_pl01x.c
>> +++ b/drivers/serial/serial_pl01x.c
>> @@ -12,6 +12,7 @@
>>
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -340,14 +341,21 @@ static const struct udevice_id pl01x_serial_id[] ={
>> int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
>> {
>> struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
>> + struct clk clk;
>> fdt_addr_t addr;
>> + int ret;
>>
>> addr = devfdt_get_addr(dev);
>> if (addr == FDT_ADDR_T_NONE)
>> return -EINVAL;
>>
>> plat->base = addr;
>> - plat->clock = dev_read_u32_default(dev, "clock", 1);
>> + plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
>
> is this needed?
This is to provide the existing behaviour as a fallback. Some SoCs have
a complex clock providing the baud rate clock (HiKey 960, FSL LS2080a),
which U-Boot doesn't suport. I'd rather not break them, but also don't
really want to provide a clock driver ;-)
Also this mimics the !DM_SERIAL behaviour, which sets this clock rate
based on Kconfig, again as a fallback. I needed that because I think the
clock driver wasn't ready that early. It's a bit hard to confirm without
serial output ;-)
So the order should be:
- If there is a clocks property and we support that clock provider
(fixed-clock), then use that value.
- If not, check for a "clock" property in the DT node and use that value.
- If there is no "clock property", use the Kconfig variable.
Just written the other way around in the code.
Does this make sense?
Cheers,
Andre.
>> + ret = clk_get_by_index(dev, 0, &clk);
>> + if (!ret) {
>> + clk_enable(&clk);
>> + plat->clock = clk_get_rate(&clk);
>> + }
>> plat->type = dev_get_driver_data(dev);
>> plat->skip_init = dev_read_bool(dev, "skip-init");
>>
>> --
>> 2.14.5
>>
>
> Regards,
> Simon
>
Re: [PATCH v2 5/5] rockchip: spl: Move board_early_init_f after cpu timer
On Thu, Mar 19, 2020 at 3:43 PM Jagan Teki wrote:
>
> Custom board_early_init_f not only deal with simple gpio
> configuration but also have a possibility to access clocks
> to process any clock related operations like checking reset
> cause state and etc.
>
> So, call it once the rockchip timer initialization done instead
> of calling first place of board_init_f which doesn't have any
> rockchip init code before.
>
> This specific concern was tested with checking reset reason
> via board_early_init_f, which indeed require a clk probe.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - none
>
> arch/arm/mach-rockchip/spl.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
> index 48ab0e60c6..4b4e756247 100644
> --- a/arch/arm/mach-rockchip/spl.c
> +++ b/arch/arm/mach-rockchip/spl.c
> @@ -120,8 +120,6 @@ void board_init_f(ulong dummy)
> debug("\nspl:debug uart enabled in %s\n", __func__);
> #endif
>
> - board_early_init_f();
> -
> ret = spl_early_init();
> if (ret) {
> printf("spl_early_init() failed: %d\n", ret);
> @@ -135,6 +133,9 @@ void board_init_f(ulong dummy)
> /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
> timer_init();
> #endif
> +
> + board_early_init_f();
> +
> #if !defined(CONFIG_TPL) || defined(CONFIG_SPL_OS_BOOT)
> debug("\nspl:init dram\n");
> ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> --
> 2.17.1
>
Tested-by: Suniel Mahesh
Re: [PATCH v2 4/5] rockchip: tpl: Print TPL banner at end-of board_init_f
On Thu, Mar 19, 2020 at 3:43 PM Jagan Teki wrote:
>
> Usually printing the TPL banner various between architecture
> or board codes.
> - Some of them would print at the end of board_init_f for
> making sure all initialization prior to this would happen
> properly. if at all there is a requirement for serial init,
> that happen properly since it prints all after that.
> - Some of them would print at the beginning once the debug
> uart done. assuming this particular banner wouldn't require
> any serial setup code.
>
> Rockchip TPL is following later one and printing early in
> board_init_f.
>
> But, sometimes there is a use case where we can print the banner
> only when the board_init_early_f done.
>
> It is because board_init_early_f has gpio configuration required
> for non-standard board design to glow the specific LEDs upon
> user interaction. These board design wouldn't recommend to
> print any console logs unless user interact with board via
> some kind of power button.
>
> This look specific to board but since all rockchip boards use
> common tpl code, this seems to the desired solution. and also
> it is following similar initialization as rockchip SPL like
> - printing banner at end of board_init_f
> - debug print at early board_init_f in debug_uart_init block.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - none
>
> arch/arm/mach-rockchip/tpl.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
> index fab85dff7d..a9eb27d788 100644
> --- a/arch/arm/mach-rockchip/tpl.c
> +++ b/arch/arm/mach-rockchip/tpl.c
> @@ -60,10 +60,7 @@ void board_init_f(ulong dummy)
> * printascii("string");
> */
> debug_uart_init();
> -#ifdef CONFIG_TPL_BANNER_PRINT
> - printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
> - U_BOOT_TIME ")\n");
> -#endif
> + debug("\ntpl:debug uart enabled in %s\n", __func__);
> #endif
> ret = spl_early_init();
> if (ret) {
> @@ -84,6 +81,11 @@ void board_init_f(ulong dummy)
> printf("DRAM init failed: %d\n", ret);
> return;
> }
> +
> +#ifdef CONFIG_TPL_BANNER_PRINT
> + printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
> + U_BOOT_TIME ")\n");
> +#endif
> }
>
> int board_return_to_bootrom(struct spl_image_info *spl_image,
> --
> 2.17.1
>
Tested-by: Suniel Mahesh
Re: [PATCH v2 3/5] rockchip: tpl: Move board_early_init_f after cpu timer
On Thu, Mar 19, 2020 at 3:43 PM Jagan Teki wrote:
>
> Custom board_early_init_f not only deal with simple gpio
> configuration but also have a possibility to access clocks
> to process any clock related operations like checking reset
> cause state and etc.
>
> So, call it once the rockchip timer initialization done instead
> of calling first place of board_init_f which doesn't have any
> rockchip init code before.
>
> This specific concern was tested with checking reset reason
> via board_early_init_f, which indeed require a clk probe.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - none
>
> arch/arm/mach-rockchip/tpl.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
> index a2b8d31cbd..fab85dff7d 100644
> --- a/arch/arm/mach-rockchip/tpl.c
> +++ b/arch/arm/mach-rockchip/tpl.c
> @@ -50,8 +50,6 @@ void board_init_f(ulong dummy)
> struct udevice *dev;
> int ret;
>
> - board_early_init_f();
> -
> #if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
> /*
> * Debug UART can be used from here if required:
> @@ -78,6 +76,9 @@ void board_init_f(ulong dummy)
> /* Init ARM arch timer in arch/arm/cpu/ */
> timer_init();
>
> + /* custom board early initialization */
> + board_early_init_f();
> +
> ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> if (ret) {
> printf("DRAM init failed: %d\n", ret);
> --
> 2.17.1
>
Tested-by: Suniel Mahesh
Re: [PATCH v2 2/5] roc-rk3399-pc: Set low power leds, power key only if POR
On Thu, Mar 19, 2020 at 3:43 PM Jagan Teki wrote:
>
> ROC-RK3399-PC has specific set of configurations for
> on-board led setup.
>
> Due to easiness for user to know the state of the board
> roc-rk339-pc board code will setup the low power led
> on/off, and waiting for user to press power key and then
> glow full power led.
>
> All this needs to happen only during power-on-reset not
> for soft reset or WDT. So add reset cause check to POR
> and configure the low power leds, power key only. Note
> that the glowing red led is common across any reset.
>
> Reported-by: Markus Reichl
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - glow red led to common across reboots
>
> board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 24 -
> 1 file changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
> b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
> index de9185a7ce..6cc81952d8 100644
> --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
> +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
> @@ -33,6 +33,7 @@ out:
> #endif
>
> #if defined(CONFIG_TPL_BUILD)
> +#include
>
> #define PMUGRF_BASE 0xff32
> #define GPIO0_BASE 0xff72
> @@ -42,18 +43,21 @@ int board_early_init_f(void)
> struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
> struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
>
> - /**
> -* 1. Glow yellow LED, termed as low power
> -* 2. Poll for on board power key press
> -* 3. Once 2 done, off yellow and glow red LED, termed as full power
> -* 4. Continue booting...
> -*/
> - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1);
> + /* Set the low power leds, power key only during POR */
> + if (!strcmp(get_reset_cause(), "POR")) {
> + /* 1. Glow yellow LED, termed as low power */
> + spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1);
>
> - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5),
> GPIO_PULL_NORMAL);
> - while (readl(&gpio0->ext_port) & 0x20);
> + /* 2. Poll for on board power key press */
> + spl_gpio_set_pull(&pmugrf->gpio0_p,
> + GPIO(BANK_A, 5), GPIO_PULL_NORMAL);
> + while (readl(&gpio0->ext_port) & 0x20);
>
> - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0);
> + /* 3. Once 2 done, turn off yellow */
> + spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0);
> + }
> +
> +/* 4. Turn on red LED, termed as full power */
> spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
>
> return 0;
> --
> 2.17.1
>
Tested-by: Suniel Mahesh
