[PATCH v1] i2c: octeon_i2c: Add I2C controller driver for Octeon
From: Suneel Garapati
Add support for I2C controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
Cc: Heiko Schocher
Cc: Simon Glass
Cc: Daniel Schwierzeck
Cc: Aaron Williams
Cc: Chandrakala Chavva
---
RFC -> v1 (Stefan):
- Separated this patch from the OcteonTX/TX2 RFC patch series into a
single patch. This is useful, as the upcoming MIPS Octeon support will
use this I2C driver.
- Added MIPS Octeon II/III support (big endian). Rename driver and its
function names from "octeontx" to "octeon" to better match all Octeon
platforms.
- Moved from union to defines / bitmasks as suggested by Simon. This makes
the driver usage on little- and big-endian platforms much easier.
- Enhanced Kconfig text
- Removed all clock macros (use values from DT)
- Removed long driver debug strings. This is only available when a debug
version of this driver is built. The user / developer can lookup the
descriptive error messages in the driver in this case anyway.
- Removed static "last_id"
- Dropped misc blank lines. Misc reformatting.
- Dropped "!= 0"
- Added missing function comments
- Added missing strut comments
- Changed comment style
- Renames "result" to "ret"
- Hex numbers uppercase
- Minor other changes
- Reword commit text and subject
drivers/i2c/Kconfig | 10 +
drivers/i2c/Makefile | 1 +
drivers/i2c/octeon_i2c.c | 803 +++
3 files changed, 814 insertions(+)
create mode 100644 drivers/i2c/octeon_i2c.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index e42b6516bf..1330b36698 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -374,6 +374,16 @@ config SYS_I2C_SANDBOX
bus. Devices can be attached to the bus using the device tree
which specifies the driver to use. See sandbox.dts as an example.
+config SYS_I2C_OCTEON
+ bool "Octeon II/III/TX/TX2 I2C driver"
+ depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
+ default y
+ help
+ Add support for the Marvell Octeon I2C driver. This is used with
+ various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
+ chips have several I2C ports and all are provided, controlled by
+ the device tree.
+
config SYS_I2C_S3C24X0
bool "Samsung I2C driver"
depends on ARCH_EXYNOS4 && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 62935b7ebc..2b58aae892 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
diff --git a/drivers/i2c/octeon_i2c.c b/drivers/i2c/octeon_i2c.c
new file mode 100644
index 00..210f98655e
--- /dev/null
+++ b/drivers/i2c/octeon_i2c.c
@@ -0,0 +1,803 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * Octeon II/III (MIPS) have different register offsets than the ARM based
+ * Octeon TX/TX2 SoCs
+ */
+#if defined(CONFIG_ARCH_OCTEON)
+#define REG_OFFS 0x
+#else
+#define REG_OFFS 0x1000
+#endif
+
+#define TWSI_SW_TWSI (REG_OFFS + 0x00)
+#define TWSI_TWSI_SW (REG_OFFS + 0x08)
+#define TWSI_INT (REG_OFFS + 0x10)
+#define TWSI_SW_TWSI_EXT (REG_OFFS + 0x18)
+
+#define TWSI_SW_DATA_MASK GENMASK_ULL(31, 0)
+#define TWSI_SW_EOP_IA_MASKGENMASK_ULL(34, 32)
+#define TWSI_SW_IA_MASKGENMASK_ULL(39, 35)
+#define TWSI_SW_ADDR_MASK GENMASK_ULL(49, 40)
+#define TWSI_SW_SCR_MASK GENMASK_ULL(51, 50)
+#define TWSI_SW_SIZE_MASK GENMASK_ULL(54, 52)
+#define TWSI_SW_SOVR BIT_ULL(55)
+#define TWSI_SW_R BIT_ULL(56)
+#define TWSI_SW_OP_MASKGENMASK_ULL(60, 57)
+#define TWSI_SW_EIAGENMASK_ULL(61)
+#define TWSI_SW_SLONLY BIT_ULL(62)
+#define TWSI_SW_V BIT_ULL(63)
+
+#define TWSI_INT_SDA_OVR BIT_ULL(8)
+#define TWSI_INT_SCL_OVR BIT_ULL(9)
+#define TWSI_INT_SDA BIT_ULL(10)
+#define TWSI_INT_SCL BIT_ULL(11)
+
+enum {
+ TWSI_OP_WRITE = 0,
+ TWSI_OP_READ= 1,
+};
+
+enum {
+ TWSI_EOP_SLAVE_ADDR = 0,
+ TWSI_EOP_CLK_CTL = 3,
+ TWSI_SW_EOP_IA = 6,
+};
+
+enum {
+ TWSI_SLAVEADD = 0,
+ TWSI_DATA = 1,
+ TWSI_CTL = 2,
+ TWSI_CLKCTL = 3,
+ TWSI_STAT = 3,
+ TWSI_SLAVEADD_EXT = 4,
+ TWSI_RST = 7,
+};
+
+enum {
+ TWSI_CTL_AA
RE: [PATCH V2 1/6] ARM: stm32: Add default config for DHCOR
Hi Marek, > From: U-Boot On Behalf Of Patrick DELAUNAY > Sent: mercredi 22 avril 2020 10:25 > > Dear Marek, > > > From: Marek Vasut > > Sent: vendredi 10 avril 2020 20:56 > > > > Add default U-Boot configuration for the DHCOR SoM on AV96 board. > > > > Signed-off-by: Marek Vasut > > Cc: Manivannan Sadhasivam > > Cc: Patrick Delaunay > > Cc: Patrice Chotard > > --- > > V2: No change > > --- > > configs/stm32mp15_dhcor_basic_defconfig | 138 > > > 1 file changed, 138 insertions(+) > > create mode 100644 configs/stm32mp15_dhcor_basic_defconfig > > Applied to u-boot-stm/master, thanks! With update of Maintainers file agreed with Marek: - board/dhelectronics/dh_stm32mp1/MAINTAINERS - index 1511ecb65d..fd70131f9e 100644 @@ -4,4 +4,5 @@ S: Maintained F: arch/arm/dts/stm32mp15xx-dhcom* F: board/dhelectronics/dh_stm32mp1/ F: configs/stm32mp15_dhcom_basic_defconfig +F: configs/stm32mp15_dhcor_basic_defconfig F: include/configs/stm32mp1.h Regards Patrick
RE: [PATCH V3 1/6] ARM: stm32: Add default config for DHCOR
Hi, > From: Marek Vasut > Sent: mercredi 22 avril 2020 13:18 > > Add default U-Boot configuration for the DHCOR SoM on AV96 board. > > Reviewed-by: Patrick Delaunay > Signed-off-by: Marek Vasut > Cc: Manivannan Sadhasivam > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > V2: No change > V3: Add RB from Patrick > --- > configs/stm32mp15_dhcor_basic_defconfig | 138 > > 1 file changed, 138 insertions(+) > create mode 100644 configs/stm32mp15_dhcor_basic_defconfig > Applied to u-boot-stm/master, thanks! With update of Maintainers file agreed with Marek: - board/dhelectronics/dh_stm32mp1/MAINTAINERS - index 1511ecb65d..fd70131f9e 100644 @@ -4,4 +4,5 @@ S: Maintained F: arch/arm/dts/stm32mp15xx-dhcom* F: board/dhelectronics/dh_stm32mp1/ F: configs/stm32mp15_dhcom_basic_defconfig +F: configs/stm32mp15_dhcor_basic_defconfig F: include/configs/stm32mp1.h For information dependency with [PATCH 12/12] net: ks8851: Add Kconfig entries Regards Patrick
RE: [PATCH V3 3/6] ARM: stm32: Implement board coding on AV96
Hi, > From: Marek Vasut > Sent: mercredi 22 avril 2020 13:18 > > The AV96 board does exist in multiple variants. To cater for all of them, > implement > board code handling. There are two GPIOs which code the type of the board, > read > them out and use the value to pick the correct device tree from an fitImage. > > Reviewed-by: Patrick Delaunay > Signed-off-by: Marek Vasut > Cc: Manivannan Sadhasivam > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > V2: No change > V3: Drop dm-pre-reloc and gpio-cells from config node > --- > arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi| 1 + > .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 1 + > arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi| 7 +++ > board/dhelectronics/dh_stm32mp1/Kconfig | 2 +- > board/dhelectronics/dh_stm32mp1/board.c | 61 +++ > .../dh_stm32mp1/u-boot-dhcom.its | 39 > .../dh_stm32mp1/u-boot-dhcor.its | 39 > configs/stm32mp15_dhcom_basic_defconfig | 3 + > configs/stm32mp15_dhcor_basic_defconfig | 3 + > include/configs/dh_stm32mp1.h | 15 + > 10 files changed, 170 insertions(+), 1 deletion(-) create mode 100644 > board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its > create mode 100644 board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its > create mode 100644 include/configs/dh_stm32mp1.h > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH V3 2/6] ARM: stm32: Add board_early_init_f() to SPL
Hi, > From: Marek Vasut > Sent: mercredi 22 avril 2020 13:18 > > Add weak implementation of board_early_init_f() hook into the > STM32MP1 SPL. This can be used to read out e.g. configuration straps before > initializing the DRAM. > > Reviewed-by: Patrick Delaunay > Signed-off-by: Marek Vasut > Cc: Manivannan Sadhasivam > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > V2: No change > V3: Add RB from Patrick > --- > arch/arm/mach-stm32mp/spl.c | 11 +++ > 1 file changed, 11 insertions(+) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH V3 4/6] ram: stm32mp1: Add support for multiple configs
Hi, > From: Marek Vasut > Sent: mercredi 22 avril 2020 13:18 > > Add support for multiple DRAM configuration subnodes, while retaining the > support for a single flat DRAM configuration node. This is useful on systems > which can be manufactured in multiple configurations and where the DRAM > configuration can be determined at runtime. > > The code is augmented by a function which can be overridden on board level, > allowing a match on the configuration node name, very much like the fitImage > configuration node name matching works. The default match is on the single > top- > level DRAM configuration, if matching on subnodes is required, then this > board_stm32mp1_ddr_config_name_match() must be overridden. > > Signed-off-by: Marek Vasut > Cc: Manivannan Sadhasivam > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > V2: Match on compatible string > V3: Rework the stm32mp1_ddr_get_ofnode() function > --- > drivers/ram/stm32mp1/stm32mp1_ram.c | 33 - > 1 file changed, 28 insertions(+), 5 deletions(-) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH V3 5/6] ARM: dts: stm32: Rework DDR DT inclusion
Hi, > From: Marek Vasut > Sent: mercredi 22 avril 2020 13:18 > > Adjust the DDR configuration dtsi such that they only generate the DRAM > configuration node, the DDR controller node is moved into the stm32mp157-u- > boot.dtsi itself. This permits including multiple DDR configuration dtsi > files in > board DT. > > Reviewed-by: Patrick Delaunay > Signed-off-by: Marek Vasut > Cc: Manivannan Sadhasivam > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > V2: Add compatible string > V3: Add RB from Patrick > --- > arch/arm/dts/stm32mp15-ddr.dtsi | 358 +++--- > .../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 1 + > .../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 1 + > arch/arm/dts/stm32mp15-u-boot.dtsi| 25 ++ > 4 files changed, 248 insertions(+), 137 deletions(-) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH V3 6/6] ARM: stm32: Implement DDR3 coding on DHCOR SoM
Hi, > From: Marek Vasut > Sent: mercredi 22 avril 2020 13:18 > > The DHCOR board does exist in multiple variants with different DDR3 DRAM > sizes. > To cater for all of them, implement DDR3 code handling. > There are two GPIOs which code the DRAM size populated on the SoM, read them > out and use the value to pick the correct DDR3 config. > > Reviewed-by: Patrick Delaunay > Signed-off-by: Marek Vasut > Cc: Manivannan Sadhasivam > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > V2: Match on compatible string > V3: Add RB from Patrick > --- > arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 2 ++ > arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 2 ++ > board/dhelectronics/dh_stm32mp1/board.c| 26 +- > configs/stm32mp15_dhcom_basic_defconfig| 1 + > configs/stm32mp15_dhcor_basic_defconfig| 1 + > 5 files changed, 31 insertions(+), 1 deletion(-) > Applied to u-boot-stm/master, thanks! Regards Patrick
Re: [PATCH v1 01/10] mips: octeon: Initial minimal support for the Marvell Octeon SoC
Hi Daniel, On 13.05.20 14:49, Daniel Schwierzeck wrote: sorry for the delay ;) NP. I know that its sometimes not easy to find the time for this maintainer / review job. ;) Am 02.05.20 um 10:59 schrieb Stefan Roese: From: Aaron Williams This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. this patch should come after the common MIPS patches Okay, I'll re-arrange the sequence of patches in v2. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- MAINTAINERS |6 + arch/Kconfig |1 + arch/mips/Kconfig| 49 +- arch/mips/Makefile |7 + arch/mips/cpu/Makefile |4 +- arch/mips/include/asm/arch-octeon/cavm-reg.h | 42 + arch/mips/include/asm/arch-octeon/clock.h| 24 + arch/mips/mach-octeon/Kconfig| 92 ++ arch/mips/mach-octeon/Makefile | 10 + arch/mips/mach-octeon/clock.c| 22 + arch/mips/mach-octeon/cpu.c | 55 + arch/mips/mach-octeon/dram.c | 27 + arch/mips/mach-octeon/include/ioremap.h | 30 + arch/mips/mach-octeon/start.S| 1241 ++ 14 files changed, 1608 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/arch-octeon/cavm-reg.h create mode 100644 arch/mips/include/asm/arch-octeon/clock.h create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/clock.c create mode 100644 arch/mips/mach-octeon/cpu.c create mode 100644 arch/mips/mach-octeon/dram.c create mode 100644 arch/mips/mach-octeon/include/ioremap.h create mode 100644 arch/mips/mach-octeon/start.S diff --git a/MAINTAINERS b/MAINTAINERS index 66f0b07263..29f2d7328c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -749,6 +749,12 @@ M: Ezequiel Garcia S:Maintained F:arch/mips/mach-jz47xx/ +MIPS Octeon +M: Aaron Williams +S: Maintained +F: arch/mips/mach-octeon/ +F: arch/mips/include/asm/arch-octeon/ + MMC M:Peng Fan S:Maintained diff --git a/arch/Kconfig b/arch/Kconfig index 91e049b322..1cd3e1dc0b 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -37,6 +37,7 @@ config MICROBLAZE config MIPS bool "MIPS architecture" + select CREATE_ARCH_SYMLINK you should not need that. The path arch/mips/mach-octeon/include/ will be automatically added to the include search paths. Thus move all files in arch/mips/include/asm/arch-octeon/ to arch/mips/mach-octeon/include/ Good idea. select HAVE_ARCH_IOREMAP select HAVE_PRIVATE_LIBGCC select SUPPORT_OF_CONTROL diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 48e754cc46..3c7f3eb94f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -106,6 +106,24 @@ config ARCH_JZ47XX select OF_CONTROL select DM +config ARCH_OCTEON + bool "Support Marvell Octeon CN7xxx platforms" + select DISPLAY_CPUINFO + select DMA_ADDR_T_64BIT + select DM + select DM_SERIAL + select MIPS_CACHE_COHERENT + select MIPS_INIT_STACK_IN_SRAM + select MIPS_L2_CACHE + select MIPS_TUNE_OCTEON3 + select ROM_EXCEPTION_VECTORS + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS64_OCTEON + select PHYS_64BIT + select OF_CONTROL + select OF_LIVE + imply CMD_DM + config MACH_PIC32 bool "Support Microchip PIC32" select DM @@ -160,6 +178,7 @@ source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-jz47xx/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mtmips/Kconfig" +source "arch/mips/mach-octeon/Kconfig" if MIPS @@ -233,6 +252,14 @@ config CPU_MIPS64_R6 Choose this option to build a kernel for release 6 or later of the MIPS64 architecture. +config CPU_MIPS64_OCTEON + bool "Marvell Octeon series of CPUs" + depends on SUPPORTS_CPU_MIPS64_OCTEON + select 64BIT + help +Choose this option for Marvell Octeon CPUs. These CPUs are between +MIPS64 R5 and R6 with other extensions. + endchoice menu "General setup" @@ -261,7 +288,7 @@ config MIPS_CM_BASE config MIPS_CACHE_INDEX_BASE hex "Index base address for cache initialisation" default 0x8000 if CPU_MIPS32 - default 0x8000 if CPU_MIPS64 + default 0xC000 if ARCH_OCTEON help This is the base address for
Re: [PATCH v1 02/10] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM
On 13.05.20 14:59, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.
Signed-off-by: Stefan Roese
---
arch/mips/lib/cache.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 1a8c87d094..9e20b39608 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -7,7 +7,7 @@
#include
#include
#include
-#ifdef CONFIG_MIPS_L2_CACHE
+#ifdef CONFIG_MIPS_CM
#include
#endif
#include
@@ -16,6 +16,17 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_MIPS_L2_CACHE) && !defined(CONFIG_MIPS_CM)
+/*
+ * Dummy implementation to avoid compile warning on platforms with L2
+ * cache but without CM
+ */
+static unsigned long mips_cm_l2_line_size(void)
+{
+ return 0;
+}
+#endif
+
static void probe_l2(void)
{
#ifdef CONFIG_MIPS_L2_CACHE
to avoid further cluttering with #ifdefs I would rather change cm.h like
so and drop the guard around #include :
#if CONFIG_IS_ENABLED(MIPS_CM)
static inline void *mips_cm_base(void)
{
return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
}
static inline unsigned long mips_cm_l2_line_size(void)
{
unsigned long l2conf, line_sz;
l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG);
line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT;
line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
return line_sz ? (2 << line_sz) : 0;
}
#else
static inline void *mips_cm_base(void)
{
return NULL;
}
static inline unsigned long mips_cm_l2_line_size(void)
{
return 0;
}
#endif
Okay, will do in v2.
Thanks,
Stefan
Re: [PATCH v1 03/10] mips: cache: Don't use cache operations with CONFIG_MIPS_CACHE_COHERENT
On 13.05.20 15:05, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
The Octeon platform is cache coherent and cache flushes and invalidates
are not needed. This patch makes use of the newly introduced Kconfig
option CONFIG_MIPS_CACHE_COHERENT to effectively disable all the cache
operations.
I don't like this extra config option. Only flush_dcache_range() is
called from generic MIPS code. You could simply add an empty function
implementation to mach-octeon/ because it's already annotated as __weak.
The other functions should be irrelevant if not used in any driver.
Okay. I've noticed though, that calling flush_cache() from reloc.c
breaks the port. So I would like to make flush_cache() also __weak
and add the empty flush_cache() function to the Octeon base port
as well.
Thanks,
Stefan
Signed-off-by: Stefan Roese
---
arch/mips/lib/cache.c | 38 ++
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 9e20b39608..e27826cbb1 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -118,6 +118,7 @@ static inline unsigned long scache_line_size(void)
} \
} while (0)
+#if !defined(CONFIG_MIPS_CACHE_COHERENT)
void flush_cache(ulong start_addr, ulong size)
{
unsigned long ilsize = icache_line_size();
@@ -188,6 +189,35 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
sync();
}
+void dcache_disable(void)
+{
+ /* change CCA to uncached */
+ change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+
+ /* ensure the pipeline doesn't contain now-invalid instructions */
+ instruction_hazard_barrier();
+}
+
+#else /* CONFIG_MIPS_CACHE_COHERENT */
+
+void flush_cache(ulong start_addr, ulong size)
+{
+}
+
+void __weak flush_dcache_range(ulong start_addr, ulong stop)
+{
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+#endif /* CONFIG_MIPS_CACHE_COHERENT */
+
int dcache_status(void)
{
unsigned int cca = read_c0_config() & CONF_CM_CMASK;
@@ -199,11 +229,3 @@ void dcache_enable(void)
puts("Not supported!\n");
}
-void dcache_disable(void)
-{
- /* change CCA to uncached */
- change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-
- /* ensure the pipeline doesn't contain now-invalid instructions */
- instruction_hazard_barrier();
-}
Viele Grüße,
Stefan
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Re: [PATCH v5 1/4] omap: mmc: Avoid using libfdt with of-platdata
Simon,
On 05/05/20 12:20 pm, Faiz Abbas wrote:
> Hi,
>
> On 04/05/20 6:44 pm, Simon Glass wrote:
>> Hi Bart,
>>
>> On Mon, 4 May 2020 at 01:10, Bartosz Golaszewski wrote:
>>>
>>> pt., 1 maj 2020 o 20:32 Tom Rini napisał(a):
On Thu, Apr 30, 2020 at 01:43:30PM +0200, Bartosz Golaszewski wrote:
> wt., 28 kwi 2020 o 09:01 Faiz Abbas napisał(a):
>>
>> +Bartosz
>>
>> On 28/04/20 9:47 am, Lokesh Vutla wrote:
>>> +Faiz,
>>>
>>> On 28/04/20 12:29 AM, Tom Rini wrote:
On Mon, Apr 27, 2020 at 05:33:41AM +, Peng Fan wrote:
>> Subject: [PATCH v5 1/4] omap: mmc: Avoid using libfdt with
>> of-platdata
>>
>> At present this driver is enabled in SPL on omapl138_lcdk, which uses
>> of-platdata. The driver needs to be ported to use of-platdata
>> properly.
>> For now, avoid a build error by returning an error.
>>
>> Signed-off-by: Simon Glass
>>>
>>> Does this break the boot on omap l138?
>>>
>>
>> I don't have a board at hand to test this out. Bartosz can you help test
>> this with
>> omapl138?
>>
>> Thanks,
>> Faiz
>
> Hi Faiz,
>
> I can confirm - this *does* break the mmc boot on da850-lcdk.
So who is going to fix the driver to unblock Simon's series?
>>>
>>> Is this something that will take a lot of work? What exactly needs
>>> doing? I'm not sure what "use of-platdata properly" means.
>>
>> This board is defining CONFIG_SPL_OF_PLATDATA which means that device
>> tree is not available in SPL. Instead you need to use a C structure
>> created by dtoc. It basically involves creating that struct and
>> getting the data from that instead of calling the DT functions. I
>> expect it will take 2-4 hours to figure out, code and test.
>>
>> See of-plat.rst for full documentation. There are quite a few examples for
>> mmc:
>>
>> grep PLATDATA drivers/mmc/*.c
>> drivers/mmc/ftsdc010_mci.c:#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/ftsdc010_mci.c:#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/ftsdc010_mci.c:#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/ftsdc010_mci.c:#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/mxsmmc.c:#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/mxsmmc.c:#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/mxsmmc.c: debug("OF_PLATDATA: regs: 0x%p bw: %d clkid: %d
>> non_removable: %d\n",
>> drivers/mmc/mxsmmc.c:#if CONFIG_IS_ENABLED(OF_CONTROL) &&
>> !CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/mxsmmc.c:#if CONFIG_IS_ENABLED(OF_CONTROL) &&
>> !CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/omap_hsmmc.c:#if CONFIG_IS_ENABLED(OF_CONTROL) &&
>> !CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/omap_hsmmc.c:#if CONFIG_IS_ENABLED(OF_CONTROL) &&
>> !CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/omap_hsmmc.c:#if CONFIG_IS_ENABLED(OF_CONTROL) &&
>> !CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/rockchip_dw_mmc.c:#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/rockchip_dw_mmc.c:#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/rockchip_dw_mmc.c:#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/rockchip_sdhci.c:#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/rockchip_sdhci.c:#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> drivers/mmc/rockchip_sdhci.c:#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>>
In all the examples above, platdata reg filed is directly being used for
to assign a register base address but looking at davinci platdata that is
generated,
spl/dts/dt-platdata.c:
static const struct dtd_simple_bus dtv_soc_at_1c0 = {
.model = "da850",
.ranges = {0x0, 0x1c0, 0x40},
};
U_BOOT_DEVICE(soc_at_1c0) = {
.name = "simple_bus",
.platdata = &dtv_soc_at_1c0,
.platdata_size = sizeof(dtv_soc_at_1c0),
};
static const struct dtd_ti_da830_uart dtv_serial_at_10d000 = {
.power_domains = {0xa, 0xd},
.reg= {0x10d000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DEVICE(serial_at_10d000) = {
.name = "ti_da830_uart",
.platdata = &dtv_serial_at_10d000,
.platdata_size = sizeof(dtv_serial_at_10d000),
};
static const struct dtd_ti_da830_mmc dtv_mmc_at_4 = {
.bus_width = 0x4,
.cap_mmc_highspeed = true,
.cap_sd_highspeed = true,
.cd_gpios = {0x16, 0x40, 0x1},
.dma_names = {"rx", "tx"},
.dmas = {0x14, 0x10, 0x0, 0x14, 0x11, 0x0},
.max_frequency = 0x2faf080,
.reg= {0x4, 0x1000},
};
U_BOOT_DEVICE(mmc_at_4) = {
.name = "ti_da830_mmc",
.platdata = &dtv_mmc_at_4,
.platdata_size = sizeof(dtv_mmc_at_4),
};
I need the base address of the MMC device (dtd_ti_da830_mmc dtv_mm
Re: [PATCH v1 04/10] mips: traps: Set WG bit in EBase register on Octeon
On 13.05.20 15:10, Daniel Schwierzeck wrote: Am 02.05.20 um 10:59 schrieb Stefan Roese: WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register. Signed-off-by: Stefan Roese --- arch/mips/lib/traps.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 8fff7541e3..ccbce97161 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -106,6 +106,10 @@ void trap_init(ulong reloc_addr) saved_ebase = read_c0_ebase() & 0xf000; + /* Set WG bit on Octeon to enable writing to bits 63:30 */ + if (IS_ENABLED(CONFIG_ARCH_OCTEON)) + ebase |= BIT(11); you should add something like this to mipsregs.h #define EBASE_WG(_ULCAST_(1) << 11) we already have EBASE_CPUNUM. Sure, will do. Thanks, Stefan
Antwort: [PATCH v2 05/35] acpi: Support generation of ACPI code
Hi Simon,
-"Simon Glass" schrieb: -
> Betreff: [PATCH v2 05/35] acpi: Support generation of ACPI code
>
> Add a new file to handle generating ACPI code programatically. This is
> used when information must be dynamically added to the tables, e.g. the
> SSDT.
>
> Initial support is just for writing simple values.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
> Changes in v1: None
>
> include/acpi/acpigen.h | 49 +++
> lib/acpi/Makefile | 1 +
> lib/acpi/acpigen.c | 38
> test/dm/Makefile | 1 +
> test/dm/acpigen.c | 65 ++
> 5 files changed, 154 insertions(+)
> create mode 100644 include/acpi/acpigen.h
> create mode 100644 lib/acpi/acpigen.c
> create mode 100644 test/dm/acpigen.c
>
> diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
> new file mode 100644
> index 00..8809cdb4e1
> --- /dev/null
> +++ b/include/acpi/acpigen.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Core ACPI (Advanced Configuration and Power Interface) support
> + *
> + * Copyright 2019 Google LLC
> + *
> + * Modified from coreboot file acpigen.h
> + */
> +
> +#ifndef __ACPI_ACPIGEN_H
> +#define __ACPI_ACPIGEN_H
> +
> +#include
> +
> +struct acpi_ctx;
> +
> +/**
> + * acpigen_get_current() - Get the current ACPI code output pointer
> + *
> + * @ctx: ACPI context pointer
> + * @return output pointer
> + */
> +u8 *acpigen_get_current(struct acpi_ctx *ctx);
> +
> +/**
> + * acpigen_emit_byte() - Emit a byte to the ACPI code
> + *
> + * @ctx: ACPI context pointer
> + * @data: Value to output
> + */
> +void acpigen_emit_byte(struct acpi_ctx *ctx, uint data);
> +
> +/**
> + * acpigen_emit_word() - Emit a 16-bit word to the ACPI code
> + *
> + * @ctx: ACPI context pointer
> + * @data: Value to output
> + */
> +void acpigen_emit_word(struct acpi_ctx *ctx, uint data);
> +
> +/**
> + * acpigen_emit_dword() - Emit a 32-bit 'double word' to the ACPI code
> + *
> + * @ctx: ACPI context pointer
> + * @data: Value to output
> + */
> +void acpigen_emit_dword(struct acpi_ctx *ctx, uint data);
> +
> +#endif
> diff --git a/lib/acpi/Makefile b/lib/acpi/Makefile
> index caae6c01bd..85a1f774ad 100644
> --- a/lib/acpi/Makefile
> +++ b/lib/acpi/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> +obj-y += acpigen.o
> obj-y += acpi_device.o
> obj-y += acpi_table.o
> diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
> new file mode 100644
> index 00..59bd3af0b7
> --- /dev/null
> +++ b/lib/acpi/acpigen.c
> @@ -0,0 +1,38 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Generation of ACPI (Advanced Configuration and Power Interface) tables
> + *
> + * Copyright 2019 Google LLC
> + * Mostly taken from coreboot
> + */
> +
> +#define LOG_CATEGORY LOGC_ACPI
> +
> +#include
> +#include
> +#include
> +#include
> +
> +u8 *acpigen_get_current(struct acpi_ctx *ctx)
> +{
> + return ctx->current;
> +}
> +
> +void acpigen_emit_byte(struct acpi_ctx *ctx, uint data)
> +{
As we expect exactly a byte, could data be of type uint8_t ?
Similar for the functions below.
> + *(u8 *)ctx->current++ = data;
> +}
> +
> +void acpigen_emit_word(struct acpi_ctx *ctx, uint data)
> +{
> + acpigen_emit_byte(ctx, data & 0xff);
> + acpigen_emit_byte(ctx, (data >> 8) & 0xff);
This function assumes little-endian host endianess. This works under
x86 and probably most of ARM, and I'm not aware of other architectures
using ACPI.
Should it be made more portable anyway e.g. by using cpu_to_le16()?
> +}
> +
> +void acpigen_emit_dword(struct acpi_ctx *ctx, uint data)
> +{
> + acpigen_emit_byte(ctx, data & 0xff);
> + acpigen_emit_byte(ctx, (data >> 8) & 0xff);
> + acpigen_emit_byte(ctx, (data >> 16) & 0xff);
> + acpigen_emit_byte(ctx, (data >> 24) & 0xff);
> +}
> diff --git a/test/dm/Makefile b/test/dm/Makefile
> index 6c18fd04ce..e3e0cccf01 100644
> --- a/test/dm/Makefile
> +++ b/test/dm/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_UT_DM) += test-uclass.o
> obj-$(CONFIG_UT_DM) += core.o
> ifneq ($(CONFIG_SANDBOX),)
> obj-$(CONFIG_ACPIGEN) += acpi.o
> +obj-$(CONFIG_ACPIGEN) += acpigen.o
> obj-$(CONFIG_SOUND) += audio.o
> obj-$(CONFIG_BLK) += blk.o
> obj-$(CONFIG_BOARD) += board.o
> diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
> new file mode 100644
> index 00..68f2b73132
> --- /dev/null
> +++ b/test/dm/acpigen.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Tests for ACPI code generation
> + *
> + * Copyright 2019 Google LLC
> + * Written by Simon Glass
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static int alloc_context(struct acpi_ctx **ctxp)
> +{
> + struct acpi_ctx *ctx;
> +
> + *ctxp = NULL;
> + ctx = malloc(sizeof(*ctx));
> + if (!ctx)
> + return -ENOMEM;
> + ctx->current =
Re: [PATCH v1 05/10] mips: Rename CONFIG_CPU_CAVIUM_OCTEON to CONFIG_CPU_MIPS64_OCTEON
On 13.05.20 15:16, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
With the introduction of the MIPS Octeon support, lets use the newly
added Kconfig symbol CONFIG_CPU_MIPS64_OCTEON instead of the old Linux
CONFIG_CPU_CAVIUM_OCTEON one (which was never set). Remove these
references completely with this patch.
please keep that symbol, otherwise it complicates future header file
syncs with Linux (currently I'm working on one). You could simply add
CONFIG_CPU_CAVIUM_OCTEON as hidden Kconfig symbol and select it from
CONFIG_CPU_MIPS64_OCTEON
Done in v2.
Thanks,
Stefan
Signed-off-by: Stefan Roese
---
arch/mips/include/asm/io.h | 4 ++--
arch/mips/include/asm/ptrace.h | 2 +-
scripts/config_whitelist.txt | 1 -
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 7c40e415c7..072d1718c9 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -223,7 +223,7 @@ static inline void iounmap(const volatile void __iomem
*addr)
plat_iounmap(addr);
}
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#ifdef CONFIG_CPU_MIPS64_OCTEON
#define war_octeon_io_reorder_wmb() wmb()
#else
#define war_octeon_io_reorder_wmb() do { } while (0)
@@ -452,7 +452,7 @@ BUILDSTRING(q, u64)
#endif
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#ifdef CONFIG_CPU_MIPS64_OCTEON
#define mmiowb() wmb()
#else
/* Depends on MIPS II instruction set */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index cb88d6d4f9..60f50450d4 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -36,7 +36,7 @@ struct pt_regs {
unsigned long cp0_badvaddr;
unsigned long cp0_cause;
unsigned long cp0_epc;
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#ifdef CONFIG_CPU_MIPS64_OCTEON
unsigned long long mpl[6];/* MTM{0-5} */
unsigned long long mtp[6];/* MTP{0-5} */
#endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 7a5da9d822..303a23fdd1 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -234,7 +234,6 @@ CONFIG_CPLD_BR_PRELIM
CONFIG_CPLD_OR_PRELIM
CONFIG_CPM2
CONFIG_CPU_ARMV8
-CONFIG_CPU_CAVIUM_OCTEON
CONFIG_CPU_FREQ_HZ
CONFIG_CPU_HAS_LLSC
CONFIG_CPU_HAS_PREFETCH
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v1 10/10] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
On 13.05.20 16:47, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this board.
Supported devices:
- UART
- reset
- CFI parallel NOR flash
Signed-off-by: Stefan Roese
---
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mrvl,octeon-ebb7304.dts| 96
arch/mips/mach-octeon/Kconfig| 14
board/Marvell/octeon_ebb7304/Kconfig | 19 +
board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++
board/Marvell/octeon_ebb7304/Makefile| 8 ++
board/Marvell/octeon_ebb7304/board.c | 12 +++
configs/octeon_ebb7304_defconfig | 34 +
include/configs/octeon_common.h | 29 +++
include/configs/octeon_ebb7304.h | 20 +
10 files changed, 240 insertions(+)
create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts
create mode 100644 board/Marvell/octeon_ebb7304/Kconfig
create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS
create mode 100644 board/Marvell/octeon_ebb7304/Makefile
create mode 100644 board/Marvell/octeon_ebb7304/board.c
create mode 100644 configs/octeon_ebb7304_defconfig
create mode 100644 include/configs/octeon_common.h
create mode 100644 include/configs/octeon_ebb7304.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index f711e9fb59..dc85901dca 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
+dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts
b/arch/mips/dts/mrvl,octeon-ebb7304.dts
new file mode 100644
index 00..4e9c2de7d4
--- /dev/null
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell / Cavium Inc. EVB CN7300
+ */
+
+/dts-v1/;
+
+/include/ "mrvl,cn73xx.dtsi"
+
+/ {
+ model = "cavium,ebb7304";
+ compatible = "cavium,ebb7304";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&bootbus {
+ /*
+* bootbus CS0 for CFI flash is remapped (0x1fc0. -> 1f40.)
+* as the initial size is too small for the 8MiB flash device
+*/
+ ranges = <0 0 0 0x1f40 0xc0>,
+<1 0 0x1 0x1000 0>,
+<2 0 0x1 0x2000 0>,
+<3 0 0x1 0x3000 0>,
+<4 0 0 0x1d02 0x1>,
+<5 0 0x1 0x5000 0>,
+<6 0 0x1 0x6000 0>,
+<7 0 0x1 0x7000 0>;
+
+ cavium,cs-config@0 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <0>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <50>;
+ cavium,t-oe = <50>;
+ cavium,t-we = <35>;
+ cavium,t-rd-hld = <25>;
+ cavium,t-wr-hld = <35>;
+ cavium,t-pause = <0>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <30>;
+ cavium,t-rd-dly = <0>;
+ cavium,page-mode = <1>;
+ cavium,pages = <8>;
+ cavium,bus-width = <8>;
+ };
+
+ cavium,cs-config@4 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <4>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <10>;
+ cavium,t-oe = <160>;
+ cavium,t-we = <100>;
+ cavium,t-rd-hld = <10>;
+ cavium,t-wr-hld = <0>;
+ cavium,t-pause = <50>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <10>;
+ cavium,t-rd-dly = <10>;
+ cavium,pages = <0>;
+ cavium,bus-width = <8>;
+ };
+
+ flash0: nor@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "bootloader";
+ reg = <0 0x34>;
+ read-only;
+ };
+
[GIT PULL] rpi: updates for v2020.07
Hi Tom,
Please have a look at the updates for RPi below.
I know I'm a bit late in the cycle. I'll try to send my pull requests earlier
next time, sorry for that.
I just pushed the tag, so the CI is not green yet:
https://travis-ci.org/github/mbgg/u-boot/builds/686914330
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi/pipelines/3241
But the tag actually refers to the same commit as my rpi-next branch, which is
all green here:
https://travis-ci.org/github/mbgg/u-boot/builds/686541087
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi/pipelines/3227
Regards and stay safe and healthy,
Matthias
---
The following changes since commit 2a38d2239d0bb4d128b00886bf097ab247a0b1a7:
Prepare v2020.07-rc2 (2020-05-11 18:28:19 -0400)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi.git
tags/rpi-next-2020.07
for you to fetch changes up to 82aef6c6f8a74a0595501bfbb2f6f763c786324f:
rpi: use the newly-added RPI_EFI_NR_SPIN_PAGES (2020-05-13 14:04:50 +0200)
- fix phy configuration for RPi4's bcmgenet
- sync RPi4's env size with other RPi configs
- add kconfig option to reserver more pages in the EFI mem map
- add support for SDMA which is used by RPi4
- fix corner case boot bug for RPi3 32-bit
Jaehoon Chung (3):
mmc: sdhci: use phys2bus macro when dma address is accessed
mmc: sdhci: not return error when SDMA is not supported
configs: rpi_4 : enable SDHCI_SDMA config
Kyle Evans (2):
rpi: Kconfig option for initial page reservation
rpi: use the newly-added RPI_EFI_NR_SPIN_PAGES
Marek Szyprowski (1):
configs: rpi_arm64: sync env size with rpi_{3,4}_defconfig
Matthias Brugger (2):
mmc: sdhci: Use debug for not supported SDMA info message
configs: rpi_arm64: enable SDHCI SDMA support
Nicolas Saenz Julienne (1):
net: bcmgenet: Don't set ID_MODE_DIS when not using RGMII
Simon Glass (2):
arm: dts: bcm283x: Allow UARTs to work before relocation
arm: bcm283x: serial: Move ofdata reading to probe() method
arch/arm/dts/bcm283x-u-boot.dtsi | 8
arch/arm/mach-bcm283x/Kconfig | 2 ++
board/raspberrypi/rpi/Kconfig | 10 ++
board/raspberrypi/rpi/rpi.c | 3 ++-
configs/rpi_4_32b_defconfig | 1 +
configs/rpi_4_defconfig | 1 +
configs/rpi_arm64_defconfig | 2 ++
drivers/mmc/sdhci.c | 17 +
drivers/net/bcmgenet.c| 5 -
drivers/serial/serial_bcm283x_mu.c| 21 +
drivers/serial/serial_bcm283x_pl011.c | 12
11 files changed, 56 insertions(+), 26 deletions(-)
create mode 100644 board/raspberrypi/rpi/Kconfig
Re: [PATCH v1 08/10] sysreset: Add Octeon sysreset driver
On 13.05.20 17:03, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.
Signed-off-by: Stefan Roese
---
drivers/sysreset/Kconfig | 7
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_octeon.c | 52 ++
3 files changed, 60 insertions(+)
create mode 100644 drivers/sysreset/sysreset_octeon.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 4be7433404..6ebc90e1d3 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -57,6 +57,13 @@ config SYSRESET_MICROBLAZE
help
This is soft reset on Microblaze which does jump to 0x0 address.
+config SYSRESET_OCTEON
+ bool "Enable support for Marvell Octeon SoC family"
+ depends on ARCH_OCTEON
+ help
+ This enables the system reset driver support for Marvell Octeon
+ SoCs.
+
config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 3ed4bab9e3..df2293b848 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
+obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
diff --git a/drivers/sysreset/sysreset_octeon.c
b/drivers/sysreset/sysreset_octeon.c
new file mode 100644
index 00..a05dac3226
--- /dev/null
+++ b/drivers/sysreset/sysreset_octeon.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Stefan Roese
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define RST_SOFT_RST 0x0080
+
+struct octeon_sysreset_data {
+ void __iomem *base;
+};
+
+static int octeon_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+ writeq(1, data->base + RST_SOFT_RST);
+
+ return -EINPROGRESS;
+}
+
+static int octeon_sysreset_probe(struct udevice *dev)
+{
+ struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+ data->base = dev_remap_addr(dev);
+
+ return 0;
+}
+
+static struct sysreset_ops octeon_sysreset = {
+ .request = octeon_sysreset_request,
+};
+
+static const struct udevice_id octeon_sysreset_ids[] = {
+ { .compatible = "mrvl,cn7xxx-rst" },
+ { }
+};
+
+U_BOOT_DRIVER(sysreset_octeon) = {
+ .id = UCLASS_SYSRESET,
+ .name = "octeon_sysreset",
+ .priv_auto_alloc_size = sizeof(struct octeon_sysreset_data),
+ .ops= &octeon_sysreset,
+ .probe = octeon_sysreset_probe,
+ .of_match = octeon_sysreset_ids,
+};
have you planned to add a real reset driver? If you add syscon/regmap
support to that reset driver, then you could simply use the generic
sysreset_syscon.c driver.
With a "real reset driver" you are referring to a driver capable of
resetting multiple (all) SoC internal peripherals?
If yes, I thought about adding such a driver. But AFAICT, Octeon does
not support resetting its peripherals via some grouped registers. The
SoC itself can be reset via RST_SOFT_RST register but not its
peripherals.
Thanks,
Stefan
Re: [PATCH v2 1/2] arm: dts: bcm283x: Allow UARTs to work before relocation
On 15/04/2020 21:59, Tom Rini wrote: > On Tue, Apr 14, 2020 at 08:23:10PM -0600, Simon Glass wrote: >> Hi, >> >> On Sun, 22 Mar 2020 at 21:16, Simon Glass wrote: >>> >>> At present the pinctrl nodes are not enabled in pre-relocation U-Boot so >>> the UARTs do not correctly select the pinconfig to enable the UART pins. >>> Fix this so that the U-Boot banner is printed. >>> >>> This fixes serial output on rpi_3b_32b with the following config.txt >>> options: >>> >>>enable_uart=1 >>>gpu_freq=250 >>> >>> Signed-off-by: Simon Glass >>> Fixes: 9821636b64 (bcm2835_pinctrl: Probe pre-reloc) >>> --- >>> >>> Changes in v2: >>> - Update commit message >>> >>> arch/arm/dts/bcm283x-u-boot.dtsi | 8 >>> 1 file changed, 8 insertions(+) >> >> Any thoughts on this series? At present all my lab tests fail. > > I don't know if the problem is my firmware is too old (and so works) or > your firmware is too old (and so fails) or if there's some > phase-of-the-moon problem. So while I'd like to know _why_ my 3B is > fine and yours is not, we should just take this I suppose. > I agree with Tom, we should try to find out what's the problem. Do you know which version (e.g. git commit or which version of rasbian etc) of the RPi FW you are using? If not, can you provide me with the md5sum's so that I can try to reproduce this. Regards, Matthias
Re: [PATCH v1 01/10] mips: octeon: Initial minimal support for the Marvell Octeon SoC
On 14.05.20 01:43, Daniel Schwierzeck wrote: Am 02.05.20 um 10:59 schrieb Stefan Roese: From: Aaron Williams This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- MAINTAINERS |6 + arch/Kconfig |1 + arch/mips/Kconfig| 49 +- arch/mips/Makefile |7 + arch/mips/cpu/Makefile |4 +- arch/mips/include/asm/arch-octeon/cavm-reg.h | 42 + arch/mips/include/asm/arch-octeon/clock.h| 24 + arch/mips/mach-octeon/Kconfig| 92 ++ arch/mips/mach-octeon/Makefile | 10 + arch/mips/mach-octeon/clock.c| 22 + arch/mips/mach-octeon/cpu.c | 55 + arch/mips/mach-octeon/dram.c | 27 + arch/mips/mach-octeon/include/ioremap.h | 30 + arch/mips/mach-octeon/start.S| 1241 ++ 14 files changed, 1608 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/arch-octeon/cavm-reg.h create mode 100644 arch/mips/include/asm/arch-octeon/clock.h create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/clock.c create mode 100644 arch/mips/mach-octeon/cpu.c create mode 100644 arch/mips/mach-octeon/dram.c create mode 100644 arch/mips/mach-octeon/include/ioremap.h create mode 100644 arch/mips/mach-octeon/start.S I couldn't completely understand the start.S. There is too much stuff in it for an initial merge. But I don't see a hard reason against using the generic start.S. So the first patch series should only implement the bare minimum needed to boot from flash, init the boot CPU core, maybe suspend all other cores and relocate to L2 cache. I already worked on using the common start.S with minimal custom additions for Octeon. This will be included in v2 of the base Octeon patchset. I know the current start.S is not really suited yet but I'm working on a refactoring to add some more hooks which a SoC/CPU can implement. Once we have your initial patch series and the refactoring in mainline, it should be possible to gradually add more Octeon stuff like memory init. Basic idea for refactoring is something like this: reset: - mips_cpu_early_init() # custom early init, fix errata - init CP0 registers, Watch registers - mips_cache_disable()# set K0 CCA to uncached - mips_cpu_core_init()# per CPU core init # -> generic code issues wait instr. # -> custom code can do custom init #or custom boot protocols - mips_cm_map() # init CM if available - mips_cache_init() # init caches, set K0 CCA to non-coh. - mips_sram_init()# init SRAM, Scratch RAM if avail - setup initial stack and global_data - debug_uart_init() - mips_mem_init() # init external memory, C env avail. - init malloc_f - board_init_f() Thanks Daniel, this sounds like a very good approach. I'll send v2 later today (as its already finished). We can then work on how to integrate it, either by using the currently available functions like mips_sram_init(), or by extending start.S (and the Octeon custom code) with some other, newly introduced functions. Thanks, Stefan + +#endif /* __ASM_MACH_OCTEON_IOREMAP_H */ diff --git a/arch/mips/mach-octeon/start.S b/arch/mips/mach-octeon/start.S new file mode 100644 index 00..acb967201a --- /dev/null +++ b/arch/mips/mach-octeon/start.S @@ -0,0 +1,1241 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Startup Code for OCTEON 64-bit CPU-core + * + * Copyright (c) 2003 Wolfgang Denk + * Copyright 2004, 2005, 2010 - 2015 Cavium Inc.. + */ + +#include +#include +#include +#include +#include + +#define BOOT_VECTOR_NUM_WORDS 8 + +#define OCTEON_BOOT_MOVEABLE_MAGIC_OFFSET 0x70 +#define OCTEON_BOOT_VECTOR_MOVEABLE_OFFSET 0x78 + +#define OCTEON_BOOT_MOVEABLE_MAGIC1_RAW0xdb00110ad358eacd +#define OCTEON_BOOT_MOVEABLE_MAGIC1OCTEON_BOOT_MOVEABLE_MAGIC1_RAW + +#define OCTEON_CIU_SOFT_RST0x800107000740 + +#defineOCTEON_L2C_WPAR_PP0 0x800118008084 +#define OCTEON_MIO_BOOT_BASE 0x80011800 +#define OCTEON_MIO_BOOT_REG_CFG0_OFF 0x +#define OCTEON_MIO_BOOT_LOC_CFG0_OFF 0x0080 +#defi
RE: [PATCH 00/11] stm32mp1: migrate MTD and DFU configuration in Kconfig
Hi, > From: Patrick DELAUNAY > Sent: mercredi 18 mars 2020 09:23 > > > This serie migrate the dynamically build MTD > (CONFIG_SYS_MTDPARTS_RUNTIME) and the DFU configuration > (CONFIG_SET_DFU_ALT_INFO) previously based on ENV variables to > CONFIG_. > > These patches reduce the size of the environment and allow to tune for each > target with a specific defconfig file. > > This serie also removes the TEE deconfig, replaced by a dynamic detection > based on op-tee driver probe. > > This serie depends on previous CONFIG migration proposed in > http://patchwork.ozlabs.org/project/uboot/list/?series=160899 > - configs: migrate CONFIG_SET_DFU_ALT_INFO to defconfigs > - configs: migrate CONFIG_SYS_MTDPARTS_RUNTIME to defconfigs > > > > Patrick Delaunay (11): > board: stm32mp1: move board_get_mtdparts in st common directory > board: stm32mp1: move set_dfu_alt_info in st common directory > stm32mp1: dynamically build DFU_ALT_INFO > stm32mp1: move MTDPART configuration in Kconfig > board: stm32mp1: reserve memory for OP-TEE in device tree > stm32mp1: dynamically detect op-tee presence > board: stm32mp1: use FDT address provided by TF-A at boot time > configs: stm32mp1: remove optee defconfig > board: stm32mp1: support boot from spi-nand > board: stm32mp1: adapt MTD partition for BOOT from NOR or NAND > doc: stm32mp1: update DFU support example > > arch/arm/dts/stm32mp157a-dk1.dts | 5 + > arch/arm/dts/stm32mp157c-ed1.dts | 5 + > arch/arm/mach-stm32mp/Kconfig | 10 - > arch/arm/mach-stm32mp/Makefile | 1 + > arch/arm/mach-stm32mp/boot_params.c| 45 > arch/arm/mach-stm32mp/cpu.c| 4 + > arch/arm/mach-stm32mp/dram_init.c | 18 ++ > arch/arm/mach-stm32mp/fdt.c| 25 ++ > arch/arm/mach-stm32mp/include/mach/stm32.h | 3 + > arch/arm/mach-stm32mp/spl.c| 2 + > board/dhelectronics/dh_stm32mp1/Kconfig| 1 + > board/dhelectronics/dh_stm32mp1/Makefile | 3 + > board/dhelectronics/dh_stm32mp1/board.c| 143 +--- > board/st/common/Kconfig| 64 ++ > board/st/common/Makefile | 5 + > board/st/common/stm32mp_dfu.c | 225 ++ > board/st/common/stm32mp_mtdparts.c | 157 + > board/st/stm32mp1/MAINTAINERS | 1 - > board/st/stm32mp1/stm32mp1.c | 253 + > configs/stm32mp15_optee_defconfig | 132 --- > configs/stm32mp15_trusted_defconfig| 3 + > doc/board/st/stm32mp1.rst | 147 +--- > include/configs/stm32mp1.h | 64 +- > 23 files changed, 634 insertions(+), 682 deletions(-) create mode 100644 > arch/arm/mach-stm32mp/boot_params.c > create mode 100644 board/st/common/stm32mp_dfu.c create mode 100644 > board/st/common/stm32mp_mtdparts.c > delete mode 100644 configs/stm32mp15_optee_defconfig > > -- > 2.17.1 For the serie applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH 00/18] stm32mp1: add command stm32prog
Hi, > From: Patrick DELAUNAY > Sent: mercredi 18 mars 2020 09:25 > > > Add a specific command stm32prog for STM32MP soc family witch allows to > update the devices on the board with the STMicroelectronics tool > STM32CubeProgrammer (http://www.st.com/STM32CubeProg). > > This command use the same UART STM32 protocol than MCU STM32 with or > USB with DFU protocol v1.1 (MCU ST extension are no supported). > > The executed actions are based on a tab separated value file with a stm32 > header > (see https://wiki.st.com/stm32mpu/wiki/STM32CubeProgrammer_flashlayout). > > This FlashLayout file is loaded in DDR by TF-A during during a serial boot or > in a > virtual device by stm32prog command and is parsed by U-Boot (see "AN5275: > USB DFU/USART protocols used in STM32MP1 Series bootloaders" for details). > > Regards > Patrick > > > > Patrick Delaunay (18): > usb: gadget: g_dnl: add function g_dnl_set_product > dfu: add prototype for dfu_transaction_initiate/cleanup > stm32mp: add function get_cpu_dev > stm32mp: add the command stm32prog > stm32mp: stm32prog: add flash layout parsing > stm32mp: stm32prog: add MMC device > stm32mp: stm32prog: add support of boot partition for eMMC device > stm32mp: stm32prog: add upport of partial update > stm32mp: stm32prog: add MTD devices support > stm32mp: stm32prog: adapt the MTD partitions > stm32mp: stm32prog: add support of ssbl copy > stm32mp: stm32prog: add support for delete option in flashlayout > stm32mp: stm32prog: add otp update support > stm32mp: stm32prog: add pmic NVM update support > stm32mp: stm32prog: add serial link support > stm32mp: stm32prog: enable videoconsole > stm32mp: stm32prog: support for script > stm32mp: stm32prog: add support of RAM target > > arch/arm/mach-stm32mp/Kconfig | 17 + > arch/arm/mach-stm32mp/Makefile|1 + > arch/arm/mach-stm32mp/cmd_stm32prog/Makefile |9 + > .../cmd_stm32prog/cmd_stm32prog.c | 192 ++ > .../mach-stm32mp/cmd_stm32prog/stm32prog.c| 1745 + > .../mach-stm32mp/cmd_stm32prog/stm32prog.h| 185 ++ > .../cmd_stm32prog/stm32prog_serial.c | 993 ++ > .../cmd_stm32prog/stm32prog_usb.c | 230 +++ > arch/arm/mach-stm32mp/cpu.c | 11 +- > .../arm/mach-stm32mp/include/mach/stm32prog.h | 16 + > .../arm/mach-stm32mp/include/mach/sys_proto.h |5 + > board/st/common/stm32mp_dfu.c | 20 + > board/st/common/stm32mp_mtdparts.c| 14 +- > configs/stm32mp15_basic_defconfig |7 +- > configs/stm32mp15_trusted_defconfig |7 +- > drivers/usb/gadget/g_dnl.c|8 + > include/dfu.h |3 + > include/g_dnl.h |1 + > 18 files changed, 3445 insertions(+), 19 deletions(-) create mode 100644 > arch/arm/mach-stm32mp/cmd_stm32prog/Makefile > create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c > create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c > create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h > create mode 100644 arch/arm/mach- > stm32mp/cmd_stm32prog/stm32prog_serial.c > create mode 100644 arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c > create mode 100644 arch/arm/mach-stm32mp/include/mach/stm32prog.h > > -- > 2.17.1 For the serie: applied to u-boot-stm/master, thanks! Regards Patrick
Re: [PATCH] dm: core: Reorder include files in read.c
Hi Simon, On 29.04.20 20:04, Simon Glass wrote: On Wed, 29 Apr 2020 at 01:08, Stefan Roese wrote: Including the assembler headers before including common.h etc leads to compilation errors upon MIPS64 based platforms using OF_LIVE. This patch reorders the include files to the "correct" oder. Signed-off-by: Stefan Roese Cc: Simon Glass --- drivers/core/read.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass Just a short reminder about this patch, as its needed for the base Octeon (MIPS) support, I'm currently working on. Otherwise, usage of OF_LIVE is not possible. Thanks, Stefan
RE: [PATCH v2 00/12] stm32mp1: several board and arch updates
Hi, > From: Patrick DELAUNAY > Sent: mercredi 22 avril 2020 14:29 > > > It is a V2 for the serie > http://patchwork.ozlabs.org/project/uboot/list/?series=167872 > > Rebased on master branch and after the first reviews: > > [01/16] arm: stm32mp: update dependency for STM32_ETZPC > is already accepted/merged > > [03/16] arm: stm32mp: reset to default environment when serial# change [04/16] > arm: stm32mp: detect U-Boot version used to save environment [11/16] board: > stm32mp1: check env_get result in board_late_init > are dropped > > [05/16] arm: stm32mp: spl: add bsec driver in SPL > this unrelated patch is moved in a separate serie: > "stm32mp1: use OPP information for PLL1 settings in SPL" > > > Changes in v2: > - minor commit message update > - simplify patch after Wolfgang review, as console init alway failed when > drivers can't probe (remove printf after preloader_console_init call) > - use CONFIG_IS_ENABLED(LED) everywhere > - remove debug message and unused return of board_ev1_init > - remove bootdelay configuration after Wolfgang's comment on dropped patch > [11/16] board: stm32mp1: check env_get result in board_late_init > > Christophe Roullier (1): > configs: stm32mp1: activate Ethernet PHY Realtek > > Patrice Chotard (1): > board: stm32mp1: Keep error led ON in case of low power detection > > Patrick Delaunay (10): > arm: stm32mp: remove dependency for STM32KEY > arm: stm32mp: spl: update error management in board_init_f > board: stm32mp1: update management of boot-led > board: stm32mp1: gt9147 IRQ before reset on EV1 > board: stm32mp1: set environment variable fdtfile > board: stm32mp1: remove bootdelay configuration for usb or serial boot > board: stm32mp1: add timeout for I/O compensation ready > gpio: stm32: support gpio ops in SPL > ARM: dts: stm32mp15: use DDR3 files generated by STM32CubeMX > configs: stm32mp1: activate CONFIG_ERRNO_STR > > .../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 49 + > .../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 49 + > arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 4 - > arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 4 - > arch/arm/mach-stm32mp/Kconfig | 2 - > arch/arm/mach-stm32mp/spl.c | 6 +- > board/st/stm32mp1/stm32mp1.c | 102 +- > configs/stm32mp15_basic_defconfig | 2 + > configs/stm32mp15_trusted_defconfig | 2 + > drivers/gpio/stm32_gpio.c | 7 +- > 10 files changed, 130 insertions(+), 97 deletions(-) > > -- > 2.17.1 For the serie applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH] stm32mp1: Fix warning display when 1.5A power supply is used
Hi Patrice > From: Patrice CHOTARD > Sent: jeudi 30 avril 2020 18:41 > > On DK1/2 board, when a 1.5A power supply is detected, a warning message is > displayed. In this message, "1.5mA" is displayed instead of "1.5A". > > Signed-off-by: Patrice Chotard > --- > > board/st/stm32mp1/stm32mp1.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH] ARM: dts: stm32: Fix AV96 and DHCOR split
Hi,
> From: Marek Vasut
> Sent: lundi 27 avril 2020 13:16
>
> The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and
> AV96 board") was not applied correctly and in full, and omitted an important
> split
> of the SoM into 3V3 and 1V8 options. The Avenger96 board is based on the 1V8
> IO option of the DHCOR SoM, however this is an optional modification of the
> 3V3
> IO DHCOR SoM with extra on-SoM regulator to cater for the 96boards 1V8 IO
> requirements.
>
> Reinstate the split between the 1V8 and 3V3 IO variants.
>
> Fixes: 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96
> board")
> Signed-off-by: Marek Vasut
> Cc: Manivannan Sadhasivam
> Cc: Patrick Delaunay
> Cc: Patrice Chotard
> ---
> arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 2 +-
> arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi | 24 +++
> ...hcor.dtsi => stm32mp15xx-dhcor-io3v3.dtsi} | 13 +-
> 3 files changed, 26 insertions(+), 13 deletions(-) create mode 100644
> arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi
> rename arch/arm/dts/{stm32mp15xx-dhcor.dtsi => stm32mp15xx-dhcor-
> io3v3.dtsi} (94%)
>
Applied to u-boot-stm/master, thanks!
Regards
Patrick
RE: [PATCH] ARM: dts: stm32: Synchronize DDR setttings on DH SoMs
Hi Marek, > From: Marek Vasut > Sent: mercredi 29 avril 2020 15:09 > > Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put > them into use by the board file instead of the default ones. These new DRAM > settings are a better fit for the SoMs. > > Signed-off-by: Marek Vasut > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > Note that these settings are generated by the cubemx tool > --- > .../stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi | 120 ++ > .../stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi | 120 ++ > .../stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 120 ++ > arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi| 5 +- > arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi| 5 +- > board/dhelectronics/dh_stm32mp1/board.c | 8 +- > 6 files changed, 372 insertions(+), 6 deletions(-) create mode 100644 > arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi > create mode 100644 arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi > create mode 100644 arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH 1/2] ARM: stm32: Define I2C EEPROM bus and address on DHCOM
Hi, > From: Marek Vasut > Sent: lundi 27 avril 2020 12:27 > > Define I2C EEPROM bus and address, so that the 'eeprom' command uses the > correct ones and does not generate the following error: > eeprom_rw_block: Cannot find udev for a bus 0 > > Signed-off-by: Marek Vasut > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > configs/stm32mp15_dhcom_basic_defconfig | 2 ++ > 1 file changed, 2 insertions(+) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH 2/2] ARM: stm32: Hog GPIO PF7 high on DHCOM to unlock SPI NOR nWP
Hi > From: Marek Vasut > Sent: lundi 27 avril 2020 12:27 > > The SPI NOR nWP line is connected to GPIO PF7 on the SoM, pull the GPIO line > high by default to clear SPI NOR WP. > > Signed-off-by: Marek Vasut > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 9 + > configs/stm32mp15_dhcom_basic_defconfig| 1 + > 2 files changed, 10 insertions(+) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH v4 1/2] arm: stm32mp: activate data cache in SPL and before relocation
Hi, > From: Patrick DELAUNAY > Sent: jeudi 30 avril 2020 16:30 > > Activate the data cache in SPL and in U-Boot before relocation. > > In arch_cpu_init(), the function early_enable_caches() sets the early TLB, > early_tlb[] located .init section, and set cacheable: > - for SPL, all the SYSRAM > - for U-Boot, all the DDR > > After relocation, the function enable_caches() (called by board_r) > reconfigures the > MMU with new TLB location (reserved in > board_f.c::reserve_mmu) and re-enable the data cache. > > This patch allows to reduce the execution time, particularly > - for the device tree parsing in U-Boot pre-reloc stage > (dm_extended_scan_fd =>dm_scan_fdt) > - in I2C timing computation in SPL (stm32_i2c_choose_solution()) > > For example, the result on STM32MP157C-DK2 board is: >1,6s gain for trusted boot chain with TF-A >2,2s gain for basic boot chain with SPL > > For information, as TLB is added in .data section, the binary size increased > and > the SPL load time by ROM code increased (30ms on DK2). > > But early malloc can't be used for TLB because arch_cpu_init() is executed > before > the early poll initialization done in spl_common_init() called by > spl_early_init() So it > too late for this use case. > And if I initialize the MMU and the cache after this function it is too late, > as > dm_init_and_scan and fdt parsing is also called in spl_common_init(). > > And .BSS can be used in board_init_f(): only stack and global can use before > BSS > init done in board_init_r(). > > So .data is the better solution without hardcoded location but if you have > size > issue for SPL you can deactivate cache for SPL only (with > CONFIG_SPL_SYS_DCACHE_OFF). > > Reviewed-by: Patrice Chotard > Signed-off-by: Patrick Delaunay > --- > > Changes in v4: > - fix commit message and comment and add Patrice Chotard reviewed-by > > Changes in v3: > - add Information in commit-message on early malloc and .BSS > > Changes in v2: > - create a new function early_enable_caches > - use TLB in .init section > - use the default weak dram_bank_mmu_setup() and > use mmu_set_region_dcache_behaviour() to setup > the early MMU configuration > - enable data cache on DDR in SPL, after DDR controller initialization > > arch/arm/mach-stm32mp/cpu.c | 43 > - > 1 file changed, 42 insertions(+), 1 deletion(-) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH v4 2/2] arm: stm32mp: activate data cache on DDR in SPL
Hi > From: Patrick DELAUNAY > Sent: jeudi 30 avril 2020 16:30 > > Activate cache on DDR to improve the accesses to DDR used by SPL: > - CONFIG_SPL_BSS_START_ADDR > - CONFIG_SYS_SPL_MALLOC_START > > Cache is configured only when DDR is fully initialized, to avoid speculative > access > and issue in get_ram_size(). > Data cache is deactivated at the end of SPL, to flush the data cache and the > TLB. > > Reviewed-by: Patrice Chotard > Signed-off-by: Patrick Delaunay > --- > > Changes in v4: > - fix commit message and add Patrice Chotard reviewed-by > > Changes in v3: > - remove debug message "bye" > > Changes in v2: > - new > > arch/arm/mach-stm32mp/spl.c | 19 +++ > 1 file changed, 19 insertions(+) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH] mmc: stm32_sdmmc2: change the displayed config name
Hi, > From: Patrick DELAUNAY > Sent: jeudi 30 avril 2020 09:52 > > Change the mmc displayed name in U-Boot for stm32_sdmmc2 driver to > “STM32 SD/MMC”. > > This stm32_sdmmc2 driver is for version 2 of the ST HW IP SDMMC but the > displayed name "STM32 SDMMC2" is confusing for user, between the instance of > SDMMC and the device identifier of MMC. > > For example on EV1 board, we have: > > STM32MP1> mmc list > STM32 SDMMC2: 0 (SD) > STM32 SDMMC2: 1 (eMMC) > > Changed to more clear: > > STM32MP1> mmc list > STM32 SD/MMC: 0 (SD) > STM32 SD/MMC: 1 (eMMC) > > Signed-off-by: Patrick Delaunay > --- > > drivers/mmc/stm32_sdmmc2.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH] clk: stm32mp1: fix CK_MPU calculation
Hi, > From: Patrick DELAUNAY > Sent: vendredi 24 avril 2020 15:48 > To: u-boot@lists.denx.de > Cc: Lionel DEBIEVE ; Patrick DELAUNAY > ; Lukasz Majewski ; Patrice > CHOTARD ; U-Boot STM32 mailman.stormreply.com> > Subject: [PATCH] clk: stm32mp1: fix CK_MPU calculation > Importance: High > > From: Lionel Debieve > > When the CK_MPU used PLL1_MPUDIV, the current rate is wrong. The clock > must use stm32mp1_mpu_div as a shift value. Fix the check value used to enter > PLL_MPUDIV. > > Signed-off-by: Lionel Debieve > Signed-off-by: Patrick Delaunay > --- > > drivers/clk/clk_stm32mp1.c | 7 --- > 1 file changed, 4 insertions(+), 3 deletions(-) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH] ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2
Hi, > From: Patrick DELAUNAY > Sent: jeudi 30 avril 2020 15:53 > To: u-boot@lists.denx.de > Cc: Patrick DELAUNAY ; Marek Vasut > ; Tom Rini ; U-Boot STM32 st...@st-md-mailman.stormreply.com> > Subject: [PATCH] ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2 > Importance: High > > DT alignment with Linux 5.7-rc2, including the kernel commits > > 431c89e6f323 ARM: dts: stm32: use correct vqmmc regu for eMMC on stm32mp1 > ED1/EV1 boards > 79e965053872 ARM: dts: stm32: add disable-wp property for SD-card on > STM32MP1 boards > 877db62ea516 ARM: dts: stm32: add cd-gpios properties for SD-cards on > STM32MP1 boards > 7519e95ba5f8 ARM: dts: stm32: Do clean up in stmpic nodes on stm32mp15 > boards f68e2dbc591a ARM: dts: stm32: Rename stmfx joystick pins on > stm32mp157c-ev1 d6210da4f8bf ARM: dts: stm32: add cpu clock-frequency > property on stm32mp15x > b65b6fc56925 ARM: dts: stm32: add wakeup-source in all I2C nodes of > stm32mp157c 1c1cf5996cfb ARM: dts: stm32: add i2c4 sleep pinctrl on > stm32mp157c-ed1 > bef15fc0fad9 ARM: dts: stm32: add i2c2/i2c5 sleep pinctrl on stm32mp157c-ev1 > b7fc0a87b9ac ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp15xx-dkx > a5e557655285 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp15 DK > boards > 8bc631b650a6 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp157c- > ed1 > fccd6a577bb3 ARM: dts: stm32: Correct stmfx node name on stm32mp157c-ev1 > board > cc775a83db65 ARM: dts: stm32: add resets property on all DMA nodes on > stm32mp151 c5fae093511b ARM: dts: stm32: enable USB OTG Dual Role on > stm32mp157c-ev1 > 9879e2165758 ARM: dts: stm32: add USB OTG pinctrl to stm32mp15 > 82ac8a81f985 ARM: dts: stm32: add USB OTG full support on stm32mp151 > 8714b26e2863 ARM: dts: stm32: remove useless properties in stm32mp157a- > avenger96 stmpic node a7959919709e ARM: dts: stm32: Add UART8 pins A > pinmux entry on stm32mp1 4d7c53a684da ARM: dts: stm32: Add USART3 pins A > pinmux entry on stm32mp1 80ab128332ee ARM: dts: stm32: Add SAI2A pins B > pinmux entry on stm32mp1 > ab7f98c0c546 ARM: dts: stm32: Add Ethernet0 RMII pins A pinmux entry on > stm32mp1 > > Signed-off-by: Patrick Delaunay > --- > Hi, > > Dependency with correction of GPIO support in SPL: > > [v2,09/12] gpio: stm32: support gpio ops in SPL > http://patchwork.ozlabs.org/project/uboot/patch/20200422142834.v2.9.I355ddbc80 > 4eba6047ea147d830be57a5b9c4a87e@changeid/ > > Patrick > > > arch/arm/dts/stm32mp15-pinctrl.dtsi | 92 + > arch/arm/dts/stm32mp151.dtsi| 13 +++- > arch/arm/dts/stm32mp153.dtsi| 1 + > arch/arm/dts/stm32mp157c-ed1.dts| 12 ++-- > arch/arm/dts/stm32mp157c-ev1.dts| 13 ++-- > arch/arm/dts/stm32mp15xx-dhcom.dtsi | 3 +- arch/arm/dts/stm32mp15xx- > dhcor.dtsi | 8 --- > arch/arm/dts/stm32mp15xx-dkx.dtsi | 10 ++-- > 8 files changed, 126 insertions(+), 26 deletions(-) > Applied to u-boot-stm/master, thanks! Regards Patrick
RE: [PATCH] armv8: ls1012a: Pass PPFE firmware to Linux through FDT.
> -Original Message- > From: Priyanka Jain (OSS) > Sent: Tuesday, May 12, 2020 2:57 PM > To: Chaitanya Sakinam ; u- > b...@lists.denx.de; joe.hershber...@ni.com > Cc: bmeng...@gmail.com; Alexandru Marginean > ; s...@chromium.org; Z.q. Hou > ; Andy Tang ; > tommyh...@gmail.com; Anji Jagarlmudi ; > Chaitanya Sakinam > Subject: RE: [PATCH] armv8: ls1012a: Pass PPFE firmware to Linux through > FDT. > > >-Original Message- > >From: U-Boot On Behalf Of Chaitanya > >Sakinam > >Sent: Tuesday, April 28, 2020 3:25 PM > >To: u-boot@lists.denx.de; joe.hershber...@ni.com; Priyanka Jain > > > >Cc: bmeng...@gmail.com; Alexandru Marginean > >; s...@chromium.org; Z.q. Hou > >; Andy Tang ; > >tommyh...@gmail.com; Anji Jagarlmudi ; > >Chaitanya Sakinam > >Subject: [PATCH] armv8: ls1012a: Pass PPFE firmware to Linux through FDT. > Don't use period '.' in subject Ok, I will correct it. > > > > >Read Linux PPFE firmware from flash partition and pass it to Linux > >through FDT entry. So that we can avoid placing PPFE firmware in Linux > rootfs. > > > How much fdt size you are increasing with this change? FDT may increase at max by 64KB. > > >Signed-off-by: Chaitanya Sakinam > >Signed-off-by: Anji J > >--- > > > Regards > Priyanka Regards, Chaitanya
[PATCH v2 01/12] mips: start.S: Add CONFIG_MIPS_INIT_JUMP_OFFSET
This Kconfig symbol will be introduced with the base Octeon MIPS support. Using it, its possible to use a TEXT_BASE address which differs from the reset PC. And with the earliest function call to mips_sram_init() the CPU will transfer execution to the actual TEXT_BASE region. So after returning from this function, all absolute addresses are okay again. This will be used by the Octeon platform to copy the U-Boot image into L2 cache and transfer execution to the cache to speed up the execution. Signed-off-by: Stefan Roese --- Changes in v2: - New patch arch/mips/cpu/start.S | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6de9a2f362..f601662cd0 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -222,6 +222,10 @@ wr_done: #ifdef CONFIG_MIPS_SRAM_INIT /* Initialize the SRAM first */ PTR_LA t9, mips_sram_init +#ifdef CONFIG_MIPS_INIT_JUMP_OFFSET + PTR_SUBU \ + t9, t9, (CONFIG_SYS_TEXT_BASE - CONFIG_MIPS_INIT_JUMP_OFFSET) +#endif jalrt9 nop #endif -- 2.26.2
[PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel UART, reset and NOR flash are supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Thanks, Stefan Changes in v2: - New patch - New patch - Restructure patch by adding empty functions to asm/cm.h instead - New patch - New patch - Move bit macro definition to mipsregs.h - Remove custom start.S and use common start.S. Minimal custom lowlevel init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt. - Removed select CREATE_ARCH_SYMLINK - Removed Octeon II support, as its currently no added in this patchset - Added cache.c to add the platform specific cache functions as no-ops for Octeon as the platform is cache coherent - Removed CONFIG_MIPS_CACHE_COHERENT - Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon to enable better sync with the Linux files in the future - Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more - Removed CONFIG_SYS_MIPS_TIMER_FREQ Aaron Williams (2): mips: mipsregs.h: Add more register macros for Octeon port mips: octeon: Initial minimal support for the Marvell Octeon SoC Stefan Roese (10): mips: start.S: Add CONFIG_MIPS_INIT_JUMP_OFFSET mips: start.S: Don't call mips_cache_reset() on ARCH_OCTEON mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM mips: cache: Make flush_cache() weak to enable overwrite mips: time: Only compile the weak get_tbclk() when needed mips: traps: Set WG bit in EBase register on Octeon mips: mipsregs.h: Sync with linux v5.7.0-rc3 version sysreset: Add Octeon sysreset driver mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file mips: octeon: Add minimal Octeon 3 EBB7304 EVK support MAINTAINERS | 7 ++ arch/mips/Kconfig | 43 + arch/mips/Makefile| 3 + arch/mips/cpu/start.S | 6 ++ arch/mips/cpu/time.c | 2 + arch/mips/dts/Makefile| 1 + arch/mips/dts/mrvl,cn73xx.dtsi| 64 + arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 +++ arch/mips/include/asm/cm.h| 12 +++ arch/mips/include/asm/mipsregs.h | 64 + arch/mips/lib/cache.c | 4 +- arch/mips/lib/traps.c | 4 + arch/mips/mach-octeon/Kconfig | 67 + arch/mips/mach-octeon/Makefile| 10 ++ arch/mips/mach-octeon/cache.c | 20 arch/mips/mach-octeon/clock.c | 27 ++ arch/mips/mach-octeon/cpu.c | 55 +++ arch/mips/mach-octeon/dram.c | 27 ++ arch/mips/mach-octeon/include/ioremap.h | 30 ++ arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 arch/mips/mach-octeon/include/mach/clock.h| 24 + arch/mips/mach-octeon/lowlevel_init.S | 75 +++ board/Marvell/octeon_ebb7304/Kconfig | 19 board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++ board/Marvell/octeon_ebb7304/Makefile | 8 ++ board/Marvell/octeon_ebb7304/board.c | 12 +++ configs/octeon_ebb7304_defconfig | 34 +++ drivers/sysreset/Kconfig | 7 ++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_octeon.c| 52 ++ include/configs/octeon_common.h | 25 + include/configs/octeon_ebb7304.h | 20 scripts/config_whitelist.txt | 1 - 33 files changed, 846 insertions(+), 23 deletions(-) create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/cache.c create mode 100644 arch/mips/mach-octeon/clock.c create mode 100644 arch/mips/mach-octeon/cpu.c create mode 100644 arch/mips/mach-octeon/dram.c create mode 100644 arch/mips/mach-octeon/include/ioremap.h create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h create mode 100644 arch/mips/mach-octeon/include/mach/clock.h create mode 100644 arch/mips/mach-octeon/lowlevel_init.S create mode 100644 board/Marvell/octeon_ebb7304/Kconfig create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS create mode 100644 board/Marvell/octeon_ebb7304/Makefile create mode 100
[PATCH v2 04/12] mips: cache: Make flush_cache() weak to enable overwrite
This patch adds __weak to flush_cache() in lib/cache.c. This makes it
possible to overwrite this function by a platforms specific version,
like done with the Octeon base port.
Signed-off-by: Stefan Roese
---
Changes in v2:
- New patch
arch/mips/lib/cache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index fdffe9493b..8dd025a79e 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -105,7 +105,7 @@ static inline unsigned long scache_line_size(void)
} \
} while (0)
-void flush_cache(ulong start_addr, ulong size)
+void __weak flush_cache(ulong start_addr, ulong size)
{
unsigned long ilsize = icache_line_size();
unsigned long dlsize = dcache_line_size();
--
2.26.2
[PATCH v2 03/12] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM
This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.
Signed-off-by: Stefan Roese
---
Changes in v2:
- Restructure patch by adding empty functions to asm/cm.h instead
arch/mips/include/asm/cm.h | 12
arch/mips/lib/cache.c | 2 --
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
index 8f37471f81..06d721d228 100644
--- a/arch/mips/include/asm/cm.h
+++ b/arch/mips/include/asm/cm.h
@@ -40,6 +40,7 @@
#include
+#if CONFIG_IS_ENABLED(MIPS_CM)
static inline void *mips_cm_base(void)
{
return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
@@ -55,6 +56,17 @@ static inline unsigned long mips_cm_l2_line_size(void)
line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
return line_sz ? (2 << line_sz) : 0;
}
+#else
+static inline void *mips_cm_base(void)
+{
+ return NULL;
+}
+
+static inline unsigned long mips_cm_l2_line_size(void)
+{
+ return 0;
+}
+#endif
#endif /* !__ASSEMBLY__ */
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 1a8c87d094..fdffe9493b 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -7,9 +7,7 @@
#include
#include
#include
-#ifdef CONFIG_MIPS_L2_CACHE
#include
-#endif
#include
#include
#include
--
2.26.2
[PATCH v2 05/12] mips: time: Only compile the weak get_tbclk() when needed
This patch opts-out the compilation of get_tbclk() if
CONFIG_SYS_MIPS_TIMER_FREQ is not defined. This is used on the Octeon
platform, where the weak get_tbclk() function is overwritten by its
platform specific one.
Signed-off-by: Stefan Roese
---
Changes in v2:
- New patch
arch/mips/cpu/time.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/cpu/time.c b/arch/mips/cpu/time.c
index e0c1868b8c..5e7a7144d0 100644
--- a/arch/mips/cpu/time.c
+++ b/arch/mips/cpu/time.c
@@ -13,7 +13,9 @@ unsigned long notrace timer_read_counter(void)
return read_c0_count();
}
+#if defined(CONFIG_SYS_MIPS_TIMER_FREQ)
ulong notrace __weak get_tbclk(void)
{
return CONFIG_SYS_MIPS_TIMER_FREQ;
}
+#endif
--
2.26.2
[PATCH v2 07/12] mips: mipsregs.h: Add more register macros for Octeon port
From: Aaron Williams Thips patch adds some more register definitions which will be used by the Octeon platform. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- Changes in v2: None arch/mips/include/asm/mipsregs.h | 19 ++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 998f84d0a1..5214b3197e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -40,15 +40,20 @@ #define CP0_CONF $3 #define CP0_GLOBALNUMBER $3, 1 #define CP0_CONTEXT $4 +#define CP0_USERLOCAL $4, 2 #define CP0_PAGEMASK $5 +#define CP0_PAGEGRAIN $5, 1 #define CP0_WIRED $6 #define CP0_INFO $7 #define CP0_HWRENA $7, 0 #define CP0_BADVADDR $8 #define CP0_BADINSTR $8, 1 #define CP0_COUNT $9 +#define CP0_CVMCOUNT $9, 6 +#define CP0_CVMCTL $9, 7 #define CP0_ENTRYHI $10 #define CP0_COMPARE $11 +#define CP0_CVMMEMCTL $11, 7 #define CP0_STATUS $12 #define CP0_CAUSE $13 #define CP0_EPC $14 @@ -56,8 +61,11 @@ #define CP0_EBASE $15, 1 #define CP0_CMGCRBASE $15, 3 #define CP0_CONFIG $16 +#define CP0_CONFIG1 $16, 1 #define CP0_CONFIG3 $16, 3 +#define CP0_CONFIG4 $16, 4 #define CP0_CONFIG5 $16, 5 +#define CP0_CVMMEMCTL2 $16, 6 #define CP0_LLADDR $17 #define CP0_WATCHLO $18 #define CP0_WATCHHI $19 @@ -67,13 +75,22 @@ #define CP0_DEBUG $23 #define CP0_DEPC $24 #define CP0_PERFORMANCE $25 +#define CP0_PERF_CNT0 $25, 1 +#define CP0_PERF_CNT1 $25, 3 +#define CP0_PERF_CNT2 $25, 5 +#define CP0_PERF_CNT3 $25, 7 #define CP0_ECC $26 #define CP0_CACHEERR $27 +#define CP0_CACHEERR_ICACHE $27 +#define CP0_CACHEERR_DCACHE $27, 1 #define CP0_TAGLO $28 #define CP0_TAGHI $29 #define CP0_ERROREPC $30 #define CP0_DESAVE $31 - +#define CP0_KSCRATCH1 $31, 2 +#define CP0_KSCRATCH2 $31, 3 +#define CP0_KSCRATCH3 $31, 4 +#define CP0_KSCRATCH4 $31, 5 /* * R4640/R4650 cp0 register names. These registers are listed * here only for completeness; without MMU these CPUs are not useable -- 2.26.2
[PATCH v2 11/12] mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC.
Signed-off-by: Stefan Roese
---
Changes in v2: None
MAINTAINERS| 1 +
arch/mips/dts/mrvl,cn73xx.dtsi | 64 ++
2 files changed, 65 insertions(+)
create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f4c325df4..15fd270762 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -757,6 +757,7 @@ M: Aaron Williams
S: Maintained
F: arch/mips/mach-octeon/
F: arch/mips/include/asm/arch-octeon/
+F: arch/mips/dts/mrvl,cn73xx.dtsi
MMC
M: Peng Fan
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
new file mode 100644
index 00..90872a3b4b
--- /dev/null
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell / Cavium Inc. CN73xx
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ soc@0 {
+ interrupt-parent = <&ciu3>;
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges; /* Direct mapping */
+
+ ciu3: interrupt-controller@10100 {
+ compatible = "cavium,octeon-7890-ciu3";
+ interrupt-controller;
+ /*
+* Interrupts are specified by two parts:
+* 1) Source number (20 significant bits)
+* 2) Trigger type: (4 == level, 1 == edge)
+*/
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x10100 0x 0x0 0xb000>;
+ };
+
+ bootbus: bootbus@11800 {
+ compatible = "cavium,octeon-3860-bootbus","simple-bus";
+ reg = <0x11800 0x 0x0 0x200>;
+ /* The chip select number and offset */
+ #address-cells = <2>;
+ /* The size of the chip select region */
+ #size-cells = <1>;
+ };
+
+ reset: reset@1180006001600 {
+ compatible = "mrvl,cn7xxx-rst";
+ reg = <0x11800 0x06001600 0x0 0x200>;
+ };
+
+ uart0: serial@118000800 {
+ compatible = "cavium,octeon-3860-uart","ns16550";
+ reg = <0x11800 0x0800 0x0 0x400>;
+ clock-frequency = <0>;
+ current-speed = <115200>;
+ reg-shift = <3>;
+ interrupts = <0x08000 4>;
+ };
+
+ uart1: serial@118000c00 {
+ compatible = "cavium,octeon-3860-uart","ns16550";
+ reg = <0x11800 0x0c00 0x0 0x400>;
+ clock-frequency = <0>;
+ current-speed = <115200>;
+ reg-shift = <3>;
+ interrupts = <0x08040 4>;
+ };
+ };
+};
--
2.26.2
[PATCH v2 09/12] sysreset: Add Octeon sysreset driver
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.
Signed-off-by: Stefan Roese
---
Changes in v2: None
drivers/sysreset/Kconfig | 7
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_octeon.c | 52 ++
3 files changed, 60 insertions(+)
create mode 100644 drivers/sysreset/sysreset_octeon.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 4be7433404..6ebc90e1d3 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -57,6 +57,13 @@ config SYSRESET_MICROBLAZE
help
This is soft reset on Microblaze which does jump to 0x0 address.
+config SYSRESET_OCTEON
+ bool "Enable support for Marvell Octeon SoC family"
+ depends on ARCH_OCTEON
+ help
+ This enables the system reset driver support for Marvell Octeon
+ SoCs.
+
config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 3ed4bab9e3..df2293b848 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
+obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
diff --git a/drivers/sysreset/sysreset_octeon.c
b/drivers/sysreset/sysreset_octeon.c
new file mode 100644
index 00..a05dac3226
--- /dev/null
+++ b/drivers/sysreset/sysreset_octeon.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Stefan Roese
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define RST_SOFT_RST 0x0080
+
+struct octeon_sysreset_data {
+ void __iomem *base;
+};
+
+static int octeon_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+ writeq(1, data->base + RST_SOFT_RST);
+
+ return -EINPROGRESS;
+}
+
+static int octeon_sysreset_probe(struct udevice *dev)
+{
+ struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+ data->base = dev_remap_addr(dev);
+
+ return 0;
+}
+
+static struct sysreset_ops octeon_sysreset = {
+ .request = octeon_sysreset_request,
+};
+
+static const struct udevice_id octeon_sysreset_ids[] = {
+ { .compatible = "mrvl,cn7xxx-rst" },
+ { }
+};
+
+U_BOOT_DRIVER(sysreset_octeon) = {
+ .id = UCLASS_SYSRESET,
+ .name = "octeon_sysreset",
+ .priv_auto_alloc_size = sizeof(struct octeon_sysreset_data),
+ .ops= &octeon_sysreset,
+ .probe = octeon_sysreset_probe,
+ .of_match = octeon_sysreset_ids,
+};
--
2.26.2
[PATCH v2 06/12] mips: traps: Set WG bit in EBase register on Octeon
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register. Signed-off-by: Stefan Roese --- Changes in v2: - Move bit macro definition to mipsregs.h arch/mips/include/asm/mipsregs.h | 1 + arch/mips/lib/traps.c| 4 2 files changed, 5 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index f80311e64e..998f84d0a1 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -365,6 +365,7 @@ * Bits in the coprocessor 0 EBase register. */ #define EBASE_CPUNUM 0x3ff +#define EBASE_WG (_ULCAST_(1) << 11) /* * Bits in the coprocessor 0 config register. diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 8fff7541e3..dfef97dce3 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -106,6 +106,10 @@ void trap_init(ulong reloc_addr) saved_ebase = read_c0_ebase() & 0xf000; + /* Set WG bit on Octeon to enable writing to bits 63:30 */ + if (IS_ENABLED(CONFIG_ARCH_OCTEON)) + ebase |= EBASE_WG; + write_c0_ebase(ebase); clear_c0_status(ST0_BEV); execution_hazard_barrier(); -- 2.26.2
[PATCH v2 02/12] mips: start.S: Don't call mips_cache_reset() on ARCH_OCTEON
Since Octeon now runs from L2 cache, we can't reset the cache at this time. So let's opt-out this function on Octeon, as the cache is coherent on Octeon anyways. Signed-off-by: Stefan Roese --- Changes in v2: - New patch arch/mips/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index f601662cd0..b3c9978a83 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -249,10 +249,12 @@ wr_done: nop # endif +# ifndef CONFIG_ARCH_OCTEON /* Initialize caches... */ PTR_LA t9, mips_cache_reset jalrt9 nop +# endif # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Initialize any external memory */ -- 2.26.2
[PATCH v2 10/12] mips: octeon: Initial minimal support for the Marvell Octeon SoC
From: Aaron Williams This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- Changes in v2: - Remove custom start.S and use common start.S. Minimal custom lowlevel init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt. - Removed select CREATE_ARCH_SYMLINK - Removed Octeon II support, as its currently no added in this patchset - Added cache.c to add the platform specific cache functions as no-ops for Octeon as the platform is cache coherent - Removed CONFIG_MIPS_CACHE_COHERENT - Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon to enable better sync with the Linux files in the future - Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more MAINTAINERS | 6 ++ arch/mips/Kconfig | 43 +++ arch/mips/Makefile| 3 + arch/mips/mach-octeon/Kconfig | 53 + arch/mips/mach-octeon/Makefile| 10 +++ arch/mips/mach-octeon/cache.c | 20 + arch/mips/mach-octeon/clock.c | 27 +++ arch/mips/mach-octeon/cpu.c | 55 ++ arch/mips/mach-octeon/dram.c | 27 +++ arch/mips/mach-octeon/include/ioremap.h | 30 arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 +++ arch/mips/mach-octeon/include/mach/clock.h| 24 ++ arch/mips/mach-octeon/lowlevel_init.S | 75 +++ scripts/config_whitelist.txt | 1 - 14 files changed, 415 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/cache.c create mode 100644 arch/mips/mach-octeon/clock.c create mode 100644 arch/mips/mach-octeon/cpu.c create mode 100644 arch/mips/mach-octeon/dram.c create mode 100644 arch/mips/mach-octeon/include/ioremap.h create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h create mode 100644 arch/mips/mach-octeon/include/mach/clock.h create mode 100644 arch/mips/mach-octeon/lowlevel_init.S diff --git a/MAINTAINERS b/MAINTAINERS index ec59ce8b88..7f4c325df4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -752,6 +752,12 @@ M: Ezequiel Garcia S: Maintained F: arch/mips/mach-jz47xx/ +MIPS Octeon +M: Aaron Williams +S: Maintained +F: arch/mips/mach-octeon/ +F: arch/mips/include/asm/arch-octeon/ + MMC M: Peng Fan S: Maintained diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 48e754cc46..bc5ad0c3ff 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -106,6 +106,25 @@ config ARCH_JZ47XX select OF_CONTROL select DM +config ARCH_OCTEON + bool "Support Marvell Octeon CN7xxx platforms" + select CPU_CAVIUM_OCTEON + select DISPLAY_CPUINFO + select DMA_ADDR_T_64BIT + select DM + select DM_SERIAL + select MIPS_INIT_STACK_IN_SRAM + select MIPS_L2_CACHE + select MIPS_TUNE_OCTEON3 + select MIPS_SRAM_INIT + select ROM_EXCEPTION_VECTORS + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS64_OCTEON + select PHYS_64BIT + select OF_CONTROL + select OF_LIVE + imply CMD_DM + config MACH_PIC32 bool "Support Microchip PIC32" select DM @@ -160,6 +179,7 @@ source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-jz47xx/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mtmips/Kconfig" +source "arch/mips/mach-octeon/Kconfig" if MIPS @@ -233,6 +253,14 @@ config CPU_MIPS64_R6 Choose this option to build a kernel for release 6 or later of the MIPS64 architecture. +config CPU_MIPS64_OCTEON + bool "Marvell Octeon series of CPUs" + depends on SUPPORTS_CPU_MIPS64_OCTEON + select 64BIT + help +Choose this option for Marvell Octeon CPUs. These CPUs are between +MIPS64 R5 and R6 with other extensions. + endchoice menu "General setup" @@ -398,6 +426,12 @@ config SUPPORTS_CPU_MIPS64_R2 config SUPPORTS_CPU_MIPS64_R6 bool +config SUPPORTS_CPU_MIPS64_OCTEON + bool + +config CPU_CAVIUM_OCTEON + bool + config CPU_MIPS32 bool default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 @@ -405,6 +439,7 @@ config CPU
[PATCH v2 12/12] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this board.
Supported devices:
- UART
- reset
- CFI parallel NOR flash
Signed-off-by: Stefan Roese
---
Changes in v2:
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mrvl,octeon-ebb7304.dts| 96
arch/mips/mach-octeon/Kconfig| 14
board/Marvell/octeon_ebb7304/Kconfig | 19 +
board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++
board/Marvell/octeon_ebb7304/Makefile| 8 ++
board/Marvell/octeon_ebb7304/board.c | 12 +++
configs/octeon_ebb7304_defconfig | 34 +
include/configs/octeon_common.h | 25 ++
include/configs/octeon_ebb7304.h | 20 +
10 files changed, 236 insertions(+)
create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts
create mode 100644 board/Marvell/octeon_ebb7304/Kconfig
create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS
create mode 100644 board/Marvell/octeon_ebb7304/Makefile
create mode 100644 board/Marvell/octeon_ebb7304/board.c
create mode 100644 configs/octeon_ebb7304_defconfig
create mode 100644 include/configs/octeon_common.h
create mode 100644 include/configs/octeon_ebb7304.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index f711e9fb59..dc85901dca 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
+dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts
b/arch/mips/dts/mrvl,octeon-ebb7304.dts
new file mode 100644
index 00..4e9c2de7d4
--- /dev/null
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell / Cavium Inc. EVB CN7300
+ */
+
+/dts-v1/;
+
+/include/ "mrvl,cn73xx.dtsi"
+
+/ {
+ model = "cavium,ebb7304";
+ compatible = "cavium,ebb7304";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&bootbus {
+ /*
+* bootbus CS0 for CFI flash is remapped (0x1fc0. -> 1f40.)
+* as the initial size is too small for the 8MiB flash device
+*/
+ ranges = <0 0 0 0x1f40 0xc0>,
+<1 0 0x1 0x1000 0>,
+<2 0 0x1 0x2000 0>,
+<3 0 0x1 0x3000 0>,
+<4 0 0 0x1d02 0x1>,
+<5 0 0x1 0x5000 0>,
+<6 0 0x1 0x6000 0>,
+<7 0 0x1 0x7000 0>;
+
+ cavium,cs-config@0 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <0>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <50>;
+ cavium,t-oe = <50>;
+ cavium,t-we = <35>;
+ cavium,t-rd-hld = <25>;
+ cavium,t-wr-hld = <35>;
+ cavium,t-pause = <0>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <30>;
+ cavium,t-rd-dly = <0>;
+ cavium,page-mode = <1>;
+ cavium,pages = <8>;
+ cavium,bus-width = <8>;
+ };
+
+ cavium,cs-config@4 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <4>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <10>;
+ cavium,t-oe = <160>;
+ cavium,t-we = <100>;
+ cavium,t-rd-hld = <10>;
+ cavium,t-wr-hld = <0>;
+ cavium,t-pause = <50>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <10>;
+ cavium,t-rd-dly = <10>;
+ cavium,pages = <0>;
+ cavium,bus-width = <8>;
+ };
+
+ flash0: nor@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "bootloader";
+ reg = <0 0x34>;
+ read-only;
+ };
+ partition@30 {
+ label = "storage";
+
[PATCH v2 08/12] mips: mipsregs.h: Sync with linux v5.7.0-rc3 version
Using .set mips3/32/64 without .set push/pop is fragile. This patch
solves this issue by sync'ing the inline-asm functions with the
latest Linux ones.
Signed-off-by: Stefan Roese
---
Changes in v2: None
arch/mips/include/asm/mipsregs.h | 44 +++-
1 file changed, 26 insertions(+), 18 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 5214b3197e..4f6d52254e 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -935,9 +935,10 @@ do {
\
: "=r" (__res));\
else\
__asm__ __volatile__( \
+ ".set\tpush\n\t"\
".set\tmips32\n\t" \
"mfc0\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
+ ".set\tpop\n\t" \
: "=r" (__res));\
__res; \
})
@@ -948,15 +949,17 @@ do {
\
__res = __read_64bit_c0_split(source, sel); \
else if (sel == 0) \
__asm__ __volatile__( \
+ ".set\tpush\n\t"\
".set\tmips3\n\t" \
"dmfc0\t%0, " #source "\n\t"\
- ".set\tmips0" \
+ ".set\tpop" \
: "=r" (__res));\
else\
__asm__ __volatile__( \
+ ".set\tpush\n\t"\
".set\tmips64\n\t" \
"dmfc0\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: "=r" (__res));\
__res; \
})
@@ -969,9 +972,10 @@ do {
\
: : "Jr" ((unsigned int)(value))); \
else\
__asm__ __volatile__( \
+ ".set\tpush\n\t"\
".set\tmips32\n\t" \
"mtc0\t%z0, " #register ", " #sel "\n\t"\
- ".set\tmips0" \
+ ".set\tpop" \
: : "Jr" ((unsigned int)(value))); \
} while (0)
@@ -981,15 +985,17 @@ do {
\
__write_64bit_c0_split(register, sel, value); \
else if (sel == 0) \
__asm__ __volatile__( \
+ ".set\tpush\n\t"\
".set\tmips3\n\t" \
"dmtc0\t%z0, " #register "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: : "Jr" (value)); \
else\
__asm__ __volatile__( \
+ ".set\tpush\n\t"\
".set\tmips64\n\t" \
"dmtc0\t%z0, " #register ", " #sel "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: : "Jr" (value)); \
} while (0)
@@ -1034,21 +1040,21 @@ do {
[PULL] Pull request: u-boot-stm/master =u-boot-stm32-20200514
Hi Tom, Please pull the STM32 related fixes for v2020.07-rc3 = u-boot-stm32-20200514 With the following changes: - stm32mp1: migrate MTD and DFU configuration in Kconfig - stm32mp1: add command stm32prog - stm32mp1: several board and arch updates - stm32mp1: activate data cache in SPL and before relocation - Many improvement for AV96 board and DHCOR SoM (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM) - clk: stm32mp1: fix CK_MPU calculation - DT alignment of stm32mp1 device tree with Linux 5.7-rc2 CI status: https://gitlab.denx.de/u-boot/custodians/u-boot-stm/pipelines/3238> Thanks, Patrick The following changes since commit 10bca13ea6d9d4b85f80f02c8795227f63240f59: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb (2020-05-12 16:20:10 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git tags/u-boot-stm32-20200514 for you to fetch changes up to 1b28a5e2b00a9bf3523cc63694baa03f23604619: ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2 (2020-05-14 09:02:12 +0200) - stm32mp1: migrate MTD and DFU configuration in Kconfig - stm32mp1: add command stm32prog - stm32mp1: several board and arch updates - stm32mp1: activate data cache in SPL and before relocation - Many improvment for AV96 board and DHCOR SoM (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM) - clk: stm32mp1: fix CK_MPU calculation - DT alignment of stm32mp1 device tree with Linux 5.7-rc2 Christophe Roullier (1): configs: stm32mp1: activate Ethernet PHY Realtek Lionel Debieve (1): clk: stm32mp1: fix CK_MPU calculation Marek Vasut (10): ARM: stm32: Add default config for DHCOR ARM: stm32: Add board_early_init_f() to SPL ARM: stm32: Implement board coding on AV96 ram: stm32mp1: Add support for multiple configs ARM: dts: stm32: Rework DDR DT inclusion ARM: stm32: Implement DDR3 coding on DHCOR SoM ARM: dts: stm32: Fix AV96 and DHCOR split ARM: dts: stm32: Synchronize DDR setttings on DH SoMs ARM: stm32: Define I2C EEPROM bus and address on DHCOM ARM: stm32: Hog GPIO PF7 high on DHCOM to unlock SPI NOR nWP Patrice Chotard (2): board: stm32mp1: Keep error led ON in case of low power detection stm32mp1: Fix warning display when 1.5A power supply is used Patrick Delaunay (43): board: stm32mp1: move board_get_mtdparts in st common directory board: stm32mp1: move set_dfu_alt_info in st common directory stm32mp1: dynamically build DFU_ALT_INFO stm32mp1: move MTDPART configuration in Kconfig board: stm32mp1: reserve memory for OP-TEE in device tree stm32mp1: dynamically detect op-tee presence board: stm32mp1: use FDT address provided by TF-A at boot time configs: stm32mp1: remove optee defconfig board: stm32mp1: support boot from spi-nand board: stm32mp1: adapt MTD partition for BOOT from NOR or NAND doc: stm32mp1: update DFU support example usb: gadget: g_dnl: add function g_dnl_set_product dfu: add prototype for dfu_transaction_initiate/cleanup stm32mp: add function get_cpu_dev stm32mp: add the command stm32prog stm32mp: stm32prog: add flash layout parsing stm32mp: stm32prog: add MMC device stm32mp: stm32prog: add support of boot partition for eMMC device stm32mp: stm32prog: add upport of partial update stm32mp: stm32prog: add MTD devices support stm32mp: stm32prog: adapt the MTD partitions stm32mp: stm32prog: add support of ssbl copy stm32mp: stm32prog: add support for delete option in flashlayout stm32mp: stm32prog: add otp update support stm32mp: stm32prog: add pmic NVM update support stm32mp: stm32prog: add serial link support stm32mp: stm32prog: enable videoconsole stm32mp: stm32prog: support for script stm32mp: stm32prog: add support of RAM target arm: stm32mp: remove dependency for STM32KEY arm: stm32mp: spl: update error management in board_init_f board: stm32mp1: update management of boot-led board: stm32mp1: gt9147 IRQ before reset on EV1 board: stm32mp1: set environment variable fdtfile board: stm32mp1: remove bootdelay configuration for usb or serial boot board: stm32mp1: add timeout for I/O compensation ready gpio: stm32: support gpio ops in SPL ARM: dts: stm32mp15: use DDR3 files generated by STM32CubeMX configs: stm32mp1: activate CONFIG_ERRNO_STR arm: stm32mp: activate data cache in SPL and before relocation arm: stm32mp: activate data cache on DDR in SPL mmc: stm32_sdmmc2: change the displayed config n
[PATCH v10 01/18] misc: add driver for the SiFive otp controller
Added a misc driver to handle OTP memory in SiFive SoCs.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/sifive-otp.c | 273 ++
3 files changed, 281 insertions(+)
create mode 100644 drivers/misc/sifive-otp.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 766402745d..59f758661e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -68,6 +68,13 @@ config ROCKCHIP_OTP
addressing and a length or through child-nodes that are generated
based on the e-fuse map retrieved from the DTS.
+config SIFIVE_OTP
+ bool "SiFive eMemory OTP driver"
+ depends on MISC
+ help
+ Enable support for reading and writing the eMemory OTP on the
+ SiFive SoCs.
+
config VEXPRESS_CONFIG
bool "Enable support for Arm Versatile Express config bus"
depends on MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 68e0e7ad17..947bd3a647 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
+obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
diff --git a/drivers/misc/sifive-otp.c b/drivers/misc/sifive-otp.c
new file mode 100644
index 00..6a788f540d
--- /dev/null
+++ b/drivers/misc/sifive-otp.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
+ * One-Time-Programmable (OTP) memory used within the SiFive FU540.
+ * It is documented in the FU540 manual here:
+ * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
+ *
+ * Copyright (C) 2018 Philipp Hug
+ * Copyright (C) 2018 Joey Hewitt
+ *
+ * Copyright (C) 2020 SiFive, Inc
+ */
+
+/*
+ * The FU540 stores 4096x32 bit (16KiB) values.
+ * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
+ * Right now first 1KiB is used to store only serial number.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define BYTES_PER_FUSE 4
+
+#define PA_RESET_VAL 0x00
+#define PAS_RESET_VAL 0x00
+#define PAIO_RESET_VAL 0x00
+#define PDIN_RESET_VAL 0x00
+#define PTM_RESET_VAL 0x00
+
+#define PCLK_ENABLE_VALBIT(0)
+#define PCLK_DISABLE_VAL 0x00
+
+#define PWE_WRITE_ENABLE BIT(0)
+#define PWE_WRITE_DISABLE 0x00
+
+#define PTM_FUSE_PROGRAM_VAL BIT(1)
+
+#define PCE_ENABLE_INPUT BIT(0)
+#define PCE_DISABLE_INPUT 0x00
+
+#define PPROG_ENABLE_INPUT BIT(0)
+#define PPROG_DISABLE_INPUT0x00
+
+#define PTRIM_ENABLE_INPUT BIT(0)
+#define PTRIM_DISABLE_INPUT0x00
+
+#define PDSTB_DEEP_STANDBY_ENABLE BIT(0)
+#define PDSTB_DEEP_STANDBY_DISABLE 0x00
+
+/* Tpw - Program Pulse width delay */
+#define TPW_DELAY 20
+
+/* Tpwi - Program Pulse interval delay */
+#define TPWI_DELAY 5
+
+/* Tasp - Program address setup delay */
+#define TASP_DELAY 1
+
+/* Tcd - read data access delay */
+#define TCD_DELAY 40
+
+/* Tkl - clok pulse low delay */
+#define TKL_DELAY 10
+
+/* Tms - PTM mode setup delay */
+#define TMS_DELAY 1
+
+struct sifive_otp_regs {
+ u32 pa; /* Address input */
+ u32 paio; /* Program address input */
+ u32 pas;/* Program redundancy cell selection input */
+ u32 pce;/* OTP Macro enable input */
+ u32 pclk; /* Clock input */
+ u32 pdin; /* Write data input */
+ u32 pdout; /* Read data output */
+ u32 pdstb; /* Deep standby mode enable input (active low) */
+ u32 pprog; /* Program mode enable input */
+ u32 ptc;/* Test column enable input */
+ u32 ptm;/* Test mode enable input */
+ u32 ptm_rep;/* Repair function test mode enable input */
+ u32 ptr;/* Test row enable input */
+ u32 ptrim; /* Repair function enable input */
+ u32 pwe;/* Write enable input (defines program cycle) */
+};
+
+struct sifive_otp_platdata {
+ struct sifive_otp_regs __iomem *regs;
+ u32 total_fuses;
+};
+
+/*
+ * offset and size are assumed aligned to the size of the fuses (32-bit).
+ */
+static int sifive_otp_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
+
+ /* Check if offset
[PATCH v10 02/18] riscv: sifive: fu540: Use OTP DM driver for serial environment variable
Use the OTP DM driver to set the serial environment variable.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 2 +
board/sifive/fu540/Kconfig| 2 +
board/sifive/fu540/fu540.c| 111 ++
4 files changed, 57 insertions(+), 72 deletions(-)
create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
new file mode 100644
index 00..db55773bd2
--- /dev/null
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2019 SiFive, Inc
+ */
+
+/ {
+ soc {
+ otp: otp@1007 {
+ compatible = "sifive,fu540-c000-otp";
+ reg = <0x0 0x1007 0x0 0x0FFF>;
+ fuse-count = <0x1000>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 2aebfab646..9af089ffe7 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2019 Jagan Teki
*/
+#include "fu540-c000-u-boot.dtsi"
+
/ {
aliases {
spi0 = &qspi0;
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 75661f35f8..4330ac4491 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -51,5 +51,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SIFIVE_GPIO
imply CMD_GPIO
imply SMP
+ imply MISC
+ imply SIFIVE_OTP
endif
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 47a2090251..540638c919 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -10,94 +10,61 @@
#include
#include
#include
+#include
+
+/*
+ * This define is a value used for error/unknown serial.
+ * If we really care about distinguishing errors and 0 is
+ * valid, we'll need a different one.
+ */
+#define ERROR_READING_SERIAL_NUMBER 0
#ifdef CONFIG_MISC_INIT_R
-#define FU540_OTP_BASE_ADDR0x1007
-
-struct fu540_otp_regs {
- u32 pa; /* Address input */
- u32 paio; /* Program address input */
- u32 pas;/* Program redundancy cell selection input */
- u32 pce;/* OTP Macro enable input */
- u32 pclk; /* Clock input */
- u32 pdin; /* Write data input */
- u32 pdout; /* Read data output */
- u32 pdstb; /* Deep standby mode enable input (active low) */
- u32 pprog; /* Program mode enable input */
- u32 ptc;/* Test column enable input */
- u32 ptm;/* Test mode enable input */
- u32 ptm_rep;/* Repair function test mode enable input */
- u32 ptr;/* Test row enable input */
- u32 ptrim; /* Repair function enable input */
- u32 pwe;/* Write enable input (defines program cycle) */
-} __packed;
-
-#define BYTES_PER_FUSE 4
-#define NUM_FUSES 0x1000
-
-static int fu540_otp_read(int offset, void *buf, int size)
+#if CONFIG_IS_ENABLED(SIFIVE_OTP)
+static u32 otp_read_serialnum(struct udevice *dev)
{
- struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR;
- unsigned int i;
- int fuseidx = offset / BYTES_PER_FUSE;
- int fusecount = size / BYTES_PER_FUSE;
- u32 fusebuf[fusecount];
-
- /* check bounds */
- if (offset < 0 || size < 0)
- return -EINVAL;
- if (fuseidx >= NUM_FUSES)
- return -EINVAL;
- if ((fuseidx + fusecount) > NUM_FUSES)
- return -EINVAL;
+ int ret;
+ u32 serial[2] = {0};
- /* init OTP */
- writel(0x01, ®s->pdstb); /* wake up from stand-by */
- writel(0x01, ®s->ptrim); /* enable repair function */
- writel(0x01, ®s->pce); /* enable input */
-
- /* read all requested fuses */
- for (i = 0; i < fusecount; i++, fuseidx++) {
- writel(fuseidx, ®s->pa);
-
- /* cycle clock to read */
- writel(0x01, ®s->pclk);
- mdelay(1);
- writel(0x00, ®s->pclk);
- mdelay(1);
-
- /* read the value */
- fusebuf[i] = readl(®s->pdout);
- }
+ for (int i = 0xfe * 4; i > 0; i -= 8) {
+ ret = misc_read(dev, i, serial, sizeof(serial));
- /* shut down */
- writel(0, ®s->pce);
- writel(0, ®s->ptrim);
- writel(0, ®s->pdstb);
+ if (ret != sizeof(serial)) {
+ printf("%s: error reading serial from OTP\n", __func__);
+ break;
+ }
- /* copy out */
- memcpy(buf
[PATCH v10 03/18] riscv: Add _image_binary_end for SPL
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
Reviewed-by: Jagan Teki
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv/cpu/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 955dd3106d..d0495ce248 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -72,6 +72,7 @@ SECTIONS
. = ALIGN(4);
_end = .;
+ _image_binary_end = .;
.bss : {
__bss_start = .;
--
2.17.1
[PATCH v10 00/18] RISC-V SiFive FU540 support SPL
This series add support for SPL to FU540. U-Boot SPL can boot from L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. This series depends on: [1] https://patchwork.ozlabs.org/patch/1281853 [2] https://patchwork.ozlabs.org/patch/1281852 All these together is available for testing here [3] [3] https://github.com/pragnesh26992/u-boot/tree/spl How to test this patch: 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y 2) export OPENSBI= 3) Change to u-boot-dir 4) make sifive_fu540_defconfig 5) make all 6) Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch) # sudo sgdisk --clear \ > --set-alignment=2 \ > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \ > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \ > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \ > /dev/sda 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082 Changes in v10: - Update commit description for ethernet clock reset (https://patchwork.ozlabs.org/patch/1289003) - Update commit description for ddr clock initialization (https://patchwork.ozlabs.org/patch/1289000) Changes in v9: - Remove cache related patches from this series sifive: dts: fu540: Enable L2 Cache in U-Boot (https://patchwork.ozlabs.org/patch/1286705) riscv: sifive: fu540: enable all cache ways from U-Boot proper (https://patchwork.ozlabs.org/patch/1286706) - Rename SiFive DDR driver from sdram_fu540.c to fu540_ddr.c and also do some typo correction in driver - Remove CONFIG_SPL_BUILD for __prci_ddr_release_reset() - Release ethernet clock reset instead of ethernet clock initialization (https://patchwork.ozlabs.org/patch/1286697) - Squash fu540 cpu patches (https://patchwork.ozlabs.org/patch/1286699) (https://patchwork.ozlabs.org/patch/1286700) - Use spl_boot_device() instead of board_boot_order() Changes in v8: - Remove SPL_CRC7_SUPPORT Kconfig option and compile crc7.o when CONFIG_MMC_SPI selected - Add "TODO" in drivers/ram/sifive/sdram_fu540.c - Remove unnecessary TODO from drivers/clk/sifive/fu540-prci.c - Make fu540-hifive-unleashed-a00-sdram-ddr4.dtsi file dual-licensed - Add 2 new patches sifive: fu540: Add sample SD gpt partition layout (https://patchwork.ozlabs.org/patch/1092) sifive: fu540: Add U-Boot proper sector start (https://patchwork.ozlabs.org/patch/1093) - Remove patch riscv: Enable cpu clock if it is present (https://patchwork.ozlabs.org/patch/1281573) - Update doc/board/sifive/fu540.rst for PLATFORM=generic Changes in v7: - Standardize SD gpt partition layout - Add delay for SiFive OTP driver - Use DM way for corepll and ddrpll - Add new cpu fu540 (arch/riscv/cpu/fu540) - Update document for FU540 (doc/board/sifive/fu540.rst) Changes in v6: - Typo Correction - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi Dual Licensed - Sync Hifive unleashed dts from Linux - Add arch/riscv/fu540 for FU540 specific code Changes in v5: - Return read/write bytes for sifive_otp_read and sifive_otp_write - Correct Palmer's email address Changes in v4: - Split misc DM driver patch into multiple patches - Added new SPL_CRC7_SUPPORT Kconfig option - Added DM driver for DDR - Added clk_enable and clk_disable ops in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added SPL config options in sifive_fu540_defconfig instead of creatiing a new config file for SPL - Update fu540.rst on how to build and flash U-boot SPL Changes in v3: - Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/ - Split SPL patches into DDR and SPL and spl defconfig - Update fu540/MAINTAINERS file - Update fu540.rst on how to build and flash U-boot SPL Changes in v2: - Add DM driver Sifive OTP - Split SPL patches into multiple patches - Add a seprate patch for _image_binary_end and crc7.c - Add a seprate patch to add board -u-boot.dtsi files - Update FU540 RISC-V documentation Jagan Teki (2): sifive: fu540: Add sample SD gpt partition layout sifive: fu540: Add U-Boot proper sector start Pragnesh Patel (16): misc: add driver for the SiFive otp controller riscv: sifive: fu540: Use OTP DM driver for serial environment variable riscv: Add _image_binary_end for SPL lib: Makefile: build crc7.c when CONFIG_MMC_SPI riscv: sifive: dts: fu540: Add board -u-boot.dtsi files sifive: fu540: add ddr driver sifive: dts: fu540: Add DDR controller and phy register settings riscv: sifive: dts: fu540: add U-Boot dmc node clk: sifive: fu540-prci: Add clock enable and disable ops clk: sifive: fu540-prci: Add ddr clock initialization clk: sifive: fu540-prci: Release ethernet clock reset riscv: dts: sifive: Sync hifive-un
[PATCH v10 05/18] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Jagan Teki
Tested-by: Bin Meng
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 61 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 15 +
2 files changed, 76 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index db55773bd2..fbfe296a03 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -4,11 +4,72 @@
*/
/ {
+ cpus {
+ assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+ assigned-clock-rates = <10>;
+ u-boot,dm-spl;
+ cpu0: cpu@0 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu2: cpu@2 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+u-boot,dm-spl;
+ };
+ };
+ cpu3: cpu@3 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu4: cpu@4 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
soc {
+ u-boot,dm-spl;
otp: otp@1007 {
compatible = "sifive,fu540-c000-otp";
reg = <0x0 0x1007 0x0 0x0FFF>;
fuse-count = <0x1000>;
};
+ clint@200 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
+ reg = <0x0 0x200 0x0 0xc>;
+ u-boot,dm-spl;
+ };
};
};
+
+&prci {
+ u-boot,dm-spl;
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&qspi2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 9af089ffe7..9787332bf1 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -10,4 +10,19 @@
spi0 = &qspi0;
spi2 = &qspi2;
};
+
+ hfclk {
+ u-boot,dm-spl;
+ };
+
+ rtcclk {
+ u-boot,dm-spl;
+ };
+
+};
+
+&qspi2 {
+ mmc@0 {
+ u-boot,dm-spl;
+ };
};
--
2.17.1
[PATCH v10 04/18] lib: Makefile: build crc7.c when CONFIG_MMC_SPI
When build U-Boot SPL, meet an issue of undefined reference to 'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when CONFIG_MMC_SPI selected. Signed-off-by: Pragnesh Patel Reviewed-by: Heinrich Schuchardt --- lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Makefile b/lib/Makefile index c6f862b0c2..a6812ea4a3 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -30,7 +30,6 @@ obj-y += charset.o endif endif obj-$(CONFIG_USB_TTY) += circbuf.o -obj-y += crc7.o obj-y += crc8.o obj-y += crc16.o obj-$(CONFIG_ERRNO_STR) += errno_str.o @@ -90,6 +89,7 @@ obj-y += errno.o obj-y += display_options.o CFLAGS_display_options.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"') obj-$(CONFIG_BCH) += bch.o +obj-$(CONFIG_MMC_SPI) += crc7.o obj-y += crc32.o obj-$(CONFIG_CRC32C) += crc32c.o obj-y += ctype.o -- 2.17.1
[PATCH v10 07/18] sifive: dts: fu540: Add DDR controller and phy register settings
Add DDR controller and phy register settings, taken from fsbl
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
.../dts/fu540-hifive-unleashed-a00-ddr.dtsi | 1489 +
1 file changed, 1489 insertions(+)
create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi
diff --git a/arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi
b/arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi
new file mode 100644
index 00..6ed5ccdbcb
--- /dev/null
+++ b/arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020 SiFive, Inc
+ */
+
+&dmc {
+ sifive,ddr-params = <
+ 0x0a00 /* DENALI_CTL_00_DATA */
+ 0x /* DENALI_CTL_01_DATA */
+ 0x /* DENALI_CTL_02_DATA */
+ 0x /* DENALI_CTL_03_DATA */
+ 0x /* DENALI_CTL_04_DATA */
+ 0x /* DENALI_CTL_05_DATA */
+ 0x000a /* DENALI_CTL_06_DATA */
+ 0x0002d362 /* DENALI_CTL_07_DATA */
+ 0x00071073 /* DENALI_CTL_08_DATA */
+ 0x0a1c0255 /* DENALI_CTL_09_DATA */
+ 0x1c1c0400 /* DENALI_CTL_10_DATA */
+ 0x0404990b /* DENALI_CTL_11_DATA */
+ 0x2b050405 /* DENALI_CTL_12_DATA */
+ 0x0e0c081e /* DENALI_CTL_13_DATA */
+ 0x08090914 /* DENALI_CTL_14_DATA */
+ 0x00fde718 /* DENALI_CTL_15_DATA */
+ 0x00180a05 /* DENALI_CTL_16_DATA */
+ 0x008b130e /* DENALI_CTL_17_DATA */
+ 0x01000118 /* DENALI_CTL_18_DATA */
+ 0x0e032101 /* DENALI_CTL_19_DATA */
+ 0x /* DENALI_CTL_20_DATA */
+ 0x0101 /* DENALI_CTL_21_DATA */
+ 0x /* DENALI_CTL_22_DATA */
+ 0x0a00 /* DENALI_CTL_23_DATA */
+ 0x /* DENALI_CTL_24_DATA */
+ 0x01450100 /* DENALI_CTL_25_DATA */
+ 0x1c36 /* DENALI_CTL_26_DATA */
+ 0x0005 /* DENALI_CTL_27_DATA */
+ 0x00170006 /* DENALI_CTL_28_DATA */
+ 0x014e0300 /* DENALI_CTL_29_DATA */
+ 0x0301 /* DENALI_CTL_30_DATA */
+ 0x000a0e00 /* DENALI_CTL_31_DATA */
+ 0x04030200 /* DENALI_CTL_32_DATA */
+ 0x031f /* DENALI_CTL_33_DATA */
+ 0x00070004 /* DENALI_CTL_34_DATA */
+ 0x /* DENALI_CTL_35_DATA */
+ 0x /* DENALI_CTL_36_DATA */
+ 0x /* DENALI_CTL_37_DATA */
+ 0x /* DENALI_CTL_38_DATA */
+ 0x /* DENALI_CTL_39_DATA */
+ 0x /* DENALI_CTL_40_DATA */
+ 0x /* DENALI_CTL_41_DATA */
+ 0x /* DENALI_CTL_42_DATA */
+ 0x /* DENALI_CTL_43_DATA */
+ 0x /* DENALI_CTL_44_DATA */
+ 0x /* DENALI_CTL_45_DATA */
+ 0x /* DENALI_CTL_46_DATA */
+ 0x /* DENALI_CTL_47_DATA */
+ 0x /* DENALI_CTL_48_DATA */
+ 0x /* DENALI_CTL_49_DATA */
+ 0x /* DENALI_CTL_50_DATA */
+ 0x /* DENALI_CTL_51_DATA */
+ 0x /* DENALI_CTL_52_DATA */
+ 0x /* DENALI_CTL_53_DATA */
+ 0x /* DENALI_CTL_54_DATA */
+ 0x /* DENALI_CTL_55_DATA */
+ 0x /* DENALI_CTL_56_DATA */
+ 0x /* DENALI_CTL_57_DATA */
+ 0x /* DENALI_CTL_58_DATA */
+ 0x /* DENALI_CTL_59_DATA */
+ 0x0424 /* DENALI_CTL_60_DATA */
+ 0x0201 /* DENALI_CTL_61_DATA */
+ 0x1008 /* DENALI_CTL_62_DATA */
+ 0x /* DENALI_CTL_63_DATA */
+ 0x0200 /* DENALI_CTL_64_DATA */
+ 0x /* DENALI_CTL_65_DATA */
+ 0x0481 /* DENALI_CTL_66_DATA */
+ 0x0400 /* DENALI_CTL_67_DATA */
+ 0x0424 /* DENALI_CTL_68_DATA */
+ 0x0201 /* DENALI_CTL_69_DATA */
+ 0x1008 /* DENALI_CTL_70_DATA */
+ 0x /* DENALI_CTL_71_DATA */
+ 0x0200 /* DENALI_CTL_72_DATA */
+ 0x /* DENALI_CTL_73_DATA */
+ 0x0481 /* DENALI_CTL_74_DATA
[PATCH v10 06/18] sifive: fu540: add ddr driver
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
board/sifive/fu540/Kconfig | 2 +
drivers/ram/Kconfig| 1 +
drivers/ram/Makefile | 2 +
drivers/ram/sifive/Kconfig | 13 +
drivers/ram/sifive/Makefile| 6 +
drivers/ram/sifive/fu540_ddr.c | 417 +
6 files changed, 441 insertions(+)
create mode 100644 drivers/ram/sifive/Kconfig
create mode 100644 drivers/ram/sifive/Makefile
create mode 100644 drivers/ram/sifive/fu540_ddr.c
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 4330ac4491..d41c305227 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -19,6 +19,8 @@ config SYS_TEXT_BASE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+ select RAM
+ select SPL_RAM if SPL
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 56fea7c94c..66074d1feb 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -75,3 +75,4 @@ config IMXRT_SDRAM
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
+source "drivers/ram/sifive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 5c897410c6..769c9d6218 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
+
+obj-$(CONFIG_RAM_SIFIVE) += sifive/
diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
new file mode 100644
index 00..6aca22ab2a
--- /dev/null
+++ b/drivers/ram/sifive/Kconfig
@@ -0,0 +1,13 @@
+config RAM_SIFIVE
+ bool "Ram drivers support for SiFive SoCs"
+ depends on RAM && RISCV
+ default y
+ help
+ This enables support for ram drivers of SiFive SoCs.
+
+config SIFIVE_FU540_DDR
+ bool "SiFive FU540 DDR driver"
+ depends on RAM_SIFIVE
+ default y if TARGET_SIFIVE_FU540
+ help
+ This enables DDR support for the platforms based on SiFive FU540 SoC.
diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
new file mode 100644
index 00..d66efec264
--- /dev/null
+++ b/drivers/ram/sifive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020 SiFive, Inc
+#
+
+obj-$(CONFIG_SIFIVE_FU540_DDR) += fu540_ddr.o
diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c
new file mode 100644
index 00..7ace6447eb
--- /dev/null
+++ b/drivers/ram/sifive/fu540_ddr.c
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DENALI_CTL_0 0
+#define DENALI_CTL_21 21
+#define DENALI_CTL_120 120
+#define DENALI_CTL_132 132
+#define DENALI_CTL_136 136
+#define DENALI_CTL_170 170
+#define DENALI_CTL_181 181
+#define DENALI_CTL_182 182
+#define DENALI_CTL_184 184
+#define DENALI_CTL_208 208
+#define DENALI_CTL_209 209
+#define DENALI_CTL_210 210
+#define DENALI_CTL_212 212
+#define DENALI_CTL_214 214
+#define DENALI_CTL_216 216
+#define DENALI_CTL_224 224
+#define DENALI_CTL_225 225
+#define DENALI_CTL_260 260
+
+#define DENALI_PHY_11521152
+#define DENALI_PHY_12141214
+
+#define PAYLOAD_DEST 0x8000
+#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL)
+
+#define DRAM_CLASS_OFFSET 8
+#define DRAM_CLASS_DDR40xA
+#define OPTIMAL_RMODW_EN_OFFSET0
+#define DISABLE_RD_INTERLEAVE_OFFSET 16
+#define OUT_OF_RANGE_OFFSET1
+#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
+#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
+#define MC_INIT_COMPLETE_OFFSET8
+#define LEVELING_OPERATION_COMPLETED_OFFSET22
+#define DFI_PHY_WRLELV_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
+#define VREF_EN_OFFSET 24
+#define PORT_ADDR_PROTECTION_EN_OFFSET 0
+#define AXI0_ADDRESS_RANGE_ENABLE 8
+#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
+#define RDLVL_EN_OFFSET16
+#define RDLVL_GATE_EN_OFFSET 24
+#define WRLVL_EN_OFFSET0
+
+#define PHY_RX_CAL_DQ0_0_OFFSET0
+#define PHY_RX_CAL_DQ1_0_OFFSET16
+
+struct fu540_ddrctl {
+ volatile u32 denali_ctl[265];
+};
+
+struct fu540_ddrphy {
+ volatile u32 denali_phy[1215];
+};
+
+/**
+ * struct fu540_ddr_i
[PATCH v10 08/18] riscv: sifive: dts: fu540: add U-Boot dmc node
Add dmc node to enable ddr driver. dmc is used to
initialize the memory controller.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index fbfe296a03..fc91a7c987 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -59,6 +59,15 @@
reg = <0x0 0x200 0x0 0xc>;
u-boot,dm-spl;
};
+ dmc: dmc@100b {
+ compatible = "sifive,fu540-c000-ddr";
+ reg = <0x0 0x100b 0x0 0x0800
+ 0x0 0x100b2000 0x0 0x2000
+ 0x0 0x100b8000 0x0 0x0fff>;
+ clocks = <&prci PRCI_CLK_DDRPLL>;
+ clock-frequency = <93324>;
+ u-boot,dm-spl;
+ };
};
};
--
2.17.1
[PATCH v10 11/18] clk: sifive: fu540-prci: Release ethernet clock reset
Release ethernet clock reset once clock is initialized.
This is necessary to do as U-Boot proper needs ethernet
clock.
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index f26a370a64..45491a77d5 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -559,6 +559,25 @@ static void __prci_ddr_release_reset(struct __prci_data
*pd)
asm volatile ("nop");
}
+/**
+ * __prci_ethernet_release_reset() - Release ethernet reset
+ * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
+ *
+ */
+static void __prci_ethernet_release_reset(struct __prci_data *pd)
+{
+ u32 v;
+
+ /* Release GEMGXL reset */
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* Procmon => core clock */
+ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
+ pd);
+}
+
/*
* PRCI integration data for each WRPLL instance
*/
@@ -579,6 +598,7 @@ static struct __prci_wrpll_data __prci_ddrpll_data = {
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
+ .release_reset = __prci_ethernet_release_reset,
};
/*
--
2.17.1
[PATCH v10 09/18] clk: sifive: fu540-prci: Add clock enable and disable ops
Added clock enable and disable functions in prci ops
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/clk/sifive/fu540-prci.c | 108
1 file changed, 96 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 8847178001..bf06c3a3bb 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -68,6 +68,11 @@
#define PRCI_COREPLLCFG0_LOCK_SHIFT31
#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
+/* COREPLLCFG1 */
+#define PRCI_COREPLLCFG1_OFFSET0x8
+#define PRCI_COREPLLCFG1_CKE_SHIFT 31
+#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
+
/* DDRPLLCFG0 */
#define PRCI_DDRPLLCFG0_OFFSET 0xc
#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
@@ -87,7 +92,7 @@
/* DDRPLLCFG1 */
#define PRCI_DDRPLLCFG1_OFFSET 0x10
-#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
+#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* GEMGXLPLLCFG0 */
@@ -114,7 +119,7 @@
/* GEMGXLPLLCFG1 */
#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
#define PRCI_GEMGXLPLLCFG1_CKE_MASK(0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
/* CORECLKSEL */
@@ -142,7 +147,7 @@
(0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
/* CLKMUXSTATUSREG */
-#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
+#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
@@ -170,6 +175,7 @@ struct __prci_data {
* @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else
NULL)
* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
+ * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
*
* @enable_bypass and @disable_bypass are used for WRPLL instances
* that contain a separate external glitchless clock mux downstream
@@ -180,6 +186,7 @@ struct __prci_wrpll_data {
void (*enable_bypass)(struct __prci_data *pd);
void (*disable_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
+ u8 cfg1_offs;
};
struct __prci_clock;
@@ -194,6 +201,7 @@ struct __prci_clock_ops {
unsigned long *parent_rate);
unsigned long (*recalc_rate)(struct __prci_clock *pc,
unsigned long parent_rate);
+ int (*enable_clk)(struct __prci_clock *pc, bool enable);
};
/**
@@ -316,7 +324,7 @@ static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
}
/**
- * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
+ * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
* @pd: PRCI context
* @pwd: PRCI WRPLL metadata
*
@@ -327,14 +335,14 @@ static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
* Context: Any context. Caller must prevent the records pointed to by
* @pd and @pwd from changing during execution.
*/
-static void __prci_wrpll_read_cfg(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd)
+static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd)
{
__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
}
/**
- * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
+ * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
* @pd: PRCI context
* @pwd: PRCI WRPLL metadata
* @c: WRPLL configuration record to write
@@ -347,15 +355,29 @@ static void __prci_wrpll_read_cfg(struct __prci_data *pd,
* Context: Any context. Caller must prevent the records pointed to by
* @pd and @pwd from changing during execution.
*/
-static void __prci_wrpll_write_cfg(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd,
- struct wrpll_cfg *c)
+static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ struct wrpll_cfg *c)
{
__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
memcpy(&pwd->c, c, sizeof(*c));
}
+/**
+ * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
+ * into the PRCI
+ * @pd: PRCI context
+ * @pwd: PRCI WRPLL metadata
+ * @enable: Clock enable or disable value
+ */
+static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+
[PATCH v10 13/18] riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel
---
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/fu540/Kconfig | 15 ++
arch/riscv/cpu/fu540/Makefile| 7 +
arch/riscv/cpu/fu540/cpu.c | 22 ++
arch/riscv/cpu/fu540/dram.c | 38
arch/riscv/include/asm/arch-fu540/clk.h | 14 +
arch/riscv/include/asm/arch-fu540/gpio.h | 38
board/sifive/fu540/Kconfig | 2 +-
8 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/cpu/fu540/Kconfig
create mode 100644 arch/riscv/cpu/fu540/Makefile
create mode 100644 arch/riscv/cpu/fu540/cpu.c
create mode 100644 arch/riscv/cpu/fu540/dram.c
create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h
create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fb5fe5afff..3044609971 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -57,6 +57,7 @@ source "board/sifive/fu540/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
+source "arch/riscv/cpu/fu540/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
new file mode 100644
index 00..e9302e87c0
--- /dev/null
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng
+
+config SIFIVE_FU540
+ bool
+ select ARCH_EARLY_INIT_R
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply CMD_CPU
+ imply SPL_CPU_SUPPORT
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
new file mode 100644
index 00..44700d998c
--- /dev/null
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 SiFive, Inc
+# Pragnesh Patel
+
+obj-y += dram.o
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/fu540/cpu.c b/arch/riscv/cpu/fu540/cpu.c
new file mode 100644
index 00..13a69ef0cc
--- /dev/null
+++ b/arch/riscv/cpu/fu540/cpu.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ */
+
+#include
+#include
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
new file mode 100644
index 00..1dc77efeca
--- /dev/null
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+ /*
+* Ensure that we run from first 4GB so that all
+* addresses used by U-Boot are 32bit addresses.
+*
+* This in-turn ensures that 32bit DMA capable
+* devices work fine because DMA mapping APIs will
+* provide 32bit DMA addresses only.
+*/
+ if (gd->ram_top > SZ_4G)
+ return SZ_4G;
+#endif
+ return gd->ram_top;
+}
diff --git a/arch/riscv/include/asm/arch-fu540/clk.h
b/arch/riscv/include/asm/arch-fu540/clk.h
new file mode 100644
index 00..d71ed4357c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive Inc
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#ifndef __CLK_SIFIVE_H
+#define __CLK_SIFIVE_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/arch/riscv/include/asm/arch-fu540/gpio.h
b/arch/riscv/include/asm/arch-fu540/gpio.h
new file mode 100644
index 00..0d16c59ca6
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/gpio.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL 0x00
+#define GPIO_INPUT_EN 0x04
+#define GPIO_OUTPUT_EN 0x08
+#define GPIO_OUTPUT_VAL0x0C
+#define GPIO_RISE_IE 0x18
+#define GPIO_RISE_IP 0x1C
+#define GPIO_FALL_IE 0x20
+#define GPIO_FALL_IP 0x24
+#define GPIO_HIGH_IE 0x28
+#define GPIO_HIGH_IP 0x2C
+#define GPIO_LOW_IE0x30
+#define GPIO_LOW_IP0x34
+#define GPIO_OUTPUT_XOR0x40
+
+#define NR_GPIOS 16
+
+
[PATCH v10 12/18] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux
This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.
Sync dts from linux v5.7-rc2 commit:
"riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file"
(sha1: 0a91330b2af9f71cd483f92774182b58f6d9)
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/fu540-c000.dtsi | 37 -
arch/riscv/dts/hifive-unleashed-a00.dts | 9 ++
2 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi
index afa43c7ea3..7db8610534 100644
--- a/arch/riscv/dts/fu540-c000.dtsi
+++ b/arch/riscv/dts/fu540-c000.dtsi
@@ -54,6 +54,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -77,6 +78,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -100,6 +102,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -123,6 +126,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -162,6 +166,13 @@
clocks = <&prci PRCI_CLK_TLCLK>;
status = "disabled";
};
+ dma: dma@300 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x300 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <23 24 25 26 27 28 29 30>;
+ #dma-cells = <1>;
+ };
uart1: serial@10011000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
reg = <0x0 0x10011000 0x0 0x1000>;
@@ -246,6 +257,30 @@
#pwm-cells = <3>;
status = "disabled";
};
-
+ l2cache: cache-controller@201 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x201 0x0 0x1000>;
+ };
+ gpio: gpio@1006 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+<14>, <15>, <16>, <17>, <18>, <19>, <20>,
+<21>, <22>;
+ reg = <0x0 0x1006 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts
b/arch/riscv/dts/hifive-unleashed-a00.dts
index 88cfcb96bf..4a2729f5ca 100644
--- a/arch/riscv/dts/hifive-unleashed-a00.dts
+++ b/arch/riscv/dts/hifive-unleashed-a00.dts
@@ -2,6 +2,7 @@
/* Copyright (c) 2018-2019 SiFive, Inc */
#include "fu540-c000.dtsi"
+#include
/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
#define RTCCLK_FREQ100
@@ -41,6 +42,10 @@
clock-frequency = ;
clock-output-names = "rtcclk";
};
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ };
};
&uart0 {
@@ -94,3 +99,7 @@
&pwm1 {
status = "okay";
};
+
+&gpio {
+ status = "okay";
+};
--
2.17.1
[PATCH v10 10/18] clk: sifive: fu540-prci: Add ddr clock initialization
Release ddr clock reset once clock is initialized
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 51 +
1 file changed, 45 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index bf06c3a3bb..f26a370a64 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -152,6 +152,12 @@
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
+/* PROCMONCFG */
+#define PRCI_PROCMONCFG_OFFSET 0xF0
+#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
+#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
+ (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
+
/*
* Private structures
*/
@@ -176,6 +182,7 @@ struct __prci_data {
* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
* @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
+ * @release_reset: fn ptr to code to release clock reset
*
* @enable_bypass and @disable_bypass are used for WRPLL instances
* that contain a separate external glitchless clock mux downstream
@@ -187,6 +194,7 @@ struct __prci_wrpll_data {
void (*disable_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
u8 cfg1_offs;
+ void (*release_reset)(struct __prci_data *pd);
};
struct __prci_clock;
@@ -476,6 +484,9 @@ static int sifive_fu540_prci_clock_enable(struct
__prci_clock *pc, bool enable)
if (enable) {
__prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
+
+ if (pwd->release_reset)
+ pwd->release_reset(pd);
} else {
u32 r;
@@ -495,11 +506,6 @@ static const struct __prci_clock_ops
sifive_fu540_prci_wrpll_clk_ops = {
.enable_clk = sifive_fu540_prci_clock_enable,
};
-static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
- .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
- .enable_clk = sifive_fu540_prci_clock_enable,
-};
-
/* TLCLKSEL clock integration */
static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(
@@ -521,6 +527,38 @@ static const struct __prci_clock_ops
sifive_fu540_prci_tlclksel_clk_ops = {
.recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
};
+/**
+ * __prci_ddr_release_reset() - Release DDR reset
+ * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
+ *
+ */
+static void __prci_ddr_release_reset(struct __prci_data *pd)
+{
+ u32 v;
+
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* HACK to get the '1 full controller clock cycle'. */
+ asm volatile ("fence");
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK);
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* HACK to get the '1 full controller clock cycle'. */
+ asm volatile ("fence");
+
+ /*
+* These take like 16 cycles to actually propagate. We can't go sending
+* stuff before they come out of reset. So wait.
+*/
+ for (int i = 0; i < 256; i++)
+ asm volatile ("nop");
+}
+
/*
* PRCI integration data for each WRPLL instance
*/
@@ -535,6 +573,7 @@ static struct __prci_wrpll_data __prci_corepll_data = {
static struct __prci_wrpll_data __prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
+ .release_reset = __prci_ddr_release_reset,
};
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
@@ -556,7 +595,7 @@ static struct __prci_clock __prci_init_clocks[] = {
[PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
- .ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
+ .ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &__prci_ddrpll_data,
},
[PRCI_CLK_GEMGXLPLL] = {
--
2.17.1
[PATCH v10 15/18] sifive: fu540: Add sample SD gpt partition layout
From: Jagan Teki
This is a sample GPT partition layout for SD card,
right now three important partitions are added to
make the system bootable.
partition layout:
PartStart LBA End LBA Name
Attributes
Type GUID
Partition GUID
1 0x0022 0x0821 "loader1"
attrs: 0x
type: 5b193300-fc78-40cd-8002-e86c45580b47
guid: cbcbef44-e627-42bc-b134-93b6f3784b8c
2 0x0822 0x2821 "loader2"
attrs: 0x
type: 2e54b353-1271-4842-806f-e436d6af6985
guid: f54eba28-d8de-4852-978d-1a673777e2ae
3 0x2822 0x00020821 "rootfs"
attrs: 0x0004
type: 0fc63daf-8483-4772-8e79-3d69d8477de4
type: linux
guid: 9561df46-8d55-4799-a83b-cfee9ef6ff93
Note:
- loader1 would be fsbl or spl
- loader2 would be U-Boot or U-Boot proper
Signed-off-by: Jagan Teki
Reviewed-by: Bin Meng
Reviewed-by: Pragnesh Patel
---
board/sifive/fu540/Kconfig | 2 ++
include/configs/sifive-fu540.h | 13 +
2 files changed, 15 insertions(+)
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 4a77a2a37b..86193d7668 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -34,6 +34,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_EXT4
imply CMD_FAT
imply CMD_FS_GENERIC
+ imply CMD_GPT
+ imply PARTITION_TYPE_GUID
imply CMD_NET
imply CMD_PING
imply CMD_SF
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index ef3ae9b650..72c841eb9b 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -47,6 +47,15 @@
#include
+#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47"
+#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985"
+#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4"
+
+#define PARTS_DEFAULT \
+ "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
+ "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
+ "name=system,size=-,bootable,type=${type_guid_gpt_system};"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x\0" \
"initrd_high=0x\0" \
@@ -55,6 +64,10 @@
"scriptaddr=0x8810\0" \
"pxefile_addr_r=0x8820\0" \
"ramdisk_addr_r=0x8830\0" \
+ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
+ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
+ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
+ "partitions=" PARTS_DEFAULT "\0" \
BOOTENV
#define CONFIG_PREBOOT \
--
2.17.1
[PATCH v10 16/18] sifive: fu540: Add U-Boot proper sector start
From: Jagan Teki Add U-Boot proper sector start offset for SiFive FU540. This value is based on the partition layout supported by SiFive FU540. u-boot.itb need to write on this specific offset so-that the SPL will retrieve it from here and load. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Reviewed-by: Pragnesh Patel --- common/spl/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 6f37f75650..24c746b2df 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -308,7 +308,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR ARCH_MX6 || ARCH_MX7 || \ ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \ ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ -OMAP44XX || OMAP54XX || AM33XX || AM43XX +OMAP44XX || OMAP54XX || AM33XX || AM43XX || TARGET_SIFIVE_FU540 help Use sector number for specifying U-Boot location on MMC/SD in raw mode. @@ -325,6 +325,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \ OMAP54XX || AM33XX || AM43XX || ARCH_K3 default 0x4000 if ARCH_ROCKCHIP + default 0x822 if TARGET_SIFIVE_FU540 help Address on the MMC to load U-Boot from, when the MMC is being used in raw mode. Units: MMC sectors (1 sector = 512 bytes). -- 2.17.1
[PATCH v10 18/18] doc: sifive: fu540: Add description for OpenSBI generic platform
OpenSBI generic platform support provides platform specific
functionality based on the FDT passed by previous booting stage.
Depends on OpenSBI commit:
platform: Add generic FDT based platform support
(sha1: f1aa9e54e6ae70aeac638d5b75093520f65d)
Signed-off-by: Pragnesh Patel
---
doc/board/sifive/fu540.rst | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
index 89e8d66c56..a51d086a6d 100644
--- a/doc/board/sifive/fu540.rst
+++ b/doc/board/sifive/fu540.rst
@@ -20,17 +20,6 @@ The support for following drivers are already enabled:
4. SiFive SPI Driver.
5. MMC SPI Driver for MMC/SD support.
-TODO:
-
-1. U-Boot expects the serial console device entry to be present under /chosen
- DT node. Without a serial console U-Boot will panic. Example:
-
-.. code-block:: none
-
- chosen {
-stdout-path = "/soc/serial@1001:115200";
- };
-
Booting from MMC using FSBL
---
@@ -61,7 +50,7 @@ firmware. We need to compile OpenSBI with below command:
.. code-block:: none
-make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=
+ make PLATFORM=generic FW_PAYLOAD_PATH=
More detailed description of steps required to build FW_PAYLOAD firmware
is beyond the scope of this document. Please refer OpenSBI documenation.
--
2.17.1
[PATCH v10 14/18] riscv: sifive: fu540: add SPL configuration
Add a support for SPL which will boot from L2 LIM (0x0800_) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.
SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Jagan Teki
---
arch/riscv/cpu/fu540/Makefile | 4 ++
arch/riscv/cpu/fu540/spl.c| 23 ++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 5 ++
arch/riscv/include/asm/arch-fu540/spl.h | 14
board/sifive/fu540/Kconfig| 10 ++-
board/sifive/fu540/Makefile | 4 ++
board/sifive/fu540/fu540.c| 21 ++
board/sifive/fu540/spl.c | 72 +++
include/configs/sifive-fu540.h| 18 +
9 files changed, 170 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/cpu/fu540/spl.c
create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h
create mode 100644 board/sifive/fu540/spl.c
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 44700d998c..043fb961a5 100644
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -3,5 +3,9 @@
# Copyright (C) 2020 SiFive, Inc
# Pragnesh Patel
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
obj-y += dram.o
obj-y += cpu.o
+endif
diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c
new file mode 100644
index 00..2e05d8a6e2
--- /dev/null
+++ b/arch/riscv/cpu/fu540/spl.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ * Pragnesh Patel
+ */
+
+#include
+#include
+
+int soc_spl_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 9787332bf1..303806454b 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include "fu540-c000-u-boot.dtsi"
+#include "fu540-hifive-unleashed-a00-ddr.dtsi"
/ {
aliases {
@@ -26,3 +27,7 @@
u-boot,dm-spl;
};
};
+
+&gpio {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/include/asm/arch-fu540/spl.h
b/arch/riscv/include/asm/arch-fu540/spl.h
new file mode 100644
index 00..0c188be747
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/spl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#ifndef _SPL_SIFIVE_H
+#define _SPL_SIFIVE_H
+
+int soc_spl_init(void);
+
+#endif /* _SPL_SIFIVE_H */
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index eb5ba3123d..4a77a2a37b 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -13,12 +13,20 @@ config SYS_CONFIG_NAME
default "sifive-fu540"
config SYS_TEXT_BASE
+ default 0x8020 if SPL
default 0x8000 if !RISCV_SMODE
default 0x8020 if RISCV_SMODE
+config SPL_TEXT_BASE
+ default 0x0800
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x8000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select GENERIC_RISCV
+ select SIFIVE_FU540
+ select SUPPORT_SPL
select RAM
select SPL_RAM if SPL
imply CMD_DHCP
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
index 6e1862c475..b05e2f5807 100644
--- a/board/sifive/fu540/Makefile
+++ b/board/sifive/fu540/Makefile
@@ -3,3 +3,7 @@
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 540638c919..535ab60aed 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
/*
* This define is a value used for error/unknown serial.
@@ -114,3 +115,23 @@ int board_init(void)
return 0;
}
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_MMC1;
+#else
+ puts("Unknown boot device\n");
+ hang();
+#endif
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c
new file mode 100644
index 00..b3ff6850e3
--- /dev/null
+++ b/board/sifive/fu540/spl.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ *
+
[PATCH v10 17/18] configs: fu540: Add config options for U-Boot SPL
With sifive_fu540_defconfig: User can use FSBL or u-boot-spl.bin anyone at a time. For FSBL, fsbl->fw_payload.bin (opensbi + U-Boot) For u-boot-spl.bin, u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb) U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT image u-boot.itb from SD card into RAM. U-Boot SPL expects u-boot.itb FIT image at the starting of SD card sector number (0x822) of GUID type "2E54B353-1271-4842-806F-E436D6AF6985" Signed-off-by: Pragnesh Patel Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki --- configs/sifive_fu540_defconfig | 8 ++ doc/board/sifive/fu540.rst | 134 + 2 files changed, 142 insertions(+) diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index f805aacc7a..8d412f8d6a 100644 --- a/configs/sifive_fu540_defconfig +++ b/configs/sifive_fu540_defconfig @@ -1,6 +1,11 @@ CONFIG_RISCV=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_ENV_SIZE=0x2 +CONFIG_SPL_MMC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_TARGET_SIFIVE_FU540=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y @@ -9,7 +14,10 @@ CONFIG_FIT=y CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_CLK=y CONFIG_DM_MTD=y diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst index 610ba87074..89e8d66c56 100644 --- a/doc/board/sifive/fu540.rst +++ b/doc/board/sifive/fu540.rst @@ -31,6 +31,9 @@ TODO: stdout-path = "/soc/serial@1001:115200"; }; +Booting from MMC using FSBL +--- + Building @@ -421,3 +424,134 @@ as well. Please press Enter to activate this console. / # + +Booting from MMC using U-Boot SPL +- + +Building + + +Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be +cloned and built for FU540 as below: + +.. code-block:: console + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=generic FW_DYNAMIC=y + +Copy OpenSBI FW_DYNAMIC image +(build/platform/generic/firmware/fw_dynamic.bin) into U-Boot +root directory + +.. code-block:: console + + cp build/platform/generic/firmware/fw_dynamic.bin + +Now build the U-Boot SPL and U-Boot proper + +.. code-block:: console + + cd + make sifive_fu540_defconfig + make + +This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb) + + +Flashing + + +ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type +5B193300-FC78-40CD-8002-E86C45580B47 + +U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID +type 2E54B353-1271-4842-806F-E436D6AF6985 + +FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and +device tree blob (hifive-unleashed-a00.dtb) + +Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch) + +.. code-block:: none + + # sudo sgdisk --clear \ + > --set-alignment=2 \ + > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \ + > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \ + > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \ + > /dev/sda + +Program the SD card + +.. code-block:: none + + sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34 + sudo dd if=u-boot.itb of=/dev/sda seek=2082 + +Booting +--- +Once you plugin the sdcard and power up, you should see the U-Boot prompt. + +Sample boot log from HiFive Unleashed board +--- + +.. code-block:: none + + U-Boot SPL 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530) + Trying to boot from MMC1 + + + U-Boot 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530) + + CPU: rv64imafdc + Model: SiFive HiFive Unleashed A00 + DRAM: 8 GiB + MMC: spi@1005:mmc@0: 0 + In:serial@1001 + Out: serial@1001 + Err: serial@1001 + Board serial number should not be 0 !! + Net: + Warning: ethernet@1009 (eth0) using random MAC address - 96:06:92:18:eb:04 + eth0: ethernet@1009 + Hit any key to stop autoboot: 0 + => version + U-Boot 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530) + + riscv64-unknown-linux-gnu-gcc (crosstool-NG 1.24.0.37-3f461da) 9.2.0 + GNU ld (crosstool-NG 1.24.0.37-3f461da) 2.32 + => mmc info + Device: spi@1005:mmc@0 + Manufacturer ID: 3 + OEM: 5344 + Name: SC16
[PATCH 2/5] cmd: sf Drop reassignment of new into flash
The new pointer points to flash found and that would
assign it to global 'flash' pointer for further flash
operations and also keep track of old flash pointer.
This would happen if the probe is successful or even
failed, but current code assigning new into flash before
and after checking the new.
So, drop the assignment after new checks so flash always
latest new pointer even if probe failed or succeed.
Cc: Simon Glass
Cc: Vignesh R
Signed-off-by: Jagan Teki
---
cmd/sf.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/cmd/sf.c b/cmd/sf.c
index e993b3e5ad..302201c2b0 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -141,13 +141,10 @@ static int do_spi_flash_probe(int argc, char * const
argv[])
new = spi_flash_probe(bus, cs, speed, mode);
flash = new;
-
if (!new) {
printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
return 1;
}
-
- flash = new;
#endif
return 0;
--
2.20.1
[PATCH 1/5] mtd: spi: Call sst_write in _write ops
Currently spi-nor code is assigning _write ops for SST and other flashes separately. Just call the sst_write from generic write ops and return if SST flash found, this way it avoids the confusion of multiple write ops assignment during the scan and makes it more feasible for code readability. No functionality changes. Cc: Simon Glass Cc: Vignesh R Signed-off-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 3d4361493e..984cece0b0 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1233,6 +1233,12 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, size_t page_offset, page_remain, i; ssize_t ret; +#ifdef CONFIG_SPI_FLASH_SST + /* sst nor chips use AAI word program */ + if (nor->info->flags & SST_WRITE) + return sst_write(mtd, to, len, retlen, buf); +#endif + dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); if (!len) @@ -2528,6 +2534,7 @@ int spi_nor_scan(struct spi_nor *nor) mtd->size = params.size; mtd->_erase = spi_nor_erase; mtd->_read = spi_nor_read; + mtd->_write = spi_nor_write; #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) /* NOR protection support for STmicro/Micron chips and similar */ @@ -2551,13 +2558,7 @@ int spi_nor_scan(struct spi_nor *nor) nor->flash_unlock = sst26_unlock; nor->flash_is_locked = sst26_is_locked; } - - /* sst nor chips use AAI word program */ - if (info->flags & SST_WRITE) - mtd->_write = sst_write; - else #endif - mtd->_write = spi_nor_write; if (info->flags & USE_FSR) nor->flags |= SNOR_F_USE_FSR; -- 2.20.1
[PATCH 0/5] sf: Cleanup
Cleanup of SF, no precise functionality changes. Any inputs? Jagan. Jagan Teki (5): mtd: spi: Call sst_write in _write ops cmd: sf Drop reassignment of new into flash env: sf: Preserve and free the previous flash mtd: sf: Drop plat from sf_probe mtd: spi: Use IS_ENABLED to prevent ifdef cmd/sf.c | 3 --- drivers/mtd/spi/sf_internal.h | 10 ++ drivers/mtd/spi/sf_probe.c | 19 --- drivers/mtd/spi/spi-nor-core.c | 13 +++-- env/sf.c | 18 ++ 5 files changed, 35 insertions(+), 28 deletions(-) -- 2.20.1
[PATCH 3/5] env: sf: Preserve and free the previous flash
env_flash is a global flash pointer, and the probe would
happen only if env_flash is NULL, but there is no checking
and free the pointer if is not NULL.
So, this patch frees the env_flash if it's not NULL, and
get the probed flash in new flash pointer and finally
assign into env_flash.
Note: Similar approach has been followed and tested in
cmd/sf.c
Cc: Simon Glass
Cc: Vignesh R
Signed-off-by: Jagan Teki
---
env/sf.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/env/sf.c b/env/sf.c
index 64c57f2cdf..af59c8375c 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -50,15 +50,17 @@ static int setup_flash_device(void)
env_flash = dev_get_uclass_priv(new);
#else
+ struct spi_flash *new;
- if (!env_flash) {
- env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
- CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
- if (!env_flash) {
- env_set_default("spi_flash_probe() failed", 0);
- return -EIO;
- }
+ if (env_flash)
+ spi_flash_free(env_flash);
+
+ new = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ env_flash = new;
+ if (!new) {
+ env_set_default("spi_flash_probe() failed", 0);
+ return -EIO;
}
#endif
return 0;
--
2.20.1
[PATCH 4/5] mtd: sf: Drop plat from sf_probe
dm_spi_slave_platdata used in sf_probe for printing
plat->cs value and there is no relevant usage apart
from this.
We have enouch debug messages available in SPI and SF
areas so drop this plat get and associated bug statement.
Cc: Simon Glass
Cc: Vignesh R
Signed-off-by: Jagan Teki
---
drivers/mtd/spi/sf_probe.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 72b6ee702d..89e384901c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -140,13 +140,11 @@ static int spi_flash_std_get_sw_write_prot(struct udevice
*dev)
int spi_flash_std_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
- struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
struct spi_flash *flash;
flash = dev_get_uclass_priv(dev);
flash->dev = dev;
flash->spi = slave;
- debug("%s: slave=%p, cs=%d\n", __func__, slave, plat->cs);
return spi_flash_probe_slave(flash);
}
--
2.20.1
[PATCH 5/5] mtd: spi: Use IS_ENABLED to prevent ifdef
Use IS_ENABLED to prevent ifdef in sf_probe.c
Cc: Simon Glass
Cc: Vignesh R
Cc: Daniel Schwierzeck
Signed-off-by: Jagan Teki
---
drivers/mtd/spi/sf_internal.h | 10 ++
drivers/mtd/spi/sf_probe.c| 17 -
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 940b2e4c9e..544ed74a5f 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -81,5 +81,15 @@ int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
int spi_flash_mtd_register(struct spi_flash *flash);
void spi_flash_mtd_unregister(void);
+#else
+static inline int spi_flash_mtd_register(struct spi_flash *flash)
+{
+ return 0;
+}
+
+static inline void spi_flash_mtd_unregister(void)
+{
+}
#endif
+
#endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 89e384901c..1e8744896c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -44,9 +44,8 @@ static int spi_flash_probe_slave(struct spi_flash *flash)
if (ret)
goto err_read_id;
-#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
- ret = spi_flash_mtd_register(flash);
-#endif
+ if (IS_ENABLED(CONFIG_SPI_FLASH_MTD))
+ ret = spi_flash_mtd_register(flash);
err_read_id:
spi_release_bus(spi);
@@ -83,9 +82,9 @@ struct spi_flash *spi_flash_probe(unsigned int busnum,
unsigned int cs,
void spi_flash_free(struct spi_flash *flash)
{
-#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
- spi_flash_mtd_unregister();
-#endif
+ if (IS_ENABLED(CONFIG_SPI_FLASH_MTD))
+ spi_flash_mtd_unregister();
+
spi_free_slave(flash->spi);
free(flash);
}
@@ -150,9 +149,9 @@ int spi_flash_std_probe(struct udevice *dev)
static int spi_flash_std_remove(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
- spi_flash_mtd_unregister();
-#endif
+ if (IS_ENABLED(CONFIG_SPI_FLASH_MTD))
+ spi_flash_mtd_unregister();
+
return 0;
}
--
2.20.1
[PATCH 04/10] tegra: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/arm/mach-tegra/ivc.c to the other macros.
Cc: Tom Warren
Signed-off-by: Tom Rini
---
arch/arm/mach-tegra/ivc.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c
index a448f2df3028..325d61f6d3a7 100644
--- a/arch/arm/mach-tegra/ivc.c
+++ b/arch/arm/mach-tegra/ivc.c
@@ -123,11 +123,11 @@ static inline int tegra_ivc_channel_empty(struct
tegra_ivc *ivc,
{
/*
* This function performs multiple checks on the same values with
-* security implications, so create snapshots with ACCESS_ONCE() to
+* security implications, so create snapshots with READ_ONCE() to
* ensure that these checks use the same values.
*/
- uint32_t w_count = ACCESS_ONCE(ch->w_count);
- uint32_t r_count = ACCESS_ONCE(ch->r_count);
+ uint32_t w_count = READ_ONCE(ch->w_count);
+ uint32_t r_count = READ_ONCE(ch->r_count);
/*
* Perform an over-full check to prevent denial of service attacks where
@@ -152,14 +152,14 @@ static inline int tegra_ivc_channel_full(struct tegra_ivc
*ivc,
* Invalid cases where the counters indicate that the queue is over
* capacity also appear full.
*/
- return (ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count)) >=
+ return (READ_ONCE(ch->w_count) - READ_ONCE(ch->r_count)) >=
ivc->nframes;
}
static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc)
{
- ACCESS_ONCE(ivc->rx_channel->r_count) =
- ACCESS_ONCE(ivc->rx_channel->r_count) + 1;
+ WRITE_ONCE(ivc->rx_channel->r_count,
+ READ_ONCE(ivc->rx_channel->r_count) + 1);
if (ivc->r_pos == ivc->nframes - 1)
ivc->r_pos = 0;
@@ -169,8 +169,8 @@ static inline void tegra_ivc_advance_rx(struct tegra_ivc
*ivc)
static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc)
{
- ACCESS_ONCE(ivc->tx_channel->w_count) =
- ACCESS_ONCE(ivc->tx_channel->w_count) + 1;
+ WRITE_ONCE(ivc->tx_channel->w_count,
+ READ_ONCE(ivc->tx_channel->w_count) + 1);
if (ivc->w_pos == ivc->nframes - 1)
ivc->w_pos = 0;
@@ -231,7 +231,7 @@ static inline uint32_t tegra_ivc_channel_avail_count(struct
tegra_ivc *ivc,
* comment in tegra_ivc_channel_empty() for an explanation about
* special over-full considerations.
*/
- return ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count);
+ return READ_ONCE(ch->w_count) - READ_ONCE(ch->r_count);
}
int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame)
@@ -357,7 +357,7 @@ int tegra_ivc_channel_notified(struct tegra_ivc *ivc)
/* Copy the receiver's state out of shared memory. */
offset = offsetof(struct tegra_ivc_channel_header, w_count);
tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset);
- peer_state = ACCESS_ONCE(ivc->rx_channel->state);
+ peer_state = READ_ONCE(ivc->rx_channel->state);
if (peer_state == ivc_state_sync) {
/*
--
2.17.1
[PATCH 03/10] Don't start ad-hoc games with -Wno-maybe-initialized
Borrowing from Linux commit 78a5255ffb6a ("Stop the ad-hoc games with
-Wno-maybe-initialized")
move to have maybe-initialized warnings be handled with building with
W=2 instead of playing more guessing games with newer compilers.
Signed-off-by: Tom Rini
---
Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Makefile b/Makefile
index a9d58ca7a0dc..951ecbd41cef 100644
--- a/Makefile
+++ b/Makefile
@@ -683,6 +683,9 @@ KBUILD_CFLAGS += $(call
cc-option,-fno-delete-null-pointer-checks)
# disable stringop warnings in gcc 8+
KBUILD_CFLAGS += $(call cc-disable-warning, stringop-truncation)
+# Enabled with W=2, disabled by default as noisy
+KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized)
+
# change __FILE__ to the relative path from the srctree
KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
--
2.17.1
[PATCH 05/10] x86: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/x86/include/asm/atomic.h to the other macros.
Cc: Simon Glass
Cc: Bin Meng
Signed-off-by: Tom Rini
---
arch/x86/include/asm/atomic.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
index 806f7873819e..002e36ba53e6 100644
--- a/arch/x86/include/asm/atomic.h
+++ b/arch/x86/include/asm/atomic.h
@@ -22,7 +22,7 @@ typedef struct { volatile int counter; } atomic_t;
*/
static inline int atomic_read(const atomic_t *v)
{
- return ACCESS_ONCE((v)->counter);
+ return READ_ONCE((v)->counter);
}
/**
--
2.17.1
[PATCH 02/10] kconfig: Add scripts/Kconfig.include from v4.19
As part of re-syncing our Kconfig logic up to v4.19, we had missed
adding this new file that includes helper macros. To quote the upstream
commit e1cfdc0e72fc ("kconfig: add basic helper macros to
scripts/Kconfig.include"):
Kconfig got text processing tools like we see in Make. Add Kconfig
helper macros to scripts/Kconfig.include like we collect Makefile
macros in scripts/Kbuild.include.
Cc: Masahiro Yamada
Signed-off-by: Tom Rini
---
Kconfig | 2 ++
scripts/Kconfig.include | 30 ++
2 files changed, 32 insertions(+)
create mode 100644 scripts/Kconfig.include
diff --git a/Kconfig b/Kconfig
index 15f1a75c61ab..72b4439264a6 100644
--- a/Kconfig
+++ b/Kconfig
@@ -5,6 +5,8 @@
#
mainmenu "U-Boot $(UBOOTVERSION) Configuration"
+source "scripts/Kconfig.include"
+
# Allow defaults in arch-specific code to override any given here
source "arch/Kconfig"
diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include
new file mode 100644
index ..dad5583451af
--- /dev/null
+++ b/scripts/Kconfig.include
@@ -0,0 +1,30 @@
+# Kconfig helper macros
+
+# Convenient variables
+comma := ,
+quote := "
+squote := '
+empty :=
+space := $(empty) $(empty)
+dollar := $
+right_paren := )
+left_paren := (
+
+# $(if-success,,,)
+# Return if exits with 0, otherwise.
+if-success = $(shell,{ $(1); } >/dev/null 2>&1 && echo "$(2)" || echo "$(3)")
+
+# $(success,)
+# Return y if exits with 0, n otherwise
+success = $(if-success,$(1),y,n)
+
+# $(cc-option,)
+# Return y if the compiler supports , n otherwise
+cc-option = $(success,$(CC) -Werror $(1) -E -x c /dev/null -o /dev/null)
+
+# $(ld-option,)
+# Return y if the linker supports , n otherwise
+ld-option = $(success,$(LD) -v $(1))
+
+# gcc version including patch level
+gcc-version := $(shell,$(srctree)/scripts/gcc-version.sh -p $(CC) | sed
's/^0*//')
--
2.17.1
[PATCH 10/10] socfpga: Enable optimized inlining on stratix10
Enable the new CONFIG_OPTIMIZE_INLINING and CONFIG_SPL_OPTIMIZE_INLINING options for this platform. With gcc-9.2 from kernel.org this saves us 1784 bytes in U-Boot and 80 bytes in SPL. Cc: Marek Vasut Cc: Chin-Liang See Cc: Dinh Nguyen Signed-off-by: Tom Rini --- configs/socfpga_stratix10_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 21014f9f8cde..e4f91477181e 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -11,6 +11,8 @@ CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_OPTIMIZE_INLINING=y +CONFIG_SPL_OPTIMIZE_INLINING=y CONFIG_BOOTDELAY=5 CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y -- 2.17.1
[PATCH 08/10] compiler_types.h: Re-introduce CONFIG_OPTIMIZE_INLINING for U-Boot
In the Linux kernel, support for forcing inline functions to be made
inline, rather than allowing the compiler to make its own choice has
been removed. With respect to performance, modern GCC (and Clang) do a
good job at deciding when to, or not to, inline code and there are no
run-time requirements in Linux anymore.
There is one downside to this, which is final binary size. On average
in U-Boot removing this support grows SPL by almost 1 kilobyte. But
there are cases where it shrinks the binary by making better inline
choices than we had forced.
Start by re-introducing CONFIG_OPTIMIZE_INLINING as a global which
essentially reverts 889b3c1245de ("compiler: remove CONFIG_OPTIMIZE_INLINING
entirely")
from Linux.
Cc: Masahiro Yamada
Signed-off-by: Tom Rini
---
Kconfig| 9 +
include/linux/compiler_types.h | 11 ++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig
index 37cc9445180f..b582db24f5d0 100644
--- a/Kconfig
+++ b/Kconfig
@@ -64,6 +64,15 @@ config CC_OPTIMIZE_FOR_SIZE
This option is enabled by default for U-Boot.
+config OPTIMIZE_INLINING
+ bool "Allow compiler to uninline functions marked 'inline'"
+ default n
+ help
+ This option determines if U-Boot forces gcc to inline the functions
+ developers have marked 'inline'. Doing so takes away freedom from gcc
to
+ do what it thinks is best, which is desirable in some cases for size
+ reasons.
+
config CC_COVERAGE
bool "Enable code coverage analysis"
depends on SANDBOX
diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h
index e970f97a7fcb..72393a8c1a6c 100644
--- a/include/linux/compiler_types.h
+++ b/include/linux/compiler_types.h
@@ -129,13 +129,22 @@ struct ftrace_likely_data {
#define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
/*
+ * Force always-inline if the user requests it so via the .config.
* Prefer gnu_inline, so that extern inline functions do not emit an
* externally visible function. This makes extern inline behave as per gnu89
* semantics rather than c99. This prevents multiple symbol definition errors
* of extern inline functions at link time.
* A lot of inline functions can cause havoc with function tracing.
+ * Do not use __always_inline here, since currently it expands to inline again
+ * (which would break users of __always_inline).
*/
-#define inline inline __gnu_inline __inline_maybe_unused notrace
+#if !defined(CONFIG_OPTIMIZE_INLINING)
+#define inline inline __attribute__((__always_inline__)) __gnu_inline \
+ __inline_maybe_unused notrace
+#else
+#define inline inline__gnu_inline \
+ __inline_maybe_unused notrace
+#endif
/*
* gcc provides both __inline__ and __inline as alternate spellings of
--
2.17.1
[PATCH 06/10] socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA case
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.
Cc: Marek Vasut
Cc: Simon Goldschmidt
Cc: Ley Foon Tan
Signed-off-by: Tom Rini
---
arch/arm/mach-socfpga/include/mach/misc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index f6de1ccb4a01..a85c5aeef955 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -20,7 +20,7 @@ extern struct bsel bsel_str[];
#ifdef CONFIG_FPGA
void socfpga_fpga_add(void *fpga_desc);
#else
-inline void socfpga_fpga_add(void *fpga_desc) {}
+static inline void socfpga_fpga_add(void *fpga_desc) {}
#endif
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
--
2.17.1
[PATCH 09/10] compilers: Introduce options for forcing inlining on SPL/TPL
There are cases where when we allow the compiler to decide about making
inline decisions rather than forcing them it can save us space.
For now, we keep the default values for inlining that we have had
historically.
Cc: Masahiro Yamada
Signed-off-by: Tom Rini
---
Kconfig| 22 +-
include/linux/compiler_types.h | 2 +-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/Kconfig b/Kconfig
index b582db24f5d0..f23c07da6819 100644
--- a/Kconfig
+++ b/Kconfig
@@ -65,7 +65,27 @@ config CC_OPTIMIZE_FOR_SIZE
This option is enabled by default for U-Boot.
config OPTIMIZE_INLINING
- bool "Allow compiler to uninline functions marked 'inline'"
+ bool "Allow compiler to uninline functions marked 'inline' in full
U-Boot"
+ default n
+ help
+ This option determines if U-Boot forces gcc to inline the functions
+ developers have marked 'inline'. Doing so takes away freedom from gcc
to
+ do what it thinks is best, which is desirable in some cases for size
+ reasons.
+
+config SPL_OPTIMIZE_INLINING
+ bool "Allow compiler to uninline functions marked 'inline' in SPL"
+ depends on SPL
+ default n
+ help
+ This option determines if U-Boot forces gcc to inline the functions
+ developers have marked 'inline'. Doing so takes away freedom from gcc
to
+ do what it thinks is best, which is desirable in some cases for size
+ reasons.
+
+config TPL_OPTIMIZE_INLINING
+ bool "Allow compiler to uninline functions marked 'inline' in TPL"
+ depends on TPL
default n
help
This option determines if U-Boot forces gcc to inline the functions
diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h
index 72393a8c1a6c..1a3060117f14 100644
--- a/include/linux/compiler_types.h
+++ b/include/linux/compiler_types.h
@@ -138,7 +138,7 @@ struct ftrace_likely_data {
* Do not use __always_inline here, since currently it expands to inline again
* (which would break users of __always_inline).
*/
-#if !defined(CONFIG_OPTIMIZE_INLINING)
+#if !CONFIG_IS_ENABLED(OPTIMIZE_INLINING)
#define inline inline __attribute__((__always_inline__)) __gnu_inline \
__inline_maybe_unused notrace
#else
--
2.17.1
[PATCH 07/10] compiler*.h: sync include/linux/compiler*.h with Linux 5.7-rc5
Copy these from Linux v5.7-rc5 tag.
This brings in some handy new attributes and is otherwise important to
keep in sync.
We drop the reference to smp_read_barrier_depends() as it is not
relevant on the architectures we support at this time, based on where
it's implemented in Linux today. We drop the call to kasan_check_read()
as that is not relevant to U-Boot as well.
Cc: Masahiro Yamada
Signed-off-by: Tom Rini
---
Kconfig | 3 +
include/linux/compiler-clang.h | 44 ++-
include/linux/compiler-gcc.h| 259 --
include/linux/compiler-intel.h | 17 +-
include/linux/compiler.h| 502 +---
include/linux/compiler_attributes.h | 273 +++
include/linux/compiler_types.h | 237 +
lib/vsprintf.c | 2 -
8 files changed, 777 insertions(+), 560 deletions(-)
create mode 100644 include/linux/compiler_attributes.h
create mode 100644 include/linux/compiler_types.h
diff --git a/Kconfig b/Kconfig
index 72b4439264a6..37cc9445180f 100644
--- a/Kconfig
+++ b/Kconfig
@@ -71,6 +71,9 @@ config CC_COVERAGE
Enabling this option will pass "--coverage" to gcc to compile
and link code instrumented for coverage analysis.
+config CC_HAS_ASM_INLINE
+ def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC)
-x c - -c -o /dev/null)
+
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux
distributions"
select AUTO_COMPLETE
diff --git a/include/linux/compiler-clang.h b/include/linux/compiler-clang.h
index d1e49d52b640..333a6695a918 100644
--- a/include/linux/compiler-clang.h
+++ b/include/linux/compiler-clang.h
@@ -1,12 +1,44 @@
-#ifndef __LINUX_COMPILER_H
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_COMPILER_TYPES_H
#error "Please don't include directly, include
instead."
#endif
-/* Some compiler specific definitions are overwritten here
- * for Clang compiler
- */
+/* Compiler specific definitions for Clang compiler */
-#ifdef uninitialized_var
-#undef uninitialized_var
#define uninitialized_var(x) x = *(&(x))
+
+/* same as gcc, this was present in clang-2.6 so we can assume it works
+ * with any version that can compile the kernel
+ */
+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+
+/* all clang versions usable with the kernel support KASAN ABI version 5 */
+#define KASAN_ABI_VERSION 5
+
+#if __has_feature(address_sanitizer) || __has_feature(hwaddress_sanitizer)
+/* emulate gcc's __SANITIZE_ADDRESS__ flag */
+#define __SANITIZE_ADDRESS__
+#define __no_sanitize_address \
+ __attribute__((no_sanitize("address", "hwaddress")))
+#else
+#define __no_sanitize_address
#endif
+
+/*
+ * Not all versions of clang implement the the type-generic versions
+ * of the builtin overflow checkers. Fortunately, clang implements
+ * __has_builtin allowing us to avoid awkward version
+ * checks. Unfortunately, we don't know which version of gcc clang
+ * pretends to be, so the macro may or may not be defined.
+ */
+#if __has_builtin(__builtin_mul_overflow) && \
+__has_builtin(__builtin_add_overflow) && \
+__has_builtin(__builtin_sub_overflow)
+#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
+#endif
+
+/* The following are for compatibility with GCC, from compiler-gcc.h,
+ * and may be redefined here because they should not be shared with other
+ * compilers, like ICC.
+ */
+#define barrier() __asm__ __volatile__("" : : : "memory")
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 8d9e0794351c..d7ee4c6bad48 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -1,4 +1,5 @@
-#ifndef __LINUX_COMPILER_H
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_COMPILER_TYPES_H
#error "Please don't include directly, include
instead."
#endif
@@ -9,11 +10,14 @@
+ __GNUC_MINOR__ * 100 \
+ __GNUC_PATCHLEVEL__)
+#if GCC_VERSION < 40600
+# error Sorry, your compiler is too old - please upgrade it.
+#endif
+
/* Optimization barrier */
/* The "volatile" is due to gcc bugs */
-#define barrier() \
- __asm__ __volatile__("": : :"memory")
+#define barrier() __asm__ __volatile__("": : :"memory")
/*
* This version is i.e. to prevent dead stores elimination on @ptr
* where gcc and llvm may behave differently when otherwise using
@@ -22,13 +26,12 @@
* clobbered. The issue is as follows: while the inline asm might
* access any memory it wants, the compiler could have fit all of
* @ptr into memory registers instead, and since @ptr never escaped
- * from that, it proofed that the inline asm wasn't touching any of
+ * from that, it proved that the inline asm wasn't touching any of
* it. This version works well with both compilers, i.e. we're telling
* the compiler that the inline asm absolutely may see the contents
* of @ptr.
[PATCH 01/10] kconfiglib: Update to the 14.1.0 release
A large number of changes have happened upstream since our last sync
in commit 65e05ddc1ae2 ("kconfiglib: Update to the 12.14.0 release").
The big motivation for this sync is support for user defined macros
within Kconfig.
Cc: Masahiro Yamada
Signed-off-by: Tom Rini
---
tools/buildman/kconfiglib.py | 614 +--
1 file changed, 372 insertions(+), 242 deletions(-)
diff --git a/tools/buildman/kconfiglib.py b/tools/buildman/kconfiglib.py
index 3908985c7b29..c67895ced6b3 100644
--- a/tools/buildman/kconfiglib.py
+++ b/tools/buildman/kconfiglib.py
@@ -554,7 +554,7 @@ from glob import iglob
from os.path import dirname, exists, expandvars, islink, join, realpath
-VERSION = (12, 14, 0)
+VERSION = (14, 1, 0)
# File layout:
@@ -773,8 +773,8 @@ class Kconfig(object):
See Kconfig.load_config() as well.
srctree:
- The value of the $srctree environment variable when the configuration was
- loaded, or the empty string if $srctree wasn't set. This gives nice
+ The value the $srctree environment variable had when the Kconfig instance
+ was created, or the empty string if $srctree wasn't set. This gives nice
behavior with os.path.join(), which treats "" as the current directory,
without adding "./".
@@ -789,13 +789,22 @@ class Kconfig(object):
if multiple configurations are loaded with different values for $srctree.
config_prefix:
- The value of the $CONFIG_ environment variable when the configuration was
- loaded. This is the prefix used (and expected) on symbol names in .config
- files and C headers. Defaults to "CONFIG_". Used in the same way in the C
- tools.
-
- Like for srctree, only the value of $CONFIG_ when the configuration is
- loaded matters.
+ The value the CONFIG_ environment variable had when the Kconfig instance
+ was created, or "CONFIG_" if CONFIG_ wasn't set. This is the prefix used
+ (and expected) on symbol names in .config files and C headers. Used in
+ the same way in the C tools.
+
+config_header:
+ The value the KCONFIG_CONFIG_HEADER environment variable had when the
+ Kconfig instance was created, or the empty string if
+ KCONFIG_CONFIG_HEADER wasn't set. This string is inserted verbatim at the
+ beginning of configuration files. See write_config().
+
+header_header:
+ The value the KCONFIG_AUTOHEADER_HEADER environment variable had when the
+ Kconfig instance was created, or the empty string if
+ KCONFIG_AUTOHEADER_HEADER wasn't set. This string is inserted verbatim at
+ the beginning of header files. See write_autoconf().
filename/linenr:
The current parsing location, for use in Python preprocessor functions.
@@ -810,11 +819,13 @@ class Kconfig(object):
"_warn_assign_no_prompt",
"choices",
"comments",
+"config_header",
"config_prefix",
"const_syms",
"defconfig_list",
"defined_syms",
"env_vars",
+"header_header",
"kconfig_filenames",
"m",
"menus",
@@ -854,7 +865,7 @@ class Kconfig(object):
#
def __init__(self, filename="Kconfig", warn=True, warn_to_stderr=True,
- encoding="utf-8"):
+ encoding="utf-8", suppress_traceback=False):
"""
Creates a new Kconfig object by parsing Kconfig files.
Note that Kconfig files are not the same as .config files (which store
@@ -919,7 +930,35 @@ class Kconfig(object):
anyway.
Related PEP: https://www.python.org/dev/peps/pep-0538/
+
+suppress_traceback (default: False):
+ Helper for tools. When True, any EnvironmentError or KconfigError
+ generated during parsing is caught, the exception message is printed
+ to stderr together with the command name, and sys.exit(1) is called
+ (which generates SystemExit).
+
+ This hides the Python traceback for "expected" errors like syntax
+ errors in Kconfig files.
+
+ Other exceptions besides EnvironmentError and KconfigError are still
+ propagated when suppress_traceback is True.
"""
+try:
+self._init(filename, warn, warn_to_stderr, encoding)
+except (EnvironmentError, KconfigError) as e:
+if suppress_traceback:
+cmd = sys.argv[0] # Empty string if missing
+if cmd:
+cmd += ": "
+# Some long exception messages have extra newlines for better
+# formatting when reported as an unhandled exception. Strip
+# them here.
+sys.exit(cmd + str(e).strip())
+raise
+
+def _init(self, filename, warn, warn_to_stderr, encoding):
+# See __init__()
+
self._encoding = encoding
self.srctree = os.getenv("srctree", "")
@@ -943,6 +982,9 @@ class
Re: [PATCH v2 35/39] bdinfo: m68k: Move m68k-specific info into its own file
Tested-by: Angelo Dureghello Environment size: 680/8188 bytes stmark2 $ bdi boot_params = 0x47d96770 DRAM bank = 0x -> start= 0x4000 -> size = 0x0800 memstart= 0x4000 memsize = 0x0800 flashstart = 0x flashsize = 0x flashoffset = 0x baudrate= 115200 bps relocaddr = 0x47dd5000 reloc off = 0xfffd4c00 Build = 32-bit fdt_blob= 0x47d90670 new_fdt = 0x47d90670 fdt_size= 0x2860 sramstart = 0x sramsize= 0x busfreq =120 MHz mbar= 0xfc00 cpufreq =240 MHz flbfreq = 60 MHz inpfreq = 30 MHz vcofreq =480 MHz stmark2 $ On Sun, May 10, 2020 at 10:17 PM Simon Glass wrote: > > We don't really want to have m68k-specific code in a generic file. Create > a new arch-specific function to hold it, and move it into that. > > Make the function weak so that any arch can implement it. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng > Tested-by: Angelo Dureghello > --- > > Changes in v2: None > > arch/m68k/lib/Makefile | 1 + > arch/m68k/lib/bdinfo.c | 29 + > cmd/bdinfo.c | 15 --- > 3 files changed, 30 insertions(+), 15 deletions(-) > create mode 100644 arch/m68k/lib/bdinfo.c --
[PATCH 0/4] bootefi fixes for aarch64/layerscape
I'm bringing up efiboot on a ARM64 board which runs without TF-a and PSCI, therefore the secondary cores are brought up by spin-tables. I ran into several problems. Here are the fixes. Michael Walle (4): efi_loader: aarch64: align runtime section to 64kb efi_loader: check alignment in efi_add_memory_map() fsl-layerscape: align first parameter of efi_add_memory_map() efi_loader: call smp_kick_all_cpus() arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- arch/arm/cpu/armv8/u-boot.lds | 9 - common/bootm.c | 9 + lib/efi_loader/efi_memory.c | 18 +- lib/efi_loader/efi_setup.c | 6 ++ 5 files changed, 29 insertions(+), 15 deletions(-) -- 2.20.1
[PATCH 3/4] fsl-layerscape: align first parameter of efi_add_memory_map()
The start parameter must be aligned to EFI_PAGE_SIZE.
Fixes: 5a37a2f0140c ("armv8: ls2080a: Declare spin tables as reserved for efi
loader")
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 3bbad827cb..fc65ad6c1e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -146,7 +146,7 @@ remove_psci_node:
fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
*boot_code_size);
#if CONFIG_IS_ENABLED(EFI_LOADER)
- efi_add_memory_map((uintptr_t)&secondary_boot_code,
+ efi_add_memory_map(ALIGN_DOWN((uintptr_t)&secondary_boot_code,
EFI_PAGE_SIZE),
ALIGN(*boot_code_size, EFI_PAGE_SIZE) >>
EFI_PAGE_SHIFT,
EFI_RESERVED_MEMORY_TYPE, false);
#endif
--
2.20.1
[PATCH 2/4] efi_loader: check alignment in efi_add_memory_map()
The first argument has to be aligned with EFI_PAGE_SIZE. This alignment
is already checked for external callers but it is not checked for
internal callers. Unfortunately, most of the time the return value is
not checked, so scream loud and clear.
Signed-off-by: Michael Walle
---
lib/efi_loader/efi_memory.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index fd79178da9..b56e19cb30 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -248,6 +248,9 @@ efi_status_t efi_add_memory_map(uint64_t start, uint64_t
pages, int memory_type,
EFI_PRINT("%s: 0x%llx 0x%llx %d %s\n", __func__,
start, pages, memory_type, overlap_only_ram ? "yes" : "no");
+ if (start & EFI_PAGE_MASK)
+ panic("%s: start not aligned\n", __func__);
+
if (memory_type >= EFI_MAX_MEMORY_TYPE)
return EFI_INVALID_PARAMETER;
--
2.20.1
[PATCH 1/4] efi_loader: aarch64: align runtime section to 64kb
Commit 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
already aligned the memory region to 64kb, but it does not align the
actual efi runtime code. Thus it is likely, that efi_add_memory_map()
actually adds a larger memory region than the efi runtime code really
is, which is no error I guess. But what actually leads to an error is
that there might be other efi_add_memory_map() calls with regions
overlapping with the already registered efi runtime code section.
Align the actual runtime code to 64kb instead.
Fixes: 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/u-boot.lds | 9 -
lib/efi_loader/efi_memory.c | 15 ++-
2 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 2554980595..3bc4675586 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -27,7 +27,14 @@ SECTIONS
CPUDIR/start.o (.text*)
}
- /* This needs to come before *(.text*) */
+ /*
+* Runtime Services must be 64KiB aligned according to the
+* "AArch64 Platforms" section in the UEFI spec (2.7+).
+*
+* This needs to come before *(.text*)
+*/
+
+ . = ALIGN(65536);
.efi_runtime : {
__efi_runtime_start = .;
*(.text.efi_runtime*)
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 97d90f069a..fd79178da9 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -734,7 +733,6 @@ __weak void efi_add_known_memory(void)
static void add_u_boot_and_runtime(void)
{
unsigned long runtime_start, runtime_end, runtime_pages;
- unsigned long runtime_mask = EFI_PAGE_MASK;
unsigned long uboot_start, uboot_pages;
unsigned long uboot_stack_size = 16 * 1024 * 1024;
@@ -745,22 +743,13 @@ static void add_u_boot_and_runtime(void)
uboot_start + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
efi_add_memory_map(uboot_start, uboot_pages, EFI_LOADER_DATA, false);
-#if defined(__aarch64__)
- /*
-* Runtime Services must be 64KiB aligned according to the
-* "AArch64 Platforms" section in the UEFI spec (2.7+).
-*/
-
- runtime_mask = SZ_64K - 1;
-#endif
-
/*
* Add Runtime Services. We mark surrounding boottime code as runtime as
* well to fulfill the runtime alignment constraints but avoid padding.
*/
- runtime_start = (ulong)&__efi_runtime_start & ~runtime_mask;
+ runtime_start = (ulong)&__efi_runtime_start & ~EFI_PAGE_MASK;
runtime_end = (ulong)&__efi_runtime_stop;
- runtime_end = (runtime_end + runtime_mask) & ~runtime_mask;
+ runtime_end = (runtime_end + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
efi_add_memory_map(runtime_start, runtime_pages,
EFI_RUNTIME_SERVICES_CODE, false);
--
2.20.1
[PATCH 4/4] efi_loader: call smp_kick_all_cpus()
On some architectures, specifically the layerscape, the secondary cores
wait for an interrupt before entering the spin-tables. This applies only
to boards which doesn't have PSCI provided by TF-a and u-boot does the
secondary cores handling.
bootm/booti already call that function for ARM architecture; also add it
to bootelf before switching to EL2. Additionally, provide a weak noop
function so we don't have to have "#ifdef CONFIG_ARM64" guards.
Signed-off-by: Michael Walle
---
common/bootm.c | 9 +
lib/efi_loader/efi_setup.c | 6 ++
2 files changed, 15 insertions(+)
diff --git a/common/bootm.c b/common/bootm.c
index db4362a643..65adf29329 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -816,6 +816,15 @@ void __weak switch_to_non_secure_mode(void)
{
}
+/**
+ * smp_kick_all_cpus() - kick all CPUs
+ *
+ * This routine is overridden by architectures requiring this feature.
+ */
+void __weak smp_kick_all_cpus(void)
+{
+}
+
#else /* USE_HOSTCC */
#if defined(CONFIG_FIT_SIGNATURE)
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index 26a7423203..7e5364adc5 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -132,6 +132,12 @@ efi_status_t efi_init_obj_list(void)
/* Allow unaligned memory access */
allow_unaligned();
+ /*
+* Some architectures need to kick secondary cores to enter their
+* spin table.
+*/
+ smp_kick_all_cpus();
+
/* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
switch_to_non_secure_mode();
--
2.20.1
How to use TPM in u-boot for Secure Boot?
How can I use TPM in u-boot for secure boot ? U-Boot has TPM support and it provide some driver support and commands. I have enabled TPM support in u-boot. But I don't know how to use it ? Have anybody used TPM in uboot ? -- Sent from: http://u-boot.10912.n7.nabble.com/
Re: [PATCH] phy: sun4i-usb: Align H6 initialization logic with the kernel
CC: ja...@amarulasolutions.com
вт, 12 мая 2020 г. в 21:25, Roman Stratiienko :
>
> H6 SOC needs additional initialization of PHY registers. Corresponding
> changes can be found in the kernel patch [1].
>
> Without this changes there is no enumeration of 'musb' gadget.
>
> [1] -
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ae409cc7c3cdb9ac4a1dba3eae70efec3d6b6c79
>
> Fixes: 35fa673e0e5f ("sunxi: phy: Add USB PHY support for Allwinner H6")
> Signed-off-by: Roman Stratiienko
> ---
> CC: Ondrej Jirman
> CC: Icenowy Zheng
> CC: Marek Vasut
> CC: linux-su...@googlegroups.com
> ---
> drivers/phy/allwinner/phy-sun4i-usb.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> b/drivers/phy/allwinner/phy-sun4i-usb.c
> index 612c428cf5..688ee7d4cc 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -279,7 +279,8 @@ static int sun4i_usb_phy_init(struct phy *phy)
> return ret;
> }
>
> - if (data->cfg->type == sun8i_a83t_phy) {
> + if (data->cfg->type == sun8i_a83t_phy ||
> + data->cfg->type == sun50i_h6_phy) {
> if (phy->id == 0) {
> val = readl(data->base + data->cfg->phyctl_offset);
> val |= PHY_CTL_VBUSVLDEXT;
> @@ -321,7 +322,8 @@ static int sun4i_usb_phy_exit(struct phy *phy)
> int ret;
>
> if (phy->id == 0) {
> - if (data->cfg->type == sun8i_a83t_phy) {
> + if (data->cfg->type == sun8i_a83t_phy ||
> + data->cfg->type == sun50i_h6_phy) {
> void __iomem *phyctl = data->base +
> data->cfg->phyctl_offset;
>
> --
> 2.25.1
>
Re: [PATCH] musb-new: Use predefined configuration data for SUN50I_H6
CC: ja...@amarulasolutions.com
пт, 8 мая 2020 г. в 15:29, Roman Stratiienko :
>
> Same was done in the kernel for all devices compatible with
> 'allwinner,sun8i-a33-musb' at [1] and [2].
>
> Fixes musb initialization on H6 SOC.
>
> [1] -
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/usb/musb/sunxi.c?h=v5.6.11#n726
> [2] -
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/usb/musb/sunxi.c?h=v5.6.11#n440
>
> Signed-off-by: Roman Stratiienko
> ---
> CC: Ondrej Jirman
> CC: Icenowy Zheng
> CC: Marek Vasut
> CC: linux-su...@googlegroups.com
>
> Hello community,
>
> '$ fastboot usb 0' command works, but host still doesn't see any USB devices.
> Does anyone have any suggestions where to look?
> ---
> drivers/usb/musb-new/musb_regs.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/musb-new/musb_regs.h
> b/drivers/usb/musb-new/musb_regs.h
> index c4d7203b85..5f012f3b41 100644
> --- a/drivers/usb/musb-new/musb_regs.h
> +++ b/drivers/usb/musb-new/musb_regs.h
> @@ -432,7 +432,9 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem
> *mbase)
> static inline u8 musb_read_configdata(void __iomem *mbase)
> {
> #if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T || \
> - defined CONFIG_MACH_SUNXI_H3_H5 || defined CONFIG_MACH_SUN50I
> + defined CONFIG_MACH_SUNXI_H3_H5 || defined CONFIG_MACH_SUN50I || \
> + defined CONFIG_MACH_SUN50I_H6
> +
> /* allwinner saves a reg, and we need to hardcode this */
> return 0xde;
> #else
> --
> 2.25.1
>
[PATCH] net: dwc_eth_qos: update the compatible supported for STM32
Update the compatible associated with the STM32 MPU glue
in the DWC ethernet driver.
The supported compatible is the specific "st,stm32mp1-dwmac"
as indicated in Linux binding
Documentation/devicetree/bindings/net/stm32-dwmac.txt
and not the "snps,dwmac-4.20a" only used to the select IP
version.
This glue is implemented in Linux kernel in:
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
For information in stm32mp151.dtsi, the 2 compatibles are
supported:
ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
...
};
Serie-cc: Christophe ROULLIER
Serie-cc: David Wu
Serie-cc: marex
Signed-off-by: Patrick Delaunay
---
drivers/net/dwc_eth_qos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index f67c5f4570..5e7ad6c658 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -2166,7 +2166,7 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)&eqos_tegra186_config
},
{
- .compatible = "snps,dwmac-4.20a",
+ .compatible = "st,stm32mp1-dwmac",
.data = (ulong)&eqos_stm32_config
},
{
--
2.17.1
Re: [PATCH] dm: core: Reorder include files in read.c
Hi Stefan, OK. Feel free to pull it in if you like as you have my review tag. Regards, SImon On Thu, 14 May 2020 at 03:30, Stefan Roese wrote: > > Hi Simon, > > On 29.04.20 20:04, Simon Glass wrote: > > On Wed, 29 Apr 2020 at 01:08, Stefan Roese wrote: > >> > >> Including the assembler headers before including common.h etc leads to > >> compilation errors upon MIPS64 based platforms using OF_LIVE. This > >> patch reorders the include files to the "correct" oder. > >> > >> Signed-off-by: Stefan Roese > >> Cc: Simon Glass > >> --- > >> drivers/core/read.c | 6 +++--- > >> 1 file changed, 3 insertions(+), 3 deletions(-) > > > > Reviewed-by: Simon Glass > > > > Just a short reminder about this patch, as its needed for the base > Octeon (MIPS) support, I'm currently working on. Otherwise, usage of > OF_LIVE is not possible. > > Thanks, > Stefan >
[PATCH] sf: Drop spl_flash_get_sw_write_prot
The get_sw_write_prot API is used to get the write-protected
bits of flash by reading the status register and other wards
it's API for reading register bits.
1) This kind of requirement can be achieved using existing
flash operations and flash locking API calls instead of
making a separate flash API.
2) Technically there is no real hardware user for this API to
use in the source tree.
3) Having a flash operations API for simple register read bits
also make difficult to extend the flash operations.
4) Instead of touching generic code, it is possible to have
this functionality inside spinor operations in the form of
flash hooks or fixups for associated flash chips.
Considering all these points, this patch drops the get_sw_write_prot
and associated code bases.
Cc: Simon Glass
Cc: Vignesh R
Signed-off-by: Jagan Teki
---
drivers/mtd/spi/sf-uclass.c| 9 -
drivers/mtd/spi/sf_internal.h | 4
drivers/mtd/spi/sf_probe.c | 8
drivers/mtd/spi/spi-nor-core.c | 11 ---
drivers/mtd/spi/spi-nor-tiny.c | 6 --
include/spi_flash.h| 27 ---
test/dm/sf.c | 8
7 files changed, 73 deletions(-)
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index 5ebcca590a..5a42ab83c8 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -29,15 +29,6 @@ int spi_flash_erase_dm(struct udevice *dev, u32 offset,
size_t len)
return log_ret(sf_get_ops(dev)->erase(dev, offset, len));
}
-int spl_flash_get_sw_write_prot(struct udevice *dev)
-{
- struct dm_spi_flash_ops *ops = sf_get_ops(dev);
-
- if (!ops->get_sw_write_prot)
- return -ENOSYS;
- return log_ret(ops->get_sw_write_prot(dev));
-}
-
/*
* TODO(s...@chromium.org): This is an old-style function. We should remove
* it when all SPI flash drivers use dm
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 544ed74a5f..5fc662875e 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -74,10 +74,6 @@ extern const struct flash_info spi_nor_ids[];
#define JEDEC_MFR(info)((info)->id[0])
#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
-/* Get software write-protect value (BP bits) */
-int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
-
-
#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
int spi_flash_mtd_register(struct spi_flash *flash);
void spi_flash_mtd_unregister(void);
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 1e8744896c..f167bfab8a 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -129,13 +129,6 @@ static int spi_flash_std_erase(struct udevice *dev, u32
offset, size_t len)
return mtd->_erase(mtd, &instr);
}
-static int spi_flash_std_get_sw_write_prot(struct udevice *dev)
-{
- struct spi_flash *flash = dev_get_uclass_priv(dev);
-
- return spi_flash_cmd_get_sw_write_prot(flash);
-}
-
int spi_flash_std_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
@@ -159,7 +152,6 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
.read = spi_flash_std_read,
.write = spi_flash_std_write,
.erase = spi_flash_std_erase,
- .get_sw_write_prot = spi_flash_std_get_sw_write_prot,
};
static const struct udevice_id spi_flash_std_ids[] = {
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 984cece0b0..c5aff6f5c6 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2639,14 +2639,3 @@ int spi_nor_scan(struct spi_nor *nor)
return 0;
}
-
-/* U-Boot specific functions, need to extend MTD to support these */
-int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
-{
- int sr = read_sr(nor);
-
- if (sr < 0)
- return sr;
-
- return (sr >> 2) & 7;
-}
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
index ccc0ab07af..06e3dad8c4 100644
--- a/drivers/mtd/spi/spi-nor-tiny.c
+++ b/drivers/mtd/spi/spi-nor-tiny.c
@@ -797,9 +797,3 @@ int spi_nor_scan(struct spi_nor *nor)
return 0;
}
-
-/* U-Boot specific functions, need to extend MTD to support these */
-int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
-{
- return -ENOTSUPP;
-}
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 0b23f57a71..d9b2af856c 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -34,19 +34,6 @@ struct dm_spi_flash_ops {
int (*write)(struct udevice *dev, u32 offset, size_t len,
const void *buf);
int (*erase)(struct udevice *dev, u32 offset, size_t len);
- /**
-* get_sw_write_prot() - Check state of software write-protect feature
-*
-* SPI flash chips can lock a region of the flash defined by a
-* 'protected area'. This function che
Re: [PATCH] dm: core: Reorder include files in read.c
Hi Simon, On 14.05.20 14:49, Simon Glass wrote: OK. Feel free to pull it in if you like as you have my review tag. Thanks Simon. Since Daniel will be the one pulling the Octeon patchset once we've reached the necessary ack's, he now knows that he can pull this one as well. But this will take a few more versions most likely. Perhaps this patch has landed in mainline until then. Thanks, Stefan Regards, SImon On Thu, 14 May 2020 at 03:30, Stefan Roese wrote: Hi Simon, On 29.04.20 20:04, Simon Glass wrote: On Wed, 29 Apr 2020 at 01:08, Stefan Roese wrote: Including the assembler headers before including common.h etc leads to compilation errors upon MIPS64 based platforms using OF_LIVE. This patch reorders the include files to the "correct" oder. Signed-off-by: Stefan Roese Cc: Simon Glass --- drivers/core/read.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass Just a short reminder about this patch, as its needed for the base Octeon (MIPS) support, I'm currently working on. Otherwise, usage of OF_LIVE is not possible. Thanks, Stefan Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
[RESEND PATCH] net: dwc_eth_qos: update the compatible supported for STM32
Update the compatible associated with the STM32 MPU glue
in the DWC ethernet driver.
The supported compatible is the specific "st,stm32mp1-dwmac"
as indicated in Linux binding
Documentation/devicetree/bindings/net/stm32-dwmac.txt
and not the "snps,dwmac-4.20a" only used to the select IP
version.
This glue is implemented in Linux kernel in:
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
For information in stm32mp151.dtsi, the 2 compatibles are
supported:
ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
...
};
Signed-off-by: Patrick Delaunay
---
RESEND with fix patman on Series-cc
drivers/net/dwc_eth_qos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index f67c5f4570..5e7ad6c658 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -2166,7 +2166,7 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)&eqos_tegra186_config
},
{
- .compatible = "snps,dwmac-4.20a",
+ .compatible = "st,stm32mp1-dwmac",
.data = (ulong)&eqos_stm32_config
},
{
--
2.17.1
[PATCH] x86: coreboot: add SMBIOS cbmem entry parsing
Signed-off-by: Christian Gmeiner
---
arch/x86/cpu/coreboot/tables.c | 14 ++
arch/x86/include/asm/arch-coreboot/sysinfo.h | 2 ++
arch/x86/include/asm/coreboot_tables.h | 11 +++
3 files changed, 27 insertions(+)
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index 0f04c4f8e9..a5d31d1dea 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -69,6 +69,17 @@ static void cb_parse_vbnv(unsigned char *ptr, struct
sysinfo_t *info)
info->vbnv_size = vbnv->vbnv_size;
}
+static void cb_parse_cbmem_entry(unsigned char *ptr, struct sysinfo_t *info)
+{
+ struct cb_cbmem_entry *entry = (struct cb_cbmem_entry *)ptr;
+
+ if (entry->id != CBMEM_ID_SMBIOS)
+ return;
+
+ info->smbios_start = entry->address;
+ info->smbios_size = entry->entry_size;
+}
+
static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info)
{
int i;
@@ -206,6 +217,9 @@ static int cb_parse_header(void *addr, int len, struct
sysinfo_t *info)
case CB_TAG_VBNV:
cb_parse_vbnv(ptr, info);
break;
+ case CB_TAG_CBMEM_ENTRY:
+ cb_parse_cbmem_entry(ptr, info);
+ break;
default:
cb_parse_unhandled(rec->tag, ptr);
break;
diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h
b/arch/x86/include/asm/arch-coreboot/sysinfo.h
index dd8d1cba92..419ec52933 100644
--- a/arch/x86/include/asm/arch-coreboot/sysinfo.h
+++ b/arch/x86/include/asm/arch-coreboot/sysinfo.h
@@ -49,6 +49,8 @@ struct sysinfo_t {
u32 vdat_size;
void*tstamp_table;
void*cbmem_cons;
+ u64 smbios_start;
+ u32 smbios_size;
struct cb_serial *serial;
};
diff --git a/arch/x86/include/asm/coreboot_tables.h
b/arch/x86/include/asm/coreboot_tables.h
index 268284f43c..7e1576768b 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -214,6 +214,17 @@ struct cb_vbnv {
uint32_t vbnv_size;
};
+#define CB_TAG_CBMEM_ENTRY 0x0031
+#define CBMEM_ID_SMBIOS0x534d4254
+
+struct cb_cbmem_entry {
+ uint32_t tag;
+ uint32_t size;
+ uint64_t address;
+ uint32_t entry_size;
+ uint32_t id;
+};
+
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table {
--
2.25.1
[RFC PATCH] mtd: spi: Drop redundent SPI flash driver
UCLASS_SPI_FLASH driver at driver/mtd/spi is a generic
spi flash driver to probe jedec,spi-nor flash chips.
Technically a probe call in U_BOOT_DRIVER is local to that
driver and not applicable to use it another driver or in
another code.
The apollolake SPL code using the generic probe by adding
extra SPI flash driver, which make more confusion in terms
of code readability and driver model structure.
The fact that apollolake SPL requires a separate SPI flash
driver to handle of-platdata via bind call, so move the
bind call in the generic flash driver and drop the driver
from apollolake code.
I hope this wouldn't break generic code usage flash chips
otherwise, we can handle this via driver data or a separate
spi driver in drivers/mtd/spi.
Cc: Bin Meng
Cc: Simon Glass
Cc: Vignesh R
Signed-off-by: Jagan Teki
---
arch/x86/cpu/apollolake/spl.c | 60 ---
drivers/mtd/spi/sf_probe.c| 29 -
include/spi_flash.h | 12 ---
3 files changed, 28 insertions(+), 73 deletions(-)
diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c
index d32f2a9898..2e6013d04c 100644
--- a/arch/x86/cpu/apollolake/spl.c
+++ b/arch/x86/cpu/apollolake/spl.c
@@ -65,66 +65,6 @@ SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP,
rom_load_image);
#if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
-static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
- void *buf)
-{
- struct spi_flash *flash = dev_get_uclass_priv(dev);
- struct mtd_info *mtd = &flash->mtd;
- size_t retlen;
-
- return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
-}
-
-static int apl_flash_probe(struct udevice *dev)
-{
- return spi_flash_std_probe(dev);
-}
-
-/*
- * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
- * need to allocate the parent_platdata since by the time this function is
- * called device_bind() has already gone past that step.
- */
-static int apl_flash_bind(struct udevice *dev)
-{
- if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
- struct dm_spi_slave_platdata *plat;
- struct udevice *spi;
- int ret;
-
- ret = uclass_first_device_err(UCLASS_SPI, &spi);
- if (ret)
- return ret;
- dev->parent = spi;
-
- plat = calloc(sizeof(*plat), 1);
- if (!plat)
- return -ENOMEM;
- dev->parent_platdata = plat;
- }
-
- return 0;
-}
-
-static const struct dm_spi_flash_ops apl_flash_ops = {
- .read = apl_flash_std_read,
-};
-
-static const struct udevice_id apl_flash_ids[] = {
- { .compatible = "jedec,spi-nor" },
- { }
-};
-
-U_BOOT_DRIVER(winbond_w25q128fw) = {
- .name = "winbond_w25q128fw",
- .id = UCLASS_SPI_FLASH,
- .of_match = apl_flash_ids,
- .bind = apl_flash_bind,
- .probe = apl_flash_probe,
- .priv_auto_alloc_size = sizeof(struct spi_flash),
- .ops= &apl_flash_ops,
-};
-
/* This uses a SPI flash device to read the next phase */
static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index f167bfab8a..06dac57daf 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -129,7 +129,7 @@ static int spi_flash_std_erase(struct udevice *dev, u32
offset, size_t len)
return mtd->_erase(mtd, &instr);
}
-int spi_flash_std_probe(struct udevice *dev)
+static int spi_flash_std_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
struct spi_flash *flash;
@@ -154,6 +154,32 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
.erase = spi_flash_std_erase,
};
+/*
+ * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
+ * need to allocate the parent_platdata since by the time this function is
+ * called device_bind() has already gone past that step.
+ */
+static int spi_flash_bind(struct udevice *dev)
+{
+ if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
+ struct dm_spi_slave_platdata *plat;
+ struct udevice *spi;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_SPI, &spi);
+ if (ret)
+ return ret;
+ dev->parent = spi;
+
+ plat = calloc(sizeof(*plat), 1);
+ if (!plat)
+ return -ENOMEM;
+ dev->parent_platdata = plat;
+ }
+
+ return 0;
+}
+
static const struct udevice_id spi_flash_std_ids[] = {
{ .compatible = "jedec,spi-nor" },
{ }
@@ -163,6 +189,7 @@ U_BOOT_DRIVER(spi_flash_std) = {
.name = "spi_f
