Re: [PATCH] spi: mvebu_a3700_spi: add support for cs-gpios

[Stefan Roese]

On 28.09.20 20:16, George Hilliard wrote:

The device tree has a way to specify GPIO lines as chip selects.  From
the binding docs:

 So if for example the controller has 2 CS lines, and the cs-gpios
 property looks like this:

 cs-gpios = < 0 0> <0> < 1 0> < 2 0>;

 Then it should be configured so that num_chipselect = 4 with the
 following mapping:

 cs0 :  0 0
 cs1 : native
 cs2 :  1 0
 cs3 :  2 0

Add support for this, while retaining backward-compatibility with
existing device trees; the driver will preserve existing behavior if a
cs-gpios list is not given, or if a particular line is specified as <0>
(native).

This implementation is inspired by similar implementations in
neighboring drivers for other platforms: atmega, mxc, etc.

Signed-off-by: George Hilliard 
---
  drivers/spi/mvebu_a3700_spi.c | 50 ++-
  1 file changed, 44 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index e860b9ec64..95be590a68 100644
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -15,6 +15,9 @@
  #include 
  #include 
  #include 
+#if CONFIG_IS_ENABLED(DM_GPIO)
+#include 
+#endif


To not add more #ifdef's, perhaps its better to include the header
unconditionally here...

  
  DECLARE_GLOBAL_DATA_PTR;
  
@@ -27,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;

  #define MVEBU_SPI_A3700_SPI_EN_0  BIT(16)
  #define MVEBU_SPI_A3700_CLK_PRESCALE_MASK 0x1f
  
+#define MAX_CS_COUNT	4
  
  /* SPI registers */

  struct spi_reg {
@@ -39,16 +43,29 @@ struct spi_reg {
  struct mvebu_spi_platdata {
struct spi_reg *spireg;
struct clk clk;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+   struct gpio_desc cs_gpios[MAX_CS_COUNT];
+#endif


...and this variable in the struct as well...


  };
  
-static void spi_cs_activate(struct spi_reg *reg, int cs)

+static void spi_cs_activate(struct mvebu_spi_platdata *plat, int cs)
  {
-   setbits_le32(>ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
+#if CONFIG_IS_ENABLED(DM_GPIO)
+   if (dm_gpio_is_valid(>cs_gpios[cs]))
+   dm_gpio_set_value(>cs_gpios[cs], 1);
+   else
+#endif
+   setbits_le32(>spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << 
cs);


... and use this instead here (and below):

if (CONFIG_IS_ENABLED(DM_GPIO)) &&
dm_gpio_is_valid(>cs_gpios[cs]))
dm_gpio_set_value(>cs_gpios[cs], 1);
else
setbits_le32(>spireg->ctrl,
MVEBU_SPI_A3700_SPI_EN_0 << cs);

What do you think?

Thanks,
Stefan


  }
  
-static void spi_cs_deactivate(struct spi_reg *reg, int cs)

+static void spi_cs_deactivate(struct mvebu_spi_platdata *plat, int cs)
  {
-   clrbits_le32(>ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
+#if CONFIG_IS_ENABLED(DM_GPIO)
+   if (dm_gpio_is_valid(>cs_gpios[cs]))
+   dm_gpio_set_value(>cs_gpios[cs], 0);
+   else
+#endif
+   clrbits_le32(>spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << 
cs);
  }
  
  /**

@@ -150,7 +167,7 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
/* Activate CS */
if (flags & SPI_XFER_BEGIN) {
debug("SPI: activate cs.\n");
-   spi_cs_activate(reg, spi_chip_select(dev));
+   spi_cs_activate(plat, spi_chip_select(dev));
}
  
  	/* Send and/or receive */

@@ -169,7 +186,7 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
return ret;
  
  		debug("SPI: deactivate cs.\n");

-   spi_cs_deactivate(reg, spi_chip_select(dev));
+   spi_cs_deactivate(plat, spi_chip_select(dev));
}
  
  	return 0;

@@ -247,6 +264,27 @@ static int mvebu_spi_probe(struct udevice *bus)
  
  	writel(data, >cfg);
  
+	/* Set up CS GPIOs in device tree, if any */

+#if CONFIG_IS_ENABLED(DM_GPIO)
+   if (gpio_get_list_count(bus, "cs-gpios") > 0) {
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
+   ret = gpio_request_by_name(bus, "cs-gpios", i, 
>cs_gpios[i], 0);
+   if (ret < 0 || !dm_gpio_is_valid(>cs_gpios[i]))
+   // Use the native CS function for this line
+   continue;
+
+   ret = dm_gpio_set_dir_flags(>cs_gpios[i],
+   GPIOD_IS_OUT | 
GPIOD_ACTIVE_LOW);
+   if (ret) {
+   dev_err(bus, "Setting cs %d error\n", i);
+   return ret;
+   }
+   }
+   }
+#endif
+
return 0;
  }
  




Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: 

Re: [PATCH] drivers: serial: probe all uart devices

[Stefan Roese]

On 28.09.20 19:43, Vabhav Sharma wrote:

From: Vabhav Sharma 

U-Boot DM model probe only single device at a time
which is enabled and configured using device tree
or platform data method.

PL011 UART IP is SBSA compliant and firmware does the
serial port set-up, initialization and let the kernel use
UART port for sending and receiving characters.

Normally software talk to one serial port time but some
LayerScape platform require all the UART devices enabled
in Linux for various use case.

Adding support to probe all enabled serial devices like SBSA
compliant PL011 UART ports probe and initialization by firmware.

Signed-off-by: Vabhav Sharma 
---
  drivers/serial/Kconfig | 17 +
  drivers/serial/serial-uclass.c | 30 ++
  2 files changed, 47 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e344677..b2e30f1 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -134,6 +134,23 @@ config SERIAL_SEARCH_ALL
  
  	  If unsure, say N.
  
+config SERIAL_PROBE_ALL

+   bool "Probe all available serial devices"
+   depends on DM_SERIAL
+   default n
+   help
+ The serial subsystem only probe for single serial device,
+ but does not probe for other remaining serial devices.
+ With this option set,we make probing and searching for
+ all available devices optional.
+ Normally, U-Boot talk to one serial port at a time but SBSA
+ compliant UART devices like PL011 require initialization
+ by firmware and let the kernel use serial port for sending
+ and receiving the characters.
+
+ If probing is not required for all remaining available
+ devices other than default current console device, say N.
+
  config SPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in SPL"
depends on DM_SERIAL && SPL_DM
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 0027625..9b2fcb0 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -86,6 +86,11 @@ static void serial_find_console_or_panic(void)
uclass_first_device(UCLASS_SERIAL, );
if (dev) {
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif


Please don't use #ifdef's here but instead something like this:

if (IS_ENABLED(CONFIG_SERIAL_PROBE_ALL)) {
/* Scanning uclass to probe all devices */
for (; dev; uclass_next_device())
;
}


return;
}
} else if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
@@ -96,11 +101,21 @@ static void serial_find_console_or_panic(void)
if (np && !uclass_get_device_by_ofnode(UCLASS_SERIAL,
np_to_ofnode(np), )) {
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif


And please everywhere else as well.

Thanks,
Stefan


return;
}
} else {
if (!serial_check_stdout(blob, )) {
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif
return;
}
}
@@ -125,6 +140,11 @@ static void serial_find_console_or_panic(void)
!uclass_get_device(UCLASS_SERIAL, INDEX, )) {
if (dev->flags & DM_FLAG_ACTIVATED) {
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif
return;
}
}
@@ -136,6 +156,11 @@ static void serial_find_console_or_panic(void)
if (!ret) {
/* Device did succeed probing */
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif
return;
}
}
@@ -144,6 +169,11 

[PATCH] armv8: dts: fsl-lx2162a: add dspi node into qds dts

[Qiang Zhao]

From: Zhao Qiang 

Add dspi node into lx2162aqds device tree

Signed-off-by: Zhao Qiang 
---
depends on: 
https://patchwork.ozlabs.org/project/uboot/patch/1599473527-21511-3-git-send-email-meenakshi.aggar...@nxp.com/

 arch/arm/dts/fsl-lx2162a-qds.dts | 99 
 1 file changed, 99 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts
index a2be9ac..92871bc 100644
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -31,6 +31,105 @@
};
 };
 
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   dflash0: n25q128a {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <0>;
+   };
+   dflash1: sst25wf040b {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <1>;
+   };
+   dflash2: en25s64 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <2>;
+   };
+};
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   dflash3: n25q128a {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <0>;
+   };
+   dflash4: sst25wf040b {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <1>;
+   };
+   dflash5: en25s64 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <2>;
+   };
+};
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   dflash6: n25q128a {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <0>;
+   };
+   dflash7: sst25wf040b {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <1>;
+   };
+   dflash8: en25s64 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <300>;
+   spi-cpol;
+   spi-cpha;
+   reg = <2>;
+   };
+};
+
  {
status = "okay";
 
-- 
2.7.4

Re: [PATCH 1/3] sunxi: dts: OrangePi Zero: Add SPI aliases to make bus usable with u-boot.

[Chen-Yu Tsai]

(Resend from @kernel.org address)

On Tue, Sep 29, 2020 at 5:02 AM Michal Suchanek  wrote:
>
> The u-boot code relies on aliases to assign bus number.
>
> Signed-off-by: Michal Suchanek 
> ---
>  arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 2 ++

Anything U-boot specific should be done in the *-u-boot.dts file.
And any changes you do to the U-boot copy of dts files will potentially
be lost when a dts sync happens.

ChenYu

>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts 
> b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
> index f19ed981da..090570148e 100644
> --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
> +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
> @@ -59,6 +59,8 @@
> /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
> ethernet0 = 
> ethernet1 = 
> +   spi0 = 
> +   spi1 = 
> };
>
> chosen {
> --
> 2.28.0
>

Re: [PATCH] net: ftgmac100: Add support for board specific PHY interface address

[Thirupathaiah Annapureddy]

Hi Tom/Joe,

Is this going to be applied to u-boot/next or u-boot-net?

Best Regards,
Thiru

On 8/17/2020 5:08 PM, Thirupathaiah Annapureddy wrote:
> ftgmac100 driver is using hard-coded PHY interface address of zero.
> Each board can have different PHY interface address (phy_addr).
> This commit modifies the driver to make use of board specific address
> by leveraging CONFIG_PHY_ADDR.
> 
> Signed-off-by: Thirupathaiah Annapureddy 
> ---
>  drivers/net/ftgmac100.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
> index 5676a5b3ba..00bda24f1f 100644
> --- a/drivers/net/ftgmac100.c
> +++ b/drivers/net/ftgmac100.c
> @@ -551,6 +551,10 @@ static int ftgmac100_probe(struct udevice *dev)
>   priv->max_speed = pdata->max_speed;
>   priv->phy_addr = 0;
>  
> +#ifdef CONFIG_PHY_ADDR
> + priv->phy_addr = CONFIG_PHY_ADDR;
> +#endif
> +
>   ret = clk_enable_bulk(>clks);
>   if (ret)
>   goto out;
> 

[PATCH 1/1] sandbox: avoid duplicate backslash input

[Heinrich Schuchardt]

When using SDL for input the SDL key codes are first converted to Linux key
codes and then to matrix entries of the cross wired keyboard.

We must not map any key code to two different places on the keyboard. So
comment out one backslash position.

Update the rest of the file from Linux 5.7.

Signed-off-by: Heinrich Schuchardt 
---
 arch/sandbox/dts/cros-ec-keyboard.dtsi | 20 +++-
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/sandbox/dts/cros-ec-keyboard.dtsi 
b/arch/sandbox/dts/cros-ec-keyboard.dtsi
index 9c7fb0acae..d885a5ecd2 100644
--- a/arch/sandbox/dts/cros-ec-keyboard.dtsi
+++ b/arch/sandbox/dts/cros-ec-keyboard.dtsi
@@ -1,12 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Keyboard dts fragment for devices that use cros-ec-keyboard
  *
  * Copyright (c) 2014 Google, Inc
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ * This file is taken from Linux
+ * arch/arm/boot/dts/cros-ec-keyboard.dtsi.
+ *
+ * A duplicate KEY_BACKSLASH key had to be removed.
+ */

 #include 

@@ -22,6 +24,7 @@
MATRIX_KEY(0x00, 0x02, KEY_F1)
MATRIX_KEY(0x00, 0x03, KEY_B)
MATRIX_KEY(0x00, 0x04, KEY_F10)
+   MATRIX_KEY(0x00, 0x05, KEY_RO)
MATRIX_KEY(0x00, 0x06, KEY_N)
MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
@@ -34,6 +37,7 @@
MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
MATRIX_KEY(0x01, 0x09, KEY_F9)
MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
+   MATRIX_KEY(0x01, 0x0c, KEY_HENKAN)

MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
MATRIX_KEY(0x02, 0x01, KEY_TAB)
@@ -45,6 +49,7 @@
MATRIX_KEY(0x02, 0x07, KEY_102ND)
MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
MATRIX_KEY(0x02, 0x09, KEY_F8)
+   MATRIX_KEY(0x02, 0x0a, KEY_YEN)

MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
MATRIX_KEY(0x03, 0x02, KEY_F2)
@@ -52,7 +57,9 @@
MATRIX_KEY(0x03, 0x04, KEY_F5)
MATRIX_KEY(0x03, 0x06, KEY_6)
MATRIX_KEY(0x03, 0x08, KEY_MINUS)
+   MATRIX_KEY(0x03, 0x09, KEY_F13)
MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
+   MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN)

MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
MATRIX_KEY(0x04, 0x01, KEY_A)
@@ -63,7 +70,10 @@
MATRIX_KEY(0x04, 0x06, KEY_J)
MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
MATRIX_KEY(0x04, 0x09, KEY_L)
-   MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
+   /*
+* Do not map any key twice
+* MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
+*/
MATRIX_KEY(0x04, 0x0b, KEY_ENTER)

MATRIX_KEY(0x05, 0x01, KEY_Z)
--
2.28.0

Re: [PATCH v2 1/1] riscv: restore global data pointer in trap handler

[Rick Chen]

Hi Heinrich

> On 28.09.20 09:45, Rick Chen wrote:
> >> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
> >> Sent: Sunday, September 27, 2020 4:24 PM
> >> To: Rick Jian-Zhi Chen(陳建志)
> >> Cc: Simon Glass; Sean Anderson; Bin Meng; u-boot@lists.denx.de; Alexander 
> >> Graf; Abner Chang; Heinrich Schuchardt
> >> Subject: [PATCH v2 1/1] riscv: restore global data pointer in trap handler
> >>
> >> The gp register is used to store U-Boot's global data pointer. We should
> >> not assume that an UEFI application leaves the gp register unchanged as
> >> the UEFI specifications does not define who is the owner of the gp and tp
> >> registers.
> >>
> >> So the following sequence should be followed in the trap handler:
> >>
> >> * save the caller's gp register
> >> * restore the global data pointer
> >> * serve interrupts or print crash dump and reset
> >> * restore the caller's gp register
> >>
> >> Cc: Abner Chang 
> >> Signed-off-by: Heinrich Schuchardt 
> >> ---
> >> v2:
> >> Saving and restoring the caller's x3 is already handled in mtrap.S.
> >> efi_loader.h provides an empty fallback efi_restore_gd() function
> >> if CONFIG_EFI_LOADER=n.
> >> ---
> >>  arch/riscv/lib/interrupts.c | 3 +++
> >>  1 file changed, 3 insertions(+)
> >
> > Reviewed-by: Rick Chen 
> >
>
> Hello Rick,
>
> I have two other corrections for the UEFI sub-system and would like to
> add this patch to my pull-request for v2020.10. Is that ok with you?

I am OK with it.

Thanks,
Rick

>
> Best regards
>
> Heinrich

Re: [BUG] sandbox: './u-boot -l ' fails

[Heinrich Schuchardt]

On 9/29/20 1:59 AM, Heinrich Schuchardt wrote:
> On 9/29/20 12:19 AM, Simon Glass wrote:
>> Hi Heinrich,
>>
>> On Mon, 28 Sep 2020 at 15:23, Heinrich Schuchardt  wrote:
>>>
>>> On 9/28/20 3:42 PM, Simon Glass wrote:
 Hi Heinrich,

 On Mon, 28 Sep 2020 at 07:30, Heinrich Schuchardt  
 wrote:
>
> On 28.09.20 15:22, Simon Glass wrote:
>> Hi Heinrich,
>>
>> On Mon, 28 Sep 2020 at 05:31, Heinrich Schuchardt  
>> wrote:
>>>
>>> On 28.09.20 06:46, Heinrich Schuchardt wrote:
 Am 28. September 2020 06:24:38 MESZ schrieb Simon Glass 
 :
> Hi Heinrich,
>
> On Sat, 19 Sep 2020 at 13:48, Heinrich Schuchardt 
> wrote:
>>
>> Hello Simon,
>>
>> when I try to run ./u-boot -l the sandbox stalls. Shouldn't it run
> out
>> of the box?
>>
>> $ ./u-boot -l -d arch/sandbox/dts/sandbox.dtb
>
> For the record you should be able to use -D to get the same effect as
> your -d above.
>
>>
>> U-Boot 2020.10-rc4-00018-g21a10244f9-dirty (Sep 19 2020 - 19:55:39
> +0200)
>>
>> Model: sandbox
>> DRAM:  128 MiB
>>
>> Warning: host_lo MAC addresses don't match:
>> Address in ROM is   26:4b:ca:6c:98:f4
>> Address in environment is   00:00:11:22:33:44
>>
>> Warning: host_virbr0 MAC addresses don't match:
>> Address in ROM is   ee:3e:c9:ce:1f:9c
>> Address in environment is   00:00:11:22:33:45
>>
>> Warning: host_docker0 MAC addresses don't match:
>> Address in ROM is   c2:85:07:7b:9a:18
>> Address in environment is   00:00:11:22:33:46
>> WDT:   Not found!
>> MMC:
>>
>> No output after this point.
>>
>> The problem also exists with U-Boot v2020.07, v2019.10, v2018.11.
>>
>> CONFIG_SANDBOX_SDL=y
>>
>> SDL_InitSubSystem() never returns. It is looping somewhere in
> U-Boot's
>> __serial_getc(). I wonder how it gets there without returning from
> the
>> function.
>>
>> I compiled SDL2.cpp from
>> https://gist.github.com/miguelmartin75/6946310#file-sdl2-cpp-L18
>> with
>>
>> g++ SDL2.cpp -D_REENTRANT -I/usr/include/SDL2 -lSDL2 -lGL -o test
>>
>> and it runs fine showing an X11 windows with red background.
>>
>> So there seems to be no general problem with the SDL2 library.
>
> I hit this myself on another computer and it turned out to be that SDL
> defined getc(), as does U-Boot, and things get confused. At least I
> think it is getc.
>
> I hacked around with changing the name of getc (I think it was getc)
> in U-Boot and the problem went away.

 Should we include a patched SDL2 with U-Boot for static linking?

>>>
>>> I cannot find a symbol getc() nor a reference to it in the SDL
>>> repository. getc() is defined in stdio.h.
>>>
>>> Our getc() takes no argument, while the stdio one wants a FILE *.
>>>
>>> But changing the U-Boot definition to "int getc(void *)" does not solve
>>> the issue.
>>
>> I just tried it on the machine where it doesn't work:
>>
>> $ gdb --args /tmp/b/sandbox/u-boot -l -D
>> GNU gdb (Debian 9.2-1) 9.2
>> Copyright (C) 2020 Free Software Foundation, Inc.
>> License GPLv3+: GNU GPL version 3 or later 
>> 
>> This is free software: you are free to change and redistribute it.
>> There is NO WARRANTY, to the extent permitted by law.
>> Type "show copying" and "show warranty" for details.
>> This GDB was configured as "x86_64-linux-gnu".
>> Type "show configuration" for configuration details.
>> For bug reporting instructions, please see:
>> .
>> Find the GDB manual and other documentation resources online at:
>> .
>>
>> For help, type "help".
>> Type "apropos word" to search for commands related to "word"...
>> Reading symbols from /tmp/b/sandbox/u-boot...
>> (gdb) br getc
>> Breakpoint 1 at 0x5b6d6: getc. (2 locations)
>> (gdb) r
>> Starting program: /tmp/b/sandbox/u-boot -l -D
>> [Thread debugging using libthread_db enabled]
>> Using host libthread_db library 
>> "/lib/x86_64-linux-gnu/libthread_db.so.1".
>>
>>
>> U-Boot 2020.10-rc5-00196-g0ac83d080a0 (Sep 28 2020 - 07:11:52 -0600)
>>
>> Model: sandbox
>> DRAM:  128 MiB
>>
>> Warning: host_lo MAC addresses don't match:
>> Address in ROM is 1a:34:9b:48:aa:53
>> Address in environment is 00:00:11:22:33:44
>> WDT:   Not found!

[PATCH 1/1] sandbox: make SDL window resizable

[Heinrich Schuchardt]

Without resizing the SDL window showed by

./u-boot -D -l

is not legible on a high resolution screen.

Start with a maximized window and allow resizing.

Signed-off-by: Heinrich Schuchardt 
---
 arch/sandbox/cpu/sdl.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c
index 7dc3dab32e..911247123f 100644
--- a/arch/sandbox/cpu/sdl.c
+++ b/arch/sandbox/cpu/sdl.c
@@ -127,7 +127,9 @@ int sandbox_sdl_init_display(int width, int height, int 
log2_bpp,
sdl.pitch = sdl.width * sdl.depth / 8;
SDL_Window *screen = SDL_CreateWindow("U-Boot", SDL_WINDOWPOS_UNDEFINED,
  SDL_WINDOWPOS_UNDEFINED,
- sdl.vis_width, sdl.vis_height, 0);
+ sdl.vis_width, sdl.vis_height,
+ SDL_WINDOW_MAXIMIZED |
+ SDL_WINDOW_RESIZABLE);
if (!screen) {
printf("Unable to initialise SDL screen: %s\n",
   SDL_GetError());
--
2.28.0

[PATCH 1/1] video: typo Normlly

[Heinrich Schuchardt]

%s/Normlly/Normally/

Signed-off-by: Heinrich Schuchardt 
---
 drivers/video/console_truetype.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c
index 22b2ea7191..8205413d2a 100644
--- a/drivers/video/console_truetype.c
+++ b/drivers/video/console_truetype.c
@@ -432,7 +432,7 @@ static int console_truetype_backspace(struct udevice *dev)
pos = >pos[--priv->pos_ptr];

/*
-* Figure out the end position for clearing. Normlly it is the current
+* Figure out the end position for clearing. Normally it is the current
 * cursor position, but if we are clearing a character on the previous
 * line, we clear from the end of the line.
 */
--
2.28.0

Re: [BUG] sandbox: './u-boot -l ' fails

[Heinrich Schuchardt]

On 9/29/20 12:19 AM, Simon Glass wrote:
> Hi Heinrich,
>
> On Mon, 28 Sep 2020 at 15:23, Heinrich Schuchardt  wrote:
>>
>> On 9/28/20 3:42 PM, Simon Glass wrote:
>>> Hi Heinrich,
>>>
>>> On Mon, 28 Sep 2020 at 07:30, Heinrich Schuchardt  
>>> wrote:

 On 28.09.20 15:22, Simon Glass wrote:
> Hi Heinrich,
>
> On Mon, 28 Sep 2020 at 05:31, Heinrich Schuchardt  
> wrote:
>>
>> On 28.09.20 06:46, Heinrich Schuchardt wrote:
>>> Am 28. September 2020 06:24:38 MESZ schrieb Simon Glass 
>>> :
 Hi Heinrich,

 On Sat, 19 Sep 2020 at 13:48, Heinrich Schuchardt 
 wrote:
>
> Hello Simon,
>
> when I try to run ./u-boot -l the sandbox stalls. Shouldn't it run
 out
> of the box?
>
> $ ./u-boot -l -d arch/sandbox/dts/sandbox.dtb

 For the record you should be able to use -D to get the same effect as
 your -d above.

>
> U-Boot 2020.10-rc4-00018-g21a10244f9-dirty (Sep 19 2020 - 19:55:39
 +0200)
>
> Model: sandbox
> DRAM:  128 MiB
>
> Warning: host_lo MAC addresses don't match:
> Address in ROM is   26:4b:ca:6c:98:f4
> Address in environment is   00:00:11:22:33:44
>
> Warning: host_virbr0 MAC addresses don't match:
> Address in ROM is   ee:3e:c9:ce:1f:9c
> Address in environment is   00:00:11:22:33:45
>
> Warning: host_docker0 MAC addresses don't match:
> Address in ROM is   c2:85:07:7b:9a:18
> Address in environment is   00:00:11:22:33:46
> WDT:   Not found!
> MMC:
>
> No output after this point.
>
> The problem also exists with U-Boot v2020.07, v2019.10, v2018.11.
>
> CONFIG_SANDBOX_SDL=y
>
> SDL_InitSubSystem() never returns. It is looping somewhere in
 U-Boot's
> __serial_getc(). I wonder how it gets there without returning from
 the
> function.
>
> I compiled SDL2.cpp from
> https://gist.github.com/miguelmartin75/6946310#file-sdl2-cpp-L18
> with
>
> g++ SDL2.cpp -D_REENTRANT -I/usr/include/SDL2 -lSDL2 -lGL -o test
>
> and it runs fine showing an X11 windows with red background.
>
> So there seems to be no general problem with the SDL2 library.

 I hit this myself on another computer and it turned out to be that SDL
 defined getc(), as does U-Boot, and things get confused. At least I
 think it is getc.

 I hacked around with changing the name of getc (I think it was getc)
 in U-Boot and the problem went away.
>>>
>>> Should we include a patched SDL2 with U-Boot for static linking?
>>>
>>
>> I cannot find a symbol getc() nor a reference to it in the SDL
>> repository. getc() is defined in stdio.h.
>>
>> Our getc() takes no argument, while the stdio one wants a FILE *.
>>
>> But changing the U-Boot definition to "int getc(void *)" does not solve
>> the issue.
>
> I just tried it on the machine where it doesn't work:
>
> $ gdb --args /tmp/b/sandbox/u-boot -l -D
> GNU gdb (Debian 9.2-1) 9.2
> Copyright (C) 2020 Free Software Foundation, Inc.
> License GPLv3+: GNU GPL version 3 or later 
> 
> This is free software: you are free to change and redistribute it.
> There is NO WARRANTY, to the extent permitted by law.
> Type "show copying" and "show warranty" for details.
> This GDB was configured as "x86_64-linux-gnu".
> Type "show configuration" for configuration details.
> For bug reporting instructions, please see:
> .
> Find the GDB manual and other documentation resources online at:
> .
>
> For help, type "help".
> Type "apropos word" to search for commands related to "word"...
> Reading symbols from /tmp/b/sandbox/u-boot...
> (gdb) br getc
> Breakpoint 1 at 0x5b6d6: getc. (2 locations)
> (gdb) r
> Starting program: /tmp/b/sandbox/u-boot -l -D
> [Thread debugging using libthread_db enabled]
> Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
>
>
> U-Boot 2020.10-rc5-00196-g0ac83d080a0 (Sep 28 2020 - 07:11:52 -0600)
>
> Model: sandbox
> DRAM:  128 MiB
>
> Warning: host_lo MAC addresses don't match:
> Address in ROM is 1a:34:9b:48:aa:53
> Address in environment is 00:00:11:22:33:44
> WDT:   Not found!
> MMC:
>
> Breakpoint 1, getc () at
> /home/sjg/cosarm/src/third_party/u-boot/files/common/console.c:414
> 414 if (!gd->have_console)
> (gdb) up
> #1  

[PATCH 1/1] common: redefine getc()

[Heinrich Schuchardt]

The sandbox is built with the SDL2 library with invokes the X11 library
which in turn calls getc(). But getc() in glibc is defined as

int getc(FILE *)

This does not match our definition.

int getc(void)

The sandbox crashes when called with parameter -l.

Rename our library symbol to be called _u_boot_getc(). To keep the coding
changes minimal use a define.

Signed-off-by: Heinrich Schuchardt 
---
 include/_exports.h | 2 +-
 include/exports.h  | 2 +-
 include/stdio.h| 2 ++
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/_exports.h b/include/_exports.h
index 1e9ba86108..1da78dea1a 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -8,7 +8,7 @@
 #define EXPORT_FUNC(a, b, c, ...)
 #endif
EXPORT_FUNC(get_version, unsigned long, get_version, void)
-   EXPORT_FUNC(getc, int, getc, void)
+   EXPORT_FUNC(getc, int, _u_boot_getc, void)
EXPORT_FUNC(tstc, int, tstc, void)
EXPORT_FUNC(putc, void, putc, const char)
EXPORT_FUNC(puts, void, puts, const char *)
diff --git a/include/exports.h b/include/exports.h
index b300554091..f982b1b49b 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -20,7 +20,7 @@ void jumptable_init(void);

 /* These are declarations of exported functions available in C code */
 unsigned long get_version(void);
-int  getc(void);
+int  _u_boot_getc(void);
 int  tstc(void);
 void putc(const char);
 void puts(const char*);
diff --git a/include/stdio.h b/include/stdio.h
index aedf374452..a204e06c69 100644
--- a/include/stdio.h
+++ b/include/stdio.h
@@ -4,6 +4,8 @@
 #include 
 #include 

+#define getc _u_boot_getc
+
 /* stdin */
 int getc(void);
 int tstc(void);
--
2.28.0

[PATCH 1/1] sandbox: add missing SDL key scan codes

[Heinrich Schuchardt]

Add missing SDL key scan codes, e.g.

* shift, ctrl, meta, alt
* brace/bracket

Signed-off-by: Heinrich Schuchardt 
---
 arch/sandbox/cpu/sdl.c | 156 +++--
 1 file changed, 89 insertions(+), 67 deletions(-)

diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c
index 6416cab96c..7dc3dab32e 100644
--- a/arch/sandbox/cpu/sdl.c
+++ b/arch/sandbox/cpu/sdl.c
@@ -172,33 +172,7 @@ int sandbox_sdl_sync(void *lcd_base)
 }

 static const unsigned short sdl_to_keycode[SDL_NUM_SCANCODES] = {
-   [SDL_SCANCODE_A]= KEY_A,
-   [SDL_SCANCODE_B]= KEY_B,
-   [SDL_SCANCODE_C]= KEY_C,
-   [SDL_SCANCODE_D]= KEY_D,
-   [SDL_SCANCODE_E]= KEY_E,
-   [SDL_SCANCODE_F]= KEY_F,
-   [SDL_SCANCODE_G]= KEY_G,
-   [SDL_SCANCODE_H]= KEY_H,
-   [SDL_SCANCODE_I]= KEY_I,
-   [SDL_SCANCODE_J]= KEY_J,
-   [SDL_SCANCODE_K]= KEY_K,
-   [SDL_SCANCODE_L]= KEY_L,
-   [SDL_SCANCODE_M]= KEY_M,
-   [SDL_SCANCODE_N]= KEY_N,
-   [SDL_SCANCODE_O]= KEY_O,
-   [SDL_SCANCODE_P]= KEY_P,
-   [SDL_SCANCODE_Q]= KEY_Q,
-   [SDL_SCANCODE_R]= KEY_R,
-   [SDL_SCANCODE_S]= KEY_S,
-   [SDL_SCANCODE_T]= KEY_T,
-   [SDL_SCANCODE_U]= KEY_U,
-   [SDL_SCANCODE_V]= KEY_V,
-   [SDL_SCANCODE_W]= KEY_W,
-   [SDL_SCANCODE_X]= KEY_X,
-   [SDL_SCANCODE_Y]= KEY_Y,
-   [SDL_SCANCODE_Z]= KEY_Z,
-
+   [SDL_SCANCODE_ESCAPE]   = KEY_ESC,
[SDL_SCANCODE_1]= KEY_1,
[SDL_SCANCODE_2]= KEY_2,
[SDL_SCANCODE_3]= KEY_3,
@@ -209,25 +183,53 @@ static const unsigned short 
sdl_to_keycode[SDL_NUM_SCANCODES] = {
[SDL_SCANCODE_8]= KEY_8,
[SDL_SCANCODE_9]= KEY_9,
[SDL_SCANCODE_0]= KEY_0,
-
-   [SDL_SCANCODE_RETURN]   = KEY_ENTER,
-   [SDL_SCANCODE_ESCAPE]   = KEY_ESC,
-   [SDL_SCANCODE_BACKSPACE]= KEY_BACKSPACE,
-   [SDL_SCANCODE_TAB]  = KEY_TAB,
-   [SDL_SCANCODE_SPACE]= KEY_SPACE,
-
[SDL_SCANCODE_MINUS]= KEY_MINUS,
[SDL_SCANCODE_EQUALS]   = KEY_EQUAL,
-   [SDL_SCANCODE_BACKSLASH]= KEY_BACKSLASH,
+   [SDL_SCANCODE_BACKSPACE]= KEY_BACKSPACE,
+   [SDL_SCANCODE_TAB]  = KEY_TAB,
+   [SDL_SCANCODE_Q]= KEY_Q,
+   [SDL_SCANCODE_W]= KEY_W,
+   [SDL_SCANCODE_E]= KEY_E,
+   [SDL_SCANCODE_R]= KEY_R,
+   [SDL_SCANCODE_T]= KEY_T,
+   [SDL_SCANCODE_Y]= KEY_Y,
+   [SDL_SCANCODE_U]= KEY_U,
+   [SDL_SCANCODE_I]= KEY_I,
+   [SDL_SCANCODE_O]= KEY_O,
+   [SDL_SCANCODE_P]= KEY_P,
+   [SDL_SCANCODE_LEFTBRACKET]  = KEY_LEFTBRACE,
+   [SDL_SCANCODE_RIGHTBRACKET] = KEY_RIGHTBRACE,
+   [SDL_SCANCODE_RETURN]   = KEY_ENTER,
+   [SDL_SCANCODE_LCTRL]= KEY_LEFTCTRL,
+   [SDL_SCANCODE_A]= KEY_A,
+   [SDL_SCANCODE_S]= KEY_S,
+   [SDL_SCANCODE_D]= KEY_D,
+   [SDL_SCANCODE_F]= KEY_F,
+   [SDL_SCANCODE_G]= KEY_G,
+   [SDL_SCANCODE_H]= KEY_H,
+   [SDL_SCANCODE_J]= KEY_J,
+   [SDL_SCANCODE_K]= KEY_K,
+   [SDL_SCANCODE_L]= KEY_L,
[SDL_SCANCODE_SEMICOLON]= KEY_SEMICOLON,
[SDL_SCANCODE_APOSTROPHE]   = KEY_APOSTROPHE,
[SDL_SCANCODE_GRAVE]= KEY_GRAVE,
+   [SDL_SCANCODE_LSHIFT]   = KEY_LEFTSHIFT,
+   [SDL_SCANCODE_BACKSLASH]= KEY_BACKSLASH,
+   [SDL_SCANCODE_Z]= KEY_Z,
+   [SDL_SCANCODE_X]= KEY_X,
+   [SDL_SCANCODE_C]= KEY_C,
+   [SDL_SCANCODE_V]= KEY_V,
+   [SDL_SCANCODE_B]= KEY_B,
+   [SDL_SCANCODE_N]= KEY_N,
+   [SDL_SCANCODE_M]= KEY_M,
[SDL_SCANCODE_COMMA]= KEY_COMMA,
[SDL_SCANCODE_PERIOD]   = KEY_DOT,
[SDL_SCANCODE_SLASH]= KEY_SLASH,
-
+   [SDL_SCANCODE_RSHIFT]   = KEY_RIGHTSHIFT,
+   [SDL_SCANCODE_KP_MULTIPLY] = KEY_KPASTERISK,
+   [SDL_SCANCODE_LALT] = KEY_LEFTALT,
+   [SDL_SCANCODE_SPACE]= KEY_SPACE,
[SDL_SCANCODE_CAPSLOCK] = KEY_CAPSLOCK,
-
[SDL_SCANCODE_F1]   = KEY_F1,
[SDL_SCANCODE_F2]   = KEY_F2,
[SDL_SCANCODE_F3]   = KEY_F3,
@@ -238,45 +240,65 @@ static const unsigned short 
sdl_to_keycode[SDL_NUM_SCANCODES] = {
[SDL_SCANCODE_F8]   = KEY_F8,
[SDL_SCANCODE_F9]   = KEY_F9,
[SDL_SCANCODE_F10]  = KEY_F10,
-   [SDL_SCANCODE_F11]  = KEY_F11,
-   [SDL_SCANCODE_F12]  = KEY_F12,
-
-   [SDL_SCANCODE_PRINTSCREEN]  = KEY_PRINT,
-   [SDL_SCANCODE_SCROLLLOCK]   = KEY_SCROLLLOCK,
-   [SDL_SCANCODE_PAUSE]= KEY_PAUSE,
-   [SDL_SCANCODE_INSERT]   = 

Re: [BUG] sandbox: './u-boot -l ' fails

[Simon Glass]

Hi Heinrich,

On Mon, 28 Sep 2020 at 15:23, Heinrich Schuchardt  wrote:
>
> On 9/28/20 3:42 PM, Simon Glass wrote:
> > Hi Heinrich,
> >
> > On Mon, 28 Sep 2020 at 07:30, Heinrich Schuchardt  
> > wrote:
> >>
> >> On 28.09.20 15:22, Simon Glass wrote:
> >>> Hi Heinrich,
> >>>
> >>> On Mon, 28 Sep 2020 at 05:31, Heinrich Schuchardt  
> >>> wrote:
> 
>  On 28.09.20 06:46, Heinrich Schuchardt wrote:
> > Am 28. September 2020 06:24:38 MESZ schrieb Simon Glass 
> > :
> >> Hi Heinrich,
> >>
> >> On Sat, 19 Sep 2020 at 13:48, Heinrich Schuchardt 
> >> wrote:
> >>>
> >>> Hello Simon,
> >>>
> >>> when I try to run ./u-boot -l the sandbox stalls. Shouldn't it run
> >> out
> >>> of the box?
> >>>
> >>> $ ./u-boot -l -d arch/sandbox/dts/sandbox.dtb
> >>
> >> For the record you should be able to use -D to get the same effect as
> >> your -d above.
> >>
> >>>
> >>> U-Boot 2020.10-rc4-00018-g21a10244f9-dirty (Sep 19 2020 - 19:55:39
> >> +0200)
> >>>
> >>> Model: sandbox
> >>> DRAM:  128 MiB
> >>>
> >>> Warning: host_lo MAC addresses don't match:
> >>> Address in ROM is   26:4b:ca:6c:98:f4
> >>> Address in environment is   00:00:11:22:33:44
> >>>
> >>> Warning: host_virbr0 MAC addresses don't match:
> >>> Address in ROM is   ee:3e:c9:ce:1f:9c
> >>> Address in environment is   00:00:11:22:33:45
> >>>
> >>> Warning: host_docker0 MAC addresses don't match:
> >>> Address in ROM is   c2:85:07:7b:9a:18
> >>> Address in environment is   00:00:11:22:33:46
> >>> WDT:   Not found!
> >>> MMC:
> >>>
> >>> No output after this point.
> >>>
> >>> The problem also exists with U-Boot v2020.07, v2019.10, v2018.11.
> >>>
> >>> CONFIG_SANDBOX_SDL=y
> >>>
> >>> SDL_InitSubSystem() never returns. It is looping somewhere in
> >> U-Boot's
> >>> __serial_getc(). I wonder how it gets there without returning from
> >> the
> >>> function.
> >>>
> >>> I compiled SDL2.cpp from
> >>> https://gist.github.com/miguelmartin75/6946310#file-sdl2-cpp-L18
> >>> with
> >>>
> >>> g++ SDL2.cpp -D_REENTRANT -I/usr/include/SDL2 -lSDL2 -lGL -o test
> >>>
> >>> and it runs fine showing an X11 windows with red background.
> >>>
> >>> So there seems to be no general problem with the SDL2 library.
> >>
> >> I hit this myself on another computer and it turned out to be that SDL
> >> defined getc(), as does U-Boot, and things get confused. At least I
> >> think it is getc.
> >>
> >> I hacked around with changing the name of getc (I think it was getc)
> >> in U-Boot and the problem went away.
> >
> > Should we include a patched SDL2 with U-Boot for static linking?
> >
> 
>  I cannot find a symbol getc() nor a reference to it in the SDL
>  repository. getc() is defined in stdio.h.
> 
>  Our getc() takes no argument, while the stdio one wants a FILE *.
> 
>  But changing the U-Boot definition to "int getc(void *)" does not solve
>  the issue.
> >>>
> >>> I just tried it on the machine where it doesn't work:
> >>>
> >>> $ gdb --args /tmp/b/sandbox/u-boot -l -D
> >>> GNU gdb (Debian 9.2-1) 9.2
> >>> Copyright (C) 2020 Free Software Foundation, Inc.
> >>> License GPLv3+: GNU GPL version 3 or later 
> >>> 
> >>> This is free software: you are free to change and redistribute it.
> >>> There is NO WARRANTY, to the extent permitted by law.
> >>> Type "show copying" and "show warranty" for details.
> >>> This GDB was configured as "x86_64-linux-gnu".
> >>> Type "show configuration" for configuration details.
> >>> For bug reporting instructions, please see:
> >>> .
> >>> Find the GDB manual and other documentation resources online at:
> >>> .
> >>>
> >>> For help, type "help".
> >>> Type "apropos word" to search for commands related to "word"...
> >>> Reading symbols from /tmp/b/sandbox/u-boot...
> >>> (gdb) br getc
> >>> Breakpoint 1 at 0x5b6d6: getc. (2 locations)
> >>> (gdb) r
> >>> Starting program: /tmp/b/sandbox/u-boot -l -D
> >>> [Thread debugging using libthread_db enabled]
> >>> Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
> >>>
> >>>
> >>> U-Boot 2020.10-rc5-00196-g0ac83d080a0 (Sep 28 2020 - 07:11:52 -0600)
> >>>
> >>> Model: sandbox
> >>> DRAM:  128 MiB
> >>>
> >>> Warning: host_lo MAC addresses don't match:
> >>> Address in ROM is 1a:34:9b:48:aa:53
> >>> Address in environment is 00:00:11:22:33:44
> >>> WDT:   Not found!
> >>> MMC:
> >>>
> >>> Breakpoint 1, getc () at
> >>> /home/sjg/cosarm/src/third_party/u-boot/files/common/console.c:414
> >>> 414 if (!gd->have_console)
> >>> (gdb) up
> >>> #1  0x77914d48 in ?? () from 

Re: What is the status of IMX8MM USB support?

[Tim Harvey]

On Thu, Sep 24, 2020 at 10:49 PM Peng Fan  wrote:
>
> Hi Tim,
>
> > Subject: What is the status of IMX8MM USB support?
> >
> > Greetings,
> >
> > I have not seen any activity to enable USB support for the IMX8MM. Is
> > anyone working on this? Last I knew the holdup had to do with a
> > power-domain driver.
>
> For U-Boot, although I am trying to clean up NXP usb patches, but have
> not find time to enable i.MX8MM.
>
> For Kernel, I think it is still stuck in power domain part.
> Let's see whether we could move to SCMI again considerting power domain
> notified patches from Uff are under reviewing.
>

Peng,

Thanks for the update. Seeing IMX8MM support would be very helpful as
that would allow SDP support for mainline U-Boot to aid in board
bringup.

Yes, for kernel it appears to just be the power domain as if that gets
enabled the existing drivers upstream work fine.

Tim

Re: [BUG] sandbox: './u-boot -l ' fails

[Heinrich Schuchardt]

On 9/28/20 3:42 PM, Simon Glass wrote:
> Hi Heinrich,
>
> On Mon, 28 Sep 2020 at 07:30, Heinrich Schuchardt  wrote:
>>
>> On 28.09.20 15:22, Simon Glass wrote:
>>> Hi Heinrich,
>>>
>>> On Mon, 28 Sep 2020 at 05:31, Heinrich Schuchardt  
>>> wrote:

 On 28.09.20 06:46, Heinrich Schuchardt wrote:
> Am 28. September 2020 06:24:38 MESZ schrieb Simon Glass 
> :
>> Hi Heinrich,
>>
>> On Sat, 19 Sep 2020 at 13:48, Heinrich Schuchardt 
>> wrote:
>>>
>>> Hello Simon,
>>>
>>> when I try to run ./u-boot -l the sandbox stalls. Shouldn't it run
>> out
>>> of the box?
>>>
>>> $ ./u-boot -l -d arch/sandbox/dts/sandbox.dtb
>>
>> For the record you should be able to use -D to get the same effect as
>> your -d above.
>>
>>>
>>> U-Boot 2020.10-rc4-00018-g21a10244f9-dirty (Sep 19 2020 - 19:55:39
>> +0200)
>>>
>>> Model: sandbox
>>> DRAM:  128 MiB
>>>
>>> Warning: host_lo MAC addresses don't match:
>>> Address in ROM is   26:4b:ca:6c:98:f4
>>> Address in environment is   00:00:11:22:33:44
>>>
>>> Warning: host_virbr0 MAC addresses don't match:
>>> Address in ROM is   ee:3e:c9:ce:1f:9c
>>> Address in environment is   00:00:11:22:33:45
>>>
>>> Warning: host_docker0 MAC addresses don't match:
>>> Address in ROM is   c2:85:07:7b:9a:18
>>> Address in environment is   00:00:11:22:33:46
>>> WDT:   Not found!
>>> MMC:
>>>
>>> No output after this point.
>>>
>>> The problem also exists with U-Boot v2020.07, v2019.10, v2018.11.
>>>
>>> CONFIG_SANDBOX_SDL=y
>>>
>>> SDL_InitSubSystem() never returns. It is looping somewhere in
>> U-Boot's
>>> __serial_getc(). I wonder how it gets there without returning from
>> the
>>> function.
>>>
>>> I compiled SDL2.cpp from
>>> https://gist.github.com/miguelmartin75/6946310#file-sdl2-cpp-L18
>>> with
>>>
>>> g++ SDL2.cpp -D_REENTRANT -I/usr/include/SDL2 -lSDL2 -lGL -o test
>>>
>>> and it runs fine showing an X11 windows with red background.
>>>
>>> So there seems to be no general problem with the SDL2 library.
>>
>> I hit this myself on another computer and it turned out to be that SDL
>> defined getc(), as does U-Boot, and things get confused. At least I
>> think it is getc.
>>
>> I hacked around with changing the name of getc (I think it was getc)
>> in U-Boot and the problem went away.
>
> Should we include a patched SDL2 with U-Boot for static linking?
>

 I cannot find a symbol getc() nor a reference to it in the SDL
 repository. getc() is defined in stdio.h.

 Our getc() takes no argument, while the stdio one wants a FILE *.

 But changing the U-Boot definition to "int getc(void *)" does not solve
 the issue.
>>>
>>> I just tried it on the machine where it doesn't work:
>>>
>>> $ gdb --args /tmp/b/sandbox/u-boot -l -D
>>> GNU gdb (Debian 9.2-1) 9.2
>>> Copyright (C) 2020 Free Software Foundation, Inc.
>>> License GPLv3+: GNU GPL version 3 or later 
>>> 
>>> This is free software: you are free to change and redistribute it.
>>> There is NO WARRANTY, to the extent permitted by law.
>>> Type "show copying" and "show warranty" for details.
>>> This GDB was configured as "x86_64-linux-gnu".
>>> Type "show configuration" for configuration details.
>>> For bug reporting instructions, please see:
>>> .
>>> Find the GDB manual and other documentation resources online at:
>>> .
>>>
>>> For help, type "help".
>>> Type "apropos word" to search for commands related to "word"...
>>> Reading symbols from /tmp/b/sandbox/u-boot...
>>> (gdb) br getc
>>> Breakpoint 1 at 0x5b6d6: getc. (2 locations)
>>> (gdb) r
>>> Starting program: /tmp/b/sandbox/u-boot -l -D
>>> [Thread debugging using libthread_db enabled]
>>> Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
>>>
>>>
>>> U-Boot 2020.10-rc5-00196-g0ac83d080a0 (Sep 28 2020 - 07:11:52 -0600)
>>>
>>> Model: sandbox
>>> DRAM:  128 MiB
>>>
>>> Warning: host_lo MAC addresses don't match:
>>> Address in ROM is 1a:34:9b:48:aa:53
>>> Address in environment is 00:00:11:22:33:44
>>> WDT:   Not found!
>>> MMC:
>>>
>>> Breakpoint 1, getc () at
>>> /home/sjg/cosarm/src/third_party/u-boot/files/common/console.c:414
>>> 414 if (!gd->have_console)
>>> (gdb) up
>>> #1  0x77914d48 in ?? () from /lib/x86_64-linux-gnu/libX11.so.6
>>> (gdb)
>>>
>>>
>>> So it seems that it is libX11 causing the problem.
>>>
>>> I don't think the best fix is to remove getc() from that library,
>>> although I do wonder if it is a bug. Renaming the symbol in U-Boot
>>> with #define (only on sandbox) might be one option.
>>>
>>> Regards,
>>> Simon
>>>
>>
>> #define getc _uboot_getc
>>
>> 

[PATCH 1/3] sunxi: dts: OrangePi Zero: Add SPI aliases to make bus usable with u-boot.

[Michal Suchanek]

The u-boot code relies on aliases to assign bus number.

Signed-off-by: Michal Suchanek 
---
 arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts 
b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
index f19ed981da..090570148e 100644
--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -59,6 +59,8 @@
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet0 = 
ethernet1 = 
+   spi0 = 
+   spi1 = 
};
 
chosen {
-- 
2.28.0

[PATCH 3/3] sunxi: Enable SPI support on Orange Pi Zero

[Michal Suchanek]

Enable support for SPI flash and the sf command.

Signed-off-by: Michal Suchanek 
---
 configs/orangepi_zero_defconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
index 998c95d151..1087baece1 100644
--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -8,6 +8,14 @@ CONFIG_SPL_SPI_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
-- 
2.28.0

[PATCH 2/3] sunxi: dts: OrangePi Zero: Enable SPI flash.

[Michal Suchanek]

This flash is optional but new boards do have it, and on boards that
don't the pins are routed to the flash pads anyway.

Signed-off-by: Michal Suchanek 
---
 arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts 
b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
index 090570148e..dc3d006010 100644
--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -165,8 +165,8 @@
 };
 
  {
-   /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */
-   status = "disabled";
+   /* Enable SPI NOR by default: it optional on Orange Pi Zero boards */
+   status = "okay";
 
flash@0 {
#address-cells = <1>;
-- 
2.28.0

[PATCH] drivers: serial: probe all uart devices

[Vabhav Sharma]

From: Vabhav Sharma 

U-Boot DM model probe only single device at a time
which is enabled and configured using device tree
or platform data method.

PL011 UART IP is SBSA compliant and firmware does the
serial port set-up, initialization and let the kernel use
UART port for sending and receiving characters.

Normally software talk to one serial port time but some
LayerScape platform require all the UART devices enabled
in Linux for various use case.

Adding support to probe all enabled serial devices like SBSA
compliant PL011 UART ports probe and initialization by firmware.

Signed-off-by: Vabhav Sharma 
---
 drivers/serial/Kconfig | 17 +
 drivers/serial/serial-uclass.c | 30 ++
 2 files changed, 47 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e344677..b2e30f1 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -134,6 +134,23 @@ config SERIAL_SEARCH_ALL
 
  If unsure, say N.
 
+config SERIAL_PROBE_ALL
+   bool "Probe all available serial devices"
+   depends on DM_SERIAL
+   default n
+   help
+ The serial subsystem only probe for single serial device,
+ but does not probe for other remaining serial devices.
+ With this option set,we make probing and searching for
+ all available devices optional.
+ Normally, U-Boot talk to one serial port at a time but SBSA
+ compliant UART devices like PL011 require initialization
+ by firmware and let the kernel use serial port for sending
+ and receiving the characters.
+
+ If probing is not required for all remaining available
+ devices other than default current console device, say N.
+
 config SPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in SPL"
depends on DM_SERIAL && SPL_DM
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 0027625..9b2fcb0 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -86,6 +86,11 @@ static void serial_find_console_or_panic(void)
uclass_first_device(UCLASS_SERIAL, );
if (dev) {
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif
return;
}
} else if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
@@ -96,11 +101,21 @@ static void serial_find_console_or_panic(void)
if (np && !uclass_get_device_by_ofnode(UCLASS_SERIAL,
np_to_ofnode(np), )) {
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif
return;
}
} else {
if (!serial_check_stdout(blob, )) {
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif
return;
}
}
@@ -125,6 +140,11 @@ static void serial_find_console_or_panic(void)
!uclass_get_device(UCLASS_SERIAL, INDEX, )) {
if (dev->flags & DM_FLAG_ACTIVATED) {
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif
return;
}
}
@@ -136,6 +156,11 @@ static void serial_find_console_or_panic(void)
if (!ret) {
/* Device did succeed probing */
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+   ;
+#endif
return;
}
}
@@ -144,6 +169,11 @@ static void serial_find_console_or_panic(void)
!uclass_get_device(UCLASS_SERIAL, INDEX, ) ||
(!uclass_first_device(UCLASS_SERIAL, ) && dev)) {
gd->cur_serial_dev = dev;
+#ifdef CONFIG_SERIAL_PROBE_ALL
+   /* Scanning uclass to probe all devices */
+   for (; dev; uclass_next_device())
+ 

[PATCH] spi: mvebu_a3700_spi: add support for cs-gpios

[George Hilliard]

The device tree has a way to specify GPIO lines as chip selects.  From
the binding docs:

So if for example the controller has 2 CS lines, and the cs-gpios
property looks like this:

cs-gpios = < 0 0> <0> < 1 0> < 2 0>;

Then it should be configured so that num_chipselect = 4 with the
following mapping:

cs0 :  0 0
cs1 : native
cs2 :  1 0
cs3 :  2 0

Add support for this, while retaining backward-compatibility with
existing device trees; the driver will preserve existing behavior if a
cs-gpios list is not given, or if a particular line is specified as <0>
(native).

This implementation is inspired by similar implementations in
neighboring drivers for other platforms: atmega, mxc, etc.

Signed-off-by: George Hilliard 
---
 drivers/spi/mvebu_a3700_spi.c | 50 ++-
 1 file changed, 44 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index e860b9ec64..95be590a68 100644
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -15,6 +15,9 @@
 #include 
 #include 
 #include 
+#if CONFIG_IS_ENABLED(DM_GPIO)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MVEBU_SPI_A3700_SPI_EN_0   BIT(16)
 #define MVEBU_SPI_A3700_CLK_PRESCALE_MASK  0x1f
 
+#define MAX_CS_COUNT   4
 
 /* SPI registers */
 struct spi_reg {
@@ -39,16 +43,29 @@ struct spi_reg {
 struct mvebu_spi_platdata {
struct spi_reg *spireg;
struct clk clk;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+   struct gpio_desc cs_gpios[MAX_CS_COUNT];
+#endif
 };
 
-static void spi_cs_activate(struct spi_reg *reg, int cs)
+static void spi_cs_activate(struct mvebu_spi_platdata *plat, int cs)
 {
-   setbits_le32(>ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
+#if CONFIG_IS_ENABLED(DM_GPIO)
+   if (dm_gpio_is_valid(>cs_gpios[cs]))
+   dm_gpio_set_value(>cs_gpios[cs], 1);
+   else
+#endif
+   setbits_le32(>spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << 
cs);
 }
 
-static void spi_cs_deactivate(struct spi_reg *reg, int cs)
+static void spi_cs_deactivate(struct mvebu_spi_platdata *plat, int cs)
 {
-   clrbits_le32(>ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
+#if CONFIG_IS_ENABLED(DM_GPIO)
+   if (dm_gpio_is_valid(>cs_gpios[cs]))
+   dm_gpio_set_value(>cs_gpios[cs], 0);
+   else
+#endif
+   clrbits_le32(>spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << 
cs);
 }
 
 /**
@@ -150,7 +167,7 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
/* Activate CS */
if (flags & SPI_XFER_BEGIN) {
debug("SPI: activate cs.\n");
-   spi_cs_activate(reg, spi_chip_select(dev));
+   spi_cs_activate(plat, spi_chip_select(dev));
}
 
/* Send and/or receive */
@@ -169,7 +186,7 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
return ret;
 
debug("SPI: deactivate cs.\n");
-   spi_cs_deactivate(reg, spi_chip_select(dev));
+   spi_cs_deactivate(plat, spi_chip_select(dev));
}
 
return 0;
@@ -247,6 +264,27 @@ static int mvebu_spi_probe(struct udevice *bus)
 
writel(data, >cfg);
 
+   /* Set up CS GPIOs in device tree, if any */
+#if CONFIG_IS_ENABLED(DM_GPIO)
+   if (gpio_get_list_count(bus, "cs-gpios") > 0) {
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
+   ret = gpio_request_by_name(bus, "cs-gpios", i, 
>cs_gpios[i], 0);
+   if (ret < 0 || !dm_gpio_is_valid(>cs_gpios[i]))
+   // Use the native CS function for this line
+   continue;
+
+   ret = dm_gpio_set_dir_flags(>cs_gpios[i],
+   GPIOD_IS_OUT | 
GPIOD_ACTIVE_LOW);
+   if (ret) {
+   dev_err(bus, "Setting cs %d error\n", i);
+   return ret;
+   }
+   }
+   }
+#endif
+
return 0;
 }
 
-- 
2.23.3

Re: [PATCH 1/2] efi: Add dependency on M-mode for RISC-V

[Sean Anderson]

On 9/28/20 2:24 PM, Heinrich Schuchardt wrote:
> On 28.09.20 19:15, Sean Anderson wrote:
>> On 9/28/20 12:27 PM, Heinrich Schuchardt wrote:
>>> On 28.09.20 18:08, Sean Anderson wrote:
 >From section 2.3.7 of the UEFI specification:

> RISC-V UEFI will only be executed in machine mode. The machine mode has
> the highest privilege and this mode is the only mandatory privilege level
> for RISC-V platforms; all other privilege levels are optional depending
> on the platform requirements. Machine mode is the first mode entered at
> the power-on reset. This level is used in UEFI for low-level access to a
> hardware platform.

 Signed-off-by: Sean Anderson 
 ---

  lib/efi_loader/Kconfig | 2 ++
  1 file changed, 2 insertions(+)

 diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
 index bad1a29ba8..2197c84bf3 100644
 --- a/lib/efi_loader/Kconfig
 +++ b/lib/efi_loader/Kconfig
 @@ -10,6 +10,8 @@ config EFI_LOADER
depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
 +  # RISC-V UEFI must run in machine mode
 +  depends on !RISCV || RISCV_M_MODE
default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
select LIB_UUID
select HAVE_BLOCK_DEVICE

>>>
>>> Hello Sean,
>>>
>>> the specification is wrong. A change request has been made to correct
>>> the specification. We should not change U-Boot here.
>>>
>>> See the discussion in this thread:
>>> https://lists.linaro.org/pipermail/boot-architecture/2020-September/001481.html
>>>
>>> Best regards
>>>
>>> Heinrich
>>>
>>
>> Thanks for linking that. I'm glad some of these issues are being addressed. 
>> However, I am concerned about your suggestion
>>
>>> * Don't trust the values of tp and gp when entered
>>>   from the payloads world.
>>
>> Because tp *must* be trusted in S-Mode...
>>
>> Of course, all this could be averted by adding an sbi_get_mhartid function...
> 
> I thought only the secondary hart uses tp in U-Boot.
> 
> Best regards
> 
> Heinrich
> 

So UEFI is only ever ran on a single hart? I thought one of the
advantages of UEFI was that it could initialize devices in parallel.

--Sean

Re: [PATCH 1/2] efi: Add dependency on M-mode for RISC-V

[Heinrich Schuchardt]

On 28.09.20 19:15, Sean Anderson wrote:
> On 9/28/20 12:27 PM, Heinrich Schuchardt wrote:
>> On 28.09.20 18:08, Sean Anderson wrote:
>>> >From section 2.3.7 of the UEFI specification:
>>>
 RISC-V UEFI will only be executed in machine mode. The machine mode has
 the highest privilege and this mode is the only mandatory privilege level
 for RISC-V platforms; all other privilege levels are optional depending
 on the platform requirements. Machine mode is the first mode entered at
 the power-on reset. This level is used in UEFI for low-level access to a
 hardware platform.
>>>
>>> Signed-off-by: Sean Anderson 
>>> ---
>>>
>>>  lib/efi_loader/Kconfig | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
>>> index bad1a29ba8..2197c84bf3 100644
>>> --- a/lib/efi_loader/Kconfig
>>> +++ b/lib/efi_loader/Kconfig
>>> @@ -10,6 +10,8 @@ config EFI_LOADER
>>> depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
>>> # We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
>>> depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
>>> +   # RISC-V UEFI must run in machine mode
>>> +   depends on !RISCV || RISCV_M_MODE
>>> default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
>>> select LIB_UUID
>>> select HAVE_BLOCK_DEVICE
>>>
>>
>> Hello Sean,
>>
>> the specification is wrong. A change request has been made to correct
>> the specification. We should not change U-Boot here.
>>
>> See the discussion in this thread:
>> https://lists.linaro.org/pipermail/boot-architecture/2020-September/001481.html
>>
>> Best regards
>>
>> Heinrich
>>
>
> Thanks for linking that. I'm glad some of these issues are being addressed. 
> However, I am concerned about your suggestion
>
>> * Don't trust the values of tp and gp when entered
>>   from the payloads world.
>
> Because tp *must* be trusted in S-Mode...
>
> Of course, all this could be averted by adding an sbi_get_mhartid function...

I thought only the secondary hart uses tp in U-Boot.

Best regards

Heinrich

Re: [PATCH V2] net: smc911x: Automatically Update ethaddr with MAC

[Joe Hershberger]

On Tue, Aug 18, 2020 at 8:19 AM Adam Ford  wrote:
>
> The ethernet controller can read the MAC from EEPROM and display it,
> but if ethaddr is not set, the ethernet is still unavailable.
>
> This patch checks will automatically set the MAC address if it has
> not already been set.
>
> Signed-off-by: Adam Ford 

Acked-by: Joe Hershberger 

Re: [patch 0/8] RFC: Pinebook pro EDP support

[Alper Nebi Yasak]

On 28/09/2020 09:41, Arnaud Patard (Rtp) wrote:
> Here, it's set to 1920x1080, and I have CONFIG_DISPLAY_ROCKCHIP_HDMI
> disabled, since there's no HDMI output on the PBP. Can you try with the
> screen size set to the one of your panel and disable the HDMI output ?
> I suspect it won't change anything, but worth trying.

Disabling DISPLAY_ROCKCHIP_HDMI (and those other than EDP) didn't change
anything with 2400x1600.

(What I was saying is if someone in the future enables it on PBP, the
eDP would likely break; but maybe that already happens with the existing
code in non-rk3399 devices. A minor issue, though.)

> I see that you've added the needed rockchip,panel properties, so it's
> possible it's related to the driver but I'm surprised that the
> blacklight turns off. iirc, the driver is only turning it on.

FWIW, commenting out panel_enable_backlight() in rk_edp.c or adding a
panel_set_backlight() after that call didn't get the backlight to stop
turning off or get it turned on before my loop in board_late_init().
Weird.

> Some logs would be nice. If USB is working or if the laptop has
> ethernet, maybe you could try netconsole (doc/README.NetConsole) with
> CONSOLE_MUX. I've not used that for ages, but there's no reason for it
> to be broken.

It doesn't have ethernet, I don't think USB works either -- assuming you
mean I'd use a USB-to-Ethernet adapter.

> btw, I'm not sure what's the current practice in uboot m-l, but maybe we
> can go on debugging your issue off-list ?

Sure. At least, I guess most of it would be spam-ish to the people
already in Cc.

Re: [PATCH 1/2] efi: Add dependency on M-mode for RISC-V

[Sean Anderson]

On 9/28/20 12:27 PM, Heinrich Schuchardt wrote:
> On 28.09.20 18:08, Sean Anderson wrote:
>> >From section 2.3.7 of the UEFI specification:
>>
>>> RISC-V UEFI will only be executed in machine mode. The machine mode has
>>> the highest privilege and this mode is the only mandatory privilege level
>>> for RISC-V platforms; all other privilege levels are optional depending
>>> on the platform requirements. Machine mode is the first mode entered at
>>> the power-on reset. This level is used in UEFI for low-level access to a
>>> hardware platform.
>>
>> Signed-off-by: Sean Anderson 
>> ---
>>
>>  lib/efi_loader/Kconfig | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
>> index bad1a29ba8..2197c84bf3 100644
>> --- a/lib/efi_loader/Kconfig
>> +++ b/lib/efi_loader/Kconfig
>> @@ -10,6 +10,8 @@ config EFI_LOADER
>>  depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
>>  # We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
>>  depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
>> +# RISC-V UEFI must run in machine mode
>> +depends on !RISCV || RISCV_M_MODE
>>  default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
>>  select LIB_UUID
>>  select HAVE_BLOCK_DEVICE
>>
> 
> Hello Sean,
> 
> the specification is wrong. A change request has been made to correct
> the specification. We should not change U-Boot here.
> 
> See the discussion in this thread:
> https://lists.linaro.org/pipermail/boot-architecture/2020-September/001481.html
> 
> Best regards
> 
> Heinrich
> 

Thanks for linking that. I'm glad some of these issues are being addressed. 
However, I am concerned about your suggestion

> * Don't trust the values of tp and gp when entered
>   from the payloads world.

Because tp *must* be trusted in S-Mode...

Of course, all this could be averted by adding an sbi_get_mhartid function...

--Sean

Re: [PATCH 2/2] efi: Fix typo in documentation

[Heinrich Schuchardt]

On 28.09.20 18:08, Sean Anderson wrote:
> There is an extra space.
>
> Signed-off-by: Sean Anderson 
> ---
>
>  lib/efi_selftest/efi_selftest_set_virtual_address_map.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/efi_selftest/efi_selftest_set_virtual_address_map.c 
> b/lib/efi_selftest/efi_selftest_set_virtual_address_map.c
> index a4e5a50f63..b097a81136 100644
> --- a/lib/efi_selftest/efi_selftest_set_virtual_address_map.c
> +++ b/lib/efi_selftest/efi_selftest_set_virtual_address_map.c
> @@ -23,7 +23,7 @@ static u32 notify_call_count;
>  static bool convert_pointer_failed;
>
>  /**
> - * notify () - notification function
> + * notify() - notification function
>   *
>   * This function is called when the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event
>   * occurs. The correct output of ConvertPointer() is checked.
>

Reviewed-by: Heinrich Schuchardt 

Re: [PATCH 1/2] efi: Add dependency on M-mode for RISC-V

[Heinrich Schuchardt]

On 28.09.20 18:08, Sean Anderson wrote:
>>From section 2.3.7 of the UEFI specification:
>
>> RISC-V UEFI will only be executed in machine mode. The machine mode has
>> the highest privilege and this mode is the only mandatory privilege level
>> for RISC-V platforms; all other privilege levels are optional depending
>> on the platform requirements. Machine mode is the first mode entered at
>> the power-on reset. This level is used in UEFI for low-level access to a
>> hardware platform.
>
> Signed-off-by: Sean Anderson 
> ---
>
>  lib/efi_loader/Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> index bad1a29ba8..2197c84bf3 100644
> --- a/lib/efi_loader/Kconfig
> +++ b/lib/efi_loader/Kconfig
> @@ -10,6 +10,8 @@ config EFI_LOADER
>   depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
>   # We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
>   depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
> + # RISC-V UEFI must run in machine mode
> + depends on !RISCV || RISCV_M_MODE
>   default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
>   select LIB_UUID
>   select HAVE_BLOCK_DEVICE
>

Hello Sean,

the specification is wrong. A change request has been made to correct
the specification. We should not change U-Boot here.

See the discussion in this thread:
https://lists.linaro.org/pipermail/boot-architecture/2020-September/001481.html

Best regards

Heinrich

[PATCH 2/2] efi: Fix typo in documentation

[Sean Anderson]

There is an extra space.

Signed-off-by: Sean Anderson 
---

 lib/efi_selftest/efi_selftest_set_virtual_address_map.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/efi_selftest/efi_selftest_set_virtual_address_map.c 
b/lib/efi_selftest/efi_selftest_set_virtual_address_map.c
index a4e5a50f63..b097a81136 100644
--- a/lib/efi_selftest/efi_selftest_set_virtual_address_map.c
+++ b/lib/efi_selftest/efi_selftest_set_virtual_address_map.c
@@ -23,7 +23,7 @@ static u32 notify_call_count;
 static bool convert_pointer_failed;
 
 /**
- * notify () - notification function
+ * notify() - notification function
  *
  * This function is called when the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event
  * occurs. The correct output of ConvertPointer() is checked.
-- 
2.28.0

[PATCH 1/2] efi: Add dependency on M-mode for RISC-V

[Sean Anderson]

>From section 2.3.7 of the UEFI specification:

> RISC-V UEFI will only be executed in machine mode. The machine mode has
> the highest privilege and this mode is the only mandatory privilege level
> for RISC-V platforms; all other privilege levels are optional depending
> on the platform requirements. Machine mode is the first mode entered at
> the power-on reset. This level is used in UEFI for low-level access to a
> hardware platform.

Signed-off-by: Sean Anderson 
---

 lib/efi_loader/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index bad1a29ba8..2197c84bf3 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -10,6 +10,8 @@ config EFI_LOADER
depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
+   # RISC-V UEFI must run in machine mode
+   depends on !RISCV || RISCV_M_MODE
default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
select LIB_UUID
select HAVE_BLOCK_DEVICE
-- 
2.28.0

Re: [PATCH 2/2] watchdog: add watchdog behavior configuration

[Tom Rini]

On Sun, Sep 27, 2020 at 06:06:38PM +0200, Michael Walle wrote:
> Am 2020-09-26 14:44, schrieb Tom Rini:
> [..]
> > > If we want to have a hardware based watchdog in the UEFI context, we
> > > need a U-Boot internal API by which we can enable and disable a
> > > hardware
> > > watchdog with an arbitrary duration (>> 5 min) with 1 second
> > > resolution.
> > > Then our implementation of SetWatchdogTimer() could call into this
> > > API.
> > 
> > Thanks for excerpting from the UEFI spec where it talks about a
> > "watchdog" at all.  It's clear from these excerpts that the spec simply
> > does not talk about a hardware watchdog at all and is using the term in
> > one of its other meanings.  Which means that we need to figure out and
> > document something nominally sane so at least it's not a surprise to the
> > user.
> > 
> > Michael, what driver under drivers/watchdog/ is your platform using
> > exactly?  Thanks!
> 
> In its current form (i.e. basic BSP support) it uses the sp805_wdt.c;
> which is a nice to have, but the real watchdog is an external device.
> There is no support in U-Boot for it yet, but I'm planning to add it
> and thus I need the CONFIG_WDT ;)
> 
> Currently this external watchdog is disabled (there are non-volatile
> configuration bits on the board and one bit is for disabling this
> watchdog at startup). Otherwise it would always activate the board's
> failsafe mode because it isn't triggered by U-Boot.
> 
> And yes, this watchdog also have a lock bit, once set, you cannot
> deactivate it anymore (although you can change the timeout period
> in a given range).
> 
> Because at the moment there is no driver for this watchdog yet (it
> is a custom one), my newest version of my "basic board support for
> Kontron sl28" has the CONFIG_WDT deactivated. I prefer having a
> usable bootefi to have support for the SoC internal watchdog.

Thanks for explaining.  I was asking in part because I was wondering if
that SoC was falling into the case of drivers/watchdog/imx_watchdog.c

-- 
Tom


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Re: [PATCH] MAINTAINERS: add Microchip PIT64B timer

[Eugen.Hristev]

On 23.09.2020 13:17, Claudiu Beznea wrote:
> Add Microchip PIT64B timer.
> 
> Signed-off-by: Claudiu Beznea 
> ---
> 
> Hi Eugen,
> 
> I chosed to have it under AT91 hood to not create an entry only for this
> driver as there are mostly architecture/subsystem related entries in
> MAINTAINERS file.
> 
> Thank you,
> Claudiu Beznea
> 

Applied to u-boot-atmel/next , thanks !

Re: [PATCH] timer: mchp-pit64b: add support for pit64b

[Eugen.Hristev]

On 22.09.2020 13:49, Claudiu Beznea - M18063 wrote:
> Hi Eugen,
> 
> On 22.09.2020 11:32, Eugen Hristev - M18282 wrote:
>> On 07.09.2020 18:36, Claudiu Beznea wrote:
>>> Add support for Microchip PIT64B timer. The timer is 64 bit length and
>>> is used as a free running counter (in continuous mode with highest values
>>> for period registers). The clock feeding the timer would be no more
>>> than 12.5MHz.
>>>
>>> Signed-off-by: Claudiu Beznea 
>>> ---
>>
>> Hi Claudiu,
>>
>> To make CI/CD scripts happy, this new driver needs a MAINTAINERS entry
> 
> Would you like me to create a new entry or add the file under the
> ARM MICROCHIP/ATMEL AT91 hood?
> 
> Thank you,
> Claudiu Beznea
> 
>>
>> Thanks !
>> Eugen

Applied to u-boot-atmel/next , thanks !

[PATCH v6 9/9] riscv: Update SiFive device tree for new CLINT driver

[Sean Anderson]

We currently do this in a u-boot specific dts, but hopefully we can get
these bindings added in Linux in the future.

Signed-off-by: Sean Anderson 
Reviewed-by: Pragnesh Patel 
Reviewed-by: Bin Meng 
---
This patch builds but has NOT been tested.

(no changes since v2)

Changes in v2:
- Fix SiFive CLINT not getting tick-rate from rtcclk

 arch/riscv/dts/fu540-c000-u-boot.dtsi   | 8 ++--
 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi 
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 5302677ee4..a06e1b11c6 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -55,9 +55,13 @@
reg = <0x0 0x1007 0x0 0x1000>;
fuse-count = <0x1000>;
};
-   clint@200 {
+   clint: clint@200 {
compatible = "riscv,clint0";
-   interrupts-extended = <_intc 3 _intc 7 
_intc 3 _intc 7 _intc 3 _intc 7 _intc 3 _intc 7 
_intc 3 _intc 7>;
+   interrupts-extended = <_intc 3 _intc 7
+  _intc 3 _intc 7
+  _intc 3 _intc 7
+  _intc 3 _intc 7
+  _intc 3 _intc 7>;
reg = <0x0 0x200 0x0 0xc>;
u-boot,dm-spl;
};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi 
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 5d0c928b29..1996149c95 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -34,6 +34,10 @@
 
 };
 
+ {
+   clocks = <>;
+};
+
  {
u-boot,dm-spl;
 
-- 
2.28.0

[PATCH v6 8/9] riscv: Update Kendryte device tree for new CLINT driver

[Sean Anderson]

The interrupt controller property is removed from the clint binding because
the clint is not an interrupt-controller. That is, no other devices have an
interrupt which is controlled by the clint.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

(no changes since v4)

Changes in v4:
- Remove clock-frequency property from k210 clint binding because we fall
  back on timebase-frequency

Changes in v2:
- New

 arch/riscv/dts/k210.dtsi | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 2546c7d4e0..84cff51c36 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -17,6 +17,8 @@
compatible = "kendryte,k210";
 
aliases {
+   cpu0 = 
+   cpu1 = 
dma0 = 
gpio0 = 
gpio1 = _0;
@@ -126,14 +128,13 @@
read-only;
};
 
-   clint0: interrupt-controller@200 {
+   clint0: clint@200 {
#interrupt-cells = <1>;
compatible = "kendryte,k210-clint", "riscv,clint0";
reg = <0x200 0xC000>;
-   interrupt-controller;
interrupts-extended = <_intc 3>, <_intc 7>,
  <_intc 3>, <_intc 7>;
-   clocks = < K210_CLK_CPU>;
+   clocks = < K210_CLK_CLINT>;
};
 
plic0: interrupt-controller@C00 {
-- 
2.28.0

[PATCH v6 7/9] riscv: clk: Add CLINT clock to kendryte clock driver

[Sean Anderson]

Another "virtual" clock (in the sense that it isn't configurable). This
could possibly be done as a clock in the device tree, but I think this is a
bit cleaner.

Signed-off-by: Sean Anderson 
---
checkpatch still complains about this one, but I don't see any reason to
break it up even further. It doesn't make sense to me to split the header
file change from everything else.

(no changes since v2)

Changes in v2:
- Split Kendryte binding changes into their own commit

 drivers/clk/kendryte/clk.c  | 4 
 include/dt-bindings/clock/k210-sysctl.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 981b3b7699..bb196961af 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -646,6 +646,10 @@ static int k210_clk_probe(struct udevice *dev)
REGISTER_GATE(K210_CLK_RTC,   "rtc",   in0);
 #undef REGISTER_GATE
 
+   /* The MTIME register in CLINT runs at one 50th the CPU clock speed */
+   clk_dm(K210_CLK_CLINT,
+  clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
+
return 0;
 }
 
diff --git a/include/dt-bindings/clock/k210-sysctl.h 
b/include/dt-bindings/clock/k210-sysctl.h
index 0e3ed3fb9f..fe852bbd92 100644
--- a/include/dt-bindings/clock/k210-sysctl.h
+++ b/include/dt-bindings/clock/k210-sysctl.h
@@ -55,5 +55,6 @@
 #define K210_CLK_OTP43
 #define K210_CLK_RTC44
 #define K210_CLK_ACLK   45
+#define K210_CLK_CLINT  46
 
 #endif /* CLOCK_K210_SYSCTL_H */
-- 
2.28.0

[PATCH v6 5/9] riscv: Clean up initialization in Andes PLIC

[Sean Anderson]

This merges the PLIC initialization code from two functions into one.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---
This patch builds but has NOT been tested.

(no changes since v1)

 arch/riscv/lib/andes_plic.c | 58 -
 1 file changed, 25 insertions(+), 33 deletions(-)

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index c2a8fe4d9e..267d6a191b 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -41,53 +41,45 @@ static int enable_ipi(int hart)
return 0;
 }
 
-static int init_plic(void)
+int riscv_init_ipi(void)
 {
-   struct udevice *dev;
-   ofnode node;
int ret;
+   long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
+   ofnode node;
+   struct udevice *dev;
u32 reg;
 
+   if (IS_ERR(base))
+   return PTR_ERR(base);
+   gd->arch.plic = base;
+
ret = uclass_find_first_device(UCLASS_CPU, );
if (ret)
return ret;
+   else if (!dev)
+   return -ENODEV;
 
-   if (dev) {
-   ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
-   const char *device_type;
+   ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+   const char *device_type;
 
-   device_type = ofnode_read_string(node, "device_type");
-   if (!device_type)
-   continue;
+   device_type = ofnode_read_string(node, "device_type");
+   if (!device_type)
+   continue;
 
-   if (strcmp(device_type, "cpu"))
-   continue;
+   if (strcmp(device_type, "cpu"))
+   continue;
 
-   /* skip if hart is marked as not available */
-   if (!ofnode_is_available(node))
-   continue;
+   /* skip if hart is marked as not available */
+   if (!ofnode_is_available(node))
+   continue;
 
-   /* read hart ID of CPU */
-   ret = ofnode_read_u32(node, "reg", );
-   if (ret == 0)
-   enable_ipi(reg);
-   }
-
-   return 0;
+   /* read hart ID of CPU */
+   ret = ofnode_read_u32(node, "reg", );
+   if (ret == 0)
+   enable_ipi(reg);
}
 
-   return -ENODEV;
-}
-
-int riscv_init_ipi(void)
-{
-   long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
-
-   if (IS_ERR(ret))
-   return PTR_ERR(ret);
-   gd->arch.plic = ret;
-
-   return init_plic();
+   return 0;
 }
 
 int riscv_send_ipi(int hart)
-- 
2.28.0

[PATCH v6 6/9] riscv: Rework Sifive CLINT as UCLASS_TIMER driver

[Sean Anderson]

This converts the clint driver from the riscv-specific interface to be a
DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously
implicitly depended on the CLINT to select REGMAP.

Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb),
the SiFive CLINT is part of the device tree passed in by qemu. This device
tree doesn't have a clocks or clock-frequency property on clint, so we need
to fall back on the timebase-frequency property. Perhaps in the future we
can get a clock-frequency property added to the qemu dtb.

Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller.
RISCV_SYSCON_CLINT is retained for this purpose.

Signed-off-by: Sean Anderson 
Reviewed-by: Pragnesh Patel 
---
This patch builds but has only been tested on the K210 and QEMU. It has NOT
been tested on a HiFive.

(no changes since v5)

Changes in v5:
- Don't add a dependency on REGMAP for SIFIVE_FU540_DDR. Instead, depend on Bin
  Meng's patch.

Changes in v4:
- Use timer_timebase_fallback

Changes in v3:
- Don't initialize the IPI in spl_invoke_opensbi. Further testing has
  revealed it to be unnecessary.

 arch/riscv/Kconfig|  4 ---
 arch/riscv/lib/sifive_clint.c | 66 +++
 2 files changed, 36 insertions(+), 34 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d9155b9bab..aaa3b833a5 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -155,10 +155,6 @@ config 64BIT
 config SIFIVE_CLINT
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
-   select REGMAP
-   select SYSCON
-   select SPL_REGMAP if SPL
-   select SPL_SYSCON if SPL
help
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index b9a2c649cc..c9704c596f 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -8,9 +8,9 @@
  */
 
 #include 
+#include 
 #include 
-#include 
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -24,35 +24,19 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int riscv_get_time(u64 *time)
-{
-   /* ensure timer register base has a sane value */
-   riscv_init_ipi();
-
-   *time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
-
-   return 0;
-}
-
-int riscv_set_timecmp(int hart, u64 cmp)
-{
-   /* ensure timer register base has a sane value */
-   riscv_init_ipi();
-
-   writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
-
-   return 0;
-}
-
 int riscv_init_ipi(void)
 {
-   if (!gd->arch.clint) {
-   long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
+   int ret;
+   struct udevice *dev;
 
-   if (IS_ERR(ret))
-   return PTR_ERR(ret);
-   gd->arch.clint = ret;
-   }
+   ret = uclass_get_device_by_driver(UCLASS_TIMER,
+ DM_GET_DRIVER(sifive_clint), );
+   if (ret)
+   return ret;
+
+   gd->arch.clint = dev_read_addr_ptr(dev);
+   if (!gd->arch.clint)
+   return -EINVAL;
 
return 0;
 }
@@ -78,14 +62,36 @@ int riscv_get_ipi(int hart, int *pending)
return 0;
 }
 
+static int sifive_clint_get_count(struct udevice *dev, u64 *count)
+{
+   *count = readq((void __iomem *)MTIME_REG(dev->priv));
+
+   return 0;
+}
+
+static const struct timer_ops sifive_clint_ops = {
+   .get_count = sifive_clint_get_count,
+};
+
+static int sifive_clint_probe(struct udevice *dev)
+{
+   dev->priv = dev_read_addr_ptr(dev);
+   if (!dev->priv)
+   return -EINVAL;
+
+   return timer_timebase_fallback(dev);
+}
+
 static const struct udevice_id sifive_clint_ids[] = {
-   { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
+   { .compatible = "riscv,clint0" },
{ }
 };
 
 U_BOOT_DRIVER(sifive_clint) = {
.name   = "sifive_clint",
-   .id = UCLASS_SYSCON,
+   .id = UCLASS_TIMER,
.of_match   = sifive_clint_ids,
+   .probe  = sifive_clint_probe,
+   .ops= _clint_ops,
.flags  = DM_FLAG_PRE_RELOC,
 };
-- 
2.28.0

[PATCH v6 1/9] riscv: Rework riscv timer driver to only support S-mode

[Sean Anderson]

The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.

This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
Reviewed-by: Rick Chen 
---

(no changes since v4)

Changes in v4:
- Modify RISCV_TIMER KConfig
  - Now depends on RISCV
  - Implied by S-Mode (with or without SPL)

Changes in v2:
- Remove RISCV_RDTIME KConfig option

 arch/riscv/Kconfig |  8 ---
 arch/riscv/cpu/ax25/Kconfig|  2 +-
 arch/riscv/cpu/fu540/Kconfig   |  2 +-
 arch/riscv/cpu/generic/Kconfig |  2 +-
 arch/riscv/lib/Makefile|  1 -
 arch/riscv/lib/rdtime.c| 38 -
 drivers/timer/Kconfig  |  4 ++--
 drivers/timer/riscv_timer.c| 39 +-
 8 files changed, 25 insertions(+), 71 deletions(-)
 delete mode 100644 arch/riscv/lib/rdtime.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 009a545fcf..21e6690f4d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -185,14 +185,6 @@ config ANDES_PLMT
  The Andes PLMT block holds memory-mapped mtime register
  associated with timer tick.
 
-config RISCV_RDTIME
-   bool
-   default y if RISCV_SMODE || SPL_RISCV_SMODE
-   help
- The provides the riscv_get_time() API that is implemented using the
- standard rdtime instruction. This is the case for S-mode U-Boot, and
- is useful for processors that support rdtime in M-mode too.
-
 config SYS_MALLOC_F_LEN
default 0x1000
 
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 8d8d71dcbf..5cb5bb51eb 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -3,7 +3,7 @@ config RISCV_NDS
select ARCH_EARLY_INIT_R
imply CPU
imply CPU_RISCV
-   imply RISCV_TIMER
+   imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply SPL_CPU_SUPPORT
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 53e19635c8..ac3f183342 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -10,7 +10,7 @@ config SIFIVE_FU540
select SPL_RAM if SPL
imply CPU
imply CPU_RISCV
-   imply RISCV_TIMER
+   imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply CMD_CPU
imply SPL_CPU_SUPPORT
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index b2cb155d6d..f4c2e2643c 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -7,7 +7,7 @@ config GENERIC_RISCV
select ARCH_EARLY_INIT_R
imply CPU
imply CPU_RISCV
-   imply RISCV_TIMER
+   imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply CMD_CPU
imply SPL_CPU_SUPPORT
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 6c503ff2b2..10ac5b06d3 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
 obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 else
-obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 endif
diff --git a/arch/riscv/lib/rdtime.c b/arch/riscv/lib/rdtime.c
deleted file mode 100644
index e128d7fce6..00
--- a/arch/riscv/lib/rdtime.c
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018, Anup Patel 
- * Copyright (C) 2018, Bin Meng 
- *
- * The riscv_get_time() API implementation that is using the
- * standard rdtime instruction.
- */
-
-#include 
-
-/* Implement the API required by RISC-V timer driver */
-int riscv_get_time(u64 *time)
-{
-#ifdef CONFIG_64BIT
-  

[PATCH v6 2/9] timer: Add helper for drivers using timebase fallback

[Sean Anderson]

This function is designed to be used when a timer used to be initialized by
the cpu (e.g. RISC-V timers), but now is initialized by dm_timer_init. In
such a case, the timer may prefer to use the clocks and clock-frequency
properties, but should be able to fall back on using the cpu's
timebase-frequency.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
Reviewed-by: Bin Meng 
Reviewed-by: Rick Chen 
---

Changes in v6:
- Don't compile timer_timebase_fallback if CONFIG_CPU is disabled. This config
  is only disabled on nds32; perhaps it can be enabled in the future? In
  addition, SPL_CPU_SUPPORT should probably be renamed to SPL_CPU

Changes in v4:
- New

 drivers/timer/timer-uclass.c | 31 +++
 include/timer.h  | 15 +++
 2 files changed, 46 insertions(+)

diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index 14dde950a1..e9802c8b43 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -4,6 +4,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -79,6 +80,36 @@ static int timer_post_probe(struct udevice *dev)
return 0;
 }
 
+/*
+ * TODO: should be CONFIG_IS_ENABLED(CPU), but the SPL config has _SUPPORT on
+ * the end...
+ */
+#if defined(CONFIG_CPU) || defined(CONFIG_SPL_CPU_SUPPORT)
+int timer_timebase_fallback(struct udevice *dev)
+{
+   struct udevice *cpu;
+   struct cpu_platdata *cpu_plat;
+   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+   /* Did we get our clock rate from the device tree? */
+   if (uc_priv->clock_rate)
+   return 0;
+
+   /* Fall back to timebase-frequency */
+   dev_dbg(dev, "missing clocks or clock-frequency property; falling back 
on timebase-frequency\n");
+   cpu = cpu_get_current_dev();
+   if (!cpu)
+   return -ENODEV;
+
+   cpu_plat = dev_get_parent_platdata(cpu);
+   if (!cpu_plat)
+   return -ENODEV;
+
+   uc_priv->clock_rate = cpu_plat->timebase_freq;
+   return 0;
+}
+#endif
+
 u64 timer_conv_64(u32 count)
 {
/* increment tbh if tbl has rolled over */
diff --git a/include/timer.h b/include/timer.h
index a49b500ce3..8b9fa51c53 100644
--- a/include/timer.h
+++ b/include/timer.h
@@ -15,6 +15,21 @@
  */
 int dm_timer_init(void);
 
+/**
+ * timer_timebase_fallback() - Helper for timers using timebase fallback
+ * @dev: A timer partially-probed timer device
+ *
+ * This is a helper function designed for timers which need to fall back on the
+ * cpu's timebase. This function is designed to be called during the driver's
+ * probe(). If there is a clocks or clock-frequency property in the timer's
+ * binding, then it will be used. Otherwise, the timebase of the current cpu
+ * will be used. This is initialized by the cpu driver, and usually gotten from
+ * ``/cpus/timebase-frequency`` or ``/cpus/cpu@X/timebase-frequency``.
+ *
+ * Return: 0 if OK, or negative error code on failure
+ */
+int timer_timebase_fallback(struct udevice *dev);
+
 /*
  * timer_conv_64 - convert 32-bit counter value to 64-bit
  *
-- 
2.28.0

[PATCH v6 4/9] riscv: Rework Andes PLMT as a UCLASS_TIMER driver

[Sean Anderson]

This converts the PLMT driver from the riscv-specific timer interface to be
a DM-based UCLASS_TIMER driver.

The clock-frequency/clocks properties are preferred over timebase-frequency
for two reasons. First, properties which affect a device should be located
near its binding in the device tree. Using timebase-frequency only really
makes sense when the cpu itself is the timer device. This is the case when
we read the time from a CSR, but not when there is a separate device.
Second, it lets the device use the clock subsystem which adds flexibility.
If the device is configured for a different clock speed, the timer can
adjust itself.

Signed-off-by: Sean Anderson 
Reviewed-by: Rick Chen 
---
This patch builds but has NOT been tested.

(no changes since v5)

Changes in v5:
- Remove RISCV_SYSCON_PLMT
- Undo changes to ae350 device trees. They are unnecessary with
  timer_timebase_fallback.

Changes in v4:
- Use timer_timebase_fallback

 arch/riscv/Kconfig   |  4 ---
 arch/riscv/include/asm/global_data.h |  3 --
 arch/riscv/include/asm/syscon.h  |  4 +--
 arch/riscv/lib/andes_plmt.c  | 44 +---
 4 files changed, 23 insertions(+), 32 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 21e6690f4d..d9155b9bab 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -177,10 +177,6 @@ config ANDES_PLIC
 config ANDES_PLMT
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
-   select REGMAP
-   select SYSCON
-   select SPL_REGMAP if SPL
-   select SPL_SYSCON if SPL
help
  The Andes PLMT block holds memory-mapped mtime register
  associated with timer tick.
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index b711fcc44d..d3a0b1d221 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -24,9 +24,6 @@ struct arch_global_data {
 #ifdef CONFIG_ANDES_PLIC
void __iomem *plic; /* plic base address */
 #endif
-#ifdef CONFIG_ANDES_PLMT
-   void __iomem *plmt; /* plmt base address */
-#endif
 #if CONFIG_IS_ENABLED(SMP)
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index 26a008ca59..c3629e4b53 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -7,13 +7,13 @@
 #define _ASM_SYSCON_H
 
 /*
- * System controllers in a RISC-V system
+ * System controllers in a RISC-V system. These should only be used for
+ * identifying IPI controllers. Other devices should use DM to probe.
  */
 enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
RISCV_SYSCON_PLIC,  /* Platform Level Interrupt Controller (PLIC) */
-   RISCV_SYSCON_PLMT,  /* Platform Level Machine Timer (PLMT) */
 };
 
 #endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
index a7e90ca992..a28c14c1eb 100644
--- a/arch/riscv/lib/andes_plmt.c
+++ b/arch/riscv/lib/andes_plmt.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2019, Rick Chen 
+ * Copyright (C) 2020, Sean Anderson 
  *
  * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
  * The PLMT block holds memory-mapped mtime register
@@ -9,46 +10,43 @@
 
 #include 
 #include 
-#include 
-#include 
+#include 
 #include 
-#include 
 #include 
 
 /* mtime register */
 #define MTIME_REG(base)((ulong)(base))
 
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PLMT_BASE_GET(void)\
-   do {\
-   long *ret;  \
-   \
-   if (!gd->arch.plmt) {   \
-   ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
-   if (IS_ERR(ret))\
-   return PTR_ERR(ret);\
-   gd->arch.plmt = ret;\
-   }   \
-   } while (0)
-
-int riscv_get_time(u64 *time)
+static int andes_plmt_get_count(struct udevice *dev, u64 *count)
 {
-   PLMT_BASE_GET();
-
-   *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+   *count = readq((void __iomem *)MTIME_REG(dev->priv));
 
return 0;
 }
 
+static const struct timer_ops andes_plmt_ops = {
+   .get_count = andes_plmt_get_count,
+};
+
+static int andes_plmt_probe(struct udevice *dev)
+{
+   dev->priv = dev_read_addr_ptr(dev);
+   if (!dev->priv)
+   return -EINVAL;
+
+   return timer_timebase_fallback(dev);
+}
+
 static const struct udevice_id andes_plmt_ids[] = {
-   

[PATCH v6 3/9] timer: Add a test for timer_timebase_fallback

[Sean Anderson]

To test this function, sandbox CPU must set cpu_platdata.timebase_freq on
bind. It also needs to expose a method to set the current cpu. I also make
some most members of cpu_sandbox_ops static.

On the timer side, the device tree property
sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe
falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
---

(no changes since v5)

Changes in v5:
- New

 arch/sandbox/dts/test.dts  |  9 +++-
 arch/sandbox/include/asm/cpu.h | 11 ++
 drivers/cpu/cpu_sandbox.c  | 39 --
 drivers/timer/sandbox_timer.c  |  4 +++-
 test/dm/timer.c| 27 ++-
 5 files changed, 80 insertions(+), 10 deletions(-)
 create mode 100644 arch/sandbox/include/asm/cpu.h

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 9f45c48e4e..2f559265a5 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -533,7 +533,9 @@
};
 
cpus {
+   timebase-frequency = <200>;
cpu-test1 {
+   timebase-frequency = <300>;
compatible = "sandbox,cpu_sandbox";
u-boot,dm-pre-reloc;
};
@@ -839,11 +841,16 @@
0x58 8>;
};
 
-   timer {
+   timer@0 {
compatible = "sandbox,timer";
clock-frequency = <100>;
};
 
+   timer@1 {
+   compatible = "sandbox,timer";
+   sandbox,timebase-frequency-fallback;
+   };
+
tpm2 {
compatible = "sandbox,tpm2";
};
diff --git a/arch/sandbox/include/asm/cpu.h b/arch/sandbox/include/asm/cpu.h
new file mode 100644
index 00..c97ac7ba95
--- /dev/null
+++ b/arch/sandbox/include/asm/cpu.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson 
+ */
+
+#ifndef __SANDBOX_CPU_H
+#define __SANDBOX_CPU_H
+
+void cpu_sandbox_set_current(const char *name);
+
+#endif /* __SANDBOX_CPU_H */
diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c
index caa26e50f2..4ba0d1b99e 100644
--- a/drivers/cpu/cpu_sandbox.c
+++ b/drivers/cpu/cpu_sandbox.c
@@ -8,14 +8,15 @@
 #include 
 #include 
 
-int cpu_sandbox_get_desc(const struct udevice *dev, char *buf, int size)
+static int cpu_sandbox_get_desc(const struct udevice *dev, char *buf, int size)
 {
snprintf(buf, size, "LEG Inc. SuperMegaUltraTurbo CPU No. 1");
 
return 0;
 }
 
-int cpu_sandbox_get_info(const struct udevice *dev, struct cpu_info *info)
+static int cpu_sandbox_get_info(const struct udevice *dev,
+   struct cpu_info *info)
 {
info->cpu_freq = 42 * 42 * 42 * 42 * 42;
info->features = 0x42424242;
@@ -24,21 +25,29 @@ int cpu_sandbox_get_info(const struct udevice *dev, struct 
cpu_info *info)
return 0;
 }
 
-int cpu_sandbox_get_count(const struct udevice *dev)
+static int cpu_sandbox_get_count(const struct udevice *dev)
 {
return 42;
 }
 
-int cpu_sandbox_get_vendor(const struct udevice *dev, char *buf, int size)
+static int cpu_sandbox_get_vendor(const struct udevice *dev, char *buf,
+ int size)
 {
snprintf(buf, size, "Languid Example Garbage Inc.");
 
return 0;
 }
 
-int cpu_sandbox_is_current(struct udevice *dev)
+static const char *cpu_current = "cpu-test1";
+
+void cpu_sandbox_set_current(const char *name)
 {
-   if (!strcmp(dev->name, "cpu-test1"))
+   cpu_current = name;
+}
+
+static int cpu_sandbox_is_current(struct udevice *dev)
+{
+   if (!strcmp(dev->name, cpu_current))
return 1;
 
return 0;
@@ -52,7 +61,22 @@ static const struct cpu_ops cpu_sandbox_ops = {
.is_current = cpu_sandbox_is_current,
 };
 
-int cpu_sandbox_probe(struct udevice *dev)
+static int cpu_sandbox_bind(struct udevice *dev)
+{
+   int ret;
+   struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+   /* first examine the property in current cpu node */
+   ret = dev_read_u32(dev, "timebase-frequency", >timebase_freq);
+   /* if not found, then look at the parent /cpus node */
+   if (ret)
+   ret = dev_read_u32(dev->parent, "timebase-frequency",
+  >timebase_freq);
+
+   return ret;
+}
+
+static int cpu_sandbox_probe(struct udevice *dev)
 {
return 0;
 }
@@ -67,5 +91,6 @@ U_BOOT_DRIVER(cpu_sandbox) = {
.id = UCLASS_CPU,
.ops= _sandbox_ops,
.of_match   = cpu_sandbox_ids,
+   .bind   = cpu_sandbox_bind,
.probe  = cpu_sandbox_probe,
 };
diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c
index 5228486082..6a503c2f15 100644
--- a/drivers/timer/sandbox_timer.c
+++ b/drivers/timer/sandbox_timer.c

[PATCH v6 0/9] riscv: Clean up timer drivers

[Sean Anderson]

This series cleans up the timer drivers in RISC-V and converts them to DM.

This series needs to be tested! I have only tested it on QEMU and the K210.
Notably, this means that the HiFive and anything Andes is completely untested.

This series depends on [1]. Without that patch, build will fail for sifive
targets.

[1] 
http://patchwork.ozlabs.org/project/uboot/patch/1600157107-57175-2-git-send-email-bmeng...@gmail.com/

Changes in v6:
- Don't compile timer_timebase_fallback if CONFIG_CPU is disabled. This config
  is only disabled on nds32; perhaps it can be enabled in the future? In
  addition, SPL_CPU_SUPPORT should probably be renamed to SPL_CPU

Changes in v5:
- Add test for timer_timebase_fallback
- Don't add a dependency on REGMAP for SIFIVE_FU540_DDR. Instead, depend on Bin
  Meng's patch.
- Remove RISCV_SYSCON_PLMT
- Undo changes to ae350 device trees. They are unnecessary with
  timer_timebase_fallback.

Changes in v4:
- Both the Andes PMLT and Sifive CLINT now fall back on timebase-frequency,
  per discussion with Anup Patel
- Introduce helper function for falling back on timebase-frequency
- Modify RISCV_TIMER KConfig
  - Now depends on RISCV
  - Implied by S-Mode (with or without SPL)
- Rebase
- Remove clock-frequency property from k210 clint binding because we fall
  back on timebase-frequency

Changes in v3:
- Don't initialize the IPI in spl_invoke_opensbi. Further testing has
  revealed it to be unnecessary.
- Rebase

Changes in v2:
- Fix SiFive CLINT not getting tick-rate from rtcclk
- Remove RISCV_RDTIME KConfig option
- Split Kendryte binding changes into their own commit

Sean Anderson (9):
  riscv: Rework riscv timer driver to only support S-mode
  timer: Add helper for drivers using timebase fallback
  timer: Add a test for timer_timebase_fallback
  riscv: Rework Andes PLMT as a UCLASS_TIMER driver
  riscv: Clean up initialization in Andes PLIC
  riscv: Rework Sifive CLINT as UCLASS_TIMER driver
  riscv: clk: Add CLINT clock to kendryte clock driver
  riscv: Update Kendryte device tree for new CLINT driver
  riscv: Update SiFive device tree for new CLINT driver

 arch/riscv/Kconfig| 16 -
 arch/riscv/cpu/ax25/Kconfig   |  2 +-
 arch/riscv/cpu/fu540/Kconfig  |  2 +-
 arch/riscv/cpu/generic/Kconfig|  2 +-
 arch/riscv/dts/fu540-c000-u-boot.dtsi |  8 ++-
 .../dts/hifive-unleashed-a00-u-boot.dtsi  |  4 ++
 arch/riscv/dts/k210.dtsi  |  7 +-
 arch/riscv/include/asm/global_data.h  |  3 -
 arch/riscv/include/asm/syscon.h   |  4 +-
 arch/riscv/lib/Makefile   |  1 -
 arch/riscv/lib/andes_plic.c   | 58 +++-
 arch/riscv/lib/andes_plmt.c   | 44 ++---
 arch/riscv/lib/rdtime.c   | 38 ---
 arch/riscv/lib/sifive_clint.c | 66 ++-
 arch/sandbox/dts/test.dts |  9 ++-
 arch/sandbox/include/asm/cpu.h| 11 
 drivers/clk/kendryte/clk.c|  4 ++
 drivers/cpu/cpu_sandbox.c | 39 +--
 drivers/timer/Kconfig |  4 +-
 drivers/timer/riscv_timer.c   | 39 +--
 drivers/timer/sandbox_timer.c |  4 +-
 drivers/timer/timer-uclass.c  | 31 +
 include/dt-bindings/clock/k210-sysctl.h   |  1 +
 include/timer.h   | 15 +
 test/dm/timer.c   | 27 +++-
 25 files changed, 254 insertions(+), 185 deletions(-)
 delete mode 100644 arch/riscv/lib/rdtime.c
 create mode 100644 arch/sandbox/include/asm/cpu.h

-- 
2.28.0

Re: pull request of u-boot-fsl-qoriq for v2020.10

[Tom Rini]

On Fri, Sep 25, 2020 at 04:48:54PM +, Priyanka Jain wrote:

> Dear Tom,
> 
> 
> 
> Please find my pull-request for u-boot-fsl-qoriq/master
> https://travis-ci.org/github/p-priyanka-jain/u-boot/builds/729991334
> 
> Summary
> Bug fixes related to PCIe, pfe, xfi,
> gpio, reset,vid,env, usb on layerscape products
> 
> Thanks
> Priyanka

Applied to u-boot/master, thanks!

-- 
Tom


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Description: PGP signature

Re: [PULL u-boot] Please pull u-boot-amlogic-20200928

[Tom Rini]

On Mon, Sep 28, 2020 at 11:59:07AM +0200, Neil Armstrong wrote:

> Hi Tom,
> 
> This PR fixes Linux EFI KASLR boot on GXL, GXM, G12A, G12B & SM1 based boards.
> 
> The CI job is at 
> https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/4642
> 
> Thanks,
> Neil
> 
> The following changes since commit 1da91d9bcd6e5ef046c1df0d373d0df87b1e8a72:
> 
>   Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2020-09-24 
> 08:34:54 -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git 
> tags/u-boot-amlogic-20200928
> 
> for you to fetch changes up to 02d249f99ecb7e398067d91760287c61d35fd34b:
> 
>   rng: meson: make core clock optional (2020-09-28 09:38:11 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Description: PGP signature

Re: Pull request for UEFI sub-system for efi-2020-10-rc6

[Tom Rini]

On Mon, Sep 28, 2020 at 12:30:46PM +0200, Heinrich Schuchardt wrote:

> Hello Tom,
> 
> The following changes since commit 1da91d9bcd6e5ef046c1df0d373d0df87b1e8a72:
> 
>   Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
> (2020-09-24 08:34:54 -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
> tags/efi-2020-10-rc6
> 
> for you to fetch changes up to c48e9f310b950e39a91cea74b6708dd4fe2eb39c:
> 
>   riscv: restore global data pointer in trap handler (2020-09-28
> 12:20:19 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Description: PGP signature

Re: [BUG] sandbox: './u-boot -l ' fails

[Simon Glass]

Hi Heinrich,

On Mon, 28 Sep 2020 at 07:30, Heinrich Schuchardt  wrote:
>
> On 28.09.20 15:22, Simon Glass wrote:
> > Hi Heinrich,
> >
> > On Mon, 28 Sep 2020 at 05:31, Heinrich Schuchardt  
> > wrote:
> >>
> >> On 28.09.20 06:46, Heinrich Schuchardt wrote:
> >>> Am 28. September 2020 06:24:38 MESZ schrieb Simon Glass 
> >>> :
>  Hi Heinrich,
> 
>  On Sat, 19 Sep 2020 at 13:48, Heinrich Schuchardt 
>  wrote:
> >
> > Hello Simon,
> >
> > when I try to run ./u-boot -l the sandbox stalls. Shouldn't it run
>  out
> > of the box?
> >
> > $ ./u-boot -l -d arch/sandbox/dts/sandbox.dtb
> 
>  For the record you should be able to use -D to get the same effect as
>  your -d above.
> 
> >
> > U-Boot 2020.10-rc4-00018-g21a10244f9-dirty (Sep 19 2020 - 19:55:39
>  +0200)
> >
> > Model: sandbox
> > DRAM:  128 MiB
> >
> > Warning: host_lo MAC addresses don't match:
> > Address in ROM is   26:4b:ca:6c:98:f4
> > Address in environment is   00:00:11:22:33:44
> >
> > Warning: host_virbr0 MAC addresses don't match:
> > Address in ROM is   ee:3e:c9:ce:1f:9c
> > Address in environment is   00:00:11:22:33:45
> >
> > Warning: host_docker0 MAC addresses don't match:
> > Address in ROM is   c2:85:07:7b:9a:18
> > Address in environment is   00:00:11:22:33:46
> > WDT:   Not found!
> > MMC:
> >
> > No output after this point.
> >
> > The problem also exists with U-Boot v2020.07, v2019.10, v2018.11.
> >
> > CONFIG_SANDBOX_SDL=y
> >
> > SDL_InitSubSystem() never returns. It is looping somewhere in
>  U-Boot's
> > __serial_getc(). I wonder how it gets there without returning from
>  the
> > function.
> >
> > I compiled SDL2.cpp from
> > https://gist.github.com/miguelmartin75/6946310#file-sdl2-cpp-L18
> > with
> >
> > g++ SDL2.cpp -D_REENTRANT -I/usr/include/SDL2 -lSDL2 -lGL -o test
> >
> > and it runs fine showing an X11 windows with red background.
> >
> > So there seems to be no general problem with the SDL2 library.
> 
>  I hit this myself on another computer and it turned out to be that SDL
>  defined getc(), as does U-Boot, and things get confused. At least I
>  think it is getc.
> 
>  I hacked around with changing the name of getc (I think it was getc)
>  in U-Boot and the problem went away.
> >>>
> >>> Should we include a patched SDL2 with U-Boot for static linking?
> >>>
> >>
> >> I cannot find a symbol getc() nor a reference to it in the SDL
> >> repository. getc() is defined in stdio.h.
> >>
> >> Our getc() takes no argument, while the stdio one wants a FILE *.
> >>
> >> But changing the U-Boot definition to "int getc(void *)" does not solve
> >> the issue.
> >
> > I just tried it on the machine where it doesn't work:
> >
> > $ gdb --args /tmp/b/sandbox/u-boot -l -D
> > GNU gdb (Debian 9.2-1) 9.2
> > Copyright (C) 2020 Free Software Foundation, Inc.
> > License GPLv3+: GNU GPL version 3 or later 
> > 
> > This is free software: you are free to change and redistribute it.
> > There is NO WARRANTY, to the extent permitted by law.
> > Type "show copying" and "show warranty" for details.
> > This GDB was configured as "x86_64-linux-gnu".
> > Type "show configuration" for configuration details.
> > For bug reporting instructions, please see:
> > .
> > Find the GDB manual and other documentation resources online at:
> > .
> >
> > For help, type "help".
> > Type "apropos word" to search for commands related to "word"...
> > Reading symbols from /tmp/b/sandbox/u-boot...
> > (gdb) br getc
> > Breakpoint 1 at 0x5b6d6: getc. (2 locations)
> > (gdb) r
> > Starting program: /tmp/b/sandbox/u-boot -l -D
> > [Thread debugging using libthread_db enabled]
> > Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
> >
> >
> > U-Boot 2020.10-rc5-00196-g0ac83d080a0 (Sep 28 2020 - 07:11:52 -0600)
> >
> > Model: sandbox
> > DRAM:  128 MiB
> >
> > Warning: host_lo MAC addresses don't match:
> > Address in ROM is 1a:34:9b:48:aa:53
> > Address in environment is 00:00:11:22:33:44
> > WDT:   Not found!
> > MMC:
> >
> > Breakpoint 1, getc () at
> > /home/sjg/cosarm/src/third_party/u-boot/files/common/console.c:414
> > 414 if (!gd->have_console)
> > (gdb) up
> > #1  0x77914d48 in ?? () from /lib/x86_64-linux-gnu/libX11.so.6
> > (gdb)
> >
> >
> > So it seems that it is libX11 causing the problem.
> >
> > I don't think the best fix is to remove getc() from that library,
> > although I do wonder if it is a bug. Renaming the symbol in U-Boot
> > with #define (only on sandbox) might be one option.
> >
> > Regards,
> > Simon
> >
>
> #define getc _uboot_getc
>
> is what I tried but it runs you into the trouble 

Re: [BUG] sandbox: './u-boot -l ' fails

[Heinrich Schuchardt]

On 28.09.20 15:22, Simon Glass wrote:
> Hi Heinrich,
>
> On Mon, 28 Sep 2020 at 05:31, Heinrich Schuchardt  wrote:
>>
>> On 28.09.20 06:46, Heinrich Schuchardt wrote:
>>> Am 28. September 2020 06:24:38 MESZ schrieb Simon Glass :
 Hi Heinrich,

 On Sat, 19 Sep 2020 at 13:48, Heinrich Schuchardt 
 wrote:
>
> Hello Simon,
>
> when I try to run ./u-boot -l the sandbox stalls. Shouldn't it run
 out
> of the box?
>
> $ ./u-boot -l -d arch/sandbox/dts/sandbox.dtb

 For the record you should be able to use -D to get the same effect as
 your -d above.

>
> U-Boot 2020.10-rc4-00018-g21a10244f9-dirty (Sep 19 2020 - 19:55:39
 +0200)
>
> Model: sandbox
> DRAM:  128 MiB
>
> Warning: host_lo MAC addresses don't match:
> Address in ROM is   26:4b:ca:6c:98:f4
> Address in environment is   00:00:11:22:33:44
>
> Warning: host_virbr0 MAC addresses don't match:
> Address in ROM is   ee:3e:c9:ce:1f:9c
> Address in environment is   00:00:11:22:33:45
>
> Warning: host_docker0 MAC addresses don't match:
> Address in ROM is   c2:85:07:7b:9a:18
> Address in environment is   00:00:11:22:33:46
> WDT:   Not found!
> MMC:
>
> No output after this point.
>
> The problem also exists with U-Boot v2020.07, v2019.10, v2018.11.
>
> CONFIG_SANDBOX_SDL=y
>
> SDL_InitSubSystem() never returns. It is looping somewhere in
 U-Boot's
> __serial_getc(). I wonder how it gets there without returning from
 the
> function.
>
> I compiled SDL2.cpp from
> https://gist.github.com/miguelmartin75/6946310#file-sdl2-cpp-L18
> with
>
> g++ SDL2.cpp -D_REENTRANT -I/usr/include/SDL2 -lSDL2 -lGL -o test
>
> and it runs fine showing an X11 windows with red background.
>
> So there seems to be no general problem with the SDL2 library.

 I hit this myself on another computer and it turned out to be that SDL
 defined getc(), as does U-Boot, and things get confused. At least I
 think it is getc.

 I hacked around with changing the name of getc (I think it was getc)
 in U-Boot and the problem went away.
>>>
>>> Should we include a patched SDL2 with U-Boot for static linking?
>>>
>>
>> I cannot find a symbol getc() nor a reference to it in the SDL
>> repository. getc() is defined in stdio.h.
>>
>> Our getc() takes no argument, while the stdio one wants a FILE *.
>>
>> But changing the U-Boot definition to "int getc(void *)" does not solve
>> the issue.
>
> I just tried it on the machine where it doesn't work:
>
> $ gdb --args /tmp/b/sandbox/u-boot -l -D
> GNU gdb (Debian 9.2-1) 9.2
> Copyright (C) 2020 Free Software Foundation, Inc.
> License GPLv3+: GNU GPL version 3 or later 
> This is free software: you are free to change and redistribute it.
> There is NO WARRANTY, to the extent permitted by law.
> Type "show copying" and "show warranty" for details.
> This GDB was configured as "x86_64-linux-gnu".
> Type "show configuration" for configuration details.
> For bug reporting instructions, please see:
> .
> Find the GDB manual and other documentation resources online at:
> .
>
> For help, type "help".
> Type "apropos word" to search for commands related to "word"...
> Reading symbols from /tmp/b/sandbox/u-boot...
> (gdb) br getc
> Breakpoint 1 at 0x5b6d6: getc. (2 locations)
> (gdb) r
> Starting program: /tmp/b/sandbox/u-boot -l -D
> [Thread debugging using libthread_db enabled]
> Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
>
>
> U-Boot 2020.10-rc5-00196-g0ac83d080a0 (Sep 28 2020 - 07:11:52 -0600)
>
> Model: sandbox
> DRAM:  128 MiB
>
> Warning: host_lo MAC addresses don't match:
> Address in ROM is 1a:34:9b:48:aa:53
> Address in environment is 00:00:11:22:33:44
> WDT:   Not found!
> MMC:
>
> Breakpoint 1, getc () at
> /home/sjg/cosarm/src/third_party/u-boot/files/common/console.c:414
> 414 if (!gd->have_console)
> (gdb) up
> #1  0x77914d48 in ?? () from /lib/x86_64-linux-gnu/libX11.so.6
> (gdb)
>
>
> So it seems that it is libX11 causing the problem.
>
> I don't think the best fix is to remove getc() from that library,
> although I do wonder if it is a bug. Renaming the symbol in U-Boot
> with #define (only on sandbox) might be one option.
>
> Regards,
> Simon
>

#define getc _uboot_getc

is what I tried but it runs you into the trouble that many other symbols
contain the getc substring.

As we always try to use the same definition in U-Boot as in glibc we
should really replace getc() by another symbol, e.g. chget() so that we
avoid confusion.

Best regards

Heinrich

Re: [BUG] sandbox: './u-boot -l ' fails

[Simon Glass]

Hi Heinrich,

On Mon, 28 Sep 2020 at 05:31, Heinrich Schuchardt  wrote:
>
> On 28.09.20 06:46, Heinrich Schuchardt wrote:
> > Am 28. September 2020 06:24:38 MESZ schrieb Simon Glass :
> >> Hi Heinrich,
> >>
> >> On Sat, 19 Sep 2020 at 13:48, Heinrich Schuchardt 
> >> wrote:
> >>>
> >>> Hello Simon,
> >>>
> >>> when I try to run ./u-boot -l the sandbox stalls. Shouldn't it run
> >> out
> >>> of the box?
> >>>
> >>> $ ./u-boot -l -d arch/sandbox/dts/sandbox.dtb
> >>
> >> For the record you should be able to use -D to get the same effect as
> >> your -d above.
> >>
> >>>
> >>> U-Boot 2020.10-rc4-00018-g21a10244f9-dirty (Sep 19 2020 - 19:55:39
> >> +0200)
> >>>
> >>> Model: sandbox
> >>> DRAM:  128 MiB
> >>>
> >>> Warning: host_lo MAC addresses don't match:
> >>> Address in ROM is   26:4b:ca:6c:98:f4
> >>> Address in environment is   00:00:11:22:33:44
> >>>
> >>> Warning: host_virbr0 MAC addresses don't match:
> >>> Address in ROM is   ee:3e:c9:ce:1f:9c
> >>> Address in environment is   00:00:11:22:33:45
> >>>
> >>> Warning: host_docker0 MAC addresses don't match:
> >>> Address in ROM is   c2:85:07:7b:9a:18
> >>> Address in environment is   00:00:11:22:33:46
> >>> WDT:   Not found!
> >>> MMC:
> >>>
> >>> No output after this point.
> >>>
> >>> The problem also exists with U-Boot v2020.07, v2019.10, v2018.11.
> >>>
> >>> CONFIG_SANDBOX_SDL=y
> >>>
> >>> SDL_InitSubSystem() never returns. It is looping somewhere in
> >> U-Boot's
> >>> __serial_getc(). I wonder how it gets there without returning from
> >> the
> >>> function.
> >>>
> >>> I compiled SDL2.cpp from
> >>> https://gist.github.com/miguelmartin75/6946310#file-sdl2-cpp-L18
> >>> with
> >>>
> >>> g++ SDL2.cpp -D_REENTRANT -I/usr/include/SDL2 -lSDL2 -lGL -o test
> >>>
> >>> and it runs fine showing an X11 windows with red background.
> >>>
> >>> So there seems to be no general problem with the SDL2 library.
> >>
> >> I hit this myself on another computer and it turned out to be that SDL
> >> defined getc(), as does U-Boot, and things get confused. At least I
> >> think it is getc.
> >>
> >> I hacked around with changing the name of getc (I think it was getc)
> >> in U-Boot and the problem went away.
> >
> > Should we include a patched SDL2 with U-Boot for static linking?
> >
>
> I cannot find a symbol getc() nor a reference to it in the SDL
> repository. getc() is defined in stdio.h.
>
> Our getc() takes no argument, while the stdio one wants a FILE *.
>
> But changing the U-Boot definition to "int getc(void *)" does not solve
> the issue.

I just tried it on the machine where it doesn't work:

$ gdb --args /tmp/b/sandbox/u-boot -l -D
GNU gdb (Debian 9.2-1) 9.2
Copyright (C) 2020 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later 
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
.
Find the GDB manual and other documentation resources online at:
.

For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from /tmp/b/sandbox/u-boot...
(gdb) br getc
Breakpoint 1 at 0x5b6d6: getc. (2 locations)
(gdb) r
Starting program: /tmp/b/sandbox/u-boot -l -D
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".


U-Boot 2020.10-rc5-00196-g0ac83d080a0 (Sep 28 2020 - 07:11:52 -0600)

Model: sandbox
DRAM:  128 MiB

Warning: host_lo MAC addresses don't match:
Address in ROM is 1a:34:9b:48:aa:53
Address in environment is 00:00:11:22:33:44
WDT:   Not found!
MMC:

Breakpoint 1, getc () at
/home/sjg/cosarm/src/third_party/u-boot/files/common/console.c:414
414 if (!gd->have_console)
(gdb) up
#1  0x77914d48 in ?? () from /lib/x86_64-linux-gnu/libX11.so.6
(gdb)


So it seems that it is libX11 causing the problem.

I don't think the best fix is to remove getc() from that library,
although I do wonder if it is a bug. Renaming the symbol in U-Boot
with #define (only on sandbox) might be one option.

Regards,
Simon

[PATCH] configs: lx2162a: Enable OPTEE support

[Gaurav Jain]

From: Ruchika Gupta 

Enable support to compile OPTEE driver, access AVB TA
and RPMB API's access via RPC from OPTEE for lx2162

Signed-off-by: Ruchika Gupta 
Signed-off-by: Gaurav Jain 
---
Depends-on:


 configs/lx2162aqds_tfa_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
index 33ca543396..dcf8c4a924 100644
--- a/configs/lx2162aqds_tfa_defconfig
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -93,3 +93,8 @@ CONFIG_CMD_DATE=y
 CONFIG_RTC_PCF2127=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_TA_AVB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_CMD_OPTEE_RPMB=y
-- 
2.17.1

Re: [BUG] sandbox: './u-boot -l ' fails

[Heinrich Schuchardt]

On 28.09.20 06:46, Heinrich Schuchardt wrote:
> Am 28. September 2020 06:24:38 MESZ schrieb Simon Glass :
>> Hi Heinrich,
>>
>> On Sat, 19 Sep 2020 at 13:48, Heinrich Schuchardt 
>> wrote:
>>>
>>> Hello Simon,
>>>
>>> when I try to run ./u-boot -l the sandbox stalls. Shouldn't it run
>> out
>>> of the box?
>>>
>>> $ ./u-boot -l -d arch/sandbox/dts/sandbox.dtb
>>
>> For the record you should be able to use -D to get the same effect as
>> your -d above.
>>
>>>
>>> U-Boot 2020.10-rc4-00018-g21a10244f9-dirty (Sep 19 2020 - 19:55:39
>> +0200)
>>>
>>> Model: sandbox
>>> DRAM:  128 MiB
>>>
>>> Warning: host_lo MAC addresses don't match:
>>> Address in ROM is   26:4b:ca:6c:98:f4
>>> Address in environment is   00:00:11:22:33:44
>>>
>>> Warning: host_virbr0 MAC addresses don't match:
>>> Address in ROM is   ee:3e:c9:ce:1f:9c
>>> Address in environment is   00:00:11:22:33:45
>>>
>>> Warning: host_docker0 MAC addresses don't match:
>>> Address in ROM is   c2:85:07:7b:9a:18
>>> Address in environment is   00:00:11:22:33:46
>>> WDT:   Not found!
>>> MMC:
>>>
>>> No output after this point.
>>>
>>> The problem also exists with U-Boot v2020.07, v2019.10, v2018.11.
>>>
>>> CONFIG_SANDBOX_SDL=y
>>>
>>> SDL_InitSubSystem() never returns. It is looping somewhere in
>> U-Boot's
>>> __serial_getc(). I wonder how it gets there without returning from
>> the
>>> function.
>>>
>>> I compiled SDL2.cpp from
>>> https://gist.github.com/miguelmartin75/6946310#file-sdl2-cpp-L18
>>> with
>>>
>>> g++ SDL2.cpp -D_REENTRANT -I/usr/include/SDL2 -lSDL2 -lGL -o test
>>>
>>> and it runs fine showing an X11 windows with red background.
>>>
>>> So there seems to be no general problem with the SDL2 library.
>>
>> I hit this myself on another computer and it turned out to be that SDL
>> defined getc(), as does U-Boot, and things get confused. At least I
>> think it is getc.
>>
>> I hacked around with changing the name of getc (I think it was getc)
>> in U-Boot and the problem went away.
>
> Should we include a patched SDL2 with U-Boot for static linking?
>

I cannot find a symbol getc() nor a reference to it in the SDL
repository. getc() is defined in stdio.h.

Our getc() takes no argument, while the stdio one wants a FILE *.

But changing the U-Boot definition to "int getc(void *)" does not solve
the issue.

Best regards

Heinrich

[PATCH 3/3] configs: migrate CONFIG_BMP_16/24/32BPP to defconfigs

[Patrick Delaunay]

Done with:
./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP

Signed-off-by: Patrick Delaunay 
---

 configs/apalis_imx6_defconfig  |  1 +
 configs/aristainetos2_defconfig|  1 +
 configs/aristainetos2b_defconfig   |  1 +
 configs/aristainetos2bcsl_defconfig|  1 +
 configs/aristainetos2c_defconfig   |  1 +
 configs/cgtqmx6eval_defconfig  |  1 +
 configs/colibri-imx6ull_defconfig  |  1 +
 configs/colibri_imx6_defconfig |  1 +
 configs/colibri_imx7_defconfig |  1 +
 configs/colibri_imx7_emmc_defconfig|  1 +
 configs/imx6dl_icore_nand_defconfig|  1 +
 configs/imx6q_icore_nand_defconfig |  1 +
 configs/imx6qdl_icore_mmc_defconfig|  1 +
 configs/imx6qdl_icore_nand_defconfig   |  1 +
 configs/imxrt1050-evk_defconfig|  1 +
 configs/khadas-vim3_defconfig  |  3 +++
 configs/khadas-vim3l_defconfig |  3 +++
 configs/libretech-ac_defconfig |  3 +++
 configs/libretech-cc_defconfig |  3 +++
 configs/libretech-s905d-pc_defconfig   |  3 +++
 configs/libretech-s912-pc_defconfig|  3 +++
 configs/m53menlo_defconfig |  1 +
 configs/marsboard_defconfig|  1 +
 configs/mx6cuboxi_defconfig|  1 +
 configs/mx6qsabrelite_defconfig|  1 +
 configs/mx6sabreauto_defconfig |  1 +
 configs/mx6sabresd_defconfig   |  1 +
 configs/mx6ul_14x14_evk_defconfig  |  1 +
 configs/mx6ul_9x9_evk_defconfig|  1 +
 configs/nitrogen6dl2g_defconfig|  1 +
 configs/nitrogen6dl_defconfig  |  1 +
 configs/nitrogen6q2g_defconfig |  1 +
 configs/nitrogen6q_defconfig   |  1 +
 configs/nitrogen6s1g_defconfig |  1 +
 configs/nitrogen6s_defconfig   |  1 +
 configs/novena_defconfig   |  1 +
 configs/odroid-c2_defconfig|  3 +++
 configs/odroid-c4_defconfig|  3 +++
 configs/odroid-n2_defconfig|  3 +++
 configs/opos6uldev_defconfig   |  3 +++
 configs/pico-dwarf-imx7d_defconfig |  1 +
 configs/pico-hobbit-imx7d_defconfig|  1 +
 configs/pico-imx6_defconfig|  1 +
 configs/pico-imx7d_bl33_defconfig  |  1 +
 configs/pico-imx7d_defconfig   |  1 +
 configs/pico-nymph-imx7d_defconfig |  1 +
 configs/pico-pi-imx7d_defconfig|  1 +
 configs/puma-rk3399_defconfig  |  3 +++
 configs/riotboard_defconfig|  1 +
 configs/riotboard_spl_defconfig|  1 +
 configs/s5p4418_nanopi2_defconfig  |  1 +
 configs/sei510_defconfig   |  3 +++
 configs/sei610_defconfig   |  3 +++
 configs/stm32f746-disco_defconfig  |  3 +++
 configs/stm32f769-disco_defconfig  |  3 +++
 configs/stm32mp15_basic_defconfig  |  3 +++
 configs/stm32mp15_dhcom_basic_defconfig|  3 +++
 configs/stm32mp15_dhcor_basic_defconfig|  3 +++
 configs/stm32mp15_trusted_defconfig|  3 +++
 ...rable-x86-conga-qa3-e3845-pcie-x4_defconfig |  1 +
 .../theadorable-x86-conga-qa3-e3845_defconfig  |  1 +
 configs/theadorable-x86-dfi-bt700_defconfig|  1 +
 configs/theadorable_debug_defconfig|  3 +++
 configs/wandboard_defconfig|  1 +
 drivers/video/Kconfig  | 18 ++
 include/configs/advantech_dms-ba16.h   |  1 -
 include/configs/apalis_imx6.h  |  1 -
 include/configs/aristainetos2.h|  1 -
 include/configs/cgtqmx6eval.h  |  1 -
 include/configs/colibri-imx6ull.h  |  1 -
 include/configs/colibri_imx6.h |  1 -
 include/configs/colibri_imx7.h |  1 -
 include/configs/embestmx6boards.h  |  1 -
 include/configs/imx6-engicam.h |  1 -
 include/configs/imxrt1050-evk.h|  1 -
 include/configs/m53menlo.h |  1 -
 include/configs/meson64.h  |  3 ---
 include/configs/mx23evk.h  |  1 -
 include/configs/mx28evk.h  |  1 -
 include/configs/mx51evk.h  |  1 -
 include/configs/mx53loco.h |  1 -
 include/configs/mx6cuboxi.h|  1 -
 include/configs/mx6sabre_common.h  |  1 -
 include/configs/mx6sxsabresd.h |  1 -
 include/configs/mx6ul_14x14_evk.h  |  1 -
 include/configs/mx7dsabresd.h  |  1 -
 include/configs/nitrogen6x.h   |  1 -
 include/configs/novena.h   |  1 

[PATCH 2/3] configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigs

[Patrick Delaunay]

Done with:
./tools/moveconfig.py VIDEO_BMP_RLE8

Signed-off-by: Patrick Delaunay 
---

 README  | 6 --
 configs/apalis_imx6_defconfig   | 1 +
 configs/aristainetos2_defconfig | 1 +
 configs/aristainetos2b_defconfig| 1 +
 configs/aristainetos2bcsl_defconfig | 1 +
 configs/aristainetos2c_defconfig| 1 +
 configs/cgtqmx6eval_defconfig   | 1 +
 configs/cm_fx6_defconfig| 1 +
 configs/colibri-imx6ull_defconfig   | 1 +
 configs/colibri_imx6_defconfig  | 1 +
 configs/colibri_imx7_defconfig  | 1 +
 configs/colibri_imx7_emmc_defconfig | 1 +
 configs/dms-ba16-1g_defconfig   | 1 +
 configs/dms-ba16_defconfig  | 1 +
 configs/imx6dl_icore_nand_defconfig | 1 +
 configs/imx6q_icore_nand_defconfig  | 1 +
 configs/imx6qdl_icore_mmc_defconfig | 1 +
 configs/imx6qdl_icore_nand_defconfig| 1 +
 configs/imxrt1050-evk_defconfig | 1 +
 configs/khadas-vim3_defconfig   | 1 +
 configs/khadas-vim3l_defconfig  | 1 +
 configs/libretech-ac_defconfig  | 1 +
 configs/libretech-cc_defconfig  | 1 +
 configs/libretech-s905d-pc_defconfig| 1 +
 configs/libretech-s912-pc_defconfig | 1 +
 configs/m53menlo_defconfig  | 1 +
 configs/marsboard_defconfig | 1 +
 configs/mx23evk_defconfig   | 1 +
 configs/mx28evk_auart_console_defconfig | 1 +
 configs/mx28evk_defconfig   | 1 +
 configs/mx28evk_nand_defconfig  | 1 +
 configs/mx28evk_spi_defconfig   | 1 +
 configs/mx51evk_defconfig   | 1 +
 configs/mx53loco_defconfig  | 1 +
 configs/mx6cuboxi_defconfig | 1 +
 configs/mx6qsabrelite_defconfig | 1 +
 configs/mx6sabreauto_defconfig  | 1 +
 configs/mx6sabresd_defconfig| 1 +
 configs/mx6sxsabresd_defconfig  | 1 +
 configs/mx6ul_14x14_evk_defconfig   | 1 +
 configs/mx6ul_9x9_evk_defconfig | 1 +
 configs/mx7dsabresd_defconfig   | 1 +
 configs/mx7dsabresd_qspi_defconfig  | 1 +
 configs/nitrogen6dl2g_defconfig | 1 +
 configs/nitrogen6dl_defconfig   | 1 +
 configs/nitrogen6q2g_defconfig  | 1 +
 configs/nitrogen6q_defconfig| 1 +
 configs/nitrogen6s1g_defconfig  | 1 +
 configs/nitrogen6s_defconfig| 1 +
 configs/novena_defconfig| 1 +
 configs/odroid-c2_defconfig | 1 +
 configs/odroid-c4_defconfig | 1 +
 configs/odroid-n2_defconfig | 1 +
 configs/opos6uldev_defconfig| 1 +
 configs/pico-dwarf-imx6ul_defconfig | 1 +
 configs/pico-dwarf-imx7d_defconfig  | 1 +
 configs/pico-hobbit-imx6ul_defconfig| 1 +
 configs/pico-hobbit-imx7d_defconfig | 1 +
 configs/pico-imx6_defconfig | 1 +
 configs/pico-imx7d_bl33_defconfig   | 1 +
 configs/pico-imx7d_defconfig| 1 +
 configs/pico-nymph-imx7d_defconfig  | 1 +
 configs/pico-pi-imx6ul_defconfig| 1 +
 configs/pico-pi-imx7d_defconfig | 1 +
 configs/pxm2_defconfig  | 1 +
 configs/riotboard_defconfig | 1 +
 configs/riotboard_spl_defconfig | 1 +
 configs/rut_defconfig   | 1 +
 configs/sandbox64_defconfig | 1 +
 configs/sandbox_defconfig   | 1 +
 configs/sandbox_flattree_defconfig  | 1 +
 configs/sandbox_spl_defconfig   | 1 +
 configs/sei510_defconfig| 1 +
 configs/sei610_defconfig| 1 +
 configs/stm32f746-disco_defconfig   | 1 +
 configs/stm32f769-disco_defconfig   | 1 +
 configs/stm32mp15_basic_defconfig   | 1 +
 configs/stm32mp15_dhcom_basic_defconfig | 1 +
 configs/stm32mp15_dhcor_basic_defconfig | 1 +
 configs/stm32mp15_trusted_defconfig | 1 +
 configs/tbs2910_defconfig   | 1 +
 configs/wandboard_defconfig | 1 +
 drivers/video/Kconfig   | 7 +++
 include/configs/advantech_dms-ba16.h| 1 -
 include/configs/apalis_imx6.h   | 1 -
 include/configs/aristainetos2.h | 1 -
 include/configs/cgtqmx6eval.h   | 1 -
 include/configs/cm_fx6.h| 2 --
 include/configs/colibri-imx6ull.h   | 1 -
 include/configs/colibri_imx6.h  | 1 -
 include/configs/colibri_imx7.h  | 1 -
 include/configs/embestmx6boards.h   | 1 -
 include/configs/imx6-engicam.h  | 1 -
 include/configs/imxrt1050-evk.h | 1 -
 include/configs/m53menlo.h  | 1 -
 include/configs/meson64.h   | 1 -
 include/configs/mx23evk.h   | 1 -
 include/configs/mx28evk.h   | 1 -
 include/configs/mx51evk.h   | 1 -
 include/configs/mx53loco.h  | 1 -
 include/configs/mx6cuboxi.h | 1 -
 include/configs/mx6sabre_common.h   | 1 -
 include/configs/mx6sxsabresd.h  | 1 -
 include/configs/mx6ul_14x14_evk.h   | 1 -
 

Re: [PATCH] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t

[Kuwano Takahiro]

On 9/25/2020 7:11 PM, Pratyush Yadav wrote:
> On 25/09/20 03:13PM, Pratyush Yadav wrote:
>>> +   if (instr->addr < erasesize) {
>>> +   instr_4k.addr = 0;
>>> +   ret = spi_nor_erase(mtd, _4k);
>>> +   }
>>> +   if (!ret && instr->addr + instr->len >= mtd->size - erasesize) {
>>> +   instr_4k.addr = mtd->size - instr_4k.len;
>>> +   ret = spi_nor_erase(mtd, _4k);
> 
> I missed this before, but say I want to erase all but the last sector on 
> a 64Mb flash. So I would issue an erase from 0x0 with length 0x3fc. 
> So instr->addr + instr->len == 0x3fc. And mtd->size == 0x400 and 
> erasesize == 0x4. So, mtd->size - erasesize == 0x3fc, making 
> this condition true. This means that even if I want to erase all but the 
> last sector I will end up erasing the last 128k as well.
> 
> The '=' needs to be dropped from the comparison.
> 

Thanks for pointing out this. Will fix.

--
Best Regards,
Takahiro Kuwano

Re: [PATCH] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t

[Kuwano Takahiro]

Hi Pratyush,

On 9/25/2020 6:43 PM, Pratyush Yadav wrote:
> Hi,
> 
> On 24/09/20 04:43PM, tkuw584...@gmail.com wrote:
>> From: Takahiro Kuwano 
>>
>> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
>> The datasheet can be found in https://community.cypress.com/docs/DOC-15165
> 
> This link takes me to a registration page where it asks me for my name, 
> email, company name and country, and asks me to consent to a T and a 
> Privacy Policy. I don't want to provide all this information just to be 
> able to review this patch. Please provide a link that is not locked 
> behind a login.
>

We don't have such link. I will send the datasheet to your email address.
  
>> This device family can be configured to non-uniform sector layout, while
>> U-Boot does not support it. To handle this, an erase hook emulates uniform
> 
> For my information, why did you not just implement non-uniform erases 
> like Linux does?
> 

In my understanding, only some of Spansion/Cypress flash parts has non-uniform
so I'm not sure non-uniform support is worth the effort. The S25FL-S family
has 4KB sectors that can be erased by large sector erase command at a time.
I selected this erase hook method because it allows the same usage with the
S25FL-S with small code change. 

>> sector layout. To enable quad mode, using volatile register is recommended
>> for safety. And some other fixups for spi_nor_flash_parameter and mtd_info
>> are added.
>>
>> Tested on Xilinx Zynq-7000 FPGA board.
>>
>> Signed-off-by: Takahiro Kuwano 
>> ---
>>  drivers/mtd/spi/spi-nor-core.c | 137 +
>>  drivers/mtd/spi/spi-nor-ids.c  |  24 ++
>>  drivers/mtd/spi/spi-nor-tiny.c |  73 ++
>>  include/linux/mtd/spi-nor.h|   3 +
>>  4 files changed, 237 insertions(+)
>>
>> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
>> index 0113e70037..ddb1cb6bcc 100644
>> --- a/drivers/mtd/spi/spi-nor-core.c
>> +++ b/drivers/mtd/spi/spi-nor-core.c
>> @@ -329,6 +329,7 @@ static int set_4byte(struct spi_nor *nor, const struct 
>> flash_info *info,
>>  case SNOR_MFR_ISSI:
>>  case SNOR_MFR_MACRONIX:
>>  case SNOR_MFR_WINBOND:
>> +case SNOR_MFR_CYPRESS:
>>  if (need_wren)
>>  write_enable(nor);
>>  
>> @@ -593,6 +594,54 @@ erase_err:
>>  return ret;
>>  }
>>  
>> +#ifdef CONFIG_SPI_FLASH_SPANSION
>> +/*
>> + * Erase for Spansioin/Cypress Flash devices that has overlaid 4KB sectors 
>> at
> 
> Typo. s/Spansioin/Spansion/
> 

Will fix.

>> + * the top and/or bottom.
>> + */
>> +static int spansion_overlaid_erase(struct mtd_info *mtd,
>> +   struct erase_info *instr)
>> +{
>> +struct spi_nor *nor = mtd_to_spi_nor(mtd);
>> +struct erase_info instr_4k;
>> +u8 opcode;
>> +u32 erasesize;
>> +int ret;
>> +
>> +/* Perform default erase operation (non-overlaid portion is erased) */
>> +ret = spi_nor_erase(mtd, instr);
>> +if (ret)
>> +return ret;
> 
> Since I don't have access to the datasheet I'm trying to understand how 
> the device behaves by looking at the code.
> 
> So here you issue an erase of the entire region, but with the regular 
> erase command...
> 
>> +
>> +/* Backup default erase opcode and size */
>> +opcode = nor->erase_opcode;
>> +erasesize = mtd->erasesize;
>> +
>> +/*
>> + * Erase 4KB sectors. Use the possible max length of 4KB sector region.
>> + * The Flash just ignores the command if the address is not configured
>> + * as 4KB sector and reports ready status immediately.
>> + */
>> +instr_4k.len = SZ_128K;
>> +nor->erase_opcode = SPINOR_OP_BE_4K_4B;
>> +mtd->erasesize = SZ_4K;
> 
> ... and then you again issue a erase command but 128k in length this 
> time with the 4k erase opcode.
> 
> The first erase will erase the latter half of the erase block and this 
> will erase the former half, correct?
>

Yes, correct.
 
>> +if (instr->addr < erasesize) {
>> +instr_4k.addr = 0;
>> +ret = spi_nor_erase(mtd, _4k);
> 
> If the erase address is less than the erase block size (256k) then you 
> set the address to 0. Since the only erase block that starts before 256k 
> will be the 0th erase block won't the address already be 0 anyway? So in 
> that case wouldn't checking for `if (instr->addr == 0)` be enough? That 
> would certainly be less cryptic than this.
>

You are right. Will fix. Thanks.
 
>> +}
>> +if (!ret && instr->addr + instr->len >= mtd->size - erasesize) {
>> +instr_4k.addr = mtd->size - instr_4k.len;
>> +ret = spi_nor_erase(mtd, _4k);
> 
> So there is another set of these 4k sectors at the end of the flash. If 
> the erase spans over that region you issue an erase for the last 128k. 
> Ok.
> 
>> +}
>> +
>> +/* Restore erase opcode and size */
>> +nor->erase_opcode = opcode;
>> +mtd->erasesize = erasesize;
>> +
>> +

[PATCH v2 12/12] pci: ls_pcie_g4: Add size check for config resource

[Wasim Khan]

resource "config" is required to have minimum 4KB space
to access all config space of PCI Express EP.

Signed-off-by: Wasim Khan 
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue
- Change size check to 4KB to access PCIe config space

Changes in V3:
- No Change

 drivers/pci/pcie_layerscape_gen4.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/pcie_layerscape_gen4.c 
b/drivers/pci/pcie_layerscape_gen4.c
index 0226bde..6e71173 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
u32 link_ctrl_sta;
u32 val;
int ret;
+   fdt_size_t cfg_size;
 
pcie->bus = dev;
 
@@ -488,6 +489,13 @@ static int ls_pcie_g4_probe(struct udevice *dev)
return ret;
}
 
+   cfg_size = fdt_resource_size(>cfg_res);
+   if (cfg_size < SZ_4K) {
+   printf("PCIe%d: %s Invalid size(0x%llx) for resource 
\"config\",expected minimum 0x%x\n",
+  PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K);
+   return 0;
+   }
+
pcie->cfg = map_physmem(pcie->cfg_res.start,
fdt_resource_size(>cfg_res),
MAP_NOCACHE);
-- 
2.7.4

[PATCH v2 10/12] arm: dts: ls1028a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan 
---
Changes in V2:
- Updated commit description

Changes in V3:
- No Change

 arch/arm/dts/fsl-ls1028a.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 9911690..ccf1a8d 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP ls1028a SOC common device tree source
  *
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  *
  */
 
@@ -85,7 +85,7 @@
status = "disabled";
};
 
-   pcie@340 {
+   pcie1: pcie@340 {
   compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
   reg = <0x00 0x0340 0x0 0x8
   0x00 0x0348 0x0 0x4   /* lut registers */
@@ -101,7 +101,7 @@
   0x8200 0x0 0x4000 0x80 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie@350 {
+   pcie2: pcie@350 {
   compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
   reg = <0x00 0x0350 0x0 0x8
   0x00 0x0358 0x0 0x4   /* lut registers */
-- 
2.7.4

[PATCH v2 09/12] arm: dts: ls1043a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan 
---
Changes in V2:
- Updated commit description

Changes in V3:
- No Change

 arch/arm/dts/fsl-ls1043a.dtsi | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index f7db44c..8ca57ea 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ * Device Tree Include file for NXP Layerscape-1043A family SoC.
  *
+ * Copyright 2020 NXP
  * Copyright (C) 2014-2015, Freescale Semiconductor
  *
  * Mingkai Hu 
@@ -240,7 +241,7 @@
dr_mode = "host";
};
 
-   pcie@340 {
+   pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x1   /* dbi registers */
   0x00 0x0341 0x0 0x1   /* lut registers */
@@ -255,7 +256,7 @@
  0x8200 0x0 0x4000 0x40 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie@350 {
+   pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x1   /* dbi registers */
   0x00 0x0351 0x0 0x1   /* lut registers */
@@ -271,7 +272,7 @@
  0x8200 0x0 0x4000 0x48 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie@360 {
+   pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x1   /* dbi registers */
   0x00 0x0361 0x0 0x1   /* lut registers */
-- 
2.7.4

[PATCH v2 07/12] arm: dts: ls1088a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan 
---
Changes in V2:
- Updated commit description

Changes in V3:
- No Change

 arch/arm/dts/fsl-ls1088a.dtsi | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index bf303c6..8de7998 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP ls1088a SOC common device tree source
  *
- * Copyright 2017 NXP
+ * Copyright 2017, 2020 NXP
  */
 
 / {
@@ -129,7 +129,7 @@
dr_mode = "host";
};
 
-   pcie@340 {
+   pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8   /* dbi registers */
   0x00 0x0348 0x0 0x8   /* lut registers */
@@ -145,7 +145,7 @@
  0x8200 0x0 0x4000 0x20 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie@350 {
+   pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8   /* dbi registers */
   0x00 0x0358 0x0 0x8   /* lut registers */
@@ -161,7 +161,7 @@
  0x8200 0x0 0x4000 0x28 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie@360 {
+   pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8   /* dbi registers */
   0x00 0x0368 0x0 0x8   /* lut registers */
-- 
2.7.4

[PATCH v2 08/12] arm: dts: ls1012a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan 
---
Changes in V2:
- Updated commit description

Changes in V3:
- No Change

 arch/arm/dts/fsl-ls1012a.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 2d70c82..c401ba3 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
+ * Copyright 2020 NXP
  * Copyright 2016 Freescale Semiconductor
  */
 
@@ -116,7 +117,7 @@
status = "disabled";
};
 
-   pcie@340 {
+   pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8   /* dbi registers */
   0x00 0x0348 0x0 0x4   /* lut registers */
-- 
2.7.4

[PATCH v2 11/12] pci: layerscape: Add size check for config resource

[Wasim Khan]

resource "config" is required to have minimum 8KB space
as per hardware documentation.

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Wasim Khan 
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue

Changes in V3:
- Fix compilation issue with ls102xa platforms

 drivers/pci/pcie_layerscape_rc.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index f9e3089..cdfcad6 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -314,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev)
return ret;
}
 
+   cfg_size = fdt_resource_size(_rc->cfg_res);
+   if (cfg_size < SZ_8K) {
+   printf("PCIe%d: %s Invalid size(0x%llx) for resource 
\"config\",expected minimum 0x%x\n",
+  PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size, 
SZ_8K);
+   return 0;
+   }
+
/*
 * Fix the pcie memory map address and PF control registers address
 * for LS2088A series SoCs
@@ -323,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev)
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
svr == SVR_LS2081A || svr == SVR_LS2041A) {
-   cfg_size = fdt_resource_size(_rc->cfg_res);
pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
-- 
2.7.4

[PATCH v2 05/12] arm: dts: ls1046a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan 
---
Changes in V2:
- Updated commit description

Changes in V3:
- No Change

 arch/arm/dts/fsl-ls1046a.dtsi | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 3f11d6c..155455d 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -241,7 +241,7 @@
dr_mode = "host";
};
 
-   pcie@340 {
+   pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8   /* dbi registers */
   0x00 0x0348 0x0 0x4   /* lut registers */
@@ -257,7 +257,7 @@
  0x8200 0x0 0x4000 0x40 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie_ep@340 {
+   pcie_ep1: pcie_ep@340 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x0340 0x0 0x8
   0x00 0x034c 0x0 0x4
@@ -268,7 +268,7 @@
big-endian;
};
 
-   pcie@350 {
+   pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8   /* dbi registers */
   0x00 0x0358 0x0 0x4   /* lut registers */
@@ -285,7 +285,7 @@
  0x8200 0x0 0x4000 0x48 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie_ep@350 {
+   pcie_ep2: pcie_ep@350 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x0350 0x0 0x8
   0x00 0x035c 0x0 0x4
@@ -296,7 +296,7 @@
big-endian;
};
 
-   pcie@360 {
+   pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8   /* dbi registers */
   0x00 0x0368 0x0 0x4   /* lut registers */
@@ -312,7 +312,7 @@
  0x8200 0x0 0x4000 0x50 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie_ep@360 {
+   pcie_ep3: pcie_ep@360 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x0360 0x0 0x8
   0x00 0x036c 0x0 0x4
-- 
2.7.4

[PATCH v2 02/12] pci: layerscape: Print pcie controller number starting from 1

[Wasim Khan]

Print pcie controller number starting from 1

Signed-off-by: Wasim Khan 
---
Changes in V2:
- No Change

Changes in V3:
- No Change

 drivers/pci/pcie_layerscape_ep.c | 4 +++-
 drivers/pci/pcie_layerscape_rc.c | 6 --
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index eba230e..26c04a9 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -294,7 +295,8 @@ static int ls_pcie_ep_probe(struct udevice *dev)
pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  "num-ob-windows", 8);
 
-   printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+   printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+  "Endpoint");
ls_pcie_setup_ep(pcie_ep);
 
if (!ls_pcie_link_up(pcie)) {
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index 25c6dde..f9e3089 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev)
 
pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
if (!pcie_rc->enabled) {
-   printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+   printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+  dev->name);
return 0;
}
 
@@ -342,7 +343,8 @@ static int ls_pcie_probe(struct udevice *dev)
  (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
  pcie->big_endian);
 
-   printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+   printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+  "Root Complex");
ls_pcie_setup_ctrl(pcie_rc);
 
if (!ls_pcie_link_up(pcie)) {
-- 
2.7.4

[PATCH v2 06/12] arm: dts: ls2080a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan 
---
Changes in V2:
- Updated commit description

Changes in V3:
- No Change

 arch/arm/dts/fsl-ls2080a.dtsi | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 90a0a3f..fae46c4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Freescale ls2080a SOC common device tree source
+ * NXP ls2080a SOC common device tree source
  *
+ * Copyright 2020 NXP
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  */
 
@@ -127,7 +128,7 @@
dr_mode = "host";
};
 
-   pcie@340 {
+   pcie1: pcie@340 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0340 0x0 0x8   /* dbi registers */
   0x00 0x0348 0x0 0x8   /* lut registers */
@@ -142,7 +143,7 @@
  0x8200 0x0 0x4000 0x10 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie@350 {
+   pcie2: pcie@350 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0350 0x0 0x8   /* dbi registers */
   0x00 0x0358 0x0 0x8   /* lut registers */
@@ -157,7 +158,7 @@
  0x8200 0x0 0x4000 0x12 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie@360 {
+   pcie3: pcie@360 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0360 0x0 0x8   /* dbi registers */
   0x00 0x0368 0x0 0x8   /* lut registers */
@@ -172,7 +173,7 @@
  0x8200 0x0 0x4000 0x14 0x4000 0x0 
0x4000>; /* non-prefetchable memory */
};
 
-   pcie@370 {
+   pcie4: pcie@370 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x0370 0x0 0x8   /* dbi registers */
   0x00 0x0378 0x0 0x8   /* lut registers */
-- 
2.7.4

[PATCH v2 03/12] pci: ls_pcie_g4: Print pcie controller number starting from 1

[Wasim Khan]

Print pcie controller number starting from 1

Signed-off-by: Wasim Khan 
---
Changes in V2:
- No Change

Changes in V3:
- No Change

 drivers/pci/pcie_layerscape_gen4.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_gen4.c 
b/drivers/pci/pcie_layerscape_gen4.c
index 428bfca..0226bde 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
  *
  * PCIe Gen4 driver for NXP Layerscape SoCs
  * Author: Hou Zhiqiang 
@@ -472,7 +472,8 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 
pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
if (!pcie->enabled) {
-   printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+   printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+  dev->name);
return 0;
}
 
@@ -522,10 +523,12 @@ static int ls_pcie_g4_probe(struct udevice *dev)
pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
 
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
-   printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+   printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+  "Endpoint");
ls_pcie_g4_setup_ep(pcie);
} else {
-   printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+   printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+  "Root Complex");
ls_pcie_g4_setup_ctrl(pcie);
}
 
-- 
2.7.4

[PATCH v2 00/12] Add label to pcie nodes

[Wasim Khan]

This patch series
- Adds label to pcie nodes in dts file for NXP's layerscape SoCs 
- Print the pcie controller number starting from 1 to match RMs
- Add checks for config resource size and fix indendation.

Changes in V2:
- Enable CONFIG_PCIE_LAYERSCAPE_GEN4 to make LX2160A-Rev1 work
- Fix CheckPatch issues
- Change 1KB size check to 4KB size check for ls_pcie_g4.
- Commit description updates

Changes in V3:
- fix compilation issue on ls102xa platforms

Wasim Khan (12):
  configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4
  pci: layerscape: Print pcie controller number starting from 1
  pci: ls_pcie_g4: Print pcie controller number starting from 1
  arm: dts: lx2160a: add label to pcie nodes in dts
  arm: dts: ls1046a: add label to pcie nodes in dts
  arm: dts: ls2080a: add label to pcie nodes in dts
  arm: dts: ls1088a: add label to pcie nodes in dts
  arm: dts: ls1012a: add label to pcie nodes in dts
  arm: dts: ls1043a: add label to pcie nodes in dts
  arm: dts: ls1028a: add label to pcie nodes in dts
  pci: layerscape: Add size check for config resource
  pci: ls_pcie_g4: Add size check for config resource

 arch/arm/dts/fsl-ls1012a.dtsi|  3 ++-
 arch/arm/dts/fsl-ls1028a.dtsi|  6 +++---
 arch/arm/dts/fsl-ls1043a.dtsi|  9 +
 arch/arm/dts/fsl-ls1046a.dtsi| 12 ++--
 arch/arm/dts/fsl-ls1088a.dtsi|  8 
 arch/arm/dts/fsl-ls2080a.dtsi| 11 ++-
 arch/arm/dts/fsl-lx2160a.dtsi| 12 ++--
 configs/lx2160aqds_tfa_SECURE_BOOT_defconfig |  1 +
 configs/lx2160aqds_tfa_defconfig |  1 +
 configs/lx2160ardb_tfa_SECURE_BOOT_defconfig |  1 +
 configs/lx2160ardb_tfa_defconfig |  1 +
 configs/lx2160ardb_tfa_stmm_defconfig|  1 +
 drivers/pci/pcie_layerscape_ep.c |  4 +++-
 drivers/pci/pcie_layerscape_gen4.c   | 19 +++
 drivers/pci/pcie_layerscape_rc.c | 14 +++---
 15 files changed, 66 insertions(+), 37 deletions(-)

-- 
2.7.4

[PATCH v2 01/12] configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4

[Wasim Khan]

LX2160A-Rev1 uses PCIe layerscape Gen4 controller.
Enable CONFIG_PCIE_LAYERSCAPE_GEN4 for lx2160a.

Signed-off-by: Wasim Khan 
---
Changes in V2:
- Added as new commit in V2

Changes in V3:
- No Change

 configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 +
 configs/lx2160aqds_tfa_defconfig | 1 +
 configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 +
 configs/lx2160ardb_tfa_defconfig | 1 +
 configs/lx2160ardb_tfa_stmm_defconfig| 1 +
 5 files changed, 5 insertions(+)

diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig 
b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 06d84be..7aa2f94 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -68,6 +68,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index af010af..a553fa7 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -75,6 +75,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig 
b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 5e30890..7f30922 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -59,6 +59,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 7021223..c882a5a 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -66,6 +66,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig 
b/configs/lx2160ardb_tfa_stmm_defconfig
index b0dc3c0..e07c7a8 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -68,6 +68,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
-- 
2.7.4

[PATCH v2 04/12] arm: dts: lx2160a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan 
---
Changes in V2:
- Updated commit description

Changes in V3:
- No Change

 arch/arm/dts/fsl-lx2160a.dtsi | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index dee1e2f..69fcc0c 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -286,7 +286,7 @@
 
};
 
-   pcie@340 {
+   pcie1: pcie@340 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0340 0x0 0x8   /* PAB registers */
   0x00 0x0348 0x0 0x4   /* LUT registers */
@@ -300,7 +300,7 @@
ranges = <0x8200 0x0 0x4000 0x80 0x4000 0x0 
0x4000>;
};
 
-   pcie@350 {
+   pcie2: pcie@350 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0350 0x0 0x8   /* PAB registers */
   0x00 0x0358 0x0 0x4   /* LUT registers */
@@ -315,7 +315,7 @@
ranges = <0x8200 0x0 0x4000 0x88 0x4000 0x0 
0x4000>;
};
 
-   pcie@360 {
+   pcie3: pcie@360 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0360 0x0 0x8   /* PAB registers */
   0x00 0x0368 0x0 0x4   /* LUT registers */
@@ -329,7 +329,7 @@
ranges = <0x8200 0x0 0x4000 0x90 0x4000 0x0 
0x4000>;
};
 
-   pcie@370 {
+   pcie4: pcie@370 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0370 0x0 0x8   /* PAB registers */
   0x00 0x0378 0x0 0x4   /* LUT registers */
@@ -343,7 +343,7 @@
ranges = <0x8200 0x0 0x4000 0x98 0x4000 0x0 
0x4000>;
};
 
-   pcie@380 {
+   pcie5: pcie@380 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0380 0x0 0x8   /* PAB registers */
   0x00 0x0388 0x0 0x4   /* LUT registers */
@@ -357,7 +357,7 @@
ranges = <0x8200 0x0 0x4000 0xa0 0x4000 0x0 
0x4000>;
};
 
-   pcie@390 {
+   pcie6: pcie@390 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x0390 0x0 0x8   /* PAB registers */
   0x00 0x0398 0x0 0x4   /* LUT registers */
-- 
2.7.4

Pull request for UEFI sub-system for efi-2020-10-rc6

[Heinrich Schuchardt]

Hello Tom,

The following changes since commit 1da91d9bcd6e5ef046c1df0d373d0df87b1e8a72:

  Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
(2020-09-24 08:34:54 -0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
tags/efi-2020-10-rc6

for you to fetch changes up to c48e9f310b950e39a91cea74b6708dd4fe2eb39c:

  riscv: restore global data pointer in trap handler (2020-09-28
12:20:19 +0200)


Pull request for UEFI sub-system for efi-2020-10-rc6

The following UEFI related issues are fixed:

* restore the global data pointer in the RISC-V trap handler
* install EFI_RNG_PROTOCOL only if we have a random number generator
* display human readable string for EFI_RNG_PROTOCOL in efidebug command


Heinrich Schuchardt (3):
  efi_loader: efidebug display RNG protocol
  efi_loader: installation of EFI_RNG_PROTOCOL
  riscv: restore global data pointer in trap handler

 arch/riscv/lib/interrupts.c|  3 +++
 cmd/efidebug.c |  5 +
 include/efi_loader.h   |  3 ++-
 lib/efi_loader/efi_rng.c   | 30 +-
 lib/efi_loader/efi_root_node.c |  4 
 lib/efi_loader/efi_setup.c |  5 +
 6 files changed, 44 insertions(+), 6 deletions(-)

[PULL u-boot] Please pull u-boot-amlogic-20200928

[Neil Armstrong]

Hi Tom,

This PR fixes Linux EFI KASLR boot on GXL, GXM, G12A, G12B & SM1 based boards.

The CI job is at 
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/4642

Thanks,
Neil

The following changes since commit 1da91d9bcd6e5ef046c1df0d373d0df87b1e8a72:

  Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2020-09-24 
08:34:54 -0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git 
tags/u-boot-amlogic-20200928

for you to fetch changes up to 02d249f99ecb7e398067d91760287c61d35fd34b:

  rng: meson: make core clock optional (2020-09-28 09:38:11 +0200)


- fix RNG driver probe & linux EFI KASLR boot on GXL, GXM, G12A, G12B & SM1 
based boards


Neil Armstrong (1):
  rng: meson: make core clock optional

 drivers/rng/meson-rng.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

[PATCH 1/3] configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigs

[Patrick Delaunay]

Done with:
./tools/moveconfig.py VIDEO_BMP_GZIP

The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN
are not activated in these defconfigs:
- trats_defconfig
- s5pc210_universal_defconfig
- trats2_defconfig

Signed-off-by: Patrick Delaunay 
---

 README  | 6 --
 configs/m53menlo_defconfig  | 1 +
 configs/mx23evk_defconfig   | 1 +
 configs/mx28evk_auart_console_defconfig | 1 +
 configs/mx28evk_defconfig   | 1 +
 configs/mx28evk_nand_defconfig  | 1 +
 configs/mx28evk_spi_defconfig   | 1 +
 configs/mx6qsabrelite_defconfig | 1 +
 configs/nitrogen6dl2g_defconfig | 1 +
 configs/nitrogen6dl_defconfig   | 1 +
 configs/nitrogen6q2g_defconfig  | 1 +
 configs/nitrogen6q_defconfig| 1 +
 configs/nitrogen6s1g_defconfig  | 1 +
 configs/nitrogen6s_defconfig| 1 +
 drivers/video/Kconfig   | 8 
 include/configs/m53menlo.h  | 1 -
 include/configs/mx23evk.h   | 1 -
 include/configs/mx28evk.h   | 1 -
 include/configs/nitrogen6x.h| 1 -
 include/configs/s5pc210_universal.h | 1 -
 include/configs/trats.h | 1 -
 include/configs/trats2.h| 1 -
 scripts/config_whitelist.txt| 1 -
 23 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/README b/README
index 6cb0567ba6..5104245082 100644
--- a/README
+++ b/README
@@ -1250,12 +1250,6 @@ The following options need to be configured:
Enables an 'i2c edid' command which can read EDID
information over I2C from an attached LCD display.
 
-- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
-
-   If this option is set, additionally to standard BMP
-   images, gzipped BMP images can be displayed via the
-   splashscreen support or the bmp command.
-
 - Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
 
If this option is set, 8-bit RLE compressed BMP images
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index db3a739af1..26e4a885b3 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -104,5 +104,6 @@ CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASHIMAGE_GUARD=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_SPLASH_SOURCE=y
+CONFIG_VIDEO_BMP_GZIP=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=8000
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 51f4a0fb73..67d8f6754d 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -39,4 +39,5 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_VIDEO=y
 CONFIG_SPLASH_SCREEN=y
+CONFIG_VIDEO_BMP_GZIP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_auart_console_defconfig 
b/configs/mx28evk_auart_console_defconfig
index 6e0a237751..bf81a8c624 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -58,4 +58,5 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
 CONFIG_SPLASH_SCREEN=y
+CONFIG_VIDEO_BMP_GZIP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index abfdb26b2d..1c3db124b9 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -58,4 +58,5 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
 CONFIG_SPLASH_SCREEN=y
+CONFIG_VIDEO_BMP_GZIP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index 8aecb8bd44..ae1d02ae81 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -59,4 +59,5 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
 CONFIG_SPLASH_SCREEN=y
+CONFIG_VIDEO_BMP_GZIP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index c4cba183bf..85d328de66 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -55,4 +55,5 @@ CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_VIDEO=y
 CONFIG_SPLASH_SCREEN=y
+CONFIG_VIDEO_BMP_GZIP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 6e7193e411..9bdafe2372 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -82,3 +82,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_GZIP=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 9615e1f506..fda334173b 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -83,3 +83,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_GZIP=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 695f9be326..2d85352e88 100644
--- a/configs/nitrogen6dl_defconfig

Re: [PATCH v2 1/1] riscv: restore global data pointer in trap handler

[Heinrich Schuchardt]

On 28.09.20 09:45, Rick Chen wrote:
>> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
>> Sent: Sunday, September 27, 2020 4:24 PM
>> To: Rick Jian-Zhi Chen(陳建志)
>> Cc: Simon Glass; Sean Anderson; Bin Meng; u-boot@lists.denx.de; Alexander 
>> Graf; Abner Chang; Heinrich Schuchardt
>> Subject: [PATCH v2 1/1] riscv: restore global data pointer in trap handler
>>
>> The gp register is used to store U-Boot's global data pointer. We should
>> not assume that an UEFI application leaves the gp register unchanged as
>> the UEFI specifications does not define who is the owner of the gp and tp
>> registers.
>>
>> So the following sequence should be followed in the trap handler:
>>
>> * save the caller's gp register
>> * restore the global data pointer
>> * serve interrupts or print crash dump and reset
>> * restore the caller's gp register
>>
>> Cc: Abner Chang 
>> Signed-off-by: Heinrich Schuchardt 
>> ---
>> v2:
>> Saving and restoring the caller's x3 is already handled in mtrap.S.
>> efi_loader.h provides an empty fallback efi_restore_gd() function
>> if CONFIG_EFI_LOADER=n.
>> ---
>>  arch/riscv/lib/interrupts.c | 3 +++
>>  1 file changed, 3 insertions(+)
>
> Reviewed-by: Rick Chen 
>

Hello Rick,

I have two other corrections for the UEFI sub-system and would like to
add this patch to my pull-request for v2020.10. Is that ok with you?

Best regards

Heinrich

Re: U-Boot issue

[Matthias Brugger]

Hi Matteo,

On 16/09/2020 00:27, Heinrich Schuchardt wrote:

On 8/17/20 11:59 AM, 0x5c4r3 wrote:

Hello guys,
I am Matteo Peruzzi, a cyber-security expert.
I am currently working on a project, creating a root of trust on RPI 2
using a TPM2 module and U-Boot.
I noticed that in the latest update, u-boot has an issue: it does not
detect my USB keyboard connected to the RPI (if I use an early version it
works, no problems), so I am not able to interrupt the autobooting and
communicate with u-boot. Are you planning to solve this in further updates?
Also, I am not able to use the UART because it uses the same pins used by
the TPM2 module.

Thanks for your time, if you need more details just text me.


Sorry for the late answer. Can give some details of your USB keyboard. Is it 
just a normal keyboard, or has it touchpad integrated? Is it USB2.0 or older?


Regards,
Matthias



The board/raspberrypi/rpi/MAINTAINERS file provides the right contact.

Cc: Matthias Brugger 



Thanks

Matteo Peruzzi

Re: SPI bus not probed

[Michal Suchánek]

On Sun, Sep 27, 2020 at 10:35:30PM +0200, Michal Suchánek wrote:
> Hello,
> 
> When I enable SPI support I do not get a SPI bus.
> 
> Config:
> --- a/configs/orangepi_zero_defconfig
> +++ b/configs/orangepi_zero_defconfig
> @@ -11,3 +11,21 @@ CONFIG_CONSOLE_MUX=y
>  CONFIG_SUN8I_EMAC=y
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_OHCI_HCD=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_SF_TEST=y
> +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> +CONFIG_SPI_FLASH_ATMEL=y
> +CONFIG_SPI_FLASH_EON=y
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_ISSI=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_SST=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_SPI_FLASH_XMC=y
> +CONFIG_SPI_FLASH_DATAFLASH=y
> 
> DT (which lists the flash types so did not really have to enable them all)
> --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
> +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
> @@ -163,10 +163,11 @@
>  };
>  
>   {
> -   /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */
> -   status = "disabled";
> +   /* Enable SPI NOR by default: it optional on Orange Pi Zero boards */
> +   status = "okay";
>  
> flash@0 {
> +status = "okay";
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "mxicy,mx25l1606e", "winbond,w25q128";
> 
> The guide on debugging says to add dm_dump_all
> --- a/drivers/spi/spi-uclass.c
> +++ b/drivers/spi/spi-uclass.c
> @@ -328,6 +328,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int 
> mode,
> bool created = false;
> int ret;
>  
> +dm_dump_all();
>  #if CONFIG_IS_ENABLED(OF_PLATDATA)
> ret = uclass_first_device_err(UCLASS_SPI, );
>  #else
> 
> which prints
> 
>  Class Index  Probed  DriverName
> ---
>  root  0  [ + ]   root_driver   root_driver
>  simple_bus0  [ + ]   simple_bus|-- soc
>  mmc   0  [ + ]   sunxi_mmc |   |-- mmc@1c0f000
>  blk   0  [   ]   mmc_blk   |   |   `-- m...@1c0f000.blk
>  mmc   1  [ + ]   sunxi_mmc |   |-- mmc@1c1
>  blk   1  [   ]   mmc_blk   |   |   `-- m...@1c1.blk
>  phy   0  [   ]   sun4i_usb_phy |   |-- phy@1c19400
>  usb   0  [   ]   ehci_generic  |   |-- usb@1c1a000
>  usb   1  [   ]   ohci_generic  |   |-- usb@1c1a400
>  usb   2  [   ]   ehci_generic  |   |-- usb@1c1b000
>  usb   3  [   ]   ohci_generic  |   |-- usb@1c1b400
>  clk   0  [ + ]   sun8i_h3_ccu  |   |-- clock@1c2
>  reset 0  [ + ]   sunxi_reset   |   |   `-- reset
>  gpio  0  [ + ]   gpio_sunxi|   |-- pinctrl@1c20800
>  gpio  1  [ + ]   gpio_sunxi|   |   |-- PA
>  gpio  2  [ + ]   gpio_sunxi|   |   |-- PB
>  gpio  3  [ + ]   gpio_sunxi|   |   |-- PC
>  gpio  4  [ + ]   gpio_sunxi|   |   |-- PD
>  gpio  5  [ + ]   gpio_sunxi|   |   |-- PE
>  gpio  6  [ + ]   gpio_sunxi|   |   |-- PF
>  gpio  7  [ + ]   gpio_sunxi|   |   |-- PG
>  gpio  8  [ + ]   gpio_sunxi|   |   |-- PH
>  gpio  9  [ + ]   gpio_sunxi|   |   `-- PI
>  eth   0  [ + ]   eth_sun8i_emac|   |-- ethernet@1c3
>  spi   0  [   ]   sun4i_spi |   |-- spi@1c68000
>  serial0  [ + ]   ns16550_serial|   |-- serial@1c28000
>  gpio 10  [ + ]   gpio_sunxi|   `-- pinctrl@1f02c00
>  gpio 11  [ + ]   gpio_sunxi|   `-- PL
>  clk   1  [ + ]   fixed_rate_clock  |-- osc24M_clk
>  clk   2  [   ]   fixed_rate_clock  `-- osc32k_clk
> Invalid bus 0 (err=-19)
> 
> -19 means ENODEV according to my /usr/include/asm-generic/errno-base.h
> 
> Debug prints added to sunxi driver are never printed:
> 
> --- a/drivers/spi/spi-sunxi.c
> +++ b/drivers/spi/spi-sunxi.c
> @@ -305,6 +305,7 @@ static int sun4i_spi_claim_bus(struct udevice *dev)
>  {
> struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
> int ret;
> +   printf("sun4i_spi_claim_bus\n");
>  
> ret = sun4i_spi_set_clock(dev->parent, true);
> if (ret)
> @@ -487,6 +488,8 @@ static int sun4i_spi_probe(struct udevice *bus)
> struct sun4i_spi_priv *priv = dev_get_priv(bus);
> int ret;
>  
> +   printf("sun4i_spi_probe\n");
> +
> ret = clk_get_by_name(bus, "ahb", >clk_ahb);
> if (ret) {
> dev_err(dev, "failed to get ahb clock\n");
> 
> AFAICT the device tree compatible matches the one in the driver.
> 
> How do I make u-boot run the 

Re: [PATCH v2 1/1] riscv: restore global data pointer in trap handler

[Rick Chen]

> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
> Sent: Sunday, September 27, 2020 4:24 PM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: Simon Glass; Sean Anderson; Bin Meng; u-boot@lists.denx.de; Alexander 
> Graf; Abner Chang; Heinrich Schuchardt
> Subject: [PATCH v2 1/1] riscv: restore global data pointer in trap handler
>
> The gp register is used to store U-Boot's global data pointer. We should
> not assume that an UEFI application leaves the gp register unchanged as
> the UEFI specifications does not define who is the owner of the gp and tp
> registers.
>
> So the following sequence should be followed in the trap handler:
>
> * save the caller's gp register
> * restore the global data pointer
> * serve interrupts or print crash dump and reset
> * restore the caller's gp register
>
> Cc: Abner Chang 
> Signed-off-by: Heinrich Schuchardt 
> ---
> v2:
> Saving and restoring the caller's x3 is already handled in mtrap.S.
> efi_loader.h provides an empty fallback efi_restore_gd() function
> if CONFIG_EFI_LOADER=n.
> ---
>  arch/riscv/lib/interrupts.c | 3 +++
>  1 file changed, 3 insertions(+)

Reviewed-by: Rick Chen 

Re: [PATCH 0/8] ARM: mach-meson: update & rework USB for GXL, GXM & AXG

[Neil Armstrong]

On 10/09/2020 10:48, Neil Armstrong wrote:
> This serie follows the recent work under Linux to rework and update support of
> the USB complex in the Amlogic GXL, GXM & AXG SoCs.
> 
> This rework follows the clean implementation for the G12A & following SoCs to 
> support
> Host, Device & OTG functionnality.
> 
> The GXL, GXM & AXG USB complex is architectured in the same was as the G12A & 
> later USB complex,
> thus we can use the same architecture but adapted to the different init & 
> config flow found
> in the Amlogic GXL, GXM & AXG SoCs.
> 
> With this patchset, USB Host functionnality is retained, working & tested on 
> the Khadas VIM2 (GXM),
> Libretech-CC (GXL) & S400 (AXG), with Device mode added and tested by using 
> the UMS gadget.
> 
> Neil Armstrong (8):
>   ARM: dts: sync amlogic AXG/GXL/GXM DT from Linux 5.8-rc1
>   usb: dwc3: add Amlogic GXL & GXL DWC3 Glue
>   ARM: mach-meson: use new DWC3 glue for GXL & GXM
>   phy: meson-gxl: remove invalid USB3 PHY driver
>   phy: meson-gxl-usb: depend on Meson AXG aswell
>   arm: meson-axg: add board_usb_init()/cleanup() for USB gadget
>   ARM: dts: meson-axg: add USB nodes for S400
>   configs: s400: enable USB
> 
>  arch/arm/dts/meson-axg-s400-u-boot.dtsi   |  12 +
>  arch/arm/dts/meson-axg-u-boot.dtsi|  62 +++
>  arch/arm/dts/meson-axg.dtsi   |   6 +-
>  arch/arm/dts/meson-gx-libretech-pc.dtsi   |  78 +++-
>  arch/arm/dts/meson-gx.dtsi|  23 +-
>  arch/arm/dts/meson-gxbb-nanopi-k2.dts |   2 +-
>  arch/arm/dts/meson-gxbb-odroidc2.dts  |   2 +-
>  arch/arm/dts/meson-gxbb.dtsi  |  23 +
>  .../meson-gxl-s805x-libretech-ac-u-boot.dtsi  |   4 -
>  arch/arm/dts/meson-gxl-s805x-libretech-ac.dts |  73 ++-
>  .../meson-gxl-s905d-libretech-pc-u-boot.dtsi  |   4 -
>  .../meson-gxl-s905x-khadas-vim-u-boot.dtsi|   4 -
>  arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |   4 +
>  .../meson-gxl-s905x-libretech-cc-u-boot.dtsi  |   4 -
>  arch/arm/dts/meson-gxl-s905x-libretech-cc.dts |  77 +++-
>  arch/arm/dts/meson-gxl-s905x-p212.dtsi|   3 +-
>  arch/arm/dts/meson-gxl-u-boot.dtsi|  16 -
>  arch/arm/dts/meson-gxl.dtsi   |  79 +++-
>  .../arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi |   4 -
>  arch/arm/dts/meson-gxm-khadas-vim2.dts|   3 +-
>  .../meson-gxm-s912-libretech-pc-u-boot.dtsi   |   4 -
>  arch/arm/dts/meson-gxm.dtsi   |   7 +-
>  arch/arm/include/asm/arch-meson/usb-gx.h  |   3 +-
>  arch/arm/mach-meson/board-axg.c   | 128 ++
>  arch/arm/mach-meson/board-gx.c| 127 +++---
>  configs/khadas-vim2_defconfig |   2 +-
>  configs/khadas-vim_defconfig  |   2 +-
>  configs/libretech-ac_defconfig|   2 +-
>  configs/libretech-cc_defconfig|   2 +-
>  configs/libretech-s905d-pc_defconfig  |   2 +-
>  configs/libretech-s912-pc_defconfig   |   2 +-
>  configs/p212_defconfig|   2 +-
>  configs/s400_defconfig|  15 +
>  drivers/phy/Kconfig   |   2 +-
>  drivers/phy/Makefile  |   2 +-
>  drivers/phy/meson-gxl-usb3.c  | 219 -
>  drivers/usb/dwc3/Kconfig  |   8 +
>  drivers/usb/dwc3/Makefile |   1 +
>  drivers/usb/dwc3/dwc3-meson-gxl.c | 425 ++
>  .../reset/amlogic,meson-gxbb-reset.h  |   2 +-
>  include/dt-bindings/sound/meson-aiu.h |  18 +
>  41 files changed, 1092 insertions(+), 366 deletions(-)
>  create mode 100644 arch/arm/dts/meson-axg-u-boot.dtsi
>  delete mode 100644 drivers/phy/meson-gxl-usb3.c
>  create mode 100644 drivers/usb/dwc3/dwc3-meson-gxl.c
>  create mode 100644 include/dt-bindings/sound/meson-aiu.h
> 

Applied to u-boot-amlogic-next

Re: [PATCH v2 0/4] amlogic: vim3: add support for dynamic PCIe enable

[Neil Armstrong]

On 21/09/2020 09:34, Neil Armstrong wrote:
> The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
> lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
> an USB3.0 Type A connector and a M.2 Key M slot.
> The PHY driving these differential lines is shared between
> the USB3.0 controller and the PCIe Controller, thus only
> a single controller can use it.
> 
> This serie adds a VIM3 specific board support and adds this dynamic
> switching right before booting Linux.
> 
> Changes since v1:
> - add missing khadas-mcu.h
> - add documentation to switch pcie on/off
> 
> Neil Armstrong (4):
>   ARM: dts: sync amlogic G12A/SM1 DT from Linux 5.9-rc1
>   board: amlogic: add a vim3 specific board support
>   configs: vim3: use the vim3 board support
>   board: amlogic: vim3: add support for dynamic PCIe enable
> 
>  arch/arm/dts/meson-g12-common.dtsi|  55 ---
>  arch/arm/dts/meson-g12b-odroid-n2.dts | 136 +-
>  arch/arm/dts/meson-khadas-vim3.dtsi   |  26 +++-
>  arch/arm/dts/meson-sm1-khadas-vim3l.dts   |  92 
>  arch/arm/dts/meson-sm1-odroid-c4.dts  |  88 
>  board/amlogic/vim3/MAINTAINERS|   9 ++
>  board/amlogic/vim3/Makefile   |   6 +
>  board/amlogic/vim3/khadas-mcu.h   |  81 +++
>  board/amlogic/vim3/vim3.c | 136 ++
>  board/amlogic/w400/MAINTAINERS|   4 -
>  configs/khadas-vim3_defconfig |   5 +-
>  configs/khadas-vim3l_defconfig|   5 +-
>  doc/board/amlogic/khadas-vim3.rst |  27 
>  doc/board/amlogic/khadas-vim3l.rst|  27 
>  include/dt-bindings/clock/g12a-clkc.h |   2 +
>  .../dt-bindings/sound/meson-g12a-toacodec.h   |  10 ++
>  16 files changed, 679 insertions(+), 30 deletions(-)
>  create mode 100644 board/amlogic/vim3/MAINTAINERS
>  create mode 100644 board/amlogic/vim3/Makefile
>  create mode 100644 board/amlogic/vim3/khadas-mcu.h
>  create mode 100644 board/amlogic/vim3/vim3.c
>  create mode 100644 include/dt-bindings/sound/meson-g12a-toacodec.h
> 

Applied to u-boot-amlogic-next

Re: [PATCH] board: s400: generate unique mac address from SoC serial

[Neil Armstrong]

On 10/09/2020 10:50, Neil Armstrong wrote:
> Enable unique mac address generation from SoC serial on S400 board.
> 
> Signed-off-by: Neil Armstrong 
> ---
>  board/amlogic/s400/s400.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c
> index 7e2f0cdae3..b081942dcc 100644
> --- a/board/amlogic/s400/s400.c
> +++ b/board/amlogic/s400/s400.c
> @@ -18,5 +18,7 @@ int misc_init_r(void)
>  {
>   meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
>  
> + meson_generate_serial_ethaddr();
> +
>   return 0;
>  }
> 

Applied to u-boot-amlogic-next

Re: [PATCH] rng: meson: make core clock optional

[Neil Armstrong]

On 25/09/2020 09:19, Neil Armstrong wrote:
> This fixes HWRNG support on Amlogic GXL, GXM, G12A, G12B & SM1
> based boards dues to the lack of the core clock in the device tree.
> 
> It was reported breaking EFI boot in the Linux EFI stub, because the
> EFI_RNG_PROTOCOL didn't check for the RNG device presence before
> installing itself.
> 
> The Linux amlogic,meson-rng.yaml doesn't mandate the core clock,
> this the clock should be ignores if not present.
> 
> Nevertheless, the clock should be present and this should be fixed
> on the Linux meson-gxl.dtsi & meson-g12-common.dtsi then synced
> with U-Boot.
> 
> The change has been tested on a Khadas VIM3, which uses the common
> meson-g12-common.dtsi like the Odroid-C4 & Odroid-N2 in Scott's
> report, along with the RNG cmd.
> 
> Cc: Heinrich Schuchardt 
> Reported-by: Scott K Logan 
> Fixes: bc40eb278b ("drivers/rng: add Amlogic hardware RNG driver")
> Signed-off-by: Neil Armstrong 
> ---
>  drivers/rng/meson-rng.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/rng/meson-rng.c b/drivers/rng/meson-rng.c
> index 4b81a62353..57a5a702a2 100644
> --- a/drivers/rng/meson-rng.c
> +++ b/drivers/rng/meson-rng.c
> @@ -90,8 +90,9 @@ static int meson_rng_ofdata_to_platdata(struct udevice *dev)
>   if (!pdata->base)
>   return -ENODEV;
>  
> + /* Get optional "core" clock */
>   err = clk_get_by_name(dev, "core", >clk);
> - if (err)
> + if (err && err != -ENODATA)
>   return err;
>  
>   return 0;
> 


Applied to u-boot-amlogic

Neil

Re: [patch 0/8] RFC: Pinebook pro EDP support

[Rtp]

Alper Nebi Yasak  writes:

Hi,

> On 25/09/2020 21:36, Arnaud Patard (Rtp) wrote:
>> This patchset add support for the rk3399 edp. It has been tested on the 
>> pinebook
>> pro devices. The only missing part is a hack used to get stable edp output 
>> after
>> a warn reset, which is possibly specific to this device. I'm not sure if 
>> it's suitable
>> for merge.
>> 
>> The changes have been written by studying the linux code, since I didn't 
>> find any
>> manual for theses part of the RK3399 SoC.
>> 
>> On the linux kernel side, on recent kernels, it needs commit "pwm: rockchip: 
>> Keep enabled PWMs
>> running while probing" otherwise the pinebook pro will freeze when probing
>> the display.
>> 
>> The kernel is also randomly failing to display something on my device. When 
>> this
>> occurs, the kernel has this following message:
>> rockchip-pm-domain ff31.power-management:power-controller: failed to set 
>> idle on domain 'pd_vopl', val=0
>> I've yet to find what's the issue.
>
> I've been trying to test your patches on a rk3399-gru-kevin with these
> patches and as a result I've posted some patches for cros_ec_pwm as a
> backlight [1], and have some yet-to-be-posted ones for kevin and bob
> because I don't truly know if they work [2]. (I don't even have the
> appropriate hardware to get a serial console / debug this board, thus
> the motivation to get the screen working).
>
> It should be possible for someone with a kevin or bob to tinker on my
> test branch and get more conclusive outcomes than I did, maybe even get
> everything fully working!
>
> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=204353
> [2] https://github.com/alpernebbi/u-boot/commits/rk3399-gru-kevin/wip
>
>
> Anyway, here's how it goes for me. I start from the Chrome OS firmware
> showing some white-background bitmap on the screen with the backlight
> enabled. I press CTRL+L to tell it to chainload my U-Boot build. I don't
> know if/how chainloading this way affects any of this.
>
> AFAICT, the firmware doesn't clear or turn off the backlight before
> doing so, because when VIDEO_ROCKCHIP_MAX_{X,Y}RES={3840,2160} the
> screen doesn't clear. I have to set {2400,1600} as it's the resolution
> of my panel. Maybe you should test this on Pinebook Pro as well, the
> defaults are {1920,1080} (same as its panel), but DISPLAY_ROCKCHIP_HDMI
> for example would change it.

Here, it's set to 1920x1080, and I have CONFIG_DISPLAY_ROCKCHIP_HDMI
disabled, since there's no HDMI output on the PBP. Can you try with the
screen size set to the one of your panel and disable the HDMI output ?
I suspect it won't change anything, but worth trying.

>
> With those initial conditions I see the the screen progressively
> clearing to black then the backlight turns off after a while. I think
> the clearing part hints this patchset is at least doing something.

I see that you've added the needed rockchip,panel properties, so it's
possible it's related to the driver but I'm surprised that the
blacklight turns off. iirc, the driver is only turning it on.

>
> I had also tried commenting out "enable-gpios" code in pwm_backlight.c
> (when I didn't really know how to turn it on properly), that results in
> the backlight turn on immediately after it turns off, where I see a
> small white artifact (?) on the mid-right part of the bottom of the
> screen, for a frame or so.
>
> Overall, I never see any content on the display and it's always black.
> Even unsetting CONFIG_SYS_WHITE_ON_BLACK doesn't change anything.
>
> Wish I could've been more helpful, but all this is as far as I could
> figure out right now.

Some logs would be nice. If USB is working or if the laptop has
ethernet, maybe you could try netconsole (doc/README.NetConsole) with
CONSOLE_MUX. I've not used that for ages, but there's no reason for it
to be broken.

btw, I'm not sure what's the current practice in uboot m-l, but maybe we
can go on debugging your issue off-list ?

Arnaud

Re: [PATCH 05/32] x86: Allow writing tables to fail

[Heinrich Schuchardt]

Am 28. September 2020 06:25:44 MESZ schrieb Simon Glass :
>At present write_tables() can fail but does not report this problem to
>its
>caller. Fix this by changing the return type.
>
>Signed-off-by: Simon Glass 
>---
>
> arch/x86/cpu/cpu.c| 7 ++-
> arch/x86/include/asm/tables.h | 4 +++-
> arch/x86/lib/tables.c | 5 -
> 3 files changed, 13 insertions(+), 3 deletions(-)
>
>diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
>index f8692753963..5c33f02f034 100644
>--- a/arch/x86/cpu/cpu.c
>+++ b/arch/x86/cpu/cpu.c
>@@ -200,6 +200,7 @@ __weak void board_final_cleanup(void)
> int last_stage_init(void)
> {
>   struct acpi_fadt __maybe_unused *fadt;
>+  int ret;
> 
>   board_final_init();
> 
>@@ -210,7 +211,11 @@ int last_stage_init(void)
>   acpi_resume(fadt);
>   }
> 
>-  write_tables();
>+  ret = write_tables();
>+  if (ret) {
>+  printf("Failed to write tables\n");
>+  return log_msg_ret("table", ret);
>+  }

If we have print available, shouldn't we also have log?

> 
>   if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
>   fadt = acpi_find_fadt();
>diff --git a/arch/x86/include/asm/tables.h
>b/arch/x86/include/asm/tables.h
>index f7c72ed3db0..bf66e79018e 100644
>--- a/arch/x86/include/asm/tables.h
>+++ b/arch/x86/include/asm/tables.h
>@@ -49,8 +49,10 @@ void table_fill_string(char *dest, const char *src,
>size_t n, char pad);
>  * This writes x86 configuration tables, including PIRQ routing table,
>  * Multi-Processor table and ACPI table. Whether a specific type of
>  * configuration table is written is controlled by a Kconfig option.
>+ *
>+ * @return 0 if OK, -ENOSPC if table too large
>  */
>-void write_tables(void);
>+int write_tables(void);
> 
> /**
>  * write_pirq_routing_table() - Write PIRQ routing table
>diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
>index 7bad5dd3032..7099866a78a 100644
>--- a/arch/x86/lib/tables.c
>+++ b/arch/x86/lib/tables.c
>@@ -64,7 +64,7 @@ void table_fill_string(char *dest, const char *src,
>size_t n, char pad)
>   dest[i] = pad;
> }
> 
>-void write_tables(void)
>+int write_tables(void)
> {
>   u32 rom_table_start = ROM_TABLE_ADDR;
>   u32 rom_table_end;
>@@ -91,6 +91,7 @@ void write_tables(void)
>   cfg_tables[i].size = table_size;
>   } else {
>   printf("%d: no memory for configuration tables\n", i);
>+  return -ENOSPC;
>   }
> #endif
> 
>@@ -105,4 +106,6 @@ void write_tables(void)
>   write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
> #endif
>   debug("- done writing tables\n");
>+
>+  return 0;
> }