Re: [PATCH V2 0/3] arm: omap3: Make functions static when possible
On 18/03/21 6:10 pm, Adam Ford wrote: > A few functions are defined without being labeled as static > to that file. In an effort to keep SPL as small as possible, > one function needs to be moved into an #ifdef so it's only enabled > when the calling function is available, and all of these can simply be > marked as static. I see some failures with this series. Can you take a look: https://source.denx.de/u-boot/custodians/u-boot-ti/-/jobs/254794 Thanks and regards, Lokesh > > Before: >text data bss dec hex filename > 50988 10531888 53929d2a9 spl/u-boot-spl > > After: >text data bss dec hex filename > 50972 10531888 53913d299 spl/u-boot-spl > > While not significant, a few bytes can be very helpful when SPL is limited. > > Adam Ford (3): > arm: omap3: Make try_unlock_memory() static > arm: omap3: Make secureworld_exit() static > arm: omap3: Make secure_unlock_mem() static > > arch/arm/include/asm/arch-omap3/sys_proto.h | 2 -- > arch/arm/mach-omap2/omap3/board.c | 21 +++-- > 2 files changed, 11 insertions(+), 12 deletions(-) >
[PATCH] checkpatch: Ignore ENOSYS warnings
There are no system calls in U-Boot, but ENOSYS is still allowed (and
preferred since 42a2668743 ("dm: core: Document the common error codes")).
Silence this warning.
Signed-off-by: Sean Anderson
Seriies-to: sjg
---
.checkpatch.conf | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.checkpatch.conf b/.checkpatch.conf
index ed0c2150ba..9e40ea060b 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -26,6 +26,9 @@
# addresses are __aligned(2)".
--ignore PREFER_ETHER_ADDR_COPY
+# ENOSYS is a conventionally used error, even though U-Boot lacks system calls.
+--ignore ENOSYS
+
# A bit shorter of a description is OK with us.
--min-conf-desc-length=2
--
2.31.0
[PATCH 11/11] test: Add K210 PLL tests to sandbox defconfigs
This adds the unit test for the K210 PLL to the sandbox defconfigs. Signed-off-by: Sean Anderson --- configs/sandbox64_defconfig| 2 ++ configs/sandbox_defconfig | 2 ++ configs/sandbox_flattree_defconfig | 2 ++ 3 files changed, 6 insertions(+) diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 4648808d51..cbaf80a004 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -106,6 +106,8 @@ CONFIG_AXI_SANDBOX=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK=y +CONFIG_CLK_K210=y +CONFIG_CLK_K210_SET_RATE=y CONFIG_CPU=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 5da8d1679e..c44843f0b8 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -129,6 +129,8 @@ CONFIG_BUTTON_GPIO=y CONFIG_CLK=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_SCMI=y +CONFIG_CLK_K210=y +CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y CONFIG_DM_DEMO=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index b68f938cb3..5dce6b5523 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -86,6 +86,8 @@ CONFIG_AXI=y CONFIG_AXI_SANDBOX=y CONFIG_CLK=y CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_K210=y +CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y CONFIG_DM_DEMO=y -- 2.31.0
[PATCH 09/11] k210: dts: Set PLL1 to the same rate as PLL0
Linux has had some stability issues when using AISRAM with a different frequency from SRAM. Mirror their change here now that we relocate into AISRAM. Signed-off-by: Sean Anderson --- arch/riscv/dts/k210.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 2492af8038..8bcd3cebde 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -501,6 +501,8 @@ #clock-cells = <1>; compatible = "kendryte,k210-clk"; clocks = <>; + assigned-clocks = < K210_CLK_PLL1>; + assigned-clock-rates = <39000>; u-boot,dm-pre-reloc; }; -- 2.31.0
[PATCH 10/11] k210: Don't imply CCF
Now that the k210 clock driver does not depend on CCF, we should no longer imply it (and probably should not have in the first place). We can also reduce the pre-relocation malloc arena back to something sensible. Signed-off-by: Sean Anderson --- board/sipeed/maix/Kconfig | 2 -- configs/sipeed_maix_bitm_defconfig | 1 - 2 files changed, 3 deletions(-) diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig index adf6abb572..b1d7a7ad93 100644 --- a/board/sipeed/maix/Kconfig +++ b/board/sipeed/maix/Kconfig @@ -37,8 +37,6 @@ config BOARD_SPECIFIC_OPTIONS imply SIFIVE_CLINT imply POWER_DOMAIN imply SIMPLE_PM_BUS - imply CLK_CCF - imply CLK_COMPOSITE_CCF imply CLK_K210 imply DM_RESET imply RESET_SYSCON diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index bd877cd055..4903476961 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -1,5 +1,4 @@ CONFIG_RISCV=y -CONFIG_SYS_MALLOC_F_LEN=0x1 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0xfff000 CONFIG_ENV_SECT_SIZE=0x1000 -- 2.31.0
[PATCH 08/11] clk: k210: Move k210 clock out of its own subdirectory
Now that we have only one clock driver, we don't need to have our own
subdirectory. Move the driver back with the rest of the clock drivers.
The MAINTAINERS for kendryte pinctrl is also fixed since it has always been
wrong.
Signed-off-by: Sean Anderson
---
MAINTAINERS| 4 ++--
drivers/clk/Kconfig| 14 +-
drivers/clk/Makefile | 2 +-
drivers/clk/{kendryte/clk.c => clk_kendryte.c} | 0
drivers/clk/kendryte/Kconfig | 12
drivers/clk/kendryte/Makefile | 1 -
6 files changed, 16 insertions(+), 17 deletions(-)
rename drivers/clk/{kendryte/clk.c => clk_kendryte.c} (100%)
delete mode 100644 drivers/clk/kendryte/Kconfig
delete mode 100644 drivers/clk/kendryte/Makefile
diff --git a/MAINTAINERS b/MAINTAINERS
index c6dd9bf838..74a915a269 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -995,8 +995,8 @@ M: Sean Anderson
S: Maintained
F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
F: doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt
-F: drivers/clk/kendryte/
-F: drivers/pinctrl/kendryte/
+F: drivers/clk/clk_kendryte.c
+F: drivers/pinctrl/pinctrl-kendryte.c
F: include/kendryte/
RNG
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4aeaa0cd58..6c61e3019f 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -159,11 +159,23 @@ config CLK_SCMI
by a SCMI agent based on SCMI clock protocol communication
with a SCMI server.
+config CLK_K210
+ bool "Clock support for Kendryte K210"
+ depends on CLK
+ help
+ This enables support clock driver for Kendryte K210 platforms.
+
+config CLK_K210_SET_RATE
+ bool "Enable setting the Kendryte K210 PLL rate"
+ depends on CLK_K210
+ help
+ Add functionality to calculate new rates for K210 PLLs. Enabling this
+ feature adds around 1K to U-Boot's final size.
+
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
-source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 645709b855..f06164bb49 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
-obj-$(CONFIG_CLK_K210) += kendryte/
+obj-$(CONFIG_CLK_K210) += clk_kendryte.o
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/clk_kendryte.c
similarity index 100%
rename from drivers/clk/kendryte/clk.c
rename to drivers/clk/clk_kendryte.c
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
deleted file mode 100644
index 0dc8e3f889..00
--- a/drivers/clk/kendryte/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-config CLK_K210
- bool "Clock support for Kendryte K210"
- depends on CLK
- help
- This enables support clock driver for Kendryte K210 platforms.
-
-config CLK_K210_SET_RATE
- bool "Enable setting the Kendryte K210 PLL rate"
- depends on CLK_K210
- help
- Add functionality to calculate new rates for K210 PLLs. Enabling this
- feature adds around 1K to U-Boot's final size.
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
deleted file mode 100644
index 0303c0b99c..00
--- a/drivers/clk/kendryte/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += clk.o
--
2.31.0
[PATCH 06/11] clk: k210: Don't set PLL rates if we are already at the correct rate
This speeds up boot by preventing multiple reconfigurations of the PLLs.
Signed-off-by: Sean Anderson
---
drivers/clk/kendryte/clk.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index cdea3d6f2b..8e845db7eb 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -847,21 +847,22 @@ static ulong k210_pll_set_rate(struct k210_clk_priv
*priv, int id, ulong rate,
const struct k210_pll_params *pll = _plls[id];
struct k210_pll_config config = {};
u32 reg;
+ ulong calc_rate;
if (rate_in < 0)
return rate_in;
- log_debug("Calculating parameters with rate=%lu and rate_in=%lu\n",
- rate, rate_in);
err = k210_pll_calc_config(rate, rate_in, );
if (err)
return err;
log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
- /*
-* Don't use clk_disable as it might not actually disable the pll due to
-* refcounting
-*/
+ /* Don't bother setting the rate if we're already at that rate */
+ calc_rate = DIV_ROUND_DOWN_ULL(((u64)rate_in) * config.f,
+ config.r * config.od);
+ if (calc_rate == k210_pll_get_rate(priv, id, rate))
+ return calc_rate;
+
k210_pll_disable(priv, id);
reg = readl(priv->base + pll->off);
@@ -875,7 +876,7 @@ static ulong k210_pll_set_rate(struct k210_clk_priv *priv,
int id, ulong rate,
| FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
writel(reg, priv->base + pll->off);
- err = k210_pll_enable(priv, id);
+ k210_pll_enable(priv, id);
serial_setbrg();
return k210_pll_get_rate(priv, id, rate);
--
2.31.0
[PATCH 07/11] clk: k210: Remove bypass driver
This driver no longer serves a purpose now that we have moved away from
CCF. Drop it.
Signed-off-by: Sean Anderson
---
drivers/clk/kendryte/Makefile | 2 +-
drivers/clk/kendryte/bypass.c | 273 --
include/kendryte/bypass.h | 31
3 files changed, 1 insertion(+), 305 deletions(-)
delete mode 100644 drivers/clk/kendryte/bypass.c
delete mode 100644 include/kendryte/bypass.h
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index 6710a1db72..0303c0b99c 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += bypass.o clk.o
+obj-y += clk.o
diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
deleted file mode 100644
index bbdbd9a10d..00
--- a/drivers/clk/kendryte/bypass.c
+++ /dev/null
@@ -1,273 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 Sean Anderson
- */
-
-#define LOG_CATEGORY UCLASS_CLK
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#define CLK_K210_BYPASS "k210_clk_bypass"
-
-/*
- * This is a small driver to do a software bypass of a clock if hardware bypass
- * is not working. I have tried to write this in a generic fashion, so that it
- * could be potentially broken out of the kendryte code at some future date.
- *
- * Say you have the following clock configuration
- *
- * +---+ +---+
- * |osc| |pll|
- * +---+ +---+
- * ^
- */|
- * / |
- * / |
- * / |
- */|
- * +---+ +---+
- * |clk| |clk|
- * +---+ +---+
- *
- * But the pll does not have a bypass, so when you configure the pll, the
- * configuration needs to change to look like
- *
- * +---+ +---+
- * |osc| |pll|
- * +---+ +---+
- * ^
- * |\
- * | \
- * | \
- * | \
- * |\
- * +---+ +---+
- * |clk| |clk|
- * +---+ +---+
- *
- * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
- * creating the child clocks, set their parent to the bypass clock. After
- * creating all the children, call k210_bypass_setchildren().
- */
-
-static int k210_bypass_dobypass(struct k210_bypass *bypass)
-{
- int ret, i;
-
- /*
-* If we already have saved parents, then the children are already
-* bypassed
-*/
- if (bypass->child_count && bypass->saved_parents[0])
- return 0;
-
- for (i = 0; i < bypass->child_count; i++) {
- struct clk *child = bypass->children[i];
- struct clk *parent = clk_get_parent(child);
-
- if (IS_ERR(parent)) {
- for (; i; i--)
- bypass->saved_parents[i] = NULL;
- return PTR_ERR(parent);
- }
- bypass->saved_parents[i] = parent;
- }
-
- for (i = 0; i < bypass->child_count; i++) {
- struct clk *child = bypass->children[i];
-
- ret = clk_set_parent(child, bypass->alt);
- if (ret) {
- for (; i; i--)
- clk_set_parent(bypass->children[i],
- bypass->saved_parents[i]);
- for (i = 0; i < bypass->child_count; i++)
- bypass->saved_parents[i] = NULL;
- return ret;
- }
- }
-
- return 0;
-}
-
-static int k210_bypass_unbypass(struct k210_bypass *bypass)
-{
- int err, ret, i;
-
- if (!bypass->child_count && !bypass->saved_parents[0]) {
- log_warning("Cannot unbypass children; dobypass not called
first\n");
- return 0;
- }
-
- ret = 0;
- for (i = 0; i < bypass->child_count; i++) {
- err = clk_set_parent(bypass->children[i],
-bypass->saved_parents[i]);
- if (err)
- ret = err;
- bypass->saved_parents[i] = NULL;
- }
- return ret;
-}
-
-static ulong k210_bypass_get_rate(struct clk *clk)
-{
- struct k210_bypass *bypass = to_k210_bypass(clk);
- const struct clk_ops *ops = bypass->bypassee_ops;
-
- if (ops->get_rate)
- return ops->get_rate(bypass->bypassee);
- else
- return clk_get_parent_rate(bypass->bypassee);
-}
-
-static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret;
- struct k210_bypass *bypass = to_k210_bypass(clk);
- const struct clk_ops *ops = bypass->bypassee_ops;
-
- /* Don't bother bypassing if we aren't going to set the rate */
- if (!ops->set_rate)
- return k210_bypass_get_rate(clk);
-
- ret = k210_bypass_dobypass(bypass);
- if (ret)
- return ret;
-
- ret = ops->set_rate(bypass->bypassee, rate);
- if (ret < 0)
- return ret;
-
- return k210_bypass_unbypass(bypass);
[PATCH 02/11] clk: k210: Rewrite to remove CCF
This is effectively a complete rewrite to remove all dependency on CCF.
The code is now smaller, and so is the binary (TODO: numbers). It also
takes up less memory at runtime (since we don't have to create 40
udevices). In general, I am much happier with this driver as much of the
complexity and late binding has been removed.
The k210_*_params structs which were previously used to initialize CCF
clocks are now used as the complete configuration. Since we can write our
own division logic, we can now do away with several "half" clocks which
only existed to provide constant factors of two.
The clock IDs have been renumbered to remove unused clocks. This may not be
the last time they are renumbered, since we have diverged with Linux. There
are also still a few clocks left out which may need to be added back in.
In general, I have tried to leave out behavioral changes. However, there is
a small bugfix regarding ACLK. According to the technical reference manual,
its mux comes *after* its divider (which is present only for PLL0). This
would have required yet another intermediate clock to fix with CCF, but
with the new driver it is just 2 lines of code :)
Signed-off-by: Sean Anderson
---
drivers/clk/kendryte/Kconfig| 2 +-
drivers/clk/kendryte/clk.c | 848 +++-
drivers/clk/kendryte/pll.c | 114 ++--
include/dt-bindings/clock/k210-sysctl.h | 94 ++-
include/kendryte/pll.h | 26 +-
5 files changed, 499 insertions(+), 585 deletions(-)
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
index 073fca0781..0dc8e3f889 100644
--- a/drivers/clk/kendryte/Kconfig
+++ b/drivers/clk/kendryte/Kconfig
@@ -1,6 +1,6 @@
config CLK_K210
bool "Clock support for Kendryte K210"
- depends on CLK && CLK_CCF && CLK_COMPOSITE_CCF
+ depends on CLK
help
This enables support clock driver for Kendryte K210 platforms.
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 2d6ac03693..34e8e742a6 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -4,7 +4,7 @@
*/
#include
-#include
+#include
#include
#include
#include
@@ -14,77 +14,6 @@
#include
#include
-/* All methods are delegated to CCF clocks */
-
-static ulong k210_clk_get_rate(struct clk *clk)
-{
- struct clk *c;
- int err = clk_get_by_id(clk->id, );
-
- if (err)
- return err;
- return clk_get_rate(c);
-}
-
-static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *c;
- int err = clk_get_by_id(clk->id, );
-
- if (err)
- return err;
- return clk_set_rate(c, rate);
-}
-
-static int k210_clk_set_parent(struct clk *clk, struct clk *parent)
-{
- struct clk *c, *p;
- int err = clk_get_by_id(clk->id, );
-
- if (err)
- return err;
-
- err = clk_get_by_id(parent->id, );
- if (err)
- return err;
-
- return clk_set_parent(c, p);
-}
-
-static int k210_clk_endisable(struct clk *clk, bool enable)
-{
- struct clk *c;
- int err = clk_get_by_id(clk->id, );
-
- if (err)
- return err;
- return enable ? clk_enable(c) : clk_disable(c);
-}
-
-static int k210_clk_enable(struct clk *clk)
-{
- return k210_clk_endisable(clk, true);
-}
-
-static int k210_clk_disable(struct clk *clk)
-{
- return k210_clk_endisable(clk, false);
-}
-
-static const struct clk_ops k210_clk_ops = {
- .set_rate = k210_clk_set_rate,
- .get_rate = k210_clk_get_rate,
- .set_parent = k210_clk_set_parent,
- .enable = k210_clk_enable,
- .disable = k210_clk_disable,
-};
-
-/* Parents for muxed clocks */
-static const char * const generic_sels[] = { "in0_half", "pll0_half" };
-/* The first clock is in0, which is filled in by k210_clk_probe */
-static const char *aclk_sels[] = { NULL, "pll0_half" };
-static const char *pll2_sels[] = { NULL, "pll0", "pll1" };
-
/*
* All parameters for different sub-clocks are collected into parameter arrays.
* These parameters are then initialized by the clock which uses them during
@@ -97,68 +26,113 @@ static const char *pll2_sels[] = { NULL, "pll0", "pll1" };
* easy to find bugs in the code.
*/
-#define DIV(id, off, shift, width) DIV_FLAGS(id, off, shift, width, 0)
+/**
+ * enum k210_clk_div_type - The type of divider
+ * @K210_DIV_ONE: freq = parent / (reg + 1)
+ * @K210_DIV_EVEN: freq = parent / 2 / (reg + 1)
+ * @K210_DIV_POWER: freq = parent / (2 << reg)
+ * @K210_DIV_FIXED: freq = parent / factor
+ */
+enum k210_clk_div_type {
+ K210_DIV_ONE,
+ K210_DIV_EVEN,
+ K210_DIV_POWER,
+ K210_DIV_FIXED,
+};
+
+/**
+ * struct k210_div_params - Parameters for dividing clocks
+ * @type: An k210_clk_div_type specifying the dividing formula
+ * @off: The offset of the divider from the sysctl base address
+ * @shift: The offset of the
[PATCH 03/11] clk: k210: Move pll into the rest of the driver
Now that there no separate PLL driver, we can no longer make the PLL
functions static. By moving the PLL driver in with the rest of the clock
code, we can make these functions static again. We still keep the pll
header for unit testing, but it is pretty reduced.
Signed-off-by: Sean Anderson
---
drivers/clk/kendryte/Makefile | 2 +-
drivers/clk/kendryte/clk.c| 606 +-
drivers/clk/kendryte/pll.c| 587
include/kendryte/clk.h| 35 --
include/kendryte/pll.h| 34 --
5 files changed, 601 insertions(+), 663 deletions(-)
delete mode 100644 drivers/clk/kendryte/pll.c
delete mode 100644 include/kendryte/clk.h
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index 6fb68253ae..6710a1db72 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += bypass.o clk.o pll.o
+obj-y += bypass.o clk.o
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 34e8e742a6..de9db84361 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -2,17 +2,30 @@
/*
* Copyright (C) 2019-20 Sean Anderson
*/
-#include
+#define LOG_CATEGORY UCLASS_CLK
#include
-#include
-#include
+#include
+#include
+#include
#include
#include
#include
-
-#include
+#include
+#include
+#include
#include
+#include
+
+/**
+ * struct k210_clk_priv - K210 clock driver private data
+ * @base: The base address of the sysctl device
+ * @in0: The "in0" external oscillator
+ */
+struct k210_clk_priv {
+ void __iomem *base;
+ struct clk in0;
+};
/*
* All parameters for different sub-clocks are collected into parameter arrays.
@@ -248,6 +261,30 @@ static const struct k210_mux_params k210_muxes[] = {
#undef MUX
#undef MUX_LIST
+/**
+ * struct k210_pll_params - K210 PLL parameters
+ * @off: The offset of the PLL from the base sysctl address
+ * @shift: The offset of the LSB of the lock status
+ * @width: The number of bits in the lock status
+ */
+struct k210_pll_params {
+ u8 off;
+ u8 shift;
+ u8 width;
+};
+
+static const struct k210_pll_params k210_plls[] = {
+#define PLL(_off, _shift, _width) { \
+ .off = (_off), \
+ .shift = (_shift), \
+ .width = (_width), \
+}
+ [0] = PLL(K210_SYSCTL_PLL0, 0, 2),
+ [1] = PLL(K210_SYSCTL_PLL1, 8, 1),
+ [2] = PLL(K210_SYSCTL_PLL2, 16, 1),
+#undef PLL
+};
+
/**
* enum k210_clk_flags - The type of a K210 clock
* @K210_CLKF_MUX: This clock has a mux and not a static parent
@@ -286,7 +323,6 @@ struct k210_clk_params {
};
};
-
static const struct k210_clk_params k210_clks[] = {
#if CONFIG_IS_ENABLED(CMD_CLK)
#define NAME(_name) .name = (_name),
@@ -382,6 +418,564 @@ static const struct k210_clk_params k210_clks[] = {
#undef CLK_LIST
};
+#define K210_PLL_CLKR GENMASK(3, 0)
+#define K210_PLL_CLKF GENMASK(9, 4)
+#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */
+#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */
+#define K210_PLL_RESET BIT(20)
+#define K210_PLL_PWRD BIT(21) /* PoWeReD */
+#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */
+#define K210_PLL_BYPASSBIT(23)
+#define K210_PLL_TEST BIT(24)
+#define K210_PLL_ENBIT(25)
+#define K210_PLL_TEST_EN BIT(26)
+
+#define K210_PLL_LOCK 0
+#define K210_PLL_CLEAR_SLIP2
+#define K210_PLL_TEST_OUT 3
+
+#ifdef CONFIG_CLK_K210_SET_RATE
+static int k210_pll_enable(struct k210_clk_priv *priv, int id);
+static int k210_pll_disable(struct k210_clk_priv *priv, int id);
+static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong
rate_in);
+
+/*
+ * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
+ * General-Purpose PLL. The logical layout of the PLL with internal feedback is
+ * approximately the following:
+ *
+ * +---+
+ * |reference clock|
+ * +---+
+ * |
+ * v
+ *+--+
+ *|/r|
+ *+--+
+ * |
+ * v
+ * +-+
+ * |divided clock|
+ * +-+
+ * |
+ * v
+ * +--+
+ * |phase detector|<---+
+ * +--+|
+ * | |
+ * v +--+
+ *+---+ |feedback clock|
+ *|VCO| +--+
+ *+---+ ^
+ * |+--+ |
+ * +--->|/f|---+
+ * |+--+
+ * v
+ *+---+
+ *|/od|
+ *+---+
+ * |
+ * v
+ * +--+
+ * |output|
+ * +--+
+ *
+ * The k210 PLLs have three factors: r, f, and od. Because of the feedback
mode,
+ * the effect of the division by f is to multiply the input frequency. The
+ * equation for the output rate is
+ * rate = (rate_in * f) / (r * od).
+ * Moving knowns to one
[PATCH 05/11] clk: k210: Re-add support for setting rate
This adds support for setting clock rates, which was left out of the
initial CCF expunging. There are several tricky bits here, mostly related
to the PLLS:
* The PLL's bypass is broken. If the PLL is reconfigured, any child clocks
will be stopped.
* PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent
stopping the CPU while we configure PLL0's rate, ACLK is reparented
to IN0 while PLL0 is disabled.
* PLL1 is the parent of the AISRAM clock. This clock cannot be reparented,
so we instead just disallow changing PLL1's rate after relocation (when
we are using the AISRAM).
Signed-off-by: Sean Anderson
---
drivers/clk/kendryte/clk.c | 88 +++---
1 file changed, 83 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 203d5f741c..cdea3d6f2b 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -17,6 +17,8 @@
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
/**
* struct k210_clk_priv - K210 clock driver private data
* @base: The base address of the sysctl device
@@ -1059,11 +1061,6 @@ static ulong k210_clk_get_rate(struct clk *clk)
return do_k210_clk_get_rate(dev_get_priv(clk->dev), clk->id);
}
-static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- return -ENOSYS;
-}
-
static int do_k210_clk_set_parent(struct k210_clk_priv *priv, int id, int new)
{
int i;
@@ -1089,6 +1086,81 @@ static int k210_clk_set_parent(struct clk *clk, struct
clk *parent)
parent->id);
}
+static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ int parent, ret, err;
+ ulong rate_in, val;
+ const struct k210_div_params *div;
+ struct k210_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id == K210_CLK_IN0)
+ return clk_set_rate(>in0, rate);
+
+ parent = k210_clk_get_parent(priv, clk->id);
+ rate_in = do_k210_clk_get_rate(priv, parent);
+
+ log_debug("id=%ld rate=%lu rate_in=%lu\n", clk->id, rate, rate_in);
+
+ if (clk->id == K210_CLK_PLL0) {
+ /* Bypass ACLK so the CPU keeps going */
+ ret = do_k210_clk_set_parent(priv, K210_CLK_ACLK, K210_CLK_IN0);
+ if (ret)
+ return ret;
+ } else if (clk->id == K210_CLK_PLL1 && gd->flags & GD_FLG_RELOC) {
+ /*
+* We can't bypass the AI clock like we can ACLK, and after
+* relocation we are using the AI ram.
+*/
+ return -EPERM;
+ }
+
+ if (k210_clks[clk->id].flags & K210_CLKF_PLL) {
+ ret = k210_pll_set_rate(priv, k210_clks[clk->id].pll, rate,
+ rate_in);
+ if (!IS_ERR_VALUE(ret) && clk->id == K210_CLK_PLL0) {
+ /*
+* This may have the side effect of reparenting ACLK,
+* but I don't really want to keep track of what the old
+* parent was.
+*/
+ err = do_k210_clk_set_parent(priv, K210_CLK_ACLK,
+K210_CLK_PLL0);
+ if (err)
+ return err;
+ }
+ return ret;
+ }
+
+ if (k210_clks[clk->id].div == K210_CLK_DIV_NONE)
+ return -ENOSYS;
+ div = _divs[k210_clks[clk->id].div];
+
+ switch (div->type) {
+ case K210_DIV_ONE:
+ val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, rate);
+ val = val ? val - 1 : 0;
+ break;
+ case K210_DIV_EVEN:
+ val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, 2 * rate);
+ break;
+ case K210_DIV_POWER:
+ /* This is ACLK, which has no divider on IN0 */
+ if (parent == K210_CLK_IN0)
+ return -ENOSYS;
+
+ DIV_ROUND_CLOSEST_ULL((u64)rate_in, rate);
+ val = __ffs(val);
+ break;
+ default:
+ assert(false);
+ return -EINVAL;
+ };
+
+ val = val ? val - 1 : 0;
+ k210_clk_writel(priv, div->off, div->shift, div->width, val);
+ return do_k210_clk_get_rate(priv, clk->id);
+}
+
static int k210_clk_endisable(struct k210_clk_priv *priv, int id, bool enable)
{
int parent = k210_clk_get_parent(priv, id);
@@ -1163,6 +1235,12 @@ static int k210_clk_probe(struct udevice *dev)
if (ret)
return ret;
+ /*
+* Force setting defaults, even before relocation. This is so we can
+* set the clock rate for PLL1 before we relocate into aisram.
+*/
+ clk_set_defaults(dev, 2);
+
return 0;
}
--
2.31.0
[PATCH 04/11] clk: k210: Implement soc_clk_dump
Since we are no longer using CCF we cannot use the default soc_clk_dump.
Instead, implement our own.
Signed-off-by: Sean Anderson
---
drivers/clk/kendryte/clk.c | 68 --
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index de9db84361..203d5f741c 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -925,14 +925,19 @@ static void k210_pll_waitfor_lock(struct k210_clk_priv
*priv, int id)
}
}
+static bool k210_pll_enabled(u32 reg)
+{
+ return (reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
+ !(reg & K210_PLL_RESET);
+}
+
/* Adapted from sysctl_pll_enable */
static int k210_pll_enable(struct k210_clk_priv *priv, int id)
{
const struct k210_pll_params *pll = _plls[id];
u32 reg = readl(priv->base + pll->off);
- if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
- !(reg & K210_PLL_RESET))
+ if (k210_pll_enabled(reg))
return 0;
reg |= K210_PLL_PWRD;
@@ -1174,3 +1179,62 @@ U_BOOT_DRIVER(k210_clk) = {
.probe = k210_clk_probe,
.priv_auto = sizeof(struct k210_clk_priv),
};
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+static char show_enabled(struct k210_clk_priv *priv, int id)
+{
+ bool enabled;
+
+ if (k210_clks[id].flags & K210_CLKF_PLL) {
+ const struct k210_pll_params *pll =
+ _plls[k210_clks[id].pll];
+
+ enabled = k210_pll_enabled(readl(priv->base + pll->off));
+ } else if (k210_clks[id].gate == K210_CLK_GATE_NONE) {
+ return '-';
+ } else {
+ const struct k210_gate_params *gate =
+ _gates[k210_clks[id].gate];
+
+ enabled = k210_clk_readl(priv, gate->off, gate->bit_idx, 1);
+ }
+
+ return enabled ? 'y' : 'n';
+}
+
+static void show_clks(struct k210_clk_priv *priv, int id, int depth)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(k210_clks); i++) {
+ if (k210_clk_get_parent(priv, i) != id)
+ continue;
+
+ printf(" %-9lu %-7c %*s%s\n", do_k210_clk_get_rate(priv, i),
+ show_enabled(priv, i), depth * 4, "",
+ k210_clks[i].name);
+
+ show_clks(priv, i, depth + 1);
+ }
+}
+
+int soc_clk_dump(void)
+{
+ int ret;
+ struct udevice *dev;
+ struct k210_clk_priv *priv;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(k210_clk),
+ );
+ if (ret)
+ return ret;
+ priv = dev_get_priv(dev);
+
+ puts(" Rate Enabled Name\n");
+ puts("\n");
+ printf(" %-9lu %-7c %*s%s\n", clk_get_rate(>in0), 'y', 0, "",
+ priv->in0.dev->name);
+ show_clks(priv, K210_CLK_IN0, 1);
+ return 0;
+}
+#endif
--
2.31.0
[PATCH 01/11] clk: Allow force setting clock defaults before relocation
Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc
state for SPL only") it has been impossible to set clock defaults before
relocation. This is annoying on boards without SPL, since there is no way
to set clock defaults before U-Boot proper. In particular, the aisram rate
must be changed before relocation on the K210, since U-Boot will hang if we
try and change the rate while we are using aisram.
To get around this, (ab)use the stage parameter to force setting defaults,
even if they would be otherwise posponed for later. A device tree property
was decided against because of the concerns in the original commit thread
about the overhead of repeatedly parsing the device tree.
Signed-off-by: Sean Anderson
---
drivers/clk/clk-uclass.c | 9 +++--
include/clk.h| 4 +++-
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 53e7be764d..cf8d35b04b 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -353,9 +353,14 @@ int clk_set_defaults(struct udevice *dev, int stage)
if (!dev_has_ofnode(dev))
return 0;
- /* If this not in SPL and pre-reloc state, don't take any action. */
+ /*
+* To avoid setting defaults twice, don't set them before relocation.
+* However, still set them for SPL. And still set them if explicitly
+* asked.
+*/
if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
- return 0;
+ if (stage <= 1)
+ return 0;
debug("%s(%s)\n", __func__, dev_read_name(dev));
diff --git a/include/clk.h b/include/clk.h
index ca6b85fa6f..2021eb0506 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -287,7 +287,9 @@ static inline int clk_release_all(struct clk *clk, int
count)
* will be processed).
* @stage: A integer. 0 indicates that this is called before the device
* is probed. 1 indicates that this is called just after the
- * device has been probed
+ * device has been probed. 2 indicates that this is called after
+ * the device has been probed, and that defaults should still be
+ * set even if they would otherwise be ignored.
*/
int clk_set_defaults(struct udevice *dev, int stage);
#else
--
2.31.0
[PATCH 00/11] clk: k210: Rewrite K210 clock without CCF
This is something I've been meaning to do for a while but only just got around to. The CCF has been quite unwieldy in a few ways: * It is very rigid, and there are not easy ways to hook into it without rewriting many things. See e.g. things like the bypass clock and all the _half clocks which were created because CCF didn't support the dividers used on the k210. While preparing this series, I encountered several edge cases which I had initially overlooked (or which were not supported in the initial release). These would have been very difficult to fix with CCF, but were much easier to address be * There is a lot of magic going on under the curtains because of all the CCF code which lives in many different files. Some things live in drivers, but many things live in e.g. clk-uclass.c. So many things live in so many files and it can be very difficult to get a handle on what exactly happens. Complicating this is that there is a conflation of struct clk as a handle and struct clk as a device. In this regard, refcounting is completely broken. IMO we should just do away with refcounts and only disable clocks when explicitly asked for. * It is very dependent on runtime initialization. Typically, everything is initialized by calling into various register() functions, usually with several wrappers to avoid specifying all the arguments. This balloons the runtime memory usage since there are so many devices created. It also makes it hard to debug, since if you do it the "typical" way it is easy to accidentally assign a clock to the wrong register. * It inflates code size by pulling in not just some dead code (e.g. this driver does not use divider tables but they are in clk-divider anyway) but also pulling in numerous imx-specific clocks. This could be fixed, but I don't want to due to the other reasons listed. I am very happy to have completely excised it from my driver. IMO there should be big warning signs on the CCF warning not to use it for new code. This would hopefully dissuade those like myself who had no idea that CCF was *not* in fact a good way to write a clock driver. Overall there is a total savings of 12k from this series. Before: textdata bss dec hex filename 292485 32672 12624 337781 52775 u-boot After: textdata bss dec hex filename 283125 29856 12624 325605 4f7e5 u-boot This series depends on https://patchwork.ozlabs.org/project/uboot/list/?series=238211 Sean Anderson (11): clk: Allow force setting clock defaults before relocation clk: k210: Rewrite to remove CCF clk: k210: Move pll into the rest of the driver clk: k210: Implement soc_clk_dump clk: k210: Re-add support for setting rate clk: k210: Don't set PLL rates if we are already at the correct rate clk: k210: Remove bypass driver clk: k210: Move k210 clock out of its own subdirectory k210: dts: Set PLL1 to the same rate as PLL0 k210: Don't imply CCF test: Add K210 PLL tests to sandbox defconfigs MAINTAINERS |4 +- arch/riscv/dts/k210.dtsi|2 + board/sipeed/maix/Kconfig |2 - configs/sandbox64_defconfig |2 + configs/sandbox_defconfig |2 + configs/sandbox_flattree_defconfig |2 + configs/sipeed_maix_bitm_defconfig |1 - drivers/clk/Kconfig | 14 +- drivers/clk/Makefile|2 +- drivers/clk/clk-uclass.c|9 +- drivers/clk/clk_kendryte.c | 1319 +++ drivers/clk/kendryte/Kconfig| 12 - drivers/clk/kendryte/Makefile |1 - drivers/clk/kendryte/bypass.c | 273 - drivers/clk/kendryte/clk.c | 668 drivers/clk/kendryte/pll.c | 585 -- include/clk.h |4 +- include/dt-bindings/clock/k210-sysctl.h | 94 +- include/kendryte/bypass.h | 31 - include/kendryte/clk.h | 35 - include/kendryte/pll.h | 34 - 21 files changed, 1399 insertions(+), 1697 deletions(-) create mode 100644 drivers/clk/clk_kendryte.c delete mode 100644 drivers/clk/kendryte/Kconfig delete mode 100644 drivers/clk/kendryte/Makefile delete mode 100644 drivers/clk/kendryte/bypass.c delete mode 100644 drivers/clk/kendryte/clk.c delete mode 100644 drivers/clk/kendryte/pll.c delete mode 100644 include/kendryte/bypass.h delete mode 100644 include/kendryte/clk.h -- 2.31.0
Re: [PATCH 2/2] net: fec: Only unregister MII bus if we registered it
On Fri, Apr 9, 2021 at 12:10 AM Sean Anderson wrote:
>
> If we fail to probe for whatever reason, we cannot unregister/free the
> MII bus unless we registered it with fec_get_miibus. This fixes FECs
> sharing an MDIO bus from destroying it, preventing the other FEC from
> using it.
>
> Fixes: 6a895d039b ("net: Update eQos driver and FEC driver to use eth phy
> interfaces")
>
> Signed-off-by: Sean Anderson
> ---
>
> drivers/net/fec_mxc.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 37eb894248..a64ba955a5 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -1355,6 +1355,7 @@ static void fec_gpio_reset(struct fec_priv *priv)
>
> static int fecmxc_probe(struct udevice *dev)
> {
> + bool dm_mii_bus = true;
> struct eth_pdata *pdata = dev_get_plat(dev);
> struct fec_priv *priv = dev_get_priv(dev);
> struct mii_dev *bus = NULL;
> @@ -1462,6 +1463,7 @@ static int fecmxc_probe(struct udevice *dev)
> #endif
>
> if (!bus) {
> + dm_mii_bus = false;
> #ifdef CONFIG_FEC_MXC_MDIO_BASE
> bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
> dev_seq(dev));
> @@ -1507,8 +1509,10 @@ static int fecmxc_probe(struct udevice *dev)
> return 0;
>
> err_phy:
> - mdio_unregister(bus);
> - free(bus);
> + if (!dm_mii_bus) {
> + mdio_unregister(bus);
> + free(bus);
> + }
> err_mii:
> err_timeout:
> fec_free_descs(priv);
> --
> 2.25.1
>
Reviewed-by: Ramon Fried
Re: [PATCH 1/2] net: fec: Don't use disabled phys
On Fri, Apr 9, 2021 at 12:10 AM Sean Anderson wrote:
>
> If a phy is disabled, don't use it. This matches Linux's behavior.
>
> Signed-off-by: Sean Anderson
> ---
>
> drivers/net/fec_mxc.c | 13 -
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index ec21157d71..37eb894248 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -1299,15 +1299,18 @@ static const struct eth_ops fecmxc_ops = {
> static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
> {
> struct ofnode_phandle_args phandle_args;
> - int reg;
> + int reg, ret;
>
> - if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> - _args)) {
> - debug("Failed to find phy-handle");
> - return -ENODEV;
> + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> +_args);
> + if (ret) {
> + debug("Failed to find phy-handle (err = %d\n)");
> + return ret;
> }
>
> priv->phy_of_node = phandle_args.node;
> + if (!ofnode_is_available(phandle_args.node))
> + return -ENOENT;
>
> reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
>
> --
> 2.25.1
>
Reviewed-by: Ramon Fried
Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
Hi Bin and Sean,
While we keep the consistency of cache control discussion going, later
today I'd like to send the v5 patch which is not directly relevant to
cache control.
Regards,
Green
On Sun, Apr 11, 2021 at 11:43 PM Sean Anderson wrote:
>
> On 4/9/21 12:05 PM, Green Wan wrote:
> > Hi folks,
> >
> > Correct me if I'm wrong, like Rick mentioned, i/dcache
> > enable/disable() is only called on the main hart. Right now the dummy
> > i/dcache enable/disable are empty and shared among all riscv CPU. The
> > ax25 is the only one that has its own implementation for now.
>
> Right, so why are caches are disabled on all harts before booting Linux
> on ax25? Is there a requirement for this on ax25 which that other
> platforms (which have always-on caches like k210, or which have
> non-disableable caches like fuX40) do not have?
>
> --Sean
>
> >
> > FU540/FU740 also leverages the dummy i/dcache enable/disable()
> > functions (only main hart calls them). L2 cache on FU540/FU740 is
> > enabled as SRAM purpose. And according to the HW design behavior, once
> > L2 is enabled, it can't be disabled unless doing a reset.[1] The Linux
> > L2$ driver will handle that according to the configuration of L2
> > registers.
> >
> > [1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf
> >
> > Thanks,
> >
> > On Fri, Apr 9, 2021 at 9:18 PM Sean Anderson wrote:
> >>
> >> On 4/9/21 4:16 AM, Rick Chen wrote:
> >>> Hi Sean ,Bin
> >>>
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, April 06, 2021 5:16 PM
> To: Sean Anderson
> Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel;
> Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim;
> U-Boot Mailing List
> Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init
> each core
>
> On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson wrote:
> >
> > On 3/30/21 1:26 AM, Green Wan wrote:
> >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
> >> allow different riscv hart perform setup code for each hart as early
> >> as possible. Since all the harts enter the callback, they must be able
> >> to run the same setup.
> >>
> >> Signed-off-by: Green Wan
> >> ---
> >> arch/riscv/cpu/cpu.c | 15 +++
> >> arch/riscv/cpu/start.S | 14 ++
> >> 2 files changed, 29 insertions(+)
> >>
> >> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> >> index 85592f5bee..1652e51137 100644
> >> --- a/arch/riscv/cpu/cpu.c
> >> +++ b/arch/riscv/cpu/cpu.c
> >> @@ -140,3 +140,18 @@ int arch_early_init_r(void)
> >> {
> >> return riscv_cpu_probe();
> >> }
> >> +
> >> +/**
> >> + * riscv_hart_early_init() - A dummy function called by
> >> + * ./arch/riscv/cpu/start.S to allow to disable/enable features of
> >> each core.
> >> + * For example, turn on or off the functional block of CPU harts.
> >> + *
> >> + * In a multi-core system, this function must not access shared
> >> resources.
> >> + *
> >> + * Any access to such resources would probably be better done with
> >> + * available_harts_lock held. However, I doubt that any such access
> >> will be
> >> + * necessary.
> >> + */
> >> +__weak void riscv_hart_early_init(void)
> >> +{
> >> +}
> >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> >> index 8589509e01..ab73008f23 100644
> >> --- a/arch/riscv/cpu/start.S
> >> +++ b/arch/riscv/cpu/start.S
> >> @@ -117,6 +117,20 @@ call_board_init_f_0:
> >> mv sp, a0
> >> #endif
> >>
> >> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> >> + /*
> >> + * Jump to riscv_hart_early_init() to perform init for each
> >> core. Not
> >> + * expect to access gd since gd is not initialized. All
> >> operations in the
> >> + * function should affect core itself only. In multi-core
> >> system, any access
> >> + * to common resource or registers outside core should be
> >> avoided or need a
> >> + * protection for multicore.
> >> + *
> >> + * A dummy implementation is provided in ./arch/riscv/cpu/cpu.c.
> >> + */
> >> +call_riscv_hart_early_init:
> >> + jal riscv_hart_early_init
> >> +#endif
> >> +
> >
> > I wonder if we could move the calls to icache_enable and dcache_enable
> > into this function. Though this would have the consequence of enabling
> > caches on all harts for CPUs which previously only enabled them for the
> > boot hart. I think ax25 is the only CPU which currently does this. Bin,
> > would this be an issue?
> >>>
> >>> No, they are functions shall be called in different stage about lottery.
> >>> riscv_hart_early_init() is called before lottery for all harts.
> >>> It shall
Re: [PATCH V2 09/24] imx: power-domain: Add fsl, imx8mn-gpc compatible string
On 4/12/21 1:28 AM, Marek Vasut wrote:
> The driver is compatible with iMX8MN, add missing compatible string.
>
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: Ye Li
> Cc: uboot-imx
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon chung
> ---
> V2: New patch
> ---
> drivers/power/domain/imx8m-power-domain.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/power/domain/imx8m-power-domain.c
> b/drivers/power/domain/imx8m-power-domain.c
> index ebac90d81c..5d34bc1290 100644
> --- a/drivers/power/domain/imx8m-power-domain.c
> +++ b/drivers/power/domain/imx8m-power-domain.c
> @@ -121,6 +121,7 @@ static int imx8m_power_domain_of_to_plat(struct udevice
> *dev)
> static const struct udevice_id imx8m_power_domain_ids[] = {
> { .compatible = "fsl,imx8mq-gpc" },
> { .compatible = "fsl,imx8mm-gpc" },
> + { .compatible = "fsl,imx8mn-gpc" },
> { }
> };
>
>
Re: [PATCH V2 08/24] imx: power-domain: Add fsl, imx8mm-gpc compatible string
On 4/12/21 1:28 AM, Marek Vasut wrote:
> The driver is compatible with iMX8MM, add missing compatible string.
>
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: Ye Li
> Cc: uboot-imx
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon chung
> ---
> V2: No change
> ---
> drivers/power/domain/imx8m-power-domain.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/power/domain/imx8m-power-domain.c
> b/drivers/power/domain/imx8m-power-domain.c
> index c4cd07ffaf..ebac90d81c 100644
> --- a/drivers/power/domain/imx8m-power-domain.c
> +++ b/drivers/power/domain/imx8m-power-domain.c
> @@ -120,6 +120,7 @@ static int imx8m_power_domain_of_to_plat(struct udevice
> *dev)
>
> static const struct udevice_id imx8m_power_domain_ids[] = {
> { .compatible = "fsl,imx8mq-gpc" },
> + { .compatible = "fsl,imx8mm-gpc" },
> { }
> };
>
>
Re: [PATCH 0/2] net: jr2: Fix for jr2 switch
Hi, A gentle ping. Thanks. The 03/10/2021 09:31, Horatiu Vultur wrote: > This patch series contains two patches. The first patch resets the > switch at probe time while the second one fixes an issue with the > serdes6g configuration which is used on jr2_pcb111 board > > Horatiu Vultur (2): > net: jr2: Reset switch > net: jr2: Fix Serdes6G configuration > > arch/mips/dts/mscc,jr2.dtsi | 6 ++-- > drivers/net/mscc_eswitch/jr2_switch.c | 43 +++ > 2 files changed, 42 insertions(+), 7 deletions(-) > > -- > 2.30.1 > -- /Horatiu
Re: [PATCH 1/6] arm: highbank: Limit FDT and initrd load addresses
On Mon, Apr 12, 2021 at 01:04:50AM +0100, Andre Przywara wrote:
> So far on Highbank/Midway machines U-Boot only ever uses 512MB of DRAM,
> even though the machines have typically 4GB and 8GB, respectively.
> That means that so far we didn't need an extra limit for placing the DTB
> and initrd, as the 512MB are lower than the kernel's limit ("lowmem",
> typically 768MB).
>
> With U-Boot now needing to learn about the actual memory size (to
> correctly populate the EFI memory map), it might relocate fdt and initrd
> to the end of DRAM, which is out of reach of the kernel.
>
> So add limiting values to the fdt_high and initrd_high environment
> variables, to prevent U-Boot from using too high addresses.
>
> Signed-off-by: Andre Przywara
Reviewed-by: Tom Rini
--
Tom
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Description: PGP signature
Re: [PATCH 54/57] ppc: Remove MPC837XEMDS board
On Sat, Feb 20, 2021 at 08:06:31PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Priyanka Jain > Signed-off-by: Tom Rini [note: Reworked to leave the rest of the ARCH support as we have another one in family that was updated] Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 53/57] ppc: Remove Cyrus_P5020 and P5040 boards
On Sat, Feb 20, 2021 at 08:06:30PM -0500, Tom Rini wrote: > These boards have not been converted to CONFIG_DM_MMC by the deadline. > Remove them. As the P5020 is the last ARCH_P5020 platform, remove that > support as well. > > Cc: Andy Fleming > Cc: Priyanka Jain > Signed-off-by: Tom Rini > Reviewed-by: Priyanka Jain Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 48/57] ppc: Remove controlcenterd boards
On Sat, Feb 20, 2021 at 08:06:25PM -0500, Tom Rini wrote: > These boards have not been converted to CONFIG_DM_MMC by the deadline. > Remove them. > > Cc: Mario Six > Cc: Dirk Eibach > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 49/57] ppc: Remove ARCH_P1022 support
On Sat, Feb 20, 2021 at 08:06:26PM -0500, Tom Rini wrote: > With the last of the ARCH_P1022 platforms removed, finish removing the > rest of the platform support. > > Cc: Priyanka Jain > Signed-off-by: Tom Rini > Reviewed-by: Priyanka Jain Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 47/57] ppc: Remove gdsys hrcon boards
On Sat, Feb 20, 2021 at 08:06:24PM -0500, Tom Rini wrote: > These boards have not been converted to CONFIG_DM_MMC, along with other > DM conversions, by the deadline. Remove them. > > Cc: Dirk Eibach > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 46/57] ppc: Remove gdsys strider boards
On Sat, Feb 20, 2021 at 08:06:23PM -0500, Tom Rini wrote: > These boards have not been converted to CONFIG_DM_MMC, along with other > DM conversions, by the deadline. Remove them. > > Cc: Dirk Eibach > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 45/57] ppc: Remove MPC8308RDB board
On Sat, Feb 20, 2021 at 08:06:22PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Ilya Yanok > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 44/57] ppc: Remove T2081QDS board and ARCH_T2081 support
On Sat, Feb 20, 2021 at 08:06:21PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. It is also the only ARCH_T2081 board so remove that support > as well. > > Cc: Shengzhou Liu > Cc: Ruchika Gupta > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 43/57] ppc: Remove TARGET_T1040QDS references
On Sat, Feb 20, 2021 at 08:06:20PM -0500, Tom Rini wrote: > The TARGET_T1040QDS platforms have been removed already, drop some > remaining references in the code. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 41/57] arm: Remove tqma6s_wru4_mmc config
On Sat, Feb 20, 2021 at 08:06:18PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Markus Niebel > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 39/57] arm: Remove mx6dlarm2 board
On Sat, Feb 20, 2021 at 08:06:16PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Jason Liu > Cc: Ye Li > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 38/57] arm: Remove cgtqmx6eval board
On Sat, Feb 20, 2021 at 08:06:15PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Otavio Salvador > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 37/57] arm: Remove titanium board
On Sat, Feb 20, 2021 at 08:06:14PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Stefan Roese > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 36/57] arm: Remove ts4800 board
On Sat, Feb 20, 2021 at 08:06:13PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Lucile Quirion > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 34/57] arm: Remove mx53evk board
On Sat, Feb 20, 2021 at 08:06:11PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Jason Liu > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 32/57] arm: Remove pfla02 board
On Sat, Feb 20, 2021 at 08:06:09PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Stefano Babic > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 31/57] arm: Remove zc5202 and zc5601 boards
On Sat, Feb 20, 2021 at 08:06:08PM -0500, Tom Rini wrote: > These boards have not been converted to CONFIG_DM_MMC by the deadline. > Remove them. > > Cc: Stefano Babic > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 29/57] arm: Remove xpress board
On Sat, Feb 20, 2021 at 08:06:06PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Stefan Roese > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 27/57] arm: Remove kc1 board
On Sat, Feb 20, 2021 at 08:06:04PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Paul Kocialkowski > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 26/57] arm: Remove am3517_crane board
On Sat, Feb 20, 2021 at 08:06:03PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Nagendra T S > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 21/57] arm: Remove platinum_picon board
On Sat, Feb 20, 2021 at 08:05:58PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Stefan Roese > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 25/57] arm: Remove omap3_ha board
On Sat, Feb 20, 2021 at 08:06:02PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Stefan Roese > Cc: Tapani Utriainen > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 24/57] arm: Remove tricorder board
On Sat, Feb 20, 2021 at 08:06:01PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Thomas Weber > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 18/57] arm: Remove bcm23550_w1d board
On Sat, Feb 20, 2021 at 08:05:55PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Steve Rae > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 20/57] arm: Remove Broadcom Cygnus boards
On Sat, Feb 20, 2021 at 08:05:57PM -0500, Tom Rini wrote: > These boards have not been converted to CONFIG_DM by the deadline. > Remove them. > > Cc: Steve Rae > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 17/57] arm: Remove bcm28155_ap board
On Sat, Feb 20, 2021 at 08:05:54PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Steve Rae > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 16/57] arm: Remove picosam9g45 board
On Sat, Feb 20, 2021 at 08:05:53PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Erik van Luijk > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 15/57] arm: Remove wb50n board
On Sat, Feb 20, 2021 at 08:05:52PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Ben Whitten > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 14/57] arm: Remove wb45n board
On Sat, Feb 20, 2021 at 08:05:51PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Ben Whitten > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 13/57] arm: Remove bcm958712k board
On Sat, Feb 20, 2021 at 08:05:50PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Jon Mason > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 12/57] arm: Remove s32v234evb board
On Sat, Feb 20, 2021 at 08:05:49PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Eddy Petrișor > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 11/57] arm: Remove secomx6quq7 board
On Sat, Feb 20, 2021 at 08:05:48PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Boris Brezillon > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 10/57] arm: Remove vexpress_ca15_tc2 board
On Sat, Feb 20, 2021 at 08:05:47PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Linus Walleij > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 05/57] arm: Remove ts4600 board
On Sat, Feb 20, 2021 at 08:05:42PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Sebastien Bourdelin > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 04/57] arm: Remove sc_sps_1 board
On Sat, Feb 20, 2021 at 08:05:41PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Marek Vasut > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 06/57] arm: Remove apf27 board
On Sat, Feb 20, 2021 at 08:05:43PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Philippe Reynes > Cc: Eric Jarrige > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 01/57] arm: Remove xfi3 board
On Sat, Feb 20, 2021 at 08:05:38PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Marek Vasut > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 03/57] arm: Remove SANSA_FUZE_PLUS board
On Sat, Feb 20, 2021 at 08:05:40PM -0500, Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Marek Vasut > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 15/16] drivers: ata: Remove mvsata_ide driver
On Tue, Feb 09, 2021 at 09:42:56PM -0500, Tom Rini wrote: > The mvsata_ide driver was due for DM conversion by v2019.07. As that > has long passed, remove the driver and disable it in the boards which > had enabled it. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 09/16] ppc: Remove MPC8349ITX board
On Tue, Feb 09, 2021 at 09:42:50PM -0500, Tom Rini wrote: > This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI. The > deadline for this conversion was the v2019.07 release. The use of CONFIG_AHCI > requires CONFIG_DM. The deadline for this conversion was v2020.01. Remove > this board. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 06/16] arm: Remove dms-ba16 board
On Tue, Feb 09, 2021 at 09:42:47PM -0500, Tom Rini wrote: > This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI. The > deadline for this conversion was the v2019.07 release. The use of CONFIG_AHCI > requires CONFIG_DM. The deadline for this conversion was v2020.01. Remove > this board. > > Cc: Akshay Bhat > Cc: Ken Lin > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 07/16] arm: Remove ot1200 board
On Tue, Feb 09, 2021 at 09:42:48PM -0500, Tom Rini wrote: > This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI. The > deadline for this conversion was the v2019.07 release. In order to > convert to using the DWC SATA driver under DM further migrations are > required. > > Cc: Christian Gmeiner > Signed-off-by: Tom Rini > Acked-by: Christian Gmeiner Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 03/16] ata: DWC_AHSATA depends on BLK
On Tue, Feb 09, 2021 at 09:42:44PM -0500, Tom Rini wrote: > The dwc ahsata driver is written such that CONFIG_BLK must be enabled, > add this as a dependency in Kconfig. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 02/16] am57xx_hs_evm_usb: Enable AHCI and BLK
On Tue, Feb 09, 2021 at 09:42:43PM -0500, Tom Rini wrote: > Enable the AHCI and BLK features to complete migration of various > drivers. > > Cc: Andrew F. Davis > Cc: Lokesh Vutla > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI
On Tue, Feb 09, 2021 at 09:42:42PM -0500, Tom Rini wrote: > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH 3/6] net: calxedagmac: Convert to DM_ETH
To squash that nasty warning message and make better use of the newly
gained OF_CONTROL feature, let's convert the calxedagmac driver to the
"new" driver model.
The conversion is pretty straight forward, mostly just adjusting the
use of the involved data structures.
The only actual change is the required split of the receive routine into
a receive and free_pkt part.
Also this allows us to get rid of the hardcoded platform information and
explicit init calls.
This also uses the opportunity to wrap the code decoding the MMIO
register base address, to make it safe for using PHYS_64BIT later.
Signed-off-by: Andre Przywara
---
arch/arm/Kconfig | 1 +
board/highbank/highbank.c| 13 ---
configs/highbank_defconfig | 1 +
drivers/net/Kconfig | 7 ++
drivers/net/calxedaxgmac.c | 192 +++
include/configs/highbank.h | 2 -
include/netdev.h | 1 -
scripts/config_whitelist.txt | 1 -
8 files changed, 137 insertions(+), 81 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd6064923fe..0082d06182a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -756,6 +756,7 @@ config ARCH_HIGHBANK
select CLK
select CLK_CCF
select AHCI
+ select DM_ETH
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 2e2300a307f..0667a48965c 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -10,7 +10,6 @@
#include
#include
#include
-#include
#include
#include
@@ -52,18 +51,6 @@ int board_init(void)
return 0;
}
-/* We know all the init functions have been run now */
-int board_eth_init(struct bd_info *bis)
-{
- int rc = 0;
-
-#ifdef CONFIG_CALXEDA_XGMAC
- rc += calxedaxgmac_initialize(0, 0xfff5);
- rc += calxedaxgmac_initialize(1, 0xfff51000);
-#endif
- return rc;
-}
-
#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index 773ed7a00bf..c3352b827d7 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -27,3 +27,4 @@ CONFIG_SCSI=y
CONFIG_CONS_INDEX=0
CONFIG_OF_LIBFDT=y
CONFIG_OF_BOARD=y
+CONFIG_CALXEDA_XGMAC=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index cf062fad4da..cebd84035c8 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -171,6 +171,13 @@ config CORTINA_NI_ENET
This driver supports the Cortina-Access Ethernet MAC for
all supported CA SoCs.
+config CALXEDA_XGMAC
+ bool "Calxeda XGMAC support"
+ depends on DM_ETH
+ help
+ This driver supports the XGMAC in Calxeda Highbank and Midway
+ machines.
+
config DWC_ETH_QOS
bool "Synopsys DWC Ethernet QOS device support"
depends on DM_ETH
diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c
index 8b2ee49b441..b98d709117a 100644
--- a/drivers/net/calxedaxgmac.c
+++ b/drivers/net/calxedaxgmac.c
@@ -10,6 +10,8 @@
#include
#include
#include
+#include
+#include /* for dev_set_priv() */
#define TX_NUM_DESC1
#define RX_NUM_DESC32
@@ -212,6 +214,18 @@ struct xgmac_dma_desc {
__le32 res[3];
};
+static struct xgmac_regs *xgmac_get_regs(struct eth_pdata *pdata)
+{
+ /*
+* We use PHYS_64BIT on Highbank, so phys_addr_t is bigger than
+* a pointer. U-Boot doesn't use LPAE (not even the MMU on highbank),
+* so we can't access anything above 4GB.
+* We have a check in the probe function below the ensure this,
+* so casting to a 32-bit pointer type is fine here.
+*/
+ return (struct xgmac_regs *)(uintptr_t)pdata->iobase;
+}
+
/* XGMAC Descriptor Access Helpers */
static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
{
@@ -304,8 +318,6 @@ struct calxeda_eth_dev {
u32 tx_currdesc;
u32 rx_currdesc;
-
- struct eth_device *dev;
} __aligned(32);
/*
@@ -313,10 +325,10 @@ struct calxeda_eth_dev {
* advanced descriptors.
*/
-static void init_rx_desc(struct calxeda_eth_dev *priv)
+static void init_rx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv)
{
struct xgmac_dma_desc *rxdesc = priv->rx_chain;
- struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
+ struct xgmac_regs *regs = xgmac_get_regs(pdata);
void *rxbuffer = priv->rxbuffer;
int i;
@@ -330,17 +342,16 @@ static void init_rx_desc(struct calxeda_eth_dev *priv)
}
}
-static void init_tx_desc(struct calxeda_eth_dev *priv)
+static void init_tx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv)
{
- struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
+ struct xgmac_regs *regs = xgmac_get_regs(pdata);
desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
[PATCH 5/6] arm: highbank: Do DRAM init from DT
So far U-Boot was hard coding a (surely sufficient) memory size of 512
MB, even though all machines out there have at least 4GB of DRAM.
Since U-Boot uses its memory knowledge to populate the EFI memory map,
we are missing out here, at best losing everything beyond 4GB on Midway
boxes (which typically come with 8GB of DRAM).
Since the management processor populated the DT memory node already with
the detected DRAM size and configuration, we use that to populate
U-Boot's memory bank information, which is the base for the UEFI memory
map.
This finally allows us to get rid of the NR_DRAM_BANKS=0 hack, that we
had in place to avoid U-Boot messing up the DT memory node before
loading the kernel.
Also, to cover the whole of memory, we need to enable PHYS_64BIT.
Signed-off-by: Andre Przywara
---
arch/arm/Kconfig | 1 +
board/highbank/highbank.c | 9 +++--
configs/highbank_defconfig | 2 +-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0082d06182a..6b5479b60be 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -757,6 +757,7 @@ config ARCH_HIGHBANK
select CLK_CCF
select AHCI
select DM_ETH
+ select PHYS_64BIT
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 0667a48965c..ffb6fd922da 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -84,8 +85,12 @@ int misc_init_r(void)
int dram_init(void)
{
- gd->ram_size = SZ_512M;
- return 0;
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
}
#if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index c3352b827d7..5d65049c5c0 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_SYS_TEXT_BASE=0x8000
-CONFIG_NR_DRAM_BANKS=0
+CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
--
2.17.5
[PATCH 6/6] arm: highbank: Update maintainership
Rob does not have access to any Calxeda systems anymore, also has expressed a lack of interest in those systems in the past. I have multiple working Midway nodes under my desk in the office, so am happy to take over maintainership. Signed-off-by: Andre Przywara --- board/highbank/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/highbank/MAINTAINERS b/board/highbank/MAINTAINERS index 69ddeddd600..a542bd1ee64 100644 --- a/board/highbank/MAINTAINERS +++ b/board/highbank/MAINTAINERS @@ -1,5 +1,5 @@ HIGHBANK BOARD -M: Rob Herring +M: Andre Przywara S: Maintained F: board/highbank/ F: include/configs/highbank.h -- 2.17.5
[PATCH 4/6] arm: highbank: Remove artificial SDRAM size
So far we were defining a somewhat confusing PHYS_SDRAM_1_SIZE variable, which originally was only used for setting the memtest boundaries. This definition in highbank.h has been removed about a year ago (moved to Kconfig), so we also don't need the hard-coded size definition any longer. Get rid of the misleading memory size definition, which was actually wrong anyway (it's 4088 MB for those machines with just 4GB of DRAM). Signed-off-by: Andre Przywara --- include/configs/highbank.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/include/configs/highbank.h b/include/configs/highbank.h index fbd26ddd0fc..ff92c4f5540 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -39,12 +39,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x80 #define CONFIG_SYS_64BIT_LBA -/*--- - * Physical Memory Map - * The DRAM is already setup, so do not touch the DT node later. - */ -#define PHYS_SDRAM_1_SIZE (4089 << 20) - /* Environment data setup */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ -- 2.17.5
[PATCH 2/6] arm: highbank: Enable OF_CONTROL
All Calxeda machines are actually a poster book example of device tree
usage: the DT is loaded from flash by the management processor into
DRAM, the memory node is populated with the detected DRAM size and this
DT is then handed over to the kernel.
So it's a shame that U-Boot didn't participate in this chain, but
fortunately this is easy to fix:
Define CONFIG_OF_CONTROL and CONFIG_OF_BOARD, and provide a trivial
function to tell U-Boot about the (fixed) location of the DTB in DRAM.
Then enable DM_SERIAL, to let the PL011 driver pick up the UART platform
data from the DT. Also define AHCI, to bring this driver into the driver
model world as well.
Signed-off-by: Andre Przywara
---
arch/arm/Kconfig | 9 -
board/highbank/highbank.c | 10 ++
configs/highbank_defconfig | 1 +
include/configs/highbank.h | 1 -
4 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 76adf7fdb24..bd6064923fe 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -748,7 +748,14 @@ config ARCH_S5PC1XX
config ARCH_HIGHBANK
bool "Calxeda Highbank"
select CPU_V7A
- select PL011_SERIAL
+ select PL01X_SERIAL
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+ select OF_BOARD
+ select CLK
+ select CLK_CCF
+ select AHCI
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 906bd9b6dda..2e2300a307f 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -119,6 +119,16 @@ int ft_board_setup(void *fdt, struct bd_info *bd)
}
#endif
+void *board_fdt_blob_setup(void)
+{
+ /*
+* The ECME management processor loads the DTB from NOR flash
+* into DRAM (at 4KB), where it gets patched to contain the
+* detected memory size.
+*/
+ return (void *)0x1000;
+}
+
static int is_highbank(void)
{
uint32_t midr;
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index 369b65ceee8..773ed7a00bf 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -26,3 +26,4 @@ CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=0
CONFIG_OF_LIBFDT=y
+CONFIG_OF_BOARD=y
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 5e3cc3a1db6..7f37c81fc9f 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -18,7 +18,6 @@
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
#define CONFIG_PL011_CLOCK 15000
-#define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
#define CONFIG_SYS_BOOTCOUNT_LE/* Use little-endian accessors
*/
--
2.17.5
[PATCH 1/6] arm: highbank: Limit FDT and initrd load addresses
So far on Highbank/Midway machines U-Boot only ever uses 512MB of DRAM,
even though the machines have typically 4GB and 8GB, respectively.
That means that so far we didn't need an extra limit for placing the DTB
and initrd, as the 512MB are lower than the kernel's limit ("lowmem",
typically 768MB).
With U-Boot now needing to learn about the actual memory size (to
correctly populate the EFI memory map), it might relocate fdt and initrd
to the end of DRAM, which is out of reach of the kernel.
So add limiting values to the fdt_high and initrd_high environment
variables, to prevent U-Boot from using too high addresses.
Signed-off-by: Andre Przywara
---
include/configs/highbank.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index bdbaa475d20..5e3cc3a1db6 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -57,4 +57,8 @@
#define CONFIG_SYS_INIT_SP_ADDR0x0100
#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x2000\0" \
+ "initrd_high=0x2000\0"
+
#endif
--
2.17.5
[PATCH 0/6] highbank: Update to driver model
The Calxeda Highbank and Midway systems have not been updated in a
while, so were gathering more and more warning messages about not being
DM compliant over time.
To avoid the support being removed, update the board to comply with
modern U-Boot standards:
- Enable OF_CONTROL, and use the DTB provided by previous firmware stages.
- Convert the XGMAC network driver over to the driver model.
- Read the actual DRAM size (as detect by the management processor) from
the DTB and use that to populate the memory node, and U-Boot internal
idea of DRAM.
Access to SATA drives broke with commit 66c54f1a3e46 ("scsi: Simplify
scsi_read()/_write()") before the v2020.01 release, and remains
non-functional with this series for now. Reverting that commit (and
massaging it a bit) brought it back to life. I will send a proper patch
once I wrapped my head around the SCSI/SATA/AHCI/DM-block connections.
To test this build, you can use chain-loading on an existing installation
(firmware updates in flash on those boards are not trivial):
$ mkimage -A arm -O u-boot -T standalone -C none -a 0x8000 -e 0x8000 \
-d u-boot.bin -n U-Boot /srv/tftp/u-boot-highbank.img
=> tftpboot 0x8000 u-boot-highbank.img
=> bootm 0x8000
Cheers,
Andre
Andre Przywara (6):
arm: highbank: Limit FDT and initrd load addresses
arm: highbank: Enable OF_CONTROL
net: calxedagmac: Convert to DM_ETH
arm: highbank: Remove artificial SDRAM size
arm: highbank: Do DRAM init from DT
arm: highbank: Update maintainership
arch/arm/Kconfig | 11 +-
board/highbank/MAINTAINERS | 2 +-
board/highbank/highbank.c| 32 +++---
configs/highbank_defconfig | 4 +-
drivers/net/Kconfig | 7 ++
drivers/net/calxedaxgmac.c | 192 +++
include/configs/highbank.h | 13 +--
include/netdev.h | 1 -
scripts/config_whitelist.txt | 1 -
9 files changed, 170 insertions(+), 93 deletions(-)
--
2.17.5
Re: [BUG][Cyrus BOARD] out of bound access in board/varisys/common/sys_eeprom.c
On Mon, Apr 12, 2021 at 12:25:32AM +0200, Heinrich Schuchardt wrote:
> Hello Andy,
>
> in the code of your patch "mpc85xx: Add support for the Varisys Cyrus
> board" merged in 2015 as 87e29878cab an out of bound access occurs. See
> below.
>
> On 11/4/15 10:48 PM, Andy Fleming wrote:
> > This board runs a P5020 or P5040 chip, and utilizes
> > an EEPROM with similar formatting to the Freescale P5020DS.
> >
> > Large amounts of this code were developed by
> > Adrian Cox
> >
> > Signed-off-by: Andy Fleming
> > Reviewed-by: York Sun
> > ---
>
>
>
> > +++ b/board/varisys/common/sys_eeprom.c
>
>
>
> > +static struct __attribute__ ((__packed__)) eeprom {
> > + u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */
> > + u8 sn[12];/* 0x04 - 0x0F Serial Number */
> > + u8 errata[5]; /* 0x10 - 0x14 Errata Level */
> > + u8 date[6]; /* 0x15 - 0x1a Build Date */
> > + u8 res_0; /* 0x1bReserved */
> > + u32 version; /* 0x1c - 0x1f NXID Version */
> > + u8 tempcal[8];/* 0x20 - 0x27 Temperature Calibration Factors */
> > + u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration
> Factors */
> > + u8 tempcalflags; /* 0x2aTemperature Calibration Flags */
> > + u8 res_1[21]; /* 0x2b - 0x3f Reserved */
> > + u8 mac_count; /* 0x40Number of MAC addresses */
> > + u8 mac_flag; /* 0x41MAC table flags */
> > + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
> > + u32 crc; /* x+1 CRC32 checksum */
> > +} e;
>
> // MAX_NUM_PORTS = 8
>
> > +int mac_read_from_eeprom_common(void)
> > +{
> > + unsigned int i;
> > + u32 crc, crc_offset = offsetof(struct eeprom, crc);
> > + u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
> > +
> > + puts("EEPROM: ");
> > +
> > + if (read_eeprom()) {
> > + printf("Read failed.\n");
> > + return 0;
> > + }
> > +
> > + if (!is_valid) {
> > + printf("Invalid ID (%02x %02x %02x %02x)\n",
> > + e.id[0], e.id[1], e.id[2], e.id[3]);
> > + return 0;
> > + }
> > +
> > + crc = crc32(0, (void *), crc_offset);
> > + crcp = (void *) + crc_offset;
> > + if (crc != be32_to_cpu(*crcp)) {
> > + printf("CRC mismatch (%08x != %08x)\n", crc,
> > + be32_to_cpu(e.crc));
> > + return 0;
> > + }
> > +
> > + /*
> > +* MAC address #9 in v1 occupies the same position as the CRC in v0.
> > +* Erase it so that it's not mistaken for a MAC address. We'll
> > +* update the CRC later.
> > +*/
> > + if (e.version == 0)
> > + memset(e.mac[8], 0xff, 6);
>
> Here you are writing 2 bytes beyond the size of e.
A useful analysis in case anyone brings these boards back. I'm about to
push the series that delete this due to lack of migration.
--
Tom
signature.asc
Description: PGP signature
[BUG][Cyrus BOARD] out of bound access in board/varisys/common/sys_eeprom.c
Hello Andy,
in the code of your patch "mpc85xx: Add support for the Varisys Cyrus
board" merged in 2015 as 87e29878cab an out of bound access occurs. See
below.
On 11/4/15 10:48 PM, Andy Fleming wrote:
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox
Signed-off-by: Andy Fleming
Reviewed-by: York Sun
---
> +++ b/board/varisys/common/sys_eeprom.c
> +static struct __attribute__ ((__packed__)) eeprom {
> + u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */
> + u8 sn[12];/* 0x04 - 0x0F Serial Number */
> + u8 errata[5]; /* 0x10 - 0x14 Errata Level */
> + u8 date[6]; /* 0x15 - 0x1a Build Date */
> + u8 res_0; /* 0x1bReserved */
> + u32 version; /* 0x1c - 0x1f NXID Version */
> + u8 tempcal[8];/* 0x20 - 0x27 Temperature Calibration Factors */
> + u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration
Factors */
> + u8 tempcalflags; /* 0x2aTemperature Calibration Flags */
> + u8 res_1[21]; /* 0x2b - 0x3f Reserved */
> + u8 mac_count; /* 0x40Number of MAC addresses */
> + u8 mac_flag; /* 0x41MAC table flags */
> + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
> + u32 crc; /* x+1 CRC32 checksum */
> +} e;
// MAX_NUM_PORTS = 8
+int mac_read_from_eeprom_common(void)
+{
+ unsigned int i;
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ puts("EEPROM: ");
+
+ if (read_eeprom()) {
+ printf("Read failed.\n");
+ return 0;
+ }
+
+ if (!is_valid) {
+ printf("Invalid ID (%02x %02x %02x %02x)\n",
+ e.id[0], e.id[1], e.id[2], e.id[3]);
+ return 0;
+ }
+
+ crc = crc32(0, (void *), crc_offset);
+ crcp = (void *) + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return 0;
+ }
+
+ /*
+* MAC address #9 in v1 occupies the same position as the CRC in v0.
+* Erase it so that it's not mistaken for a MAC address. We'll
+* update the CRC later.
+*/
+ if (e.version == 0)
+ memset(e.mac[8], 0xff, 6);
Here you are writing 2 bytes beyond the size of e.
Best regards
Heinrich
Re: [PATCH v2] power: regulator: Add support for regulator-force-boot-off
On 4/10/21 3:42 PM, Stefan Roese wrote:
> From: Konstantin Porotchkin
>
> Add support for regulator-force-boot-off DT property.
> This property can be used by the board/device drivers for
> turning off regulators on early init stages as pre-requisite
> for the other components initialization.
>
> Signed-off-by: Konstantin Porotchkin
> Signed-off-by: Stefan Roese
> Cc: Jaehoon Chung
> Cc: Simon Glass
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> v2:
> - Add check for uc_pdata in regulator_unset()
>
> drivers/power/regulator/regulator-uclass.c | 38 ++
> include/power/regulator.h | 23 +
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/power/regulator/regulator-uclass.c
> b/drivers/power/regulator/regulator-uclass.c
> index 4d2e730271f9..fac960682331 100644
> --- a/drivers/power/regulator/regulator-uclass.c
> +++ b/drivers/power/regulator/regulator-uclass.c
> @@ -311,6 +311,17 @@ int regulator_autoset(struct udevice *dev)
> return ret;
> }
>
> +int regulator_unset(struct udevice *dev)
> +{
> + struct dm_regulator_uclass_plat *uc_pdata;
> +
> + uc_pdata = dev_get_uclass_plat(dev);
> + if (uc_pdata && uc_pdata->force_off)
> + return regulator_set_enable(dev, false);
> +
> + return -EMEDIUMTYPE;
> +}
> +
> static void regulator_show(struct udevice *dev, int ret)
> {
> struct dm_regulator_uclass_plat *uc_pdata;
> @@ -443,6 +454,7 @@ static int regulator_pre_probe(struct udevice *dev)
> uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
> uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay",
> 0);
> + uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off");
>
> node = dev_read_subnode(dev, "regulator-state-mem");
> if (ofnode_valid(node)) {
> @@ -495,6 +507,32 @@ int regulators_enable_boot_on(bool verbose)
> return ret;
> }
>
> +int regulators_enable_boot_off(bool verbose)
> +{
> + struct udevice *dev;
> + struct uclass *uc;
> + int ret;
> +
> + ret = uclass_get(UCLASS_REGULATOR, );
> + if (ret)
> + return ret;
> + for (uclass_first_device(UCLASS_REGULATOR, );
> + dev;
> + uclass_next_device()) {
> + ret = regulator_unset(dev);
> + if (ret == -EMEDIUMTYPE) {
> + ret = 0;
> + continue;
> + }
> + if (verbose)
> + regulator_show(dev, ret);
> + if (ret == -ENOSYS)
> + ret = 0;
> + }
> +
> + return ret;
> +}
> +
> UCLASS_DRIVER(regulator) = {
> .id = UCLASS_REGULATOR,
> .name = "regulator",
> diff --git a/include/power/regulator.h b/include/power/regulator.h
> index da9a065bdde0..fad87c99e5db 100644
> --- a/include/power/regulator.h
> +++ b/include/power/regulator.h
> @@ -151,6 +151,7 @@ enum regulator_flag {
> * @max_uA*- maximum amperage (micro Amps)
> * @always_on* - bool type, true or false
> * @boot_on* - bool type, true or false
> + * @force_off* - bool type, true or false
> * TODO(s...@chromium.org): Consider putting the above two into @flags
> * @ramp_delay - Time to settle down after voltage change (unit: uV/us)
> * @flags: - flags value (see REGULATOR_FLAG_...)
> @@ -176,6 +177,7 @@ struct dm_regulator_uclass_plat {
> unsigned int ramp_delay;
> bool always_on;
> bool boot_on;
> + bool force_off;
> const char *name;
> int flags;
> u8 ctrl_reg;
> @@ -420,6 +422,15 @@ int regulator_set_mode(struct udevice *dev, int mode_id);
> */
> int regulators_enable_boot_on(bool verbose);
>
> +/**
> + * regulators_enable_boot_off() - disable regulators needed for boot
> + *
> + * This disables all regulators which are marked to be off at boot time.
> + *
> + * This effectively calls regulator_unset() for every regulator.
> + */
> +int regulators_enable_boot_off(bool verbose);
> +
> /**
> * regulator_autoset: setup the voltage/current on a regulator
> *
> @@ -439,6 +450,18 @@ int regulators_enable_boot_on(bool verbose);
> */
> int regulator_autoset(struct udevice *dev);
>
> +/**
> + * regulator_unset: turn off a regulator
> + *
> + * The setup depends on constraints found in device's uclass's platform data
> + * (struct dm_regulator_uclass_platdata):
> + *
> + * - Disable - will set - if 'force_off' is set to true,
> + *
> + * The function returns on the first-encountered error.
> + */
> +int regulator_unset(struct udevice *dev);
> +
> /**
> * regulator_autoset_by_name: setup the regulator given by its uclass's
> * platform data name field. The setup depends on constraints found in
> device's
>
Re: [patch v4 0/9] rk3399 (Pinebook pro) EDP support
On Fri, 05 Mar 2021 11:27:45 +0100 Arnaud Patard (Rtp) arnaud.pat...@rtp-net.org wrote: > This patchset add support for the rk3399 eDP. It has been tested on the > pinebook > pro and Google Kevin chromeos devices. > > The changes have been written by studying the linux code, since I didn't find > any > manual for theses part of the RK3399 SoC. > > On the linux kernel side, on recent kernels, it needs commit "pwm: rockchip: > Keep > enabled PWMs running while probing" otherwise the pinebook pro will freeze > when probing > the display. Series applied to u-boot-video/master, thanks! -- Anatolij
Re: [PATCH v3 2/2] pwm: Add a driver for Chrome OS EC PWM
On Thu, 22 Oct 2020 23:49:27 +0300 Alper Nebi Yasak alpernebiya...@gmail.com wrote: ... > doc/device-tree-bindings/pwm/cros-ec-pwm.txt | 23 ++ > drivers/misc/cros_ec.c | 17 > drivers/pwm/Kconfig | 9 +++ > drivers/pwm/Makefile | 1 + > drivers/pwm/cros_ec_pwm.c| 84 > include/cros_ec.h| 13 +++ > 6 files changed, 147 insertions(+) > create mode 100644 doc/device-tree-bindings/pwm/cros-ec-pwm.txt > create mode 100644 drivers/pwm/cros_ec_pwm.c applied to u-boot-video/master, thanks! -- Anatolij
Re: [PATCH v3 1/2] video: backlight: Support PWMs without a known period_ns
On Thu, 22 Oct 2020 23:49:26 +0300 Alper Nebi Yasak alpernebiya...@gmail.com wrote: ... > drivers/pwm/sandbox_pwm.c | 11 +-- > drivers/video/pwm_backlight.c | 20 ++-- > include/pwm.h | 8 > test/dm/pwm.c | 11 +++ > 4 files changed, 42 insertions(+), 8 deletions(-) applied to u-boot-video/master, thanks! -- Anatolij
Re: [PATCH] video: SIMPLE_PANEL depends on DM_GPIO
On Wed, 3 Mar 2021 14:46:47 +1100 Asherah Connor a...@kivikakk.ee wrote: ... > drivers/video/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) applied to u-boot-video/master, thanks! -- Anatolij
Re: [PATCH] finish removing mb862xx video driver
On Mon, 15 Mar 2021 18:52:45 -0400 Trevor Woerner twoer...@gmail.com wrote: ... > drivers/video/cfb_console.c | 14 -- > scripts/config_whitelist.txt | 1 - > 2 files changed, 15 deletions(-) applied to u-boot-video/master, thanks! -- Anatolij
Re: [PATCH] board_f: cosmetic: change the debug trace to KB in reserve_video
On Fri, 9 Apr 2021 18:02:06 +0200
Patrick Delaunay patrick.delau...@foss.st.com wrote:
...
> Fixes: 5630d2fbc50f3035 ("board: Show memory for frame buffers")
> Signed-off-by: Patrick Delaunay
> ---
>
> common/board_f.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
applied to u-boot-video/master, thanks!
--
Anatolij
Re: [RFC 1/1] tegra: video: fix tegra_dc_sor_config_panel()
On Mon, 5 Apr 2021 01:48:51 +0200 Heinrich Schuchardt xypron.g...@gmx.de wrote: ... > --- > drivers/video/tegra124/sor.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) applied to u-boot-video/master, thanks! -- Anatolij
Re: [PATCH] video: Fix line padding calculation for 16 and 24 BPP bitmaps
On Tue, 1 Dec 2020 12:30:50 +0100 Sylwester Nawrocki s.nawro...@samsung.com wrote: > Each row in the pixel array in the bitmap file is padded > if necessary so the row size is always a multiple of 4 bytes. > In current code the complement of row size to a multiple of > 4 bytes is further unnecessarily multiplied by the pixel size. > This results in incorrect displaying of bitmaps having row size > that is not a multiple of 4 bytes. Fix this by removing > the unnecessary multiplication. > > Tested with 24BPP bitmap and XRGB32 display. > > Signed-off-by: Sylwester Nawrocki > --- > drivers/video/video_bmp.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) applied to u-boot-video/master, thanks! -- Anatolij
[PATCH 2/2] clk: renesas: Synchronize Gen2 MSTP teardown tables
Synchronize Gen2 MSTP teardown tables with datasheet Rev.2.00
Feb 01, 2016. This corrects the following bits:
- added H2 MSTP3[10] SCIF2
- added H2/M2/E2 MSTP7[29] TCON
- removed E2 MSTP5[22] Thermal Sensor
- removed E2 MSTP10[31,24:22] SRC0, SRC7:9
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/clk/renesas/r8a7790-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a7794-cpg-mssr.c | 6 +++---
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c
b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 09e7dbd3a3..d5079da3ff 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -239,11 +239,11 @@ static const struct mstp_stop_table r8a7790_mstp_table[]
= {
{ 0x00640801, 0x40, 0x00640801, 0x0 },
{ 0xDB6E9BDF, 0x0, 0xDB6E9BDF, 0x0 },
{ 0x300DA1FC, 0x2010, 0x300DA1FC, 0x0 },
- { 0xF08CF831, 0x0, 0xF08CF831, 0x0 },
+ { 0xF08CFC31, 0x0, 0xF08CFC31, 0x0 },
{ 0x8184, 0x180, 0x8184, 0x0 },
{ 0x44C00046, 0x0, 0x44C00046, 0x0 },
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
- { 0x07F30718, 0x20, 0x07F30718, 0x0 },
+ { 0x27F30718, 0x20, 0x27F30718, 0x0 },
{ 0x01F0FF84, 0x0, 0x01F0FF84, 0x0 },
{ 0xF5979FCF, 0x0, 0xF5979FCF, 0x0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c
b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index 675ac83a61..fa0e275afd 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -245,7 +245,7 @@ static const struct mstp_stop_table r8a7791_mstp_table[] = {
{ 0x81C4, 0x180, 0x81C4, 0x0 },
{ 0x44C00046, 0x0, 0x44C00046, 0x0 },
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
- { 0x05BFE618, 0x20, 0x05BFE618, 0x0 },
+ { 0x25BFE618, 0x20, 0x25BFE618, 0x0 },
{ 0x40C0FE85, 0x0, 0x40C0FE85, 0x0 },
{ 0xFF979FFF, 0x0, 0xFF979FFF, 0x0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c
b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index 1fcac9b59d..d05f89deb1 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -218,12 +218,12 @@ static const struct mstp_stop_table r8a7794_mstp_table[]
= {
{ 0x100D21FC, 0x2000, 0x100D21FC, 0x0 },
{ 0xE084D810, 0x0, 0xE084D810, 0x0 },
{ 0x81C4, 0x180, 0x81C4, 0x0 },
- { 0x40C00044, 0x0, 0x40C00044, 0x0 },
+ { 0x40800044, 0x0, 0x40800044, 0x0 },
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
- { 0x013FE618, 0x8, 0x013FE618, 0x0 },
+ { 0x21BFE618, 0x8, 0x21BFE618, 0x0 },
{ 0x40803C05, 0x0, 0x40803C05, 0x0 },
{ 0xFB879FEE, 0x0, 0xFB879FEE, 0x0 },
- { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
+ { 0x7E3EFFE0, 0x0, 0x7E3EFFE0, 0x0 },
{ 0x01C0, 0x0, 0x01C0, 0x0 },
};
--
2.30.2
[PATCH 1/2] clk: renesas: Only ever access documented bits in clock driver teardown
The clock driver used a heavy-handed approach where it turned off
all available clocks, while also possibly setting bits which are not
documented in the R-Car datasheet. Update the tables so that only
the bits which are documented are set or cleared when tearing down
the clock driver.
Note that the only clock left running before booting Linux are now
MFIC, INTC-AP, INTC-EX and SCIF2 / SCIF0 on V3x.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
Cc: Simon Glass
Cc: Tom Rini
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 22 +++---
drivers/clk/renesas/r8a7796-cpg-mssr.c | 22 +++---
drivers/clk/renesas/r8a77965-cpg-mssr.c | 24
drivers/clk/renesas/r8a77970-cpg-mssr.c | 22 +++---
drivers/clk/renesas/r8a77980-cpg-mssr.c | 24
drivers/clk/renesas/r8a77990-cpg-mssr.c | 24
drivers/clk/renesas/r8a77995-cpg-mssr.c | 24
7 files changed, 81 insertions(+), 81 deletions(-)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 101f6583fa..b137564962 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -327,17 +327,17 @@ static const struct rcar_gen3_cpg_pll_config
cpg_pll_configs[16] = {
};
static const struct mstp_stop_table r8a7795_mstp_table[] = {
- { 0x00640800, 0x0, 0x00640800, 0 },
- { 0xF3EE9390, 0x0, 0xF3EE9390, 0 },
- { 0x340FAFDC, 0x2040, 0x340FAFDC, 0 },
- { 0xD80C7CDF, 0x400, 0xD80C7CDF, 0 },
- { 0x8184, 0x180, 0x8184, 0 },
- { 0x40BFFF46, 0x0, 0x40BFFF46, 0 },
- { 0xE5FBEECF, 0x0, 0xE5FBEECF, 0 },
- { 0x390E, 0x0, 0x390E, 0 },
- { 0x01F19FF4, 0x0, 0x01F19FF4, 0 },
- { 0xFFDF, 0x0, 0xFFDF, 0 },
- { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
+ { 0x0021, 0x0, 0x0021, 0 },
+ { 0xc3ec13a0, 0x0, 0xc3ec13a0, 0 },
+ { 0x040e2fdc, 0x2000, 0x040e2fdc, 0 },
+ { 0xf4cc7cdf, 0x400, 0xf4cc7cdf, 0 },
+ { 0x8004, 0x180, 0x8004, 0 },
+ { 0x40dfff46, 0x0, 0x40dfff46, 0 },
+ { 0xc5e8ccce, 0x0, 0xc5e8ccce, 0 },
+ { 0x39ffdf3f, 0x0, 0x39ffdf3f, 0 },
+ { 0x01f09ff6, 0x0, 0x01f09ff6, 0 },
+ { 0xfddfdffe, 0x0, 0xfddfdffe, 0 },
+ { 0xfffeffe0, 0x0, 0xfffeffe0, 0 },
{ 0x, 0x0, 0x, 0 },
};
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 3c17bcbb18..6745305a59 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -306,17 +306,17 @@ static const struct rcar_gen3_cpg_pll_config
cpg_pll_configs[16] = {
static const struct mstp_stop_table r8a7796_mstp_table[] = {
{ 0x0020, 0x0, 0x0020, 0 },
- { 0x, 0x0, 0x, 0 },
- { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
- { 0xFFDF, 0x400, 0xFFDF, 0 },
- { 0x8184, 0x180, 0x8184, 0 },
- { 0xC3FF, 0x0, 0xC3FF, 0 },
- { 0x, 0x0, 0x, 0 },
- { 0x, 0x0, 0x, 0 },
- { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
- { 0xFFFE, 0x0, 0xFFFE, 0 },
- { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
- { 0x00B7, 0x0, 0x00B7, 0 },
+ { 0xd3e813a0, 0x0, 0xd3e813a0, 0 },
+ { 0x040e2fdc, 0x2000, 0x040e2fdc, 0 },
+ { 0xd00c7cdf, 0x400, 0xd00c7cdf, 0 },
+ { 0x8004, 0x180, 0x8004, 0 },
+ { 0x40dfff46, 0x0, 0x40dfff46, 0 },
+ { 0x84ea888e, 0x0, 0x84ea888e, 0 },
+ { 0x29df5e1c, 0x0, 0x29df5e1c, 0 },
+ { 0x01c01ff7, 0x0, 0x01f01ff7, 0 },
+ { 0xfddfdffe, 0x0, 0xfddfdffe, 0 },
+ { 0xfffeffe0, 0x0, 0xfffeffe0, 0 },
+ { 0x, 0x0, 0x, 0 },
};
static const void *r8a7796_get_pll_config(const u32 cpg_mode)
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c
b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 5f37f6285f..8d792bceee 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -303,18 +303,18 @@ static const struct rcar_gen3_cpg_pll_config
cpg_pll_configs[16] = {
};
static const struct mstp_stop_table r8a77965_mstp_table[] = {
- { 0x0020, 0x0, 0x0020, 0 },
- { 0x, 0x0, 0x, 0 },
- { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
- { 0xFFDF, 0x400, 0xFFDF, 0 },
- { 0x8184, 0x180, 0x8184, 0 },
- { 0xC3FF, 0x0, 0xC3FF, 0 },
- { 0x, 0x0, 0x, 0 },
- { 0x, 0x0, 0x, 0 },
- { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
- { 0xFFFE, 0x0, 0xFFFE, 0 },
- { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
- { 0x00B7, 0x0, 0x00B7, 0 },
+ { 0x0021, 0x0, 0x0021, 0 },
+ { 0xc3e813a0, 0x0, 0xc3e813a0, 0 },
+ { 0x040e2fdc, 0x2000, 0x040e2fdc, 0 },
+ { 0xd0cc7cdf,
[PATCH] ARM: renesas: Scrub duplicate memory nodes from DT on Gen3
Scrub duplicate /memory@* node entries here. Some R-Car DTs might
contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
either generates single /memory node or updates the first /memory
node. Any remaining memory nodes are thus potential duplicates.
However, it is not possible to delete all the memory nodes right
away, since some of those might not be DRAM memory nodes, but some
sort of other memory. Thus, delete only the memory nodes which are
in the R-Car3 DBSC ranges.
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Kconfig | 1 +
board/renesas/rcar-common/common.c | 80 ++
2 files changed, 81 insertions(+)
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 8cef3f5675..41322b2c4c 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -13,6 +13,7 @@ config RCAR_GEN3
select ARM64
select PHY
select CMD_CACHE
+ select OF_BOARD_SETUP
select PINCTRL
select PINCONF
select PINCTRL_PFC
diff --git a/board/renesas/rcar-common/common.c
b/board/renesas/rcar-common/common.c
index e77357968a..c53a74ae74 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -43,4 +43,84 @@ int dram_init_banksize(void)
return 0;
}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
+{
+ struct fdt_resource first_mem_res, curr_mem_res;
+ int curr_mem_reg, first_mem_reg = 0;
+ int ret;
+
+ for (;;) {
+ ret = fdt_get_resource(blob, first_mem_node, "reg",
+ first_mem_reg++, _mem_res);
+ if (ret) /* No more entries, no overlap found */
+ return 0;
+
+ curr_mem_reg = 0;
+ for (;;) {
+ ret = fdt_get_resource(blob, curr_mem_node, "reg",
+ curr_mem_reg++, _mem_res);
+ if (ret) /* No more entries, check next tuple */
+ break;
+
+ if (curr_mem_res.end < first_mem_res.start)
+ continue;
+
+ if (curr_mem_res.start >= first_mem_res.end)
+ continue;
+
+ debug("Overlap found: 0x%llx..0x%llx /
0x%llx..0x%llx\n",
+ first_mem_res.start, first_mem_res.end,
+ curr_mem_res.start, curr_mem_res.end);
+
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /*
+* Scrub duplicate /memory@* node entries here. Some R-Car DTs might
+* contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
+* either generates single /memory node or updates the first /memory
+* node. Any remaining memory nodes are thus potential duplicates.
+*
+* However, it is not possible to delete all the memory nodes right
+* away, since some of those might not be DRAM memory nodes, but some
+* sort of other memory. Thus, delete only the memory nodes which are
+* in the R-Car3 DBSC ranges.
+*/
+ int mem = 0, first_mem_node = 0;
+
+ for (;;) {
+ mem = fdt_node_offset_by_prop_value(blob, mem,
+ "device_type", "memory", 7);
+ if (mem < 0)
+ break;
+ if (!fdtdec_get_is_enabled(blob, mem))
+ continue;
+
+ /* First memory node, patched by U-Boot */
+ if (!first_mem_node) {
+ first_mem_node = mem;
+ continue;
+ }
+
+ /* Check the remaining nodes and delete duplicates */
+ if (!is_mem_overlap(blob, first_mem_node, mem))
+ continue;
+
+ /* Delete duplicate node, start again */
+ fdt_del_node(blob, mem);
+ first_mem_node = 0;
+ mem = 0;
+ }
+
+ return 0;
+}
+#endif
#endif
--
2.30.2
[PATCH] ARM: rmobile: Enable NVMe support on RCar3
Enable support for PCIe NVMe devices. Signed-off-by: Marek Vasut --- configs/rcar3_salvator-x_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index cd250e93d3..c5215d6a5d 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -72,6 +72,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y -- 2.30.2
Re: [PATCH v2 1/2] dm: core: Add size operations on device tree references
On Fri, 2 Apr 2021 at 19:30, chenguanqiao wrote:
>
> Add functions to add size of addresses in the device tree using ofnode
> references.
>
> Signed-off-by: Chen Guanqiao
> ---
> drivers/core/ofnode.c | 9 +
> include/dm/ofnode.h | 10 ++
> 2 files changed, 19 insertions(+)
>
Reviewed-by: Simon Glass
> diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
> index fa0bd2a9c4..952c3cf9dd 100644
> --- a/drivers/core/ofnode.c
> +++ b/drivers/core/ofnode.c
> @@ -347,6 +347,15 @@ fdt_addr_t ofnode_get_addr(ofnode node)
> return ofnode_get_addr_index(node, 0);
> }
>
> +fdt_size_t ofnode_get_size(ofnode node)
> +{
> + fdt_size_t size;
> +
> + ofnode_get_addr_size_index(node, 0, );
size is not set if this function returns an error, so in that can you
need to return something
> +
> + return size;
> +}
> +
> int ofnode_stringlist_search(ofnode node, const char *property,
> const char *string)
> {
> diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
> index 2c0597c407..e91f81282b 100644
> --- a/include/dm/ofnode.h
> +++ b/include/dm/ofnode.h
> @@ -510,6 +510,16 @@ phys_addr_t ofnode_get_addr_index(ofnode node, int
> index);
> */
> phys_addr_t ofnode_get_addr(ofnode node);
>
> +/**
> + * ofnode_get_size() - get size from a node
> + *
> + * This reads the register size from a node
> + *
> + * @node: node to read from
> + * @return size of the address
> + */
> +fdt_size_t ofnode_get_size(ofnode node);
> +
> /**
> * ofnode_stringlist_search() - find a string in a string list and return
> index
> *
> --
> 2.25.1
>
Re: [PATCH v2 2/2] test: dm: add test item for ofnode_get_addr() and ofnode_get_size()
On Fri, 2 Apr 2021 at 19:28, chenguanqiao wrote: > > Add test item for getting address and size functions > > Test the following function: > - ofnode_get_addr() > - ofnode_get_size() > > Signed-off-by: Chen Guanqiao > --- > test/dm/ofnode.c | 24 > 1 file changed, 24 insertions(+) Reviewed-by: Simon Glass
Re: [PATCH v3 1/4] psci: add features/reset2 support
Hi Igor, On Thu, 1 Apr 2021 at 09:16, Igor Opaniuk wrote: > > From: Igor Opaniuk > > Adds support for: > * PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API > that allows discovering whether a specific PSCI function is implemented > and its features. > * SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing > SYSTEM_RESET. It provides support for vendor-specific resets, providing > reset_type as an additional param. > > For additional details visit [1]. > > Implementations of some functions were borrowed from Linux PSCI driver > code [2]. > > [1] https://developer.arm.com/documentation/den0022/latest/ > [2] drivers/firmware/psci/psci.c > > Signed-off-by: Igor Opaniuk > --- > > drivers/firmware/psci.c | 68 + > include/linux/psci.h| 3 ++ > 2 files changed, 71 insertions(+) Do we have a test for this? Regards, Simon
Re: [PATCH 1/1] doc: duplicate target 'youtube'
On Sun, 11 Apr 2021 at 06:36, Heinrich Schuchardt wrote: > > Two external references cannot have the same name: > > doc/chromium/overview.rst:5: > WARNING: Duplicate explicit target name: "youtube" > > Signed-off-by: Heinrich Schuchardt > --- > doc/chromium/overview.rst | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass
[PATCH] ARM: rmobile: Enable CONFIG_SYS_FLASH_PROTECTION
Enable CONFIG_SYS_FLASH_PROTECTION on Salvator-X(S), ULCB, Ebisu,
which means the Spansion HF PPB protection bits can be operated
using the 'protect' U-Boot command.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
configs/r8a77990_ebisu_defconfig | 3 +++
configs/rcar3_salvator-x_defconfig | 3 +++
configs/rcar3_ulcb_defconfig | 3 +++
include/configs/ebisu.h| 2 --
include/configs/salvator-x.h | 2 --
include/configs/ulcb.h | 2 --
6 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index cb75b5c3a6..d5797378b0 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -58,7 +58,10 @@ CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CFI_FLASH=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/rcar3_salvator-x_defconfig
b/configs/rcar3_salvator-x_defconfig
index 6109a23a31..cd250e93d3 100644
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -60,7 +60,10 @@ CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CFI_FLASH=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
index df202a7598..e345086f30 100644
--- a/configs/rcar3_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig
@@ -60,9 +60,12 @@ CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CFI_FLASH=y
CONFIG_RENESAS_RPC_HF=y
+CONFIG_FLASH_CFI_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_PHY_MICREL=y
diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h
index ee9ddb1336..19ec74fb58 100644
--- a/include/configs/ebisu.h
+++ b/include/configs/ebisu.h
@@ -23,8 +23,6 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_MTD
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST{ 0x0800 }
diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
index db06fa5ffd..1eafff10ff 100644
--- a/include/configs/salvator-x.h
+++ b/include/configs/salvator-x.h
@@ -20,8 +20,6 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_MTD
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST{ 0x0800 }
diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h
index 165c82d508..1ce844f492 100644
--- a/include/configs/ulcb.h
+++ b/include/configs/ulcb.h
@@ -20,8 +20,6 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_MTD
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST{ 0x0800 }
--
2.30.2
[PATCH] mtd: cfi: Fix PPB lock status readout
According to S26KL512S datasheet [1] and S29GL01GS datasheet [2],
the procedure to read out PPB lock bits is to send the PPB Entry,
PPB Read, Reset/ASO Exit. Currently, the code does send incorrect
PPB Entry, PPB Read and Reset/ASO Exit is completely missing.
The PPB Entry sent is implemented by sending flash_unlock_seq()
and flash_write_cmd(..., FLASH_CMD_READ_ID). This translates to
sequence 0x555:0xaa, 0x2aa:0x55, 0x555:0x90=FLASH_CMD_READ_ID.
However, both [1] and [2] specify the last byte of PPB Entry as
0xc0=AMD_CMD_SET_PPB_ENTRY instead of 0x90=FLASH_CMD_READ_ID,
that is 0x555:0xaa, 0x2aa:0x55, 0x555:0xc0=AMD_CMD_SET_PPB_ENTRY.
Since this does make sense, this patch fixes it and thus also
aligns the code in flash_get_size() with flash_real_protect().
The PPB Read returns 00h in case of Protected state and 01h in case
of Unprotected state, according to [1] Note 83 and [2] Note 17, so
invert the result. Moreover, align the arguments with similar code
in flash_real_protect().
Finally, Reset/ASO Exit command should be executed to exit the PPB
mode, so add the missing reset.
[1] https://www.cypress.com/file/213346/download
Document Number: 001-99198 Rev. *M
Table 40. Command Definitions, Nonvolatile Sector Protection
Command Set Definitions
[2] https://www.cypress.com/file/177976/download
Document Number: 001-98285 Rev. *R
Table 7.1 Command Definitions, Nonvolatile Sector Protection
Command Set Definitions
Fixes: 03deff433e ("cfi_flash: Read PPB sector protection from device for
AMD/Spansion chips")
Signed-off-by: Marek Vasut
Cc: Stefan Roese
---
drivers/mtd/cfi_flash.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 9642d7c7dc..9c27fea5d8 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2276,12 +2276,12 @@ ulong flash_get_size(phys_addr_t base, int banknum)
flash_unlock_seq(info, 0);
flash_write_cmd(info, 0,
info->addr_unlock1,
- FLASH_CMD_READ_ID);
+ AMD_CMD_SET_PPB_ENTRY);
info->protect[sect_cnt] =
- flash_isset(
- info, sect_cnt,
- FLASH_OFFSET_PROTECT,
- FLASH_STATUS_PROTECT);
+ !flash_isset(info, sect_cnt,
+0, 0x01);
+ flash_write_cmd(info, 0, 0,
+ info->cmd_reset);
break;
default:
/* default: not protected */
--
2.30.2
Re: Please pull u-boot-video
On Sat, Apr 10, 2021 at 11:21:03PM +0200, Anatolij Gustschin wrote: > Hi Tom, > > please pull video patches for v2021.07-rc1. > > gitlab CI: > https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/7124 > > Thanks, > Anatolij > > The following changes since commit a1e95e3805eacca1162f6049dceb9b1d2726cbf5: > > Merge tag 'u-boot-imx-20210409' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2021-04-09 10:08:52 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-video.git > tags/video-2021-07-rc1 > > for you to fetch changes up to 38e18d6392fca9f6809cb3079af3069efc3d181f: > > video: Fix line padding calculation for 16 and 24 BPP bitmaps (2021-04-10 > 17:09:59 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH] doc: imx: psb: Fix missing setexpr arguments
Due to copy-paste error, two of the setexpr arguments were missing.
Add the missing arguments.
Signed-off-by: Marek Vasut
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
doc/imx/misc/psb.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/imx/misc/psb.rst b/doc/imx/misc/psb.rst
index 4d6f001b74..1458126b5a 100644
--- a/doc/imx/misc/psb.rst
+++ b/doc/imx/misc/psb.rst
@@ -150,7 +150,7 @@ Examples of writing SIT and two copies of bootloader to SD
or eMMC:
=> mmc write ${loadaddr} 0x41 0x1
=> dhcp ${loadaddr} flash.bin
-=> setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt
+=> setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
=> mmc dev 1
=> mmc write ${loadaddr} 0x42 ${blkcnt}
=> mmc write ${loadaddr} 0x1042 ${blkcnt}
--
2.30.2
Re: [PATCH 1/1] doc: imx: psb: fix footnotes
On 4/11/21 5:06 PM, Heinrich Schuchardt wrote: In reStructured text footnotes are referenced like [1]_. Add missing underscores. Signed-off-by: Heinrich Schuchardt Acked-by: Marek Vasut Thanks
[PATCH V2 24/24] ARM: imx8m: verdin-imx8mm: Enable USB Host support
Enable USB host support on MX8MM Verdin. Signed-off-by: Marek Vasut Cc: Marcel Ziswiler Cc: Max Krummenacher Cc: Oleksandr Suvorov --- V2: No change --- configs/verdin-imx8mm_defconfig | 8 +++- include/configs/verdin-imx8mm.h | 5 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index ea0b5978f1..c8c3420b6a 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -37,7 +37,6 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SYS_PROMPT="Verdin iMX8MM # " # CONFIG_BOOTM_NETBSD is not set @@ -50,6 +49,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_REGULATOR=y @@ -89,6 +89,8 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_PMIC_PFUZE100=y @@ -101,5 +103,9 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 4751bf5a5a..e2a817891c 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -117,5 +117,10 @@ #define FEC_QUIRK_ENET_MAC #define IMX_FEC_BASE 0x30BE +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + #endif /*_VERDIN_IMX8MM_H */ -- 2.30.2
[PATCH V2 23/24] usb: ehci-mx6: Add iMX8M support
The iMX8M uses nop PHY, select PHY and NOP_PHY automatically. Otherwise, the DM capable driver is now perfectly compatible. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Cc: Ye Li Cc: uboot-imx --- V2: Permit the driver on all iMX8M SoCs, not just iMX8MM --- drivers/usb/host/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0971a7c813..bf5d82f035 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -156,7 +156,9 @@ config USB_EHCI_MX6 config USB_EHCI_MX7 bool "Support for i.MX7 on-chip EHCI USB controller" - depends on ARCH_MX7 + depends on ARCH_MX7 || IMX8M + select PHY if IMX8M + select NOP_PHY if IMX8M default y ---help--- Enables support for the on-chip EHCI controller on i.MX7 SoCs. -- 2.30.2
[PATCH V2 21/24] usb: ehci-mx6: Add fsl,imx7d-usb compatible string
Add new compatible string, used by some more up-to-date DTs.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Cc: uboot-imx
---
V2: No change
---
drivers/usb/host/ehci-mx6.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index d3308c60ee..28db593b7e 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -749,6 +749,7 @@ int ehci_usb_remove(struct udevice *dev)
static const struct udevice_id mx6_usb_ids[] = {
{ .compatible = "fsl,imx27-usb" },
+ { .compatible = "fsl,imx7d-usb" },
{ }
};
--
2.30.2
