Re: [PATCH v1 08/10] net: mvpp2: fix missing switch case break
On 29.04.21 22:24, Ramon Fried wrote: On Tue, Apr 27, 2021 at 4:28 PM Stefan Roese wrote: From: Ben Peled Signed-off-by: Ben Peled Reviewed-by: Stefan Chulski Reviewed-by: Kostya Porotchkin Tested-by: sa_ip-sw-jenkins Please remove this, Jenkins is not a person. I've left these lines in because most of these patches are plain cherry-picked from the Marvell SDK. Should I resubmit this patch only or the complete patchset? Or could you perhaps remove this line while collecting the patches for a pull request? Thanks, Stefan Signed-off-by: Stefan Roese --- drivers/net/mvpp2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 61a0ea0894a7..3d920e85ffef 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -3247,9 +3247,11 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port) case PHY_INTERFACE_MODE_1000BASEX: gop_gmac_1000basex_cfg(port); + break; case PHY_INTERFACE_MODE_2500BASEX: gop_gmac_2500basex_cfg(port); + break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: -- 2.31.1 Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 04/13] gpio: Introduce CONFIG_ONLY_GENERIC_GPIO to cleanup #ifdefs
Hi Simon, 2021年4月30日(金) 1:10 Simon Glass : > > Hi Masami, > > On Fri, 16 Apr 2021 at 16:38, Masami Hiramatsu > wrote: > > > > Many architecture do not have specific asm/arch/gpio.h, so instead > > of adding !defined(CONFIG_ARCH_xxx), introduce CONFIG_ONLY_GENERIC_GPIO > > This seems OK, but I think GPIO_GENERIC_ONLY is a better name, since > it uses the GPIO prefix. > > I would also prefer to have a 'positive' option, but I suspect that > might be a pain to do? Would you mean making it something like CONFIG_GPIO_EXTRA_HEADER ? I think it is also possible. My concern is if I missed any arch which should say y that :P. Thank you, > > > and select it. > > > > Signed-off-by: Masami Hiramatsu > > --- > > arch/arm/Kconfig | 17 + > > arch/arm/include/asm/gpio.h |8 +--- > > board/cortina/common/Kconfig |1 + > > 3 files changed, 19 insertions(+), 7 deletions(-) > > > > [..] > > Regards, > Simon -- Masami Hiramatsu
Re: [PATCH v3 5/7] image-fdt: save no-map parameter of reserve-memory
Hi Simon, On Fri, Apr 30, 2021 at 12:13 AM Simon Glass wrote: > > Hi Patrick, > > On Wed, 28 Apr 2021 at 03:23, Patrick Delaunay > wrote: > > > > Save the no-map information present in 'reserved-memory' node to allow > > correct handling when the MMU is configured in board to avoid > > speculative access. > > > > Signed-off-by: Patrick Delaunay > > --- > > > > (no changes since v1) > > > > common/image-fdt.c | 23 +++ > > 1 file changed, 15 insertions(+), 8 deletions(-) > > Where is no-map documented? See Linux kernel Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt > > Reviewed-by: Simon Glass Regards, Bin
Please pull u-boot-dm
Hi Tom, https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/7344 The following changes since commit 79b0f08d6af498e6fda8cd257d62e2095764410c: configs: Resync with savedefconfig (2021-04-27 08:28:38 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-dm.git tags/dm-pull-29apr21 for you to fetch changes up to 5b700cdcff61426843405ca1df4b549237e8bbc2: tpm: missing event types (2021-04-29 04:10:55 -0700) buildman environment fix binman FMAP improvements minor test improvements and fixes minor dm improvements Andy Shevchenko (2): test: Allow simple glob pattern in the test name test: Use positive conditional in test_matches() Chen Guanqiao (2): dm: core: Add size operations on device tree references test: dm: add test item for ofnode_get_addr() and ofnode_get_size() Evan Benn (1): patman: Parse checkpatch by message instead of by line Heinrich Schuchardt (1): tpm: missing event types Patrick Delaunay (1): dm: core: Add address translation in fdt_get_resource Sean Anderson (1): dm: core: Fix uninitialized return value from dm_scan_fdt_node Simon Glass (8): binman: Correct testSplNoDtb() and Tpl also dtoc: Correct dtoc output when testing binman: Tweak implementation of fmap binman: Support adding sections to FMAPs buildman: Tidy up a few comments buildman: Use common code to send an result buildman: Handle exceptions in threads gracefully buildman: Use bytes for the environment Tom Rini (3): Azure/GitLab: Ensure we use requirements.txt for testsuites tests: patman: Add requests to the module list patman: Assume we always have pygit2 for tests .azure-pipelines.yml | 2 +- .gitlab-ci.yml | 2 +- drivers/core/ofnode.c | 11 ++ drivers/core/root.c| 2 +- drivers/firmware/scmi/smt.c| 12 +- drivers/net/mscc_eswitch/jr2_switch.c | 4 +- drivers/net/mscc_eswitch/ocelot_switch.c | 4 +- drivers/net/mscc_eswitch/serval_switch.c | 4 +- drivers/net/mscc_eswitch/servalt_switch.c | 4 +- include/dm/ofnode.h| 10 ++ include/fdtdec.h | 5 +- include/tpm-v2.h | 24 ++-- lib/fdtdec.c | 6 +- scripts/checkpatch.pl | 18 +-- test/dm/ofnode.c | 31 test/py/requirements.txt | 1 + test/test-main.c | 23 +-- tools/binman/entries.rst | 13 +- tools/binman/etype/fmap.py | 19 ++- tools/binman/ftest.py | 86 tools/binman/test/095_fmap_x86_section.dts | 2 +- tools/buildman/builder.py | 22 ++- tools/buildman/builderthread.py| 50 +-- tools/buildman/control.py | 18 ++- tools/buildman/func_test.py| 40 +- tools/buildman/toolchain.py| 24 ++-- tools/dtoc/dtb_platdata.py | 24 +--- tools/dtoc/test_dtoc.py| 51 +++ tools/patman/checkpatch.py | 218 ++--- tools/patman/func_test.py | 19 +-- 30 files changed, 472 insertions(+), 277 deletions(-) Regards, Simon
Re: [PATCH] Makefile: Fix generation of flash.bin u-boot.itb with binman
On Sat, Apr 24, 2021 at 8:57 PM Marek Vasut wrote: > > On 2/25/21 9:50 PM, Marek Vasut wrote: > > In case binman is enabled, the u-boot.itb is generated using this tool > > and there is no direct u-boot.itb target, but instead the binman tool > > must be invoked. Add support for this case. > > > > Signed-off-by: Marek Vasut > > Cc: Peng Fan > > Cc: Stefano Babic > > This bugfix is still missing from upstream. + Simon
Re: [PATCH 03/17] x86: Allow coreboot serial driver to guess the UART
Hi Simon,
On Fri, Apr 30, 2021 at 12:10 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Sun, 25 Apr 2021 at 18:21, Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Sun, Apr 25, 2021 at 10:10 AM Simon Glass wrote:
> > >
> > > Hi Bin,
> > >
> > > On Sun, 25 Apr 2021 at 13:49, Bin Meng wrote:
> > > >
> > > > Hi Simon,
> > > >
> > > > On Sat, Apr 24, 2021 at 12:56 PM Simon Glass wrote:
> > > > >
> > > > > Hi Bin,
> > > > >
> > > > > On Thu, 8 Apr 2021 at 14:23, Bin Meng wrote:
> > > > > >
> > > > > > Hi Simon,
> > > > > >
> > > > > > On Wed, Apr 7, 2021 at 12:32 PM Simon Glass
> > > > > > wrote:
> > > > > > >
> > > > > > > At present this driver relies on coreboot to provide information
> > > > > > > about
> > > > > > > the console UART. However if coreboot is not compiled with the
> > > > > > > UART
> > > > > > > enabled, the information is left out. This configuration is quite
> > > > > > > common, e.g. with shipping x86-based Chrome OS Chromebooks.
> > > > > > >
> > > > > > > Add a way to determine the UART settings in this case, using a
> > > > > > > hard-coded list of PCI IDs.
> > > > > > >
> > > > > > > Signed-off-by: Simon Glass
> > > > > > > ---
> > > > > > >
> > > > > > > drivers/serial/serial_coreboot.c | 68
> > > > > > >
> > > > > > > include/pci_ids.h| 1 +
> > > > > > > 2 files changed, 61 insertions(+), 8 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/serial/serial_coreboot.c
> > > > > > > b/drivers/serial/serial_coreboot.c
> > > > > > > index de09c8681f5..4b4619432d8 100644
> > > > > > > --- a/drivers/serial/serial_coreboot.c
> > > > > > > +++ b/drivers/serial/serial_coreboot.c
> > > > > > > @@ -11,19 +11,71 @@
> > > > > > > #include
> > > > > > > #include
> > > > > > >
> > > > > > > +static const struct pci_device_id ids[] = {
> > > > > > > + { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> > > > > > > PCI_DEVICE_ID_INTEL_APL_UART2) },
> > > > > > > + {},
> > > > > > > +};
> > > > > > > +
> > > > > > > +/*
> > > > > > > + * Coreboot only sets up the UART if it uses it and doesn't
> > > > > > > bother to put the
> > > > > > > + * details in sysinfo if it doesn't. Try to guess in that case,
> > > > > > > using devices
> > > > > > > + * we know about
> > > > > > > + *
> > > > > > > + * @plat: Platform data to fill in
> > > > > > > + * @return 0 if found, -ve if no UART was found
> > > > > > > + */
> > > > > > > +static int guess_uart(struct ns16550_plat *plat)
> > > > > >
> > > > > > This is really not a guess, but use a pre-configured platform data.
> > > > > > Also this only work for Apollo Lake board, and will break other
> > > > > > boards
> > > > > > if they don't have cbinfo available.
> > > > >
> > > > > Which bit of it breaks other boards?
> > > >
> > > > I see it does not return the error code to the caller, that's okay ...
> > > >
> > > > >
> > > > > >
> > > > > > Why not just simply put a serial node in the device tree and we are
> > > > > > all done?
> > > > >
> > > > > See my other email...I am trying to make this boot on any board that
> > > > > coreboot supports.
> > > >
> > > > But this solution does not scale. One has to put all known UARTs into
> > > > serial_coreboot.c.
> > >
> > > Yes that's right...but this is only for when coreboot does not enable
> > > serial. Also the number of new platforms is not that great.
> > >
> > > >
> > > > Why not patch coreboot instead? Why coreboot does not provide a cbinfo
> > > > with serial?
> > >
> > > Because it does not even set up the serial device in that case, so
> > > doesn't know the details. The driver is completely missing.
> >
> > Sigh. Is it possible to upstream a patch to coreboot to enable that?
>
> Well I'm not even sure upstream coreboot boots on the various
> Chromebooks I am targetting. If it does, then serial is probablt
> enabled. But certainly for chromebooks, it is not. My goal is to have
> U-Boot boot on a chromebook in altfw mode with serial enabled.
>
> >
> > I don't like the current approach because it ends up duplicating all
> > UART IDs/info in C.
>
> Yes. Do you think it would be better to put it in the devicetree? I
> suppose we could add some more stuff to the compatible string,
> although U-Boot does not support the PCI compatible strings at
> present.
Putting it in the device tree also looks odd, because it only matters
on a dedicated board.
> What do you suggest?
Or parse the ACPI table coreboot has set up? But that might be another
huge monster :(
Regards,
Bin
Re: Qemu U-boot Standalone Application Crash
Hi, On Fri, Apr 30, 2021 at 1:20 AM prashant basva wrote: > > Hi, > i am trying to execute standalone application from qemu u-boot, but when i > trued to execute using go or bootm , its getting crashed saying trap > Below is command used to launch qemu ppc u-boot > $ sudo qemu-system-ppc -m 1024 -M mpc8544ds -cpu MPC8548 -no-reboot > -nographic -net nic,model=e1000 -net If there is no special reason of using machine "mpc8544ds", you can try machine "ppce500" instead. See https://u-boot.readthedocs.io/en/latest/board/emulation/qemu-ppce500.html for instructions. > tap,ifname=vnet0,script=no,downscript=no u-boot.bin > > -- > > WARNING: Image format was not specified for 'u-boot.bin' and probing > guessed raw. > Automatically detecting the format is dangerous for raw images, > write operations on block 0 will be restricted. > Specify the 'raw' format explicitly to remove the restrictions. > > [snip] Regards, Bin
Re: [PATCH] net: phy: micrel: Get phy node from phy-handle
On Mon, Apr 26, 2021 at 6:43 AM Ley Foon Tan wrote:
>
> If can't find ethernet-phy subnode, try to get phy node from "phy-handle".
> Lastly, only use Ethernet node if can't find phy node from ethernet-phy
> subnode and phy-handle.
>
> Signed-off-by: Ley Foon Tan
> ---
> drivers/net/phy/micrel_ksz90x1.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/phy/micrel_ksz90x1.c
> b/drivers/net/phy/micrel_ksz90x1.c
> index e5f578201f35..e33789b7f747 100644
> --- a/drivers/net/phy/micrel_ksz90x1.c
> +++ b/drivers/net/phy/micrel_ksz90x1.c
> @@ -112,6 +112,7 @@ static int ksz90x1_of_config_group(struct phy_device
> *phydev,
> {
> struct udevice *dev = phydev->dev;
> struct phy_driver *drv = phydev->drv;
> + struct ofnode_phandle_args phandle;
> int val[4];
> int i, changed = 0, offset, max;
> u16 regval = 0;
> @@ -128,8 +129,14 @@ static int ksz90x1_of_config_group(struct phy_device
> *phydev,
> }
>
> if (!ofnode_valid(node)) {
> - /* No node found, look in the Ethernet node */
> - node = dev_ofnode(dev);
> + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> + )) {
> + /* No phy-handle found, look in the Ethernet node */
> + node = dev_ofnode(dev);
> + } else {
> + /* phy-handle found */
> + node = phandle.node;
> + }
> }
>
> for (i = 0; i < ofcfg->grpsz; i++) {
> --
> 2.25.1
>
Reviewed-by: Ramon Fried
Re: [PATCH v1 09/10] net: mvpp2: allow MDIO registration for fixed links
On Tue, Apr 27, 2021 at 4:29 PM Stefan Roese wrote:
>
> From: Stefan Chulski
>
> Currently, there are 2 valid cases for interface, PHY
> and mdio relation:
> - If an interface has PHY handler, it'll call
> mdio_mii_bus_get_from_phy(), which will register
> MDIO bus.
> - If we want to use fixed-link for an interface,
> PHY handle is not defined in the DTS, and no
> MDIO is registered.
>
> There is a third case, for some boards (with switch),
> the MDIO is used for switch configuration, but the interface
> itself uses fixed link. This patch allows this option by
> checking if fixed-link subnode is defined, in this case,
> MDIO bus is registers, but the PHY address is set to
> PHY_MAX_ADDR for this interface, so this interface will
> not try to access the PHY later on.
>
> Signed-off-by: Stefan Chulski
> Signed-off-by: Stefan Roese
> ---
>
> drivers/net/mvpp2.c | 17 +
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index 3d920e85ffef..c5bfe41281d6 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -4787,16 +4787,25 @@ static int phy_info_parse(struct udevice *dev, struct
> mvpp2_port *port)
> u32 id;
> u32 phyaddr = 0;
> int phy_mode = -1;
> + int fixed_link = 0;
> int ret;
>
> phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
> + fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node,
> "fixed-link");
>
> if (phy_node > 0) {
> int parent;
> - phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
> - if (phyaddr < 0) {
> - dev_err(dev, "could not find phy address\n");
> - return -1;
> +
> + if (fixed_link != -FDT_ERR_NOTFOUND) {
> + /* phy_addr is set to invalid value for fixed links */
> + phyaddr = PHY_MAX_ADDR;
> + } else {
> + phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node,
> +"reg", 0);
> + if (phyaddr < 0) {
> + dev_err(dev, "could not find phy address\n");
> + return -1;
> + }
> }
> parent = fdt_parent_offset(gd->fdt_blob, phy_node);
> ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
> --
> 2.31.1
>
Reviewed-by: Ramon Fried
Re: [PATCH v1 10/10] net: mvpp2: add explicit sgmii-2500 support
On Tue, Apr 27, 2021 at 4:29 PM Stefan Roese wrote:
>
> From: Marcin Wojtas
>
> Until now the mvpp2 driver used an extra 'phy-speed'
> DT property in order to differentiate between the
> SGMII and SGMII @2.5GHz. As there is a dedicated
> PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter
> start using it and drop the custom flag.
>
> Signed-off-by: Marcin Wojtas
> Reviewed-by: Stefan Chulski
> Reviewed-by: Nadav Haklai
> Tested-by: Nadav Haklai
> Signed-off-by: Stefan Roese
> ---
>
> drivers/net/mvpp2.c | 28
> 1 file changed, 12 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index c5bfe41281d6..4c0a7b0a9f5c 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -976,8 +976,6 @@ struct mvpp2_port {
> unsigned int duplex;
> unsigned int speed;
>
> - unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
> -
> struct mvpp2_bm_pool *pool_long;
> struct mvpp2_bm_pool *pool_short;
>
> @@ -2875,6 +2873,7 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
>
> switch (port->phy_interface) {
> case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_SGMII_2500:
> val |= MVPP2_GMAC_INBAND_AN_MASK;
> break;
> case PHY_INTERFACE_MODE_1000BASEX:
> @@ -2942,6 +2941,7 @@ static void mvpp2_port_loopback_set(struct mvpp2_port
> *port)
> val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
>
> if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
> + port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 ||
> port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
> port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
> val |= MVPP2_GMAC_PCS_LB_EN_MASK;
> @@ -3239,12 +3239,11 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port)
> /* Set TX FIFO thresholds */
> switch (port->phy_interface) {
> case PHY_INTERFACE_MODE_SGMII:
> - if (port->phy_speed == 2500)
> - gop_gmac_sgmii2_5_cfg(port);
> - else
> - gop_gmac_sgmii_cfg(port);
> + gop_gmac_sgmii_cfg(port);
> + break;
> + case PHY_INTERFACE_MODE_SGMII_2500:
> + gop_gmac_sgmii2_5_cfg(port);
> break;
> -
> case PHY_INTERFACE_MODE_1000BASEX:
> gop_gmac_1000basex_cfg(port);
> break;
> @@ -3425,6 +3424,7 @@ static int gop_port_init(struct mvpp2_port *port)
> break;
>
> case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_SGMII_2500:
> case PHY_INTERFACE_MODE_1000BASEX:
> case PHY_INTERFACE_MODE_2500BASEX:
> /* configure PCS */
> @@ -3484,6 +3484,7 @@ static void gop_port_enable(struct mvpp2_port *port,
> int enable)
> case PHY_INTERFACE_MODE_RGMII:
> case PHY_INTERFACE_MODE_RGMII_ID:
> case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_SGMII_2500:
> case PHY_INTERFACE_MODE_1000BASEX:
> case PHY_INTERFACE_MODE_2500BASEX:
> if (enable)
> @@ -3520,6 +3521,7 @@ static u32 mvpp2_netc_cfg_create(int gop_id,
> phy_interface_t phy_type)
>
> if (gop_id == 2) {
> if (phy_type == PHY_INTERFACE_MODE_SGMII ||
> + phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
> phy_type == PHY_INTERFACE_MODE_1000BASEX ||
> phy_type == PHY_INTERFACE_MODE_2500BASEX)
> val |= MV_NETC_GE_MAC2_SGMII;
> @@ -3530,6 +3532,7 @@ static u32 mvpp2_netc_cfg_create(int gop_id,
> phy_interface_t phy_type)
>
> if (gop_id == 3) {
> if (phy_type == PHY_INTERFACE_MODE_SGMII ||
> + phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
> phy_type == PHY_INTERFACE_MODE_1000BASEX ||
> phy_type == PHY_INTERFACE_MODE_2500BASEX)
> val |= MV_NETC_GE_MAC3_SGMII;
> @@ -4528,6 +4531,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
> case PHY_INTERFACE_MODE_RGMII:
> case PHY_INTERFACE_MODE_RGMII_ID:
> case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_SGMII_2500:
> case PHY_INTERFACE_MODE_1000BASEX:
> case PHY_INTERFACE_MODE_2500BASEX:
> mvpp2_gmac_max_rx_size_set(port);
> @@ -4838,15 +4842,6 @@ static int phy_info_parse(struct udevice *dev, struct
> mvpp2_port *port)
> >phy_tx_disable_gpio, GPIOD_IS_OUT);
> #endif
>
> - /*
> -* ToDo:
> -* Not sure if this DT property "phy-speed" will get accepted, so
> -* this might change later
> -*/
> - /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
> - port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
> -
Re: [PATCH v1 08/10] net: mvpp2: fix missing switch case break
On Tue, Apr 27, 2021 at 4:28 PM Stefan Roese wrote: > > From: Ben Peled > > Signed-off-by: Ben Peled > Reviewed-by: Stefan Chulski > Reviewed-by: Kostya Porotchkin > Tested-by: sa_ip-sw-jenkins Please remove this, Jenkins is not a person. > Signed-off-by: Stefan Roese > --- > > drivers/net/mvpp2.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c > index 61a0ea0894a7..3d920e85ffef 100644 > --- a/drivers/net/mvpp2.c > +++ b/drivers/net/mvpp2.c > @@ -3247,9 +3247,11 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port) > > case PHY_INTERFACE_MODE_1000BASEX: > gop_gmac_1000basex_cfg(port); > + break; > > case PHY_INTERFACE_MODE_2500BASEX: > gop_gmac_2500basex_cfg(port); > + break; > > case PHY_INTERFACE_MODE_RGMII: > case PHY_INTERFACE_MODE_RGMII_ID: > -- > 2.31.1 >
Re: [PATCH v1 04/10] net: mvpp2: remove redundant SMI address configuration
On Tue, Apr 27, 2021 at 4:28 PM Stefan Roese wrote:
>
> From: Marcin Wojtas
>
> Because the mvpp2 driver now relies on the PHYLIB and
> the external MDIO driver, configuring low level
> SMI bus settings is redundant.
>
> Signed-off-by: Marcin Wojtas
> Tested-by: sa_ip-sw-jenkins
> Reviewed-by: Kostya Porotchkin
> Reviewed-by: Stefan Chulski
> Signed-off-by: Stefan Roese
> ---
>
> drivers/net/mvpp2.c | 12
> 1 file changed, 12 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index 847007d5b487..2043bdf10aa4 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -5292,14 +5292,6 @@ static int mvpp2_write_hwaddr(struct udevice *dev)
> return mvpp2_prs_update_mac_da(port, port->dev_addr);
> }
>
> -static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
> -{
> - writel(port->phyaddr, port->priv->iface_base +
> - MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
> -
> - return 0;
> -}
> -
> static int mvpp2_base_probe(struct udevice *dev)
> {
> struct mvpp2 *priv = dev_get_priv(dev);
> @@ -5422,10 +5414,6 @@ static int mvpp2_probe(struct udevice *dev)
> port->base = priv->iface_base + MVPP22_PORT_BASE +
> port->gop_id * MVPP22_PORT_OFFSET;
>
> - /* Set phy address of the port */
> - if (port->phyaddr < PHY_MAX_ADDR)
> - mvpp22_smi_phy_addr_cfg(port);
> -
> /* GoP Init */
> gop_port_init(port);
> }
> --
> 2.31.1
>
Reviewed-by: Ramon Fried
Re: [PATCH v1 03/10] net: mvpp2: add 1000BaseX and 2500BaseX ppv2 support
On Tue, Apr 27, 2021 at 4:28 PM Stefan Roese wrote:
>
> From: Stefan Chulski
>
> Signed-off-by: Stefan Chulski
> Signed-off-by: Stefan Roese
> ---
>
> drivers/net/mvpp2.c | 117 ++--
> 1 file changed, 112 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index 015f5329de74..847007d5b487 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -2880,6 +2880,10 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
> case PHY_INTERFACE_MODE_SGMII:
> val |= MVPP2_GMAC_INBAND_AN_MASK;
> break;
> + case PHY_INTERFACE_MODE_1000BASEX:
> + case PHY_INTERFACE_MODE_2500BASEX:
> + val &= ~MVPP2_GMAC_INBAND_AN_MASK;
> + break;
> case PHY_INTERFACE_MODE_RGMII:
> case PHY_INTERFACE_MODE_RGMII_ID:
> val |= MVPP2_GMAC_PORT_RGMII_MASK;
> @@ -2940,7 +2944,9 @@ static void mvpp2_port_loopback_set(struct mvpp2_port
> *port)
> else
> val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
>
> - if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
> + if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
> + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
> + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
> val |= MVPP2_GMAC_PCS_LB_EN_MASK;
> else
> val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
> @@ -3051,10 +3057,10 @@ static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port
> *port)
>
> val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
> /*
> -* Configure GIG MAC to 1000Base-X mode connected to a fiber
> +* Configure GIG MAC to SGMII mode connected to a fiber
> * transceiver
> */
> - val |= MVPP2_GMAC_PORT_TYPE_MASK;
> + val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
> writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
>
> /* configure AN 0x9268 */
> @@ -3106,6 +3112,89 @@ static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
> writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
> }
>
> +static void gop_gmac_2500basex_cfg(struct mvpp2_port *port)
> +{
> + u32 val, thresh;
> +
> + /*
> +* Configure minimal level of the Tx FIFO before the lower part
> +* starts to read a packet
> +*/
> + thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
> + val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
> + val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
> + val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
> + writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
> +
> + /* Disable bypass of sync module */
> + val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
> + val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
> + /* configure DP clock select according to mode */
> + val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
> + /* configure QSGMII bypass according to mode */
> + val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
> + writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
> +
> + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
> + /*
> +* Configure GIG MAC to 2500Base-X mode connected to a fiber
> +* transceiver
> +*/
> + val |= MVPP2_GMAC_PORT_TYPE_MASK;
> + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
> +
> + /* In 2500BaseX mode, we can't negotiate speed
> +* and we do not want InBand autoneg
> +* bypass enabled (link interrupt storm risk
> +* otherwise).
> +*/
> + val = MVPP2_GMAC_EN_PCS_AN |
> + MVPP2_GMAC_CONFIG_GMII_SPEED |
> + MVPP2_GMAC_CONFIG_FULL_DUPLEX |
> + MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
> + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
> +}
> +
> +static void gop_gmac_1000basex_cfg(struct mvpp2_port *port)
> +{
> + u32 val, thresh;
> +
> + /*
> +* Configure minimal level of the Tx FIFO before the lower part
> +* starts to read a packet
> +*/
> + thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
> + val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
> + val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
> + val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
> + writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
> +
> + /* Disable bypass of sync module */
> + val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
> + val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
> + /* configure DP clock select according to mode */
> + val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
> + /* configure QSGMII bypass according to mode */
> + val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
> + writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
> +
> + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
> + /* configure GIG MAC to 1000BASEX mode */
>
Re: [PATCH v1 02/10] net: mvpp2: add CP115 port1 10G/5G SFI support
On Tue, Apr 27, 2021 at 4:27 PM Stefan Roese wrote:
>
> From: Stefan Chulski
>
> 1. Differ between Port1 RGMII and SFI modes in Netcomplex config.
> 2. Remove XPCS config from SFI mode.
>Port1 doesn't XPCS domain, XPCS config should be removed.
>Access to Port1 XPCS can cause stall.
> 3. Add Port1 MPCS configurations.
>
> Signed-off-by: Stefan Chulski
> Signed-off-by: Stefan Roese
> ---
>
> drivers/net/mvpp2.c | 75 ++---
> 1 file changed, 17 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index 1cf522b8fe57..015f5329de74 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -520,8 +520,9 @@ do {
> \
> /* Net Complex */
> enum mv_netc_topology {
> MV_NETC_GE_MAC2_SGMII = BIT(0),
> - MV_NETC_GE_MAC3_SGMII = BIT(1),
> - MV_NETC_GE_MAC3_RGMII = BIT(2),
> + MV_NETC_GE_MAC2_RGMII = BIT(1),
> + MV_NETC_GE_MAC3_SGMII = BIT(2),
> + MV_NETC_GE_MAC3_RGMII = BIT(3),
> };
>
> enum mv_netc_phase {
> @@ -3208,56 +3209,31 @@ static int gop_gpcs_reset(struct mvpp2_port *port,
> int reset)
> return 0;
> }
>
> -/* Set the internal mux's to the required PCS in the PI */
> -static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
> -{
> - u32 val;
> - int lane;
> -
> - switch (num_of_lanes) {
> - case 1:
> - lane = 0;
> - break;
> - case 2:
> - lane = 1;
> - break;
> - case 4:
> - lane = 2;
> - break;
> - default:
> - return -1;
> - }
> -
> - /* configure XG MAC mode */
> - val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
> - val &= ~MVPP22_XPCS_PCSMODE_MASK;
> - val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
> - val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
> - writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
> -
> - return 0;
> -}
> -
> static int gop_mpcs_mode(struct mvpp2_port *port)
> {
> u32 val;
>
> /* configure PCS40G COMMON CONTROL */
> - val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
> + val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET
> +
> + PCS40G_COMMON_CONTROL);
> val &= ~FORWARD_ERROR_CORRECTION_MASK;
> - writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
> + writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET
> +
> + PCS40G_COMMON_CONTROL);
>
> /* configure PCS CLOCK RESET */
> - val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
> + val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET
> +
> + PCS_CLOCK_RESET);
> val &= ~CLK_DIVISION_RATIO_MASK;
> val |= 1 << CLK_DIVISION_RATIO_OFFS;
> - writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
> + writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET
> +
> + PCS_CLOCK_RESET);
>
> val &= ~CLK_DIV_PHASE_SET_MASK;
> val |= MAC_CLK_RESET_MASK;
> val |= RX_SD_CLK_RESET_MASK;
> val |= TX_SD_CLK_RESET_MASK;
> - writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
> + writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET
> +
> + PCS_CLOCK_RESET);
>
> return 0;
> }
> @@ -3300,22 +3276,6 @@ static int gop_xlg_mac_mode_cfg(struct mvpp2_port
> *port, int num_of_act_lanes)
> return 0;
> }
>
> -/* Set PCS to reset or exit from reset */
> -static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
> -{
> - u32 val;
> -
> - /* read - modify - write */
> - val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
> - if (reset)
> - val &= ~MVPP22_XPCS_PCSRESET;
> - else
> - val |= MVPP22_XPCS_PCSRESET;
> - writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
> -
> - return 0;
> -}
> -
> /* Set the MAC to reset or exit from reset */
> static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
> {
> @@ -3387,14 +3347,10 @@ static int gop_port_init(struct mvpp2_port *port)
> num_of_act_lanes = 2;
> mac_num = 0;
> /* configure PCS */
> - gop_xpcs_mode(port, num_of_act_lanes);
> gop_mpcs_mode(port);
> /* configure MAC */
> gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
>
> - /* pcs unreset */
> - gop_xpcs_reset(port, 0);
> -
> /* mac unreset */
> gop_xlg_mac_reset(port, 0);
> break;
> @@ -3465,6
Re: [PATCH 4/4] net: mvpp2: Remove PHY_INTERFACE_MODE_SGMII_2500
On Tue, Apr 27, 2021 at 12:49 PM Stefan Roese wrote:
>
> As was discussed on the list, PHY_INTERFACE_MODE_SGMII_2500 is used
> incorrectly in the Marvell mvpp2 network driver and the Marvell PHY
> code. This patch removes the references to this macro in the mvpp2
> network driver for now.
>
> The correct support shall be implemented at a later time.
>
> Signed-off-by: Stefan Roese
> Cc: Konstantin Porotchkin
> Cc: Stefan Chulski
> Cc: Nadav Haklai
> Cc: Marek Behun
> ---
> This patch is targeted on-top of the latest Marvell SERDES, mvpp2 and
> PHY patches to resolve the ongoing discussion of the incorrect usage of
> SGMII_2500 for now.
>
> drivers/net/mvpp2.c | 53 -
> 1 file changed, 53 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index 4c0a7b0a9f5c..b0287f561e2e 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -2873,7 +2873,6 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
>
> switch (port->phy_interface) {
> case PHY_INTERFACE_MODE_SGMII:
> - case PHY_INTERFACE_MODE_SGMII_2500:
> val |= MVPP2_GMAC_INBAND_AN_MASK;
> break;
> case PHY_INTERFACE_MODE_1000BASEX:
> @@ -2941,7 +2940,6 @@ static void mvpp2_port_loopback_set(struct mvpp2_port
> *port)
> val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
>
> if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
> - port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 ||
> port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
> port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
> val |= MVPP2_GMAC_PCS_LB_EN_MASK;
> @@ -3029,48 +3027,6 @@ static int gop_bypass_clk_cfg(struct mvpp2_port *port,
> int en)
> return 0;
> }
>
> -static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
> -{
> - u32 val, thresh;
> -
> - /*
> -* Configure minimal level of the Tx FIFO before the lower part
> -* starts to read a packet
> -*/
> - thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
> - val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
> - val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
> - val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
> - writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
> -
> - /* Disable bypass of sync module */
> - val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
> - val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
> - /* configure DP clock select according to mode */
> - val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
> - /* configure QSGMII bypass according to mode */
> - val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
> - writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
> -
> - val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
> - /*
> -* Configure GIG MAC to SGMII mode connected to a fiber
> -* transceiver
> -*/
> - val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
> - writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
> -
> - /* configure AN 0x9268 */
> - val = MVPP2_GMAC_EN_PCS_AN |
> - MVPP2_GMAC_AN_BYPASS_EN |
> - MVPP2_GMAC_CONFIG_MII_SPEED |
> - MVPP2_GMAC_CONFIG_GMII_SPEED |
> - MVPP2_GMAC_FC_ADV_EN|
> - MVPP2_GMAC_CONFIG_FULL_DUPLEX |
> - MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
> - writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
> -}
> -
> static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
> {
> u32 val, thresh;
> @@ -3241,9 +3197,6 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port)
> case PHY_INTERFACE_MODE_SGMII:
> gop_gmac_sgmii_cfg(port);
> break;
> - case PHY_INTERFACE_MODE_SGMII_2500:
> - gop_gmac_sgmii2_5_cfg(port);
> - break;
> case PHY_INTERFACE_MODE_1000BASEX:
> gop_gmac_1000basex_cfg(port);
> break;
> @@ -3424,7 +3377,6 @@ static int gop_port_init(struct mvpp2_port *port)
> break;
>
> case PHY_INTERFACE_MODE_SGMII:
> - case PHY_INTERFACE_MODE_SGMII_2500:
> case PHY_INTERFACE_MODE_1000BASEX:
> case PHY_INTERFACE_MODE_2500BASEX:
> /* configure PCS */
> @@ -3484,7 +3436,6 @@ static void gop_port_enable(struct mvpp2_port *port,
> int enable)
> case PHY_INTERFACE_MODE_RGMII:
> case PHY_INTERFACE_MODE_RGMII_ID:
> case PHY_INTERFACE_MODE_SGMII:
> - case PHY_INTERFACE_MODE_SGMII_2500:
> case PHY_INTERFACE_MODE_1000BASEX:
> case PHY_INTERFACE_MODE_2500BASEX:
> if (enable)
> @@ -3521,7 +3472,6 @@ static u32 mvpp2_netc_cfg_create(int gop_id,
> phy_interface_t phy_type)
>
> if (gop_id == 2) {
> if (phy_type == PHY_INTERFACE_MODE_SGMII ||
> - phy_type ==
Re: [PATCH 3/4] net: phy: marvell: Remove PHY_INTERFACE_MODE_SGMII_2500
On Tue, Apr 27, 2021 at 12:49 PM Stefan Roese wrote:
>
> As was discussed on the list, PHY_INTERFACE_MODE_SGMII_2500 is used
> incorrectly in the Marvell mvpp2 network driver and the Marvell PHY
> code. This patch removes the references to this macro in the Marvell
> PHY driver for now.
>
> The correct support shall be implemented at a later time.
>
> Signed-off-by: Stefan Roese
> Cc: Konstantin Porotchkin
> Cc: Stefan Chulski
> Cc: Nadav Haklai
> Cc: Marek Behun
> ---
> This patch is targeted on-top of the latest Marvell SERDES, mvpp2 and
> PHY patches to resolve the ongoing discussion of the incorrect usage of
> SGMII_2500 for now.
>
> drivers/net/phy/marvell.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
> index 3bcb0033b391..8850b604ef47 100644
> --- a/drivers/net/phy/marvell.c
> +++ b/drivers/net/phy/marvell.c
> @@ -634,8 +634,7 @@ static int m88e2110_config(struct phy_device *phydev)
> /* Disabled 10G advertisement */
> phy_write(phydev, 7, 0x20, 0x1e1);
> } else {
> - if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500 ||
> - phydev->interface == PHY_INTERFACE_MODE_2500BASEX) {
> + if (phydev->interface == PHY_INTERFACE_MODE_2500BASEX) {
> /* Disabled 10G/5G advertisements */
> phy_write(phydev, 7, 0x20, 0xa1);
> } else {
> --
> 2.31.1
>
Reviewed-by: Ramon Fried
Re: [PATCH v2 6/6] net: dwc: add a common empty ops eqos_null_ops
On Mon, Apr 26, 2021 at 6:47 PM Patrick Delaunay
wrote:
>
> Add a common empty ops: eqos_null_ops() to remove the duplicated empty
> functions and reduce the driver size for stm32 and imx config.
>
> This patch also aligns the prototype of ops 'eqos_stop_clks' with other
> eqos ops by adding return value.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v2:
> - cleanup ops by adding a common null ops (NEW)
>
> drivers/net/dwc_eth_qos.c | 97 +--
> 1 file changed, 22 insertions(+), 75 deletions(-)
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index 3fb8bfaf3a..4d1e5d6f8f 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -285,7 +285,7 @@ struct eqos_ops {
> int (*eqos_remove_resources)(struct udevice *dev);
> int (*eqos_stop_resets)(struct udevice *dev);
> int (*eqos_start_resets)(struct udevice *dev);
> - void (*eqos_stop_clks)(struct udevice *dev);
> + int (*eqos_stop_clks)(struct udevice *dev);
> int (*eqos_start_clks)(struct udevice *dev);
> int (*eqos_calibrate_pads)(struct udevice *dev);
> int (*eqos_disable_calibration)(struct udevice *dev);
> @@ -615,12 +615,7 @@ err:
> #endif
> }
>
> -static int eqos_start_clks_imx(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> -static void eqos_stop_clks_tegra186(struct udevice *dev)
> +static int eqos_stop_clks_tegra186(struct udevice *dev)
> {
> #ifdef CONFIG_CLK
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -635,9 +630,10 @@ static void eqos_stop_clks_tegra186(struct udevice *dev)
> #endif
>
> debug("%s: OK\n", __func__);
> + return 0;
> }
>
> -static void eqos_stop_clks_stm32(struct udevice *dev)
> +static int eqos_stop_clks_stm32(struct udevice *dev)
> {
> #ifdef CONFIG_CLK
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -652,11 +648,7 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
> #endif
>
> debug("%s: OK\n", __func__);
> -}
> -
> -static void eqos_stop_clks_imx(struct udevice *dev)
> -{
> - /* empty */
> + return 0;
> }
>
> static int eqos_start_resets_tegra186(struct udevice *dev)
> @@ -698,16 +690,6 @@ static int eqos_start_resets_tegra186(struct udevice
> *dev)
> return 0;
> }
>
> -static int eqos_start_resets_stm32(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> -static int eqos_start_resets_imx(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> static int eqos_stop_resets_tegra186(struct udevice *dev)
> {
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -718,16 +700,6 @@ static int eqos_stop_resets_tegra186(struct udevice *dev)
> return 0;
> }
>
> -static int eqos_stop_resets_stm32(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> -static int eqos_stop_resets_imx(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> static int eqos_calibrate_pads_tegra186(struct udevice *dev)
> {
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -816,26 +788,6 @@ static ulong eqos_get_tick_clk_rate_imx(struct udevice
> *dev)
> return imx_get_eqos_csr_clk();
> }
>
> -static int eqos_calibrate_pads_stm32(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> -static int eqos_calibrate_pads_imx(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> -static int eqos_disable_calibration_stm32(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> -static int eqos_disable_calibration_imx(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> static int eqos_set_full_duplex(struct udevice *dev)
> {
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -932,11 +884,6 @@ static int eqos_set_tx_clk_speed_tegra186(struct udevice
> *dev)
> return 0;
> }
>
> -static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
> {
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -1894,11 +1841,6 @@ static int eqos_remove_resources_stm32(struct udevice
> *dev)
> return 0;
> }
>
> -static int eqos_remove_resources_imx(struct udevice *dev)
> -{
> - return 0;
> -}
> -
> static int eqos_probe(struct udevice *dev)
> {
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -1987,6 +1929,11 @@ static int eqos_remove(struct udevice *dev)
> return 0;
> }
>
> +static int eqos_null_ops(struct udevice *dev)
> +{
> + return 0;
> +}
> +
> static const struct eth_ops eqos_ops = {
> .start = eqos_start,
> .stop = eqos_stop,
> @@ -2032,13 +1979,13 @@ static struct eqos_ops eqos_stm32_ops = {
> .eqos_flush_buffer = eqos_flush_buffer_generic,
> .eqos_probe_resources = eqos_probe_resources_stm32,
> .eqos_remove_resources = eqos_remove_resources_stm32,
> - .eqos_stop_resets = eqos_stop_resets_stm32,
> - .eqos_start_resets = eqos_start_resets_stm32,
> +
Re: [PATCH v2 5/6] net: dwc_eth_qos: use generic ethernet phy for stm32 variant
On Mon, Apr 26, 2021 at 6:47 PM Patrick Delaunay
wrote:
>
> Use the generic ethernet phy which already manages the correct binding
> for gpio reset, including the assert an deassert delays.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v2:
> - use generic ethernet phy for stm32 variant, this patch is a REWORK of
> previous serie: the device parsing is done in eth-phy driver and the gpio
> support is removed in stm32 variant: eqos_start/stop_resets_stm32 and
> eqos_probe_resources_stm32.
>
> drivers/net/Kconfig | 1 +
> drivers/net/dwc_eth_qos.c | 50 ---
> 2 files changed, 1 insertion(+), 50 deletions(-)
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 382639044b..adf43fb42a 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -206,6 +206,7 @@ config DWC_ETH_QOS_IMX
> config DWC_ETH_QOS_STM32
> bool "Synopsys DWC Ethernet QOS device support for STM32"
> depends on DWC_ETH_QOS
> + select DM_ETH_PHY
> default y if ARCH_STM32MP
> help
> The Synopsys Designware Ethernet QOS IP block with the specific
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index e625aea8d1..3fb8bfaf3a 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -700,29 +700,6 @@ static int eqos_start_resets_tegra186(struct udevice
> *dev)
>
> static int eqos_start_resets_stm32(struct udevice *dev)
> {
> - struct eqos_priv *eqos = dev_get_priv(dev);
> - int ret;
> -
> - debug("%s(dev=%p):\n", __func__, dev);
> - if (dm_gpio_is_valid(>phy_reset_gpio)) {
> - ret = dm_gpio_set_value(>phy_reset_gpio, 1);
> - if (ret < 0) {
> - pr_err("dm_gpio_set_value(phy_reset, assert) failed:
> %d",
> - ret);
> - return ret;
> - }
> -
> - udelay(2);
> -
> - ret = dm_gpio_set_value(>phy_reset_gpio, 0);
> - if (ret < 0) {
> - pr_err("dm_gpio_set_value(phy_reset, deassert)
> failed: %d",
> - ret);
> - return ret;
> - }
> - }
> - debug("%s: OK\n", __func__);
> -
> return 0;
> }
>
> @@ -743,18 +720,6 @@ static int eqos_stop_resets_tegra186(struct udevice *dev)
>
> static int eqos_stop_resets_stm32(struct udevice *dev)
> {
> - struct eqos_priv *eqos = dev_get_priv(dev);
> - int ret;
> -
> - if (dm_gpio_is_valid(>phy_reset_gpio)) {
> - ret = dm_gpio_set_value(>phy_reset_gpio, 1);
> - if (ret < 0) {
> - pr_err("dm_gpio_set_value(phy_reset, assert) failed:
> %d",
> - ret);
> - return ret;
> - }
> - }
> -
> return 0;
> }
>
> @@ -1785,7 +1750,6 @@ static int eqos_probe_resources_stm32(struct udevice
> *dev)
> struct eqos_priv *eqos = dev_get_priv(dev);
> int ret;
> phy_interface_t interface;
> - struct ofnode_phandle_args phandle_args;
>
> debug("%s(dev=%p):\n", __func__, dev);
>
> @@ -1825,20 +1789,6 @@ static int eqos_probe_resources_stm32(struct udevice
> *dev)
> if (ret)
> pr_warn("No phy clock provided %d", ret);
>
> - ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> -_args);
> - if (!ret) {
> - /* search "reset-gpios" in phy node */
> - ret = gpio_request_by_name_nodev(phandle_args.node,
> -"reset-gpios", 0,
> ->phy_reset_gpio,
> -GPIOD_IS_OUT |
> -GPIOD_IS_OUT_ACTIVE);
> - if (ret)
> - pr_warn("gpio_request_by_name(phy reset) not provided
> %d",
> - ret);
> - }
> -
> debug("%s: OK\n", __func__);
> return 0;
>
> --
> 2.17.1
>
Reviewed-by: Ramon Fried
Re: [PATCH v2 4/6] net: dwc_eth_qos: remove the field phyaddr of the struct eqos_priv
On Mon, Apr 26, 2021 at 6:47 PM Patrick Delaunay
wrote:
>
> Since the commit commit 6a895d039ba7 ("net: Update eQos driver and FEC
> driver to use eth phy interfaces") the field phyaddr of driver private data
> struct eqos_priv is no more used in eqos_start() for the phy_connect()
> parameter.
>
> Now this variable is only initialized in eqos_probe_resources_stm32()
> it can be removed.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v2:
> - remove unused element in the struct eqos_priv (NEW)
>
> drivers/net/dwc_eth_qos.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index e8242ca4e1..e625aea8d1 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -311,7 +311,6 @@ struct eqos_priv {
> struct clk clk_slave_bus;
> struct mii_dev *mii;
> struct phy_device *phy;
> - int phyaddr;
> u32 max_speed;
> void *descs;
> int tx_desc_idx, rx_desc_idx;
> @@ -1826,7 +1825,6 @@ static int eqos_probe_resources_stm32(struct udevice
> *dev)
> if (ret)
> pr_warn("No phy clock provided %d", ret);
>
> - eqos->phyaddr = -1;
> ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> _args);
> if (!ret) {
> @@ -1839,9 +1837,6 @@ static int eqos_probe_resources_stm32(struct udevice
> *dev)
> if (ret)
> pr_warn("gpio_request_by_name(phy reset) not provided
> %d",
> ret);
> -
> - eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
> - "reg", -1);
> }
>
> debug("%s: OK\n", __func__);
> --
> 2.17.1
>
Reviewed-by: Ramon Fried
Re: [PATCH v2 3/6] net: eth-phy: manage subnode mdio0
On Mon, Apr 26, 2021 at 6:47 PM Patrick Delaunay
wrote:
>
> Bind any subnode with name beginning by mdio, mdio0 for example,
> and not only the "mdio" as namei of subnode.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v2:
> - update eth-phy driver to support STM32 binding with a mdio0 subnode (NEW)
>
> drivers/net/eth-phy-uclass.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c
> index 962084a7c9..f04f1c8f09 100644
> --- a/drivers/net/eth-phy-uclass.c
> +++ b/drivers/net/eth-phy-uclass.c
> @@ -27,12 +27,18 @@ int eth_phy_binds_nodes(struct udevice *eth_dev)
> const char *node_name;
> int ret;
>
> - mdio_node = dev_read_subnode(eth_dev, "mdio");
> + /* search a subnode named "mdio.*" */
> + dev_for_each_subnode(mdio_node, eth_dev) {
> + node_name = ofnode_get_name(mdio_node);
> + if (!strncmp(node_name, "mdio", 4))
> + break;
> + }
> if (!ofnode_valid(mdio_node)) {
> - dev_dbg(eth_dev, "%s: %s mdio subnode not found!", __func__,
> + dev_dbg(eth_dev, "%s: %s mdio subnode not found!\n", __func__,
> eth_dev->name);
> return -ENXIO;
> }
> + dev_dbg(eth_dev, "%s: %s subnode found!\n", __func__, node_name);
>
> ofnode_for_each_subnode(phy_node, mdio_node) {
> node_name = ofnode_get_name(phy_node);
> --
> 2.17.1
>
Reviewed-by: Ramon Fried
Re: [PATCH v2 2/6] net: eth-phy: use dev_dbg and log_notice
On Mon, Apr 26, 2021 at 6:47 PM Patrick Delaunay
wrote:
>
> Replace debug trace and printf to log macros:
> - debug() replaced by dev_dbg() when device is available, this macro
> indicate the device name since commit ceb70bb870ac ("dm: Print device
> name in dev_xxx like Linux")
> - printf() replaced by log_notice() to allow dispatch to log backends.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v2:
> - use log macro in eth-phy driver (NEW)
>
> drivers/net/eth-phy-uclass.c | 20 +++-
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c
> index 153f6909eb..962084a7c9 100644
> --- a/drivers/net/eth-phy-uclass.c
> +++ b/drivers/net/eth-phy-uclass.c
> @@ -5,8 +5,10 @@
>
> #include
> #include
> +#include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -27,25 +29,25 @@ int eth_phy_binds_nodes(struct udevice *eth_dev)
>
> mdio_node = dev_read_subnode(eth_dev, "mdio");
> if (!ofnode_valid(mdio_node)) {
> - debug("%s: %s mdio subnode not found!", __func__,
> - eth_dev->name);
> + dev_dbg(eth_dev, "%s: %s mdio subnode not found!", __func__,
> + eth_dev->name);
> return -ENXIO;
> }
>
> ofnode_for_each_subnode(phy_node, mdio_node) {
> node_name = ofnode_get_name(phy_node);
>
> - debug("* Found child node: '%s'\n", node_name);
> + dev_dbg(eth_dev, "* Found child node: '%s'\n", node_name);
>
> ret = device_bind_driver_to_node(eth_dev,
> "eth_phy_generic_drv",
> node_name, phy_node, NULL);
> if (ret) {
> - debug(" - Eth phy binding error: %d\n", ret);
> + dev_dbg(eth_dev, " - Eth phy binding error: %d\n",
> ret);
> continue;
> }
>
> - debug(" - bound phy device: '%s'\n", node_name);
> + dev_dbg(eth_dev, " - bound phy device: '%s'\n", node_name);
> }
>
> return 0;
> @@ -86,14 +88,14 @@ struct mii_dev *eth_phy_get_mdio_bus(struct udevice
> *eth_dev)
> */
> uc_priv = (struct eth_phy_device_priv
> *)(dev_get_uclass_priv(phy_dev));
> if (uc_priv->mdio_bus)
> - printf("Get shared mii bus on %s\n",
> eth_dev->name);
> + log_notice("Get shared mii bus on %s\n",
> eth_dev->name);
> else
> - printf("Can't get shared mii bus on %s\n",
> eth_dev->name);
> + log_notice("Can't get shared mii bus on
> %s\n", eth_dev->name);
>
> return uc_priv->mdio_bus;
> }
> } else {
> - printf("FEC: can't find phy-handle\n");
> + log_notice("FEC: can't find phy-handle\n");
> }
>
> return NULL;
> @@ -106,7 +108,7 @@ int eth_phy_get_addr(struct udevice *dev)
>
> if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
>_args)) {
> - debug("Failed to find phy-handle");
> + dev_dbg(dev, "Failed to find phy-handle");
> return -ENODEV;
> }
>
> --
> 2.17.1
>
Reviewed-by: Ramon Fried
Re: [PATCH v2 1/6] net: eth-phy: add support of device tree configuration for gpio reset
On Mon, Apr 26, 2021 at 6:47 PM Patrick Delaunay
wrote:
>
> The gpio reset and the assert or deassert delay are defined in generic
> binding of the ethernet phy in Linux:
> Documentation/devicetree/bindings/net/ethernet-phy.yaml
>
> reset-gpios:
> maxItems: 1
> description:
> The GPIO phandle and specifier for the PHY reset signal.
>
> reset-assert-us:
> description:
> Delay after the reset was asserted in microseconds. If this
> property is missing the delay will be skipped.
>
> reset-deassert-us:
> description:
> Delay after the reset was deasserted in microseconds. If
> this property is missing the delay will be skipped.
>
> See also U-Boot: doc/device-tree-bindings/net/phy.txt
>
> This patch adds the parsing of this common DT properties in the
> u-class "eth_phy_generic", used by default in the associated driver
> "eth_phy_generic_drv"
>
> This parsing function eth_phy_of_to_plat can be reused by other
> ethernet phy drivers for this uclass UCLASS_ETH_PHY.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> Changes in v2:
> - Update eth-phy driver (NEW)
>
> drivers/net/eth-phy-uclass.c | 50
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c
> index 07aebd935e..153f6909eb 100644
> --- a/drivers/net/eth-phy-uclass.c
> +++ b/drivers/net/eth-phy-uclass.c
> @@ -6,12 +6,17 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> +#include
>
> struct eth_phy_device_priv {
> struct mii_dev *mdio_bus;
> + struct gpio_desc reset_gpio;
> + u32 reset_assert_delay;
> + u32 reset_deassert_delay;
> };
>
> int eth_phy_binds_nodes(struct udevice *eth_dev)
> @@ -110,13 +115,58 @@ int eth_phy_get_addr(struct udevice *dev)
> return reg;
> }
>
> +/* parsing generic properties of devicetree/bindings/net/ethernet-phy.yaml */
> +static int eth_phy_of_to_plat(struct udevice *dev)
> +{
> + struct eth_phy_device_priv *uc_priv = dev_get_uclass_priv(dev);
> + int ret;
> +
> + /* search "reset-gpios" in phy node */
> + ret = gpio_request_by_name(dev, "reset-gpios", 0,
> + _priv->reset_gpio,
> + GPIOD_IS_OUT);
> + if (ret != -ENOENT)
> + return ret;
> +
> + uc_priv->reset_assert_delay = dev_read_u32_default(dev,
> "reset-assert-us", 0);
> + uc_priv->reset_deassert_delay = dev_read_u32_default(dev,
> "reset-deassert-us", 0);
> +
> + return 0;
> +}
> +
> +void eth_phy_reset(struct udevice *dev, int value)
> +{
> + struct eth_phy_device_priv *uc_priv = dev_get_uclass_priv(dev);
> + u32 delay;
> +
> + if (!dm_gpio_is_valid(_priv->reset_gpio))
> + return;
> +
> + dm_gpio_set_value(_priv->reset_gpio, value);
> +
> + delay = value ? uc_priv->reset_assert_delay :
> uc_priv->reset_deassert_delay;
> + if (delay)
> + udelay(delay);
> +}
> +
> +static int eth_phy_pre_probe(struct udevice *dev)
> +{
> + /* Assert and deassert the reset signal */
> + eth_phy_reset(dev, 1);
> + eth_phy_reset(dev, 0);
> +
> + return 0;
> +}
> +
> UCLASS_DRIVER(eth_phy_generic) = {
> .id = UCLASS_ETH_PHY,
> .name = "eth_phy_generic",
> .per_device_auto= sizeof(struct eth_phy_device_priv),
> + .pre_probe = eth_phy_pre_probe,
> };
>
> U_BOOT_DRIVER(eth_phy_generic_drv) = {
> .name = "eth_phy_generic_drv",
> .id = UCLASS_ETH_PHY,
> + .of_to_plat = eth_phy_of_to_plat,
> };
> --
> 2.17.1
>
Reviewed-by: Ramon Fried
Re: [PATCH 2/3] net: dwc_eth_qos: define LOG_CATEGORY
On Mon, Apr 26, 2021 at 6:25 PM Patrick Delaunay wrote: > > Define LOG_CATEGORY to allow filtering with log command. > > Signed-off-by: Patrick Delaunay > --- > > drivers/net/dwc_eth_qos.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c > index e8242ca4e1..e423c31753 100644 > --- a/drivers/net/dwc_eth_qos.c > +++ b/drivers/net/dwc_eth_qos.c > @@ -27,6 +27,8 @@ > *all clock and reset signals to the HW block. > */ > > +#define LOG_CATEGORY UCLASS_ETH > + > #include > #include > #include > -- > 2.17.1 > Reviewed-by: Ramon Fried
Re: [PATCH 3/3] net: define LOG_CATEGORY
On Mon, Apr 26, 2021 at 6:25 PM Patrick Delaunay wrote: > > Define LOG_CATEGORY to allow filtering with log command. > > Signed-off-by: Patrick Delaunay > --- > > net/eth-uclass.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/net/eth-uclass.c b/net/eth-uclass.c > index 34ca731d1e..63ad0908d9 100644 > --- a/net/eth-uclass.c > +++ b/net/eth-uclass.c > @@ -5,6 +5,8 @@ > * Joe Hershberger, National Instruments > */ > > +#define LOG_CATEGORY UCLASS_ETH > + > #include > #include > #include > -- > 2.17.1 > Reviewed-by: Ramon Fried
Re: [PATCH 1/3] net: eth-phy: define LOG_CATEGORY
On Mon, Apr 26, 2021 at 6:25 PM Patrick Delaunay wrote: > > Define LOG_CATEGORY to allow filtering with log command. > > Signed-off-by: Patrick Delaunay > --- > > drivers/net/eth-phy-uclass.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c > index 07aebd935e..abb658bf21 100644 > --- a/drivers/net/eth-phy-uclass.c > +++ b/drivers/net/eth-phy-uclass.c > @@ -3,6 +3,8 @@ > * Copyright 2020 NXP > */ > > +#define LOG_CATEGORY UCLASS_ETH_PHY > + > #include > #include > #include > -- > 2.17.1 > Reviewed-by: Ramon Fried
Re: [PATCH] net: use a more deterministic approach to get the active ethernet device
On Wed, Feb 24, 2021 at 6:30 PM Michael Walle wrote:
>
> If the environment variable "ethact" is not set, the first device in the
> uclass is returned. This depends on the probing order of the ethernet
> devices. Moreover it is not not configurable at all.
>
> Try to return the ethernet device with sequence id 0 first which then
> can be configured by the aliases in a device tree. Fall back to the old
> mechanism in case of an error.
>
> Signed-off-by: Michael Walle
> ---
> net/eth-uclass.c | 17 -
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/net/eth-uclass.c b/net/eth-uclass.c
> index 34ca731d1e..0b4260dc5b 100644
> --- a/net/eth-uclass.c
> +++ b/net/eth-uclass.c
> @@ -69,8 +69,11 @@ void eth_set_current_to_next(void)
> /*
> * Typically this will simply return the active device.
> * In the case where the most recent active device was unset, this will
> attempt
> - * to return the first device. If that device doesn't exist or fails to
> probe,
> - * this function will return NULL.
> + * to return the device with sequence id 0 (which can be configured by the
> + * device tree). If this fails, fall back to just getting the first device.
> + * The latter is non-deterministic and depends on the order of the probing.
> + * If that device doesn't exist or fails to probe, this function will return
> + * NULL.
> */
> struct udevice *eth_get_dev(void)
> {
> @@ -80,9 +83,13 @@ struct udevice *eth_get_dev(void)
> if (!uc_priv)
> return NULL;
>
> - if (!uc_priv->current)
> - eth_errno = uclass_first_device(UCLASS_ETH,
> - _priv->current);
> + if (!uc_priv->current) {
> + eth_errno = uclass_get_device_by_seq(UCLASS_ETH, 0,
> +_priv->current);
> + if (eth_errno)
> + eth_errno = uclass_first_device(UCLASS_ETH,
> + _priv->current);
> + }
> return uc_priv->current;
> }
>
> --
> 2.20.1
>
Reviewed-by: Ramon Fried
Re: [PATCH] efi_loader: check query_variable_info attributes
On 4/29/21 7:46 PM, Vincent Stehlé wrote:
QueryVariableInfo() must return EFI_INVALID_PARAMETER when an invalid
combination of attribute bits is supplied.
This fixes three SCT QueryVariableInfo_Conf failures.
Signed-off-by: Vincent Stehlé
Reviewed-by: Grant Likely
Cc: Heinrich Schuchardt
Cc: Alexander Graf
Changes since v1:
- Remove if/else and return directly
---
lib/efi_loader/efi_var_common.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c
index b11ed91a74a..cbf8685fad5 100644
--- a/lib/efi_loader/efi_var_common.c
+++ b/lib/efi_loader/efi_var_common.c
@@ -160,6 +160,10 @@ efi_status_t EFIAPI efi_query_variable_info(
EFI_ENTRY("%x %p %p %p", attributes, maximum_variable_storage_size,
remaining_variable_storage_size, maximum_variable_size);
+ if (!attributes || ((attributes & EFI_VARIABLE_RUNTIME_ACCESS) &&
+ !(attributes & EFI_VARIABLE_BOOTSERVICE_ACCESS)))
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
Thank you for looking into closing this UEFI compliance gap.
The checks must be executed at runtime too. efi_query_variable_info()
only covers boot time.
StandaloneMM has its own check in RuntimeServiceQueryVariableInfo().
That function only checks that attributes is non-zero. If you consider
that check wrong, you would have to fix it there.
Your U-Boot side checks should be put into efi_query_variable_info_int().
Why should we consider the following values valid?
attributes == EFI_VARIABLE_APPEND_WRITE
attributes == EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS
attributes == EFI_VARIABLE_HARDWARE_ERROR_RECORD
attributes == 0xff00
EFI_VARIABLE_APPEND_WRITE shall be ignored according to chapter 8.2
"Variable Services". Shouldn't we remove the bit before checking the
remaining value?
EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS for a variable that is neither
BS nor RT makes little sense.
According to chapter 8.2.4.2, "Hardware Error Record Variables" a
hardware error variable must be NV, BS, RT, HR.
0xff00 has bits set that can never appear in attributes.
efi_set_variable_int() would also accept some invalid combinations of
flags. You could try to extract a common function for checking.
Best regards
Heinrich
+
ret = efi_query_variable_info_int(attributes,
maximum_variable_storage_size,
remaining_variable_storage_size,
Re: [GIT PULL] xilinx patches for v2021.07-rc2
On Thu, Apr 29, 2021 at 03:59:06PM +0200, Michal Simek wrote: > Hi Tom, > > please pull these changes to your tree. I can't see any issue from > gitlab CI and also buildman doesn't show any problem. > Key part of this series is to fix issue with gmii2rgmii bridge which > ends up in a while loop on every ZynqMP board. > And then usb dfu fixes with also enabling dfu functionality with efi > capsule update. Also enabling saving variables based on actual bootmode. > There needs to be some additional work to better locate where variables > should be saved but it will require some time to do it properly. > > Thanks, > Michal > > The following changes since commit 275a4490fd2f30df76f2aa07efa0f595fef4d46f: > > Merge branch '2021-04-22-udoo_neo-update' (2021-04-22 11:29:32 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-microblaze.git > tags/xilinx-for-v2021.07-rc2 > > for you to fetch changes up to b00bad9dc81ee0337761cc50443dffa22a6cdedf: > > spi: zynqmp: Remove gd reference (2021-04-29 14:48:31 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH] efi_loader: check query_variable_info attributes
QueryVariableInfo() must return EFI_INVALID_PARAMETER when an invalid
combination of attribute bits is supplied.
This fixes three SCT QueryVariableInfo_Conf failures.
Signed-off-by: Vincent Stehlé
Reviewed-by: Grant Likely
Cc: Heinrich Schuchardt
Cc: Alexander Graf
Changes since v1:
- Remove if/else and return directly
---
lib/efi_loader/efi_var_common.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c
index b11ed91a74a..cbf8685fad5 100644
--- a/lib/efi_loader/efi_var_common.c
+++ b/lib/efi_loader/efi_var_common.c
@@ -160,6 +160,10 @@ efi_status_t EFIAPI efi_query_variable_info(
EFI_ENTRY("%x %p %p %p", attributes, maximum_variable_storage_size,
remaining_variable_storage_size, maximum_variable_size);
+ if (!attributes || ((attributes & EFI_VARIABLE_RUNTIME_ACCESS) &&
+ !(attributes & EFI_VARIABLE_BOOTSERVICE_ACCESS)))
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
ret = efi_query_variable_info_int(attributes,
maximum_variable_storage_size,
remaining_variable_storage_size,
--
2.30.2
Re: Kirkwood: Fix tv sec/usec normalization in kwboot
>From c200095d4136a071dd9526a48be642ce58fae8c9 Mon Sep 17 00:00:00 2001
From: Dagan Martinez
Date: Tue, 27 Apr 2021 15:48:31 -0400
Subject: [PATCH v2] Kirkwood: Fix tv sec/usec normalization in kwboot
`kwboot.c` had an issue where it failed to normalize the `tv` struct in
the case where the `tv_usec` field was 100, ie one second.
This caused issues on Fedora Linux 34, where `select` would return
`EINVAL`, preventing kwboot from communicating with the board.
Signed-off-by: Dagan Martinez
---
Changes for v2:
- Use real author name in patch
tools/kwboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/kwboot.c b/tools/kwboot.c
index 4be094c9c8..5d5d501d36 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -167,7 +167,7 @@ kwboot_tty_recv(int fd, void *buf, size_t len, int timeo)
tv.tv_sec = 0;
tv.tv_usec = timeo * 1000;
-if (tv.tv_usec > 100) {
+if (tv.tv_usec >= 100) {
tv.tv_sec += tv.tv_usec / 100;
tv.tv_usec %= 100;
}
--
2.31.1
[Patch v2 2/2] board: Add Zynq Mxic picozed development board support
Add the Zynq Mxic picozed development board support.
Signed-off-by: Zhengxun Li
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/zynq-mxic-picozed.dts | 72 ++
2 files changed, 74 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1dd6c4b..b5addc4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -287,7 +287,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zturn.dtb \
zynq-zturn-v5.dtb \
zynq-zybo.dtb \
- zynq-zybo-z7.dtb
+ zynq-zybo-z7.dtb \
+ zynq-mxic-picozed.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb\
diff --git a/arch/arm/dts/zynq-mxic-picozed.dts
b/arch/arm/dts/zynq-mxic-picozed.dts
new file mode 100644
index 000..1f24ca1
--- /dev/null
+++ b/arch/arm/dts/zynq-mxic-picozed.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Macronix Inc.
+ *
+ * Author: Zhengxun Li
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq MXIC PicoZed Development Board";
+ compatible = "mxicy,zynq-mxic-picozed", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ spi0 = _controller;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x3000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ clkwizard: clkwizard@43c2 {
+ compatible = "xlnx,clk-wizard-5.1";
+ reg = <0x43c2 0x1>;
+ clocks = < 18>, < 18>;
+ clock-names = "aclk", "clk_in1";
+ #clock-cells = <1>;
+ clock-frequency = <13330>;
+ };
+
+ spi_controller: spi@43c3 {
+ compatible = "mxicy,mx25f0a-spi";
+ reg = <0x43c3 0x1>;
+ reg-names = "regs";
+ clocks = < 0>, < 1>, < 18>;
+ clock-names = "send_clk", "send_dly_clk", "ps_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <2500>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+ };
+};
+
+ {
+ ps-clk-frequency = <>;
+};
+
+ {
+ status = "okay";
+ phy-mode = "rgmii-id";
+};
+
+ {
+ status = "okay";
+};
--
1.9.1
[Patch v2 1/2] clk: zynq: Add clock wizard driver
The Clocking Wizard IP supports clock circuits customized
to your clocking requirements. The wizard support for
dynamically reconfiguring the clocking primitives for
Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
Limited by uboot clk uclass without set_phase API, this
patch only provides set_rate to modify the frequency.
Signed-off-by: Zhengxun Li
---
drivers/clk/Kconfig | 9 +++
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 152
3 files changed, 162 insertions(+)
create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4aeaa0c..f0d4fe0 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -136,6 +136,15 @@ config CLK_ZYNQMP
This clock driver adds support for clock realted settings for
ZynqMP platform.
+config COMMON_CLK_XLNX_CLKWZRD
+ bool "Xilinx Clocking Wizard"
+ depends on CLK
+ help
+ Support for the Xilinx Clocking Wizard IP core clock generator.
+ Adds support for clocking wizard and compatible.
+ This driver supports the Xilinx clocking wizard programmable clock
+ synthesizer.
+
config CLK_STM32MP1
bool "Enable RCC clock driver for STM32MP1"
depends on ARCH_STM32MP && CLK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 645709b..f4ddbe8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
+obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock-wizard.c
new file mode 100644
index 000..55adb16
--- /dev/null
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx 'Clocking Wizard' driver
+ *
+ * Copyright (c) 2021 Macronix Inc.
+ *
+ * Author: Zhengxun Li
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define SRR0x0
+
+#define SR 0x4
+#define SR_LOCKED BIT(0)
+
+#define CCR(x) (0x200 + ((x) * 4))
+
+#define FBOUT_CFG CCR(0)
+#define FBOUT_DIV(x) (x)
+#define FBOUT_GET_DIV(x) ((x) & GENMASK(7, 0))
+#define FBOUT_MUL(x) ((x) << 8)
+#define FBOUT_GET_MUL(x) (((x) & GENMASK(15, 8)) >> 8)
+#define FBOUT_FRAC(x) ((x) << 16)
+#define FBOUT_GET_FRAC(x) (((x) & GENMASK(25, 16)) >> 16)
+#define FBOUT_FRAC_EN BIT(26)
+
+#define FBOUT_PHASECCR(1)
+
+#define OUT_CFG(x) CCR(2 + ((x) * 3))
+#define OUT_DIV(x) (x)
+#define OUT_GET_DIV(x) ((x) & GENMASK(7, 0))
+#define OUT_FRAC(x)((x) << 8)
+#define OUT_GET_FRAC(x)(((x) & GENMASK(17, 8)) >> 8)
+#define OUT_FRAC_ENBIT(18)
+
+#define OUT_PHASE(x) CCR(3 + ((x) * 3))
+#define OUT_DUTY(x)CCR(4 + ((x) * 3))
+
+#define CTRL CCR(23)
+#define CTRL_SEN BIT(2)
+#define CTRL_SADDR BIT(1)
+#define CTRL_LOAD BIT(0)
+
+/*
+ * struct clkwzrd - Clock wizard private data structure
+ *
+ * @lock Lock pointer
+ * @base Memory base
+ * @vco_clkvoltage-controlled oscillator frequency
+ */
+struct clkwzd {
+ void __iomem *base;
+ u64 vco_clk;
+};
+
+static int clk_wzrd_enable(struct clk *clk)
+{
+ struct clkwzd *priv = dev_get_priv(clk->dev);
+ int ret;
+ u32 val;
+
+ ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED,
+ 1, 100);
+ if (!ret) {
+ writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL);
+ writel(CTRL_SADDR, priv->base + CTRL);
+ ret = readl_poll_sleep_timeout(priv->base + SR, val,
+ val & SR_LOCKED, 1, 100);
+ }
+
+ return ret;
+}
+
+static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)
+{
+ struct clkwzd *priv = dev_get_priv(clk->dev);
+ u64 div;
+ u32 cfg;
+
+ /* Get output clock divide value */
+ div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate);
+ if (div < 1000 || div > 255999)
+ return -EINVAL;
+
+ cfg = OUT_DIV((u32)div / 1000);
+
+ writel(cfg, priv->base + OUT_CFG(clk->id));
+
+ return 0;
+}
+
+static int clk_wzrd_of_to_plat(struct udevice *dev)
+{
+ struct clkwzd *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ u64 clk_in1, vco_clk;
+ u32 cfg;
+
+ addr =
[Patch v2 0/2] Add Xilinx clock wizard driver support
This series add support to enable clock wizard for zynq platform. Changes in v2: - naming is aligned with linux - delete inappropriate description and code Zhengxun Li (2): clk: zynq: Add clock wizard driver board: Add Zynq Mxic picozed development board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/zynq-mxic-picozed.dts | 72 + drivers/clk/Kconfig | 9 +++ drivers/clk/Makefile| 1 + drivers/clk/clk-xlnx-clock-wizard.c | 152 5 files changed, 236 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c -- 1.9.1
Re: [PATCH 1/5] clk: ti: add custom API for memory access
On 28/04/2021 20:31, Dario Binacchi wrote:
Hi Tero,
Il 27/04/2021 09:01 Tero Kristo ha scritto:
Hi Dario,
One question below.
On 25/04/2021 17:17, Dario Binacchi wrote:
As pointed by [1] and [2], commit
d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong:
- It makes every 'reg' DT property translatable. It changes the address
translation so that for an I2C 'reg' address you'll get back as reg
the I2C controller address + reg value.
- The quirk must be fixed with platform code.
The clk_ti_get_reg_addr() is the platform code able to make the correct
address translation for the AM33xx clocks registers. Its implementation
was inspired by the Linux Kernel code.
[1]
https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng...@gmail.com/
[2]
https://lore.kernel.org/linux-clk/20210402192054.7934-1-dario...@libero.it/T/
Signed-off-by: Dario Binacchi
---
drivers/clk/ti/clk.c | 92
drivers/clk/ti/clk.h | 13 +++
2 files changed, 105 insertions(+)
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index c999df213a..68abe053cb 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -6,10 +6,23 @@
*/
#include
+#include
#include
+#include
#include
+#include
#include "clk.h"
+#define CLK_MAX_MEMMAPS 10
+
+struct clk_iomap {
+ struct regmap *regmap;
+ ofnode node;
+};
+
+static unsigned int clk_memmaps_num;
+static struct clk_iomap clk_memmaps[CLK_MAX_MEMMAPS];
+
static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg)
{
u32 v;
@@ -33,3 +46,82 @@ void clk_ti_latch(fdt_addr_t reg, s8 shift)
clk_ti_rmw(0, latch, reg);
readl(reg); /* OCP barrier */
}
+
+void clk_ti_writel(u32 val, struct clk_ti_reg *reg)
+{
+ struct clk_iomap *io = _memmaps[reg->index];
+
+ regmap_write(io->regmap, reg->offset, val);
+}
+
+u32 clk_ti_readl(struct clk_ti_reg *reg)
+{
+ struct clk_iomap *io = _memmaps[reg->index];
+ u32 val;
+
+ regmap_read(io->regmap, reg->offset, );
+ return val;
+}
+
+#if CONFIG_IS_ENABLED(AM33XX)
Why do you have this ifdef here? These drivers are not planned to be
used by anything but am33xx, or they don't work on any other device?
The patch was developed and tested for the AM33XX SOC (beaglebone black).
The drivers in the clk/ti folder were added by my patches but can also be
used by boards based on different device trees. In those cases, if required,
platform versions of clk_ti_get_regmap_node() could be implemented.
Ok, but this could be handled simply via the defconfigs? None of these
drivers are enabled explicitly for any platform afaics. If someone wants
to try this out, it might work out of box for, say am43xx also. Having
to deal with this ifdef seems counter intuitive.
-Tero
Thanks and regards,
Dario
-Tero
+static ofnode clk_ti_get_regmap_node(struct udevice *dev)
+{
+ ofnode node = dev_ofnode(dev), parent;
+
+ if (!ofnode_valid(node))
+ return ofnode_null();
+
+ parent = ofnode_get_parent(node);
+ if (strcmp(ofnode_get_name(parent), "clocks"))
+ return ofnode_null();
+
+ return ofnode_get_parent(parent);
+}
+#else
+static ofnode clk_ti_get_regmap_node(struct udevice *dev)
+{
+ return ofnode_null();
+}
+#endif
+
+int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg)
+{
+ ofnode node;
+ int i, ret;
+ u32 val;
+
+ ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", index, );
+ if (ret) {
+ dev_err(dev, "%s must have reg[%d]\n", ofnode_get_name(node),
+ index);
+ return ret;
+ }
+
+ /* parent = ofnode_get_parent(parent); */
+ node = clk_ti_get_regmap_node(dev);
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "failed to get regmap node\n");
+ return -EFAULT;
+ }
+
+ for (i = 0; i < clk_memmaps_num; i++) {
+ if (ofnode_equal(clk_memmaps[i].node, node))
+ break;
+ }
+
+ if (i == clk_memmaps_num) {
+ if (i == CLK_MAX_MEMMAPS)
+ return -ENOMEM;
+
+ ret = regmap_init_mem(node, _memmaps[i].regmap);
+ if (ret)
+ return ret;
+
+ clk_memmaps[i].node = node;
+ clk_memmaps_num++;
+ }
+
+ reg->index = i;
+ reg->offset = val;
+ return 0;
+}
diff --git a/drivers/clk/ti/clk.h b/drivers/clk/ti/clk.h
index 601c3823f7..ea36d065ac 100644
--- a/drivers/clk/ti/clk.h
+++ b/drivers/clk/ti/clk.h
@@ -9,5 +9,18 @@
#define _CLK_TI_H
void clk_ti_latch(fdt_addr_t reg, s8 shift);
+/**
+ * struct clk_ti_reg - TI register declaration
+ * @offset: offset from the master IP module base address
+ * @index: index of the master IP module
+
Re: [PATCH] fdtdec: fdtdec_get_aliases_highest_id: skip aliases to disabled nodes
On Thu, Apr 29, 2021 at 9:10 AM Simon Glass wrote: > > Hi Tim, > > On Fri, 16 Apr 2021 at 14:30, Tim Harvey wrote: > > > > When looking for an alias with the highest id skip aliases for nodes > > that are disabled. > > > > Signed-off-by: Tim Harvey > > --- > > lib/fdtdec.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/lib/fdtdec.c b/lib/fdtdec.c > > index 864589193b..d47195525a 100644 > > --- a/lib/fdtdec.c > > +++ b/lib/fdtdec.c > > @@ -546,6 +546,8 @@ int fdtdec_get_alias_highest_id(const void *blob, const > > char *base) > > if (*prop != '/' || prop[len - 1] || > > strncmp(name, base, base_len)) > > continue; > > + if (!fdtdec_get_is_enabled(blob, fdt_path_offset(blob, > > prop))) > > + continue; > > We really can't do this here. It is quite an expensive operation to > locate the node for a path. > > Why is this needed? It seems odd to have an alias pointing to a disabled > device. > Simon, The issue I ran into here was with an imx6 based board that does not use the FEC ethernet on the SoC. In this case imx6qdl.dtsi delcares an alias 'thernet0 = ' yet the fec node is not enabled. However because fdtdec_get_alias_highest_id does not skip this alias to a disabled device any enumerated ethernet devices get an index of 1 instead of 0 which is incorrect and causes the mac addresses to be misaligned. In general it is just wrong to reserve id's for disabled devices. Tim
[PATCH] include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile
Legacy boot flow (SPL->U-Boot Proper->OS) boot to OS via Kernel Image and dtb files using booti command. ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file using bootm command. Change to use CONFIG_SPL_ATF to differentiate the bootfile of default environment variable. We shouldn't use CONFIG_FIT because it is enabled by default for U-Boot Proper. Signed-off-by: Siew Chin Lim --- include/configs/socfpga_soc64_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index f0b7884ebc..347620e1b5 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -82,7 +82,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * Environment variable */ -#ifdef CONFIG_FIT +#if IS_ENABLED(CONFIG_SPL_ATF) #define CONFIG_BOOTFILE "kernel.itb" #else #define CONFIG_BOOTFILE "Image" -- 2.19.0
Re: [PATCH 1/1] doc: fatinfo man-page
Am 29. April 2021 18:10:01 MESZ schrieb Simon Glass : >On Sat, 17 Apr 2021 at 11:04, Heinrich Schuchardt >wrote: >> >> Provide a man-page for the fatinfo command. > >It seems to provide a link to it, not the actual page. A follow up patch with the missing file has already been merged. Thanks for reviewing. Best regards Heinrich > >> >> Signed-off-by: Heinrich Schuchardt >> --- >> doc/usage/index.rst | 1 + >> 1 file changed, 1 insertion(+) > >Reviewed-by: Simon Glass
Re: [PATCH v3 2/7] lmb: add lmb_is_reserved_flags
Hi Patrick,
On Wed, 28 Apr 2021 at 03:23, Patrick Delaunay
wrote:
>
> Add a new function lmb_is_reserved_flags to check is a
> address is reserved with a specific flags.
>
> This function can be used to check if an address was
> reserved with no-map flags with:
>
> lmb_is_reserved_flags(lmb, addr, LMB_NOMAP);
>
> Signed-off-by: Patrick Delaunay
> ---
>
> (no changes since v1)
>
> include/lmb.h | 1 +
> lib/lmb.c | 10 --
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/include/lmb.h b/include/lmb.h
> index aa196c63bf..6537d56e18 100644
> --- a/include/lmb.h
> +++ b/include/lmb.h
> @@ -91,6 +91,7 @@ extern phys_addr_t lmb_alloc_addr(struct lmb *lmb,
> phys_addr_t base,
> phys_size_t size);
> extern phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
> extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
> +extern int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int
> flags);
drop extern and please add a function comment
> extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
>
> extern void lmb_dump_all(struct lmb *lmb);
> diff --git a/lib/lmb.c b/lib/lmb.c
> index 69700bf9ba..e270e86186 100644
> --- a/lib/lmb.c
> +++ b/lib/lmb.c
> @@ -443,7 +443,7 @@ phys_size_t lmb_get_free_size(struct lmb *lmb,
> phys_addr_t addr)
> return 0;
> }
>
> -int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
> +int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags)
> {
> int i;
>
> @@ -451,11 +451,17 @@ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
> phys_addr_t upper = lmb->reserved.region[i].base +
> lmb->reserved.region[i].size - 1;
> if ((addr >= lmb->reserved.region[i].base) && (addr <= upper))
> - return 1;
> + return !!((lmb->reserved.region[i].flags & flags)
> + == flags);
I don't know what flags is since there is no comment, but it seems
that you should drop the !!()
> }
> return 0;
> }
>
> +int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
> +{
> + return lmb_is_reserved_flags(lmb, addr, LMB_NONE);
> +}
> +
> __weak void board_lmb_reserve(struct lmb *lmb)
> {
> /* please define platform specific board_lmb_reserve() */
> --
> 2.17.1
>
Regards,
Simon
Re: [PATCH v3 1/7] lmb: Add support of flags for no-map properties
Hi Patrick,
On Wed, 28 Apr 2021 at 03:23, Patrick Delaunay
wrote:
>
> Add "flags" in lmb_property to save the "no-map" property of
> reserved region and a new function lmb_reserve_flags() to check
> this flag.
>
> The default allocation use flags = LMB_NONE.
>
> The adjacent reserved memory region are merged only when they have
> the same flags value.
>
> This patch is partially based on flags support done in Linux kernel
> mm/memblock .c (previously lmb.c); it is why LMB_NOMAP = 0x4, it is
> aligned with MEMBLOCK_NOMAP value.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - remove unnecessary comments in lmb.h
> - rebase on latest lmb patches
>
> include/lmb.h | 20
> lib/lmb.c | 52 ++-
> 2 files changed, 63 insertions(+), 9 deletions(-)
Reviewed-by: Simon Glass
>
> diff --git a/include/lmb.h b/include/lmb.h
> index 541e17093c..aa196c63bf 100644
> --- a/include/lmb.h
> +++ b/include/lmb.h
> @@ -12,6 +12,16 @@
> * Copyright (C) 2001 Peter Bergner, IBM Corp.
> */
>
> +/**
> + * enum lmb_flags - definition of memory region attributes
> + * @LMB_NONE: no special request
> + * @LMB_NOMAP: don't add to mmu configuration
> + */
> +enum lmb_flags {
> + LMB_NONE= 0x0,
> + LMB_NOMAP = 0x4,
> +};
> +
> /**
> * struct lmb_property - Description of one region.
> *
> @@ -21,6 +31,7 @@
> struct lmb_property {
> phys_addr_t base;
> phys_size_t size;
> + enum lmb_flags flags;
> };
>
> /**
> @@ -69,6 +80,8 @@ extern void lmb_init_and_reserve_range(struct lmb *lmb,
> phys_addr_t base,
>phys_size_t size, void *fdt_blob);
> extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
> extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
> +extern long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base,
> + phys_size_t size, enum lmb_flags flags);
Needs a comment
[..]
Regards,
Simon
Re: [PATCH v2] dm: core: Add address translation in fdt_get_resource
Hi Patrick,
On Wed, 28 Apr 2021 at 03:39, Patrick Delaunay
wrote:
>
> Today of_address_to_resource() is called only in
> ofnode_read_resource() for livetree support and
> fdt_get_resource() is called when livetree is not supported.
>
> The fdt_get_resource() doesn't do the address translation
> so when it is required, but the address translation is done
> by ofnode_read_resource() caller, for example in
> drivers/firmware/scmi/smt.c::scmi_dt_get_smt_buffer() {
> ...
> ret = ofnode_read_resource(args.node, 0, );
> if (ret)
> return ret;
>
> faddr = cpu_to_fdt32(resource.start);
> paddr = ofnode_translate_address(args.node, );
> ...
>
> The both behavior should be aligned and the address translation
> must be called in fdt_get_resource() and removed for each caller.
>
> Fixes: a44810123f9e ("dm: core: Add dev_read_resource() to read device
> resources")
> Signed-off-by: Patrick Delaunay
> ---
>
> This patch allows to remove the workaround in smci/smt.c
> introduced by [1].
>
> But it impact with all user of
> - ofnode_read_resource
> - ofnode_read_resource_byname
> - dev_read_resource
> - dev_read_resource_byname
>
> After my first check, the only impacts are in drivers/net/mscc_eswitch
> => I remove the unnecessary translate after code review,
>this patch need to be verify on real hardware
>
> I proposed to merge the workaround [1] as soon as possible to avoid issue
> on stm32mp1 platform and this patch can be merged when it will be acked
> by mscc_eswitch maintainers and other API users.
>
> [1] "scmi: translate the resource only when livetree is not activated"
> http://patchwork.ozlabs.org/project/uboot/list/?series=236526=*
>
>
> Changes in v2:
> - remove translate in luton_switch.c:luton_probe()
>
> drivers/firmware/scmi/smt.c | 12 +---
> drivers/net/mscc_eswitch/jr2_switch.c | 4 +---
> drivers/net/mscc_eswitch/luton_switch.c | 5 +
> drivers/net/mscc_eswitch/ocelot_switch.c | 4 +---
> drivers/net/mscc_eswitch/serval_switch.c | 4 +---
> drivers/net/mscc_eswitch/servalt_switch.c | 4 +---
> lib/fdtdec.c | 6 +-
> 7 files changed, 11 insertions(+), 28 deletions(-)
Can you please also add a test for fdt_get_resource()?
Regards,
Simon
Re: [PATCH v3 4/7] test: lmb: add test for lmb_reserve_flags
On Wed, 28 Apr 2021 at 03:23, Patrick Delaunay
wrote:
>
> Add a test to check the management of reserved region with flags.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> (no changes since v1)
>
> test/lib/lmb.c | 89 ++
> 1 file changed, 89 insertions(+)
Reviewed-by: Simon Glass
>
> diff --git a/test/lib/lmb.c b/test/lib/lmb.c
> index 0d8963fcbf..b2c2b99ef1 100644
> --- a/test/lib/lmb.c
> +++ b/test/lib/lmb.c
> @@ -723,3 +723,92 @@ static int lib_test_lmb_max_regions(struct
> unit_test_state *uts)
>
> DM_TEST(lib_test_lmb_max_regions,
> UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
> +
> +static int lib_test_lmb_flags(struct unit_test_state *uts)
> +{
> + const phys_addr_t ram = 0x4000;
> + const phys_size_t ram_size = 0x2000;
> + struct lmb lmb;
> + long ret;
> +
> + lmb_init();
> +
> + ret = lmb_add(, ram, ram_size);
> + ut_asserteq(ret, 0);
> +
> + /* reserve, same flag */
> + ret = lmb_reserve_flags(, 0x4001, 0x1, LMB_NOMAP);
> + ut_asserteq(ret, 0);
> + ASSERT_LMB(, ram, ram_size, 1, 0x4001, 0x1,
> + 0, 0, 0, 0);
> +
> + /* reserve again, same flag */
> + ret = lmb_reserve_flags(, 0x4001, 0x1, LMB_NOMAP);
> + ut_asserteq(ret, 0);
> + ASSERT_LMB(, ram, ram_size, 1, 0x4001, 0x1,
> + 0, 0, 0, 0);
> +
> + /* reserve again, new flag */
> + ret = lmb_reserve_flags(, 0x4001, 0x1, LMB_NONE);
> + ut_asserteq(ret, -1);
> + ASSERT_LMB(, ram, ram_size, 1, 0x4001, 0x1,
> + 0, 0, 0, 0);
> +
> + ut_asserteq(lmb_is_nomap([0]), 1);
> +
> + /* merge after */
> + ret = lmb_reserve_flags(, 0x4002, 0x1, LMB_NOMAP);
> + ut_asserteq(ret, 1);
> + ASSERT_LMB(, ram, ram_size, 1, 0x4001, 0x2,
> + 0, 0, 0, 0);
> +
> + /* merge before */
> + ret = lmb_reserve_flags(, 0x4000, 0x1, LMB_NOMAP);
> + ut_asserteq(ret, 1);
> + ASSERT_LMB(, ram, ram_size, 1, 0x4000, 0x3,
> + 0, 0, 0, 0);
> +
> + ut_asserteq(lmb_is_nomap([0]), 1);
> +
> + ret = lmb_reserve_flags(, 0x4003, 0x1, LMB_NONE);
> + ut_asserteq(ret, 0);
> + ASSERT_LMB(, ram, ram_size, 2, 0x4000, 0x3,
> + 0x4003, 0x1, 0, 0);
> +
> + ut_asserteq(lmb_is_nomap([0]), 1);
> + ut_asserteq(lmb_is_nomap([1]), 0);
> +
> + /* test that old API use LMB_NONE */
> + ret = lmb_reserve(, 0x4004, 0x1);
> + ut_asserteq(ret, 1);
> + ASSERT_LMB(, ram, ram_size, 2, 0x4000, 0x3,
> + 0x4003, 0x2, 0, 0);
> +
> + ut_asserteq(lmb_is_nomap([0]), 1);
> + ut_asserteq(lmb_is_nomap([1]), 0);
> +
> + ret = lmb_reserve_flags(, 0x4007, 0x1, LMB_NOMAP);
> + ut_asserteq(ret, 0);
> + ASSERT_LMB(, ram, ram_size, 3, 0x4000, 0x3,
> + 0x4003, 0x2, 0x4007, 0x1);
> +
> + ret = lmb_reserve_flags(, 0x4005, 0x1, LMB_NOMAP);
> + ut_asserteq(ret, 0);
> + ASSERT_LMB(, ram, ram_size, 4, 0x4000, 0x3,
> + 0x4003, 0x2, 0x4005, 0x1);
> +
> + /* merge with 2 adjacent regions */
> + ret = lmb_reserve_flags(, 0x4006, 0x1, LMB_NOMAP);
> + ut_asserteq(ret, 2);
> + ASSERT_LMB(, ram, ram_size, 3, 0x4000, 0x3,
> + 0x4003, 0x2, 0x4005, 0x3);
> +
> + ut_asserteq(lmb_is_nomap([0]), 1);
> + ut_asserteq(lmb_is_nomap([1]), 0);
> + ut_asserteq(lmb_is_nomap([2]), 1);
> +
> + return 0;
> +}
> +
> +DM_TEST(lib_test_lmb_flags,
> + UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
> --
> 2.17.1
>
Regards,
Simon
Re: [PATCH v3 5/7] image-fdt: save no-map parameter of reserve-memory
Hi Patrick, On Wed, 28 Apr 2021 at 03:23, Patrick Delaunay wrote: > > Save the no-map information present in 'reserved-memory' node to allow > correct handling when the MMU is configured in board to avoid > speculative access. > > Signed-off-by: Patrick Delaunay > --- > > (no changes since v1) > > common/image-fdt.c | 23 +++ > 1 file changed, 15 insertions(+), 8 deletions(-) Where is no-map documented? Reviewed-by: Simon Glass
Re: [PATCH v1 3/6] common: integrate crypt-based passwords
Hi Steffen,
On Mon, 26 Apr 2021 at 05:19, Steffen Jaeckel
wrote:
>
> Hook into the autoboot flow as an alternative to the existing
> mechanisms.
>
> Signed-off-by: Steffen Jaeckel
> ---
>
> common/Kconfig.boot | 23 +---
> common/autoboot.c | 85 -
> 2 files changed, 95 insertions(+), 13 deletions(-)
>
> diff --git a/common/Kconfig.boot b/common/Kconfig.boot
> index 5a18d62d78..d8012ead3e 100644
> --- a/common/Kconfig.boot
> +++ b/common/Kconfig.boot
> @@ -812,10 +812,16 @@ config AUTOBOOT_ENCRYPTION
> depends on AUTOBOOT_KEYED
> help
> This option allows a string to be entered into U-Boot to stop the
> - autoboot. The string itself is hashed and compared against the hash
> - in the environment variable 'bootstopkeysha256'. If it matches then
> - boot stops and a command-line prompt is presented.
> -
> + autoboot.
> + The behavior depends whether CONFIG_CRYPT_PW is enabled or not.
> + In case CONFIG_CRYPT_PW is enabled, the string will be forwarded
> + to the crypt-based functionality and be compared against the
> + string in the environment variable 'bootstopkeycrypt'.
> + In case CONFIG_CRYPT_PW is disabled the string itself is hashed
> + and compared against the hash in the environment variable
> + 'bootstopkeysha256'.
> + If it matches in either case then boot stops and
> + a command-line prompt is presented.
> This provides a way to ship a secure production device which can
> also
> be accessed at the U-Boot command line.
>
> @@ -853,6 +859,15 @@ config AUTOBOOT_KEYED_CTRLC
> Setting this variable provides an escape sequence from the
> limited "password" strings.
>
> +config AUTOBOOT_STOP_STR_CRYPT
> + string "Stop autobooting via crypt-hashed password"
> + depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
> + help
> + This option adds the feature to only stop the autobooting,
> + and therefore boot into the U-Boot prompt, when the input
> + string / password matches a values that is hashed via
> + one of support crypt options and saved in the environment.
> +
> config AUTOBOOT_STOP_STR_SHA256
> string "Stop autobooting via SHA256 encrypted password"
> depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
> diff --git a/common/autoboot.c b/common/autoboot.c
> index 0bb08e7a4c..de60635d2a 100644
> --- a/common/autoboot.c
> +++ b/common/autoboot.c
> @@ -23,6 +23,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -38,18 +39,80 @@ DECLARE_GLOBAL_DATA_PTR;
> static int stored_bootdelay;
> static int menukey;
>
> -#ifdef CONFIG_AUTOBOOT_ENCRYPTION
> -#define AUTOBOOT_STOP_STR_SHA256 CONFIG_AUTOBOOT_STOP_STR_SHA256
> -#else
> -#define AUTOBOOT_STOP_STR_SHA256 ""
> +#if defined(CONFIG_AUTOBOOT_ENCRYPTION)
> +#if defined(CONFIG_CRYPT_PW) && defined(CONFIG_AUTOBOOT_STOP_STR_CRYPT)
> +#define AUTOBOOT_STOP_STR_ENC CONFIG_AUTOBOOT_STOP_STR_CRYPT
> +#define HAS_STOP_STR_CRYPT 1
See other patch about splitting Kconfig
> +#elif defined(CONFIG_AUTOBOOT_STOP_STR_SHA256)
> +#define AUTOBOOT_STOP_STR_ENC CONFIG_AUTOBOOT_STOP_STR_SHA256
> +#endif
> +#endif
> +#if !defined(AUTOBOOT_STOP_STR_ENC)
> +#define AUTOBOOT_STOP_STR_ENC ""
> #endif
> -
> #ifdef CONFIG_USE_AUTOBOOT_MENUKEY
> #define AUTOBOOT_MENUKEY CONFIG_USE_AUTOBOOT_MENUKEY
> #else
> #define AUTOBOOT_MENUKEY 0
> #endif
>
> +/**
> + * passwd_abort_crypt() - check for a crypt-style hashed key sequence to
> abort booting
> + *
> + * This checks for the user entering a password within a given time.
> + *
> + * The entered password is hashed via one of the crypt-style hash methods
> + * and compared to the pre-defined value from either
> + * the environment variable "bootstopkeycrypt"
> + * or
> + * the config value CONFIG_AUTOBOOT_STOP_STR_CRYPT
> + *
> + * @etime: Timeout value ticks (stop when get_ticks() reachs this)
> + * @return 0 if autoboot should continue, 1 if it should stop
> + */
> +static int passwd_abort_crypt(uint64_t etime)
> +{
> + const char *crypt_env_str = env_get("bootstopkeycrypt");
> + char presskey[MAX_DELAY_STOP_STR];
> + u_int presskey_len = 0;
uint
> + int abort = 0;
> + int err;
> +
> + if (IS_ENABLED(HAS_STOP_STR_CRYPT) && !crypt_env_str)
> + crypt_env_str = AUTOBOOT_STOP_STR_ENC;
> +
> + if (!crypt_env_str)
> + return 0;
> +
> + /* We expect the stop-string to be newline terminated. */
newline-terminated
No need for the period
> + do {
> + if (tstc()) {
> + /* Check for input string overflow */
> + if (presskey_len >= MAX_DELAY_STOP_STR)
> + return 0;
> +
> + presskey[presskey_len] = getchar();
> +
> +
Re: [PATCH 0/5] Revert "fdt: translate address if #size-cells = <0>"
On Sun, 25 Apr 2021 at 07:17, Dario Binacchi wrote:
>
>
> As pointed by [1] and [2] the d64b9cdcd4 ("fdt: translate address if
> #size-cells = <0>")
> commit was wrong. The series reverts the patch and fixes the issue with
> platform code, adding custom routines to access the clocks registers.
> The solution has been inspired by the Linux Kernel code.
>
> [1]
> https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng...@gmail.com/
> [2]
> https://lore.kernel.org/linux-clk/20210402192054.7934-1-dario...@libero.it/T/
>
>
> Dario Binacchi (5):
> clk: ti: add custom API for memory access
> clk: ti: change clk_ti_latch() signature
> clk: ti: gate: use custom API for memory access
> clk: ti: am3-dpll: use custom API for memory access
> Revert "fdt: translate address if #size-cells = <0>"
>
> arch/sandbox/dts/test.dts | 21 --
> common/fdt_support.c | 6 +-
> drivers/clk/ti/clk-am3-dpll.c | 86 +++--
> drivers/clk/ti/clk-divider.c | 20 +++---
> drivers/clk/ti/clk-gate.c | 23 +++
> drivers/clk/ti/clk-mux.c | 20 +++---
> drivers/clk/ti/clk.c | 102 --
> drivers/clk/ti/clk.h | 15 -
> drivers/core/Kconfig | 12
> drivers/core/fdtaddr.c| 2 +-
> drivers/core/of_addr.c| 13 +++-
> drivers/core/ofnode.c | 7 +-
> drivers/core/root.c | 3 -
> include/asm-generic/global_data.h | 24 ---
> test/dm/test-fdt.c| 68
> 15 files changed, 213 insertions(+), 209 deletions(-)
Reviewed-by: Simon Glass
Re: [PATCH v3 3/7] lmb: add lmb_dump_region() function
On Wed, 28 Apr 2021 at 03:23, Patrick Delaunay wrote: > > Add lmb_dump_region() function, to simplify lmb_dump_all_force(). > This patch is based on Linux memblock dump function. > > An example of bdinfo output is: > > . > fdt_size= 0x000146a0 > FB base = 0xfdd0 > lmb_dump_all: > memory.cnt = 0x1 > memory[0] [0xc000-0x], 0x4000 bytes flags: 0 > reserved.cnt = 0x6 > reserved[0][0x1000-0x10045fff], 0x00046000 bytes flags: 4 > reserved[1][0x3000-0x3003], 0x0004 bytes flags: 4 > reserved[2][0x3800-0x3800], 0x0001 bytes flags: 4 > reserved[3][0xe800-0xefff], 0x0800 bytes flags: 4 > reserved[4][0xfbaea344-0xfdff], 0x02515cbc bytes flags: 0 > reserved[5][0xfe00-0x], 0x0200 bytes flags: 4 > arch_number = 0x > TLB addr= 0xfdff > > > Signed-off-by: Patrick Delaunay > --- > > (no changes since v1) > > lib/lmb.c | 40 > 1 file changed, 20 insertions(+), 20 deletions(-) Reviewed-by: Simon Glass
Re: [PATCH] dm: define LOG_CATEGORY for all uclass
On Tue, 27 Apr 2021 at 02:02, Patrick Delaunay wrote: > > Define LOG_CATEGORY for all uclass to allow filtering with > log command. > > Signed-off-by: Patrick Delaunay > --- > > drivers/adc/adc-uclass.c| 2 ++ > drivers/ata/ahci-uclass.c | 2 ++ > drivers/axi/axi-emul-uclass.c | 2 ++ > drivers/axi/axi-uclass.c| 2 ++ > drivers/block/blk-uclass.c | 2 ++ > drivers/block/ide.c | 2 ++ > drivers/bootcount/bootcount-uclass.c| 2 ++ > drivers/button/button-uclass.c | 2 ++ > drivers/cache/cache-uclass.c| 2 ++ > drivers/clk/clk-uclass.c| 2 ++ > drivers/core/root.c | 2 ++ > drivers/core/simple-bus.c | 2 ++ > drivers/cpu/cpu-uclass.c| 2 ++ > drivers/crypto/rsa_mod_exp/mod_exp_uclass.c | 2 ++ > drivers/dma/dma-uclass.c| 2 ++ > drivers/firmware/firmware-uclass.c | 2 ++ > drivers/hwspinlock/hwspinlock-uclass.c | 2 ++ > drivers/i2c/i2c-emul-uclass.c | 2 ++ > drivers/i2c/i2c-uclass.c| 2 ++ > drivers/i2c/muxes/i2c-mux-uclass.c | 2 ++ > drivers/input/keyboard-uclass.c | 2 ++ > drivers/led/led-uclass.c| 2 ++ > drivers/mailbox/mailbox-uclass.c| 2 ++ > drivers/misc/fs_loader.c| 3 +++ > drivers/misc/i2c_eeprom.c | 2 ++ > drivers/misc/misc-uclass.c | 2 ++ > drivers/misc/p2sb-uclass.c | 2 ++ > drivers/misc/pwrseq-uclass.c| 2 ++ > drivers/mmc/mmc-uclass.c| 2 ++ > drivers/mtd/mtd-uclass.c| 2 ++ > drivers/mtd/spi/sf-uclass.c | 2 ++ > drivers/mux/mux-uclass.c| 2 ++ > drivers/nvme/nvme-uclass.c | 2 ++ > drivers/pch/pch-uclass.c| 2 ++ > drivers/pci/pci-uclass.c| 2 ++ > drivers/pci_endpoint/pci_ep-uclass.c| 2 ++ > drivers/phy/phy-uclass.c| 2 ++ > drivers/pinctrl/pinctrl-uclass.c| 2 ++ > drivers/power/domain/power-domain-uclass.c | 2 ++ > drivers/power/pmic/pmic-uclass.c| 2 ++ > drivers/power/regulator/regulator-uclass.c | 2 ++ > drivers/pwm/pwm-uclass.c| 2 ++ > drivers/ram/ram-uclass.c| 2 ++ > drivers/remoteproc/rproc-uclass.c | 3 +++ > drivers/reset/reset-uclass.c| 2 ++ > drivers/rng/rng-uclass.c| 2 ++ > drivers/rtc/rtc-uclass.c| 2 ++ > drivers/scsi/scsi-uclass.c | 2 ++ > drivers/serial/serial-uclass.c | 2 ++ > drivers/smem/smem-uclass.c | 2 ++ > drivers/soc/soc-uclass.c| 2 ++ > drivers/sound/codec-uclass.c| 2 ++ > drivers/sound/i2s-uclass.c | 2 ++ > drivers/sound/sound-uclass.c| 2 ++ > drivers/spi/spi-emul-uclass.c | 2 ++ > drivers/spmi/spmi-uclass.c | 2 ++ > drivers/sysinfo/sysinfo-uclass.c| 2 ++ > drivers/tee/tee-uclass.c| 2 ++ > drivers/thermal/thermal-uclass.c| 2 ++ > drivers/timer/timer-uclass.c| 2 ++ > drivers/ufs/ufs-uclass.c| 2 ++ > drivers/usb/emul/usb-emul-uclass.c | 2 ++ > drivers/usb/gadget/udc/udc-uclass.c | 2 ++ > drivers/usb/host/usb-uclass.c | 2 ++ > drivers/video/backlight-uclass.c| 2 ++ > drivers/video/bridge/video-bridge-uclass.c | 2 ++ > drivers/video/display-uclass.c | 2 ++ > drivers/video/dsi-host-uclass.c | 2 ++ > drivers/video/panel-uclass.c| 2 ++ > drivers/video/vidconsole-uclass.c | 2 ++ > drivers/video/video-uclass.c| 2 ++ > drivers/video/video_osd-uclass.c| 2 ++ > drivers/virtio/virtio-uclass.c | 2 ++ > drivers/w1-eeprom/w1-eeprom-uclass.c| 2 ++ > drivers/w1/w1-uclass.c | 2 ++ > drivers/watchdog/wdt-uclass.c | 2 ++ > drivers/xen/pvblock.c | 3 +++ > 77 files changed, 157 insertions(+) > Reviewed-by: Simon Glass
Re: [PATCH v4 2/6] lib: ecdsa: Add skeleton to implement ecdsa verification in u-boot
Hi Alex, On Mon, 26 Apr 2021 at 07:21, Alex G. wrote: > > > > On 4/23/21 11:56 PM, Simon Glass wrote: > > Hi Tom, Alex, > > > > On Fri, 23 Apr 2021 at 12:47, Tom Rini wrote: > >> > >> On Fri, Apr 23, 2021 at 11:55:57AM +1200, Simon Glass wrote: > >>> Hi Alex, > >>> > >>> On Thu, 22 Apr 2021 at 07:30, Alex G. wrote: > > On 4/21/21 2:15 AM, Simon Glass wrote: > > Hi Alexandru, > > > > On Fri, 16 Apr 2021 at 08:07, Alexandru Gagniuc > > wrote: > >> > >> Prepare the source tree for accepting implementations of the ECDSA > >> algorithm. This patch deals with the boring aspects of Makefiles and > >> Kconfig files. > >> > >> Signed-off-by: Alexandru Gagniuc > >> --- > >>include/image.h | 10 +- > >>include/u-boot/rsa.h | 2 +- > >>lib/Kconfig | 1 + > >>lib/Makefile | 1 + > >>lib/ecdsa/Kconfig| 23 +++ > >>lib/ecdsa/Makefile | 1 + > >>lib/ecdsa/ecdsa-verify.c | 13 + > >>7 files changed, 45 insertions(+), 6 deletions(-) > >>create mode 100644 lib/ecdsa/Kconfig > >>create mode 100644 lib/ecdsa/Makefile > >>create mode 100644 lib/ecdsa/ecdsa-verify.c > > > > Reviewed-by: Simon Glass > > > > nit below > > > >> > >> diff --git a/include/image.h b/include/image.h > >> index 3ff3c035a7..9b95f6783b 100644 > >> --- a/include/image.h > >> +++ b/include/image.h > >> @@ -1224,20 +1224,20 @@ int calculate_hash(const void *data, int > >> data_len, const char *algo, > >>#if defined(USE_HOSTCC) > >># if defined(CONFIG_FIT_SIGNATURE) > >># define IMAGE_ENABLE_SIGN1 > >> -# define IMAGE_ENABLE_VERIFY 1 > >> +# define IMAGE_ENABLE_VERIFY_RSA 1 > >># define IMAGE_ENABLE_VERIFY_ECDSA1 > >># define FIT_IMAGE_ENABLE_VERIFY 1 > >># include > >># else > >># define IMAGE_ENABLE_SIGN0 > >> -# define IMAGE_ENABLE_VERIFY 0 > >> +# define IMAGE_ENABLE_VERIFY_RSA 0 > >># define IMAGE_ENABLE_VERIFY_ECDSA 0 > >># define FIT_IMAGE_ENABLE_VERIFY 0 > >># endif > >>#else > >># define IMAGE_ENABLE_SIGN 0 > >> -# define IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(RSA_VERIFY) > >> -# define IMAGE_ENABLE_VERIFY_ECDSA 0 > >> +# define IMAGE_ENABLE_VERIFY_RSA CONFIG_IS_ENABLED(RSA_VERIFY) > >> +# define IMAGE_ENABLE_VERIFY_ECDSA CONFIG_IS_ENABLED(ECDSA_VERIFY) > > > > Since we are using Kconfig now, can we drop this IMAGE_... stuff and > > just use CONFIG_IS_ENABLED() in the code? > > CONFIG_IS_ENABLED() doesn't work for host tools. > >>> > >>> I wonder if that and IS_ENABLED() can be fixed? > >> > >> Not super easily? Some sort of seeing about cleaning up the code we > >> share with userspace would be nice, yes. But it should also probably > >> means that for the user side of things we always enable a bunch of stuff > >> so that in the end we end up with (nearly) target-agnostic tools. > > > > (just to be clear, this discussion should not hold up this patch IMO) > > > > Yes and in fact at present we allow some things to be disabled in > > tools where we probably should not. > > > > My original question was about CONFIG_IS_ENABLED(). I wonder if it > > doesn't work because the CONFIG is not enabled or because of some > > other reason? > > CONFIG_IS_ENABLED() macro isn't available when compiling host tools. I > suspect nobody implemented it host-side? I think it should map to IS_ENABLED(). But also, do we include kconfig.h in the tools? Regards, Simon
Re: [PATCH v1 1/6] lib: add crypt subsystem
Hi Steffen, On Mon, 26 Apr 2021 at 05:19, Steffen Jaeckel wrote: > > Add the basic functionality required to support the standard crypt > format. > The files crypt-sha256.c and crypt-sha512.c originate from libxcrypt and > their formatting is therefor retained. > The integration is done via a crypt_compare() function in crypt.c. > > ``` > libxcrypt $ git describe --long --always --all > tags/v4.4.17-0-g6b110bc > ``` > > Signed-off-by: Steffen Jaeckel > --- > > Changes in v1: > Added unit-tests of crypt_compare() > Wrapped crypt functions to encapsulate errno > > include/crypt.h | 13 ++ > lib/Kconfig | 1 + > lib/Makefile | 1 + > lib/crypt/Kconfig| 29 > lib/crypt/Makefile | 10 ++ > lib/crypt/alg-sha256.h | 17 ++ > lib/crypt/alg-sha512.h | 17 ++ > lib/crypt/crypt-port.h | 28 > lib/crypt/crypt-sha256.c | 313 + > lib/crypt/crypt-sha512.c | 328 +++ > lib/crypt/crypt.c| 73 + > test/Kconfig | 9 ++ > test/lib/Makefile| 1 + > test/lib/test_crypt.c| 44 ++ > 14 files changed, 884 insertions(+) > create mode 100644 include/crypt.h > create mode 100644 lib/crypt/Kconfig > create mode 100644 lib/crypt/Makefile > create mode 100644 lib/crypt/alg-sha256.h > create mode 100644 lib/crypt/alg-sha512.h > create mode 100644 lib/crypt/crypt-port.h > create mode 100644 lib/crypt/crypt-sha256.c > create mode 100644 lib/crypt/crypt-sha512.c > create mode 100644 lib/crypt/crypt.c > create mode 100644 test/lib/test_crypt.c Reviewed-by: Simon Glass nits below > > diff --git a/include/crypt.h b/include/crypt.h > new file mode 100644 > index 00..e0be2832ff > --- /dev/null > +++ b/include/crypt.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* Copyright (C) 2020 Steffen Jaeckel */ > + > +/** > + * Compare should with the processed passphrase. > + * > + * @should The crypt-style string to compare against > + * @passphrase The plaintext passphrase > + * @equal Pointer to an int where the result is stored > + * '0' = unequal > + * '1' = equal Can this be a return value from the function? true/false > + */ > +void crypt_compare(const char *should, const char *passphrase, int *equal); > diff --git a/lib/Kconfig b/lib/Kconfig > index 6d2d41de30..c7c0b87ec7 100644 > --- a/lib/Kconfig > +++ b/lib/Kconfig > @@ -297,6 +297,7 @@ config AES > > source lib/rsa/Kconfig > source lib/crypto/Kconfig > +source lib/crypt/Kconfig > > config TPM > bool "Trusted Platform Module (TPM) Support" > diff --git a/lib/Makefile b/lib/Makefile > index 6825671955..f0d91986b1 100644 > --- a/lib/Makefile > +++ b/lib/Makefile > @@ -65,6 +65,7 @@ obj-$(CONFIG_FIT_SIGNATURE) += hash-checksum.o > obj-$(CONFIG_SHA1) += sha1.o > obj-$(CONFIG_SHA256) += sha256.o > obj-$(CONFIG_SHA512_ALGO) += sha512.o > +obj-$(CONFIG_CRYPT_PW) += crypt/ > > obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ > obj-$(CONFIG_$(SPL_)ZSTD) += zstd/ > diff --git a/lib/crypt/Kconfig b/lib/crypt/Kconfig > new file mode 100644 > index 00..6f828cefd6 > --- /dev/null > +++ b/lib/crypt/Kconfig > @@ -0,0 +1,29 @@ > +config CRYPT_PW > + bool "Add crypt support for password-based unlock" > + help > + Enable support for crypt-style hashed passphrases. > + This will then be used as the mechanism of choice to > + verify whether the entered password to unlock the > + console is correct or not. > + To make it fully functional, one has also to enable > + CONFIG_AUTOBOOT_KEYED and CONFIG_AUTOBOOT_ENCRYPTION So should CRYPT_PW depend on one or both of those? > + > +if CRYPT_PW > + > +config CRYPT_PW_SHA256 > + bool "Provide sha256crypt" > + select SHA256 > + select SHA256_ALGO > + help > + Enables support for the sha256crypt password-hashing algorithm. > + The prefix is "$5$". > + > +config CRYPT_PW_SHA512 > + bool "Provide sha512crypt" > + select SHA512 > + select SHA512_ALGO > + help > + Enables support for the sha512crypt password-hashing algorithm. > + The prefix is "$6$". > + > +endif > diff --git a/lib/crypt/Makefile b/lib/crypt/Makefile > new file mode 100644 > index 00..290231064c > --- /dev/null > +++ b/lib/crypt/Makefile > @@ -0,0 +1,10 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +# > +# Copyright (c) 2013, Google Inc. > +# > +# (C) Copyright 2000-2007 > +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. > + > +obj-$(CONFIG_CRYPT_PW) += crypt.o > +obj-$(CONFIG_CRYPT_PW_SHA256) += crypt-sha256.o > +obj-$(CONFIG_CRYPT_PW_SHA512) += crypt-sha512.o > diff --git a/lib/crypt/alg-sha256.h b/lib/crypt/alg-sha256.h > new file mode 100644 > index 00..e4b29c9f31 > --- /dev/null > +++ b/lib/crypt/alg-sha256.h > @@ -0,0 +1,17 @@ > +/*
Re: [PATCH] net: use the same alias stem for ethernet as linux
On Thu, 25 Feb 2021 at 07:51, Michael Walle wrote:
>
> Linux uses the prefix "ethernet" whereas u-boot uses "eth". This is from
> the linux tree:
>
> $ grep "eth[0-9].*=.*&" arch/**/*dts{,i}|wc -l
> 0
> $ grep "ethernet[0-9].*=.*&" arch/**/*dts{,i}|wc -l
> 633
>
> In u-boot device trees both prefixes are used. Until recently the only
> user of the ethernet alias was the sandbox test device tree. This
> changed with commit fc054d563bfb ("net: Introduce DSA class for Ethernet
> switches"). There, the MAC addresses are inherited based on the devices
> sequence IDs which is in turn given by the device tree.
>
> Before there are more users in u-boot and both worlds will differ even
> more, rename the alias prefix to "ethernet" to match the linux ones.
> Also adapt the test cases and rename any old aliases in the u-boot
> device trees.
>
> Cc: David Wu
> Signed-off-by: Michael Walle
> ---
> Vladimir, I didn't do another patch to rename any ethernet aliases to
> "eth". Though kontron boards contain "ethernetN" aliases, all in tree
> variants don't make use of it. So there is nothing to be fixed.
>
> arch/arm/dts/fsl-ls1028a-rdb.dts | 12 ++--
> arch/sandbox/dts/test.dts| 10 +-
> net/eth-uclass.c | 4 ++--
> test/dm/ofnode.c | 2 +-
> test/dm/test-fdt.c | 2 +-
> 5 files changed, 15 insertions(+), 15 deletions(-)
Reviewed-by: Simon Glass
Re: [PATCH 03/17] x86: Allow coreboot serial driver to guess the UART
Hi Bin,
On Sun, 25 Apr 2021 at 18:21, Bin Meng wrote:
>
> Hi Simon,
>
> On Sun, Apr 25, 2021 at 10:10 AM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Sun, 25 Apr 2021 at 13:49, Bin Meng wrote:
> > >
> > > Hi Simon,
> > >
> > > On Sat, Apr 24, 2021 at 12:56 PM Simon Glass wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > On Thu, 8 Apr 2021 at 14:23, Bin Meng wrote:
> > > > >
> > > > > Hi Simon,
> > > > >
> > > > > On Wed, Apr 7, 2021 at 12:32 PM Simon Glass wrote:
> > > > > >
> > > > > > At present this driver relies on coreboot to provide information
> > > > > > about
> > > > > > the console UART. However if coreboot is not compiled with the UART
> > > > > > enabled, the information is left out. This configuration is quite
> > > > > > common, e.g. with shipping x86-based Chrome OS Chromebooks.
> > > > > >
> > > > > > Add a way to determine the UART settings in this case, using a
> > > > > > hard-coded list of PCI IDs.
> > > > > >
> > > > > > Signed-off-by: Simon Glass
> > > > > > ---
> > > > > >
> > > > > > drivers/serial/serial_coreboot.c | 68
> > > > > >
> > > > > > include/pci_ids.h| 1 +
> > > > > > 2 files changed, 61 insertions(+), 8 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/serial/serial_coreboot.c
> > > > > > b/drivers/serial/serial_coreboot.c
> > > > > > index de09c8681f5..4b4619432d8 100644
> > > > > > --- a/drivers/serial/serial_coreboot.c
> > > > > > +++ b/drivers/serial/serial_coreboot.c
> > > > > > @@ -11,19 +11,71 @@
> > > > > > #include
> > > > > > #include
> > > > > >
> > > > > > +static const struct pci_device_id ids[] = {
> > > > > > + { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> > > > > > PCI_DEVICE_ID_INTEL_APL_UART2) },
> > > > > > + {},
> > > > > > +};
> > > > > > +
> > > > > > +/*
> > > > > > + * Coreboot only sets up the UART if it uses it and doesn't bother
> > > > > > to put the
> > > > > > + * details in sysinfo if it doesn't. Try to guess in that case,
> > > > > > using devices
> > > > > > + * we know about
> > > > > > + *
> > > > > > + * @plat: Platform data to fill in
> > > > > > + * @return 0 if found, -ve if no UART was found
> > > > > > + */
> > > > > > +static int guess_uart(struct ns16550_plat *plat)
> > > > >
> > > > > This is really not a guess, but use a pre-configured platform data.
> > > > > Also this only work for Apollo Lake board, and will break other boards
> > > > > if they don't have cbinfo available.
> > > >
> > > > Which bit of it breaks other boards?
> > >
> > > I see it does not return the error code to the caller, that's okay ...
> > >
> > > >
> > > > >
> > > > > Why not just simply put a serial node in the device tree and we are
> > > > > all done?
> > > >
> > > > See my other email...I am trying to make this boot on any board that
> > > > coreboot supports.
> > >
> > > But this solution does not scale. One has to put all known UARTs into
> > > serial_coreboot.c.
> >
> > Yes that's right...but this is only for when coreboot does not enable
> > serial. Also the number of new platforms is not that great.
> >
> > >
> > > Why not patch coreboot instead? Why coreboot does not provide a cbinfo
> > > with serial?
> >
> > Because it does not even set up the serial device in that case, so
> > doesn't know the details. The driver is completely missing.
>
> Sigh. Is it possible to upstream a patch to coreboot to enable that?
Well I'm not even sure upstream coreboot boots on the various
Chromebooks I am targetting. If it does, then serial is probablt
enabled. But certainly for chromebooks, it is not. My goal is to have
U-Boot boot on a chromebook in altfw mode with serial enabled.
>
> I don't like the current approach because it ends up duplicating all
> UART IDs/info in C.
Yes. Do you think it would be better to put it in the devicetree? I
suppose we could add some more stuff to the compatible string,
although U-Boot does not support the PCI compatible strings at
present.
What do you suggest?
Regards,
Simon
Re: [PATCH 2/5] common: integrate crypt-based passwords
Hi Steffen,
On Wed, 21 Apr 2021 at 01:55, Steffen Jaeckel
wrote:
>
> On 4/21/21 9:14 AM, Simon Glass wrote:
> > Hi Steffen,
> >
> > On Tue, 13 Apr 2021 at 10:16, Steffen Jaeckel
> > wrote:
> >>
> >> Hook into the autoboot flow as an alternative to the existing
> >> mechanisms.
> >>
> >> Signed-off-by: Steffen Jaeckel
> >> ---
> >>
> >> common/Kconfig.boot | 23 +---
> >> common/autoboot.c | 67 +++--
> >> 2 files changed, 77 insertions(+), 13 deletions(-)
> >>
> >> diff --git a/common/Kconfig.boot b/common/Kconfig.boot
> >> index 9c335f4f8c..59fec48c5d 100644
> >> --- a/common/Kconfig.boot
> >> +++ b/common/Kconfig.boot
> >> @@ -802,10 +802,16 @@ config AUTOBOOT_ENCRYPTION
> >> depends on AUTOBOOT_KEYED
> >> help
> >> This option allows a string to be entered into U-Boot to stop the
> >> - autoboot. The string itself is hashed and compared against the
> >> hash
> >> - in the environment variable 'bootstopkeysha256'. If it matches
> >> then
> >> - boot stops and a command-line prompt is presented.
> >> -
> >> + autoboot.
> >> + The behavior depends whether CONFIG_CRYPT_PW is enabled or not.
> >> + In case CONFIG_CRYPT_PW is enabled, the string will be forwarded
> >> + to the crypt-based functionality and be compared against the
> >> + string in the environment variable 'bootstopkeycrypt'.
> >> + In case CONFIG_CRYPT_PW is disabled the string itself is hashed
> >> + and compared against the hash in the environment variable
> >> + 'bootstopkeysha256'.
> >> + If it matches in either case then boot stops and
> >> + a command-line prompt is presented.
> >> This provides a way to ship a secure production device which can
> >> also
> >> be accessed at the U-Boot command line.
> >>
> >> @@ -843,6 +849,15 @@ config AUTOBOOT_KEYED_CTRLC
> >> Setting this variable provides an escape sequence from the
> >> limited "password" strings.
> >>
> >> +config AUTOBOOT_STOP_STR_CRYPT
> >> + string "Stop autobooting via crypt-hashed password"
> >> + depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
> >> + help
> >> + This option adds the feature to only stop the autobooting,
> >> + and therefore boot into the U-Boot prompt, when the input
> >> + string / password matches a values that is hashed via
> >> + one of support crypt options and saved in the environment.
> >> +
> >> config AUTOBOOT_STOP_STR_SHA256
> >> string "Stop autobooting via SHA256 encrypted password"
> >> depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
> >> diff --git a/common/autoboot.c b/common/autoboot.c
> >> index 0bb08e7a4c..732a01d0e5 100644
> >> --- a/common/autoboot.c
> >> +++ b/common/autoboot.c
> >> @@ -23,6 +23,7 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >>
> >> DECLARE_GLOBAL_DATA_PTR;
> >>
> >> @@ -38,18 +39,62 @@ DECLARE_GLOBAL_DATA_PTR;
> >> static int stored_bootdelay;
> >> static int menukey;
> >>
> >> -#ifdef CONFIG_AUTOBOOT_ENCRYPTION
> >> -#define AUTOBOOT_STOP_STR_SHA256 CONFIG_AUTOBOOT_STOP_STR_SHA256
> >> -#else
> >> -#define AUTOBOOT_STOP_STR_SHA256 ""
> >> +#if defined(CONFIG_AUTOBOOT_ENCRYPTION)
> >> +#if defined(CONFIG_CRYPT_PW) && defined(CONFIG_AUTOBOOT_STOP_STR_CRYPT)
> >> +#define AUTOBOOT_STOP_STR_ENC CONFIG_AUTOBOOT_STOP_STR_CRYPT
> >> +#define HAS_STOP_STR_CRYPT 1
> >> +#elif defined(CONFIG_AUTOBOOT_STOP_STR_SHA256)
> >> +#define AUTOBOOT_STOP_STR_ENC CONFIG_AUTOBOOT_STOP_STR_SHA256
> >> +#endif
> >> +#endif
> >> +#if !defined(AUTOBOOT_STOP_STR_ENC)
> >> +#define AUTOBOOT_STOP_STR_ENC ""
> >> #endif
> >
> > I wonder if we actually need all this now that things are in Kconfig?
> > Can we use IS_ENABLED() in the code instead?
>
> The problem here is that CONFIG_AUTOBOOT_STOP_STR_{CRYPT,SHA256} are
> strings which can't be checked with IS_ENABLED().
OK...then they should be split into a CONFIG that enables the feature
and one that sets the value.
>
>
> >> -
> >> #ifdef CONFIG_USE_AUTOBOOT_MENUKEY
> >> #define AUTOBOOT_MENUKEY CONFIG_USE_AUTOBOOT_MENUKEY
> >> #else
> >> #define AUTOBOOT_MENUKEY 0
> >> #endif
> >>
> >> +static int passwd_abort_crypt(uint64_t etime)
> >
> > Please add function comment
>
> OK
>
>
> > Also unsigned long if you can...if you need 64-bit on 32-bit machines
> > it is u64...but why? That is a very large number of milliseconds!
>
> I've simply c'ed the prototype of the existing functions :)
> static int passwd_abort_sha256(uint64_t etime)
> static int passwd_abort_key(uint64_t etime)
OK but it still seems wrong to me so I don't think we should copy it.
Perhaps clean up the existing code?
>
>
> >> +{
> >> + const char *crypt_env_str = env_get("bootstopkeycrypt");
> >> + char presskey[MAX_DELAY_STOP_STR];
> >> + u_int presskey_len = 0;
> >
> > uint
> >
> > Can
Re: [Uboot-stm32] [PATCH 1/2] cmd: pinmux: update result of do_status
Hi Patrick,
On Tue, 20 Apr 2021 at 03:21, Patrice CHOTARD wrote:
>
> Hi Patrick
>
> -Original Message-
> From: Uboot-stm32 On
> Behalf Of Patrick DELAUNAY
> Sent: mercredi 28 octobre 2020 11:07
> To: u-boot@lists.denx.de
> Cc: U-Boot STM32 ; Simon Glass
> ; Patrick DELAUNAY ; Sean
> Anderson
> Subject: [Uboot-stm32] [PATCH 1/2] cmd: pinmux: update result of do_status
>
> Update the result of do_status and alway returns a CMD_RET_ value (-ENOSYS
> was a possible result of show_pinmux).
>
> This patch also adds pincontrol name in error messages (dev->name) and treats
> correctly the status sub command when pin-controller device is not selected.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> cmd/pinmux.c | 44 +++-
> test/py/tests/test_pinmux.py | 4 ++--
> 2 files changed, 25 insertions(+), 23 deletions(-)
>
> diff --git a/cmd/pinmux.c b/cmd/pinmux.c index 9942b15419..af04c95a46 100644
> --- a/cmd/pinmux.c
> +++ b/cmd/pinmux.c
> @@ -41,7 +41,7 @@ static int do_dev(struct cmd_tbl *cmdtp, int flag, int argc,
> return CMD_RET_SUCCESS;
> }
>
> -static int show_pinmux(struct udevice *dev)
I think it is better to return the error code and let the caller
ignore it, If we later want to report the error code, we can.
> +static void show_pinmux(struct udevice *dev)
> {
> char pin_name[PINNAME_SIZE];
> char pin_mux[PINMUX_SIZE];
> @@ -51,54 +51,56 @@ static int show_pinmux(struct udevice *dev)
>
> pins_count = pinctrl_get_pins_count(dev);
>
> - if (pins_count == -ENOSYS) {
> - printf("Ops get_pins_count not supported\n");
> - return pins_count;
> + if (pins_count < 0) {
Why change this to < 0 ?
I believe that -ENOSYS is the only valid error. We should update the
get_pins_count() API function to indicate that.
> + printf("Ops get_pins_count not supported by %s\n", dev->name);
> + return;
> }
>
> for (i = 0; i < pins_count; i++) {
> ret = pinctrl_get_pin_name(dev, i, pin_name, PINNAME_SIZE);
> - if (ret == -ENOSYS) {
> - printf("Ops get_pin_name not supported\n");
> - return ret;
> + if (ret) {
> + printf("Ops get_pin_name error (%d) by %s\n",
> + ret, dev->name);
> + return;
> }
>
> ret = pinctrl_get_pin_muxing(dev, i, pin_mux, PINMUX_SIZE);
> if (ret) {
> - printf("Ops get_pin_muxing error (%d)\n", ret);
> - return ret;
> + printf("Ops get_pin_muxing error (%d) by %s in %s\n",
> + ret, pin_name, dev->name);
> + return;
> }
>
> printf("%-*s: %-*s\n", PINNAME_SIZE, pin_name,
>PINMUX_SIZE, pin_mux);
> }
> -
> - return 0;
> }
>
> static int do_status(struct cmd_tbl *cmdtp, int flag, int argc,
> char *const argv[])
> {
> struct udevice *dev;
> - int ret = CMD_RET_USAGE;
>
> - if (currdev && (argc < 2 || strcmp(argv[1], "-a")))
> - return show_pinmux(currdev);
> + if (argc < 2) {
> + if (!currdev) {
> + printf("pin-controller device not selected\n");
> + return CMD_RET_FAILURE;
> + }
> + show_pinmux(currdev);
> + return CMD_RET_SUCCESS;
> + }
>
> - if (argc < 2 || strcmp(argv[1], "-a"))
> - return ret;
> + if (strcmp(argv[1], "-a"))
> + return CMD_RET_USAGE;
>
> uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
> /* insert a separator between each pin-controller display */
> printf("--\n");
> printf("%s:\n", dev->name);
> - ret = show_pinmux(dev);
> - if (ret < 0)
> - printf("Can't display pin muxing for %s\n",
> - dev->name);
> + show_pinmux(dev);
> }
>
> - return ret;
> + return CMD_RET_SUCCESS;
> }
>
> static int do_list(struct cmd_tbl *cmdtp, int flag, int argc, diff --git
> a/test/py/tests/test_pinmux.py b/test/py/tests/test_pinmux.py index
> 0cbbae000c..b3ae2ab024 100644
> --- a/test/py/tests/test_pinmux.py
> +++ b/test/py/tests/test_pinmux.py
> @@ -13,9 +13,9 @@ def test_pinmux_usage_1(u_boot_console):
> @pytest.mark.buildconfigspec('cmd_pinmux')
> def test_pinmux_usage_2(u_boot_console):
> """Test that 'pinmux status' executed without previous "pinmux dev"
> -command displays pinmux usage."""
> +command displays error message."""
> output = u_boot_console.run_command('pinmux status')
> -assert 'Usage:' in output
> +
Re: [PATCH v2 5/5] test/py: Add usb gadget binding test
On Mon, 19 Apr 2021 at 02:58, Patrice Chotard wrote: > > Add a specific usb gadget binding test which check that > binding a driver without compatible string is working as expected. > > the command "bind /usb@1 usb_ether" should give the following "dm tree" > command output: > > [...] > usb 0 [ ] usb_sandbox |-- usb@1 > usb_hub 0 [ ] usb_hub | |-- hub > usb_emul 0 [ ] usb_sandbox_hub | | `-- hub-emul > usb_emul 1 [ ] usb_sandbox_flash | | |-- flash-stick@0 > usb_emul 2 [ ] usb_sandbox_flash | | |-- flash-stick@1 > usb_emul 3 [ ] usb_sandbox_flash | | |-- flash-stick@2 > usb_emul 4 [ ] usb_sandbox_keyb | | `-- keyb@3 > eth 4 [ ] usb_ether | `-- usb@1 > [...] > > Signed-off-by: Patrice Chotard > Cc: Marek Vasut > Cc: Herbert Poetzl > > --- > > Changes in v2: > - add bind test > > test/py/tests/test_bind.py | 7 +++ > 1 file changed, 7 insertions(+) Reviewed-by: Simon Glass
Re: [PATCH 2/2] cmd: pinmux: support pin name in status command
Hi Patrick,
On Wed, 28 Oct 2020 at 03:06, Patrick Delaunay wrote:
>
> Allow pin name parameter for pimux staus command,
> as gpio command to get status of one pin.
>
> The possible usage of the command is:
>
> > pinmux dev pinctrl
> > pinmux status
>
> > pinmux status -a
>
> > pinmux status
>
> Signed-off-by: Patrick Delaunay
> ---
>
> cmd/pinmux.c | 41 +---
> test/py/tests/test_pinmux.py | 29 +
> 2 files changed, 58 insertions(+), 12 deletions(-)
>
> diff --git a/cmd/pinmux.c b/cmd/pinmux.c
> index af04c95a46..e096f16982 100644
> --- a/cmd/pinmux.c
> +++ b/cmd/pinmux.c
> @@ -41,19 +41,20 @@ static int do_dev(struct cmd_tbl *cmdtp, int flag, int
> argc,
> return CMD_RET_SUCCESS;
> }
>
> -static void show_pinmux(struct udevice *dev)
> +static bool show_pinmux(struct udevice *dev, char *name)
How about returning -ENOENT if there is no pin.
> {
> char pin_name[PINNAME_SIZE];
> char pin_mux[PINMUX_SIZE];
> int pins_count;
> int i;
> int ret;
> + bool found = false;
>
> pins_count = pinctrl_get_pins_count(dev);
>
> if (pins_count < 0) {
> printf("Ops get_pins_count not supported by %s\n", dev->name);
> - return;
> + return found;
Here found will be false, so I think you are conflating different
errors. Better to return pins_count in this case.
> }
>
> for (i = 0; i < pins_count; i++) {
> @@ -61,43 +62,59 @@ static void show_pinmux(struct udevice *dev)
> if (ret) {
> printf("Ops get_pin_name error (%d) by %s\n",
>ret, dev->name);
> - return;
> + return found;
> }
> -
> + if (name && strcmp(name, pin_name))
> + continue;
> + found = true;
> ret = pinctrl_get_pin_muxing(dev, i, pin_mux, PINMUX_SIZE);
> if (ret) {
> printf("Ops get_pin_muxing error (%d) by %s in %s\n",
>ret, pin_name, dev->name);
> - return;
> + return found;
> }
>
> printf("%-*s: %-*s\n", PINNAME_SIZE, pin_name,
>PINMUX_SIZE, pin_mux);
> }
> +
> + return found;
> }
>
> static int do_status(struct cmd_tbl *cmdtp, int flag, int argc,
> char *const argv[])
> {
> struct udevice *dev;
> + char *name;
> + bool found = false;
>
> if (argc < 2) {
> if (!currdev) {
> printf("pin-controller device not selected\n");
> return CMD_RET_FAILURE;
> }
> - show_pinmux(currdev);
> + show_pinmux(currdev, NULL);
> return CMD_RET_SUCCESS;
> }
>
> if (strcmp(argv[1], "-a"))
> - return CMD_RET_USAGE;
> + name = argv[1];
> + else
> + name = NULL;
>
> uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
> - /* insert a separator between each pin-controller display */
> - printf("--\n");
> - printf("%s:\n", dev->name);
> - show_pinmux(dev);
> + if (!name) {
> + /* insert a separator between each pin-controller
> display */
> + printf("--\n");
> + printf("%s:\n", dev->name);
> + }
> + if (show_pinmux(dev, name))
> + found = true;
> + }
> +
> + if (name && !found) {
> + printf("%s not found\n", name);
> + return CMD_RET_FAILURE;
> }
>
> return CMD_RET_SUCCESS;
> @@ -148,5 +165,5 @@ U_BOOT_CMD(pinmux, CONFIG_SYS_MAXARGS, 1, do_pinmux,
>"show pin-controller muxing",
>"list - list UCLASS_PINCTRL devices\n"
>"pinmux dev [pincontroller-name] - select pin-controller device\n"
> - "pinmux status [-a] - print pin-controller muxing
> [for all]\n"
> + "pinmux status [-a | pin-name] - print pin-controller muxing
> [for all | for pin-name]\n"
> )
> diff --git a/test/py/tests/test_pinmux.py b/test/py/tests/test_pinmux.py
> index b3ae2ab024..fbde1d99b1 100644
> --- a/test/py/tests/test_pinmux.py
> +++ b/test/py/tests/test_pinmux.py
> @@ -82,3 +82,32 @@ def test_pinmux_status(u_boot_console):
> assert ('P6: GPIO1 drive-open-drain.' in output)
> assert ('P7: GPIO2 bias-pull-down input-enable.' in output)
> assert ('P8: GPIO3 bias-disable.' in output)
> +
> +@pytest.mark.buildconfigspec('cmd_pinmux')
> +@pytest.mark.boardspec('sandbox')
> +def
Re: [PATCH 1/1] doc: fatinfo man-page
On Sat, 17 Apr 2021 at 11:04, Heinrich Schuchardt wrote: > > Provide a man-page for the fatinfo command. It seems to provide a link to it, not the actual page. > > Signed-off-by: Heinrich Schuchardt > --- > doc/usage/index.rst | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Simon Glass
Re: [PATCH v2 4/5] configs: sandbox: add USB_ETHER and GADGET_DOWNLOAD gadget support
On Mon, 19 Apr 2021 at 02:49, Patrice Chotard wrote: > > This is needed for new gadget binding test. > > Signed-off-by: Patrice Chotard > Cc: Marek Vasut > Cc: Herbert Poetzl > --- > > (no changes since v1) > > configs/sandbox_defconfig | 3 +++ > 1 file changed, 3 insertions(+) Reviewed-by: Simon Glass
Re: [PATCH v2 04/13] gpio: Introduce CONFIG_ONLY_GENERIC_GPIO to cleanup #ifdefs
Hi Masami, On Fri, 16 Apr 2021 at 16:38, Masami Hiramatsu wrote: > > Many architecture do not have specific asm/arch/gpio.h, so instead > of adding !defined(CONFIG_ARCH_xxx), introduce CONFIG_ONLY_GENERIC_GPIO This seems OK, but I think GPIO_GENERIC_ONLY is a better name, since it uses the GPIO prefix. I would also prefer to have a 'positive' option, but I suspect that might be a pain to do? > and select it. > > Signed-off-by: Masami Hiramatsu > --- > arch/arm/Kconfig | 17 + > arch/arm/include/asm/gpio.h |8 +--- > board/cortina/common/Kconfig |1 + > 3 files changed, 19 insertions(+), 7 deletions(-) > [..] Regards, Simon
Re: [RFC PATCH v1] lib: rsa: introduce RSA_SOFTWARE_EXP_TINY
Hi Igor, On Fri, 16 Apr 2021 at 01:10, Igor Opaniuk wrote: > > From: Igor Opaniuk > > Introduce RSA_SOFTWARE_EXP_TINY Kconfig option, which does not require > DM to be enabled. This can be handy on devices, where SPL + signed > U-Boot FIT image setup is used, where it isn't possible to enable SPL_DM > mainly due to SRAM size constraits. > > For example, on iMX8MM with this option enabled and SPL_DM disabled > it's possible to save almost 11Kb: That seems a lot...do you have OF_PLATDATA enabled? > > With RSA_SOFTWARE_EXP_TINY enabled: > spl/u-boot-spl-nodtb.bin 99824 > > Without: > spl/u-boot-spl-nodtb.bin 111088 > > Signed-off-by: Igor Opaniuk > --- > > lib/rsa/Kconfig | 11 ++- > lib/rsa/rsa-verify.c | 8 > 2 files changed, 14 insertions(+), 5 deletions(-) Regards, Simon
Re: [PATCH] fdtdec: fdtdec_get_aliases_highest_id: skip aliases to disabled nodes
Hi Tim,
On Fri, 16 Apr 2021 at 14:30, Tim Harvey wrote:
>
> When looking for an alias with the highest id skip aliases for nodes
> that are disabled.
>
> Signed-off-by: Tim Harvey
> ---
> lib/fdtdec.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 864589193b..d47195525a 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -546,6 +546,8 @@ int fdtdec_get_alias_highest_id(const void *blob, const
> char *base)
> if (*prop != '/' || prop[len - 1] ||
> strncmp(name, base, base_len))
> continue;
> + if (!fdtdec_get_is_enabled(blob, fdt_path_offset(blob, prop)))
> + continue;
We really can't do this here. It is quite an expensive operation to
locate the node for a path.
Why is this needed? It seems odd to have an alias pointing to a disabled device.
>
> val = trailing_strtol(name);
> if (val > max) {
> --
> 2.17.1
>
Regards,
Simon
Re: [PATCH v2 2/4] test: Allow simple glob pattern in the test name
On Thu, 11 Feb 2021 at 07:40, Andy Shevchenko wrote: > > When run `ut dm [test name]` allow to use simple pattern to run all tests > started with given prefix. For example, to run all ACPI test cases: > ut dm acpi* > > Signed-off-by: Andy Shevchenko > --- > v2: rebased against dm/test-working branch (Simon) Sadly that is deferred, but we can pick this patch up later. > test/test-main.c | 11 +-- > 1 file changed, 9 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass Applied to u-boot-dm, thanks!
Re: [PATCH 1/2] binman: Tweak implementation of fmap
Use an interator in two of the fmap tests so it is easier to add new items. Also check the name first since that is the first indication that something is wrong. Use a variable for the expected size of the fmap to avoid repeating the code. Signed-off-by: Simon Glass --- tools/binman/ftest.py | 69 --- 1 file changed, 38 insertions(+), 31 deletions(-) Applied to u-boot-dm, thanks!
Re: [PATCH v2 3/4] test: Use positive conditional in test_matches()
On Thu, 11 Feb 2021 at 07:40, Andy Shevchenko
wrote:
>
> It is easier to read the positive conditional.
>
> While at it, convert hard coded length of "_test_" to strlen("_test_")
> which will be converted to a constant bu optimizing compiler.
>
> Signed-off-by: Andy Shevchenko
> ---
> v2: new patch
> test/test-main.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass
Applied to u-boot-dm, thanks!
Re: [PATCH 3/5] Azure/GitLab: Ensure we use requirements.txt for testsuites
On Fri, Feb 26, 2021 at 10:31 PM Tom Rini wrote: > > On Fri, Feb 26, 2021 at 10:25:30PM +0800, Bin Meng wrote: > > On Fri, Feb 26, 2021 at 8:53 PM Tom Rini wrote: > > > > > > Given that test/py/requirements.txt has all required test modules, make > > > use of that rather than a manual pip install list before running our > > > assorted tool testsuites. > > > > > > Signed-off-by: Tom Rini > > > --- > > > .azure-pipelines.yml | 2 +- > > > .gitlab-ci.yml | 2 +- > > > 2 files changed, 2 insertions(+), 2 deletions(-) > > > Applied to u-boot-dm, thanks!
Re: [PATCH 2/2] binman: Support adding sections to FMAPs
When used with hierarchical images, use the Chromium OS convention of adding a section before all the subentries it contains. Signed-off-by: Simon Glass --- tools/binman/entries.rst | 13 +-- tools/binman/etype/fmap.py | 20 +++-- tools/binman/ftest.py | 25 ++ tools/binman/test/095_fmap_x86_section.dts | 2 +- 4 files changed, 51 insertions(+), 9 deletions(-) Applied to u-boot-dm, thanks!
Re: [PATCH] dm: core: Fix uninitialized return value from dm_scan_fdt_node
On Thu, 8 Apr 2021 at 22:15, Sean Anderson wrote:
>
> If there are no nodes or if all nodes are disabled, this function would
> return err without setting it first. Fix this by initializing err to
> zero.
>
> Fixes: 94f7afdf7e ("dm: core: Ignore disabled devices when binding")
>
> Signed-off-by: Sean Anderson
> ---
>
> drivers/core/root.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass
Applied to u-boot-dm, thanks!
Re: [PATCH 1/4] buildman: Tidy up a few comments
Add some function comments which are missing, or missing arguments. Signed-off-by: Simon Glass --- tools/buildman/builderthread.py | 10 +++--- tools/buildman/control.py | 2 ++ tools/buildman/func_test.py | 13 +++-- 3 files changed, 20 insertions(+), 5 deletions(-) Applied to u-boot-dm, thanks!
Re: [PATCH 2/4] buildman: Use common code to send an result
At present the code to report a build result is duplicated. Put it in a common function to avoid this. Signed-off-by: Simon Glass --- tools/buildman/builderthread.py | 21 + 1 file changed, 13 insertions(+), 8 deletions(-) Applied to u-boot-dm, thanks!
Re: [PATCH] patman: Parse checkpatch by message instead of by line
On Thu, 1 Apr 2021 at 15:50, Evan Benn wrote: > > Parse each empty-line-delimited message separately. This saves having to > deal with all the different line content styles, we only care about the > header ERROR | WARNING | NOTE... > > Also make checkpatch print line information for a uboot specific > warning. > > Signed-off-by: Evan Benn > --- > > scripts/checkpatch.pl | 18 +-- > tools/patman/checkpatch.py | 218 +++-- > 2 files changed, 144 insertions(+), 92 deletions(-) Reviewed-by: Simon Glass Applied to u-boot-dm, thanks!
Re: [PATCH 4/4] buildman: Use bytes for the environment
At present we sometimes see problems in gitlab where the environment has
0x80 characters or sequences which are not valid UTF-8.
Avoid this by using bytes for the environment, both internal to buildman
and when writing out the 'env' file. Add a test to make sure this works
as expected.
Reported-by: Marek Vasut
Fixes: e5fc79ea718 ("buildman: Write the environment out to an 'env' file")
Signed-off-by: Simon Glass
---
tools/buildman/builderthread.py | 5 ++---
tools/buildman/func_test.py | 12
tools/buildman/toolchain.py | 24
3 files changed, 30 insertions(+), 11 deletions(-)
Applied to u-boot-dm, thanks!
Re: [PATCH 3/4] buildman: Handle exceptions in threads gracefully
There have been at least a few cases where an exception has occurred in a thread and resulted in buildman hanging: running out of disk space and getting a unicode error. Handle these by collecting a list of exceptions, printing them out and reporting failure if any are found. Add a test for this. Signed-off-by: Simon Glass --- tools/buildman/builder.py | 22 +- tools/buildman/builderthread.py | 14 +- tools/buildman/control.py | 16 +++- tools/buildman/func_test.py | 15 +++ 4 files changed, 56 insertions(+), 11 deletions(-) Applied to u-boot-dm, thanks!
Re: [PATCH v3 2/2] test: dm: add test item for ofnode_get_addr() and ofnode_get_size()
On Mon, 12 Apr 2021 at 18:51, chenguanqiao wrote: > > From: Chen Guanqiao > > Add test item for getting address and size functions > > Test the following function: > - ofnode_get_addr() > - ofnode_get_size() > > Signed-off-by: Chen Guanqiao > --- > test/dm/ofnode.c | 31 +++ > 1 file changed, 31 insertions(+) Reviewed-by: Simon Glass Applied to u-boot-dm, thanks!
Re: [PATCH v3 1/2] dm: core: Add size operations on device tree references
On Mon, 12 Apr 2021 at 18:51, chenguanqiao wrote: > > From: Chen Guanqiao > > Add functions to add size of addresses in the device tree using ofnode > references. > > If the size is not set, return FDT_SIZE_T_NONE. > > Signed-off-by: Chen Guanqiao > --- > drivers/core/ofnode.c | 11 +++ > include/dm/ofnode.h | 10 ++ > include/fdtdec.h | 5 +++-- > 3 files changed, 24 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass Applied to u-boot-dm, thanks!
Re: [PATCH] binman: Correct testSplNoDtb() and Tpl also
On Sun, Apr 25, 2021 at 08:39:32AM +1200, Simon Glass wrote: > These two tests require an ELF image so that symbol information can be > written into the SPL/TPL binary. At present they rely on other tests > having set it up first, but every test must run independently. This can > cause occasional errors in CI. > > Fix this by setting up the required files, as other tests do. > > Signed-off-by: Simon Glass Reviewed-by: Tom Rini -- Tom Applied to u-boot-dm, thanks!
Re: [PATCH 1/1] tpm: missing event types
On Wed, Apr 21, 2021 at 12:24:29PM +0200, Heinrich Schuchardt wrote: > Add a reference for the TPM event types and provide missing constants. > > Signed-off-by: Heinrich Schuchardt > --- > include/tpm-v2.h | 24 > 1 file changed, 16 insertions(+), 8 deletions(-) > Applied to u-boot-dm, thanks!
Re: [PATCH] dtoc: Correct dtoc output when testing
At present each invocation of run_steps() updates OUTPUT_FILES_COMMON, since it does not make a copy of the dict. This is fine for a single invocation, but for tests, run_steps() is invoked many times. As a result it may include unwanted items from the previous run, if it happens that a test runs twice on the same CPU. The problem has not been noticied previously, as there are few enough tests and enough CPUs that is is rare for the 'wrong' combination of tests to run together. Fix this by making a copy of the dict, before updating it. Update the tests to suit, taking account of the files that are no-longer generated. With this fix, we no-longer generate files which are not needed for a particular state of OF_PLATDATA_INST, so the check_instantiate() function is not needed anymore. It has become dead code and so fails the code-coverage test (dtoc -T). Remove it. Signed-off-by: Simon Glass --- tools/dtoc/dtb_platdata.py | 24 +- tools/dtoc/test_dtoc.py| 51 -- 2 files changed, 22 insertions(+), 53 deletions(-) Applied to u-boot-dm, thanks!
[PATCH] configs: sama7g5ek: increase bootm len
Increase the BOOTM_LEN to 32M . This would allow a bigger kernel image to be booted, for example the multi_v7_defconfig. Loading Kernel Image Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover resetting ... Signed-off-by: Eugen Hristev --- include/configs/sama7g5ek.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index ef3bfa36fd..96db82e9d4 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -11,7 +11,7 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 2400 /* from 24 MHz crystal */ - +#define CONFIG_SYS_BOOTM_LEN SZ_32M /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x6000 #define CONFIG_SYS_SDRAM_SIZE 0x2000 -- 2.25.1
Re: Please pull u-boot-cfi-flash/master
On Thu, Apr 29, 2021 at 10:48:45AM +0200, Stefan Roese wrote: > Hi Tom, > > please pull the following cfi-flash related patches: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Please pull u-boot-marvell/master
On Thu, Apr 29, 2021 at 08:47:03AM +0200, Stefan Roese wrote: > Hi Tom, > > please pull the next batch of Marvell Armada related patches. Here the > summary log: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-usb/master
On Thu, Apr 29, 2021 at 12:09:43AM +0200, Marek Vasut wrote: > The following changes since commit 79b0f08d6af498e6fda8cd257d62e2095764410c: > > configs: Resync with savedefconfig (2021-04-27 08:28:38 -0400) > > are available in the Git repository at: > > git://source.denx.de/u-boot-usb.git master > > for you to fetch changes up to 53396d67baef4acbcc257c5f2c702935b62cc858: > > usb: ehci-mx6: Limit PHY address parsing to !CONFIG_PHY (2021-04-28 > 17:16:18 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL u-boot] Please pull u-boot-amlogic-20210428
On Wed, Apr 28, 2021 at 05:50:41PM +0200, Neil Armstrong wrote: > Hi Tom, > > A single patch to fix boot on (at least) Odroid-C4, where the MDIO bus reset > used random > sleep values instead of the proper pdata values. > > The CI job is at > https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/7337 > > Thanks, > Neil > > The following changes since commit 79b0f08d6af498e6fda8cd257d62e2095764410c: > > configs: Resync with savedefconfig (2021-04-27 08:28:38 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-amlogic.git > tags/u-boot-amlogic-20210428 > > for you to fetch changes up to 98b8204626ac2837e927e79d3dfe77246e506c02: > > net: designware: fix PHY reset with DM_MDIO (2021-04-28 17:45:26 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 6/6] net: octeontx: smi: fix mii probe
On Wed, Apr 28, 2021 at 10:21 PM Stefan Roese wrote:
>
> Hi Tim,
>
> On 28.04.21 17:11, Tim Harvey wrote:
> > On Mon, Apr 26, 2021 at 10:19 PM Stefan Roese wrote:
> >>
> >> Hi Tim,
> >>
> >> On 26.03.21 16:55, Tim Harvey wrote:
> >>> On Thu, Mar 25, 2021 at 11:48 PM Stefan Roese wrote:
>
> On 26.03.21 01:07, Tim Harvey wrote:
> > The fdt node offset is apparently not set properly when probed
> > causing no MDIO busses to be found. Fix this by obtaining the
> > offset.
> >
> > Signed-off-by: Tim Harvey
>
> Reviewed-by: Stefan Roese
>
> Thanks,
> Stefan
>
> > ---
> > drivers/net/octeontx/smi.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c
> > index 91dcd05e4b..27f4423c6a 100644
> > --- a/drivers/net/octeontx/smi.c
> > +++ b/drivers/net/octeontx/smi.c
> > @@ -325,6 +325,8 @@ int octeontx_smi_probe(struct udevice *dev)
> > return -1;
> > }
> >
> > + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
> > +
> > "cavium,thunder-8890-mdio-nexus");
> > fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
> > ret = fdt_node_check_compatible(gd->fdt_blob, subnode,
> >
> > "cavium,thunder-8890-mdio");
> >
> >>>
> >>> Honestly this is the wrong fix for this issue and I'm hoping someone
> >>> could educate me. I'm a bit confused at why there are several ways to
> >>> work with dt (int offsets vs ofnodes which are unions of int offsets
> >>> and node pointers???).
> >>>
> >>> The above patch was not needed previously so something changed in the
> >>> ofnode field of struct udevice between v2019.10 and v2021.01.
> >>>
> >>> Simon, could you explain what the proper way to work with dev->ofnode
> >>> in probe functions is to loop over subnodes?
> >>
> >> This version is in mainline now. Tim, could you please re-visit this
> >> and perhaps switch to using live tree API, as suggested by Suneel:
> >>
> >> ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
> >> ret = ofnode_device_is_compatible(subnode,
> >> "cavium,thunder-8890-mdio");
> >>
> >
> > Stefan,
> >
> > Yes, I can submit this but I would really like to understand the
> > original issue. Do you or Simon perhaps know why the fdt node offset
> > in dev passed to probe is wrong? It's not null but it does not appear
> > to point to a device-tree (or perhaps I was using the wrong functions
> > on it not fully understanding the current state of this live tree
> > API).
>
> I don't have an OcteonTX board installed right now, so it's not easy to
> really verify this. AFAIU, fdt_for_each_subnode() etc is deprecated and
> the use of e.g. this API seems "more modern":
>
> ofnode subnode;
>
> dev_for_each_subnode(subnode, dev) {
> ...
>
> Does this work for you?
>
Stefan,
Yes thanks - I didn't read your original suggestion closely enough. I
have a patch I will submit.
Thanks,
Tim
[GIT PULL] xilinx patches for v2021.07-rc2
Hi Tom, please pull these changes to your tree. I can't see any issue from gitlab CI and also buildman doesn't show any problem. Key part of this series is to fix issue with gmii2rgmii bridge which ends up in a while loop on every ZynqMP board. And then usb dfu fixes with also enabling dfu functionality with efi capsule update. Also enabling saving variables based on actual bootmode. There needs to be some additional work to better locate where variables should be saved but it will require some time to do it properly. Thanks, Michal The following changes since commit 275a4490fd2f30df76f2aa07efa0f595fef4d46f: Merge branch '2021-04-22-udoo_neo-update' (2021-04-22 11:29:32 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2021.07-rc2 for you to fetch changes up to b00bad9dc81ee0337761cc50443dffa22a6cdedf: spi: zynqmp: Remove gd reference (2021-04-29 14:48:31 +0200) Xilinx changes for v2021.07-rc2 xilinx: - Enable saving variables based on bootmode - Cleanup usb dfu setup and wire it up with usb bootmode - Fix bootscript address logic - Remove GD references (spi, Versal) - Enable capsule update clk: - Small Kconfig fix net: - Fix gmii2rgmii bridge binding usb: - Propagate error (dfu gadget) Ashok Reddy Soma (2): xilinx: zynq: Add support for saving env based on bootmode xilinx: versal: Add support for saving env based on bootmode Michal Simek (10): env: Setup default value for ENV_OFFSET_REDUND xilinx: Enable redundant variable handling cmd: dfu: Propagate error if dfu gadget fails xilinx: zynqmp: Remove dfu_ram_info setup xilinx: Enable GUID partitions and EFI variable commands clk: Fix typo in Zynq Kconfig symbol description arm64: versal: Remove gd reference arm64: zynqmp: Enable capsule update net: phy: xilinx: Break while loop over ethernet phy spi: zynqmp: Remove gd reference T Karthik Reddy (5): xilinx: zynqmp: Add usb dfu/thor distro boot support xilinx: versal: Add usb dfu/thor distro boot support xilinx: zynq: Add usb dfu/thor distro boot support xilinx: Enable DFU_TIMEOUT config xilinx: common: Fix boot script address arch/arm/mach-versal/mp.c| 3 --- board/xilinx/common/board.c | 6 ++ board/xilinx/versal/board.c | 32 +++- board/xilinx/zynq/board.c| 32 board/xilinx/zynqmp/zynqmp.c | 2 +- cmd/dfu.c| 2 +- configs/microblaze-generic_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 7 +++ configs/xilinx_zynq_virt_defconfig | 7 ++- configs/xilinx_zynqmp_virt_defconfig | 14 ++ drivers/clk/Kconfig | 2 +- drivers/net/phy/phy.c| 4 ++-- drivers/spi/zynqmp_gqspi.c | 3 --- env/Kconfig | 3 ++- include/configs/syzygy_hub.h | 1 - include/configs/topic_miami.h| 1 - include/configs/xilinx_versal.h | 52 +++- include/configs/xilinx_zynqmp.h | 51 --- include/configs/zynq-common.h| 61 ++--- 19 files changed, 189 insertions(+), 95 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] spi: zynqmp: Remove gd reference
po 26. 4. 2021 v 8:28 odesílatel Michal Simek napsal:
>
> gd is not used in this file that's why doesn't make sense to declare it.
>
> Signed-off-by: Michal Simek
> ---
>
> drivers/spi/zynqmp_gqspi.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
> index 900cb2610c7f..eee8e9df0f7d 100644
> --- a/drivers/spi/zynqmp_gqspi.c
> +++ b/drivers/spi/zynqmp_gqspi.c
> @@ -10,7 +10,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> @@ -156,8 +155,6 @@ struct zynqmp_qspi_dma_regs {
> u32 dmadstmsb; /* 0x28 */
> };
>
> -DECLARE_GLOBAL_DATA_PTR;
> -
> struct zynqmp_qspi_plat {
> struct zynqmp_qspi_regs *regs;
> struct zynqmp_qspi_dma_regs *dma_regs;
> --
> 2.31.1
>
Applied.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support
Hi Green, On Thu, Apr 29, 2021 at 7:11 PM Green Wan wrote: > > Hi Bin, > > How should this patch set be proceeded? > > To summary the major changes, > - I've rebased to mainstream and merged pcie refactoring code which > based on pcie_dw_common.c > - separate unmatched dts into separated patch. > I don't have specific comments. Rick should pick this up via the riscv tree. Thanks! Regards, Bin
RE: [v1 06/17] drivers: clk: Add memory clock driver for Intel N5X device
> -Original Message-
> From: Tan, Ley Foon
> Sent: Thursday, April 8, 2021 6:32 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v1 06/17] drivers: clk: Add memory clock driver for Intel N5X
> device
>
>
>
> > -Original Message-
> > From: Lim, Elly Siew Chin
> > Sent: Wednesday, March 31, 2021 10:39 PM
> > To: u-boot@lists.denx.de
> > Cc: Marek Vasut ; Tan, Ley Foon
> > ; See, Chin Liang ;
> > Simon Goldschmidt ; Chee, Tien Fong
> > ; Westergreen, Dalon
> > ; Simon Glass ; Gan,
> > Yau Wai ; Lim, Elly Siew Chin
> >
> > Subject: [v1 06/17] drivers: clk: Add memory clock driver for Intel
> > N5X device
> >
> > Add memory clock manager driver for N5X. Provides memory clock
> > initialization and enable functions.
> >
> > Signed-off-by: Siew Chin Lim
> > ---
> > drivers/clk/altera/Makefile | 1 +
> > drivers/clk/altera/clk-mem-n5x.c | 136
> > +++
> > drivers/clk/altera/clk-mem-n5x.h | 84
> > 3 files changed, 221 insertions(+)
> > create mode 100644 drivers/clk/altera/clk-mem-n5x.c create mode
> > 100644 drivers/clk/altera/clk-mem-n5x.h
> >
> > diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
> > index
> > 38cd730685..33db092918 100644
> > --- a/drivers/clk/altera/Makefile
> > +++ b/drivers/clk/altera/Makefile
> > @@ -6,3 +6,4 @@
> > obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
> > obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
> > obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
> > diff --git a/drivers/clk/altera/clk-mem-n5x.c
> > b/drivers/clk/altera/clk-mem- n5x.c new file mode 100644 index
> > 00..ca44998641
> > --- /dev/null
> > +++ b/drivers/clk/altera/clk-mem-n5x.c
> > @@ -0,0 +1,136 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020-2021 Intel Corporation */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include "clk-mem-n5x.h"
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> Sorting the include name.
>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +struct socfpga_mem_clk_plat {
> > + void __iomem *regs;
> > +};
> > +
> > +++ b/drivers/clk/altera/clk-mem-n5x.h
> > @@ -0,0 +1,84 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2020-2021 Intel Corporation */
> > +
> > +#ifndef_CLK_MEM_N5X_
> > +#define_CLK_MEM_N5X_
> > +
> > +#ifndef __ASSEMBLY__
> > +#include
> > +#endif
> > +
> > +/* Clock Manager registers */
> > +#define MEMCLKMGR_STAT 4
> > +#define MEMCLKMGR_INTRGEN 8
> > +#define MEMCLKMGR_INTRMSK 0x0C
> For consistency, use small letter for 0x0C.
>
> > +#define MEMCLKMGR_INTRCLR 0x10
> > +#define MEMCLKMGR_INTRSTS 0x14
> > +#define MEMCLKMGR_INTRSTK 0x18
> > +#define MEMCLKMGR_INTRRAW 0x1C
> Same here.
>
>
>
> > +
> > +/* Memory Clock Manager PPL group registers */
> > +#define MEMCLKMGR_MEMPLL_EN0x20
> > +#define MEMCLKMGR_MEMPLL_ENS 0x24
> > +#define MEMCLKMGR_MEMPLL_ENR 0x28
> > +#define MEMCLKMGR_MEMPLL_BYPASS0x2c
> > +#define MEMCLKMGR_MEMPLL_BYPASSS 0x30
> > +#define MEMCLKMGR_MEMPLL_BYPASSR 0x34
> > +#define MEMCLKMGR_MEMPLL_MEMDIV0x38
> > +#define MEMCLKMGR_MEMPLL_PLLGLOB 0x3c
> > +#define MEMCLKMGR_MEMPLL_PLLCTRL 0x40
> > +#define MEMCLKMGR_MEMPLL_PLLDIV0x44
> > +#define MEMCLKMGR_MEMPLL_PLLOUTDIV 0x48
> > +#define MEMCLKMGR_MEMPLL_EXTCNTRST 0x4c
> > +
> > +#define MEMCLKMGR_CTRL_BOOTMODEBIT(0)
> > +
> > +#define MEMCLKMGR_STAT_MEMPLL_LOCKED BIT(8)
> > +
> > +#define MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK \
> > + (MEMCLKMGR_STAT_MEMPLL_LOCKED)
> > +
> > +#define MEMCLKMGR_INTER_MEMPLLLOCKED_MASK
> > 0x0001
> > +#define MEMCLKMGR_INTER_MEMPLLLOST_MASK
> > 0x0004
> > +
> > +#define MEMCLKMGR_BYPASS_MEMPLL_ALL0x1
> > +
> > +#define MEMCLKMGR_MEMDIV_MPFEDIV_OFFSET
> 0
> > +#define MEMCLKMGR_MEMDIV_APBDIV_OFFSET 4
> > +#define MEMCLKMGR_MEMDIV_DFICTRLDIV_OFFSET 8
> > +#define MEMCLKMGR_MEMDIV_DFIDIV_OFFSET 12
> > +#define MEMCLKMGR_MEMDIV_DFICTRLDIV_MASK 0x1
> > +#define MEMCLKMGR_MEMDIV_DIVIDER_MASK 0x3
> > +
> > +#define MEMCLKMGR_PLLGLOB_PSRC_MASK
> > GENMASK(17, 16)
> >
RE: [v1 04/17] drivers: clk: Add clock driver for Intel N5X device
> -Original Message-
> From: Tan, Ley Foon
> Sent: Monday, April 5, 2021 3:37 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v1 04/17] drivers: clk: Add clock driver for Intel N5X device
>
>
>
> > -Original Message-
> > From: Lim, Elly Siew Chin
> > Sent: Wednesday, March 31, 2021 10:39 PM
> > To: u-boot@lists.denx.de
> > Cc: Marek Vasut ; Tan, Ley Foon
> > ; See, Chin Liang ;
> > Simon Goldschmidt ; Chee, Tien Fong
> > ; Westergreen, Dalon
> > ; Simon Glass ; Gan,
> > Yau Wai ; Lim, Elly Siew Chin
> >
> > Subject: [v1 04/17] drivers: clk: Add clock driver for Intel N5X
> > device
> >
> > Add clock manager driver for N5X. Provides clock initialization and
> > get_rate functions.
> >
> > Signed-off-by: Siew Chin Lim
> > ---
> > drivers/clk/altera/Makefile | 3 +-
> > drivers/clk/altera/clk-n5x.c | 489
> > ++
> > drivers/clk/altera/clk-n5x.h | 217 +++
> > include/dt-bindings/clock/n5x-clock.h | 71 +
> > 4 files changed, 779 insertions(+), 1 deletion(-) create mode 100644
> > drivers/clk/altera/clk-n5x.c create mode 100644
> > drivers/clk/altera/clk-n5x.h create mode 100644
> > include/dt-bindings/clock/n5x-clock.h
> >
> > diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
> > index
> > 96215ad5c4..38cd730685 100644
> > --- a/drivers/clk/altera/Makefile
> > +++ b/drivers/clk/altera/Makefile
> > @@ -1,7 +1,8 @@
> > # SPDX-License-Identifier: GPL-2.0+
> > #
> > -# Copyright (C) 2018 Marek Vasut
> > +# Copyright (C) 2018-2021 Marek Vasut
> > #
> >
> > obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
> > obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
> > diff --git a/drivers/clk/altera/clk-n5x.c
> > b/drivers/clk/altera/clk-n5x.c new file mode 100644 index
> > 00..12e6aa9ac2
> > --- /dev/null
> > +++ b/drivers/clk/altera/clk-n5x.c
> > @@ -0,0 +1,489 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020-2021 Intel Corporation */
> > +
> > +#include
>
> Sorting the include name.
>
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
>
> [...]
>
>
> > +
> > + /* Take all PLLs out of bypass */
> > + clk_write_bypass_mainpll(plat, 0);
> > + clk_write_bypass_perpll(plat, 0);
> > +
> > + /* Clear the loss of lock bits (write 1 to clear) */
> > + CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
> > + CLKMGR_INTER_PERPLLLOST_MASK |
> > + CLKMGR_INTER_MAINPLLLOST_MASK);
> Comment "write 1 to clear" is valid?
>
> > +
> > + /* Take all ping pong counters out of reset */
> > + CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
> > + CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK);
> > +
> > + /* Out of boot mode */
> > + clk_write_ctrl(plat,
> > + CM_REG_READL(plat, CLKMGR_CTRL) &
> > ~CLKMGR_CTRL_BOOTMODE); }
> > +
> > +static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u32
> > +reg) {
> > + u32 clksrc = CM_REG_READL(plat, reg);
> > +
> > + return (clksrc & CLKMGR_CLKSRC_MASK) >>
> > CLKMGR_CLKSRC_OFFSET; }
> > +
> > +static u64 clk_get_pll_output_hz(struct socfpga_clk_plat *plat,
> > +u32 pllglob_reg, u32 plldiv_reg) {
> > + u64 clock = 0;
> > + u32 clklsrc, divf, divr, divq, power = 1;
> > +
> > + /* Get input clock frequency */
> > + clklsrc = (CM_REG_READL(plat, pllglob_reg) &
> Redundant () can be removed. Same for other code in this source file.
>
> > + CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
> > + CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
> > +
> > + switch (clklsrc) {
> > + case CLKMGR_VCO_PSRC_EOSC1:
> > + clock = cm_get_osc_clk_hz();
> > + break;
> > + case CLKMGR_VCO_PSRC_INTOSC:
> > + clock = cm_get_intosc_clk_hz();
> > + break;
> > + case CLKMGR_VCO_PSRC_F2S:
> > + clock = cm_get_fpga_clk_hz();
> > + break;
> > + }
> > +
>
> Regards
> Ley Foon
Noted, I will update in next review.
Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support
Hi Bin, How should this patch set be proceeded? To summary the major changes, - I've rebased to mainstream and merged pcie refactoring code which based on pcie_dw_common.c - separate unmatched dts into separated patch. Thanks, - Green On Thu, Apr 22, 2021 at 5:13 PM Green Wan wrote: > > This patch set is to add SiFive fu740 chip and HiFive Unmatched board > support. Patches are split into several parts: > > - [PATCH v7 1/8] support for fu740 cpu > - [PATCH v7 2/8] support for fu740 clk driver > - [PATCH v7 3/8] rename and support for fu740 ram driver > - [PATCH v7 4/8] add pcie driver > - [PATCH v7 5/8] dts for SiFive fu740 > - [PATCH v7 6/8] dts for SiFive Unmatched board > - [PATCH v7 7/8] add Unmatched board support > - [PATCH v7 8/8] add fu740 support to macb driver > > Description > > - For fu740 cpu support, reuse most of fu540 cpu. > - For prci driver, add one abstract layer to separate fu540 and > fu740. Move orignal fu540 code to separate files. > - For pcie driver, it depends on gpio, prci, clk and reset drivers > to do init works. Also based on pcie_dw_common.c > - Align with Linux DT file. > > Tests and patch checks > > - Able to boot both unmatched and unleashed boards. > - PCIe tests > . M.2 NVMe SSD > . e1000 compatibale ethernet adapter (ping) > . pci-to-usb adapter(usb mass storage) > - checkpatch is performed. To keep code derived from other boards > the same, ignore some warnings/errors in [PATCH 7/8]. > > Changlogs > - V7 > . Rebase to latest master branch > . Moved dts for fu740 patch [v6 1/7] to [v7 5/8] and seperate dts of > Unmatched board from [v6 6/7] into [v7 6/8] > . Applied PCIe refactoring patch to base on the common code in > pcie_dw_common.c > - V6 > . Remove redundant DT string for 1.2GHz CPU clock and squash to > [1/7] > - V5 > . Fix unleashed build error in patch [6/8] > . Append one more set for 1.2GHz CPU speed > . Add "#include " back to sifive_ddr.c > . Add Reviewed-by to [4/8] and [7/8] > - V4 > . fixed incorrect file name in ./board/sifive/unmatched/Makefile > . fixed link in doc/board/sifive/index.rst, passed 'make htmldocs' > - V3 > . Rebase to unleashed rename v2 patch > . Rename > doc/board/sifive/unmatched.rst > board/sifive/unmatched/unmatched.c > . Fix tail whitespace > . Add 'git mv' info to ram driver and merge patch back to one > . Add comment to macb driver for PLL hardware quirk > . Add reviewed-by to patch [6/7] > . Add 'gpio-poweroff' node for upcoming opensbi integration > - V2 > . Rebase to unleashed rename patch > . remove unnessaary fu540 changes > . split ram driver patch into 2 to keep 'git mv' info > . use a shorter name for unmatched support > . Remove redundant temperature-sensor in DT > . Remove unnecessary USB EHCI & OHCI from defconfig > . Revised fu740 doc > . Fixed year of copyright > . Add reviewed-by received in v1 patch > > David Abdurachmanov (1): > drivers: net: macb: add fu740 support > > Green Wan (7): > riscv: cpu: fu740: Add support for cpu fu740 > drivers: clk: add fu740 support > drivers: ram: sifive: rename fu540_ddr and add fu740 support > drivers: pci: add pcie support for fu740 > riscv: dts: add fu740 support > riscv: dts: add SiFive Unmatched board support > board: sifive: add HiFive Unmatched board support > > arch/riscv/Kconfig|5 + > arch/riscv/cpu/fu740/Kconfig | 37 + > arch/riscv/cpu/fu740/Makefile | 12 + > arch/riscv/cpu/fu740/cache.c | 55 + > arch/riscv/cpu/fu740/cpu.c| 22 + > arch/riscv/cpu/fu740/dram.c | 38 + > arch/riscv/cpu/fu740/spl.c| 23 + > arch/riscv/dts/Makefile |1 + > arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++ > arch/riscv/dts/fu740-c000.dtsi| 329 > .../dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 + > .../dts/hifive-unmatched-a00-u-boot.dtsi | 40 + > arch/riscv/dts/hifive-unmatched-a00.dts | 259 +++ > arch/riscv/include/asm/arch-fu740/cache.h | 14 + > arch/riscv/include/asm/arch-fu740/clk.h | 14 + > arch/riscv/include/asm/arch-fu740/gpio.h | 38 + > arch/riscv/include/asm/arch-fu740/reset.h | 13 + > arch/riscv/include/asm/arch-fu740/spl.h | 14 + > arch/riscv/lib/sifive_clint.c |1 - > board/sifive/unleashed/Kconfig|1 + > board/sifive/unmatched/Kconfig| 50 + > board/sifive/unmatched/MAINTAINERS|9 + > board/sifive/unmatched/Makefile |9 + > board/sifive/unmatched/spl.c | 85 + > board/sifive/unmatched/unmatched.c| 24 + > common/spl/Kconfig|
Re: [Patch v2 1/2] clk: zynq: Add clock wizard driver
On 4/29/21 11:31 AM, Zhengxun Li wrote:
> The Clocking Wizard IP supports clock circuits customized
> to your clocking requirements. The wizard support for
> dynamically reconfiguring the clocking primitives for
> Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
>
> Limited by uboot clk uclass without set_phase API, this
> patch only provides set_rate to modify the frequency.
>
> Signed-off-by: Zhengxun Li
> ---
> drivers/clk/Kconfig | 9 +++
> drivers/clk/Makefile| 1 +
> drivers/clk/clk-xlnx-clock-wizard.c | 152
>
> 3 files changed, 162 insertions(+)
> create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 4aeaa0c..f0d4fe0 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -136,6 +136,15 @@ config CLK_ZYNQMP
> This clock driver adds support for clock realted settings for
> ZynqMP platform.
>
> +config COMMON_CLK_XLNX_CLKWZRD
> + bool "Xilinx Clocking Wizard"
> + depends on CLK
> + help
> + Support for the Xilinx Clocking Wizard IP core clock generator.
> + Adds support for clocking wizard and compatible.
> + This driver supports the Xilinx clocking wizard programmable clock
> + synthesizer.
> +
> config CLK_STM32MP1
> bool "Enable RCC clock driver for STM32MP1"
> depends on ARCH_STM32MP && CLK
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 645709b..f4ddbe8 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
> obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
> obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
> obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
> +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
> obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
> obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
> obj-$(CONFIG_SANDBOX) += clk_sandbox.o
> diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
> b/drivers/clk/clk-xlnx-clock-wizard.c
> new file mode 100644
> index 000..55adb16
> --- /dev/null
> +++ b/drivers/clk/clk-xlnx-clock-wizard.c
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx 'Clocking Wizard' driver
> + *
> + * Copyright (c) 2021 Macronix Inc.
> + *
> + * Author: Zhengxun Li
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define SRR 0x0
> +
> +#define SR 0x4
> +#define SR_LOCKEDBIT(0)
> +
> +#define CCR(x) (0x200 + ((x) * 4))
> +
> +#define FBOUT_CFGCCR(0)
> +#define FBOUT_DIV(x) (x)
> +#define FBOUT_GET_DIV(x) ((x) & GENMASK(7, 0))
> +#define FBOUT_MUL(x) ((x) << 8)
> +#define FBOUT_GET_MUL(x) (((x) & GENMASK(15, 8)) >> 8)
> +#define FBOUT_FRAC(x)((x) << 16)
> +#define FBOUT_GET_FRAC(x)(((x) & GENMASK(25, 16)) >> 16)
> +#define FBOUT_FRAC_ENBIT(26)
> +
> +#define FBOUT_PHASE CCR(1)
> +
> +#define OUT_CFG(x) CCR(2 + ((x) * 3))
> +#define OUT_DIV(x) (x)
> +#define OUT_GET_DIV(x) ((x) & GENMASK(7, 0))
> +#define OUT_FRAC(x) ((x) << 8)
> +#define OUT_GET_FRAC(x) (((x) & GENMASK(17, 8)) >> 8)
> +#define OUT_FRAC_EN BIT(18)
> +
> +#define OUT_PHASE(x) CCR(3 + ((x) * 3))
> +#define OUT_DUTY(x) CCR(4 + ((x) * 3))
> +
> +#define CTRL CCR(23)
> +#define CTRL_SEN BIT(2)
> +#define CTRL_SADDR BIT(1)
> +#define CTRL_LOADBIT(0)
> +
> +/*
/**
> + * struct clkwzrd - Clock wizard private data structure
> + *
> + * @lock Lock pointer
not listed below
> + * @base Memory base
missing :
> + * @vco_clk voltage-controlled oscillator frequency
missing :
> + */
> +struct clkwzd {
> + void __iomem *base;
> + u64 vco_clk;
> +};
> +
> +static int clk_wzrd_enable(struct clk *clk)
> +{
> + struct clkwzd *priv = dev_get_priv(clk->dev);
> + int ret;
> + u32 val;
> +
> + ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED,
> +1, 100);
> + if (!ret) {
> + writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL);
> + writel(CTRL_SADDR, priv->base + CTRL);
> + ret = readl_poll_sleep_timeout(priv->base + SR, val,
> +val & SR_LOCKED, 1, 100);
> + }
> +
> + return ret;
> +}
> +
> +static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)
> +{
> + struct clkwzd *priv = dev_get_priv(clk->dev);
> + u64 div;
> + u32 cfg;
> +
> + /* Get output clock divide value */
> + div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate);
> + if (div < 1000 || div > 255999)
> + return -EINVAL;
> +
> + cfg = OUT_DIV((u32)div /
Re: [Patch v2 2/2] board: Add Zynq Mxic picozed development board support
On 4/29/21 11:31 AM, Zhengxun Li wrote:
> Add the Zynq Mxic picozed development board support.
>
> Signed-off-by: Zhengxun Li
> ---
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/zynq-mxic-picozed.dts | 72
> ++
> 2 files changed, 74 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 1dd6c4b..b5addc4 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -287,7 +287,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
> zynq-zturn.dtb \
> zynq-zturn-v5.dtb \
> zynq-zybo.dtb \
> - zynq-zybo-z7.dtb
> + zynq-zybo-z7.dtb \
> + zynq-mxic-picozed.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP) += \
> avnet-ultra96-rev1.dtb \
> avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb\
> diff --git a/arch/arm/dts/zynq-mxic-picozed.dts
> b/arch/arm/dts/zynq-mxic-picozed.dts
> new file mode 100644
> index 000..1f24ca1
> --- /dev/null
> +++ b/arch/arm/dts/zynq-mxic-picozed.dts
> @@ -0,0 +1,72 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Macronix Inc.
> + *
> + * Author: Zhengxun Li
> + */
> +
> +/dts-v1/;
> +/include/ "zynq-7000.dtsi"
> +
> +/ {
> + model = "Zynq MXIC PicoZed Development Board";
> + compatible = "mxicy,zynq-mxic-picozed", "xlnx,zynq-7000";
> +
> + aliases {
> + ethernet0 =
> + serial0 =
> + spi0 = _controller;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x3000>;
> + };
> +
> + chosen {
> + bootargs = "";
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> + {
> + clkwizard: clkwizard@43c2 {
> + compatible = "xlnx,clk-wizard-5.1";
> + reg = <0x43c2 0x1>;
> + clocks = < 18>, < 18>;
> + clock-names = "aclk", "clk_in1";
> + #clock-cells = <1>;
> + clock-frequency = <13330>;
> + };
> +
> + spi_controller: spi@43c3 {
> + compatible = "mxicy,mx25f0a-spi";
> + reg = <0x43c3 0x1>;
> + reg-names = "regs";
> + clocks = < 0>, < 1>, < 18>;
> + clock-names = "send_clk", "send_dly_clk", "ps_clk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <2500>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> + };
> +};
> +
> + {
> + ps-clk-frequency = <>;
> +};
> +
> + {
> + status = "okay";
> + phy-mode = "rgmii-id";
> +};
> +
> + {
> + status = "okay";
> +};
>
As I said this is clear NACK. Description for PL is not acceptable.
Thanks,
Michal
[PATCH 2/2] MAINTAINERS: Add an entry for VirtIO
This was missed when VirtIO support was initially brought to U-Boot back in 2018. Add an entry for it and list myself as the maintainer. Signed-off-by: Bin Meng --- MAINTAINERS | 12 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2d267aeff2..20092cb367 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1171,6 +1171,18 @@ F: common/lcd*.c F: include/lcd*.h F: include/video*.h +VirtIO +M: Bin Meng +S: Maintained +F: drivers/virtio/ +F: cmd/virtio.c +F: include/config/virtio/ +F: include/config/virtio.h +F: include/config/cmd/virtio.h +F: include/virtio*.h +F: test/dm/virtio.c +F: doc/develop/driver-model/virtio.rst + X86 M: Simon Glass M: Bin Meng -- 2.25.1
[PATCH 1/2] doc: develop: Convert README.virtio to reST
This convers the existing README.virtio to reST, and puts it under
the develop/driver-model/ directory.
Signed-off-by: Bin Meng
---
doc/develop/driver-model/index.rst| 1 +
.../driver-model/virtio.rst} | 90 +--
2 files changed, 63 insertions(+), 28 deletions(-)
rename doc/{README.virtio => develop/driver-model/virtio.rst} (86%)
diff --git a/doc/develop/driver-model/index.rst
b/doc/develop/driver-model/index.rst
index fd4575db9b..10a76256b0 100644
--- a/doc/develop/driver-model/index.rst
+++ b/doc/develop/driver-model/index.rst
@@ -27,3 +27,4 @@ subsystems
soc-framework
spi-howto
usb-info
+ virtio
diff --git a/doc/README.virtio b/doc/develop/driver-model/virtio.rst
similarity index 86%
rename from doc/README.virtio
rename to doc/develop/driver-model/virtio.rst
index d3652f2e2f..8ac9c94caf 100644
--- a/doc/README.virtio
+++ b/doc/develop/driver-model/virtio.rst
@@ -1,11 +1,10 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018, Bin Meng
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng
VirtIO Support
==
-This document describes the information about U-Boot support for VirtIO [1]
+This document describes the information about U-Boot support for VirtIO_
devices, including supported boards, build instructions, driver details etc.
What's VirtIO?
@@ -15,7 +14,7 @@ just the guest's device driver "knows" it is running in a
virtual environment,
and cooperates with the hypervisor. This enables guests to get high performance
network and disk operations, and gives most of the performance benefits of
paravirtualization. In the U-Boot case, the guest is U-Boot itself, while the
-virtual environment are normally QEMU [2] targets like ARM, RISC-V and x86.
+virtual environment are normally QEMU_ targets like ARM, RISC-V and x86.
Status
--
@@ -49,6 +48,8 @@ Building U-Boot for pre-configured QEMU targets is no
different from others.
For example, we can do the following with the CROSS_COMPILE environment
variable being properly set to a working toolchain for ARM:
+.. code-block:: bash
+
$ make qemu_arm_defconfig
$ make
@@ -56,11 +57,13 @@ You can even create a QEMU ARM target with VirtIO devices
showing up on both
MMIO and PCI buses. In this case, you can enable the PCI transport driver
from 'make menuconfig':
-Device Drivers --->
- ...
- VirtIO Drivers --->
- ...
- [*] PCI driver for virtio devices
+.. code-block:: none
+
+ Device Drivers --->
+ ...
+ VirtIO Drivers --->
+ ...
+ [*] PCI driver for virtio devices
Other drivers are at the same location and can be tuned to suit the needs.
@@ -74,6 +77,8 @@ Testing
The following QEMU command line is used to get U-Boot up and running with
VirtIO net and block devices on ARM.
+.. code-block:: bash
+
$ qemu-system-arm -nographic -machine virt -bios u-boot.bin \
-netdev tap,ifname=tap0,id=net0 \
-device virtio-net-device,netdev=net0 \
@@ -82,6 +87,8 @@ VirtIO net and block devices on ARM.
On x86, command is slightly different to create PCI VirtIO devices.
+.. code-block:: bash
+
$ qemu-system-i386 -nographic -bios u-boot.rom \
-netdev tap,ifname=tap0,id=net0 \
-device virtio-net-pci,netdev=net0 \
@@ -93,6 +100,8 @@ parameters. It is also possible to specify both MMIO and PCI
VirtIO devices.
For example, the following commnad creates 3 VirtIO devices, with 1 on MMIO
and 2 on PCI bus.
+.. code-block:: bash
+
$ qemu-system-arm -nographic -machine virt -bios u-boot.bin \
-netdev tap,ifname=tap0,id=net0 \
-device virtio-net-pci,netdev=net0 \
@@ -104,6 +113,8 @@ and 2 on PCI bus.
By default QEMU creates VirtIO legacy devices by default. To create non-legacy
(aka modern) devices, pass additional device property/value pairs like below:
+.. code-block:: bash
+
$ qemu-system-i386 -nographic -bios u-boot.rom \
-netdev tap,ifname=tap0,id=net0 \
-device
virtio-net-pci,netdev=net0,disable-legacy=true,disable-modern=false \
@@ -112,6 +123,8 @@ By default QEMU creates VirtIO legacy devices by default.
To create non-legacy
A 'virtio' command is provided in U-Boot shell.
+.. code-block:: none
+
=> virtio
virtio - virtio block devices sub-system
@@ -127,10 +140,14 @@ A 'virtio' command is provided in U-Boot shell.
To probe all the VirtIO devices, type:
+.. code-block:: none
+
=> virtio scan
Then we can show the connected block device details by:
+.. code-block:: none
+
=> virtio info
Device 0: QEMU VirtIO Block Device
Type: Hard Disk
@@ -138,6 +155,8 @@ Then we can show the connected block device details by:
And list the directories and files on the disk by:
+.. code-block:: none
+
=> ls virtio 0 /
4096 .
4096 ..
@@ -167,6 +186,8 @@ Driver Internals
There are 3 level of drivers in the VirtIO driver
Re: [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
Hi Marek, (Added Tom and Simon to Cc) On 29.04.21 10:27, Marek Behun wrote: On Thu, 29 Apr 2021 08:46:36 +0200 Stefan Roese wrote: phy: marvell: add RX training command Applied to u-boot-marvell/master Thanks, Stefan Stefan, do you think it would make sense to at least create a special mechanism for these platform commands? For example via a top-level command "plat", i.e. instead of > rx_training params we would call > plat rx_training params The plat command could list all registered platform specific commands... Not sure. If you want to split it up, then we would perhaps also need to add a mechanism for board specific commands as well. E.g. for commands not common for a platform but only for specific boards. My feeling is that this makes things overly complex. And I also don't see a real problem with the current "flat" structure of these commands being "global". Again, I mention the many already existing board and platform specific commands in current mainline. Perhaps other people can comment on this use / introduction of platform specific U-Boot commands? BTW: Again, we can definitely rename this specific "rx_training" command, if you feel this is absolutely misleading. IIRC, then I already made a suggestion for this. Thanks, Stefan
Re: [PATCH] arm64: zynqmp: Enable capsule update
On 4/29/21 10:52 AM, Heinrich Schuchardt wrote: > On 26.04.21 13:08, Michal Simek wrote: >> Enable EFI capsule update features to be enabled by default also with all >> dfu valid options for ZynqMP. >> >> This feature was tested on Xilinx ZynqMP zcu104 board with defining >> dfu_alt_info="mmc 0:1=boot.bin fat 0 1;u-boot.itb fat 0 1" >> and >> dfu_alt_info="sf 0:0=boot.bin raw 0 0x5;u-boot.itb raw 0x8 >> 0x50". >> >> There is a need to increase malloc size for getting dfu mmc to work. >> >> Signed-off-by: Michal Simek >> CC: Sughosh Ganu >> CC: Ilias Apalodimas >> CC: Heinrich Schuchardt >> --- >> >> I actually didn't try to boot out of qspi because qspi writing is likely >> broken and should be fixed. But I have checked that images are written to >> that previously erased locations. > > There is a DFU driver for writing to RAM. You should be able to write to > memory using capsule update and then do a CRC32 on the memory region for > testing the correct result. That's a good point. As I said to Ilias and Sughosh I think it will be good to list all dfu_alt_info setting and these testing procedures to be able to test them quickly. The same is when runtime service is working how to use it with fwupd. Ilias also mentioned work in progress on A/B update which I would like to enable when it is ready. Thanks, Michal
Re: [PATCH] arm64: zynqmp: Enable capsule update
On 26.04.21 13:08, Michal Simek wrote: > Enable EFI capsule update features to be enabled by default also with all > dfu valid options for ZynqMP. > > This feature was tested on Xilinx ZynqMP zcu104 board with defining > dfu_alt_info="mmc 0:1=boot.bin fat 0 1;u-boot.itb fat 0 1" > and > dfu_alt_info="sf 0:0=boot.bin raw 0 0x5;u-boot.itb raw 0x8 > 0x50". > > There is a need to increase malloc size for getting dfu mmc to work. > > Signed-off-by: Michal Simek > CC: Sughosh Ganu > CC: Ilias Apalodimas > CC: Heinrich Schuchardt > --- > > I actually didn't try to boot out of qspi because qspi writing is likely > broken and should be fixed. But I have checked that images are written to > that previously erased locations. There is a DFU driver for writing to RAM. You should be able to write to memory using capsule update and then do a CRC32 on the memory region for testing the correct result. Best regards Heinrich > > U-Boot SPL 2021.04-00978-g76a8101e4548 (Apr 26 2021 - 13:01:46 +0200) > PMUFW:v1.1 > Loading new PMUFW cfg obj (2024 bytes) > Silicon version: 3 > EL Level: EL3 > Chip ID: zu7e > Multiboot:0 > Trying to boot from MMC2 > spl: could not initialize mmc. error: -19 > Trying to boot from MMC1 > spl_load_image_fat_os: error reading image u-boot.bin, err - -2 > NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000 > NOTICE: BL31: v2.2(release):xilinx-v2020.2.2-k26 > NOTICE: BL31: Built : 11:51:16, Apr 21 2021 > > U-Boot 2021.04-00978-g76a8101e4548 (Apr 26 2021 - 13:01:46 +0200) > > Model: ZynqMP ZCU104 RevC > Board: Xilinx ZynqMP > DRAM: 2 GiB > PMUFW:v1.1 > EL Level: EL2 > Chip ID: zu7e > WDT: Started with servicing (60s timeout) > NAND: 0 MiB > MMC: mmc@ff17: 0 > Loading Environment from FAT... OK > In:serial > Out: serial > Err: serial > Net: > ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id > eth0: ethernet@ff0e > Scanning disk m...@ff17.blk... > Found 4 disks > ##Hit any key to stop autoboot: 0 > ZynqMP> reset > resetting ... > > U-Boot SPL 2021.04-00978-g01e9f0ec63e4 (Apr 26 2021 - 13:04:48 +0200) > PMUFW:v1.1 > Loading new PMUFW cfg obj (2024 bytes) > Silicon version: 3 > EL Level: EL3 > Chip ID: zu7e > Multiboot:0 > Trying to boot from MMC2 > spl: could not initialize mmc. error: -19 > Trying to boot from MMC1 > spl_load_image_fat_os: error reading image u-boot.bin, err - -2 > NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000 > NOTICE: BL31: v2.2(release):xilinx-v2020.2.2-k26 > NOTICE: BL31: Built : 11:51:16, Apr 21 2021 > > U-Boot 2021.04-00978-g01e9f0ec63e4 (Apr 26 2021 - 13:04:48 +0200) > > Model: ZynqMP ZCU104 RevC > Board: Xilinx ZynqMP > DRAM: 2 GiB > PMUFW:v1.1 > EL Level: EL2 > Chip ID: zu7e > WDT: Started with servicing (60s timeout) > NAND: 0 MiB > MMC: mmc@ff17: 0 > Loading Environment from FAT... OK > In:serial > Out: serial > Err: serial > Net: > ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id > eth0: ethernet@ff0e > Scanning disk m...@ff17.blk... > Found 4 disks > Hit any key to stop autoboot: 0 > ZynqMP> > > --- > configs/xilinx_zynqmp_virt_defconfig | 9 + > include/configs/xilinx_zynqmp.h | 2 +- > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/configs/xilinx_zynqmp_virt_defconfig > b/configs/xilinx_zynqmp_virt_defconfig > index 89c1dae2a1d9..9c496098584f 100644 > --- a/configs/xilinx_zynqmp_virt_defconfig > +++ b/configs/xilinx_zynqmp_virt_defconfig > @@ -86,7 +86,11 @@ CONFIG_SATA_CEVA=y > CONFIG_CLK_ZYNQMP=y > CONFIG_DFU_TFTP=y > CONFIG_DFU_TIMEOUT=y > +CONFIG_DFU_MMC=y > +CONFIG_DFU_NAND=y > CONFIG_DFU_RAM=y > +CONFIG_DFU_SF=y > +CONFIG_DFU_MTD=y > CONFIG_USB_FUNCTION_FASTBOOT=y > CONFIG_FASTBOOT_FLASH=y > CONFIG_FASTBOOT_FLASH_MMC_DEV=0 > @@ -178,3 +182,8 @@ CONFIG_TPM=y > CONFIG_SPL_GZIP=y > # CONFIG_SPL_HEXDUMP is not set > CONFIG_OF_LIBFDT_OVERLAY=y > +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y > +CONFIG_EFI_CAPSULE_ON_DISK=y > +CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y > +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y > +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y > diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h > index 36f3d962e417..986af2be7819 100644 > --- a/include/configs/xilinx_zynqmp.h > +++ b/include/configs/xilinx_zynqmp.h > @@ -27,7 +27,7 @@ > #endif > > /* Size of malloc() pool */ > -#define CONFIG_SYS_MALLOC_LEN(CONFIG_ENV_SIZE + 0x200) > +#define CONFIG_SYS_MALLOC_LEN(CONFIG_ENV_SIZE + 0x400) > > /* Serial setup */ > #define CONFIG_CPU_ARMV8 >
Please pull u-boot-cfi-flash/master
Hi Tom, please pull the following cfi-flash related patches: - mtd: cfi: Fix PPB lock status readout (Marek) Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=84=results Thanks, Stefan The following changes since commit 79b0f08d6af498e6fda8cd257d62e2095764410c: configs: Resync with savedefconfig (2021-04-27 08:28:38 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-cfi-flash.git for you to fetch changes up to 94657482f3fb64de124cc68b14c869a6836eaaf3: mtd: cfi: Fix PPB lock status readout (2021-04-28 10:29:36 +0200) Marek Vasut (1): mtd: cfi: Fix PPB lock status readout drivers/mtd/cfi_flash.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-)
Re: [PATCH] mtd: cfi: Fix PPB lock status readout
On 11.04.21 20:47, Marek Vasut wrote:
According to S26KL512S datasheet [1] and S29GL01GS datasheet [2],
the procedure to read out PPB lock bits is to send the PPB Entry,
PPB Read, Reset/ASO Exit. Currently, the code does send incorrect
PPB Entry, PPB Read and Reset/ASO Exit is completely missing.
The PPB Entry sent is implemented by sending flash_unlock_seq()
and flash_write_cmd(..., FLASH_CMD_READ_ID). This translates to
sequence 0x555:0xaa, 0x2aa:0x55, 0x555:0x90=FLASH_CMD_READ_ID.
However, both [1] and [2] specify the last byte of PPB Entry as
0xc0=AMD_CMD_SET_PPB_ENTRY instead of 0x90=FLASH_CMD_READ_ID,
that is 0x555:0xaa, 0x2aa:0x55, 0x555:0xc0=AMD_CMD_SET_PPB_ENTRY.
Since this does make sense, this patch fixes it and thus also
aligns the code in flash_get_size() with flash_real_protect().
The PPB Read returns 00h in case of Protected state and 01h in case
of Unprotected state, according to [1] Note 83 and [2] Note 17, so
invert the result. Moreover, align the arguments with similar code
in flash_real_protect().
Finally, Reset/ASO Exit command should be executed to exit the PPB
mode, so add the missing reset.
[1] https://www.cypress.com/file/213346/download
Document Number: 001-99198 Rev. *M
Table 40. Command Definitions, Nonvolatile Sector Protection
Command Set Definitions
[2] https://www.cypress.com/file/177976/download
Document Number: 001-98285 Rev. *R
Table 7.1 Command Definitions, Nonvolatile Sector Protection
Command Set Definitions
Fixes: 03deff433e ("cfi_flash: Read PPB sector protection from device for
AMD/Spansion chips")
Signed-off-by: Marek Vasut
Cc: Stefan Roese
Applied to u-boot-cfi-flash/master
Thanks,
Stefan
---
drivers/mtd/cfi_flash.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 9642d7c7dc..9c27fea5d8 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2276,12 +2276,12 @@ ulong flash_get_size(phys_addr_t base, int banknum)
flash_unlock_seq(info, 0);
flash_write_cmd(info, 0,
info->addr_unlock1,
- FLASH_CMD_READ_ID);
+ AMD_CMD_SET_PPB_ENTRY);
info->protect[sect_cnt] =
- flash_isset(
- info, sect_cnt,
- FLASH_OFFSET_PROTECT,
- FLASH_STATUS_PROTECT);
+ !flash_isset(info, sect_cnt,
+0, 0x01);
+ flash_write_cmd(info, 0, 0,
+ info->cmd_reset);
break;
default:
/* default: not protected */
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
On Thu, 29 Apr 2021 08:46:36 +0200 Stefan Roese wrote: > >phy: marvell: add RX training command > > Applied to u-boot-marvell/master > > Thanks, > Stefan Stefan, do you think it would make sense to at least create a special mechanism for these platform commands? For example via a top-level command "plat", i.e. instead of > rx_training params we would call > plat rx_training params The plat command could list all registered platform specific commands... Marek
Re: [PATCH] net: phy: xilinx: Break while loop over ethernet phy
Hi Bin,
On 4/28/21 6:36 PM, Bin Meng wrote:
> Hi Michal,
>
> On Thu, Apr 29, 2021 at 12:17 AM Michal Simek wrote:
>>
>> Hi Bin,
>>
>> On 4/28/21 5:57 PM, Bin Meng wrote:
>>> Hi Michal,
>>>
>>> On Wed, Apr 28, 2021 at 11:03 PM Michal Simek
>>> wrote:
Hi Bin,
On 4/28/21 4:37 PM, Bin Meng wrote:
> Hi Michal,
>
> On Tue, Apr 27, 2021 at 7:22 PM Michal Simek
> wrote:
>>
>> Hi Bin,
>>
>> On 4/27/21 7:17 AM, Bin Meng wrote:
>>> Hi Michal,
>>>
>>> On Mon, Apr 26, 2021 at 8:31 PM Michal Simek
>>> wrote:
The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF
tree") change driver behavior to while loop which wasn't correct
because
the driver was looping over again and again. The reason was that
ofnode_valid() is taking 0 as correct value.
>>>
>>> I am still trying to understand the problem. The changes in
>>> 6c993815bbea sound correct from an fdtdec <=> OF API mapping
>>> perspective. If the new OF API does not work, the old fdtdec may fail
>>> too. Could you please explain a little bit?
>>
>> here is behavior of origin code.
>>
>> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
>> phy_connect_gmii2rgmii sn 11348
>> phy_connect_gmii2rgmii 1off -1
>> phy_connect_gmii2rgmii 2off -1
>> phy_connect_gmii2rgmii sn2 11752
>> phy_connect_gmii2rgmii 1off -1
>> phy_connect_gmii2rgmii 2off -1
>> phy_connect_gmii2rgmii sn2 -1
>> phy_connect_gmii2rgmii phydev
>> eth0: ethernet@ff0e
>> Scanning disk m...@ff17.blk...
>> Found 4 disks
>> Hit any key to stop autoboot: 0
>> ZynqMP>
>>
>>
>> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
>> index 89e3076bfd25..d0960d93ae08 100644
>> --- a/drivers/net/phy/phy.c
>> +++ b/drivers/net/phy/phy.c
>> @@ -956,22 +956,28 @@ static struct phy_device
>> *phy_connect_gmii2rgmii(struct mii_dev *bus,
>> int sn = dev_of_offset(dev);
>> int off;
>>
>> + printf("%s sn %d\n", __func__, sn);
>> while (sn > 0) {
>> off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
>>
>> "xlnx,gmii-to-rgmii-1.0");
>> + printf("%s 1off %d\n", __func__, off);
>> if (off > 0) {
>> phydev = phy_device_create(bus, off,
>>PHY_GMII2RGMII_ID,
>> false,
>>interface);
>> break;
>> }
>> - if (off == -FDT_ERR_NOTFOUND)
>> + printf("%s 2off %d\n", __func__, off);
>> +
>> + if (off == -FDT_ERR_NOTFOUND) {
>> sn = fdt_first_subnode(gd->fdt_blob, sn);
>> - else
>> + printf("%s sn2 %d\n", __func__, sn);
>> + } else
>> printf("%s: Error finding compat string:%d\n",
>>__func__, off);
>> }
>>
>> + printf("%s phydev %p\n", __func__, phydev);
>> return phydev;
>> }
>> #endif
>>
>>
>> With latest code and some prints
>> ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 2952
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> phy_connect_gmii2rgmii 1valid 1 ethernet@ff0e
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> ofnode_valid: node.of_offset 11348
>> phy_connect_gmii2rgmii 2valid 1 ethernet@ff0e
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset 0
>> ofnode_valid: node.of_offset 0
>> phy_connect_gmii2rgmii 3valid 1
>> ofnode_valid: node.of_offset 0
>> ofnode_valid: node.of_offset 0
>> ofnode_valid: node.of_offset 0
>> phy_connect_gmii2rgmii 2valid 1
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset -1
>> ofnode_valid: node.of_offset 0
>> ofnode_valid: node.of_offset 0
>> phy_connect_gmii2rgmii 3valid 1
>> ...
>>
>>
>> [u-boot](debian-sent)$ git diff
>> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
>> index dcdef9e661d6..56072ad55216 100644
>> --- a/drivers/net/phy/phy.c
>> +++ b/drivers/net/phy/phy.c
>> @@ -950,7 +950,10 @@ static struct phy_device
>> *phy_connect_gmii2rgmii(struct mii_dev *bus,
>> struct
Re: [PATCH] arm64: zynqmp: Enable capsule update
po 26. 4. 2021 v 13:08 odesílatel Michal Simek napsal: > > Enable EFI capsule update features to be enabled by default also with all > dfu valid options for ZynqMP. > > This feature was tested on Xilinx ZynqMP zcu104 board with defining > dfu_alt_info="mmc 0:1=boot.bin fat 0 1;u-boot.itb fat 0 1" > and > dfu_alt_info="sf 0:0=boot.bin raw 0 0x5;u-boot.itb raw 0x8 > 0x50". > > There is a need to increase malloc size for getting dfu mmc to work. > > Signed-off-by: Michal Simek > CC: Sughosh Ganu > CC: Ilias Apalodimas > CC: Heinrich Schuchardt > --- > > I actually didn't try to boot out of qspi because qspi writing is likely > broken and should be fixed. But I have checked that images are written to > that previously erased locations. > > U-Boot SPL 2021.04-00978-g76a8101e4548 (Apr 26 2021 - 13:01:46 +0200) > PMUFW: v1.1 > Loading new PMUFW cfg obj (2024 bytes) > Silicon version:3 > EL Level: EL3 > Chip ID:zu7e > Multiboot: 0 > Trying to boot from MMC2 > spl: could not initialize mmc. error: -19 > Trying to boot from MMC1 > spl_load_image_fat_os: error reading image u-boot.bin, err - -2 > NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000 > NOTICE: BL31: v2.2(release):xilinx-v2020.2.2-k26 > NOTICE: BL31: Built : 11:51:16, Apr 21 2021 > > U-Boot 2021.04-00978-g76a8101e4548 (Apr 26 2021 - 13:01:46 +0200) > > Model: ZynqMP ZCU104 RevC > Board: Xilinx ZynqMP > DRAM: 2 GiB > PMUFW: v1.1 > EL Level: EL2 > Chip ID:zu7e > WDT: Started with servicing (60s timeout) > NAND: 0 MiB > MMC: mmc@ff17: 0 > Loading Environment from FAT... OK > In:serial > Out: serial > Err: serial > Net: > ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id > eth0: ethernet@ff0e > Scanning disk m...@ff17.blk... > Found 4 disks > ##Hit any key to stop autoboot: 0 > ZynqMP> reset > resetting ... > > U-Boot SPL 2021.04-00978-g01e9f0ec63e4 (Apr 26 2021 - 13:04:48 +0200) > PMUFW: v1.1 > Loading new PMUFW cfg obj (2024 bytes) > Silicon version:3 > EL Level: EL3 > Chip ID:zu7e > Multiboot: 0 > Trying to boot from MMC2 > spl: could not initialize mmc. error: -19 > Trying to boot from MMC1 > spl_load_image_fat_os: error reading image u-boot.bin, err - -2 > NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000 > NOTICE: BL31: v2.2(release):xilinx-v2020.2.2-k26 > NOTICE: BL31: Built : 11:51:16, Apr 21 2021 > > U-Boot 2021.04-00978-g01e9f0ec63e4 (Apr 26 2021 - 13:04:48 +0200) > > Model: ZynqMP ZCU104 RevC > Board: Xilinx ZynqMP > DRAM: 2 GiB > PMUFW: v1.1 > EL Level: EL2 > Chip ID:zu7e > WDT: Started with servicing (60s timeout) > NAND: 0 MiB > MMC: mmc@ff17: 0 > Loading Environment from FAT... OK > In:serial > Out: serial > Err: serial > Net: > ZYNQ GEM: ff0e, mdio bus ff0e, phyaddr 12, interface rgmii-id > eth0: ethernet@ff0e > Scanning disk m...@ff17.blk... > Found 4 disks > Hit any key to stop autoboot: 0 > ZynqMP> > > --- > configs/xilinx_zynqmp_virt_defconfig | 9 + > include/configs/xilinx_zynqmp.h | 2 +- > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/configs/xilinx_zynqmp_virt_defconfig > b/configs/xilinx_zynqmp_virt_defconfig > index 89c1dae2a1d9..9c496098584f 100644 > --- a/configs/xilinx_zynqmp_virt_defconfig > +++ b/configs/xilinx_zynqmp_virt_defconfig > @@ -86,7 +86,11 @@ CONFIG_SATA_CEVA=y > CONFIG_CLK_ZYNQMP=y > CONFIG_DFU_TFTP=y > CONFIG_DFU_TIMEOUT=y > +CONFIG_DFU_MMC=y > +CONFIG_DFU_NAND=y > CONFIG_DFU_RAM=y > +CONFIG_DFU_SF=y > +CONFIG_DFU_MTD=y > CONFIG_USB_FUNCTION_FASTBOOT=y > CONFIG_FASTBOOT_FLASH=y > CONFIG_FASTBOOT_FLASH_MMC_DEV=0 > @@ -178,3 +182,8 @@ CONFIG_TPM=y > CONFIG_SPL_GZIP=y > # CONFIG_SPL_HEXDUMP is not set > CONFIG_OF_LIBFDT_OVERLAY=y > +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y > +CONFIG_EFI_CAPSULE_ON_DISK=y > +CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y > +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y > +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y > diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h > index 36f3d962e417..986af2be7819 100644 > --- a/include/configs/xilinx_zynqmp.h > +++ b/include/configs/xilinx_zynqmp.h > @@ -27,7 +27,7 @@ > #endif > > /* Size of malloc() pool */ > -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x200) > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x400) > > /* Serial setup */ > #define CONFIG_CPU_ARMV8 > -- > 2.31.1 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Please pull u-boot-marvell/master
Hi Tom,
please pull the next batch of Marvell Armada related patches. Here the
summary log:
- Add base support for Marvell OcteonTX2 CN9130 CRB (mostly done
by Kostya)
- Sync Armada 3k/7k/8k SERDES code with Marvell version (misc Marvell
authors)
- pci-aardvark: Fix processing PIO transfers (Pali)
Here the Azure build, without any issues:
https://dev.azure.com/sr0718/u-boot/_build/results?buildId=83=results
Thanks,
Stefan
The following changes since commit 939c4934c8e91b34b258c9487be6a889a6a43546:
configs: Resync with savedefconfig (2021-04-28 10:05:13 +0200)
are available in the Git repository at:
g...@source.denx.de:u-boot/custodians/u-boot-marvell.git
for you to fetch changes up to eccbd4ad8e4e182638eafbfb87ac139c04f24a01:
arm: a37xx: pci: Fix processing PIO transfers (2021-04-29 07:45:43 +0200)
Christine Gharzuzi (1):
phy: marvell: fix handling of unconnected comphy
Grzegorz Jaszczyk (8):
phy: marvell: cp110: let the firmware configure comphy for RXAUI
phy: marvell: cp110: let the firmware configure comphy for USB
phy: marvell: cp110: let the firmware perform training for XFI
phy: marvell: cp110: remove both phy and pipe selector configuration
phy: marvell: cp110: clean up driver after it was moved to atf
phy: marvell: allow to initialize up to 6 USB ports
phy: marvell: fix pll initialization for second utmi port
phy: marvell: utmi: update utmi config which fixes usb2.0 instability
Igal Liberman (11):
phy: marvell: rename comphy related definitions to COMPHY_XX
phy: marvell: add missing speed during info prints
phy: marvell: cp110: utmi: update analog parameters according to
latest ETP
phy: marvell: fix several minor bugs in comphy_probe
phy: marvell: save comphy_map_data priv structure
phy: marvell: add RX training command
phy: marvell: enable comphy info prints for all devices
phy: marvell: pass sgmii id to firmware
phy: marvell: cp110: mark u-boot power-off calls
phy: marvell: add support for SFI1
doc: dt-bindings: add Marvell comphy binding
Konstantin Porotchkin (7):
power: regulator: Add support for regulator-force-boot-off
cmd/mvebu: fix the bubt command
arm: armada: dts: Use a single dtsi for cp110 die description
arm: armada: dts: Add support for ap807-based platforms
arm: armada: configs: Move environment location for mvebu
arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRB
arm: octeontx2: Add Octeon TX2 CN9130 CRB support
Marcin Wojtas (1):
phy: marvell: cp110: remove unused definitions
Omri Itach (1):
phy: marvell: cp110: initialize only enabled UTMI units
Pali Rohár (1):
arm: a37xx: pci: Fix processing PIO transfers
Stefan Roese (1):
arm: octeontx2: cn9130-crb.dtsi: Disable eth2 for now
jinghua (1):
phy: marvell: add comphy type PHY_TYPE_USB3
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/armada-3720-db.dts| 8 +-
arch/arm/dts/armada-3720-espressobin.dts | 12 +-
arch/arm/dts/armada-3720-turris-mox.dts| 12 +-
arch/arm/dts/armada-3720-uDPU.dts | 23 +-
arch/arm/dts/armada-7040-db-nand.dts | 97 +--
arch/arm/dts/armada-7040-db.dts| 104 ++--
arch/arm/dts/armada-7040.dtsi | 91 +--
arch/arm/dts/armada-8020.dtsi | 56 --
arch/arm/dts/armada-8040-clearfog-gt-8k.dts| 104 ++--
arch/arm/dts/armada-8040-db.dts| 125 ++--
arch/arm/dts/armada-8040-mcbin.dts | 91 +--
arch/arm/dts/armada-8040-puzzle-m801.dts | 126 ++--
arch/arm/dts/armada-8040.dtsi | 116 ++--
arch/arm/dts/armada-8k.dtsi| 18 +
arch/arm/dts/armada-ap806-quad.dtsi| 82 ---
arch/arm/dts/armada-ap806.dtsi | 281 +
arch/arm/dts/armada-ap807.dtsi | 40 ++
arch/arm/dts/armada-ap80x-quad.dtsi| 52 ++
arch/arm/dts/armada-ap80x.dtsi | 211 +++
arch/arm/dts/armada-common.dtsi| 30 +
arch/arm/dts/armada-cp110-slave.dtsi | 368
...{armada-cp110-master.dtsi => armada-cp110.dtsi} | 315 +-
arch/arm/dts/cn9130-crb-A.dts | 57 ++
arch/arm/dts/cn9130-crb-B.dts | 61 ++
arch/arm/dts/cn9130-crb.dtsi | 257
arch/arm/dts/cn9130.dtsi | 73 +++
arch/arm/mach-mvebu/Kconfig| 10 +
board/CZ.NIC/turris_mox/turris_mox.c | 8 +-
board/Marvell/octeontx2_cn913x/MAINTAINERS
