[PATCH v4 06/13] makefile: Pass OpenSBI blob to binman make rules
This updates the make rules to pass OpenSBI blob to binman.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v1)
Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/Makefile b/Makefile
index 404977efa5..3d88559b67 100644
--- a/Makefile
+++ b/Makefile
@@ -1287,6 +1287,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if
$(BINMAN_DEBUG),-D) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
-a atf-bl31-path=${BL31} \
+ -a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
--
2.25.1
[PATCH v4 07/13] riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb
At present SiFive Unleashed board uses the Makefile to create the FIT,
using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
warning. Update to use binman instead.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v3)
Changes in v3:
- Fix the opensbi entry type in binman.dtsi
arch/riscv/dts/binman.dtsi| 70 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 1 +
board/sifive/unleashed/Kconfig| 1 +
configs/sifive_unleashed_defconfig| 1 +
4 files changed, 73 insertions(+)
create mode 100644 arch/riscv/dts/binman.dtsi
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
new file mode 100644
index 00..e02597e73d
--- /dev/null
+++ b/arch/riscv/dts/binman.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng
+ */
+
+#include
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load OpenSBI before
U-Boot";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+
+ images {
+ uboot {
+ description = "U-Boot";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "riscv";
+ compression = "none";
+ load = ;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ opensbi {
+ description = "OpenSBI fw_dynamic
Firmware";
+ type = "firmware";
+ os = "opensbi";
+ arch = "riscv";
+ compression = "none";
+ load = ;
+ entry = ;
+
+ opensbi_blob: opensbi {
+ filename = "fw_dynamic.bin";
+ };
+ };
+
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "conf-1";
+
+ @conf-SEQ {
+ description = "NAME";
+ firmware = "opensbi";
+ loadables = "uboot";
+ fdt = "fdt-SEQ";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 1996149c95..51b566116d 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) 2019 Jagan Teki
*/
+#include "binman.dtsi"
#include "fu540-c000-u-boot.dtsi"
#include "fu540-hifive-unleashed-a00-ddr.dtsi"
diff --git a/board/sifive/unleashed/Kconfig b/board/sifive/unleashed/Kconfig
index dbffd59c98..502916e86a 100644
--- a/board/sifive/unleashed/Kconfig
+++ b/board/sifive/unleashed/Kconfig
@@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SIFIVE_FU540
select ENV_IS_IN_SPI_FLASH
+ select BINMAN
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
diff --git a/configs/sifive_unleashed_defconfig
b/configs/sifive_unleashed_defconfig
index 62416a7c1d..dc9313e572 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -14,6 +14,7 @@ CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8400
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_MISC_INIT_R=y
--
2.25.1
[PATCH v4 08/13] lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED
Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED. For the other OF_CONTROL methods, it's quite possible binman node is not available as binman is invoked during the build phase instead of runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default. Signed-off-by: Bin Meng --- (no changes since v3) Changes in v3: - new patch: "lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED" lib/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Kconfig b/lib/Kconfig index 6d2d41de30..7d5990c940 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -25,7 +25,7 @@ config BCH config BINMAN_FDT bool "Allow access to binman information in the device tree" depends on BINMAN && DM && OF_CONTROL - default y + default y if OF_SEPARATE || OF_EMBED help This enables U-Boot to access information about binman entries, stored in the device tree in a binman node. Typical uses are to -- 2.25.1
[PATCH v4 09/13] binman: Support packaging U-Boot for scenarios like OF_BOARD or OF_PRIOR_STAGE
For scenarios like OF_BOARD or OF_PRIOR_STAGE, no device tree blob is provided in the U-Boot build phase hence the binman node information is not available. In order to support such use case, a new Kconfig option BINMAN_STANDALONE_FDT is introduced, to tell the build system that a device tree blob containing binman node is explicitly required when using binman to package U-Boot. Signed-off-by: Bin Meng --- Changes in v4: - update the makefile dependency on u-boot.img instead of u-boot.bin Changes in v3: - rename the Kconfig option name to BINMAN_STANDALONE_FDT - make BINMAN_STANDALONE_FDT default y for OF_BOARD as well - reword the Kconfig option help message a little bit Changes in v2: - new patch: "binman: Support packaging U-Boot for scenarios like OF_PRIOR_STAGE" Makefile| 3 ++- dts/Kconfig | 18 ++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3d88559b67..1dbf0b0b8c 100644 --- a/Makefile +++ b/Makefile @@ -918,6 +918,7 @@ endif endif INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb +INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb ifeq ($(CONFIG_SPL_FRAMEWORK),y) INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img endif @@ -1392,7 +1393,7 @@ u-boot-lzma.img: u-boot.bin.lzma FORCE u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \ $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \ - $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \ ,$(UBOOT_BIN)) FORCE $(call if_changed,mkimage) $(BOARD_SIZE_CHECK) diff --git a/dts/Kconfig b/dts/Kconfig index 99ce75e1a2..dabe0080c1 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -19,6 +19,24 @@ config BINMAN bool select DTOC +config BINMAN_STANDALONE_FDT + bool + depends on BINMAN + default y if OF_BOARD || OF_PRIOR_STAGE + help + This option tells U-Boot build system that a standalone device tree + source is explicitly required when using binman to package U-Boot. + + This is not necessary in a common scenario where a device tree source + that contains the binman node is provided in the arch//dts + directory for a specific board. Such device tree sources are built for + OF_SEPARATE or OF_EMBED. However for a scenario like the board device + tree blob is not provided in the U-Boot build tree, but fed to U-Boot + in the runtime, e.g.: in the OF_PRIOR_STAGE case that it is passed by + a prior stage bootloader. For such scenario, a standalone device tree + blob containing binman node to describe how to package U-Boot should + be provided explicitly. + menu "Device Tree Control" depends on SUPPORT_OF_CONTROL -- 2.25.1
[PATCH v4 12/13] riscv: ae350: Switch to use binman to generate u-boot.itb
Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs,
so that binman is now used to generate u-boot.itb.
Signed-off-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- new patch: "riscv: ae350: Switch to use binman to generate u-boot.itb"
arch/riscv/dts/ae350_32.dts | 2 ++
arch/riscv/dts/ae350_64.dts | 2 ++
board/AndesTech/ax25-ae350/Kconfig | 1 +
configs/ae350_rv32_spl_defconfig | 2 ++
configs/ae350_rv32_spl_xip_defconfig | 2 ++
configs/ae350_rv64_spl_defconfig | 2 ++
configs/ae350_rv64_spl_xip_defconfig | 2 ++
7 files changed, 13 insertions(+)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 3f8525fe56..a0ab5e9be2 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -1,5 +1,7 @@
/dts-v1/;
+#include "binman.dtsi"
+
/ {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 482c707503..f654f4809a 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -1,5 +1,7 @@
/dts-v1/;
+#include "binman.dtsi"
+
/ {
#address-cells = <2>;
#size-cells = <2>;
diff --git a/board/AndesTech/ax25-ae350/Kconfig
b/board/AndesTech/ax25-ae350/Kconfig
index 321dd0cb10..e50f505a2b 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
select SUPPORT_SPL
+ select BINMAN if SPL
imply SMP
imply SPL_RAM_SUPPORT
imply SPL_RAM_DEVICE
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 153266f647..47c8e9a621 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -3,11 +3,13 @@ CONFIG_SYS_TEXT_BASE=0x0120
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
diff --git a/configs/ae350_rv32_spl_xip_defconfig
b/configs/ae350_rv32_spl_xip_defconfig
index 651b1eb733..206ffe2720 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -4,12 +4,14 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_TEXT_BASE=0x8000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index f434091d47..ef04e4a4b6 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -3,12 +3,14 @@ CONFIG_SYS_TEXT_BASE=0x0120
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
diff --git a/configs/ae350_rv64_spl_xip_defconfig
b/configs/ae350_rv64_spl_xip_defconfig
index b0afdb4cfe..21b7e8895b 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -4,6 +4,7 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_TEXT_BASE=0x8000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
@@ -11,6 +12,7 @@ CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
--
2.25.1
[PATCH v4 10/13] riscv: dts: Sort build targets in alphabetical order
Sort the RISC-V DTS build targets by their Kconfig target names in alphabetical order. Signed-off-by: Bin Meng --- (no changes since v2) Changes in v2: - new patch: "riscv: dts: Sort build targets in alphabetical order" arch/riscv/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 8138d89d84..3780334875 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb -dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb targets += $(dtb-y) -- 2.25.1
[PATCH v4 11/13] riscv: qemu: Switch to use binman to generate u-boot.itb
By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along
with a new dedicated device tree source file for the QEMU virt target
used for binman only, we can now use binman to generate u-boot.itb.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- new patch: "riscv: qemu: Switch to use binman to generate u-boot.itb"
arch/riscv/cpu/generic/Kconfig | 1 +
arch/riscv/dts/Makefile| 1 +
arch/riscv/dts/binman.dtsi | 8
arch/riscv/dts/qemu-virt.dts | 8
configs/qemu-riscv32_spl_defconfig | 2 ++
configs/qemu-riscv64_spl_defconfig | 2 ++
6 files changed, 22 insertions(+)
create mode 100644 arch/riscv/dts/qemu-virt.dts
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index 198e36e969..a4934bb957 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -4,6 +4,7 @@
config GENERIC_RISCV
bool
+ select BINMAN if SPL
select ARCH_EARLY_INIT_R
imply CPU
imply CPU_RISCV
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3780334875..26ef853282 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index e02597e73d..d26cfdb78a 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -48,21 +48,29 @@
};
};
+#ifndef CONFIG_OF_PRIOR_STAGE
@fdt-SEQ {
description = "NAME";
type = "flat_dt";
compression = "none";
};
+#endif
};
configurations {
default = "conf-1";
+#ifndef CONFIG_OF_PRIOR_STAGE
@conf-SEQ {
+#else
+ conf-1 {
+#endif
description = "NAME";
firmware = "opensbi";
loadables = "uboot";
+#ifndef CONFIG_OF_PRIOR_STAGE
fdt = "fdt-SEQ";
+#endif
};
};
};
diff --git a/arch/riscv/dts/qemu-virt.dts b/arch/riscv/dts/qemu-virt.dts
new file mode 100644
index 00..fecff542b9
--- /dev/null
+++ b/arch/riscv/dts/qemu-virt.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
diff --git a/configs/qemu-riscv32_spl_defconfig
b/configs/qemu-riscv32_spl_defconfig
index 18dfe33ca8..a4c156612a 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -2,11 +2,13 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8020
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_MII is not set
diff --git a/configs/qemu-riscv64_spl_defconfig
b/configs/qemu-riscv64_spl_defconfig
index 897adf6a29..6c680483ce 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -2,12 +2,14 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8020
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_MII is not set
--
2.25.1
[PATCH v4 13/13] riscv: Drop USE_SPL_FIT_GENERATOR
Now that we have switched to binman to generate u-boot.itb for all
RISC-V boards, USE_SPL_FIT_GENERATOR is no longer needed and can
be dropped.
Signed-off-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- remove USE_SPL_FIT_GENERATOR in ae350_ defconfigs
Changes in v2:
- new patch: "riscv: Drop USE_SPL_FIT_GENERATOR"
arch/riscv/lib/mkimage_fit_opensbi.sh | 100 --
common/Kconfig.boot | 3 +-
configs/ae350_rv32_spl_defconfig | 1 -
configs/ae350_rv32_spl_xip_defconfig | 1 -
configs/ae350_rv64_spl_defconfig | 1 -
configs/ae350_rv64_spl_xip_defconfig | 1 -
configs/qemu-riscv32_spl_defconfig| 1 -
configs/qemu-riscv64_spl_defconfig| 1 -
configs/sifive_unleashed_defconfig| 1 -
9 files changed, 1 insertion(+), 109 deletions(-)
delete mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
diff --git a/arch/riscv/lib/mkimage_fit_opensbi.sh
b/arch/riscv/lib/mkimage_fit_opensbi.sh
deleted file mode 100755
index d6f95e5bfd..00
--- a/arch/riscv/lib/mkimage_fit_opensbi.sh
+++ /dev/null
@@ -1,100 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0+
-#
-# script to generate FIT image source for RISC-V boards with OpenSBI
-# and, optionally, multiple device trees (given on the command line).
-#
-# usage: $0 [ [&2
- OPENSBI=/dev/null
-fi
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
- description = "Configuration to load OpenSBI before U-Boot";
-
- images {
- uboot {
- description = "U-Boot";
- data = /incbin/("u-boot-nodtb.bin");
- type = "standalone";
- os = "U-Boot";
- arch = "riscv";
- compression = "none";
- load = <$UBOOT_LOAD_ADDR>;
- };
- opensbi {
- description = "RISC-V OpenSBI";
- data = /incbin/("$OPENSBI");
- type = "firmware";
- os = "opensbi";
- arch = "riscv";
- compression = "none";
- load = <$OPENSBI_LOAD_ADDR>;
- entry = <$OPENSBI_LOAD_ADDR>;
- };
-__HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
- cat << __FDT_IMAGE_EOF
- fdt_$cnt {
- description = "$(basename $dtname .dtb)";
- data = /incbin/("$dtname");
- type = "flat_dt";
- compression = "none";
- };
-__FDT_IMAGE_EOF
-cnt=$((cnt+1))
-done
-
-cat << __CONF_HEADER_EOF
- };
- configurations {
- default = "config_1";
-
-__CONF_HEADER_EOF
-
-if [ $# -eq 0 ]; then
-cat << __CONF_SECTION_EOF
- config_1 {
- description = "U-Boot FIT";
- firmware = "opensbi";
- loadables = "uboot";
- };
-__CONF_SECTION_EOF
-else
-cnt=1
-for dtname in $*
-do
-cat << __CONF_SECTION_EOF
- config_$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt_$cnt";
- };
-__CONF_SECTION_EOF
-cnt=$((cnt+1))
-done
-fi
-
-cat << __ITS_EOF
- };
-};
-__ITS_EOF
diff --git a/common/Kconfig.boot b/common/Kconfig.boot
index 94d82c27dd..89a3161f1f 100644
--- a/common/Kconfig.boot
+++ b/common/Kconfig.boot
@@ -273,14 +273,13 @@ config SPL_FIT_SOURCE
config USE_SPL_FIT_GENERATOR
bool "Use a script to generate the .its script"
- default y if SPL_FIT && !ARCH_SUNXI
+ default y if SPL_FIT && (!ARCH_SUNXI && !RISCV)
config SPL_FIT_GENERATOR
string ".its file generator script for U-Boot FIT image"
depends on USE_SPL_FIT_GENERATOR
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT &&
ARCH_ROCKCHIP
default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT &&
ARCH_ZYNQMP
- default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
Specifies a (platform specific) script file to generate the FIT
source file used to build the U-Boot FIT image file. This gets
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 47c8e9a621..25b4ada427 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -9,7 +9,6 @@ CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020
-# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
diff --git a/configs/ae350_rv32_spl_xip_defconfig
b/configs/ae350_rv32_spl_xip_defconfig
index 206ffe2720..c5d7ac3bc1 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv
Re: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
On Mon, May 10, 2021 at 2:58 PM Bin Meng wrote:
>
> This series updates binman to handle creation of u-boot.itb image for
> RISC-V boards.
>
> Azure results: PASS
> https://dev.azure.com/bmeng/GitHub/_build/results?buildId=363&view=results
>
> The following tests were performed:
> * booting qemu-riscv{32|64}_spl_defconfig on QEMU virt
> * booting sifive_unleashed_defconfig on QEMU sifive_u
>
> AE350 SPL defconfigs are not tested. @Rick, could you please test and report?
+Leo
>
> The series is available at u-boot-x86/riscv_binman for testing.
>
>
> Changes in v4:
> - update the makefile dependency on u-boot.img instead of u-boot.bin
[PATCH V2] doc: usage: modify mmc man-page
Modify mmc man-page. - Change a description about mmc erase command. - Add whitespace to distinguish. Signed-off-by: Jaehoon Chung Reviewed-by: Bin Meng --- Changelog on V2: - Added Bin Meng's reviewed-tag - Fixed typo in commit-msg - Changed from count to cnt --- doc/usage/mmc.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/usage/mmc.rst b/doc/usage/mmc.rst index 57284ed6741e..458c7642c076 100644 --- a/doc/usage/mmc.rst +++ b/doc/usage/mmc.rst @@ -40,7 +40,7 @@ The 'mmc write' command writes raw data to MMC device from memory address with b cnt block count -The 'mmc erase' command erases MMC device from block offset until count. +The 'mmc erase' command erases *cnt* blocks on the MMC device starting at block *blk#*. blk# start block offset @@ -110,6 +110,7 @@ The 'mmc partconf' command shows or changes PARTITION_CONFIG field. partitions to access The 'mmc bootpart-resize' command changes sizes of boot and RPMB partitions. + dev device number boot part size MB -- 2.29.0
Re: FW: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
Hi Bin,
> From: Bin Meng
> Sent: Monday, May 10, 2021 2:58 PM
> To: Simon Glass ; Rick Jian-Zhi Chen(陳建志)
> ; u-boot@lists.denx.de
> Subject: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
>
> This series updates binman to handle creation of u-boot.itb image for RISC-V
> boards.
>
> Azure results: PASS
> https://dev.azure.com/bmeng/GitHub/_build/results?buildId=363&view=results
>
> The following tests were performed:
> * booting qemu-riscv{32|64}_spl_defconfig on QEMU virt
> * booting sifive_unleashed_defconfig on QEMU sifive_u
>
> AE350 SPL defconfigs are not tested. @Rick, could you please test and report?
OK. I will verify it on AE350.
Thanks,
Rick
Re: [PATCH 01/11] clk: Allow force setting clock defaults before relocation
Hi Sean,
This patch series produces conflicts when applying.
Could you please rebase them? Thanks!
Best regards,
Leo
On Sun, Apr 11, 2021 at 11:57:57PM -0400, Sean Anderson wrote:
> Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc
> state for SPL only") it has been impossible to set clock defaults before
> relocation. This is annoying on boards without SPL, since there is no way
> to set clock defaults before U-Boot proper. In particular, the aisram rate
> must be changed before relocation on the K210, since U-Boot will hang if we
> try and change the rate while we are using aisram.
>
> To get around this, (ab)use the stage parameter to force setting defaults,
> even if they would be otherwise posponed for later. A device tree property
> was decided against because of the concerns in the original commit thread
> about the overhead of repeatedly parsing the device tree.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Simon Glass
> ---
>
> drivers/clk/clk-uclass.c | 9 +++--
> include/clk.h| 4 +++-
> 2 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> index 53e7be764d..cf8d35b04b 100644
> --- a/drivers/clk/clk-uclass.c
> +++ b/drivers/clk/clk-uclass.c
> @@ -353,9 +353,14 @@ int clk_set_defaults(struct udevice *dev, int stage)
> if (!dev_has_ofnode(dev))
> return 0;
>
> - /* If this not in SPL and pre-reloc state, don't take any action. */
> + /*
> + * To avoid setting defaults twice, don't set them before relocation.
> + * However, still set them for SPL. And still set them if explicitly
> + * asked.
> + */
> if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
> - return 0;
> + if (stage <= 1)
> + return 0;
>
> debug("%s(%s)\n", __func__, dev_read_name(dev));
>
> diff --git a/include/clk.h b/include/clk.h
> index ca6b85fa6f..2021eb0506 100644
> --- a/include/clk.h
> +++ b/include/clk.h
> @@ -287,7 +287,9 @@ static inline int clk_release_all(struct clk *clk, int
> count)
> * will be processed).
> * @stage: A integer. 0 indicates that this is called before the device
> * is probed. 1 indicates that this is called just after the
> - * device has been probed
> + * device has been probed. 2 indicates that this is called after
> + * the device has been probed, and that defaults should still be
> + * set even if they would otherwise be ignored.
> */
> int clk_set_defaults(struct udevice *dev, int stage);
> #else
Re: FW: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
Hi Bin
> Hi Bin,
>
> > From: Bin Meng
> > Sent: Monday, May 10, 2021 2:58 PM
> > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志)
> > ; u-boot@lists.denx.de
> > Subject: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
> >
> > This series updates binman to handle creation of u-boot.itb image for
> > RISC-V boards.
> >
> > Azure results: PASS
> > https://dev.azure.com/bmeng/GitHub/_build/results?buildId=363&view=results
> >
> > The following tests were performed:
> > * booting qemu-riscv{32|64}_spl_defconfig on QEMU virt
> > * booting sifive_unleashed_defconfig on QEMU sifive_u
> >
> > AE350 SPL defconfigs are not tested. @Rick, could you please test and
> > report?
>
> OK. I will verify it on AE350.
It fail as below messages:
U-Boot SPL 2021.07-rc1-00218-g468b3b3 (May 10 2021 - 15:13:03 +0800)
Trying to boot from RAM
alloc space exhausted
Could not get FIT buffer of 499076 bytes
check CONFIG_SYS_SPL_MALLOC_SIZE
No device tree specified in SPL image
### ERROR ### Please RESET the board ###
Any comments ?
Thanks,
Rick
>
> Thanks,
> Rick
Re: [PATCH 07/17] reset: Avoid a warning in devm_regmap_init()
> Subject: [PATCH 07/17] reset: Avoid a warning in devm_regmap_init() s/reset/regmap/ On 08/05/21 04:00PM, Simon Glass wrote: > The devres_alloc() function is intended to avoid the need for freeing > memory, although in practice it may not be enabled, thus leading to a true > leak. > > Nevertheless this is intended. Add a comment to molify Coverity. > > Signed-off-by: Simon Glass > Reported-by: Coverity (CID: 312951) Acked-by: Pratyush Yadav > --- > > drivers/core/regmap.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c > index b51ce108c14..15ed189352c 100644 > --- a/drivers/core/regmap.c > +++ b/drivers/core/regmap.c > @@ -293,6 +293,7 @@ struct regmap *devm_regmap_init(struct udevice *dev, > int rc; > struct regmap **mapp, *map; > > + /* coverity[RESOURCE_LEAK] */ > mapp = devres_alloc(devm_regmap_release, sizeof(struct regmap *), > __GFP_ZERO); > if (unlikely(!mapp)) -- Regards, Pratyush Yadav Texas Instruments Inc.
Re: FW: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
Hi Rick,
On Mon, May 10, 2021 at 3:22 PM Rick Chen wrote:
>
> Hi Bin
>
> > Hi Bin,
> >
> > > From: Bin Meng
> > > Sent: Monday, May 10, 2021 2:58 PM
> > > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志)
> > > ; u-boot@lists.denx.de
> > > Subject: [PATCH v4 00/13] riscv: Switch to use binman to generate
> > > u-boot.itb
> > >
> > > This series updates binman to handle creation of u-boot.itb image for
> > > RISC-V boards.
> > >
> > > Azure results: PASS
> > > https://dev.azure.com/bmeng/GitHub/_build/results?buildId=363&view=results
> > >
> > > The following tests were performed:
> > > * booting qemu-riscv{32|64}_spl_defconfig on QEMU virt
> > > * booting sifive_unleashed_defconfig on QEMU sifive_u
> > >
> > > AE350 SPL defconfigs are not tested. @Rick, could you please test and
> > > report?
> >
> > OK. I will verify it on AE350.
>
> It fail as below messages:
>
> U-Boot SPL 2021.07-rc1-00218-g468b3b3 (May 10 2021 - 15:13:03 +0800)
> Trying to boot from RAM
> alloc space exhausted
Looks it is running out of memory.
> Could not get FIT buffer of 499076 bytes
> check CONFIG_SYS_SPL_MALLOC_SIZE
Could you please try increasing CONFIG_SYS_SPL_MALLOC_SIZE?
> No device tree specified in SPL image
> ### ERROR ### Please RESET the board ###
>
> Any comments ?
Regards,
Bin
Re: [PATCHv3 19/26] arm: mach-k3: do board config for PM and RM only if supported
On 09/05/2021 08:54, Vignesh Raghavendra wrote:
On 5/5/21 11:25 PM, Tero Kristo wrote:
From: Tero Kristo
If the raw PM support is built in, we are operating in the split
firmware approach mode where RM and PM support is not available. In this
case, skip the board config for these two.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 0bacfc4d07..64472353c4 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -159,11 +159,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
ret);
/* Apply power/clock (PM) specific configuration to SYSFW */
+#ifndef CONFIG_K3_DM_FW
ret = board_ops->board_config_pm(ti_sci,
(u64)(u32)cfg_fragment_addr,
(u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
+#endif
/* Extract resource management (RM) specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
@@ -172,12 +174,14 @@ static void k3_sysfw_configure_using_fit(void *fit,
panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
ret);
+#ifndef CONFIG_K3_DM_FW
/* Apply resource management (RM) configuration to SYSFW */
ret = board_ops->board_config_rm(ti_sci,
(u64)(u32)cfg_fragment_addr,
(u32)cfg_fragment_size);
if (ret)
panic("Failed to set board RM configuration (%d)\n", ret);
+#endif
/* Extract security specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
We still need to send RM CFG to TIFS in case of J721e in order for DMA
to work at R5 SPL. TIFS needs RM CFG to disable firewalls when R5 SPL
sends DMA channel cfg requests.
Could you squash the following diff for next version:
Yes, I can squash that in. I believe you have tested this change and it
works? (I will obviously double check at my end though.)
-Tero
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index b95137fbdd..ac719cd46f 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -263,14 +263,7 @@ static void k3_sysfw_configure_using_fit(void *fit,
panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
ret);
-#ifndef CONFIG_K3_DM_FW
- /* Apply resource management (RM) configuration to SYSFW */
- ret = board_ops->board_config_rm(ti_sci,
-(u64)(u32)cfg_fragment_addr,
-(u32)cfg_fragment_size);
- if (ret)
- panic("Failed to set board RM configuration (%d)\n", ret);
-#else
+#ifdef CONFIG_K3_DM_FW
if (copy_bcfg) {
desc = &bcfg_header->descs[1];
@@ -284,6 +277,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
}
#endif
+ /* Apply resource management (RM) configuration to SYSFW */
+ ret = board_ops->board_config_rm(ti_sci,
+(u64)(u32)cfg_fragment_addr,
+(u32)cfg_fragment_size);
+ if (ret)
+ panic("Failed to set board RM configuration (%d)\n", ret);
+
/* Extract security specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
&cfg_fragment_addr, &cfg_fragment_size);
Regards
Vignesh
[PATCH] efi_loader: capsule: add a debug message in case of no key
It will probably be a common error case that a certificate (public key)
is not provided by the system while capsule authentication is enabled.
So add a debug message.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_capsule.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 90893f85e22c..84ddaf50d13f 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -316,8 +316,10 @@ efi_status_t efi_capsule_authenticate(const void *capsule,
efi_uintn_t capsule_s
}
ret = efi_get_public_key_data(&fdt_pkey, &pkey_len);
- if (ret < 0)
+ if (ret < 0) {
+ debug("Public key/certificate not found\n");
goto out;
+ }
pkey = malloc(pkey_len);
if (!pkey)
--
2.31.0
[PATCH] efi_loader: capsule: remove unused guid
EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID is never used.
Just remove it.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_capsule.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 84ddaf50d13f..b0dffd3ac9ce 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -208,9 +208,6 @@ skip:
#if defined(CONFIG_EFI_CAPSULE_AUTHENTICATE)
-const efi_guid_t efi_guid_capsule_root_cert_guid =
- EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
-
#if defined(CONFIG_EFI_PKEY_DTB_EMBED)
int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
{
--
2.31.0
[PATCH] efi_loader: capsule: remove authentication data
If capsule authentication is disabled and yet a capsule file is signed,
its signature must be removed from image data to flush.
Otherwise, the firmware will be corrupted after update.
Fixes: 04be98bd6bcf ("efi: capsule: Add support for uefi capsule
authentication")
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_capsule.c | 70 +---
1 file changed, 57 insertions(+), 13 deletions(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index b0dffd3ac9ce..5d156c730faa 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -206,6 +206,39 @@ skip:
return NULL;
}
+/**
+ * efi_remove_auth_hdr - remove authentication data from image
+ * @image: Pointer to pointer to Image
+ * @image_size:Pointer to Image size
+ *
+ * Remove the authentication data from image if possible.
+ * Update @image and @image_size.
+ *
+ * Return: status code
+ */
+static efi_status_t efi_remove_auth_hdr(void **image, efi_uintn_t *image_size)
+{
+ struct efi_firmware_image_authentication *auth_hdr;
+ efi_status_t ret = EFI_INVALID_PARAMETER;
+
+ auth_hdr = (struct efi_firmware_image_authentication *)*image;
+ if (*image_size < sizeof(*auth_hdr))
+ goto out;
+
+ if (auth_hdr->auth_info.hdr.dwLength <=
+ offsetof(struct win_certificate_uefi_guid, cert_data))
+ goto out;
+
+ *image = (uint8_t *)*image + sizeof(auth_hdr->monotonic_count) +
+ auth_hdr->auth_info.hdr.dwLength;
+ *image_size = *image_size - auth_hdr->auth_info.hdr.dwLength -
+ sizeof(auth_hdr->monotonic_count);
+
+ ret = EFI_SUCCESS;
+out:
+ return ret;
+}
+
#if defined(CONFIG_EFI_CAPSULE_AUTHENTICATE)
#if defined(CONFIG_EFI_PKEY_DTB_EMBED)
@@ -271,21 +304,15 @@ efi_status_t efi_capsule_authenticate(const void
*capsule, efi_uintn_t capsule_s
if (capsule == NULL || capsule_size == 0)
goto out;
- auth_hdr = (struct efi_firmware_image_authentication *)capsule;
- if (capsule_size < sizeof(*auth_hdr))
- goto out;
-
- if (auth_hdr->auth_info.hdr.dwLength <=
- offsetof(struct win_certificate_uefi_guid, cert_data))
+ *image = (uint8_t *)capsule;
+ *image_size = capsule_size;
+ if (efi_remove_auth_hdr(image, image_size) != EFI_SUCCESS)
goto out;
+ auth_hdr = (struct efi_firmware_image_authentication *)capsule;
if (guidcmp(&auth_hdr->auth_info.cert_type, &efi_guid_cert_type_pkcs7))
goto out;
- *image = (uint8_t *)capsule + sizeof(auth_hdr->monotonic_count) +
- auth_hdr->auth_info.hdr.dwLength;
- *image_size = capsule_size - auth_hdr->auth_info.hdr.dwLength -
- sizeof(auth_hdr->monotonic_count);
memcpy(&monotonic_count, &auth_hdr->monotonic_count,
sizeof(monotonic_count));
@@ -367,7 +394,7 @@ static efi_status_t efi_capsule_update_firmware(
{
struct efi_firmware_management_capsule_header *capsule;
struct efi_firmware_management_capsule_image_header *image;
- size_t capsule_size;
+ size_t capsule_size, image_binary_size;
void *image_binary, *vendor_code;
efi_handle_t *handles;
efi_uintn_t no_handles;
@@ -429,13 +456,30 @@ static efi_status_t efi_capsule_update_firmware(
}
/* do update */
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE) &&
+ !(image->image_capsule_support &
+ CAPSULE_SUPPORT_AUTHENTICATION)) {
+ /* no signature */
+ ret = EFI_SECURITY_VIOLATION;
+ goto out;
+ }
+
image_binary = (void *)image + sizeof(*image);
- vendor_code = image_binary + image->update_image_size;
+ image_binary_size = image->update_image_size;
+ vendor_code = image_binary + image_binary_size;
+ if (!IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE) &&
+ (image->image_capsule_support &
+ CAPSULE_SUPPORT_AUTHENTICATION)) {
+ ret = efi_remove_auth_hdr(&image_binary,
+ &image_binary_size);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
abort_reason = NULL;
ret = EFI_CALL(fmp->set_image(fmp, image->update_image_index,
image_binary,
- image->update_image_size,
+ image_binary_size,
vendor_code, NULL,
&abort_reason));
if (ret != EF
[PATCH] efi_loader: move asm/setjmp.h to efi_loader.h
In the commit c982874e930d ("efi_loader: refactor
efi_setup_loaded_image()"), setjmp-related definitions were moved to
efi_loaded_image_obj in efi_loader.h. So setjmp.h is no longer
refererenced in efi_api.h.
This also fixes some error when efi_api.h will be included in
mkeficapsule.c.
On the other hand, a tweak will be necessary in common/main.c as
some architectures have no setjmp support.
Fixes: c982874e930d ("efi_loader: refactor efi_setup_loaded_image()")
Signed-off-by: AKASHI Takahiro
---
common/main.c| 6 ++
include/efi_api.h| 4
include/efi_loader.h | 1 +
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/common/main.c b/common/main.c
index ae5bcdb32f8b..a41c57c26611 100644
--- a/common/main.c
+++ b/common/main.c
@@ -16,7 +16,13 @@
#include
#include
#include
+#ifdef CONFIG_EFI_LOADER
+/*
+ * Unfortunately, efi_loader requires setjmp.h, but there are
+ * some architectures which have no support for setjmp.
+ */
#include
+#endif
static void run_preboot_environment_command(void)
{
diff --git a/include/efi_api.h b/include/efi_api.h
index 18a1adf02390..e854a8b3a112 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -20,10 +20,6 @@
#include
#include
-#ifdef CONFIG_EFI_LOADER
-#include
-#endif
-
/* UEFI spec version 2.8 */
#define EFI_SPECIFICATION_VERSION (2 << 16 | 80)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index de1a496a9726..6994a951bc19 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
struct blk_desc;
--
2.31.0
[PATCH] test/py: efi_capsule: aligned with efidebug syntax changes
After the commit c70f44817d46 ("efi_loader: simplify 'printenv -e'"),
"-all" option is no longer necessary.
Just remove them in the test script.
Fixes: c70f44817d46 ("efi_loader: simplify 'printenv -e'")
Signed-off-by: AKASHI Takahiro
---
test/py/tests/test_efi_capsule/test_capsule_firmware.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
index 4697ca6f1c5c..9eeaae27d626 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
@@ -85,7 +85,7 @@ class TestEfiCapsuleFirmwareFit(object):
# need to run uefi command to initiate capsule handling
output = u_boot_console.run_command(
-'env print -e -all Capsule')
+'env print -e Capsule')
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
@@ -160,7 +160,7 @@ class TestEfiCapsuleFirmwareFit(object):
# need to run uefi command to initiate capsule handling
output = u_boot_console.run_command(
-'env print -e -all Capsule')
+'env print -e Capsule')
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
@@ -227,7 +227,7 @@ class TestEfiCapsuleFirmwareFit(object):
# need to run uefi command to initiate capsule handling
output = u_boot_console.run_command(
-'env print -e -all Capsule')
+'env print -e Capsule')
output = u_boot_console.run_command_list(['efidebug capsule esrt'])
--
2.31.0
Re: [PATCHv3 19/26] arm: mach-k3: do board config for PM and RM only if supported
On 5/10/21 1:48 PM, Tero Kristo wrote:
> On 09/05/2021 08:54, Vignesh Raghavendra wrote:
>>
>>
>> On 5/5/21 11:25 PM, Tero Kristo wrote:
>>> From: Tero Kristo
>>>
>>> If the raw PM support is built in, we are operating in the split
>>> firmware approach mode where RM and PM support is not available. In this
>>> case, skip the board config for these two.
>>>
>>> Signed-off-by: Tero Kristo
>>> Signed-off-by: Tero Kristo
>>> ---
>>> arch/arm/mach-k3/sysfw-loader.c | 4
>>> 1 file changed, 4 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-k3/sysfw-loader.c
>>> b/arch/arm/mach-k3/sysfw-loader.c
>>> index 0bacfc4d07..64472353c4 100644
>>> --- a/arch/arm/mach-k3/sysfw-loader.c
>>> +++ b/arch/arm/mach-k3/sysfw-loader.c
>>> @@ -159,11 +159,13 @@ static void k3_sysfw_configure_using_fit(void
>>> *fit,
>>> ret);
>>> /* Apply power/clock (PM) specific configuration to SYSFW */
>>> +#ifndef CONFIG_K3_DM_FW
>>> ret = board_ops->board_config_pm(ti_sci,
>>> (u64)(u32)cfg_fragment_addr,
>>> (u32)cfg_fragment_size);
>>> if (ret)
>>> panic("Failed to set board PM configuration (%d)\n", ret);
>>> +#endif
>>> /* Extract resource management (RM) specific configuration
>>> from FIT */
>>> ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
>>> @@ -172,12 +174,14 @@ static void k3_sysfw_configure_using_fit(void
>>> *fit,
>>> panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
>>> ret);
>>> +#ifndef CONFIG_K3_DM_FW
>>> /* Apply resource management (RM) configuration to SYSFW */
>>> ret = board_ops->board_config_rm(ti_sci,
>>> (u64)(u32)cfg_fragment_addr,
>>> (u32)cfg_fragment_size);
>>> if (ret)
>>> panic("Failed to set board RM configuration (%d)\n", ret);
>>> +#endif
>>> /* Extract security specific configuration from FIT */
>>> ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
>>>
>>
>>
>> We still need to send RM CFG to TIFS in case of J721e in order for DMA
>> to work at R5 SPL. TIFS needs RM CFG to disable firewalls when R5 SPL
>> sends DMA channel cfg requests.
>>
>> Could you squash the following diff for next version:
>
> Yes, I can squash that in. I believe you have tested this change and it
> works? (I will obviously double check at my end though.)
>
Yes, I discovered this when adding DMA support at R5 SPL level
on top of current series. Diff is essentially this commit by Dave on TI SDK
tree:
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2021.01&id=33f243f7c99f3e07afdc022e268cc65106781561
Regards
Vignesh
Re: [PATCH v2 01/50] lib: Add memdup()
On 06/05/2021 19.41, Simon Glass wrote: > Hi Pratyush, > > On Thu, 6 May 2021 at 10:07, Pratyush Yadav wrote: >> >> On 06/05/21 08:23AM, Simon Glass wrote: >>> Add a function to duplicate a memory region, a little like strdup(). >>> >>> Signed-off-by: Simon Glass >>> --- >>> >>> Changes in v2: >>> - Add a patch to introduce a memdup() function >>> >>> include/linux/string.h | 13 + >>> lib/string.c | 13 + >>> test/lib/string.c | 32 >>> 3 files changed, 58 insertions(+) >>> >>> diff --git a/include/linux/string.h b/include/linux/string.h >>> index dd255f21633..3169c93796e 100644 >>> --- a/include/linux/string.h >>> +++ b/include/linux/string.h >>> @@ -129,6 +129,19 @@ extern void * memchr(const void *,int,__kernel_size_t); >>> void *memchr_inv(const void *, int, size_t); >>> #endif >>> >>> +/** >>> + * memdup() - allocate a buffer and copy in the contents >>> + * >>> + * Note that this returns a valid pointer even if @len is 0 >> >> I'm uneducated about U-Boot's memory allocator. But I wonder how it >> returns a valid pointer even on 0 length allocations. What location does >> it point to? What are users expected to do with that pointer? They >> obviously can't read/write to it since it is supposed to be a 0 byte >> long allocation. If another positive length allocation happens before >> the said pointer is freed, will it point to the same memory location? If >> not, isn't the 0-length pointer actually at least a 1-length pointer? > > I think it is just a 0-length pointer and that the only thing you can > do with it is call free(). > > I am certainly no expert on this sort of thing though. It seems that > some implementations return NULL for a zero size, some return a valid > pointer which can be passed to free(). It's implementation-defined, which means that one cannot know for certain that a given malloc implementation won't return NULL for a request of 0 bytes. The linux kernel solved that problem by introducing ZERO_SIZE_PTR which is basically just (void*)16L or something like that - that way callers don't have to write their "did the allocation succeed" test in the ugly if (!p && size != 0) error_out; way. Of course kfree() must then accept that in addition to NULL, but it's not really more expensive to have that early nop check be if ((unsigned long)ptr <= 16) return; instead of if (!ptr) return; "man malloc" says RETURN VALUE The malloc() and calloc() functions return a pointer to the allocated memory, which is suitably aligned for any built-in type. On error, these functions return NULL. NULL may also be returned by a successful call to malloc() with a size of zero, or by a successful call to calloc() with nmemb or size equal to zero. Anyway, I don't think this helper should be put in string.c - it needs to be in some C file that's easily compiled for both board, sandbox and host tools (for the latter probably via the "tiny one-line wrapper that just includes the whole real C file"). I see there's linux_string.c already. Rasmus
[PATCH] Revert "riscv: cpu: fu740: clear feature disable CSR"
This reverts commit bc8bbb77f74f21582b3bfd790334397757f88575.
This commit breaks U-Boot booting on SiFive Unleashed board, as
there is no such CSR on U54 core.
Signed-off-by: Bin Meng
---
arch/riscv/cpu/fu540/spl.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c
index 1740ef98b6..45657b7909 100644
--- a/arch/riscv/cpu/fu540/spl.c
+++ b/arch/riscv/cpu/fu540/spl.c
@@ -6,9 +6,6 @@
#include
#include
-#include
-
-#define CSR_U74_FEATURE_DISABLE0x7c1
int spl_soc_init(void)
{
@@ -24,15 +21,3 @@ int spl_soc_init(void)
return 0;
}
-
-void harts_early_init(void)
-{
- /*
-* Feature Disable CSR
-*
-* Clear feature disable CSR to '0' to turn on all features for
-* each core. This operation must be in M-mode.
-*/
- if (CONFIG_IS_ENABLED(RISCV_MMODE))
- csr_write(CSR_U74_FEATURE_DISABLE, 0);
-}
--
2.25.1
[PATCH] mtd: mxs_nand: default to legacy bch and rename to modern bch option
Linux kernel defaults to use legacy bch setting, this was creating a
mismatch between U-boot and Linux default settings.
Fixes: 51cdf83eea ("mtd: gpmi: provide the option to use legacy bch geometry")
Signed-off-by: Sean Nyekjaer
---
drivers/mtd/nand/raw/mxs_nand.c| 2 +-
drivers/mtd/nand/raw/mxs_nand_dt.c | 2 +-
include/mxs_nand.h | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index e6bbfac4d6..49795e20d2 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -1119,7 +1119,7 @@ static int mxs_nand_set_geometry(struct mtd_info *mtd,
struct bch_geometry *geo)
}
if ((!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) &&
-mtd->oobsize < 1024) || nand_info->legacy_bch_geometry) {
+mtd->oobsize < 1024) || !nand_info->modern_bch_geometry) {
dev_warn(mtd->dev, "use legacy bch geometry\n");
return mxs_nand_legacy_calc_ecc_layout(geo, mtd);
}
diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c
b/drivers/mtd/nand/raw/mxs_nand_dt.c
index 878796d555..bbb7396324 100644
--- a/drivers/mtd/nand/raw/mxs_nand_dt.c
+++ b/drivers/mtd/nand/raw/mxs_nand_dt.c
@@ -92,7 +92,7 @@ static int mxs_nand_dt_probe(struct udevice *dev)
info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
- info->legacy_bch_geometry = dev_read_bool(dev,
"fsl,legacy-bch-geometry");
+ info->modern_bch_geometry = dev_read_bool(dev,
"fsl,modern-bch-geometry");
if (IS_ENABLED(CONFIG_CLK) && IS_ENABLED(CONFIG_IMX8)) {
/* Assigned clock already set clock */
diff --git a/include/mxs_nand.h b/include/mxs_nand.h
index c0cefaca90..7e254d6b31 100644
--- a/include/mxs_nand.h
+++ b/include/mxs_nand.h
@@ -43,8 +43,8 @@ struct mxs_nand_info {
struct udevice *dev;
unsigned intmax_ecc_strength_supported;
booluse_minimum_ecc;
- /* legacy bch geometry flag */
- boollegacy_bch_geometry;
+ /* modern bch geometry flag */
+ boolmodern_bch_geometry;
int cur_chip;
uint32_tcmd_queue_len;
--
2.31.0
Re: [PATCH v2 01/50] lib: Add memdup()
On 5/10/21 11:00 AM, Rasmus Villemoes wrote: On 06/05/2021 19.41, Simon Glass wrote: Hi Pratyush, On Thu, 6 May 2021 at 10:07, Pratyush Yadav wrote: On 06/05/21 08:23AM, Simon Glass wrote: Add a function to duplicate a memory region, a little like strdup(). Signed-off-by: Simon Glass --- Changes in v2: - Add a patch to introduce a memdup() function include/linux/string.h | 13 + lib/string.c | 13 + test/lib/string.c | 32 3 files changed, 58 insertions(+) diff --git a/include/linux/string.h b/include/linux/string.h index dd255f21633..3169c93796e 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -129,6 +129,19 @@ extern void * memchr(const void *,int,__kernel_size_t); void *memchr_inv(const void *, int, size_t); #endif +/** + * memdup() - allocate a buffer and copy in the contents + * + * Note that this returns a valid pointer even if @len is 0 I'm uneducated about U-Boot's memory allocator. But I wonder how it returns a valid pointer even on 0 length allocations. What location does it point to? What are users expected to do with that pointer? They obviously can't read/write to it since it is supposed to be a 0 byte long allocation. If another positive length allocation happens before the said pointer is freed, will it point to the same memory location? If not, isn't the 0-length pointer actually at least a 1-length pointer? I think it is just a 0-length pointer and that the only thing you can do with it is call free(). I am certainly no expert on this sort of thing though. It seems that some implementations return NULL for a zero size, some return a valid pointer which can be passed to free(). It's implementation-defined, which means that one cannot know for certain that a given malloc implementation won't return NULL for a request of 0 bytes. The linux kernel solved that problem by introducing ZERO_SIZE_PTR which is basically just (void*)16L or something like that - that way callers don't have to write their "did the allocation succeed" test in the ugly if (!p && size != 0) error_out; way. Of course kfree() must then accept that in addition to NULL, but it's not really more expensive to have that early nop check be if ((unsigned long)ptr <= 16) return; instead of if (!ptr) return; "man malloc" says RETURN VALUE The malloc() and calloc() functions return a pointer to the allocated memory, which is suitably aligned for any built-in type. On error, these functions return NULL. NULL may also be returned by a successful call to malloc() with a size of zero, or by a successful call to calloc() with nmemb or size equal to zero. Anyway, I don't think this helper should be put in string.c - it needs to be in some C file that's easily compiled for both board, sandbox and host tools (for the latter probably via the "tiny one-line wrapper that just includes the whole real C file"). I see there's linux_string.c already. Rasmus Our malloc() implementation allocates space for metadata of type struct malloc_chunk even if the argument is zero. This metadata is used to check that a call to free() refers to a valid pointer. I don't see a need to change this behavior. Best regards Heinrich
[PATCH] rtc: m41t62: fix wrong register use for set/reset ST bit
Fix wrong register use when set/reset ST bit.
ST bit is in register M41T62_REG_SEC not in M41T62_REG_ALARM_HOUR.
I have not actually tested this. But this seemed buggy from inspection.
Fixes: 9bbe210512c4539 ("rtc: m41t62: add oscillator fail bit reset support")
Signed-off-by: Max Yang
---
drivers/rtc/m41t62.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c
index 0a4e12d698..8be532c3e3 100644
--- a/drivers/rtc/m41t62.c
+++ b/drivers/rtc/m41t62.c
@@ -213,13 +213,13 @@ static int m41t62_rtc_restart_osc(struct udevice *dev)
/* 1. Set stop bit */
val |= M41T62_SEC_ST;
- ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+ ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
if (ret)
return ret;
/* 2. Clear stop bit */
val &= ~M41T62_SEC_ST;
- ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+ ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
if (ret)
return ret;
*
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use of the intended recipient(s) and may contain confidential and
privileged information. Any unauthorized review, use, disclosure or
distribution is prohibited. If you are not the intended recipient, please
contact the sender by reply e-mail and destroy all copies of the original
message. [Delta Electronics, INC. Taiwan]
*
Please pull u-boot-x86
Hi Tom,
This PR includes the following changes for v2021.07 release:
- x86: correct regwidth prompt in cbsysinfo
- virtio: convert README.virtio to reST
Azure results: PASS
https://dev.azure.com/bmeng/GitHub/_build/results?buildId=364&view=results
The following changes since commit 07b53103b7a6c228ae8b74ae720b9c5d219ee7fd:
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
(2021-05-07 08:57:32 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-x86
for you to fetch changes up to 200fdd3bff569369f9264e648ddc9c02547b6186:
MAINTAINERS: Add an entry for VirtIO (2021-05-10 13:56:12 +0800)
Bin Meng (2):
doc: develop: Convert README.virtio to reST
MAINTAINERS: Add an entry for VirtIO
Simon Glass (1):
x86: Correct regwidth prompt in cbsysinfo
MAINTAINERS| 12
cmd/x86/cbsysinfo.c| 2 +-
doc/develop/driver-model/index.rst | 1 +
doc/{README.virtio => develop/driver-model/virtio.rst} | 90
++
4 files changed, 76 insertions(+), 29 deletions(-)
rename doc/{README.virtio => develop/driver-model/virtio.rst} (86%)
Regards,
Bin
[PATCH v5 00/13] riscv: Switch to use binman to generate u-boot.itb
This series updates binman to handle creation of u-boot.itb image for
RISC-V boards.
Azure results: PASS
https://dev.azure.com/bmeng/GitHub/_build/results?buildId=363&view=results
The following tests were performed:
* booting qemu-riscv{32|64}_spl_defconfig on QEMU virt
* booting sifive_unleashed_defconfig on QEMU sifive_u
AE350 SPL defconfigs are not tested. @Rick, could you please test and report?
The series is available at u-boot-x86/riscv_binman for testing.
Changes in v5:
- update binman.rst for OF_BOARD or OF_PRIOR_STAGE usage
Changes in v4:
- update the makefile dependency on u-boot.img instead of u-boot.bin
Changes in v3:
- Fix the opensbi entry type in binman.dtsi
- new patch: "lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED"
- rename the Kconfig option name to BINMAN_STANDALONE_FDT
- make BINMAN_STANDALONE_FDT default y for OF_BOARD as well
- reword the Kconfig option help message a little bit
- new patch: "riscv: ae350: Switch to use binman to generate u-boot.itb"
- remove USE_SPL_FIT_GENERATOR in ae350_ defconfigs
Changes in v2:
- drop patch: "binman: test: Correct the name of 170_fit_fdt_missing_prop.dts",
as it was based on a wrong version
- drop patch: "makefile: Update clean rule to remove files generated by binman",
as it is better to refactor binman to generate all intermediate files for
makefile to clean
- drop "size = <16>" in the binman node
- new patch: "binman: Support packaging U-Boot for scenarios like
OF_PRIOR_STAGE"
- new patch: "riscv: dts: Sort build targets in alphabetical order"
- new patch: "riscv: qemu: Switch to use binman to generate u-boot.itb"
- new patch: "riscv: Drop USE_SPL_FIT_GENERATOR"
Bin Meng (13):
common: kconfig: Correct a typo in SPL_LOAD_FIT
binman: Correct '-a' description in the doc
binman: Correct the comment for ATF entry type
binman: test: Rename 172_fit_fdt.dts to 170_fit_fdt.dts
binman: Add support for RISC-V OpenSBI fw_dynamic blob
makefile: Pass OpenSBI blob to binman make rules
riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb
lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED
binman: Support packaging U-Boot for scenarios like OF_BOARD or
OF_PRIOR_STAGE
riscv: dts: Sort build targets in alphabetical order
riscv: qemu: Switch to use binman to generate u-boot.itb
riscv: ae350: Switch to use binman to generate u-boot.itb
riscv: Drop USE_SPL_FIT_GENERATOR
Makefile | 4 +-
arch/riscv/cpu/generic/Kconfig| 1 +
arch/riscv/dts/Makefile | 3 +-
arch/riscv/dts/ae350_32.dts | 2 +
arch/riscv/dts/ae350_64.dts | 2 +
arch/riscv/dts/binman.dtsi| 78 ++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 1 +
arch/riscv/dts/qemu-virt.dts | 8 ++
arch/riscv/lib/mkimage_fit_opensbi.sh | 100 --
board/AndesTech/ax25-ae350/Kconfig| 1 +
board/sifive/unleashed/Kconfig| 1 +
common/Kconfig.boot | 5 +-
configs/ae350_rv32_spl_defconfig | 1 +
configs/ae350_rv32_spl_xip_defconfig | 1 +
configs/ae350_rv64_spl_defconfig | 1 +
configs/ae350_rv64_spl_xip_defconfig | 1 +
configs/qemu-riscv32_spl_defconfig| 1 +
configs/qemu-riscv64_spl_defconfig| 1 +
dts/Kconfig | 18
lib/Kconfig | 2 +-
tools/binman/binman.rst | 28 -
tools/binman/entries.rst | 13 +++
tools/binman/etype/atf_bl31.py| 2 +-
tools/binman/etype/opensbi.py | 23
tools/binman/ftest.py | 17 ++-
.../test/{172_fit_fdt.dts => 170_fit_fdt.dts} | 0
tools/binman/test/201_opensbi.dts | 14 +++
27 files changed, 215 insertions(+), 114 deletions(-)
create mode 100644 arch/riscv/dts/binman.dtsi
create mode 100644 arch/riscv/dts/qemu-virt.dts
delete mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
create mode 100644 tools/binman/etype/opensbi.py
rename tools/binman/test/{172_fit_fdt.dts => 170_fit_fdt.dts} (100%)
create mode 100644 tools/binman/test/201_opensbi.dts
--
2.25.1
[PATCH v5 01/13] common: kconfig: Correct a typo in SPL_LOAD_FIT
It should be FDT, not FTD. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- (no changes since v1) common/Kconfig.boot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/Kconfig.boot b/common/Kconfig.boot index 5a18d62d78..94d82c27dd 100644 --- a/common/Kconfig.boot +++ b/common/Kconfig.boot @@ -204,7 +204,7 @@ config SPL_LOAD_FIT This path has the following limitations: - 1. "loadables" images, other than FTDs, which do not have a "load" + 1. "loadables" images, other than FDTs, which do not have a "load" property will not be loaded. This limitation also applies to FPGA images with the correct "compatible" string. 2. For FPGA images, only the "compatible" = "u-boot,fpga-legacy" -- 2.25.1
[PATCH v5 02/13] binman: Correct '-a' description in the doc
It needs a space around '-a'. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- (no changes since v1) tools/binman/binman.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index 1aa2459d50..b3df3a6428 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -322,9 +322,9 @@ Sometimes it is useful to pass binman the value of an entry property from the command line. For example some entries need access to files and it is not always convenient to put these filenames in the image definition (device tree). -The-a option supports this:: +The -a option supports this:: --a= +-a = where:: -- 2.25.1
[PATCH v5 03/13] binman: Correct the comment for ATF entry type
This is wrongly referring to Intel ME, which should be ATF. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- (no changes since v1) tools/binman/etype/atf_bl31.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/binman/etype/atf_bl31.py b/tools/binman/etype/atf_bl31.py index 163d714184..2041da416c 100644 --- a/tools/binman/etype/atf_bl31.py +++ b/tools/binman/etype/atf_bl31.py @@ -2,7 +2,7 @@ # Copyright 2020 Google LLC # Written by Simon Glass # -# Entry-type module for Intel Management Engine binary blob +# Entry-type module for ARM Trusted Firmware binary blob # from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg -- 2.25.1
[PATCH v5 04/13] binman: test: Rename 172_fit_fdt.dts to 170_fit_fdt.dts
Currently there are 2 binman test cases using the same 172 number.
It seems that 172_fit_fdt.dts was originally named as 170_, but
commit c0f1ebe9c1b9 ("binman: Allow selecting default FIT configuration")
changed its name to 172_ for no reason. Let's change it back.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v1)
tools/binman/ftest.py | 10 +-
tools/binman/test/{172_fit_fdt.dts => 170_fit_fdt.dts} | 0
2 files changed, 5 insertions(+), 5 deletions(-)
rename tools/binman/test/{172_fit_fdt.dts => 170_fit_fdt.dts} (100%)
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index f36823f51b..b0daccbc3b 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -3826,7 +3826,7 @@ class TestFunctional(unittest.TestCase):
'default-dt': 'test-fdt2',
}
data = self._DoReadFileDtb(
-'172_fit_fdt.dts',
+'170_fit_fdt.dts',
entry_args=entry_args,
extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):])
@@ -3848,7 +3848,7 @@ class TestFunctional(unittest.TestCase):
def testFitFdtMissingList(self):
"""Test handling of a missing 'of-list' entry arg"""
with self.assertRaises(ValueError) as e:
-self._DoReadFile('172_fit_fdt.dts')
+self._DoReadFile('170_fit_fdt.dts')
self.assertIn("Generator node requires 'of-list' entry argument",
str(e.exception))
@@ -3871,7 +3871,7 @@ class TestFunctional(unittest.TestCase):
entry_args = {
'of-list': '',
}
-data = self._DoReadFileDtb('172_fit_fdt.dts', entry_args=entry_args)[0]
+data = self._DoReadFileDtb('170_fit_fdt.dts', entry_args=entry_args)[0]
def testFitFdtMissing(self):
"""Test handling of a missing 'default-dt' entry arg"""
@@ -3880,7 +3880,7 @@ class TestFunctional(unittest.TestCase):
}
with self.assertRaises(ValueError) as e:
self._DoReadFileDtb(
-'172_fit_fdt.dts',
+'170_fit_fdt.dts',
entry_args=entry_args,
extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
self.assertIn("Generated 'default' node requires default-dt entry
argument",
@@ -3894,7 +3894,7 @@ class TestFunctional(unittest.TestCase):
}
with self.assertRaises(ValueError) as e:
self._DoReadFileDtb(
-'172_fit_fdt.dts',
+'170_fit_fdt.dts',
entry_args=entry_args,
extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
self.assertIn("default-dt entry argument 'test-fdt3' not found in fdt
list: test-fdt1, test-fdt2",
diff --git a/tools/binman/test/172_fit_fdt.dts
b/tools/binman/test/170_fit_fdt.dts
similarity index 100%
rename from tools/binman/test/172_fit_fdt.dts
rename to tools/binman/test/170_fit_fdt.dts
--
2.25.1
[PATCH v5 06/13] makefile: Pass OpenSBI blob to binman make rules
This updates the make rules to pass OpenSBI blob to binman.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v1)
Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/Makefile b/Makefile
index 404977efa5..3d88559b67 100644
--- a/Makefile
+++ b/Makefile
@@ -1287,6 +1287,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if
$(BINMAN_DEBUG),-D) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
-a atf-bl31-path=${BL31} \
+ -a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
--
2.25.1
[PATCH v5 05/13] binman: Add support for RISC-V OpenSBI fw_dynamic blob
Add an entry for RISC-V OpenSBI's 'fw_dynamic' firmware payload.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- drop "size = <16>" in the binman node
tools/binman/entries.rst | 13 +
tools/binman/etype/opensbi.py | 23 +++
tools/binman/ftest.py | 7 +++
tools/binman/test/201_opensbi.dts | 14 ++
4 files changed, 57 insertions(+)
create mode 100644 tools/binman/etype/opensbi.py
create mode 100644 tools/binman/test/201_opensbi.dts
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index f1c3b7de7a..dcac700c46 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -761,6 +761,19 @@ binman.
+Entry: opensbi: RISC-V OpenSBI fw_dynamic blob
+--
+
+Properties / Entry arguments:
+- opensbi-path: Filename of file to read into entry. This is typically
+called fw_dynamic.bin
+
+This entry holds the run-time firmware, typically started by U-Boot SPL.
+See the U-Boot README for your architecture or board for how to use it. See
+https://github.com/riscv/opensbi for more information about OpenSBI.
+
+
+
Entry: powerpc-mpc85xx-bootpg-resetvec: PowerPC mpc85xx bootpg + resetvec code
for U-Boot
-
diff --git a/tools/binman/etype/opensbi.py b/tools/binman/etype/opensbi.py
new file mode 100644
index 00..74d473d535
--- /dev/null
+++ b/tools/binman/etype/opensbi.py
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021, Bin Meng
+#
+# Entry-type module for RISC-V OpenSBI binary blob
+#
+
+from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
+
+class Entry_opensbi(Entry_blob_named_by_arg):
+"""RISC-V OpenSBI fw_dynamic blob
+
+Properties / Entry arguments:
+- opensbi-path: Filename of file to read into entry. This is typically
+called fw_dynamic.bin
+
+This entry holds the run-time firmware, typically started by U-Boot SPL.
+See the U-Boot README for your architecture or board for how to use it. See
+https://github.com/riscv/opensbi for more information about OpenSBI.
+"""
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node, 'opensbi')
+self.external = True
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index b0daccbc3b..5383eec489 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -76,6 +76,7 @@ FSP_M_DATA= b'fsp_m'
FSP_S_DATA= b'fsp_s'
FSP_T_DATA= b'fsp_t'
ATF_BL31_DATA = b'bl31'
+OPENSBI_DATA = b'opensbi'
SCP_DATA = b'scp'
TEST_FDT1_DATA= b'fdt1'
TEST_FDT2_DATA= b'test-fdt2'
@@ -178,6 +179,7 @@ class TestFunctional(unittest.TestCase):
TestFunctional._MakeInputFile('compress', COMPRESS_DATA)
TestFunctional._MakeInputFile('compress_big', COMPRESS_DATA_BIG)
TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA)
+TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA)
TestFunctional._MakeInputFile('scp.bin', SCP_DATA)
# Add a few .dtb files for testing
@@ -4535,5 +4537,10 @@ class TestFunctional(unittest.TestCase):
expected += tools.GetBytes(0, 88 - len(expected)) + U_BOOT_NODTB_DATA
self.assertEqual(expected, data)
+def testPackOpenSBI(self):
+"""Test that an image with an OpenSBI binary can be created"""
+data = self._DoReadFile('201_opensbi.dts')
+self.assertEqual(OPENSBI_DATA, data[:len(OPENSBI_DATA)])
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/binman/test/201_opensbi.dts
b/tools/binman/test/201_opensbi.dts
new file mode 100644
index 00..942183f990
--- /dev/null
+++ b/tools/binman/test/201_opensbi.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ opensbi {
+ filename = "fw_dynamic.bin";
+ };
+ };
+};
--
2.25.1
[PATCH v5 09/13] binman: Support packaging U-Boot for scenarios like OF_BOARD or OF_PRIOR_STAGE
For scenarios like OF_BOARD or OF_PRIOR_STAGE, no device tree blob is provided in the U-Boot build phase hence the binman node information is not available. In order to support such use case, a new Kconfig option BINMAN_STANDALONE_FDT is introduced, to tell the build system that a device tree blob containing binman node is explicitly required when using binman to package U-Boot. Signed-off-by: Bin Meng --- Changes in v5: - update binman.rst for OF_BOARD or OF_PRIOR_STAGE usage Changes in v4: - update the makefile dependency on u-boot.img instead of u-boot.bin Changes in v3: - rename the Kconfig option name to BINMAN_STANDALONE_FDT - make BINMAN_STANDALONE_FDT default y for OF_BOARD as well - reword the Kconfig option help message a little bit Changes in v2: - new patch: "binman: Support packaging U-Boot for scenarios like OF_PRIOR_STAGE" Makefile| 3 ++- dts/Kconfig | 18 ++ tools/binman/binman.rst | 24 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3d88559b67..1dbf0b0b8c 100644 --- a/Makefile +++ b/Makefile @@ -918,6 +918,7 @@ endif endif INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb +INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb ifeq ($(CONFIG_SPL_FRAMEWORK),y) INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img endif @@ -1392,7 +1393,7 @@ u-boot-lzma.img: u-boot.bin.lzma FORCE u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \ $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \ - $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \ ,$(UBOOT_BIN)) FORCE $(call if_changed,mkimage) $(BOARD_SIZE_CHECK) diff --git a/dts/Kconfig b/dts/Kconfig index 99ce75e1a2..dabe0080c1 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -19,6 +19,24 @@ config BINMAN bool select DTOC +config BINMAN_STANDALONE_FDT + bool + depends on BINMAN + default y if OF_BOARD || OF_PRIOR_STAGE + help + This option tells U-Boot build system that a standalone device tree + source is explicitly required when using binman to package U-Boot. + + This is not necessary in a common scenario where a device tree source + that contains the binman node is provided in the arch//dts + directory for a specific board. Such device tree sources are built for + OF_SEPARATE or OF_EMBED. However for a scenario like the board device + tree blob is not provided in the U-Boot build tree, but fed to U-Boot + in the runtime, e.g.: in the OF_PRIOR_STAGE case that it is passed by + a prior stage bootloader. For such scenario, a standalone device tree + blob containing binman node to describe how to package U-Boot should + be provided explicitly. + menu "Device Tree Control" depends on SUPPORT_OF_CONTROL diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index b3df3a6428..bc635aa00a 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -232,6 +232,30 @@ You can use other, more specific CONFIG options - see 'Automatic .dtsi inclusion' below. +Using binman with OF_BOARD or OF_PRIOR_STAGE + + +Normally binman is used with a board configured with OF_SEPARATE or OF_EMBED. +This is a typical scenario where a device tree source that contains the binman +node is provided in the arch//dts directory for a specific board. + +However for a board configured with OF_BOARD or OF_PRIOR_STAGE, no device tree +blob is provided in the U-Boot build phase hence the binman node information +is not available. In order to support such use case, a new Kconfig option +BINMAN_STANDALONE_FDT is introduced, to tell the build system that a standalone +device tree blob containing binman node is explicitly required. + +Note there is a Kconfig option BINMAN_FDT which enables U-Boot run time to +access information about binman entries, stored in the device tree in a binman +node. Generally speaking, this option makes sense for OF_SEPARATE or OF_EMBED. +For the other OF_CONTROL methods, it's quite possible binman node is not +available as binman is invoked during the build phase, thus this option is not +turned on by default for these OF_CONTROL methods. + +See qemu-riscv64_spl_defconfig for an example of how binman is used with +OF_PRIOR_STAGE to generate u-boot.itb image. + + Access to binman entry offsets at run time (symbols) -- 2.25.1
[PATCH v5 07/13] riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb
At present SiFive Unleashed board uses the Makefile to create the FIT,
using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
warning. Update to use binman instead.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v3)
Changes in v3:
- Fix the opensbi entry type in binman.dtsi
arch/riscv/dts/binman.dtsi| 70 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 1 +
board/sifive/unleashed/Kconfig| 1 +
configs/sifive_unleashed_defconfig| 1 +
4 files changed, 73 insertions(+)
create mode 100644 arch/riscv/dts/binman.dtsi
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
new file mode 100644
index 00..e02597e73d
--- /dev/null
+++ b/arch/riscv/dts/binman.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng
+ */
+
+#include
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load OpenSBI before
U-Boot";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+
+ images {
+ uboot {
+ description = "U-Boot";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "riscv";
+ compression = "none";
+ load = ;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ opensbi {
+ description = "OpenSBI fw_dynamic
Firmware";
+ type = "firmware";
+ os = "opensbi";
+ arch = "riscv";
+ compression = "none";
+ load = ;
+ entry = ;
+
+ opensbi_blob: opensbi {
+ filename = "fw_dynamic.bin";
+ };
+ };
+
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "conf-1";
+
+ @conf-SEQ {
+ description = "NAME";
+ firmware = "opensbi";
+ loadables = "uboot";
+ fdt = "fdt-SEQ";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 1996149c95..51b566116d 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) 2019 Jagan Teki
*/
+#include "binman.dtsi"
#include "fu540-c000-u-boot.dtsi"
#include "fu540-hifive-unleashed-a00-ddr.dtsi"
diff --git a/board/sifive/unleashed/Kconfig b/board/sifive/unleashed/Kconfig
index dbffd59c98..502916e86a 100644
--- a/board/sifive/unleashed/Kconfig
+++ b/board/sifive/unleashed/Kconfig
@@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SIFIVE_FU540
select ENV_IS_IN_SPI_FLASH
+ select BINMAN
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
diff --git a/configs/sifive_unleashed_defconfig
b/configs/sifive_unleashed_defconfig
index 62416a7c1d..dc9313e572 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -14,6 +14,7 @@ CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8400
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_MISC_INIT_R=y
--
2.25.1
[PATCH v5 10/13] riscv: dts: Sort build targets in alphabetical order
Sort the RISC-V DTS build targets by their Kconfig target names in alphabetical order. Signed-off-by: Bin Meng --- (no changes since v2) Changes in v2: - new patch: "riscv: dts: Sort build targets in alphabetical order" arch/riscv/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 8138d89d84..3780334875 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb -dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb targets += $(dtb-y) -- 2.25.1
[PATCH v5 11/13] riscv: qemu: Switch to use binman to generate u-boot.itb
By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along
with a new dedicated device tree source file for the QEMU virt target
used for binman only, we can now use binman to generate u-boot.itb.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- new patch: "riscv: qemu: Switch to use binman to generate u-boot.itb"
arch/riscv/cpu/generic/Kconfig | 1 +
arch/riscv/dts/Makefile| 1 +
arch/riscv/dts/binman.dtsi | 8
arch/riscv/dts/qemu-virt.dts | 8
configs/qemu-riscv32_spl_defconfig | 2 ++
configs/qemu-riscv64_spl_defconfig | 2 ++
6 files changed, 22 insertions(+)
create mode 100644 arch/riscv/dts/qemu-virt.dts
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index 198e36e969..a4934bb957 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -4,6 +4,7 @@
config GENERIC_RISCV
bool
+ select BINMAN if SPL
select ARCH_EARLY_INIT_R
imply CPU
imply CPU_RISCV
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3780334875..26ef853282 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index e02597e73d..d26cfdb78a 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -48,21 +48,29 @@
};
};
+#ifndef CONFIG_OF_PRIOR_STAGE
@fdt-SEQ {
description = "NAME";
type = "flat_dt";
compression = "none";
};
+#endif
};
configurations {
default = "conf-1";
+#ifndef CONFIG_OF_PRIOR_STAGE
@conf-SEQ {
+#else
+ conf-1 {
+#endif
description = "NAME";
firmware = "opensbi";
loadables = "uboot";
+#ifndef CONFIG_OF_PRIOR_STAGE
fdt = "fdt-SEQ";
+#endif
};
};
};
diff --git a/arch/riscv/dts/qemu-virt.dts b/arch/riscv/dts/qemu-virt.dts
new file mode 100644
index 00..fecff542b9
--- /dev/null
+++ b/arch/riscv/dts/qemu-virt.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
diff --git a/configs/qemu-riscv32_spl_defconfig
b/configs/qemu-riscv32_spl_defconfig
index 18dfe33ca8..a4c156612a 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -2,11 +2,13 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8020
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_MII is not set
diff --git a/configs/qemu-riscv64_spl_defconfig
b/configs/qemu-riscv64_spl_defconfig
index 897adf6a29..6c680483ce 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -2,12 +2,14 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8020
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_MII is not set
--
2.25.1
[PATCH v5 08/13] lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED
Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED. For the other OF_CONTROL methods, it's quite possible binman node is not available as binman is invoked during the build phase instead of runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default. Signed-off-by: Bin Meng --- (no changes since v3) Changes in v3: - new patch: "lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED" lib/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Kconfig b/lib/Kconfig index 6d2d41de30..7d5990c940 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -25,7 +25,7 @@ config BCH config BINMAN_FDT bool "Allow access to binman information in the device tree" depends on BINMAN && DM && OF_CONTROL - default y + default y if OF_SEPARATE || OF_EMBED help This enables U-Boot to access information about binman entries, stored in the device tree in a binman node. Typical uses are to -- 2.25.1
[PATCH v5 12/13] riscv: ae350: Switch to use binman to generate u-boot.itb
Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs,
so that binman is now used to generate u-boot.itb.
Signed-off-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- new patch: "riscv: ae350: Switch to use binman to generate u-boot.itb"
arch/riscv/dts/ae350_32.dts | 2 ++
arch/riscv/dts/ae350_64.dts | 2 ++
board/AndesTech/ax25-ae350/Kconfig | 1 +
configs/ae350_rv32_spl_defconfig | 2 ++
configs/ae350_rv32_spl_xip_defconfig | 2 ++
configs/ae350_rv64_spl_defconfig | 2 ++
configs/ae350_rv64_spl_xip_defconfig | 2 ++
7 files changed, 13 insertions(+)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 3f8525fe56..a0ab5e9be2 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -1,5 +1,7 @@
/dts-v1/;
+#include "binman.dtsi"
+
/ {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 482c707503..f654f4809a 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -1,5 +1,7 @@
/dts-v1/;
+#include "binman.dtsi"
+
/ {
#address-cells = <2>;
#size-cells = <2>;
diff --git a/board/AndesTech/ax25-ae350/Kconfig
b/board/AndesTech/ax25-ae350/Kconfig
index 321dd0cb10..e50f505a2b 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
select SUPPORT_SPL
+ select BINMAN if SPL
imply SMP
imply SPL_RAM_SUPPORT
imply SPL_RAM_DEVICE
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 153266f647..47c8e9a621 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -3,11 +3,13 @@ CONFIG_SYS_TEXT_BASE=0x0120
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
diff --git a/configs/ae350_rv32_spl_xip_defconfig
b/configs/ae350_rv32_spl_xip_defconfig
index 651b1eb733..206ffe2720 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -4,12 +4,14 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_TEXT_BASE=0x8000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index f434091d47..ef04e4a4b6 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -3,12 +3,14 @@ CONFIG_SYS_TEXT_BASE=0x0120
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
diff --git a/configs/ae350_rv64_spl_xip_defconfig
b/configs/ae350_rv64_spl_xip_defconfig
index b0afdb4cfe..21b7e8895b 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -4,6 +4,7 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_TEXT_BASE=0x8000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
@@ -11,6 +12,7 @@ CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
--
2.25.1
[PATCH v5 13/13] riscv: Drop USE_SPL_FIT_GENERATOR
Now that we have switched to binman to generate u-boot.itb for all
RISC-V boards, USE_SPL_FIT_GENERATOR is no longer needed and can
be dropped.
Signed-off-by: Bin Meng
---
(no changes since v3)
Changes in v3:
- remove USE_SPL_FIT_GENERATOR in ae350_ defconfigs
Changes in v2:
- new patch: "riscv: Drop USE_SPL_FIT_GENERATOR"
arch/riscv/lib/mkimage_fit_opensbi.sh | 100 --
common/Kconfig.boot | 3 +-
configs/ae350_rv32_spl_defconfig | 1 -
configs/ae350_rv32_spl_xip_defconfig | 1 -
configs/ae350_rv64_spl_defconfig | 1 -
configs/ae350_rv64_spl_xip_defconfig | 1 -
configs/qemu-riscv32_spl_defconfig| 1 -
configs/qemu-riscv64_spl_defconfig| 1 -
configs/sifive_unleashed_defconfig| 1 -
9 files changed, 1 insertion(+), 109 deletions(-)
delete mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
diff --git a/arch/riscv/lib/mkimage_fit_opensbi.sh
b/arch/riscv/lib/mkimage_fit_opensbi.sh
deleted file mode 100755
index d6f95e5bfd..00
--- a/arch/riscv/lib/mkimage_fit_opensbi.sh
+++ /dev/null
@@ -1,100 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0+
-#
-# script to generate FIT image source for RISC-V boards with OpenSBI
-# and, optionally, multiple device trees (given on the command line).
-#
-# usage: $0 [ [&2
- OPENSBI=/dev/null
-fi
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
- description = "Configuration to load OpenSBI before U-Boot";
-
- images {
- uboot {
- description = "U-Boot";
- data = /incbin/("u-boot-nodtb.bin");
- type = "standalone";
- os = "U-Boot";
- arch = "riscv";
- compression = "none";
- load = <$UBOOT_LOAD_ADDR>;
- };
- opensbi {
- description = "RISC-V OpenSBI";
- data = /incbin/("$OPENSBI");
- type = "firmware";
- os = "opensbi";
- arch = "riscv";
- compression = "none";
- load = <$OPENSBI_LOAD_ADDR>;
- entry = <$OPENSBI_LOAD_ADDR>;
- };
-__HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
- cat << __FDT_IMAGE_EOF
- fdt_$cnt {
- description = "$(basename $dtname .dtb)";
- data = /incbin/("$dtname");
- type = "flat_dt";
- compression = "none";
- };
-__FDT_IMAGE_EOF
-cnt=$((cnt+1))
-done
-
-cat << __CONF_HEADER_EOF
- };
- configurations {
- default = "config_1";
-
-__CONF_HEADER_EOF
-
-if [ $# -eq 0 ]; then
-cat << __CONF_SECTION_EOF
- config_1 {
- description = "U-Boot FIT";
- firmware = "opensbi";
- loadables = "uboot";
- };
-__CONF_SECTION_EOF
-else
-cnt=1
-for dtname in $*
-do
-cat << __CONF_SECTION_EOF
- config_$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt_$cnt";
- };
-__CONF_SECTION_EOF
-cnt=$((cnt+1))
-done
-fi
-
-cat << __ITS_EOF
- };
-};
-__ITS_EOF
diff --git a/common/Kconfig.boot b/common/Kconfig.boot
index 94d82c27dd..89a3161f1f 100644
--- a/common/Kconfig.boot
+++ b/common/Kconfig.boot
@@ -273,14 +273,13 @@ config SPL_FIT_SOURCE
config USE_SPL_FIT_GENERATOR
bool "Use a script to generate the .its script"
- default y if SPL_FIT && !ARCH_SUNXI
+ default y if SPL_FIT && (!ARCH_SUNXI && !RISCV)
config SPL_FIT_GENERATOR
string ".its file generator script for U-Boot FIT image"
depends on USE_SPL_FIT_GENERATOR
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT &&
ARCH_ROCKCHIP
default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT &&
ARCH_ZYNQMP
- default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
Specifies a (platform specific) script file to generate the FIT
source file used to build the U-Boot FIT image file. This gets
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 47c8e9a621..25b4ada427 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -9,7 +9,6 @@ CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020
-# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="RISC-V # "
diff --git a/configs/ae350_rv32_spl_xip_defconfig
b/configs/ae350_rv32_spl_xip_defconfig
index 206ffe2720..c5d7ac3bc1 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv
Re: [PATCH 03/17] sandbox: Indicate NULL-pointer access in 'sigsegv' command
On Sat, May 08, 2021 at 04:00:07PM -0600, Simon Glass wrote:
> This is intended to crash. Add an annotation to keep coverity happy.
>
> Reported-by: Coverity (CID: 316347)
>
> Signed-off-by: Simon Glass
> ---
>
> cmd/sandbox/exception.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/cmd/sandbox/exception.c b/cmd/sandbox/exception.c
> index 1aa1d673aed..d865922e863 100644
> --- a/cmd/sandbox/exception.c
> +++ b/cmd/sandbox/exception.c
> @@ -13,7 +13,9 @@ static int do_sigsegv(struct cmd_tbl *cmdtp, int flag, int
> argc,
> {
> u8 *ptr = NULL;
>
> + /* coverity[FORWARD_NULL] */
> *ptr = 0;
> +
> return CMD_RET_FAILURE;
For here and later on in the series, I would rather just mark some as
intentional in the dashboard and if it makes sense and isn't obvious
from the code (so not here, but elsewhere in this series) a comment
saying why we're doing something a static analysis tool is going to
catch. Thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v9 00/28] mtd: spi-nor-core: add xSPI Octal DTR support
Jagan, On 05/05/21 03:11PM, Pratyush Yadav wrote: > Hi, > > This series adds support for octal DTR flashes in the SPI NOR framework, > and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA > flashes. > > The Cadence QSPI controller driver is also updated to run in Octal DTR > mode. > > Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Also tested > on MT25QU512A for regressions. Can you please pick this series up as soon as possible? It makes lots of changes to the SPI NOR core. Let's cook this in next for a while to catch out any issues. This would avoid surprises close to the merge window. -- Regards, Pratyush Yadav Texas Instruments Inc.
Re: [PATCH] mmc: sdhci: Write to HOST_CONTROL2 register for HS400 speed mode
Hi Peng, On 07/04/21 3:52 am, Jaehoon Chung wrote: > On 4/5/21 11:44 PM, Aswath Govindraju wrote: >> From: Faiz Abbas >> >> Enable HS400 speed mode by writing to HOST_CONTROL2 register. >> >> Signed-off-by: Faiz Abbas >> Signed-off-by: Aswath Govindraju > > Reviewed-by: Jaehoon Chung > Can you please pick this patch if there are no comments. Thanks, Aswath > Best Regards, > Jaehoon Chung > >> --- >> drivers/mmc/sdhci.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c >> index d9ab6a0a839e..eea4701d8af5 100644 >> --- a/drivers/mmc/sdhci.c >> +++ b/drivers/mmc/sdhci.c >> @@ -507,6 +507,9 @@ void sdhci_set_uhs_timing(struct sdhci_host *host) >> case MMC_HS_200: >> reg |= SDHCI_CTRL_UHS_SDR104; >> break; >> +case MMC_HS_400: >> +reg |= SDHCI_CTRL_HS400; >> +break; >> default: >> reg |= SDHCI_CTRL_UHS_SDR12; >> } >> >
[PATCH 00/10] arm64: zynqmp: Add support for KRIA boards and update phy/pinctrl descs
Hi, this patchset is adding support for new Xilinx SOM platform. SOM+CC. Also adding description for pin control and PSGTR phys with also some small fixes in DT. Thanks, Michal Michal Simek (6): arm64: zynqmp: Add missing silabs,skip-recall for si570 ref clk nodes arm64: zynqmp: Remove comment about clock chips arm64: zynqmp: Add missing mio-bank properties to sdhci arm64: zynqmp: Add pinctrl description arm64: zynqmp: Add psgtr DT descriptions arm64: zynqmp: Add description for SOM/Kria boards Raviteja Narayanam (1): arm64: zynqmp: Add 'i2c-mux-idle-disconnect' property Saeed Nowshadi (2): arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk node arm64: zynqmp: Add label to all GPIO lines for VCK190 SC T Karthik Reddy (1): arm64: zynqmp: Add zynqmp firmware specific DT nodes arch/arm/dts/Makefile| 4 + arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 20 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 3 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 3 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 3 +- arch/arm/dts/zynqmp-mini-emmc0.dts | 40 ++ arch/arm/dts/zynqmp-mini-emmc1.dts | 40 ++ arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 23 ++ arch/arm/dts/zynqmp-sck-kv-g-revA.dts| 373 +++ arch/arm/dts/zynqmp-sck-kv-g-revB.dts| 353 ++ arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi | 21 ++ arch/arm/dts/zynqmp-sm-k26-revA.dts | 316 arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi | 21 ++ arch/arm/dts/zynqmp-smk-k26-revA.dts | 21 ++ arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 260 + arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 306 +++ arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 330 arch/arm/dts/zynqmp-zcu100-revC.dts | 242 +++- arch/arm/dts/zynqmp-zcu102-revA.dts | 290 ++ arch/arm/dts/zynqmp-zcu104-revA.dts | 218 +++ arch/arm/dts/zynqmp-zcu104-revC.dts | 218 +++ arch/arm/dts/zynqmp-zcu106-revA.dts | 290 ++ arch/arm/dts/zynqmp-zcu111-revA.dts | 234 +++- arch/arm/dts/zynqmp-zcu208-revA.dts | 83 - arch/arm/dts/zynqmp-zcu216-revA.dts | 83 - configs/xilinx_zynqmp_virt_defconfig | 2 +- include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 + 27 files changed, 3792 insertions(+), 24 deletions(-) create mode 100644 arch/arm/dts/zynqmp-sck-kv-g-revA.dts create mode 100644 arch/arm/dts/zynqmp-sck-kv-g-revB.dts create mode 100644 arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi create mode 100644 arch/arm/dts/zynqmp-sm-k26-revA.dts create mode 100644 arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi create mode 100644 arch/arm/dts/zynqmp-smk-k26-revA.dts create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h -- 2.31.1
[PATCH 01/10] arm64: zynqmp: Add missing silabs, skip-recall for si570 ref clk nodes
All si570 which are used for ps reference clock generation should contain silabs,skip-recall property not to cause break on ps clock. On Versal boards this will cause hang on Versal cpu when it is booted at the same time with SC. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 1 + arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 3 ++- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 3 ++- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 3 ++- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 1 + 5 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index aae3c626f562..135c83f502e8 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -475,6 +475,7 @@ factory-fout = <>; clock-frequency = <>; clock-output-names = "ref_clk"; + silabs,skip-recall; }; /* and connector J212D */ }; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 19e1ebdb1d6a..213149a3dc83 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -343,9 +343,10 @@ compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; - factory-fout = <15625>; /* FIXME every chip can be different */ + factory-fout = <>; clock-frequency = <>; clock-output-names = "REF_CLK"; /* FIXME */ + silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 46ec427648fa..c458110e5a89 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -349,9 +349,10 @@ compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; - factory-fout = <15625>; /* FIXME every chip can be different */ + factory-fout = <>; clock-frequency = <>; clock-output-names = "REF_CLK"; /* FIXME */ + silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 6eb58e6701ad..cee7ca1fa995 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -339,9 +339,10 @@ compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; - factory-fout = <15625>; /* FIXME every chip can be different */ + factory-fout = <>; clock-frequency = <>; clock-output-names = "REF_CLK"; /* FIXME */ + silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 4f7824ae4007..8e1e6b7f903b 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -390,6 +390,7 @@ factory-fout = <>; clock-frequency = <>; clock-output-names = "ref_clk"; + silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ -- 2.31.1
[PATCH 04/10] arm64: zynqmp: Add 'i2c-mux-idle-disconnect' property
From: Raviteja Narayanam
I2C muxes that have the slave devices with same address are
falling into the below problem.
VCK190 system controller (SC) - zynqmp-e-a2197-00-revA.dts
I2C1 (0xff03) -> Mux1 (@0x74) -> Channel 3 -> 0x50
I2C1 (0xff03) -> Mux2 (@0x75) -> Channel 0 -> 0x50
1. SC accesses I2C1 - Mux1 (0x74) - Channel 3 and then
2. SC accesses I2C1 - Mux2 (0x75) - Channel 0.
Now it results in 2 slave devices with same address (0x50)
on the I2C bus, making the communication un-reliable.
When ' i2c-mux-idle-disconnect' is in DT, after '1', the Mux
channel output is disconnected, making none of the channels
available to the I2C1. So, there is no question of having the
same addressed slave (0x50) present on the bus when we are doing '2'.
Same pattern is seen in below two boards also.
ZCU208 - zynqmp-zcu208-revA.dts
ZCU216 - zynqmp-zcu216-revA.dts
Signed-off-by: Raviteja Narayanam
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu208-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu216-revA.dts | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index ffa3dbb5f71f..8ec2e866535b 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -457,6 +457,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
+ i2c-mux-idle-disconnect;
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B
GPIO_ACTIVE_HIGH>; */
dc_i2c: i2c@0 { /* DC_I2C */
#address-cells = <1>;
@@ -561,6 +562,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
+ i2c-mux-idle-disconnect;
i2c@0 { /* SFP0_IIC */
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts
b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 0e114cdacb1a..c24301090dde 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -388,6 +388,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B
GPIO_ACTIVE_HIGH>; */
i2c_eeprom: i2c@0 {
#address-cells = <1>;
@@ -504,6 +505,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B
GPIO_ACTIVE_HIGH>; */
i2c@0 {
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts
b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 2302b07c4825..675baf4bed61 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -399,6 +399,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B
GPIO_ACTIVE_HIGH>; */
i2c_eeprom: i2c@0 {
#address-cells = <1>;
@@ -515,6 +516,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B
GPIO_ACTIVE_HIGH>; */
i2c@0 {
#address-cells = <1>;
--
2.31.1
[PATCH 02/10] arm64: zynqmp: Add 'silabs, skip-recall' to DDR DIMM si570 clk node
From: Saeed Nowshadi
The 'silabs,skip-recall' property prevents interruption in operation of
the clock while the driver is being probed. Without this property, the
DDR DIMM clk can cause a failure during Versal's boot.
Signed-off-by: Saeed Nowshadi
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 135c83f502e8..e5d75e552346 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx Versal a2197 RevA System Controller
*
- * (C) Copyright 2019 - 2020, Xilinx, Inc.
+ * (C) Copyright 2019 - 2021, Xilinx, Inc.
*
* Michal Simek
*/
@@ -505,6 +505,7 @@
factory-fout = <2>;
clock-frequency = <2>;
clock-output-names = "si570_ddrdimm1_clk";
+ silabs,skip-recall;
};
};
i2c@4 { /* LPDDR4_SI570_CLK2 */
--
2.31.1
[PATCH 05/10] arm64: zynqmp: Remove comment about clock chips
These comments weren't push to mainline that's why remove them.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zcu208-revA.dts | 10 +-
arch/arm/dts/zynqmp-zcu216-revA.dts | 10 +-
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts
b/arch/arm/dts/zynqmp-zcu208-revA.dts
index c24301090dde..cd2f02f21de5 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -424,27 +424,27 @@
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz
*/
reg = <9>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
};
};
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts
b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 675baf4bed61..8aecb1529250 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -435,27 +435,27 @@
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz
*/
reg = <9>;
- always-on; /* assigned-clocks does not
enable, so do it here */
+ always-on;
};
};
};
--
2.31.1
[PATCH 06/10] arm64: zynqmp: Add missing mio-bank properties to sdhci
Add missing xlnx,mio-bank property to sdhci node. Also add properties with
0 value to have it listed in case that files are copied to different
projects where default case doesn't need to be handled in the same way.
That's why explicitly list them too.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 8d8ebeaac3bf..0f1094804d91 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -93,6 +93,7 @@
&sdhci0 {
status = "okay";
no-1-8-v;
+ xlnx,mio-bank = <0>;
};
&ttc0 {
--
2.31.1
[PATCH 03/10] arm64: zynqmp: Add label to all GPIO lines for VCK190 SC
From: Saeed Nowshadi Add label to GPIO lines so the user-level applications can find any line without knowing its physical path on System Controller on VCK190/VMK180. These labels are describing EMIO gpio connection which depends on PL which we normally don't describe but that's only way to go for now. Lately this should be done out of this source code. Signed-off-by: Saeed Nowshadi Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index e5d75e552346..ffa3dbb5f71f 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -163,20 +163,20 @@ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ - "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 - 89 */ - "", "", "", "", "", /* 90 - 94 */ - "", "", "", "", "", /* 95 - 99 */ + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ + "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ + "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ + "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ - "", "", "", "", "", /* 130 - 134 */ + "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ - "", "", "", "", "", /* 140 - 144 */ - "", "", "", "", "", /* 145 - 149 */ + "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ + "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ -- 2.31.1
[PATCH 07/10] arm64: zynqmp: Add zynqmp firmware specific DT nodes
From: T Karthik Reddy
Probe zynqmp firmware driver by adding zynqmp firmware, power &
ipi mailbox device tree nodes for mini emmc.
Signed-off-by: T Karthik Reddy
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-mini-emmc0.dts | 40 ++
arch/arm/dts/zynqmp-mini-emmc1.dts | 40 ++
2 files changed, 80 insertions(+)
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts
b/arch/arm/dts/zynqmp-mini-emmc0.dts
index 8467dd8e1cc7..8d9f9ca37259 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -41,6 +41,46 @@
clock-frequency = <2>;
};
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ #power-domain-cells = <1>;
+ method = "smc";
+ u-boot,dm-pre-reloc;
+
+ zynqmp_power: zynqmp-power {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-power";
+ mboxes = <&ipi_mailbox_pmu1 0>,
+<&ipi_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
+ };
+
+ zynqmp_ipi: zynqmp_ipi {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ xlnx,ipi-id = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipi_mailbox_pmu1: mailbox@ff990400 {
+ u-boot,dm-pre-reloc;
+ reg = <0x0 0xff9905c0 0x0 0x20>,
+ <0x0 0xff9905e0 0x0 0x20>,
+ <0x0 0xff990e80 0x0 0x20>,
+ <0x0 0xff990ea0 0x0 0x20>;
+ reg-names = "local_request_region",
+ "local_response_region",
+ "remote_request_region",
+ "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <4>;
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts
b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 2afcc7751b9f..5722b762d679 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -41,6 +41,46 @@
clock-frequency = <2>;
};
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ #power-domain-cells = <1>;
+ method = "smc";
+ u-boot,dm-pre-reloc;
+
+ zynqmp_power: zynqmp-power {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-power";
+ mboxes = <&ipi_mailbox_pmu1 0>,
+<&ipi_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
+ };
+
+ zynqmp_ipi: zynqmp_ipi {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ xlnx,ipi-id = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipi_mailbox_pmu1: mailbox@ff990400 {
+ u-boot,dm-pre-reloc;
+ reg = <0x0 0xff9905c0 0x0 0x20>,
+ <0x0 0xff9905e0 0x0 0x20>,
+ <0x0 0xff990e80 0x0 0x20>,
+ <0x0 0xff990ea0 0x0 0x20>;
+ reg-names = "local_request_region",
+ "local_response_region",
+ "remote_request_region",
+ "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <4>;
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
--
2.31.1
[PATCH 09/10] arm64: zynqmp: Add psgtr DT descriptions
Mainline kernel has psgtr driver that's why it is good to add description
to DT files. Some boards are just missing description for USB3 and sata.
zc1751-dc1 and p-a2197 are also missing clock descriptions for input
clocks.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 22 +
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 31
arch/arm/dts/zynqmp-zcu100-revC.dts | 4 +++
arch/arm/dts/zynqmp-zcu102-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu104-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu104-revC.dts | 2 ++
arch/arm/dts/zynqmp-zcu106-revA.dts | 2 ++
arch/arm/dts/zynqmp-zcu111-revA.dts | 9 ++-
arch/arm/dts/zynqmp-zcu208-revA.dts | 3 +++
arch/arm/dts/zynqmp-zcu216-revA.dts | 3 +++
10 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index 8e1e6b7f903b..1f5201ac8883 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -11,6 +11,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include
+#include
/ {
model = "Versal System Controller on a2197 Processor Char board RevA";
/* Tenzing */
@@ -43,6 +44,18 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x8000>;
};
+
+ si5332_1: si5332_1 { /* clk0_sgmii - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <>; /* FIXME */
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2700>;
+ };
};
&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
@@ -70,6 +83,13 @@
xlnx,mio-bank = <1>;
};
+&psgtr {
+ status = "okay";
+ /* sgmii, usb3 */
+ clocks = <&si5332_1>, <&si5332_2>;
+ clock-names = "ref0", "ref1";
+};
+
&gem0 {
status = "okay";
phy-handle = <&phy0>;
@@ -537,6 +557,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
maximum-speed = "super-speed";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
};
&usb1 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index d5862c1cabe9..039a8da1a960 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -11,6 +11,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include
#include
#include
@@ -39,6 +40,31 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x8000>, <0x8 0x 0x0 0x8000>;
};
+
+ clock_si5338_0: clk27 { /* u55 SI5338-GM */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2700>;
+ };
+
+ clock_si5338_2: clk26 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ };
+
+ clock_si5338_3: clk150 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <15000>;
+ };
+};
+
+&psgtr {
+ status = "okay";
+ /* dp, usb3, sata */
+ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
+ clock-names = "ref1", "ref2", "ref3";
};
&fpd_dma_chan1 {
@@ -363,6 +389,8 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* eMMC */
@@ -402,6 +430,9 @@
&dwc3_0 {
status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&zynqmp_dpdma {
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts
b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 9603043db109..b83696cccd2b 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -567,6 +567,8 @@
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
maximum-speed = "super-speed";
};
@@ -580,6 +582,8 @@
&dwc3_1 {
status = "okay";
dr_mode = "host";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
maximum-speed = "super-speed";
};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 27c3dcc87f96..ec61b7089da2 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -1034,6 +1034,8 @@
status = "okay";
dr_mod
[PATCH 08/10] arm64: zynqmp: Add pinctrl description
ZynqMP pinctrl Linux driver has been merged to 5.13-rc1 kernel. Based on it
DT files can be extended by pinctrl configurations.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 229 +
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 306 +
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 329 +++
arch/arm/dts/zynqmp-zcu100-revC.dts | 238 +-
arch/arm/dts/zynqmp-zcu102-revA.dts | 288
arch/arm/dts/zynqmp-zcu104-revA.dts | 216
arch/arm/dts/zynqmp-zcu104-revC.dts | 216
arch/arm/dts/zynqmp-zcu106-revA.dts | 288
arch/arm/dts/zynqmp-zcu111-revA.dts | 225 +
arch/arm/dts/zynqmp-zcu208-revA.dts | 68
arch/arm/dts/zynqmp-zcu216-revA.dts | 68
include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 ++
12 files changed, 2489 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index b8c5efb6a914..d5862c1cabe9 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -11,6 +11,8 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include
+#include
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
@@ -75,6 +77,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@0 {
reg = <0>;
};
@@ -82,6 +86,8 @@
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -91,6 +97,11 @@
&i2c1 {
status = "okay";
clock-frequency = <40>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
eeprom: eeprom@55 {
compatible = "atmel,24c64"; /* 24AA64 */
@@ -98,6 +109,216 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_9_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_9_grp";
+ bias-pull-up;
+ slew-rate = ;
+ power-source = ;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ slew-rate = ;
+ power-source = ;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_8_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_8_grp";
+ slew-rate = ;
+ power-source = ;
+ };
+
+ conf-rx {
+ pins = "MIO34";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO35";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = ;
+ power-source = ;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = ;
+ power-source = ;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+
[PATCH 10/10] arm64: zynqmp: Add description for SOM/Kria boards
The patch contains several DT files for SOM platform.
Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter
kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC.
Files are divided in this way to make sure that SOM can be plugged to
different carrier card and all peripherals on SOM (or defined by a spec) can
be used by U-Boot. Full DT for SOM+CC can be merged together as overlays.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile| 4 +
arch/arm/dts/zynqmp-sck-kv-g-revA.dts| 373 +++
arch/arm/dts/zynqmp-sck-kv-g-revB.dts| 353 ++
arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi | 21 ++
arch/arm/dts/zynqmp-sm-k26-revA.dts | 316
arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi | 21 ++
arch/arm/dts/zynqmp-smk-k26-revA.dts | 21 ++
configs/xilinx_zynqmp_virt_defconfig | 2 +-
8 files changed, 1110 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynqmp-sck-kv-g-revA.dts
create mode 100644 arch/arm/dts/zynqmp-sck-kv-g-revB.dts
create mode 100644 arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
create mode 100644 arch/arm/dts/zynqmp-sm-k26-revA.dts
create mode 100644 arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
create mode 100644 arch/arm/dts/zynqmp-smk-k26-revA.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a5cae010c263..ed40b1f85a6d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -305,6 +305,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb\
zynqmp-mini-qspi.dtb\
+ zynqmp-sm-k26-revA.dtb \
+ zynqmp-smk-k26-revA.dtb \
+ zynqmp-sck-kv-g-revA.dtbo \
+ zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb\
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
new file mode 100644
index ..cad2d0572185
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KV260 revA Carrier Card
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * SD level shifter:
+ * "A" – A01 board un-modified (NXP)
+ * "Y" – A01 board modified with legacy interposer (Nexperia)
+ * "Z" – A01 board modified with Diode interposer
+ *
+ * Michal Simek
+ */
+
+ #include
+ #include
+ #include
+ #include
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-sk-kv260-revA",
+"xlnx,zynqmp-sk-kv260-revY",
+"xlnx,zynqmp-sk-kv260-revZ",
+"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+
+ fragment1 {
+ target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ u14: ina260@40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+ };
+ };
+
+ fragment1a {
+ target = <&amba>;
+ __overlay__ {
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
+ si5332_0: si5332_0 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12500>;
+ };
+
+ si5332_1: si5332_1 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500>;
+ };
+
+ si5332_2: si5332_2 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4800>;
+ };
+
+ si5332_3: si5332_3 { /* u17 */
+ compatible = "fixed-cloc
[PATCH 01/12] firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest
Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support
AM64x BCDMA Block copy channels.
Signed-off-by: Vignesh Raghavendra
---
drivers/firmware/ti_sci.c | 3 +++
drivers/firmware/ti_sci.h | 18 ++
include/linux/soc/ti/ti_sci_protocol.h | 14 ++
3 files changed, 35 insertions(+)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 0cdfb0e91a..2aec2e34d3 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -2466,6 +2466,9 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(
req.tx_orderid = params->tx_orderid;
req.fdepth = params->fdepth;
req.tx_sched_priority = params->tx_sched_priority;
+ req.tx_burst_size = params->tx_burst_size;
+ req.tx_tdtype = params->tx_tdtype;
+ req.extended_ch_type = params->extended_ch_type;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 327bb820f3..eec488f065 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -998,6 +998,9 @@ struct ti_sci_msg_psil_unpair {
* 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
* 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
* 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
+ * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
+ * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
+ * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
*
* @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
*
@@ -1058,6 +1061,18 @@ struct ti_sci_msg_psil_unpair {
* @tx_sched_priority: UDMAP transmit channel tx scheduling priority
* configuration to be programmed into the priority field of the channel's
* TCHAN_TST_SCHED register.
+ *
+ * @tx_burst_size: UDMAP transmit channel burst size configuration to be
+ * programmed into the tx_burst_size field of the TCHAN_TCFG register.
+ *
+ * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
+ * programmed into the tdtype field of the TCHAN_TCFG register:
+ * 0 - Return immediately
+ * 1 - Wait for completion message from remote peer
+ *
+ * @extended_ch_type: Valid for BCDMA.
+ * 0 - the channel is split tx channel (tchan)
+ * 1 - the channel is block copy channel (bchan)
*/
struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
struct ti_sci_msg_hdr hdr;
@@ -1078,6 +1093,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
+ u8 tx_burst_size;
+ u8 tx_tdtype;
+ u8 extended_ch_type;
} __packed;
/**
diff --git a/include/linux/soc/ti/ti_sci_protocol.h
b/include/linux/soc/ti/ti_sci_protocol.h
index eb916ba101..794737923c 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -379,6 +379,13 @@ struct ti_sci_rm_psil_ops {
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
+
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
+
/* UDMAP TX/RX channel valid_params common declarations */
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALIDBIT(0)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALIDBIT(1)
@@ -389,6 +396,7 @@ struct ti_sci_rm_psil_ops {
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
/**
* Configures a Navigator Subsystem UDMAP transmit channel
@@ -403,6 +411,8 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALIDBIT(11)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALIDBIT(13)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALIDBIT(15)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALIDBIT(16)
u16 nav_id;
u16 index;
u8 tx_pause_on_err;
@@ -419,6 +429,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
+ u8 tx_burst_size;
+ u8 tx_tdtype;
+ u8 extended_ch_type;
};
/**
@@ -448,6 +461,7 @@ struct ti_sci_msg_rm_udmap_rx_ch_cfg {
u8 rx_chan_type;
u8 rx_ignore_short;
u8 rx_ignore_long;
+ u8 rx_burst_size;
};
/**
--
2.31.1
[PATCH 02/12] soc: ti: k3-navss-ringacc: Add AM64 ringacc support
AM64 dual mode rings are modeled as pair of Rings objects which has common
configuration and memory buffer, but separate real-time control register
sets for each direction mem2dev (forward) and dev2mem (reverse).
AM64 rings must be requested only using k3_ringacc_request_rings_pair(),
and forward ring must always be initialized/configured. After this any
other Ringacc APIs can be used without any callers changes.
Signed-off-by: Vignesh Raghavendra
---
drivers/soc/ti/k3-navss-ringacc.c | 273 +++-
include/linux/soc/ti/k3-navss-ringacc.h | 15 ++
2 files changed, 283 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/ti/k3-navss-ringacc.c
b/drivers/soc/ti/k3-navss-ringacc.c
index c5099ad084..10ef6be720 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#define set_bit(bit, bitmap) __set_bit(bit, bitmap)
#define clear_bit(bit, bitmap) __clear_bit(bit, bitmap)
@@ -56,6 +57,7 @@ staticu32 ringacc_readl(void __iomem *reg)
}
#define KNAV_RINGACC_CFG_RING_SIZE_ELCNT_MASK GENMASK(19, 0)
+#define K3_DMARING_RING_CFG_RING_SIZE_ELCNT_MASK GENMASK(15, 0)
/**
* struct k3_nav_ring_rt_regs - The RA Control/Status Registers region
@@ -71,6 +73,13 @@ struct k3_nav_ring_rt_regs {
};
#define KNAV_RINGACC_RT_REGS_STEP 0x1000
+#define K3_DMARING_RING_RT_REGS_STEP 0x2000
+#define K3_DMARING_RING_RT_REGS_REVERSE_OFS0x1000
+#define KNAV_RINGACC_RT_OCC_MASK GENMASK(20, 0)
+#define K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE BIT(31)
+#define K3_DMARING_RING_RT_DB_ENTRY_MASK GENMASK(7, 0)
+#define K3_DMARING_RING_RT_DB_TDOWN_ACKBIT(31)
+
/**
* struct k3_nav_ring_fifo_regs - The Ring Accelerator Queues Registers region
@@ -173,6 +182,7 @@ struct k3_nav_ring {
u32 flags;
#define KNAV_RING_FLAG_BUSYBIT(1)
#define K3_NAV_RING_FLAG_SHAREDBIT(2)
+#define K3_NAV_RING_FLAG_REVERSE BIT(3)
struct k3_nav_ring_state state;
u32 ring_id;
struct k3_nav_ringacc *parent;
@@ -200,6 +210,7 @@ struct k3_nav_ringacc_ops {
* @tisci_ring_ops - ti-sci rings ops
* @tisci_dev_id - ti-sci device id
* @ops: SoC specific ringacc operation
+ * @dual_ring: indicate k3_dmaring dual ring support
*/
struct k3_nav_ringacc {
struct udevice *dev;
@@ -220,8 +231,24 @@ struct k3_nav_ringacc {
u32 tisci_dev_id;
const struct k3_nav_ringacc_ops *ops;
+ bool dual_ring;
};
+static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring)
+{
+ return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK;
+}
+
+static void k3_nav_ringacc_ring_update_occ(struct k3_nav_ring *ring)
+{
+ u32 val;
+
+ val = readl(&ring->rt->occ);
+
+ ring->state.occ = val & KNAV_RINGACC_RT_OCC_MASK;
+ ring->state.tdown_complete = !!(val &
K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE);
+}
+
static long k3_nav_ringacc_ring_get_fifo_pos(struct k3_nav_ring *ring)
{
return KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES -
@@ -235,12 +262,23 @@ static void *k3_nav_ringacc_get_elm_addr(struct
k3_nav_ring *ring, u32 idx)
static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem);
static int k3_nav_ringacc_ring_pop_mem(struct k3_nav_ring *ring, void *elem);
+static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem);
+static int k3_dmaring_ring_reverse_pop_mem(struct k3_nav_ring *ring, void
*elem);
static struct k3_nav_ring_ops k3_nav_mode_ring_ops = {
.push_tail = k3_nav_ringacc_ring_push_mem,
.pop_head = k3_nav_ringacc_ring_pop_mem,
};
+static struct k3_nav_ring_ops k3_dmaring_fwd_ring_ops = {
+ .push_tail = k3_nav_ringacc_ring_push_mem,
+ .pop_head = k3_dmaring_ring_fwd_pop_mem,
+};
+
+static struct k3_nav_ring_ops k3_dmaring_reverse_ring_ops = {
+ .pop_head = k3_dmaring_ring_reverse_pop_mem,
+};
+
static int k3_nav_ringacc_ring_push_io(struct k3_nav_ring *ring, void *elem);
static int k3_nav_ringacc_ring_pop_io(struct k3_nav_ring *ring, void *elem);
static int k3_nav_ringacc_ring_push_head_io(struct k3_nav_ring *ring,
@@ -328,6 +366,27 @@ error:
return NULL;
}
+static int k3_dmaring_ring_request_rings_pair(struct k3_nav_ringacc *ringacc,
+ int fwd_id, int compl_id,
+ struct k3_nav_ring **fwd_ring,
+ struct k3_nav_ring **compl_ring)
+{
+ /* k3_dmaring: fwd_id == compl_id, so we ignore compl_id */
+ if (fwd_id < 0)
+ return -EINVAL;
+
+ if (test_bit(fwd_id, ringacc->rings_inuse))
+ return -EBUSY;
+
+ *fwd_ring = &ringacc->rings[fwd_id];
+ *compl_ring = &ringacc->rings[fwd_id + ringacc-
[PATCH 03/12] soc: ti: k3-navss-ringacc: Remove unused ring modes
With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed
ring mode, all other K3 SoCs have also been moved to this common
baseline. Therefore drop other modes such as
K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint.
There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/soc/ti/k3-navss-ringacc.c | 311 +---
include/linux/soc/ti/k3-navss-ringacc.h | 7 +-
2 files changed, 8 insertions(+), 310 deletions(-)
diff --git a/drivers/soc/ti/k3-navss-ringacc.c
b/drivers/soc/ti/k3-navss-ringacc.c
index 10ef6be720..b5a5c9da98 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -91,36 +91,6 @@ struct k3_nav_ring_fifo_regs {
u32 peek_tail_data[128];/* Ring Peek Tail Entry Data Regs */
};
-/**
- * struct k3_ringacc_proxy_gcfg_regs - RA Proxy Global Config MMIO Region
- */
-struct k3_ringacc_proxy_gcfg_regs {
- u32 revision; /* Revision Register */
- u32 config; /* Config Register */
-};
-
-#define K3_RINGACC_PROXY_CFG_THREADS_MASK GENMASK(15, 0)
-
-/**
- * struct k3_ringacc_proxy_target_regs - RA Proxy Datapath MMIO Region
- */
-struct k3_ringacc_proxy_target_regs {
- u32 control;/* Proxy Control Register */
- u32 status; /* Proxy Status Register */
- u8 resv_512[504];
- u32 data[128]; /* Proxy Data Register */
-};
-
-#define K3_RINGACC_PROXY_TARGET_STEP 0x1000
-#define K3_RINGACC_PROXY_NOT_USED (-1)
-
-enum k3_ringacc_proxy_access_mode {
- PROXY_ACCESS_MODE_HEAD = 0,
- PROXY_ACCESS_MODE_TAIL = 1,
- PROXY_ACCESS_MODE_PEEK_HEAD = 2,
- PROXY_ACCESS_MODE_PEEK_TAIL = 3,
-};
-
#define KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES (512U)
#define KNAV_RINGACC_FIFO_REGS_STEP0x1000
#define KNAV_RINGACC_MAX_DB_RING_CNT(127U)
@@ -156,7 +126,6 @@ struct k3_nav_ring_state {
*
* @rt - Ring control/status registers
* @fifos - Ring queues registers
- * @proxy - Ring Proxy Datapath registers
* @ring_mem_dma - Ring buffer dma address
* @ring_mem_virt - Ring buffer virt address
* @ops - Ring operations
@@ -167,12 +136,10 @@ struct k3_nav_ring_state {
* @ring_id - Ring Id
* @parent - Pointer on struct @k3_nav_ringacc
* @use_count - Use count for shared rings
- * @proxy_id - RA Ring Proxy Id (only if @K3_NAV_RINGACC_RING_USE_PROXY)
*/
struct k3_nav_ring {
struct k3_nav_ring_rt_regs __iomem *rt;
struct k3_nav_ring_fifo_regs __iomem *fifos;
- struct k3_ringacc_proxy_target_regs __iomem *proxy;
dma_addr_t ring_mem_dma;
void*ring_mem_virt;
struct k3_nav_ring_ops *ops;
@@ -187,7 +154,6 @@ struct k3_nav_ring {
u32 ring_id;
struct k3_nav_ringacc *parent;
u32 use_count;
- int proxy_id;
};
struct k3_nav_ringacc_ops {
@@ -198,8 +164,6 @@ struct k3_nav_ringacc_ops {
* struct k3_nav_ringacc - Rings accelerator descriptor
*
* @dev - pointer on RA device
- * @proxy_gcfg - RA proxy global config registers
- * @proxy_target_base - RA proxy datapath region
* @num_rings - number of ring in RA
* @rm_gp_range - general purpose rings range from tisci
* @dma_ring_reset_quirk - DMA reset w/a enable
@@ -214,14 +178,11 @@ struct k3_nav_ringacc_ops {
*/
struct k3_nav_ringacc {
struct udevice *dev;
- struct k3_ringacc_proxy_gcfg_regs __iomem *proxy_gcfg;
- void __iomem *proxy_target_base;
u32 num_rings; /* number of rings in Ringacc module */
unsigned long *rings_inuse;
struct ti_sci_resource *rm_gp_range;
bool dma_ring_reset_quirk;
u32 num_proxies;
- unsigned long *proxy_inuse;
struct k3_nav_ring *rings;
struct list_head list;
@@ -249,12 +210,6 @@ static void k3_nav_ringacc_ring_update_occ(struct
k3_nav_ring *ring)
ring->state.tdown_complete = !!(val &
K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE);
}
-static long k3_nav_ringacc_ring_get_fifo_pos(struct k3_nav_ring *ring)
-{
- return KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES -
- (4 << ring->elm_size);
-}
-
static void *k3_nav_ringacc_get_elm_addr(struct k3_nav_ring *ring, u32 idx)
{
return (idx * (4 << ring->elm_size) + ring->ring_mem_virt);
@@ -279,44 +234,14 @@ static struct k3_nav_ring_ops k3_dmaring_reverse_ring_ops
= {
.pop_head = k3_dmaring_ring_reverse_pop_mem,
};
-static int k3_nav_ringacc_ring_push_io(struct k3_nav_ring *ring, void *elem);
-static int k3_nav_ringacc_ring_pop_io(struct k3_nav_ring *ring, void *elem);
-static int k3_nav_ringacc_ring_push_head_io(struct k3_nav_ring *ring,
- void *elem);
-static int k3_nav_ringacc_ring_pop_tail_io(struct k3_nav_ring *ring,
-
[PATCH 00/12] AM64x: DMA and ethernet support
This series add ethernet and DMA support for AM64x SoC. Vignesh Raghavendra (12): firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest soc: ti: k3-navss-ringacc: Add AM64 ringacc support soc: ti: k3-navss-ringacc: Remove unused ring modes dma: ti: k3-psil-am654: Drop unused PSIL EP static data dma: ti: k3-psil: Extend PSIL EP data extension for AM64 dma: ti: k3-psil-am64: Add AM64 PSIL endpoint data dma: ti: k3-udma: Add BCDMA and PKTDMA support net: ti: am65-cpsw-nuss: Prepare to support non primary ext port net: ti: am65-cpsw-nuss: Don't cache disabled port ID net: ti: am65-cpsw-nuss: Add a new compatible for AM64 ARM: dts: k3-am64-main: Add CPSW DT nodes ARM: dts: k3-am642-sk: Add ethernet related DT nodes arch/arm/dts/k3-am64-main.dtsi | 74 ++ arch/arm/dts/k3-am64.dtsi |2 + arch/arm/dts/k3-am642-evm-u-boot.dtsi | 16 + arch/arm/dts/k3-am642-evm.dts | 93 +++ arch/arm/dts/k3-am642-sk-u-boot.dtsi| 16 + arch/arm/dts/k3-am642-sk.dts| 62 ++ drivers/dma/ti/Makefile |1 + drivers/dma/ti/k3-psil-am64.c | 156 drivers/dma/ti/k3-psil-am654.c | 32 +- drivers/dma/ti/k3-psil-priv.h |1 + drivers/dma/ti/k3-psil.c|2 + drivers/dma/ti/k3-psil.h| 16 + drivers/dma/ti/k3-udma.c| 1003 +-- drivers/firmware/ti_sci.c |3 + drivers/firmware/ti_sci.h | 18 + drivers/net/ti/am65-cpsw-nuss.c |5 +- drivers/soc/ti/k3-navss-ringacc.c | 530 ++-- include/linux/soc/ti/k3-navss-ringacc.h | 22 +- include/linux/soc/ti/ti_sci_protocol.h | 14 + 19 files changed, 1687 insertions(+), 379 deletions(-) create mode 100644 drivers/dma/ti/k3-psil-am64.c -- 2.31.1
[PATCH 04/12] dma: ti: k3-psil-am654: Drop unused PSIL EP static data
ICSSG Ethernet driver uses two src threads per port (one per slice).
Similarly CPSW uses one src thread.
Drop PSIL EP static data for other src threads in order to reduce
R5 SPL footprint. This makes AM65x board bootable again.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-psil-am654.c | 32 +++-
1 file changed, 7 insertions(+), 25 deletions(-)
diff --git a/drivers/dma/ti/k3-psil-am654.c b/drivers/dma/ti/k3-psil-am654.c
index f95d99cfd3..d16c07566b 100644
--- a/drivers/dma/ti/k3-psil-am654.c
+++ b/drivers/dma/ti/k3-psil-am654.c
@@ -44,40 +44,22 @@ static struct psil_ep am654_src_ep_map[] = {
static struct psil_ep am654_dst_ep_map[] = {
/* PRU_ICSSG0 */
PSIL_ETHERNET(0xc100),
- PSIL_ETHERNET(0xc101),
- PSIL_ETHERNET(0xc102),
- PSIL_ETHERNET(0xc103),
+ /* PSIL: 0xc101 - 0xc103 unused */
PSIL_ETHERNET(0xc104),
- PSIL_ETHERNET(0xc105),
- PSIL_ETHERNET(0xc106),
- PSIL_ETHERNET(0xc107),
+ /* PSIL: 0xc105 - 0xc107 unused */
/* PRU_ICSSG1 */
PSIL_ETHERNET(0xc200),
- PSIL_ETHERNET(0xc201),
- PSIL_ETHERNET(0xc202),
- PSIL_ETHERNET(0xc203),
+ /* PSIL: 0xc201 - 0xc203 unused */
PSIL_ETHERNET(0xc204),
- PSIL_ETHERNET(0xc205),
- PSIL_ETHERNET(0xc206),
- PSIL_ETHERNET(0xc207),
+ /* PSIL: 0xc205 - 0xc207 unused */
/* PRU_ICSSG2 */
PSIL_ETHERNET(0xc300),
- PSIL_ETHERNET(0xc301),
- PSIL_ETHERNET(0xc302),
- PSIL_ETHERNET(0xc303),
+ /* PSIL: 0xc301 - 0xc303 unused */
PSIL_ETHERNET(0xc304),
- PSIL_ETHERNET(0xc305),
- PSIL_ETHERNET(0xc306),
- PSIL_ETHERNET(0xc307),
+ /* PSIL: 0xc305 - 0xc307 unused */
/* CPSW0 */
PSIL_ETHERNET(0xf000),
- PSIL_ETHERNET(0xf001),
- PSIL_ETHERNET(0xf002),
- PSIL_ETHERNET(0xf003),
- PSIL_ETHERNET(0xf004),
- PSIL_ETHERNET(0xf005),
- PSIL_ETHERNET(0xf006),
- PSIL_ETHERNET(0xf007),
+ /* PSIL: 0xf001 - 0xf007 unused */
};
struct psil_ep_map am654_ep_map = {
--
2.31.1
[PATCH 05/12] dma: ti: k3-psil: Extend PSIL EP data extension for AM64
Extend PSIL EP data to include AM64 DMA specific information
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-psil.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/dma/ti/k3-psil.h b/drivers/dma/ti/k3-psil.h
index 53c61b4595..1e0fe06c0a 100644
--- a/drivers/dma/ti/k3-psil.h
+++ b/drivers/dma/ti/k3-psil.h
@@ -50,6 +50,15 @@ enum psil_endpoint_type {
* @channel_tpl: Desired throughput level for the channel
* @pdma_acc32:ACC32 must be enabled on the PDMA side
* @pdma_burst:BURST must be enabled on the PDMA side
+ * @mapped_channel_id: PKTDMA thread to channel mapping for mapped
+ * channels. The thread must be serviced by the specified
+ * channel if mapped_channel_id is >= 0 in case of PKTDMA
+ * @flow_start:PKTDMA flow range start of mapped channel.
Unmapped
+ * channels use flow_id == chan_id
+ * @flow_num: PKTDMA flow count of mapped channel. Unmapped
+ * channels use flow_id == chan_id
+ * @default_flow_id: PKTDMA default (r)flow index of mapped channel.
+ * Must be within the flow range of the mapped channel.
*/
struct psil_endpoint_config {
enum psil_endpoint_type ep_type;
@@ -63,5 +72,12 @@ struct psil_endpoint_config {
/* PDMA properties, valid for PSIL_EP_PDMA_* */
unsigned pdma_acc32:1;
unsigned pdma_burst:1;
+
+ /* PKTDMA mapped channel */
+ int mapped_channel_id;
+ /* PKTDMA tflow and rflow ranges for mapped channel */
+ u16 flow_start;
+ u16 flow_num;
+ u16 default_flow_id;
};
#endif /* K3_PSIL_H_ */
--
2.31.1
[PATCH 06/12] dma: ti: k3-psil-am64: Add AM64 PSIL endpoint data
Add AM64 SoC specific channel mapping and endpoint data.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-am64.c | 156 ++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 +
4 files changed, 160 insertions(+)
create mode 100644 drivers/dma/ti/k3-psil-am64.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 4ea9c626cc..0391cd3d80 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
k3-psil-data-y += k3-psil.o
k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
+k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
diff --git a/drivers/dma/ti/k3-psil-am64.c b/drivers/dma/ti/k3-psil-am64.c
new file mode 100644
index 00..15742c3723
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am64.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Peter Ujfalusi
+ */
+
+#include
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1,\
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1,\
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 16, \
+ .mapped_channel_id = ch,\
+ .flow_start = flow_base,\
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 64, \
+ .mapped_channel_id = ch,\
+ .flow_start = flow_base,\
+ .flow_num = flow_cnt, \
+ .default_flow_id = default_flow,\
+ .notdpkt = tx, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am64_src_ep_map[] = {
+ /* SAUL */
+ PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
+ PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
+ PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
+ PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
+ /* ICSS_G0 */
+ PSIL_ETHERNET(0x4100, 21, 48, 16),
+ PSIL_ETHERNET(0x4101, 22, 64, 16),
+ PSIL_ETHERNET(0x4102, 23, 80, 16),
+ PSIL_ETHERNET(0x4103, 24, 96, 16),
+ /* ICSS_G1 */
+ PSIL_ETHERNET(0x4200, 25, 112, 16),
+ PSIL_ETHERNET(0x4201, 26, 128, 16),
+ PSIL_ETHERNET(0x4202, 27, 144, 16),
+ PSIL_ETHERNET(0x4203, 28, 160, 16),
+ /* PDMA_MAIN0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4300),
+ PSIL_PDMA_XY_PKT(0x4301),
+ PSIL_PDMA_XY_PKT(0x4302),
+ PSIL_PDMA_XY_PKT(0x4303),
+ PSIL_PDMA_XY_PKT(0x4304),
+ PSIL_PDMA_XY_PKT(0x4305),
+ PSIL_PDMA_XY_PKT(0x4306),
+ PSIL_PDMA_XY_PKT(0x43
[PATCH 08/12] net: ti: am65-cpsw-nuss: Prepare to support non primary ext port
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8) Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port) as preparation to allow any one of the 8 ports to be used as ethernet interface in U-Boot. Signed-off-by: Vignesh Raghavendra --- drivers/net/ti/am65-cpsw-nuss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index e6954b64b7..9f11ce63b9 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -26,7 +26,7 @@ #include "cpsw_mdio.h" -#define AM65_CPSW_CPSWNU_MAX_PORTS 2 +#define AM65_CPSW_CPSWNU_MAX_PORTS 9 #define AM65_CPSW_SS_BASE 0x0 #define AM65_CPSW_SGMII_BASE 0x100 -- 2.31.1
[PATCH 07/12] dma: ti: k3-udma: Add BCDMA and PKTDMA support
Sync BCDMA and PKTDMA support from Kernel for AM64 SoC
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 1003 +++---
1 file changed, 939 insertions(+), 64 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index f3ec827897..601868d7fc 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include "k3-udma-hwdef.h"
#include "k3-psil-priv.h"
@@ -36,15 +37,25 @@
struct udma_chan;
+enum k3_dma_type {
+ DMA_TYPE_UDMA = 0,
+ DMA_TYPE_BCDMA,
+ DMA_TYPE_PKTDMA,
+};
+
enum udma_mmr {
MMR_GCFG = 0,
+ MMR_BCHANRT,
MMR_RCHANRT,
MMR_TCHANRT,
MMR_LAST,
};
static const char * const mmr_names[] = {
- "gcfg", "rchanrt", "tchanrt"
+ [MMR_GCFG] = "gcfg",
+ [MMR_BCHANRT] = "bchanrt",
+ [MMR_RCHANRT] = "rchanrt",
+ [MMR_TCHANRT] = "tchanrt",
};
struct udma_tchan {
@@ -53,6 +64,16 @@ struct udma_tchan {
int id;
struct k3_nav_ring *t_ring; /* Transmit ring */
struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
+ int tflow_id; /* applicable only for PKTDMA */
+
+};
+
+#define udma_bchan udma_tchan
+
+struct udma_rflow {
+ int id;
+ struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
+ struct k3_nav_ring *r_ring; /* Receive ring */
};
struct udma_rchan {
@@ -61,32 +82,45 @@ struct udma_rchan {
int id;
};
+struct udma_oes_offsets {
+ /* K3 UDMA Output Event Offset */
+ u32 udma_rchan;
+
+ /* BCDMA Output Event Offsets */
+ u32 bcdma_bchan_data;
+ u32 bcdma_bchan_ring;
+ u32 bcdma_tchan_data;
+ u32 bcdma_tchan_ring;
+ u32 bcdma_rchan_data;
+ u32 bcdma_rchan_ring;
+
+ /* PKTDMA Output Event Offsets */
+ u32 pktdma_tchan_flow;
+ u32 pktdma_rchan_flow;
+};
+
#define UDMA_FLAG_PDMA_ACC32 BIT(0)
#define UDMA_FLAG_PDMA_BURST BIT(1)
#define UDMA_FLAG_TDTYPE BIT(2)
struct udma_match_data {
+ enum k3_dma_type type;
u32 psil_base;
bool enable_memcpy_support;
u32 flags;
u32 statictr_z_mask;
- u32 rchan_oes_offset;
+ struct udma_oes_offsets oes;
u8 tpl_levels;
u32 level_start_idx[];
};
-struct udma_rflow {
- int id;
-
- struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
- struct k3_nav_ring *r_ring; /* Receive ring*/
-};
-
enum udma_rm_range {
- RM_RANGE_TCHAN = 0,
+ RM_RANGE_BCHAN = 0,
+ RM_RANGE_TCHAN,
RM_RANGE_RCHAN,
RM_RANGE_RFLOW,
+ RM_RANGE_TFLOW,
RM_RANGE_LAST,
};
@@ -111,15 +145,21 @@ struct udma_dev {
u32 features;
+ int bchan_cnt;
int tchan_cnt;
int echan_cnt;
int rchan_cnt;
int rflow_cnt;
+ int tflow_cnt;
+ unsigned long *bchan_map;
unsigned long *tchan_map;
unsigned long *rchan_map;
unsigned long *rflow_map;
unsigned long *rflow_map_reserved;
+ unsigned long *rflow_in_use;
+ unsigned long *tflow_map;
+ struct udma_bchan *bchans;
struct udma_tchan *tchans;
struct udma_rchan *rchans;
struct udma_rflow *rflows;
@@ -143,6 +183,11 @@ struct udma_chan_config {
enum psil_endpoint_type ep_type;
enum udma_tp_level channel_tpl; /* Channel Throughput Level */
+ /* PKTDMA mapped channel */
+ int mapped_channel_id;
+ /* PKTDMA default tflow or rflow for mapped channel */
+ int default_flow_id;
+
enum dma_direction dir;
unsigned int pkt_mode:1; /* TR or packet */
@@ -156,6 +201,7 @@ struct udma_chan {
struct udma_dev *ud;
char name[20];
+ struct udma_bchan *bchan;
struct udma_tchan *tchan;
struct udma_rchan *rchan;
struct udma_rflow *rflow;
@@ -289,6 +335,14 @@ static inline char *udma_get_dir_text(enum dma_direction
dir)
return "invalid";
}
+static void udma_reset_uchan(struct udma_chan *uc)
+{
+ memset(&uc->config, 0, sizeof(uc->config));
+ uc->config.remote_thread_id = -1;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
+}
+
static inline bool udma_is_chan_running(struct udma_chan *uc)
{
u32 trt_ctl = 0;
@@ -371,7 +425,7 @@ static void udma_reset_rings(struct udma_chan *uc)
}
if (ring1)
- k3_nav_ringacc_ring_reset_dma(ring1, 0);
+ k3_nav_ringacc_ring_reset_dma(ring1,
k3_nav_ringacc_ring_get_occ(ring1));
if (ring2)
k3_nav_ringacc_ring_reset(ring2);
}
@@ -390,8 +444,10 @@ static void udma_reset_counters(struct udma_chan *uc)
val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
-
[PATCH 09/12] net: ti: am65-cpsw-nuss: Don't cache disabled port ID
Currently driver may end up caching disabled port ID as active interface. Fix this by bailing out earlier in case port is marked disabled in the DT. Signed-off-by: Vignesh Raghavendra --- drivers/net/ti/am65-cpsw-nuss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 9f11ce63b9..3534a6d807 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -719,11 +719,11 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) if (!port_id) continue; - priv->port_id = port_id; cpsw_common->ports[port_id].disabled = disabled; if (disabled) continue; + priv->port_id = port_id; ret = am65_cpsw_ofdata_parse_phy(dev, node); if (ret) goto out; -- 2.31.1
[PATCH 12/12] ARM: dts: k3-am642-sk: Add ethernet related DT nodes
Add CPSW related nodes for AM642 SK. There are two CPSW ports on the
board but U-Boot supports only the first port.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-am642-sk-u-boot.dtsi | 16 +++
arch/arm/dts/k3-am642-sk.dts | 62
2 files changed, 78 insertions(+)
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 8a987f1421..700a55b420 100644
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -85,3 +85,19 @@
&main_mmc1_pins_default {
u-boot,dm-spl;
};
+
+&cpsw3g {
+ reg = <0x0 0x800 0x0 0x20>,
+ <0x0 0x43000200 0x0 0x8>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel@04044 {
+ compatible = "ti,am64-phy-gmii-sel";
+ reg = <0x0 0x43004044 0x0 0x8>;
+ };
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts
index d557c49d16..df76c6e0b9 100644
--- a/arch/arm/dts/k3-am642-sk.dts
+++ b/arch/arm/dts/k3-am642-sk.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include
+#include
#include "k3-am642.dtsi"
/ {
@@ -57,6 +58,47 @@
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19)
I2C1_SDA */
>;
};
+
+ mdio1_pins_default: mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2)
PRG0_PRU1_GPO19.MDIO0_MDC */
+ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5)
PRG0_PRU1_GPO18.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13)
PRG1_PRU1_GPO5.RGMII1_RD0 */
+ AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12)
PRG1_PRU1_GPO8.RGMII1_RD1 */
+ AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13)
PRG1_PRU1_GPO18.RGMII1_RD2 */
+ AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12)
PRG1_PRU1_GPO19.RGMII1_RD3 */
+ AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13)
PRG1_PRU0_GPO8.RGMII1_RXC */
+ AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13)
PRG1_PRU0_GPO5.RGMII1_RX_CTL */
+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15)
PRG1_PRU1_GPO7.RGMII1_TD0 */
+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14)
PRG1_PRU1_GPO9.RGMII1_TD1 */
+ AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14)
PRG1_PRU1_GPO10.RGMII1_TD2 */
+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14)
PRG1_PRU1_GPO17.RGMII1_TD3 */
+ AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14)
PRG1_PRU0_GPO10.RGMII1_TXC */
+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15)
PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11)
PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11)
PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12)
PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12)
PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11)
PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12)
PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10)
PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10)
PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10)
PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11)
PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10)
PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11)
PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
};
&main_uart1 {
@@ -92,3 +134,23 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default
+&rgmii1_pins_default
+&rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = ;
+ ti,fifo-depth = ;
+ };
+};
--
2.31.1
[PATCH 10/12] net: ti: am65-cpsw-nuss: Add a new compatible for AM64
Add a new compatible to support AM64 SoC
Signed-off-by: Vignesh Raghavendra
---
drivers/net/ti/am65-cpsw-nuss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 3534a6d807..3ab6a30828 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -782,6 +782,7 @@ out:
static const struct udevice_id am65_cpsw_nuss_ids[] = {
{ .compatible = "ti,am654-cpsw-nuss" },
{ .compatible = "ti,j721e-cpsw-nuss" },
+ { .compatible = "ti,am642-cpsw-nuss" },
{ }
};
--
2.31.1
[PATCH 11/12] ARM: dts: k3-am64-main: Add CPSW DT nodes
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same
(based on kernel DT).
Disable second port as its by default set to ICSS usage on EVM.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-am64-main.dtsi| 74 +
arch/arm/dts/k3-am64.dtsi | 2 +
arch/arm/dts/k3-am642-evm-u-boot.dtsi | 16 +
arch/arm/dts/k3-am642-evm.dts | 93 +++
4 files changed, 185 insertions(+)
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index 4b6cd6cc90..a65011b396 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -178,6 +178,12 @@
compatible = "ti,am654-chipid";
reg = <0x0014 0x4>;
};
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
};
main_uart0: serial@280 {
@@ -403,6 +409,74 @@
ti,clkbuf-sel = <0x7>;
};
+ cpsw3g: ethernet@800 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x800 0x0 0x20>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x800 0x0 0x20>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 1>;
+ assigned-clock-parents = <&k3_clks 13 9>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_pktdma 0xC500 15>,
+ <&main_pktdma 0xC501 15>,
+ <&main_pktdma 0xC502 15>,
+ <&main_pktdma 0xC503 15>,
+ <&main_pktdma 0xC504 15>,
+ <&main_pktdma 0xC505 15>,
+ <&main_pktdma 0xC506 15>,
+ <&main_pktdma 0xC507 15>,
+ <&main_pktdma 0x4500 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 de ad be ef];
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 01 de ad be ef];
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <100>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 13 1>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
main_gpio0: gpio@60 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x0060 0x00 0x100>;
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
index fde63463ca..6b2d0803b4 100644
--- a/arch/arm/dts/k3-am64.dtsi
+++ b/arch/arm/dts/k3-am64.dtsi
@@ -30,6 +30,8 @@
serial8 = &main_uart6;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
};
chosen { };
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 3bab736a18..5e0e41567f 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -81,3 +81,19 @@
&sdhci1 {
u-boot,dm-spl;
};
+
+&cpsw3g {
+ reg = <0x0 0x800 0x0 0x20>,
+ <0x0 0x43000200 0x0 0x8>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /dele
[PATCH 2/2] sandbox: add test of wdt_gpio driver
It seems that no other test has claimed gpio_a:7 yet, so use that.
The only small wrinkle is modifying the existing wdt test to use
uclass_get_device_by_driver() since we now have to UCLASS_WDT
instances in play, so it's a little more robust to fetch the device by
driver and not merely uclass+index.
Signed-off-by: Rasmus Villemoes
---
arch/sandbox/dts/test.dts | 5 +
configs/sandbox64_defconfig | 1 +
configs/sandbox_defconfig | 1 +
test/dm/wdt.c | 32 +++-
4 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index fe26ced31d..e6e1f50bd0 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -756,6 +756,11 @@
};
};
+ gpio-wdt {
+ gpios = <&gpio_a 7 0>;
+ compatible = "linux,wdt-gpio";
+ };
+
mbox: mbox {
compatible = "sandbox,mbox";
#mbox-cells = <1>;
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 9a373bab6f..ed41c6c897 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -224,6 +224,7 @@ CONFIG_SANDBOX_OSD=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_WDT=y
+CONFIG_WDT_GPIO=y
CONFIG_WDT_SANDBOX=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index bdbf714e2b..fef2d8777a 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -271,6 +271,7 @@ CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_SANDBOX=y
CONFIG_WDT=y
+CONFIG_WDT_GPIO=y
CONFIG_WDT_SANDBOX=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
diff --git a/test/dm/wdt.c b/test/dm/wdt.c
index 24b991dff6..fe75cbfea7 100644
--- a/test/dm/wdt.c
+++ b/test/dm/wdt.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -19,7 +20,8 @@ static int dm_test_wdt_base(struct unit_test_state *uts)
struct udevice *dev;
const u64 timeout = 42;
- ut_assertok(uclass_get_device(UCLASS_WDT, 0, &dev));
+ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT,
+ DM_DRIVER_GET(wdt_sandbox),
&dev));
ut_assertnonnull(dev);
ut_asserteq(0, state->wdt.counter);
ut_asserteq(false, state->wdt.running);
@@ -39,3 +41,31 @@ static int dm_test_wdt_base(struct unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_wdt_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int dm_test_wdt_gpio(struct unit_test_state *uts)
+{
+ /*
+* The sandbox wdt gpio is "connected" to gpio bank a, offset
+* 7. Use the sandbox back door to verify that the gpio-wdt
+* driver behaves as expected.
+*/
+ struct udevice *wdt, *gpio;
+ const int offset = 7;
+ int val;
+
+ ut_assertok(uclass_get_device_by_driver(UCLASS_WDT,
+ DM_DRIVER_GET(wdt_gpio), &wdt));
+ ut_assertnonnull(wdt);
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios",
&gpio));
+ ut_assertnonnull(gpio);
+
+ val = sandbox_gpio_get_value(gpio, offset);
+ ut_assertok(wdt_reset(wdt));
+ ut_asserteq(!val, sandbox_gpio_get_value(gpio, offset));
+ ut_assertok(wdt_reset(wdt));
+ ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
+
+ return 0;
+}
+DM_TEST(dm_test_wdt_gpio, UT_TESTF_SCAN_FDT);
--
2.29.2
[PATCH 1/2] watchdog: add gpio watchdog driver
A rather common kind of external watchdog circuit is one that is kept
alive by toggling a gpio. Add a driver for handling such a watchdog.
The compatible string is probably a little odd as it has nothing to do
with linux per se - however, I chose that to make .dts snippets
reusable between device trees used with U-Boot and linux, and this is
the (only) compatible string that linux' corresponding driver and DT
binding accepts. I have asked whether one should/could add "wdt-gpio"
to that binding, but the answer was no:
https://lore.kernel.org/lkml/CAL_JsqKEGaFpiFV_oAtE+S_bnHkg4qry+bhx2EDs=nsbvf_...@mail.gmail.com/
If someone feels strongly about this, I can certainly remove the
"linux," part from the string - it probably wouldn't the only place where
one can't reuse a DT snippet as-is between linux and U-Boot.
Signed-off-by: Rasmus Villemoes
---
.../watchdog/gpio-wdt.txt | 15 ++
drivers/watchdog/Kconfig | 7 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/gpio_wdt.c | 51 +++
4 files changed, 74 insertions(+)
create mode 100644 doc/device-tree-bindings/watchdog/gpio-wdt.txt
create mode 100644 drivers/watchdog/gpio_wdt.c
diff --git a/doc/device-tree-bindings/watchdog/gpio-wdt.txt
b/doc/device-tree-bindings/watchdog/gpio-wdt.txt
new file mode 100644
index 00..2283b7ba6e
--- /dev/null
+++ b/doc/device-tree-bindings/watchdog/gpio-wdt.txt
@@ -0,0 +1,15 @@
+GPIO watchdog timer
+
+Describes a simple watchdog timer which is reset by toggling a gpio.
+
+Required properties:
+
+- compatible: must be "linux,wdt-gpio"
+- gpios: gpio to toggle when wdt driver reset method is called
+
+Example:
+
+ gpio-wdt {
+ gpios = <&gpio0 1 0>;
+ compatible = "linux,wdt-gpio";
+ };
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f0ff2612a6..2cf378db29 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -147,6 +147,13 @@ config WDT_CORTINA
This driver support all CPU ISAs supported by Cortina
Access CA SoCs.
+config WDT_GPIO
+ bool "External gpio watchdog support"
+ depends on WDT
+ depends on DM_GPIO
+ help
+ Support for external watchdog fed by toggling a gpio.
+
config WDT_MPC8xx
bool "MPC8xx watchdog timer support"
depends on WDT && MPC8xx
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 5c7ef593fe..f14415bb8e 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
+obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
diff --git a/drivers/watchdog/gpio_wdt.c b/drivers/watchdog/gpio_wdt.c
new file mode 100644
index 00..9dba9c254e
--- /dev/null
+++ b/drivers/watchdog/gpio_wdt.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+#include
+#include
+#include
+
+struct gpio_wdt_priv {
+ struct gpio_desc gpio;
+ int state;
+};
+
+static int gpio_wdt_reset(struct udevice *dev)
+{
+ struct gpio_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->state = !priv->state;
+ return dm_gpio_set_value(&priv->gpio, priv->state);
+}
+
+static int dm_probe(struct udevice *dev)
+{
+ struct gpio_wdt_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT);
+ if (ret < 0) {
+ dev_err(dev, "Request for wdt gpio failed: %d\n", ret);
+ return ret;
+ }
+ return gpio_wdt_reset(dev);
+}
+
+static const struct wdt_ops gpio_wdt_ops = {
+ .reset = gpio_wdt_reset,
+};
+
+static const struct udevice_id gpio_wdt_ids[] = {
+ { .compatible = "linux,wdt-gpio" },
+ {}
+};
+
+U_BOOT_DRIVER(wdt_gpio) = {
+ .name = "wdt_gpio",
+ .id = UCLASS_WDT,
+ .of_match = gpio_wdt_ids,
+ .ops = &gpio_wdt_ops,
+ .probe = dm_probe,
+ .priv_auto = sizeof(struct gpio_wdt_priv),
+};
--
2.29.2
Re: [PATCH v2 2/7] lib: wrap crypt API to hide errno usage
On Mon, 10 May 2021 at 00:19, Steffen Jaeckel wrote: > > In order to prevent using the global errno, replace it with a static > version and create a wrapper function which returns the error value. > > Signed-off-by: Steffen Jaeckel > --- > > (no changes since v1) > > include/crypt.h | 3 ++- > lib/crypt/alg-sha256.h | 6 -- > lib/crypt/alg-sha512.h | 6 -- > lib/crypt/crypt-port.h | 18 ++ > lib/crypt/crypt-sha256.c | 26 -- > lib/crypt/crypt-sha512.c | 26 -- > lib/crypt/crypt.c| 25 ++--- > test/lib/test_crypt.c| 24 ++-- > 8 files changed, 96 insertions(+), 38 deletions(-) > Reviewed-by: Simon Glass
Re: [RFC PATCH u-boot 00/12] U-Boot LTO (Sandbox + ARM Nokia RX-51)
Hi Marek, On Sun, 9 May 2021 at 12:45, Marek Behun wrote: > > On Sun, 9 May 2021 09:14:14 -0500 > Adam Ford wrote: > > > On Sat, Mar 6, 2021 at 10:06 PM Marek Behun wrote: > > > > > > On Sat, 6 Mar 2021 21:45:02 -0600 > > > Adam Ford wrote: > > > > > > > On Sat, Mar 6, 2021 at 3:49 PM Marek Behun wrote: > > > > > > > > > > On Sat, 6 Mar 2021 22:38:52 +0100 > > > > > Pali Rohár wrote: > > > > > > > > > > > On Saturday 06 March 2021 22:19:22 Marek Behun wrote: > > > > > > > On Sat, 6 Mar 2021 22:00:45 +0100 > > > > > > > Pali Rohár wrote: > > > > > > > > > > > > > > > On Saturday 06 March 2021 21:54:00 Marek Behun wrote: > > > > > > > > > On Sat, 6 Mar 2021 21:41:14 +0100 > > > > > > > > > Pali Rohár wrote: > > > > > > > > > > > > > > > > > > > On Saturday 06 March 2021 15:08:13 Tom Rini wrote: > > > > > > > > > > > Perhaps we'll default to yes on some SoCs. The omap3 > > > > > > > > > > > thing is a bit > > > > > > > > > > > odd, but we'll see what happens on real N900 hardware. > > > > > > > > > > > > > > > > > > > > Hello! > > > > > > > > > > > > > > > > > > > > Could you send me a link to git repo / branch and tell me > > > > > > > > > > from which > > > > > > > > > > commit should I do tests on real N900 hardware? I will test > > > > > > > > > > it and let > > > > > > > > > > you know results. > > > > > > > > > > > > > > > > > > > > Adding maemo ML to the loop as on the maemo list are more > > > > > > > > > > people with > > > > > > > > > > N900 HW and U-Boot. > > > > > > > > > > > > > > > > > > https://github.com/elkablo/u-boot branch lto > > > > > > > > > > > > > > > > Sorry, compilation is failing :-( > > > > > > > > > > > > > > > > $ git clone https://github.com/elkablo/u-boot -b lto --depth=100 > > > > > > > > Cloning into 'u-boot'... > > > > > > > > remote: Enumerating objects: 33644, done. > > > > > > > > remote: Counting objects: 100% (33644/33644), done. > > > > > > > > remote: Compressing objects: 100% (20116/20116), done. > > > > > > > > remote: Total 33644 (delta 15838), reused 19947 (delta 13018), > > > > > > > > pack-reused 0 > > > > > > > > Receiving objects: 100% (33644/33644), 26.28 MiB | 10.21 MiB/s, > > > > > > > > done. > > > > > > > > Resolving deltas: 100% (15838/15838), done. > > > > > > > > > > > > > > > > $ cd u-boot > > > > > > > > > > > > > > > > $ make CROSS_COMPILE=arm-linux-gnueabi- nokia_rx51_config > > > > > > > > HOSTCC scripts/basic/fixdep > > > > > > > > HOSTCC scripts/kconfig/conf.o > > > > > > > > YACCscripts/kconfig/zconf.tab.c > > > > > > > > LEX scripts/kconfig/zconf.lex.c > > > > > > > > HOSTCC scripts/kconfig/zconf.tab.o > > > > > > > > HOSTLD scripts/kconfig/conf > > > > > > > > # > > > > > > > > # configuration written to .config > > > > > > > > # > > > > > > > > > > > > > > > > $ make CROSS_COMPILE=arm-linux-gnueabi- u-boot.bin > > > > > > > > ... > > > > > > > > LTO u-boot > > > > > > > > /usr/lib/gcc-cross/arm-linux-gnueabi/8/../../../../arm-linux-gnueabi/bin/ld: > > > > > > > > > > > > > > > > /usr/lib/gcc-cross/arm-linux-gnueabi/8/../../../../arm-linux-gnueabi/bin/ld: > > > > > > > > DWARF error: offset (1258291444) greater than or equal to > > > > > > > > .debug_str size (676) > > > > > > > > /usr/lib/gcc-cross/arm-linux-gnueabi/8/../../../../arm-linux-gnueabi/bin/ld: > > > > > > > > DWARF error: offset (1459618036) greater than or equal to > > > > > > > > .debug_str size (676) > > > > > > > > /usr/lib/gcc-cross/arm-linux-gnueabi/8/../../../../arm-linux-gnueabi/bin/ld: > > > > > > > > DWARF error: could not find abbrev number 48028 > > > > > > > > /tmp/cc8l0QSQ.ltrans3.ltrans.o: in function > > > > > > > > `omap3_set_aux_cr_secure': > > > > > > > > :(.text+0x6eb8): undefined reference to > > > > > > > > `do_omap3_emu_romcode_call' > > > > > > > > collect2: error: ld returned 1 exit status > > > > > > > > make: *** [Makefile:1808: u-boot] Error 1 > > > > > > > > > > > > > > > > > > > > > > > > I'm using arm-linux-gnueabi-gcc version 8.3.0 which is > > > > > > > > available in > > > > > > > > current Debian stable (Debian 10 Buster). > > > > > > > > > > > > > > Fixed and force-pushed, it seems ar needs the P flag that Bin Meng > > > > > > > questioned. > > > > > > > > > > > > Problem is fixed, now compilation succeeded. u-boot.bin has size > > > > > > 243788 > > > > > > bytes. > > > > > > > > > > > > And seems that compiled U-Boot is working fine! > > > > > > > > > > > > Nokia RX-51 # version > > > > > > U-Boot 2021.04-rc3-00338-g88d0a5042c97 (Mar 06 2021 - 22:19:08 > > > > > > +0100) > > > > > > > > > > > > arm-linux-gnueabi-gcc (Debian 8.3.0-2) 8.3.0 > > > > > > GNU ld (GNU Binutils for Debian) 2.31.1 > > > > > > > > > > > > I can send binary files via usbtty and 'loadb' command. I can boot > > > > > > linux > > > > > > kernel via 'bootm'. I can chainload to another U-Boot binary > > > > > > (loaded by > > > > > > 'loadb') via 'go' command. Also 'ext4ls' and 'fatls' commands are > > > > > > work
Re: [PATCH 16/17] clk: Detect failure to set defaults
Hi Sean,
On Sat, 8 May 2021 at 18:40, Sean Anderson wrote:
>
> On 5/8/21 6:00 PM, Simon Glass wrote:
> > When the default clocks cannot be set, the clock is silently probed and
> > the error is ignored. This is incorrect, since having the clocks at the
> > correct speed may be important for operation of the system.
> >
> > Fix it by checking the return code.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > drivers/clk/clk-uclass.c | 6 +-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> > index 4ab3c402ed8..2a2e1cfbd61 100644
> > --- a/drivers/clk/clk-uclass.c
> > +++ b/drivers/clk/clk-uclass.c
> > @@ -796,13 +796,17 @@ void devm_clk_put(struct udevice *dev, struct clk
> > *clk)
> >
> > int clk_uclass_post_probe(struct udevice *dev)
> > {
> > + int ret;
> > +
> > /*
> >* when a clock provider is probed. Call clk_set_defaults()
> >* also after the device is probed. This takes care of cases
> >* where the DT is used to setup default parents and rates
> >* using assigned-clocks
> >*/
> > - clk_set_defaults(dev, 1);
> > + ret = clk_set_defaults(dev, 1);
> > + if (ret)
> > + return log_ret(ret);
> >
> > return 0;
> > }
> >
>
> See also:
> https://patchwork.ozlabs.org/project/uboot/patch/20210409021313.433558-2-sean...@gmail.com/
So which should we do? My feeling is that a failure that is
programmatically silent could cause things to fail, but is there a
reason why this might be wrong but everything is still OK?
Regards,
Simon
> Reviewed-by: Sean Anderson
Re: [PATCH v5 10/13] riscv: dts: Sort build targets in alphabetical order
On Mon, 10 May 2021 at 06:24, Bin Meng wrote: > > Sort the RISC-V DTS build targets by their Kconfig target names in > alphabetical order. > > Signed-off-by: Bin Meng > > --- > > (no changes since v2) > > Changes in v2: > - new patch: "riscv: dts: Sort build targets in alphabetical order" > > arch/riscv/dts/Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass (as I have not seen anyone review this patch through several revisions...who is the maintainer?)
Re: [PATCH v5 13/13] riscv: Drop USE_SPL_FIT_GENERATOR
On Mon, 10 May 2021 at 06:24, Bin Meng wrote: > > Now that we have switched to binman to generate u-boot.itb for all > RISC-V boards, USE_SPL_FIT_GENERATOR is no longer needed and can > be dropped. > > Signed-off-by: Bin Meng > > --- > > (no changes since v3) > > Changes in v3: > - remove USE_SPL_FIT_GENERATOR in ae350_ defconfigs > > Changes in v2: > - new patch: "riscv: Drop USE_SPL_FIT_GENERATOR" > > arch/riscv/lib/mkimage_fit_opensbi.sh | 100 -- > common/Kconfig.boot | 3 +- > configs/ae350_rv32_spl_defconfig | 1 - > configs/ae350_rv32_spl_xip_defconfig | 1 - > configs/ae350_rv64_spl_defconfig | 1 - > configs/ae350_rv64_spl_xip_defconfig | 1 - > configs/qemu-riscv32_spl_defconfig| 1 - > configs/qemu-riscv64_spl_defconfig| 1 - > configs/sifive_unleashed_defconfig| 1 - > 9 files changed, 1 insertion(+), 109 deletions(-) > delete mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh Reviewed-by: Simon Glass Great to see this!
Re: [PATCH v5 12/13] riscv: ae350: Switch to use binman to generate u-boot.itb
On Mon, 10 May 2021 at 06:24, Bin Meng wrote: > > Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs, > so that binman is now used to generate u-boot.itb. > > Signed-off-by: Bin Meng > > --- > > (no changes since v3) > > Changes in v3: > - new patch: "riscv: ae350: Switch to use binman to generate u-boot.itb" > > arch/riscv/dts/ae350_32.dts | 2 ++ > arch/riscv/dts/ae350_64.dts | 2 ++ > board/AndesTech/ax25-ae350/Kconfig | 1 + > configs/ae350_rv32_spl_defconfig | 2 ++ > configs/ae350_rv32_spl_xip_defconfig | 2 ++ > configs/ae350_rv64_spl_defconfig | 2 ++ > configs/ae350_rv64_spl_xip_defconfig | 2 ++ > 7 files changed, 13 insertions(+) Reviewed-by: Simon Glass
Re: [PATCH v2 7/7] configs: add new sandbox with crypt-based password
Hi Steffen, On Mon, 10 May 2021 at 00:19, Steffen Jaeckel wrote: > > This is a copy of the regular sandbox with crypt-based password entry > enabled. > > Signed-off-by: Steffen Jaeckel > --- > > (no changes since v1) > > configs/sandbox_cryptpass_defconfig | 296 > 1 file changed, 296 insertions(+) > create mode 100644 configs/sandbox_cryptpass_defconfig Is this so you can add a test? In that case I think you need to adjust things... For sandbox you need to be able to build in both options, so your if/else approach won't work. You could control it with an env var perhaps, when both are enabled. Then it is easy enough to select the required setup with sandbox. Regards, Simon
Re: [PATCH v5 08/13] lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED
Hi Bin, On Mon, 10 May 2021 at 06:24, Bin Meng wrote: > > Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED. > For the other OF_CONTROL methods, it's quite possible binman node is > not available as binman is invoked during the build phase instead of > runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default. > > Signed-off-by: Bin Meng > > --- > > (no changes since v3) > > Changes in v3: > - new patch: "lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED" > > lib/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) I think you need to handle the sandbox case too - OF_HOSTFILE Perhaps we don't have tests for this? I need to add some. Regards, SImon
Re: [PATCH 2/2] sandbox: add test of wdt_gpio driver
On Mon, 10 May 2021 at 09:47, Rasmus Villemoes wrote: > > It seems that no other test has claimed gpio_a:7 yet, so use that. > > The only small wrinkle is modifying the existing wdt test to use > uclass_get_device_by_driver() since we now have to UCLASS_WDT > instances in play, so it's a little more robust to fetch the device by > driver and not merely uclass+index. > > Signed-off-by: Rasmus Villemoes > --- > arch/sandbox/dts/test.dts | 5 + > configs/sandbox64_defconfig | 1 + > configs/sandbox_defconfig | 1 + > test/dm/wdt.c | 32 +++- > 4 files changed, 38 insertions(+), 1 deletion(-) Reviewed-by: Simon Glass
Re: [PATCH v2 3/7] common: integrate crypt-based passwords
On Mon, 10 May 2021 at 00:19, Steffen Jaeckel wrote: > > Hook into the autoboot flow as an alternative to the existing > mechanisms. > > Signed-off-by: Steffen Jaeckel > --- > > (no changes since v1) > > common/Kconfig.boot | 37 ++--- > common/autoboot.c | 80 - > 2 files changed, 103 insertions(+), 14 deletions(-) Reviewed-by: Simon Glass But I think you'll need to allow both to be enabled.
Re: [PATCH 1/2] watchdog: add gpio watchdog driver
Hi Rasmus,
On Mon, 10 May 2021 at 09:47, Rasmus Villemoes
wrote:
>
> A rather common kind of external watchdog circuit is one that is kept
> alive by toggling a gpio. Add a driver for handling such a watchdog.
>
> The compatible string is probably a little odd as it has nothing to do
> with linux per se - however, I chose that to make .dts snippets
> reusable between device trees used with U-Boot and linux, and this is
> the (only) compatible string that linux' corresponding driver and DT
> binding accepts. I have asked whether one should/could add "wdt-gpio"
> to that binding, but the answer was no:
>
>
> https://lore.kernel.org/lkml/CAL_JsqKEGaFpiFV_oAtE+S_bnHkg4qry+bhx2EDs=nsbvf_...@mail.gmail.com/
>
> If someone feels strongly about this, I can certainly remove the
> "linux," part from the string - it probably wouldn't the only place where
> one can't reuse a DT snippet as-is between linux and U-Boot.
It seems fine to me. We share DT bindings with Linux anyway.
>
> Signed-off-by: Rasmus Villemoes
> ---
> .../watchdog/gpio-wdt.txt | 15 ++
> drivers/watchdog/Kconfig | 7 +++
> drivers/watchdog/Makefile | 1 +
> drivers/watchdog/gpio_wdt.c | 51 +++
> 4 files changed, 74 insertions(+)
> create mode 100644 doc/device-tree-bindings/watchdog/gpio-wdt.txt
> create mode 100644 drivers/watchdog/gpio_wdt.c
>
> diff --git a/doc/device-tree-bindings/watchdog/gpio-wdt.txt
> b/doc/device-tree-bindings/watchdog/gpio-wdt.txt
> new file mode 100644
> index 00..2283b7ba6e
> --- /dev/null
> +++ b/doc/device-tree-bindings/watchdog/gpio-wdt.txt
> @@ -0,0 +1,15 @@
> +GPIO watchdog timer
> +
> +Describes a simple watchdog timer which is reset by toggling a gpio.
> +
> +Required properties:
> +
> +- compatible: must be "linux,wdt-gpio"
> +- gpios: gpio to toggle when wdt driver reset method is called
> +
> +Example:
> +
> + gpio-wdt {
> + gpios = <&gpio0 1 0>;
> + compatible = "linux,wdt-gpio";
> + };
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index f0ff2612a6..2cf378db29 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -147,6 +147,13 @@ config WDT_CORTINA
> This driver support all CPU ISAs supported by Cortina
> Access CA SoCs.
>
> +config WDT_GPIO
> + bool "External gpio watchdog support"
> + depends on WDT
> + depends on DM_GPIO
> + help
> + Support for external watchdog fed by toggling a gpio.
please add a bit more detail. How do you configure it? e.g. point to
the binding file (which you should add to U-Boot if not there).
> +
> config WDT_MPC8xx
> bool "MPC8xx watchdog timer support"
> depends on WDT && MPC8xx
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index 5c7ef593fe..f14415bb8e 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -25,6 +25,7 @@ obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
> obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
> obj-$(CONFIG_WDT_ORION) += orion_wdt.o
> obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
> +obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
> obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
> obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o
> obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
> diff --git a/drivers/watchdog/gpio_wdt.c b/drivers/watchdog/gpio_wdt.c
> new file mode 100644
> index 00..9dba9c254e
> --- /dev/null
> +++ b/drivers/watchdog/gpio_wdt.c
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct gpio_wdt_priv {
> + struct gpio_desc gpio;
> + int state;
bool ?
> +};
> +
> +static int gpio_wdt_reset(struct udevice *dev)
> +{
> + struct gpio_wdt_priv *priv = dev_get_priv(dev);
> +
> + priv->state = !priv->state;
blank line before final return (please fix below also)
> + return dm_gpio_set_value(&priv->gpio, priv->state);
> +}
> +
> +static int dm_probe(struct udevice *dev)
> +{
> + struct gpio_wdt_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio,
> GPIOD_IS_OUT);
> + if (ret < 0) {
> + dev_err(dev, "Request for wdt gpio failed: %d\n", ret);
> + return ret;
> + }
> + return gpio_wdt_reset(dev);
> +}
> +
> +static const struct wdt_ops gpio_wdt_ops = {
> + .reset = gpio_wdt_reset,
> +};
> +
> +static const struct udevice_id gpio_wdt_ids[] = {
> + { .compatible = "linux,wdt-gpio" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(wdt_gpio) = {
> + .name = "wdt_gpio",
> + .id = UCLASS_WDT,
> + .of_match = gpio_wdt_ids,
> + .ops = &gpio_wdt_ops,
> + .probe = dm_probe,
> + .priv_auto = sizeof(struct gpio_wdt_priv),
> +};
> --
> 2.29.2
>
Regards,
Simon
Re: [PATCH v5 09/13] binman: Support packaging U-Boot for scenarios like OF_BOARD or OF_PRIOR_STAGE
On Mon, 10 May 2021 at 06:24, Bin Meng wrote: > > For scenarios like OF_BOARD or OF_PRIOR_STAGE, no device tree blob is > provided in the U-Boot build phase hence the binman node information > is not available. In order to support such use case, a new Kconfig > option BINMAN_STANDALONE_FDT is introduced, to tell the build system > that a device tree blob containing binman node is explicitly required > when using binman to package U-Boot. > > Signed-off-by: Bin Meng > > --- > > Changes in v5: > - update binman.rst for OF_BOARD or OF_PRIOR_STAGE usage > > Changes in v4: > - update the makefile dependency on u-boot.img instead of u-boot.bin > > Changes in v3: > - rename the Kconfig option name to BINMAN_STANDALONE_FDT > - make BINMAN_STANDALONE_FDT default y for OF_BOARD as well > - reword the Kconfig option help message a little bit > > Changes in v2: > - new patch: "binman: Support packaging U-Boot for scenarios like > OF_PRIOR_STAGE" > > Makefile| 3 ++- > dts/Kconfig | 18 ++ > tools/binman/binman.rst | 24 > 3 files changed, 44 insertions(+), 1 deletion(-) Reviewed-by: Simon Glass
Re: [PATCH v2 01/50] lib: Add memdup()
Hi Rasmus, On Mon, 10 May 2021 at 03:00, Rasmus Villemoes wrote: > > On 06/05/2021 19.41, Simon Glass wrote: > > Hi Pratyush, > > > > On Thu, 6 May 2021 at 10:07, Pratyush Yadav wrote: > >> > >> On 06/05/21 08:23AM, Simon Glass wrote: > >>> Add a function to duplicate a memory region, a little like strdup(). > >>> > >>> Signed-off-by: Simon Glass > >>> --- > >>> > >>> Changes in v2: > >>> - Add a patch to introduce a memdup() function > >>> > >>> include/linux/string.h | 13 + > >>> lib/string.c | 13 + > >>> test/lib/string.c | 32 > >>> 3 files changed, 58 insertions(+) > >>> > >>> diff --git a/include/linux/string.h b/include/linux/string.h > >>> index dd255f21633..3169c93796e 100644 > >>> --- a/include/linux/string.h > >>> +++ b/include/linux/string.h > >>> @@ -129,6 +129,19 @@ extern void * memchr(const void > >>> *,int,__kernel_size_t); > >>> void *memchr_inv(const void *, int, size_t); > >>> #endif > >>> > >>> +/** > >>> + * memdup() - allocate a buffer and copy in the contents > >>> + * > >>> + * Note that this returns a valid pointer even if @len is 0 > >> > >> I'm uneducated about U-Boot's memory allocator. But I wonder how it > >> returns a valid pointer even on 0 length allocations. What location does > >> it point to? What are users expected to do with that pointer? They > >> obviously can't read/write to it since it is supposed to be a 0 byte > >> long allocation. If another positive length allocation happens before > >> the said pointer is freed, will it point to the same memory location? If > >> not, isn't the 0-length pointer actually at least a 1-length pointer? > > > > I think it is just a 0-length pointer and that the only thing you can > > do with it is call free(). > > > > I am certainly no expert on this sort of thing though. It seems that > > some implementations return NULL for a zero size, some return a valid > > pointer which can be passed to free(). > > It's implementation-defined, which means that one cannot know for > certain that a given malloc implementation won't return NULL for a > request of 0 bytes. The linux kernel solved that problem by introducing This function is for U-Boot board code. Note that the C-library malloc() is used for tools and we don't run these tests using that, so it is safe to assume that it is the U-Boot malloc() that is used in all cases where this function is used. > ZERO_SIZE_PTR which is basically just (void*)16L or something like that > - that way callers don't have to write their "did the allocation > succeed" test in the ugly > > if (!p && size != 0) > error_out; > > way. Of course kfree() must then accept that in addition to NULL, but > it's not really more expensive to have that early nop check be > > if ((unsigned long)ptr <= 16) > return; > > instead of > > if (!ptr) > return; > > > "man malloc" says > > RETURN VALUE >The malloc() and calloc() functions return a pointer to the > allocated memory, which is suitably aligned for any built-in type. On > error, these functions >return NULL. NULL may also be returned by a successful call to > malloc() with a size of zero, or by a successful call to calloc() with > nmemb or size equal >to zero. > > > Anyway, I don't think this helper should be put in string.c - it needs > to be in some C file that's easily compiled for both board, sandbox and > host tools (for the latter probably via the "tiny one-line wrapper that > just includes the whole real C file"). I see there's linux_string.c already. I'm not a big fan of adding a function that can be used from tools as well as U-Boot. Sandbox just uses the U-Boot libraries, so far as possible. Only a few files even compile with the host C libraries (e.g. os.c). So if we want this functionality in the host tools, I suggest we add it into the tools dir somewhere. Regards, SImon
Re: [PATCH v5 08/13] lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED
Hi Simon, On Tue, May 11, 2021 at 12:28 AM Simon Glass wrote: > > Hi Bin, > > On Mon, 10 May 2021 at 06:24, Bin Meng wrote: > > > > Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED. > > For the other OF_CONTROL methods, it's quite possible binman node is > > not available as binman is invoked during the build phase instead of > > runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default. > > > > Signed-off-by: Bin Meng > > > > --- > > > > (no changes since v3) > > > > Changes in v3: > > - new patch: "lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED" > > > > lib/Kconfig | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > I think you need to handle the sandbox case too - OF_HOSTFILE Ah, that's odd :) Or maybe we should just ignore the -ENOENT error and return 0 in binman_init(), instead of changing the Kconfig? ret = find_image_node(&binman->image); if (ret) return 0; What do you think? > > Perhaps we don't have tests for this? I need to add some. Regards, Bin
Re: [PATCH v5 08/13] lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED
Hi Bin, On Mon, 10 May 2021 at 10:34, Bin Meng wrote: > > Hi Simon, > > On Tue, May 11, 2021 at 12:28 AM Simon Glass wrote: > > > > Hi Bin, > > > > On Mon, 10 May 2021 at 06:24, Bin Meng wrote: > > > > > > Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED. > > > For the other OF_CONTROL methods, it's quite possible binman node is > > > not available as binman is invoked during the build phase instead of > > > runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default. > > > > > > Signed-off-by: Bin Meng > > > > > > --- > > > > > > (no changes since v3) > > > > > > Changes in v3: > > > - new patch: "lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED" > > > > > > lib/Kconfig | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > I think you need to handle the sandbox case too - OF_HOSTFILE > > Ah, that's odd :) > > Or maybe we should just ignore the -ENOENT error and return 0 in > binman_init(), instead of changing the Kconfig? > > ret = find_image_node(&binman->image); > if (ret) > return 0; > > What do you think? Not too keen since I'd like to know if it works, i.e. keep it deterministic. So if sandbox still runs OK with this change, then we can figure it out later. Reviewed-by: Simon Glass Regards, Simon
Re: [PATCH v2 3/7] common: integrate crypt-based passwords
On 5/10/21 6:27 PM, Simon Glass wrote: > On Mon, 10 May 2021 at 00:19, Steffen Jaeckel > wrote: >> >> Hook into the autoboot flow as an alternative to the existing >> mechanisms. >> >> Signed-off-by: Steffen Jaeckel >> --- >> >> (no changes since v1) >> >> common/Kconfig.boot | 37 ++--- >> common/autoboot.c | 80 - >> 2 files changed, 103 insertions(+), 14 deletions(-) > > Reviewed-by: Simon Glass > > But I think you'll need to allow both to be enabled. Sorry, but what exactly do you mean?
Re: [PATCH v2 2/7] lib: wrap crypt API to hide errno usage
On 5/10/21 6:27 PM, Simon Glass wrote: > On Mon, 10 May 2021 at 00:19, Steffen Jaeckel > wrote: >> >> In order to prevent using the global errno, replace it with a static >> version and create a wrapper function which returns the error value. >> >> Signed-off-by: Steffen Jaeckel >> --- >> >> (no changes since v1) >> >> include/crypt.h | 3 ++- >> lib/crypt/alg-sha256.h | 6 -- >> lib/crypt/alg-sha512.h | 6 -- >> lib/crypt/crypt-port.h | 18 ++ >> lib/crypt/crypt-sha256.c | 26 -- >> lib/crypt/crypt-sha512.c | 26 -- >> lib/crypt/crypt.c| 25 ++--- >> test/lib/test_crypt.c| 24 ++-- >> 8 files changed, 96 insertions(+), 38 deletions(-) >> > > Reviewed-by: Simon Glass Thx! Cheers Steffen
[PATCH 0/7] J72xx: R5 SPL DMA support post HSM Rearch
This series add DMA support for R5 SPL on J721e/J7200 SoCs post HSM Rearch. Depends on Tero's base HSM rearch support series. Vignesh Raghavendra (7): mailbox: k3-sec-proxy: Add DM to DMSC communication thread firmware: ti_sci: Implement GET_RANGE with static data firmware: ti_sci: Add support for Resoure Management at R5 SPL stage. ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node ARM: dts: k3: Add cfg register space for ringacc and udmap soc: ti: k3-navss-ringacc: Add support for native configuration of rings dma: ti: k3-udma: Add support for native configuration of chan/flow arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++ .../k3-j7200-common-proc-board-u-boot.dtsi| 26 +++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 17 ++ .../k3-j721e-common-proc-board-u-boot.dtsi| 14 ++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 18 ++ .../firmware/ti,j721e-dm-sci.txt | 32 drivers/dma/ti/k3-udma-u-boot.c | 177 ++ drivers/dma/ti/k3-udma.c | 42 - drivers/firmware/ti_sci.c | 107 +++ drivers/firmware/ti_sci_static_data.h | 92 + drivers/mailbox/k3-sec-proxy.c| 2 +- drivers/soc/ti/k3-navss-ringacc-u-boot.c | 61 ++ drivers/soc/ti/k3-navss-ringacc.c | 36 +++- 13 files changed, 630 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt create mode 100644 drivers/dma/ti/k3-udma-u-boot.c create mode 100644 drivers/firmware/ti_sci_static_data.h create mode 100644 drivers/soc/ti/k3-navss-ringacc-u-boot.c -- 2.31.1
[PATCH 1/7] mailbox: k3-sec-proxy: Add DM to DMSC communication thread
R5 SPL would need to talk to DMSC using DM to DMSC sec-proxy threads.
Mark these as valid threads in the driver.
Signed-off-by: Vignesh Raghavendra
---
drivers/mailbox/k3-sec-proxy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index 88f320515a..20fdb09f31 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@@ -409,7 +409,7 @@ static int k3_sec_proxy_remove(struct udevice *dev)
return 0;
}
-static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13 };
+static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13,
20, 21, 22, 23 };
static const struct k3_sec_proxy_desc am654_desc = {
.thread_count = 90,
--
2.31.1
[PATCH 2/7] firmware: ti_sci: Implement GET_RANGE with static data
In case of R5 SPL, GET_RANGE API service is not available (as DM
services are not yet up), therefore service such calls locally using
per SoC static data.
Signed-off-by: Vignesh Raghavendra
---
drivers/firmware/ti_sci.c | 36 +++
drivers/firmware/ti_sci_static_data.h | 92 +++
2 files changed, 128 insertions(+)
create mode 100644 drivers/firmware/ti_sci_static_data.h
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 2aec2e34d3..c27fbc682a 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -23,6 +23,7 @@
#include
#include "ti_sci.h"
+#include "ti_sci_static_data.h"
/* List of all TI SCI devices active in system */
static LIST_HEAD(ti_sci_list);
@@ -1667,6 +1668,33 @@ fail:
return ret;
}
+static int __maybe_unused
+ti_sci_get_resource_range_static(u32 dev_id, u8 subtype, u16 *range_start,
+u16 *range_num)
+{
+ struct ti_sci_resource_static_data *data;
+ int i = 0;
+
+ while (1) {
+ data = &rm_static_data[i];
+
+ if (!data->dev_id)
+ return -EINVAL;
+
+ if (data->dev_id != dev_id || data->subtype != subtype) {
+ i++;
+ continue;
+ }
+
+ *range_start = data->range_start;
+ *range_num = data->range_num;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
/**
* ti_sci_cmd_get_resource_range - Get a range of resources assigned to host
*that is same as ti sci interface host.
@@ -1683,6 +1711,11 @@ static int ti_sci_cmd_get_resource_range(const struct
ti_sci_handle *handle,
u32 dev_id, u8 subtype,
u16 *range_start, u16 *range_num)
{
+ if (CONFIG_IS_ENABLED(TI_K3_RAW_RM))
+ return ti_sci_get_resource_range_static(dev_id, subtype,
+ range_start,
+ range_num);
+
return ti_sci_get_resource_range(handle, dev_id, subtype,
TI_SCI_IRQ_SECONDARY_HOST_INVALID,
range_start, range_num);
@@ -1706,6 +1739,9 @@ int ti_sci_cmd_get_resource_range_from_shost(const struct
ti_sci_handle *handle,
u32 dev_id, u8 subtype, u8 s_host,
u16 *range_start, u16 *range_num)
{
+ if (CONFIG_IS_ENABLED(TI_K3_RAW_RM))
+ return -EINVAL;
+
return ti_sci_get_resource_range(handle, dev_id, subtype, s_host,
range_start, range_num);
}
diff --git a/drivers/firmware/ti_sci_static_data.h
b/drivers/firmware/ti_sci_static_data.h
new file mode 100644
index 00..2816cb2827
--- /dev/null
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ */
+
+#ifndef __TI_SCI_STATIC_DATA_H
+#define __TI_SCI_STATIC_DATA_H
+
+struct ti_sci_resource_static_data {
+ u32 dev_id;
+ u16 range_start;
+ u16 range_num;
+ u8 subtype;
+};
+
+#if IS_ENABLED(CONFIG_K3_DM_FW)
+
+#ifdef CONFIG_TARGET_J721E_R5_EVM
+static struct ti_sci_resource_static_data rm_static_data[] = {
+ /* Free rings */
+ {
+ .dev_id = 235,
+ .subtype = 1,
+ .range_start = 124,
+ .range_num = 32,
+ },
+ /* TX channels */
+ {
+ .dev_id = 236,
+ .subtype = 13,
+ .range_start = 6,
+ .range_num = 2,
+ },
+ /* RX channels */
+ {
+ .dev_id = 236,
+ .subtype = 10,
+ .range_start = 6,
+ .range_num = 2,
+ },
+ /* RX Free flows */
+ {
+ .dev_id = 236,
+ .subtype = 0,
+ .range_start = 60,
+ .range_num = 8,
+ },
+ { },
+};
+#endif /* CONFIG_TARGET_J721E_R5_EVM */
+
+#ifdef CONFIG_TARGET_J7200_R5_EVM
+static struct ti_sci_resource_static_data rm_static_data[] = {
+ /* Free rings */
+ {
+ .dev_id = 235,
+ .subtype = 1,
+ .range_start = 144,
+ .range_num = 32,
+ },
+ /* TX channels */
+ {
+ .dev_id = 236,
+ .subtype = 13,
+ .range_start = 7,
+ .range_num = 2,
+ },
+ /* RX channels */
+ {
+ .dev_id = 236,
+ .subtype = 10,
+ .range_start = 7,
+ .range_num = 2,
+ },
+ /* RX Free flows */
+ {
+ .dev_id = 236,
+
[PATCH 3/7] firmware: ti_sci: Add support for Resoure Management at R5 SPL stage.
On J721e and J7200, MCU R5 core (boot master) itself would run Device
Manager (DM) Firmware and interact with TI Foundational Security (TIFS)
firmware to enable DMA and such other Resource Management (RM) services.
So, during R5 SPL stage there is no such RM service available and ti_sci
driver will have to directly interact with TIFS using DM to DMSC
channels to request RM resources.
Therefore add DT binding and driver for the same. This driver will
handle Resource Management services at R5 SPL stage.
Signed-off-by: Vignesh Raghavendra
---
.../firmware/ti,j721e-dm-sci.txt | 32 +++
drivers/firmware/ti_sci.c | 91 +--
2 files changed, 113 insertions(+), 10 deletions(-)
create mode 100644 doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt
diff --git a/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt
b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt
new file mode 100644
index 00..0217341f0c
--- /dev/null
+++ b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt
@@ -0,0 +1,32 @@
+Bindings for Texas Instruments System Control Interface (TI-SCI) Message
+Protocol for Device Manager(DM) to TI Foundational Security(TIFS)
+Firmware communication
+
+Required properties:
+
+- compatible: should be "ti,j721e-dm-sci"
+- mbox-names:
+ "rx" - Mailbox corresponding to receive path
+ "tx" - Mailbox corresponding to transmit path
+
+- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes
+ property should contain a phandle to the mailbox controller device
+ node and an args specifier that will be the phandle to the intended
+ sub-mailbox child node to be used for communication.
+
+- ti,host-id: Host ID to use for communication.
+
+Optional Properties:
+
+- ti,secure-host: If the host is defined as secure.
+
+Example:
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ };
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index c27fbc682a..f75ad5db67 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -1669,8 +1669,9 @@ fail:
}
static int __maybe_unused
-ti_sci_get_resource_range_static(u32 dev_id, u8 subtype, u16 *range_start,
-u16 *range_num)
+ti_sci_cmd_get_resource_range_static(const struct ti_sci_handle *handle,
+u32 dev_id, u8 subtype,
+u16 *range_start, u16 *range_num)
{
struct ti_sci_resource_static_data *data;
int i = 0;
@@ -1711,11 +1712,6 @@ static int ti_sci_cmd_get_resource_range(const struct
ti_sci_handle *handle,
u32 dev_id, u8 subtype,
u16 *range_start, u16 *range_num)
{
- if (CONFIG_IS_ENABLED(TI_K3_RAW_RM))
- return ti_sci_get_resource_range_static(dev_id, subtype,
- range_start,
- range_num);
-
return ti_sci_get_resource_range(handle, dev_id, subtype,
TI_SCI_IRQ_SECONDARY_HOST_INVALID,
range_start, range_num);
@@ -1739,9 +1735,6 @@ int ti_sci_cmd_get_resource_range_from_shost(const struct
ti_sci_handle *handle,
u32 dev_id, u8 subtype, u8 s_host,
u16 *range_start, u16 *range_num)
{
- if (CONFIG_IS_ENABLED(TI_K3_RAW_RM))
- return -EINVAL;
-
return ti_sci_get_resource_range(handle, dev_id, subtype, s_host,
range_start, range_num);
}
@@ -3051,6 +3044,58 @@ static int ti_sci_probe(struct udevice *dev)
return ret;
}
+/**
+ * ti_sci_dm_probe() - Basic probe for DM to TIFS SCI
+ * @dev: corresponding system controller interface device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static __maybe_unused int ti_sci_dm_probe(struct udevice *dev)
+{
+ struct ti_sci_rm_core_ops *rm_core_ops;
+ struct ti_sci_rm_udmap_ops *udmap_ops;
+ struct ti_sci_rm_ringacc_ops *rops;
+ struct ti_sci_rm_psil_ops *psilops;
+ struct ti_sci_ops *ops;
+ struct ti_sci_info *info;
+ int ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ info = dev_get_priv(dev);
+ info->desc = (void *)dev_get_driver_data(dev);
+
+ ret = ti_sci_of_to_info(dev, info);
+ if (ret) {
+ dev_err(dev, "%s: Probe failed with error %d\n", __func__, ret);
+ return ret;
+ }
+
+ info->dev = d
[PATCH 4/7] ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node
Add DM firmware node which will provide DM services during R5 SPL stage.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 17 +
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 18 ++
2 files changed, 35 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 0491432060..9963746c1d 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -79,6 +79,16 @@
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
};
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ u-boot,dm-spl;
+ };
};
&dmsc {
@@ -276,4 +286,11 @@
};
};
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
#include "k3-j7200-common-proc-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 4e8422e662..0542b2f8b8 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -76,6 +76,16 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ u-boot,dm-spl;
+ };
};
&cbass_main {
@@ -345,3 +355,11 @@
u-boot,dm-spl;
};
};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
--
2.31.1
[PATCH 5/7] ARM: dts: k3: Add cfg register space for ringacc and udmap
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING
CFG, TCHAN CFG and RCHAN CFG address ranges.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++
.../k3-j7200-common-proc-board-u-boot.dtsi| 26 +++
.../k3-j721e-common-proc-board-u-boot.dtsi| 14 ++
3 files changed, 54 insertions(+)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index b0602d1dad..2840258518 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -35,11 +35,25 @@
u-boot,dm-spl;
ringacc@2b80 {
+ reg = <0x0 0x2b80 0x0 0x40>,
+ <0x0 0x2b00 0x0 0x40>,
+ <0x0 0x2859 0x0 0x100>,
+ <0x0 0x2a50 0x0 0x4>,
+ <0x0 0x2844 0x0 0x4>;
+ reg-names = "rt", "fifos", "proxy_gcfg",
"proxy_target", "cfg";
u-boot,dm-spl;
ti,dma-ring-reset-quirk;
};
dma-controller@285c {
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x284c 0x0 0x4000>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x284a 0x0 0x4000>,
+ <0x0 0x2aa0 0x0 0x4>,
+ <0x0 0x2840 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
u-boot,dm-spl;
};
};
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index c3aae65b39..41ce9fcb59 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -40,6 +40,32 @@
chipid@4314 {
u-boot,dm-spl;
};
+
+ mcu-navss{
+ u-boot,dm-spl;
+
+ ringacc@2b80 {
+ reg = <0x0 0x2b80 0x0 0x40>,
+ <0x0 0x2b00 0x0 0x40>,
+ <0x0 0x2859 0x0 0x100>,
+ <0x0 0x2a50 0x0 0x4>,
+ <0x0 0x2844 0x0 0x4>;
+ reg-names = "rt", "fifos", "proxy_gcfg",
"proxy_target", "cfg";
+ u-boot,dm-spl;
+ };
+
+ dma-controller@285c {
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x284c 0x0 0x4000>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x284a 0x0 0x4000>,
+ <0x0 0x2aa0 0x0 0x4>,
+ <0x0 0x2840 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+ };
+ };
};
&secure_proxy_main {
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 1135de5a92..ed64f2720d 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -54,10 +54,24 @@
u-boot,dm-spl;
ringacc@2b80 {
+ reg = <0x0 0x2b80 0x0 0x40>,
+ <0x0 0x2b00 0x0 0x40>,
+ <0x0 0x2859 0x0 0x100>,
+ <0x0 0x2a50 0x0 0x4>,
+ <0x0 0x2844 0x0 0x4>;
+ reg-names = "rt", "fifos", "proxy_gcfg",
"proxy_target", "cfg";
u-boot,dm-spl;
};
dma-controller@285c {
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x284c 0x0 0x4000>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x284a 0x0 0x4000>,
+ <0x0 0x2aa0 0x0 0x4>,
+ <0x0 0x2840 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
u-boot,dm-spl;
};
};
--
2.31.1
[PATCH 6/7] soc: ti: k3-navss-ringacc: Add support for native configuration of rings
In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup Ring Cfg registers. Add support for
the same.
Note that we still need to send RING_CFG message to TIFS via TISCI
client driver in order to open up firewalls around Rings.
U-Boot specific code is in a separate file included in main driver so
as to maintain similarity with kernel driver in order to ease porting of
code in future.
Signed-off-by: Vignesh Raghavendra
---
drivers/soc/ti/k3-navss-ringacc-u-boot.c | 61
drivers/soc/ti/k3-navss-ringacc.c| 36 --
2 files changed, 94 insertions(+), 3 deletions(-)
create mode 100644 drivers/soc/ti/k3-navss-ringacc-u-boot.c
diff --git a/drivers/soc/ti/k3-navss-ringacc-u-boot.c
b/drivers/soc/ti/k3-navss-ringacc-u-boot.c
new file mode 100644
index 00..f958239c2a
--- /dev/null
+++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot specific helpers for TI K3 AM65x NAVSS Ring accelerator
+ * Manager (RA) subsystem driver
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+struct k3_nav_ring_cfg_regs {
+ u32 resv_64[16];
+ u32 ba_lo; /* Ring Base Address Lo Register */
+ u32 ba_hi; /* Ring Base Address Hi Register */
+ u32 size; /* Ring Size Register */
+ u32 event; /* Ring Event Register */
+ u32 orderid;/* Ring OrderID Register */
+};
+
+#define KNAV_RINGACC_CFG_REGS_STEP 0x100
+
+#define KNAV_RINGACC_CFG_RING_BA_HI_ADDR_HI_MASK GENMASK(15, 0)
+
+#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK GENMASK(31, 30)
+#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT (30)
+
+#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK GENMASK(26, 24)
+#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT(24)
+
+static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring)
+{
+ writel(0, &ring->cfg->size);
+}
+
+static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum
k3_nav_ring_mode mode)
+{
+ u32 val;
+
+ val = readl(&ring->cfg->size);
+ val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK;
+ val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT;
+ writel(val, &ring->cfg->size);
+}
+
+static void k3_ringacc_ring_free_raw(struct k3_nav_ring *ring)
+{
+ writel(0, &ring->cfg->ba_hi);
+ writel(0, &ring->cfg->ba_lo);
+ writel(0, &ring->cfg->size);
+}
+
+static void k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring *ring)
+{
+ u32 val;
+
+ writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo);
+ writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi);
+
+ val = ring->mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT |
+ ring->elm_size << KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT |
+ ring->size;
+ writel(val, &ring->cfg->size);
+}
diff --git a/drivers/soc/ti/k3-navss-ringacc.c
b/drivers/soc/ti/k3-navss-ringacc.c
index b5a5c9da98..f110d78ce1 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -124,6 +124,7 @@ struct k3_nav_ring_state {
/**
* struct k3_nav_ring - RA Ring descriptor
*
+ * @cfg - Ring configuration registers
* @rt - Ring control/status registers
* @fifos - Ring queues registers
* @ring_mem_dma - Ring buffer dma address
@@ -138,6 +139,7 @@ struct k3_nav_ring_state {
* @use_count - Use count for shared rings
*/
struct k3_nav_ring {
+ struct k3_nav_ring_cfg_regs __iomem *cfg;
struct k3_nav_ring_rt_regs __iomem *rt;
struct k3_nav_ring_fifo_regs __iomem *fifos;
dma_addr_t ring_mem_dma;
@@ -195,6 +197,8 @@ struct k3_nav_ringacc {
bool dual_ring;
};
+#include "k3-navss-ringacc-u-boot.c"
+
static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring)
{
return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK;
@@ -330,6 +334,9 @@ static void k3_ringacc_ring_reset_sci(struct k3_nav_ring
*ring)
struct k3_nav_ringacc *ringacc = ring->parent;
int ret;
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ return k3_ringacc_ring_reset_raw(ring);
+
ret = ringacc->tisci_ring_ops->config(
ringacc->tisci,
TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID,
@@ -362,6 +369,9 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct
k3_nav_ring *ring,
struct k3_nav_ringacc *ringacc = ring->parent;
int ret;
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ return k3_ringacc_ring_reconfig_qmode_raw(ring, mode);
+
ret = ringacc->tisci_ring_ops->config(
ringacc->tisci,
TI_SCI_MSG_VALUE_RM_RING_MODE_VALID,
@@ -442,6 +452,9 @@ static void k3_ringacc_ring_free_sci(struct k3_nav_ring
*ring)
struct k3_nav_ringacc *ringacc = ring->
[PATCH 7/7] dma: ti: k3-udma: Add support for native configuration of chan/flow
In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers.
Add support for the same.
Note that we still need to send chan/flow cfg message to TIFS via TISCI
client driver in order to open up firewalls around chan/flow but setting
up of cfg registers is handled locally.
U-Boot specific code is in a separate file included in main driver so
as to maintain similarity with kernel driver in order to ease porting of
code in future.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma-u-boot.c | 177
drivers/dma/ti/k3-udma.c| 42 +++-
2 files changed, 215 insertions(+), 4 deletions(-)
create mode 100644 drivers/dma/ti/k3-udma-u-boot.c
diff --git a/drivers/dma/ti/k3-udma-u-boot.c b/drivers/dma/ti/k3-udma-u-boot.c
new file mode 100644
index 00..3e04f551e2
--- /dev/null
+++ b/drivers/dma/ti/k3-udma-u-boot.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#define UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT (16)
+
+/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */
+#define UDMA_RFLOW_SRCTAG_NONE 0
+#define UDMA_RFLOW_SRCTAG_CFG_TAG 1
+#define UDMA_RFLOW_SRCTAG_FLOW_ID 2
+#define UDMA_RFLOW_SRCTAG_SRC_TAG 4
+
+#define UDMA_RFLOW_DSTTAG_NONE 0
+#define UDMA_RFLOW_DSTTAG_CFG_TAG 1
+#define UDMA_RFLOW_DSTTAG_FLOW_ID 2
+#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4
+#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5
+
+#define UDMA_RFLOW_RFC_DEFAULT \
+ ((UDMA_RFLOW_SRCTAG_NONE << UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT) | \
+(UDMA_RFLOW_SRCTAG_SRC_TAG << UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT) | \
+(UDMA_RFLOW_DSTTAG_DST_TAG_HI << UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT)
| \
+(UDMA_RFLOW_DSTTAG_DST_TAG_LO << UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT))
+
+#define UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT (16)
+
+/* TCHAN */
+static inline u32 udma_tchan_read(struct udma_tchan *tchan, int reg)
+{
+ if (!tchan)
+ return 0;
+ return udma_read(tchan->reg_chan, reg);
+}
+
+static inline void udma_tchan_write(struct udma_tchan *tchan, int reg, u32 val)
+{
+ if (!tchan)
+ return;
+ udma_write(tchan->reg_chan, reg, val);
+}
+
+static inline void udma_tchan_update_bits(struct udma_tchan *tchan, int reg,
+ u32 mask, u32 val)
+{
+ if (!tchan)
+ return;
+ udma_update_bits(tchan->reg_chan, reg, mask, val);
+}
+
+/* RCHAN */
+static inline u32 udma_rchan_read(struct udma_rchan *rchan, int reg)
+{
+ if (!rchan)
+ return 0;
+ return udma_read(rchan->reg_chan, reg);
+}
+
+static inline void udma_rchan_write(struct udma_rchan *rchan, int reg, u32 val)
+{
+ if (!rchan)
+ return;
+ udma_write(rchan->reg_chan, reg, val);
+}
+
+static inline void udma_rchan_update_bits(struct udma_rchan *rchan, int reg,
+ u32 mask, u32 val)
+{
+ if (!rchan)
+ return;
+ udma_update_bits(rchan->reg_chan, reg, mask, val);
+}
+
+/* RFLOW */
+static inline u32 udma_rflow_read(struct udma_rflow *rflow, int reg)
+{
+ if (!rflow)
+ return 0;
+ return udma_read(rflow->reg_rflow, reg);
+}
+
+static inline void udma_rflow_write(struct udma_rflow *rflow, int reg, u32 val)
+{
+ if (!rflow)
+ return;
+ udma_write(rflow->reg_rflow, reg, val);
+}
+
+static inline void udma_rflow_update_bits(struct udma_rflow *rflow, int reg,
+ u32 mask, u32 val)
+{
+ if (!rflow)
+ return;
+ udma_update_bits(rflow->reg_rflow, reg, mask, val);
+}
+
+static void udma_alloc_tchan_raw(struct udma_chan *uc)
+{
+ u32 mode, fetch_size;
+
+ if (uc->config.pkt_mode)
+ mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR;
+ else
+ mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR;
+
+ udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG,
+ UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode);
+
+ if (uc->config.dir == DMA_MEM_TO_MEM)
+ fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
+ else
+ fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
+ uc->config.psd_size, 0) >> 2;
+
+ udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG,
+ UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size);
+ udma_tchan_write(uc->tchan, UDMA_TCHAN_TCQ_REG,
+k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring));
+}
+
+static void udma_alloc_rchan_raw(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ int fd_ring = k3_nav_ringacc_get_ring_id(uc->rflow->fd_ring);
+ int
[PATCH] board: ti: am64x: Parse MAC address from board EEPROM
Parse MAC addresses from EEPROM and set them in the env. This is needed
to get MAC address for additional ethernet ports on the EVM.
Signed-off-by: Vignesh Raghavendra
---
board/ti/am64x/evm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index a1ffcb929c..35cd9e027c 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -136,8 +136,17 @@ static void setup_serial(void)
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
setup_board_eeprom_env();
setup_serial();
+ /*
+* The first MAC address for ethernet a.k.a. ethernet0 comes
from
+* efuse populated via the am654 gigabit eth switch subsystem
driver.
+* All the other ones are populated via EEPROM, hence continue
with
+* an index of 1.
+*/
+ board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
}
return 0;
--
2.31.1
[PATCH] efi_loader: Clean up tcg2 once in case of failure
efi_init_event_log() calls tcg2_uninit() in case of failure. We can skip that since the function is called on efi_tcg2_register() which also cleans up if an error occurs Signed-off-by: Ilias Apalodimas --- lib/efi_loader/efi_tcg2.c | 4 1 file changed, 4 deletions(-) diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 94e8f22bbb69..570cc746ed4e 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -1053,12 +1053,8 @@ static efi_status_t efi_init_event_log(void) event_log.last_event_size = event_log.pos; ret = create_final_event(); - if (ret != EFI_SUCCESS) - goto out; - return EFI_SUCCESS; out: - tcg2_uninit(); return ret; } -- 2.31.0
[PATCH] efi_loader: Uninstall the TCG2 protocol if logging s-crtm fails
Instead of just failing, clean up the installed config table and EventLog memory if logging an s-crtm event fails during the protocol installation Signed-off-by: Ilias Apalodimas --- lib/efi_loader/efi_tcg2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 570cc746ed4e..8f8a26e7b7ae 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -1113,7 +1113,7 @@ efi_status_t efi_tcg2_register(void) ret = efi_append_scrtm_version(dev); if (ret != EFI_SUCCESS) - goto out; + goto fail; ret = efi_add_protocol(efi_root, &efi_guid_tcg2_protocol, (void *)&efi_tcg2_protocol); -- 2.31.0
Re: [PATCH v2 7/7] configs: add new sandbox with crypt-based password
Hi Simon, On 5/10/21 6:28 PM, Simon Glass wrote: > Hi Steffen, > > On Mon, 10 May 2021 at 00:19, Steffen Jaeckel > wrote: >> >> This is a copy of the regular sandbox with crypt-based password entry >> enabled. >> >> Signed-off-by: Steffen Jaeckel >> --- >> >> (no changes since v1) >> >> configs/sandbox_cryptpass_defconfig | 296 >> 1 file changed, 296 insertions(+) >> create mode 100644 configs/sandbox_cryptpass_defconfig > > Is this so you can add a test? In that case I think you need to adjust > things... > > For sandbox you need to be able to build in both options, so your > if/else approach won't work. > > You could control it with an env var perhaps, when both are enabled. > Then it is easy enough to select the required setup with sandbox. as mentioned in the cover letter, I guess this commit could also be removed. I'm going to make a v3 without it.
