RE: [PATCH] ARM: rmobile: beacon-renesom: Enable QSPI NOR Flash
Hi Adam,
Thanks for the patch.
> -Original Message-
> From: Adam Ford
> Sent: 28 May 2021 01:31
> To: u-boot@lists.denx.de
> Cc: Biju Das ; Adam Ford
> Subject: [PATCH] ARM: rmobile: beacon-renesom: Enable QSPI NOR Flash
>
> There is a QSPI NOR flash part on the board. Because this chip isn't yet
> supported in Linux, but it is supported in U-Boot, and the face that the
> RPC_SPI compatible names are different in U-Boot and Linux, the device
> tree updates are confined to -u-boot.dtsi files.
>
If RPC is configured for secure access in TF-A, u-boot fails. This patch works
only
if RPC configured for normal access(by compiling TF-A with
RZG_RPC_HYPERFLASH_LOCKED=0).
May be you need to update this in the commit message.
> Signed-off-by: Adam Ford
Reviewed-by: Biju Bas
>
> diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
> b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
> index a0c0a7f35c..06271537b7 100644
> --- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
> +++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
> @@ -4,11 +4,19 @@
> */
>
> / {
> + aliases {
> + spi0 = &rpc;
> + };
> +
> soc {
> u-boot,dm-pre-reloc;
> };
> };
>
> +&avb {
> + phy-mode = "rgmii-txid";
> +};
> +
> &cpg {
> u-boot,dm-pre-reloc;
> };
> @@ -25,6 +33,25 @@
> u-boot,dm-pre-reloc;
> };
>
> +&rpc {
> + compatible = "renesas,rcar-gen3-rpc";
> + num-cs = <1>;
> + spi-max-frequency = <4000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + flash0: spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + compatible = "spi-flash", "jedec,spi-nor";
> + spi-max-frequency = <4000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> +};
> +
> &sdhi0 {
> /delete-property/ cd-gpios;
> };
> diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
> b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
> index a0c0a7f35c..be0ce54e55 100644
> --- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
> +++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
> @@ -4,6 +4,10 @@
> */
>
> / {
> + aliases {
> + spi0 = &rpc;
> + };
> +
> soc {
> u-boot,dm-pre-reloc;
> };
> @@ -25,6 +29,25 @@
> u-boot,dm-pre-reloc;
> };
>
> +&rpc {
> + compatible = "renesas,rcar-gen3-rpc";
> + num-cs = <1>;
> + spi-max-frequency = <4000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + flash0: spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + compatible = "spi-flash", "jedec,spi-nor";
> + spi-max-frequency = <4000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> +};
> +
> &sdhi0 {
> /delete-property/ cd-gpios;
> };
> diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
> b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
> index eef200af2d..228391e0df 100644
> --- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
> +++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
> @@ -4,6 +4,10 @@
> */
>
> / {
> + aliases {
> + spi0 = &rpc;
> + };
> +
> soc {
> u-boot,dm-pre-reloc;
> };
> @@ -25,6 +29,25 @@
> u-boot,dm-pre-reloc;
> };
>
> +&rpc {
> + compatible = "renesas,rcar-gen3-rpc";
> + num-cs = <1>;
> + spi-max-frequency = <4000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + flash0: spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + compatible = "spi-flash", "jedec,spi-nor";
> + spi-max-frequency = <4000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> +};
> +
> &sdhi0 {
> /delete-property/ cd-gpios;
> sd-uhs-sdr12;
> diff --git a/configs/r8a774a1_beacon_defconfig
> b/configs/r8a774a1_beacon_defconfig
> index 58d3f9f019..ff29a40d15 100644
> --- a/configs/r8a774a1_beacon_defconfig
> +++ b/configs/r8a774a1_beacon_defconfig
> @@ -17,7 +17,9 @@ CONFIG_CMD_BOOTZ=y
> CONFIG_CMD_GPIO=y
> CONFIG_CMD_I2C=y
> CONFIG_CMD_MMC=y
> +CONFIG_CMD_MTD=y
> CONFIG_CMD_PART=y
> +CONFIG_CMD_SPI=y
> CONFIG_CMD_USB=y
> CONFIG_CMD_DHCP=y
> CONFIG_CMD_MII=y
> @@ -46,6 +48,10 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y
> CONFIG_MMC_HS200_SUPPORT=y CONFIG_RENESAS_SDHI=y
> +CONFIG_MTD=y
> +CONFIG_DM_MTD=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH_WINBOND=y
> CONFIG_BITBANGMII=y
> CONFIG_PHY_REALTEK=y
> CONFIG_DM_ETH=y
> @@ -55,6 +61,9 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y
> CONFIG_S
Re: [PATCHv2] drivers: tpm2: update reset gpio semantics
On 6/1/21 8:09 AM, Jorge Ramirez-Ortiz wrote:
> Use the more generic reset-gpios propery name.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> ---
> v2: kept gpio-reset as legacy
>
> .../tpm2/tis-tpm2-spi.txt | 2 +-
> drivers/tpm/tpm2_tis_spi.c| 21 ---
> 2 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> index 3a2ee4bd17..bbcd12950f 100644
> --- a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> +++ b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> @@ -6,7 +6,7 @@ Required properties:
> - reg: SPI Chip select
>
> Optional properties:
> -- gpio-reset : Reset GPIO (if not connected to the SoC reset line)
As I said you shouldn't remove this. Just extend description that it is
deprecated and reset-gpios should be used instead.
> +- reset-gpios: Reset GPIO (if not connected to the SoC reset
> line)
> - spi-max-frequency : See spi-bus.txt
>
> Example:
> diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
> index 4b33ac8fd3..1f9f89f68f 100644
> --- a/drivers/tpm/tpm2_tis_spi.c
> +++ b/drivers/tpm/tpm2_tis_spi.c
> @@ -589,18 +589,23 @@ static int tpm_tis_spi_probe(struct udevice *dev)
> if (CONFIG_IS_ENABLED(DM_GPIO)) {
> struct gpio_desc reset_gpio;
>
> - ret = gpio_request_by_name(dev, "gpio-reset", 0,
> + ret = gpio_request_by_name(dev, "reset-gpios", 0,
> &reset_gpio, GPIOD_IS_OUT);
> if (ret) {
> - log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n",
> - __func__);
> - } else {
> - dm_gpio_set_value(&reset_gpio, 1);
> - mdelay(1);
> - dm_gpio_set_value(&reset_gpio, 0);
> + /* legacy reset */
> + ret = gpio_request_by_name(dev, "gpio-reset", 0,
> +&reset_gpio, GPIOD_IS_OUT);
> + if (ret) {
> + log(LOGC_NONE, LOGL_NOTICE,
> + "%s: missing reset GPIO\n", __func__);
> + goto init;
> + }
And here it is clear that gpio-reset is used which should deprecated
that's why you should print message about it here.
> }
> + dm_gpio_set_value(&reset_gpio, 1);
> + mdelay(1);
> + dm_gpio_set_value(&reset_gpio, 0);
> }
What about this to remove that goto?
ret = gpio_request_by_name(dev, "reset-gpios", 0,
&reset_gpio, GPIOD_IS_OUT);
if (ret) {
/* trying legacy reset */
ret = gpio_request_by_name(dev, "gpio-reset", 0,
&reset_gpio, GPIOD_IS_OUT);
if (!ret)
log(LOGC_NONE, LOGL_NOTICE,
"%s: Using deprecated gpio-reset switch to reset-gpios\n",
__func__);
}
if (!ret) {
dm_gpio_set_value(&reset_gpio, 1);
mdelay(1);
dm_gpio_set_value(&reset_gpio, 0);
}
> -
> +init:
> /* Ensure a minimum amount of time elapsed since reset of the TPM */
> mdelay(drv_data->time_before_first_cmd_ms);
>
>
M
[PATCHv2] drivers: tpm2: update reset gpio semantics
Use the more generic reset-gpios propery name.
Signed-off-by: Jorge Ramirez-Ortiz
---
v2: kept gpio-reset as legacy
.../tpm2/tis-tpm2-spi.txt | 2 +-
drivers/tpm/tpm2_tis_spi.c| 21 ---
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
index 3a2ee4bd17..bbcd12950f 100644
--- a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
+++ b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
@@ -6,7 +6,7 @@ Required properties:
- reg : SPI Chip select
Optional properties:
-- gpio-reset : Reset GPIO (if not connected to the SoC reset line)
+- reset-gpios : Reset GPIO (if not connected to the SoC reset line)
- spi-max-frequency: See spi-bus.txt
Example:
diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
index 4b33ac8fd3..1f9f89f68f 100644
--- a/drivers/tpm/tpm2_tis_spi.c
+++ b/drivers/tpm/tpm2_tis_spi.c
@@ -589,18 +589,23 @@ static int tpm_tis_spi_probe(struct udevice *dev)
if (CONFIG_IS_ENABLED(DM_GPIO)) {
struct gpio_desc reset_gpio;
- ret = gpio_request_by_name(dev, "gpio-reset", 0,
+ ret = gpio_request_by_name(dev, "reset-gpios", 0,
&reset_gpio, GPIOD_IS_OUT);
if (ret) {
- log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n",
- __func__);
- } else {
- dm_gpio_set_value(&reset_gpio, 1);
- mdelay(1);
- dm_gpio_set_value(&reset_gpio, 0);
+ /* legacy reset */
+ ret = gpio_request_by_name(dev, "gpio-reset", 0,
+ &reset_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log(LOGC_NONE, LOGL_NOTICE,
+ "%s: missing reset GPIO\n", __func__);
+ goto init;
+ }
}
+ dm_gpio_set_value(&reset_gpio, 1);
+ mdelay(1);
+ dm_gpio_set_value(&reset_gpio, 0);
}
-
+init:
/* Ensure a minimum amount of time elapsed since reset of the TPM */
mdelay(drv_data->time_before_first_cmd_ms);
--
2.31.1
[PATCH] cmd:Elaborate ‘blkcache’ cmd HELP statement
From: Adarsh Babu Kalepalli "HELP description is provided for ‘configure’ sub-command of ‘blkcache’. Signed-off-by: Adarsh Babu Kalepalli --- cmd/blkcache.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/blkcache.c b/cmd/blkcache.c index 25f252e455..89ae52150a 100644 --- a/cmd/blkcache.c +++ b/cmd/blkcache.c @@ -84,4 +84,5 @@ U_BOOT_CMD( "block cache diagnostics and control", "show - show and reset statistics\n" "blkcache configure blocks entries\n" + " - configure 'max blocks/entry' to 'blocks' and 'max cache entries' to 'entries'\n" ); -- 2.17.1
[BUG] network is broken on Orange Pi PC
Dear all, network is broken in U-Boot on orangepi_pc_defconfig: U-Boot 2021.07-rc3-00059-gd8729a114e (May 31 2021 - 21:26:56 +) Allwinner Technology eth0: ethernet@1c3 => dhcp sun8i_emac_eth_start: Timeout Best regards Heinrich
[PATCH] board: sama5d3_xplained: add Falcon boot support
This supports Falcon boot support for Microchip SAMA5D3 Xplained,
tested on raw MMC, and on raw NAND.
spl_start_uboot() is has the simplest possible implementation.
It doesn't test the environment because enabling environment support
currently causes the SPL to exceed its maximum size (64 KiB).
It doesn't check the serial for incoming characters either because
this functionality currently doesn't seem to work from the SPL
on this board.
Settings for Falcon boot from at FAT partition are also added to
avoid compile failures when CONFIG_SPL_OS_BOOT is enabled, but this
particular case is currently not functional as adding FAT and
partition support cause the SPL to be too big again.
Signed-off-by: Michael Opdenacker
---
board/atmel/sama5d3_xplained/sama5d3_xplained.c | 7 +++
include/configs/sama5d3_xplained.h | 14 ++
2 files changed, 21 insertions(+)
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index db9603f584..c25bf42e0a 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -132,6 +132,13 @@ void spl_board_init(void)
#endif
}
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ return 0;
+}
+#endif
+
static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
diff --git a/include/configs/sama5d3_xplained.h
b/include/configs/sama5d3_xplained.h
index 1113214bcf..4c25964b43 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -79,4 +79,18 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x2
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+/* Falcon boot support on raw MMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE /
512)
+/* U-Boot proper stored by default at 0x200 (256 KiB) */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR0x1000 /* 2MB */
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x2200
+
+/* Falcon boot support on FAT on MMC */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+
+/* Falcon boot support on raw NAND */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS0x1a
+
#endif
--
2.25.1
Re: U-Boot "lib: Add support for ECDSA image signing" commit breaks socfpga_*_atf_defconfig compilation
On 4/24/21 2:43 AM, Lim, Elly Siew Chin wrote: Add this discussion to denx mailing list. [snip] I can think of two enhancement to fix this: (1) Add separate CONFIG to gate ECDSA algorithm. This enhancement benefits all use cases. I assume not all user need ECDSA algorithm when FIT_SIGNATURE is used. (2) Enhance spl/spl_fit.c to support verification of data integrity based on hash(es) in FIT image instead of based on FIT_SIGNATURE. What do you think? If you agree: For (1), can we ask Alex's help to change it? For (2), who will be the right person to change this kind of common code? FYI, I proposed a change to decouple OpenSSL from FIT_SIGNATURE [1] [1] https://patchwork.ozlabs.org/project/uboot/patch/20210524202317.1492578-1-mr.nuke...@gmail.com/ That would enable you to have FIT_SIGNATURE, but not need OpenSSL support in mkimage. Alex
Re: [PULL] u-boot-riscv/master
On Mon, May 31, 2021 at 06:16:19PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit ffd810487ec2ff6095edf3f3d058d7ed6eb85ff3: > > Merge tag 'u-boot-stm32-20210528' of > https://source.denx.de/u-boot/custodians/u-boot-stm (2021-05-28 14:11:06 > -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to d7da718bd94943309a7f25f14e694226a45b2aef: > > drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-31 > 16:35:55 +0800) > > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/ > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Pull request: u-boot-sunxi/master for v2021.07
On Mon, May 31, 2021 at 01:23:45AM +0100, Andre Przywara wrote: > Hi Tom, > > please pull the master branch from u-boot-sunxi, containing the fix > to bring back the SD card as MMC0. In the long run we are looking into a > more robust solution, but for now we need to fix this, as this breaks > the user experience left, right, and centre. > Also add the one MAINTAINERS path addition from Samuel. > > Thanks, > Andre > > == > The following changes since commit ffd810487ec2ff6095edf3f3d058d7ed6eb85ff3: > > Merge tag 'u-boot-stm32-20210528' of > https://source.denx.de/u-boot/custodians/u-boot-stm (2021-05-28 14:11:06 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-sunxi.git master > > for you to fetch changes up to f264e796c06d7ce6c039bfc7255390309cbc5191: > > MAINTAINERS: Add allwinner/sunxi driver directories (2021-05-31 00:39:54 > +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH v4 4/5] stm32mp1: spl: Configure TrustZone controller for OP-TEE
OP-TEE is very particular about how the TZC should be configured.
When booting an OP-TEE payload, an incorrect TZC configuration will
result in a panic.
Most information can be derived from the SPL devicetree. The only
information we don't have is the split between TZDRAM and shared
memory. This has to be hardcoded. The rest of the configuration is
fairly easy, and only requires 3 TZC regions. Configure them.
Signed-off-by: Alexandru Gagniuc
---
arch/arm/mach-stm32mp/spl.c | 92 +
1 file changed, 92 insertions(+)
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index b53659a698a..405eff68a3b 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -11,11 +11,13 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
+#include
#include
u32 spl_boot_device(void)
@@ -92,6 +94,96 @@ __weak int board_early_init_f(void)
return 0;
}
+uint32_t stm32mp_get_dram_size(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ if (uclass_get_device(UCLASS_RAM, 0, &dev))
+ return 0;
+
+ ret = ram_get_info(dev, &ram);
+ if (ret)
+ return 0;
+
+ return ram.size;
+}
+
+static int optee_get_reserved_memory(uint32_t *start, uint32_t *size)
+{
+ phys_size_t fdt_mem_size;
+ fdt_addr_t fdt_start;
+ ofnode node;
+
+ node = ofnode_path("/reserved-memory/optee");
+ if (!ofnode_valid(node))
+ return 0;
+
+ fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
+ *start = fdt_start;
+ *size = fdt_mem_size;
+ return (fdt_start < 0) ? fdt_start : 0;
+}
+
+#define CFG_SHMEM_SIZE 0x20
+#define STM32_TZC_NSID_ALL 0x
+#define STM32_TZC_FILTER_ALL 3
+
+void stm32_init_tzc_for_optee(void)
+{
+ const uint32_t dram_size = stm32mp_get_dram_size();
+ const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1);
+ uint32_t optee_base, optee_size, tee_shmem_base;
+ const uintptr_t tzc = STM32_TZC_BASE;
+ int ret;
+
+ if (dram_size == 0)
+ panic("Cannot determine DRAM size from devicetree\n");
+
+ ret = optee_get_reserved_memory(&optee_base, &optee_size);
+ if (ret < 0 || optee_size <= CFG_SHMEM_SIZE)
+ panic("Invalid OPTEE reserved memory in devicetree\n");
+
+ tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE;
+
+ const struct tzc_region optee_config[] = {
+ {
+ .base = STM32_DDR_BASE,
+ .top = optee_base - 1,
+ .sec_mode = TZC_ATTR_SEC_NONE,
+ .nsec_id = STM32_TZC_NSID_ALL,
+ .filters_mask = STM32_TZC_FILTER_ALL,
+ }, {
+ .base = optee_base,
+ .top = tee_shmem_base - 1,
+ .sec_mode = TZC_ATTR_SEC_RW,
+ .nsec_id = 0,
+ .filters_mask = STM32_TZC_FILTER_ALL,
+ }, {
+ .base = tee_shmem_base,
+ .top = dram_top,
+ .sec_mode = TZC_ATTR_SEC_NONE,
+ .nsec_id = STM32_TZC_NSID_ALL,
+ .filters_mask = STM32_TZC_FILTER_ALL,
+ }, {
+ .top = 0,
+ }
+ };
+
+ flush_dcache_all();
+
+ tzc_configure(tzc, optee_config);
+ tzc_dump_config(tzc);
+
+ dcache_disable();
+}
+
+void spl_board_prepare_for_optee(void *fdt)
+{
+ stm32_init_tzc_for_optee();
+}
+
void board_init_f(ulong dummy)
{
struct udevice *dev;
--
2.31.1
[PATCH v4 3/5] arm: stm32mp: Implement support for TZC 400 controller
The purpose of this change is to allow configuring TrustZone (TZC)
memory permissions. For example, OP-TEE expects TZC regions to be
configured in a very particular way. The API presented here is
intended to allow exactly that.
UCLASS support is not implemented, because it would not be too useful.
Changing TZC permissions needs to be done with care, so as not to cut
off access to memory we are currently using. One place where we can
use this is at the end of SPL, right before jumping to OP-TEE.
Signed-off-by: Alexandru Gagniuc
Reviewed-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Makefile | 1 +
arch/arm/mach-stm32mp/include/mach/tzc.h | 33 ++
arch/arm/mach-stm32mp/tzc400.c | 136 +++
3 files changed, 170 insertions(+)
create mode 100644 arch/arm/mach-stm32mp/include/mach/tzc.h
create mode 100644 arch/arm/mach-stm32mp/tzc400.c
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index aa39867080d..879c1961fef 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -10,6 +10,7 @@ obj-y += bsec.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
+obj-y += tzc400.o
else
obj-y += cmd_stm32prog/
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
diff --git a/arch/arm/mach-stm32mp/include/mach/tzc.h
b/arch/arm/mach-stm32mp/include/mach/tzc.h
new file mode 100644
index 000..16db55c4645
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/tzc.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Simple API for configuring TrustZone memory regions
+ *
+ * The premise is that the desired TZC layout is known beforehand, and it can
+ * be configured in one step. tzc_configure() provides this functionality.
+ */
+#ifndef MACH_TZC_H
+#define MACH_TZC_H
+
+#include
+
+enum tzc_sec_mode {
+ TZC_ATTR_SEC_NONE = 0,
+ TZC_ATTR_SEC_R = 1,
+ TZC_ATTR_SEC_W = 2,
+ TZC_ATTR_SEC_RW = 3
+};
+
+struct tzc_region {
+ uintptr_t base;
+ uintptr_t top;
+ enum tzc_sec_mode sec_mode;
+ uint16_t nsec_id;
+ uint16_t filters_mask;
+};
+
+int tzc_configure(uintptr_t tzc, const struct tzc_region *cfg);
+int tzc_disable_filters(uintptr_t tzc, uint16_t filters_mask);
+int tzc_enable_filters(uintptr_t tzc, uint16_t filters_mask);
+void tzc_dump_config(uintptr_t tzc);
+
+#endif /* MACH_TZC_H */
diff --git a/arch/arm/mach-stm32mp/tzc400.c b/arch/arm/mach-stm32mp/tzc400.c
new file mode 100644
index 000..cdc4a40edaf
--- /dev/null
+++ b/arch/arm/mach-stm32mp/tzc400.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Simple API for configuring TrustZone memory restrictions for TZC400
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include
+#include
+
+#define TZC_TIMEOUT_US 100
+
+#define TZC_BUILD_CONFIG 0x00
+#define TZC_ACTION 0x04
+#define TZC_ACTION_NONE0
+#define TZC_ACTION_ERR 1
+#define TZC_ACTION_INT 2
+#define TZC_ACTION_INT_ERR 3
+#define TZC_GATE_KEEPER0x08
+
+#define TZC_REGION0_OFFSET 0x100
+#define TZC_REGION_CFG_SIZE0x20
+#define TZC_REGION1_OFFSET 0x120
+#define TZC_REGION_BASE0x00
+#define TZC_REGION_TOP 0x08
+#define TZC_REGION_ATTRIBUTE 0x10
+#define TZC_REGION_ACCESS 0x14
+
+static uint32_t tzc_read(uintptr_t tzc, size_t reg)
+{
+ return readl(tzc + reg);
+}
+
+static void tzc_write(uintptr_t tzc, size_t reg, uint32_t val)
+{
+ writel(val, tzc + reg);
+}
+
+static uint16_t tzc_config_get_active_filters(const struct tzc_region *cfg)
+{
+ uint16_t active_filters = 0;
+
+ for ( ; cfg->top != 0; cfg++)
+ active_filters |= cfg->filters_mask;
+
+ return active_filters;
+}
+
+int tzc_configure(uintptr_t tzc, const struct tzc_region *cfg)
+{
+ uintptr_t region = tzc + TZC_REGION1_OFFSET;
+ uint32_t nsid, attr_reg, active_filters;
+ int ret;
+
+ active_filters = tzc_config_get_active_filters(cfg);
+ if (active_filters == 0)
+ return -EINVAL;
+
+ ret = tzc_disable_filters(tzc, active_filters);
+ if (ret < 0)
+ return ret;
+
+ for ( ; cfg->top != 0; cfg++, region += TZC_REGION_CFG_SIZE) {
+ attr_reg = (cfg->sec_mode & 0x03) << 30;
+ attr_reg |= (cfg->filters_mask & 0x03) << 0;
+ nsid = cfg->nsec_id & 0x;
+ nsid |= nsid << 16;
+
+ tzc_write(region, TZC_REGION_BASE, cfg->base);
+ tzc_write(region, TZC_REGION_TOP, cfg->top);
+ tzc_write(region, TZC_REGION_ACCESS, nsid);
+ tzc_write(region, TZC_REGION_ATTRIBUTE, attr_reg);
+ }
+
+ tzc_write(tzc, TZC_ACTION, TZC_ACTION_ERR);
+ return tzc_enable_filters(tzc, active_filters);
+}
+
+int tzc_disable_filters(uintptr_t tzc, uint16_t filters_mask)
+{
+ uint32_t gate = tzc_read(tzc, TZC_GATE_KEEPER);
+ uint32_t filter_status = fi
[PATCH v4 5/5] ARM: dts: stm32mp: Add OP-TEE reserved memory to SPL dtb
Add the "/reserved-memory/optee" node to the SPL devicetree. The
purpose is to allow configuring TZC regions when booting OP-TEE.
Signed-off-by: Alexandru Gagniuc
Reviewed-by: Simon Glass
---
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 67876192900..55d634f7db2 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -30,9 +30,12 @@
};
reserved-memory {
+ u-boot,dm-spl;
+
optee@de00 {
reg = <0xde00 0x0200>;
no-map;
+ u-boot,dm-spl;
};
};
--
2.31.1
[PATCH v4 2/5] spl: Introduce spl_board_prepare_for_optee() hook
OP-TEE requires some particular setup, which is not needed for linux
or other payloads. Add a hook for platform-specific code to perform
any OP-TEE related configuration and initialization.
A weak function is used because it is symmetrical to other
spl_board_prepare_for_*() implementations. A solution to avoid the use
of weak functions would trivially apply to all these implementations.
However, re-designing this is beyond the scope of this patch.
Signed-off-by: Alexandru Gagniuc
Reviewed-by: Tom Rini
Reviewed-by: Simon Glass
Reviewed-by: Patrick Delaunay
---
common/spl/spl.c | 5 +
include/spl.h| 14 ++
2 files changed, 19 insertions(+)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index a0a608fd772..56f6d47b164 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -165,6 +165,10 @@ __weak void spl_board_prepare_for_linux(void)
/* Nothing to do! */
}
+__weak void spl_board_prepare_for_optee(void *fdt)
+{
+}
+
__weak void spl_board_prepare_for_boot(void)
{
/* Nothing to do! */
@@ -745,6 +749,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
#if CONFIG_IS_ENABLED(OPTEE)
case IH_OS_TEE:
debug("Jumping to U-Boot via OP-TEE\n");
+ spl_board_prepare_for_optee(spl_image.fdt_addr);
spl_optee_entry(NULL, NULL, spl_image.fdt_addr,
(void *)spl_image.entry_point);
break;
diff --git a/include/spl.h b/include/spl.h
index cee9a42ddb5..04ab2b6d7d8 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -388,6 +388,20 @@ int spl_parse_image_header(struct spl_image_info
*spl_image,
const struct image_header *header);
void spl_board_prepare_for_linux(void);
+
+/**
+ * spl_board_prepare_for_optee() - Prepare board for an OPTEE payload
+ *
+ * Prepares the board for booting an OP-TEE payload. Initialization is platform
+ * specific, and may include configuring the TrustZone memory, and other
+ * initialization steps required by OP-TEE.
+ * Note that @fdt is not used directly by OP-TEE. OP-TEE passes this @fdt to
+ * its normal world target. This target is not guaranteed to be u-boot, so @fdt
+ * changes that would normally be done by u-boot should be done in this step.
+ *
+ * @fdt: Devicetree that will be passed on, or NULL
+ */
+void spl_board_prepare_for_optee(void *fdt);
void spl_board_prepare_for_boot(void);
int spl_board_ubi_load_image(u32 boot_device);
int spl_board_boot_device(u32 boot_device);
--
2.31.1
[PATCH v4 1/5] spl: mmc: Support OP-TEE payloads in Falcon mode
In general, Falcon mode means we're booting a linux kernel directly.
With FIT images, however, an OP-TEE secure kernel can be booted before
linux. Thus, if the next stage is an IH_OS_TEE, this isn't necessarily
a problem.
Of course, a general solution would involve mmc_load_image_raw_os()
only loading the binary, and leaving the decision of suitability to
someone else. However, a rework of the boot flow is beyond the scope
of this patch. Accept IH_OS_TEE as a valid OS value.
Signed-off-by: Alexandru Gagniuc
Reviewed-by: Tom Rini
Reviewed-by: Patrick Delaunay
---
common/spl/spl_mmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index add2785b4e3..bab558d055f 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -230,8 +230,10 @@ static int mmc_load_image_raw_os(struct spl_image_info
*spl_image,
if (ret)
return ret;
- if (spl_image->os != IH_OS_LINUX) {
- puts("Expected Linux image is not found. Trying to start
U-boot\n");
+ if (spl_image->os != IH_OS_LINUX && spl_image->os != IH_OS_TEE) {
+ puts("Expected OS image is not found. Instead found ");
+ puts(genimg_get_os_name(spl_image->os));
+ puts(". Trying to start U-boot\n");
return -ENOENT;
}
--
2.31.1
[PATCH v4 0/5] stm32mp: Enable OP-TEE and TZC support in SPL
The purpose of this series is to allow booting an OP-TEE image from
SPL, by corectly configuring the TrustZone (TZC) memory regions.
Although TZC400 is a generic silicon logic that could apply to other
mach- families, support is currently restricted to stm32mp. I have
neither a feasible way nor interest in validating this for other
chips. It's fairly trivial to move the code from mach- to arch/,
should another use case arise.
The configuration of the memory regions is devicetree-driven, so there
isn't much to hardcode, However the delineation between OP-TEE secure
memory and shared memory is not given in the devicetree. This is the
one thing that has to be hardcoded.
Changes since v3:
- Pass a "phys_size_t *" to ofnode_get_addr_size() to resolve warning
- s/u-boot,dm-pre-reloc/u-boot,dm-spl/ in devicetree for clarity
Changes since v2:
- Use ram_get_info() instead of ofnode_read("st,mem-size")
- Only hardcode shared memory size instead of TZDRAM size
- Use log_info() instead of pr_info()
Changes since v1:
- Removed "Weak functions are stupid" comment
- Addressed blank line complaints from checkpatch
Alexandru Gagniuc (5):
spl: mmc: Support OP-TEE payloads in Falcon mode
spl: Introduce spl_board_prepare_for_optee() hook
arm: stm32mp: Implement support for TZC 400 controller
stm32mp1: spl: Configure TrustZone controller for OP-TEE
ARM: dts: stm32mp: Add OP-TEE reserved memory to SPL dtb
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 3 +
arch/arm/mach-stm32mp/Makefile | 1 +
arch/arm/mach-stm32mp/include/mach/tzc.h | 33 ++
arch/arm/mach-stm32mp/spl.c | 92 +++
arch/arm/mach-stm32mp/tzc400.c | 136 +++
common/spl/spl.c | 5 +
common/spl/spl_mmc.c | 6 +-
include/spl.h| 14 +++
8 files changed, 288 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-stm32mp/include/mach/tzc.h
create mode 100644 arch/arm/mach-stm32mp/tzc400.c
--
2.31.1
Re: [PATCH v3 4/5] stm32mp1: spl: Configure TrustZone controller for OP-TEE
On 5/28/21 5:22 AM, Patrick DELAUNAY wrote: Hi, On 4/15/21 6:48 PM, Alexandru Gagniuc wrote: [snip] + fdt_start = ofnode_get_addr_size(node, "reg", size); warning here because size is 'fdt_size_t *' not 'u32*' arch/arm/mach-stm32mp/spl.c:122:48: warning: passing argument 3 of ‘ofnode_get_addr_size’ from inc Fixed in v4 + + tzc_configure(tzc, optee_config); + tzc_dump_config(tzc); Dump is always require, even for nomal boot, or only for debug cases ? Because tzc_dump_config() uses log_info(), only prints when the appropriate log level is enabled. This is by design, so that we don't need extra logic here to invoke dump(). + + dcache_disable(); You disable cache why, it is not supported by OP-TEE ? => if it is a generic issue it should be in spl.c for case IH_OS_TEE or in spl_optee_entry() and not in board specific weak function as it done in bl31_entry for TF-A I don't know if this can be safely generalized. stm32mp is the only platform to enable TZC in SPL, which brings special constraints: We're running in secure mode, and we've touched memory that will be reserved to the normal world, for example the linux devicetree. Once we enable TZC, we can't touch that memory anymore. This could happen later as the CPU is evicting cache lines. To make sure we don't hit a TZC violation as cache lines are evicted, we both flush the dcache, and disable the dcache. Doing this another way is not tested, and I can't guarantee that other variations will work reliably. Alex
Re: [PATCH v3 3/5] arm: stm32mp: Implement support for TZC 400 controller
Hi Patrick, On 5/28/21 4:59 AM, Patrick DELAUNAY wrote: Hi, Any reason to prefer uint16_t and uint32_t ? I use standard C types. u32, _u32, and __u32 are non-standard, and they have different meanings depending on how they're used. I avoid them for this reason. Alex See checkpatch warning arch/arm/mach-stm32mp/include/mach/tzc.h:24: check: Prefer kernel type 'u16' over 'uint16_t' arch/arm/mach-stm32mp/include/mach/tzc.h:25: check: Prefer kernel type 'u16' over 'uint16_t' arch/arm/mach-stm32mp/tzc400.c:41: check: Prefer kernel type 'u16' over 'uint16_t' arch/arm/mach-stm32mp/tzc400.c:52: check: Prefer kernel type 'u32' over 'uint32_t' arch/arm/mach-stm32mp/tzc400.c:81: check: Prefer kernel type 'u32' over 'uint32_t' arch/arm/mach-stm32mp/tzc400.c:82: check: Prefer kernel type 'u32' over 'uint32_t' arch/arm/mach-stm32mp/tzc400.c:93: check: Prefer kernel type 'u32' over 'uint32_t' arch/arm/mach-stm32mp/tzc400.c:94: check: Prefer kernel type 'u32' over 'uint32_t' arch/arm/mach-stm32mp/tzc400.c:113: check: Prefer kernel type 'u32' over 'uint32_t' But except these remarks: Reviewed-by: Patrick Delaunay Thanks Patrick
Re: [PATCH] rk3399: Add basic support for helios64【请注意，邮件由cglom...@redhat.com代发】
Any news on this? Uwe, Christian?
Am Tue, Mar 30, 2021 at 03:21:32PM +0800 schrieb Kever Yang:
> Hi
>
> Could you send new patch set if everything is ready.
>
>
> Thanks,
>
> - Kever
>
> On 2021/3/9 上午12:29, Christian Glombek wrote:
> > I've looked into this a bit over the weekend - my current WIP patch can
> > be found here:
> > https://src.fedoraproject.org/fork/lorbus/rpms/uboot-tools/blob/helios64/f/0001-arm-Add-support-for-Kobol-Helios64-board.patch
> >
> > It's essentially the entire devicetree used in Armbian, only that I had
> > to remove the gpio{1,2,4} initialization since `gpio-hog` doesn't appear
> > to work with upstream u-boot.
> > It boots fine with current Fedora IoT 34 nightlies, but kernel crashes
> > are very regular (sometimes recoverable, sometimes not), which looks to
> > me like the same problem that Armbian builds have, logs seem to point to
> > an issue with the dmc frequency.
> > I've compiled an excerpt of interesting looking logs from a couple of
> > boots here (you should be able to comment on the doc as well):
> > https://hackmd.io/@lorbus/SyXTj0lXu
> >
> > Please take a look and let me know what you think.
> >
> > Best regards,
> > Christian
>
>
[PATCH] net: e1000: Fix Unchecked return value coverity
From: Hou Zhiqiang
Added check for return value of e1000_read_phy_reg().
Signed-off-by: Hou Zhiqiang
---
drivers/net/e1000.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 694114eca7..1f0d559415 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -4738,12 +4738,16 @@ e1000_phy_init_script(struct e1000_hw *hw)
uint16_t fused, fine, coarse;
/* Move to analog registers page */
- e1000_read_phy_reg(hw,
- IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
+ if (e1000_read_phy_reg(hw,
+
IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
+ &fused))
+ return;
if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
- e1000_read_phy_reg(hw,
- IGP01E1000_ANALOG_FUSE_STATUS, &fused);
+ if (e1000_read_phy_reg(hw,
+
IGP01E1000_ANALOG_FUSE_STATUS,
+ &fused))
+ return;
fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
coarse = fused
--
2.17.1
Re: [[PATCH] colibri_imx6: add board_fit_config_name_match to support FIT in SPL
On 5/31/21 3:06 AM, liu.min...@gmail.com wrote:
From: Ming Liu
Only one dtb is currently supported, so match with imx6-colibri.
Signed-off-by: Ming Liu
---
board/toradex/colibri_imx6/colibri_imx6.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c
b/board/toradex/colibri_imx6/colibri_imx6.c
index c0e7754469..587d92a8e9 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -1081,6 +1081,16 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "imx6-colibri"))
+ return 0;
+
+ return -1;
Please use an errno.
+}
+#endif
+
void reset_cpu(void)
{
}
Do you need to match "imx6-colibri", or could you use the default config?
--Sean
[PATCH v7] imx: support for conga-QMX8 board
Add i.MX8QM qmx8 congatec board support
U-Boot 2021.07-rc3-00528-gc9a966d9dd (May 31 2021 - 15:21:25 +0200)
CPU: NXP i.MX8QM RevB A53 at 1200 MHz
Model: Congatec QMX8 Qseven series
Board: conga-QMX8
Build: SCFW 494c97f3, SECO-FW d63fdb21, ATF 09c5cc9
Boot: SD2
DRAM: 6 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:serial@5a06
Out: serial@5a06
Err: serial@5a06
switch to partitions #0, OK
mmc2 is current device
Net:
Error: ethernet@5b04 address not set.
No ethernet found.
Hit any key to stop autoboot: 0
Signed-off-by: Oliver Graute
Cc: Stefano Babic
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Simon Glass
Cc: Ye Li
Cc: uboot-imx
---
These changes are based on this vendor tree:
git.congatec.com/imx8_early_access/imx8_uboot_internal.git
Changes for v7:
- removed superflous include in board/congatec/common/mmc.c
- added congatec to doc/board/index.rst
Changes for v6:
- fixed build warnings because of missing prototypes
Changes for v5:
- fixed checkpatch errors
- fixed some checkpatch warnings
Changes for v4:
- fixed missing DTS file in MAINTAINERS
- replaced bd_t with struct bd_info
- replaced README with imx8qm-dmsse20-a1.rst
- move CMD_FUSE to Kconfig
- replaced power_domain_lookup_name with imx8_power_domain_lookup_name
Changes for v3:
- include log.h
- include delay.h
- improved README
- set phy register to six
- Remove 'fdt_high' and 'initrd_high' environment variables
- set CONFIG_SYS_BOOTMAPSZ to 256MB
- increased CONFIG_SYS_FSL_USDHC_NUM to 3
Changes for v2:
- added USDHC3_BASE_ADDR
- replaced CONFIG_FSL_ESDHC with CONFIG_FSL_ESDHC_IMX
- set CONFIG_FEC_MXC_PHYADDR to -1
- moved CONFIG_ENV_SIZE and CONFIG_ENV_OFFSET to defconfig
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx8qm-cgtqmx8.dts | 404
arch/arm/mach-imx/imx8/Kconfig | 7 +
board/congatec/cgtqmx8/Kconfig | 14 +
board/congatec/cgtqmx8/MAINTAINERS | 7 +
board/congatec/cgtqmx8/Makefile | 11 +
board/congatec/cgtqmx8/cgtqmx8.c| 460
board/congatec/cgtqmx8/imximage.cfg | 21 ++
board/congatec/cgtqmx8/spl.c| 77 +
board/congatec/common/Kconfig | 48 +++
board/congatec/common/Makefile | 23 ++
board/congatec/common/mmc.c | 49 +++
configs/cgtqmx8_defconfig | 86 ++
doc/board/congatec/cgtqmx8.rst | 70 +
doc/board/congatec/index.rst| 9 +
doc/board/index.rst | 1 +
include/configs/cgtqmx8.h | 181 +++
17 files changed, 1469 insertions(+)
create mode 100644 arch/arm/dts/imx8qm-cgtqmx8.dts
create mode 100644 board/congatec/cgtqmx8/Kconfig
create mode 100644 board/congatec/cgtqmx8/MAINTAINERS
create mode 100644 board/congatec/cgtqmx8/Makefile
create mode 100644 board/congatec/cgtqmx8/cgtqmx8.c
create mode 100644 board/congatec/cgtqmx8/imximage.cfg
create mode 100644 board/congatec/cgtqmx8/spl.c
create mode 100644 board/congatec/common/Kconfig
create mode 100644 board/congatec/common/Makefile
create mode 100644 board/congatec/common/mmc.c
create mode 100644 configs/cgtqmx8_defconfig
create mode 100644 doc/board/congatec/cgtqmx8.rst
create mode 100644 doc/board/congatec/index.rst
create mode 100644 include/configs/cgtqmx8.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 096068261d..b95960c704 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -836,6 +836,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
fsl-imx8qm-mek.dtb \
+ imx8qm-cgtqmx8.dtb \
imx8qm-rom7720-a1.dtb \
fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \
diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts
new file mode 100644
index 00..555c357f6f
--- /dev/null
+++ b/arch/arm/dts/imx8qm-cgtqmx8.dts
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Copyright 2017 congatec AG
+ * Copyright (C) 2019 Oliver Graute
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x8000 0x0002;
+
+#include "fsl-imx8qm.dtsi"
+
+/ {
+ model = "Congatec QMX8 Qseven series";
+ compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200
earlycon=lpuart32,0x5a06,115200";
+ stdout-path = &lpuart0;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sw-3p3-sd1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+
Re: [PATCH v6] imx: support for conga-QMX8 board
On 02/03/21, Fabio Estevam wrote: > Hi Stefano, > > On Tue, Mar 2, 2021 at 5:30 PM Stefano Babic wrote: > > > I get now an error with CI for htmldocs: > > > > /builds/u-boot/custodians/u-boot-imx/doc/board/congatec/index.rst:document > > isn't included in any toctree > > Does this fix it? > > --- a/doc/board/index.rst > +++ b/doc/board/index.rst > @@ -11,6 +11,7 @@ Board-specific doc > AndesTech/index > amlogic/index > atmel/index > + congatec/index > coreboot/index > emulation/index > freescale/index thx for this hint. I included it for next patch revision. Best regards, Oliver
Re: [PATCH v6] imx: support for conga-QMX8 board
On 08/04/21, Stefano Babic wrote: > Hi Oliver, > > I was quite convinced this was the right one and I could merge it. Most > builds were okl, until...x86 is built ! > > In fact, there are congatec boards based on intel, they are using the common > path (../common), and due to your changes some i.MX specific include file is > searched. And then, of course, it fails. > > Here is what I get if I just run "make > conga-qeval20-qa3-e3845_defconfig;make" > > CC board/congatec/common/mmc.o > board/congatec/common/mmc.c:8:10: fatal error: asm/arch/sys_proto.h: No such > file or directory > 8 | #include > | ^~ > > So I have to drop again the patch from u-boot-imx. Could you take a look > please ? Thanks ! ok, the include statement was superflous so I removed it. > Here is what I get if I just run "make > conga-qeval20-qa3-e3845_defconfig;make" now the above board is compiling again. Best regards, Oliver
Re: [[PATCH] colibri_imx6: add board_fit_config_name_match to support FIT in SPL
Hi Ming
On Mon, 2021-05-31 at 09:06 +0200, liu.min...@gmail.com wrote:
> From: Ming Liu
>
> Only one dtb is currently supported, so match with imx6-colibri.
Looks similar to commit 6f8ef051c5dd ("apalis_imx6: add
board_fit_config_name_match to support FIT in SPL") to
me.
I guess as we are currently not using that CONFIG_SPL_LOAD_FIT in our default
configuration(s) at all it won't
actually do anything. However, usually, it may be smarter to do so together
with also enabling it in the
default configuration as otherwise it will neither be compiled in nor really
tested at all. And could therefore
just as well not be done in the first place. But of course, then it would also
definitely be a "real" change
that bears risks...
Anyway, might be interesting to learn the real reason for doing it and if that
is deemed real useful to also
enable it by default. Thanks!
BTW: Do you always send your patches twice? I don't think that is required.
Cheers
Marcel
> Signed-off-by: Ming Liu
> ---
> board/toradex/colibri_imx6/colibri_imx6.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/board/toradex/colibri_imx6/colibri_imx6.c
> b/board/toradex/colibri_imx6/colibri_imx6.c
> index c0e7754469..587d92a8e9 100644
> --- a/board/toradex/colibri_imx6/colibri_imx6.c
> +++ b/board/toradex/colibri_imx6/colibri_imx6.c
> @@ -1081,6 +1081,16 @@ void board_init_f(ulong dummy)
> board_init_r(NULL, 0);
> }
>
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> + if (!strcmp(name, "imx6-colibri"))
> + return 0;
> +
> + return -1;
> +}
> +#endif
> +
> void reset_cpu(void)
> {
> }
Re: [PATCH] drivers: tpm2: update reset gpio semantics
On 5/31/21 3:17 PM, Jorge Ramirez-Ortiz, Foundries wrote:
> On 31/05/21, Michal Simek wrote:
>>
>>
>> On 5/28/21 6:18 PM, Bruno Thomsen wrote:
>>> Den tor. 27. maj 2021 kl. 09.15 skrev Michal Simek
>>> :
On 5/26/21 9:57 PM, Jorge Ramirez-Ortiz wrote:
> Use the more generic reset-gpios propery name.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> ---
> doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt | 2 +-
> drivers/tpm/tpm2_tis_spi.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> index 3a2ee4bd17..bbcd12950f 100644
> --- a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> +++ b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> @@ -6,7 +6,7 @@ Required properties:
> - reg: SPI Chip select
>
> Optional properties:
> -- gpio-reset : Reset GPIO (if not connected to the SoC reset
> line)
> +- reset-gpios: Reset GPIO (if not connected to the SoC
> reset line)
> - spi-max-frequency : See spi-bus.txt
>
> Example:
> diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
> index 4b33ac8fd3..94ac52d9ce 100644
> --- a/drivers/tpm/tpm2_tis_spi.c
> +++ b/drivers/tpm/tpm2_tis_spi.c
> @@ -589,7 +589,7 @@ static int tpm_tis_spi_probe(struct udevice *dev)
> if (CONFIG_IS_ENABLED(DM_GPIO)) {
> struct gpio_desc reset_gpio;
>
> - ret = gpio_request_by_name(dev, "gpio-reset", 0,
> + ret = gpio_request_by_name(dev, "reset-gpios", 0,
> &reset_gpio, GPIOD_IS_OUT);
> if (ret) {
> log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset
> GPIO\n",
>
I think you should deprecate gpio-reset but keep supporting that option
with any warning and add code for reset-gpios.
Also would be good to add it as optional property to Linux kernel to
keep it in sync.
>>>
>>> Hi
>>>
>>> The reason the Linux kernel does not have a TPM reset signal, is
>>> that being able to reset the chip from software is a vulnerability.
>>> There was a discussion on it over on the Barebox mailing list
>>> a while ago.
>>>
>>> TLDR: TPM reset needs to follow SOC reset.
>>
>> I expect chip has the reset in both cases and it is just about who
>> should be calling it. But we should be using the same DT for u-boot and
>> Linux. It means it should be handled properly but described properly.
>
> right, I agree that it should be described properly (that was the
> patch intent).
>
> but do we need to keep the legacy property?
I prefer all the time to have some time for transition. It means add
support for new property. Keep there old one with message that this will
be removed in near future. Not aware if there is any time defined. We
normally keep it there for a year.
Thanks,
Michal
Re: [PATCH] drivers: tpm2: update reset gpio semantics
On 31/05/21, Michal Simek wrote:
>
>
> On 5/28/21 6:18 PM, Bruno Thomsen wrote:
> > Den tor. 27. maj 2021 kl. 09.15 skrev Michal Simek
> > :
> >>
> >>
> >>
> >> On 5/26/21 9:57 PM, Jorge Ramirez-Ortiz wrote:
> >>> Use the more generic reset-gpios propery name.
> >>>
> >>> Signed-off-by: Jorge Ramirez-Ortiz
> >>> ---
> >>> doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt | 2 +-
> >>> drivers/tpm/tpm2_tis_spi.c | 2 +-
> >>> 2 files changed, 2 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> >>> b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> >>> index 3a2ee4bd17..bbcd12950f 100644
> >>> --- a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> >>> +++ b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> >>> @@ -6,7 +6,7 @@ Required properties:
> >>> - reg: SPI Chip select
> >>>
> >>> Optional properties:
> >>> -- gpio-reset : Reset GPIO (if not connected to the SoC reset
> >>> line)
> >>> +- reset-gpios: Reset GPIO (if not connected to the SoC
> >>> reset line)
> >>> - spi-max-frequency : See spi-bus.txt
> >>>
> >>> Example:
> >>> diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
> >>> index 4b33ac8fd3..94ac52d9ce 100644
> >>> --- a/drivers/tpm/tpm2_tis_spi.c
> >>> +++ b/drivers/tpm/tpm2_tis_spi.c
> >>> @@ -589,7 +589,7 @@ static int tpm_tis_spi_probe(struct udevice *dev)
> >>> if (CONFIG_IS_ENABLED(DM_GPIO)) {
> >>> struct gpio_desc reset_gpio;
> >>>
> >>> - ret = gpio_request_by_name(dev, "gpio-reset", 0,
> >>> + ret = gpio_request_by_name(dev, "reset-gpios", 0,
> >>> &reset_gpio, GPIOD_IS_OUT);
> >>> if (ret) {
> >>> log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset
> >>> GPIO\n",
> >>>
> >>
> >> I think you should deprecate gpio-reset but keep supporting that option
> >> with any warning and add code for reset-gpios.
> >>
> >> Also would be good to add it as optional property to Linux kernel to
> >> keep it in sync.
> >
> > Hi
> >
> > The reason the Linux kernel does not have a TPM reset signal, is
> > that being able to reset the chip from software is a vulnerability.
> > There was a discussion on it over on the Barebox mailing list
> > a while ago.
> >
> > TLDR: TPM reset needs to follow SOC reset.
>
> I expect chip has the reset in both cases and it is just about who
> should be calling it. But we should be using the same DT for u-boot and
> Linux. It means it should be handled properly but described properly.
right, I agree that it should be described properly (that was the
patch intent).
but do we need to keep the legacy property?
>
> Thanks,
> Michal
>
>
[PATCH] zynqmp: Remove u-boot,dm-pre-reloc for uart instances
Uarts already have u-boot,dm-pre-reloc via zynqmp.dtsi that's why there is
no need to have them in platform DT files too.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-a2197-revA.dts | 1 -
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 1 -
arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 1 -
arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 --
arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 --
arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 --
arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 --
7 files changed, 11 deletions(-)
diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts
b/arch/arm/dts/zynqmp-a2197-revA.dts
index 315313854254..27a9c60949a7 100644
--- a/arch/arm/dts/zynqmp-a2197-revA.dts
+++ b/arch/arm/dts/zynqmp-a2197-revA.dts
@@ -35,7 +35,6 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&i2c0 {
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 8ec2e866535b..7bcdbdfdbb06 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -124,7 +124,6 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index f94b797d1a24..69a3901ccf6c 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -75,7 +75,6 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&gem0 { /* eth MDIO 76/77 */
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 213149a3dc83..a5db599c9497 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -94,12 +94,10 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&uart1 { /* uart1 MIO40-41 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index c458110e5a89..58df328c987f 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -90,12 +90,10 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&uart1 { /* uart1 MIO40-41 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index cee7ca1fa995..25d87532be77 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -90,12 +90,10 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&uart1 { /* uart1 MIO40-41 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index 1f5201ac8883..82d5ef83f764 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -68,12 +68,10 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&uart1 { /* uart1 MIO40-41 */
status = "okay";
- u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
--
2.31.1
RE: [v2 04/17] arm: socfpga: Add handoff data support for Intel N5X device
Hi Ley Foon,
> -Original Message-
> From: Ley Foon Tan
> Sent: Friday, 14 May, 2021 5:13 PM
> To: Lim, Elly Siew Chin
> Cc: ZY - u-boot ; Marek Vasut ;
> Tan, Ley Foon ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: Re: [v2 04/17] arm: socfpga: Add handoff data support for Intel N5X
> device
>
> On Fri, Apr 30, 2021 at 3:39 PM Siew Chin Lim
> wrote:
> >
> > N5X support both HPS handoff data and DDR handoff data.
> > Existing HPS handoff functions are restructured to support both
> > existing devices and N5X device.
> >
> > Signed-off-by: Siew Chin Lim
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> > v2:
> > - Enabled auto detect the endianness from the magic word
> > - Merged and simplifying the big and little endian flow
> > ---
> > .../mach-socfpga/include/mach/handoff_soc64.h | 38 +-
> > arch/arm/mach-socfpga/system_manager_soc64.c | 18 +--
> > arch/arm/mach-socfpga/wrap_handoff_soc64.c| 126 +--
> ---
> > 3 files changed, 136 insertions(+), 46 deletions(-)
>
> [...]
>
> >
> > @@ -10,12 +10,54 @@
> > #include
> > #include "log.h"
> >
> > -int socfpga_get_handoff_size(void *handoff_address, enum endianness
> > endian)
> > +static enum endianness check_endianness(u32 handoff) {
> > + switch (handoff) {
> > + case SOC64_HANDOFF_MAGIC_BOOT:
> > + case SOC64_HANDOFF_MAGIC_MUX:
> > + case SOC64_HANDOFF_MAGIC_IOCTL:
> > + case SOC64_HANDOFF_MAGIC_FPGA:
> > + case SOC64_HANDOFF_MAGIC_DELAY:
> > + case SOC64_HANDOFF_MAGIC_CLOCK:
> > + case SOC64_HANDOFF_MAGIC_MISC:
> > + return BIG_ENDIAN;
> > +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> > + case SOC64_HANDOFF_DDR_UMCTL2_MAGIC:
> > + debug("%s: umctl2 handoff data\n", __func__);
> > + return LITTLE_ENDIAN;
> > + case SOC64_HANDOFF_DDR_PHY_MAGIC:
> > + debug("%s: PHY handoff data\n", __func__);
> > + return LITTLE_ENDIAN;
> > + case SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC:
> > + debug("%s: PHY engine handoff data\n", __func__);
> > + return LITTLE_ENDIAN;
> Can merge to one 'return' and print the 'handoff' if needed.
I can merge to one 'return' but has to compromise accuracy of DDR handoff type
debug print out. So, I don’t see any benefit of doing these.
Do you have any suggestion?
>
> > +#endif
> > + default:
> > + debug("%s: Unknown endianness!!\n", __func__);
> > + return UNKNOWN_ENDIANNESS;
> > + }
> > +}
> > +
> > +int socfpga_get_handoff_size(void *handoff_address)
> > {
> > u32 size;
> > + enum endianness endian_t;
> > +
> > + /* Checking handoff data is little endian ? */
> > + endian_t = check_endianness(readl(handoff_address));
> > +
> > + if (endian_t == UNKNOWN_ENDIANNESS) {
> > + /* Trying to check handoff data is big endian? */
> > + endian_t = check_endianness(swab32(readl(handoff_address)));
> > + if (endian_t == UNKNOWN_ENDIANNESS) {
> > + debug("%s: Cannot find HANDOFF MAGIC ", __func__);
> > + debug("at addr 0x%p\n", (u32 *)handoff_address);
> > + return -EPERM;
> > + }
> > + }
> >
> > size = readl(handoff_address + SOC64_HANDOFF_OFFSET_LENGTH);
> > - if (endian == BIG_ENDIAN)
> > + if (endian_t == BIG_ENDIAN)
> > size = swab32(size);
> >
> > size = (size - SOC64_HANDOFF_OFFSET_DATA) / sizeof(u32); @@
> > -26,41 +68,61 @@ int socfpga_get_handoff_size(void *handoff_address,
> enum endianness endian)
> > return size;
> > }
> >
> > -int socfpga_handoff_read(void *handoff_address, void *table, u32
> table_len,
> > -enum endianness big_endian)
> > +int socfpga_handoff_read(void *handoff_address, void *table, u32
> > +table_len)
> > {
> > - u32 temp, i;
> > + u32 temp;
> > u32 *table_x32 = table;
> > + u32 i = 0;
> > + enum endianness endian_t;
> > +
> > + /* Checking handoff data is little endian ? */
> > + endian_t = check_endianness(readl(handoff_address));
> This code is similar in socfpga_get_handoff_size(). Can have a function to get
> the endianness.
Okay.
>
> >
> > - debug("%s: handoff addr = 0x%p ", __func__, (u32
> *)handoff_address);
> > -
> > - if (big_endian) {
> > - if (swab32(readl(SOC64_HANDOFF_BASE)) ==
> SOC64_HANDOFF_MAGIC_BOOT) {
> > - debug("Handoff table address = 0x%p ", table_x32);
> > - debug("table length = 0x%x\n", table_len);
> > - debug("%s: handoff data =\n{\n", __func__);
> > -
> > - for (i = 0; i < table_len; i++) {
> > - temp = readl(handoff_address +
> > -
[PATCH] test/py:Update python tests for ‘gpio’ cmd
From: Adarsh Babu Kalepalli
Generic Python Test cases are developed to verfiy 'gpio' command.
Signed-off-by: Adarsh Babu Kalepalli
---
test/py/tests/test_gpio.py | 175 -
1 file changed, 174 insertions(+), 1 deletion(-)
diff --git a/test/py/tests/test_gpio.py b/test/py/tests/test_gpio.py
index 8c64f686b0..109649e2c7 100644
--- a/test/py/tests/test_gpio.py
+++ b/test/py/tests/test_gpio.py
@@ -1,6 +1,16 @@
-# SPDX-License-Identifier: GPL-2.0+
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2021 Adarsh Babu Kalepalli
+# Copyright (c) 2020 Alex Kiernan
import pytest
+import time
+import u_boot_utils
+
+"""
+ test_gpio_input is intended to test the fix 4dbc107f4683.
+ 4dbc107f4683:"cmd: gpio: Correct do_gpio() return value"
+"""
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpio')
@@ -35,3 +45,166 @@ def test_gpio_exit_statuses(u_boot_console):
assert(expected_response in response)
response = u_boot_console.run_command('gpio input 200; echo rc:$?')
assert(expected_response in response)
+
+
+"""
+Generic Tests for 'gpio' command on sandbox and real hardware.
+The below sequence of tests rely on env__gpio_dev_config for configuration
values of gpio pins.
+
+ Configuration data for gpio command.
+ The set,clear,toggle ,input and status options of 'gpio' command are
verified.
+ For sake of verification,A LED/buzzer could be connected to GPIO pins
configured as O/P.
+ Logic level '1'/'0' can be applied onto GPIO pins configured as I/P
+
+
+env__gpio_dev_config = {
+#the number of 'gpio_str_x' strings should equal to
+#'gpio_str_count' value
+'gpio_str_count':4 ,
+'gpio_str_1': '0',
+'gpio_str_2': '31',
+'gpio_str_3': '63',
+'gpio_str_4': '127',
+'gpio_op_pin': '64',
+'gpio_ip_pin_set':'65',
+'gpio_ip_pin_clear':'66',
+'gpio_clear_value': 'value is 0',
+'gpio_set_value': 'value is 1',
+}
+"""
+
+
+@pytest.mark.buildconfigspec('cmd_gpio')
+def test_gpio_status_all_generic(u_boot_console):
+"""Test the 'gpio status' command.
+
+ Displays all gpio pins available on the Board.
+ To verify if the status of pins is displayed or not,
+the user can configure (gpio_str_count) and verify existence of certain
+ pins.The details of these can be configured in 'gpio_str_n'.
+of boardenv_* (example above).User can configure any
+number of such pins and mention that count in 'gpio_str_count'.
+"""
+
+f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+if not f:
+pytest.skip("gpio not configured")
+
+gpio_str_count = f['gpio_str_count']
+
+#Display all the GPIO ports
+cmd = 'gpio status -a'
+response = u_boot_console.run_command(cmd)
+
+for str_value in range(1,gpio_str_count + 1):
+assert f["gpio_str_%d" %(str_value)] in response
+
+
+@pytest.mark.buildconfigspec('cmd_gpio')
+def test_gpio_set_generic(u_boot_console):
+"""Test the 'gpio set' command.
+
+ A specific gpio pin configured by user as output
+(mentioned in gpio_op_pin) is verified for
+ 'set' option
+
+"""
+
+f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+if not f:
+pytest.skip("gpio not configured")
+
+gpio_pin_adr = f['gpio_op_pin'];
+gpio_set_value = f['gpio_set_value'];
+
+
+cmd = 'gpio set ' + gpio_pin_adr
+response = u_boot_console.run_command(cmd)
+good_response = gpio_set_value
+assert good_response in response
+
+
+
+@pytest.mark.buildconfigspec('cmd_gpio')
+def test_gpio_clear_generic(u_boot_console):
+"""Test the 'gpio clear' command.
+
+ A specific gpio pin configured by user as output
+(mentioned in gpio_op_pin) is verified for
+ 'clear' option
+"""
+
+f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+if not f:
+pytest.skip("gpio not configured")
+
+gpio_pin_adr = f['gpio_op_pin'];
+gpio_clear_value = f['gpio_clear_value'];
+
+
+cmd = 'gpio clear ' + gpio_pin_adr
+response = u_boot_console.run_command(cmd)
+good_response = gpio_clear_value
+assert good_response in response
+
+
+@pytest.mark.buildconfigspec('cmd_gpio')
+def test_gpio_toggle_generic(u_boot_console):
+"""Test the 'gpio toggle' command.
+
+ A specific gpio pin configured by user as output
+(mentioned in gpio_op_pin) is verified for
+ 'toggle' option
+"""
+
+
+f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+if not f:
+pytest.skip("gpio not configured")
+
+gpio_pin_adr = f['gpio_op_pin'];
+gpio_set_value = f['gpio_set_value'];
+gpio_clear_value = f['gpio_clear_value'];
+
+cmd = 'gpio set ' + gpio_pin_adr
+response = u_boot_console.run_command(cmd)
+good_response = gpio_set_value
+assert good_response in response
+
+cmd = 'gpio t
[PULL] u-boot-riscv/master
Hi Tom,
The following changes since commit ffd810487ec2ff6095edf3f3d058d7ed6eb85ff3:
Merge tag 'u-boot-stm32-20210528' of
https://source.denx.de/u-boot/custodians/u-boot-stm (2021-05-28 14:11:06 -0400)
are available in the Git repository at:
g...@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to d7da718bd94943309a7f25f14e694226a45b2aef:
drivers: pci: pcie_dw_common: fix Werror compilation error (2021-05-31
16:35:55 +0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/
Green Wan (9):
riscv: cpu: fu740: Add support for cpu fu740
drivers: clk: add fu740 support
drivers: ram: sifive: rename fu540_ddr and add fu740 support
drivers: pci: add pcie support for fu740
riscv: dts: add fu740 support
riscv: dts: add SiFive Unmatched board support
board: sifive: add HiFive Unmatched board support
riscv: cpu: fu740: clear feature disable CSR
drivers: pci: pcie_dw_common: fix Werror compilation error
arch/riscv/Kconfig |5 +
arch/riscv/cpu/fu540/Kconfig |2 +-
arch/riscv/cpu/fu740/Kconfig | 37 +
arch/riscv/cpu/fu740/Makefile | 12 +
arch/riscv/cpu/fu740/cache.c | 55 +
arch/riscv/cpu/fu740/cpu.c | 22 +
arch/riscv/cpu/fu740/dram.c| 38 +
arch/riscv/cpu/fu740/spl.c | 38 +
arch/riscv/dts/Makefile|1 +
arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++
arch/riscv/dts/fu740-c000.dtsi | 329 +
arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489
arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi| 41 +
arch/riscv/dts/hifive-unmatched-a00.dts| 259
arch/riscv/include/asm/arch-fu740/cache.h | 14 +
arch/riscv/include/asm/arch-fu740/clk.h| 14 +
arch/riscv/include/asm/arch-fu740/gpio.h | 38 +
arch/riscv/include/asm/arch-fu740/reset.h | 13 +
arch/riscv/include/asm/arch-fu740/spl.h| 14 +
board/sifive/unleashed/Kconfig |1 +
board/sifive/unmatched/Kconfig | 51 +
board/sifive/unmatched/MAINTAINERS |9 +
board/sifive/unmatched/Makefile|9 +
board/sifive/unmatched/spl.c | 85 ++
board/sifive/unmatched/unmatched.c | 24 +
common/spl/Kconfig |4 +-
configs/sifive_unmatched_defconfig | 54 +
doc/board/sifive/index.rst |1 +
doc/board/sifive/unmatched.rst | 536 +++
drivers/clk/sifive/Kconfig |8 +-
drivers/clk/sifive/Makefile|4 +-
drivers/clk/sifive/fu540-prci.c| 769 +-
drivers/clk/sifive/fu540-prci.h| 22 +
drivers/clk/sifive/fu740-prci.c| 158 +++
drivers/clk/sifive/fu740-prci.h| 22 +
drivers/clk/sifive/sifive-prci.c | 733 ++
drivers/clk/sifive/sifive-prci.h | 323 +
drivers/pci/Kconfig| 10 +
drivers/pci/Makefile |1 +
drivers/pci/pcie_dw_common.c | 54 +-
drivers/pci/pcie_dw_sifive.c | 507 +++
drivers/ram/sifive/Kconfig |8 +-
drivers/ram/sifive/Makefile|2 +-
drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} | 89 +-
drivers/reset/Kconfig |2 +-
include/configs/sifive-unmatched.h | 83 ++
include/dt-bindings/clock/sifive-fu740-prci.h | 25 +
include/dt-bindings/reset/sifive-fu740-prci.h | 19 +
48 files changed, 5308 insertions(+), 831 deletions(-)
create mode 100644 arch/riscv/cpu/fu740/Kconfig
create mode 100644 arch/riscv/cpu/fu740/Makefile
create mode 100644 arch/riscv/cpu/fu740/cache.c
create mode 100644 arch/riscv/cpu/fu740/cpu.c
create mode 100644 arch/riscv/cpu/fu740/dram.c
create mode 100644 arch/riscv/cpu/fu740/spl.c
create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/fu740-c000.dtsi
create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h
create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h
create mode 100644 arch/riscv/include/asm/arc
[PATCH 3/3] zynqmp: Pass bl32 entry to TF-A via xilinx handoff structure
There is need to pass entry about secure OS when bl32_entry is defined.
Currently only 64bit support is added but /fit-images node have been
extended to also record if this is 32bit or 64bit secure OS. When this is
tested the code will be update to support this configuration too.
Signed-off-by: Michal Simek
---
arch/arm/mach-zynqmp/handoff.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c
index 7d7ab9da6ec2..31346d9b2e21 100644
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c
@@ -71,6 +71,7 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t
bl32_entry,
uintptr_t fdt_addr)
{
struct xfsbl_atf_handoff_params *atfhandoffparams;
+ u32 index = 0;
atfhandoffparams = (void *)CONFIG_SPL_TEXT_BASE;
atfhandoffparams->magic[0] = 'X';
@@ -78,14 +79,22 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t
bl32_entry,
atfhandoffparams->magic[2] = 'N';
atfhandoffparams->magic[3] = 'X';
- atfhandoffparams->num_entries = 0;
+ if (bl32_entry) {
+ atfhandoffparams->partition[index].entry_point = bl32_entry;
+ atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL1 <<
FSBL_FLAGS_EL_SHIFT |
+ FSBL_FLAGS_SECURE <<
FSBL_FLAGS_TZ_SHIFT;
+ index++;
+ }
+
if (bl33_entry) {
- atfhandoffparams->partition[0].entry_point = bl33_entry;
- atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
- FSBL_FLAGS_EL_SHIFT;
- atfhandoffparams->num_entries++;
+ atfhandoffparams->partition[index].entry_point = bl33_entry;
+ atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL2 <<
+ FSBL_FLAGS_EL_SHIFT;
+ index++;
}
+ atfhandoffparams->num_entries = index;
+
writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6);
return NULL;
--
2.31.1
[PATCH 2/3] zynqmp: Generate u-boot.its also with TEE dynamically
The first change is to trying to find out TF-A load address based on
reading elf file. Expectation is that bl31.bin is in the same folder as
bl31.elf. It brings new flexibility to place TF-A to any address (DDR
included).
And also enable TEE generation also with TEE configuration.
Expecation is the same as above that tee.bin and tee.elf are in the same
folder.
User has to just define link to BL31/BL32 binary files and the rest should
be handled by the script.
Signed-off-by: Michal Simek
---
I am using bash that's why not sure if ${BL31%.*} will work on other
shells but let's see.
---
arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
index 92e31849f88d..700871dbe109 100755
--- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
+++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
@@ -8,9 +8,19 @@
BL33="u-boot-nodtb.bin"
[ -z "$BL31" ] && BL31="bl31.bin"
-# Can be also done as ${CROSS_COMPILE}readelf -l bl31.elf | awk '/Entry point/
{ print $3 }'
+BL31_ELF="${BL31%.*}.elf"
+[ -f ${BL31_ELF} ] && ATF_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL31_ELF}"
| \
+awk '/Entry point/ { print $3 }'`
+
[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000"
+[ -z "$BL32" ] && BL32="tee.bin"
+BL32_ELF="${BL32%.*}.elf"
+[ -f ${BL32_ELF} ] && TEE_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL32_ELF}"
| \
+awk '/Entry point/ { print $3 }'`
+
+[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0x6000"
+
if [ -z "$BL33_LOAD_ADDR" ];then
BL33_LOAD_ADDR=`awk '/CONFIG_SYS_TEXT_BASE/ { print $3 }'
include/generated/autoconf.h`
fi
@@ -75,6 +85,24 @@ cat << __ATF
__ATF
fi
+if [ -f $BL32 ]; then
+cat << __TEE
+ tee {
+ description = "TEE firmware";
+ data = /incbin/("$BL32");
+ type = "firmware";
+ os = "tee";
+ arch = "arm64";
+ compression = "none";
+ load = <$TEE_LOAD_ADDR>;
+ entry = <$TEE_LOAD_ADDR>;
+ hash {
+ algo = "md5";
+ };
+ };
+__TEE
+fi
+
DEFAULT=1
cnt=1
for dtname in $DT
@@ -117,6 +145,16 @@ cat << __CONF_SECTION1_EOF
};
__CONF_SECTION1_EOF
else
+if [ -f $BL32 ]; then
+cat << __CONF_SECTION1_EOF
+ config_$cnt {
+ description = "$(basename $dtname .dtb)";
+ firmware = "atf";
+ loadables = "uboot", "tee";
+ fdt = "fdt_$cnt";
+ };
+__CONF_SECTION1_EOF
+else
cat << __CONF_SECTION1_EOF
config_$cnt {
description = "$(basename $dtname .dtb)";
@@ -126,6 +164,7 @@ cat << __CONF_SECTION1_EOF
};
__CONF_SECTION1_EOF
fi
+fi
cnt=$((cnt+1))
done
--
2.31.1
[PATCH 1/3] zynqmp: Do not place u-boot to reserved memory location
TF-A and SecureOS can allocate the part of DDR for self but U-Boot is not
handling this configuration that the part of memory is reserved and
shouldn't be used by U-Boot. That's why read all reserved memory locations
and don't use it.
The code was taken from commit 4a1b975dac02 ("board: stm32mp1: reserve
memory for OP-TEE in device tree") and commit 1419e5b5167e ("stm32mp:
update MMU config before the relocation") which is used by stm32 and does
the job properly.
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 46dee80470fa..3fe0b0dc29f6 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -11,6 +11,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -442,6 +444,25 @@ int dram_init(void)
return 0;
}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ phys_size_t size;
+ phys_addr_t reg;
+ struct lmb lmb;
+
+ /* found enough not-reserved memory to relocated U-Boot */
+ lmb_init(&lmb);
+ lmb_add(&lmb, gd->ram_base, gd->ram_size);
+ boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
+ size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
+ reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
+
+ if (!reg)
+ reg = gd->ram_top - size;
+
+ return reg + size;
+}
#else
int dram_init_banksize(void)
{
--
2.31.1
[PATCH 0/3] zynqmp: Add support for secure OS loading
Hi, this series is adding support for working with TEE in much easier and flexible way. TF-A can be placed to any location. When it is placed to DDR you should enable DT support which reserve location where TF-A is https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/10131 The similar DT support can be added to secure OS but I haven't sent that patches out in OPTEE case yet. Thanks, Michal Michal Simek (3): zynqmp: Do not place u-boot to reserved memory location zynqmp: Generate u-boot.its also with TEE dynamically zynqmp: Pass bl32 entry to TF-A via xilinx handoff structure arch/arm/mach-zynqmp/handoff.c | 19 +--- arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 41 - board/xilinx/zynqmp/zynqmp.c| 21 + 3 files changed, 75 insertions(+), 6 deletions(-) -- 2.31.1
[PATCH] spl: fit: Also record architecture in /fit-images
On ARM64 secure OS can run as 64bit or 32bit that's why it is necessary to
record information about architecture that other code can read it and
properly pass it to TF-A and start in 64bit or 32bit mode.
Signed-off-by: Michal Simek
---
common/fdt_support.c | 4 +++-
common/spl/spl_fit.c | 3 ++-
include/fdt_support.h | 3 ++-
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index a9a32df1e78f..240f1e57d135 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -594,7 +594,7 @@ void fdt_fixup_ethernet(void *fdt)
int fdt_record_loadable(void *blob, u32 index, const char *name,
uintptr_t load_addr, u32 size, uintptr_t entry_point,
- const char *type, const char *os)
+ const char *type, const char *os, const char *arch)
{
int err, node;
@@ -622,6 +622,8 @@ int fdt_record_loadable(void *blob, u32 index, const char
*name,
fdt_setprop_string(blob, node, "type", type);
if (os)
fdt_setprop_string(blob, node, "os", os);
+ if (arch)
+ fdt_setprop_string(blob, node, "arch", arch);
return node;
}
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index caddf5119679..f6c475315ed6 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -480,7 +480,8 @@ static int spl_fit_record_loadable(const struct
spl_fit_info *ctx, int index,
ret = fdt_record_loadable(blob, index, name, image->load_addr,
image->size, image->entry_point,
fdt_getprop(ctx->fit, node, "type", NULL),
- fdt_getprop(ctx->fit, node, "os", NULL));
+ fdt_getprop(ctx->fit, node, "os", NULL),
+ fdt_getprop(ctx->fit, node, "arch", NULL));
return ret;
}
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 1e4dbc0a8f65..f6f46bb8e9ce 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -160,11 +160,12 @@ static inline void fdt_fixup_crypto_node(void *blob, int
sec_rev) {}
* @param entry_point entry point (if specified, otherwise pass -1)
* @param type type (if specified, otherwise pass NULL)
* @param osos-type (if specified, otherwise pass NULL)
+ * @param arch architecture (if specified, otherwise pass NULL)
* @return 0 if ok, or -1 or -FDT_ERR_... on error
*/
int fdt_record_loadable(void *blob, u32 index, const char *name,
uintptr_t load_addr, u32 size, uintptr_t entry_point,
- const char *type, const char *os);
+ const char *type, const char *os, const char *arch);
#ifdef CONFIG_PCI
#include
--
2.31.1
Re: [PATCH v2] drivers: pci: pcie_dw_common: fix Werror compilation error
On 19/05/2021 13:16, Green Wan wrote:
> Fix compilation error when Werror is turned on. The warning could
> possible break some CI builds.
>
> Signed-off-by: Green Wan
> ---
> drivers/pci/pcie_dw_common.c | 54 +++-
> 1 file changed, 29 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
> index 785fd3aad0..e66fb1490a 100644
> --- a/drivers/pci/pcie_dw_common.c
> +++ b/drivers/pci/pcie_dw_common.c
> @@ -213,7 +213,7 @@ int pcie_dw_read_config(const struct udevice *bus,
> pci_dev_t bdf,
>
> va_address = set_cfg_address(pcie, bdf, offset);
>
> - value = readl(va_address);
> + value = readl((void __iomem *)va_address);
>
> debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
> *valuep = pci_conv_32_to_size(value, offset, size);
> @@ -257,9 +257,9 @@ int pcie_dw_write_config(struct udevice *bus, pci_dev_t
> bdf,
>
> va_address = set_cfg_address(pcie, bdf, offset);
>
> - old = readl(va_address);
> + old = readl((void __iomem *)va_address);
> value = pci_conv_size_to_32(old, value, offset, size);
> - writel(value, va_address);
> + writel(value, (void __iomem *)va_address);
>
> return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
>PCIE_ATU_TYPE_IO,
> pcie->io.phys_start,
> @@ -333,33 +333,37 @@ void pcie_dw_setup_host(struct pcie_dw *pci)
> }
> }
>
> - dev_dbg(pci->dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n",
> - pci->cfg_base, pci->cfg_base + pci->cfg_size,
> - pci->cfg_size);
> + dev_dbg(pci->dev, "Config space: [0x%llx - 0x%llx, size 0x%llx]\n",
> + (u64)pci->cfg_base, (u64)pci->cfg_base + pci->cfg_size,
> + (u64)pci->cfg_size);
>
> - dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%lx]\n",
> - pci->io.phys_start, pci->io.phys_start + pci->io.size,
> - pci->io.size);
> + dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n",
> + (u64)pci->io.phys_start, (u64)pci->io.phys_start + pci->io.size,
> + (u64)pci->io.size);
>
> - dev_dbg(pci->dev, "IO bus: [0x%lx - 0x%lx, size 0x%lx]\n",
> - pci->io.bus_start, pci->io.bus_start + pci->io.size,
> - pci->io.size);
> + dev_dbg(pci->dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n",
> + (u64)pci->io.bus_start, (u64)pci->io.bus_start + pci->io.size,
> + (u64)pci->io.size);
>
> - dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%lx]\n",
> - pci->mem.phys_start, pci->mem.phys_start + pci->mem.size,
> - pci->mem.size);
> + dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%llx]\n",
> + (u64)pci->mem.phys_start,
> + (u64)pci->mem.phys_start + pci->mem.size,
> + (u64)pci->mem.size);
>
> - dev_dbg(pci->dev, "MEM bus: [0x%lx - 0x%lx, size 0x%lx]\n",
> - pci->mem.bus_start, pci->mem.bus_start + pci->mem.size,
> - pci->mem.size);
> + dev_dbg(pci->dev, "MEM bus: [0x%llx - 0x%llx, size 0x%llx]\n",
> + (u64)pci->mem.bus_start,
> + (u64)pci->mem.bus_start + pci->mem.size,
> + (u64)pci->mem.size);
>
> if (pci->prefetch.size) {
> - dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size
> 0x%lx]\n",
> - pci->prefetch.phys_start, pci->prefetch.phys_start +
> pci->prefetch.size,
> - pci->prefetch.size);
> -
> - dev_dbg(pci->dev, "PREFETCH bus: [0x%lx - 0x%lx, size
> 0x%lx]\n",
> - pci->prefetch.bus_start, pci->prefetch.bus_start +
> pci->prefetch.size,
> - pci->prefetch.size);
> + dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size
> 0x%llx]\n",
> + (u64)pci->prefetch.phys_start,
> + (u64)pci->prefetch.phys_start + pci->prefetch.size,
> + (u64)pci->prefetch.size);
> +
> + dev_dbg(pci->dev, "PREFETCH bus: [0x%llx - 0x%llx, size
> 0x%llx]\n",
> + (u64)pci->prefetch.bus_start,
> + (u64)pci->prefetch.bus_start + pci->prefetch.size,
> + (u64)pci->prefetch.size);
> }
> }
>
Reviewed-by: Neil Armstrong
Re: [PATCHv2 3/3] pci: pcie_dw_rockchip: Use mleep macro to fix below error
On 21/05/2021 18:59, Anand Moon wrote:
> Define msleep macro to fix below error.
>
> drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
> declaration of function 'msleep' [-Wimplicit-function-declaration]
>
> Cc: Patrick Wildt
> Cc: Neil Armstrong
> Cc: Kever Yang
> Signed-off-by: Anand Moon
> ---
> v1: drop the udelay changes.
> ---
> drivers/pci/pcie_dw_rockchip.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
> index 4e448c0a3d..bdc4d51007 100644
> --- a/drivers/pci/pcie_dw_rockchip.c
> +++ b/drivers/pci/pcie_dw_rockchip.c
> @@ -60,6 +60,7 @@ struct rk_pcie {
> #define PCIE_CLIENT_DBG_TRANSITION_DATA 0x
> #define PCIE_CLIENT_DBF_EN 0x0003
>
> +#define msleep(a) udelay((a) * 1000)
> /* Parameters for the waiting for #perst signal */
> #define PERST_WAIT_MS1000
>
>
Please replace msleep occurences by udelay with either:
- udelay(MACRO_MS * 1000)
- udelay(MACRO_US) and replace MACRO_MS with MACRO_US with values *1000
Neil
Re: [PATCHv2 2/3] pci: pcie_dw_rockchip: Drop the unused variable warning
On 21/05/2021 18:59, Anand Moon wrote:
> Drop the unused variable warning below.
>
> drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable
> 'val' [-Wunused-variable]
> 161 | u32 val;
> | ^~~
>
> Cc: Patrick Wildt
> Cc: Neil Armstrong
> Cc: Kever Yang
> Signed-off-by: Anand Moon
> ---
> drivers/pci/pcie_dw_rockchip.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
> index 3ac2434b69..4e448c0a3d 100644
> --- a/drivers/pci/pcie_dw_rockchip.c
> +++ b/drivers/pci/pcie_dw_rockchip.c
> @@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie
> *rk_pcie, u32 reg,
> */
> static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
> {
> - u32 val;
> -
> dw_pcie_dbi_write_enable(&pci->dw, true);
>
> clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
>
Reviewed-by: Neil Armstrong
Re: [PATCHv2 1/3] pci: pcie_dw_rockchip: Fixed the below compilation error
On 21/05/2021 18:59, Anand Moon wrote:
> Use the generic error number instead of specific error number.
> Changes fix the below error.
>
> drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
> drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
> undeclared (first use in this function)
>70 | return PCIBIOS_UNSUPPORTED;
> | ^~~
> drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write':
> drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED'
> undeclared (first use in this function)
>90 | return PCIBIOS_UNSUPPORTED;
> | ^~~
>
> Cc: Patrick Wildt
> Cc: Neil Armstrong
> Cc: Kever Yang
> Signed-off-by: Anand Moon
> ---
> v1: Drop the PCI ERROR MACRO,
> ---
> drivers/pci/pcie_dw_rockchip.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
> index bc22af4230..3ac2434b69 100644
> --- a/drivers/pci/pcie_dw_rockchip.c
> +++ b/drivers/pci/pcie_dw_rockchip.c
> @@ -67,7 +67,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32
> *val)
> {
> if ((uintptr_t)addr & (size - 1)) {
> *val = 0;
> - return PCIBIOS_UNSUPPORTED;
> + return -EOPNOTSUPP;
> }
>
> if (size == 4) {
> @@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32
> *val)
> static int rk_pcie_write(void __iomem *addr, int size, u32 val)
> {
> if ((uintptr_t)addr & (size - 1))
> - return PCIBIOS_UNSUPPORTED;
> + return -EOPNOTSUPP;
>
> if (size == 4)
> writel(val, addr);
>
Reviewed-by: Neil Armstrong
[PATCH] zynqmp: Enable regulators
Enable command and fixed regulators. XDP platform is using them. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_virt_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 1df0ef66c22c..8191b7f73c67 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -61,6 +61,7 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_GETTIME=y CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_TPM=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y @@ -142,6 +143,8 @@ CONFIG_PHY_XILINX_GMII2RGMII=y CONFIG_PHY_FIXED=y CONFIG_XILINX_AXIEMAC=y CONFIG_ZYNQ_GEM=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_SCSI=y -- 2.31.1
Re: [PATCH] arm64: zynqmp: Add psu_init_gpl for k26 boards
st 19. 5. 2021 v 13:05 odesílatel Michal Simek napsal:
>
> Add psu_init_gpl file for getting SPL to work directly from the tree.
>
> Signed-off-by: Michal Simek
> ---
>
> .../zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 673 ++
> board/xilinx/zynqmp/zynqmp-smk-k26-revA | 1 +
> 2 files changed, 674 insertions(+)
> create mode 100644 board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
> create mode 12 board/xilinx/zynqmp/zynqmp-smk-k26-revA
>
> diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
> b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
> new file mode 100644
> index ..c448f2abb1a5
> --- /dev/null
> +++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
> @@ -0,0 +1,673 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
> + */
> +
> +#include
> +#include
> +
> +static unsigned long psu_pll_init_data(void)
> +{
> + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
> + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
> + psu_mask_write(0xFF5E0030, 0x0008U, 0x0008U);
> + psu_mask_write(0xFF5E0030, 0x0001U, 0x0001U);
> + psu_mask_write(0xFF5E0030, 0x0001U, 0xU);
> + mask_poll(0xFF5E0040, 0x0002U);
> + psu_mask_write(0xFF5E0030, 0x0008U, 0xU);
> + psu_mask_write(0xFF5E0048, 0x3F00U, 0x0300U);
> + psu_mask_write(0xFF5E0038, 0x8000U, 0xU);
> + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
> + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
> + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x2D00U);
> + psu_mask_write(0xFF5E0020, 0x0008U, 0x0008U);
> + psu_mask_write(0xFF5E0020, 0x0001U, 0x0001U);
> + psu_mask_write(0xFF5E0020, 0x0001U, 0xU);
> + mask_poll(0xFF5E0040, 0x0001U);
> + psu_mask_write(0xFF5E0020, 0x0008U, 0xU);
> + psu_mask_write(0xFF5E0044, 0x3F00U, 0x0300U);
> + psu_mask_write(0xFF5E0028, 0x8000U, 0xU);
> + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
> + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
> + psu_mask_write(0xFD1A0020, 0x0008U, 0x0008U);
> + psu_mask_write(0xFD1A0020, 0x0001U, 0x0001U);
> + psu_mask_write(0xFD1A0020, 0x0001U, 0xU);
> + mask_poll(0xFD1A0044, 0x0001U);
> + psu_mask_write(0xFD1A0020, 0x0008U, 0xU);
> + psu_mask_write(0xFD1A0048, 0x3F00U, 0x0300U);
> + psu_mask_write(0xFD1A0028, 0x8000U, 0xU);
> + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
> + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
> + psu_mask_write(0xFD1A002C, 0x0008U, 0x0008U);
> + psu_mask_write(0xFD1A002C, 0x0001U, 0x0001U);
> + psu_mask_write(0xFD1A002C, 0x0001U, 0xU);
> + mask_poll(0xFD1A0044, 0x0002U);
> + psu_mask_write(0xFD1A002C, 0x0008U, 0xU);
> + psu_mask_write(0xFD1A004C, 0x3F00U, 0x0300U);
> + psu_mask_write(0xFD1A0034, 0x8000U, 0xU);
> + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
> + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
> + psu_mask_write(0xFD1A0038, 0x0008U, 0x0008U);
> + psu_mask_write(0xFD1A0038, 0x0001U, 0x0001U);
> + psu_mask_write(0xFD1A0038, 0x0001U, 0xU);
> + mask_poll(0xFD1A0044, 0x0004U);
> + psu_mask_write(0xFD1A0038, 0x0008U, 0xU);
> + psu_mask_write(0xFD1A0050, 0x3F00U, 0x0300U);
> + psu_mask_write(0xFD1A0040, 0x8000U, 0xU);
> +
> + return 1;
> +}
> +
> +static unsigned long psu_clock_init_data(void)
> +{
> + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
> + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
> + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
> + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
> + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
> + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
> + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
> + psu_mask_write(0xFF18030C, 0x00020003U, 0xU);
> + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
> + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
> + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
> + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
> + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
> + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
> + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
> + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
> + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
> +
Re: [PATCH] ARM: zynq: Rename bus to be align with simple-bus yaml
st 19. 5. 2021 v 12:59 odesílatel Michal Simek napsal:
>
> Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI
> point-to-point channels for communicating addresses, data, and response
> transactions between master and slave clients. This ARM AMBA 3.0..."
>
> Issues are reported as:
> .. amba: $nodename:0: 'amba' does not match
> '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
> >From schema:
> ../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml
>
> Similar change has been done for Xilinx ZynqMP SoC.
>
> Signed-off-by: Michal Simek
> Link:
> https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.si...@xilinx.com
> ---
>
> arch/arm/dts/zynq-7000.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
> index c35eb2344fa8..4dda753671c2 100644
> --- a/arch/arm/dts/zynq-7000.dtsi
> +++ b/arch/arm/dts/zynq-7000.dtsi
> @@ -95,7 +95,7 @@
> };
> };
>
> - amba: amba {
> + amba: axi {
> u-boot,dm-pre-reloc;
> compatible = "simple-bus";
> #address-cells = <1>;
> --
> 2.31.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] arm64: zynqmp: Enable gpio driver for zcu1275/zcu1285
st 19. 5. 2021 v 11:56 odesílatel Michal Simek napsal:
>
> Enable gpio driver on these boards. GPIOs can be used on any board.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/dts/zynqmp-zcu1275-revA.dts | 4
> arch/arm/dts/zynqmp-zcu1275-revB.dts | 4
> arch/arm/dts/zynqmp-zcu1285-revA.dts | 4
> 3 files changed, 12 insertions(+)
>
> diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts
> b/arch/arm/dts/zynqmp-zcu1275-revA.dts
> index cdd5c341878f..b9a9d9802d93 100644
> --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
> +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
> @@ -39,6 +39,10 @@
> status = "okay";
> };
>
> +&gpio {
> + status = "okay";
> +};
> +
> &qspi {
> status = "okay";
> flash@0 {
> diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts
> b/arch/arm/dts/zynqmp-zcu1275-revB.dts
> index 1de890c30f64..f14707419b40 100644
> --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
> +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
> @@ -64,6 +64,10 @@
> };
> };
>
> +&gpio {
> + status = "okay";
> +};
> +
> &qspi {
> status = "okay";
> flash@0 {
> diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts
> b/arch/arm/dts/zynqmp-zcu1285-revA.dts
> index 21d62e993a33..42a73ea31aec 100644
> --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
> +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
> @@ -245,6 +245,10 @@
> };
> };
>
> +&gpio {
> + status = "okay";
> +};
> +
> &qspi {
> status = "okay";
> flash@0 {
> --
> 2.31.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] arm64: zynqmp: Enable EFI secure boot
st 19. 5. 2021 v 12:28 odesílatel Michal Simek napsal: > > Enabling EFI secure boot which is required for EBBR specification. > Enabling this will fix > "RT.SetVariable - Create one Time Base Auth Variable, the expect return > status should be EFI_SUCCESS" > > Signed-off-by: Michal Simek > --- > > configs/xilinx_zynqmp_virt_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/xilinx_zynqmp_virt_defconfig > b/configs/xilinx_zynqmp_virt_defconfig > index e939b04ef6a5..ece527e07468 100644 > --- a/configs/xilinx_zynqmp_virt_defconfig > +++ b/configs/xilinx_zynqmp_virt_defconfig > @@ -190,3 +190,4 @@ CONFIG_EFI_CAPSULE_ON_DISK=y > CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y > CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y > CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y > +CONFIG_EFI_SECURE_BOOT=y > -- > 2.31.1 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] arm64: zynqmp: Add support for SVD devices
st 19. 5. 2021 v 10:45 odesílatel Michal Simek napsal:
>
> SVD (Software Virtual Devices) are using different name which can't be
> handled via zynqmp_devices structure. That's why introduce
> zynqmp_detect_svd_name() which checks ID code for these devices and show
> proper name for them.
>
> Signed-off-by: Michal Simek
> ---
>
> board/xilinx/zynqmp/zynqmp.c | 28 +++-
> 1 file changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index d05f0b2e1202..6e353e3b0a57 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -185,6 +185,32 @@ static const struct {
> },
> };
>
> +static const struct {
> + u32 id;
> + char *name;
> +} zynqmp_svd_devices[] = {
> + {
> + .id = 0x04714093,
> + .name = "xck24"
> + },
> + {
> + .id = 0x04724093,
> + .name = "xck26",
> + },
> +};
> +
> +static char *zynqmp_detect_svd_name(u32 idcode)
> +{
> + u32 i;
> +
> + for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) {
> + if (zynqmp_svd_devices[i].id == (idcode & 0x0FFF))
> + return zynqmp_svd_devices[i].name;
> + }
> +
> + return "unknown";
> +}
> +
> static char *zynqmp_get_silicon_idcode_name(void)
> {
> u32 i;
> @@ -219,7 +245,7 @@ static char *zynqmp_get_silicon_idcode_name(void)
> }
>
> if (i >= ARRAY_SIZE(zynqmp_devices))
> - return "unknown";
> + return zynqmp_detect_svd_name(idcode);
>
> /* Add device prefix to the name */
> ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
> --
> 2.31.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc
st 19. 5. 2021 v 12:19 odesílatel Michal Simek napsal: > > From: T Karthik Reddy > > CONFIG_ZYNQMP_FIRMWARE enables zynqmp firmware driver. > > Signed-off-by: T Karthik Reddy > Signed-off-by: Michal Simek > --- > > configs/xilinx_versal_mini_emmc0_defconfig | 1 + > configs/xilinx_versal_mini_emmc1_defconfig | 1 + > configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + > configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + > 4 files changed, 4 insertions(+) > > diff --git a/configs/xilinx_versal_mini_emmc0_defconfig > b/configs/xilinx_versal_mini_emmc0_defconfig > index 8837987e35e9..5721e005d7cb 100644 > --- a/configs/xilinx_versal_mini_emmc0_defconfig > +++ b/configs/xilinx_versal_mini_emmc0_defconfig > @@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > # CONFIG_NET is not set > # CONFIG_DM_WARN is not set > # CONFIG_DM_DEVICE_REMOVE is not set > +CONFIG_ZYNQMP_FIRMWARE=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ZYNQ=y > CONFIG_ARM_DCC=y > diff --git a/configs/xilinx_versal_mini_emmc1_defconfig > b/configs/xilinx_versal_mini_emmc1_defconfig > index b07dc0406070..db06ea3ab649 100644 > --- a/configs/xilinx_versal_mini_emmc1_defconfig > +++ b/configs/xilinx_versal_mini_emmc1_defconfig > @@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > # CONFIG_NET is not set > # CONFIG_DM_WARN is not set > # CONFIG_DM_DEVICE_REMOVE is not set > +CONFIG_ZYNQMP_FIRMWARE=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ZYNQ=y > CONFIG_ARM_DCC=y > diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig > b/configs/xilinx_zynqmp_mini_emmc0_defconfig > index 4594f8096d39..bafbd8a3d317 100644 > --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig > +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig > @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > # CONFIG_DM_WARN is not set > # CONFIG_DM_DEVICE_REMOVE is not set > CONFIG_SPL_DM_SEQ_ALIAS=y > +CONFIG_ZYNQMP_FIRMWARE=y > CONFIG_SUPPORT_EMMC_BOOT=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ZYNQ=y > diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig > b/configs/xilinx_zynqmp_mini_emmc1_defconfig > index d7c64b9da535..ef2be75e1fa6 100644 > --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig > +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig > @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > # CONFIG_DM_WARN is not set > # CONFIG_DM_DEVICE_REMOVE is not set > CONFIG_SPL_DM_SEQ_ALIAS=y > +CONFIG_ZYNQMP_FIRMWARE=y > CONFIG_SUPPORT_EMMC_BOOT=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ZYNQ=y > -- > 2.31.1 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] arm64: zynqmp: Fix application loading on R5 core1
st 19. 5. 2021 v 12:02 odesílatel Michal Simek napsal:
>
> From: Ashok Reddy Soma
>
> From U-Boot, loading application on RPU core 0 is fine but loading on
> core 1 is not handled properly. Lock-step mode needs both the R5 cores
> to be initialized and it is working fine. Whereas in SPLIT mode individual
> R5 cores needs to be initialized as they need to execute differenet
> applications. Handle both these lock-step and split modes by propagating
> mode and RPU core number(4 for RPU0 and 5 for RPU1) for various functions
> and by adding conditions in those functions.
>
> Signed-off-by: Ashok Reddy Soma
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/mach-zynqmp/mp.c | 70 ++-
> 1 file changed, 39 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
> index 656678a1551f..74783ae5a78a 100644
> --- a/arch/arm/mach-zynqmp/mp.c
> +++ b/arch/arm/mach-zynqmp/mp.c
> @@ -37,6 +37,8 @@
>
> #define ZYNQMP_CORE_APU0 0
> #define ZYNQMP_CORE_APU3 3
> +#define ZYNQMP_CORE_RPU0 4
> +#define ZYNQMP_CORE_RPU1 5
>
> #define ZYNQMP_MAX_CORES 6
>
> @@ -54,18 +56,20 @@ int cpu_reset(u32 nr)
> return 0;
> }
>
> -static void set_r5_halt_mode(u8 halt, u8 mode)
> +static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
> {
> u32 tmp;
>
> - tmp = readl(&rpu_base->rpu0_cfg);
> - if (halt == HALT)
> - tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
> - else
> - tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
> - writel(tmp, &rpu_base->rpu0_cfg);
> + if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
> + tmp = readl(&rpu_base->rpu0_cfg);
> + if (halt == HALT)
> + tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
> + else
> + tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
> + writel(tmp, &rpu_base->rpu0_cfg);
> + }
>
> - if (mode == LOCK) {
> + if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
> tmp = readl(&rpu_base->rpu1_cfg);
> if (halt == HALT)
> tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
> @@ -93,30 +97,34 @@ static void set_r5_tcm_mode(u8 mode)
> writel(tmp, &rpu_base->rpu_glbl_ctrl);
> }
>
> -static void set_r5_reset(u8 mode)
> +static void set_r5_reset(u32 nr, u8 mode)
> {
> u32 tmp;
>
> tmp = readl(&crlapb_base->rst_lpd_top);
> - tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
> - ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
> + if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
> + tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
> + ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
>
> - if (mode == LOCK)
> - tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
> + if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
> + tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
> + ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
>
> writel(tmp, &crlapb_base->rst_lpd_top);
> }
>
> -static void release_r5_reset(u8 mode)
> +static void release_r5_reset(u32 nr, u8 mode)
> {
> u32 tmp;
>
> tmp = readl(&crlapb_base->rst_lpd_top);
> - tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
> - ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
> + if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
> + tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
> +ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
>
> - if (mode == LOCK)
> - tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
> + if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
> + tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
> +ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
>
> writel(tmp, &crlapb_base->rst_lpd_top);
> }
> @@ -141,7 +149,7 @@ int cpu_disable(u32 nr)
> val |= 1 << nr;
> writel(val, &crfapb_base->rst_fpd_apu);
> } else {
> - set_r5_reset(LOCK);
> + set_r5_reset(nr, SPLIT);
> }
>
> return 0;
> @@ -212,14 +220,14 @@ void initialize_tcm(bool mode)
> {
> if (!mode) {
> set_r5_tcm_mode(LOCK);
> - set_r5_halt_mode(HALT, LOCK);
> + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK);
> enable_clock_r5();
> - release_r5_reset(LOCK);
> + release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
> } else {
> set_r5_tcm_mode(SPLIT);
> - set_r5_halt_mode(HALT, SPLIT);
> + set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
> enable_clock_r5();
> - release_r5_reset(SPLIT);
> + release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
> }
> }
>
> @@ -268,28 +276,28 @@ int cpu_release(u32 nr, int argc, char *const argv[])
>
> if (!strncmp(argv
Re: [PATCH 1/2] ARM: zynq: Convert at25 binding to new description on zc770-xm013
čt 27. 5. 2021 v 12:19 odesílatel Michal Simek napsal:
>
> The Linux commit f8f79fa6bb25 ("dt-bindings: at25: convert the binding
> document to yaml") converted binding to yaml and 3 deprecated properties
> pop up.
>
> The patch is fixing these warnings:
> .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property
> .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property
> .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property
> >From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml
>
> by converting them to new binding.
>
> Signed-off-by: Michal Simek
> Link:
> https://lore.kernel.org/r/be2c1125d98386033e182012eb08986924707a76.1606397101.git.michal.si...@xilinx.com
> ---
>
> arch/arm/dts/zynq-zc770-xm013.dts | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/zynq-zc770-xm013.dts
> b/arch/arm/dts/zynq-zc770-xm013.dts
> index bdf0c2f956d1..7218ee3ad8ef 100644
> --- a/arch/arm/dts/zynq-zc770-xm013.dts
> +++ b/arch/arm/dts/zynq-zc770-xm013.dts
> @@ -68,13 +68,12 @@
> num-cs = <4>;
> is-decoded-cs = <0>;
> eeprom: eeprom@2 {
> - at25,byte-len = <8192>;
> - at25,addr-mode = <2>;
> - at25,page-size = <32>;
> -
> compatible = "atmel,at25";
> reg = <2>;
> spi-max-frequency = <100>;
> + size = <8192>;
> + address-width = <16>;
> + pagesize = <32>;
> };
> };
>
> --
> 2.31.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 2/2] ARM: zynq: Fix OCM mapping to be aligned with binding on zc702
čt 27. 5. 2021 v 12:19 odesílatel Michal Simek napsal:
>
> The Linux commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to
> json-schema") converted binding to yaml and some missing required
> properties started to be reported. Align binding based on it.
>
> The patch is fixing these warnings:
> .../zynq-zc702.dt.yaml: sram@fffc: '#address-cells' is a required property
> .../zynq-zc702.dt.yaml: sram@fffc: '#size-cells' is a required property
> .../zynq-zc702.dt.yaml: sram@fffc: 'ranges' is a required property
> >From schema: .../Documentation/devicetree/bindings/sram/sram.yaml
>
> Signed-off-by: Michal Simek
> Link:
> https://lore.kernel.org/r/87c02786ccd8d7827827a9d95a8737bb300caeb0.1606397101.git.michal.si...@xilinx.com
> ---
>
> arch/arm/dts/zynq-zc702.dts | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
> index e45eba3d90b3..4474f4bfd7b2 100644
> --- a/arch/arm/dts/zynq-zc702.dts
> +++ b/arch/arm/dts/zynq-zc702.dts
> @@ -68,6 +68,12 @@
> ocm: sram@fffc {
> compatible = "mmio-sram";
> reg = <0xfffc 0x1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0xfffc 0x1>;
> + ocm-sram@0 {
> + reg = <0x0 0x1>;
> + };
> };
> };
>
> --
> 2.31.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
[PATCH 7/7] arm64: zynqmp: Update Copyright years to 2021
Trivial change for all files I have touched recently. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 2 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu1285-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index ef7cf0a36b21..65dd4e1f3a5d 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 039a8da1a960..0c6a2a92dfe5 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index d6e924803354..1a8cfdeb7f45 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 46b27a000949..41ab20c3895f 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 3be69ad9bce4..cad1a23e9539 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek * Nathalie Chan King Choy diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index ec61b7089da2..7190e876d8dd 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index c25ac9af48e8..76c635f0d460 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index ce9d8fb3b815..f9eb4caaf8c0 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 2fd41ad2d523..4da7a3edf548 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 10bb45b49f1a..85821065dd43 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek */ diff --git a/arch/arm/dts/zynqmp-zcu1275-
[PATCH 6/7] arm64: zynqmp: Add label for zynqmp_ipi
Add label which is used by bootloader for adding bootloader specific flag.
Signed-off-by: Michal Simek
Link:
https://lore.kernel.org/r/3dc8416abdd3498e61edcd83830a12af295c5c6d.1611224800.git.michal.si...@xilinx.com
---
arch/arm/dts/zynqmp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 345ab97e269a..deb3fa3ab3f3 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -100,7 +100,7 @@
};
};
- zynqmp_ipi {
+ zynqmp_ipi: zynqmp_ipi {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
--
2.31.1
[PATCH 5/7] arm64: zynqmp: Move DP nodes to the end of file (zcu106)
Just sync it with others for easier comparison.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zcu106-revA.dts | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts
b/arch/arm/dts/zynqmp-zcu106-revA.dts
index e86fef5be6f0..2fd41ad2d523 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -163,17 +163,6 @@
status = "okay";
};
-&zynqmp_dpdma {
- status = "okay";
-};
-
-&zynqmp_dpsub {
- status = "okay";
- phy-names = "dp-phy0", "dp-phy1";
- phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
- <&psgtr 0 PHY_TYPE_DP 1 3>;
-};
-
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
@@ -1056,3 +1045,14 @@
&watchdog0 {
status = "okay";
};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+ <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
--
2.31.1
[PATCH 3/7] arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi
From: Stefano Stabellini
The SMMU is disabled in device tree so this change has no impact.
The benefit is that this way it is in sync with xen.dtsi. Xen enables
the SMMU and makes use of it.
Signed-off-by: Stefano Stabellini
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index db4099b7516b..37ee9539801c 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -648,6 +648,8 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x4d0>;
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
--
2.31.1
[PATCH 2/7] arm64: zynqmp: Disable CCI by default
There is no reason to have CCI no enabled by default. Enable it when your
system configuration requires it. In Xilinx configuration flow this is
work for Device Tree Generator which reads information from HW Design
configuration.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 84d9770225aa..db4099b7516b 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -246,6 +246,7 @@
cci: cci@fd6e {
compatible = "arm,cci-400";
+ status = "disabled";
reg = <0x0 0xfd6e 0x0 0x9000>;
ranges = <0x0 0x0 0xfd6e 0x1>;
#address-cells = <1>;
--
2.31.1
[PATCH 1/7] arm64: zynqmp: Update psgtr clocks index for boards
Update the psgtr clock indexing for couple of zynqmp boards.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zcu100-revC.dts | 18 +-
arch/arm/dts/zynqmp-zcu106-revA.dts | 14 +++---
arch/arm/dts/zynqmp-zcu111-revA.dts | 14 +++---
arch/arm/dts/zynqmp-zcu208-revA.dts | 6 +++---
arch/arm/dts/zynqmp-zcu216-revA.dts | 6 +++---
5 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts
b/arch/arm/dts/zynqmp-zcu100-revC.dts
index b83696cccd2b..3be69ad9bce4 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -132,13 +132,13 @@
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
- si5335a_0: clk26 {
+ si5335_0: si5335_0 { /* clk0_usb - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2600>;
};
- si5335a_1: clk27 {
+ si5335_1: si5335_1 { /* clk1_dp - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2700>;
@@ -483,13 +483,6 @@
};
};
-&psgtr {
- status = "okay";
- /* usb3, dps */
- clocks = <&si5335a_0>, <&si5335a_1>;
- clock-names = "ref0", "ref1";
-};
-
&rtc {
status = "okay";
};
@@ -525,6 +518,13 @@
};
};
+&psgtr {
+ status = "okay";
+ /* usb3, dp */
+ clocks = <&si5335_0>, <&si5335_1>;
+ clock-names = "ref0", "ref1";
+};
+
&spi0 { /* Low Speed connector */
status = "okay";
label = "LS-SPI0";
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts
b/arch/arm/dts/zynqmp-zcu106-revA.dts
index ae20e581c0f4..e86fef5be6f0 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -958,13 +958,6 @@
};
};
-&psgtr {
- status = "okay";
- /* nc, sata, usb3, dp */
- clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
- clock-names = "ref1", "ref2", "ref3";
-};
-
&qspi {
status = "okay";
is-dual = <1>;
@@ -995,6 +988,13 @@
};
};
+&psgtr {
+ status = "okay";
+ /* nc, sata, usb3, dp */
+ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&rtc {
status = "okay";
};
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts
b/arch/arm/dts/zynqmp-zcu111-revA.dts
index d564f74344c9..10bb45b49f1a 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -773,13 +773,6 @@
};
};
-&psgtr {
- status = "okay";
- /* nc, sata, usb3, dp */
- clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
- clock-names = "ref1", "ref2", "ref3";
-};
-
&qspi {
status = "okay";
is-dual = <1>;
@@ -810,6 +803,13 @@
};
};
+&psgtr {
+ status = "okay";
+ /* nc, dp, usb3, sata */
+ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&rtc {
status = "okay";
};
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts
b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 880281d4e79b..496e8d1de22b 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -651,9 +651,9 @@
&psgtr {
status = "okay";
- /* pcie, sata, usb3, dp */
- clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
- clock-names = "ref0", "ref1", "ref2", "ref3";
+ /* nc, nc, usb3, sata */
+ clocks = <&si5341 0 2>, <&si5341 0 3>;
+ clock-names = "ref2", "ref3";
};
&rtc {
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts
b/arch/arm/dts/zynqmp-zcu216-revA.dts
index f899226ae198..3a205c089444 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -132,9 +132,9 @@
&psgtr {
status = "okay";
- /* pcie, sata, usb3, dp */
- clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
- clock-names = "ref0", "ref1", "ref2", "ref3";
+ /* nc, nc, usb3, sata */
+ clocks = <&si5341 0 2>, <&si5341 0 3>;
+ clock-names = "ref2", "ref3";
};
&dcc {
--
2.31.1
[PATCH 4/7] arm64: zynqmp: Add reset description for sata
Sata needs to get reset before configuration that's why add property for it there. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 37ee9539801c..345ab97e269a 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -701,6 +701,7 @@ interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; -- 2.31.1
[PATCH 0/7] arm64: zynqmp: DT syncup
Hi, I am sending this series to align DT files with the latest description. Couple of changes are taken from Linux kernel and others from Xilinx trees. Thanks, Michal Michal Simek (6): arm64: zynqmp: Update psgtr clocks index for boards arm64: zynqmp: Disable CCI by default arm64: zynqmp: Add reset description for sata arm64: zynqmp: Move DP nodes to the end of file (zcu106) arm64: zynqmp: Add label for zynqmp_ipi arm64: zynqmp: Update Copyright years to 2021 Stefano Stabellini (1): arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 2 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 20 ++--- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 38 arch/arm/dts/zynqmp-zcu111-revA.dts | 16 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu1285-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 8 ++--- arch/arm/dts/zynqmp-zcu216-revA.dts | 8 ++--- arch/arm/dts/zynqmp.dtsi | 8 +++-- 16 files changed, 61 insertions(+), 57 deletions(-) -- 2.31.1
[PATCH] arm64: zynqmp: Handle MMC seq number based on boot device
K26 has EMMC and SD and default 0 is not working when system is booting out
of SD which is controller 1. Add controller autodetection via
mmc_get_env_dev(). The same code is used for distro_boot selection done in
board_late_init(). bootseq variable can't be reused because this is called
so late.
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c | 35
configs/xilinx_zynqmp_virt_defconfig | 1 +
2 files changed, 36 insertions(+)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 6e353e3b0a57..46dee80470fa 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -709,6 +709,41 @@ int checkboard(void)
return 0;
}
+int mmc_get_env_dev(void)
+{
+ struct udevice *dev;
+ int bootseq = 0;
+
+ switch (zynqmp_get_bootmode()) {
+ case EMMC_MODE:
+ case SD_MODE:
+ if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@ff16", &dev) &&
+ uclass_get_device_by_name(UCLASS_MMC,
+ "sdhci@ff16", &dev)) {
+ return -1;
+ }
+ bootseq = dev_seq(dev);
+ break;
+ case SD1_LSHFT_MODE:
+ case SD_MODE1:
+ if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@ff17", &dev) &&
+ uclass_get_device_by_name(UCLASS_MMC,
+ "sdhci@ff17", &dev)) {
+ return -1;
+ }
+ bootseq = dev_seq(dev);
+ break;
+ default:
+ break;
+ }
+
+ debug("bootseq %d\n", bootseq);
+
+ return bootseq;
+}
+
enum env_location env_get_location(enum env_operation op, int prio)
{
u32 bootmode = zynqmp_get_bootmode();
diff --git a/configs/xilinx_zynqmp_virt_defconfig
b/configs/xilinx_zynqmp_virt_defconfig
index ece527e07468..1df0ef66c22c 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -76,6 +76,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART=":auto"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
--
2.31.1
[[PATCH] colibri_imx6: add board_fit_config_name_match to support FIT in SPL
From: Ming Liu
Only one dtb is currently supported, so match with imx6-colibri.
Signed-off-by: Ming Liu
---
board/toradex/colibri_imx6/colibri_imx6.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c
b/board/toradex/colibri_imx6/colibri_imx6.c
index c0e7754469..587d92a8e9 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -1081,6 +1081,16 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "imx6-colibri"))
+ return 0;
+
+ return -1;
+}
+#endif
+
void reset_cpu(void)
{
}
--
2.29.0
Re: [PATCH] drivers: tpm2: update reset gpio semantics
On 5/28/21 6:18 PM, Bruno Thomsen wrote:
> Den tor. 27. maj 2021 kl. 09.15 skrev Michal Simek :
>>
>>
>>
>> On 5/26/21 9:57 PM, Jorge Ramirez-Ortiz wrote:
>>> Use the more generic reset-gpios propery name.
>>>
>>> Signed-off-by: Jorge Ramirez-Ortiz
>>> ---
>>> doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt | 2 +-
>>> drivers/tpm/tpm2_tis_spi.c | 2 +-
>>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
>>> b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
>>> index 3a2ee4bd17..bbcd12950f 100644
>>> --- a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
>>> +++ b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
>>> @@ -6,7 +6,7 @@ Required properties:
>>> - reg: SPI Chip select
>>>
>>> Optional properties:
>>> -- gpio-reset : Reset GPIO (if not connected to the SoC reset line)
>>> +- reset-gpios: Reset GPIO (if not connected to the SoC
>>> reset line)
>>> - spi-max-frequency : See spi-bus.txt
>>>
>>> Example:
>>> diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
>>> index 4b33ac8fd3..94ac52d9ce 100644
>>> --- a/drivers/tpm/tpm2_tis_spi.c
>>> +++ b/drivers/tpm/tpm2_tis_spi.c
>>> @@ -589,7 +589,7 @@ static int tpm_tis_spi_probe(struct udevice *dev)
>>> if (CONFIG_IS_ENABLED(DM_GPIO)) {
>>> struct gpio_desc reset_gpio;
>>>
>>> - ret = gpio_request_by_name(dev, "gpio-reset", 0,
>>> + ret = gpio_request_by_name(dev, "reset-gpios", 0,
>>> &reset_gpio, GPIOD_IS_OUT);
>>> if (ret) {
>>> log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset
>>> GPIO\n",
>>>
>>
>> I think you should deprecate gpio-reset but keep supporting that option
>> with any warning and add code for reset-gpios.
>>
>> Also would be good to add it as optional property to Linux kernel to
>> keep it in sync.
>
> Hi
>
> The reason the Linux kernel does not have a TPM reset signal, is
> that being able to reset the chip from software is a vulnerability.
> There was a discussion on it over on the Barebox mailing list
> a while ago.
>
> TLDR: TPM reset needs to follow SOC reset.
I expect chip has the reset in both cases and it is just about who
should be calling it. But we should be using the same DT for u-boot and
Linux. It means it should be handled properly but described properly.
Thanks,
Michal
[[PATCH] tools: image-host: fix wrong return value
From: Ming Liu
The return value '-ENOSPC' of fit_set_timestamp function does not match
the caller fit_image_write_sig's expection which is '-FDT_ERR_NOSPACE'.
Fix it by not calling fit_set_timestamp, but call fdt_setprop instead.
This fixes a following mkimage error:
| Can't write signature for 'signature@1' signature node in
| 'c...@imx6ull-colibri-wifi-eval-v3.dtb' conf node:
| mkimage Can't add hashes to FIT blob: -1
Signed-off-by: Ming Liu
---
tools/image-host.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tools/image-host.c b/tools/image-host.c
index 270d36fe45..73095461a7 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -132,8 +132,10 @@ static int fit_image_write_sig(void *fit, int noffset,
uint8_t *value,
if (!ret) {
time_t timestamp = imagetool_get_source_date(cmdname,
time(NULL));
+ uint32_t t = cpu_to_uimage(timestamp);
- ret = fit_set_timestamp(fit, noffset, timestamp);
+ ret = fdt_setprop(fit, noffset, FIT_TIMESTAMP_PROP, &t,
+ sizeof(uint32_t));
}
if (region_prop && !ret) {
uint32_t strdata[2];
--
2.29.0
