Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages
Le ven. 9 juil. 2021 à 03:09, Julius Werner a écrit : > > Of course every project would like not to change... > > > > For TF-A I wonder whether it will/should in fact use devicetree if there > is a lot of complex data? TBD, I suppose. > > Okay, sorry, now I'm a bit confused -- I thought the discussion in > this thread was about which parameter hand-off mechanism to use *for > TF-A*? Or did it shift to discuss other projects in the meantime (I > didn't always follow it closely)? I think it started with the UEFI > guys wanting to implement a HOB format to interface with TF-A, and I > think we now concluded that they're okay with using a simple parameter > list instead (and wrapping their custom HOBs into a parameter blob > that contains their UUID and everything else in the data part). > > So for TF-A, if the decision is that we want a parameter list, I think > it makes sense to keep using the format that has already been there > and in use for several years, and define new tags for the UEFI HOB use > case in that. I don't really see a reason to switch TF-A and all other > projects currently interfacing with it that way (e.g. coreboot) to > something only used by U-Boot right now, if they're practically > identical in concept. Looking at bl_au_params: used by 3 SoCs to deal with gpio and serial. Migration may not be that a big effort (handful lines of code?). The key thing is that the biggest consumer of them are BL33 and a little bit by some OS drivers (OS itself shall not be a consumer). U-Boot has an established mechanism which is used in particular on all chrome books in both x86 and Arm environments. I have the impression that U-Boot is the typical BL33 so I would import the mechanism into TFA, not the other way round. EDK2 has typically its own code for TFA matters and may just import BL31, so it does not appear a priority in that decision. But I may be wrong… > > -- François-Frédéric Ozog | *Director Business Development* T: +33.67221.6485 francois.o...@linaro.org | Skype: ffozog
Re: [PATCH 1/6] dm: pci: add option to map virtual system memory base address
On 06.07.21 16:22, Daniel Schwierzeck wrote:
On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE
is still used as a virtual, CPU-mapped address instead of being used
as physical address. Converting all MIPS boards and generic MIPS code
to fix that is not trivial. Due to the approaching deadline for
PCI DM conversion, this workaround is required for MIPS boards with
PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved.
Add a compile-time option to let the PCI uclass core optionally map
the DRAM address to a physical address when adding the PCI region
of type PCI_REGION_SYS_MEMORY.
Signed-off-by: Daniel Schwierzeck
---
drivers/pci/Kconfig | 13 +
drivers/pci/pci-uclass.c | 9 ++---
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b2b7b253f8..02c34077e2 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -54,6 +54,19 @@ config PCI_REGION_MULTI_ENTRY
region type. This helps to add support for SoC's like OcteonTX/TX2
where every peripheral is on the PCI bus.
+config PCI_MAP_SYSTEM_MEMORY
+ bool "Map local system memory from a virtual base address"
+ depends on PCI || DM_PCI
+ depends on MIPS
+ default n
AFAIK, "default n" is not needed as it's the "default" setting.
Apart from this:
Reviewed-by: Stefan Roese
Thanks,
Stefan
+ help
+ Say Y if base address of system memory is being used as a virtual
address
+ instead of a physical address (e.g. on MIPS). The PCI core will then
remap
+ the virtual memory base address to a physical address when adding the
PCI
+ region of type PCI_REGION_SYS_MEMORY.
+ This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is
still
+ being used as virtual address.
+
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
depends on PCI || DM_PCI
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 22a033e632..1e2ed5426e 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -998,10 +998,13 @@ static void decode_regions(struct pci_controller *hose,
ofnode parent_node,
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
+ phys_addr_t start = bd->bi_dram[i].start;
+
+ if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
+ start = virt_to_phys((void
*)(uintptr_t)bd->bi_dram[i].start);
+
pci_set_region(hose->regions + hose->region_count++,
- bd->bi_dram[i].start,
- bd->bi_dram[i].start,
- bd->bi_dram[i].size,
+ start, start, bd->bi_dram[i].size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
}
}
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
[PATCH 2/6] mmc: zynq_sdhci: Allow configuring zero Tap values
Allow configuring ITAP and OTAP values with zero to avoid failures in
some cases (one of them is SD boot mode). Legacy, SDR12 modes require
to program the ITAP and OTAP values as zero, whereas for SDR50 and SDR104
modes ITAP value is zero.
In SD boot mode firmware configures the SD ITAP and OTAP values and
in this case u-boot has to re-configure required tap values(including zero)
based on the operating mode.
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index cb785fd735..4f014da7ea 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -198,9 +198,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -253,9 +251,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -307,9 +303,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -370,9 +364,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
--
2.17.1
[PATCH 4/6] mmc: zynq_sdhci: Split set_tapdelay function to in and out
Split arasan_zynqmp_set_tapdelay() to handle input and output tapdelays
separately. This is required to handle zero values for ITAP and OTAP
values. If we dont split, we will have to remove the if() in the
function, which makes ITAP values to be overwritten when OTAP values are
called to set and vice-versa.
Restrict tap_delay value calculated to max allowed 8 bits for ITAP and 6
bits for OTAP for ZynqMP.
Signed-off-by: Ashok Reddy Soma
---
board/xilinx/zynqmp/tap_delays.c | 73 +---
drivers/mmc/zynq_sdhci.c | 10 -
include/zynqmp_tap_delay.h | 7 +--
3 files changed, 50 insertions(+), 40 deletions(-)
diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c
index 1cab25f00a..d16bbb8eff 100644
--- a/board/xilinx/zynqmp/tap_delays.c
+++ b/board/xilinx/zynqmp/tap_delays.c
@@ -50,48 +50,51 @@ void zynqmp_dll_reset(u8 deviceid)
zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
}
-void arasan_zynqmp_set_tapdelay(u8 deviceid, u32 itap_delay, u32 otap_delay)
+void arasan_zynqmp_set_in_tapdelay(u8 deviceid, u32 itap_delay)
{
if (deviceid == 0) {
- zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
- SD0_DLL_RST);
- /* Program ITAP */
- if (itap_delay) {
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
- SD0_ITAPCHGWIN);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
- SD0_ITAPDLYENA);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
- itap_delay);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
- 0x0);
- }
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, SD0_DLL_RST);
- /* Program OTAP */
- if (otap_delay)
- zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
- otap_delay);
+ /* Program ITAP delay */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+ SD0_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
+ SD0_ITAPDLYENA);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, itap_delay);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
} else {
- zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
- SD1_DLL_RST);
- /* Program ITAP */
- if (itap_delay) {
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
- SD1_ITAPCHGWIN);
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
- SD1_ITAPDLYENA);
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
- (itap_delay << 16));
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
- 0x0);
- }
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST);
+
+ /* Program ITAP delay */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+ SD1_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
+ SD1_ITAPDLYENA);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
+ (itap_delay << 16));
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
+
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+ }
+}
+
+void arasan_zynqmp_set_out_tapdelay(u8 deviceid, u32 otap_delay)
+{
+ if (deviceid == 0) {
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, SD0_DLL_RST);
+
+ /* Program OTAP delay */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, otap_delay);
+
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+ } else {
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST);
- /* Program OTAP */
- if (otap_delay)
- zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
- (otap_delay << 16));
+ /* Program OTAP delay */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ (otap_delay << 16));
zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
}
diff -
[PATCH 5/6] mmc: zynq_sdhci: Fix kernel doc warnings
From: Michal Simek
Fix these kernel doc warnings:
drivers/mmc/zynq_sdhci.c:181: warning: contents before sections
drivers/mmc/zynq_sdhci.c:187: warning: Function parameter or member 'degrees'
not described in 'sdhci_zynqmp_sdcardclk_set_phase'
drivers/mmc/zynq_sdhci.c:236: warning: contents before sections
drivers/mmc/zynq_sdhci.c:242: warning: Function parameter or member 'degrees'
not described in 'sdhci_zynqmp_sampleclk_set_phase'
drivers/mmc/zynq_sdhci.c:291: warning: contents before sections
drivers/mmc/zynq_sdhci.c:297: warning: Function parameter or member 'degrees'
not described in 'sdhci_versal_sdcardclk_set_phase'
drivers/mmc/zynq_sdhci.c:354: warning: contents before sections
drivers/mmc/zynq_sdhci.c:360: warning: Function parameter or member 'degrees'
not described in 'sdhci_versal_sampleclk_set_phase'
drivers/mmc/zynq_sdhci.c:467: warning: contents before sections
Signed-off-by: Michal Simek
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 926569f5d0..1e6efb1cd4 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -181,11 +181,11 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc,
u8 opcode)
/**
* sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
*
- * Set the SD Output Clock Tap Delays for Output path
- *
* @host: Pointer to the sdhci_host structure.
- * @degreesThe clock phase shift between 0 - 359.
+ * @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Output Clock Tap Delays for Output path
*/
static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -237,11 +237,11 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
/**
* sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
*
- * Set the SD Input Clock Tap Delays for Input path
- *
* @host: Pointer to the sdhci_host structure.
- * @degreesThe clock phase shift between 0 - 359.
+ * @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Input Clock Tap Delays for Input path
*/
static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -293,11 +293,11 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
/**
* sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
*
- * Set the SD Output Clock Tap Delays for Output path
- *
* @host: Pointer to the sdhci_host structure.
- * @degreesThe clock phase shift between 0 - 359.
+ * @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Output Clock Tap Delays for Output path
*/
static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -355,11 +355,11 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
/**
* sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
*
- * Set the SD Input Clock Tap Delays for Input path
- *
* @host: Pointer to the sdhci_host structure.
- * @degreesThe clock phase shift between 0 - 359.
+ * @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Input Clock Tap Delays for Input path
*/
static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -467,9 +467,9 @@ static void arasan_dt_read_clk_phase(struct udevice *dev,
unsigned char timing,
/**
* arasan_dt_parse_clk_phases - Read Tap Delay values from DT
*
- * Called at initialization to parse the values of Tap Delays.
- *
* @dev:Pointer to our struct udevice.
+ *
+ * Called at initialization to parse the values of Tap Delays.
*/
static void arasan_dt_parse_clk_phases(struct udevice *dev)
{
--
2.17.1
[PATCH 6/6] mmc: zynq_sdhci: Make variables/structure static
From: Michal Simek
All these variables/structure are local and should be static.
Issues are reported by sparse:
drivers/mmc/zynq_sdhci.c:49:11: warning: symbol 'zynqmp_iclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:50:11: warning: symbol 'zynqmp_oclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:53:11: warning: symbol 'versal_iclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:54:11: warning: symbol 'versal_oclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:546:24: warning: symbol 'arasan_ops' was not declared.
Should it be static?
Signed-off-by: Michal Simek
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 1e6efb1cd4..85a436b242 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -50,12 +50,16 @@ struct arasan_sdhci_priv {
#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
/* Default settings for ZynqMP Clock Phases */
-const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0};
-const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0};
+static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
+0, 183, 54, 0, 0};
+static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
+135, 48, 72, 135, 0};
/* Default settings for Versal Clock Phases */
-const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0};
-const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0};
+static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
+0, 0, 162, 90, 0, 0};
+static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
+90, 36, 60, 90, 0};
static const u8 mode2timing[] = {
[MMC_LEGACY] = MMC_TIMING_LEGACY,
@@ -541,8 +545,8 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host
*host)
sdhci_set_uhs_timing(host);
}
-const struct sdhci_ops arasan_ops = {
- .platform_execute_tuning = &arasan_sdhci_execute_tuning,
+static const struct sdhci_ops arasan_ops = {
+ .platform_execute_tuning= &arasan_sdhci_execute_tuning,
.set_delay = &arasan_sdhci_set_tapdelay,
.set_control_reg = &arasan_sdhci_set_control_reg,
};
--
2.17.1
[PATCH 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
set_phase() functions are not modifying the ret value and returning
the same uninitialized ret, return 0 instead.
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index b79c4021b6..cb785fd735 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -182,8 +182,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
* Set the SD Output Clock Tap Delays for Output path
*
* @host: Pointer to the sdhci_host structure.
- * @degrees: The clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * @degreesThe clock phase shift between 0 - 359.
+ * Return: 0
*/
static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -191,7 +191,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -229,7 +228,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
- return ret;
+ return 0;
}
/**
@@ -238,8 +237,8 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
* Set the SD Input Clock Tap Delays for Input path
*
* @host: Pointer to the sdhci_host structure.
- * @degrees: The clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * @degreesThe clock phase shift between 0 - 359.
+ * Return: 0
*/
static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -247,7 +246,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -285,7 +283,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
- return ret;
+ return 0;
}
/**
@@ -295,14 +293,13 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
*
* @host: Pointer to the sdhci_host structure.
* @degreesThe clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * Return: 0
*/
static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
{
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -349,7 +346,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
}
- return ret;
+ return 0;
}
/**
@@ -359,14 +356,13 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
*
* @host: Pointer to the sdhci_host structure.
* @degreesThe clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * Return: 0
*/
static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
{
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -417,7 +413,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
}
- return ret;
+ return 0;
}
static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
--
2.17.1
[PATCH 0/6] This patch set fixes minor issues related to tapdelays
This patch set fixes below issues in zynq_sdhc driver - Fix issues in tap delay functions where it returns uninitialized values - Allow configuring zero tap delay values - Split tapdelay functions to set input and output tap delay's separately. - Fix kernel doc warnings - Make local structures as static structures Ashok Reddy Soma (4): mmc: zynq_sdhci: Resolve uninitialized return value mmc: zynq_sdhci: Allow configuring zero Tap values mmc: zynq_sdhci: Use Mask writes for Tap delays mmc: zynq_sdhci: Split set_tapdelay function to in and out Michal Simek (2): mmc: zynq_sdhci: Fix kernel doc warnings mmc: zynq_sdhci: Make variables/structure static board/xilinx/zynqmp/tap_delays.c | 73 drivers/mmc/zynq_sdhci.c | 144 --- include/zynqmp_tap_delay.h | 7 +- 3 files changed, 115 insertions(+), 109 deletions(-) -- 2.17.1
[PATCH 3/6] mmc: zynq_sdhci: Use Mask writes for Tap delays
Restrict tap_delay value to the allowed size(8bits for itap and 6 bits
for otap) before writing to the tap delay register.
Clear ITAP and OTAP delay bits before updating with the new tap value
for Versal platform.
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 58 +---
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 4f014da7ea..c600d97f1e 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -19,11 +19,13 @@
#include
#include
-#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
-#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
-#define SDHCI_ITAPDLY_CHGWIN0x200
-#define SDHCI_ITAPDLY_ENABLE0x100
-#define SDHCI_OTAPDLY_ENABLE0x40
+#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
+#define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
+#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
+#define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
+#define SDHCI_ITAPDLY_CHGWIN 0x200
+#define SDHCI_ITAPDLY_ENABLE 0x100
+#define SDHCI_OTAPDLY_ENABLE 0x40
#define SDHCI_TUNING_LOOP_COUNT40
#define MMC_BANK2 0x2
@@ -297,6 +299,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
+ u32 regval;
/*
* This is applicable for SDHCI_SPEC_300 and above
@@ -329,16 +332,16 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
tap_delay = (degrees * tap_max) / 360;
+ /* Limit output tap_delay value to 6 bits */
+ tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
+
/* Set the Clock Phase */
- if (tap_delay) {
- u32 regval;
-
- regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
- regval |= SDHCI_OTAPDLY_ENABLE;
- sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
- regval |= tap_delay;
- sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
- }
+ regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
+ regval |= SDHCI_OTAPDLY_ENABLE;
+ sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
+ regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
+ regval |= tap_delay;
+ sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
return 0;
}
@@ -358,6 +361,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
+ u32 regval;
/*
* This is applicable for SDHCI_SPEC_300 and above
@@ -390,20 +394,20 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
tap_delay = (degrees * tap_max) / 360;
+ /* Limit input tap_delay value to 8 bits */
+ tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
+
/* Set the Clock Phase */
- if (tap_delay) {
- u32 regval;
-
- regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval |= SDHCI_ITAPDLY_CHGWIN;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval |= SDHCI_ITAPDLY_ENABLE;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval |= tap_delay;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval &= ~SDHCI_ITAPDLY_CHGWIN;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- }
+ regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval |= SDHCI_ITAPDLY_CHGWIN;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval |= SDHCI_ITAPDLY_ENABLE;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
+ regval |= tap_delay;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval &= ~SDHCI_ITAPDLY_CHGWIN;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
return 0;
}
--
2.17.1
[PATCH] stm32mp1: add pull-up for gpio button PA13 and PA14
When a push-button is released and PA13/PA14 are defined as input (high-Z)
the LED should not be active as the circuit is open but a small current
leak through PCB or push-button close the circuit and allows a small LED
bias giving erroneous level voltage.
So it is recommended to activate an internal pull-up in order to clearly
fix the voltage at PA13/PA14 when button is released and to wait
a short delay before to read the GPIO value only when the pull-up is
correctly configured.
Signed-off-by: Patrick Delaunay
---
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 4 ++--
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 4 ++--
board/st/stm32mp1/stm32mp1.c | 2 ++
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 6787619290..d44da7566f 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -18,8 +18,8 @@
u-boot,error-led = "error";
u-boot,mmc-env-partition = "ssbl";
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
- st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
- st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
+ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
};
firmware {
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index f3002e995b..3b94218b2f 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -18,8 +18,8 @@
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
u-boot,mmc-env-partition = "ssbl";
- st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
- st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
+ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW |
GPIO_PULL_UP)>;
};
firmware {
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 18b8870269..e1796e7e31 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -155,6 +155,7 @@ static void board_key_check(void)
&gpio, GPIOD_IS_IN)) {
log_debug("could not find a
/config/st,fastboot-gpios\n");
} else {
+ udelay(20);
if (dm_gpio_get_value(&gpio)) {
log_notice("Fastboot key pressed, ");
boot_mode = BOOT_FASTBOOT;
@@ -168,6 +169,7 @@ static void board_key_check(void)
&gpio, GPIOD_IS_IN)) {
log_debug("could not find a
/config/st,stm32prog-gpios\n");
} else {
+ udelay(20);
if (dm_gpio_get_value(&gpio)) {
log_notice("STM32Programmer key pressed, ");
boot_mode = BOOT_STM32PROG;
--
2.25.1
[PATCH] board: sifive: drop stuff related to unmatched revision 1
This patch reverts the following commits:
- 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1")
- ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board")
We won't plan to support unmatched that the revision below 3 in u-boot,
so they can be dropped because they might be useless.
Signed-off-by: Zong Li
Suggested-by: David Abdurachmanov
---
arch/riscv/dts/Makefile |2 +-
.../fu740-hifive-unmatched-a00-ddr-rev1.dtsi | 1489 -
.../dts/hifive-unmatched-a00-rev1-u-boot.dtsi |7 -
arch/riscv/dts/hifive-unmatched-a00-rev1.dts |4 -
board/sifive/unmatched/spl.c | 28 +-
configs/sifive_unmatched_defconfig|4 -
6 files changed, 3 insertions(+), 1531 deletions(-)
delete mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
delete mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index ba69894eb5..b6e9166767 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) +=
microchip-mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
-dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
hifive-unmatched-a00-rev1.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
deleted file mode 100644
index 0c4dedd166..00
--- a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
+++ /dev/null
@@ -1,1489 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * (C) Copyright 2020 SiFive, Inc
- */
-
-&dmc {
- sifive,ddr-params = <
- 0x0a00 /* DENALI_CTL_00_DATA */
- 0x /* DENALI_CTL_01_DATA */
- 0x /* DENALI_CTL_02_DATA */
- 0x /* DENALI_CTL_03_DATA */
- 0x /* DENALI_CTL_04_DATA */
- 0x /* DENALI_CTL_05_DATA */
- 0x000b /* DENALI_CTL_06_DATA */
- 0x00033f1e /* DENALI_CTL_07_DATA */
- 0x00081dcb /* DENALI_CTL_08_DATA */
- 0x0b200300 /* DENALI_CTL_09_DATA */
- 0x1c1c0400 /* DENALI_CTL_10_DATA */
- 0x04049a0d /* DENALI_CTL_11_DATA */
- 0x32060406 /* DENALI_CTL_12_DATA */
- 0x100d0823 /* DENALI_CTL_13_DATA */
- 0x080a0a17 /* DENALI_CTL_14_DATA */
- 0x0123b818 /* DENALI_CTL_15_DATA */
- 0x00180b06 /* DENALI_CTL_16_DATA */
- 0x00a01510 /* DENALI_CTL_17_DATA */
- 0x01000118 /* DENALI_CTL_18_DATA */
- 0x10032501 /* DENALI_CTL_19_DATA */
- 0x /* DENALI_CTL_20_DATA */
- 0x0101 /* DENALI_CTL_21_DATA */
- 0x /* DENALI_CTL_22_DATA */
- 0x0a00 /* DENALI_CTL_23_DATA */
- 0x /* DENALI_CTL_24_DATA */
- 0x01750100 /* DENALI_CTL_25_DATA */
- 0x2069 /* DENALI_CTL_26_DATA */
- 0x0005 /* DENALI_CTL_27_DATA */
- 0x001a0007 /* DENALI_CTL_28_DATA */
- 0x017f0300 /* DENALI_CTL_29_DATA */
- 0x0301 /* DENALI_CTL_30_DATA */
- 0x000b0f00 /* DENALI_CTL_31_DATA */
- 0x04030200 /* DENALI_CTL_32_DATA */
- 0x031f /* DENALI_CTL_33_DATA */
- 0x00070004 /* DENALI_CTL_34_DATA */
- 0x /* DENALI_CTL_35_DATA */
- 0x /* DENALI_CTL_36_DATA */
- 0x /* DENALI_CTL_37_DATA */
- 0x /* DENALI_CTL_38_DATA */
- 0x /* DENALI_CTL_39_DATA */
- 0x /* DENALI_CTL_40_DATA */
- 0x /* DENALI_CTL_41_DATA */
- 0x /* DENALI_CTL_42_DATA */
- 0x /* DENALI_CTL_43_DATA */
- 0x /* DENALI_CTL_44_DATA */
- 0x /* DENALI_CTL_45_DATA */
- 0x /* DENALI_CTL_46_DATA */
- 0x /* DENALI_CTL_47_DATA */
- 0x /* DENALI_CTL_48_DATA */
- 0x /* DENALI_CTL_49_DATA */
- 0x /* DENALI_CTL_50_DATA */
- 0x
[PATCH] board: sifive: remove the command for setting serial number
We wouldn't like to allow user to change the serial number, so remove
the command for changing serial number in EEPROM.
Signed-off-by: Zong Li
Suggested-by: David Abdurachmanov
---
.../unmatched/hifive-platform-i2c-eeprom.c| 23 +--
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
index a2151f15e0..ad2f3155d0 100644
--- a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
+++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
@@ -401,24 +401,6 @@ static void set_product_id(char *string)
update_crc();
}
-/**
- * set_serial_number() - set the PCB serial number in the in-memory copy
- *
- * Set the board serial number in the in-memory EEPROM copy from the supplied
- * string argument, and update the CRC.
- */
-static void set_serial_number(char *string)
-{
- if (strlen(string) > SERIAL_NUMBER_BYTES) {
- printf("Serial number must not be greater than 16 bytes\n");
- return;
- }
-
- memset(e.serial, 0, sizeof(e.serial));
- strncpy((char *)e.serial, string, sizeof(e.serial));
- update_crc();
-}
-
/**
* init_local_copy() - initialize the in-memory EEPROM copy
*
@@ -468,10 +450,7 @@ int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char
*const argv[])
return 0;
}
- if (!strcmp(cmd, "serial_number")) {
- set_serial_number(argv[2]);
- return 0;
- } else if (!strcmp(cmd, "manuf_test_status")) {
+ if (!strcmp(cmd, "manuf_test_status")) {
set_manuf_test_status(argv[2]);
return 0;
} else if (!strcmp(cmd, "mac_address")) {
--
2.31.1
Re: [PATCH v4 4/5] stm32mp1: spl: Configure TrustZone controller for OP-TEE
Hi, On 5/31/21 7:43 PM, Alexandru Gagniuc wrote: OP-TEE is very particular about how the TZC should be configured. When booting an OP-TEE payload, an incorrect TZC configuration will result in a panic. Most information can be derived from the SPL devicetree. The only information we don't have is the split between TZDRAM and shared memory. This has to be hardcoded. The rest of the configuration is fairly easy, and only requires 3 TZC regions. Configure them. Signed-off-by: Alexandru Gagniuc --- arch/arm/mach-stm32mp/spl.c | 92 + 1 file changed, 92 insertions(+) Reviewed-by: Patrick Delaunay Thanks Patrick
Re: [PATCH 1/4] mmc: arm_pl180_mmci: Don't bind to all arm,primecell devices
On 7/6/21 11:54 PM, Stephan Gerhold wrote:
> The arm,primecell compatible is used for lots of different types
> of devices, e.g. I2C, SPI, coresight, ... We really should not bind
> the MMC driver to all of them.
>
> Looking through the device trees in U-Boot there seems to be always
> a second compatible string for the pl180 device, either arm,pl180
> (already listed) or arm,pl18x. Add the "arm,pl18x" compatible to the
> list but remove the generic "arm,primecell".
>
> Note that on Linux these compatibles cannot be found in drivers
> because AMBA/primecell devices are matched based on their peripheral ID
> instead of the compatible.
>
> This fixes the following error messages when booting the ST-Ericsson
> U8500 "stemmy" board with the arm_pl180_mmci driver enabled:
>
> MMC: ptm@801ae000 - probe failed: -38
> ptm@801af000 - probe failed: -38
> funnel@801a6000 - probe failed: -38
> tpiu@8019 - probe failed: -38
> etb@801a4000 - probe failed: -38
>
> Cc: Patrice Chotard
> Fixes: 6f41d1a17e20 ("mmc: arm_pl180_mmci: Sync compatible with kernel")
> Signed-off-by: Stephan Gerhold
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
>
> drivers/mmc/arm_pl180_mmci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
> index b2d1b4f9aa..5d1ee64356 100644
> --- a/drivers/mmc/arm_pl180_mmci.c
> +++ b/drivers/mmc/arm_pl180_mmci.c
> @@ -539,7 +539,7 @@ static int arm_pl180_mmc_of_to_plat(struct udevice *dev)
>
> static const struct udevice_id arm_pl180_mmc_match[] = {
> { .compatible = "arm,pl180" },
> - { .compatible = "arm,primecell" },
> + { .compatible = "arm,pl18x" },
> { /* sentinel */ }
> };
>
>
Re: [PATCH 2/4] mmc: arm_pl180_mmci: Simplify code using dev_read_addr_ptr()
On 7/6/21 11:54 PM, Stephan Gerhold wrote:
> Simplify the code a bit by using dev_read_addr_ptr() instead of
> dev_read_addr(). This avoids having to cast explicitly to void*.
>
> Signed-off-by: Stephan Gerhold
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
>
> drivers/mmc/arm_pl180_mmci.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
> index 5d1ee64356..e632eed03f 100644
> --- a/drivers/mmc/arm_pl180_mmci.c
> +++ b/drivers/mmc/arm_pl180_mmci.c
> @@ -526,14 +526,11 @@ static const struct dm_mmc_ops arm_pl180_dm_mmc_ops = {
> static int arm_pl180_mmc_of_to_plat(struct udevice *dev)
> {
> struct pl180_mmc_host *host = dev_get_priv(dev);
> - fdt_addr_t addr;
>
> - addr = dev_read_addr(dev);
> - if (addr == FDT_ADDR_T_NONE)
> + host->base = dev_read_addr_ptr(dev);
> + if (!host->base)
> return -EINVAL;
>
> - host->base = (void *)addr;
> -
> return 0;
> }
>
>
Re: [PATCH 3/4] mmc: arm_pl180_mmci: Simplify code using mmc_of_parse()
On 7/6/21 11:54 PM, Stephan Gerhold wrote:
> Simplify the code a bit by using the common mmc_of_parse() function
> instead of duplicating the device tree parsing code. We can still get
> a default value for cfg->f_max by assigning it before calling
> mmc_of_parse().
>
> Another advantage of this refactoring is that we parse more properties
> now, e.g. "non-removable" can be used to disable CD entirely.
>
> Signed-off-by: Stephan Gerhold
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
>
> drivers/mmc/arm_pl180_mmci.c | 19 ---
> 1 file changed, 4 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
> index e632eed03f..809b86570a 100644
> --- a/drivers/mmc/arm_pl180_mmci.c
> +++ b/drivers/mmc/arm_pl180_mmci.c
> @@ -424,7 +424,6 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
> struct pl180_mmc_host *host = dev_get_priv(dev);
> struct mmc_config *cfg = &pdata->cfg;
> struct clk clk;
> - u32 bus_width;
> u32 periphid;
> int ret;
>
> @@ -457,24 +456,14 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
> cfg->voltages = VOLTAGE_WINDOW_SD;
> cfg->host_caps = 0;
> cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
> - cfg->f_max = dev_read_u32_default(dev, "max-frequency", MMC_CLOCK_MAX);
> + cfg->f_max = MMC_CLOCK_MAX;
> cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
>
> gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
>
> - bus_width = dev_read_u32_default(dev, "bus-width", 1);
> - switch (bus_width) {
> - case 8:
> - cfg->host_caps |= MMC_MODE_8BIT;
> - /* Hosts capable of 8-bit transfers can also do 4 bits */
> - case 4:
> - cfg->host_caps |= MMC_MODE_4BIT;
> - break;
> - case 1:
> - break;
> - default:
> - dev_err(dev, "Invalid bus-width value %u\n", bus_width);
> - }
> + ret = mmc_of_parse(dev, cfg);
> + if (ret)
> + return ret;
>
> arm_pl180_mmc_init(host);
> mmc->priv = host;
>
Re: [PATCH 4/4] mmc: arm_pl180_mmci: Add configuration for ST-Ericsson Ux500v2
On 7/6/21 11:54 PM, Stephan Gerhold wrote:
> For the eMMC on ST-Ericsson Ux500v2 we need slightly different
> configuration values. Use the existing switch statement to match
> the peripheral ID of Ux500v2 (0x10480180) and override the necessary
> values to make the eMMC work on devices with ST-Ericsson Ux500.
>
> Cc: Linus Walleij
> Signed-off-by: Stephan Gerhold
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
>
> drivers/mmc/arm_pl180_mmci.c | 22 +++---
> drivers/mmc/arm_pl180_mmci.h | 1 +
> 2 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
> index 809b86570a..f99b5f997e 100644
> --- a/drivers/mmc/arm_pl180_mmci.c
> +++ b/drivers/mmc/arm_pl180_mmci.c
> @@ -443,22 +443,30 @@ static int arm_pl180_mmc_probe(struct udevice *dev)
> SDI_CLKCR_HWFC_EN;
> host->clock_in = clk_get_rate(&clk);
>
> + cfg->name = dev->name;
> + cfg->voltages = VOLTAGE_WINDOW_SD;
> + cfg->host_caps = 0;
> + cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
> + cfg->f_max = MMC_CLOCK_MAX;
> + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
> +
> periphid = dev_read_u32_default(dev, "arm,primecell-periphid", 0);
> switch (periphid) {
> case STM32_MMCI_ID: /* stm32 variant */
> host->version2 = false;
> break;
> + case UX500V2_MMCI_ID:
> + host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
> + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | SDI_CLKCR_CLKEN |
> + SDI_CLKCR_HWFC_EN;
> + cfg->voltages = VOLTAGE_WINDOW_MMC;
> + cfg->f_min = host->clock_in / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
> + host->version2 = true;
> + break;
> default:
> host->version2 = true;
> }
>
> - cfg->name = dev->name;
> - cfg->voltages = VOLTAGE_WINDOW_SD;
> - cfg->host_caps = 0;
> - cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
> - cfg->f_max = MMC_CLOCK_MAX;
> - cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
> -
> gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
>
> ret = mmc_of_parse(dev, cfg);
> diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h
> index 61ee96a112..15c29beadb 100644
> --- a/drivers/mmc/arm_pl180_mmci.h
> +++ b/drivers/mmc/arm_pl180_mmci.h
> @@ -142,6 +142,7 @@
> #define SDI_FIFO_BURST_SIZE 8
>
> #define STM32_MMCI_ID0x00880180
> +#define UX500V2_MMCI_ID 0x10480180
>
> struct sdi_registers {
> u32 power; /* 0x00*/
>
Re: [PATCH 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
Hi Ashok,
On 7/9/21 4:17 PM, Ashok Reddy Soma wrote:
> set_phase() functions are not modifying the ret value and returning
> the same uninitialized ret, return 0 instead.
Why didn't you change from int to void?
Best Regards,
Jaehoon Chung
>
> Signed-off-by: Ashok Reddy Soma
> ---
>
> drivers/mmc/zynq_sdhci.c | 24 ++--
> 1 file changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index b79c4021b6..cb785fd735 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -182,8 +182,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc,
> u8 opcode)
> * Set the SD Output Clock Tap Delays for Output path
> *
> * @host:Pointer to the sdhci_host structure.
> - * @degrees: The clock phase shift between 0 - 359.
> - * Return: 0 on success and error value on error
> + * @degrees The clock phase shift between 0 - 359.
> + * Return: 0
> */
> static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
> int degrees)
> @@ -191,7 +191,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> - int ret;
> int timing = mode2timing[mmc->selected_mode];
>
> /*
> @@ -229,7 +228,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
>
> arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
>
> - return ret;
> + return 0;
> }
>
> /**
> @@ -238,8 +237,8 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
> * Set the SD Input Clock Tap Delays for Input path
> *
> * @host:Pointer to the sdhci_host structure.
> - * @degrees: The clock phase shift between 0 - 359.
> - * Return: 0 on success and error value on error
> + * @degrees The clock phase shift between 0 - 359.
> + * Return: 0
> */
> static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
> int degrees)
> @@ -247,7 +246,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> sdhci_host *host,
> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> - int ret;
> int timing = mode2timing[mmc->selected_mode];
>
> /*
> @@ -285,7 +283,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> sdhci_host *host,
>
> arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
>
> - return ret;
> + return 0;
> }
>
> /**
> @@ -295,14 +293,13 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> sdhci_host *host,
> *
> * @host:Pointer to the sdhci_host structure.
> * @degrees The clock phase shift between 0 - 359.
> - * Return: 0 on success and error value on error
> + * Return: 0
> */
> static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
> int degrees)
> {
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> - int ret;
> int timing = mode2timing[mmc->selected_mode];
>
> /*
> @@ -349,7 +346,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
> }
>
> - return ret;
> + return 0;
> }
>
> /**
> @@ -359,14 +356,13 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> *
> * @host:Pointer to the sdhci_host structure.
> * @degrees The clock phase shift between 0 - 359.
> - * Return: 0 on success and error value on error
> + * Return: 0
> */
> static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
> int degrees)
> {
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> - int ret;
> int timing = mode2timing[mmc->selected_mode];
>
> /*
> @@ -417,7 +413,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
> sdhci_host *host,
> sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> }
>
> - return ret;
> + return 0;
> }
>
> static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
>
Re: [PATCH 5/6] mmc: zynq_sdhci: Fix kernel doc warnings
Hi Ashok,
On 7/9/21 4:17 PM, Ashok Reddy Soma wrote:
> From: Michal Simek
>
> Fix these kernel doc warnings:
> drivers/mmc/zynq_sdhci.c:181: warning: contents before sections
> drivers/mmc/zynq_sdhci.c:187: warning: Function parameter or member 'degrees'
> not described in 'sdhci_zynqmp_sdcardclk_set_phase'
> drivers/mmc/zynq_sdhci.c:236: warning: contents before sections
> drivers/mmc/zynq_sdhci.c:242: warning: Function parameter or member 'degrees'
> not described in 'sdhci_zynqmp_sampleclk_set_phase'
> drivers/mmc/zynq_sdhci.c:291: warning: contents before sections
> drivers/mmc/zynq_sdhci.c:297: warning: Function parameter or member 'degrees'
> not described in 'sdhci_versal_sdcardclk_set_phase'
> drivers/mmc/zynq_sdhci.c:354: warning: contents before sections
> drivers/mmc/zynq_sdhci.c:360: warning: Function parameter or member 'degrees'
> not described in 'sdhci_versal_sampleclk_set_phase'
> drivers/mmc/zynq_sdhci.c:467: warning: contents before sections
I didn't understand this patch. You are changing from "@degrees:" to "@degree"
on [PATCH 1/6].
But reverted them in this patch.
Best Regards,
Jaehoon Chung
>
> Signed-off-by: Michal Simek
> Signed-off-by: Ashok Reddy Soma
> ---
>
> drivers/mmc/zynq_sdhci.c | 28 ++--
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index 926569f5d0..1e6efb1cd4 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -181,11 +181,11 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc,
> u8 opcode)
> /**
> * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
> *
> - * Set the SD Output Clock Tap Delays for Output path
> - *
> * @host:Pointer to the sdhci_host structure.
> - * @degrees The clock phase shift between 0 - 359.
> + * @degrees: The clock phase shift between 0 - 359.
> * Return: 0
> + *
> + * Set the SD Output Clock Tap Delays for Output path
> */
> static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
> int degrees)
> @@ -237,11 +237,11 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
> /**
> * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
> *
> - * Set the SD Input Clock Tap Delays for Input path
> - *
> * @host:Pointer to the sdhci_host structure.
> - * @degrees The clock phase shift between 0 - 359.
> + * @degrees: The clock phase shift between 0 - 359.
> * Return: 0
> + *
> + * Set the SD Input Clock Tap Delays for Input path
> */
> static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
> int degrees)
> @@ -293,11 +293,11 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> sdhci_host *host,
> /**
> * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
> *
> - * Set the SD Output Clock Tap Delays for Output path
> - *
> * @host:Pointer to the sdhci_host structure.
> - * @degrees The clock phase shift between 0 - 359.
> + * @degrees: The clock phase shift between 0 - 359.
> * Return: 0
> + *
> + * Set the SD Output Clock Tap Delays for Output path
> */
> static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
> int degrees)
> @@ -355,11 +355,11 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> /**
> * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
> *
> - * Set the SD Input Clock Tap Delays for Input path
> - *
> * @host:Pointer to the sdhci_host structure.
> - * @degrees The clock phase shift between 0 - 359.
> + * @degrees: The clock phase shift between 0 - 359.
> * Return: 0
> + *
> + * Set the SD Input Clock Tap Delays for Input path
> */
> static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
> int degrees)
> @@ -467,9 +467,9 @@ static void arasan_dt_read_clk_phase(struct udevice *dev,
> unsigned char timing,
> /**
> * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
> *
> - * Called at initialization to parse the values of Tap Delays.
> - *
> * @dev:Pointer to our struct udevice.
> + *
> + * Called at initialization to parse the values of Tap Delays.
> */
> static void arasan_dt_parse_clk_phases(struct udevice *dev)
> {
>
Re: [PATCH] arm: stm32mp1: force boot_device variable for invalid TAMP register value
Hi Patrick
On 7/8/21 10:53 AM, Patrick Delaunay wrote:
> When the TAMP register 20 have an invalid value (0x0 for example after
> TAMPER error) the "boot_device" U-Boot env variable have no value and
> no error is displayed in U-Boot log.
>
> The STM32MP boot command bootcmd_stm32mp failed with strange trace:
> "Boot over !"
>
> and the next command in bootcmd_stm32mp failed with few indication:
> if test ${boot_device} = serial || test ${boot_device} = usb;
> then stm32prog ${boot_device} ${boot_instance};
>
> As it is difficult to investigate, the current patch avoids this issue:
> - change the debug message to error: "unexpected boot mode" is displayed
> - display trace "Boot over invalid!" in bootcmd_stm32mp
> - execute "run distro_bootcmd" to try all the possible target
>
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/mach-stm32mp/cpu.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
> index 592bfd413d..5ea1ddc497 100644
> --- a/arch/arm/mach-stm32mp/cpu.c
> +++ b/arch/arm/mach-stm32mp/cpu.c
> @@ -542,7 +542,9 @@ static void setup_boot_mode(void)
> env_set("boot_instance", "0");
> break;
> default:
> - log_debug("unexpected boot mode = %x\n", boot_mode);
> + env_set("boot_device", "invalid");
> + env_set("boot_instance", "");
> + log_err("unexpected boot mode = %x\n", boot_mode);
> break;
> }
>
>
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages
On Fri, Jul 09, 2021 at 09:05:09AM +0200, François Ozog wrote: > Le ven. 9 juil. 2021 à 03:09, Julius Werner a écrit : > > > > Of course every project would like not to change... > > > > > > For TF-A I wonder whether it will/should in fact use devicetree if there > > is a lot of complex data? TBD, I suppose. > > > > Okay, sorry, now I'm a bit confused -- I thought the discussion in > > this thread was about which parameter hand-off mechanism to use *for > > TF-A*? Or did it shift to discuss other projects in the meantime (I > > didn't always follow it closely)? I think it started with the UEFI > > guys wanting to implement a HOB format to interface with TF-A, and I > > think we now concluded that they're okay with using a simple parameter > > list instead (and wrapping their custom HOBs into a parameter blob > > that contains their UUID and everything else in the data part). > > > > So for TF-A, if the decision is that we want a parameter list, I think > > it makes sense to keep using the format that has already been there > > and in use for several years, and define new tags for the UEFI HOB use > > case in that. I don't really see a reason to switch TF-A and all other > > projects currently interfacing with it that way (e.g. coreboot) to > > something only used by U-Boot right now, if they're practically > > identical in concept. > > Looking at bl_au_params: used by 3 SoCs to deal with gpio and serial. I presume this analysis only covers those SoCs where someone (vendor, customer, community) has upstreamed their TF-A implementation? It is only relatively recently[1] that the TF-A CLA requirements that inhibited upstreaming were relaxed. Additionally the current silicon supply crunch is forcing board designers to second (third and forth) source critical components which can drive usage of firmware parameter passing. In short are you confident adopting a mantra of "it doesn't exist unless it's upstreamed" is sufficient? Daniel. [1] Perhaps not that recent if measured in years... but certainly recent relative to firmware life cycles! > Migration may not be that a big effort (handful lines of code?). The > key thing is that the biggest consumer of them are BL33 and a little > bit by some OS drivers (OS itself shall not be a consumer). U-Boot > has an established mechanism which is used in particular on all chrome > books in both x86 and Arm environments. I have the impression that > U-Boot is the typical BL33 so I would import the mechanism into TFA, > not the other way round. EDK2 has typically its own code for TFA > matters and may just import BL31, so it does not appear a priority in > that decision. But I may be wrong… > > > > > -- > François-Frédéric Ozog | *Director Business Development* T: > +33.67221.6485 francois.o...@linaro.org | Skype: ffozog > ___ boot-architecture > mailing list boot-architect...@lists.linaro.org > https://lists.linaro.org/mailman/listinfo/boot-architecture
RE: [PATCH 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
Hi Jaehoon,
> -Original Message-
> From: Jaehoon Chung
> Sent: Friday, July 9, 2021 3:08 PM
> To: Ashok Reddy Soma ; u-boot@lists.denx.de
> Cc: peng@nxp.com; git ; mon...@monstr.eu;
> somaashokre...@gmail.com
> Subject: Re: [PATCH 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
>
> Hi Ashok,
>
> On 7/9/21 4:17 PM, Ashok Reddy Soma wrote:
> > set_phase() functions are not modifying the ret value and returning
> > the same uninitialized ret, return 0 instead.
>
> Why didn't you change from int to void?
>
We are planning to change the way tapdelay's are set to use firmware function
xilinx_pm_request() in place of arasan_zynqmp_set_out_tapdelay().
This return type int is a provision for that.
Thanks,
Ashok
> Best Regards,
> Jaehoon Chung
>
>
> >
> > Signed-off-by: Ashok Reddy Soma
> > ---
> >
> > drivers/mmc/zynq_sdhci.c | 24 ++--
> > 1 file changed, 10 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index
> > b79c4021b6..cb785fd735 100644
> > --- a/drivers/mmc/zynq_sdhci.c
> > +++ b/drivers/mmc/zynq_sdhci.c
> > @@ -182,8 +182,8 @@ static int arasan_sdhci_execute_tuning(struct mmc
> *mmc, u8 opcode)
> > * Set the SD Output Clock Tap Delays for Output path
> > *
> > * @host: Pointer to the sdhci_host structure.
> > - * @degrees: The clock phase shift between 0 - 359.
> > - * Return: 0 on success and error value on error
> > + * @degreesThe clock phase shift between 0 - 359.
> > + * Return: 0
> > */
> > static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
> > int degrees)
> > @@ -191,7 +191,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
> > struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > - int ret;
> > int timing = mode2timing[mmc->selected_mode];
> >
> > /*
> > @@ -229,7 +228,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> > sdhci_host *host,
> >
> > arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
> >
> > - return ret;
> > + return 0;
> > }
> >
> > /**
> > @@ -238,8 +237,8 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
> > * Set the SD Input Clock Tap Delays for Input path
> > *
> > * @host: Pointer to the sdhci_host structure.
> > - * @degrees: The clock phase shift between 0 - 359.
> > - * Return: 0 on success and error value on error
> > + * @degreesThe clock phase shift between 0 - 359.
> > + * Return: 0
> > */
> > static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
> > int degrees)
> > @@ -247,7 +246,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> sdhci_host *host,
> > struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > - int ret;
> > int timing = mode2timing[mmc->selected_mode];
> >
> > /*
> > @@ -285,7 +283,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> > sdhci_host *host,
> >
> > arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
> >
> > - return ret;
> > + return 0;
> > }
> >
> > /**
> > @@ -295,14 +293,13 @@ static int
> sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
> > *
> > * @host: Pointer to the sdhci_host structure.
> > * @degreesThe clock phase shift between 0 - 359.
> > - * Return: 0 on success and error value on error
> > + * Return: 0
> > */
> > static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
> > int degrees)
> > {
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > - int ret;
> > int timing = mode2timing[mmc->selected_mode];
> >
> > /*
> > @@ -349,7 +346,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> > sdhci_writel(host, regval,
> SDHCI_ARASAN_OTAPDLY_REGISTER);
> > }
> >
> > - return ret;
> > + return 0;
> > }
> >
> > /**
> > @@ -359,14 +356,13 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> > *
> > * @host: Pointer to the sdhci_host structure.
> > * @degreesThe clock phase shift between 0 - 359.
> > - * Return: 0 on success and error value on error
> > + * Return: 0
> > */
> > static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
> > int degrees)
> > {
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > - int ret;
> > int timing = mode2timing[mmc->selected_mode];
> >
> > /*
> > @@ -417,7 +413,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
> sdhci_
RE: [PATCH 5/6] mmc: zynq_sdhci: Fix kernel doc warnings
Hi Jaehoon, > -Original Message- > From: Jaehoon Chung > Sent: Friday, July 9, 2021 3:12 PM > To: Ashok Reddy Soma ; u-boot@lists.denx.de > Cc: peng@nxp.com; git ; mon...@monstr.eu; > somaashokre...@gmail.com; Michal Simek > Subject: Re: [PATCH 5/6] mmc: zynq_sdhci: Fix kernel doc warnings > > Hi Ashok, > > On 7/9/21 4:17 PM, Ashok Reddy Soma wrote: > > From: Michal Simek > > > > Fix these kernel doc warnings: > > drivers/mmc/zynq_sdhci.c:181: warning: contents before sections > > drivers/mmc/zynq_sdhci.c:187: warning: Function parameter or member > 'degrees' not described in 'sdhci_zynqmp_sdcardclk_set_phase' > > drivers/mmc/zynq_sdhci.c:236: warning: contents before sections > > drivers/mmc/zynq_sdhci.c:242: warning: Function parameter or member > 'degrees' not described in 'sdhci_zynqmp_sampleclk_set_phase' > > drivers/mmc/zynq_sdhci.c:291: warning: contents before sections > > drivers/mmc/zynq_sdhci.c:297: warning: Function parameter or member > 'degrees' not described in 'sdhci_versal_sdcardclk_set_phase' > > drivers/mmc/zynq_sdhci.c:354: warning: contents before sections > > drivers/mmc/zynq_sdhci.c:360: warning: Function parameter or member > 'degrees' not described in 'sdhci_versal_sampleclk_set_phase' > > drivers/mmc/zynq_sdhci.c:467: warning: contents before sections > > I didn't understand this patch. You are changing from "@degrees:" to > "@degree" on [PATCH 1/6]. > But reverted them in this patch. I made a mistake in patch 1/6, Michal corrected it in this patch. I will correct/move this change to 1/6 and send V2. Thanks, Ashok > > Best Regards, > Jaehoon Chung > > > > > > Signed-off-by: Michal Simek > > Signed-off-by: Ashok Reddy Soma > > --- > > > > drivers/mmc/zynq_sdhci.c | 28 ++-- > > 1 file changed, 14 insertions(+), 14 deletions(-) > > > > diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index > > 926569f5d0..1e6efb1cd4 100644 > > --- a/drivers/mmc/zynq_sdhci.c > > +++ b/drivers/mmc/zynq_sdhci.c > > @@ -181,11 +181,11 @@ static int arasan_sdhci_execute_tuning(struct > > mmc *mmc, u8 opcode) > > /** > > * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays > > * > > - * Set the SD Output Clock Tap Delays for Output path > > - * > > * @host: Pointer to the sdhci_host structure. > > - * @degreesThe clock phase shift between 0 - 359. > > + * @degrees: The clock phase shift between 0 - 359. > > * Return: 0 > > + * > > + * Set the SD Output Clock Tap Delays for Output path > > */ > > static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host, > > int degrees) > > @@ -237,11 +237,11 @@ static int > > sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host, > > /** > > * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays > > * > > - * Set the SD Input Clock Tap Delays for Input path > > - * > > * @host: Pointer to the sdhci_host structure. > > - * @degreesThe clock phase shift between 0 - 359. > > + * @degrees: The clock phase shift between 0 - 359. > > * Return: 0 > > + * > > + * Set the SD Input Clock Tap Delays for Input path > > */ > > static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host, > > int degrees) > > @@ -293,11 +293,11 @@ static int > > sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host, > > /** > > * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays > > * > > - * Set the SD Output Clock Tap Delays for Output path > > - * > > * @host: Pointer to the sdhci_host structure. > > - * @degreesThe clock phase shift between 0 - 359. > > + * @degrees: The clock phase shift between 0 - 359. > > * Return: 0 > > + * > > + * Set the SD Output Clock Tap Delays for Output path > > */ > > static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host, > > int degrees) > > @@ -355,11 +355,11 @@ static int > > sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host, > > /** > > * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays > > * > > - * Set the SD Input Clock Tap Delays for Input path > > - * > > * @host: Pointer to the sdhci_host structure. > > - * @degreesThe clock phase shift between 0 - 359. > > + * @degrees: The clock phase shift between 0 - 359. > > * Return: 0 > > + * > > + * Set the SD Input Clock Tap Delays for Input path > > */ > > static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host, > > int degrees) > > @@ -467,9 +467,9 @@ static void arasan_dt_read_clk_phase(struct > > udevice *dev, unsigned char timing, > > /** > > * arasan_dt_parse_clk_phases - Read Tap Delay values from DT > > * > > - * Called at initialization to parse the
Re: [PATCH v2 0/6] net: dwc_eth_qos: add support of device tree configuration for reset delay
Hi Ramon, On 4/26/21 5:46 PM, Patrick Delaunay wrote: It is the V2 version of [1] after Marek remarks: all commit are new. I change the DWC_ETH_QOS STM32 variant by using generic eth phy driver. This driver is updated to use the gpio reset and assert/deassert delay from DT with the generic binding defined in linux: Documentation/devicetree/bindings/net/ethernet-phy.yaml or in U-Boot: doc/device-tree-bindings/net/phy.txt [1] net: dwc_eth_qos: add support of device tree configuration for reset delay http://patchwork.ozlabs.org/project/uboot/list/?series=238253&state=* Changes in v2: - Update eth-phy driver (NEW) - use log macro in eth-phy driver (NEW) - update eth-phy driver to support STM32 binding with a mdio0 subnode (NEW) - remove unused element in the struct eqos_priv (NEW) - use generic ethernet phy for stm32 variant, this patch is a REWORK of previous serie: the device parsing is done in eth-phy driver and the gpio support is removed in stm32 variant: eqos_start/stop_resets_stm32 and eqos_probe_resources_stm32. - cleanup ops by adding a common null ops (NEW) Patrick Delaunay (6): net: eth-phy: add support of device tree configuration for gpio reset net: eth-phy: use dev_dbg and log_notice net: eth-phy: manage subnode mdio0 net: dwc_eth_qos: remove the field phyaddr of the struct eqos_priv net: dwc_eth_qos: use generic ethernet phy for stm32 variant net: dwc: add a common empty ops eqos_null_ops drivers/net/Kconfig | 1 + drivers/net/dwc_eth_qos.c| 152 +-- drivers/net/eth-phy-uclass.c | 78 +++--- 3 files changed, 91 insertions(+), 140 deletions(-) This serie is also accepted in patchwork, but not merged in u-boot-net/network_master: http://patchwork.ozlabs.org/project/uboot/list/?series=240808&state=* Do you plan to integrate it in you next pull request for v2021.10 ? Regards Patrick
[PATCH] efi_loader: replace board_get_usable_ram_top by gd->ram_top
As gd->ram_top = board_get_usable_ram_top() in board_r
the EFI loader don't need to call this function again and after relocation.
This patch avoid issue if board assumed that this function is called
only one time and before relocation.
Signed-off-by: Patrick Delaunay
---
https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/7399
lib/efi_loader/efi_memory.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index be2f655dff..f5bc37a20a 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -7,7 +7,6 @@
#include
#include
-#include
#include
#include
#include
@@ -731,7 +730,7 @@ efi_status_t efi_add_conventional_memory_map(u64 ram_start,
u64 ram_end,
__weak void efi_add_known_memory(void)
{
- u64 ram_top = board_get_usable_ram_top(0) & ~EFI_PAGE_MASK;
+ u64 ram_top = gd->ram_top & ~EFI_PAGE_MASK;
int i;
/*
--
2.25.1
[PATCH v2 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
set_phase() functions are not modifying the ret value and returning
the same uninitialized ret, return 0 instead.
Signed-off-by: Ashok Reddy Soma
---
Changes in v2:
- Changed "@degree" to "@degrees:" in function descriptions of tap
delay functions
drivers/mmc/zynq_sdhci.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index b79c4021b6..03600188ba 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -183,7 +183,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
*
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * Return: 0
*/
static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -191,7 +191,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -229,7 +228,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
- return ret;
+ return 0;
}
/**
@@ -239,7 +238,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
*
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * Return: 0
*/
static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -247,7 +246,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -285,7 +283,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
- return ret;
+ return 0;
}
/**
@@ -294,15 +292,14 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
* Set the SD Output Clock Tap Delays for Output path
*
* @host: Pointer to the sdhci_host structure.
- * @degreesThe clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * @degrees: The clock phase shift between 0 - 359.
+ * Return: 0
*/
static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
{
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -349,7 +346,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
}
- return ret;
+ return 0;
}
/**
@@ -358,15 +355,14 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
* Set the SD Input Clock Tap Delays for Input path
*
* @host: Pointer to the sdhci_host structure.
- * @degreesThe clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * @degrees: The clock phase shift between 0 - 359.
+ * Return: 0
*/
static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
{
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -417,7 +413,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
}
- return ret;
+ return 0;
}
static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
--
2.17.1
[PATCH v2 5/6] mmc: zynq_sdhci: Fix kernel doc warnings
From: Michal Simek
Fix these kernel doc warnings:
drivers/mmc/zynq_sdhci.c:181: warning: contents before sections
drivers/mmc/zynq_sdhci.c:236: warning: contents before sections
drivers/mmc/zynq_sdhci.c:291: warning: contents before sections
drivers/mmc/zynq_sdhci.c:354: warning: contents before sections
drivers/mmc/zynq_sdhci.c:467: warning: contents before sections
Signed-off-by: Michal Simek
Signed-off-by: Ashok Reddy Soma
---
Changes in v2:
- Removed @degree warning from commit description since it is fixed in
patch 1/6.
drivers/mmc/zynq_sdhci.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index dd06b56838..1e6efb1cd4 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -181,11 +181,11 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc,
u8 opcode)
/**
* sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
*
- * Set the SD Output Clock Tap Delays for Output path
- *
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Output Clock Tap Delays for Output path
*/
static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -237,11 +237,11 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
/**
* sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
*
- * Set the SD Input Clock Tap Delays for Input path
- *
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Input Clock Tap Delays for Input path
*/
static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -293,11 +293,11 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
/**
* sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
*
- * Set the SD Output Clock Tap Delays for Output path
- *
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Output Clock Tap Delays for Output path
*/
static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -355,11 +355,11 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
/**
* sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
*
- * Set the SD Input Clock Tap Delays for Input path
- *
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Input Clock Tap Delays for Input path
*/
static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -467,9 +467,9 @@ static void arasan_dt_read_clk_phase(struct udevice *dev,
unsigned char timing,
/**
* arasan_dt_parse_clk_phases - Read Tap Delay values from DT
*
- * Called at initialization to parse the values of Tap Delays.
- *
* @dev:Pointer to our struct udevice.
+ *
+ * Called at initialization to parse the values of Tap Delays.
*/
static void arasan_dt_parse_clk_phases(struct udevice *dev)
{
--
2.17.1
[PATCH v2 2/6] mmc: zynq_sdhci: Allow configuring zero Tap values
Allow configuring ITAP and OTAP values with zero to avoid failures in
some cases (one of them is SD boot mode). Legacy, SDR12 modes require
to program the ITAP and OTAP values as zero, whereas for SDR50 and SDR104
modes ITAP value is zero.
In SD boot mode firmware configures the SD ITAP and OTAP values and
in this case u-boot has to re-configure required tap values(including zero)
based on the operating mode.
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
drivers/mmc/zynq_sdhci.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 03600188ba..b229c24a8b 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -198,9 +198,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -253,9 +251,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -307,9 +303,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -370,9 +364,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
--
2.17.1
[PATCH v2 0/6] This patch set fixes minor issues related to tapdelays
This patch set fixes below issues in zynq_sdhc driver - Fix issues in tap delay functions where it returns uninitialized values - Allow configuring zero tap delay values - Split tapdelay functions to set input and output tap delay's separately. - Fix kernel doc warnings - Make local structures as static structures Changes in v2: - Changed "@degree" to "@degrees:" in function descriptions of tap delay functions - Removed @degree warning from commit description since it is fixed in patch 1/6. Ashok Reddy Soma (4): mmc: zynq_sdhci: Resolve uninitialized return value mmc: zynq_sdhci: Allow configuring zero Tap values mmc: zynq_sdhci: Use Mask writes for Tap delays mmc: zynq_sdhci: Split set_tapdelay function to in and out Michal Simek (2): mmc: zynq_sdhci: Fix kernel doc warnings mmc: zynq_sdhci: Make variables/structure static board/xilinx/zynqmp/tap_delays.c | 73 drivers/mmc/zynq_sdhci.c | 144 --- include/zynqmp_tap_delay.h | 7 +- 3 files changed, 115 insertions(+), 109 deletions(-) -- 2.17.1
[PATCH v2 3/6] mmc: zynq_sdhci: Use Mask writes for Tap delays
Restrict tap_delay value to the allowed size(8bits for itap and 6 bits
for otap) before writing to the tap delay register.
Clear ITAP and OTAP delay bits before updating with the new tap value
for Versal platform.
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
drivers/mmc/zynq_sdhci.c | 58 +---
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index b229c24a8b..44eb982b9a 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -19,11 +19,13 @@
#include
#include
-#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
-#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
-#define SDHCI_ITAPDLY_CHGWIN0x200
-#define SDHCI_ITAPDLY_ENABLE0x100
-#define SDHCI_OTAPDLY_ENABLE0x40
+#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
+#define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
+#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
+#define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
+#define SDHCI_ITAPDLY_CHGWIN 0x200
+#define SDHCI_ITAPDLY_ENABLE 0x100
+#define SDHCI_OTAPDLY_ENABLE 0x40
#define SDHCI_TUNING_LOOP_COUNT40
#define MMC_BANK2 0x2
@@ -297,6 +299,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
+ u32 regval;
/*
* This is applicable for SDHCI_SPEC_300 and above
@@ -329,16 +332,16 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
tap_delay = (degrees * tap_max) / 360;
+ /* Limit output tap_delay value to 6 bits */
+ tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
+
/* Set the Clock Phase */
- if (tap_delay) {
- u32 regval;
-
- regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
- regval |= SDHCI_OTAPDLY_ENABLE;
- sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
- regval |= tap_delay;
- sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
- }
+ regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
+ regval |= SDHCI_OTAPDLY_ENABLE;
+ sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
+ regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
+ regval |= tap_delay;
+ sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
return 0;
}
@@ -358,6 +361,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
+ u32 regval;
/*
* This is applicable for SDHCI_SPEC_300 and above
@@ -390,20 +394,20 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
tap_delay = (degrees * tap_max) / 360;
+ /* Limit input tap_delay value to 8 bits */
+ tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
+
/* Set the Clock Phase */
- if (tap_delay) {
- u32 regval;
-
- regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval |= SDHCI_ITAPDLY_CHGWIN;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval |= SDHCI_ITAPDLY_ENABLE;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval |= tap_delay;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval &= ~SDHCI_ITAPDLY_CHGWIN;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- }
+ regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval |= SDHCI_ITAPDLY_CHGWIN;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval |= SDHCI_ITAPDLY_ENABLE;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
+ regval |= tap_delay;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval &= ~SDHCI_ITAPDLY_CHGWIN;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
return 0;
}
--
2.17.1
[PATCH v2 6/6] mmc: zynq_sdhci: Make variables/structure static
From: Michal Simek
All these variables/structure are local and should be static.
Issues are reported by sparse:
drivers/mmc/zynq_sdhci.c:49:11: warning: symbol 'zynqmp_iclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:50:11: warning: symbol 'zynqmp_oclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:53:11: warning: symbol 'versal_iclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:54:11: warning: symbol 'versal_oclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:546:24: warning: symbol 'arasan_ops' was not declared.
Should it be static?
Signed-off-by: Michal Simek
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
drivers/mmc/zynq_sdhci.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 1e6efb1cd4..85a436b242 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -50,12 +50,16 @@ struct arasan_sdhci_priv {
#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
/* Default settings for ZynqMP Clock Phases */
-const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0};
-const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0};
+static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
+0, 183, 54, 0, 0};
+static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
+135, 48, 72, 135, 0};
/* Default settings for Versal Clock Phases */
-const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0};
-const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0};
+static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
+0, 0, 162, 90, 0, 0};
+static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
+90, 36, 60, 90, 0};
static const u8 mode2timing[] = {
[MMC_LEGACY] = MMC_TIMING_LEGACY,
@@ -541,8 +545,8 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host
*host)
sdhci_set_uhs_timing(host);
}
-const struct sdhci_ops arasan_ops = {
- .platform_execute_tuning = &arasan_sdhci_execute_tuning,
+static const struct sdhci_ops arasan_ops = {
+ .platform_execute_tuning= &arasan_sdhci_execute_tuning,
.set_delay = &arasan_sdhci_set_tapdelay,
.set_control_reg = &arasan_sdhci_set_control_reg,
};
--
2.17.1
[PATCH v2 4/6] mmc: zynq_sdhci: Split set_tapdelay function to in and out
Split arasan_zynqmp_set_tapdelay() to handle input and output tapdelays
separately. This is required to handle zero values for ITAP and OTAP
values. If we dont split, we will have to remove the if() in the
function, which makes ITAP values to be overwritten when OTAP values are
called to set and vice-versa.
Restrict tap_delay value calculated to max allowed 8 bits for ITAP and 6
bits for OTAP for ZynqMP.
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
board/xilinx/zynqmp/tap_delays.c | 73 +---
drivers/mmc/zynq_sdhci.c | 10 -
include/zynqmp_tap_delay.h | 7 +--
3 files changed, 50 insertions(+), 40 deletions(-)
diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c
index 1cab25f00a..d16bbb8eff 100644
--- a/board/xilinx/zynqmp/tap_delays.c
+++ b/board/xilinx/zynqmp/tap_delays.c
@@ -50,48 +50,51 @@ void zynqmp_dll_reset(u8 deviceid)
zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
}
-void arasan_zynqmp_set_tapdelay(u8 deviceid, u32 itap_delay, u32 otap_delay)
+void arasan_zynqmp_set_in_tapdelay(u8 deviceid, u32 itap_delay)
{
if (deviceid == 0) {
- zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
- SD0_DLL_RST);
- /* Program ITAP */
- if (itap_delay) {
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
- SD0_ITAPCHGWIN);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
- SD0_ITAPDLYENA);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
- itap_delay);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
- 0x0);
- }
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, SD0_DLL_RST);
- /* Program OTAP */
- if (otap_delay)
- zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
- otap_delay);
+ /* Program ITAP delay */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+ SD0_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
+ SD0_ITAPDLYENA);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, itap_delay);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
} else {
- zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
- SD1_DLL_RST);
- /* Program ITAP */
- if (itap_delay) {
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
- SD1_ITAPCHGWIN);
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
- SD1_ITAPDLYENA);
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
- (itap_delay << 16));
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
- 0x0);
- }
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST);
+
+ /* Program ITAP delay */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+ SD1_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
+ SD1_ITAPDLYENA);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
+ (itap_delay << 16));
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
+
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+ }
+}
+
+void arasan_zynqmp_set_out_tapdelay(u8 deviceid, u32 otap_delay)
+{
+ if (deviceid == 0) {
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, SD0_DLL_RST);
+
+ /* Program OTAP delay */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, otap_delay);
+
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+ } else {
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST);
- /* Program OTAP */
- if (otap_delay)
- zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
- (otap_delay << 16));
+ /* Program OTAP delay */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ (otap_delay << 16));
zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
Re: [PATCH 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
Hi Ashok,
On 7/9/21 7:15 PM, Ashok Reddy Soma wrote:
> Hi Jaehoon,
>
>> -Original Message-
>> From: Jaehoon Chung
>> Sent: Friday, July 9, 2021 3:08 PM
>> To: Ashok Reddy Soma ; u-boot@lists.denx.de
>> Cc: peng@nxp.com; git ; mon...@monstr.eu;
>> somaashokre...@gmail.com
>> Subject: Re: [PATCH 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
>>
>> Hi Ashok,
>>
>> On 7/9/21 4:17 PM, Ashok Reddy Soma wrote:
>>> set_phase() functions are not modifying the ret value and returning
>>> the same uninitialized ret, return 0 instead.
>>
>> Why didn't you change from int to void?
>>
>
> We are planning to change the way tapdelay's are set to use firmware function
> xilinx_pm_request() in place of arasan_zynqmp_set_out_tapdelay().
> This return type int is a provision for that.
Thanks for kindly explanation.
Could you add the brief comment about that in commit-msg? Then It will be
clarified more than now.
Because there is no mentioned why keep to int type.
Other things look good to me.
Best Regards,
Jaehoon Chung
>
> Thanks,
> Ashok
>
>> Best Regards,
>> Jaehoon Chung
>>
>>
>>>
>>> Signed-off-by: Ashok Reddy Soma
>>> ---
>>>
>>> drivers/mmc/zynq_sdhci.c | 24 ++--
>>> 1 file changed, 10 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index
>>> b79c4021b6..cb785fd735 100644
>>> --- a/drivers/mmc/zynq_sdhci.c
>>> +++ b/drivers/mmc/zynq_sdhci.c
>>> @@ -182,8 +182,8 @@ static int arasan_sdhci_execute_tuning(struct mmc
>> *mmc, u8 opcode)
>>> * Set the SD Output Clock Tap Delays for Output path
>>> *
>>> * @host: Pointer to the sdhci_host structure.
>>> - * @degrees: The clock phase shift between 0 - 359.
>>> - * Return: 0 on success and error value on error
>>> + * @degreesThe clock phase shift between 0 - 359.
>>> + * Return: 0
>>> */
>>> static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
>>> int degrees)
>>> @@ -191,7 +191,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
>> sdhci_host *host,
>>> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
>>> struct mmc *mmc = (struct mmc *)host->mmc;
>>> u8 tap_delay, tap_max = 0;
>>> - int ret;
>>> int timing = mode2timing[mmc->selected_mode];
>>>
>>> /*
>>> @@ -229,7 +228,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
>>> sdhci_host *host,
>>>
>>> arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
>>>
>>> - return ret;
>>> + return 0;
>>> }
>>>
>>> /**
>>> @@ -238,8 +237,8 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
>> sdhci_host *host,
>>> * Set the SD Input Clock Tap Delays for Input path
>>> *
>>> * @host: Pointer to the sdhci_host structure.
>>> - * @degrees: The clock phase shift between 0 - 359.
>>> - * Return: 0 on success and error value on error
>>> + * @degreesThe clock phase shift between 0 - 359.
>>> + * Return: 0
>>> */
>>> static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
>>> int degrees)
>>> @@ -247,7 +246,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
>> sdhci_host *host,
>>> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
>>> struct mmc *mmc = (struct mmc *)host->mmc;
>>> u8 tap_delay, tap_max = 0;
>>> - int ret;
>>> int timing = mode2timing[mmc->selected_mode];
>>>
>>> /*
>>> @@ -285,7 +283,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
>>> sdhci_host *host,
>>>
>>> arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
>>>
>>> - return ret;
>>> + return 0;
>>> }
>>>
>>> /**
>>> @@ -295,14 +293,13 @@ static int
>> sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
>>> *
>>> * @host: Pointer to the sdhci_host structure.
>>> * @degreesThe clock phase shift between 0 - 359.
>>> - * Return: 0 on success and error value on error
>>> + * Return: 0
>>> */
>>> static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
>>> int degrees)
>>> {
>>> struct mmc *mmc = (struct mmc *)host->mmc;
>>> u8 tap_delay, tap_max = 0;
>>> - int ret;
>>> int timing = mode2timing[mmc->selected_mode];
>>>
>>> /*
>>> @@ -349,7 +346,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
>> sdhci_host *host,
>>> sdhci_writel(host, regval,
>> SDHCI_ARASAN_OTAPDLY_REGISTER);
>>> }
>>>
>>> - return ret;
>>> + return 0;
>>> }
>>>
>>> /**
>>> @@ -359,14 +356,13 @@ static int sdhci_versal_sdcardclk_set_phase(struct
>> sdhci_host *host,
>>> *
>>> * @host: Pointer to the sdhci_host structure.
>>> * @degreesThe clock phase shift between 0 - 359.
>>> - * Return: 0 on success and error value on error
>>> + * Return: 0
>>> */
>>> static int sdhci_versal_sampleclk_set_phase(struc
[PATCH 0/6] arm64: synquacer: DeveloperBox updates
Hi, Here is the series of patches to update the DeveloperBox support. [1/6] board: synquacer: Initialize SCBM SMMU at board_init() - This is a driver cleanup, split the SMMU setup from the driver. [2/6] configs: synquacer: Make U-Boot binary position independent - This makes U-Boot position independent for usability. [3/6] dts: synquacer: Add partition information to the spi-nor [4/6] configs: synquacer: Remove mtdparts settings and update DFU setting - These are the fixes according to the MTD subsystem update. (Thanks Marek!) [5/6] configs: synquacer: Drop Ext2/4 support by default [6/6] configs: synquacer: Enable UEFI secure boot - These are making U-Boot more likely to EDK2 behaviors. Thank you, --- Masami Hiramatsu (6): board: synquacer: Initialize SCBM SMMU at board_init() configs: synquacer: Make U-Boot binary position independent dts: synquacer: Add partition information to the spi-nor configs: synquacer: Remove mtdparts settings and update DFU setting configs: synquacer: Drop Ext2/4 support by default configs: synquacer: Enable UEFI secure boot .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 42 board/socionext/developerbox/developerbox.c| 15 +++ configs/synquacer_developerbox_defconfig |9 ++-- drivers/net/sni_netsec.c |7 --- include/configs/synquacer.h|2 - 5 files changed, 62 insertions(+), 13 deletions(-) -- Masami Hiramatsu
[PATCH 1/6] board: synquacer: Initialize SCBM SMMU at board_init()
Since the SCBM SMMU is not only connected to the NETSEC
but also shared with the F_SDH30 (eMMC controller), that
should be initialized at board level instead of NETSEC.
Move the SMMU initialization code into board support
and call it from board_init().
Without this fix, if the NETSEC is disabled, the Linux
eMMC ADMA cause an error because SMMU is not initialized.
Signed-off-by: Masami Hiramatsu
---
board/socionext/developerbox/developerbox.c | 15 +++
drivers/net/sni_netsec.c|7 ---
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/board/socionext/developerbox/developerbox.c
b/board/socionext/developerbox/developerbox.c
index 34335baec3..9552bfcdc3 100644
--- a/board/socionext/developerbox/developerbox.c
+++ b/board/socionext/developerbox/developerbox.c
@@ -62,6 +62,19 @@ DECLARE_GLOBAL_DATA_PTR;
#define LOAD_OFFSET 0x100
+/* SCBM System MMU is used for eMMC and NETSEC */
+#define SCBM_SMMU_ADDR (0x52e0UL)
+#define SMMU_SCR0_OFFS (0x0)
+#define SMMU_SCR0_SHCFG_INNER (0x2 << 22)
+#define SMMU_SCR0_MTCFG(0x1 << 20)
+#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16)
+
+static void synquacer_setup_scbm_smmu(void)
+{
+ writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG |
SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
+ SCBM_SMMU_ADDR + SMMU_SCR0_OFFS);
+}
+
/*
* Miscellaneous platform dependent initialisations
*/
@@ -71,6 +84,8 @@ int board_init(void)
gd->env_addr = (ulong)&default_environment[0];
+ synquacer_setup_scbm_smmu();
+
return 0;
}
diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c
index a9ebf6af9c..4901321d0c 100644
--- a/drivers/net/sni_netsec.c
+++ b/drivers/net/sni_netsec.c
@@ -1059,18 +1059,11 @@ static int netsec_of_to_plat(struct udevice *dev)
return 0;
}
-#define SMMU_SCR0_SHCFG_INNER (0x2 << 22)
-#define SMMU_SCR0_MTCFG (0x1 << 20)
-#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16)
-
static int netsec_probe(struct udevice *dev)
{
struct netsec_priv *priv = dev_get_priv(dev);
int ret;
- writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG |
SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
- (phys_addr_t)0x52E0);
-
netsec_reset_hardware(priv, true);
ret = netsec_mdiobus_init(priv, dev->name);
[PATCH 2/6] configs: synquacer: Make U-Boot binary position independent
Make the U-Boot bianry for SynQuacer position independent so that the previous bootloader (SCP firmware or BL2) can load the U-Boot anywhere. Signed-off-by: Masami Hiramatsu --- configs/synquacer_developerbox_defconfig |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index d42db9a1d6..fe30f0169f 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -1,11 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SYNQUACER=y -CONFIG_SYS_TEXT_BASE=0x0820 +CONFIG_SYS_TEXT_BASE=0x CONFIG_ENV_SIZE=0x3 CONFIG_ENV_OFFSET=0x30 CONFIG_DEBUG_UART_BASE=0x2a40 CONFIG_DEBUG_UART_CLOCK=6250 CONFIG_ENV_SECT_SIZE=0x1 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_INIT_SP_RELATIVE=y CONFIG_DM_GPIO=y CONFIG_TARGET_DEVELOPERBOX=y CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
[PATCH 3/6] dts: synquacer: Add partition information to the spi-nor
Add partition information to the spi-nor flash.
This is required for accessing NOR flash via mtdparts.
Signed-off-by: Masami Hiramatsu
---
.../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 42
1 file changed, 42 insertions(+)
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
index 2f13a42235..245ebcda01 100644
--- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -31,6 +31,48 @@
spi-max-frequency = <3125>;
spi-rx-bus-width = <0x1>;
spi-tx-bus-width = <0x1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "BootStrap-BL1";
+ reg = <0x0 0x7>;
+ read-only;
+ };
+ partition@7 {
+ label = "Flash-Writer";
+ reg = <0x7 0x9>;
+ read-only;
+ };
+ partition@10 {
+ label = "SCP-BL2";
+ reg = <0x10 0x8>;
+ read-only;
+ };
+ partition@18 {
+ label = "FIP-TFA";
+ reg = <0x18 0x78000>;
+ };
+ partition@1f8000 {
+ label = "Stage2Tables";
+ reg = <0x1f8000 0x8000>;
+ };
+ partition@20 {
+ label = "U-Boot";
+ reg = <0x20 0x10>;
+ };
+ partition@30 {
+ label = "UBoot-Env";
+ reg = <0x30 0x10>;
+ };
+ partition@50 {
+ label = "Ex-OPTEE";
+ reg = <0x50 0x20>;
+ };
+ };
};
};
[PATCH 4/6] configs: synquacer: Remove mtdparts settings and update DFU setting
Since MTD partitions are based on the devicetree name, remove unneeded mtdparts settings and update DFU setting. Signed-off-by: Masami Hiramatsu --- configs/synquacer_developerbox_defconfig |2 -- include/configs/synquacer.h |2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index fe30f0169f..bea13be874 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -45,8 +45,6 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y -CONFIG_MTDPARTS_DEFAULT="nor1:448k(BootStrap-BL1),576k(Flash-Writer),512k(SCP-BL2),480k(FIP-TFA),32k(Stg2-Tables),1m@2m(U-Boot),1m@3m(UBoot-Env),2m@5m(Ex-OPTEE)" -CONFIG_MTDIDS_DEFAULT="nor1=nor1" CONFIG_CMD_LOG=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_EFI_PARTITION=y diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 8fe10d7485..4503cf3f6d 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -62,7 +62,7 @@ /* #define CONFIG_SYS_PCI_64BIT1 */ #define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ - "mtd nor1=u-boot.bin raw 20 10;"\ + "mtd mx66u51235f=u-boot.bin raw 20 10;" \ "fip.bin raw 18 78000;" \ "optee.bin raw 50 10\0"
[PATCH 5/6] configs: synquacer: Drop Ext2/4 support by default
Since the U-Boot for the SynQuacer DeveloperBox is designed for compatible with EDK2 boot, we don't need to support Ext2/4 fs support by default. Drop it. Signed-off-by: Masami Hiramatsu --- configs/synquacer_developerbox_defconfig |2 -- 1 file changed, 2 deletions(-) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index bea13be874..208c939412 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -41,8 +41,6 @@ CONFIG_CMD_SATA=y CONFIG_CMD_NVME=y CONFIG_CMD_USB=y CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y
[PATCH 6/6] configs: synquacer: Enable UEFI secure boot
Enable UEFI secure boot on synquacer. Note that unless user setup their keys, the secure boot will not work. Signed-off-by: Masami Hiramatsu --- configs/synquacer_developerbox_defconfig |1 + 1 file changed, 1 insertion(+) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 208c939412..fba8fa2deb 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -115,6 +115,7 @@ CONFIG_EFI_CAPSULE_FIRMWARE=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y CONFIG_EFI_CAPSULE_FMP_HEADER=y +CONFIG_EFI_SECURE_BOOT=y CONFIG_FLASH_CFI_MTD=y CONFIG_CMD_DFU=y CONFIG_DFU_TFTP=y
Re: [PATCH 2/6] configs: synquacer: Make U-Boot binary position independent
On Fri, 9 Jul 2021 19:50:18 +0900 Masami Hiramatsu wrote: > Make the U-Boot bianry for SynQuacer position independent so *binary
Re: [PATCH 3/6] dts: synquacer: Add partition information to the spi-nor
On Fri, 9 Jul 2021 19:50:27 +0900
Masami Hiramatsu wrote:
> Add partition information to the spi-nor flash.
> This is required for accessing NOR flash via mtdparts.
>
> Signed-off-by: Masami Hiramatsu
> ---
> .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 42
> 1 file changed, 42 insertions(+)
>
> diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
> b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi index
> 2f13a42235..245ebcda01 100644 ---
> a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi +++
> b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -31,6
> +31,48 @@ spi-max-frequency = <3125>;
> spi-rx-bus-width = <0x1>;
> spi-tx-bus-width = <0x1>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "BootStrap-BL1";
> + reg = <0x0 0x7>;
> + read-only;
> + };
> + partition@7 {
> + label = "Flash-Writer";
> + reg = <0x7 0x9>;
> + read-only;
> + };
> + partition@10 {
> + label = "SCP-BL2";
> + reg = <0x10 0x8>;
> + read-only;
> + };
> + partition@18 {
> + label = "FIP-TFA";
> + reg = <0x18 0x78000>;
> + };
> + partition@1f8000 {
> + label = "Stage2Tables";
> + reg = <0x1f8000 0x8000>;
> + };
> + partition@20 {
> + label = "U-Boot";
> + reg = <0x20 0x10>;
> + };
> + partition@30 {
> + label = "UBoot-Env";
> + reg = <0x30 0x10>;
> + };
> + partition@50 {
> + label = "Ex-OPTEE";
> + reg = <0x50 0x20>;
> + };
> + };
> };
> };
>
>
Just a style hint: the individual partition nodes should be IMO
separated by an additional newline character, i.e.:
partition@0 {
label = "BootStrap-BL1";
reg = <0x0 0x7>;
read-only;
};
partition@7 {
label = "Flash-Writer";
reg = <0x7 0x9>;
read-only;
};
partition@10 {
label = "SCP-BL2";
reg = <0x10 0x8>;
read-only;
};
Other than that:
Reviewed-by: Marek Behún
Btw, did you test this? Does this work correctly with mtd command?
RE: [PATCH 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
Hi Jaehoon,
> -Original Message-
> From: Jaehoon Chung
> Sent: Friday, July 9, 2021 4:21 PM
> To: Ashok Reddy Soma ; u-boot@lists.denx.de
> Cc: peng@nxp.com; git ; mon...@monstr.eu;
> somaashokre...@gmail.com
> Subject: Re: [PATCH 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
>
> Hi Ashok,
>
> On 7/9/21 7:15 PM, Ashok Reddy Soma wrote:
> > Hi Jaehoon,
> >
> >> -Original Message-
> >> From: Jaehoon Chung
> >> Sent: Friday, July 9, 2021 3:08 PM
> >> To: Ashok Reddy Soma ; u-boot@lists.denx.de
> >> Cc: peng@nxp.com; git ; mon...@monstr.eu;
> >> somaashokre...@gmail.com
> >> Subject: Re: [PATCH 1/6] mmc: zynq_sdhci: Resolve uninitialized
> >> return value
> >>
> >> Hi Ashok,
> >>
> >> On 7/9/21 4:17 PM, Ashok Reddy Soma wrote:
> >>> set_phase() functions are not modifying the ret value and returning
> >>> the same uninitialized ret, return 0 instead.
> >>
> >> Why didn't you change from int to void?
> >>
> >
> > We are planning to change the way tapdelay's are set to use firmware
> function xilinx_pm_request() in place of arasan_zynqmp_set_out_tapdelay().
> > This return type int is a provision for that.
>
> Thanks for kindly explanation.
>
> Could you add the brief comment about that in commit-msg? Then It will be
> clarified more than now.
> Because there is no mentioned why keep to int type.
> Other things look good to me.
>
Thanks for the review !!
I will update it in the commit message and send v3.
Thanks,
Ashok
> Best Regards,
> Jaehoon Chung
>
> >
> > Thanks,
> > Ashok
> >
> >> Best Regards,
> >> Jaehoon Chung
> >>
> >>
> >>>
> >>> Signed-off-by: Ashok Reddy Soma
> >>> ---
> >>>
> >>> drivers/mmc/zynq_sdhci.c | 24 ++--
> >>> 1 file changed, 10 insertions(+), 14 deletions(-)
> >>>
> >>> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> >>> index
> >>> b79c4021b6..cb785fd735 100644
> >>> --- a/drivers/mmc/zynq_sdhci.c
> >>> +++ b/drivers/mmc/zynq_sdhci.c
> >>> @@ -182,8 +182,8 @@ static int arasan_sdhci_execute_tuning(struct
> >>> mmc
> >> *mmc, u8 opcode)
> >>> * Set the SD Output Clock Tap Delays for Output path
> >>> *
> >>> * @host:Pointer to the sdhci_host structure.
> >>> - * @degrees: The clock phase shift between 0 - 359.
> >>> - * Return: 0 on success and error value on error
> >>> + * @degrees The clock phase shift between 0 - 359.
> >>> + * Return: 0
> >>> */
> >>> static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
> >>> int degrees)
> >>> @@ -191,7 +191,6 @@ static int
> >>> sdhci_zynqmp_sdcardclk_set_phase(struct
> >> sdhci_host *host,
> >>> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> >>> struct mmc *mmc = (struct mmc *)host->mmc;
> >>> u8 tap_delay, tap_max = 0;
> >>> - int ret;
> >>> int timing = mode2timing[mmc->selected_mode];
> >>>
> >>> /*
> >>> @@ -229,7 +228,7 @@ static int
> >>> sdhci_zynqmp_sdcardclk_set_phase(struct
> >>> sdhci_host *host,
> >>>
> >>> arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
> >>>
> >>> - return ret;
> >>> + return 0;
> >>> }
> >>>
> >>> /**
> >>> @@ -238,8 +237,8 @@ static int
> >>> sdhci_zynqmp_sdcardclk_set_phase(struct
> >> sdhci_host *host,
> >>> * Set the SD Input Clock Tap Delays for Input path
> >>> *
> >>> * @host:Pointer to the sdhci_host structure.
> >>> - * @degrees: The clock phase shift between 0 - 359.
> >>> - * Return: 0 on success and error value on error
> >>> + * @degrees The clock phase shift between 0 - 359.
> >>> + * Return: 0
> >>> */
> >>> static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
> >>> int degrees)
> >>> @@ -247,7 +246,6 @@ static int
> >>> sdhci_zynqmp_sampleclk_set_phase(struct
> >> sdhci_host *host,
> >>> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> >>> struct mmc *mmc = (struct mmc *)host->mmc;
> >>> u8 tap_delay, tap_max = 0;
> >>> - int ret;
> >>> int timing = mode2timing[mmc->selected_mode];
> >>>
> >>> /*
> >>> @@ -285,7 +283,7 @@ static int
> >>> sdhci_zynqmp_sampleclk_set_phase(struct
> >>> sdhci_host *host,
> >>>
> >>> arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
> >>>
> >>> - return ret;
> >>> + return 0;
> >>> }
> >>>
> >>> /**
> >>> @@ -295,14 +293,13 @@ static int
> >> sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
> >>> *
> >>> * @host:Pointer to the sdhci_host structure.
> >>> * @degrees The clock phase shift between 0 - 359.
> >>> - * Return: 0 on success and error value on error
> >>> + * Return: 0
> >>> */
> >>> static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
> >>> int degrees)
> >>> {
> >>> struct mmc *mmc = (struct mmc *)host->mmc;
> >>> u8 tap_delay, tap_max = 0;
> >>> - int ret;
> >>> int timing = mode2ti
Re: [PATCH v2 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
On 7/9/21 12:46 PM, Ashok Reddy Soma wrote:
> set_phase() functions are not modifying the ret value and returning
> the same uninitialized ret, return 0 instead.
>
> Signed-off-by: Ashok Reddy Soma
> ---
>
> Changes in v2:
> - Changed "@degree" to "@degrees:" in function descriptions of tap
>delay functions
>
> drivers/mmc/zynq_sdhci.c | 24 ++--
> 1 file changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index b79c4021b6..03600188ba 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -183,7 +183,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc,
> u8 opcode)
> *
> * @host:Pointer to the sdhci_host structure.
> * @degrees: The clock phase shift between 0 - 359.
> - * Return: 0 on success and error value on error
> + * Return: 0
> */
> static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
> int degrees)
> @@ -191,7 +191,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> - int ret;
> int timing = mode2timing[mmc->selected_mode];
>
> /*
> @@ -229,7 +228,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
>
> arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
>
> - return ret;
> + return 0;
> }
>
> /**
> @@ -239,7 +238,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
> *
> * @host:Pointer to the sdhci_host structure.
> * @degrees: The clock phase shift between 0 - 359.
> - * Return: 0 on success and error value on error
> + * Return: 0
> */
> static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
> int degrees)
> @@ -247,7 +246,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> sdhci_host *host,
> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> - int ret;
> int timing = mode2timing[mmc->selected_mode];
>
> /*
> @@ -285,7 +283,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> sdhci_host *host,
>
> arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
>
> - return ret;
> + return 0;
> }
>
> /**
> @@ -294,15 +292,14 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> sdhci_host *host,
> * Set the SD Output Clock Tap Delays for Output path
> *
> * @host:Pointer to the sdhci_host structure.
> - * @degrees The clock phase shift between 0 - 359.
> - * Return: 0 on success and error value on error
> + * @degrees: The clock phase shift between 0 - 359.
this should be also the part of 5/6
> + * Return: 0
> */
> static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
> int degrees)
> {
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> - int ret;
> int timing = mode2timing[mmc->selected_mode];
>
> /*
> @@ -349,7 +346,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
> }
>
> - return ret;
> + return 0;
> }
>
> /**
> @@ -358,15 +355,14 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> * Set the SD Input Clock Tap Delays for Input path
> *
> * @host:Pointer to the sdhci_host structure.
> - * @degrees The clock phase shift between 0 - 359.
> - * Return: 0 on success and error value on error
> + * @degrees: The clock phase shift between 0 - 359.
this should be also the part of 5/6
> + * Return: 0
> */
> static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
> int degrees)
> {
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> - int ret;
> int timing = mode2timing[mmc->selected_mode];
>
> /*
> @@ -417,7 +413,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
> sdhci_host *host,
> sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> }
>
> - return ret;
> + return 0;
> }
>
> static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
>
M
Re: [PATCH v2 3/6] mmc: zynq_sdhci: Use Mask writes for Tap delays
On 7/9/21 12:47 PM, Ashok Reddy Soma wrote:
> Restrict tap_delay value to the allowed size(8bits for itap and 6 bits
> for otap) before writing to the tap delay register.
>
> Clear ITAP and OTAP delay bits before updating with the new tap value
> for Versal platform.
>
> Signed-off-by: Ashok Reddy Soma
> ---
>
> (no changes since v1)
>
> drivers/mmc/zynq_sdhci.c | 58 +---
> 1 file changed, 31 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index b229c24a8b..44eb982b9a 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -19,11 +19,13 @@
> #include
> #include
>
> -#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
> -#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
> -#define SDHCI_ITAPDLY_CHGWIN0x200
> -#define SDHCI_ITAPDLY_ENABLE0x100
> -#define SDHCI_OTAPDLY_ENABLE0x40
> +#define SDHCI_ARASAN_ITAPDLY_REGISTER0xF0F8
> +#define SDHCI_ARASAN_ITAPDLY_SEL_MASK0xFF
> +#define SDHCI_ARASAN_OTAPDLY_REGISTER0xF0FC
> +#define SDHCI_ARASAN_OTAPDLY_SEL_MASK0x3F
> +#define SDHCI_ITAPDLY_CHGWIN 0x200
> +#define SDHCI_ITAPDLY_ENABLE 0x100
> +#define SDHCI_OTAPDLY_ENABLE 0x40
when you are touching this maybe better to use BIT and GENMASK macros.
>
> #define SDHCI_TUNING_LOOP_COUNT 40
> #define MMC_BANK20x2
> @@ -297,6 +299,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> int timing = mode2timing[mmc->selected_mode];
> + u32 regval;
>
> /*
>* This is applicable for SDHCI_SPEC_300 and above
> @@ -329,16 +332,16 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
>
> tap_delay = (degrees * tap_max) / 360;
>
> + /* Limit output tap_delay value to 6 bits */
> + tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
> +
> /* Set the Clock Phase */
> - if (tap_delay) {
> - u32 regval;
> -
> - regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
> - regval |= SDHCI_OTAPDLY_ENABLE;
> - sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
> - regval |= tap_delay;
> - sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
> - }
> + regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
> + regval |= SDHCI_OTAPDLY_ENABLE;
> + sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
> + regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
> + regval |= tap_delay;
> + sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
>
> return 0;
> }
> @@ -358,6 +361,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
> sdhci_host *host,
> struct mmc *mmc = (struct mmc *)host->mmc;
> u8 tap_delay, tap_max = 0;
> int timing = mode2timing[mmc->selected_mode];
> + u32 regval;
>
> /*
>* This is applicable for SDHCI_SPEC_300 and above
> @@ -390,20 +394,20 @@ static int sdhci_versal_sampleclk_set_phase(struct
> sdhci_host *host,
>
> tap_delay = (degrees * tap_max) / 360;
>
> + /* Limit input tap_delay value to 8 bits */
> + tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
> +
> /* Set the Clock Phase */
> - if (tap_delay) {
> - u32 regval;
> -
> - regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
> - regval |= SDHCI_ITAPDLY_CHGWIN;
> - sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> - regval |= SDHCI_ITAPDLY_ENABLE;
> - sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> - regval |= tap_delay;
> - sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> - regval &= ~SDHCI_ITAPDLY_CHGWIN;
> - sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> - }
> + regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
> + regval |= SDHCI_ITAPDLY_CHGWIN;
> + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> + regval |= SDHCI_ITAPDLY_ENABLE;
> + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> + regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
> + regval |= tap_delay;
> + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> + regval &= ~SDHCI_ITAPDLY_CHGWIN;
> + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
>
> return 0;
> }
>
M
RE: [PATCH v2 3/6] mmc: zynq_sdhci: Use Mask writes for Tap delays
HI Michal,
> -Original Message-
> From: Michal Simek
> Sent: Friday, July 9, 2021 4:37 PM
> To: Ashok Reddy Soma ; u-boot@lists.denx.de
> Cc: peng@nxp.com; jh80.ch...@samsung.com; git ;
> mon...@monstr.eu; somaashokre...@gmail.com
> Subject: Re: [PATCH v2 3/6] mmc: zynq_sdhci: Use Mask writes for Tap delays
>
>
>
> On 7/9/21 12:47 PM, Ashok Reddy Soma wrote:
> > Restrict tap_delay value to the allowed size(8bits for itap and 6 bits
> > for otap) before writing to the tap delay register.
> >
> > Clear ITAP and OTAP delay bits before updating with the new tap value
> > for Versal platform.
> >
> > Signed-off-by: Ashok Reddy Soma
> > ---
> >
> > (no changes since v1)
> >
> > drivers/mmc/zynq_sdhci.c | 58
> > +---
> > 1 file changed, 31 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index
> > b229c24a8b..44eb982b9a 100644
> > --- a/drivers/mmc/zynq_sdhci.c
> > +++ b/drivers/mmc/zynq_sdhci.c
> > @@ -19,11 +19,13 @@
> > #include
> > #include
> >
> > -#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
> > -#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
> > -#define SDHCI_ITAPDLY_CHGWIN0x200
> > -#define SDHCI_ITAPDLY_ENABLE0x100
> > -#define SDHCI_OTAPDLY_ENABLE0x40
> > +#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
> > +#define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
> > +#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
> > +#define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
> > +#define SDHCI_ITAPDLY_CHGWIN 0x200
> > +#define SDHCI_ITAPDLY_ENABLE 0x100
> > +#define SDHCI_OTAPDLY_ENABLE 0x40
>
> when you are touching this maybe better to use BIT and GENMASK macros.
Sure,
Will change it in v3.
Thanks,
Ashok
>
> >
> > #define SDHCI_TUNING_LOOP_COUNT40
> > #define MMC_BANK2 0x2
> > @@ -297,6 +299,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > int timing = mode2timing[mmc->selected_mode];
> > + u32 regval;
> >
> > /*
> > * This is applicable for SDHCI_SPEC_300 and above @@ -329,16
> > +332,16 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> > sdhci_host *host,
> >
> > tap_delay = (degrees * tap_max) / 360;
> >
> > + /* Limit output tap_delay value to 6 bits */
> > + tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
> > +
> > /* Set the Clock Phase */
> > - if (tap_delay) {
> > - u32 regval;
> > -
> > - regval = sdhci_readl(host,
> SDHCI_ARASAN_OTAPDLY_REGISTER);
> > - regval |= SDHCI_OTAPDLY_ENABLE;
> > - sdhci_writel(host, regval,
> SDHCI_ARASAN_OTAPDLY_REGISTER);
> > - regval |= tap_delay;
> > - sdhci_writel(host, regval,
> SDHCI_ARASAN_OTAPDLY_REGISTER);
> > - }
> > + regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
> > + regval |= SDHCI_OTAPDLY_ENABLE;
> > + sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
> > + regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
> > + regval |= tap_delay;
> > + sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
> >
> > return 0;
> > }
> > @@ -358,6 +361,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
> sdhci_host *host,
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > int timing = mode2timing[mmc->selected_mode];
> > + u32 regval;
> >
> > /*
> > * This is applicable for SDHCI_SPEC_300 and above @@ -390,20
> > +394,20 @@ static int sdhci_versal_sampleclk_set_phase(struct
> > sdhci_host *host,
> >
> > tap_delay = (degrees * tap_max) / 360;
> >
> > + /* Limit input tap_delay value to 8 bits */
> > + tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
> > +
> > /* Set the Clock Phase */
> > - if (tap_delay) {
> > - u32 regval;
> > -
> > - regval = sdhci_readl(host,
> SDHCI_ARASAN_ITAPDLY_REGISTER);
> > - regval |= SDHCI_ITAPDLY_CHGWIN;
> > - sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> > - regval |= SDHCI_ITAPDLY_ENABLE;
> > - sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> > - regval |= tap_delay;
> > - sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> > - regval &= ~SDHCI_ITAPDLY_CHGWIN;
> > - sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> > - }
> > + regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
> > + regval |= SDHCI_ITAPDLY_CHGWIN;
> > + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> > + regval |= SDHCI_ITAPDLY_ENABLE;
> > + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> > + regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
> > + regval |= tap_delay;
> > + sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> > + regval &= ~SDHCI_ITAPD
RE: [PATCH v2 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
Hi Michal,
> -Original Message-
> From: Michal Simek
> Sent: Friday, July 9, 2021 4:35 PM
> To: Ashok Reddy Soma ; u-boot@lists.denx.de
> Cc: peng@nxp.com; jh80.ch...@samsung.com; git ;
> mon...@monstr.eu; somaashokre...@gmail.com
> Subject: Re: [PATCH v2 1/6] mmc: zynq_sdhci: Resolve uninitialized return
> value
>
>
>
> On 7/9/21 12:46 PM, Ashok Reddy Soma wrote:
> > set_phase() functions are not modifying the ret value and returning
> > the same uninitialized ret, return 0 instead.
> >
> > Signed-off-by: Ashok Reddy Soma
> > ---
> >
> > Changes in v2:
> > - Changed "@degree" to "@degrees:" in function descriptions of tap
> >delay functions
> >
> > drivers/mmc/zynq_sdhci.c | 24 ++--
> > 1 file changed, 10 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index
> > b79c4021b6..03600188ba 100644
> > --- a/drivers/mmc/zynq_sdhci.c
> > +++ b/drivers/mmc/zynq_sdhci.c
> > @@ -183,7 +183,7 @@ static int arasan_sdhci_execute_tuning(struct mmc
> *mmc, u8 opcode)
> > *
> > * @host: Pointer to the sdhci_host structure.
> > * @degrees: The clock phase shift between 0 - 359.
> > - * Return: 0 on success and error value on error
> > + * Return: 0
> > */
> > static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
> > int degrees)
> > @@ -191,7 +191,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
> > struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > - int ret;
> > int timing = mode2timing[mmc->selected_mode];
> >
> > /*
> > @@ -229,7 +228,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> > sdhci_host *host,
> >
> > arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
> >
> > - return ret;
> > + return 0;
> > }
> >
> > /**
> > @@ -239,7 +238,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
> sdhci_host *host,
> > *
> > * @host: Pointer to the sdhci_host structure.
> > * @degrees: The clock phase shift between 0 - 359.
> > - * Return: 0 on success and error value on error
> > + * Return: 0
> > */
> > static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
> > int degrees)
> > @@ -247,7 +246,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> sdhci_host *host,
> > struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > - int ret;
> > int timing = mode2timing[mmc->selected_mode];
> >
> > /*
> > @@ -285,7 +283,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
> > sdhci_host *host,
> >
> > arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
> >
> > - return ret;
> > + return 0;
> > }
> >
> > /**
> > @@ -294,15 +292,14 @@ static int
> sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
> > * Set the SD Output Clock Tap Delays for Output path
> > *
> > * @host: Pointer to the sdhci_host structure.
> > - * @degreesThe clock phase shift between 0 - 359.
> > - * Return: 0 on success and error value on error
> > + * @degrees: The clock phase shift between 0 - 359.
>
> this should be also the part of 5/6
Sure will move it to 5/6.
>
> > + * Return: 0
> > */
> > static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
> > int degrees)
> > {
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > - int ret;
> > int timing = mode2timing[mmc->selected_mode];
> >
> > /*
> > @@ -349,7 +346,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> > sdhci_writel(host, regval,
> SDHCI_ARASAN_OTAPDLY_REGISTER);
> > }
> >
> > - return ret;
> > + return 0;
> > }
> >
> > /**
> > @@ -358,15 +355,14 @@ static int sdhci_versal_sdcardclk_set_phase(struct
> sdhci_host *host,
> > * Set the SD Input Clock Tap Delays for Input path
> > *
> > * @host: Pointer to the sdhci_host structure.
> > - * @degreesThe clock phase shift between 0 - 359.
> > - * Return: 0 on success and error value on error
> > + * @degrees: The clock phase shift between 0 - 359.
>
> this should be also the part of 5/6
will move it to 5/6 here too.
Thanks,
Ashok
>
> > + * Return: 0
> > */
> > static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
> > int degrees)
> > {
> > struct mmc *mmc = (struct mmc *)host->mmc;
> > u8 tap_delay, tap_max = 0;
> > - int ret;
> > int timing = mode2timing[mmc->selected_mode];
> >
> > /*
> > @@ -417,7 +413,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
> sd
Re: [PATCH u-boot-mvebu 00/31] kwboot / kwbimage improvements
Hi Stefan On Fri, 9 Jul 2021 08:05:40 +0200 Stefan Roese wrote: > > The main goal of this series is to correctly use BootROM's code > > for loading U-Boot from NOR / NAND: currently only SPL is read by > > BootROM and the main U-Boot is read by SPL. By using BootROM to also > > load main U-Boot we can reduce the size of SPL image, since it does > > not need to contain code for reading NOR / NAND. > > Before going into a review of the patches, let me ask about the > motivation of this patchset. Is the reduction of the SPL image size > the main motivation for this series? Or did you experiece some > problems with the SPL code for U-Boot proper loading? The motivation is reduction of SPL code size. Pali started working on something different (adding support for higher baudrates to kwboot, so that a bricked board can be booted over UART faster), and he is still working on it, but when he started studying the kwbimage/kwboot code and A38x documentation, he noticed that these things could be improved, so first he did this series. > BTW: This patch / mail subject "kwboot / kwbimage improvements" does > not really match its content AFAIU. Here, the SPL returns always back > to the BootROM for U-Boot proper loading part is missing. Or do I > misunderstand something? You are right, the subject of the series could have been better. I shall change it in v2. > > BTW2: Could you please list the affected MVEBU SoC's that are affected > by this series so that this is clear? OK. Marek
Re: [PATCH 3/6] dts: synquacer: Add partition information to the spi-nor
Hi Marek,
2021年7月9日(金) 19:54 Marek Behún :
>
> On Fri, 9 Jul 2021 19:50:27 +0900
> Masami Hiramatsu wrote:
>
> > Add partition information to the spi-nor flash.
> > This is required for accessing NOR flash via mtdparts.
> >
> > Signed-off-by: Masami Hiramatsu
> > ---
> > .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 42
> > 1 file changed, 42 insertions(+)
> >
> > diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
> > b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi index
> > 2f13a42235..245ebcda01 100644 ---
> > a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi +++
> > b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -31,6
> > +31,48 @@ spi-max-frequency = <3125>;
> > spi-rx-bus-width = <0x1>;
> > spi-tx-bus-width = <0x1>;
> > +
> > + partitions {
> > + compatible = "fixed-partitions";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + partition@0 {
> > + label = "BootStrap-BL1";
> > + reg = <0x0 0x7>;
> > + read-only;
> > + };
> > + partition@7 {
> > + label = "Flash-Writer";
> > + reg = <0x7 0x9>;
> > + read-only;
> > + };
> > + partition@10 {
> > + label = "SCP-BL2";
> > + reg = <0x10 0x8>;
> > + read-only;
> > + };
> > + partition@18 {
> > + label = "FIP-TFA";
> > + reg = <0x18 0x78000>;
> > + };
> > + partition@1f8000 {
> > + label = "Stage2Tables";
> > + reg = <0x1f8000 0x8000>;
> > + };
> > + partition@20 {
> > + label = "U-Boot";
> > + reg = <0x20 0x10>;
> > + };
> > + partition@30 {
> > + label = "UBoot-Env";
> > + reg = <0x30 0x10>;
> > + };
> > + partition@50 {
> > + label = "Ex-OPTEE";
> > + reg = <0x50 0x20>;
> > + };
> > + };
> > };
> > };
> >
> >
>
> Just a style hint: the individual partition nodes should be IMO
> separated by an additional newline character, i.e.:
Ah, OK.
>
> partition@0 {
> label = "BootStrap-BL1";
> reg = <0x0 0x7>;
> read-only;
> };
>
> partition@7 {
> label = "Flash-Writer";
> reg = <0x7 0x9>;
> read-only;
> };
>
> partition@10 {
> label = "SCP-BL2";
> reg = <0x10 0x8>;
> read-only;
> };
>
> Other than that:
>
> Reviewed-by: Marek Behún
>
> Btw, did you test this? Does this work correctly with mtd command?
Yes, I've tested that, and mtd list works. But it seems "mtd erase"
commands don't work well.
See the log below;
---
=> log level 7
=> mtd list
List of MTD devices:
* mx66u51235f
- device: spi-flash@0
- parent: spi@5480
- driver: jedec_spi_nor
- path: /spi@5480/spi-flash@0
- type: NOR flash
- block size: 0x1000 bytes
- min I/O: 0x1 bytes
- 0x-0x0400 : "mx66u51235f"
- 0x-0x0007 : "BootStrap-BL1"
- 0x0007-0x0010 : "Flash-Writer"
- 0x0010-0x0018 : "SCP-BL2"
- 0x0018-0x001f8000 : "FIP-TFA"
- 0x001f8000-0x0020 : "Stage2Tables"
- 0x0020-0x0040 : "EDK2"
- 0x0040-0x0050 : "EDK2-Env"
- 0x0050-0x00700
[PATCH v3 0/6] This patch set fixes minor issues related to tapdelays
This patch set fixes below issues in zynq_sdhc driver - Fix issues in tap delay functions where it returns uninitialized values - Allow configuring zero tap delay values - Split tapdelay functions to set input and output tap delay's separately. - Fix kernel doc warnings - Make local structures as static structures Changes in v3: - Updated commmit description to explain why return type int is kept - Change "@degree" to "@degrees:" in 5/6, so revert it in 1/6 from sdhci_zynqmp_sampleclk_set_phase() and sdhci_versal_sdcardclk_set_phase() - Updated macro's with BIT() and GENMASK() for readability - Change "@degree" to "@degrees:" in sdhci_zynqmp_sampleclk_set_phase() and sdhci_versal_sdcardclk_set_phase() and update description with these warnings. Changes in v2: - Changed "@degree" to "@degrees:" in function descriptions of tap delay functions - Removed @degree warning from commit description since it is fixed in patch 1/6. Ashok Reddy Soma (4): mmc: zynq_sdhci: Resolve uninitialized return value mmc: zynq_sdhci: Allow configuring zero Tap values mmc: zynq_sdhci: Use Mask writes for Tap delays mmc: zynq_sdhci: Split set_tapdelay function to in and out Michal Simek (2): mmc: zynq_sdhci: Fix kernel doc warnings mmc: zynq_sdhci: Make variables/structure static board/xilinx/zynqmp/tap_delays.c | 73 drivers/mmc/zynq_sdhci.c | 144 --- include/zynqmp_tap_delay.h | 7 +- 3 files changed, 115 insertions(+), 109 deletions(-) -- 2.17.1
[PATCH v3 4/6] mmc: zynq_sdhci: Split set_tapdelay function to in and out
Split arasan_zynqmp_set_tapdelay() to handle input and output tapdelays
separately. This is required to handle zero values for ITAP and OTAP
values. If we dont split, we will have to remove the if() in the
function, which makes ITAP values to be overwritten when OTAP values are
called to set and vice-versa.
Restrict tap_delay value calculated to max allowed 8 bits for ITAP and 6
bits for OTAP for ZynqMP.
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
board/xilinx/zynqmp/tap_delays.c | 73 +---
drivers/mmc/zynq_sdhci.c | 10 -
include/zynqmp_tap_delay.h | 7 +--
3 files changed, 50 insertions(+), 40 deletions(-)
diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c
index 1cab25f00a..d16bbb8eff 100644
--- a/board/xilinx/zynqmp/tap_delays.c
+++ b/board/xilinx/zynqmp/tap_delays.c
@@ -50,48 +50,51 @@ void zynqmp_dll_reset(u8 deviceid)
zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
}
-void arasan_zynqmp_set_tapdelay(u8 deviceid, u32 itap_delay, u32 otap_delay)
+void arasan_zynqmp_set_in_tapdelay(u8 deviceid, u32 itap_delay)
{
if (deviceid == 0) {
- zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
- SD0_DLL_RST);
- /* Program ITAP */
- if (itap_delay) {
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
- SD0_ITAPCHGWIN);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
- SD0_ITAPDLYENA);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
- itap_delay);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
- 0x0);
- }
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, SD0_DLL_RST);
- /* Program OTAP */
- if (otap_delay)
- zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
- otap_delay);
+ /* Program ITAP delay */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+ SD0_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
+ SD0_ITAPDLYENA);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, itap_delay);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
} else {
- zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
- SD1_DLL_RST);
- /* Program ITAP */
- if (itap_delay) {
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
- SD1_ITAPCHGWIN);
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
- SD1_ITAPDLYENA);
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
- (itap_delay << 16));
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
- 0x0);
- }
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST);
+
+ /* Program ITAP delay */
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+ SD1_ITAPCHGWIN);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
+ SD1_ITAPDLYENA);
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
+ (itap_delay << 16));
+ zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
+
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+ }
+}
+
+void arasan_zynqmp_set_out_tapdelay(u8 deviceid, u32 otap_delay)
+{
+ if (deviceid == 0) {
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, SD0_DLL_RST);
+
+ /* Program OTAP delay */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, otap_delay);
+
+ zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+ } else {
+ zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST);
- /* Program OTAP */
- if (otap_delay)
- zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
- (otap_delay << 16));
+ /* Program OTAP delay */
+ zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+ (otap_delay << 16));
zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
[PATCH v3 6/6] mmc: zynq_sdhci: Make variables/structure static
From: Michal Simek
All these variables/structure are local and should be static.
Issues are reported by sparse:
drivers/mmc/zynq_sdhci.c:49:11: warning: symbol 'zynqmp_iclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:50:11: warning: symbol 'zynqmp_oclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:53:11: warning: symbol 'versal_iclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:54:11: warning: symbol 'versal_oclk_phases' was not
declared. Should it be static?
drivers/mmc/zynq_sdhci.c:546:24: warning: symbol 'arasan_ops' was not declared.
Should it be static?
Signed-off-by: Michal Simek
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
drivers/mmc/zynq_sdhci.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 47862c0bf5..ba87ee8dd5 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -50,12 +50,16 @@ struct arasan_sdhci_priv {
#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
/* Default settings for ZynqMP Clock Phases */
-const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0};
-const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0};
+static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
+0, 183, 54, 0, 0};
+static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
+135, 48, 72, 135, 0};
/* Default settings for Versal Clock Phases */
-const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0};
-const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0};
+static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
+0, 0, 162, 90, 0, 0};
+static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
+90, 36, 60, 90, 0};
static const u8 mode2timing[] = {
[MMC_LEGACY] = MMC_TIMING_LEGACY,
@@ -541,8 +545,8 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host
*host)
sdhci_set_uhs_timing(host);
}
-const struct sdhci_ops arasan_ops = {
- .platform_execute_tuning = &arasan_sdhci_execute_tuning,
+static const struct sdhci_ops arasan_ops = {
+ .platform_execute_tuning= &arasan_sdhci_execute_tuning,
.set_delay = &arasan_sdhci_set_tapdelay,
.set_control_reg = &arasan_sdhci_set_control_reg,
};
--
2.17.1
[PATCH v3 5/6] mmc: zynq_sdhci: Fix kernel doc warnings
From: Michal Simek
Fix these kernel doc warnings:
drivers/mmc/zynq_sdhci.c:181: warning: contents before sections
drivers/mmc/zynq_sdhci.c:236: warning: contents before sections
drivers/mmc/zynq_sdhci.c:291: warning: contents before sections
drivers/mmc/zynq_sdhci.c:297: warning: Function parameter or member 'degrees'
not described in 'sdhci_versal_sdcardclk_set_phase'
drivers/mmc/zynq_sdhci.c:354: warning: contents before sections
drivers/mmc/zynq_sdhci.c:360: warning: Function parameter or member 'degrees'
not described in 'sdhci_versal_sampleclk_set_phase'
drivers/mmc/zynq_sdhci.c:467: warning: contents before sections
Signed-off-by: Michal Simek
Signed-off-by: Ashok Reddy Soma
---
Changes in v3:
- Change "@degree" to "@degrees:" in sdhci_zynqmp_sampleclk_set_phase()
and sdhci_versal_sdcardclk_set_phase() and update description with
these warnings.
Changes in v2:
- Removed @degree warning from commit description since it is fixed in
patch 1/6.
drivers/mmc/zynq_sdhci.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 95d42ccef4..47862c0bf5 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -181,11 +181,11 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc,
u8 opcode)
/**
* sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
*
- * Set the SD Output Clock Tap Delays for Output path
- *
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Output Clock Tap Delays for Output path
*/
static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -237,11 +237,11 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
/**
* sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
*
- * Set the SD Input Clock Tap Delays for Input path
- *
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Input Clock Tap Delays for Input path
*/
static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -293,11 +293,11 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
/**
* sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
*
- * Set the SD Output Clock Tap Delays for Output path
- *
* @host: Pointer to the sdhci_host structure.
- * @degreesThe clock phase shift between 0 - 359.
+ * @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Output Clock Tap Delays for Output path
*/
static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -355,11 +355,11 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
/**
* sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
*
- * Set the SD Input Clock Tap Delays for Input path
- *
* @host: Pointer to the sdhci_host structure.
- * @degreesThe clock phase shift between 0 - 359.
+ * @degrees: The clock phase shift between 0 - 359.
* Return: 0
+ *
+ * Set the SD Input Clock Tap Delays for Input path
*/
static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -467,9 +467,9 @@ static void arasan_dt_read_clk_phase(struct udevice *dev,
unsigned char timing,
/**
* arasan_dt_parse_clk_phases - Read Tap Delay values from DT
*
- * Called at initialization to parse the values of Tap Delays.
- *
* @dev:Pointer to our struct udevice.
+ *
+ * Called at initialization to parse the values of Tap Delays.
*/
static void arasan_dt_parse_clk_phases(struct udevice *dev)
{
--
2.17.1
[PATCH v3 2/6] mmc: zynq_sdhci: Allow configuring zero Tap values
Allow configuring ITAP and OTAP values with zero to avoid failures in
some cases (one of them is SD boot mode). Legacy, SDR12 modes require
to program the ITAP and OTAP values as zero, whereas for SDR50 and SDR104
modes ITAP value is zero.
In SD boot mode firmware configures the SD ITAP and OTAP values and
in this case u-boot has to re-configure required tap values(including zero)
based on the operating mode.
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
drivers/mmc/zynq_sdhci.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 5bad5cb9e7..f65a87a4e1 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -198,9 +198,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -253,9 +251,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -307,9 +303,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
@@ -370,9 +364,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
--
2.17.1
[PATCH v3 3/6] mmc: zynq_sdhci: Use Mask writes for Tap delays
Restrict tap_delay value to the allowed size(8bits for itap and 6 bits
for otap) before writing to the tap delay register.
Clear ITAP and OTAP delay bits before updating with the new tap value
for Versal platform.
Signed-off-by: Ashok Reddy Soma
---
Changes in v3:
- Updated macro's with BIT() and GENMASK() for readability
drivers/mmc/zynq_sdhci.c | 58 +---
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index f65a87a4e1..bf638e9675 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -19,11 +19,13 @@
#include
#include
-#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
-#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
-#define SDHCI_ITAPDLY_CHGWIN0x200
-#define SDHCI_ITAPDLY_ENABLE0x100
-#define SDHCI_OTAPDLY_ENABLE0x40
+#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
+#define SDHCI_ARASAN_ITAPDLY_SEL_MASK GENMASK(7, 0)
+#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
+#define SDHCI_ARASAN_OTAPDLY_SEL_MASK GENMASK(5, 0)
+#define SDHCI_ITAPDLY_CHGWIN BIT(9)
+#define SDHCI_ITAPDLY_ENABLE BIT(8)
+#define SDHCI_OTAPDLY_ENABLE BIT(6)
#define SDHCI_TUNING_LOOP_COUNT40
#define MMC_BANK2 0x2
@@ -297,6 +299,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
+ u32 regval;
/*
* This is applicable for SDHCI_SPEC_300 and above
@@ -329,16 +332,16 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
tap_delay = (degrees * tap_max) / 360;
+ /* Limit output tap_delay value to 6 bits */
+ tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
+
/* Set the Clock Phase */
- if (tap_delay) {
- u32 regval;
-
- regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
- regval |= SDHCI_OTAPDLY_ENABLE;
- sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
- regval |= tap_delay;
- sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
- }
+ regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
+ regval |= SDHCI_OTAPDLY_ENABLE;
+ sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
+ regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
+ regval |= tap_delay;
+ sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
return 0;
}
@@ -358,6 +361,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
+ u32 regval;
/*
* This is applicable for SDHCI_SPEC_300 and above
@@ -390,20 +394,20 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
tap_delay = (degrees * tap_max) / 360;
+ /* Limit input tap_delay value to 8 bits */
+ tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
+
/* Set the Clock Phase */
- if (tap_delay) {
- u32 regval;
-
- regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval |= SDHCI_ITAPDLY_CHGWIN;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval |= SDHCI_ITAPDLY_ENABLE;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval |= tap_delay;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- regval &= ~SDHCI_ITAPDLY_CHGWIN;
- sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
- }
+ regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval |= SDHCI_ITAPDLY_CHGWIN;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval |= SDHCI_ITAPDLY_ENABLE;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
+ regval |= tap_delay;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+ regval &= ~SDHCI_ITAPDLY_CHGWIN;
+ sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
return 0;
}
--
2.17.1
[PATCH v3 1/6] mmc: zynq_sdhci: Resolve uninitialized return value
set_phase() functions are not modifying the ret value and returning
the same uninitialized ret, return 0 instead.
Keep the return type as int to return errors when the tapdelay's are
set via xilinx_pm_request() in future.
Signed-off-by: Ashok Reddy Soma
---
Changes in v3:
- Updated commmit description to explain why return type int is kept
- Change "@degree" to "@degrees:" in 5/6, so revert it in 1/6 from
sdhci_zynqmp_sampleclk_set_phase() and sdhci_versal_sdcardclk_set_phase()
Changes in v2:
- Changed "@degree" to "@degrees:" in function descriptions of tap
delay functions
drivers/mmc/zynq_sdhci.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index b79c4021b6..5bad5cb9e7 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -183,7 +183,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
*
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * Return: 0
*/
static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -191,7 +191,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -229,7 +228,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
arasan_zynqmp_set_tapdelay(priv->deviceid, 0, tap_delay);
- return ret;
+ return 0;
}
/**
@@ -239,7 +238,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
*
* @host: Pointer to the sdhci_host structure.
* @degrees: The clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * Return: 0
*/
static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
@@ -247,7 +246,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -285,7 +283,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
arasan_zynqmp_set_tapdelay(priv->deviceid, tap_delay, 0);
- return ret;
+ return 0;
}
/**
@@ -295,14 +293,13 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
*
* @host: Pointer to the sdhci_host structure.
* @degreesThe clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * Return: 0
*/
static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
int degrees)
{
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -349,7 +346,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
}
- return ret;
+ return 0;
}
/**
@@ -359,14 +356,13 @@ static int sdhci_versal_sdcardclk_set_phase(struct
sdhci_host *host,
*
* @host: Pointer to the sdhci_host structure.
* @degreesThe clock phase shift between 0 - 359.
- * Return: 0 on success and error value on error
+ * Return: 0
*/
static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
int degrees)
{
struct mmc *mmc = (struct mmc *)host->mmc;
u8 tap_delay, tap_max = 0;
- int ret;
int timing = mode2timing[mmc->selected_mode];
/*
@@ -417,7 +413,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
sdhci_host *host,
sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
}
- return ret;
+ return 0;
}
static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
--
2.17.1
Re: [PATCH 3/6] dts: synquacer: Add partition information to the spi-nor
On Fri, 9 Jul 2021 20:27:18 +0900
Masami Hiramatsu wrote:
> Hi Marek,
>
> 2021年7月9日(金) 19:54 Marek Behún :
> >
> > On Fri, 9 Jul 2021 19:50:27 +0900
> > Masami Hiramatsu wrote:
> >
> > > Add partition information to the spi-nor flash.
> > > This is required for accessing NOR flash via mtdparts.
> > >
> > > Signed-off-by: Masami Hiramatsu
> > > ---
> > > .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 42
> > > 1 file changed, 42 insertions(+)
> > >
> > > diff --git
> > > a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
> > > b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi index
> > > 2f13a42235..245ebcda01 100644 ---
> > > a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi +++
> > > b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -31,6
> > > +31,48 @@ spi-max-frequency = <3125>; spi-rx-bus-width =
> > > <0x1>; spi-tx-bus-width = <0x1>;
> > > +
> > > + partitions {
> > > + compatible = "fixed-partitions";
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > +
> > > + partition@0 {
> > > + label = "BootStrap-BL1";
> > > + reg = <0x0 0x7>;
> > > + read-only;
> > > + };
> > > + partition@7 {
> > > + label = "Flash-Writer";
> > > + reg = <0x7 0x9>;
> > > + read-only;
> > > + };
> > > + partition@10 {
> > > + label = "SCP-BL2";
> > > + reg = <0x10 0x8>;
> > > + read-only;
> > > + };
> > > + partition@18 {
> > > + label = "FIP-TFA";
> > > + reg = <0x18 0x78000>;
> > > + };
> > > + partition@1f8000 {
> > > + label = "Stage2Tables";
> > > + reg = <0x1f8000 0x8000>;
> > > + };
> > > + partition@20 {
> > > + label = "U-Boot";
> > > + reg = <0x20 0x10>;
> > > + };
> > > + partition@30 {
> > > + label = "UBoot-Env";
> > > + reg = <0x30 0x10>;
> > > + };
> > > + partition@50 {
> > > + label = "Ex-OPTEE";
> > > + reg = <0x50 0x20>;
> > > + };
> > > + };
> > > };
> > > };
> > >
> > >
> >
> > Just a style hint: the individual partition nodes should be IMO
> > separated by an additional newline character, i.e.:
>
> Ah, OK.
>
> >
> > partition@0 {
> > label = "BootStrap-BL1";
> > reg = <0x0 0x7>;
> > read-only;
> > };
> >
> > partition@7 {
> > label = "Flash-Writer";
> > reg = <0x7 0x9>;
> > read-only;
> > };
> >
> > partition@10 {
> > label = "SCP-BL2";
> > reg = <0x10 0x8>;
> > read-only;
> > };
> >
> > Other than that:
> >
> > Reviewed-by: Marek Behún
> >
> > Btw, did you test this? Does this work correctly with mtd command?
>
> Yes, I've tested that, and mtd list works. But it seems "mtd erase"
> commands don't work well.
> See the log below;
>
> ---
> => log level 7
> => mtd list
> List of MTD devices:
> * mx66u51235f
> - device: spi-flash@0
> - parent: spi@5480
> - driver: jedec_spi_nor
> - path: /spi@5480/spi-flash@0
> - type: NOR flash
> - block size: 0x1000 bytes
> - min I/O: 0x1 bytes
> - 0x-0x0400 : "mx66u51235f"
> - 0x-0x0007 : "BootStrap-BL1"
> - 0x0007-0x0010 : "Flash-Writer"
> - 0x0010-0x0018 : "
[PATCH] clk: stm32mp1: add support of missing SPI clocks
Add the missing SPI clock even if these instances are not available
on STMicroelectronics boards: SPI2_K, SPI3_K, SPI4_K, SPI6_K.
With this patch, the SPI2 / SPI3 / SPI4 / SPI6 instances can be used on
customer design without the clock driver error:
stm32mp1_clk_get_id: clk id 131 not found
Reviewed-by: Patrice Chotard
Signed-off-by: Patrick Delaunay
---
drivers/clk/clk_stm32mp1.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 0c0ef366a1..599c2e7095 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -73,6 +73,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define RCC_PLL2FRACR 0xA0
#define RCC_PLL2CSGR 0xA4
#define RCC_I2C46CKSELR0xC0
+#define RCC_SPI6CKSELR 0xC4
#define RCC_CPERCKSELR 0xD0
#define RCC_STGENCKSELR0xD4
#define RCC_DDRITFCR 0xD8
@@ -103,6 +104,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define RCC_I2C12CKSELR0x8C0
#define RCC_I2C35CKSELR0x8C4
#define RCC_SPI2S1CKSELR 0x8D8
+#define RCC_SPI2S23CKSELR 0x8DC
#define RCC_SPI45CKSELR0x8E0
#define RCC_UART6CKSELR0x8E4
#define RCC_UART24CKSELR 0x8E8
@@ -313,7 +315,9 @@ enum stm32mp1_parent_sel {
_DSI_SEL,
_ADC12_SEL,
_SPI1_SEL,
+ _SPI23_SEL,
_SPI45_SEL,
+ _SPI6_SEL,
_RTC_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
@@ -524,6 +528,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] =
{
STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 11, SPI2_K, _SPI23_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 12, SPI3_K, _SPI23_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
@@ -536,6 +542,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] =
{
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 9, SPI4_K, _SPI45_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
@@ -548,6 +555,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] =
{
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
@@ -612,10 +620,13 @@ static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
+/* same parents for SPI1=RCC_SPI2S1CKSELR and SPI2&3 = RCC_SPI2S23CKSELR */
static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
_PLL3_R};
static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
_HSE_KER};
+static const u8 spi6_parents[] = {_PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER, _PLL3_Q};
static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
@@ -642,7 +653,9 @@ static const struct stm32mp1_clk_sel
stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
+ STM32MP1_CLK_PARENT(_SPI23_SEL, RCC_SPI2S23CKSELR, 0, 0x7, spi_parents),
STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
+ STM32MP1_CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents),
STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
(RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
rtc_parents),
--
2.25.1
Re: [PATCH u-boot-mvebu 00/31] kwboot / kwbimage improvements
Hi Marek, On 09.07.21 13:22, Marek Behún wrote: Hi Stefan On Fri, 9 Jul 2021 08:05:40 +0200 Stefan Roese wrote: The main goal of this series is to correctly use BootROM's code for loading U-Boot from NOR / NAND: currently only SPL is read by BootROM and the main U-Boot is read by SPL. By using BootROM to also load main U-Boot we can reduce the size of SPL image, since it does not need to contain code for reading NOR / NAND. Before going into a review of the patches, let me ask about the motivation of this patchset. Is the reduction of the SPL image size the main motivation for this series? Or did you experiece some problems with the SPL code for U-Boot proper loading? The motivation is reduction of SPL code size. Pali started working on something different (adding support for higher baudrates to kwboot, so that a bricked board can be booted over UART faster), and he is still working on it, but when he started studying the kwbimage/kwboot code and A38x documentation, he noticed that these things could be improved, so first he did this series. BTW: This patch / mail subject "kwboot / kwbimage improvements" does not really match its content AFAIU. Here, the SPL returns always back to the BootROM for U-Boot proper loading part is missing. Or do I misunderstand something? You are right, the subject of the series could have been better. I shall change it in v2. BTW2: Could you please list the affected MVEBU SoC's that are affected by this series so that this is clear? OK. Thanks. And could you please also do one (or more) boot-time comparisons, old vs. new version? This way we can see, if and how the boot-time is affected (perhaps improved, which would be great) by this patch series. Thanks, Stefan Marek Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH] stm32mp1: add pull-up for gpio button PA13 and PA14
Hi Patrick
On 7/9/21 9:53 AM, Patrick Delaunay wrote:
> When a push-button is released and PA13/PA14 are defined as input (high-Z)
> the LED should not be active as the circuit is open but a small current
> leak through PCB or push-button close the circuit and allows a small LED
> bias giving erroneous level voltage.
>
> So it is recommended to activate an internal pull-up in order to clearly
> fix the voltage at PA13/PA14 when button is released and to wait
> a short delay before to read the GPIO value only when the pull-up is
> correctly configured.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 4 ++--
> arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 4 ++--
> board/st/stm32mp1/stm32mp1.c | 2 ++
> 3 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> index 6787619290..d44da7566f 100644
> --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> @@ -18,8 +18,8 @@
> u-boot,error-led = "error";
> u-boot,mmc-env-partition = "ssbl";
> st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
> - st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
> - st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
> + st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW |
> GPIO_PULL_UP)>;
> + st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW |
> GPIO_PULL_UP)>;
> };
>
> firmware {
> diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> index f3002e995b..3b94218b2f 100644
> --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> @@ -18,8 +18,8 @@
> u-boot,boot-led = "heartbeat";
> u-boot,error-led = "error";
> u-boot,mmc-env-partition = "ssbl";
> - st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
> - st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
> + st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW |
> GPIO_PULL_UP)>;
> + st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW |
> GPIO_PULL_UP)>;
> };
>
> firmware {
> diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
> index 18b8870269..e1796e7e31 100644
> --- a/board/st/stm32mp1/stm32mp1.c
> +++ b/board/st/stm32mp1/stm32mp1.c
> @@ -155,6 +155,7 @@ static void board_key_check(void)
> &gpio, GPIOD_IS_IN)) {
> log_debug("could not find a
> /config/st,fastboot-gpios\n");
> } else {
> + udelay(20);
> if (dm_gpio_get_value(&gpio)) {
> log_notice("Fastboot key pressed, ");
> boot_mode = BOOT_FASTBOOT;
> @@ -168,6 +169,7 @@ static void board_key_check(void)
> &gpio, GPIOD_IS_IN)) {
> log_debug("could not find a
> /config/st,stm32prog-gpios\n");
> } else {
> + udelay(20);
> if (dm_gpio_get_value(&gpio)) {
> log_notice("STM32Programmer key pressed, ");
> boot_mode = BOOT_STM32PROG;
>
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 1/5] arm: stm32mp: add config for STM32IMAGE support
Hi Patrick
On 7/8/21 11:17 AM, Patrick Delaunay wrote:
> By default for trusted boot with TF-A, U-Boot (u-boot-nodtb)
> is located in FIP container with its device tree and with
> the secure monitor (provided by TF-A or OP-TEE).
> The FIP file is loaded by TF-A BL2 and each components is
> extracted at the final location.
>
> This patch add CONFIG_STM32MP15x_STM32IMAGE to request the
> STM32 image generation for SOC STM32MP15x
> when FIP container is not used (u-boot.stm32 is loaded by TF-A
> as done previously to keep the backward compatibility).
>
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/mach-stm32mp/Kconfig | 7 +++
> arch/arm/mach-stm32mp/config.mk | 2 +-
> board/st/stm32mp1/stm32mp1.c| 10 +++---
> configs/stm32mp15_trusted_defconfig | 1 +
> 4 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
> index 7c25266f33..09d0b4096f 100644
> --- a/arch/arm/mach-stm32mp/Kconfig
> +++ b/arch/arm/mach-stm32mp/Kconfig
> @@ -56,6 +56,13 @@ config STM32MP15x
> dual core A7 for STM32MP157/3, monocore for STM32MP151
> target all the STMicroelectronics board with SOC STM32MP1 family
>
> +config STM32MP15x_STM32IMAGE
> + bool "Support STM32 image for generated U-Boot image"
> + depends on STM32MP15x && TFABOOT
> + help
> + Support of STM32 image generation for SOC STM32MP15x
> + for TF-A boot when FIP container is not used
> +
> choice
> prompt "STM32MP15x board select"
> optional
> diff --git a/arch/arm/mach-stm32mp/config.mk b/arch/arm/mach-stm32mp/config.mk
> index c30bf482f7..f7f5b77c41 100644
> --- a/arch/arm/mach-stm32mp/config.mk
> +++ b/arch/arm/mach-stm32mp/config.mk
> @@ -4,7 +4,7 @@
> #
>
> ifndef CONFIG_SPL
> -INPUTS-y += u-boot.stm32
> +INPUTS-$(CONFIG_STM32MP15x_STM32IMAGE) += u-boot.stm32
> else
> ifdef CONFIG_SPL_BUILD
> INPUTS-y += u-boot-spl.stm32
> diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
> index 261ec15e1b..d8335efa53 100644
> --- a/board/st/stm32mp1/stm32mp1.c
> +++ b/board/st/stm32mp1/stm32mp1.c
> @@ -105,10 +105,14 @@ int checkboard(void)
> const char *fdt_compat;
> int fdt_compat_len;
>
> - if (IS_ENABLED(CONFIG_TFABOOT))
> - mode = "trusted";
> - else
> + if (IS_ENABLED(CONFIG_TFABOOT)) {
> + if (IS_ENABLED(CONFIG_STM32MP15x_STM32IMAGE))
> + mode = "trusted - stm32image";
> + else
> + mode = "trusted";
> + } else {
> mode = "basic";
> + }
>
> fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
>&fdt_compat_len);
> diff --git a/configs/stm32mp15_trusted_defconfig
> b/configs/stm32mp15_trusted_defconfig
> index 5bc5e79400..e008d1fba7 100644
> --- a/configs/stm32mp15_trusted_defconfig
> +++ b/configs/stm32mp15_trusted_defconfig
> @@ -7,6 +7,7 @@ CONFIG_SYS_MEMTEST_END=0xc400
> CONFIG_ENV_OFFSET=0x28
> CONFIG_ENV_SECT_SIZE=0x4
> CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
> +CONFIG_STM32MP15x_STM32IMAGE=y
> CONFIG_TARGET_ST_STM32MP15x=y
> CONFIG_CMD_STM32PROG=y
> CONFIG_ENV_OFFSET_REDUND=0x2C
>
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 2/5] arm: stm32mp: handle the OP-TEE nodes in DT with FIP support
Hi Patrick
On 7/8/21 11:17 AM, Patrick Delaunay wrote:
> With FIP support in TF-A (when CONFIG_STM32MP15x_STM32IMAGE
> is not activated), the DT nodes needed by OP-TEE are added by OP-TEE
> firmware in U-Boot device tree, present in FIP.
>
> These nodes are only required in trusted boot, when TF-A load the file
> u-boot.stm32, including the U-Boot device tree with STM32IMAGE header,
> in this case OP-TEE can't update the U-Boot device tree.
>
> Moreover in trusted boot mode with FIP, as the OP-TEE nodes are present
> in U-Boot device tree only when needed the function
> stm32_fdt_disable_optee can be removed.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 3 +++
> arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 3 +++
> arch/arm/mach-stm32mp/fdt.c | 11 ++-
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> index 6787619290..49305979bb 100644
> --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> @@ -22,6 +22,8 @@
> st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
> };
>
> +#ifdef CONFIG_STM32MP15x_STM32IMAGE
> + /* only needed for boot with TF-A, witout FIP support */
> firmware {
> optee {
> compatible = "linaro,optee-tz";
> @@ -35,6 +37,7 @@
> no-map;
> };
> };
> +#endif
>
> led {
> red {
> diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> index f3002e995b..956332ea9a 100644
> --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> @@ -22,6 +22,8 @@
> st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
> };
>
> +#ifdef CONFIG_STM32MP15x_STM32IMAGE
> + /* only needed for boot with TF-A, witout FIP support */
> firmware {
> optee {
> compatible = "linaro,optee-tz";
> @@ -35,6 +37,7 @@
> no-map;
> };
> };
> +#endif
>
> led {
> red {
> diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c
> index ce2fe0206f..a19e954cf7 100644
> --- a/arch/arm/mach-stm32mp/fdt.c
> +++ b/arch/arm/mach-stm32mp/fdt.c
> @@ -332,7 +332,16 @@ int ft_system_setup(void *blob, struct bd_info *bd)
> "st,package", pkg, false);
> }
>
> - if (!CONFIG_IS_ENABLED(OPTEE) ||
> + /*
> + * TEMP: remove OP-TEE nodes in kernel device tree
> + * copied from U-Boot device tree by optee_copy_fdt_nodes
> + * when OP-TEE is not detected (probe failed)
> + * these OP-TEE nodes are present in -u-boot.dtsi
> + * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
> + * when FIP is not used by TF-A
> + */
> + if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
> + CONFIG_IS_ENABLED(OPTEE) &&
> !tee_find_device(NULL, NULL, NULL, NULL))
> stm32_fdt_disable_optee(blob);
>
>
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH 3/5] arm: stm32mp: add defconfig for trusted boot with FIP
Hi Patrick
On 7/8/21 11:17 AM, Patrick Delaunay wrote:
> Add TF-A FIP support for trusted boot on STM32MP15x,
> when STM32MP15x_STM32IMAGE is not activated.
>
> With FIP support the SSBL partition is named "fip" and its size is 4MB,
> so the ENV partition name in device tree (for SD card or eMMC)
> or offset in defconfig (CONFIG_ENV_OFFSET / CONFIG_ENV_OFFSET_REDUND)
> need to be modified.
>
> With FIP the TEE MTD partitions are removed because the OP-TEE binray are
> included in the FIP containers.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 6 +-
> arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 6 +-
> board/st/common/Kconfig | 21 ++-
> board/st/common/stm32mp_mtdparts.c | 31 +++--
> board/st/stm32mp1/MAINTAINERS| 1 +
> configs/stm32mp15_defconfig | 157 +++
> 6 files changed, 206 insertions(+), 16 deletions(-)
> create mode 100644 configs/stm32mp15_defconfig
>
> diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> index 49305979bb..41dead3230 100644
> --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> @@ -16,13 +16,17 @@
> config {
> u-boot,boot-led = "heartbeat";
> u-boot,error-led = "error";
> - u-boot,mmc-env-partition = "ssbl";
> + u-boot,mmc-env-partition = "fip";
> st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
> st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
> st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
> };
>
> #ifdef CONFIG_STM32MP15x_STM32IMAGE
> + config {
> + u-boot,mmc-env-partition = "ssbl";
> + };
> +
> /* only needed for boot with TF-A, witout FIP support */
> firmware {
> optee {
> diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> index 956332ea9a..06daa17a89 100644
> --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> @@ -17,12 +17,16 @@
> config {
> u-boot,boot-led = "heartbeat";
> u-boot,error-led = "error";
> - u-boot,mmc-env-partition = "ssbl";
> + u-boot,mmc-env-partition = "fip";
> st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
> st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
> };
>
> #ifdef CONFIG_STM32MP15x_STM32IMAGE
> + config {
> + u-boot,mmc-env-partition = "ssbl";
> + };
> +
> /* only needed for boot with TF-A, witout FIP support */
> firmware {
> optee {
> diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig
> index ddcf33a122..2f57118bb2 100644
> --- a/board/st/common/Kconfig
> +++ b/board/st/common/Kconfig
> @@ -8,18 +8,22 @@ config CMD_STBOARD
>
> config MTDPARTS_NAND0_BOOT
> string "mtd boot partitions for nand0"
> - default "2m(fsbl),2m(ssbl1),2m(ssbl2)"
> + default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || \
> + !TFABOOT
> + default "2m(fsbl),4m(fip1),4m(fip2)"
> depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
> help
> This define the partitions of nand0 used to build mtparts dynamically
> for boot from nand0.
> Each partition need to be aligned with the device erase block size,
> 512KB is the max size for the NAND supported by stm32mp1 platform.
> + The fsbl partition support multiple copy of the same binary, one by
> + erase block.
>
> config MTDPARTS_NAND0_TEE
> string "mtd tee partitions for nand0"
> default "512k(teeh),512k(teed),512k(teex)"
> - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
> + depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE
> help
> This define the tee partitions added in mtparts dynamically
> when tee is supported with boot from nand0.
> @@ -28,7 +32,9 @@ config MTDPARTS_NAND0_TEE
>
> config MTDPARTS_NOR0_BOOT
> string "mtd boot partitions for nor0"
> - default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)"
> + default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)" if
> STM32MP15x_STM32IMAGE || \
> +!TFABOOT
> + default "256k(fsbl1),256k(fsbl2),4m(fip),512k(u-boot-env)"
> depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
> help
> This define the partitions of nand0 used to build mtparts dynamically
> @@ -40,24 +46,27 @@ config MTDPARTS_NOR0_BOOT
> config MTDPARTS_NOR0_TEE
> string "mtd tee partitions for nor0"
> default "256k(teeh),512k(teed),256k(teex)"
> - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP
> + depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM3
Re: [PATCH 4/5] doc: st: stm32mp1: Add FIP support for trusted boot
Hi Patrick One typo below On 7/8/21 11:17 AM, Patrick Delaunay wrote: > TF-A for STM32MP15 now supports the FIP: it is a packaging format which > includes the secure monitor, u-boot-nodtb.bin and u-boot.dtb > > This FIP file is loaded by FSBL = TF-A BL2. > > This patch updates the board documentation to use this FIP file and no > more u-boot.stm32 (with STM32 image header) which is no more generated. > > Signed-off-by: Patrick Delaunay > --- > > doc/board/st/stm32mp1.rst | 166 ++ > 1 file changed, 97 insertions(+), 69 deletions(-) > > diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst > index f0c2b09b98..6048fa36a7 100644 > --- a/doc/board/st/stm32mp1.rst > +++ b/doc/board/st/stm32mp1.rst > @@ -60,7 +60,7 @@ Currently the following boards are supported: > Boot Sequences > -- > > -3 boot configurations are supported with: > +2 boot configurations are supported with: > > > +--++-+--+ > | **ROM** | **FSBL** | **SSBL**| **OS** > | > @@ -70,10 +70,12 @@ Boot Sequences > | | embedded RAM | DDR > | > > +--++-+--+ > > -The **Trusted** boot chain > -`` > +The **Trusted** boot chain with TF-A > +` > > -defconfig_file : stm32mp15_trusted_defconfig > +defconfig_file : > + + **stm32mp15_defconfig** (for TF-A with FIP support) > + + **stm32mp15_trusted_defconfig** (for TF-A without FIP support) > > +-+-++---+ > | ROM code | FSBL| SSBL | OS| > @@ -83,19 +85,16 @@ defconfig_file : stm32mp15_trusted_defconfig > | TrustZone |secure monitor| > +-+-++---+ > > -TF-A performs a full initialization of Secure peripherals and installs a > -secure monitor, BL32: > +TF-A (BL2) initialize the DDR and loads the next stage binaries from a FIP > file: > + + BL32: a secure monitor BL32 = SPMin provided by TF-A or OP-TEE : > performs a full initialization of Secure peripherals and provides service to > normal world > + + BL33: a non-trusted firmware = U-Boot, running in normal world and uses > the secure monitor to access to secure resources. > + + HW_CONFIG: The hardware configuration file = the U-Boot device tree > > - * SPMin provided by TF-A or > - * OP-TEE from specific partitions (teeh, teed, teex). > +The **Basic** boot chain with SPL > +` > > -U-Boot is running in normal world and uses the secure monitor to access > -to secure resources. > - > -The **Basic** boot chain > - > - > -defconfig_file : stm32mp15_basic_defconfig > +defconfig_file : > + + **stm32mp15_basic_defconfig** > > +-+++---+ > | ROM code | FSBL | SSBL | OS| > @@ -163,12 +162,13 @@ Build Procedure > > for example: use one output directory for each configuration:: > > + # export KBUILD_OUTPUT=stm32mp15 > # export KBUILD_OUTPUT=stm32mp15_trusted > # export KBUILD_OUTPUT=stm32mp15_basic > > you can build outside of code directory:: > > - # export KBUILD_OUTPUT=../build/stm32mp15_trusted > + # export KBUILD_OUTPUT=../build/stm32mp15 > > 4. Configure U-Boot:: > > @@ -176,7 +176,7 @@ Build Procedure > > with : > > - - For **trusted** boot mode : **stm32mp15_trusted_defconfig** > + - For **trusted** boot mode : **stm32mp15_defconfig** or > stm32mp15_trusted_defconfig > - For basic boot mode: stm32mp15_basic_defconfig > > 5. Configure the device-tree and build the U-Boot image:: > @@ -185,13 +185,13 @@ Build Procedure > > Examples: > > - a) trusted boot on ev1:: > + a) trusted boot with FIP on ev1:: > > - # export KBUILD_OUTPUT=stm32mp15_trusted > - # make stm32mp15_trusted_defconfig > + # export KBUILD_OUTPUT=stm32mp15 > + # make stm32mp15_defconfig > # make DEVICE_TREE=stm32mp157c-ev1 all > > - b) trusted with OP-TEE boot on dk2:: > + b) trusted boot without FIP on dk2:: > ># export KBUILD_OUTPUT=stm32mp15_trusted ># make stm32mp15_trusted_defconfig > @@ -223,16 +223,32 @@ Build Procedure > > 6. Output files > > - BootRom and TF-A expect binaries with STM32 image header > - SPL expects file with U-Boot uImage header > + The ROM code expects FSBL binaries with STM32 image header. > + TF-A expects: > + - a FIP binary, including the OS monitor (SPmin or OP-TEE) and the > U-Boot > + binary + device tree > + - binaries with STM32 image header: U-Boot and OP-TEE > + SPL expects file with U-Boot uImage header. > > So in the ou
Re: [PATCH 5/5] stm32mp1: stm32prog: remove stm32prog_get_tee_partitions with FIP
Hi Patrick
On 7/8/21 11:17 AM, Patrick Delaunay wrote:
> The MTD tee partitions used to save the OP-TEE binary are needed when
> TF-A doesn't use the FIP container to load binaries.
>
> This patch puts under CONFIG_STM32MP15x_STM32IMAGE flag the associated
> code in U-Boot binary and prepare the code cleanup when
> CONFIG_STM32MP15x_STM32IMAGE support will be removed after TF-A migration
> to FIP support.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 2 ++
> arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4
> arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | 2 ++
> arch/arm/mach-stm32mp/include/mach/stm32prog.h | 2 ++
> 4 files changed, 10 insertions(+)
>
> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
> b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
> index e36501a86b..821c174bbe 100644
> --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
> +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
> @@ -175,6 +175,7 @@ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog,
> " = size of flashlayout\n"
> );
>
> +#ifdef CONFIG_STM32MP15x_STM32IMAGE
> bool stm32prog_get_tee_partitions(void)
> {
> if (stm32prog_data)
> @@ -182,6 +183,7 @@ bool stm32prog_get_tee_partitions(void)
>
> return false;
> }
> +#endif
>
> bool stm32prog_get_fsbl_nor(void)
> {
> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
> b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
> index 4c4d8a7a69..2fb1f1f24a 100644
> --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
> +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
> @@ -823,7 +823,9 @@ static int treat_partition_list(struct stm32prog_data
> *data)
> INIT_LIST_HEAD(&data->dev[j].part_list);
> }
>
> +#ifdef CONFIG_STM32MP15x_STM32IMAGE
> data->tee_detected = false;
> +#endif
> data->fsbl_nor_detected = false;
> for (i = 0; i < data->part_nb; i++) {
> part = &data->part_array[i];
> @@ -877,10 +879,12 @@ static int treat_partition_list(struct stm32prog_data
> *data)
> /* fallthrough */
> case STM32PROG_NAND:
> case STM32PROG_SPI_NAND:
> +#ifdef CONFIG_STM32MP15x_STM32IMAGE
> if (!data->tee_detected &&
> !strncmp(part->name, "tee", 3))
> data->tee_detected = true;
> break;
> +#endif
> default:
> break;
> }
> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
> b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
> index 581b10d0ac..5b18f2fd4f 100644
> --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
> +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
> @@ -121,7 +121,9 @@ struct stm32prog_data {
> struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */
> int part_nb;/* nb of partition */
> struct stm32prog_part_t *part_array;/* array of partition */
> +#ifdef CONFIG_STM32MP15x_STM32IMAGE
> booltee_detected;
> +#endif
> boolfsbl_nor_detected;
>
> /* command internal information */
> diff --git a/arch/arm/mach-stm32mp/include/mach/stm32prog.h
> b/arch/arm/mach-stm32mp/include/mach/stm32prog.h
> index c080b9cc42..99be4e1d65 100644
> --- a/arch/arm/mach-stm32mp/include/mach/stm32prog.h
> +++ b/arch/arm/mach-stm32mp/include/mach/stm32prog.h
> @@ -11,6 +11,8 @@ int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64
> offset,
> void *buf, long *len);
> int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size);
>
> +#ifdef CONFIG_STM32MP15x_STM32IMAGE
> bool stm32prog_get_tee_partitions(void);
> +#endif
>
> bool stm32prog_get_fsbl_nor(void);
>
Reviewed-by: Patrice Chotard
Thanks
Patrice
Re: [PATCH v3 13/20] ARM: dts: k3-j721e: Add the entries required for USB3 support on USB0
Hi Tom, On 07/05/21 10:44 pm, Tom Rini wrote: > On Tue, May 04, 2021 at 04:11:48PM +0530, Kishon Vijay Abraham I wrote: > >> Partially sync with Linux's dts to add the entries required for USB3 >> support on USB0. >> Note that the default mode is still "peripheral" not "host". USB3 is >> supported only for the host mode. >> >> Signed-off-by: Jean-Jacques Hiblot >> Signed-off-by: Vignesh Raghavendra >> Signed-off-by: Kishon Vijay Abraham I >> --- >> .../k3-j721e-common-proc-board-u-boot.dtsi| 19 ++- >> 1 file changed, 18 insertions(+), 1 deletion(-) > > You're doing a partial sync with Linux in the -u-boot.dtsi file, why? This only changes the part that deals with USB. Other's will be added as when it's getting tested and verified in u-boot. Thanks Kishon
Re: [PATCH u-boot-mvebu 00/31] kwboot / kwbimage improvements
On Fri, 9 Jul 2021 14:35:15 +0200 Stefan Roese wrote: > Thanks. And could you please also do one (or more) boot-time > comparisons, old vs. new version? This way we can see, if and how the > boot-time is affected (perhaps improved, which would be great) by this > patch series. For Turris Omnia, the size of the u-boot-spl.kwb binary decreases by ~37 KiB, mainly due to not needing padding anymore. The size of the SPL binary itself (u-boot-spl.bin) decreases by 7.5 KiB (due to code reduction - no SPI NOR code). Unfortunately the boot time increases by 815 ms, from 2341 ms (on average) to 3156 ms (on average). This is probably because BootROM read the memory differently (lower frequency or some other reason). I think this 815 ms increase in boot time into U-Boot prompt is worth the 37 KiB saved space for U-Boot code (mainly because on Omnia we have 960 KiB for U-Boot and currently we are at 860 KiB, so enabling some other features in the future may push us to the limit), but others may not agree. I am going to put this information also into v2 cover letter. Marek
[PATCHv2 1/4] ge_bx50v3: Remove unused USB related defines
These USB defines do not change the build as there is no USB support enabled currently. Cc: Ian Ray Cc: Sebastian Reichel Signed-off-by: Tom Rini --- Changes in v2: - New patch --- include/configs/ge_bx50v3.h | 11 --- 1 file changed, 11 deletions(-) diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index c8e9d3b17f5e..2b61172cc739 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -33,17 +33,6 @@ #define CONFIG_LBA48 #endif -/* USB Configs */ -#ifdef CONFIG_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_MASS_STORAGE -#endif - /* Serial Flash */ #define CONFIG_LOADADDR0x1200 -- 2.17.1
[PATCHv2 2/4] tegra: Test on CONFIG_CMD_USB being enabled for distro bootcmd
Reuse the common logic to allow for BOOT_TARGET_DEVICES to list USB as a possibility if we're building for a platform that will have USB but not if we don't, so that we don't hit the link-time check for trying to have USB boot on a non-USB system. Cc: Tom Warren Signed-off-by: Tom Rini --- Changes in v2: - New patch. This problem shows up later in the series when we stop building USB framework without a host controller of some sort also enabled. --- include/configs/tegra-common-post.h | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index fae0e761fb42..dd7a75ae4674 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -21,11 +21,18 @@ #define CONFIG_SYS_NONCACHED_MEMORY(1 << 20) /* 1 MiB */ #ifndef CONFIG_SPL_BUILD + +#if CONFIG_IS_ENABLED(CMD_USB) +# define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +# define BOOT_TARGET_USB(func) +#endif + #ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ - func(USB, usb, 0) \ + BOOT_TARGET_USB(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) #endif -- 2.17.1
[PATCHv2 3/4] treewide: Test on CONFIG_USB_HOST (or CONFIG_CMD_USB) not CONFIG_USB
As the logic here is only used when we have a USB host controller, test
on CONFIG_USB_HOST rather than CONFIG_USB in general. This lets us move
towards using CONFIG_USB only as a menu symbol to say that we have some
form of USB, and then USB_HOST or USB_GADGET depending on the role that
USB plays within the build.
Signed-off-by: Tom Rini
---
Changes in v2:
- New patch
---
board/freescale/lx2160a/lx2160a.c | 2 +-
board/freescale/mpc837xerdb/mpc837xerdb.c | 2 +-
board/tplink/wdr4300/wdr4300.c| 2 +-
cmd/Kconfig | 2 +-
include/configs/lx2160a_common.h | 2 +-
include/configs/stm32mp1.h| 2 +-
include/configs/topic_miami.h | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 47a7024f3313..891bc0051413 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -781,7 +781,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c
b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 66b3d9a4651c..84671f63c60b 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -220,7 +220,7 @@ int misc_init_r(void)
int board_late_init(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x4000);
#endif
return 0;
diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c
index 9134d6bf6d43..f2b92109b6ac 100644
--- a/board/tplink/wdr4300/wdr4300.c
+++ b/board/tplink/wdr4300/wdr4300.c
@@ -15,7 +15,7 @@
#include
#include
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
static void wdr4300_usb_start(void)
{
void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
diff --git a/cmd/Kconfig b/cmd/Kconfig
index f196e6cdd821..e40d390f8820 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1322,7 +1322,7 @@ config CMD_UNIVERSE
config CMD_USB
bool "usb"
- depends on USB
+ depends on USB_HOST
select HAVE_BLOCK_DEVICE
help
USB support.
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 15ea0e4ce1f7..1338ee3cda3b 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -142,7 +142,7 @@
#endif
/* USB */
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
#define CONFIG_HAS_FSL_XHCI_USB
#ifndef CONFIG_TARGET_LX2162AQDS
#define CONFIG_USB_MAX_CONTROLLER_COUNT2
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index 440efa1a55af..c73a2e7b5683 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -101,7 +101,7 @@
#define BOOT_TARGET_UBIFS(func)
#endif
-#ifdef CONFIG_USB
+#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_USB(func) func(USB, usb, 0)
#else
#define BOOT_TARGET_USB(func)
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index c12cd7ccad8f..b668817c6c8d 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -34,7 +34,7 @@
/* Setup proper boot sequences for Miami boards */
-#if defined(CONFIG_USB)
+#if defined(CONFIG_USB_HOST)
# define EXTRA_ENV_USB \
"usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
"i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
--
2.17.1
[PATCHv2 4/4] usb: Enforce DM_USB migration for USB_HOST devices.
As the deadline for migration to DM_USB, when using a USB host controller has now gone two years past the deadline, enforce migration. This is done by: - Ensuring that all host controller options (other than the very legacy old MUSB ones) now select USB_HOST. USB_HOST now enforces DM_USB and OF_CONTROL. - Remove other parts of Kconfig logic that had platforms pick DM_USB. - To keep Kconfig happy, have some select statements test for USB_HOST as well. - Re-order some Kconfig entries and menus so that we can cleanly pick host or gadget roles. For the various HCD options that have platform glue options, group them together and update dependencies in some cases. - As SPL_DM_USB is not required, on platforms that had not yet enabled it, disable it. Cc: Marek Vasut Cc: Icenowy Zheng Cc: Samuel Holland Cc: FUKAUMI Naoki Cc: Andre Przywara Cc: Jagan Teki Signed-off-by: Tom Rini --- Changes in v2: - Rework the final stage of migration to result in splitting USB_HOST and USB_GADGET from the plain USB symbol. This resolves the problem of gadget-only platforms seeing a migration warning. As part of this, a few boards get converted to DM_USB, because they had everything required but hadn't enabled the options. Also as part of this, and why I've cc'd some sunxi board maintainers, a number of platforms like pinephone and pinecube free up space as they had been building in USB host or gadget support without having a controller enabled. With the Kconfig changes here we no longer build in that functionality. --- Makefile | 2 -- arch/arm/Kconfig | 15 +++ arch/arm/mach-imx/mx5/Kconfig | 1 - arch/arm/mach-imx/mx6/Kconfig | 2 -- arch/arm/mach-omap2/am33xx/Kconfig | 1 - board/tqc/tqma6/Kconfig| 1 - configs/devkit3250_defconfig | 1 + configs/draco_defconfig| 1 + configs/etamin_defconfig | 1 + configs/imx6dl_mamoj_defconfig | 1 + configs/k2e_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/pxm2_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/rut_defconfig | 1 + configs/sniper_defconfig | 1 - configs/socrates_defconfig | 1 + configs/thuban_defconfig | 1 + drivers/block/Kconfig | 2 +- drivers/usb/Kconfig| 14 +- drivers/usb/cdns3/Kconfig | 2 +- drivers/usb/dwc3/Kconfig | 2 +- drivers/usb/emul/Kconfig | 4 +++- drivers/usb/gadget/Kconfig | 2 ++ drivers/usb/host/Kconfig | 20 ++-- drivers/usb/mtu3/Kconfig | 2 +- drivers/usb/musb-new/Kconfig | 13 - 28 files changed, 51 insertions(+), 45 deletions(-) diff --git a/Makefile b/Makefile index 0d3192cebade..6fa83bfca0dd 100644 --- a/Makefile +++ b/Makefile @@ -1118,8 +1118,6 @@ ifneq ($(CONFIG_DM),y) @echo >&2 "See doc/driver-model/migration.rst for more info." @echo >&2 "" endif - $(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\ - USB,v2019.07,$(CONFIG_USB)) $(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI)) $(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\ $(CONFIG_LCD)$(CONFIG_VIDEO)) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7f493a8e8fd6..9de97cc10152 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -984,7 +984,7 @@ config ARCH_SUNXI select BINMAN select CMD_GPIO select CMD_MMC if MMC - select CMD_USB if DISTRO_DEFAULTS + select CMD_USB if DISTRO_DEFAULTS && USB_HOST select CLK select DM select DM_ETH @@ -993,7 +993,6 @@ config ARCH_SUNXI select DM_MMC if MMC select DM_SCSI if SCSI select DM_SERIAL - select DM_USB if DISTRO_DEFAULTS select GPIO_EXTRA_HEADER select OF_BOARD_SETUP select OF_CONTROL @@ -1006,8 +1005,8 @@ config ARCH_SUNXI select SYS_NS16550 select SYS_THUMB_BUILD if !ARM64 select USB if DISTRO_DEFAULTS - select USB_KEYBOARD if DISTRO_DEFAULTS - select USB_STORAGE if DISTRO_DEFAULTS + select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST + select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST select SPL_USE_TINY_PRINTF select USE_PREBOOT select SYS_RELOC_GD_ENV_ADDR @@ -1035,7 +1034,6 @@ config ARCH_U8500 select DM_GPIO select DM_MMC if MMC select DM_SERIAL - select DM_USB if USB select OF_CONTROL select SYSRESET select TIMER @@ -1078,7 +1076,6 @@ config ARCH_ZYNQ select DM_SERIAL select DM_SPI select DM_SPI_FLASH - select DM_USB if USB select GPIO_EXTRA_HEADER select OF_CONTR
Re: [PATCH v3 13/20] ARM: dts: k3-j721e: Add the entries required for USB3 support on USB0
On Fri, Jul 09, 2021 at 07:36:45PM +0530, Kishon Vijay Abraham I wrote: > Hi Tom, > > On 07/05/21 10:44 pm, Tom Rini wrote: > > On Tue, May 04, 2021 at 04:11:48PM +0530, Kishon Vijay Abraham I wrote: > > > >> Partially sync with Linux's dts to add the entries required for USB3 > >> support on USB0. > >> Note that the default mode is still "peripheral" not "host". USB3 is > >> supported only for the host mode. > >> > >> Signed-off-by: Jean-Jacques Hiblot > >> Signed-off-by: Vignesh Raghavendra > >> Signed-off-by: Kishon Vijay Abraham I > >> --- > >> .../k3-j721e-common-proc-board-u-boot.dtsi| 19 ++- > >> 1 file changed, 18 insertions(+), 1 deletion(-) > > > > You're doing a partial sync with Linux in the -u-boot.dtsi file, why? > > This only changes the part that deals with USB. Other's will be added as > when it's getting tested and verified in u-boot. I would really really like to see the files be fully re-synced. I'm not NAK'ing this, but it's also a bad idea to pass Linux old/mismatched dtb files. Which you can do trivially with `bootefi`. So it's a bad idea. -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 19/20] env: ti: j721e-evm: Add env variable to power on & reset QSGMII PHY in J7200 EVM
Hi Tom,
On 11/05/21 8:03 pm, Tom Rini wrote:
> On Tue, May 11, 2021 at 07:28:10PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Tom,
>>
>> On 07/05/21 10:44 pm, Tom Rini wrote:
>>> On Tue, May 04, 2021 at 04:11:54PM +0530, Kishon Vijay Abraham I wrote:
>>>
MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII
operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN
controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1"
on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22),
PIN: 18.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Suman Anna
---
include/configs/j721e_evm.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index b707fc4e89..00d0a18a68 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -139,11 +139,24 @@
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
\
+ "do_main_cpsw0_qsgmii_phyinit=1\0" \
>>>
>>> When would this be not true?
>>
>> If the user don't want to use QSGMII, this could be set to false. For
>> instance the SERDES in J7200 can be used such that it can be used with
>> two protocols at a time. So it can be either PCIe + QSGMII or PCIe +
>> USB. So for use cases which require PCIe + USB, this could be set to false.
>
> Then we need to create doc/board/ti/j721e_evm.rst with some general
> content and then document the above in there.
There is already a document @ board/ti/j721e/README which has some
general information. Maybe that could be updated and moved to
doc/board/ti/j721e_evm.rst?
Thanks
Kishon
>
+ "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
+ "gpio clear gpio@22_16\0" \
+ "main_cpsw0_qsgmii_phyinit="\
+ "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
-eq 1 && " \
+ "test ${boot} = mmc; then " \
>>>
>>> And why only on mmc?
>>
>> The current J7200 u-boot code loads firmwares for remote cores only from
>> MMC. So if it's not mmc, it's not going to load ethernet firmware and
>> hence not required to configure the PHY.
>
> OK. Please make sure this is also part of the documentation. Thanks.
>
Re: [PATCH v3 19/20] env: ti: j721e-evm: Add env variable to power on & reset QSGMII PHY in J7200 EVM
On Fri, Jul 09, 2021 at 08:02:03PM +0530, Kishon Vijay Abraham I wrote: > Hi Tom, > > On 11/05/21 8:03 pm, Tom Rini wrote: > > On Tue, May 11, 2021 at 07:28:10PM +0530, Kishon Vijay Abraham I wrote: > >> Hi Tom, > >> > >> On 07/05/21 10:44 pm, Tom Rini wrote: > >>> On Tue, May 04, 2021 at 04:11:54PM +0530, Kishon Vijay Abraham I wrote: > >>> > MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII > operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN > controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1" > on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22), > PIN: 18. > > Signed-off-by: Kishon Vijay Abraham I > Reviewed-by: Suman Anna > --- > include/configs/j721e_evm.h | 16 +++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h > index b707fc4e89..00d0a18a68 100644 > --- a/include/configs/j721e_evm.h > +++ b/include/configs/j721e_evm.h > @@ -139,11 +139,24 @@ > #endif /* CONFIG_TARGET_J721E_A72_EVM */ > > #ifdef CONFIG_TARGET_J7200_A72_EVM > +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY > \ > +"do_main_cpsw0_qsgmii_phyinit=1\0" > \ > >>> > >>> When would this be not true? > >> > >> If the user don't want to use QSGMII, this could be set to false. For > >> instance the SERDES in J7200 can be used such that it can be used with > >> two protocols at a time. So it can be either PCIe + QSGMII or PCIe + > >> USB. So for use cases which require PCIe + USB, this could be set to false. > > > > Then we need to create doc/board/ti/j721e_evm.rst with some general > > content and then document the above in there. > > There is already a document @ board/ti/j721e/README which has some > general information. Maybe that could be updated and moved to > doc/board/ti/j721e_evm.rst? Yes, board/*/boardname/README should be converted to doc/board/*/boardname.rst in geneal. -- Tom signature.asc Description: PGP signature
[PATCH] Makefile: add support to build dedicated devicetree
Add the support to build a dedicated devicetree located in arch/$(ARCH)/dts This devicetree does not need to be listed in the relevant devicetree makefile. Just run the following command to build the foo devicetree placed before at the right path: $ make foo.dtb Signed-off-by: Kory Maincent --- Makefile | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Makefile b/Makefile index 027e31e09e..2ebeaee515 100644 --- a/Makefile +++ b/Makefile @@ -1136,6 +1136,12 @@ dtbs: dts/dt.dtb dts/dt.dtb: u-boot $(Q)$(MAKE) $(build)=dts dtbs +ifneq ($(wildcard $(srctree)/arch/$(ARCH)/dts/),) +dtstree := arch/$(ARCH)/dts +%.dtb: u-boot + $(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@ +endif + quiet_cmd_copy = COPY$@ cmd_copy = cp $< $@ -- 2.25.1
[PATCH] Kconfig.boot: Make 0x0 the default SYS_TEXT_BASE for POSITION_INDEPENDENT
When we build U-Boot with POSITION_INDEPENDENT we must have SYS_TEXT_BASE be set to zero. Make this the default in that case. Signed-off-by: Tom Rini --- common/Kconfig.boot | 1 + 1 file changed, 1 insertion(+) diff --git a/common/Kconfig.boot b/common/Kconfig.boot index 89a3161f1faa..f078743f06ed 100644 --- a/common/Kconfig.boot +++ b/common/Kconfig.boot @@ -358,6 +358,7 @@ config HAVE_SYS_TEXT_BASE config SYS_TEXT_BASE depends on HAVE_SYS_TEXT_BASE + default 0x0 if POSITION_INDEPENDENT default 0x8080 if ARCH_OMAP2PLUS || ARCH_K3 default 0x4a00 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S default 0x2a00 if ARCH_SUNXI && MACH_SUN9I -- 2.17.1
Re: [PATCH v3 2/9] arm: dts: imx8mp: Add common u-boot dtsi
On Wed, Jul 7, 2021 at 5:58 AM Teresa Remmet wrote:
>
> Factor out the common node settings for dm-spl and dm-pre-reloc
> and move them to imx8mp-u-boot.dtsi
>
> Signed-off-by: Teresa Remmet
> Reviewed-by: Fabio Estevam
> Reviewed-by: Heiko Schocher
> ---
> Changes in v3:
> - Moved binman nodes to common imx8mp-u-boot.dtsi
> Changes in v2:
> - none
>
> arch/arm/dts/imx8mp-evk-u-boot.dtsi | 143 +
> .../imx8mp-phyboard-pollux-rdk-u-boot.dtsi| 39 +
> arch/arm/dts/imx8mp-u-boot.dtsi | 149 ++
> 3 files changed, 153 insertions(+), 178 deletions(-)
> create mode 100644 arch/arm/dts/imx8mp-u-boot.dtsi
>
> diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> index 4162f41cffb6..2abcf1f03d4f 100644
> --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> @@ -3,11 +3,9 @@
> * Copyright 2019 NXP
> */
>
> -/ {
> - binman: binman {
> - multiple-images;
> - };
> +#include "imx8mp-u-boot.dtsi"
>
> +/ {
> wdt-reboot {
> compatible = "wdt-reboot";
> wdt = <&wdog1>;
> @@ -21,43 +19,6 @@
> };
> };
>
> -&{/soc@0} {
> - u-boot,dm-pre-reloc;
> - u-boot,dm-spl;
> -};
> -
> -&clk {
> - u-boot,dm-spl;
> - u-boot,dm-pre-reloc;
> -};
> -
> -&osc_32k {
> - u-boot,dm-spl;
> - u-boot,dm-pre-reloc;
> -};
> -
> -&osc_24m {
> - u-boot,dm-spl;
> - u-boot,dm-pre-reloc;
> -};
> -
> -&aips1 {
> - u-boot,dm-spl;
> - u-boot,dm-pre-reloc;
> -};
> -
> -&aips2 {
> - u-boot,dm-spl;
> -};
> -
> -&aips3 {
> - u-boot,dm-spl;
> -};
> -
> -&iomuxc {
> - u-boot,dm-spl;
> -};
> -
> ®_usdhc2_vmmc {
> u-boot,off-on-delay-us = <2>;
> };
> @@ -156,104 +117,4 @@
> phy-reset-post-delay = <100>;
> };
>
> -&binman {
> -u-boot-spl-ddr {
> - filename = "u-boot-spl-ddr.bin";
> - pad-byte = <0xff>;
> - align-size = <4>;
> - align = <4>;
>
> - u-boot-spl {
> - align-end = <4>;
> - };
> -
> - blob_1: blob-ext@1 {
> - filename = "lpddr4_pmu_train_1d_imem_202006.bin";
> - size = <0x8000>;
> - };
> -
> - blob_2: blob-ext@2 {
> - filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
> - size = <0x4000>;
> - };
> -
> - blob_3: blob-ext@3 {
> - filename = "lpddr4_pmu_train_2d_imem_202006.bin";
> - size = <0x8000>;
> - };
> -
> - blob_4: blob-ext@4 {
> - filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
> - size = <0x4000>;
> - };
> - };
> -
> -
> - flash {
> - mkimage {
> - args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
> 0x92";
> -
> - blob {
> - filename = "u-boot-spl-ddr.bin";
> - };
> - };
> - };
> -
> - itb {
> - filename = "u-boot.itb";
> -
> - fit {
> - description = "Configuration to load ATF before
> U-Boot";
> - #address-cells = <1>;
> - fit,external-offset = ;
> -
> - images {
> - uboot {
> - description = "U-Boot (64-bit)";
> - type = "standalone";
> - arch = "arm64";
> - compression = "none";
> - load = ;
> -
> - uboot_blob: blob-ext {
> - filename = "u-boot-nodtb.bin";
> - };
> - };
> -
> - atf {
> - description = "ARM Trusted Firmware";
> - type = "firmware";
> - arch = "arm64";
> - compression = "none";
> - load = <0x97>;
> - entry = <0x97>;
> -
> - atf_blob: blob-ext {
> - filename = "bl31.bin";
> - };
> - };
> -
> - fdt {
> - description = "NAME";
> - type = "flat_dt";
> -
Re: [PATCH u-boot-mvebu 00/31] kwboot / kwbimage improvements
Hi Marek, Pali,
On Thu, Jul 08 2021, Marek Behún wrote:
> Hi Stefan and others,
>
> this is a series of improvements to kwboot, kwbimage and mvebu.
>
> The main goal of this series is to correctly use BootROM's code
> for loading U-Boot from NOR / NAND: currently only SPL is read by
> BootROM and the main U-Boot is read by SPL. By using BootROM to also
> load main U-Boot we can reduce the size of SPL image, since it does
> not need to contain code for reading NOR / NAND.
>
> Before merging, this series should be tested on as many relevant
> boards as possible.
Is this series available for pull at a public git repo? If not, what
commit is this series based on?
What platforms have you tested?
baruch
> Marek Behún (2):
> tools: kwbimage: Add constant for SDIO bootfrom
> tools: kwbimage: Cosmetic fix - remove redundant space character
>
> Pali Rohár (29):
> tools: kwbimage: Fix compilation without CONFIG_SYS_U_BOOT_OFFS
> tools: kwbimage: Simplify aligning and calculating checksum
> tools: kwbimage: Align SPI and NAND images to 256 bytes
> tools: kwbimage: Fix generation of SATA, SDIO and PCIe images
> tools: kwbimage: Don't crash when binary file name does not contain
> '/'
> tools: kwbimage: Fix check for v0 extended header checksum
> tools: kwbimage: Validate extended headers of v1 images
> tools: kwbimage: Validate data checksum of v1 images
> tools: kwbimage: Print size of binary header in
> kwbimage_print_header()
> tools: kwboot: Fix wrong parameter passed to read()
> tools: kwboot: Fix restoring terminal
> tools: kwboot: Print trailing newline after terminal is terminated
> tools: kwboot: Cosmetic fix - add missing curly brackets
> tools: kwboot: Check for v1 header size
> tools: kwbimage: Use -a parameter (load address) for v1 images
> arm: mvebu: Fix return_to_bootrom()
> arm: mvebu: Mark return_to_bootrom() as a noreturn function
> arm: mvebu: Implement return_to_bootrom() via U-Boot's SPL framework
> arm: mvebu: Use U-Boot's SPL BootROM framework for booting from
> NAND/UART
> arm: mvebu: Always use BootROM for loading the rest of U-Boot's binary
> arm: mvebu: gdsys: Remove custom spl_board_init()
> arm: mvebu: Remove legacy U-Boot header from kwbimage v1 files
> tools: kwbimage: Remove v1 kwbimage SPL padding to
> CONFIG_SYS_U_BOOT_OFFS bytes
> arm: mvebu: Remove unused macro CONFIG_SYS_U_BOOT_OFFS
> tools: kwbimage: Add support for more BINARY headers
> tools: kwbimage: Don't parse PAYLOAD keyword
> tools: kwbimage: Add support for DATA command also for v1 images
> tools: kwbimage: Add support for a new DATA_DELAY command
> tools: kwbimage: Do not hide usage of secure header under
> CONFIG_ARMADA_38X
>
> Makefile | 2 +-
> arch/arm/mach-mvebu/Kconfig| 16 +-
> arch/arm/mach-mvebu/include/mach/cpu.h | 2 +-
> arch/arm/mach-mvebu/lowlevel_spl.S | 3 +-
> arch/arm/mach-mvebu/spl.c | 90 +--
> board/gdsys/a38x/Makefile | 2 +-
> board/gdsys/a38x/spl.c | 20 --
> include/configs/clearfog.h | 6 +-
> include/configs/controlcenterdc.h | 8 +-
> include/configs/db-88f6720.h | 3 -
> include/configs/db-88f6820-amc.h | 5 -
> include/configs/db-88f6820-gp.h| 6 -
> include/configs/db-mv784mp-gp.h| 3 -
> include/configs/ds414.h| 5 -
> include/configs/helios4.h | 6 +-
> include/configs/theadorable.h | 3 -
> include/configs/turris_omnia.h | 6 -
> include/configs/x530.h | 3 -
> scripts/config_whitelist.txt | 1 -
> tools/Makefile | 8 -
> tools/kwbimage.c | 339 +
> tools/kwbimage.h | 30 ++-
> tools/kwboot.c | 14 +-
> 23 files changed, 296 insertions(+), 285 deletions(-)
> delete mode 100644 board/gdsys/a38x/spl.c
--
~. .~ Tk Open Systems
=}ooO--U--Ooo{=
- bar...@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
[PATCH u-boot-mvebu 1/2] arm: mvebu: turris_omnia: force 40 MHz speed on SPI NOR
Commit e2e95e5e2542 ("spi: Update speed/mode on change") changed the
boot time on Turris Omnia from ~2.3s to over 8s, due to SPL loading main
U-Boot from SPI NOR at 1 MHz instead of 40 MHz.
This is because the SPL code passes the CONFIG_SF_DEFAULT_SPEED option
to spi_flash_probe(), and with the above commit spi_flash_probe() starts
prefering this parameter instead of the one specified in device-tree.
The proper solution here would probably be to fix the SF subsystem to
prefer the frequency specified in the device-tree, if it is present, but
I am not sure what else will be affected on other boards with such a
change. So until then we need a more simple fix.
Since the CONFIG_SF_DEFAULT_SPEED option is used by the code, put the
correct value there for Turris Omnia. Also put the correct value to
CONFIG_SF_DEFAULT_MODE and use 40 MHz when reading environment.
Signed-off-by: Marek Behún
Cc: Stefan Roese
Cc: Tom Rini
Cc: Marek Vasut
Cc: Jagan Teki
Cc: Patrick Delaunay
Cc: Pali Rohár
---
configs/turris_omnia_defconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 57ab384f63..ec2294699f 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -56,7 +56,7 @@ CONFIG_CMD_FS_UUID=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=5000
+CONFIG_ENV_SPI_MAX_HZ=4000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_AHCI_PCI=y
@@ -67,6 +67,8 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=4000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
--
2.31.1
[PATCH u-boot-mvebu 2/2] arm: mvebu: turris_{omnia, mox}: enable MTD command
Now that the MTD subsystem properly supports OF partitions of a SPI NOR, we can enable the MTD command and start using it instead of the deprecated sf command. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Pali Rohár --- configs/turris_mox_defconfig | 3 +++ configs/turris_omnia_defconfig | 4 2 files changed, 7 insertions(+) diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 2c6f4938db..34127dc3e6 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -60,12 +61,14 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index ec2294699f..f860cf5e7d 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_LZMADEC=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_SATA=y CONFIG_CMD_SPI=y @@ -65,8 +66,11 @@ CONFIG_AHCI_MVEBU=y CONFIG_DM_PCA953X=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MV=y +CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MTD=y CONFIG_SF_DEFAULT_MODE=0x0 CONFIG_SF_DEFAULT_SPEED=4000 CONFIG_PHY_MARVELL=y -- 2.31.1
Re: [PATCH u-boot-mvebu 00/31] kwboot / kwbimage improvements
On Fri, 09 Jul 2021 17:54:25 +0300 Baruch Siach wrote: > Hi Marek, Pali, > > On Thu, Jul 08 2021, Marek Behún wrote: > > Hi Stefan and others, > > > > this is a series of improvements to kwboot, kwbimage and mvebu. > > > > The main goal of this series is to correctly use BootROM's code > > for loading U-Boot from NOR / NAND: currently only SPL is read by > > BootROM and the main U-Boot is read by SPL. By using BootROM to also > > load main U-Boot we can reduce the size of SPL image, since it does > > not need to contain code for reading NOR / NAND. > > > > Before merging, this series should be tested on as many relevant > > boards as possible. > > Is this series available for pull at a public git repo? If not, what > commit is this series based on? > > What platforms have you tested? Based on current u-boot master, commit fd075f77ca56ffb07e0b1979f0cb47fc8831600f Tested only on Turris Omnia (Armada 385). Marek
Re: [PATCH u-boot-mvebu 1/2] arm: mvebu: turris_omnia: force 40 MHz speed on SPI NOR
On Fri, 9 Jul 2021 16:56:13 +0200
Marek Behún wrote:
> Commit e2e95e5e2542 ("spi: Update speed/mode on change") changed the
> boot time on Turris Omnia from ~2.3s to over 8s, due to SPL loading
> main U-Boot from SPI NOR at 1 MHz instead of 40 MHz.
>
> This is because the SPL code passes the CONFIG_SF_DEFAULT_SPEED option
> to spi_flash_probe(), and with the above commit spi_flash_probe()
> starts prefering this parameter instead of the one specified in
> device-tree.
>
> The proper solution here would probably be to fix the SF subsystem to
> prefer the frequency specified in the device-tree, if it is present,
> but I am not sure what else will be affected on other boards with
> such a change. So until then we need a more simple fix.
>
> Since the CONFIG_SF_DEFAULT_SPEED option is used by the code, put the
> correct value there for Turris Omnia. Also put the correct value to
> CONFIG_SF_DEFAULT_MODE and use 40 MHz when reading environment.
BTW this change is currently needed even if the other series (making
use of BootROM code to load main U-Boot instead of SPL doing it) is
accepted: commit e2e95e5e2542 also changed the behavior of the
sf read / sf update
command - it is slower since it operates at 1 MHz now instead of 40 MHz
as specified in the device-tree.
Marek
Re: [PATCH] Kconfig.boot: Make 0x0 the default SYS_TEXT_BASE for POSITION_INDEPENDENT
> From: Tom Rini > Date: Fri, 9 Jul 2021 10:39:21 -0400 > > When we build U-Boot with POSITION_INDEPENDENT we must have > SYS_TEXT_BASE be set to zero. Make this the default in that case. Makes sense. I had to set this for the (still in progress) Apple M1 support. So: Reviewed-by: Mark Kettenis P.S. Any chance of picking up the first diff I sent a while ago that was acked by Marc Zyngier? https://patchwork.ozlabs.org/project/uboot/patch/20210210191456.25644-1-kette...@openbsd.org/ > Signed-off-by: Tom Rini > --- > common/Kconfig.boot | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/common/Kconfig.boot b/common/Kconfig.boot > index 89a3161f1faa..f078743f06ed 100644 > --- a/common/Kconfig.boot > +++ b/common/Kconfig.boot > @@ -358,6 +358,7 @@ config HAVE_SYS_TEXT_BASE > > config SYS_TEXT_BASE > depends on HAVE_SYS_TEXT_BASE > + default 0x0 if POSITION_INDEPENDENT > default 0x8080 if ARCH_OMAP2PLUS || ARCH_K3 > default 0x4a00 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S > default 0x2a00 if ARCH_SUNXI && MACH_SUN9I > -- > 2.17.1 > >
[PATCH u-boot-mvebu] arm: mvebu: armada-3720: remove unused config option
The config option CONFIG_DEBUG_UART_CLOCK is not used by Armada 3720's serial driver (it wasn't even before the recent update of that driver). Remove it. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Pali Rohár --- configs/mvebu_db-88f3720_defconfig | 1 - configs/mvebu_espressobin-88f3720_defconfig | 1 - configs/turris_mox_defconfig| 1 - configs/uDPU_defconfig | 1 - 4 files changed, 4 deletions(-) diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index c9935da102..ff4668e837 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db" CONFIG_DEBUG_UART_BASE=0xd0012000 -CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 157a4b7cb2..dc199cfe50 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin" CONFIG_DEBUG_UART_BASE=0xd0012000 -CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 2c6f4938db..b3458acb98 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox" CONFIG_DEBUG_UART_BASE=0xd0012000 -CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index cdf6b2274c..649248d74d 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -10,7 +10,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU" CONFIG_DEBUG_UART_BASE=0xd0012000 -CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -- 2.31.1
Re: [PATCH] Kconfig.boot: Make 0x0 the default SYS_TEXT_BASE for POSITION_INDEPENDENT
On Fri, Jul 09, 2021 at 05:02:19PM +0200, Mark Kettenis wrote: > > From: Tom Rini > > Date: Fri, 9 Jul 2021 10:39:21 -0400 > > > > When we build U-Boot with POSITION_INDEPENDENT we must have > > SYS_TEXT_BASE be set to zero. Make this the default in that case. > > Makes sense. I had to set this for the (still in progress) Apple M1 > support. So: > > Reviewed-by: Mark Kettenis > > > P.S. Any chance of picking up the first diff I sent a while ago that > was acked by Marc Zyngier? > > > https://patchwork.ozlabs.org/project/uboot/patch/20210210191456.25644-1-kette...@openbsd.org/ Ah that, yeah, I need to get a PR going of general ARM changes, I should do that today, thanks. -- Tom signature.asc Description: PGP signature
Re: [PATCH u-boot-mvebu] arm: mvebu: armada-3720: remove unused config option
On Friday 09 July 2021 17:27:02 Marek Behún wrote: > The config option CONFIG_DEBUG_UART_CLOCK is not used by Armada 3720's > serial driver (it wasn't even before the recent update of that driver). > > Remove it. > > Signed-off-by: Marek Behún > Cc: Stefan Roese > Cc: Pali Rohár Reviewed-by: Pali Rohár > --- > configs/mvebu_db-88f3720_defconfig | 1 - > configs/mvebu_espressobin-88f3720_defconfig | 1 - > configs/turris_mox_defconfig| 1 - > configs/uDPU_defconfig | 1 - > 4 files changed, 4 deletions(-) > > diff --git a/configs/mvebu_db-88f3720_defconfig > b/configs/mvebu_db-88f3720_defconfig > index c9935da102..ff4668e837 100644 > --- a/configs/mvebu_db-88f3720_defconfig > +++ b/configs/mvebu_db-88f3720_defconfig > @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db" > CONFIG_DEBUG_UART_BASE=0xd0012000 > -CONFIG_DEBUG_UART_CLOCK=25804800 This value was even incorrect as base clock is 25 MHz (not 25.8048 MHz). So it fine that unused and wrong value is going to be removed. > CONFIG_DEBUG_UART=y > CONFIG_AHCI=y > CONFIG_DISTRO_DEFAULTS=y > diff --git a/configs/mvebu_espressobin-88f3720_defconfig > b/configs/mvebu_espressobin-88f3720_defconfig > index 157a4b7cb2..dc199cfe50 100644 > --- a/configs/mvebu_espressobin-88f3720_defconfig > +++ b/configs/mvebu_espressobin-88f3720_defconfig > @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin" > CONFIG_DEBUG_UART_BASE=0xd0012000 > -CONFIG_DEBUG_UART_CLOCK=25804800 > CONFIG_DEBUG_UART=y > CONFIG_AHCI=y > CONFIG_DISTRO_DEFAULTS=y > diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig > index 2c6f4938db..b3458acb98 100644 > --- a/configs/turris_mox_defconfig > +++ b/configs/turris_mox_defconfig > @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox" > CONFIG_DEBUG_UART_BASE=0xd0012000 > -CONFIG_DEBUG_UART_CLOCK=25804800 > CONFIG_DEBUG_UART=y > CONFIG_OF_BOARD_FIXUP=y > CONFIG_DISTRO_DEFAULTS=y > diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig > index cdf6b2274c..649248d74d 100644 > --- a/configs/uDPU_defconfig > +++ b/configs/uDPU_defconfig > @@ -10,7 +10,6 @@ CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU" > CONFIG_DEBUG_UART_BASE=0xd0012000 > -CONFIG_DEBUG_UART_CLOCK=25804800 > CONFIG_DEBUG_UART=y > CONFIG_AHCI=y > CONFIG_DISTRO_DEFAULTS=y > -- > 2.31.1 >
Re: [PATCH u-boot-mvebu] arm: mvebu: armada-3720: remove unused config option
Please ignore this. It seems that the option is needed, because it does not have a default. A different way to solve this is needed. Will post another patch. Marek
[PATCH u-boot-mvebu v2] arm: mvebu: armada-3720: remove unused config option
The config option CONFIG_DEBUG_UART_CLOCK is not used by Armada 3720's serial driver (it wasn't even before the recent update of that driver). Even if it was used, the value was incorrect (the frequency of the clock is 25 MHz, not 25.8048 MHz). Remove it from config files and set the default value to 0. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Pali Rohár --- Change since v1: - we also need to specify a default value for this variable in Kconfig, otherwise the make command will ask for a value. Use 0 for the default value since it is not used - updated commit message --- configs/mvebu_db-88f3720_defconfig | 1 - configs/mvebu_espressobin-88f3720_defconfig | 1 - configs/turris_mox_defconfig| 1 - configs/uDPU_defconfig | 1 - drivers/serial/Kconfig | 1 + 5 files changed, 1 insertion(+), 4 deletions(-) diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index c9935da102..ff4668e837 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db" CONFIG_DEBUG_UART_BASE=0xd0012000 -CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 157a4b7cb2..dc199cfe50 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin" CONFIG_DEBUG_UART_BASE=0xd0012000 -CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 2c6f4938db..b3458acb98 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox" CONFIG_DEBUG_UART_BASE=0xd0012000 -CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index cdf6b2274c..649248d74d 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -10,7 +10,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU" CONFIG_DEBUG_UART_BASE=0xd0012000 -CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 961e3fb031..93348c0929 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -443,6 +443,7 @@ config DEBUG_UART_CLOCK int "UART input clock" depends on DEBUG_UART default 0 if DEBUG_UART_SANDBOX + default 0 if DEBUG_MVEBU_A3700_UART help The UART input clock determines the speed of the internal UART circuitry. The baud rate is derived from this by dividing the input -- 2.31.1
Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages
Please find my replies To Julius's question: Just to clarify: are you using "bloblist" as a general term for the concept of a simple linked list of tagged data blobs, or to refer specifically to the U-Boot implementation with that name? The existing TF-A implementation (bl_aux_params) is basically identical in concept to the U-Boot bloblist, but not binary compatible. Are we talking about just keeping that, or throwing it away in order to reimplement the exact structure U-Boot is using? (I would prefer to keep the bl_aux_params as they are to avoid disrupting existing uses, of course. Making backwards-incompatible changes to an interface that passes across multiple repos and firmware components is always a big pain.) - "bloblist" is a general term for concept of linked list and it's not exactly U-boot implementation. The proposed solution will cause some degree of changes in all the participating projects. For backward compatibility issue, we have already though about it and proposed to have build configs which will be enabled by platform integrators. To Daniel's question: In short are you confident adopting a mantra of "it doesn't exist unless it's upstreamed" is sufficient? - "If it is not upstreamed we don't know if it exists or not?", Since we can't know/control what all are hidden in closed sources, so we are only concentrating on open sources. Finally, We are trying to solve a problem(in a standard way) which is already solved in different projects differently. To have a common solution acceptable to all, changes in participating projects are inevitable. Once we get agreement in principle, we should be ready to have some changes in the codebase. The TF-A project is willing to put effort to put something out there that will enable other projects, but we need some degree of assurances that proposed changes will be accepted in other projects also. Thanks Manish From: Daniel Thompson Sent: 09 July 2021 11:07 To: François Ozog Cc: Julius Werner ; Ed Stuber ; Boot Architecture Mailman List ; undefined ; Harb Abdulhamid OS ; Simon Glass ; Arjun Khare ; U-Boot Mailing List ; t...@lists.trustedfirmware.org ; Paul Isaac's ; Ron Minnich ; Moe Ammar ; Manish Pandey2 Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages On Fri, Jul 09, 2021 at 09:05:09AM +0200, François Ozog wrote: > Le ven. 9 juil. 2021 à 03:09, Julius Werner a écrit : > > > > Of course every project would like not to change... > > > > > > For TF-A I wonder whether it will/should in fact use devicetree if there > > is a lot of complex data? TBD, I suppose. > > > > Okay, sorry, now I'm a bit confused -- I thought the discussion in > > this thread was about which parameter hand-off mechanism to use *for > > TF-A*? Or did it shift to discuss other projects in the meantime (I > > didn't always follow it closely)? I think it started with the UEFI > > guys wanting to implement a HOB format to interface with TF-A, and I > > think we now concluded that they're okay with using a simple parameter > > list instead (and wrapping their custom HOBs into a parameter blob > > that contains their UUID and everything else in the data part). > > > > So for TF-A, if the decision is that we want a parameter list, I think > > it makes sense to keep using the format that has already been there > > and in use for several years, and define new tags for the UEFI HOB use > > case in that. I don't really see a reason to switch TF-A and all other > > projects currently interfacing with it that way (e.g. coreboot) to > > something only used by U-Boot right now, if they're practically > > identical in concept. > > Looking at bl_au_params: used by 3 SoCs to deal with gpio and serial. I presume this analysis only covers those SoCs where someone (vendor, customer, community) has upstreamed their TF-A implementation? It is only relatively recently[1] that the TF-A CLA requirements that inhibited upstreaming were relaxed. Additionally the current silicon supply crunch is forcing board designers to second (third and forth) source critical components which can drive usage of firmware parameter passing. In short are you confident adopting a mantra of "it doesn't exist unless it's upstreamed" is sufficient? Daniel. [1] Perhaps not that recent if measured in years... but certainly recent relative to firmware life cycles! > Migration may not be that a big effort (handful lines of code?). The > key thing is that the biggest consumer of them are BL33 and a little > bit by some OS drivers (OS itself shall not be a consumer). U-Boot > has an established mechanism which is used in particular on all chrome > books in both x86 and Arm environments. I have the impression that > U-Boot is the typical BL33 so I would import the mechanism into TFA, > not the other way round. EDK2 has typically its own code for TFA > matters and may just import BL31, so
Re: [PATCH] arm64: Update memcpy_{from, to}io() helpers
On Fri, Feb 26, 2021 at 01:44:51PM +0100, Patrice Chotard wrote:
> At early U-Boot stage, before relocation, MMU is not yet configured
> and disabled. DDR may not be configured with the correct memory
> attributes (can be configured in MT_DEVICE instead of MT_MEMORY).
>
> In this case, usage of memcpy_{from, to}io() may leads to synchronous
> abort in AARCH64 in case the normal memory address is not 64Bits aligned.
>
> To avoid such situation, forbid usage of normal memory cast to (u64 *) in
> case MMU is not enabled.
>
> Signed-off-by: Patrice Chotard
> Cc: mark.kette...@xs4all.nl
> Reviewed-by: Patrick Delaunay
Sorry for the delay. If this is still needed, you'll need to address
the build failures on platforms such as cgtqmx8:
+(cgtqmx8) board/congatec/cgtqmx8/cgtqmx8.c:377:6: error: conflicting types for
'reset_cpu'
+(cgtqmx8) void reset_cpu(ulong addr)
+(cgtqmx8) ^
+(cgtqmx8) In file included from arch/arm/include/asm/io.h:341:0,
+(cgtqmx8) from board/congatec/cgtqmx8/cgtqmx8.c:12:
+(cgtqmx8) include/cpu_func.h:88:6: note: previous declaration of 'reset_cpu'
was here
+(cgtqmx8) void reset_cpu(void);
that are introduced with this patch. Thanks.
--
Tom
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Re: [PATCH u-boot-mvebu 1/2] arm: mvebu: turris_omnia: force 40 MHz speed on SPI NOR
On Fri, Jul 09, 2021 at 05:00:09PM +0200, Marek Behún wrote:
> On Fri, 9 Jul 2021 16:56:13 +0200
> Marek Behún wrote:
>
> > Commit e2e95e5e2542 ("spi: Update speed/mode on change") changed the
> > boot time on Turris Omnia from ~2.3s to over 8s, due to SPL loading
> > main U-Boot from SPI NOR at 1 MHz instead of 40 MHz.
> >
> > This is because the SPL code passes the CONFIG_SF_DEFAULT_SPEED option
> > to spi_flash_probe(), and with the above commit spi_flash_probe()
> > starts prefering this parameter instead of the one specified in
> > device-tree.
> >
> > The proper solution here would probably be to fix the SF subsystem to
> > prefer the frequency specified in the device-tree, if it is present,
> > but I am not sure what else will be affected on other boards with
> > such a change. So until then we need a more simple fix.
> >
> > Since the CONFIG_SF_DEFAULT_SPEED option is used by the code, put the
> > correct value there for Turris Omnia. Also put the correct value to
> > CONFIG_SF_DEFAULT_MODE and use 40 MHz when reading environment.
>
> BTW this change is currently needed even if the other series (making
> use of BootROM code to load main U-Boot instead of SPL doing it) is
> accepted: commit e2e95e5e2542 also changed the behavior of the
> sf read / sf update
> command - it is slower since it operates at 1 MHz now instead of 40 MHz
> as specified in the device-tree.
Ugh. This is the second bit of unexpected fall-out from that change.
Since it's the start now of the merge window, no point in reverting the
change now. Sorry about that!
--
Tom
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RE: [PATCHv2 2/4] tegra: Test on CONFIG_CMD_USB being enabled for distro bootcmd
Acked-by twar...@nvidia.com -Original Message- From: Tom Rini Sent: Friday, July 9, 2021 7:12 AM To: u-boot@lists.denx.de Cc: Tom Warren Subject: [PATCHv2 2/4] tegra: Test on CONFIG_CMD_USB being enabled for distro bootcmd External email: Use caution opening links or attachments Reuse the common logic to allow for BOOT_TARGET_DEVICES to list USB as a possibility if we're building for a platform that will have USB but not if we don't, so that we don't hit the link-time check for trying to have USB boot on a non-USB system. Cc: Tom Warren Signed-off-by: Tom Rini --- Changes in v2: - New patch. This problem shows up later in the series when we stop building USB framework without a host controller of some sort also enabled. --- include/configs/tegra-common-post.h | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index fae0e761fb42..dd7a75ae4674 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -21,11 +21,18 @@ #define CONFIG_SYS_NONCACHED_MEMORY(1 << 20) /* 1 MiB */ #ifndef CONFIG_SPL_BUILD + +#if CONFIG_IS_ENABLED(CMD_USB) +# define BOOT_TARGET_USB(func) func(USB, usb, 0) #else # define +BOOT_TARGET_USB(func) #endif + #ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ - func(USB, usb, 0) \ + BOOT_TARGET_USB(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) #endif -- 2.17.1
Re: [PATCH] get_maintainer.pl: update from Linux kernel v5.13-rc6
On Thu, Jul 08, 2021 at 08:22:35AM -0400, Trevor Woerner wrote: > ping? > > Tom, have you had a chance to try out this update? Thanks, I need to do a build/related PR shortly and I'll pick this up then. > > On Tue, Jun 15, 2021 at 3:30 AM Trevor Woerner wrote: > > > Update U-Boot's version of scripts/get_maintainer.pl to sync it up with > > the > > latest changes to the Linux kernel's version of the same script. > > > > The last sync was with Linux kernel version v4.16. The commits to the > > kernel's > > get_maintainer.pl since then (starting with the most recent) are: > > > > 6343f6b71f83 get_maintainer: exclude MAINTAINERS file(s) from > > --git-fallback > > cdfe2d220476 get_maintainer: add test for file in VCS > > e33c9fe8b80c get_maintainer: fix unexpected behavior for > > path/to//file (double slashes) > > 0c78c0137621 get_maintainer: add email addresses from .yaml files > > 0ef82fcefb99 scripts/get_maintainer.pl: deprioritize old Fixes: > > addresses > > ef0c08192ac0 get_maintainer: remove uses of P: for maintainer name > > 2f5bd343694e scripts/get_maintainer.pl: add signatures from > > Fixes: lines in commit message > > 49662503e8e4 get_maintainer: add ability to skip moderated mailing > > lists > > 0fbd75fd7fee get_maintainer: allow option --mpath to > > read all files in > > 5f0baf95b1ed get_maintainer.pl: add -mpath= for > > MAINTAINERS file location > > 31bb82c9caa9 get_maintainer: allow usage outside of kernel tree > > 0455c74788fd get_maintainer: improve patch recognition > > 882ea1d64eb3 scripts: use SPDX tag in get_maintainer and checkpatch > > > > Signed-off-by: Trevor Woerner > > --- > > scripts/get_maintainer.pl | 204 +- > > 1 file changed, 134 insertions(+), 70 deletions(-) > > > > diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl > > index e3b41616c9..81116e215e 100755 > > --- a/scripts/get_maintainer.pl > > +++ b/scripts/get_maintainer.pl > > @@ -1,4 +1,6 @@ > > #!/usr/bin/env perl > > +# SPDX-License-Identifier: GPL-2.0 > > +# > > # (c) 2007, Joe Perches > > # created from checkpatch.pl > > # > > @@ -7,8 +9,6 @@ > > # > > # usage: perl scripts/get_maintainer.pl [OPTIONS] > > #perl scripts/get_maintainer.pl [OPTIONS] -f > > -# > > -# Licensed under the terms of the GNU GPL License version 2 > > > > use warnings; > > use strict; > > @@ -19,6 +19,7 @@ my $V = '0.26'; > > use Getopt::Long qw(:config no_auto_abbrev); > > use Cwd; > > use File::Find; > > +use File::Spec::Functions; > > > > my $cur_path = fastgetcwd() . '/'; > > my $lk_path = "./"; > > @@ -26,7 +27,9 @@ my $email = 1; > > my $email_usename = 1; > > my $email_maintainer = 1; > > my $email_reviewer = 1; > > +my $email_fixes = 1; > > my $email_list = 1; > > +my $email_moderated_list = 1; > > my $email_subscriber_list = 0; > > my $email_git_penguin_chiefs = 0; > > my $email_git = 0; > > @@ -48,24 +51,31 @@ my $output_roles = 0; > > my $output_rolestats = 1; > > my $output_section_maxlen = 50; > > my $scm = 0; > > +my $tree = 1; > > my $web = 0; > > my $subsystem = 0; > > my $status = 0; > > my $letters = ""; > > my $keywords = 1; > > my $sections = 0; > > -my $file_emails = 0; > > +my $email_file_emails = 0; > > my $from_filename = 0; > > my $pattern_depth = 0; > > my $self_test = undef; > > my $version = 0; > > my $help = 0; > > -my $find_maintainer_files = 1; > > - > > +my $find_maintainer_files = 0; > > +my $maintainer_path; > > my $vcs_used = 0; > > > > my $exit = 0; > > > > +my @files = (); > > +my @fixes = ();# If a patch description includes > > Fixes: lines > > +my @range = (); > > +my @keyword_tvi = (); > > +my @file_emails = (); > > + > > my %commit_author_hash; > > my %commit_signer_hash; > > > > @@ -245,6 +255,8 @@ if (!GetOptions( > > 'r!' => \$email_reviewer, > > 'n!' => \$email_usename, > > 'l!' => \$email_list, > > + 'fixes!' => \$email_fixes, > > + 'moderated!' => \$email_moderated_list, > > 's!' => \$email_subscriber_list, > > 'multiline!' => \$output_multiline, > > 'roles!' => \$output_roles, > > @@ -253,14 +265,16 @@ if (!GetOptions( > > 'subsystem!' => \$subsystem, > > 'status!' => \$status, > > 'scm!' => \$scm, > > + 'tree!' => \$tree, > > 'web!' => \$web, > > 'letters=s' => \$letters, > > 'pattern-depth=i' => \$pattern_depth, > > 'k|keywords!' => \$keywords, > > 'sections!' => \$sections, > > - 'fe|file-emails!' => \$file_emails, > > + 'fe|file-emails!' => \$email_file_emails, > > 'f|file' => \$from_filename, > > 'find-maintainer-files'
RZ/G2 USB quirks U-Boot
I recently broke my dominant wrist, so I apologize if this message is hard to read. I have been running some tests with the RZ/G2 MNH processors, and I noticed a difference in behavior between a cold boot, a soft reset, and a hardware reset. If I'm in u-boot, an issue the reset instruction, and I return to you boot and attempt to start the USB system, the system hangs. >From a cold boot, I can use USB 3, but the USB 2 does not enumerate slave devices. If I press the reset button, both USB 3 and USB to host enumerate slave devices. I've tried different versions and combinations of ATF and u-boot, but the problem seems to affect u-boot itself. I wanted to see if anybody had any suggestions on where I should look to troubleshoot this and if anybody else has already observed this. Thanks. adam
Re: [PATCH u-boot-mvebu v2] arm: mvebu: armada-3720: remove unused config option
On Friday 09 July 2021 17:40:59 Marek Behún wrote: > The config option CONFIG_DEBUG_UART_CLOCK is not used by Armada 3720's > serial driver (it wasn't even before the recent update of that driver). > > Even if it was used, the value was incorrect (the frequency of the clock > is 25 MHz, not 25.8048 MHz). > > Remove it from config files and set the default value to 0. > > Signed-off-by: Marek Behún > Cc: Stefan Roese > Cc: Pali Rohár Reviewed-by: Pali Rohár > --- > Change since v1: > - we also need to specify a default value for this variable in Kconfig, > otherwise the make command will ask for a value. Use 0 for the default > value since it is not used > - updated commit message > --- > configs/mvebu_db-88f3720_defconfig | 1 - > configs/mvebu_espressobin-88f3720_defconfig | 1 - > configs/turris_mox_defconfig| 1 - > configs/uDPU_defconfig | 1 - > drivers/serial/Kconfig | 1 + > 5 files changed, 1 insertion(+), 4 deletions(-) > > diff --git a/configs/mvebu_db-88f3720_defconfig > b/configs/mvebu_db-88f3720_defconfig > index c9935da102..ff4668e837 100644 > --- a/configs/mvebu_db-88f3720_defconfig > +++ b/configs/mvebu_db-88f3720_defconfig > @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db" > CONFIG_DEBUG_UART_BASE=0xd0012000 > -CONFIG_DEBUG_UART_CLOCK=25804800 > CONFIG_DEBUG_UART=y > CONFIG_AHCI=y > CONFIG_DISTRO_DEFAULTS=y > diff --git a/configs/mvebu_espressobin-88f3720_defconfig > b/configs/mvebu_espressobin-88f3720_defconfig > index 157a4b7cb2..dc199cfe50 100644 > --- a/configs/mvebu_espressobin-88f3720_defconfig > +++ b/configs/mvebu_espressobin-88f3720_defconfig > @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin" > CONFIG_DEBUG_UART_BASE=0xd0012000 > -CONFIG_DEBUG_UART_CLOCK=25804800 > CONFIG_DEBUG_UART=y > CONFIG_AHCI=y > CONFIG_DISTRO_DEFAULTS=y > diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig > index 2c6f4938db..b3458acb98 100644 > --- a/configs/turris_mox_defconfig > +++ b/configs/turris_mox_defconfig > @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox" > CONFIG_DEBUG_UART_BASE=0xd0012000 > -CONFIG_DEBUG_UART_CLOCK=25804800 > CONFIG_DEBUG_UART=y > CONFIG_OF_BOARD_FIXUP=y > CONFIG_DISTRO_DEFAULTS=y > diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig > index cdf6b2274c..649248d74d 100644 > --- a/configs/uDPU_defconfig > +++ b/configs/uDPU_defconfig > @@ -10,7 +10,6 @@ CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU" > CONFIG_DEBUG_UART_BASE=0xd0012000 > -CONFIG_DEBUG_UART_CLOCK=25804800 > CONFIG_DEBUG_UART=y > CONFIG_AHCI=y > CONFIG_DISTRO_DEFAULTS=y > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig > index 961e3fb031..93348c0929 100644 > --- a/drivers/serial/Kconfig > +++ b/drivers/serial/Kconfig > @@ -443,6 +443,7 @@ config DEBUG_UART_CLOCK > int "UART input clock" > depends on DEBUG_UART > default 0 if DEBUG_UART_SANDBOX > + default 0 if DEBUG_MVEBU_A3700_UART > help > The UART input clock determines the speed of the internal UART > circuitry. The baud rate is derived from this by dividing the input > -- > 2.31.1 >
Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages
> - "bloblist" is a general term for concept of linked list and it's not > exactly U-boot implementation. The proposed solution will cause some degree > of changes in all the participating projects. For backward compatibility > issue, we have already though about it and proposed to have build configs > which will be enabled by platform integrators. Okay, let's gather the requirements and then decide how the existing system needs to be expanded to meet them. Please keep me in the loop on those discussions. > > U-Boot has an established mechanism which is used in particular on all > > chrome > > books in both x86 and Arm environments. I have the impression that > > U-Boot is the typical BL33 so I would import the mechanism into TFA, > > not the other way round. There has been no Chromebook (x86 or Arm) shipping with U-Boot since 2013 (before TF-A existed). In fact, Chromebooks are all running coreboot today and using the bl_aux_params mechanism (it's 3 SoC vendors, more than 3 SoCs, but the parameter code is shared at the vendor level), and one of my concerns here is trying to limit disruption to those existing setups. I don't have enough data to say what the "typical" boot flow among all TF-A devices in existence is, but at least for the millions of Chromebooks out there it is coreboot + TF-A, not U-Boot.
IMX8M Mini HAB secure boot - working?
Greetings, Has anyone successfully used secure boot with IMX8M Mini or other IMX8M? Peng's recent series got merged with the exception of what looks like the addition of couple of 'caam' commands to blob/deblob DEK's. There are no guides yet however I'm following the guides for the downstream NXP U-Boot and thus far have been able to get the SPL to boot with no HAB events but when it tries to authenticate the FIT image it validate_ivt fails with 'Error: Invalid IVT structure'. I'm not entirely clear if my CSF is wrong, or in the wrong place or if there is something missing. Best regards, Tim
Re: [PATCH u-boot-mvebu 00/31] kwboot / kwbimage improvements
Hi Marek, On 09.07.21 16:08, Marek Behún wrote: On Fri, 9 Jul 2021 14:35:15 +0200 Stefan Roese wrote: Thanks. And could you please also do one (or more) boot-time comparisons, old vs. new version? This way we can see, if and how the boot-time is affected (perhaps improved, which would be great) by this patch series. For Turris Omnia, the size of the u-boot-spl.kwb binary decreases by ~37 KiB, mainly due to not needing padding anymore. The size of the SPL binary itself (u-boot-spl.bin) decreases by 7.5 KiB (due to code reduction - no SPI NOR code). Unfortunately the boot time increases by 815 ms, from 2341 ms (on average) to 3156 ms (on average). Ups. This boot-time increase is quite big. And there might be some Armada / MVEBU U-Boot targets that are tuned for fast booting. I can speak for the Armada XP theadorable board, where boot-time is quite critical. I remember that we tuned and optimized here and an increase of perhaps 100ms would be acceptable. But an increase of nearly 1 second is definitely not acceptable here, I'm afraid. Please see below. This is probably because BootROM read the memory differently (lower frequency or some other reason). I think this 815 ms increase in boot time into U-Boot prompt is worth the 37 KiB saved space for U-Boot code (mainly because on Omnia we have 960 KiB for U-Boot and currently we are at 860 KiB, so enabling some other features in the future may push us to the limit), but others may not agree. Yes, I disagree here. Boot-time is critical for some platforms and this increase is just too high. I might be able to do some tests on theadorable to get actual numbers for this platform. Could you perhaps add this "SPL returns to BootROM" support as an optional feature that can be selected on a per-board basis? Thanks, Stefan I am going to put this information also into v2 cover letter. Marek
Re: [PATCH u-boot-mvebu 00/31] kwboot / kwbimage improvements
On Saturday 10 July 2021 02:31:32 Stefan Roese wrote: > Could you perhaps add this "SPL returns to BootROM" support as an > optional feature that can be selected on a per-board basis? Hi Stefan! I was thinking about it and it should not be hard. Based on defconfig options you decide if you want to use SPL NOR code or stick with return to BootROM. It is acceptable? What is needed is just to extend SPL SPI NOR code to parse also kwbimage header (at offset zero) instead of legacy U-Boot header which is removing by this patch series and which was on variable offset.
Re: [PATCH u-boot-mvebu 00/31] kwboot / kwbimage improvements
On Saturday 10 July 2021 02:43:12 Pali Rohár wrote: > On Saturday 10 July 2021 02:31:32 Stefan Roese wrote: > > Could you perhaps add this "SPL returns to BootROM" support as an > > optional feature that can be selected on a per-board basis? > > Hi Stefan! I was thinking about it and it should not be hard. Based on > defconfig options you decide if you want to use SPL NOR code or stick > with return to BootROM. It is acceptable? > > What is needed is just to extend SPL SPI NOR code to parse also kwbimage > header (at offset zero) instead of legacy U-Boot header which is > removing by this patch series and which was on variable offset. Anyway, this switch "return to BootROM" is done in patch 22. Previous patches 01 - 21 can be applied and used without later patches. So meanwhile could you look at patches 01 - 21 if they are OK and if they could be merged independently of "return to BootROM" patches?
