date:20210923

Hi,

On Thu, 16 Sept 2021 at 09:43, Alex G.  wrote:
>
> Hi,
>
> On 7/29/21 8:08 PM, Chia-Wei Wang wrote:
> > Add UCLASS_HASH for hash driver development. Thus the
> > hash drivers (SW or HW-accelerated) can be developed
> > in the DM-based fashion.
>
> Software hashing implementations are shared tightly with host tools.
> With DM, there's no opportunity for code sharing with host tools. The
> design question that I have is "do we want to DM hashes, or do we want
> to DM hardware accelerators for hashes?"
>
> I did some parallel work expose remaining hash algos via
> hash_lookup_algo() and hash_progressive_lookup_algo().
>
> > Signed-off-by: Chia-Wei Wang 
> > ---
> >   drivers/crypto/Kconfig|   2 +
> >   drivers/crypto/Makefile   |   1 +
> >   drivers/crypto/hash/Kconfig   |   5 ++
> >   drivers/crypto/hash/Makefile  |   5 ++
> >   drivers/crypto/hash/hash-uclass.c | 121 ++
> >   include/dm/uclass-id.h|   1 +
> >   include/u-boot/hash.h |  61 +++
> >   7 files changed, 196 insertions(+)
> >   create mode 100644 drivers/crypto/hash/Kconfig
> >   create mode 100644 drivers/crypto/hash/Makefile
> >   create mode 100644 drivers/crypto/hash/hash-uclass.c
> >   create mode 100644 include/u-boot/hash.h
> >
> > diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> > index 1ea116be75..0082177c21 100644
> > --- a/drivers/crypto/Kconfig
> > +++ b/drivers/crypto/Kconfig
> > @@ -1,5 +1,7 @@
> >   menu "Hardware crypto devices"
> >
> > +source drivers/crypto/hash/Kconfig
> > +
> Hashes are useful outside of cryptographic functions, so it seems odd to
> merge them in crypto. For example, CRC32 is not a hash useful in crypto,
> but otherwise widely used in u-boot.

Are you syching to move this to drivers/hash ? I feel that hashing is
close enough to crypto that it might not be worth having a new
'top-level' driver directory.

Some might say that md5 is in the same board (not useful for crypto)
but it used to be. Similarly, sha1 is fading away.

>
> [snip]
> > diff --git a/drivers/crypto/hash/hash-uclass.c 
> > b/drivers/crypto/hash/hash-uclass.c
> > new file mode 100644
> > index 00..446eb9e56a
> > --- /dev/null
> > +++ b/drivers/crypto/hash/hash-uclass.c
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2021 ASPEED Technology Inc.
> > + * Author: ChiaWei Wang 
> > + */
> > +
> > +#define LOG_CATEGORY UCLASS_HASH
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +struct hash_info {
> > + char *name;
> > + uint32_t digest_size;
> > +};
> > +
> > +static const struct hash_info hash_info[HASH_ALGO_NUM] = {
> > + [HASH_ALGO_CRC16_CCITT] = { "crc16-ccitt", 2 },
> > + [HASH_ALGO_CRC32] = { "crc32", 4 },
> > + [HASH_ALGO_MD5] = { "md5", 16 },
> > + [HASH_ALGO_SHA1] = { "sha1", 20 },
> > + [HASH_ALGO_SHA256] = { "sha256", 32 },
> > + [HASH_ALGO_SHA384] = { "sha384", 48 },
> > + [HASH_ALGO_SHA512] = { "sha512", 64},
> > +};
>
> It seems a step backwards to have to enum {} our hash algos, since we
> already identify them by their strings (e.g. "sha256"). and then
> associated ops structure. The
>
> > +
> > +enum HASH_ALGO hash_algo_lookup_by_name(const char *name)
>
>  string -> hash_lookup_algo() -> ops struct
>
> Is the current way to do things. hash_algo_lookup_by_name() does the
> roundabout through an enum. That doesn't make sense to me.

Actually I'd like to see an enum to describe these, since looking up a
string is less efficient in a bootloader. So some way of doing that
seems good to me.

Of course it means we need a global list of this algos in a header
file and each driver needs to indicate which one(s) it supports.

Regards,
Simon

Re: [PATCH 05/10] remoteproc: uclass: Add remoteproc resource handling helpers

Hi Amjad,

On Thu, 23 Sept 2021 at 10:47, Amjad Ouled-Ameur
 wrote:
>
> From: Keerthy 
>
> Add remoteproc resource handling helpers. These functions
> are primarily to parse the resource table and to handle
> different types of resources. Carveout, devmem, trace &
> vring resources are handled.
>
> Signed-off-by: Keerthy 
> [Amjad: fix redefinition of "struct resource_table" and compile warnings ]
> Signed-off-by: Amjad Ouled-Ameur 
> ---
>
>  drivers/remoteproc/rproc-uclass.c | 562 ++
>  include/remoteproc.h  | 384 +++-
>  2 files changed, 945 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/remoteproc/rproc-uclass.c 
> b/drivers/remoteproc/rproc-uclass.c
> index 64c47c1e7225..3f7096045548 100644
> --- a/drivers/remoteproc/rproc-uclass.c
> +++ b/drivers/remoteproc/rproc-uclass.c
> @@ -8,6 +8,7 @@
>
>  #define pr_fmt(fmt) "%s: " fmt, __func__
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -19,9 +20,21 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> +struct resource_table {
> +   u32 ver;
> +   u32 num;
> +   u32 reserved[2];
> +   u32 offset[0];
> +} __packed;
> +
> +typedef int (*handle_resource_t) (struct udevice *, void *, int offset, int 
> avail);
> +
> +static struct resource_table *rsc_table;
> +
>  /**
>   * for_each_remoteproc_device() - iterate through the list of rproc devices
>   * @fn: check function to call per match, if this function returns fail,
> @@ -208,6 +221,86 @@ static int rproc_post_probe(struct udevice *dev)
> return 0;
>  }
>
> +/**
> + * rproc_add_res() - After parsing the resource table add the mappings
> + * @dev:   device we finished probing
> + * @mapping: rproc_mem_entry for the resource
> + *
> + * Return: if the remote proc driver has a add_res routine, invokes it and
> + * hands over the return value. overall, 0 if all went well, else appropriate
> + * error value.
> + */
> +static int rproc_add_res(struct udevice *dev, struct rproc_mem_entry 
> *mapping)
> +{
> +   const struct dm_rproc_ops *ops;
> +
> +   ops = rproc_get_ops(dev);
> +   if (!ops) {
> +   debug("%s driver has no ops?\n", dev->name);
> +   return -EINVAL;
> +   }

Please don't check this as it just bloats the code. The ops must be
provided. Please fix throughout.

> +
> +   if (ops->add_res)
> +   return ops->add_res(dev, mapping);

Don't you want to return -ENOSYS if there is no method here?

> +
> +   return 0;
> +}
> +
> +/**
> + * rproc_alloc_mem() - After parsing the resource table allocat mem
> + * @dev:   device we finished probing
> + * @len: rproc_mem_entry for the resource
> + * @align: alignment for the resource
> + *
> + * Return: if the remote proc driver has a add_res routine, invokes it and
> + * hands over the return value. overall, 0 if all went well, else appropriate
> + * error value.
> + */
> +static void *rproc_alloc_mem(struct udevice *dev, unsigned long len,
> +unsigned long align)
> +{
> +   const struct dm_rproc_ops *ops;
> +
> +   ops = rproc_get_ops(dev);
> +   if (!ops) {
> +   debug("%s driver has no ops?\n", dev->name);
> +   return NULL;
> +   }
> +
> +   if (ops->alloc_mem)
> +   return ops->alloc_mem(dev, len, align);
> +
> +   return NULL;
> +}
> +
> +/**
> + * rproc_config_pagetable() - Configure page table for remote processor
> + * @dev:   device we finished probing
> + * @virt: Virtual address of the resource
> + * @phys: Physical address the resource
> + * @len: length the resource
> + *
> + * Return: if the remote proc driver has a add_res routine, invokes it and
> + * hands over the return value. overall, 0 if all went well, else appropriate
> + * error value.
> + */
> +static int rproc_config_pagetable(struct udevice *dev, unsigned int virt,
> + unsigned int phys, unsigned int len)
> +{
> +   const struct dm_rproc_ops *ops;
> +
> +   ops = rproc_get_ops(dev);
> +   if (!ops) {
> +   debug("%s driver has no ops?\n", dev->name);
> +   return -EINVAL;
> +   }
> +
> +   if (ops->config_pagetable)
> +   return ops->config_pagetable(dev, virt, phys, len);
> +
> +   return 0;
> +}
> +
>  UCLASS_DRIVER(rproc) = {
> .id = UCLASS_REMOTEPROC,
> .name = "remoteproc",
> @@ -438,3 +531,472 @@ int rproc_is_running(int id)
>  {
> return _rproc_ops_wrapper(id, RPROC_RUNNING);
>  };
> +
> +/*
> + * Virtio ring descriptors: 16 bytes.  These can chain together via
> + * "next".

What is this code doing in the uclass:

> + */
> +struct vring_desc {
> +   u64 addr;
> +   u32 len;
> +   u16 flags;
> +   u16 next;
> +};
> +
> +/*
> + * u32 is used here for ids for padding reasons.
> + */
> +struct vring_used_elem {
> +   u32 id;
> +   u32 len;
>

Re: S25HS512 not functional with u-boot 2021.10.rc3

Hi Harkirat,

On Tue, 14 Sept 2021 at 19:50, Harkirat Virk  wrote:
>
> I have a custom board using imx6ul and Spansion S25HS512T Flash. On the 
> current version of u-boot (2021.10.rc3) and I am guessing even previous ones 
> the Spansion flash is not functioning
>
> => sf probe
> drivers/core/uclass.c:325-uclass_find_device_by_seq() 0
> drivers/core/uclass.c:333-uclass_find_device_by_seq()- 0 'spi@21e'
> drivers/core/uclass.c:336-uclass_find_device_by_seq()- found
> drivers/spi/spi-uclass.c:282-spi_find_chip_select() fsl_qspi spi@21e: 
> spi_find_chip_select: plat=9ef2bf60, cs=0
> drivers/core/uclass.c:325-uclass_find_device_by_seq() 0
> drivers/core/uclass.c:333-uclass_find_device_by_seq()- 0 'spi@21e'
> drivers/core/uclass.c:336-uclass_find_device_by_seq()- found
> drivers/spi/spi-uclass.c:282-spi_find_chip_select() fsl_qspi spi@21e: 
> spi_find_chip_select: plat=9ef2bf60, cs=0
> drivers/core/uclass.c:325-uclass_find_device_by_seq() 0
> drivers/core/uclass.c:333-uclass_find_device_by_seq()- 0 'iomuxc@20e'
> drivers/core/uclass.c:336-uclass_find_device_by_seq()- found
> drivers/pinctrl/pinctrl-uclass.c:300-pinctrl_select_state_simple() 
> jedec_spi_nor s25hs512t@0: set_state_simple op missing
> drivers/spi/fsl_qspi.c:464-fsl_qspi_prepare_lut() fsl_qspi spi@21e: 
> CMD[9f] lutval[0:1c00049f1:0 2:0 3:0]
> drivers/spi/spi-uclass.c:438-  spi_get_bus_and_cs() spi_get_bus_and_cs: Error 
> path, created=0, device 's25hs512t@0'
> Failed to initialize SPI flash at 0:0 (error -524)
>
> Result is the same with different modes and frequencies, bus and CS are 
> correct
>
> My DTSI is
>
>  {
> pinctrl-names = "default";
> pinctrl-0 = <_qspi>;
> status = "okay";
>
> flash0: s25hs512t@0 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "spansion,s25hs512t", "jedec,spi-nor";
> spi-max-frequency = <4000>;
> spi-rx-bus-width = <4>;
> spi-tx-bus-width = <4>;
> reg = <0>;
> spi-mode = <0>;
> m25p,fast-read;
> status = "okay";
> /* some partition information*/
> };
> };
>
> Defconfig has
>
> CONFIG_SPI=y
> CONFIG_DM_SPI=y
> CONFIG_FSL_QSPI=y
> CONFIG_MTD=y
> CONFIG_DM_MTD=y
> CONFIG_DM_SPI_FLASH=y
> CONFIG_SF_DEFAULT_MODE=0
> CONFIG_SF_DEFAULT_SPEED=4000
> CONFIG_SPI_FLASH_SPANSION=y
>
>  DM Tree
>
> => dm tree
>  Class Index  Probed  DriverName
> ---
>  root  0  [ + ]   root_driver   root_driver
>  thermal   0  [   ]   imx_thermal   |-- imx_thermal
>  simple_bus0  [ + ]   simple_bus|-- soc
>  simple_bus1  [ + ]   simple_bus|   |-- aips-bus@200
>  simple_bus2  [ + ]   simple_bus|   |   |-- spba-bus@200
>  serial0  [ + ]   serial_mxc|   |   |   `-- serial@202
>  gpio  0  [   ]   gpio_mxc  |   |   |-- gpio@209c000
>  gpio  1  [   ]   gpio_mxc  |   |   |-- gpio@20a
>  gpio  2  [   ]   gpio_mxc  |   |   |-- gpio@20a4000
>  gpio  3  [   ]   gpio_mxc  |   |   |-- gpio@20a8000
>  gpio  4  [   ]   gpio_mxc  |   |   |-- gpio@20ac000
>  simple_bus3  [   ]   simple_bus|   |   |-- anatop@20c8000
>  simple_bus4  [   ]   simple_bus|   |   |-- snvs@20cc000
>  pinctrl   0  [ + ]   fsl_imx6q_iomuxc  |   |   `-- iomuxc@20e
>  pinconfig 0  [   ]   pinconfig |   |   |-- i2c1grp
>  pinconfig 1  [   ]   pinconfig |   |   |-- i2c2grp
>  pinconfig 2  [ + ]   pinconfig |   |   |-- qspigrp
>  pinconfig 3  [   ]   pinconfig |   |   |-- ledsgrp
>  pinconfig 4  [ + ]   pinconfig |   |   |-- uart1grp
>  pinconfig 5  [ + ]   pinconfig |   |   |-- usdhc2grp
>  pinconfig 6  [   ]   pinconfig |   |   `-- wdoggrp
>  simple_bus5  [ + ]   simple_bus|   `-- aips-bus@210
>  usb   0  [   ]   ehci_mx6  |   |-- usb@2184000
>  mmc   0  [ + ]   fsl_esdhc |   |-- usdhc@2194000
>  blk   0  [   ]   mmc_blk   |   |   `-- 
> us...@2194000.blk
>  i2c   0  [   ]   i2c_mxc   |   |-- i2c@21a
>  i2c   1  [   ]   i2c_mxc   |   |-- i2c@21a4000
>  spi   0  [ + ]   fsl_qspi  |   `-- spi@21e
>  spi_flash 0  [   ]   jedec_spi_nor |   `-- s25hs512t@0
>  regulator 0  [   ]   regulator_fixed   |-- regulator-sd2-vmmc
>  led   0  [   ]   gpio_led  `-- leds
>  led   1  [   ]   gpio_led  |--

Re: [PATCH 2/4] dm: hash: Add new UCLASS_HASH support

Hi,

On Wed, 22 Sept 2021 at 17:56, ChiaWei Wang  wrote:
>
> Hi Simon,
>
> > From: Simon Glass 
> > Sent: Thursday, September 23, 2021 12:19 AM
> >
> > Hi,
> >
> > On Thu, 2 Sept 2021 at 07:28, Tom Rini  wrote:
> > >
> > > On Fri, Jul 30, 2021 at 09:08:03AM +0800, Chia-Wei Wang wrote:
> > >
> > > > Add UCLASS_HASH for hash driver development. Thus the hash drivers
> > > > (SW or HW-accelerated) can be developed in the DM-based fashion.
> > > >
> > > > Signed-off-by: Chia-Wei Wang 
> > >
> > > Applied to u-boot/next, thanks!
> >
> > Oddly enough I didn't see this patch but did see Tom's reply.
>
> Truly odd. You and Tom are on the '--to' list.
> I also checked the content sent on U-Boot Patchwork as shown below.
>
> ---
> To: , , 
> Subject: [PATCH 2/4] dm: hash: Add new UCLASS_HASH support

Well it doesn't matter. It actually happened about 6 months ago too, I
think. I don't know what causes it but I suspect a spam filter as I
found a few patches in my spam folder. I'll try to train it.

Regards,
Simon

Re: [PATCH 09/11] sandbox: Add a way to map a file into memory

Hi Marek,

On Wed, 22 Sept 2021 at 20:09, Tom Rini  wrote:
>
> On Wed, Aug 18, 2021 at 09:40:31PM -0600, Simon Glass wrote:
>
> > It is useful to map a file into memory so that it can be accessed using
> > simple pointers. Add a function to support this.
> >
> > Signed-off-by: Simon Glass 
>
> Applied to u-boot/next, thanks!

I'll send a new patch for your comment. I have it locally but the mmc
malloc() thing needs a substantial effort to resolve, so I'm not sure
when I'll send this.

Regards,
Simon

Re: [PATCH 1/1] doc: add system reset to API documentation

On Thu, 23 Sept 2021 at 03:12, Heinrich Schuchardt
 wrote:
>
> Complete the Sphinx documentation in include/sysreset.h
> Add the include to the generated HTML documentation of the U-Boot API.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  doc/api/index.rst|  1 +
>  doc/api/sysreset.rst |  7 ++
>  include/sysreset.h   | 53 
>  3 files changed, 42 insertions(+), 19 deletions(-)
>  create mode 100644 doc/api/sysreset.rst

Reviewed-by: Simon Glass

Re: [PATCH 11/35] RFC: efi: Drop code that doesn't work with driver model

Hi Mark,

On Thu, 9 Sept 2021 at 15:45, Mark Kettenis  wrote:
>
> > Date: Thu, 9 Sep 2021 16:23:08 -0400
> > From: Tom Rini 
> >
> > On Thu, Sep 09, 2021 at 10:15:44PM +0200, Mark Kettenis wrote:
> > > > From: Simon Glass 
> > > > Date: Thu, 9 Sep 2021 13:57:39 -0600
> > > >
> > > > Hi Heinrich,
> > > >
> > > > On Thu, 9 Sept 2021 at 03:26, Heinrich Schuchardt  
> > > > wrote:
> > > > >
> > > > >
> > > > >
> > > > > On 9/9/21 10:57 AM, Simon Glass wrote:
> > > > > > Hi Heinrich,
> > > > > >
> > > > > > On Wed, 8 Sept 2021 at 11:44, Heinrich Schuchardt 
> > > > > >  wrote:
> > > > > >>
> > > > > >>
> > > > > >>
> > > > > >> On 9/8/21 3:33 PM, Simon Glass wrote:
> > > > > >>> This code should never have been added as it builds a new feature 
> > > > > >>> on top
> > > > > >>> of legacy code. Drop it and add a dependency on BLK for this 
> > > > > >>> feature.
> > > > > >>>
> > > > > >>> Boards which want EFI_LOADER should migrate to driver model first.
> > > > > >>>
> > > > > >>> Signed-off-by: Simon Glass 
> > > > > >>
> > > > > >> This patch is not related to the rest of the series and the code 
> > > > > >> has a
> > > > > >> different maintainer.
> > > > > >>
> > > > > >> So, please, separate it from the series.
> > > > > >
> > > > > > Who is the maintainer?
> > > > >
> > > > > Until 623b3a57976 ("efi_selftest: provide an EFI selftest 
> > > > > application")
> > > > > there was no official maintainer for lib/efi/ but you were the main
> > > > > contributor.
> > > > >
> > > > > But with that patch directory lib/efi/ was assigned to EFI PAYLOAD.
> > > > >
> > > > > I am happy if you would continue to care about U-Boot on EFI.
> > > >
> > > > OK.
> > > >
> > > > >
> > > > > >
> > > > > > I need this patch for this series to work. You can still review 
> > > > > > things
> > > > > > for other maintainers and in this case it is common for one 
> > > > > > maintainer
> > > > > > to pick up the series once the others are happy.
> > > > >
> > > > > The direction of this patch is completely correct.
> > > > >
> > > > > There are some things that will have to be changed, e.g we should not
> > > > > require CONFIG_DM_ETH=y. I will work on reviewing this patch in 
> > > > > detail.
> > > >
> > > > OK, but why not require DM_ETH? The deadline passed a year ago.
> > >
> > > Because we support boards without network ports?
> >
> > Boards without networking should disable the relevant code, and as
> > needed the EFI code return the proper error code?
>
> Yes, but it means you can't make DM_ETH a (hard) requirement for
> EFI_LOADER support.  What I mean is that it should still be possible
> to build U-Boot with EFI_LOADER support even if DM_EFI isn't set for a
> board.  It should just result in a UEFI implementation with no network
> support instead.

I think you are misunderstanding my patch. I have:

depends on DM_ETH || !NET

which means that if NET is used, DM_ETH must be. I think that is reasonable.

Regards,
Simon

Re: [PATCH v4 3/5] sf: Tidy up code to avoid #ifdef

Hi Pratyush,

On Mon, 20 Sept 2021 at 05:08, Pratyush Yadav  wrote:
>
> Hi Simon,
>
> On 19/09/21 03:49PM, Simon Glass wrote:
> > Update this code to use IS_ENABLED() instead.
> >
> > Signed-off-by: Simon Glass 
> >
> > Reviewed-by: Pratyush Yadav 
>
> Nitpick: Trailers shouldn't have a blank line between them. I see it for
> this patch and 4/5 as well. It probably doesn't matter, but I wonder if
> it will trip up some tools that work on commit trailers like
> git-interpret-trailers. Something you might want to fix in your
> workflow...

The fix to 'patman status -d ' is in mainline but was not
in the tree where I ran this tool, unfortunately.

So hopefully this won't happen again.

Regards,
Simon

Re: [PATCH 12/12] lmb: x86: Add arch_lmb_reserve()

On Fri, Sep 10, 2021 at 10:47:18PM +0200, Marek Vasut wrote:

> Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
> It is rather likely this architecture also needs to cover U-Boot with
> LMB before booting Linux.
> 
> Signed-off-by: Marek Vasut 
> Cc: Simon Glass 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 11/12] lmb: xtensa: Add arch_lmb_reserve()

On Fri, Sep 10, 2021 at 10:47:17PM +0200, Marek Vasut wrote:

> Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
> It is rather likely this architecture also needs to cover U-Boot with
> LMB before booting Linux.
> 
> Signed-off-by: Marek Vasut 
> Cc: Chris Zankel 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 10/12] lmb: sh: Add arch_lmb_reserve()

On Fri, Sep 10, 2021 at 10:47:16PM +0200, Marek Vasut wrote:

> Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
> This architecture also needs to cover U-Boot with LMB before booting
> Linux.
> 
> Signed-off-by: Marek Vasut 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 08/12] lmb: nds32: Add arch_lmb_reserve()

On Fri, Sep 10, 2021 at 10:47:14PM +0200, Marek Vasut wrote:

> Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
> It is rather likely this architecture also needs to cover U-Boot with
> LMB before booting Linux.
> 
> Reviewed-by: Rick Chen 
> Signed-off-by: Marek Vasut 
> Cc: Rick Chen 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 09/12] lmb: riscv: Add arch_lmb_reserve()

On Fri, Sep 10, 2021 at 10:47:15PM +0200, Marek Vasut wrote:

> Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
> It is rather likely this architecture also needs to cover U-Boot with
> LMB before booting Linux.
> 
> Reviewed-by: Rick Chen 
> Signed-off-by: Marek Vasut 
> Cc: Atish Patra 
> Cc: Leo 
> Cc: Rick Chen 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 05/12] lmb: arm: Increase LMB alignment to 16k in arch_lmb_reserve_generic()

On Fri, Sep 10, 2021 at 10:47:11PM +0200, Marek Vasut wrote:

> According to input NXP, the 4k alignment is not always sufficient.
> Currently iMX works around this problem by implementing board specific
> LMB reservation, however it is likely this could also occur on other
> systems. Increase the LMB reservation alignment to 16k by default.
> 
> Signed-off-by: Marek Vasut 
> Cc: Alexey Brodkin 
> Cc: Angelo Dureghello 
> Cc: Daniel Schwierzeck 
> Cc: Eugeniy Paltsev 
> Cc: Hai Pham 
> Cc: Michal Simek 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 
> Cc: Wolfgang Denk 
> Cc: Ye Li 
> Reviewed-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 07/12] lmb: nios2: Add arch_lmb_reserve()

On Fri, Sep 10, 2021 at 10:47:13PM +0200, Marek Vasut wrote:

> Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
> It is rather likely this architecture also needs to cover U-Boot with
> LMB before booting Linux.
> 
> Signed-off-by: Marek Vasut 
> Cc: Simon Goldschmidt 
> Cc: Thomas Chou 
> Cc: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 06/12] lmb: Remove imx board_lmb_reserve()

On Fri, Sep 10, 2021 at 10:47:12PM +0200, Marek Vasut wrote:

> This function is clearly architecture specific code, not board specific
> code. The only difference from the previous arm arch_lmb_reserve() is the
> extra reservation of 16k of memory below the stack bottom, rather than
> the 4k. The common code now also uses 16k alignment. Remove this custom
> implementation, as it now behaves exactly as the common code.
> 
> Signed-off-by: Marek Vasut 
> Cc: Alexey Brodkin 
> Cc: Angelo Dureghello 
> Cc: Daniel Schwierzeck 
> Cc: Eugeniy Paltsev 
> Cc: Hai Pham 
> Cc: Michal Simek 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 
> Cc: Wolfgang Denk 
> Cc: Ye Li 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 03/12] lmb: Add generic arch_lmb_reserve_generic()

On Fri, Sep 10, 2021 at 10:47:09PM +0200, Marek Vasut wrote:

> The arc/arm/m68k/microblaze/mips/ppc arch_lmb_reserve() implementations
> are all mostly the same, except for a couple of details. Implement a
> generic arch_lmb_reserve_generic() function which can be parametrized
> enough to cater for those differences between architectures. This can
> also be parametrized enough so it can handle cases where U-Boot is not
> relocated to the end of DRAM e.g. because there is some other reserved
> memory past U-Boot (e.g. unmovable firmware for coprocessor), it is not
> relocated at all, and other such use cases.
> 
> Signed-off-by: Marek Vasut 
> Cc: Alexey Brodkin 
> Cc: Angelo Dureghello 
> Cc: Daniel Schwierzeck 
> Cc: Eugeniy Paltsev 
> Cc: Hai Pham 
> Cc: Michal Simek 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 
> Cc: Wolfgang Denk 
> Reviewed-by: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 04/12] lmb: Switch to generic arch_lmb_reserve_generic()

On Fri, Sep 10, 2021 at 10:47:10PM +0200, Marek Vasut wrote:

> Switch arc/arm/m68k/microblaze/mips/ppc arch_lmb_reserve() to
> arch_lmb_reserve_generic().
> 
> Reviewed-by: Tom Rini 
> Signed-off-by: Marek Vasut 
> Cc: Alexey Brodkin 
> Cc: Angelo Dureghello 
> Cc: Daniel Schwierzeck 
> Cc: Eugeniy Paltsev 
> Cc: Hai Pham 
> Cc: Michal Simek 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 
> Cc: Wolfgang Denk 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges

On Fri, Sep 10, 2021 at 01:33:35PM +0200, Pali Rohár wrote:

> Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved
> and should be zero. So do not set them to non-zero value.
> 
> Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers
> contain information if 64-bit memory addressing is supported. So preserve
> this information when overwriting these registers.
> 
> Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information
> if 32-bit io addressing is supported. So preserve this information and do
> not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and
> PCI_IO_LIMIT_UPPER16 registers) when it is unsupported.
> 
> Signed-off-by: Pali Rohár 
> Reviewed-by: Stefan Roese 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 02/12] lmb: Always compile arch_lmb_reserve() into U-Boot on arc

On Fri, Sep 10, 2021 at 10:47:08PM +0200, Marek Vasut wrote:

> The arch_lmb_reserve() is called by lib/lmb.c lmb_reserve_common() even
> if CMD_BOOTM is not enabled. However, the arc variant of arch_lmb_reserve()
> is only compiled in if CMD_BOOTM is enabled.
> 
> This currently does not trigger build error, because there is an empty
> weak implementation of arch_lmb_reserve(), however that is not the
> function that should be used on arc.
> 
> Fix this by moving the arch_lmb_reserve() implementation into common
> code and always compile it in.
> 
> Signed-off-by: Marek Vasut 
> Cc: Simon Glass 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 01/12] lmb: Always compile arch_lmb_reserve() into U-Boot on arm

On Fri, Sep 10, 2021 at 10:47:07PM +0200, Marek Vasut wrote:

> The arch_lmb_reserve() is called by lib/lmb.c lmb_reserve_common() even
> if CMD_BOOT{I,M,Z} is not enabled. However, the arm32/arm64 variant of
> arch_lmb_reserve() is only compiled in if CMD_BOOT{I,M,Z} is enabled.
> 
> This currently does not trigger build error, because there is an empty
> weak implementation of arch_lmb_reserve(), however that is not the
> function that should be used on arm32/arm64.
> 
> Fix this by moving the arch_lmb_reserve() implementation into common
> code and always compile it in.
> 
> Reviewed-by: Tom Rini 
> Signed-off-by: Marek Vasut 
> Cc: Simon Glass 
> Cc: Simon Goldschmidt 
> Cc: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] image: add lz4 zstd compression magic map

On Tue, Aug 31, 2021 at 06:22:18PM +0800, Artem Lapkin wrote:

> Add lz4 and zstd compression magic map. Already can decompress images
> with lz4 and zstd compression type.
> 
> Signed-off-by: Artem Lapkin 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v2] arm: mediatek: merge board Kconfigs into mach-mediatek

On Fri, Sep 10, 2021 at 10:21:06AM +0200, Guillaume La Roque wrote:

> On MediaTek boards we cannot override the SYS_BOARD / SYS_CONFIG_NAME
> variables from defconfig.
> This is because in board/mediatek/mt/Kconfig this value was override
> by default due to the if CONFIG_TARGET_MT condition.
> 
> Merge all the Kconfigs to the mach-medatek/Kconfig.
> 
> This way:
> - we only define SYS_{SOC,VENDOR} once
> - all board definitions are in a single place, simplifying the build logic.
> 
> Signed-off-by: Guillaume La Roque 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] crc32: Add crc32 implementation using __builtin_aarch64_crc32b

On Mon, Aug 30, 2021 at 03:05:23PM +0200, Marek Vasut wrote:

> ARMv8.0 has optional crc32 instruction for crc32 calculation. The
> instruction is mandatory since ARMv8.1. The crc32 calculation is
> faster using the dedicated instruction, e.g. 1.4 GHz iMX8MN gives:
> 
>   => time crc32 0x5000 0x200
>   time: 0.126 seconds # crc32 instruction
>   time: 0.213 seconds # software crc32
> 
> Add implementation using the compiler builtin wrapper for the crc32
> instruction and enable it by default, since we don't support any
> platforms which do not implement this instruction.
> 
> Signed-off-by: Marek Vasut 
> Cc: Simon Glass 
> Cc: Tom Rini 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 2/2] armv8/cache.S: Triple with single instruction

On Fri, Aug 27, 2021 at 06:04:10PM +0200, Pierre-Clément Tosi wrote:

> Replace the current 2-instruction 2-step tripling code by a
> corresponding single instruction leveraging ARMv8-A's "flexible second
> operand as a register with optional shift". This has the added benefit
> (albeit arguably negligible) of reducing the final code size.
> 
> Fix the comment as the tripled cache level is placed in x12, not x0.
> 
> Signed-off-by: Pierre-Clément Tosi 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH 1/2] armv8/cache.S: Read sysreg fields through ubfx

On Fri, Aug 27, 2021 at 06:03:45PM +0200, Pierre-Clément Tosi wrote:

> Improve the file's readability and conciseness by using the appropriate
> Aarch64 instruction: ubfx (unsigned bitfield extract). This makes the
> code easier to follow as it directly manipulates the offsets and widths
> of the fields read from system registers, as they are expressed in the
> Standard (ARM ARM). This has the added benefit (albeit arguably
> negligible) of reducing the final code size.
> 
> Signed-off-by: Pierre-Clément Tosi 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] env: Make _init() expect _INVALID when _IS_NOWHERE

On Thu, Aug 12, 2021 at 03:28:31PM +, Pierre-Clément Tosi wrote:

> Avoid applying the "fix" introduced by commit 5557eec01cbf ("env: Fix
> invalid env handling in env_init()") to the environment "nowhere".
> 
> This is necessary as that commit, by setting the return value of
> env_init() to -ENOENT if gd->env_valid is ENV_INVALID, forces that
> function to reset gd->env_valid to ENV_VALID. By doing so, it breaks the
> assumption (required by ENV_IS_NOWHERE) that gd->env_valid must be
> ENV_INVALID.
> 
> This, in turn, results in env_relocate() calling env_load() (it should
> not), which itself, calls U_BOOT_ENV_LOCATION(nowhere).load() i.e.
> env_nowhere_load(). That function, being implemented under the
> assumption mentioned above, calls env_set_default(), which in turn,
> seeing that gd->env_valid is ENV_VALID (it should not), tries to
> dereference whatever lies in gd->env_addr (most likely garbage), leading
> to a faulty memory access.
> 
> Note that other env_locations might be concerned by this bug but that
> this commit only intends to fix it for when ENV_IS_NOWHERE.
> 
> Fixes: 5557eec01cbf ("env: Fix invalid env handling in env_init()")
> Signed-off-by: Pierre-Clément Tosi 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH] ARM: dts: imx: use generic name bus

2021-09-23 Thread Peng Fan (OSS)




On 2021/9/24 4:14, Oleksandr Suvorov wrote:

Synchronize the u-boot and kernel imx device trees, using tuned
script from commit c0157bdcafa1 ("ARM: dts: imx: use generic name bus")

Per devicetree specification, generic names are recommended to be
used, such as bus.

i.MX AIPS is an AHB - IP bridge bus, so we could use bus as node
name.

Script:
sed -i "s/\
---

  arch/arm/dts/imx53-m53menlo-u-boot.dtsi | 2 +-
  arch/arm/dts/imx53.dtsi | 4 ++--
  arch/arm/dts/imx6dl.dtsi| 4 ++--
  arch/arm/dts/imx6q-display5-u-boot.dtsi | 2 +-
  arch/arm/dts/imx6q.dtsi | 2 +-
  arch/arm/dts/imx6qdl-u-boot.dtsi| 4 ++--
  arch/arm/dts/imx6qdl.dtsi   | 4 ++--
  arch/arm/dts/imx6qp.dtsi| 2 +-
  arch/arm/dts/imx6sl.dtsi| 4 ++--
  arch/arm/dts/imx6sll.dtsi   | 4 ++--
  arch/arm/dts/imx6sx.dtsi| 6 +++---
  arch/arm/dts/imx6ul.dtsi| 4 ++--
  arch/arm/dts/imx6ull.dtsi   | 2 +-
  arch/arm/dts/imx7s.dtsi | 6 +++---
  arch/arm/dts/vf.dtsi| 4 ++--
  15 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi 
b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
index bc4b3483a6..869adb9dad 100644
--- a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
+++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
@@ -7,7 +7,7 @@
soc {
u-boot,dm-pre-reloc;
  
-		aips@5000 {

+   bus@5000 {
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index ed341cfd9d..8536f59f59 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -222,7 +222,7 @@
clock-names = "core_clk", "mem_iface_clk";
};
  
-		aips@5000 { /* AIPS1 */

+   bus@5000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -654,7 +654,7 @@
};
};
  
-		aips@6000 {	/* AIPS2 */

+   bus@6000 {  /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
index f0607eb41d..ae5aad6b9e 100644
--- a/arch/arm/dts/imx6dl.dtsi
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -84,7 +84,7 @@
clocks = < IMX6QDL_CLK_OCRAM>;
};
  
-		aips1: aips-bus@200 {

+   aips1: bus@200 {
iomuxc: iomuxc@20e {
compatible = "fsl,imx6dl-iomuxc";
};
@@ -100,7 +100,7 @@
};
};
  
-		aips2: aips-bus@210 {

+   aips2: bus@210 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/imx6q-display5-u-boot.dtsi 
b/arch/arm/dts/imx6q-display5-u-boot.dtsi
index aa660b5aeb..ced4dacc73 100644
--- a/arch/arm/dts/imx6q-display5-u-boot.dtsi
+++ b/arch/arm/dts/imx6q-display5-u-boot.dtsi
@@ -23,7 +23,7 @@
soc {
u-boot,dm-pre-reloc;
  
-		aips-bus@210 {

+   bus@210 {
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index 71543a4a68..c37484dce3 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -162,7 +162,7 @@
clocks = < IMX6QDL_CLK_OCRAM>;
};
  
-		aips-bus@200 { /* AIPS1 */

+   bus@200 { /* AIPS1 */
spba-bus@200 {
ecspi5: spi@2018000 {
#address-cells = <1>;
diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi
index 1279cc2338..f74af6c423 100644
--- a/arch/arm/dts/imx6qdl-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-u-boot.dtsi
@@ -13,14 +13,14 @@
u-boot,dm-spl;
u-boot,dm-pre-reloc;
  
-		aips-bus@200 {

+   bus@200 {
u-boot,dm-spl;
spba-bus@200 {
u-boot,dm-spl;
};
};
  
-		aips-bus@210 {

+   bus@210 {
u-boot,dm-spl;
};
};
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index e4daf15088..1cdb498c72 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -283,7 +283,7 @@
status = "disabled";
};
  
-		aips-bus@200 { /* AIPS1 */

Re: [PATCH] cmd: mmc: check whether card is SD or eMMC before hwpartition

2021-09-23 Thread Peng Fan (OSS)




On 2021/9/24 8:23, Jaehoon Chung wrote:

It doesn't need to follow more sequence to do the hwparititioning,
because SD doesn't support hwpartitioning feature.

Signed-off-by: Jaehoon Chung 
---
  cmd/mmc.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/cmd/mmc.c b/cmd/mmc.c
index f1e30d0cf64b..62c7e9129666 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -673,6 +673,11 @@ static int do_mmc_hwpartition(struct cmd_tbl *cmdtp, int 
flag,
if (!mmc)
return CMD_RET_FAILURE;
  
+	if (IS_SD(mmc)) {

+   puts("SD doesn't support partitioning\n");
+   return CMD_RET_FAILURE;
+   }
+
if (argc < 1)
return CMD_RET_USAGE;
i = 1;



Reviewed-by: Peng Fan

Re: [PATCH 1/1] riscv: ae350: enable Coherence Manager for ae350

2021-09-23 Thread Rick Chen

> From: Leo Yu-Chi Liang(梁育齊) 
> Sent: Thursday, September 23, 2021 10:34 AM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊) 
> 
> Subject: [PATCH 1/1] riscv: ae350: enable Coherence Manager for ae350
>
> If Coherence Manager were not set in the beginning, u-boot-spl would 
> sometimes fail to boot to u-boot proper.
>
> Enable CM and I/D cache at the same time in harts_early_init
>
> Signed-off-by: Leo Yu-Chi Liang 
> ---
>  arch/riscv/cpu/ax25/cpu.c | 42 +++
>  1 file changed, 42 insertions(+)

Reviewed-by: Rick Chen

[PATCH] cmd: mmc: check whether card is SD or eMMC before hwpartition

It doesn't need to follow more sequence to do the hwparititioning,
because SD doesn't support hwpartitioning feature.

Signed-off-by: Jaehoon Chung 
---
 cmd/mmc.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/cmd/mmc.c b/cmd/mmc.c
index f1e30d0cf64b..62c7e9129666 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -673,6 +673,11 @@ static int do_mmc_hwpartition(struct cmd_tbl *cmdtp, int 
flag,
if (!mmc)
return CMD_RET_FAILURE;
 
+   if (IS_SD(mmc)) {
+   puts("SD doesn't support partitioning\n");
+   return CMD_RET_FAILURE;
+   }
+
if (argc < 1)
return CMD_RET_USAGE;
i = 1;
-- 
2.29.0

Re: [RFC PATCH 4/4] nvme: translate virtual addresses into the bus's address space

On 2021-09-24 01:20, Stefan Agner wrote:
> So far we've been content with passing physical/CPU addresses when
> configuring memory addresses into NVMe controllers, but not all
> platforms have buses with transparent mappings. Specifically the
> Raspberry Pi 4 might introduce an offset to memory accesses incoming
> from its PCIe port.
> 
> Introduce nvme_virt_to_bus() and nvme_bus_to_virt() to cater with these
> limitations, and make sure we don't break non DM users.
> For devices where PCIe's view of host memory doesn't match the memory
> as seen by the CPU.
> 
> A similar change has been introduced for XHCI controller with
> commit 1a474559d90a ("xhci: translate virtual addresses into the bus's
> address space").
> 
> Signed-off-by: Stefan Agner 
> ---
> 
>  drivers/nvme/nvme.c | 32 ++--
>  drivers/nvme/nvme.h | 15 +++
>  2 files changed, 33 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
> index 4c4dc7cc4d..0b7082d71b 100644
> --- a/drivers/nvme/nvme.c
> +++ b/drivers/nvme/nvme.c
> @@ -95,7 +95,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
>   buffer += (page_size - offset);
>  
>   if (length <= page_size) {
> - *prp2 = (u64)buffer;
> + *prp2 = nvme_virt_to_bus(dev, buffer);
>   return 0;
>   }
>  
> @@ -120,16 +120,16 @@ static int nvme_setup_prps(struct nvme_dev *dev,
> u64 *prp2,
>   i = 0;
>   while (nprps) {
>   if (i == prps_per_page) {
> - u64 next_prp_list = (u64)prp_pool + page_size;
> - *(prp_pool + i) = cpu_to_le64(next_prp_list);
> + u64 next = nvme_virt_to_bus(dev, prp_pool + page_size);
> + *(prp_pool + i) = cpu_to_le64(next);
>   i = 0;
>   prp_pool += page_size;
>   }
> - *(prp_pool + i++) = cpu_to_le64((u64)buffer);
> + *(prp_pool + i++) = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
>   buffer += page_size;
>   nprps--;
>   }
> - *prp2 = (u64)dev->prp_pool;
> + *prp2 = nvme_virt_to_bus(dev, dev->prp_pool);
>  
>   flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool +
>  dev->prp_entry_num * sizeof(u64));
> @@ -356,6 +356,7 @@ static int nvme_configure_admin_queue(struct nvme_dev 
> *dev)
>   int result;
>   u32 aqa;
>   u64 cap = dev->cap;
> + u64 dma_addr;
>   struct nvme_queue *nvmeq;
>   /* most architectures use 4KB as the page size */
>   unsigned page_shift = 12;
> @@ -396,8 +397,10 @@ static int nvme_configure_admin_queue(struct nvme_dev 
> *dev)
>   dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
>  
>   writel(aqa, >bar->aqa);
> - nvme_writeq((ulong)nvmeq->sq_cmds, >bar->asq);
> - nvme_writeq((ulong)nvmeq->cqes, >bar->acq);
> + dma_addr = nvme_virt_to_bus(dev, nvmeq->sq_cmds);
> + nvme_writeq(dma_addr, >bar->asq);
> + dma_addr = nvme_virt_to_bus(dev, nvmeq->cqes);
> + nvme_writeq(dma_addr, >bar->acq);
>  
>   result = nvme_enable_ctrl(dev);
>   if (result)
> @@ -423,7 +426,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid,
>  
>   memset(, 0, sizeof(c));
>   c.create_cq.opcode = nvme_admin_create_cq;
> - c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes);
> + c.create_cq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->cqes));
>   c.create_cq.cqid = cpu_to_le16(qid);
>   c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
>   c.create_cq.cq_flags = cpu_to_le16(flags);
> @@ -440,7 +443,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid,
>  
>   memset(, 0, sizeof(c));
>   c.create_sq.opcode = nvme_admin_create_sq;
> - c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds);
> + c.create_sq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->sq_cmds));
>   c.create_sq.sqid = cpu_to_le16(qid);
>   c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
>   c.create_sq.sq_flags = cpu_to_le16(flags);
> @@ -461,14 +464,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,
>   memset(, 0, sizeof(c));
>   c.identify.opcode = nvme_admin_identify;
>   c.identify.nsid = cpu_to_le32(nsid);
> - c.identify.prp1 = cpu_to_le64((u64)buffer);
> + c.identify.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
>  
>   length -= (page_size - offset);
>   if (length <= 0) {
>   c.identify.prp2 = 0;
>   } else {
>   buffer += (page_size - offset);
> - c.identify.prp2 = cpu_to_le64((u64)buffer);
> + c.identify.prp2 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
>   }
>  
>   c.identify.cns = cpu_to_le32(cns);
> @@ -493,7 +496,7 @@ int nvme_get_features(struct nvme_dev *dev,
> unsigned fid, unsigned nsid,
>   memset(, 0, sizeof(c));
>   c.features.opcode =

[RFC PATCH 3/4] nvme: Use pointer for CPU addressed buffers

Pass buffers which use CPU addressing as void pointers. This aligns with
DMA APIs which use void pointers as argument. It will avoid unnecessary
type casts when adding support bus address translations.

Signed-off-by: Stefan Agner 
---

 drivers/nvme/nvme.c  | 50 
 drivers/nvme/nvme_show.c |  4 ++--
 include/nvme.h   | 12 +-
 3 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 677e66b1bb..4c4dc7cc4d 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -74,11 +74,11 @@ static int nvme_wait_ready(struct nvme_dev *dev, bool 
enabled)
 }
 
 static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
-  int total_len, u64 dma_addr)
+  int total_len, void *buffer)
 {
const u32 page_size = dev->page_size;
const u32 prps_per_page = (page_size >> 3) - 1;
-   int offset = dma_addr & (page_size - 1);
+   int offset = (uintptr_t)buffer & (page_size - 1);
u64 *prp_pool;
int length = total_len;
int i, nprps;
@@ -92,10 +92,10 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
}
 
if (length)
-   dma_addr += (page_size - offset);
+   buffer += (page_size - offset);
 
if (length <= page_size) {
-   *prp2 = dma_addr;
+   *prp2 = (u64)buffer;
return 0;
}
 
@@ -125,11 +125,11 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 
*prp2,
i = 0;
prp_pool += page_size;
}
-   *(prp_pool + i++) = cpu_to_le64(dma_addr);
-   dma_addr += page_size;
+   *(prp_pool + i++) = cpu_to_le64((u64)buffer);
+   buffer += page_size;
nprps--;
}
-   *prp2 = (ulong)dev->prp_pool;
+   *prp2 = (u64)dev->prp_pool;
 
flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool +
   dev->prp_entry_num * sizeof(u64));
@@ -450,42 +450,42 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid,
 }
 
 int nvme_identify(struct nvme_dev *dev, unsigned nsid,
- unsigned cns, dma_addr_t dma_addr)
+ unsigned int cns, void *buffer)
 {
struct nvme_command c;
u32 page_size = dev->page_size;
-   int offset = dma_addr & (page_size - 1);
+   int offset = (uintptr_t)buffer & (page_size - 1);
int length = sizeof(struct nvme_id_ctrl);
int ret;
 
memset(, 0, sizeof(c));
c.identify.opcode = nvme_admin_identify;
c.identify.nsid = cpu_to_le32(nsid);
-   c.identify.prp1 = cpu_to_le64(dma_addr);
+   c.identify.prp1 = cpu_to_le64((u64)buffer);
 
length -= (page_size - offset);
if (length <= 0) {
c.identify.prp2 = 0;
} else {
-   dma_addr += (page_size - offset);
-   c.identify.prp2 = cpu_to_le64(dma_addr);
+   buffer += (page_size - offset);
+   c.identify.prp2 = cpu_to_le64((u64)buffer);
}
 
c.identify.cns = cpu_to_le32(cns);
 
-   invalidate_dcache_range(dma_addr,
-   dma_addr + sizeof(struct nvme_id_ctrl));
+   invalidate_dcache_range((uintptr_t)buffer,
+   (uintptr_t)buffer + sizeof(struct 
nvme_id_ctrl));
 
ret = nvme_submit_admin_cmd(dev, , NULL);
if (!ret)
-   invalidate_dcache_range(dma_addr,
-   dma_addr + sizeof(struct nvme_id_ctrl));
+   invalidate_dcache_range((uintptr_t)buffer,
+   (uintptr_t)buffer + sizeof(struct 
nvme_id_ctrl));
 
return ret;
 }
 
 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
- dma_addr_t dma_addr, u32 *result)
+ void *buffer, u32 *result)
 {
struct nvme_command c;
int ret;
@@ -493,7 +493,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, 
unsigned nsid,
memset(, 0, sizeof(c));
c.features.opcode = nvme_admin_get_features;
c.features.nsid = cpu_to_le32(nsid);
-   c.features.prp1 = cpu_to_le64(dma_addr);
+   c.features.prp1 = cpu_to_le64((u64)buffer);
c.features.fid = cpu_to_le32(fid);
 
ret = nvme_submit_admin_cmd(dev, , result);
@@ -513,13 +513,13 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, 
unsigned nsid,
 }
 
 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
- dma_addr_t dma_addr, u32 *result)
+ void *buffer, u32 *result)
 {
struct nvme_command c;
 
memset(, 0, sizeof(c));
c.features.opcode = nvme_admin_set_features;
-   c.features.prp1 = cpu_to_le64(dma_addr);
+   c.features.prp1 =

[RFC PATCH 4/4] nvme: translate virtual addresses into the bus's address space

So far we've been content with passing physical/CPU addresses when
configuring memory addresses into NVMe controllers, but not all
platforms have buses with transparent mappings. Specifically the
Raspberry Pi 4 might introduce an offset to memory accesses incoming
from its PCIe port.

Introduce nvme_virt_to_bus() and nvme_bus_to_virt() to cater with these
limitations, and make sure we don't break non DM users.
For devices where PCIe's view of host memory doesn't match the memory
as seen by the CPU.

A similar change has been introduced for XHCI controller with
commit 1a474559d90a ("xhci: translate virtual addresses into the bus's
address space").

Signed-off-by: Stefan Agner 
---

 drivers/nvme/nvme.c | 32 ++--
 drivers/nvme/nvme.h | 15 +++
 2 files changed, 33 insertions(+), 14 deletions(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 4c4dc7cc4d..0b7082d71b 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -95,7 +95,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
buffer += (page_size - offset);
 
if (length <= page_size) {
-   *prp2 = (u64)buffer;
+   *prp2 = nvme_virt_to_bus(dev, buffer);
return 0;
}
 
@@ -120,16 +120,16 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 
*prp2,
i = 0;
while (nprps) {
if (i == prps_per_page) {
-   u64 next_prp_list = (u64)prp_pool + page_size;
-   *(prp_pool + i) = cpu_to_le64(next_prp_list);
+   u64 next = nvme_virt_to_bus(dev, prp_pool + page_size);
+   *(prp_pool + i) = cpu_to_le64(next);
i = 0;
prp_pool += page_size;
}
-   *(prp_pool + i++) = cpu_to_le64((u64)buffer);
+   *(prp_pool + i++) = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
buffer += page_size;
nprps--;
}
-   *prp2 = (u64)dev->prp_pool;
+   *prp2 = nvme_virt_to_bus(dev, dev->prp_pool);
 
flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool +
   dev->prp_entry_num * sizeof(u64));
@@ -356,6 +356,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
int result;
u32 aqa;
u64 cap = dev->cap;
+   u64 dma_addr;
struct nvme_queue *nvmeq;
/* most architectures use 4KB as the page size */
unsigned page_shift = 12;
@@ -396,8 +397,10 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
 
writel(aqa, >bar->aqa);
-   nvme_writeq((ulong)nvmeq->sq_cmds, >bar->asq);
-   nvme_writeq((ulong)nvmeq->cqes, >bar->acq);
+   dma_addr = nvme_virt_to_bus(dev, nvmeq->sq_cmds);
+   nvme_writeq(dma_addr, >bar->asq);
+   dma_addr = nvme_virt_to_bus(dev, nvmeq->cqes);
+   nvme_writeq(dma_addr, >bar->acq);
 
result = nvme_enable_ctrl(dev);
if (result)
@@ -423,7 +426,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid,
 
memset(, 0, sizeof(c));
c.create_cq.opcode = nvme_admin_create_cq;
-   c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes);
+   c.create_cq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->cqes));
c.create_cq.cqid = cpu_to_le16(qid);
c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
c.create_cq.cq_flags = cpu_to_le16(flags);
@@ -440,7 +443,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid,
 
memset(, 0, sizeof(c));
c.create_sq.opcode = nvme_admin_create_sq;
-   c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds);
+   c.create_sq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->sq_cmds));
c.create_sq.sqid = cpu_to_le16(qid);
c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
c.create_sq.sq_flags = cpu_to_le16(flags);
@@ -461,14 +464,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,
memset(, 0, sizeof(c));
c.identify.opcode = nvme_admin_identify;
c.identify.nsid = cpu_to_le32(nsid);
-   c.identify.prp1 = cpu_to_le64((u64)buffer);
+   c.identify.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
 
length -= (page_size - offset);
if (length <= 0) {
c.identify.prp2 = 0;
} else {
buffer += (page_size - offset);
-   c.identify.prp2 = cpu_to_le64((u64)buffer);
+   c.identify.prp2 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
}
 
c.identify.cns = cpu_to_le32(cns);
@@ -493,7 +496,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, 
unsigned nsid,
memset(, 0, sizeof(c));
c.features.opcode = nvme_admin_get_features;
c.features.nsid = cpu_to_le32(nsid);
-   c.features.prp1 = cpu_to_le64((u64)buffer);
+

[RFC PATCH 1/4] Revert "nvme: Correct the prps per page calculation method"

This reverts commit 859b33c948945f7904f60a2c12a3792d356d51ad.

If there is more than one PRP List the last entry is a pointer to
the next list. From the NVM Express specification:

"The last entry within a memory page, as indicated by the memory page
size in the CC.MPS field, shall be a PRP List pointer if there is more
than a single memory page of data to be transferred."

For the purpose of calculating the number of pages required for PRP
lists we should always assume that the last entry is required for
the next PRP list.

Signed-off-by: Stefan Agner 
Cc: Wesley Sheng 
---

 drivers/nvme/nvme.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index f6465ea7f4..1ae3001a90 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -81,7 +81,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
u64 *prp_pool;
int length = total_len;
int i, nprps;
-   u32 prps_per_page = page_size >> 3;
+   u32 prps_per_page = (page_size >> 3) - 1;
u32 num_pages;
 
length -= (page_size - offset);
-- 
2.33.0

[RFC PATCH 2/4] nvme: improve readability of nvme_setup_prps()

Improve readability by introducing consts, reuse consts where
appropriate and adding variables with discriptive name.

Signed-off-by: Stefan Agner 
---

 drivers/nvme/nvme.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 1ae3001a90..677e66b1bb 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -76,12 +76,12 @@ static int nvme_wait_ready(struct nvme_dev *dev, bool 
enabled)
 static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
   int total_len, u64 dma_addr)
 {
-   u32 page_size = dev->page_size;
+   const u32 page_size = dev->page_size;
+   const u32 prps_per_page = (page_size >> 3) - 1;
int offset = dma_addr & (page_size - 1);
u64 *prp_pool;
int length = total_len;
int i, nprps;
-   u32 prps_per_page = (page_size >> 3) - 1;
u32 num_pages;
 
length -= (page_size - offset);
@@ -119,9 +119,9 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
prp_pool = dev->prp_pool;
i = 0;
while (nprps) {
-   if (i == ((page_size >> 3) - 1)) {
-   *(prp_pool + i) = cpu_to_le64((ulong)prp_pool +
-   page_size);
+   if (i == prps_per_page) {
+   u64 next_prp_list = (u64)prp_pool + page_size;
+   *(prp_pool + i) = cpu_to_le64(next_prp_list);
i = 0;
prp_pool += page_size;
}
-- 
2.33.0

Re: [PATCH v2 00/15] Add CAAM driver model support

2021-09-23 Thread Tim Harvey

On Fri, Sep 3, 2021 at 12:04 AM Gaurav Jain  wrote:
>
> This patchset adds the support for following:
> 1) CAAM Driver model for all i.MX, layerscape, PPC platforms.
> 2) Added crypto node in device tree files.
> 3) CAAM support for blob key encryption key(bkek), random number generation.
> 4) fixed hwrng performance issue in kernel.
>
> i.MX platforms:
> i.MX6, i.MX7, i.MX7ULP, i.MX8MM/MN/MP/MQ, i.MX8QM/QXP
>
> Layerscape platforms:
> LS1021, LS1012, LS1028, LS1043, LS1046, LS1088, LS2088, LX2160, LX2162
>
> Powerpc platforms:
> P3041, P4080, P5040, P2041, T1024, T1042, T2080, T4240
>
> Gaurav Jain (14):
>   crypto/fsl: Add support for CAAM Job ring driver model
>   crypto/fsl: Add CAAM support for bkek, random number generation
>   i.MX8M: crypto: updated device tree for supporting DM in SPL
>   crypto/fsl: i.MX8M: Enable Job ring driver model in SPL and U-Boot.
>   i.MX6: Enable Job ring driver model in U-Boot.
>   i.MX7: Enable Job ring driver model in U-Boot.
>   i.MX7ULP: Enable Job ring driver model in U-Boot.
>   i.MX8: Add crypto node in device tree
>   crypto/fsl: i.MX8: Enable Job ring driver model in SPL and U-Boot.
>   Layerscape: Add crypto node in device tree
>   Layerscape: Enable Job ring driver model in U-Boot.
>   PPC: Add crypto node in device tree
>   PPC: Enable Job ring driver model in U-Boot
>   update CAAM MAINTAINER
>
> Ye Li (1):
>   crypto/fsl: Fix kick_trng
>

Gaurav,

I am interested in seeing support added to provide a command to
blob/deblob data using CAAM. Peng submitted previously a patch
'crypto: caam: Add fsl caam driver' [1] which was not merged because
it was adding a new CAAM driver instead of adding functionality to the
existing one. Peng's patch added driver support and added a 'caam'
command to allow 'caam genblob' and 'caam decap'.

If that is what you are trying to do in this series I see you add a
function derive_blob_kek but it appears to be not used anywhere. Were
you going to also add a command or add this to the 'dek_blob' command?

Best regards,

Tim

[1] 
https://patchwork.ozlabs.org/project/uboot/patch/20210325093036.3270101-32-peng@oss.nxp.com/

Re: [EXT] Re: [PATCH v2 03/15] i.MX8M: crypto: updated device tree for supporting DM in SPL

2021-09-23 Thread Tim Harvey

On Sun, Sep 12, 2021 at 9:55 PM Gaurav Jain  wrote:
>
> Hello Tim,
>
> > -Original Message-
> > From: Tim Harvey 
> > Sent: Friday, September 10, 2021 8:17 PM
> > To: Gaurav Jain 
> > Cc: u-boot ; Stefano Babic ; Fabio
> > Estevam ; Peng Fan ; Simon Glass
> > ; Priyanka Jain ; Ye Li
> > ; Horia Geanta ; Ji Luo
> > ; Franck Lenormand ; Silvano Di
> > Ninno ; Sahil Malhotra ;
> > Pankaj Gupta ; Varun Sethi ; dl-
> > uboot-imx ; Shengzhou Liu ;
> > Mingkai Hu ; Rajesh Bhagat ;
> > Meenakshi Aggarwal ; Wasim Khan
> > ; Alison Wang ; Pramod
> > Kumar ; Andy Tang ;
> > Adrian Alonso ; Vladimir Oltean 
> > Subject: [EXT] Re: [PATCH v2 03/15] i.MX8M: crypto: updated device tree for
> > supporting DM in SPL
> >
> > Caution: EXT Email
> >
> > On Fri, Sep 3, 2021 at 12:04 AM Gaurav Jain  wrote:
> > >
> > > disabled use of JR0 in SPL and uboot, as JR0 is reserved for secure
> > > boot.
> > >
> > > Signed-off-by: Gaurav Jain 
> > > ---
> > >  arch/arm/dts/imx8mm-evk-u-boot.dtsi  | 18 +-
> > >  arch/arm/dts/imx8mm.dtsi |  1 +
> > >  arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 18 +-
> > >  arch/arm/dts/imx8mn.dtsi |  1 +
> > >  arch/arm/dts/imx8mp-evk-u-boot.dtsi  | 18 +-
> > >  arch/arm/dts/imx8mp.dtsi |  1 +
> > >  arch/arm/dts/imx8mq.dtsi |  1 +
> > >  7 files changed, 55 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > > b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > > index f200afac9f..3c2502cbba 100644
> > > --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > > +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > > @@ -1,6 +1,6 @@
> > >  // SPDX-License-Identifier: GPL-2.0+
> > >  /*
> > > - * Copyright 2019 NXP
> > > + * Copyright 2019, 2021 NXP
> > >   */
> > >
> > >  #include "imx8mm-u-boot.dtsi"
> > > @@ -72,6 +72,22 @@
> > > u-boot,dm-spl;
> > >  };
> > >
> > > + {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > > +_jr0 {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > > +_jr1 {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > > +_jr2 {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > >   {
> > > u-boot,dm-spl;
> > >  };
> > > diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index
> > > b142b80734..00bf3a 100644
> > > --- a/arch/arm/dts/imx8mm.dtsi
> > > +++ b/arch/arm/dts/imx8mm.dtsi
> > > @@ -824,6 +824,7 @@
> > > compatible = 
> > > "fsl,sec-v4.0-job-ring";
> > > reg = <0x1000 0x1000>;
> > > interrupts =  > > IRQ_TYPE_LEVEL_HIGH>;
> > > +   status = "disabled";
> > > };
> > >
> > > sec_jr1: jr@2000 { diff --git
> > > a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > > b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > > index 1d3844437d..b462d24eb2 100644
> > > --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > > +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > > @@ -1,6 +1,6 @@
> > >  // SPDX-License-Identifier: GPL-2.0+
> > >  /*
> > > - * Copyright 2019 NXP
> > > + * Copyright 2019, 2021 NXP
> > >   */
> > >
> > >  / {
> > > @@ -104,6 +104,22 @@
> > > u-boot,dm-spl;
> > >  };
> > >
> > > + {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > > +_jr0 {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > > +_jr1 {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > > +_jr2 {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > >   {
> > > u-boot,dm-spl;
> > >  };
> > > diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index
> > > edcb415b53..1820a5af37 100644
> > > --- a/arch/arm/dts/imx8mn.dtsi
> > > +++ b/arch/arm/dts/imx8mn.dtsi
> > > @@ -822,6 +822,7 @@
> > >  compatible = 
> > > "fsl,sec-v4.0-job-ring";
> > >  reg = <0x1000 0x1000>;
> > >  interrupts =  > > IRQ_TYPE_LEVEL_HIGH>;
> > > +status = "disabled";
> > > };
> > >
> > > sec_jr1: jr@2000 { diff --git
> > > a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > > b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > > index 2abcf1f03d..5415d5b617 100644
> > > --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > > +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> > > @@ -1,6 +1,6 @@
> > >  // SPDX-License-Identifier: GPL-2.0+
> > >  /*
> > > - * Copyright 2019 NXP
> > > + * Copyright 2019, 2021 NXP
> > >   */
> > >
> > >  #include "imx8mp-u-boot.dtsi"
> > > @@ -67,6 +67,22 @@
> > > u-boot,dm-spl;
> > >  };
> > >
> > > + {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > > +_jr0 {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > > +_jr1 {
> > > +   u-boot,dm-spl;
> > > +};
> > > +
> > > +_jr2 {
> > > +

Re: [PULL] u-boot-socfpga/master

On Thu, Sep 23, 2021 at 12:36:27AM +0200, Marek Vasut wrote:

> Bugfixes for this one socfpga platform, should go into 2021.10
> 
> The following changes since commit a49930f4c6ed5dcbf5127f7bf6d189afa92bffb3:
> 
>   Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-09-22
> 11:43:12 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-socfpga.git master
> 
> for you to fetch changes up to 532010da67329a1c3dbe92a167486df6e61d4f4a:
> 
>   ddr: altera: use KBUILD_BASENAME instead of __FILE__ (2021-09-22 21:31:05
> +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PULL] u-boot-usb/master

On Thu, Sep 23, 2021 at 12:35:44AM +0200, Marek Vasut wrote:

> Late bunch of USB fixes (incl. the xhci usb 3.1 support)
> 
> The following changes since commit a49930f4c6ed5dcbf5127f7bf6d189afa92bffb3:
> 
>   Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-09-22
> 11:43:12 -0400)
> 
> are available in the Git repository at:
> 
>   git://source.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to 53eed9adfac17921511ebf9e00c429bcb385d231:
> 
>   usb: xhci-dwc3: Add support for USB 3.1 controllers (2021-09-22 21:29:56
> +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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[PATCH] ARM: dts: imx: use generic name bus

2021-09-23 Thread Oleksandr Suvorov

Synchronize the u-boot and kernel imx device trees, using tuned
script from commit c0157bdcafa1 ("ARM: dts: imx: use generic name bus")

Per devicetree specification, generic names are recommended to be
used, such as bus.

i.MX AIPS is an AHB - IP bridge bus, so we could use bus as node
name.

Script:
sed -i "s/\
---

 arch/arm/dts/imx53-m53menlo-u-boot.dtsi | 2 +-
 arch/arm/dts/imx53.dtsi | 4 ++--
 arch/arm/dts/imx6dl.dtsi| 4 ++--
 arch/arm/dts/imx6q-display5-u-boot.dtsi | 2 +-
 arch/arm/dts/imx6q.dtsi | 2 +-
 arch/arm/dts/imx6qdl-u-boot.dtsi| 4 ++--
 arch/arm/dts/imx6qdl.dtsi   | 4 ++--
 arch/arm/dts/imx6qp.dtsi| 2 +-
 arch/arm/dts/imx6sl.dtsi| 4 ++--
 arch/arm/dts/imx6sll.dtsi   | 4 ++--
 arch/arm/dts/imx6sx.dtsi| 6 +++---
 arch/arm/dts/imx6ul.dtsi| 4 ++--
 arch/arm/dts/imx6ull.dtsi   | 2 +-
 arch/arm/dts/imx7s.dtsi | 6 +++---
 arch/arm/dts/vf.dtsi| 4 ++--
 15 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi 
b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
index bc4b3483a6..869adb9dad 100644
--- a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
+++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
@@ -7,7 +7,7 @@
soc {
u-boot,dm-pre-reloc;
 
-   aips@5000 {
+   bus@5000 {
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index ed341cfd9d..8536f59f59 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -222,7 +222,7 @@
clock-names = "core_clk", "mem_iface_clk";
};
 
-   aips@5000 { /* AIPS1 */
+   bus@5000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -654,7 +654,7 @@
};
};
 
-   aips@6000 { /* AIPS2 */
+   bus@6000 {  /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
index f0607eb41d..ae5aad6b9e 100644
--- a/arch/arm/dts/imx6dl.dtsi
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -84,7 +84,7 @@
clocks = < IMX6QDL_CLK_OCRAM>;
};
 
-   aips1: aips-bus@200 {
+   aips1: bus@200 {
iomuxc: iomuxc@20e {
compatible = "fsl,imx6dl-iomuxc";
};
@@ -100,7 +100,7 @@
};
};
 
-   aips2: aips-bus@210 {
+   aips2: bus@210 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/imx6q-display5-u-boot.dtsi 
b/arch/arm/dts/imx6q-display5-u-boot.dtsi
index aa660b5aeb..ced4dacc73 100644
--- a/arch/arm/dts/imx6q-display5-u-boot.dtsi
+++ b/arch/arm/dts/imx6q-display5-u-boot.dtsi
@@ -23,7 +23,7 @@
soc {
u-boot,dm-pre-reloc;
 
-   aips-bus@210 {
+   bus@210 {
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index 71543a4a68..c37484dce3 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -162,7 +162,7 @@
clocks = < IMX6QDL_CLK_OCRAM>;
};
 
-   aips-bus@200 { /* AIPS1 */
+   bus@200 { /* AIPS1 */
spba-bus@200 {
ecspi5: spi@2018000 {
#address-cells = <1>;
diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi
index 1279cc2338..f74af6c423 100644
--- a/arch/arm/dts/imx6qdl-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-u-boot.dtsi
@@ -13,14 +13,14 @@
u-boot,dm-spl;
u-boot,dm-pre-reloc;
 
-   aips-bus@200 {
+   bus@200 {
u-boot,dm-spl;
spba-bus@200 {
u-boot,dm-spl;
};
};
 
-   aips-bus@210 {
+   bus@210 {
u-boot,dm-spl;
};
};
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index e4daf15088..1cdb498c72 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -283,7 +283,7 @@
status = "disabled";
};
 
-

Re: [PATCH] imx8mn_beacon: Fix booting hang and switch to binman

2021-09-23 Thread Adam Ford

On Tue, Sep 14, 2021 at 9:49 PM Peng Fan (OSS)  wrote:
>
>
>
> On 2021/9/11 4:19, Adam Ford wrote:
> > Somewhere along the line, the board stopped being able to boot.
> > Rather than just fixing the issue, let's fix the issue and migrate
> > to binman to eliminate a warning when using custom imx tools for
> > generating the binary.
> >

Any chance this can make it into 2021.10?  it's currently broken, and
this seems to fix the problem.  i didn't bisect to see where the issue
broke, or i would have added a fixes tag.

adam
> > Signed-off-by: Adam Ford 
> >
> > diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi 
> > b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> > index bbc64a2819..69fd69c8d0 100644
> > --- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> > +++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> > @@ -4,6 +4,10 @@
> >*/
> >
> >   / {
> > + binman: binman {
> > + multiple-images;
> > + };
> > +
> >   wdt-reboot {
> >   compatible = "wdt-reboot";
> >   wdt = <>;
> > @@ -40,6 +44,9 @@
> >{
> >   u-boot,dm-spl;
> >   u-boot,dm-pre-reloc;
> > + /delete-property/ assigned-clocks;
> > + /delete-property/ assigned-clock-parents;
> > + /delete-property/ assigned-clock-rates;
> >   };
> >
> >{
> > @@ -99,6 +106,10 @@
> >   u-boot,off-on-delay-us = <2>;
> >   };
> >
> > + {
> > + u-boot,dm-spl;
> > +};
> > +
> >{
> >   u-boot,dm-spl;
> >   sd-uhs-sdr104;
> > @@ -120,3 +131,122 @@
> >{
> >   u-boot,dm-spl;
> >   };
> > +
> > + {
> > +  u-boot-spl-ddr {
> > + filename = "u-boot-spl-ddr.bin";
> > + pad-byte = <0xff>;
> > + align-size = <4>;
> > + align = <4>;
> > +
> > + u-boot-spl {
> > + align-end = <4>;
> > + };
> > +
> > + blob_1: blob-ext@1 {
> > + filename = "lpddr4_pmu_train_1d_imem.bin";
> > + size = <0x8000>;
> > + };
> > +
> > + blob_2: blob-ext@2 {
> > + filename = "lpddr4_pmu_train_1d_dmem.bin";
> > + size = <0x4000>;
> > + };
> > +
> > + blob_3: blob-ext@3 {
> > + filename = "lpddr4_pmu_train_2d_imem.bin";
> > + size = <0x8000>;
> > + };
> > +
> > + blob_4: blob-ext@4 {
> > + filename = "lpddr4_pmu_train_2d_dmem.bin";
> > + size = <0x4000>;
> > + };
> > + };
> > +
> > +
> > + spl {
> > + filename = "spl.bin";
> > +
> > + mkimage {
> > + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 
> > 0x912000";
> > +
> > + blob {
> > + filename = "u-boot-spl-ddr.bin";
> > + };
> > + };
> > + };
> > +
> > + itb {
> > + filename = "u-boot.itb";
> > +
> > + fit {
> > + description = "Configuration to load ATF before 
> > U-Boot";
> > + #address-cells = <1>;
> > + fit,external-offset = ;
> > +
> > + images {
> > + uboot {
> > + description = "U-Boot (64-bit)";
> > + type = "standalone";
> > + arch = "arm64";
> > + compression = "none";
> > + load = ;
> > +
> > + uboot_blob: blob-ext {
> > + filename = "u-boot-nodtb.bin";
> > + };
> > + };
> > +
> > + atf {
> > + description = "ARM Trusted Firmware";
> > + type = "firmware";
> > + arch = "arm64";
> > + compression = "none";
> > + load = <0x96>;
> > + entry = <0x96>;
> > +
> > + atf_blob: blob-ext {
> > + filename = "bl31.bin";
> > + };
> > + };
> > +
> > + fdt {
> > + description = "NAME";
> > + type = "flat_dt";
> > + compression = "none";
> > +
> > + uboot_fdt_blob: blob-ext {
> > + filename = "u-boot.dtb";
> > + };
> > + };
> > + };

Re: [PATCH] mtd: sf: Set SF parameters as env variables

2021-09-23 Thread Marek Vasut


On 9/23/21 8:53 PM, Pratyush Yadav wrote:

On 14/09/21 05:28AM, Marek Vasut wrote:

Set the SF page size, erase block size and total size as an environment
variable after "sf probe". This lets us discern boards with multiple
distinct SPI flash options and also e.g. set mtdparts accordingly.


I don't quite follow the rationale for making these environment
variables. Wouldn't you be better off finding this info out via mtd or
sf command?


I need to use that info in a script, that's why these env vars.

Re: [PATCH v6 3/3] arm64: Kconfig: Enable usage of optimized memset/memcpy/memmove

On Thu, Sep 02, 2021 at 05:00:19PM +0200, Stefan Roese wrote:

> This patch enables the use of the optimized memset(), memmove() &
> memcpy() versions recently added on ARM64.
> 
> Please note that these optimized functions are now only enabled for
> recent GCC versions (>= 9.4), as earlier GCC versions throw these
> errors:
> 
> aarch64-linux-ar: warning: arch/arm/lib/memset-arm64.o: unsupported 
> GNU_PROPERTY_TYPE (5) type: 0xc000
> ...
> 
> Signed-off-by: Stefan Roese 

So, I'm tempted to re-do this patch with default off, on ARM64.  As-is,
this causes failure to boot on two similar but different TI platforms
(am65x_evm_a53, j721e_evm_a72) and my amlogic Le Potato (libretech-cc).
This seems to be fine on my Pi 3.

-- 
Tom

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[PATCH 6/6 v3] board: samsung: add Samsung Galaxy S9/S9+(SM-G96x0) board

From: Dzmitry Sankouski 

Samsung S9 SM-G9600 - Snapdragon SDM845 version of the phone,
for China \ Hong Kong markets.
Has unlockable bootloader, unlike SM-G960U (American market version),
which allows running u-boot as a chain-loaded bootloader.

Signed-off-by: Dzmitry Sankouski 
Cc: Ramon Fried 
Cc: Tom Rini 
---
Changes for v2:
- Create documentation file for SDM845 boards
- Add starqltechn board documentation
Changes for v3:
- fix comment in starqltechn.c

 arch/arm/dts/Makefile   |  1 +
 arch/arm/dts/starqltechn-uboot.dtsi | 39 ++
 arch/arm/dts/starqltechn.dts| 53 +
 arch/arm/mach-snapdragon/Kconfig| 13 ++
 board/samsung/starqltechn/Kconfig   | 14 +++
 board/samsung/starqltechn/MAINTAINERS   |  6 +++
 board/samsung/starqltechn/Makefile  |  9 +
 board/samsung/starqltechn/starqltechn.c | 10 +
 configs/starqltechn_defconfig   | 33 +++
 doc/board/qualcomm/index.rst|  1 +
 doc/board/qualcomm/sdm845.rst   | 38 ++
 include/configs/starqltechn.h   | 16 
 12 files changed, 233 insertions(+)
 create mode 100644 arch/arm/dts/starqltechn-uboot.dtsi
 create mode 100644 arch/arm/dts/starqltechn.dts
 create mode 100644 board/samsung/starqltechn/Kconfig
 create mode 100644 board/samsung/starqltechn/MAINTAINERS
 create mode 100644 board/samsung/starqltechn/Makefile
 create mode 100644 board/samsung/starqltechn/starqltechn.c
 create mode 100644 configs/starqltechn_defconfig
 create mode 100644 doc/board/qualcomm/sdm845.rst
 create mode 100644 include/configs/starqltechn.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 82a0790cc0..90d922dab7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -467,6 +467,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
 
 dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
 dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
+dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
 
 dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
 
diff --git a/arch/arm/dts/starqltechn-uboot.dtsi 
b/arch/arm/dts/starqltechn-uboot.dtsi
new file mode 100644
index 00..d8d75e018a
--- /dev/null
+++ b/arch/arm/dts/starqltechn-uboot.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to handle Samsung S9 SM-G9600 (starqltechn) pins
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski 
+ *
+ */
+
+/
+{
+   soc {
+   u-boot,dm-pre-reloc;
+   gcc {
+   clock-controller@10 {
+   u-boot,dm-pre-reloc;
+   };
+   serial@0xa84000 {
+   u-boot,dm-pre-reloc;
+   };
+   gpio_north@390 {
+   u-boot,dm-pre-reloc;
+   };
+   pinctrl@390 {
+   u-boot,dm-pre-reloc;
+   };
+   };
+   };
+};
+
+_pon {
+   key_vol_down {
+   gpios = <_pon 1 0>;
+   label = "key_vol_down";
+   };
+   key_power {
+   gpios = <_pon 0 0>;
+   label = "key_power";
+   };
+};
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
new file mode 100644
index 00..387420f30b
--- /dev/null
+++ b/arch/arm/dts/starqltechn.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung S9 SM-G9600 (starqltechn) board device tree source
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski 
+ *
+ */
+
+/dts-v1/;
+
+#include "sdm845.dtsi"
+
+/ {
+   model = "Samsung S9 (SM-G9600)";
+   compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   };
+
+   aliases {
+   serial0 = _uart;
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0 0x8000 0 0xfe1b>;
+   };
+
+   psci {
+   compatible = "arm,psci-1.0";
+   method = "smc";
+   };
+
+   soc: soc {
+   serial@0xa84000 {
+   status = "ok";
+   };
+
+   pinctrl@390 {
+   muic_i2c: muic_i2c {
+   pins = "GPIO_33", "GPIO_34";
+   drive-strength = <0x2>;
+   function = "gpio";
+   bias-disable;
+   };
+   };
+   };
+};
+
+#include "starqltechn-uboot.dtsi"
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 1a6a608967..90c9fcca2c 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -40,9

[PATCH 5/6] SoC: qcom: add support for SDM845

From: Dzmitry Sankouski 

Hi-end qualcomm chip, introduced in late 2017.
Mostly used in flagship phones and tablets of 2018.
Features:
- arm64 arch
- total of 8 Kryo 385 Gold / Silver cores
- Hexagon 685 DSP
- Adreno 630 GPU

Tested only as second-stage bootloader.

Signed-off-by: Dzmitry Sankouski 
Cc: Ramon Fried 
Cc: Tom Rini 
---
 arch/arm/dts/sdm845.dtsi  | 118 ++
 arch/arm/mach-snapdragon/Kconfig  |   4 +
 arch/arm/mach-snapdragon/Makefile |   4 +
 .../include/mach/sysmap-sdm845.h  |  42 +++
 arch/arm/mach-snapdragon/init_sdm845.c|  82 
 arch/arm/mach-snapdragon/sysmap-sdm845.c  |  31 +
 include/configs/sdm845.h  |  33 +
 7 files changed, 314 insertions(+)
 create mode 100644 arch/arm/dts/sdm845.dtsi
 create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
 create mode 100644 arch/arm/mach-snapdragon/init_sdm845.c
 create mode 100644 arch/arm/mach-snapdragon/sysmap-sdm845.c
 create mode 100644 include/configs/sdm845.h

diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
new file mode 100644
index 00..bf32c6995d
--- /dev/null
+++ b/arch/arm/dts/sdm845.dtsi
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM845 chip device tree source
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski 
+ *
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+
+/ {
+   soc: soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0 0 0x>;
+   compatible = "simple-bus";
+
+   gcc: clock-controller@10 {
+   u-boot,dm-pre-reloc;
+   compatible = "qcom,gcc-sdm845";
+   reg = <0x0010 0x1f>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   #power-domain-cells = <1>;
+   };
+
+   gpio_north: gpio_north@390 {
+   u-boot,dm-pre-reloc;
+   #gpio-cells = <2>;
+   compatible = "qcom,sdm845-pinctrl";
+   reg = <0x390 0x40>;
+   gpio-count = <150>;
+   gpio-controller;
+   gpio-ranges = <_north 0 0 150>;
+   gpio-bank-name = "soc_north.";
+   };
+
+   tlmm_north: pinctrl_north@390 {
+   u-boot,dm-pre-reloc;
+   compatible = "qcom,tlmm-sdm845";
+   reg = <0x0390 0x40>;
+   gpio-count = <150>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   gpio-ranges = <_north 0 0 150>;
+
+   /* DEBUG UART */
+   qup_uart9: qup-uart9-default {
+   pinmux {
+   pins = "GPIO_4", "GPIO_5";
+   function = "qup9";
+   };
+   };
+   };
+
+   debug_uart: serial@0xa84000 {
+   compatible = "qcom,msm-geni-uart";
+   reg = <0xa84000 0x4000>;
+   reg-names = "se_phys";
+   clock-names = "se-clk";
+   clocks = < 0x58>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_uart9>;
+   qcom,wrapper-core = <0x8a>;
+   status = "disabled";
+   };
+
+   spmi@c44 {
+   compatible = "qcom,spmi-pmic-arb";
+   reg = <0xc44 0x1100>,
+ <0xc60 0x200>,
+ <0xe60 0x10>;
+   reg-names = "cnfg", "core", "obsrvr";
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+
+   qcom,revid@100 {
+   compatible = "qcom,qpnp-revid";
+   reg = <0x100 0x100>;
+   linux,phandle = <0x3ac>;
+   phandle = <0x3ac>;
+   };
+
+   pmic0: pm8998@0 {
+   compatible = "qcom,spmi-pmic";
+   reg = <0x0 0x1>;
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
+
+   pm8998_pon: pm8998_pon@800 {
+   compatible = "qcom,pm8998-pwrkey";
+   reg = <0x800 0x100>;
+   #gpio-cells = <2>;
+   gpio-controller;
+

[PATCH 3/6] pinctrl: qcom: add pinctrl and gpio drivers for SDM845 SoC

From: Dzmitry Sankouski 

Signed-off-by: Dzmitry Sankouski 
Cc: Ramon Fried 
Cc: Tom Rini 
---
 arch/arm/mach-snapdragon/pinctrl-sdm845.c | 44 +++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c |  1 +
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h |  1 +
 drivers/gpio/msm_gpio.c   |  1 +
 drivers/gpio/pm8916_gpio.c|  8 ++--
 5 files changed, 52 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-sdm845.c

diff --git a/arch/arm/mach-snapdragon/pinctrl-sdm845.c 
b/arch/arm/mach-snapdragon/pinctrl-sdm845.c
new file mode 100644
index 00..6d66582aa6
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-sdm845.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM845 pinctrl
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski 
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include 
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN];
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+   {"qup9", 1},
+   {"gpio", 0},
+};
+
+static const char *sdm845_get_function_name(struct udevice *dev,
+unsigned int selector)
+{
+   return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sdm845_get_pin_name(struct udevice *dev,
+   unsigned int selector)
+{
+   snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+   return pin_name;
+}
+
+static unsigned int sdm845_get_function_mux(unsigned int selector)
+{
+   return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data sdm845_data = {
+   .pin_count = 150,
+   .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+   .get_function_name = sdm845_get_function_name,
+   .get_function_mux = sdm845_get_function_mux,
+   .get_pin_name = sdm845_get_pin_name,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c 
b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index e6b87c3573..c0ed943036 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -116,6 +116,7 @@ static struct pinctrl_ops msm_pinctrl_ops = {
 static const struct udevice_id msm_pinctrl_ids[] = {
{ .compatible = "qcom,tlmm-apq8016", .data = (ulong)_data },
{ .compatible = "qcom,tlmm-apq8096", .data = (ulong)_data },
+   { .compatible = "qcom,tlmm-sdm845", .data = (ulong)_data },
{ }
 };
 
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h 
b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
index 61d466f4d8..ea524312a0 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -27,5 +27,6 @@ struct pinctrl_function {
 
 extern struct msm_pinctrl_data apq8016_data;
 extern struct msm_pinctrl_data apq8096_data;
+extern struct msm_pinctrl_data sdm845_data;
 
 #endif
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index e1ff84c1c0..a3c3cd7824 100644
--- a/drivers/gpio/msm_gpio.c
+++ b/drivers/gpio/msm_gpio.c
@@ -120,6 +120,7 @@ static const struct udevice_id msm_gpio_ids[] = {
{ .compatible = "qcom,msm8916-pinctrl" },
{ .compatible = "qcom,apq8016-pinctrl" },
{ .compatible = "qcom,ipq4019-pinctrl" },
+   { .compatible = "qcom,sdm845-pinctrl" },
{ }
 };
 
diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/pm8916_gpio.c
index 40b0f2578b..7ad95784a8 100644
--- a/drivers/gpio/pm8916_gpio.c
+++ b/drivers/gpio/pm8916_gpio.c
@@ -202,6 +202,7 @@ static int pm8916_gpio_of_to_plat(struct udevice *dev)
 static const struct udevice_id pm8916_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
{ .compatible = "qcom,pm8994-gpio" },   /* 22 GPIO's */
+   { .compatible = "qcom,pm8998-gpio" },
{ }
 };
 
@@ -266,7 +267,7 @@ static int pm8941_pwrkey_probe(struct udevice *dev)
return log_msg_ret("bad type", -ENXIO);
 
reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
-   if (reg != 0x1)
+   if ((reg & 0x5) == 0)
return log_msg_ret("bad subtype", -ENXIO);
 
return 0;
@@ -287,11 +288,12 @@ static int pm8941_pwrkey_of_to_plat(struct udevice *dev)
 static const struct udevice_id pm8941_pwrkey_ids[] = {
{ .compatible = "qcom,pm8916-pwrkey" },
{ .compatible = "qcom,pm8994-pwrkey" },
+   { .compatible = "qcom,pm8998-pwrkey" },
{ }
 };
 
-U_BOOT_DRIVER(pwrkey_pm8941) = {
-   .name   = "pwrkey_pm8916",
+U_BOOT_DRIVER(pwrkey_pm89xx) = {
+   .name   = "pwrkey_pm89xx",
.id = UCLASS_GPIO,
.of_match = pm8941_pwrkey_ids,
.of_to_plat = pm8941_pwrkey_of_to_plat,
-- 
2.20.1

[PATCH 2/6 v3] spmi: msm: add arbiter version 5 support

From: Dzmitry Sankouski 

Currently driver supports only version 1 and 2.
Version 5 has slightly different registers structure

Signed-off-by: Dzmitry Sankouski 
Cc: Ramon Fried 
Cc: Tom Rini 
---
Changes for v2:
- change string formats in debug statements
Changes for v3
- remove if else braces where possible

 MAINTAINERS |   1 +
 drivers/spmi/spmi-msm.c | 156 +++-
 2 files changed, 107 insertions(+), 50 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 52ddc99cda..6b8b0783d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -392,6 +392,7 @@ F:  drivers/phy/msm8916-usbh-phy.c
 F: drivers/serial/serial_msm.c
 F: drivers/serial/serial_msm_geni.c
 F: drivers/smem/msm_smem.c
+F: drivers/spmi/spmi-msm.c
 F: drivers/usb/host/ehci-msm.c
 
 ARM STI
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 5a335e50aa..c5bc55bc6f 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -19,39 +19,63 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* PMIC Arbiter configuration registers */
-#define PMIC_ARB_VERSION   0x
-#define PMIC_ARB_VERSION_V2_MIN0x2001
-
-#define ARB_CHANNEL_OFFSET(n)  (0x4 * (n))
-#define SPMI_CH_OFFSET(chnl)   ((chnl) * 0x8000)
-
-#define SPMI_REG_CMD0  0x0
-#define SPMI_REG_CONFIG0x4
-#define SPMI_REG_STATUS0x8
-#define SPMI_REG_WDATA 0x10
-#define SPMI_REG_RDATA 0x18
-
-#define SPMI_CMD_OPCODE_SHIFT  27
-#define SPMI_CMD_SLAVE_ID_SHIFT20
-#define SPMI_CMD_ADDR_SHIFT12
-#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
-#define SPMI_CMD_BYTE_CNT_SHIFT0
-
-#define SPMI_CMD_EXT_REG_WRITE_LONG0x00
-#define SPMI_CMD_EXT_REG_READ_LONG 0x01
-
-#define SPMI_STATUS_DONE   0x1
+#define PMIC_ARB_VERSION 0x
+#define PMIC_ARB_VERSION_V2_MIN 0x2001
+#define PMIC_ARB_VERSION_V3_MIN 0x3000
+#define PMIC_ARB_VERSION_V5_MIN 0x5000
+
+#define APID_MAP_OFFSET_V1_V2_V3 (0x800)
+#define APID_MAP_OFFSET_V5 (0x900)
+#define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
+#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
+#define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
+#define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x1)
+
+#define SPMI_REG_CMD0 0x0
+#define SPMI_REG_CONFIG 0x4
+#define SPMI_REG_STATUS 0x8
+#define SPMI_REG_WDATA 0x10
+#define SPMI_REG_RDATA 0x18
+
+#define SPMI_CMD_OPCODE_SHIFT 27
+#define SPMI_CMD_SLAVE_ID_SHIFT 20
+#define SPMI_CMD_ADDR_SHIFT 12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
+#define SPMI_CMD_BYTE_CNT_SHIFT 0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
+#define SPMI_CMD_EXT_REG_READ_LONG 0x01
+
+#define SPMI_STATUS_DONE 0x1
+
+#define SPMI_MAX_CHANNELS 128
+#define SPMI_MAX_SLAVES 16
+#define SPMI_MAX_PERIPH 256
+
+enum arb_ver {
+   V1 = 1,
+   V2,
+   V3,
+   V5 = 5
+};
 
-#define SPMI_MAX_CHANNELS  128
-#define SPMI_MAX_SLAVES16
-#define SPMI_MAX_PERIPH256
+/*
+ * PMIC arbiter version 5 uses different register offsets for read/write vs
+ * observer channels.
+ */
+enum pmic_arb_channel {
+   PMIC_ARB_CHANNEL_RW,
+   PMIC_ARB_CHANNEL_OBS,
+};
 
 struct msm_spmi_priv {
-   phys_addr_t arb_chnl; /* ARB channel mapping base */
+   phys_addr_t arb_chnl;  /* ARB channel mapping base */
phys_addr_t spmi_core; /* SPMI core */
-   phys_addr_t spmi_obs; /* SPMI observer */
+   phys_addr_t spmi_obs;  /* SPMI observer */
/* SPMI channel map */
uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+   /* SPMI bus arbiter version */
+   u32 arb_ver;
 };
 
 static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
@@ -59,6 +83,7 @@ static int msm_spmi_write(struct udevice *dev, int usid, int 
pid, int off,
 {
struct msm_spmi_priv *priv = dev_get_priv(dev);
unsigned channel;
+   unsigned int ch_offset;
uint32_t reg = 0;
 
if (usid >= SPMI_MAX_SLAVES)
@@ -69,8 +94,8 @@ static int msm_spmi_write(struct udevice *dev, int usid, int 
pid, int off,
channel = priv->channel_map[usid][pid];
 
/* Disable IRQ mode for the current channel*/
-   writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
-  SPMI_REG_CONFIG);
+   writel(0x0,
+  priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
 
/* Write single byte */
writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
@@ -82,6 +107,12 @@ static int msm_spmi_write(struct udevice *dev, int usid, 
int pid, int off,
reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
reg |= 1; /* byte count */
 
+   if (priv->arb_ver == V5) {
+   ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+   } else {
+   ch_offset = SPMI_CH_OFFSET(channel);
+   }
+
/* Send write command */

[PATCH 4/6] clocks: qcom: add clocks for SDM845 debug uart

From: Dzmitry Sankouski 

Allows to change clock frequency of debug uart,
thus supporting wide range of baudrates.
Enable / disable functionality is not implemented yet.
In most use cases of SDM845 (i.e. mobile phones and tablets)
it's not needed, because qualcomm first stage bootloader leaves it
initialized, and on the other hand there's no possibility to
replace signed first stage bootloader with u-boot.

Signed-off-by: Dzmitry Sankouski 
Cc: Ramon Fried 
Cc: Tom Rini 
---
 arch/arm/mach-snapdragon/clock-sdm845.c | 92 +
 arch/arm/mach-snapdragon/clock-snapdragon.c |  1 +
 arch/arm/mach-snapdragon/clock-snapdragon.h |  3 +-
 3 files changed, 95 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-snapdragon/clock-sdm845.c

diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c 
b/arch/arm/mach-snapdragon/clock-sdm845.c
new file mode 100644
index 00..9572639238
--- /dev/null
+++ b/arch/arm/mach-snapdragon/clock-sdm845.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm SDM845
+ *
+ * (C) Copyright 2017 Jorge Ramirez Ortiz 
+ * (C) Copyright 2021 Dzmitry Sankouski 
+ *
+ * Based on Little Kernel driver, simplified
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "clock-snapdragon.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+struct freq_tbl {
+   uint freq;
+   uint src;
+   u8 pre_div;
+   u16 m;
+   u16 n;
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+   F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+   F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+   F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
+   F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+   F(3200, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+   F(4800, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+   F(6400, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+   F(8000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+   F(9600, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+   F(1, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+   F(10240, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
+   F(11200, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
+   F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
+   F(12000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
+   F(12800, CFG_CLK_SRC_GPLL0, 1, 16, 75),
+   { }
+};
+
+static const struct bcr_regs uart2_regs = {
+   .cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
+   .cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
+   .M = SE9_UART_APPS_M,
+   .N = SE9_UART_APPS_N,
+   .D = SE9_UART_APPS_D,
+};
+
+const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
+{
+   if (!f)
+   return NULL;
+
+   if (!f->freq)
+   return f;
+
+   for (; f->freq; f++)
+   if (rate <= f->freq)
+   return f;
+
+   /* Default to our fastest rate */
+   return f - 1;
+}
+
+static int clk_init_uart(struct msm_clk_priv *priv, uint rate)
+{
+   const struct freq_tbl *freq = 
qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
+
+   clk_rcg_set_rate_mnd(priv->base, _regs,
+   freq->pre_div, freq->m, 
freq->n, freq->src);
+
+   return 0;
+}
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+   struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+   switch (clk->id) {
+   case 0x58: /*UART2*/
+   return clk_init_uart(priv, rate);
+   default:
+   return 0;
+   }
+}
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c 
b/arch/arm/mach-snapdragon/clock-snapdragon.c
index 2b76371718..3deb08ac4a 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -135,6 +135,7 @@ static const struct udevice_id msm_clk_ids[] = {
{ .compatible = "qcom,gcc-apq8016" },
{ .compatible = "qcom,gcc-msm8996" },
{ .compatible = "qcom,gcc-apq8096" },
+   { .compatible = "qcom,gcc-sdm845" },
{ }
 };
 
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h 
b/arch/arm/mach-snapdragon/clock-snapdragon.h
index 58fab40a2e..2ac53b538d 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.h
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Qualcomm APQ8016, APQ8096
+ * Qualcomm APQ8016, APQ8096, SDM845
  *
  * (C) Copyright 2017 Jorge Ramirez-Ortiz 
  */
@@ -9,6 +9,7 @@
 
 #define CFG_CLK_SRC_CXO   (0 << 8)
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
+#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
 #define CFG_CLK_SRC_MASK  (7 << 8)
 
 struct pll_vote_clk {
-- 
2.20.1

[PATCH 1/6 v3] serial: qcom: add support for GENI serial driver

From: Dzmitry Sankouski 

Generic Interface (GENI) Serial Engine (SE) based uart
can be found on newer qualcomm SOCs, starting from SDM845.
Tested on Samsung SM-G9600(starqltechn)
by chain-loading u-boot with stock bootloader.

Signed-off-by: Dzmitry Sankouski 
Cc: Ramon Fried 
Cc: Tom Rini 
---
Changes for v2:
- change functions return type to void, where possible
- remove '.' from summary line
Changes for v3:
- move function open brace on new line
- use tab between define name and value
- define: wrap expression with braces, remove braces from constants

 MAINTAINERS   |   1 +
 .../serial/msm-geni-serial.txt|   6 +
 drivers/serial/Kconfig|  17 +
 drivers/serial/Makefile   |   1 +
 drivers/serial/serial_msm_geni.c  | 602 ++
 5 files changed, 627 insertions(+)
 create mode 100644 doc/device-tree-bindings/serial/msm-geni-serial.txt
 create mode 100644 drivers/serial/serial_msm_geni.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 776ff703b9..52ddc99cda 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -390,6 +390,7 @@ F:  drivers/gpio/msm_gpio.c
 F: drivers/mmc/msm_sdhci.c
 F: drivers/phy/msm8916-usbh-phy.c
 F: drivers/serial/serial_msm.c
+F: drivers/serial/serial_msm_geni.c
 F: drivers/smem/msm_smem.c
 F: drivers/usb/host/ehci-msm.c
 
diff --git a/doc/device-tree-bindings/serial/msm-geni-serial.txt 
b/doc/device-tree-bindings/serial/msm-geni-serial.txt
new file mode 100644
index 00..9eadc2561b
--- /dev/null
+++ b/doc/device-tree-bindings/serial/msm-geni-serial.txt
@@ -0,0 +1,6 @@
+Qualcomm GENI UART
+
+Required properties:
+- compatible: must be "qcom,msm-geni-uart"
+- reg: start address and size of the registers
+- clock: interface clock (must accept baudrate as a frequency)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 93348c0929..b420a5720d 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -278,6 +278,14 @@ config DEBUG_UART_S5P
  will need to provide parameters to make this work. The driver will
  be available until the real driver-model serial is running.
 
+config DEBUG_UART_MSM_GENI
+   bool "Qualcomm snapdragon"
+   depends on ARCH_SNAPDRAGON
+   help
+ Select this to enable a debug UART using the serial_msm driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
 config DEBUG_UART_MESON
bool "Amlogic Meson"
depends on MESON_SERIAL
@@ -783,6 +791,15 @@ config MSM_SERIAL
  for example APQ8016 and MSM8916.
  Single baudrate is supported in current implementation (115200).
 
+config MSM_GENI_SERIAL
+   bool "Qualcomm on-chip GENI UART"
+   help
+ Support UART based on Generic Interface (GENI) Serial Engine (SE), 
used on Qualcomm Snapdragon SoCs.
+ Should support all qualcomm SOCs with Qualcomm Universal Peripheral 
(QUP) Wrapper cores,
+ i.e. newer ones, starting from SDM845.
+ Driver works in FIFO mode.
+ Multiple baudrates supported.
+
 config OCTEON_SERIAL_BOOTCMD
bool "MIPS Octeon PCI remote bootcmd input"
depends on ARCH_OCTEON
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 3cbea8156f..d44caf4ea2 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
 obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
 obj-$(CONFIG_BCM283X_PL011_SERIAL) += serial_bcm283x_pl011.o
 obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
+obj-$(CONFIG_MSM_GENI_SERIAL) += serial_msm_geni.o
 obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
 obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
 obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
new file mode 100644
index 00..391d47b538
--- /dev/null
+++ b/drivers/serial/serial_msm_geni.c
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm GENI serial engine UART driver
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski 
+ *
+ * Based on Linux driver.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define UART_OVERSAMPLING  32
+#define STALE_TIMEOUT  160
+#define SE_UART_RX_STALE_CNT   0x294
+#define S_GENI_CMD_ABORT   (BIT(1))
+
+#define SE_GENI_S_CMD_CTRL_REG 0x634
+#define SE_GENI_M_CMD_CTRL_REG 0x604
+
+/* GENI_M_CMD_CTRL_REG */
+#define M_GENI_CMD_CANCEL  (BIT(2))
+#define M_GENI_CMD_ABORT   (BIT(1))
+#define M_GENI_DISABLE (BIT(0))
+
+/* GENI_S_CMD0 fields */
+#define S_OPCODE_MSK   (GENMASK(31, 27))
+#define S_OPCODE_SHFT  27
+#define S_PARAMS_MSK   (GENMASK(26, 0))
+
+/* GENI_STATUS fields */
+#define M_GENI_CMD_ACTIVE  (BIT(0))
+#define S_GENI_CMD_ACTIVE

[PATCH 0/6] Add support for SDM845 based boards, and SM-G9600

From: Dzmitry Sankouski 

Snapdragon 845 - hi-end qualcomm chip, introduced in late 2017.
Mostly used in flagship phones and tablets of 2018.
Features:
- arm64 arch
- total of 8 Kryo 385 Gold / Silver cores
- Hexagon 685 DSP
- Adreno 630 GPU

Tested only as second-stage bootloader.

Samsung S9 SM-G9600 - Snapdragon SDM845 version of the phone,
for China \ Hong Kong markets.
Has unlockable bootloader, unlike SM-G960U (American market version),
which allows running u-boot as a chain-loaded bootloader.

Dzmitry Sankouski (6):
  serial: qcom: add support for GENI serial driver
  spmi: msm: add arbiter version 5 support
  pinctrl: qcom: add pinctrl and gpio drivers for SDM845  SoC
  clocks: qcom: add clocks for SDM845 debug uart
  SoC: qcom: add support for SDM845
  board: samsung: add Samsung Galaxy S9/S9+(SM-G96x0) board

 MAINTAINERS   |   2 +
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/sdm845.dtsi  | 118 
 arch/arm/dts/starqltechn-uboot.dtsi   |  39 ++
 arch/arm/dts/starqltechn.dts  |  53 ++
 arch/arm/mach-snapdragon/Kconfig  |  17 +
 arch/arm/mach-snapdragon/Makefile |   4 +
 arch/arm/mach-snapdragon/clock-sdm845.c   |  92 +++
 arch/arm/mach-snapdragon/clock-snapdragon.c   |   1 +
 arch/arm/mach-snapdragon/clock-snapdragon.h   |   3 +-
 .../include/mach/sysmap-sdm845.h  |  42 ++
 arch/arm/mach-snapdragon/init_sdm845.c|  82 +++
 arch/arm/mach-snapdragon/pinctrl-sdm845.c |  44 ++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c |   1 +
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h |   1 +
 arch/arm/mach-snapdragon/sysmap-sdm845.c  |  31 +
 board/samsung/starqltechn/Kconfig |  14 +
 board/samsung/starqltechn/MAINTAINERS |   6 +
 board/samsung/starqltechn/Makefile|   9 +
 board/samsung/starqltechn/starqltechn.c   |  10 +
 configs/starqltechn_defconfig |  33 +
 doc/board/qualcomm/index.rst  |   1 +
 doc/board/qualcomm/sdm845.rst |  38 ++
 .../serial/msm-geni-serial.txt|   6 +
 drivers/gpio/msm_gpio.c   |   1 +
 drivers/gpio/pm8916_gpio.c|   8 +-
 drivers/serial/Kconfig|  17 +
 drivers/serial/Makefile   |   1 +
 drivers/serial/serial_msm_geni.c  | 602 ++
 drivers/spmi/spmi-msm.c   | 156 +++--
 include/configs/sdm845.h  |  33 +
 include/configs/starqltechn.h |  16 +
 32 files changed, 1428 insertions(+), 54 deletions(-)
 create mode 100644 arch/arm/dts/sdm845.dtsi
 create mode 100644 arch/arm/dts/starqltechn-uboot.dtsi
 create mode 100644 arch/arm/dts/starqltechn.dts
 create mode 100644 arch/arm/mach-snapdragon/clock-sdm845.c
 create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
 create mode 100644 arch/arm/mach-snapdragon/init_sdm845.c
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-sdm845.c
 create mode 100644 arch/arm/mach-snapdragon/sysmap-sdm845.c
 create mode 100644 board/samsung/starqltechn/Kconfig
 create mode 100644 board/samsung/starqltechn/MAINTAINERS
 create mode 100644 board/samsung/starqltechn/Makefile
 create mode 100644 board/samsung/starqltechn/starqltechn.c
 create mode 100644 configs/starqltechn_defconfig
 create mode 100644 doc/board/qualcomm/sdm845.rst
 create mode 100644 doc/device-tree-bindings/serial/msm-geni-serial.txt
 create mode 100644 drivers/serial/serial_msm_geni.c
 create mode 100644 include/configs/sdm845.h
 create mode 100644 include/configs/starqltechn.h

-- 
2.20.1

Re: [PATCH] mtd: sf: Set SF parameters as env variables

2021-09-23 Thread Pratyush Yadav

On 14/09/21 05:28AM, Marek Vasut wrote:
> Set the SF page size, erase block size and total size as an environment
> variable after "sf probe". This lets us discern boards with multiple
> distinct SPI flash options and also e.g. set mtdparts accordingly.

I don't quite follow the rationale for making these environment 
variables. Wouldn't you be better off finding this info out via mtd or 
sf command?

> 
> Signed-off-by: Marek Vasut 
> Cc: Jagan Teki 
> Cc: Vignesh R 
> ---
>  drivers/mtd/spi/spi-nor-core.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index d5d905fa5a1..448653b9931 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -3829,8 +3830,11 @@ int spi_nor_scan(struct spi_nor *nor)
>  #ifndef CONFIG_SPL_BUILD
>   printf("SF: Detected %s with page size ", nor->name);
>   print_size(nor->page_size, ", erase size ");
> + env_set_hex("sf_pagesize", nor->page_size);
>   print_size(nor->erase_size, ", total ");
> + env_set_hex("sf_erasesize", nor->erase_size);
>   print_size(nor->size, "");
> + env_set_hex("sf_size", nor->size);
>   puts("\n");
>  #endif
>  
> -- 
> 2.33.0
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

[PATCH 10/10] dts: am57xx*: Add ipu early boot DT changes

From: Keerthy 

Add support for ipu early boot.

Signed-off-by: Keerthy 
Signed-off-by: Amjad Ouled-Ameur 

---

 MAINTAINERS  | 1 +
 arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi | 7 +++
 arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi  | 7 +++
 arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi   | 7 +++
 arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi | 7 +++
 arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi| 7 +++
 6 files changed, 36 insertions(+)
 create mode 100644 arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
 create mode 100644 arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
 create mode 100644 arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
 create mode 100644 arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
 create mode 100644 arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 404ad283ff4a..c9ce9991c8b0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -500,6 +500,7 @@ F:  arch/arm/mach-omap2/
 F: arch/arm/include/asm/arch-omap*/
 F: arch/arm/include/asm/ti-common/
 F: arch/arm/dts/dra7*
+F: arch/arm/dts/am57xx*
 F: board/ti/
 F: drivers/dma/ti*
 F: drivers/firmware/ti_sci.*
diff --git a/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi 
b/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
new file mode 100644
index ..49b16215e528
--- /dev/null
+++ b/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi 
b/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
new file mode 100644
index ..49b16215e528
--- /dev/null
+++ b/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi 
b/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
new file mode 100644
index ..49b16215e528
--- /dev/null
+++ b/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi 
b/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
new file mode 100644
index ..49b16215e528
--- /dev/null
+++ b/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi 
b/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi
new file mode 100644
index ..49b16215e528
--- /dev/null
+++ b/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
-- 
2.25.1

[PATCH 06/10] remoteproc: ipu: Add driver to bring up ipu

From: Keerthy 

The driver enables IPU support. Basically enables the clocks,
timers, watchdog timers and bare minimal MMU and supports
loading the firmware from mmc.

Signed-off-by: Keerthy 
[Amjad: fix compile warnings]
Signed-off-by: Amjad Ouled-Ameur 
---

 MAINTAINERS|   1 +
 drivers/remoteproc/Kconfig |  10 +
 drivers/remoteproc/Makefile|   1 +
 drivers/remoteproc/ipu_rproc.c | 759 +
 4 files changed, 771 insertions(+)
 create mode 100644 drivers/remoteproc/ipu_rproc.c

diff --git a/MAINTAINERS b/MAINTAINERS
index ce6e7ef08252..9e93c2785cf9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -515,6 +515,7 @@ F:  drivers/ram/k3*
 F: drivers/remoteproc/k3_system_controller.c
 F: drivers/remoteproc/pruc_rpoc.c
 F: drivers/remoteproc/ti*
+F: drivers/remoteproc/ipu_rproc.c
 F: drivers/reset/reset-ti-sci.c
 F: drivers/reset/reset-dra7.c
 F: drivers/rtc/davinci.c
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 24e536463bbd..27e4a60ff5b1 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -92,4 +92,14 @@ config REMOTEPROC_TI_PRU
help
  Say 'y' here to add support for TI' K3 remoteproc driver.
 
+config REMOTEPROC_TI_IPU
+   bool "Support for TI's K3 based IPU remoteproc driver"
+   select REMOTEPROC
+   depends on DM
+   depends on SPL_DRIVERS_MISC
+   depends on SPL_FS_LOADER
+   depends on OF_CONTROL
+   help
+ Say 'y' here to add support for TI' K3 remoteproc driver.
+
 endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index f0e83451d66f..fbe9c172bc04 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
 obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
+obj-$(CONFIG_REMOTEPROC_TI_IPU) += ipu_rproc.o
diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers/remoteproc/ipu_rproc.c
new file mode 100644
index ..b4a06bc955a9
--- /dev/null
+++ b/drivers/remoteproc/ipu_rproc.c
@@ -0,0 +1,759 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IPU remoteproc driver for various SoCs
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Angela Stegmaier  
+ * Venkateswara Rao Mandela 
+ *  Keerthy 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define IPU1_LOAD_ADDR (0xa17ff000)
+#define MAX_REMOTECORE_BIN_SIZE (8 * 0x10)
+
+enum ipu_num {
+   IPU1 = 0,
+   IPU2,
+   RPROC_END_ENUMS,
+};
+
+#define IPU2_LOAD_ADDR (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
+
+#define PAGE_SHIFT 12
+#define PAGESIZE_1M  0x0
+#define PAGESIZE_64K 0x1
+#define PAGESIZE_4K  0x2
+#define PAGESIZE_16M 0x3
+#define LE   0
+#define BE   1
+#define ELEMSIZE_8   0x0
+#define ELEMSIZE_16  0x1
+#define ELEMSIZE_32  0x2
+#define MIXED_TLB0x0
+#define MIXED_CPU0x1
+
+#define PGT_SMALLPAGE_SIZE   0x1000
+#define PGT_LARGEPAGE_SIZE   0x0001
+#define PGT_SECTION_SIZE 0x0010
+#define PGT_SUPERSECTION_SIZE0x0100
+
+#define PGT_L1_DESC_PAGE 0x1
+#define PGT_L1_DESC_SECTION  0x2
+#define PGT_L1_DESC_SUPERSECTION 0x40002
+
+#define PGT_L1_DESC_PAGE_MASK0xfC00
+#define PGT_L1_DESC_SECTION_MASK 0xfff0
+#define PGT_L1_DESC_SUPERSECTION_MASK0xff00
+
+#define PGT_L1_DESC_SMALLPAGE_INDEX_SHIFT12
+#define PGT_L1_DESC_LARGEPAGE_INDEX_SHIFT16
+#define PGT_L1_DESC_SECTION_INDEX_SHIFT  20
+#define PGT_L1_DESC_SUPERSECTION_INDEX_SHIFT 24
+
+#define PGT_L2_DESC_SMALLPAGE   0x02
+#define PGT_L2_DESC_LARGEPAGE   0x01
+
+#define PGT_L2_DESC_SMALLPAGE_MASK  0xf000
+#define PGT_L2_DESC_LARGEPAGE_MASK  0x
+
+/*
+ * The memory for the page tables (256 KB per IPU) is placed just before
+ * the carveout memories for the remote processors. 16 KB of memory is
+ * needed for the L1 page table (4096 entries * 4 bytes per 1 MB section).
+ * Any smaller page (64 KB or 4 KB) entries are supported through L2 page
+ * tables (1 KB per table). The remaining 240 KB can provide support for
+ * 240 L2 page tables. Any remoteproc

[PATCH 05/10] remoteproc: uclass: Add remoteproc resource handling helpers

From: Keerthy 

Add remoteproc resource handling helpers. These functions
are primarily to parse the resource table and to handle
different types of resources. Carveout, devmem, trace &
vring resources are handled.

Signed-off-by: Keerthy 
[Amjad: fix redefinition of "struct resource_table" and compile warnings ]
Signed-off-by: Amjad Ouled-Ameur 
---

 drivers/remoteproc/rproc-uclass.c | 562 ++
 include/remoteproc.h  | 384 +++-
 2 files changed, 945 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/rproc-uclass.c 
b/drivers/remoteproc/rproc-uclass.c
index 64c47c1e7225..3f7096045548 100644
--- a/drivers/remoteproc/rproc-uclass.c
+++ b/drivers/remoteproc/rproc-uclass.c
@@ -8,6 +8,7 @@
 
 #define pr_fmt(fmt) "%s: " fmt, __func__
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -19,9 +20,21 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct resource_table {
+   u32 ver;
+   u32 num;
+   u32 reserved[2];
+   u32 offset[0];
+} __packed;
+
+typedef int (*handle_resource_t) (struct udevice *, void *, int offset, int 
avail);
+
+static struct resource_table *rsc_table;
+
 /**
  * for_each_remoteproc_device() - iterate through the list of rproc devices
  * @fn: check function to call per match, if this function returns fail,
@@ -208,6 +221,86 @@ static int rproc_post_probe(struct udevice *dev)
return 0;
 }
 
+/**
+ * rproc_add_res() - After parsing the resource table add the mappings
+ * @dev:   device we finished probing
+ * @mapping: rproc_mem_entry for the resource
+ *
+ * Return: if the remote proc driver has a add_res routine, invokes it and
+ * hands over the return value. overall, 0 if all went well, else appropriate
+ * error value.
+ */
+static int rproc_add_res(struct udevice *dev, struct rproc_mem_entry *mapping)
+{
+   const struct dm_rproc_ops *ops;
+
+   ops = rproc_get_ops(dev);
+   if (!ops) {
+   debug("%s driver has no ops?\n", dev->name);
+   return -EINVAL;
+   }
+
+   if (ops->add_res)
+   return ops->add_res(dev, mapping);
+
+   return 0;
+}
+
+/**
+ * rproc_alloc_mem() - After parsing the resource table allocat mem
+ * @dev:   device we finished probing
+ * @len: rproc_mem_entry for the resource
+ * @align: alignment for the resource
+ *
+ * Return: if the remote proc driver has a add_res routine, invokes it and
+ * hands over the return value. overall, 0 if all went well, else appropriate
+ * error value.
+ */
+static void *rproc_alloc_mem(struct udevice *dev, unsigned long len,
+unsigned long align)
+{
+   const struct dm_rproc_ops *ops;
+
+   ops = rproc_get_ops(dev);
+   if (!ops) {
+   debug("%s driver has no ops?\n", dev->name);
+   return NULL;
+   }
+
+   if (ops->alloc_mem)
+   return ops->alloc_mem(dev, len, align);
+
+   return NULL;
+}
+
+/**
+ * rproc_config_pagetable() - Configure page table for remote processor
+ * @dev:   device we finished probing
+ * @virt: Virtual address of the resource
+ * @phys: Physical address the resource
+ * @len: length the resource
+ *
+ * Return: if the remote proc driver has a add_res routine, invokes it and
+ * hands over the return value. overall, 0 if all went well, else appropriate
+ * error value.
+ */
+static int rproc_config_pagetable(struct udevice *dev, unsigned int virt,
+ unsigned int phys, unsigned int len)
+{
+   const struct dm_rproc_ops *ops;
+
+   ops = rproc_get_ops(dev);
+   if (!ops) {
+   debug("%s driver has no ops?\n", dev->name);
+   return -EINVAL;
+   }
+
+   if (ops->config_pagetable)
+   return ops->config_pagetable(dev, virt, phys, len);
+
+   return 0;
+}
+
 UCLASS_DRIVER(rproc) = {
.id = UCLASS_REMOTEPROC,
.name = "remoteproc",
@@ -438,3 +531,472 @@ int rproc_is_running(int id)
 {
return _rproc_ops_wrapper(id, RPROC_RUNNING);
 };
+
+/*
+ * Virtio ring descriptors: 16 bytes.  These can chain together via
+ * "next".
+ */
+struct vring_desc {
+   u64 addr;
+   u32 len;
+   u16 flags;
+   u16 next;
+};
+
+/*
+ * u32 is used here for ids for padding reasons.
+ */
+struct vring_used_elem {
+   u32 id;
+   u32 len;
+};
+
+static unsigned int vring_size(unsigned int num, unsigned long align)
+{
+   return ((sizeof(struct vring_desc) * num + sizeof(u16) * (3 + num)
++ align - 1) & ~(align - 1))
+   + sizeof(u16) * 3 + sizeof(struct vring_used_elem) * num;
+}
+
+static int handle_trace(struct udevice *dev, struct fw_rsc_trace *rsc,
+   int offset, int avail)
+{
+   if (sizeof(*rsc) > avail) {
+   debug("trace rsc is truncated\n");
+   return -EINVAL;
+   }
+
+   /*
+* make sure reserved bytes are zeroes
+

[PATCH 09/10] arm: dts: dra7*/am57xx-idk-evm-u-boot: Add ipu early boot DT changes

From: Keerthy 

Add support for ipu early boot.

Signed-off-by: Keerthy 
Signed-off-by: Amjad Ouled-Ameur 
---

 arch/arm/dts/am57xx-idk-common-u-boot.dtsi | 1 +
 arch/arm/dts/dra7-evm-u-boot.dtsi  | 1 +
 arch/arm/dts/dra71-evm-u-boot.dtsi | 1 +
 arch/arm/dts/dra72-evm-revc-u-boot.dtsi| 1 +
 arch/arm/dts/dra76-evm-u-boot.dtsi | 1 +
 5 files changed, 5 insertions(+)

diff --git a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi 
b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
index b07aea0048d5..d0ce469f9189 100644
--- a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
@@ -3,6 +3,7 @@
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  */
 #include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
 
 / {
xtal25mhz: xtal25mhz {
diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi 
b/arch/arm/dts/dra7-evm-u-boot.dtsi
index f06c701dbd1f..5622512b2401 100644
--- a/arch/arm/dts/dra7-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra7-evm-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
 
 _gpio_21{
u-boot,i2c-offset-len = <0>;
diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi 
b/arch/arm/dts/dra71-evm-u-boot.dtsi
index b56d4fc9d896..40443da5c855 100644
--- a/arch/arm/dts/dra71-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra71-evm-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
 
 _gpio_21{
u-boot,i2c-offset-len = <0>;
diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi 
b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
index b56d4fc9d896..40443da5c855 100644
--- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
+++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
 
 _gpio_21{
u-boot,i2c-offset-len = <0>;
diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi 
b/arch/arm/dts/dra76-evm-u-boot.dtsi
index a4dfbe7e601a..5fae6ba91936 100644
--- a/arch/arm/dts/dra76-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra76-evm-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "omap5-u-boot.dtsi"
+#include "dra7-ipu-common-early-boot.dtsi"
 
 _emac0 {
phy-handle = <_0>;
-- 
2.25.1

[PATCH 07/10] dts: dra7-ipu-common-early-boot.dtsi: Add all the ipu early boot related nodes

From: Keerthy 

Add all the ipu early boot related nodes

Signed-off-by: Keerthy 
Signed-off-by: Amjad Ouled-Ameur 
---

 MAINTAINERS  |   1 +
 arch/arm/dts/dra7-ipu-common-early-boot.dtsi | 113 +++
 2 files changed, 114 insertions(+)
 create mode 100644 arch/arm/dts/dra7-ipu-common-early-boot.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 9e93c2785cf9..404ad283ff4a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -499,6 +499,7 @@ F:  arch/arm/mach-keystone/
 F: arch/arm/mach-omap2/
 F: arch/arm/include/asm/arch-omap*/
 F: arch/arm/include/asm/ti-common/
+F: arch/arm/dts/dra7*
 F: board/ti/
 F: drivers/dma/ti*
 F: drivers/firmware/ti_sci.*
diff --git a/arch/arm/dts/dra7-ipu-common-early-boot.dtsi 
b/arch/arm/dts/dra7-ipu-common-early-boot.dtsi
new file mode 100644
index ..ec6040ff93eb
--- /dev/null
+++ b/arch/arm/dts/dra7-ipu-common-early-boot.dtsi
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/ {
+   chosen {
+   firmware-loader = _loader0;
+   };
+
+   fs_loader0: fs_loader@0 {
+   u-boot,dm-pre-reloc;
+   compatible = "u-boot,fs-loader";
+   phandlepart = < 1>;
+   };
+
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   u-boot,dm-spl;
+
+   ipu2_memory_region: ipu2-memory@9580 {
+   compatible = "shared-dma-pool";
+   reg = <0x0 0x9580 0x0 0x380>;
+   reusable;
+   status = "okay";
+   u-boot,dm-spl;
+   };
+
+   ipu1_memory_region: ipu1-memory@9d00 {
+   compatible = "shared-dma-pool";
+   reg = <0x0 0x9d00 0x0 0x200>;
+   reusable;
+   status = "okay";
+   u-boot,dm-spl;
+   };
+
+   ipu1_pgtbl: ipu1-pgtbl@9570 {
+   reg = <0x0 0x9570 0x0 0x4>;
+   no-map;
+   u-boot,dm-spl;
+   };
+
+   ipu2_pgtbl: ipu2-pgtbl@9574 {
+   reg = <0x0 0x9574 0x0 0x4>;
+   no-map;
+   u-boot,dm-spl;
+   };
+   };
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+_ipu1 {
+   u-boot,dm-spl;
+};
+
+_ipu2 {
+   u-boot,dm-spl;
+};
+
+ {
+   status = "okay";
+   memory-region = <_memory_region>;
+   pg-tbl = <_pgtbl>;
+   u-boot,dm-spl;
+};
+
+ {
+   status = "okay";
+   memory-region = <_memory_region>;
+   pg-tbl = <_pgtbl>;
+   u-boot,dm-spl;
+};
+
+_wkup {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+_rst {
+   u-boot,dm-spl;
+};
+
+_rst {
+   u-boot,dm-spl;
+};
-- 
2.25.1

[PATCH 08/10] arm: dts: dra7: Add ipu and related nodes

From: Keerthy 

Add ipu and the associated nodes.

Signed-off-by: Keerthy 
Signed-off-by: Amjad Ouled-Ameur 
---

 arch/arm/dts/dra7.dtsi | 45 +-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index fd1aea0b1b16..e2e958b36626 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -41,6 +41,8 @@
d_can0 = 
d_can1 = 
spi0 = 
+   remoteproc0 = 
+   remoteproc1 = 
};
 
timer {
@@ -263,9 +265,12 @@
};
 
prm: prm@6000 {
-   compatible = "ti,dra7-prm";
+   compatible = "ti,dra7-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = ;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x6000 0x3000>;
 
prm_clocks: clocks {
#address-cells = <1>;
@@ -274,6 +279,20 @@
 
prm_clockdomains: clockdomains {
};
+
+   ipu1_rst: ipu1_rst@510 {
+   compatible = "ti,dra7-reset";
+   reg = <0x510 0x8>;
+   ti,nresets = <3>;
+   #reset-cells = <1>;
+   };
+
+   ipu2_rst: ipu2_rst@910 {
+   compatible = "ti,dra7-reset";
+   reg = <0x910 0x8>;
+   ti,nresets = <3>;
+   #reset-cells = <1>;
+   };
};
 
scm_wkup: scm_conf@c000 {
@@ -2032,6 +2051,30 @@
clocks = <_iclk_div>;
clock-names = "fck";
};
+
+   ipu1: ipu@5882 {
+   compatible = "ti,dra7-ipu";
+   reg = <0x5882 0x1>;
+   reg-names = "l2ram";
+   ti,hwmods = "ipu1";
+   resets = <_rst 0>, <_rst 1>, <_rst 2>;
+   iommus = <_ipu1>;
+   ti,rproc-standby-info = <0x4a005520>;
+   timers = <>;
+   watchdog-timers = <>, <>;
+   };
+
+   ipu2: ipu@5502 {
+   compatible = "ti,dra7-ipu";
+   reg = <0x5502 0x1>;
+   reg-names = "l2ram";
+   ti,hwmods = "ipu2";
+   resets = <_rst 0>, <_rst 1>, <_rst 2>;
+   iommus = <_ipu2>;
+   ti,rproc-standby-info = <0x4a008920>;
+   timers = <>;
+   watchdog-timers = <>, <>;
+   };
};
 
thermal_zones: thermal-zones {
-- 
2.25.1

[PATCH 04/10] linux: bitmap.h: Add find_next_zero_area function

From: Keerthy 

Add find_next_zero_area to fetch the next zero area in the map.

Signed-off-by: Keerthy 
Signed-off-by: Amjad Ouled-Ameur 
---

 include/linux/bitmap.h | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index dae4225be549..0a8503af9f14 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -159,6 +159,32 @@ static inline unsigned long find_first_bit(const unsigned 
long *addr, unsigned l
 (bit) < (size);\
 (bit) = find_next_bit((addr), (size), (bit) + 1))
 
+static inline unsigned long
+bitmap_find_next_zero_area(unsigned long *map,
+  unsigned long size,
+  unsigned long start,
+  unsigned int nr, unsigned long align_mask)
+{
+   unsigned long index, end, i;
+again:
+   index = find_next_zero_bit(map, size, start);
+
+   /*
+* Align allocation
+*/
+   index = (index + align_mask) & ~align_mask;
+
+   end = index + nr;
+   if (end > size)
+   return end;
+   i = find_next_bit(map, end, index);
+   if (i < end) {
+   start = i + 1;
+   goto again;
+   }
+   return index;
+}
+
 static inline void bitmap_fill(unsigned long *dst, unsigned int nbits)
 {
if (small_const_nbits(nbits)) {
-- 
2.25.1

[PATCH 03/10] drivers: misc: Makefile: Enable fs_loader compilation at SPL Level

From: Keerthy 

Enable fs_loader compilation at SPL Level.

Signed-off-by: Keerthy 
[Amjad: fix compilation failures for J721e platform]
Signed-off-by: Amjad Ouled-Ameur 
---

 arch/arm/mach-k3/common.c | 10 +++---
 configs/j721e_evm_r5_defconfig|  1 +
 configs/j721e_hs_evm_r5_defconfig |  1 +
 drivers/misc/Kconfig  |  9 +
 drivers/misc/Makefile |  2 +-
 5 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 2666cd2d7b17..dddad8e3b056 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -156,13 +156,15 @@ void init_env(void)
 #endif
 }
 
-#ifdef CONFIG_FS_LOADER
 int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
 {
struct udevice *fsdev;
char *name = NULL;
int size = 0;
 
+   if (!IS_ENABLED(CONFIG_FS_LOADER))
+   return 0;
+
*loadaddr = 0;
 #ifdef CONFIG_SPL_ENV_SUPPORT
switch (spl_boot_device()) {
@@ -186,12 +188,6 @@ int load_firmware(char *name_fw, char *name_loadaddr, u32 
*loadaddr)
 
return size;
 }
-#else
-int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
-{
-   return 0;
-}
-#endif
 
 __weak void release_resources_for_core_shutdown(void)
 {
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index b5fd3bf23734..edc003f46b90 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -88,6 +88,7 @@ CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
 CONFIG_ESM_K3=y
 CONFIG_K3_AVS0=y
 CONFIG_ESM_PMIC=y
diff --git a/configs/j721e_hs_evm_r5_defconfig 
b/configs/j721e_hs_evm_r5_defconfig
index 3a8e0b1cd15b..6c3675c1726c 100644
--- a/configs/j721e_hs_evm_r5_defconfig
+++ b/configs/j721e_hs_evm_r5_defconfig
@@ -82,6 +82,7 @@ CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
 CONFIG_K3_AVS0=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 997b71322110..e6a1dc677d6e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -468,6 +468,15 @@ config FS_LOADER
  The consumer driver would then use this loader to program whatever,
  ie. the FPGA device.
 
+config SPL_FS_LOADER
+   bool "Enable loader driver for file system"
+   help
+ This is file system generic loader which can be used to load
+ the file image from the storage into target such as memory.
+
+ The consumer driver would then use this loader to program whatever,
+ ie. the FPGA device.
+
 config GDSYS_SOC
bool "Enable gdsys SOC driver"
depends on MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index b64cd2a4de91..c7c95ee76767 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -37,7 +37,7 @@ obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
 obj-$(CONFIG_FSL_IIM) += fsl_iim.o
 obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
 obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
-obj-$(CONFIG_FS_LOADER) += fs_loader.o
+obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o
 obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
 obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
 obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
-- 
2.25.1

[PATCH 02/10] arm: mach-omap2: load/start remoteproc IPU1/IPU2

From: Keerthy 

First check the presence of the ipu firmware in the boot partition.
If present enable the ipu and the related clocks & then move
on to load the firmware and eventually start remoteproc IPU1/IPU2.

do_enable_clocks by default puts the clock domains into auto
which does not work well with reset. Hence adding do_enable_ipu_clocks
function.

Signed-off-by: Keerthy 
[Amjad: fix IPU1_LOAD_ADDR and compile warnings]
Signed-off-by: Amjad Ouled-Ameur 
---

 arch/arm/include/asm/arch-omap5/clock.h |  3 +
 arch/arm/include/asm/omap_common.h  | 10 +++
 arch/arm/mach-omap2/boot-common.c   | 95 +
 arch/arm/mach-omap2/clocks-common.c | 33 +
 arch/arm/mach-omap2/omap5/hw_data.c | 92 ++--
 arch/arm/mach-omap2/omap5/prcm-regs.c   |  9 ++-
 6 files changed, 235 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/clock.h 
b/arch/arm/include/asm/arch-omap5/clock.h
index 87eb3f335ab0..a00626e357c9 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -135,6 +135,9 @@
 #define HSMMC_CLKCTRL_CLKSEL_MASK  (1 << 24)
 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK  (3 << 25)
 
+/* CM_IPU1_IPU1_CLKCTRL CLKSEL MASK */
+#define IPU1_CLKCTRL_CLKSEL_MASK   BIT(24)
+
 /* CM_L3INIT_SATA_CLKCTRL */
 #define SATA_CLKCTRL_OPTFCLKEN_MASK(1 << 8)
 
diff --git a/arch/arm/include/asm/omap_common.h 
b/arch/arm/include/asm/omap_common.h
index de8fc99d0478..264a2e717a70 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -362,6 +362,10 @@ struct prcm_regs {
/* IPU */
u32 cm_ipu_clkstctrl;
u32 cm_ipu_i2c5_clkctrl;
+   u32 cm_ipu1_clkstctrl;
+   u32 cm_ipu1_ipu1_clkctrl;
+   u32 cm_ipu2_clkstctrl;
+   u32 cm_ipu2_ipu2_clkctrl;
 
/*l3main1 edma*/
u32 cm_l3main1_tptc1_clkctrl;
@@ -632,6 +636,12 @@ void do_disable_clocks(u32 const *clk_domains,
   u8 wait_for_disable);
 #endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
 
+void do_enable_ipu_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_hw_auto,
+ u32 const *clk_modules_explicit_en,
+ u8 wait_for_enable);
+void enable_ipu1_clocks(void);
+void enable_ipu2_clocks(void);
 void setup_post_dividers(u32 const base,
const struct dpll_params *params);
 u32 omap_ddr_clk(void);
diff --git a/arch/arm/mach-omap2/boot-common.c 
b/arch/arm/mach-omap2/boot-common.c
index 7cdf7f158981..2bf4aff74c3a 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -10,6 +10,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -19,9 +21,14 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define IPU1_LOAD_ADDR (0xa17ff000)
+#define MAX_REMOTECORE_BIN_SIZE (8 * 0x10)
+#define IPU2_LOAD_ADDR (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
+
 __weak u32 omap_sys_boot_device(void)
 {
return BOOT_DEVICE_NONE;
@@ -194,6 +201,91 @@ u32 spl_mmc_boot_mode(const u32 boot_device)
return gd->arch.omap_boot_mode;
 }
 
+int load_firmware(char *name_fw, u32 *loadaddr)
+{
+   struct udevice *fsdev;
+   int size = 0;
+
+   if (!IS_ENABLED(CONFIG_FS_LOADER))
+   return 0;
+
+   if (!*loadaddr)
+   return 0;
+
+   if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, )) {
+   size = request_firmware_into_buf(fsdev, name_fw,
+(void *)*loadaddr, 0, 0);
+   }
+
+   return size;
+}
+
+void spl_boot_ipu(void)
+{
+   int ret, size;
+   u32 loadaddr = IPU1_LOAD_ADDR;
+
+   if (!IS_ENABLED(CONFIG_SPL_BUILD) ||
+   !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+   return;
+
+   size = load_firmware("dra7-ipu1-fw.xem4", );
+   if (size <= 0) {
+   pr_err("Firmware loading failed\n");
+   goto skip_ipu1;
+   }
+
+   enable_ipu1_clocks();
+   ret = rproc_dev_init(0);
+   if (ret) {
+   debug("%s: IPU1 failed to initialize on rproc (%d)\n",
+ __func__, ret);
+   goto skip_ipu1;
+   }
+
+   ret = rproc_load(0, IPU1_LOAD_ADDR, 0x200);
+   if (ret) {
+   debug("%s: IPU1 failed to load on rproc (%d)\n", __func__,
+ ret);
+   goto skip_ipu1;
+   }
+
+   debug("Starting IPU1...\n");
+
+   ret = rproc_start(0);
+   if (ret)
+   debug("%s: IPU1 failed to start (%d)\n", __func__, ret);
+
+skip_ipu1:
+   loadaddr = IPU2_LOAD_ADDR;
+   size = load_firmware("dra7-ipu2-fw.xem4", );
+   if (size <= 0) {
+   pr_err("Firmware loading failed for ipu2\n");
+   return;
+   }
+
+

[PATCH 01/10] reset: dra7: Add a reset driver

From: Keerthy 

Add a reset driver to bring IPs out of reset.

Signed-off-by: Keerthy 
[Amjad: reset_ops structure member "free" has been renamed to "rfree",
use the latter instead]
Signed-off-by: Amjad Ouled-Ameur 
---

 MAINTAINERS|  1 +
 drivers/reset/Kconfig  |  6 +++
 drivers/reset/Makefile |  1 +
 drivers/reset/reset-dra7.c | 97 ++
 4 files changed, 105 insertions(+)
 create mode 100644 drivers/reset/reset-dra7.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 67c96a604546..ce6e7ef08252 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -516,6 +516,7 @@ F:  drivers/remoteproc/k3_system_controller.c
 F: drivers/remoteproc/pruc_rpoc.c
 F: drivers/remoteproc/ti*
 F: drivers/reset/reset-ti-sci.c
+F: drivers/reset/reset-dra7.c
 F: drivers/rtc/davinci.c
 F: drivers/serial/serial_omap.c
 F: drivers/soc/ti/
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index d73daf5e3189..b57714111b5a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -206,4 +206,10 @@ config RESET_ZYNQMP
  passing request via Xilinx firmware interface to TF-A and PMU
  firmware.
 
+config RESET_DRA7
+   bool "Support for TI's DRA7 Reset driver"
+   depends on DM_RESET
+   help
+ Support for TI DRA7-RESET subsystem. Basic Assert/Deassert
+ is supported.
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index d69486bdeb9e..97e3a782c0d8 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -30,3 +30,4 @@ obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
 obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
+obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c
new file mode 100644
index ..585f8323c52e
--- /dev/null
+++ b/drivers/reset/reset-dra7.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Texas Instruments DRA7 reset driver
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Keerthy 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct dra7_reset_priv {
+   u32 rstctrl;
+   u32 rstst;
+   u8 nreset;
+};
+
+static int dra7_reset_request(struct reset_ctl *reset_ctl)
+{
+   return 0;
+}
+
+static int dra7_reset_free(struct reset_ctl *reset_ctl)
+{
+   return 0;
+}
+
+static inline void dra7_reset_rmw(u32 addr, u32 value, u32 mask)
+{
+   writel(((readl(addr) & (~mask)) | (value & mask)), addr);
+}
+
+static int dra7_reset_deassert(struct reset_ctl *reset_ctl)
+{
+   struct dra7_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+   int mask = 1 << reset_ctl->id;
+
+   if (reset_ctl->id < 0 || reset_ctl->id >= priv->nreset)
+   return -EINVAL;
+
+   dra7_reset_rmw(priv->rstctrl, 0x0, mask);
+
+   while ((readl(priv->rstst) & mask) != mask)
+   ;
+
+   return 0;
+}
+
+static int dra7_reset_assert(struct reset_ctl *reset_ctl)
+{
+   struct dra7_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+   int mask = 1 << reset_ctl->id;
+
+   if (reset_ctl->id < 0 || reset_ctl->id >= priv->nreset)
+   return -EINVAL;
+
+   dra7_reset_rmw(priv->rstctrl, mask, 0x0);
+
+   return 0;
+}
+
+struct reset_ops dra7_reset_ops = {
+   .request = dra7_reset_request,
+   .rfree = dra7_reset_free,
+   .rst_assert = dra7_reset_assert,
+   .rst_deassert = dra7_reset_deassert,
+};
+
+static const struct udevice_id dra7_reset_ids[] = {
+   { .compatible = "ti,dra7-reset" },
+   { }
+};
+
+static int dra7_reset_probe(struct udevice *dev)
+{
+   struct dra7_reset_priv *priv = dev_get_priv(dev);
+
+   priv->rstctrl = dev_read_addr(dev);
+   priv->rstst = priv->rstctrl + 0x4;
+   priv->nreset = dev_read_u32_default(dev, "ti,nresets", 1);
+
+   dev_info(dev, "dra7-reset successfully probed %s\n", dev->name);
+
+   return 0;
+}
+
+U_BOOT_DRIVER(dra7_reset) = {
+   .name = "dra7_reset",
+   .id = UCLASS_RESET,
+   .of_match = dra7_reset_ids,
+   .probe = dra7_reset_probe,
+   .ops = _reset_ops,
+   .priv_auto = sizeof(struct dra7_reset_priv),
+};
-- 
2.25.1

[PATCH 00/10] dra7: bring up and support IPU load/start

This patchset enables support for loading and starting IPU firmware,
the following have been implemented:
- Enable fs_loader compilation at SPL Level, that is necessary in order
  to load IPU firmware from /boot partition.
- Define necessary related IPU dts nodes.
- Add necessary drivers and helpers to bring up, load and start IPU
  firmware.

The underlying patches are interdependent, therefore should be applied
in the order they are numbered in this patchset.

Tests:
- Please find SPL, u-boot and kernel console logs in here [0]
- At SPL stage, debug logs have been enabled to make sure that
IPU1 and IPU2 are loaded and started properly. In fact, these two log
messages are only displayed when the firmware has been loaded, and if no
errors appear afterwards, it means that firmware started successfully as
well:
  - Starting IPU1...
  - Starting IPU2...

At U-boot stage, "rproc" command-line tool was used for the testing. In
the logs [0], "rproc list" was run before and after IPU1 and IPU2 are
initialized by "rproc init". The before run gave an empty list, while
the after run listed successfully the two IPUs with their correct
addresses:
  - 0 - Name:'ipu@5882' type:'internal memory mapped'
  - 1 - Name:'ipu@5502' type:'internal memory mapped'

"rproc start" and "rproc stop" were also used for both IPU1 and IPU2,
both were successful as no error logs were displayed.

[0]: https://pastebin.com/puCZ5GSm

These U-boot/SPL flags have been purposely enabled during tests to ensure
IPU load/start work properly:
- CONFIG_DM_RESET=y
- CONFIG_RESET_DRA7=y
- CONFIG_SPL_DM_RESET=y
- CONFIG_FS_LOADER=y
- CONFIG_SPL_FS_LOADER=y
- CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
- CONFIG_REMOTEPROC_TI_IPU=y
- CONFIG_SPL_REMOTEPROC=y
- CONFIG_CMD_REMOTEPROC=y



Keerthy (10):
  reset: dra7: Add a reset driver
  arm: mach-omap2: load/start remoteproc IPU1/IPU2
  drivers: misc: Makefile: Enable fs_loader compilation at SPL Level
  linux: bitmap.h: Add find_next_zero_area function
  remoteproc: uclass: Add remoteproc resource handling helpers
  remoteproc: ipu: Add driver to bring up ipu
  dts: dra7-ipu-common-early-boot.dtsi: Add all the ipu early boot
related nodes
  arm: dts: dra7: Add ipu and related nodes
  arm: dts: dra7*/am57xx-idk-evm-u-boot: Add ipu early boot DT changes
  dts: am57xx*: Add ipu early boot DT changes

 MAINTAINERS   |   4 +
 .../dts/am57xx-beagle-x15-revb1-u-boot.dtsi   |   7 +
 .../dts/am57xx-beagle-x15-revc-u-boot.dtsi|   7 +
 arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi|   7 +
 arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi  |   7 +
 arch/arm/dts/am57xx-idk-common-u-boot.dtsi|   1 +
 arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi |   7 +
 arch/arm/dts/dra7-evm-u-boot.dtsi |   1 +
 arch/arm/dts/dra7-ipu-common-early-boot.dtsi  | 113 +++
 arch/arm/dts/dra7.dtsi|  45 +-
 arch/arm/dts/dra71-evm-u-boot.dtsi|   1 +
 arch/arm/dts/dra72-evm-revc-u-boot.dtsi   |   1 +
 arch/arm/dts/dra76-evm-u-boot.dtsi|   1 +
 arch/arm/include/asm/arch-omap5/clock.h   |   3 +
 arch/arm/include/asm/omap_common.h|  10 +
 arch/arm/mach-k3/common.c |  10 +-
 arch/arm/mach-omap2/boot-common.c |  95 +++
 arch/arm/mach-omap2/clocks-common.c   |  33 +
 arch/arm/mach-omap2/omap5/hw_data.c   |  92 ++-
 arch/arm/mach-omap2/omap5/prcm-regs.c |   9 +-
 configs/j721e_evm_r5_defconfig|   1 +
 configs/j721e_hs_evm_r5_defconfig |   1 +
 drivers/misc/Kconfig  |   9 +
 drivers/misc/Makefile |   2 +-
 drivers/remoteproc/Kconfig|  10 +
 drivers/remoteproc/Makefile   |   1 +
 drivers/remoteproc/ipu_rproc.c| 759 ++
 drivers/remoteproc/rproc-uclass.c | 562 +
 drivers/reset/Kconfig |   6 +
 drivers/reset/Makefile|   1 +
 drivers/reset/reset-dra7.c|  97 +++
 include/linux/bitmap.h|  26 +
 include/remoteproc.h  | 384 -
 33 files changed, 2296 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
 create mode 100644 arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
 create mode 100644 arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
 create mode 100644 arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
 create mode 100644 arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi
 create mode 100644 arch/arm/dts/dra7-ipu-common-early-boot.dtsi
 create mode 100644 drivers/remoteproc/ipu_rproc.c
 create mode 100644 drivers/reset/reset-dra7.c

-- 
2.25.1

Re: [PATCH] arm: a37xx: pci: Increase PCIe IO size from 64 KiB to 1 MiB

2021-09-23 Thread Stefan Roese


On 23.09.21 11:07, Pali Rohár wrote:

Commit 079b35a26111 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB
to 127 MiB") increased size of PCIe MEM to 127 MiB, which is the maximal
possible size for allocated 128 MiB PCIe window. PCIe IO size in that
commit was unchanged.

Armada 3720 PCIe controller supports 32-bit IO space mapping so it is
possible to assign more than 64 KiB if address space for IO.

Currently controller has assigned 127 MiB + 64 KiB memory and therefore
there is 960 KiB of unused memory. So assign it to IO space by increasing
IO window from 64 KiB to 1 MiB.

Signed-off-by: Pali Rohár 
Fixes: 079b35a26111 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 
MiB")


Reviewed-by: Stefan Roese 

Thanks,
Stefan


---
  arch/arm/dts/armada-37xx.dtsi | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 2615b8c748c1..fec34609cf82 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -335,14 +335,14 @@
/*
 * The 128 MiB address range [0xe800-0xf000] is
 * dedicated for PCIe and can be assigned to 8 windows
-* with size a power of two. Use one 64 KiB window for
+* with size a power of two. Use one 1 MiB window for
 * IO at the end and the remaining seven windows
 * (totaling 127 MiB) for MEM.
 */
ranges = <0x8200 0 0xe800
 0 0xe800 0 0x7f0 /* Port 0 MEM */
-0x8100 0 0xefff
-0 0xefff 0 0x1>; /* Port 0 IO*/
+0x8100 0 0xeff0
+0 0xeff0 0 0x10>; /* Port 0 IO*/
};
};
  };




Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de

Of capsules, signatures and device trees, TGTBTU

2021-09-23 Thread François Ozog

Hi,

Following the EFI capsule revert, here* is a contribution to
understand the context in which we designed the patch set. (everyone
is a commenter, please be mindful).

The presentation explores booting, with more details for the Arm
context, pre and post U-Boot. On Arm, pre-U-Boot is shaped after
Firmware Framework-A and other interfaces. There is a similar approach
in RISC-V with OpenSBI.

There is nothing to agree on: many elements of the presentation are
specifications for the Arm ecosystem. The purpose is to reach common
understanding of those for rest of the journey.

Careful reading is required because as we all know very well the
topic, we may skip over stuff and miss key elements that may have
changed since you last checked. So I'll attract your attention on:

Slide 9: there can be multiple device trees in a Trusted Firmware FIP
(nothing to agree on...)
Slide 11: roles and responsibilities of firmware go far beyond booting
and OTA. CoreBoot and SPL will have to take those into account in the
future.
Slide 17: there is a new boot flow based on "give-me-my-initrd" UEFI protocol
Slide 24: when the firmware is stored on Secure Storage which is a
common case for products, U-Boot/Linux have absolutely no means to
perform the update (see notes for details).
Slide 28: there are plenty of keys needed, the U-Boot and U-Boot
updater can be different; as well as all firmware components.

I acknowledge that the presentation is hard to read without enough
speaker notes or myself talking to it. Let's say that I prefer to keep
the ball rolling before we can actually program a call: could you send
me in private message your preferred day of the week and best time
(with TZ) for such a thing?

Cordially,

--
François-Frédéric Ozog

*)
https://docs.google.com/presentation/d/1AHTf9xMNqPXbiDLkBpoKt45UTjV8s34JdtmrxYlfp9M/edit?usp=sharing

[PATCH 1/1] mx7ulp: Update wdog disable sequence

2021-09-23 Thread Oleksandr Suvorov

From: Ye Li 

Update the mx7ulp wdog disable sequence to avoid potential reset
issue in unlock or refresh sequence. Both sequence need two words
write to wdog CNT register in 16 bus clocks window, if miss the
window, the write will cause violation in wdog and reset the chip.

Current u-boot code is using writel() function which has a DMB
barrier to order the memory access. The DMB between two words write
may introduce some delay in certain circumstance, causing the wdog
reset due to 16 bus clock window requirement.

Also, WDOG1 might have been enabled already depending on FUSE hence
we need to be as close as possible to its reconfiguration timing
requirement of 128 bus clock limit.

This patch replaces writel() function by __raw_writel() to avoid such
issue, and improve to check if watchdog is already disabled or
unlocked.

Signed-off-by: Ye Li 
Co-developed-by: Jorge Ramirez-Ortiz 
Signed-off-by: Jorge Ramirez-Ortiz 
Co-developed-by: Ricardo Salveti 
Signed-off-by: Ricardo Salveti 
Signed-off-by: Oleksandr Suvorov 
---

 arch/arm/mach-imx/mx7ulp/soc.c | 31 ---
 1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 320f24dd29..7f097d6850 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -93,14 +93,31 @@ int board_postclk_init(void)
 
 static void disable_wdog(u32 wdog_base)
 {
-   writel(UNLOCK_WORD0, (wdog_base + 0x04));
-   writel(UNLOCK_WORD1, (wdog_base + 0x04));
-   writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
-   writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
-   writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
+   u32 val_cs = readl(wdog_base + 0x00);
 
-   writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
-   writel(REFRESH_WORD1, (wdog_base + 0x04));
+   if (!(val_cs & 0x80))
+   return;
+
+   dmb();
+   __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
+   __raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
+   dmb();
+
+   if (!(val_cs & 800)) {
+   dmb();
+   __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
+   __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
+   dmb();
+
+   while (!(readl(wdog_base + 0x00) & 0x800));
+   }
+   dmb();
+   __raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */
+   __raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 
*/
+   __raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */
+   dmb();
+
+   while (!(readl(wdog_base + 0x00) & 0x400));
 }
 
 void init_wdog(void)
-- 
2.31.1

[PATCH 0/1] mx7ulp: Update wdog disable sequence

2021-09-23 Thread Oleksandr Suvorov



This patch was originally picked up from the NXP repo and improved
in Foundries.IO. It is needed to proper work of watchdog on iMX7ULP.



Ye Li (1):
  mx7ulp: Update wdog disable sequence

 arch/arm/mach-imx/mx7ulp/soc.c | 31 ---
 1 file changed, 24 insertions(+), 7 deletions(-)

-- 
2.31.1

[RFC v2 1/2] mtd: Add support for Linux slc-mode for MLC NAND

2021-09-23 Thread Chris Morgan

From: Chris Morgan 

Add support for setting the slc-mode parameter for a given MLC NAND
device. This allows a given device to write only to the first set
of paried pages to help reduce data corruption and increase reliability
of the NAND.

I haven't tested these patches extensively yet, but thus far I have
been able to boot from a ubifs partition from a vmlinuz, initramfs,
devicetree, and boot.scr from said partition.

As I am unfamiliar with NAND and have limited experience with the MTD
subsystems, please let me know what else I can do to improve the driver.

Thank you.

Signed-off-by: Chris Morgan 
---
 drivers/mtd/mtdcore.c| 542 ---
 drivers/mtd/mtdcore.h|   1 -
 drivers/mtd/mtdpart.c|   7 +
 drivers/mtd/nand/raw/nand_base.c |  50 +++
 include/linux/mtd/mtd.h  | 190 ++-
 include/linux/mtd/partitions.h   |  24 +-
 include/mtd/mtd-abi.h|   1 +
 7 files changed, 692 insertions(+), 123 deletions(-)

diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 582129d0df..f7bc518c96 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -397,6 +397,114 @@ static struct device_type mtd_devtype = {
 };
 #endif
 
+/**
+ * mtd_wunit_to_pairing_info - get pairing information of a wunit
+ * @mtd: pointer to new MTD device info structure
+ * @wunit: write unit we are interested in
+ * @info: returned pairing information
+ *
+ * Retrieve pairing information associated to the wunit.
+ * This is mainly useful when dealing with MLC/TLC NANDs where pages can be
+ * paired together, and where programming a page may influence the page it is
+ * paired with.
+ * The notion of page is replaced by the term wunit (write-unit) to stay
+ * consistent with the ->writesize field.
+ *
+ * The @wunit argument can be extracted from an absolute offset using
+ * mtd_offset_to_wunit(). @info is filled with the pairing information attached
+ * to @wunit.
+ *
+ * From the pairing info the MTD user can find all the wunits paired with
+ * @wunit using the following loop:
+ *
+ * for (i = 0; i < mtd_pairing_groups(mtd); i++) {
+ * info.pair = i;
+ * mtd_pairing_info_to_wunit(mtd, );
+ * ...
+ * }
+ */
+int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit,
+ struct mtd_pairing_info *info)
+{
+   struct mtd_info *master = mtd_get_master(mtd);
+   int npairs = mtd_wunit_per_eb(master) / mtd_pairing_groups(master);
+
+   if (wunit < 0 || wunit >= npairs)
+   return -EINVAL;
+
+   if (master->pairing && master->pairing->get_info)
+   return master->pairing->get_info(master, wunit, info);
+
+   info->group = 0;
+   info->pair = wunit;
+
+   return 0;
+}
+EXPORT_SYMBOL_GPL(mtd_wunit_to_pairing_info);
+
+/**
+ * mtd_pairing_info_to_wunit - get wunit from pairing information
+ * @mtd: pointer to new MTD device info structure
+ * @info: pairing information struct
+ *
+ * Returns a positive number representing the wunit associated to the info
+ * struct, or a negative error code.
+ *
+ * This is the reverse of mtd_wunit_to_pairing_info(), and can help one to
+ * iterate over all wunits of a given pair (see mtd_wunit_to_pairing_info()
+ * doc).
+ *
+ * It can also be used to only program the first page of each pair (i.e.
+ * page attached to group 0), which allows one to use an MLC NAND in
+ * software-emulated SLC mode:
+ *
+ * info.group = 0;
+ * npairs = mtd_wunit_per_eb(mtd) / mtd_pairing_groups(mtd);
+ * for (info.pair = 0; info.pair < npairs; info.pair++) {
+ * wunit = mtd_pairing_info_to_wunit(mtd, );
+ * mtd_write(mtd, mtd_wunit_to_offset(mtd, blkoffs, wunit),
+ *   mtd->writesize, , buf + (i * mtd->writesize));
+ * }
+ */
+int mtd_pairing_info_to_wunit(struct mtd_info *mtd,
+ const struct mtd_pairing_info *info)
+{
+   struct mtd_info *master = mtd_get_master(mtd);
+   int ngroups = mtd_pairing_groups(master);
+   int npairs = mtd_wunit_per_eb(master) / ngroups;
+
+   if (!info || info->pair < 0 || info->pair >= npairs ||
+   info->group < 0 || info->group >= ngroups)
+   return -EINVAL;
+
+   if (master->pairing && master->pairing->get_wunit)
+   return mtd->pairing->get_wunit(master, info);
+
+   return info->pair;
+}
+EXPORT_SYMBOL_GPL(mtd_pairing_info_to_wunit);
+
+/**
+ * mtd_pairing_groups - get the number of pairing groups
+ * @mtd: pointer to new MTD device info structure
+ *
+ * Returns the number of pairing groups.
+ *
+ * This number is usually equal to the number of bits exposed by a single
+ * cell, and can be used in conjunction with mtd_pairing_info_to_wunit()
+ * to iterate over all pages of a given pair.
+ */
+int mtd_pairing_groups(struct mtd_info *mtd)
+{
+   struct mtd_info *master = mtd_get_master(mtd);
+
+   if (!master->pairing || !master->pairing->ngroups)
+   return 1;
+
+   return

[RFC v2 2/2] mtd: Add pairing info for Toshiba TC58TEG5DCLTA00 NAND

2021-09-23 Thread Chris Morgan

From: Chris Morgan 

Add pairing info for the Toshiba TC58TEG5DCLTA00 NAND so that we may
utilize slc-mode emulation for enhanced reliability and compatibility
with upstream Linux.

Signed-off-by: Chris Morgan 
---
 drivers/mtd/nand/raw/nand_base.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 845bf57c53..ac5b17af70 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4549,6 +4549,15 @@ ident_done:
break;
}
 
+   /* Special handling for TC58TEG5DCLTA00 to match upstream Linux */
+   if (id_data[0] == NAND_MFR_TOSHIBA && id_data[1] == 0xd7
+   && id_data[2] == 0x84 && id_data[3] == 0x93
+   && id_data[4] == 0x72 && id_data[5] == 0x51
+   && id_data[6] == 0x08 && id_data[7] == 0x04) {
+   chip->options |= NAND_NEED_SCRAMBLING;
+   mtd_set_pairing_scheme(mtd, _pairing_scheme);
+   }
+
if (chip->options & NAND_BUSWIDTH_AUTO) {
WARN_ON(chip->options & NAND_BUSWIDTH_16);
chip->options |= busw;
-- 
2.30.2

[RFC v2 0/2] mtd: Support slc-mode for Toshiba TC58TEG5DCLTA00

2021-09-23 Thread Chris Morgan

From: Chris Morgan 

Add support for slc-mode implemented in Linux for the Toshiba
TC58TEG5DCLTA00 NAND flash found on the NTC CHIP. This requires the
addition of a paired-pages scheme, a new parameter for MTD partitions
of slc-mode, and setting the correct paired-pages scheme for the
TC58TEG5DCLTA00 flash chip. I will likely need some help making sure
this is consistent with the quality expected of upstream.

Changes since V1:

 - Updated mtd_read and mtd_write to match upstream Linux.
 - Additional mtd_get_master to match upstream Linux.
 - Removed notes about ubifs not working, because it is now.

Signed-off-by: Chris Morgan 

Chris Morgan (3):
  mtd: Add support for Linux slc-mode for MLC NAND
  mtd: Add pairing info for Toshiba TC58TEG5DCLTA00 NAND
  NOT FOR UPSTREAM

 arch/arm/dts/sun5i-r8-chip.dts   |  39 +++
 drivers/mtd/mtdcore.c| 542 ---
 drivers/mtd/mtdcore.h|   1 -
 drivers/mtd/mtdpart.c|   7 +
 drivers/mtd/nand/raw/nand_base.c |  59 
 include/configs/sunxi-common.h   |   2 +
 include/linux/mtd/mtd.h  | 190 ++-
 include/linux/mtd/partitions.h   |  24 +-
 include/mtd/mtd-abi.h|   1 +
 9 files changed, 742 insertions(+), 123 deletions(-)

-- 
2.30.2

uboot oob size

2021-09-23 Thread Ivan Riabtsov

addition to the question:

I have a system on an mx28evk chip, I have two types of nand memory,
one with 64 bytes, the other 128 bytes, I am building a buildroot, I
need a universal firmware for both types of memory, I found how to
patch uboot so that it works with both memory types, but buildroot has
an option for u-boot.nand NAND OOB size, which is not recognized by
the bootloader during boot, but is hardcoded in u-boot.nand,

accordingly, if I set u-boot.nand oob size to 128 bytes, then the
system with 64 memory will not boot and vice versa, tell me, is it
possible to somehow create a universal firmware for both types of nand
memory?

the code in uboot/drivers/mtd/nand/nand_base.c recognizes the OOB size
correctly, but mxsboot cant set up OOB size universally, only one OOB
size can be passed to the mxsboot, respectively, the question is how
you can set the environment variable to uboot from a file
uboot/drivers/mtd/nand/nand_base.c?

Re: Subject: [PATCH 1/6 v3] serial: qcom: add support for GENI serial driver

Hey,

For the series, can you please repost all of the patches, and check your
git send-email settings?  Looking at things over in patchwork, the
spacing is mangled (so they won't apply cleanly) and I can't retrieve
the patches from patchwork either, as they show up as empty.  Thanks!

-- 
Tom


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Re: [PATCH 1/2] mmc: add helper to query max enhanced part size

2021-09-23 Thread Matthias Schiffer

On Thu, 2021-09-23 at 20:58 +0900, Jaehoon Chung wrote:
> Hi,
> 
> On 9/22/21 9:30 PM, Matthias Schiffer wrote:
> > From: Markus Niebel 
> > 
> > This helper will be used later on in an extension of the mmc
> > command.
> > 
> > Signed-off-by: Markus Niebel 
> > Signed-off-by: Matthias Schiffer 
> > ---
> >  drivers/mmc/mmc.c | 38 ++
> >  include/mmc.h |  1 +
> >  2 files changed, 39 insertions(+)
> > 
> > diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> > index d3babbfeb1c..c1b1ef7eb0b 100644
> > --- a/drivers/mmc/mmc.c
> > +++ b/drivers/mmc/mmc.c
> > @@ -1039,6 +1039,44 @@ int mmc_switch_part(struct mmc *mmc, unsigned int 
> > part_num)
> >  }
> >  
> >  #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
> > +int mmc_max_enhanced_size_sectors(struct mmc *mmc, u64 *size)
> > +{
> > +   u64 sz;
> > +   int err;
> > +
> > +   ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
> > +
> > +   if (IS_SD(mmc) || mmc->version < MMC_VERSION_4_41) {
> > +   pr_err("eMMC >= 4.4 required for enhanced user data area\n");
> 
> Error log is considering about only eMMC. It can be SD-card.

This check and message were taken from mmc_hwpart_config(). I think it
is okay (after all it tells you "eMMC [...] required [...]" if you try
the command on an SD card), but I can extend the message if you want.

I also noticed another slight difference between the check and the
message: The check is for eMMC 4.41, while the message talks about eMMC
4.4. I'd like to make both match, but I don't know whether 4.4 or 4.41
is the correct requirement.


> 
> > +   return -EMEDIUMTYPE;
> > +   }
> > +
> > +   if (!(mmc->part_support & PART_SUPPORT)) {
> > +   pr_err("Card does not support partitioning\n");
> > +   return -EMEDIUMTYPE;
> > +   }
> > +
> > +   if (!mmc->hc_wp_grp_size) {
> > +   pr_err("Card does not define HC WP group size\n");
> > +   return -EMEDIUMTYPE;
> > +   }
> > +
> > +   err = mmc_send_ext_csd(mmc, ext_csd);
> > +   if (err)
> > +   return err;
> > +
> > +   sz =
> > +   (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 2] << 16) +
> > +   (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 1] << 8) +
> > +   ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
> > +   sz *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
> > +   sz *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
> > +   sz *= SZ_1K;
> 
> To use the num of sector, i think better that is adding Comment.
> And using not "sz" as variable. It seems to describe real size, not sector.
> According to spec, it's 512kByte. It can be confused.

Makes sense, I'll change the variable name.

> 
> Best Regards,
> Jaehoon Chung
> 
> > +   *size = sz;
> > +
> > +   return 0;
> > +}
> > +
> >  int mmc_hwpart_config(struct mmc *mmc,
> >   const struct mmc_hwpart_conf *conf,
> >   enum mmc_hwpart_conf_mode mode)
> > diff --git a/include/mmc.h b/include/mmc.h
> > index b92e2553402..3e1fc82d9b4 100644
> > --- a/include/mmc.h
> > +++ b/include/mmc.h
> > @@ -846,6 +846,7 @@ void print_mmc_devices(char separator);
> >   */
> >  int get_mmc_num(void);
> >  int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
> > +int mmc_max_enhanced_size_sectors(struct mmc *mmc, u64 *size);
> >  int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
> >   enum mmc_hwpart_conf_mode mode);
> >  
> > 
> 
>

Re: [PATCH] Makelfile: clean target should remove itb*

2021-09-23 Thread Bin Meng

Hi Heinrich,

On Thu, Sep 23, 2021 at 6:12 PM Heinrich Schuchardt
 wrote:
>
> In the U-Boot directory files itb.fit.fit, itb.fit.itb, itb.map are
> created (e.g. for sifive_unmatched_defconfig). These should be removed by
> the clean target.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  Makefile | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

See 
http://patchwork.ozlabs.org/project/uboot/patch/20210505141557.23901-8-bmeng...@gmail.com/

Simon suggested binman should be updated to output the generated files.

Regards,
Bin

Re: [PATCH] drivers: pmic: Add sysreset driver to da9063 pmic device

Hi Alexandre,

On 9/21/21 12:48 AM, Alexandre Ghiti wrote:
> This pmic device is present on the SiFive Unmatched board and this
> new driver adds the possibility to reset it.

Is there any patch before applying this?
I cant' apply this from patchwork for checking.
If i missed something, let me know, plz.

Best Regards,
Jaehoon Chung

> 
> Signed-off-by: Alexandre Ghiti 
> ---
>  configs/sifive_unmatched_defconfig |  2 ++
>  drivers/power/pmic/da9063.c| 49 ++
>  2 files changed, 51 insertions(+)
> 
> diff --git a/configs/sifive_unmatched_defconfig 
> b/configs/sifive_unmatched_defconfig
> index 978818b688..9ab058be39 100644
> --- a/configs/sifive_unmatched_defconfig
> +++ b/configs/sifive_unmatched_defconfig
> @@ -43,3 +43,5 @@ CONFIG_DM_USB=y
>  CONFIG_USB_XHCI_HCD=y
>  CONFIG_USB_XHCI_PCI=y
>  CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_DM_PMIC=y
> +CONFIG_DM_PMIC_DA9063=y
> diff --git a/drivers/power/pmic/da9063.c b/drivers/power/pmic/da9063.c
> index 25101d18f7..b04879d9c5 100644
> --- a/drivers/power/pmic/da9063.c
> +++ b/drivers/power/pmic/da9063.c
> @@ -10,6 +10,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -87,6 +88,7 @@ static int da9063_bind(struct udevice *dev)
>  {
>   ofnode regulators_node;
>   int children;
> + int ret;
>  
>   regulators_node = dev_read_subnode(dev, "regulators");
>   if (!ofnode_valid(regulators_node)) {
> @@ -101,6 +103,14 @@ static int da9063_bind(struct udevice *dev)
>   if (!children)
>   debug("%s: %s - no child found\n", __func__, dev->name);
>  
> + if (CONFIG_IS_ENABLED(SYSRESET)) {
> + ret = device_bind_driver(dev, "da9063-sysreset",
> +  "da9063-sysreset", NULL);
> + if (ret)
> + debug("%s: %s - failed to bind sysreset driver\n",
> +   __func__, dev->name);
> + }
> +
>   /* Always return success for this device */
>   return 0;
>  }
> @@ -129,3 +139,42 @@ U_BOOT_DRIVER(pmic_da9063) = {
>   .probe = da9063_probe,
>   .ops = _ops,
>  };
> +
> +#ifdef CONFIG_SYSRESET
> +#include 
> +
> +static int da9063_sysreset_request(struct udevice *dev, enum sysreset_t type)
> +{
> + struct udevice *pmic_dev = dev->parent;
> + uint ret;
> +
> + if (type != SYSRESET_WARM && type != SYSRESET_COLD)
> + return -EPROTONOSUPPORT;
> +
> + ret = pmic_reg_write(pmic_dev, DA9063_REG_PAGE_CON, 0x00);
> + if (ret < 0)
> + return ret;
> +
> + /* Sets the WAKE_UP bit */
> + ret = pmic_reg_write(pmic_dev, DA9063_REG_CONTROL_F, 0x04);
> + if (ret < 0)
> + return ret;
> +
> + /* Powerdown! */
> + ret = pmic_reg_write(pmic_dev, DA9063_REG_CONTROL_A, 0x68);
> + if (ret < 0)
> + return ret;
> +
> + return -EINPROGRESS;
> +}
> +
> +static struct sysreset_ops da9063_sysreset_ops = {
> + .request = da9063_sysreset_request,
> +};
> +
> +U_BOOT_DRIVER(da9063_sysreset) = {
> + .name = "da9063-sysreset",
> + .id = UCLASS_SYSRESET,
> + .ops = _sysreset_ops,
> +};
> +#endif
>

Re: [PATCH 2/2] cmd/mmc: add subcommand to query max enhanced partition size

On 9/22/21 9:30 PM, Matthias Schiffer wrote:
> From: Markus Niebel 
> 
> The new command prints the sector count and size in a human-readable
> format and sets an environment variable for scripted handling. The
> variable value is set in decimal to match what the 'mmc hwpartition'
> command expects.
> 
> The environment variable can be used for automated partitioning scripts,
> for example the following would convert a whole eMMC to pSLC mode:
> 
> mmc maxhwpartsectors
> mmc hwpartition user enh 0 ${maxhwpartsectors} wrrel on complete


I don't have any objection about this patch.
If we can use more simpler variable name than maxhwpartsectors, I think that 
it's more useful.
But it's not important. :)

And Could you update doc/usage/mmc.rst about this command?

Best Regards,
Jaehoon Chung

> 
> Signed-off-by: Markus Niebel 
> Signed-off-by: Matthias Schiffer 
> ---
> 
> The human-readable output of the command could also be added to `mmc info`,
> but it would still be great to have a separate command that sets an
> environment variable for scripting, like this patch adds.
> 
> 
>  cmd/mmc.c | 30 ++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/cmd/mmc.c b/cmd/mmc.c
> index f1e30d0cf64..d0b33cc0494 100644
> --- a/cmd/mmc.c
> +++ b/cmd/mmc.c
> @@ -593,6 +593,33 @@ static int do_mmc_list(struct cmd_tbl *cmdtp, int flag,
>  }
>  
>  #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
> +static int do_mmc_maxhwpartsectors(struct cmd_tbl *cmdtp, int flag, int 
> argc, char * const argv[])
> +{
> + struct mmc *mmc;
> + u64 sectors;
> +
> + mmc = init_mmc_device(curr_device, false);
> + if (!mmc)
> + return CMD_RET_FAILURE;
> +
> + if (mmc_max_enhanced_size_sectors(mmc, ))
> + return CMD_RET_FAILURE;
> +
> + /* Ensure that the value fits in mmc_hwpart_conf::user.enh_size */
> + if (sectors > UINT_MAX) {
> + puts("ERROR: sector count larger than UINT_MAX\n");
> + return CMD_RET_FAILURE;
> + }
> +
> + env_set_ulong("maxhwpartsectors", sectors);
> +
> + printf("Maximum size of hardware partition: %u sectors (",
> +(uint)sectors);
> + print_size(sectors * 512, ")\n");
> +
> + return 0;
> +}
> +
>  static int parse_hwpart_user(struct mmc_hwpart_conf *pconf,
>int argc, char *const argv[])
>  {
> @@ -1021,6 +1048,7 @@ static struct cmd_tbl cmd_mmc[] = {
>   U_BOOT_CMD_MKENT(dev, 4, 0, do_mmc_dev, "", ""),
>   U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""),
>  #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
> + U_BOOT_CMD_MKENT(maxhwpartsectors, 1, 0, do_mmc_maxhwpartsectors, "", 
> ""),
>   U_BOOT_CMD_MKENT(hwpartition, 28, 0, do_mmc_hwpartition, "", ""),
>  #endif
>  #ifdef CONFIG_SUPPORT_EMMC_BOOT
> @@ -1084,6 +1112,8 @@ U_BOOT_CMD(
>   "mmc list - lists available devices\n"
>   "mmc wp - power on write protect boot partitions\n"
>  #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
> + "mmc maxhwpartsectors - shows the maximum number of 512-byte blocks 
> usable for hardware partitioning\n"
> + "  Sets env var maxhwpartsectors on success.\n"
>   "mmc hwpartition- does hardware partitioning\n"
>   "  arguments (sizes in 512-byte blocks):\n"
>   "   USER -  <{on|off}>\n"
>

Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing

On Thu, Sep 23, 2021 at 01:50:41PM +0200, Francesco Dolcini wrote:
> On Thu, Sep 23, 2021 at 07:36:34AM -0400, Tom Rini wrote:
> > On Thu, Sep 23, 2021 at 09:55:21AM +0200, Francesco Dolcini wrote:
> > 
> > > colibri-imx6ull ethernet device is fec2, while the optional secondary
> > > ethernet is fec1, update the ethernet aliases in the .dts file so that
> > > ethaddr is set to fec2 and eth1addr to fec1.
> > > 
> > > Without this change the ethernet interfaces have a different
> > > mac address between Linux and U-Boot.
> > > 
> > > Signed-off-by: Francesco Dolcini 
> > > 
> > > ---
> > > 
> > >  arch/arm/dts/imx6ull-colibri.dtsi | 6 ++
> > >  1 file changed, 6 insertions(+)
> > > 
> > > diff --git a/arch/arm/dts/imx6ull-colibri.dtsi 
> > > b/arch/arm/dts/imx6ull-colibri.dtsi
> > > index b7bf79f28c..104207be97 100644
> > > --- a/arch/arm/dts/imx6ull-colibri.dtsi
> > > +++ b/arch/arm/dts/imx6ull-colibri.dtsi
> > > @@ -8,6 +8,12 @@
> > >  #include "imx6ull.dtsi"
> > >  
> > >  / {
> > > + /* Ethernet aliases to ensure correct MAC addresses */
> > > + aliases {
> > > + ethernet0 = 
> > > + ethernet1 = 
> > > + };
> > > +
> > >   chosen {
> > >   stdout-path = 
> > >   };
> > 
> > The main dts* files aren't supposed to change between U-Boot and Linux.
> > Is this re-syncing the file with current upstream then?  Thanks.
> 
> Currently they are out of sync, correct, and because of this difference on the
> ethernet aliases we have the situation in which the MAC address assigned to 
> the
> ethernet interfaces is different between Linux an U-Boot.

OK, we can take this now as an important bugfix.

> There are other differences that this patchset is not trying to address and
> that are not causing any known issues.

Please plan to sync the trees up for the next merge window, they are not
supposed to stay out of sync.  Thanks.

-- 
Tom


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Re: [PATCH 1/2] mmc: add helper to query max enhanced part size

Hi,

On 9/22/21 9:30 PM, Matthias Schiffer wrote:
> From: Markus Niebel 
> 
> This helper will be used later on in an extension of the mmc
> command.
> 
> Signed-off-by: Markus Niebel 
> Signed-off-by: Matthias Schiffer 
> ---
>  drivers/mmc/mmc.c | 38 ++
>  include/mmc.h |  1 +
>  2 files changed, 39 insertions(+)
> 
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index d3babbfeb1c..c1b1ef7eb0b 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -1039,6 +1039,44 @@ int mmc_switch_part(struct mmc *mmc, unsigned int 
> part_num)
>  }
>  
>  #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
> +int mmc_max_enhanced_size_sectors(struct mmc *mmc, u64 *size)
> +{
> + u64 sz;
> + int err;
> +
> + ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
> +
> + if (IS_SD(mmc) || mmc->version < MMC_VERSION_4_41) {
> + pr_err("eMMC >= 4.4 required for enhanced user data area\n");

Error log is considering about only eMMC. It can be SD-card.

> + return -EMEDIUMTYPE;
> + }
> +
> + if (!(mmc->part_support & PART_SUPPORT)) {
> + pr_err("Card does not support partitioning\n");
> + return -EMEDIUMTYPE;
> + }
> +
> + if (!mmc->hc_wp_grp_size) {
> + pr_err("Card does not define HC WP group size\n");
> + return -EMEDIUMTYPE;
> + }
> +
> + err = mmc_send_ext_csd(mmc, ext_csd);
> + if (err)
> + return err;
> +
> + sz =
> + (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 2] << 16) +
> + (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 1] << 8) +
> + ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
> + sz *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
> + sz *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
> + sz *= SZ_1K;

To use the num of sector, i think better that is adding Comment.
And using not "sz" as variable. It seems to describe real size, not sector.
According to spec, it's 512kByte. It can be confused.

Best Regards,
Jaehoon Chung

> + *size = sz;
> +
> + return 0;
> +}
> +
>  int mmc_hwpart_config(struct mmc *mmc,
> const struct mmc_hwpart_conf *conf,
> enum mmc_hwpart_conf_mode mode)
> diff --git a/include/mmc.h b/include/mmc.h
> index b92e2553402..3e1fc82d9b4 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -846,6 +846,7 @@ void print_mmc_devices(char separator);
>   */
>  int get_mmc_num(void);
>  int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
> +int mmc_max_enhanced_size_sectors(struct mmc *mmc, u64 *size);
>  int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
> enum mmc_hwpart_conf_mode mode);
>  
>

Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing

2021-09-23 Thread Francesco Dolcini

On Thu, Sep 23, 2021 at 07:36:34AM -0400, Tom Rini wrote:
> On Thu, Sep 23, 2021 at 09:55:21AM +0200, Francesco Dolcini wrote:
> 
> > colibri-imx6ull ethernet device is fec2, while the optional secondary
> > ethernet is fec1, update the ethernet aliases in the .dts file so that
> > ethaddr is set to fec2 and eth1addr to fec1.
> > 
> > Without this change the ethernet interfaces have a different
> > mac address between Linux and U-Boot.
> > 
> > Signed-off-by: Francesco Dolcini 
> > 
> > ---
> > 
> >  arch/arm/dts/imx6ull-colibri.dtsi | 6 ++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/arch/arm/dts/imx6ull-colibri.dtsi 
> > b/arch/arm/dts/imx6ull-colibri.dtsi
> > index b7bf79f28c..104207be97 100644
> > --- a/arch/arm/dts/imx6ull-colibri.dtsi
> > +++ b/arch/arm/dts/imx6ull-colibri.dtsi
> > @@ -8,6 +8,12 @@
> >  #include "imx6ull.dtsi"
> >  
> >  / {
> > +   /* Ethernet aliases to ensure correct MAC addresses */
> > +   aliases {
> > +   ethernet0 = 
> > +   ethernet1 = 
> > +   };
> > +
> > chosen {
> > stdout-path = 
> > };
> 
> The main dts* files aren't supposed to change between U-Boot and Linux.
> Is this re-syncing the file with current upstream then?  Thanks.

Currently they are out of sync, correct, and because of this difference on the
ethernet aliases we have the situation in which the MAC address assigned to the
ethernet interfaces is different between Linux an U-Boot.

There are other differences that this patchset is not trying to address and
that are not causing any known issues.

Francesco

Re: [PATCH] ARM: dts: colibri-imx6ull: fix mac address passing