[PATCH] net: phy: add TI DP83869HM ethernet driver
From: Dominic Rath This driver is based on an older downstream TI kernel, with changes and cleanups to work with mainline device-tree bindings. Signed-off-by: Dominic Rath Signed-off-by: Christian Gmeiner --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83869.c| 507 +++ drivers/net/phy/ti_phy_init.c| 4 + drivers/net/phy/ti_phy_init.h| 1 + include/dt-bindings/net/ti-dp83869.h | 60 6 files changed, 579 insertions(+) create mode 100644 drivers/net/phy/dp83869.c create mode 100644 include/dt-bindings/net/ti-dp83869.h diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 68ee7d7a2d..c6e58058d9 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -290,6 +290,12 @@ config PHY_TI_DP83867 ---help--- Adds support for the TI DP83867 1Gbit PHY. +config PHY_TI_DP83869 + select PHY_TI + bool "Texas Instruments Ethernet DP83869 PHY support" + ---help--- + Adds support for the TI DP83869 1Gbit PHY. + config PHY_TI_GENERIC select PHY_TI bool "Texas Instruments Generic Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 218b8c7669..77f7f60621 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o obj-$(CONFIG_PHY_TI) += ti_phy_init.o obj-$(CONFIG_PHY_TI_DP83867) += dp83867.o +obj-$(CONFIG_PHY_TI_DP83869) += dp83869.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c new file mode 100644 index 00..c9461185cf --- /dev/null +++ b/drivers/net/phy/dp83869.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI PHY drivers + * + */ + +#include +#include +#include +#include + +#include +#include + +/* TI DP83869 */ +#define DP83869_DEVADDR0x1f + +#define MII_DP83869_PHYCTRL0x10 +#define MII_DP83869_MICR 0x12 +#define MII_DP83869_CFG2 0x14 +#define MII_DP83869_BISCR 0x16 +#define DP83869_CTRL 0x1f +#define DP83869_CFG4 0x1e + +/* Extended Registers */ +#define DP83869_GEN_CFG3 0x0031 +#define DP83869_RGMIICTL 0x0032 +#define DP83869_STRAP_STS1 0x006E +#define DP83869_RGMIIDCTL 0x0086 +#define DP83869_IO_MUX_CFG 0x0170 +#define DP83869_OP_MODE0x01df +#define DP83869_FX_CTRL0x0c00 + +#define DP83869_SW_RESET BIT(15) +#define DP83869_SW_RESTART BIT(14) + +/* MICR Interrupt bits */ +#define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) +#define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) +#define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) +#define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) +#define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) +#define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) +#define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) +#define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_ENBIT(4) +#define MII_DP83869_MICR_WOL_INT_ENBIT(3) +#define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) +#define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) +#define MII_DP83869_MICR_JABBER_INT_EN BIT(0) + +#define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ +BMCR_FULLDPLX | \ +BMCR_SPEED1000) + +/* This is the same bit mask as the BMCR so re-use the BMCR default */ +#define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT + +/* CFG1 bits */ +#define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \ +ADVERTISE_1000FULL | \ +CTL1000_AS_MASTER) + +/* RGMIICTL bits */ +#define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) +#define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) + +/* STRAP_STS1 bits */ +#define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) +#define DP83869_STRAP_STS1_RESERVEDBIT(11) +#define DP83869_STRAP_MIRROR_ENABLED BIT(12) + +/* PHY CTRL bits */ +#define DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT 12 +#define DP83869_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) +#define DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT 14 +#define DP83869_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) +#define DP83869_PHYCR_RESERVED_MASKBIT(11) +#define DP83869_PHYCR_MDI_CROSSOVER_SHIFT 5 +#define DP83869_PHYCR_MDI_CROSSOVER_MDIX 2 +#define DP83869_PHY_CTRL_DEFAULT 0x48 + +/* RGMIIDCTL bits */ +#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 +#define DP83869_CLK_DELAY_DEF
RE: printf works but how can I make debug() printed to serial port console?
As the document said, I tried added "#define DEBUG" in each file but it doesn't work. If I add "#define debug printf" then, of course debug() is printed. -Original Message- From: U-Boot On Behalf Of Chan Kim Sent: Wednesday, December 22, 2021 3:13 PM To: U-Boot Mailing List Subject: printf works but how can I make debug() printed to serial port console? Hello all, I'm trying to boot from RAM using SPL only. (Another scp processor loads the FIT image to the SDRAM before starting u-boot-spl is started) Since the debugger doesn't work yet, I have to rely on prints to debug. The printf works fine (I once asked about initializing serial port here, and later found serial_init is done in board_init_f ). I tried to make debug(xxx) printed to serial port but couldn't figure out how to do it. I tried 1. Adding #define DEBUG to the relevant source file 2. Giving DEBUG=1 in the make command (or CFLAGS=-DDEBUG) But it doesn't work (of course I can change debug to printf to see it). How can I make debug( ) macro output to the serial port? Thank you! Chan Kim
printf works but how can I make debug() printed to serial port console?
Hello all, I'm trying to boot from RAM using SPL only. (Another scp processor loads the FIT image to the SDRAM before starting u-boot-spl is started) Since the debugger doesn't work yet, I have to rely on prints to debug. The printf works fine (I once asked about initializing serial port here, and later found serial_init is done in board_init_f ). I tried to make debug(xxx) printed to serial port but couldn't figure out how to do it. I tried 1. Adding #define DEBUG to the relevant source file 2. Giving DEBUG=1 in the make command (or CFLAGS=-DDEBUG) But it doesn't work (of course I can change debug to printf to see it). How can I make debug( ) macro output to the serial port? Thank you! Chan Kim
Re: [PATCH v2 1/2] doc: Add documentation for the Arm VExpress64 board configs
On Mon, Dec 20, 2021 at 7:12 PM Andre Przywara wrote: > From: Peter Hoyes > > Create a new documentation section for Arm Ltd boards with a sub-page > for the FVP VExpress64 system. > > Signed-off-by: Peter Hoyes > [Andre: remove Juno stub, RSTify] > Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij Yours, Linus Walleij
Re: [PATCH v2 2/2] doc: add Arm Juno board documentation
On Mon, Dec 20, 2021 at 7:12 PM Andre Przywara wrote: > The Juno Arm development board is an open, vendor-neutral, Armv8-A > development platform. > Add documentation that briefly outlines the hardware, and describes > building and installation of U-Boot. > > Signed-off-by: Andre Przywara This is excellent and much needed documentation. Thank you so much for doing this Andre! Reviewed-by: Linus Walleij Yours, Linus Walleij
Re: [PATCH] udoo_neo: Move to DM for REGUALTOR/PMIC/I2C drivers
Hi Peter,
On Tue, Dec 21, 2021 at 9:17 PM Peter Robinson wrote:
>
> This moves over the PMIC power init to DM and the associated i2c and
> regulator bits.
>
> Signed-off-by: Peter Robinson
> ---
> board/udoo/neo/neo.c | 139 +++--
> configs/udoo_neo_defconfig | 10 +--
> include/configs/udoo_neo.h | 5 --
> 3 files changed, 15 insertions(+), 139 deletions(-)
Nice diff ;-)
Reviewed-by: Fabio Estevam
>
> diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
> index 62f81fff68..d374b86b5d 100644
> --- a/board/udoo/neo/neo.c
> +++ b/board/udoo/neo/neo.c
> @@ -51,11 +51,6 @@ enum {
> PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
> PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>
> -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> - PAD_CTL_ODE)
> -
> #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
> PAD_CTL_SPEED_MED | \
> PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> @@ -81,135 +76,25 @@ int dram_init(void)
> return 0;
> }
>
> -#ifdef CONFIG_SYS_I2C_MXC
> -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> -/* I2C1 for PMIC */
> -static struct i2c_pads_info i2c_pad_info1 = {
> - .scl = {
> - .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
> - .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
> - .gp = IMX_GPIO_NR(1, 0),
> - },
> - .sda = {
> - .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
> - .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
> - .gp = IMX_GPIO_NR(1, 1),
> - },
> -};
> -#endif
> -
> -#if CONFIG_IS_ENABLED(POWER_LEGACY)
> int power_init_board(void)
> {
> - struct pmic *p;
> - int ret;
> - unsigned int reg, rev_id;
> -
> - ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
> - if (ret)
> - return ret;
> -
> - p = pmic_get("PFUZE3000");
> - ret = pmic_probe(p);
> - if (ret)
> - return ret;
> + struct udevice *dev;
> + int ret, dev_id, rev_id;
>
> - pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
> - pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
> - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
> -
> - /* disable Low Power Mode during standby mode */
> - pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
> - reg |= 0x1;
> - ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
> - if (ret)
> + ret = pmic_get("pfuze3000@8", &dev);
> + if (ret == -ENODEV)
> + return 0;
> + if (ret != 0)
> return ret;
>
> - ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
> - if (ret)
> - return ret;
> + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
> + rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
> + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
>
> - ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
> - if (ret)
> - return ret;
> -
> - ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
> - if (ret)
> - return ret;
> -
> - ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
> - if (ret)
> - return ret;
> -
> - /* set SW1A standby voltage 0.975V */
> - pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®);
> - reg &= ~0x3f;
> - reg |= PFUZE3000_SW1AB_SETP(9750);
> - ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
> - if (ret)
> - return ret;
> -
> - /* set SW1B standby voltage 0.975V */
> - pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®);
> - reg &= ~0x3f;
> - reg |= PFUZE3000_SW1AB_SETP(9750);
> - ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
> - if (ret)
> - return ret;
> -
> - /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
> - pmic_reg_read(p, PFUZE3000_SW1ACONF, ®);
> - reg &= ~0xc0;
> - reg |= 0x40;
> - ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
> - if (ret)
> - return ret;
> -
> - /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
> - pmic_reg_read(p, PFUZE3000_SW1BCONF, ®);
> - reg &= ~0xc0;
> - reg |= 0x40;
> - ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
> - if (ret)
> - return ret;
> -
> - /* set VDD_ARM_IN to 1.350V */
> - pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®);
> - reg &= ~0x3f;
> - reg |= PFUZE3000_SW1AB_SETP(13500);
> - ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
> - if (ret)
> - return ret;
> -
> - /* set VDD_SOC_IN to 1.350V */
> - pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
> - reg
[PATCH] udoo_neo: Move to DM for REGUALTOR/PMIC/I2C drivers
This moves over the PMIC power init to DM and the associated i2c and
regulator bits.
Signed-off-by: Peter Robinson
---
board/udoo/neo/neo.c | 139 +++--
configs/udoo_neo_defconfig | 10 +--
include/configs/udoo_neo.h | 5 --
3 files changed, 15 insertions(+), 139 deletions(-)
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 62f81fff68..d374b86b5d 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -51,11 +51,6 @@ enum {
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
-
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
@@ -81,135 +76,25 @@ int dram_init(void)
return 0;
}
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
- .gp = IMX_GPIO_NR(1, 0),
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
- .gp = IMX_GPIO_NR(1, 1),
- },
-};
-#endif
-
-#if CONFIG_IS_ENABLED(POWER_LEGACY)
int power_init_board(void)
{
- struct pmic *p;
- int ret;
- unsigned int reg, rev_id;
-
- ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
- if (ret)
- return ret;
-
- p = pmic_get("PFUZE3000");
- ret = pmic_probe(p);
- if (ret)
- return ret;
+ struct udevice *dev;
+ int ret, dev_id, rev_id;
- pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
- pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
-
- /* disable Low Power Mode during standby mode */
- pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
- reg |= 0x1;
- ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
- if (ret)
+ ret = pmic_get("pfuze3000@8", &dev);
+ if (ret == -ENODEV)
+ return 0;
+ if (ret != 0)
return ret;
- ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
- if (ret)
- return ret;
+ dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
- ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
- if (ret)
- return ret;
-
- ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
- if (ret)
- return ret;
-
- ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
- if (ret)
- return ret;
-
- /* set SW1A standby voltage 0.975V */
- pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®);
- reg &= ~0x3f;
- reg |= PFUZE3000_SW1AB_SETP(9750);
- ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
- if (ret)
- return ret;
-
- /* set SW1B standby voltage 0.975V */
- pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®);
- reg &= ~0x3f;
- reg |= PFUZE3000_SW1AB_SETP(9750);
- ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
- if (ret)
- return ret;
-
- /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE3000_SW1ACONF, ®);
- reg &= ~0xc0;
- reg |= 0x40;
- ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
- if (ret)
- return ret;
-
- /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE3000_SW1BCONF, ®);
- reg &= ~0xc0;
- reg |= 0x40;
- ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
- if (ret)
- return ret;
-
- /* set VDD_ARM_IN to 1.350V */
- pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®);
- reg &= ~0x3f;
- reg |= PFUZE3000_SW1AB_SETP(13500);
- ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
- if (ret)
- return ret;
-
- /* set VDD_SOC_IN to 1.350V */
- pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
- reg &= ~0x3f;
- reg |= PFUZE3000_SW1AB_SETP(13500);
- ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
- if (ret)
- return ret;
-
- /* set DDR_1_5V to 1.350V */
- pmic_reg_read(p, PFUZE3000_SW3VOLT, ®);
- reg &= ~0x0f;
- reg |= PFUZE3000_SW3_SETP(13500);
- ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
- if (ret)
-
[PATCH 11/11] drivers/usb/gadget/dwc2_udc_otg.c: Fix spelling of "resetting".
---
drivers/usb/gadget/dwc2_udc_otg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c
b/drivers/usb/gadget/dwc2_udc_otg.c
index 2f31814442..b30604eba0 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -461,7 +461,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
u32 max_hw_ep;
int pdata_hw_ep;
- debug("Reseting OTG controller\n");
+ debug("Resetting OTG controller\n");
dflt_gusbcfg =
0<<15 /* PHY Low Power Clock sel*/
--
2.30.2
[PATCH 09/11] arch/arm/mach-keystone/ddr3.c: Fix spelling of "resetting".
---
arch/arm/mach-keystone/ddr3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 9ee3284156..53117c2695 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -344,7 +344,7 @@ void ddr3_check_ecc_int(u32 base)
puts("DDR3 ECC 2-bit error interrupted\n");
if (!ecc_test) {
- puts("Reseting the device ...\n");
+ puts("Resetting the device ...\n");
reset_cpu();
}
}
--
2.30.2
[PATCH 10/11] drivers/ddr/altera/sequencer.c: Fix spelling of "resetting".
--- drivers/ddr/altera/sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 8a016f0628..e402f2929a 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -2770,7 +2770,7 @@ rw_mgr_mem_calibrate_dqs_enable_calibration(struct socfpga_sdrseq *seq, ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(seq, rw_group); debug_cond(DLEVEL >= 1, - "%s:%d: g=%u found=%u; Reseting delay chain to zero\n", + "%s:%d: g=%u found=%u; Resetting delay chain to zero\n", __func__, __LINE__, rw_group, !ret); for (r = 0; r < seq->rwcfg->mem_number_of_ranks; -- 2.30.2
[PATCH 07/11] common/fdt_support.c: Fix spelling of "shouldn't".
---
common/fdt_support.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 8992ac5d3f..a7dbe0efdf 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -1407,7 +1407,7 @@ int fdt_get_dma_range(const void *blob, int node,
phys_addr_t *cpu,
node = parent;
parent = fdt_parent_offset(blob, node);
if (parent < 0) {
- printf("Found dma-ranges in root node, shoudln't happen\n");
+ printf("Found dma-ranges in root node, shouldn't happen\n");
ret = -EINVAL;
goto out;
}
--
2.30.2
[PATCH 08/11] drivers/core/of_addr.c: Fix spelling of "shouldn't".
---
drivers/core/of_addr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c
index 3fbc0a7afa..431dd4e565 100644
--- a/drivers/core/of_addr.c
+++ b/drivers/core/of_addr.c
@@ -367,7 +367,7 @@ int of_get_dma_range(const struct device_node *dev,
phys_addr_t *cpu,
/* switch to that node */
parent = of_get_parent(dev);
if (!parent) {
- printf("Found dma-ranges in root node, shoudln't happen\n");
+ printf("Found dma-ranges in root node, shouldn't happen\n");
ret = -EINVAL;
goto out;
}
--
2.30.2
[PATCH 06/11] drivers/net/fec_mxc.c: Fix spelling of "resetting".
---
drivers/net/fec_mxc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 40a86a3e12..811bc275c1 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1465,7 +1465,7 @@ static int fecmxc_probe(struct udevice *dev)
start = get_timer(0);
while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
- printf("FEC MXC: Timeout reseting chip\n");
+ printf("FEC MXC: Timeout resetting chip\n");
goto err_timeout;
}
udelay(10);
--
2.30.2
[PATCH 05/11] cmd/Kconfig: Fix spelling of "resetting".
--- cmd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 5b30b13e43..bb11aec9b7 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1012,7 +1012,7 @@ config CMD_IDE select IDE help Provides an 'ide' command which allows accessing the IDE drive, - reseting the IDE interface, printing the partition table and + resetting the IDE interface, printing the partition table and geting device info. It also enables the 'diskboot' command which permits booting from an IDE drive. -- 2.30.2
[PATCH 04/11] arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c: Fix spelling of "resetting".
--- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index 41c89b8904..60769e139e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -249,7 +249,7 @@ int setup_serdes_volt(u32 svdd) /* * If SVDD set failed, will not return directly, so that the -* serdes lanes can complete reseting. +* serdes lanes can complete resetting. */ ret = set_serdes_volt(svdd_tar); if (ret) -- 2.30.2
[PATCH 03/11] drivers/usb/musb/musb_udc.c: Fix spelling of "mismatch".
---
drivers/usb/musb/musb_udc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c
index b9510e3045..2ffcb7caaa 100644
--- a/drivers/usb/musb/musb_udc.c
+++ b/drivers/usb/musb/musb_udc.c
@@ -269,7 +269,7 @@ static void musb_peri_ep0_set_address(void)
__PRETTY_FUNCTION__, udc_device->address);
} else {
if (debug_level > 0)
- serial_printf("ERROR : %s Address missmatch "
+ serial_printf("ERROR : %s Address mismatch "
"sw %d vs hw %d\n",
__PRETTY_FUNCTION__,
udc_device->address, faddr);
--
2.30.2
[PATCH 02/11] drivers/mtd/ubispl/ubispl.c: Fix spelling of "mismatched".
---
drivers/mtd/ubispl/ubispl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c
index 03b31f002b..b58d8e8d56 100644
--- a/drivers/mtd/ubispl/ubispl.c
+++ b/drivers/mtd/ubispl/ubispl.c
@@ -953,7 +953,7 @@ retry:
* Check, if the total number of blocks is correct
*/
if (be32_to_cpu(vh->used_ebs) != last) {
- ubi_dbg("Block count missmatch.");
+ ubi_dbg("Block count mismatch.");
ubi_dbg("vh->used_ebs: %d nrblocks: %d",
be32_to_cpu(vh->used_ebs), last);
generic_set_bit(pnum, ubi->corrupt);
--
2.30.2
[PATCH 01/11] arch/arm/mach-bcm283x/msg.c: Fix spelling of "Failed".
---
arch/arm/mach-bcm283x/msg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
index 01a8ed2a7b..fe243e2dca 100644
--- a/arch/arm/mach-bcm283x/msg.c
+++ b/arch/arm/mach-bcm283x/msg.c
@@ -194,7 +194,7 @@ int bcm2711_notify_vl805_reset(void)
ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
&msg_notify_vl805_reset->hdr);
if (ret) {
- printf("bcm2711: Faild to load vl805's firmware, %d\n", ret);
+ printf("bcm2711: Failed to load vl805's firmware, %d\n", ret);
return -EIO;
}
--
2.30.2
Aw: extend environment with file
Hi, as far as i have debugged it: soc-config is in CONFIG_EXTRA_ENV_SETTINGS distroboot (include/config_distro_bootcmd.h) lands in BOOTENV magic is in include/env_default.h where at least CONFIG_EXTRA_ENV_SETTINGS is only mapped if CONFIG_USE_DEFAULT_ENV_FILE is not set, if set a generated headerfile generated/defaultenv_autogenerated.h is included which contains some magic numbers (i guess hex-values of the chars from the file). this seems to be generated in main Makefile, but i'm not sure how exactly (anyhow with tools/env/). any idea to concatenate both sources? regards Frank > Gesendet: Dienstag, 21. Dezember 2021 um 13:56 Uhr > Von: "Frank Wunderlich" > An: "U-Boot Mailing List" > Betreff: extend environment with file > > Hi, > > currently i use distroboot on my board which sets some environment-variables, > some other (memory addresses) were set in my soc-specific header file > (include/configs/rk3568_common.h). > > But distroboot is a bit too limited for my needs (no tftp, no script, ...), > so imho i need to use the bootmenu way here, but for local kernel-bootup run > distro_bootcmd. > > I want to add some more variables (e.g. for bootmenu) and for easier > maintaining i used a txt-file for it and defined > > CONFIG_DEFAULT_ENV_FILE="uEnv_r2pro.txt" > > but this option seems to clear the previous environment from distroboot and > soc header file...i have now only the vars from the file defined. > > i tried adding CONFIG_ENV_APPEND=y but i have still only the vars from the > file. > > Is there a way to append (distrocmd + soc-header + uenv-file) instead of > overwriting? > > regards Frank >
Re: [PATCH 0/3] misc: atsha204a: bug fixes
On Tue, 21 Dec 2021 10:00:14 -0700 Josh Datko wrote: > Thanks everyone for including me — I don’t have any code comments but I will > say that this i2c driver, with the exception of the i2c default address > (which looks like is being set via the device tree anyway), should also work > with the ATECC508, ATECC608A, ATECC608B (which is the one of those three > recommended for new designs) as I believe the interface at this level was not > changed. We have been unable to get those, wich current chip crisis, and so we couldn't test. Marek
Re: [PATCH 3/3] misc: atsha204a: fix i2c address readout from DTS
On Tue, 21 Dec 2021 17:17:22 +0100 Adrian Fiergolski wrote: > This patch replaces use fdtdec_get_addr with recommended > fdtdec_get_addr_size_auto_parent. And why is that required? If at all, I would rather change it to simple dev_read_addr(). Marek
Re: [PATCH 2/3] misc: atsha204a: add delay after sending the message
On Tue, 21 Dec 2021 17:17:21 +0100 Adrian Fiergolski wrote: > Once request is sent, and before receiving a response, the delay is required. > This patch fixes missing delay for before first response try. > > Signed-off-by: Adrian Fiergolski Reviewed-by: Marek Behún
Re: [PATCH 1/3] misc: atsha204a: return timeout from wakeup function
On Tue, 21 Dec 2021 17:17:20 +0100 Adrian Fiergolski wrote: > If the maximum number of wake-up attempts is exceeded, return -ETIMEDOUT. > > Signed-off-by: Adrian Fiergolski Reviewed-by: Marek Behún
[PATCH] armv8: apple: Disable PSCI reset
Apple's ARMv8 cores don't implement EL3 and therefore don't provide a PSCI implementation. So don't attempt to use PSCI to reset on machines using Apple SoCs. Signed-off-by: Mark Kettenis --- arch/arm/cpu/armv8/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 0a3fdfa471..9967376eca 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -102,7 +102,7 @@ config PSCI_RESET bool "Use PSCI for reset and shutdown" default y select ARM_SMCCC if OF_CONTROL - depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \ + depends on !ARCH_APPLE && !ARCH_BCM283X && !ARCH_EXYNOS7 && \ !TARGET_LS2080AQDS && \ !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \ !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \ -- 2.34.1
[PATCH 3/3] misc: atsha204a: fix i2c address readout from DTS
This patch replaces use fdtdec_get_addr with recommended
fdtdec_get_addr_size_auto_parent.
Signed-off-by: Adrian Fiergolski
---
drivers/misc/atsha204a-i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index d264477927..1008b914c2 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -388,7 +388,7 @@ static int atsha204a_of_to_plat(struct udevice *dev)
fdt_addr_t *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
dev_of_offset(dev), "reg", 0, NULL, false);
if (addr == FDT_ADDR_T_NONE) {
debug("Can't get ATSHA204A I2C base address\n");
return -ENXIO;
--
2.34.1
[PATCH 2/3] misc: atsha204a: add delay after sending the message
Once request is sent, and before receiving a response, the delay is required.
This patch fixes missing delay for before first response try.
Signed-off-by: Adrian Fiergolski
---
drivers/misc/atsha204a-i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index 9d069fb33c..d264477927 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -280,6 +280,7 @@ static int atsha204a_transaction(struct udevice *dev,
struct atsha204a_req *req,
}
do {
+ udelay(ATSHA204A_EXECTIME);
res = atsha204a_recv_resp(dev, resp);
if (!res || res == -EMSGSIZE || res == -EBADMSG)
break;
@@ -287,7 +288,6 @@ static int atsha204a_transaction(struct udevice *dev,
struct atsha204a_req *req,
debug("ATSHA204A transaction polling for response "
"(timeout = %d)\n", timeout);
- udelay(ATSHA204A_EXECTIME);
timeout -= ATSHA204A_EXECTIME;
} while (timeout > 0);
--
2.34.1
[PATCH 1/3] misc: atsha204a: return timeout from wakeup function
If the maximum number of wake-up attempts is exceeded, return -ETIMEDOUT.
Signed-off-by: Adrian Fiergolski
---
drivers/misc/atsha204a-i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index 715dabb279..9d069fb33c 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -240,10 +240,10 @@ int atsha204a_wakeup(struct udevice *dev)
}
debug("success\n");
- break;
+ return 0;
}
- return 0;
+ return -ETIMEDOUT;
}
int atsha204a_idle(struct udevice *dev)
--
2.34.1
[PATCH 0/3] misc: atsha204a: bug fixes
Series of patches fixing atsha204a driver. Partially inspired by Enclustra's repo [1]. [1] https://github.com/enclustra-bsp/xilinx-uboot Adrian Fiergolski (3): misc: atsha204a: return timeout from wakeup function misc: atsha204a: add delay after sending the message misc: atsha204a: fix i2c address readout from DTS drivers/misc/atsha204a-i2c.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.34.1
[PATCH u-boot-marvell 14/16] tools: kwbimage/kwboot: Check ext field for non-zero value
Despite the official specification, BootROM does not look at the lowest bit
of ext field but rather checks if ext field is non-zero.
Moreover original Marvell doimage tool puts into the mhdr->ext field the
number of extended headers, so basically it sets ext filed to non-zero
value if some extended header is present.
Fix U-Boot dumpimage and kwboot tools to parse correctly also kwbimage
files created by Marvell doimage tool, in the same way as the BootROM is
doing it when booting these images.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 2 +-
tools/kwbimage.h | 6 +++---
tools/kwboot.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 2a0216a537ba..08b0332f5979 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1899,7 +1899,7 @@ static int kwbimage_verify_header(unsigned char *ptr, int
image_size,
if (kwbimage_version(ptr) == 0) {
struct main_hdr_v0 *mhdr = (struct main_hdr_v0 *)ptr;
- if (mhdr->ext & 0x1) {
+ if (mhdr->ext) {
struct ext_hdr_v0 *ext_hdr = (void *)(mhdr + 1);
csum = image_checksum8(ext_hdr, sizeof(*ext_hdr) - 1);
diff --git a/tools/kwbimage.h b/tools/kwbimage.h
index c000cba4b8d1..9ebc7d72d363 100644
--- a/tools/kwbimage.h
+++ b/tools/kwbimage.h
@@ -208,7 +208,7 @@ static inline size_t kwbheader_size(const void *header)
const struct main_hdr_v0 *hdr = header;
return sizeof(*hdr) +
- (hdr->ext & 0x1) ? sizeof(struct ext_hdr_v0) : 0;
+ hdr->ext ? sizeof(struct ext_hdr_v0) : 0;
} else {
const struct main_hdr_v1 *hdr = header;
@@ -252,7 +252,7 @@ static inline struct opt_hdr_v1 *opt_hdr_v1_first(void
*img) {
return NULL;
mhdr = img;
- if (mhdr->ext & 0x1)
+ if (mhdr->ext)
return (struct opt_hdr_v1 *)(mhdr + 1);
else
return NULL;
@@ -272,7 +272,7 @@ static inline struct opt_hdr_v1 *_opt_hdr_v1_next(struct
opt_hdr_v1 *cur)
static inline struct opt_hdr_v1 *opt_hdr_v1_next(struct opt_hdr_v1 *cur)
{
- if (*opt_hdr_v1_ext(cur) & 0x1)
+ if (*opt_hdr_v1_ext(cur))
return _opt_hdr_v1_next(cur);
else
return NULL;
diff --git a/tools/kwboot.c b/tools/kwboot.c
index d22e6ea96a5c..c3d8ab654417 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -1398,7 +1398,7 @@ kwboot_add_bin_ohdr_v1(void *img, size_t *size, uint32_t
binsz)
uint32_t ohdrsz;
uint8_t *prev_ext;
- if (hdr->ext & 0x1) {
+ if (hdr->ext) {
for_each_opt_hdr_v1 (ohdr, img)
if (opt_hdr_v1_next(ohdr) == NULL)
break;
@@ -1422,7 +1422,7 @@ kwboot_add_bin_ohdr_v1(void *img, size_t *size, uint32_t
binsz)
ohdrsz = sizeof(*ohdr) + 4 + 4 * num_args + binsz + 4;
kwboot_img_grow_hdr(hdr, size, ohdrsz);
- *prev_ext |= 1;
+ *prev_ext = 1;
ohdr->headertype = OPT_HDR_V1_BINARY_TYPE;
ohdr->headersz_msb = ohdrsz >> 16;
--
2.20.1
[PATCH u-boot-marvell 12/16] tools: kwbimage: Dump kwbimage config file on '-p -1' option
To regenerate kwbimage from existing image, it is needed to have kwbimage
config file. Add a new option to generate kwbimage config file from
existing kwbimage when '-p 1' option is given.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 175 +++
1 file changed, 175 insertions(+)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 094ebb1049c3..2a0216a537ba 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -209,6 +209,17 @@ static int image_boot_mode_id(const char *boot_mode_name)
return -1;
}
+static const char *image_nand_ecc_mode_name(unsigned int id)
+{
+ int i;
+
+ for (i = 0; nand_ecc_modes[i].name; i++)
+ if (nand_ecc_modes[i].id == id)
+ return nand_ecc_modes[i].name;
+
+ return NULL;
+}
+
static int image_nand_ecc_mode_id(const char *nand_ecc_mode_name)
{
int i;
@@ -343,6 +354,29 @@ static uint32_t image_checksum32(void *start, uint32_t len)
return csum;
}
+static unsigned int options_to_baudrate(uint8_t options)
+{
+ switch (options & 0x7) {
+ case MAIN_HDR_V1_OPT_BAUD_2400:
+ return 2400;
+ case MAIN_HDR_V1_OPT_BAUD_4800:
+ return 4800;
+ case MAIN_HDR_V1_OPT_BAUD_9600:
+ return 9600;
+ case MAIN_HDR_V1_OPT_BAUD_19200:
+ return 19200;
+ case MAIN_HDR_V1_OPT_BAUD_38400:
+ return 38400;
+ case MAIN_HDR_V1_OPT_BAUD_57600:
+ return 57600;
+ case MAIN_HDR_V1_OPT_BAUD_115200:
+ return 115200;
+ case MAIN_HDR_V1_OPT_BAUD_DEFAULT:
+ default:
+ return 0;
+ }
+}
+
static uint8_t baudrate_to_option(unsigned int baudrate)
{
switch (baudrate) {
@@ -2034,6 +2068,143 @@ static int kwbimage_generate(struct image_tool_params
*params,
return 4 + (4 - s.st_size % 4) % 4;
}
+static int kwbimage_generate_config(void *ptr, struct image_tool_params
*params)
+{
+ struct main_hdr_v0 *mhdr0 = (struct main_hdr_v0 *)ptr;
+ struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
+ size_t header_size = kwbheader_size(ptr);
+ struct register_set_hdr_v1 *regset_hdr;
+ struct ext_hdr_v0_reg *regdata;
+ struct ext_hdr_v0 *ehdr0;
+ struct opt_hdr_v1 *ohdr;
+ int cur_idx;
+ int version;
+ FILE *f;
+ int i;
+
+ f = fopen(params->outfile, "w");
+ if (!f) {
+ fprintf(stderr, "Can't open \"%s\": %s\n", params->outfile,
strerror(errno));
+ return -1;
+ }
+
+ version = kwbimage_version(ptr);
+
+ if (version != 0)
+ fprintf(f, "VERSION %d\n", version);
+
+ fprintf(f, "BOOT_FROM %s\n", image_boot_mode_name(mhdr->blockid) ?:
"");
+
+ if (version == 0 && mhdr->blockid == IBR_HDR_NAND_ID)
+ fprintf(f, "NAND_ECC_MODE %s\n",
image_nand_ecc_mode_name(mhdr0->nandeccmode));
+
+ if (mhdr->blockid == IBR_HDR_NAND_ID)
+ fprintf(f, "NAND_PAGE_SIZE 0x%x\n",
(unsigned)mhdr->nandpagesize);
+
+ if (version != 0 && mhdr->blockid == IBR_HDR_NAND_ID) {
+ fprintf(f, "NAND_BLKSZ 0x%x\n", (unsigned)mhdr->nandblocksize);
+ fprintf(f, "NAND_BADBLK_LOCATION 0x%x\n",
(unsigned)mhdr->nandbadblklocation);
+ }
+
+ if (version == 0 && mhdr->blockid == IBR_HDR_SATA_ID)
+ fprintf(f, "SATA_PIO_MODE %u\n", (unsigned)mhdr0->satapiomode);
+
+ /*
+* Addresses and sizes which are specified by mkimage command line
+* arguments and not in kwbimage config file
+*/
+
+ if (version != 0)
+ fprintf(f, "#HEADER_SIZE 0x%x\n",
+ ((unsigned)mhdr->headersz_msb << 8) |
le16_to_cpu(mhdr->headersz_lsb));
+
+ fprintf(f, "#SRC_ADDRESS 0x%x\n", le32_to_cpu(mhdr->srcaddr));
+ fprintf(f, "#BLOCK_SIZE 0x%x\n", le32_to_cpu(mhdr->blocksize));
+ fprintf(f, "#DEST_ADDRESS 0x%08x\n", le32_to_cpu(mhdr->destaddr));
+ fprintf(f, "#EXEC_ADDRESS 0x%08x\n", le32_to_cpu(mhdr->execaddr));
+
+ if (version != 0) {
+ if (options_to_baudrate(mhdr->options))
+ fprintf(f, "BAUDRATE %u\n",
options_to_baudrate(mhdr->options));
+ if (options_to_baudrate(mhdr->options) ||
+ ((mhdr->options >> 3) & 0x3) || ((mhdr->options >> 5) &
0x7)) {
+ fprintf(f, "UART_PORT %u\n", (unsigned)((mhdr->options
>> 3) & 0x3));
+ fprintf(f, "UART_MPP 0x%x\n", (unsigned)((mhdr->options
>> 5) & 0x7));
+ }
+ if (mhdr->flags & 0x1)
+ fprintf(f, "DEBUG 1\n");
+ }
+
+ cur_idx = 1;
+ for_each_opt_hdr_v1(ohdr, ptr) {
+ if (ohdr->headertype == OPT_HDR_V1_SECURE_TYPE) {
+ fprintf(f, "#SECURE_HEADER\n");
+
[PATCH u-boot-marvell 15/16] tools: kwbimage: Extract main data image without -p arg for dumpimage
When there is no -p argument for dumpimage tool specified, extract the main
data image from kwbimage file. This makes dumpimage consistent with other
image formats.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 67 +---
1 file changed, 40 insertions(+), 27 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 08b0332f5979..3feab40c3fe1 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -2211,7 +2211,7 @@ static int kwbimage_extract_subimage(void *ptr, struct
image_tool_params *params
size_t header_size = kwbheader_size(ptr);
struct opt_hdr_v1 *ohdr;
int idx = params->pflag;
- int cur_idx = 0;
+ int cur_idx;
uint32_t offset;
ulong image;
ulong size;
@@ -2220,41 +2220,54 @@ static int kwbimage_extract_subimage(void *ptr, struct
image_tool_params *params
if (idx == -1)
return kwbimage_generate_config(ptr, params);
- for_each_opt_hdr_v1 (ohdr, ptr) {
- if (ohdr->headertype != OPT_HDR_V1_BINARY_TYPE)
- continue;
+ image = 0;
+ size = 0;
+
+ if (idx == 0) {
+ /* Extract data image when -p is not specified or when '-p 0'
is specified */
+ offset = le32_to_cpu(mhdr->srcaddr);
- if (idx == cur_idx) {
- image = (ulong)&ohdr->data[4 + 4 * ohdr->data[0]];
- size = opt_hdr_v1_size(ohdr) - 12 - 4 * ohdr->data[0];
- goto extract;
+ if (mhdr->blockid == IBR_HDR_SATA_ID) {
+ offset -= 1;
+ offset *= 512;
}
- ++cur_idx;
- }
+ if (mhdr->blockid == IBR_HDR_SDIO_ID)
+ offset *= 512;
- if (idx != cur_idx) {
- printf("Image %d is not present\n", idx);
- return -1;
- }
-
- offset = le32_to_cpu(mhdr->srcaddr);
+ if (mhdr->blockid == IBR_HDR_PEX_ID && offset == 0x)
+ offset = header_size;
- if (mhdr->blockid == IBR_HDR_SATA_ID) {
- offset -= 1;
- offset *= 512;
- }
+ image = (ulong)((uint8_t *)ptr + offset);
+ size = le32_to_cpu(mhdr->blocksize) - 4;
+ } else {
+ /* Extract N-th binary header executabe image when other '-p N'
is specified */
+ cur_idx = 1;
+ for_each_opt_hdr_v1(ohdr, ptr) {
+ if (ohdr->headertype != OPT_HDR_V1_BINARY_TYPE)
+ continue;
- if (mhdr->blockid == IBR_HDR_SDIO_ID)
- offset *= 512;
+ if (idx == cur_idx) {
+ image = (ulong)&ohdr->data[4 + 4 *
ohdr->data[0]];
+ size = opt_hdr_v1_size(ohdr) - 12 - 4 *
ohdr->data[0];
+ break;
+ }
- if (mhdr->blockid == IBR_HDR_PEX_ID && offset == 0x)
- offset = header_size;
+ ++cur_idx;
+ }
- image = (ulong)((uint8_t *)ptr + offset);
- size = le32_to_cpu(mhdr->blocksize) - 4;
+ if (!image) {
+ fprintf(stderr, "Argument -p %d is invalid\n", idx);
+ fprintf(stderr, "Available subimages:\n");
+ fprintf(stderr, " -p -1 - kwbimage config file\n");
+ fprintf(stderr, " -p 0 - data image\n");
+ if (cur_idx - 1 > 0)
+ fprintf(stderr, " -p N - Nth binary header
image (totally: %d)\n",
+ cur_idx - 1);
+ return -1;
+ }
+ }
-extract:
return imagetool_save_subimage(params->outfile, image, size);
}
--
2.20.1
[PATCH u-boot-marvell 16/16] tools: kwbimage: Fix mkimage/dumpimage -l argument
Do not check for kwbimage configuration file when just showing information
about existing kwbimage file.
The check for kwbimage configuration file is required only when creating
kwbimage, not when showing information about image or when extracting data
from image.
With this change, it is possible to call mkimage -l and dumpimage -l also
for existing kwbimage file.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 3feab40c3fe1..4a3daf2d7cb0 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -2276,7 +2276,8 @@ static int kwbimage_extract_subimage(void *ptr, struct
image_tool_params *params
*/
static int kwbimage_check_params(struct image_tool_params *params)
{
- if (!params->iflag && (!params->imagename ||
!strlen(params->imagename))) {
+ if (!params->lflag && !params->iflag &&
+ (!params->imagename || !strlen(params->imagename))) {
char *msg = "Configuration file for kwbimage creation omitted";
fprintf(stderr, "Error:%s - %s\n", params->cmdname, msg);
--
2.20.1
[PATCH u-boot-marvell 13/16] tools: kwbimage: Do not cast const pointers to non-const pointers
Avoid casting const to non-const.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/kwbimage.h b/tools/kwbimage.h
index 8d37357e5abd..c000cba4b8d1 100644
--- a/tools/kwbimage.h
+++ b/tools/kwbimage.h
@@ -235,11 +235,11 @@ static inline int opt_hdr_v1_valid_size(const struct
opt_hdr_v1 *ohdr,
{
uint32_t ohdr_size;
- if ((void *)(ohdr + 1) > mhdr_end)
+ if ((const void *)(ohdr + 1) > mhdr_end)
return 0;
ohdr_size = opt_hdr_v1_size(ohdr);
- if (ohdr_size < 8 || (void *)((uint8_t *)ohdr + ohdr_size) > mhdr_end)
+ if (ohdr_size < 8 || (const void *)((const uint8_t *)ohdr + ohdr_size)
> mhdr_end)
return 0;
return 1;
--
2.20.1
[PATCH u-boot-marvell 06/16] tools: kwbimage: Add support for specifying LOAD_ADDRESS for BINARY command
ARM executable code included in kwbimage binary header, which is not
position independent, needs to be loaded and executed by BootROM at the
correct fixed address.
Armada BootROMs load kwbimage header (in which the executable code is also
stored) at fixed address 0x4000, which seems to be mapped to CESA SRAM.
Thus the only way to specify load and execute address of this executable
code in binary kwbimage header is by filling dummy arguments into the
binary header, using the same mechanism we already have for achieving
128-bit boundary alignment on A370 and AXP SoCs.
Extend kwbimage config file parser to allow to specify load address as
part of BINARY command with syntax:
BINARY path_to_binary arg1 arg2 ... argN LOAD_ADDRESS address
If the specified load address is invalid or cannot be used, mkimage will
throw fatal error and exit. This will prevent generating kwbimage with
invalid load address for non-position independent binary code.
If no load address is specified, kwbimage will not fill any the dummy
arguments, thus it will behave the same as before this change.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 92 +++-
1 file changed, 76 insertions(+), 16 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index f298883b2cb0..c21ed7b23fcf 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -153,6 +153,7 @@ struct image_cfg_element {
unsigned int bootfrom;
struct {
const char *file;
+ unsigned int loadaddr;
unsigned int args[BINARY_MAX_ARGS];
unsigned int nargs;
} binary;
@@ -991,10 +992,12 @@ static void *image_create_v0(size_t *imagesz, struct
image_tool_params *params,
static size_t image_headersz_v1(int *hasext)
{
- struct image_cfg_element *binarye, *e;
+ struct image_cfg_element *e;
unsigned int count;
size_t headersz;
+ struct stat s;
int cfgi;
+ int ret;
/*
* Calculate the size of the header and the size of the
@@ -1020,19 +1023,11 @@ static size_t image_headersz_v1(int *hasext)
headersz += sizeof(struct register_set_hdr_v1) + 8 *
count + 4;
count = 0;
}
- }
- if (count > 0)
- headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
- for (cfgi = 0; cfgi < cfgn; cfgi++) {
- int ret;
- struct stat s;
-
- binarye = &image_cfg[cfgi];
- if (binarye->type != IMAGE_CFG_BINARY)
+ if (e->type != IMAGE_CFG_BINARY)
continue;
- ret = stat(binarye->binary.file, &s);
+ ret = stat(e->binary.file, &s);
if (ret < 0) {
char cwd[PATH_MAX];
char *dir = cwd;
@@ -1047,18 +1042,48 @@ static size_t image_headersz_v1(int *hasext)
"Didn't find the file '%s' in '%s' which is
mandatory to generate the image\n"
"This file generally contains the DDR3 training
code, and should be extracted from an existing bootable\n"
"image for your board. Use 'dumpimage -T
kwbimage -p 0' to extract it from an existing image.\n",
- binarye->binary.file, dir);
+ e->binary.file, dir);
return 0;
}
headersz += sizeof(struct opt_hdr_v1) + sizeof(uint32_t) +
- (binarye->binary.nargs) * sizeof(uint32_t);
- headersz = ALIGN(headersz, 16);
+ (e->binary.nargs) * sizeof(uint32_t);
+
+ if (e->binary.loadaddr) {
+ /*
+* BootROM loads kwbimage header (in which the
+* executable code is also stored) to address
+* 0x4000. Thus there is restriction for the
+* load address of the N-th BINARY image.
+*/
+ unsigned int low_addr, high_addr;
+
+ low_addr = 0x4000 + headersz;
+ high_addr = low_addr +
+ (BINARY_MAX_ARGS - e->binary.nargs) *
sizeof(uint32_t);
+
+ if (e->binary.loadaddr % 4 || e->binary.loadaddr <
low_addr ||
+ e->binary.loadaddr > high_addr) {
+ fprintf(stderr,
+ "Invalid LOAD_ADDRESS 0x%08x for BINARY
%s with %d args.\n"
+ "Address must be 4-byte aligned and in
range 0x%08x-0x%08x\n.",
+ e->binary.loadaddr, e->binary.file,
+
[PATCH u-boot-marvell 11/16] tools: kwbimage: Show binary image address in mkimage -l, in addition to size
For debugging purposes it is good to know where the binary image would be
loaded and also it is needed to know if printed size is image size or the
size of header together with image.
Make it unambiguous by showoing that printed size is not the size of the
whole header, but only the size of executable code, and print also the
load/execute address of this binary image.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 4b3b40ce24fb..094ebb1049c3 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1823,9 +1823,12 @@ static void kwbimage_print_header(const void *ptr)
for_each_opt_hdr_v1 (ohdr, mhdr) {
if (ohdr->headertype == OPT_HDR_V1_BINARY_TYPE) {
- printf("BIN Hdr Size: ");
+ printf("BIN Img Size: ");
genimg_print_size(opt_hdr_v1_size(ohdr) - 12 -
4 * ohdr->data[0]);
+ printf("BIN Img Addr: %08x\n", 0x4000 +
+ (unsigned)((uint8_t *)ohdr - (uint8_t *)mhdr) +
+ 8 + 4 * ohdr->data[0]);
}
}
--
2.20.1
[PATCH u-boot-marvell 08/16] arm: mvebu: Correctly set LOAD_ADDRESS for U-Boot SPL binary in kwbimage
U-Boot SPL for mvebu platform is not compiled as position independent.
Therefore it is required to instruct BootROM to load U-Boot SPL at the
correct address. Loading of kwbimage binary code at specific address can be
now achieved by the new LOAD_ADDRESS token as part of BINARY command in
kwbimage config file.
Update mvebu Makefile to put value of $(CONFIG_SPL_TEXT_BASE) into
LOAD_ADDRESS token when generating kwbimage.cfg from kwbimage.cfg.in.
It is required to update regex for sed to find replacement tokens at any
position on a line in kwbimage config file and not only at the beginning of
the line. This is because LOAD_ADDRESS is specified at the end of line
containing the BINARY command.
It looks like all Armada boards set CONFIG_SPL_TEXT_BASE to value
0x4030. Why this value? It is because main kwbimage header is at
address 0x4000 and it is 32 bytes long. After the main header there is
the binary header, which consist of 1 byte for type, 3 bytes for size, 1
byte for number of arguments, 3 reserved bytes and then 4 bytes for each
argument. After these arguments comes the executable code.
So arguments start at address 0x4028. Before commit e6571f38c943 ("arm:
mvebu: Remove dummy BIN header arguments for SPL binary") there were two
(dummy) arguments, which resulted in load address of 0x4030, always.
After that commit (which removed dummy arguments), load address stayed same
due to the 128-bit alignment done by mkimage.
This patch now reflects the dependency between $(CONFIG_SPL_TEXT_BASE),
load address and dummy kwbimage arguments, and allows the user to adjust
$(CONFIG_SPL_TEXT_BASE) config option to some other value.
For unsupported values, when mkimage/kwbimage cannot set chosen load address
as specified by $(CONFIG_SPL_TEXT_BASE), the build process now fails,
instead of silently generating non-working kwbimage.
Removal of this alignment between $(CONFIG_SPL_TEXT_BASE) and LOAD_ADDRESS
can only be done by compiling U-Boot SPL as position independent. But this
currently is not possible for 32-bit ARM version of U-Boot SPL.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
arch/arm/mach-mvebu/Makefile| 5 -
arch/arm/mach-mvebu/kwbimage.cfg.in | 4 ++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index acbaa6449d3d..0fc638086ee5 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -30,6 +30,9 @@ obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
extra-y += kwbimage.cfg
+KWB_REPLACE += LOAD_ADDRESS
+KWB_CFG_LOAD_ADDRESS = $(CONFIG_SPL_TEXT_BASE)
+
KWB_REPLACE += BOOT_FROM
ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI),)
KWB_CFG_BOOT_FROM=spi
@@ -59,7 +62,7 @@ KWB_CFG_SEC_FUSE_DUMP = a38x
endif
quiet_cmd_kwbcfg = KWBCFG $@
-cmd_kwbcfg = sed -ne '$(foreach V,$(KWB_REPLACE),s/^\#@$(V)/$(V)
$(KWB_CFG_$(V))/;)p' \
+cmd_kwbcfg = sed -ne '$(foreach V,$(KWB_REPLACE),s/\#@$(V)/$(V)
$(KWB_CFG_$(V))/;)p' \
<$< >$(dir $@)$(@F)
$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
diff --git a/arch/arm/mach-mvebu/kwbimage.cfg.in
b/arch/arm/mach-mvebu/kwbimage.cfg.in
index 049d23c6ef08..2791c21617b3 100644
--- a/arch/arm/mach-mvebu/kwbimage.cfg.in
+++ b/arch/arm/mach-mvebu/kwbimage.cfg.in
@@ -8,5 +8,5 @@ VERSION 1
# Boot Media configurations
#@BOOT_FROM
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin
+# Include U-Boot SPL with DDR3 training code into Binary Header
+BINARY spl/u-boot-spl.bin #@LOAD_ADDRESS
--
2.20.1
[PATCH u-boot-marvell 09/16] arm: mvebu: Enable BootROM output on A38x
BootROMs on pre-A38x SoCs enabled its output on UART by default, but A38x' BootROM has its output on UART disabled by default. To enable BootROM output on A38x SoC, it is required to set DEBUG flag (which only enables BootROM output and nothing more) in kwbimage. For UART images this DEBUG flag is ignored by BootROM. Enable kwbimage DEBUG flag for all A38x boards. With this change BootROM prints the following (success) information on UART before booting U-Boot kwbimage: BootROM - 1.73 Booting from SPI flash Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- arch/arm/mach-mvebu/Makefile| 7 +++ arch/arm/mach-mvebu/kwbimage.cfg.in | 3 +++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 0fc638086ee5..4e15101a40cf 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -61,6 +61,13 @@ KWB_REPLACE += SEC_FUSE_DUMP KWB_CFG_SEC_FUSE_DUMP = a38x endif +ifdef CONFIG_ARMADA_38X +# BootROM output is by default enabled on pre-A38x and disabled on A38x +# DEBUG flag on A38x for non-UART boot source only enable BootROM output and nothing more +KWB_REPLACE += DEBUG +KWB_CFG_DEBUG = 1 +endif + quiet_cmd_kwbcfg = KWBCFG $@ cmd_kwbcfg = sed -ne '$(foreach V,$(KWB_REPLACE),s/\#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \ <$< >$(dir $@)$(@F) diff --git a/arch/arm/mach-mvebu/kwbimage.cfg.in b/arch/arm/mach-mvebu/kwbimage.cfg.in index 2791c21617b3..75f90766dda4 100644 --- a/arch/arm/mach-mvebu/kwbimage.cfg.in +++ b/arch/arm/mach-mvebu/kwbimage.cfg.in @@ -8,5 +8,8 @@ VERSION 1 # Boot Media configurations #@BOOT_FROM +# Enable BootROM output via DEBUG flag on SoCs which require it +#@DEBUG + # Include U-Boot SPL with DDR3 training code into Binary Header BINARY spl/u-boot-spl.bin #@LOAD_ADDRESS -- 2.20.1
[PATCH u-boot-marvell 10/16] tools: kwbimage: Add missing check for maximal value for DATA_DELAY
Data delay is stored as 8-bit number in kwbimage structure. Ensure the
given value is at most 255.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 4
1 file changed, 4 insertions(+)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 7759a5f94098..4b3b40ce24fb 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1610,6 +1610,10 @@ static int image_create_config_parse_oneline(char *line,
el->regdata_delay =
REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP;
else
el->regdata_delay =
REGISTER_SET_HDR_OPT_DELAY_MS(strtoul(value1, NULL, 10));
+ if (el->regdata_delay > 255) {
+ fprintf(stderr, "Maximal DATA_DELAY is 255\n");
+ return -1;
+ }
break;
case IMAGE_CFG_BAUDRATE:
el->baudrate = strtoul(value1, NULL, 10);
--
2.20.1
[PATCH u-boot-marvell 07/16] tools: kwbimage: Check the return value of image_headersz_v1()
Function image_headersz_v1() may return zero on fatal errors.
In this case the function already printed an error message.
Check the return value of image_headersz_v1() in kwbimage_generate(),
and exit on zero value with EXIT_FAILURE.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 4
1 file changed, 4 insertions(+)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index c21ed7b23fcf..7759a5f94098 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1984,6 +1984,10 @@ static int kwbimage_generate(struct image_tool_params
*params,
case 1:
alloc_len = image_headersz_v1(NULL);
+ if (!alloc_len) {
+ free(image_cfg);
+ exit(EXIT_FAILURE);
+ }
break;
default:
--
2.20.1
[PATCH u-boot-marvell 04/16] tools: kwbimage: Preserve order of BINARY, DATA and DATA_DELAY commands
Preserve the order of BINARY, DATA and DATA_DELAY commands as they appear
in the input file. They may depend on each other.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 58 +++-
1 file changed, 38 insertions(+), 20 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 6432551065ab..f298883b2cb0 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1015,7 +1015,8 @@ static size_t image_headersz_v1(int *hasext)
if (e->type == IMAGE_CFG_DATA)
count++;
- if (e->type == IMAGE_CFG_DATA_DELAY) {
+ if (e->type == IMAGE_CFG_DATA_DELAY ||
+ (e->type == IMAGE_CFG_BINARY && count > 0)) {
headersz += sizeof(struct register_set_hdr_v1) + 8 *
count + 4;
count = 0;
}
@@ -1287,6 +1288,7 @@ static void *image_create_v1(size_t *imagesz, struct
image_tool_params *params,
int hasext = 0;
uint8_t *next_ext = NULL;
int cfgi, datai;
+ uint8_t delay;
/*
* Calculate the size of the header and the size of the
@@ -1380,34 +1382,50 @@ static void *image_create_v1(size_t *imagesz, struct
image_tool_params *params,
for (cfgi = 0; cfgi < cfgn; cfgi++) {
e = &image_cfg[cfgi];
if (e->type != IMAGE_CFG_DATA &&
- e->type != IMAGE_CFG_DATA_DELAY)
+ e->type != IMAGE_CFG_DATA_DELAY &&
+ e->type != IMAGE_CFG_BINARY)
continue;
+
if (datai == 0)
register_set_hdr = (struct register_set_hdr_v1 *)cur;
- if (e->type == IMAGE_CFG_DATA_DELAY) {
+
+ /* If delay is not specified, use the smallest possible value.
*/
+ if (e->type == IMAGE_CFG_DATA_DELAY)
+ delay = e->regdata_delay;
+ else
+ delay = REGISTER_SET_HDR_OPT_DELAY_MS(0);
+
+ /*
+* DATA_DELAY command is the last entry in the register set
+* header and BINARY command inserts new binary header.
+* Therefore BINARY command requires to finish register set
+* header if some DATA command was specified. And DATA_DELAY
+* command automatically finish register set header even when
+* there was no DATA command.
+*/
+ if (e->type == IMAGE_CFG_DATA_DELAY ||
+ (e->type == IMAGE_CFG_BINARY && datai != 0))
finish_register_set_header_v1(&cur, &next_ext,
register_set_hdr,
- &datai, e->regdata_delay);
- continue;
+ &datai, delay);
+
+ if (e->type == IMAGE_CFG_DATA) {
+ register_set_hdr->data[datai].entry.address =
+ cpu_to_le32(e->regdata.raddr);
+ register_set_hdr->data[datai].entry.value =
+ cpu_to_le32(e->regdata.rdata);
+ datai++;
+ }
+
+ if (e->type == IMAGE_CFG_BINARY) {
+ if (add_binary_header_v1(&cur, &next_ext, e, main_hdr))
+ return NULL;
}
- register_set_hdr->data[datai].entry.address =
- cpu_to_le32(e->regdata.raddr);
- register_set_hdr->data[datai].entry.value =
- cpu_to_le32(e->regdata.rdata);
- datai++;
}
if (datai != 0) {
/* Set delay to the smallest possible value. */
+ delay = REGISTER_SET_HDR_OPT_DELAY_MS(0);
finish_register_set_header_v1(&cur, &next_ext, register_set_hdr,
- &datai,
REGISTER_SET_HDR_OPT_DELAY_MS(0));
- }
-
- for (cfgi = 0; cfgi < cfgn; cfgi++) {
- e = &image_cfg[cfgi];
- if (e->type != IMAGE_CFG_BINARY)
- continue;
-
- if (add_binary_header_v1(&cur, &next_ext, e, main_hdr))
- return NULL;
+ &datai, delay);
}
if (secure_hdr && add_secure_header_v1(params, ptr, payloadsz +
headersz,
--
2.20.1
[PATCH u-boot-marvell 02/16] tools: kwbimage: Deduplicate v1 regtype header finishing
Deduplicate code that finishes OPT_HDR_V1_REGISTER_TYPE header by
extracing it into separate function.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 41 ++---
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 9f852923dc61..9ac74cfbe514 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1247,6 +1247,22 @@ static int add_secure_header_v1(struct image_tool_params
*params, uint8_t *ptr,
return 0;
}
+static void finish_register_set_header_v1(uint8_t **cur, uint8_t **next_ext,
+ struct register_set_hdr_v1
*register_set_hdr,
+ int *datai, uint8_t delay)
+{
+ int size = sizeof(struct register_set_hdr_v1) + 8 * (*datai) + 4;
+
+ register_set_hdr->headertype = OPT_HDR_V1_REGISTER_TYPE;
+ register_set_hdr->headersz_lsb = cpu_to_le16(size & 0x);
+ register_set_hdr->headersz_msb = size >> 16;
+ register_set_hdr->data[*datai].last_entry.delay = delay;
+ *cur += size;
+ **next_ext = 1;
+ *next_ext = ®ister_set_hdr->data[*datai].last_entry.next;
+ *datai = 0;
+}
+
static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
uint8_t *ptr, int payloadsz)
{
@@ -1259,7 +1275,7 @@ static void *image_create_v1(size_t *imagesz, struct
image_tool_params *params,
uint8_t *image, *cur;
int hasext = 0;
uint8_t *next_ext = NULL;
- int cfgi, datai, size;
+ int cfgi, datai;
/*
* Calculate the size of the header and the size of the
@@ -1357,15 +1373,8 @@ static void *image_create_v1(size_t *imagesz, struct
image_tool_params *params,
e->type != IMAGE_CFG_DATA_DELAY)
continue;
if (e->type == IMAGE_CFG_DATA_DELAY) {
- size = sizeof(struct register_set_hdr_v1) + 8 * datai +
4;
- register_set_hdr->headertype = OPT_HDR_V1_REGISTER_TYPE;
- register_set_hdr->headersz_lsb = cpu_to_le16(size &
0x);
- register_set_hdr->headersz_msb = size >> 16;
- register_set_hdr->data[datai].last_entry.delay =
e->regdata_delay;
- cur += size;
- *next_ext = 1;
- next_ext =
®ister_set_hdr->data[datai].last_entry.next;
- datai = 0;
+ finish_register_set_header_v1(&cur, &next_ext,
register_set_hdr,
+ &datai, e->regdata_delay);
continue;
}
register_set_hdr->data[datai].entry.address =
@@ -1375,15 +1384,9 @@ static void *image_create_v1(size_t *imagesz, struct
image_tool_params *params,
datai++;
}
if (datai != 0) {
- size = sizeof(struct register_set_hdr_v1) + 8 * datai + 4;
- register_set_hdr->headertype = OPT_HDR_V1_REGISTER_TYPE;
- register_set_hdr->headersz_lsb = cpu_to_le16(size & 0x);
- register_set_hdr->headersz_msb = size >> 16;
- /* Set delay to the smallest possible value 1ms. */
- register_set_hdr->data[datai].last_entry.delay = 1;
- cur += size;
- *next_ext = 1;
- next_ext = ®ister_set_hdr->data[datai].last_entry.next;
+ /* Set delay to the smallest possible value. */
+ finish_register_set_header_v1(&cur, &next_ext, register_set_hdr,
+ &datai,
REGISTER_SET_HDR_OPT_DELAY_MS(0));
}
for (cfgi = 0; cfgi < cfgn; cfgi++) {
--
2.20.1
[PATCH u-boot-marvell 05/16] arm: mvebu: Generate kwbimage.cfg with $(call cmd, ...)
Usage of $(call cmd,...) is standard way to call other commands which generate things. It also has the advantage of printing build information in the form KWBCFG arch/arm/mach-mvebu/kwbimage.cfg if verbosity is disabled, and printing the build command otherwise. Note that the '#' character needs to be escaped in Makefile when used as value for make variable assignment. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- arch/arm/mach-mvebu/Makefile | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 7e9c206ed6b8..acbaa6449d3d 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -58,10 +58,13 @@ KWB_REPLACE += SEC_FUSE_DUMP KWB_CFG_SEC_FUSE_DUMP = a38x endif +quiet_cmd_kwbcfg = KWBCFG $@ +cmd_kwbcfg = sed -ne '$(foreach V,$(KWB_REPLACE),s/^\#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \ + <$< >$(dir $@)$(@F) + $(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ include/config/auto.conf - $(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \ - <$< >$(dir $@)$(@F) + $(call cmd,kwbcfg) endif # CONFIG_SPL_BUILD obj-y += gpio.o -- 2.20.1
[PATCH u-boot-marvell 03/16] tools: kwbimage: Fix generating image with multiple DATA_DELAY commands
Register set header consists of sequence of DATA commands followed by
exactly one DATA_DELAY command. Thus if we are generating image with
multiple DATA_DELAY commands, we need to create more register set headers.
Fix calculation of image size with multiple DATA_DELAY commands and
correctly set pointer to struct register_set_hdr_v1 when initializing new
register set header.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 9ac74cfbe514..6432551065ab 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -991,7 +991,7 @@ static void *image_create_v0(size_t *imagesz, struct
image_tool_params *params,
static size_t image_headersz_v1(int *hasext)
{
- struct image_cfg_element *binarye;
+ struct image_cfg_element *binarye, *e;
unsigned int count;
size_t headersz;
int cfgi;
@@ -1008,7 +1008,18 @@ static size_t image_headersz_v1(int *hasext)
*hasext = 1;
}
- count = image_count_options(IMAGE_CFG_DATA);
+ count = 0;
+ for (cfgi = 0; cfgi < cfgn; cfgi++) {
+ e = &image_cfg[cfgi];
+
+ if (e->type == IMAGE_CFG_DATA)
+ count++;
+
+ if (e->type == IMAGE_CFG_DATA_DELAY) {
+ headersz += sizeof(struct register_set_hdr_v1) + 8 *
count + 4;
+ count = 0;
+ }
+ }
if (count > 0)
headersz += sizeof(struct register_set_hdr_v1) + 8 * count + 4;
@@ -1366,12 +1377,13 @@ static void *image_create_v1(size_t *imagesz, struct
image_tool_params *params,
}
datai = 0;
- register_set_hdr = (struct register_set_hdr_v1 *)cur;
for (cfgi = 0; cfgi < cfgn; cfgi++) {
e = &image_cfg[cfgi];
if (e->type != IMAGE_CFG_DATA &&
e->type != IMAGE_CFG_DATA_DELAY)
continue;
+ if (datai == 0)
+ register_set_hdr = (struct register_set_hdr_v1 *)cur;
if (e->type == IMAGE_CFG_DATA_DELAY) {
finish_register_set_header_v1(&cur, &next_ext,
register_set_hdr,
&datai, e->regdata_delay);
--
2.20.1
[PATCH u-boot-marvell 01/16] tools: kwbimage: Mark all local functions as static
Mark all local functions as static.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
tools/kwbimage.c | 37 +++--
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 875f636c7a4f..9f852923dc61 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -197,7 +197,7 @@ static const char *image_boot_mode_name(unsigned int id)
return NULL;
}
-int image_boot_mode_id(const char *boot_mode_name)
+static int image_boot_mode_id(const char *boot_mode_name)
{
int i;
@@ -208,7 +208,7 @@ int image_boot_mode_id(const char *boot_mode_name)
return -1;
}
-int image_nand_ecc_mode_id(const char *nand_ecc_mode_name)
+static int image_nand_ecc_mode_id(const char *nand_ecc_mode_name)
{
int i;
@@ -600,7 +600,8 @@ static int kwb_export_pubkey(RSA *key, struct pubkey_der_v1
*dst, FILE *hashf,
return 0;
}
-int kwb_sign(RSA *key, void *data, int datasz, struct sig_v1 *sig, char
*signame)
+static int kwb_sign(RSA *key, void *data, int datasz, struct sig_v1 *sig,
+ char *signame)
{
EVP_PKEY *evp_key;
EVP_MD_CTX *ctx;
@@ -660,8 +661,8 @@ err_key:
return ret;
}
-int kwb_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig,
- char *signame)
+static int kwb_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig,
+ char *signame)
{
EVP_PKEY *evp_key;
EVP_MD_CTX *ctx;
@@ -720,8 +721,8 @@ err_key:
return ret;
}
-int kwb_sign_and_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig,
- char *signame)
+static int kwb_sign_and_verify(RSA *key, void *data, int datasz,
+ struct sig_v1 *sig, char *signame)
{
if (kwb_sign(key, data, datasz, sig, signame) < 0)
return -1;
@@ -733,7 +734,7 @@ int kwb_sign_and_verify(RSA *key, void *data, int datasz,
struct sig_v1 *sig,
}
-int kwb_dump_fuse_cmds_38x(FILE *out, struct secure_hdr_v1 *sec_hdr)
+static int kwb_dump_fuse_cmds_38x(FILE *out, struct secure_hdr_v1 *sec_hdr)
{
struct hash_v1 kak_pub_hash;
struct image_cfg_element *e;
@@ -1049,9 +1050,9 @@ static size_t image_headersz_v1(int *hasext)
return image_headersz_align(headersz, image_get_bootfrom());
}
-int add_binary_header_v1(uint8_t **cur, uint8_t **next_ext,
-struct image_cfg_element *binarye,
-struct main_hdr_v1 *main_hdr)
+static int add_binary_header_v1(uint8_t **cur, uint8_t **next_ext,
+ struct image_cfg_element *binarye,
+ struct main_hdr_v1 *main_hdr)
{
struct opt_hdr_v1 *hdr = (struct opt_hdr_v1 *)*cur;
uint32_t add_args;
@@ -1133,7 +1134,7 @@ err_close:
return -1;
}
-int export_pub_kak_hash(RSA *kak, struct secure_hdr_v1 *secure_hdr)
+static int export_pub_kak_hash(RSA *kak, struct secure_hdr_v1 *secure_hdr)
{
FILE *hashf;
int res;
@@ -1152,8 +1153,8 @@ int export_pub_kak_hash(RSA *kak, struct secure_hdr_v1
*secure_hdr)
return res < 0 ? 1 : 0;
}
-int kwb_sign_csk_with_kak(struct image_tool_params *params,
- struct secure_hdr_v1 *secure_hdr, RSA *csk)
+static int kwb_sign_csk_with_kak(struct image_tool_params *params,
+struct secure_hdr_v1 *secure_hdr, RSA *csk)
{
RSA *kak = NULL;
RSA *kak_pub = NULL;
@@ -1194,9 +1195,9 @@ int kwb_sign_csk_with_kak(struct image_tool_params
*params,
return 0;
}
-int add_secure_header_v1(struct image_tool_params *params, uint8_t *ptr,
-int payloadsz, size_t headersz, uint8_t *image,
-struct secure_hdr_v1 *secure_hdr)
+static int add_secure_header_v1(struct image_tool_params *params, uint8_t *ptr,
+ int payloadsz, size_t headersz, uint8_t *image,
+ struct secure_hdr_v1 *secure_hdr)
{
struct image_cfg_element *e_jtagdelay;
struct image_cfg_element *e_boxid;
@@ -1413,7 +1414,7 @@ static void *image_create_v1(size_t *imagesz, struct
image_tool_params *params,
return image;
}
-int recognize_keyword(char *keyword)
+static int recognize_keyword(char *keyword)
{
int kw_id;
--
2.20.1
[PATCH u-boot-marvell 00/16] tools: kwbimage: Load address fixes
This patch series fixes generating images in kwbimage format, main fix is setting correct load address of U-Boot SPL. Also it adds support for generating kwbimage config file from existing kwbimage file via dumpimage tool. Pali Rohár (16): tools: kwbimage: Mark all local functions as static tools: kwbimage: Deduplicate v1 regtype header finishing tools: kwbimage: Fix generating image with multiple DATA_DELAY commands tools: kwbimage: Preserve order of BINARY, DATA and DATA_DELAY commands arm: mvebu: Generate kwbimage.cfg with $(call cmd,...) tools: kwbimage: Add support for specifying LOAD_ADDRESS for BINARY command tools: kwbimage: Check the return value of image_headersz_v1() arm: mvebu: Correctly set LOAD_ADDRESS for U-Boot SPL binary in kwbimage arm: mvebu: Enable BootROM output on A38x tools: kwbimage: Add missing check for maximal value for DATA_DELAY tools: kwbimage: Show binary image address in mkimage -l, in addition to size tools: kwbimage: Dump kwbimage config file on '-p -1' option tools: kwbimage: Do not cast const pointers to non-const pointers tools: kwbimage/kwboot: Check ext field for non-zero value tools: kwbimage: Extract main data image without -p arg for dumpimage tools: kwbimage: Fix mkimage/dumpimage -l argument arch/arm/mach-mvebu/Makefile| 17 +- arch/arm/mach-mvebu/kwbimage.cfg.in | 7 +- tools/kwbimage.c| 494 ++-- tools/kwbimage.h| 10 +- tools/kwboot.c | 4 +- 5 files changed, 421 insertions(+), 111 deletions(-) -- 2.20.1
Re: [PATCH v2 2/2] doc: add Arm Juno board documentation
On Mon, Dec 20, 2021 at 06:12:04PM +, Andre Przywara wrote: > The Juno Arm development board is an open, vendor-neutral, Armv8-A > development platform. > Add documentation that briefly outlines the hardware, and describes > building and installation of U-Boot. > Reviewed-by: Sudeep Holla -- Regards, Sudeep
Re: [PATCH v2 1/2] doc: Add documentation for the Arm VExpress64 board configs
On Mon, Dec 20, 2021 at 06:12:03PM +, Andre Przywara wrote: > From: Peter Hoyes > > Create a new documentation section for Arm Ltd boards with a sub-page > for the FVP VExpress64 system. > Reviewed-by: Sudeep Holla -- Regards, Sudeep
Re: [PATCH 4/4] udoo_neo: Enable support for USB and storage
On Tue, Dec 21, 2021 at 9:33 AM Peter Robinson wrote: > > Enable support for USB and USB storage on the UDOO Neo. > > Signed-off-by: Peter Robinson Reviewed-by: Fabio Estevam
Re: [PATCH 3/4] udoo_neo: Fix ethernet
On Tue, Dec 21, 2021 at 9:32 AM Peter Robinson wrote: > > The ethernet has a RMII not RGMII, also needs DM_MDIO and finally > initialise it later in the process as it's not needed that early on > and not everything is ready so it locks up the device. > > Signed-off-by: Peter Robinson Reviewed-by: Fabio Estevam
Re: [PATCH 2/4] udoo_neo: Fixes for booting from the mSD card
On Tue, Dec 21, 2021 at 9:32 AM Peter Robinson wrote: > > This fixes booting from the mSD card from both SPL and when > using it for the OS booting. It also cleans up a few mmc > booting bits that are no longer needed. > > Signed-off-by: Peter Robinson Reviewed-by: Fabio Estevam
Re: [PATCH 1/4] udoo_neo: Call gpio_request()
On Tue, Dec 21, 2021 at 9:32 AM Peter Robinson wrote:
>
> Calling gpio_request() prior to its usage is now mandatory.
>
> This fixes the following GPIO errors:
> gpio@20a8000: set_dir_flags: error: gpio GPIO4_16 not reserved
> gpio@20a8000: set_dir_flags: error: gpio GPIO4_13 not reserved
> gpio@20a8000: set_dir_flags: error: gpio GPIO4_0 not reserved
> gpio@20a8000: get_value: error: gpio GPIO4_13 not reserved
> gpio@20a8000: get_value: error: gpio GPIO4_0 not reserved
> gpio@20a: set_dir_flags: error: gpio GPIO2_1 not reserved
> gpio@20a: set_value: error: gpio GPIO2_1 not reserved
>
> Fixes: 191840ae99 ("ARM: imx: udoo_neo: Enable OF_CONTROL and DM gpio/pin
> control")
> Signed-off-by: Peter Robinson
Reviewed-by: Fabio Estevam
extend environment with file
Hi, currently i use distroboot on my board which sets some environment-variables, some other (memory addresses) were set in my soc-specific header file (include/configs/rk3568_common.h). But distroboot is a bit too limited for my needs (no tftp, no script, ...), so imho i need to use the bootmenu way here, but for local kernel-bootup run distro_bootcmd. I want to add some more variables (e.g. for bootmenu) and for easier maintaining i used a txt-file for it and defined CONFIG_DEFAULT_ENV_FILE="uEnv_r2pro.txt" but this option seems to clear the previous environment from distroboot and soc header file...i have now only the vars from the file defined. i tried adding CONFIG_ENV_APPEND=y but i have still only the vars from the file. Is there a way to append (distrocmd + soc-header + uenv-file) instead of overwriting? regards Frank
Re: [PATCH 1/1] doc: remove duplicate page inclusion
On Tue, Dec 21, 2021 at 09:00:44AM +0100, Heinrich Schuchardt wrote: > doc/usage/index.rst in branch origin/next includes usage/environment twice. > Remove the duplicate entry. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] doc: remove duplicate page inclusion
On Tue, Dec 21, 2021 at 09:00:44AM +0100, Heinrich Schuchardt wrote: > doc/usage/index.rst in branch origin/next includes usage/environment twice. > Remove the duplicate entry. > > Signed-off-by: Heinrich Schuchardt > --- > Hello Tom, > > this seems to be merge error. We need this patch to build 'make htmldocs'. > Please, apply to origin/next without further pull request. I'm applying this note. Just for the record, CI is passing: https://source.denx.de/u-boot/u-boot/-/jobs/367582 and also passed before I pushed to next itself: https://source.denx.de/u-boot/u-boot/-/jobs/367539 -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/4] Convert CONFIG_TIMESTAMP to Kconfig
Hi Sean, On Sat, 18 Dec 2021 at 08:16, Sean Anderson wrote: > > On 12/18/21 10:08 AM, Simon Glass wrote: > > This converts the following to Kconfig: > > CONFIG_TIMESTAMP > > > > Signed-off-by: Simon Glass > > --- > > [...] > > > diff --git a/net/Kconfig b/net/Kconfig > > index 3d3329912da..1983506bb8e 100644 > > --- a/net/Kconfig > > +++ b/net/Kconfig > > @@ -109,6 +109,7 @@ config KEEP_SERVERADDR > > > > config UDP_CHECKSUM > > bool "Check the UDP checksum" > > + default y if SANDBOX > > help > > Enable this to verify the checksum on UDP packets. If the checksum > > is wrong then the packet is discussed and an error is shown, like > > Should this hunk be part of the previous patch? Yes, it should. I will fix it when I send another version. Regards, Simon
[PATCH 4/4] udoo_neo: Enable support for USB and storage
Enable support for USB and USB storage on the UDOO Neo. Signed-off-by: Peter Robinson --- configs/udoo_neo_defconfig | 7 +++ include/configs/udoo_neo.h | 1 + 2 files changed, 8 insertions(+) diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 2a37757100..ca08de1bd4 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_FS_EXT4=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y @@ -53,5 +54,11 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_ANATOP=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index e2b432e1c4..3a7cb050b1 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -50,6 +50,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ + func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -- 2.33.1
[PATCH 2/4] udoo_neo: Fixes for booting from the mSD card
This fixes booting from the mSD card from both SPL and when
using it for the OS booting. It also cleans up a few mmc
booting bits that are no longer needed.
Signed-off-by: Peter Robinson
---
arch/arm/dts/imx6sx-udoo-neo-u-boot.dtsi | 7 -
board/udoo/neo/neo.c | 40
configs/udoo_neo_defconfig | 1 +
include/configs/udoo_neo.h | 4 +--
4 files changed, 43 insertions(+), 9 deletions(-)
delete mode 100644 arch/arm/dts/imx6sx-udoo-neo-u-boot.dtsi
diff --git a/arch/arm/dts/imx6sx-udoo-neo-u-boot.dtsi
b/arch/arm/dts/imx6sx-udoo-neo-u-boot.dtsi
deleted file mode 100644
index daf2489cfd..00
--- a/arch/arm/dts/imx6sx-udoo-neo-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-/ {
- aliases {
- mmc0 = &usdhc2;
- };
-};
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 61195be744..8b0d13b1ca 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -19,6 +19,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -214,6 +216,19 @@ static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* CD pin */
+ MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* Power */
+ MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
static iomux_v3_cfg_t const phy_control_pads[] = {
/* 25MHz Ethernet PHY Clock */
MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
@@ -327,6 +342,31 @@ int board_early_init_f(void)
return 0;
}
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC2_BASE_ADDR},
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !gpio_get_value(USDHC2_CD_GPIO);
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr");
+ gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd");
+ gpio_direction_input(USDHC2_CD_GPIO);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
static char *board_string(void)
{
switch (get_board_value()) {
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index b2a3e9be4c..f01d2e22e9 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -35,6 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SYS_I2C_LEGACY=y
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index b06abc9286..e2b432e1c4 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h
@@ -29,7 +29,7 @@
"fdt_addr=0x8300\0" \
"fdt_addr_r=0x8300\0" \
"ip_dyn=yes\0" \
- "mmcdev=0\0" \
+ "mmcdev=1\0" \
"mmcrootfstype=ext4\0" \
"findfdt="\
"if test $board_name = BASIC; then " \
@@ -49,7 +49,7 @@
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
func(DHCP, dhcp, na)
#include
--
2.33.1
[PATCH 3/4] udoo_neo: Fix ethernet
The ethernet has a RMII not RGMII, also needs DM_MDIO and finally
initialise it later in the process as it's not needed that early on
and not everything is ready so it locks up the device.
Signed-off-by: Peter Robinson
---
board/udoo/neo/neo.c | 3 ++-
configs/udoo_neo_defconfig | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 8b0d13b1ca..62f81fff68 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -303,6 +303,8 @@ int board_init(void)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
+ setup_fec();
+
return 0;
}
@@ -337,7 +339,6 @@ static int get_board_value(void)
int board_early_init_f(void)
{
setup_iomux_uart();
- setup_fec();
return 0;
}
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index f01d2e22e9..2a37757100 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -46,8 +46,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
--
2.33.1
[PATCH 1/4] udoo_neo: Call gpio_request()
Calling gpio_request() prior to its usage is now mandatory.
This fixes the following GPIO errors:
gpio@20a8000: set_dir_flags: error: gpio GPIO4_16 not reserved
gpio@20a8000: set_dir_flags: error: gpio GPIO4_13 not reserved
gpio@20a8000: set_dir_flags: error: gpio GPIO4_0 not reserved
gpio@20a8000: get_value: error: gpio GPIO4_13 not reserved
gpio@20a8000: get_value: error: gpio GPIO4_0 not reserved
gpio@20a: set_dir_flags: error: gpio GPIO2_1 not reserved
gpio@20a: set_value: error: gpio GPIO2_1 not reserved
Fixes: 191840ae99 ("ARM: imx: udoo_neo: Enable OF_CONTROL and DM gpio/pin
control")
Signed-off-by: Peter Robinson
---
board/udoo/neo/neo.c | 4
1 file changed, 4 insertions(+)
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index ce005d31cc..61195be744 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -249,6 +249,7 @@ static int setup_fec(void)
ARRAY_SIZE(phy_control_pads));
/* Reset PHY */
+ gpio_request(IMX_GPIO_NR(2, 1), "enet_rst");
gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
udelay(1);
gpio_set_value(IMX_GPIO_NR(2, 1), 1);
@@ -280,6 +281,7 @@ int board_init(void)
ARRAY_SIZE(peri_3v3_pads));
/* Active high for ncp692 */
+ gpio_request(IMX_GPIO_NR(4, 16), "ncp692");
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
#ifdef CONFIG_SYS_I2C_MXC
@@ -296,6 +298,8 @@ static int get_board_value(void)
imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
ARRAY_SIZE(board_recognition_pads));
+ gpio_request(IMX_GPIO_NR(4, 13), "r184");
+ gpio_request(IMX_GPIO_NR(4, 0), "r185");
gpio_direction_input(IMX_GPIO_NR(4, 13));
gpio_direction_input(IMX_GPIO_NR(4, 0));
--
2.33.1
[PATCH u-boot-marvell 9/9] arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c
As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.
Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.
Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.
Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.
This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.
Signed-off-by: Pali Rohár
---
arch/arm/dts/armada-375.dtsi | 2 +
arch/arm/dts/armada-380.dtsi | 3 +
arch/arm/dts/armada-385.dtsi | 4 ++
arch/arm/dts/armada-xp-98dx3236.dtsi | 1 +
arch/arm/dts/armada-xp-mv78230.dtsi | 5 ++
arch/arm/dts/armada-xp-mv78260.dtsi | 9 +++
arch/arm/dts/armada-xp-mv78460.dtsi | 10
arch/arm/dts/armada-xp-synology-ds414.dts | 1 +
arch/arm/dts/armada-xp-theadorable.dts| 1 +
arch/arm/mach-mvebu/serdes/a38x/Makefile | 1 -
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c| 57 ---
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h| 27 -
.../serdes/a38x/high_speed_env_spec.c | 19 ---
drivers/pci/Kconfig | 1 +
drivers/pci/pci_mvebu.c | 43 +-
15 files changed, 79 insertions(+), 105 deletions(-)
delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
diff --git a/arch/arm/dts/armada-375.dtsi b/arch/arm/dts/armada-375.dtsi
index fdf2d6dbdc84..ff0ad7a9c7fd 100644
--- a/arch/arm/dts/armada-375.dtsi
+++ b/arch/arm/dts/armada-375.dtsi
@@ -617,6 +617,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -635,6 +636,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
diff --git a/arch/arm/dts/armada-380.dtsi b/arch/arm/dts/armada-380.dtsi
index cff1269f3fbf..f3d7f4b27ddb 100644
--- a/arch/arm/dts/armada-380.dtsi
+++ b/arch/arm/dts/armada-380.dtsi
@@ -73,6 +73,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -92,6 +93,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -111,6 +113,7 @@
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
+ resets = <&systemc 0 2>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/armada-385.dtsi b/arch/arm/dts/armada-385.dtsi
index f0022d10c715..581a7d9beac3 100644
--- a/arch/arm/dts/armada-385.dtsi
+++ b/arch/arm/dts/armada-385.dtsi
@@ -78,6 +78,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -97,6 +98,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 1>;
status = "disabled";
[PATCH u-boot-marvell 4/9] pci: pci_mvebu: Inline mvebu_pcie_port_parse_dt() function
Function mvebu_pcie_port_parse_dt() is called only from
mvebu_pcie_of_to_plat() function. Both these function parse DT properties
required to setup mvebu pcie. So inline mvebu_pcie_port_parse_dt() function
into mvebu_pcie_of_to_plat() to have all code related to parsing DT
properties at one place.
Signed-off-by: Pali Rohár
---
drivers/pci/pci_mvebu.c | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index eaaa6cbe326d..c47551807bc2 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -488,22 +488,6 @@ static int mvebu_pcie_probe(struct udevice *dev)
return 0;
}
-static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
-{
- const u32 *addr;
- int len;
-
- addr = ofnode_get_property(node, "assigned-addresses", &len);
- if (!addr) {
- pr_err("property \"assigned-addresses\" not found");
- return -FDT_ERR_NOTFOUND;
- }
-
- pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
-
- return 0;
-}
-
#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
#defineDT_TYPE_IO 0x1
#defineDT_TYPE_MEM32 0x2
@@ -567,7 +551,9 @@ static int mvebu_get_tgt_attr(ofnode node, int devfn,
static int mvebu_pcie_of_to_plat(struct udevice *dev)
{
struct mvebu_pcie *pcie = dev_get_plat(dev);
+ const u32 *addr;
int ret = 0;
+ int len;
/* Get port number, lane number and memory target / attr */
if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
@@ -605,9 +591,14 @@ static int mvebu_pcie_of_to_plat(struct udevice *dev)
}
/* Parse PCIe controller register base from DT */
- ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
- if (ret < 0)
+ addr = ofnode_get_property(dev_ofnode(dev), "assigned-addresses", &len);
+ if (!addr) {
+ printf("%s: property \"assigned-addresses\" not found\n",
pcie->name);
+ ret = -FDT_ERR_NOTFOUND;
goto err;
+ }
+
+ pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
return 0;
--
2.20.1
[PATCH u-boot-marvell 8/9] arm: mvebu: Implement simple mvebu-reset driver for enabling/disabling PCIe ports
Enabling and disabling PCIe ports is done via address space of system
controller. All 32-bit Armada SoCs use low 4 bits in SoC Control 1 Register
for enabling and disabling some or more PCIe ports. Correct mapping needs
to be set in particular DTS files.
DT API for mvebu-reset is prepared for implementing resets also for other
HW blocks, but currently only PCIe is implemented via index 0.
Currently this driver is not used as PCIe ports are automatically enabled
by SerDes code executed by U-Boot SPL. But this will change in followup
patches.
Signed-off-by: Pali Rohár
---
arch/arm/dts/armada-375.dtsi| 3 +-
arch/arm/dts/armada-38x.dtsi| 1 +
arch/arm/dts/armada-xp-98dx3236.dtsi| 1 +
arch/arm/dts/armada-xp.dtsi | 1 +
arch/arm/mach-mvebu/Makefile| 1 +
arch/arm/mach-mvebu/system-controller.c | 105
6 files changed, 111 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-mvebu/system-controller.c
diff --git a/arch/arm/dts/armada-375.dtsi b/arch/arm/dts/armada-375.dtsi
index 62a548a55f3f..fdf2d6dbdc84 100644
--- a/arch/arm/dts/armada-375.dtsi
+++ b/arch/arm/dts/armada-375.dtsi
@@ -384,9 +384,10 @@
interrupts = ;
};
- system-controller@18200 {
+ systemc: system-controller@18200 {
compatible =
"marvell,armada-375-system-controller";
reg = <0x18200 0x100>;
+ #reset-cells = <2>;
};
gateclk: clock-gating-control@18220 {
diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi
index 72c49beb71a4..061bd7852081 100644
--- a/arch/arm/dts/armada-38x.dtsi
+++ b/arch/arm/dts/armada-38x.dtsi
@@ -328,6 +328,7 @@
compatible =
"marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
+ #reset-cells = <2>;
};
gateclk: clock-gating-control@18220 {
diff --git a/arch/arm/dts/armada-xp-98dx3236.dtsi
b/arch/arm/dts/armada-xp-98dx3236.dtsi
index 5df1d1848dbc..8369de79afa2 100644
--- a/arch/arm/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/dts/armada-xp-98dx3236.dtsi
@@ -136,6 +136,7 @@
systemc: system-controller@18200 {
compatible =
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
+ #reset-cells = <2>;
};
gateclk: clock-gating-control@18220 {
diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi
index d856d9602272..fb5640bbd93c 100644
--- a/arch/arm/dts/armada-xp.dtsi
+++ b/arch/arm/dts/armada-xp.dtsi
@@ -78,6 +78,7 @@
systemc: system-controller@18200 {
compatible =
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
+ #reset-cells = <2>;
};
gateclk: clock-gating-control@18220 {
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 7e9c206ed6b8..0b2c57e57360 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -21,6 +21,7 @@ else # CONFIG_ARCH_KIRKWOOD
obj-y = cpu.o
obj-y += dram.o
+obj-$(CONFIG_DM_RESET) += system-controller.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
diff --git a/arch/arm/mach-mvebu/system-controller.c
b/arch/arm/mach-mvebu/system-controller.c
new file mode 100644
index ..a59fc26e38b1
--- /dev/null
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) 2021 Pali Rohár
+
+#include
+#include
+#include
+#include
+
+#define MVEBU_SOC_CONTROL_1_REG 0x4
+
+#define MVEBU_PCIE_ID 0
+
+struct mvebu_reset_data {
+ void *base;
+};
+
+static int mvebu_reset_of_xlate(struct reset_ctl *rst,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count < 2)
+ return -EINVAL;
+
+ rst->id = args->args[0];
+ rst->data = args->args[1];
+
+ /* Currently only PCIe is implemented */
+ if (rst->id != MVEBU_PCIE_ID)
+ return -EINVAL;
+
+ /* Four PCIe enable bits are shared across more PCIe links */
+ if (!(rst->data >= 0 && rst->data <= 3))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int mvebu_reset_request(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int mvebu_reset_free(struct reset
[PATCH u-boot-marvell 6/9] pci: pci_mvebu: Split initialization of PCIe ports into 3 phases
In first phase just parse DT properties and fill struct mvebu_pcie. In
second phase setup all PCIe links (without enabling them). And in the last
third phase enable all PCIe links and create UCLASS_PCI device for each
one.
Because parsing of DT is done before UCLASS_PCI is created, we cannot use
DM for this action anymore. So remove .of_to_plat callback and replace it
by ad-hoc function for parsing DT properties and filling struct mvebu_pcie.
Signed-off-by: Pali Rohár
---
drivers/pci/pci_mvebu.c | 106 +++-
1 file changed, 84 insertions(+), 22 deletions(-)
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index ba776217c9e6..504ff501aa2e 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -364,17 +364,30 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
}
-static int mvebu_pcie_probe(struct udevice *dev)
+/* Only enable PCIe link, do not setup it */
+static int mvebu_pcie_enable_link(struct mvebu_pcie *pcie, ofnode node)
+{
+ /* PCIe link is currently automatically enabled in SerDes code */
+ return 0;
+}
+
+/* Setup PCIe link but do not enable it */
+static void mvebu_pcie_setup_link(struct mvebu_pcie *pcie)
{
- struct mvebu_pcie *pcie = dev_get_plat(dev);
- struct udevice *ctlr = pci_get_controller(dev);
- struct pci_controller *hose = dev_get_uclass_priv(ctlr);
u32 reg;
/* Setup PCIe controller to Root Complex mode */
reg = readl(pcie->base + PCIE_CTRL_OFF);
reg |= PCIE_CTRL_RC_MODE;
writel(reg, pcie->base + PCIE_CTRL_OFF);
+}
+
+static int mvebu_pcie_probe(struct udevice *dev)
+{
+ struct mvebu_pcie *pcie = dev_get_plat(dev);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ u32 reg;
/*
* Change Class Code of PCI Bridge device to PCI Bridge (0x600400)
@@ -440,7 +453,8 @@ static int mvebu_pcie_probe(struct udevice *dev)
mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
(phys_addr_t)pcie->mem.start,
resource_size(&pcie->mem))) {
- printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
+ printf("%s: unable to add mbus window for mem at %08x+%08x\n",
+ pcie->name,
(u32)pcie->mem.start,
(unsigned)resource_size(&pcie->mem));
pcie->mem.start = 0;
pcie->mem.end = -1;
@@ -450,7 +464,8 @@ static int mvebu_pcie_probe(struct udevice *dev)
mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
(phys_addr_t)pcie->io.start,
resource_size(&pcie->io))) {
- printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
+ printf("%s: unable to add mbus window for IO at %08x+%08x\n",
+ pcie->name,
(u32)pcie->io.start, (unsigned)resource_size(&pcie->io));
pcie->io.start = 0;
pcie->io.end = -1;
@@ -549,33 +564,34 @@ static int mvebu_get_tgt_attr(ofnode node, int devfn,
return -ENOENT;
}
-static int mvebu_pcie_of_to_plat(struct udevice *dev)
+static int mvebu_pcie_port_parse_dt(ofnode node, ofnode parent, struct
mvebu_pcie *pcie)
{
- struct mvebu_pcie *pcie = dev_get_plat(dev);
+ struct fdt_pci_addr pci_addr;
const u32 *addr;
int ret = 0;
int len;
/* Get port number, lane number and memory target / attr */
- if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
+ if (ofnode_read_u32(node, "marvell,pcie-port",
&pcie->port)) {
ret = -ENODEV;
goto err;
}
- if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
+ if (ofnode_read_u32(node, "marvell,pcie-lane", &pcie->lane))
pcie->lane = 0;
sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
- /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
- pcie->devfn = pci_get_devfn(dev);
- if (pcie->devfn < 0) {
- ret = -ENODEV;
+ /* devfn is in bits [15:8], see PCI_DEV usage */
+ ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
&pci_addr);
+ if (ret < 0) {
+ printf("%s: property \"reg\" is invalid\n", pcie->name);
goto err;
}
+ pcie->devfn = pci_addr.phys_hi & 0xff00;
- ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
+ ret = mvebu_get_tgt_attr(parent, pcie->devfn,
IORESOURCE_MEM,
&pcie->mem_target, &pcie->mem_attr);
if (ret < 0) {
@@ -583,
[PATCH u-boot-marvell 7/9] pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe()
After function mvebu_pcie_probe() returns U-Boot DM expects that PCIe link
is already up. In followup patches link initialization will be moved from
SPL to proper and therefore explicitly link up delay is required.
Delay mvebu_pcie_probe() for 100ms to ensure that PCIe link is up after
function finish. In the case when no card is connected to the PCIe slot,
this will delay probe time by 100ms, which should not be problematic.
This change fixes detection and initialization of some QCA98xx cards on
the first serdes when configured in x1 mode. Default configuration of
the first serdes on A385 is x4 mode, so it looks as if some delay is
required when x4 is changed to x1 and card correctly links with A385.
Other PCIe serdes ports on A385 are x1-only, and so they don't have this
problem.
Signed-off-by: Pali Rohár
---
drivers/pci/pci_mvebu.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 504ff501aa2e..b5b0897b2124 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -69,6 +70,9 @@
#define PCIE_DEBUG_CTRL0x1a60
#define PCIE_DEBUG_SOFT_RESET BIT(20)
+#define LINK_WAIT_RETRIES 100
+#define LINK_WAIT_TIMEOUT 1000
+
struct mvebu_pcie {
struct pci_controller hose;
void __iomem *base;
@@ -98,6 +102,23 @@ static inline bool mvebu_pcie_link_up(struct mvebu_pcie
*pcie)
return !(val & PCIE_STAT_LINK_DOWN);
}
+static void mvebu_pcie_wait_for_link(struct mvebu_pcie *pcie)
+{
+ int retries;
+
+ /* check if the link is up or not */
+ for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) {
+ if (mvebu_pcie_link_up(pcie)) {
+ printf("%s: Link up\n", pcie->name);
+ return;
+ }
+
+ udelay(LINK_WAIT_TIMEOUT);
+ }
+
+ printf("%s: Link down\n", pcie->name);
+}
+
static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
{
u32 stat;
@@ -501,6 +522,8 @@ static int mvebu_pcie_probe(struct udevice *dev)
pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] =
PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16);
+ mvebu_pcie_wait_for_link(pcie);
+
return 0;
}
--
2.20.1
[PATCH u-boot-marvell 3/9] pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping
Do not call pci_set_region() for resources which were not properly mapped.
This prevents U-Boot to access unmapped memory space.
Update MBUS_PCI_MEM_SIZE and MBUS_PCI_IO_SIZE macros to cover all PCIe MEM
and IO ranges. Previously these macros covered only address ranges for the
first PCIe port. Between MBUS_PCI_IO_BASE and MBUS_PCI_MEM_BASE there is
space for six 128 MB long address ranges. So set MBUS_PCI_MEM_SIZE to value
of 6*128 MB. Similarly set MBUS_PCI_IO_SIZE to 6*64 KB.
Function resource_size() returns zero when start address is 0 and end
address is -1. So set invalid resources to these values to indicate that
resource has no mapping.
Split global PCIe MEM and IO resources (defined by MBUS_PCI_*_* macros)
into PCIe ports in mvebu_pcie_bind() function which allocates per-port
based struct mvebu_pcie, instead of using global state variables
mvebu_pcie_membase and mvebu_pcie_iobase. This makes pci_mvebu.c driver
independent of global static variables (which store the state of
allocation) and allows to bind and unbind the driver more times.
Signed-off-by: Pali Rohár
Signed-off-by: Marek Behún
---
arch/arm/mach-mvebu/include/mach/cpu.h | 5 +-
drivers/pci/pci_mvebu.c| 84 ++
2 files changed, 62 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h
b/arch/arm/mach-mvebu/include/mach/cpu.h
index a7a62c7e7d53..b99d86a87a03 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -74,10 +74,11 @@ enum {
/*
* Default Device Address MAP BAR values
*/
+#define MBUS_PCI_MAX_PORTS 6
#define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX
-#define MBUS_PCI_MEM_SIZE (128 << 20)
+#define MBUS_PCI_MEM_SIZE ((MBUS_PCI_MAX_PORTS * 128) << 20)
#define MBUS_PCI_IO_BASE 0xF110
-#define MBUS_PCI_IO_SIZE (64 << 10)
+#define MBUS_PCI_IO_SIZE ((MBUS_PCI_MAX_PORTS * 64) << 10)
#define MBUS_SPI_BASE 0xF400
#define MBUS_SPI_SIZE (8 << 20)
#define MBUS_DFX_BASE 0xF600
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 9248cbc294ce..eaaa6cbe326d 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
/* PCIe unit register offsets */
#define SELECT(x, n) ((x >> n) & 1UL)
@@ -89,14 +90,6 @@ struct mvebu_pcie {
u32 cfgcache[(0x3c - 0x10) / 4];
};
-/*
- * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
- * into SoCs address space. Each controller will map 128M of MEM
- * and 64K of I/O space when registered.
- */
-static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
-static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE;
-
static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
{
u32 val;
@@ -442,26 +435,24 @@ static int mvebu_pcie_probe(struct udevice *dev)
mvebu_pcie_set_local_bus_nr(pcie, 0);
mvebu_pcie_set_local_dev_nr(pcie, 1);
- pcie->mem.start = (u32)mvebu_pcie_membase;
- pcie->mem.end = pcie->mem.start + MBUS_PCI_MEM_SIZE - 1;
- mvebu_pcie_membase += MBUS_PCI_MEM_SIZE;
-
- if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
+ if (resource_size(&pcie->mem) &&
+ mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
(phys_addr_t)pcie->mem.start,
resource_size(&pcie->mem))) {
printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
(u32)pcie->mem.start,
(unsigned)resource_size(&pcie->mem));
+ pcie->mem.start = 0;
+ pcie->mem.end = -1;
}
- pcie->io.start = (u32)mvebu_pcie_iobase;
- pcie->io.end = pcie->io.start + MBUS_PCI_IO_SIZE - 1;
- mvebu_pcie_iobase += MBUS_PCI_IO_SIZE;
-
- if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
+ if (resource_size(&pcie->io) &&
+ mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
(phys_addr_t)pcie->io.start,
resource_size(&pcie->io))) {
printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
(u32)pcie->io.start, (unsigned)resource_size(&pcie->io));
+ pcie->io.start = 0;
+ pcie->io.end = -1;
}
/* Setup windows and configure host bridge */
@@ -470,13 +461,23 @@ static int mvebu_pcie_probe(struct udevice *dev)
/* PCI memory space */
pci_set_region(hose->regions + 0, pcie->mem.start,
pcie->mem.start, resource_size(&pcie->mem),
PCI_REGION_MEM);
- pci_set_region(hose->regions + 1,
- 0, 0,
- gd->ram_size,
- PCI_REGION_MEM | PCI_REGION_S
[PATCH u-boot-marvell 5/9] pci: pci_mvebu: Remove dependency on SOC_REGS_PHY_BASE macro
SoC specific macro SOC_REGS_PHY_BASE is used for two things:
* calculation of base PCIe port address
* filling PCIe register with address of internal registers
For calculating base PCIe port address use function
ofnode_translate_address() which translates DT "assigned-addresses" to
final PCIe port address.
And for calculating address of internal registers use untranslated and
translated DT "assigned-addresses".
Basically this change reads SOC_REGS_PHY_BASE address indirectly from DT.
Signed-off-by: Pali Rohár
---
drivers/pci/pci_mvebu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index c47551807bc2..ba776217c9e6 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -76,6 +76,7 @@ struct mvebu_pcie {
struct resource mem;
void __iomem *iobase;
struct resource io;
+ u32 intregs;
u32 port;
u32 lane;
int devfn;
@@ -359,7 +360,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
pcie->base + PCIE_BAR_CTRL_OFF(1));
/* Setup BAR[0] to internal registers. */
- writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
+ writel(pcie->intregs, pcie->base + PCIE_BAR_LO_OFF(0));
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
}
@@ -598,7 +599,8 @@ static int mvebu_pcie_of_to_plat(struct udevice *dev)
goto err;
}
- pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
+ pcie->base = (void *)(u32)ofnode_translate_address(dev_ofnode(dev),
addr);
+ pcie->intregs = (u32)pcie->base - fdt32_to_cpu(addr[2]);
return 0;
--
2.20.1
[PATCH u-boot-marvell 2/9] board: gdsys: a38x: Enable PCIe link 2 in spl_board_init()
A385 controlcenterdc board does not use PCI DM properly and touches some
PCIe devices directly in its board code.
This controlcenterdc spl_board_init() function expects that PCIe link is
already initialized. Link itself is initialized in a38x serdes code but
this will change in future and link initialization will be postponed from
U-Boot SPL to proper U-Boot.
So explicitly enable PCIe link 2 in spl_board_init() function via
SoC Control Register 1 to not break this code by future changes. This board
has PCIe link 2 just x1, so no additional initialization (except enabling
PCIe port) is needed.
Signed-off-by: Pali Rohár
---
board/gdsys/a38x/controlcenterdc.c | 4
1 file changed, 4 insertions(+)
diff --git a/board/gdsys/a38x/controlcenterdc.c
b/board/gdsys/a38x/controlcenterdc.c
index 243d02232667..7d65400ccb0d 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -100,6 +100,10 @@ void spl_board_init(void)
uint k;
struct gpio_desc gpio = {};
+ /* Enable PCIe link 2 */
+ setbits_32(MVEBU_REGISTER(0x18204), BIT(2));
+ mdelay(10);
+
if (!request_gpio_by_name(&gpio, "pca9698@22", 31,
"fpga-program-gpio")) {
/* prepare FPGA reconfiguration */
dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
--
2.20.1
[PATCH u-boot-marvell 1/9] arm: mvebu: Convert board_pex_config() to CONFIG_SPL_BOARD_INIT
The only user of board_pex_config() weak function is A385 controlcenterdc
board. It looks like that code in its board_pex_config() function needs to
be executed after PCIe link is up. Therefore put this code into
spl_board_init() function which is called after a38x serdes initialization,
and therefore it is after the serdes hws_pex_config() function finishes
(which is the state before this change).
With this change completely remove board_pex_config() function as it is not
used anymore.
Signed-off-by: Pali Rohár
---
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 7 ---
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 1 -
board/gdsys/a38x/controlcenterdc.c | 2 +-
configs/controlcenterdc_defconfig | 1 +
4 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
index 55c3f9ca390b..b3cbddf6a2f0 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
@@ -14,11 +14,6 @@
#include "ctrl_pex.h"
#include "sys_env_lib.h"
-__weak void board_pex_config(void)
-{
- /* nothing in this weak default implementation */
-}
-
int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
{
enum serdes_type serdes_type;
@@ -58,7 +53,5 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8
count)
reg_write(SOC_CONTROL_REG1, tmp);
- board_pex_config();
-
return MV_OK;
}
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
index 64193d528886..abdbe3c66045 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
@@ -23,6 +23,5 @@
#define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
-void board_pex_config(void);
#endif
diff --git a/board/gdsys/a38x/controlcenterdc.c
b/board/gdsys/a38x/controlcenterdc.c
index dc424f271c5e..243d02232667 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -94,7 +94,7 @@ int hws_board_topology_load(struct serdes_map
**serdes_map_array, u8 *count)
return 0;
}
-void board_pex_config(void)
+void spl_board_init(void)
{
#ifdef CONFIG_SPL_BUILD
uint k;
diff --git a/configs/controlcenterdc_defconfig
b/configs/controlcenterdc_defconfig
index 44db3110916c..87ad273a5131 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -33,6 +33,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_LAST_STAGE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_I2C=y
CONFIG_HUSH_PARSER=y
--
2.20.1
[PATCH u-boot-marvell 0/9] mvebu: Move PCIe code from serdes to PCIe driver
This patch series removes gdsys's board_pex_config() function by converting it to spl_board_init(), adds a new mvebu-reset driver for enabling / disabling PCIe ports and finally moves PCIe code from serdes driver to pci_mvebu.c driver. After all these changes, PCIe link is not initialized in serdes code anymore, but in pci_mvebu.c driver with help of mvebu-reset driver. I'm not sure if change for gdsys board is correct, so if somebody has this board, please test it. I tested this change on A385 board Turris Omnia and I verified that PCIe links are really enabled by pci_mvebu.c driver and not before. This patch series is based on u-boot-marvell/next branch. Pali Rohár (9): arm: mvebu: Convert board_pex_config() to CONFIG_SPL_BOARD_INIT board: gdsys: a38x: Enable PCIe link 2 in spl_board_init() pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping pci: pci_mvebu: Inline mvebu_pcie_port_parse_dt() function pci: pci_mvebu: Remove dependency on SOC_REGS_PHY_BASE macro pci: pci_mvebu: Split initialization of PCIe ports into 3 phases pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe() arm: mvebu: Implement simple mvebu-reset driver for enabling/disabling PCIe ports arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c arch/arm/dts/armada-375.dtsi | 5 +- arch/arm/dts/armada-380.dtsi | 3 + arch/arm/dts/armada-385.dtsi | 4 + arch/arm/dts/armada-38x.dtsi | 1 + arch/arm/dts/armada-xp-98dx3236.dtsi | 2 + arch/arm/dts/armada-xp-mv78230.dtsi | 5 + arch/arm/dts/armada-xp-mv78260.dtsi | 9 + arch/arm/dts/armada-xp-mv78460.dtsi | 10 + arch/arm/dts/armada-xp-synology-ds414.dts | 1 + arch/arm/dts/armada-xp-theadorable.dts| 1 + arch/arm/dts/armada-xp.dtsi | 1 + arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/include/mach/cpu.h| 5 +- arch/arm/mach-mvebu/serdes/a38x/Makefile | 1 - arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c| 64 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h| 28 -- .../serdes/a38x/high_speed_env_spec.c | 19 -- arch/arm/mach-mvebu/system-controller.c | 105 +++ board/gdsys/a38x/controlcenterdc.c| 6 +- configs/controlcenterdc_defconfig | 1 + drivers/pci/Kconfig | 1 + drivers/pci/pci_mvebu.c | 275 ++ 22 files changed, 371 insertions(+), 177 deletions(-) delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h create mode 100644 arch/arm/mach-mvebu/system-controller.c -- 2.20.1
Re: [PATCH u-boot-marvell 00/10] PCI mvebu and aardvark changes
On Tuesday 21 December 2021 09:19:12 Stefan Roese wrote: > Hi Pali, > > On 12/20/21 14:30, Pali Rohár wrote: > > On Saturday 18 December 2021 14:53:52 Stefan Roese wrote: > > > Hi Pali, > > > > > > On 12/16/21 11:28, Pali Rohár wrote: > > > > On Wednesday 15 December 2021 09:10:50 Stefan Roese wrote: > > > > > Hi Pali, > > > > > > > > > > On 12/13/21 11:27, Pali Rohár wrote: > > > > > > On Monday 13 December 2021 08:41:30 Stefan Roese wrote: > > > > > > > Hi Pali, > > > > > > > > > > > > > > On 12/12/21 12:23, Pali Rohár wrote: > > > > > > > > On Thursday 11 November 2021 16:35:39 Marek Behún wrote: > > > > > > > > > From: Marek Behún > > > > > > > > > > > > > > > > > > Hello Stefan, > > > > > > > > > > > > > > > > > > we have some more fixes for PCI (mvebu and aardvark), and one > > > > > > > > > patch > > > > > > > > > for Turris MOX board code. > > > > > > > > > > > > > > > > > > Marek > > > > > > > > > > > > > > > > Hello Stefan, patches 1, 2 and 7 still needs some > > > > > > > > modifications. But > > > > > > > > other remaining patches should be OK. Would you merge remaining > > > > > > > > patches? > > > > > > > > And then we can focus on issues with link initialization. > > > > > > > > > > > > > > Sure, I can pull the "remaining patches" into next (for master > > > > > > > it's too > > > > > > > late in the release cycle) if this helps. Just let me know and > > > > > > > I'll go > > > > > > > through the patch queue in the next days to push more Marvell > > > > > > > related > > > > > > > patches into next. > > > > > > > > > > > > Ok. But please consider applying patches 5, 6 and 9 to master as > > > > > > they > > > > > > have Fixes tag for commits which are already in master branch. > > > > > > > > > > Okay, thanks for the reminder. The Azure world build is running. So > > > > > I'll > > > > > send the pull request for these 3 patches most likely later today. > > > > > > > > Hello and thank you! Could you include patches prepared for next into > > > > some branch, so I can prepare new patches on top of that branch to so > > > > patches would be correctly rebased? > > > > > > Done. As you will have noticed, I've pulled a bunch of patches into next > > > and did send a pull request just a few minutes ago. > > > > Perfect! > > > > > Please let me know if I forgot something. Once all this lands in Tom's > > > next branch, this should be a good base for your rebase. > > > > Could you include into next branch also other patches from this patch > > series which you have already reviewed, which are OK? > > Sure, if this helps. > > > Patches 1, 2 and 7 are those which need modifications and are not ready > > yet. > > Thanks. The other patches are "on the way" to next. Ok! I will send new pci mvebu patches rebased on top of the u-boot-marvell/next branch.
Re: [PATCH 6/6] udoo: Select CMD_DM
On Sat, Dec 18, 2021 at 9:10 PM Fabio Estevam wrote: > > CMD_DM is useful for showing the whole DM tree. > > Enable it via "imply CMD_DM". > > Signed-off-by: Fabio Estevam Reviewed-by: Peter Robinson > --- > arch/arm/mach-imx/mx6/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig > index 62de942a32aa..98df4d4e4281 100644 > --- a/arch/arm/mach-imx/mx6/Kconfig > +++ b/arch/arm/mach-imx/mx6/Kconfig > @@ -588,6 +588,7 @@ config TARGET_UDOO > depends on MX6QDL > select BOARD_LATE_INIT > select SUPPORT_SPL > + imply CMD_DM > > config TARGET_UDOO_NEO > bool "UDOO Neo" > -- > 2.25.1 >
Re: [PATCH 5/6] udoo: Increase CONFIG_ENV_OFFSET
On Sat, Dec 18, 2021 at 9:10 PM Fabio Estevam wrote: > > Increase CONFIG_ENV_OFFSET to avoid the environment region to > overlap with U-Boot proper. > > Signed-off-by: Fabio Estevam Reviewed-by: Peter Robinson > --- > configs/udoo_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig > index 284ea0588465..ab2b2ee67550 100644 > --- a/configs/udoo_defconfig > +++ b/configs/udoo_defconfig > @@ -7,7 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y > CONFIG_SPL_LIBGENERIC_SUPPORT=y > CONFIG_NR_DRAM_BANKS=1 > CONFIG_ENV_SIZE=0x2000 > -CONFIG_ENV_OFFSET=0x6 > +CONFIG_ENV_OFFSET=0xC > CONFIG_MX6QDL=y > CONFIG_TARGET_UDOO=y > CONFIG_DM_GPIO=y > -- > 2.25.1 >
Re: [PATCH 4/6] udoo: Adjust the SD card device numbering
On Sat, Dec 18, 2021 at 9:10 PM Fabio Estevam wrote:
>
> After the conversion to DM the SD card shows up as 'mmc 2'
> device.
>
> Adjust the 'mmcdev' and the distro command 'func' accordingly.
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Peter Robinson
> ---
> configs/udoo_defconfig | 1 +
> include/configs/udoo.h | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
> index 8e1bba112041..284ea0588465 100644
> --- a/configs/udoo_defconfig
> +++ b/configs/udoo_defconfig
> @@ -35,6 +35,7 @@ CONFIG_OF_CONTROL=y
> CONFIG_ENV_OVERWRITE=y
> CONFIG_ENV_IS_IN_MMC=y
> CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SYS_MMC_ENV_DEV=2
> CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> CONFIG_DM=y
> CONFIG_BOUNCE_BUFFER=y
> diff --git a/include/configs/udoo.h b/include/configs/udoo.h
> index fe6ea68dd461..4bddc0eca30e 100644
> --- a/include/configs/udoo.h
> +++ b/include/configs/udoo.h
> @@ -28,7 +28,7 @@
> "fdt_addr=0x1800\0" \
> "fdt_addr_r=0x1800\0" \
> "ip_dyn=yes\0" \
> - "mmcdev=0\0" \
> + "mmcdev=2\0" \
> "mmcrootfstype=ext4\0" \
> "findfdt="\
> "if test ${board_rev} = MX6Q; then " \
> @@ -44,7 +44,7 @@
> BOOTENV
>
> #define BOOT_TARGET_DEVICES(func) \
> - func(MMC, mmc, 0) \
> + func(MMC, mmc, 2) \
> func(SATA, sata, 0) \
> func(DHCP, dhcp, na)
>
> --
> 2.25.1
>
Re: [PATCH 0/3] Apple M1 power management controller support
> From: Jaehoon Chung > Date: Tue, 21 Dec 2021 08:00:38 +0900 Hello Jaehoon, > Dear Mark, > > On 12/7/21 4:03 AM, Mark Kettenis wrote: > > This series adds support for the power management controller found on > > Apple SoCs based on the device tree bindings submitted to upstream > > Linux. This is needed to enable power domains for devices that > > haven't been enabled by earlier boot stages. > > Is there any patch before applied this patchset? This is based on next, with the watchdog patch applied: https://patchwork.ozlabs.org/project/uboot/list/?series=271919 The drivers are independent, but I suppose you get conflicts in Kconfig and maybe the device tree without that series applied. Cheers, Mark > > > > > > Mark Kettenis (3): > > arm: dts: apple: Update Apple M1 device trees > > arm: dts: apple: Add u-boot,dm-pre-reloc properties > > power: domain: Add Apple pmgr driver > > > > arch/arm/Kconfig|4 + > > arch/arm/dts/Makefile |5 +- > > arch/arm/dts/t8103-j274-u-boot.dtsi |1 + > > arch/arm/dts/t8103-j274.dts | 122 +-- > > arch/arm/dts/t8103-j293-u-boot.dtsi |1 + > > arch/arm/dts/t8103-j293.dts | 92 +-- > > arch/arm/dts/t8103-j313-u-boot.dtsi |1 + > > arch/arm/dts/t8103-j313.dts | 57 ++ > > arch/arm/dts/t8103-j456-u-boot.dtsi |1 + > > arch/arm/dts/t8103-j456.dts | 71 ++ > > arch/arm/dts/t8103-j457-u-boot.dtsi |1 + > > arch/arm/dts/t8103-j457.dts | 59 ++ > > arch/arm/dts/t8103-jxxx.dtsi| 140 > > arch/arm/dts/t8103-pmgr.dtsi| 1136 +++ > > arch/arm/dts/t8103-u-boot.dtsi | 25 + > > arch/arm/dts/t8103.dtsi | 585 +++--- > > drivers/mailbox/Kconfig |9 + > > drivers/mailbox/Makefile|1 + > > drivers/power/domain/Kconfig|8 + > > drivers/power/domain/Makefile |1 + > > drivers/power/domain/apple-pmgr.c | 113 +++ > > 21 files changed, 2005 insertions(+), 428 deletions(-) > > create mode 100644 arch/arm/dts/t8103-j274-u-boot.dtsi > > create mode 100644 arch/arm/dts/t8103-j293-u-boot.dtsi > > create mode 100644 arch/arm/dts/t8103-j313-u-boot.dtsi > > create mode 100644 arch/arm/dts/t8103-j313.dts > > create mode 100644 arch/arm/dts/t8103-j456-u-boot.dtsi > > create mode 100644 arch/arm/dts/t8103-j456.dts > > create mode 100644 arch/arm/dts/t8103-j457-u-boot.dtsi > > create mode 100644 arch/arm/dts/t8103-j457.dts > > create mode 100644 arch/arm/dts/t8103-jxxx.dtsi > > create mode 100644 arch/arm/dts/t8103-pmgr.dtsi > > create mode 100644 arch/arm/dts/t8103-u-boot.dtsi > > create mode 100644 drivers/power/domain/apple-pmgr.c > > > >
Please pull u-boot-marvell/next
Hi Tom, please pull the following Marvell MVEBU related patches into next: - pci_mvebu: Misc improvements and cleanup (Pali) - turris_mox: Remove extra newline after module topology (Marek) Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=142&view=results Thanks, Stefan The following changes since commit 4afab30caea3211032710c4298a8839d3254e7f7: Merge tag 'v2022.01-rc4' into next (2021-12-20 17:12:04 -0500) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-marvell.git next for you to fetch changes up to 6488939b4a78e03999c15314bed358b4e26940d0: arm: mvebu: turris_mox: Remove extra newline after module topology (2021-12-21 07:42:01 +0100) Marek Behún (1): arm: mvebu: turris_mox: Remove extra newline after module topology Pali Rohár (3): pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size() pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTR board/CZ.NIC/turris_mox/turris_mox.c | 3 --- drivers/pci/pci_mvebu.c | 27 +-- 2 files changed, 13 insertions(+), 17 deletions(-)
Re: [PATCH u-boot-marvell 10/10] arm: mvebu: turris_mox: Remove extra newline after module topology
On 11/11/21 16:35, Marek Behún wrote:
From: Marek Behún
Remove extra newline after module topology is printed.
Signed-off-by: Marek Behún
Applied to u-boot-marvell/next
Thanks,
Stefan
---
board/CZ.NIC/turris_mox/turris_mox.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c
b/board/CZ.NIC/turris_mox/turris_mox.c
index 2202eb8cfb..52fa77d68c 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -607,9 +607,6 @@ int show_board_info(void)
}
}
- if (module_count)
- printf("\n");
-
return 0;
}
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH u-boot-marvell 08/10] pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTR
On 11/11/21 16:35, Marek Behún wrote: From: Pali Rohár The global data pointer is not used in this driver, remove it's declaration. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Applied to u-boot-marvell/next Thanks, Stefan --- drivers/pci/pci_mvebu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index fea32414bf..f3830f67aa 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -28,8 +27,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* PCIe unit register offsets */ #define SELECT(x, n) ((x >> n) & 1UL) Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v7 09/24] efi: Add a few comments to the stub
On 12/18/21 19:28, Simon Glass wrote:
Comment some functions that need more information.
Signed-off-by: Simon Glass
---
(no changes since v6)
Changes in v6:
- Fix comment style in setup_info_table()
lib/efi/efi_stub.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/lib/efi/efi_stub.c b/lib/efi/efi_stub.c
index b3393e47fae..e8a594cb2aa 100644
--- a/lib/efi/efi_stub.c
+++ b/lib/efi/efi_stub.c
@@ -225,6 +225,22 @@ static int get_codeseg32(void)
return cs32;
}
+/**
+ * setup_info_table() - sets up a table containing information from EFI
+ *
+ * We must call exit_boot_services() before jumping out of the stub into U-Boot
+ * proper, so that U-Boot has full control of peripherals, memory, etc.
+ *
+ * Once we do this, we cannot call any boot-services functions so we must find
+ * out everything we need to before doing that.
+ *
+ * Set up a struct efi_info_hdr table which can hold various records (e.g.
+ * struct efi_entry_memmap) with information obtained from EFI.
+ *
+ * @priv: Pointer to our private information which contains the list
+ * @size: Size of the table to allocate
+ * Return: 0 if OK, non-zero on error
+ */
static int setup_info_table(struct efi_priv *priv, int size)
{
struct efi_info_hdr *info;
@@ -248,6 +264,12 @@ static int setup_info_table(struct efi_priv *priv, int
size)
return 0;
}
+/**
+ * add_entry_addr() - Add a new entry to the efi_info list
+ *
+ * @priv: Pointer to our private information which contains the list
You missed a few arguments.
Best regards
Heinrich
+ *
+ */
static void add_entry_addr(struct efi_priv *priv, enum efi_entry_t type,
void *ptr1, int size1, void *ptr2, int size2)
{
Re: [PATCH u-boot-marvell 04/10] pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size()
On 11/11/21 16:35, Marek Behún wrote:
From: Pali Rohár
Use more appropriate resource_size() function when working with data in
struct resource.
Signed-off-by: Pali Rohár
Signed-off-by: Marek Behún
Applied to u-boot-marvell/next
Thanks,
Stefan
---
drivers/pci/pci_mvebu.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 97c7b5604f..fde52ec99d 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -477,9 +477,9 @@ static int mvebu_pcie_probe(struct udevice *dev)
if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
(phys_addr_t)pcie->mem.start,
- MBUS_PCI_MEM_SIZE)) {
+ resource_size(&pcie->mem))) {
printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
- (u32)pcie->mem.start, MBUS_PCI_MEM_SIZE);
+ (u32)pcie->mem.start,
(unsigned)resource_size(&pcie->mem));
}
pcie->io.start = (u32)mvebu_pcie_iobase;
@@ -488,9 +488,9 @@ static int mvebu_pcie_probe(struct udevice *dev)
if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
(phys_addr_t)pcie->io.start,
- MBUS_PCI_IO_SIZE)) {
+ resource_size(&pcie->io))) {
printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
- (u32)pcie->io.start, MBUS_PCI_IO_SIZE);
+ (u32)pcie->io.start, (unsigned)resource_size(&pcie->io));
}
/* Setup windows and configure host bridge */
@@ -498,13 +498,13 @@ static int mvebu_pcie_probe(struct udevice *dev)
/* PCI memory space */
pci_set_region(hose->regions + 0, pcie->mem.start,
- pcie->mem.start, MBUS_PCI_MEM_SIZE, PCI_REGION_MEM);
+ pcie->mem.start, resource_size(&pcie->mem),
PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
0, 0,
gd->ram_size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
pci_set_region(hose->regions + 2, pcie->io.start,
- pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
+ pcie->io.start, resource_size(&pcie->io), PCI_REGION_IO);
hose->region_count = 3;
/* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH u-boot-marvell 03/10] pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup
On 11/11/21 16:35, Marek Behún wrote:
From: Pali Rohár
Function mvebu_pcie_setup_wins() sets up all other BARs, so move setup of
BAR[0] to this function to have common code at one place.
In the past, commit 193a1e9f196b ("pci: pci_mvebu: set BAR0 after memory
space is set") moved setup of BAR[0] to another location, due to ath10k
not working in kernel, but the reason why was unknown, but it seems to
work now, and we think the issue then was cause by the PCIe Root Port
presenting itself as a Memory Controller and therefore U-Boot's code
have overwritten the BAR. Since the driver now ignores any write
operations to PCIe Root Port BARs, this should not be an issue anymore.
Signed-off-by: Pali Rohár
Signed-off-by: Marek Behún
Applied to u-boot-marvell/next
Thanks,
Stefan
---
drivers/pci/pci_mvebu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 278dc2756f..97c7b5604f 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -335,7 +335,9 @@ static int mvebu_pcie_write_config(struct udevice *bus,
pci_dev_t bdf,
/*
* Setup PCIE BARs and Address Decode Wins:
- * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * BAR[0] -> internal registers
+ * BAR[1] -> covers all DRAM banks
+ * BAR[2] -> disabled
* WIN[0-3] -> DRAM bank[0-3]
*/
static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
@@ -386,6 +388,10 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
writel(((size - 1) & 0x) | 0x1,
pcie->base + PCIE_BAR_CTRL_OFF(1));
+
+ /* Setup BAR[0] to internal registers. */
+ writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
+ writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
}
static int mvebu_pcie_probe(struct udevice *dev)
@@ -501,10 +507,6 @@ static int mvebu_pcie_probe(struct udevice *dev)
pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
hose->region_count = 3;
- /* Set BAR0 to internal registers */
- writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
- writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
-
/* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v7 08/24] efi: Fix ll_boot_init() operation with the app
On 12/18/21 19:28, Simon Glass wrote: This should return false when the EFI app is running, since UEFI has done the required low-level init. Fix it. Signed-off-by: Simon Glass --- (no changes since v1) include/init.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/init.h b/include/init.h index f2cd46dead0..3ce7b8b95bd 100644 --- a/include/init.h +++ b/include/init.h @@ -15,7 +15,7 @@ #include /* Avoid using CONFIG_EFI_STUB directly as we may boot from other loaders */ Please, adjust the comment which seems not to fit anymore, e.g. /* * In case of the EFI app the UEFI firmware provides the low level * initialization. */ Best regards Heinrich -#ifdef CONFIG_EFI_STUB +#ifdef CONFIG_EFI #define ll_boot_init()false #else #include
Re: [PATCH u-boot-marvell 00/10] PCI mvebu and aardvark changes
Hi Pali, On 12/20/21 14:30, Pali Rohár wrote: On Saturday 18 December 2021 14:53:52 Stefan Roese wrote: Hi Pali, On 12/16/21 11:28, Pali Rohár wrote: On Wednesday 15 December 2021 09:10:50 Stefan Roese wrote: Hi Pali, On 12/13/21 11:27, Pali Rohár wrote: On Monday 13 December 2021 08:41:30 Stefan Roese wrote: Hi Pali, On 12/12/21 12:23, Pali Rohár wrote: On Thursday 11 November 2021 16:35:39 Marek Behún wrote: From: Marek Behún Hello Stefan, we have some more fixes for PCI (mvebu and aardvark), and one patch for Turris MOX board code. Marek Hello Stefan, patches 1, 2 and 7 still needs some modifications. But other remaining patches should be OK. Would you merge remaining patches? And then we can focus on issues with link initialization. Sure, I can pull the "remaining patches" into next (for master it's too late in the release cycle) if this helps. Just let me know and I'll go through the patch queue in the next days to push more Marvell related patches into next. Ok. But please consider applying patches 5, 6 and 9 to master as they have Fixes tag for commits which are already in master branch. Okay, thanks for the reminder. The Azure world build is running. So I'll send the pull request for these 3 patches most likely later today. Hello and thank you! Could you include patches prepared for next into some branch, so I can prepare new patches on top of that branch to so patches would be correctly rebased? Done. As you will have noticed, I've pulled a bunch of patches into next and did send a pull request just a few minutes ago. Perfect! Please let me know if I forgot something. Once all this lands in Tom's next branch, this should be a good base for your rebase. Could you include into next branch also other patches from this patch series which you have already reviewed, which are OK? Sure, if this helps. Patches 1, 2 and 7 are those which need modifications and are not ready yet. Thanks. The other patches are "on the way" to next. Thanks, Stefan Thanks, Stefan Thanks, Stefan Thanks, Stefan Marek Behún (2): pci: pci_mvebu, pci_aardvark: Fix size of configuration cache arm: mvebu: turris_mox: Remove extra newline after module topology Pali Rohár (8): pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe() arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size() pci: pci_mvebu: Do not allow setting ROM BAR on PCI Bridge pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTR arm: a37xx: pci: Do not allow setting ROM BAR on PCI Bridge arch/arm/mach-mvebu/include/mach/cpu.h| 4 +- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h| 4 - .../serdes/a38x/high_speed_env_spec.c | 15 -- board/CZ.NIC/turris_mox/turris_mox.c | 3 - drivers/pci/pci-aardvark.c| 54 +++-- drivers/pci/pci_mvebu.c | 205 -- 6 files changed, 175 insertions(+), 110 deletions(-) -- 2.32.0 Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
[PATCH 1/1] efi: fix typo in description of struct efi_entry_hdr
Add missing colon.
Signed-off-by: Heinrich Schuchardt
---
include/efi.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/efi.h b/include/efi.h
index 0ec5913ddd..1432038838 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -321,7 +321,7 @@ struct efi_info_hdr {
* struct efi_entry_hdr - Header for a table entry
*
* @type: enum eft_entry_t
- * @size size of entry bytes excluding header and padding
+ * @size: size of entry bytes excluding header and padding
* @addr: address of this entry (0 if it follows the header )
* @link: size of entry including header and padding
* @spare1:Spare space for expansion
--
2.33.1
[PATCH 1/1] doc: remove duplicate page inclusion
doc/usage/index.rst in branch origin/next includes usage/environment twice. Remove the duplicate entry. Signed-off-by: Heinrich Schuchardt --- Hello Tom, this seems to be merge error. We need this patch to build 'make htmldocs'. Please, apply to origin/next without further pull request. Best regards Heinrich --- doc/usage/index.rst | 1 - 1 file changed, 1 deletion(-) diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 3905540735..33761af96a 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -11,7 +11,6 @@ Use U-Boot netconsole partitions cmdline - environment Shell commands -- -- 2.33.1
