Re: [PATCH v3 4/4] arm: kirkwood: Pogoplug-V4 : Add board implementation files
On 1/18/22 07:58, Tony Dinh wrote: Note: currently the fdt_get_phy_addr function in this file is duplicate in this board and many other Kirkwood boards (eg. Sheevaplug, GoFlex Home, etc.). This function is being factored out into common area by another patch. And because it was written for flattree only, the patch is being rewritten to use livetree calls. Signed-off-by: Tony Dinh --- Changes in v3: - Squash board file small patches into one patch Changes in v2: - Move constants to .c file and remove header file board/cloudengines/pogo_v4/MAINTAINERS | 6 + board/cloudengines/pogo_v4/Makefile | 10 ++ board/cloudengines/pogo_v4/kwbimage.cfg | 148 board/cloudengines/pogo_v4/pogo_v4.c| 220 4 files changed, 384 insertions(+) create mode 100644 board/cloudengines/pogo_v4/MAINTAINERS create mode 100644 board/cloudengines/pogo_v4/Makefile create mode 100644 board/cloudengines/pogo_v4/kwbimage.cfg create mode 100644 board/cloudengines/pogo_v4/pogo_v4.c diff --git a/board/cloudengines/pogo_v4/MAINTAINERS b/board/cloudengines/pogo_v4/MAINTAINERS new file mode 100644 index 00..35fd7858b7 --- /dev/null +++ b/board/cloudengines/pogo_v4/MAINTAINERS @@ -0,0 +1,6 @@ +POGO_V4 BOARD +M: Tony Dinh +S: Maintained +F: board/cloudengines/pogo_v4/ +F: include/configs/pogo_v4.h +F: configs/pogo_v4_defconfig diff --git a/board/cloudengines/pogo_v4/Makefile b/board/cloudengines/pogo_v4/Makefile new file mode 100644 index 00..511bf5ff7e --- /dev/null +++ b/board/cloudengines/pogo_v4/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2014-2021 Tony Dinh +# +# Based on +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# + +obj-y := pogo_v4.o diff --git a/board/cloudengines/pogo_v4/kwbimage.cfg b/board/cloudengines/pogo_v4/kwbimage.cfg new file mode 100644 index 00..f6294fe313 --- /dev/null +++ b/board/cloudengines/pogo_v4/kwbimage.cfg @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2012 +# David Purdy +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar marvell.com> + +# Boot Media configurations (DONE) +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME) +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=3 @ 200MHz (need CL=3 @ 200MHz?) +DATA 0xffd01400 0x43000618 # DDR Configuration register +# bit13-0: 0x200 (200 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xffd01404 0x34143000 # DDR Controller Control Low +# bit 4:0=addr/cmd in smame cycle +# bit 5:0=clk is driven during self refresh, we don't care for APX +# bit 6:0=use recommended falling edge of clk for addr/cmd +# bit14:0=input buffer always powered up +# bit18:1=cpu lock transaction enabled +# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31:0=no additional STARTBURST delay + +DATA 0xffd01408 0x11012227 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20:TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x0819 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xffd01410 0x0001 # DDR Address Control (changed to Dockstar vals) +# bit1-0: 00, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16:0, Cs0AddrSel +# bit17:0, Cs1AddrSel +# bit18:0, Cs2AddrSel +# bit19:0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xffd01414 0x # DDR Open Pages Control +# bit0:0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xffd01418 0x # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xffd0141c 0x0632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5(<= change to CL=3 ?) +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery +# bit12:0, PD must be zero +# bit31-13: 0 required + +DATA 0xffd01420 0x0040 # DDR Extended Mode +#
Re: [PATCH v2 00/20] J721S2: Add initial support
Hi all, On 11/01/22 1:25 pm, Aswath Govindraju wrote: > The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration in automotive ADAS applications and > industrial applications requiring AI at the network edge. This SoC extends > the Jacinto 7 family of SoCs with focus on lowering system costs and power > while providing interfaces, memory architecture and compute performance for > single and multi-sensor applications. > > Some highlights of this SoC are: > > * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable > dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x > floating point Vector DSP. > * 3D GPU: Automotive grade IMG BXS-4-64 > * Vision Processing Accelerator (VPAC) with image signal processor and > Depth and Motion Processing Accelerator (DMPAC) > * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. > * Two Ethernet ports with RGMII support. > * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, > * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, > QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. > * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL > management. > * Chips and Media Wave521CL H.264/H.265 encode/decode engine > > See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) > for further details: http://www.ti.com/lit/pdf/spruj28 > > bootlog: > - https://pastebin.ubuntu.com/p/WDpTxGHcGD/ > > Changes since v1: > - Removed unused serial aliases > - Assigned serial2 alias for main uart8 instance > - Moved aliases to respective board files > I have posted v3 for this series after fixing the patches based on the comments received. Thanks, Aswath > Aswath Govindraju (10): > ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance > ram: k3-ddrss: Add support for multiple instances of DDR subsystems > ram: k3-ddrss: Add support for configuring MSMC subsystem in case of > Multiple DDR subsystems > dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC > dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 > arm: dts: Add initial support for J721S2 SoC > arm: dts: Add initial support for J721S2 System on Module > arm: dts: Add support for A72 specific J721S2 Common Processor Board > arm: dts: k3-j721s2: Add r5 specific dt support > arm: dts: k3-j721s2-ddr: Add DDR support > > David Huang (9): > arm: K3: Add basic support for J721S2 SoC definition > drivers: dma: Add support for J721S2 > clk: clk-k3: Add support for J721S2 SoC > power: domain: ti: Add support for J721S2 SoC > ram: k3-ddrss: Add support for J721S2 SoC > soc: ti: k3-socinfo: Add entry for J721S2 SoC > board: ti: j721s2: Add board support for J721S2 > configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig > configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig > > Nishanth Menon (1): > remoteproc: k3_system_controller: Support optional boot_notification > channel > > arch/arm/dts/Makefile |2 + > .../k3-j721s2-common-proc-board-u-boot.dtsi | 149 + > arch/arm/dts/k3-j721s2-common-proc-board.dts | 430 ++ > arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi | 4387 > arch/arm/dts/k3-j721s2-ddr.dtsi | 4440 + > arch/arm/dts/k3-j721s2-main.dtsi | 937 > arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi| 302 ++ > .../dts/k3-j721s2-r5-common-proc-board.dts| 198 + > arch/arm/dts/k3-j721s2-som-p0.dtsi| 173 + > arch/arm/dts/k3-j721s2.dtsi | 167 + > arch/arm/mach-k3/Kconfig | 11 +- > arch/arm/mach-k3/Makefile |1 + > arch/arm/mach-k3/arm64-mmu.c | 53 + > arch/arm/mach-k3/include/mach/hardware.h |4 + > .../mach-k3/include/mach/j721s2_hardware.h| 60 + > arch/arm/mach-k3/include/mach/j721s2_spl.h| 46 + > arch/arm/mach-k3/include/mach/spl.h |4 + > arch/arm/mach-k3/j721s2/Makefile |5 + > arch/arm/mach-k3/j721s2/clk-data.c| 403 ++ > arch/arm/mach-k3/j721s2/dev-data.c| 85 + > arch/arm/mach-k3/j721s2_init.c| 312 ++ > board/ti/j721s2/Kconfig | 63 + > board/ti/j721s2/MAINTAINERS |7 + > board/ti/j721s2/Makefile |8 + > board/ti/j721s2/evm.c | 180 + > configs/j721s2_evm_a72_defconfig | 207 + > configs/j721s2_evm_r5_defconfig | 171 + > .../remoteproc/k3-system-controller.txt |3 + > drivers/clk/ti/clk-k3.c |5 + > drivers/dma/ti/Makefile |1 + > drivers/dma/ti/k3-psil-j721s2.c | 167 + > drivers/dma/ti/k3-psil-priv.h |1 + >
[PATCH v3 20/20] configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig
From: David Huang
Enable A72 specific configs for J721S2
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Hari Nagalla
---
configs/j721s2_evm_a72_defconfig | 207 +++
1 file changed, 207 insertions(+)
create mode 100644 configs/j721s2_evm_a72_defconfig
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
new file mode 100644
index ..92f668f8f931
--- /dev/null
+++ b/configs/j721s2_evm_a72_defconfig
@@ -0,0 +1,207 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_A72_EVM=y
+CONFIG_ENV_SIZE=0x2
+CONFIG_ENV_OFFSET=0x68
+CONFIG_SYS_MALLOC_LEN=0x200
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_ENV_OFFSET_REDUND=0x6A
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run
get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_LOGLEVEL=7
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0,nor0=47034000.hyperbus"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=4704.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80
+CONFIG_CLK_CCF=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x8200
+CONFIG_FASTBOOT_BUF_SIZE=0x2F00
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HS512T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
[PATCH v3 19/20] configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig
From: David Huang Enable R5 SPL specific configs for J721S2. Signed-off-by: David Huang Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Hari Nagalla --- configs/j721s2_evm_r5_defconfig | 171 1 file changed, 171 insertions(+) create mode 100644 configs/j721s2_evm_r5_defconfig diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig new file mode 100644 index ..4ecab605357c --- /dev/null +++ b/configs/j721s2_evm_r5_defconfig @@ -0,0 +1,171 @@ +CONFIG_PANIC_HANG=y +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x1 +CONFIG_SOC_K3_J721S2=y +CONFIG_K3_EARLY_CONS=y +CONFIG_TARGET_J721S2_R5_EVM=y +CONFIG_ENV_SIZE=0x2 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x41c0 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8008 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +# CONFIG_CLK_TI_SCI is not set +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_FS_LOADER=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HS512T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +# CONFIG_TI_SCI_POWER_DOMAIN is not set +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_QSPI_PHY=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6168 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_TI_POWER_DOMAIN=y +CONFIG_SPL_CLK_CCF=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_K3_DM_FW=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_LIBFDT=y +CONFIG_SPL_DM_GPIO=y +CONFIG_SYS_MALLOC_LEN=0x200 +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SIZE_LIMIT=0x8
[PATCH v3 17/20] arm: dts: k3-j721s2: Add r5 specific dt support
Add initial support for device tree that runs on R5.
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/Makefile | 3 +-
.../dts/k3-j721s2-r5-common-proc-board.dts| 196 ++
2 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 63b451af2a2d..ea3e56d49af1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1133,7 +1133,8 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
-dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb
+dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb\
+ k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
new file mode 100644
index ..12590d391fce
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2-som-p0.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = _loader0;
+ stdout-path = _uart8;
+ tick-timer =
+ };
+
+ aliases {
+ remoteproc0 =
+ remoteproc1 = _0;
+ };
+
+ fs_loader0: fs_loader@0 {
+ compatible = "u-boot,fs-loader";
+ u-boot,dm-pre-reloc;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a9 0x0 0x10>;
+ power-domains = <_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <_reset 202 0>;
+ clocks = <_clks 61 1>;
+ assigned-clocks = <_clks 61 1>, <_clks 202 0>;
+ assigned-clock-parents = <_clks 61 2>;
+ assigned-clock-rates = <2>, <20>;
+ ti,sci = <>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ clk_200mhz: dummy_clock_200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ u-boot,dm-spl;
+ };
+
+ clk_19_2mhz: dummy_clock_19_2mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1920>;
+ u-boot,dm-spl;
+ };
+};
+
+_mcu_wakeup {
+ sa3_secproxy: secproxy@4488 {
+ u-boot,dm-spl;
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x4488 0x0 0x2>,
+ <0x0 0x4486 0x0 0x2>,
+ <0x0 0x4360 0x0 0x1>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ };
+
+ mcu_secproxy: secproxy@2a38 {
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a38 0x0 0x8>,
+ <0x0 0x2a40 0x0 0x8>,
+ <0x0 0x2a48 0x0 0x8>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ u-boot,dm-spl;
+ };
+
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <_secproxy 4>, <_secproxy 5>, <_secproxy 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ u-boot,dm-spl;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <_secproxy 21>,
+ <_secproxy 23>;
+ u-boot,dm-spl;
+ };
+};
+
+_pmx0 {
+ main_uart8_pins_default: main-uart8-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28)
MCASP0_AXR0.UART8_CTSn */
+ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26)
MCASP0_AXR1.UART8_RTSn */
+ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26)
SPI0_CS1.UART8_RXD */
+ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27)
SPI0_CLK.UART8_TXD */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+
[PATCH v3 16/20] arm: dts: Add support for A72 specific J721S2 Common Processor Board
The EVM architecture for J721S2 is similar to that of J721E and J7200. It
is as follows,
+--+
| +---+ |
| | | |
| |Add-on Card 1 Options | |
| | | |
| +---+ |
| |
| |
| +---+|
| | ||
| | SOM ||
| +--+ | ||
| | | | ||
| | Add-on | +---+|
| | Card 2 ||Power Supply
| | Options |||
| | |||
| +--+| <---
+--+
Common Processor Board
Common Processor board is the baseboard that contains most of the actual
connectors, power supply etc. The System on Module (SoM) is plugged on to
the common processor baord. Therefore, add support for peripherals brought
out in the common processor board.
Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439
Signed-off-by: Aswath Govindraju
---
Notes:
- k3-j721s2-common-proc-board.dts fine is synced from
upstream kernel v5.17-rc1 tag
arch/arm/dts/Makefile | 1 +
.../k3-j721s2-common-proc-board-u-boot.dtsi | 149 ++
arch/arm/dts/k3-j721s2-common-proc-board.dts | 430 ++
3 files changed, 580 insertions(+)
create mode 100644 arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-j721s2-common-proc-board.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1b65e65eb84c..63b451af2a2d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1133,6 +1133,7 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
+dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
new file mode 100644
index ..749bc717f390
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer =
+ };
+
+ aliases {
+ serial0 = _uart0;
+ serial1 = _uart0;
+ serial2 = _uart8;
+ i2c0 = _i2c0;
+ i2c1 = _i2c0;
+ i2c2 = _i2c1;
+ i2c3 = _i2c0;
+ ethernet0 = _port1;
+ };
+};
+
+_i2c0 {
+ u-boot,dm-spl;
+};
+
+_main {
+ u-boot,dm-spl;
+};
+
+_navss {
+ u-boot,dm-spl;
+};
+
+_mcu_wakeup {
+ u-boot,dm-spl;
+
+ timer1: timer@4040 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x4040 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <2500>;
+ u-boot,dm-spl;
+ };
+
+ chipid@4314 {
+ u-boot,dm-spl;
+ };
+};
+
+_navss {
+ u-boot,dm-spl;
+};
+
+_ringacc {
+ reg = <0x0 0x2b80 0x0 0x40>,
+ <0x0 0x2b00 0x0 0x40>,
+ <0x0 0x2859 0x0 0x100>,
+ <0x0 0x2a50 0x0 0x4>,
+ <0x0 0x2844 0x0 0x4>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ u-boot,dm-spl;
+};
+
+_udmap {
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x284c 0x0 0x4000>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x284a 0x0 0x4000>,
+ <0x0 0x2aa0 0x0 0x4>,
+ <0x0 0x2840 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+};
+
+_proxy_main {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+
[PATCH v3 15/20] arm: dts: Add initial support for J721S2 System on Module
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.
Signed-off-by: Aswath Govindraju
---
Notes:
- This patch is synced from upstream kernel v5.17-rc1 tag
arch/arm/dts/k3-j721s2-som-p0.dtsi | 173 +
1 file changed, 173 insertions(+)
create mode 100644 arch/arm/dts/k3-j721s2-som-p0.dtsi
diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi
b/arch/arm/dts/k3-j721s2-som-p0.dtsi
new file mode 100644
index ..c0687fece017
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2.dtsi"
+#include
+
+/ {
+ memory@8000 {
+ device_type = "memory";
+ /* 16 GB RAM */
+ reg = <0x00 0x8000 0x00 0x8000>,
+ <0x08 0x8000 0x03 0x8000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e80 {
+ reg = <0x00 0x9e80 0x00 0x0180>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ };
+
+ transceiver0: can-phy0 {
+ /* standby pin has been grounded by default */
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <500>;
+ };
+};
+
+_pmx0 {
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25)
I2C0_SCL */
+ J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24)
I2C0_SDA */
+ >;
+ };
+
+ main_mcan16_pins_default: main-mcan16-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
+ J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
+ >;
+ };
+};
+
+_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c0_pins_default>;
+ clock-frequency = <40>;
+
+ exp_som: gpio@21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
+ "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
+ "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
+ "GPIO_LIN_EN", "CAN_STB";
+ };
+};
+
+_mcan16 {
+ pinctrl-0 = <_mcan16_pins_default>;
+ pinctrl-names = "default";
+ phys = <>;
+};
+
+_cluster0 {
+ status = "disabled";
+};
+
+_cluster1 {
+ status = "disabled";
+};
+
+_cluster2 {
+ status = "disabled";
+};
+
+_cluster3 {
+ status = "disabled";
+};
+
+_cluster4 {
+ status = "disabled";
+};
+
+_cluster5 {
+ status = "disabled";
+};
+
+_cluster6 {
+ status = "disabled";
+};
+
+_cluster7 {
+ status = "disabled";
+};
+
+_cluster8 {
+ status = "disabled";
+};
+
+_cluster9 {
+ status = "disabled";
+};
+
+_cluster10 {
+ status = "disabled";
+};
+
+_cluster11 {
+ status = "disabled";
+};
+
+_cluster0 {
+ status = "disabled";
+};
+
+_cluster1 {
+ status = "disabled";
+};
+
+_cluster2 {
+ status = "disabled";
+};
+
+_cluster3 {
+ status = "disabled";
+};
+
+_cluster4 {
+ status = "disabled";
+};
+
+_cluster5 {
+ status = "disabled";
+};
+
+_cluster6 {
+ status = "disabled";
+};
+
+_cluster7 {
+ status = "disabled";
+};
+
+_cluster8 {
+ status = "disabled";
+};
+
+_cluster9 {
+ status = "disabled";
+};
+
+_cluster10 {
+ status = "disabled";
+};
+
+_cluster11 {
+ status = "disabled";
+};
--
2.17.1
[PATCH v3 14/20] arm: dts: Add initial support for J721S2 SoC
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.
See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28
Introduce basic support for the J721S2 SoC.
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Nishanth Menon
---
Notes:
- This patch is synced from upstream kernel v5.17-rc1 tag
arch/arm/dts/k3-j721s2-main.dtsi | 937 +
arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 302
arch/arm/dts/k3-j721s2.dtsi| 167 +
3 files changed, 1406 insertions(+)
create mode 100644 arch/arm/dts/k3-j721s2-main.dtsi
create mode 100644 arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
create mode 100644 arch/arm/dts/k3-j721s2.dtsi
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi
new file mode 100644
index ..976ba1e95aba
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-main.dtsi
@@ -0,0 +1,937 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J721S2 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+_main {
+ msmc_ram: sram@7000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x7000 0x0 0x40>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x7000 0x40>;
+
+ atf-sram@0 {
+ reg = <0x0 0x2>;
+ };
+
+ tifs-sram@1f {
+ reg = <0x1f 0x1>;
+ };
+
+ l3cache-sram@20 {
+ reg = <0x20 0x20>;
+ };
+ };
+
+ gic500: interrupt-controller@180 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x0180 0x00 0x20>, /* GICD */
+ <0x00 0x0190 0x00 0x10>; /* GICR */
+
+ /* vcpumntirq: virtual CPU interface maintenance interrupt */
+ interrupts = ;
+
+ gic_its: msi-controller@182 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x0182 0x00 0x1>;
+ socionext,synquacer-pre-its = <0x100 0x40>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_gpio_intr: interrupt-controller@a0 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x00a0 0x00 0x800>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <>;
+ #interrupt-cells = <1>;
+ ti,sci = <>;
+ ti,sci-dev-id = <148>;
+ ti,interrupt-ranges = <8 360 56>;
+ };
+
+ main_pmx0: pinctrl@11c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x0 0x11c000 0x0 0x120>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x>;
+ };
+
+ main_uart0: serial@280 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x0280 0x00 0x200>;
+ interrupts = ;
+ current-speed = <115200>;
+ clocks = <_clks 146 3>;
+ clock-names = "fclk";
+ power-domains = <_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_uart1: serial@281 {
+ compatible =
[PATCH v3 13/20] dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2
Add pinctrl macros for J721S2 SoC. These macro definitions are similar to that of J721E, but adding new definitions to avoid any naming confusions in the soc dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Aswath Govindraju --- Notes: - This patch is synced from upstream kernel v5.17-rc1 tag include/dt-bindings/pinctrl/k3.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index e085f102b283..63e038e36ca3 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -38,4 +38,7 @@ #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode)(((pa) & 0x1fff)) ((val) | (muxmode)) + #endif -- 2.17.1
[PATCH v3 11/20] board: ti: j721s2: Add board support for J721S2
From: David Huang
Add board support for J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
board/ti/j721s2/Kconfig | 63 +
board/ti/j721s2/MAINTAINERS | 16
board/ti/j721s2/Makefile| 8 ++
board/ti/j721s2/evm.c | 180
4 files changed, 267 insertions(+)
create mode 100644 board/ti/j721s2/Kconfig
create mode 100644 board/ti/j721s2/MAINTAINERS
create mode 100644 board/ti/j721s2/Makefile
create mode 100644 board/ti/j721s2/evm.c
diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig
new file mode 100644
index ..2e115f14171d
--- /dev/null
+++ b/board/ti/j721s2/Kconfig
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+# David Huang
+
+choice
+ prompt "K3 J721S2 board"
+ optional
+
+config TARGET_J721S2_A72_EVM
+ bool "TI K3 based J721S2 EVM running on A72"
+ select ARM64
+ select SOC_K3_J721S2
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
+ select SYS_DISABLE_DCACHE_OPS
+
+config TARGET_J721S2_R5_EVM
+ bool "TI K3 based J721S2 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select SOC_K3_J721S2
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+if TARGET_J721S2_A72_EVM
+
+config SYS_BOARD
+ default "j721s2"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j721s2_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J721S2_R5_EVM
+
+config SYS_BOARD
+ default "j721s2"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j721s2_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS
new file mode 100644
index ..323bd2353a7e
--- /dev/null
+++ b/board/ti/j721s2/MAINTAINERS
@@ -0,0 +1,16 @@
+J721S2 BOARD
+M: Aswath Govindraju
+S: Maintained
+F: board/ti/j721s2
+F: include/configs/j721s2_evm.h
+F: configs/j721s2_evm_r5_defconfig
+F: configs/j721s2_evm_a72_defconfig
+F: arch/arm/dts/k3-j721s2.dtsi
+F: arch/arm/dts/k3-j721s2-main.dtsi
+F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
+F: arch/arm/dts/k3-j721s2-som-p0.dtsi
+F: arch/arm/dts/k3-j721s2-common-proc-board.dts
+F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+F: arch/arm/dts//k3-j721s2-r5-common-proc-board.dts
+F: arch/arm/dts/k3-j721s2-ddr.dtsi
+F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
diff --git a/board/ti/j721s2/Makefile b/board/ti/j721s2/Makefile
new file mode 100644
index ..9dced1269942
--- /dev/null
+++ b/board/ti/j721s2/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+# David Huang
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
new file mode 100644
index ..3c75ecfc0fe4
--- /dev/null
+++ b/board/ti/j721s2/evm.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J721S2 EVM
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * David Huang
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../common/board_detect.h"
+
+#define board_is_j721s2_som() board_ti_k3_is("J721S2X-PM1-SOM")
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+#ifdef CONFIG_PHYS_64BIT
+ gd->ram_size = 0x1;
+#else
+ gd->ram_size = 0x8000;
+#endif
+
+ return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x1)
+ return 0x1;
+#endif
+
+ return gd->ram_top;
+}
+
+int dram_init_banksize(void)
+{
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x7fff;
+ gd->ram_size = 0x8000;
+
+#ifdef CONFIG_PHYS_64BIT
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].size = 0x37fff;
+ gd->ram_size = 0x4;
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "k3-j721s2-common-proc-board"))
+ return
[PATCH v3 12/20] dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC
There are 4 lanes in the single instance of J721S2 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by: Aswath Govindraju --- Notes: - This patch is synced from upstream kernel v5.17-rc1 tag include/dt-bindings/mux/ti-serdes.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index d417b9268b16..d3116c52ab72 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -95,4 +95,26 @@ #define AM64_SERDES0_LANE0_PCIE0 0x0 #define AM64_SERDES0_LANE0_USB 0x1 +/* J721S2 */ + +#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 +#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J721S2_SERDES0_LANE0_IP3_UNUSED0x2 +#define J721S2_SERDES0_LANE0_IP4_UNUSED0x3 + +#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 +#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J721S2_SERDES0_LANE1_USB 0x2 +#define J721S2_SERDES0_LANE1_IP4_UNUSED0x3 + +#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 +#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J721S2_SERDES0_LANE2_IP3_UNUSED0x2 +#define J721S2_SERDES0_LANE2_IP4_UNUSED0x3 + +#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 +#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J721S2_SERDES0_LANE3_USB 0x2 +#define J721S2_SERDES0_LANE3_IP4_UNUSED0x3 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */ -- 2.17.1
[PATCH v3 09/20] ram: k3-ddrss: Add support for J721S2 SoC
From: David Huang Add support for DDR subsystem in J721S2 SoC. Signed-off-by: David Huang Signed-off-by: Aswath Govindraju --- drivers/ram/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index a79594d35198..709c916a2a11 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -62,7 +62,7 @@ choice depends on K3_DDRSS prompt "K3 DDRSS Arch Support" - default K3_J721E_DDRSS if SOC_K3_J721E + default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 default K3_AM64_DDRSS if SOC_K3_AM642 config K3_J721E_DDRSS -- 2.17.1
[PATCH v3 10/20] soc: ti: k3-socinfo: Add entry for J721S2 SoC
From: David Huang Add support for J721S2 SoC identification. Signed-off-by: David Huang Signed-off-by: Aswath Govindraju --- drivers/soc/soc_ti_k3.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 9abed7d490a2..c8f7a5768775 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -14,6 +14,7 @@ #define J721E 0xbb64 #define J7200 0xbb6d #define AM64X 0xbb38 +#define J721S2 0xbb75 #define REV_SR1_0 0 #define REV_SR2_0 1 @@ -48,6 +49,9 @@ static const char *get_family_string(u32 idreg) case AM64X: family = "AM64X"; break; + case J721S2: + family = "J721S2"; + break; default: family = "Unknown Silicon"; }; -- 2.17.1
[PATCH v3 08/20] power: domain: ti: Add support for J721S2 SoC
From: David Huang
Add support for J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/power/domain/ti-power-domain.c | 5 +
include/k3-dev.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/power/domain/ti-power-domain.c
b/drivers/power/domain/ti-power-domain.c
index 4fe31686bd35..6af5dbb24191 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -81,6 +81,11 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.family = "J7200",
.data = _pd_platdata,
},
+#elif CONFIG_SOC_K3_J721S2
+ {
+ .family = "J721S2",
+ .data = _pd_platdata,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/include/k3-dev.h b/include/k3-dev.h
index 55c5057db35a..b46b8c3aabc7 100644
--- a/include/k3-dev.h
+++ b/include/k3-dev.h
@@ -77,6 +77,7 @@ struct ti_k3_pd_platdata {
extern const struct ti_k3_pd_platdata j721e_pd_platdata;
extern const struct ti_k3_pd_platdata j7200_pd_platdata;
+extern const struct ti_k3_pd_platdata j721s2_pd_platdata;
u8 ti_pd_state(struct ti_pd *pd);
u8 lpsc_get_state(struct ti_lpsc *lpsc);
--
2.17.1
[PATCH v3 07/20] clk: clk-k3: Add support for J721S2 SoC
From: David Huang
Add support for J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/clk/ti/clk-k3.c | 5 +
include/k3-clk.h| 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index e04c57eff252..74beb4d8ebda 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -68,6 +68,11 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
.family = "J7200",
.data = _clk_platdata,
},
+#elif CONFIG_SOC_K3_J721S2
+ {
+ .family = "J721S2",
+ .data = _clk_platdata,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/include/k3-clk.h b/include/k3-clk.h
index 59c76db86ead..31292b59f20c 100644
--- a/include/k3-clk.h
+++ b/include/k3-clk.h
@@ -173,6 +173,7 @@ struct ti_k3_clk_platdata {
extern const struct ti_k3_clk_platdata j721e_clk_platdata;
extern const struct ti_k3_clk_platdata j7200_clk_platdata;
+extern const struct ti_k3_clk_platdata j721s2_clk_platdata;
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
void __iomem *reg);
--
2.17.1
[PATCH v3 05/20] arm: K3: Add basic support for J721S2 SoC definition
From: David Huang
Add basic support for J721S2 SoC definition
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
Signed-off-by: Dave Gerlach
Signed-off-by: Nishanth Menon
Signed-off-by: Hari Nagalla
---
arch/arm/mach-k3/Kconfig | 15 +-
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/arm64-mmu.c | 53 +++
arch/arm/mach-k3/include/mach/hardware.h | 4 +
.../mach-k3/include/mach/j721s2_hardware.h| 60 +++
arch/arm/mach-k3/include/mach/j721s2_spl.h| 46 ++
arch/arm/mach-k3/include/mach/spl.h | 4 +
arch/arm/mach-k3/j721s2/Makefile | 5 +
arch/arm/mach-k3/j721s2/clk-data.c| 403 ++
arch/arm/mach-k3/j721s2/dev-data.c| 85
arch/arm/mach-k3/j721s2_init.c| 312 ++
include/configs/j721s2_evm.h | 191 +
12 files changed, 1174 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/mach-k3/include/mach/j721s2_hardware.h
create mode 100644 arch/arm/mach-k3/include/mach/j721s2_spl.h
create mode 100644 arch/arm/mach-k3/j721s2/Makefile
create mode 100644 arch/arm/mach-k3/j721s2/clk-data.c
create mode 100644 arch/arm/mach-k3/j721s2/dev-data.c
create mode 100644 arch/arm/mach-k3/j721s2_init.c
create mode 100644 include/configs/j721s2_evm.h
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 526f5f8b76c2..a01bf2351499 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -10,6 +10,9 @@ config SOC_K3_AM6
config SOC_K3_J721E
bool "TI's K3 based J721E SoC Family Support"
+config SOC_K3_J721S2
+ bool "TI's K3 based J721S2 SoC Family Support"
+
config SOC_K3_AM642
bool "TI's K3 based AM642 SoC Family Support"
@@ -21,7 +24,7 @@ config SYS_SOC
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
default 0x8 if SOC_K3_AM6
- default 0x10 if SOC_K3_J721E
+ default 0x10 if SOC_K3_J721E || SOC_K3_J721S2
default 0x1c if SOC_K3_AM642
help
Describes the total size of the MCU or OCMC MSRAM present on
@@ -32,7 +35,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
default 0x58000 if SOC_K3_AM6
- default 0xc if SOC_K3_J721E
+ default 0xc if SOC_K3_J721E || SOC_K3_J721S2
default 0x18 if SOC_K3_AM642
help
Describes the maximum size of the image that ROM can download
@@ -41,14 +44,14 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
config SYS_K3_MCU_SCRATCHPAD_BASE
hex
default 0x4028 if SOC_K3_AM6
- default 0x4028 if SOC_K3_J721E
+ default 0x4028 if SOC_K3_J721E || SOC_K3_J721S2
help
Describes the base address of MCU Scratchpad RAM.
config SYS_K3_MCU_SCRATCHPAD_SIZE
hex
default 0x200 if SOC_K3_AM6
- default 0x200 if SOC_K3_J721E
+ default 0x200 if SOC_K3_J721E || SOC_K3_J721S2
help
Describes the size of MCU Scratchpad RAM.
@@ -56,6 +59,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
hex
default 0x41c7fbfc if SOC_K3_AM6
default 0x41cffbfc if SOC_K3_J721E
+ default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642
help
Address at which ROM stores the value which determines if SPL
@@ -156,7 +160,7 @@ config K3_ATF_LOAD_ADDR
config K3_DM_FW
bool "Separate DM firmware image"
- depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI &&
!TI_SCI_POWER_DOMAIN
+ depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) &&
!CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
@@ -169,4 +173,5 @@ source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"
source "board/siemens/iot2050/Kconfig"
+source "board/ti/j721s2/Kconfig"
endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 47cf7b6d17a8..c0a6a9c87d8f 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 94242e1e5cc3..c7f455c8818a 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -181,6 +181,59 @@ struct mm_region *mem_map = j7200_mem_map;
#endif /* CONFIG_SOC_K3_J721E */
+#ifdef CONFIG_SOC_K3_J721S2
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
+ {
+ .virt = 0x0UL,
+
[PATCH v3 06/20] drivers: dma: Add support for J721S2
From: David Huang
Add support for DMA in J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-j721s2.c | 167 ++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 +
drivers/firmware/ti_sci_static_data.h | 40 +-
5 files changed, 208 insertions(+), 3 deletions(-)
create mode 100644 drivers/dma/ti/k3-psil-j721s2.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 0391cd3d80c9..6a4f4f1365bd 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -5,4 +5,5 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
k3-psil-data-y += k3-psil.o
k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
+k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
diff --git a/drivers/dma/ti/k3-psil-j721s2.c b/drivers/dma/ti/k3-psil-j721s2.c
new file mode 100644
index ..4c4172a4d271
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-j721s2.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1,\
+ .pdma_burst = 1,\
+ }, \
+ }
+
+#define PSIL_ETHERNET(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 16, \
+ }, \
+ }
+
+#define PSIL_SA2UL(x, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 64, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep j721s2_src_ep_map[] = {
+ /* PDMA_MCASP - McASP0-4 */
+ PSIL_PDMA_MCASP(0x4400),
+ PSIL_PDMA_MCASP(0x4401),
+ PSIL_PDMA_MCASP(0x4402),
+ PSIL_PDMA_MCASP(0x4403),
+ PSIL_PDMA_MCASP(0x4404),
+ /* PDMA_SPI_G0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4600),
+ PSIL_PDMA_XY_PKT(0x4601),
+ PSIL_PDMA_XY_PKT(0x4602),
+ PSIL_PDMA_XY_PKT(0x4603),
+ PSIL_PDMA_XY_PKT(0x4604),
+ PSIL_PDMA_XY_PKT(0x4605),
+ PSIL_PDMA_XY_PKT(0x4606),
+ PSIL_PDMA_XY_PKT(0x4607),
+ PSIL_PDMA_XY_PKT(0x4608),
+ PSIL_PDMA_XY_PKT(0x4609),
+ PSIL_PDMA_XY_PKT(0x460a),
+ PSIL_PDMA_XY_PKT(0x460b),
+ PSIL_PDMA_XY_PKT(0x460c),
+ PSIL_PDMA_XY_PKT(0x460d),
+ PSIL_PDMA_XY_PKT(0x460e),
+ PSIL_PDMA_XY_PKT(0x460f),
+ /* PDMA_SPI_G1 - SPI4-7 */
+ PSIL_PDMA_XY_PKT(0x4610),
+ PSIL_PDMA_XY_PKT(0x4611),
+ PSIL_PDMA_XY_PKT(0x4612),
+ PSIL_PDMA_XY_PKT(0x4613),
+ PSIL_PDMA_XY_PKT(0x4614),
+ PSIL_PDMA_XY_PKT(0x4615),
+ PSIL_PDMA_XY_PKT(0x4616),
+ PSIL_PDMA_XY_PKT(0x4617),
+ PSIL_PDMA_XY_PKT(0x4618),
+ PSIL_PDMA_XY_PKT(0x4619),
+
[PATCH v3 03/20] ram: k3-ddrss: Add support for multiple instances of DDR subsystems
The current driver only supports single instance of DRR subsystem. Add
support for probing multiple instances of DDR subsystem.
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/k3-ddrss.c | 138
1 file changed, 87 insertions(+), 51 deletions(-)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 95b5cf9128b0..96084d0b83d9 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -30,6 +30,9 @@
#define DDRSS_V2A_R1_MAT_REG 0x0020
#define DDRSS_ECC_CTRL_REG 0x0120
+#define SINGLE_DDR_SUBSYSTEM 0x1
+#define MULTI_DDR_SUBSYSTEM0x2
+
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
@@ -42,14 +45,12 @@ struct k3_ddrss_desc {
u32 ddr_freq2;
u32 ddr_fhs_cnt;
struct udevice *vtt_supply;
+ u32 instance;
+ lpddr4_obj *driverdt;
+ lpddr4_config config;
+ lpddr4_privatedata pd;
};
-static lpddr4_obj *driverdt;
-static lpddr4_config config;
-static lpddr4_privatedata pd;
-
-static struct k3_ddrss_desc *ddrss;
-
struct reginitdata {
u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
@@ -83,15 +84,16 @@ struct reginitdata {
offset = offset * 10 + (*i - '0'); } \
} while (0)
-static u32 k3_lpddr4_read_ddr_type(void)
+static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
{
u32 status = 0U;
u32 offset = 0U;
u32 regval = 0U;
u32 dram_class = 0U;
+ struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
- status = driverdt->readreg(, LPDDR4_CTL_REGS, offset, );
+ status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, );
if (status > 0U) {
printf("%s: Failed to read DRAM_CLASS\n", __func__);
hang();
@@ -102,23 +104,23 @@ static u32 k3_lpddr4_read_ddr_type(void)
return dram_class;
}
-static void k3_lpddr4_freq_update(void)
+static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
{
unsigned int req_type, counter;
for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS +
ddrss->instance * 0x10, 0x80,
true, 1, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
req_type = readl(ddrss->ddrss_ctrl_mmr +
-CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
+CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS +
ddrss->instance * 0x10) & 0x03;
- debug("%s: received freq change req: req type = %d, req no. =
%d\n",
- __func__, req_type, counter);
+ debug("%s: received freq change req: req type = %d, req no. =
%d, instance = %d\n",
+ __func__, req_type, counter, ddrss->instance);
if (req_type == 1)
clk_set_rate(>ddr_clk, ddrss->ddr_freq1);
@@ -132,31 +134,32 @@ static void k3_lpddr4_freq_update(void)
printf("%s: Invalid freq request type\n", __func__);
writel(0x1, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance *
0x10);
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS +
ddrss->instance * 0x10, 0x80,
false, 10, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
writel(0x0, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance *
0x10);
}
}
-static void k3_lpddr4_ack_freq_upd_req(void)
+static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
{
u32 dram_class;
+ struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
- dram_class = k3_lpddr4_read_ddr_type();
+ dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
break;
case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
- k3_lpddr4_freq_update();
+
[PATCH v3 04/20] ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems
In Multi DDR subystems with interleaving support, the following needs to
configured,
- interleaving granular size and region
- EMIFs to be enabled
- EMIFs with ecc to be enabled
- EMIF separated or interleaved
- number of cycles of unsuccessful EMIF arbitration to wait before
arbitrating for a different EMIF port, by default set to 3
Add support for configuring all the above by using a MSMC device
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/k3-ddrss.c | 158
1 file changed, 158 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 96084d0b83d9..25e3976e6569 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -33,6 +33,75 @@
#define SINGLE_DDR_SUBSYSTEM 0x1
#define MULTI_DDR_SUBSYSTEM0x2
+#define MULTI_DDR_CFG0 0x00114100
+#define MULTI_DDR_CFG1 0x00114104
+#define DDR_CFG_LOAD0x00114110
+
+enum intrlv_gran {
+ GRAN_128B,
+ GRAN_512B,
+ GRAN_2KB,
+ GRAN_4KB,
+ GRAN_16KB,
+ GRAN_32KB,
+ GRAN_512KB,
+ GRAN_1GB,
+ GRAN_1_5GB,
+ GRAN_2GB,
+ GRAN_3GB,
+ GRAN_4GB,
+ GRAN_6GB,
+ GRAN_8GB,
+ GRAN_16GB
+};
+
+enum intrlv_size {
+ SIZE_0,
+ SIZE_128MB,
+ SIZE_256MB,
+ SIZE_512MB,
+ SIZE_1GB,
+ SIZE_2GB,
+ SIZE_3GB,
+ SIZE_4GB,
+ SIZE_6GB,
+ SIZE_8GB,
+ SIZE_12GB,
+ SIZE_16GB,
+ SIZE_32GB
+};
+
+struct k3_ddrss_data {
+ u32 flags;
+};
+
+enum ecc_enable {
+ DISABLE_ALL = 0,
+ ENABLE_0,
+ ENABLE_1,
+ ENABLE_ALL
+};
+
+enum emif_config {
+ INTERLEAVE_ALL = 0,
+ SEPR0,
+ SEPR1
+};
+
+enum emif_active {
+ EMIF_0 = 1,
+ EMIF_1,
+ EMIF_ALL
+};
+
+struct k3_msmc {
+ enum intrlv_gran gran;
+ enum intrlv_size size;
+ enum ecc_enable enable;
+ enum emif_config config;
+ enum emif_active active;
+};
+
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
@@ -512,3 +581,92 @@ U_BOOT_DRIVER(k3_ddrss) = {
.probe = k3_ddrss_probe,
.priv_auto = sizeof(struct k3_ddrss_desc),
};
+
+static int k3_msmc_set_config(struct k3_msmc *msmc)
+{
+ u32 ddr_cfg0 = 0;
+ u32 ddr_cfg1 = 0;
+
+ ddr_cfg0 |= msmc->gran << 24;
+ ddr_cfg0 |= msmc->size << 16;
+ /* heartbeat_per, bit[4:0] setting to 3 is advisable */
+ ddr_cfg0 |= 3;
+
+ /* Program MULTI_DDR_CFG0 */
+ writel(ddr_cfg0, MULTI_DDR_CFG0);
+
+ ddr_cfg1 |= msmc->enable << 16;
+ ddr_cfg1 |= msmc->config << 8;
+ ddr_cfg1 |= msmc->active;
+
+ /* Program MULTI_DDR_CFG1 */
+ writel(ddr_cfg1, MULTI_DDR_CFG1);
+
+ /* Program DDR_CFG_LOAD */
+ writel(0x6000, DDR_CFG_LOAD);
+
+ return 0;
+}
+
+static int k3_msmc_probe(struct udevice *dev)
+{
+ struct k3_msmc *msmc = dev_get_priv(dev);
+ int ret = 0;
+
+ /* Read the granular size from DT */
+ ret = dev_read_u32(dev, "intrlv-gran", >gran);
+ if (ret) {
+ dev_err(dev, "missing intrlv-gran property");
+ return -EINVAL;
+ }
+
+ /* Read the interleave region from DT */
+ ret = dev_read_u32(dev, "intrlv-size", >size);
+ if (ret) {
+ dev_err(dev, "missing intrlv-size property");
+ return -EINVAL;
+ }
+
+ /* Read ECC enable config */
+ ret = dev_read_u32(dev, "ecc-enable", >enable);
+ if (ret) {
+ dev_err(dev, "missing ecc-enable property");
+ return -EINVAL;
+ }
+
+ /* Read EMIF configuration */
+ ret = dev_read_u32(dev, "emif-config", >config);
+ if (ret) {
+ dev_err(dev, "missing emif-config property");
+ return -EINVAL;
+ }
+
+ /* Read EMIF active */
+ ret = dev_read_u32(dev, "emif-active", >active);
+ if (ret) {
+ dev_err(dev, "missing emif-active property");
+ return -EINVAL;
+ }
+
+ ret = k3_msmc_set_config(msmc);
+ if (ret) {
+ dev_err(dev, "error setting msmc config");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id k3_msmc_ids[] = {
+ { .compatible = "ti,j721s2-msmc"},
+ {}
+};
+
+U_BOOT_DRIVER(k3_msmc) = {
+ .name = "k3_msmc",
+ .of_match = k3_msmc_ids,
+ .id = UCLASS_MISC,
+ .probe = k3_msmc_probe,
+ .priv_auto = sizeof(struct k3_msmc),
+ .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
--
2.17.1
[PATCH v3 02/20] ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance
Add a pointer to ddr instance int the lpddr4_privatedata_s structure for
supporting mutliple instances of DDR in the drivers.
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/lpddr4_structs_if.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h
b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
index e41cbb7ff488..f2f1210c3c4e 100644
--- a/drivers/ram/k3-ddrss/lpddr4_structs_if.h
+++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
@@ -24,6 +24,7 @@ struct lpddr4_privatedata_s {
lpddr4_infocallback infohandler;
lpddr4_ctlcallback ctlinterrupthandler;
lpddr4_phyindepcallback phyindepinterrupthandler;
+ void *ddr_instance;
};
struct lpddr4_debuginfo_s {
--
2.17.1
[PATCH v3 00/20] J721S2: Add initial support
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. * Chips and Media Wave521CL H.264/H.265 encode/decode engine See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 bootlog: - https://pastebin.ubuntu.com/p/8FfVJjVVSC/ Notes: - Patches 12, 13, 14, 15 and 16 are synced from upstream kernel v5.17-rc1 tag Changes since v2: - Removed the redundant config K3_J721S2_DDRSS and instead used K3_J721E_DDRSS - Formatted the Kconfig files to remove extra lines - Added dts files in the MAINTAINERS baord folder Changes since v1: - Removed unused serial aliases - Assigned serial2 alias for main uart8 instance - Moved aliases to respective board files Aswath Govindraju (10): ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance ram: k3-ddrss: Add support for multiple instances of DDR subsystems ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 arm: dts: Add initial support for J721S2 SoC arm: dts: Add initial support for J721S2 System on Module arm: dts: Add support for A72 specific J721S2 Common Processor Board arm: dts: k3-j721s2: Add r5 specific dt support arm: dts: k3-j721s2-ddr: Add DDR support David Huang (9): arm: K3: Add basic support for J721S2 SoC definition drivers: dma: Add support for J721S2 clk: clk-k3: Add support for J721S2 SoC power: domain: ti: Add support for J721S2 SoC ram: k3-ddrss: Add support for J721S2 SoC soc: ti: k3-socinfo: Add entry for J721S2 SoC board: ti: j721s2: Add board support for J721S2 configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig Nishanth Menon (1): remoteproc: k3_system_controller: Support optional boot_notification channel arch/arm/dts/Makefile |2 + .../k3-j721s2-common-proc-board-u-boot.dtsi | 149 + arch/arm/dts/k3-j721s2-common-proc-board.dts | 430 ++ arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi | 4387 arch/arm/dts/k3-j721s2-ddr.dtsi | 4440 + arch/arm/dts/k3-j721s2-main.dtsi | 937 arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi| 302 ++ .../dts/k3-j721s2-r5-common-proc-board.dts| 198 + arch/arm/dts/k3-j721s2-som-p0.dtsi| 173 + arch/arm/dts/k3-j721s2.dtsi | 167 + arch/arm/mach-k3/Kconfig | 15 +- arch/arm/mach-k3/Makefile |1 + arch/arm/mach-k3/arm64-mmu.c | 53 + arch/arm/mach-k3/include/mach/hardware.h |4 + .../mach-k3/include/mach/j721s2_hardware.h| 60 + arch/arm/mach-k3/include/mach/j721s2_spl.h| 46 + arch/arm/mach-k3/include/mach/spl.h |4 + arch/arm/mach-k3/j721s2/Makefile |5 + arch/arm/mach-k3/j721s2/clk-data.c| 403 ++ arch/arm/mach-k3/j721s2/dev-data.c| 85 + arch/arm/mach-k3/j721s2_init.c| 312 ++ board/ti/j721s2/Kconfig | 63 + board/ti/j721s2/MAINTAINERS | 16 + board/ti/j721s2/Makefile |8 + board/ti/j721s2/evm.c | 180 + configs/j721s2_evm_a72_defconfig | 207 + configs/j721s2_evm_r5_defconfig | 171 + .../remoteproc/k3-system-controller.txt |3 + drivers/clk/ti/clk-k3.c |5 + drivers/dma/ti/Makefile |1 + drivers/dma/ti/k3-psil-j721s2.c | 167 + drivers/dma/ti/k3-psil-priv.h |1 + drivers/dma/ti/k3-psil.c |2 +
[PATCH v3 01/20] remoteproc: k3_system_controller: Support optional boot_notification channel
From: Nishanth Menon
If there is an optional boot notification channel that an SoC uses
separate from the rx path, use the same.
Signed-off-by: Nishanth Menon
---
.../remoteproc/k3-system-controller.txt | 3 +++
drivers/remoteproc/k3_system_controller.c | 20 ++-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
index 32f4720b0d17..33dc46812ed4 100644
--- a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
+++ b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
@@ -13,6 +13,9 @@ Required properties:
"rx" for Receive channel
- mboxes: Corresponding phandles to mailbox channels.
+Optional properties:
+
+- mbox-names: "boot_notify" for Optional alternate boot notification
channel.
Example:
diff --git a/drivers/remoteproc/k3_system_controller.c
b/drivers/remoteproc/k3_system_controller.c
index 89cb90207dcb..e2affe69c678 100644
--- a/drivers/remoteproc/k3_system_controller.c
+++ b/drivers/remoteproc/k3_system_controller.c
@@ -77,14 +77,18 @@ struct k3_sysctrler_desc {
* struct k3_sysctrler_privdata - Structure representing System Controller
data.
* @chan_tx: Transmit mailbox channel
* @chan_rx: Receive mailbox channel
+ * @chan_boot_notify: Boot notification channel
* @desc: SoC description for this instance
* @seq_nr:Counter for number of messages sent.
+ * @has_boot_notify: Has separate boot notification channel
*/
struct k3_sysctrler_privdata {
struct mbox_chan chan_tx;
struct mbox_chan chan_rx;
+ struct mbox_chan chan_boot_notify;
struct k3_sysctrler_desc *desc;
u32 seq_nr;
+ bool has_boot_notify;
};
static inline
@@ -223,7 +227,8 @@ static int k3_sysctrler_start(struct udevice *dev)
debug("%s(dev=%p)\n", __func__, dev);
/* Receive the boot notification. Note that it is sent only once. */
- ret = mbox_recv(>chan_rx, , priv->desc->max_rx_timeout_us);
+ ret = mbox_recv(priv->has_boot_notify ? >chan_boot_notify :
+ >chan_rx, , priv->desc->max_rx_timeout_us);
if (ret) {
dev_err(dev, "%s: Boot Notification response failed. ret =
%d\n",
__func__, ret);
@@ -272,6 +277,19 @@ static int k3_of_to_priv(struct udevice *dev,
return ret;
}
+ /* Some SoCs may have a optional channel for boot notification. */
+ priv->has_boot_notify = 1;
+ ret = mbox_get_by_name(dev, "boot_notify", >chan_boot_notify);
+ if (ret == -ENODATA) {
+ dev_dbg(dev, "%s: Acquiring optional Boot_notify failed. ret =
%d. Using Rx\n",
+ __func__, ret);
+ priv->has_boot_notify = 0;
+ } else if (ret) {
+ dev_err(dev, "%s: Acquiring boot_notify channel failed. ret =
%d\n",
+ __func__, ret);
+ return ret;
+ }
+
return 0;
}
--
2.17.1
Re: [PATCH v2] image-board: fix wrong implementation ram disk address setup from cmdline
On Tue, Jan 18, 2022 at 3:47 AM Tom Rini wrote:
>
> On Thu, Nov 25, 2021 at 11:08:59AM +0800, Artem Lapkin wrote:
>
> > Problem
> >
> > Wrong implementation logic: ramdisk cmdline image address always ignored!
> > Next block { rd_addr = hextoul(select, NULL) } unusable for raw initrd.
> >
> > We have unbootable raw initrd images because, select_ramdisk for raw
> > initrd images ignore submited select addr and setup rd_datap value to 0
> >
> > Signed-off-by: Artem Lapkin
> > Reviewed-by: Simon Glass
> > ---
> > V2 changes
> > _ rebase to master
> > _ from
> > https://patchwork.ozlabs.org/project/uboot/patch/20211016051915.4157293-1-...@khadas.com/
> > ---
> > boot/image-board.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/boot/image-board.c b/boot/image-board.c
> > index bf8817165c..87a8f07432 100644
> > --- a/boot/image-board.c
> > +++ b/boot/image-board.c
> > @@ -334,7 +334,7 @@ static int select_ramdisk(bootm_headers_t *images,
> > const char *select, u8 arch,
> >
> > if (select) {
> > ulong default_addr;
> > - bool done = true;
> > + bool done = false;
> >
> > if (CONFIG_IS_ENABLED(FIT)) {
> > /*
> > @@ -352,13 +352,13 @@ static int select_ramdisk(bootm_headers_t *images,
> > const char *select, u8 arch,
> > _uname_config)) {
> > debug("* ramdisk: config '%s' from image at
> > 0x%08lx\n",
> > fit_uname_config, rd_addr);
> > + done = true;
> > } else if (fit_parse_subimage(select, default_addr,
> > _addr,
> > _uname_ramdisk)) {
> > debug("* ramdisk: subimage '%s' from image
> > at 0x%08lx\n",
> > fit_uname_ramdisk, rd_addr);
> > - } else {
> > - done = false;
> > + done = true;
> > }
> > }
> > if (!done) {
>
> I think we still need this? Can you please confirm and if so rebase to
> master again, sorry, thanks!
i need to check master and test it again - i'll replay soon tnx
>
> --
> Tom
Re: [PATCH v2] ARM: mvebu: x530: Add option for ECC
Hi Chris,
On 1/11/22 02:49, Chris Packham wrote:
Some older x530 boards have layout issues that cause problems for DDR.
These are usually seen as training failures but can also cause problems
after training has completed. Add an option to enable ECC leaving the
default as N which will work with both old and new boards.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
Changes in v2:
- Define Kconfig symbol for SPL.
arch/arm/mach-mvebu/Kconfig | 1 +
board/alliedtelesis/x530/Kconfig | 25 +
board/alliedtelesis/x530/x530.c | 8 +++-
3 files changed, 33 insertions(+), 1 deletion(-)
create mode 100644 board/alliedtelesis/x530/Kconfig
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index d23cc0c760f1..7388ade98d52 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -341,5 +341,6 @@ config SECURED_MODE_CSK_INDEX
source "board/solidrun/clearfog/Kconfig"
source "board/kobol/helios4/Kconfig"
+source "board/alliedtelesis/x530/Kconfig"
endif
diff --git a/board/alliedtelesis/x530/Kconfig b/board/alliedtelesis/x530/Kconfig
new file mode 100644
index ..9e676f17f39c
--- /dev/null
+++ b/board/alliedtelesis/x530/Kconfig
@@ -0,0 +1,25 @@
+menu "x530 configuration"
+ depends on TARGET_X530
+
+config X530_ECC
+ bool "Enable DDR3 ECC"
+ help
+ Some of the older x530 board have layout issues which cause problems
+ for the DDR which usually exhibit as DDR training failures or
+ problems accessing DDR after training.
+
+ The known affected boards are:
+
+ * 844-001897-00 (x530-28GTXm, x530-28GPXm, GS980MX/28PSm)
+ * 844-001948-00 (GS980MX/28)
+ * 844-002008-00 (x530L-52GTX, x530L-52GPX)
+ * 844-001974-00 (x530-52GTXm, x530-52GPXm, GS980MX/52PSm)
+
+ If you have a newer board you can set Y here, otherwise say N.
+
+config SPL_X530_ECC
+ bool
+ depends on X530_ECC
+ default X530_ECC
+
This seems a bit superfluous, as you don't really need to differentiate
between SPL and non-SPL, right?
Did you take a look at my comment about this in v1 of this patch? Here
again:
AFAIK, IS_ENABLED(CONFIG_X530_ECC) would be a solution here. There is
no need for a new SPL Kconfig option this way. Please give it a try.
Thanks,
Stefan
+endmenu
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index 866b6e68cc16..de20684f4353 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -45,6 +45,12 @@ int hws_board_topology_load(struct serdes_map
**serdes_map_array, u8 *count)
return 0;
}
+#if CONFIG_IS_ENABLED(X530_ECC)
+ #define BUS_MASK BUS_MASK_32BIT_ECC
+#else
+ #define BUS_MASK BUS_MASK_32BIT
+#endif
+
/*
* Define the DDR layout / topology here in the board file. This will
* be used by the DDR3 init code in the SPL U-Boot version to configure
@@ -66,7 +72,7 @@ static struct mv_ddr_topology_map board_topology_map = {
0, 0, /* cas_l cas_wl */
MV_DDR_TEMP_LOW,/* temperature */
MV_DDR_TIM_2T} }, /* timing */
- BUS_MASK_32BIT_ECC, /* subphys mask */
+ BUS_MASK, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined */
{ {0} },/* raw spd data */
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v3 1/1] rsa: adds rsa3072 algorithm
The 01/18/2022 07:02, Jamin Lin wrote:
> The 01/14/2022 18:14, Tom Rini wrote:
> > On Fri, Dec 10, 2021 at 02:00:55PM +0800, Jamin Lin wrote:
> >
> > > Add to support rsa 3072 bits algorithm in tools
> > > for image sign at host side and adds rsa 3072 bits
> > > verification in the image binary.
> > >
> > > Add test case in vboot for sha384 with rsa3072 algorithm testing.
> > >
> > > Signed-off-by: Jamin Lin
> > > ---
> > > include/u-boot/rsa.h| 1 +
> > > lib/rsa/rsa-verify.c| 6 +++
> > > test/py/tests/test_vboot.py | 12 +-
> > > test/py/tests/vboot/sign-configs-sha384.its | 45 +
> > > test/py/tests/vboot/sign-images-sha384.its | 42 +++
> > > tools/image-sig-host.c | 7
> > > 6 files changed, 111 insertions(+), 2 deletions(-)
> > > create mode 100644 test/py/tests/vboot/sign-configs-sha384.its
> > > create mode 100644 test/py/tests/vboot/sign-images-sha384.its
> > >
> > > diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h
> > > index 7556aa5b4b..bb56c2243c 100644
> > > --- a/include/u-boot/rsa.h
> > > +++ b/include/u-boot/rsa.h
> > > @@ -110,6 +110,7 @@ int padding_pss_verify(struct image_sign_info *info,
> > > #define RSA_DEFAULT_PADDING_NAME "pkcs-1.5"
> > >
> > > #define RSA2048_BYTES(2048 / 8)
> > > +#define RSA3072_BYTES(3072 / 8)
> > > #define RSA4096_BYTES(4096 / 8)
> > >
> > > /* This is the minimum/maximum key size we support, in bits */
> > > diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
> > > index 83f7564101..4fe487d7e5 100644
> > > --- a/lib/rsa/rsa-verify.c
> > > +++ b/lib/rsa/rsa-verify.c
> > > @@ -588,6 +588,12 @@ U_BOOT_CRYPTO_ALGO(rsa2048) = {
> > > .verify = rsa_verify,
> > > };
> > >
> > > +U_BOOT_CRYPTO_ALGO(rsa3072) = {
> > > + .name = "rsa3072",
> > > + .key_len = RSA3072_BYTES,
> > > + .verify = rsa_verify,
> > > +};
> > > +
> > > U_BOOT_CRYPTO_ALGO(rsa4096) = {
> > > .name = "rsa4096",
> > > .key_len = RSA4096_BYTES,
> > > diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
> > > index 095e00cce3..b080d482af 100644
> > > --- a/test/py/tests/test_vboot.py
> > > +++ b/test/py/tests/test_vboot.py
> > > @@ -45,6 +45,8 @@ TESTDATA = [
> > > ['sha256-pss-pad', 'sha256', '-pss', '-E -p 0x1', False, False],
> > > ['sha256-pss-required', 'sha256', '-pss', None, True, False],
> > > ['sha256-pss-pad-required', 'sha256', '-pss', '-E -p 0x1', True,
> > > True],
> > > +['sha384-basic', 'sha384', '', None, False, False],
> > > +['sha384-pad', 'sha384', '', '-E -p 0x1', False, False],
> > > ]
> > >
> > > @pytest.mark.boardspec('sandbox')
> > > @@ -180,10 +182,16 @@ def test_vboot(u_boot_console, name, sha_algo,
> > > padding, sign_options, required,
> > > name: Name of of the key (e.g. 'dev')
> > > """
> > > public_exponent = 65537
> > > +
> > > +if sha_algo == "sha384":
> > > +rsa_keygen_bits = 3072
> > > +else:
> > > +rsa_keygen_bits = 2048
> > > +
> > > util.run_and_log(cons, 'openssl genpkey -algorithm RSA -out
> > > %s%s.key '
> > > - '-pkeyopt rsa_keygen_bits:2048 '
> > > + '-pkeyopt rsa_keygen_bits:%d '
> > > '-pkeyopt rsa_keygen_pubexp:%d' %
> > > - (tmpdir, name, public_exponent))
> > > + (tmpdir, name, rsa_keygen_bits, public_exponent))
> > >
> > > # Create a certificate containing the public key
> > > util.run_and_log(cons, 'openssl req -batch -new -x509 -key
> > > %s%s.key '
> > > diff --git a/test/py/tests/vboot/sign-configs-sha384.its
> > > b/test/py/tests/vboot/sign-configs-sha384.its
> > > new file mode 100644
> > > index 00..2869401991
> > > --- /dev/null
> > > +++ b/test/py/tests/vboot/sign-configs-sha384.its
> > > @@ -0,0 +1,45 @@
> > > +/dts-v1/;
> > > +
> > > +/ {
> > > + description = "Chrome OS kernel image with one or more FDT blobs";
> > > + #address-cells = <1>;
> > > +
> > > + images {
> > > + kernel {
> > > + data = /incbin/("test-kernel.bin");
> > > + type = "kernel_noload";
> > > + arch = "sandbox";
> > > + os = "linux";
> > > + compression = "none";
> > > + load = <0x4>;
> > > + entry = <0x8>;
> > > + kernel-version = <1>;
> > > + hash-1 {
> > > + algo = "sha384";
> > > + };
> > > + };
> > > + fdt-1 {
> > > + description = "snow";
> > > + data = /incbin/("sandbox-kernel.dtb");
> > > + type = "flat_dt";
> > > + arch = "sandbox";
> > > + compression = "none";
> > > + fdt-version = <1>;
> > > +
Re: [PATCH v3 1/1] rsa: adds rsa3072 algorithm
The 01/14/2022 18:14, Tom Rini wrote:
> On Fri, Dec 10, 2021 at 02:00:55PM +0800, Jamin Lin wrote:
>
> > Add to support rsa 3072 bits algorithm in tools
> > for image sign at host side and adds rsa 3072 bits
> > verification in the image binary.
> >
> > Add test case in vboot for sha384 with rsa3072 algorithm testing.
> >
> > Signed-off-by: Jamin Lin
> > ---
> > include/u-boot/rsa.h| 1 +
> > lib/rsa/rsa-verify.c| 6 +++
> > test/py/tests/test_vboot.py | 12 +-
> > test/py/tests/vboot/sign-configs-sha384.its | 45 +
> > test/py/tests/vboot/sign-images-sha384.its | 42 +++
> > tools/image-sig-host.c | 7
> > 6 files changed, 111 insertions(+), 2 deletions(-)
> > create mode 100644 test/py/tests/vboot/sign-configs-sha384.its
> > create mode 100644 test/py/tests/vboot/sign-images-sha384.its
> >
> > diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h
> > index 7556aa5b4b..bb56c2243c 100644
> > --- a/include/u-boot/rsa.h
> > +++ b/include/u-boot/rsa.h
> > @@ -110,6 +110,7 @@ int padding_pss_verify(struct image_sign_info *info,
> > #define RSA_DEFAULT_PADDING_NAME "pkcs-1.5"
> >
> > #define RSA2048_BYTES (2048 / 8)
> > +#define RSA3072_BYTES (3072 / 8)
> > #define RSA4096_BYTES (4096 / 8)
> >
> > /* This is the minimum/maximum key size we support, in bits */
> > diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
> > index 83f7564101..4fe487d7e5 100644
> > --- a/lib/rsa/rsa-verify.c
> > +++ b/lib/rsa/rsa-verify.c
> > @@ -588,6 +588,12 @@ U_BOOT_CRYPTO_ALGO(rsa2048) = {
> > .verify = rsa_verify,
> > };
> >
> > +U_BOOT_CRYPTO_ALGO(rsa3072) = {
> > + .name = "rsa3072",
> > + .key_len = RSA3072_BYTES,
> > + .verify = rsa_verify,
> > +};
> > +
> > U_BOOT_CRYPTO_ALGO(rsa4096) = {
> > .name = "rsa4096",
> > .key_len = RSA4096_BYTES,
> > diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
> > index 095e00cce3..b080d482af 100644
> > --- a/test/py/tests/test_vboot.py
> > +++ b/test/py/tests/test_vboot.py
> > @@ -45,6 +45,8 @@ TESTDATA = [
> > ['sha256-pss-pad', 'sha256', '-pss', '-E -p 0x1', False, False],
> > ['sha256-pss-required', 'sha256', '-pss', None, True, False],
> > ['sha256-pss-pad-required', 'sha256', '-pss', '-E -p 0x1', True,
> > True],
> > +['sha384-basic', 'sha384', '', None, False, False],
> > +['sha384-pad', 'sha384', '', '-E -p 0x1', False, False],
> > ]
> >
> > @pytest.mark.boardspec('sandbox')
> > @@ -180,10 +182,16 @@ def test_vboot(u_boot_console, name, sha_algo,
> > padding, sign_options, required,
> > name: Name of of the key (e.g. 'dev')
> > """
> > public_exponent = 65537
> > +
> > +if sha_algo == "sha384":
> > +rsa_keygen_bits = 3072
> > +else:
> > +rsa_keygen_bits = 2048
> > +
> > util.run_and_log(cons, 'openssl genpkey -algorithm RSA -out
> > %s%s.key '
> > - '-pkeyopt rsa_keygen_bits:2048 '
> > + '-pkeyopt rsa_keygen_bits:%d '
> > '-pkeyopt rsa_keygen_pubexp:%d' %
> > - (tmpdir, name, public_exponent))
> > + (tmpdir, name, rsa_keygen_bits, public_exponent))
> >
> > # Create a certificate containing the public key
> > util.run_and_log(cons, 'openssl req -batch -new -x509 -key
> > %s%s.key '
> > diff --git a/test/py/tests/vboot/sign-configs-sha384.its
> > b/test/py/tests/vboot/sign-configs-sha384.its
> > new file mode 100644
> > index 00..2869401991
> > --- /dev/null
> > +++ b/test/py/tests/vboot/sign-configs-sha384.its
> > @@ -0,0 +1,45 @@
> > +/dts-v1/;
> > +
> > +/ {
> > + description = "Chrome OS kernel image with one or more FDT blobs";
> > + #address-cells = <1>;
> > +
> > + images {
> > + kernel {
> > + data = /incbin/("test-kernel.bin");
> > + type = "kernel_noload";
> > + arch = "sandbox";
> > + os = "linux";
> > + compression = "none";
> > + load = <0x4>;
> > + entry = <0x8>;
> > + kernel-version = <1>;
> > + hash-1 {
> > + algo = "sha384";
> > + };
> > + };
> > + fdt-1 {
> > + description = "snow";
> > + data = /incbin/("sandbox-kernel.dtb");
> > + type = "flat_dt";
> > + arch = "sandbox";
> > + compression = "none";
> > + fdt-version = <1>;
> > + hash-1 {
> > + algo = "sha384";
> > + };
> > + };
> > + };
> > + configurations {
> > + default = "conf-1";
> > + conf-1 {
> > +
[PATCH v3 4/4] arm: kirkwood: Pogoplug-V4 : Add board implementation files
Note: currently the fdt_get_phy_addr function in this file is duplicate in this board and many other Kirkwood boards (eg. Sheevaplug, GoFlex Home, etc.). This function is being factored out into common area by another patch. And because it was written for flattree only, the patch is being rewritten to use livetree calls. Signed-off-by: Tony Dinh --- Changes in v3: - Squash board file small patches into one patch Changes in v2: - Move constants to .c file and remove header file board/cloudengines/pogo_v4/MAINTAINERS | 6 + board/cloudengines/pogo_v4/Makefile | 10 ++ board/cloudengines/pogo_v4/kwbimage.cfg | 148 board/cloudengines/pogo_v4/pogo_v4.c| 220 4 files changed, 384 insertions(+) create mode 100644 board/cloudengines/pogo_v4/MAINTAINERS create mode 100644 board/cloudengines/pogo_v4/Makefile create mode 100644 board/cloudengines/pogo_v4/kwbimage.cfg create mode 100644 board/cloudengines/pogo_v4/pogo_v4.c diff --git a/board/cloudengines/pogo_v4/MAINTAINERS b/board/cloudengines/pogo_v4/MAINTAINERS new file mode 100644 index 00..35fd7858b7 --- /dev/null +++ b/board/cloudengines/pogo_v4/MAINTAINERS @@ -0,0 +1,6 @@ +POGO_V4 BOARD +M: Tony Dinh +S: Maintained +F: board/cloudengines/pogo_v4/ +F: include/configs/pogo_v4.h +F: configs/pogo_v4_defconfig diff --git a/board/cloudengines/pogo_v4/Makefile b/board/cloudengines/pogo_v4/Makefile new file mode 100644 index 00..511bf5ff7e --- /dev/null +++ b/board/cloudengines/pogo_v4/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2014-2021 Tony Dinh +# +# Based on +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# + +obj-y := pogo_v4.o diff --git a/board/cloudengines/pogo_v4/kwbimage.cfg b/board/cloudengines/pogo_v4/kwbimage.cfg new file mode 100644 index 00..f6294fe313 --- /dev/null +++ b/board/cloudengines/pogo_v4/kwbimage.cfg @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2012 +# David Purdy +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar marvell.com> + +# Boot Media configurations (DONE) +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME) +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=3 @ 200MHz (need CL=3 @ 200MHz?) +DATA 0xffd01400 0x43000618 # DDR Configuration register +# bit13-0: 0x200 (200 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xffd01404 0x34143000 # DDR Controller Control Low +# bit 4:0=addr/cmd in smame cycle +# bit 5:0=clk is driven during self refresh, we don't care for APX +# bit 6:0=use recommended falling edge of clk for addr/cmd +# bit14:0=input buffer always powered up +# bit18:1=cpu lock transaction enabled +# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31:0=no additional STARTBURST delay + +DATA 0xffd01408 0x11012227 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20:TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x0819 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xffd01410 0x0001 # DDR Address Control (changed to Dockstar vals) +# bit1-0: 00, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16:0, Cs0AddrSel +# bit17:0, Cs1AddrSel +# bit18:0, Cs2AddrSel +# bit19:0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xffd01414 0x # DDR Open Pages Control +# bit0:0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xffd01418 0x # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xffd0141c 0x0632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5(<= change to CL=3 ?) +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery +# bit12:0, PD must be zero +# bit31-13: 0 required + +DATA 0xffd01420 0x0040 # DDR Extended Mode +# bit0:0, DDR DLL enabled +# bit1:0, DDR
[PATCH v3 3/4] arm: kirkwood: Pogoplug-V4 : Add Kconfig files
Add Kconfig files for Pogoplug V4 board Signed-off-by: Tony Dinh --- Changes in v3: - Migrate symbols from board include header to Kconfig arch/arm/mach-kirkwood/Kconfig | 6 ++ board/cloudengines/pogo_v4/Kconfig | 16 2 files changed, 22 insertions(+) create mode 100644 board/cloudengines/pogo_v4/Kconfig diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index c060cc8546..382b836267 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -51,6 +51,11 @@ config TARGET_POGO_E02 select FEROCEON_88FR131 select KW88F6281 +config TARGET_POGO_V4 + bool "Pogoplug V4 Board" + select FEROCEON_88FR131 + select KW88F6192 + config TARGET_DNS325 bool "dns325 Board" select FEROCEON_88FR131 @@ -123,6 +128,7 @@ source "board/Marvell/guruplug/Kconfig" source "board/Marvell/sheevaplug/Kconfig" source "board/buffalo/lsxl/Kconfig" source "board/cloudengines/pogo_e02/Kconfig" +source "board/cloudengines/pogo_v4/Kconfig" source "board/d-link/dns325/Kconfig" source "board/iomega/iconnect/Kconfig" source "board/keymile/Kconfig" diff --git a/board/cloudengines/pogo_v4/Kconfig b/board/cloudengines/pogo_v4/Kconfig new file mode 100644 index 00..db3b76b4d4 --- /dev/null +++ b/board/cloudengines/pogo_v4/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2014-2021 Tony Dinh +# +if TARGET_POGO_V4 + +config SYS_BOARD + default "pogo_v4" + +config SYS_VENDOR + default "cloudengines" + +config SYS_CONFIG_NAME + default "pogo_v4" + +endif -- 2.30.2
[PATCH v3 2/4] arm: kirkwood: Pogoplug V4 : Add board include header and defconfig files
Add board include header and defconfig files for Pogoplug V4
Signed-off-by: Tony Dinh
---
Changes in v3:
- Migrate config symbols from board include header to defconfig
- Remove obsolete config symbols from header file
- Don't use ifdefs for unselectable config symbols in header file
Changes in v2:
- Use canonical format for defconfig file
configs/pogo_v4_defconfig | 79 +++
include/configs/pogo_v4.h | 56 +++
2 files changed, 135 insertions(+)
create mode 100644 configs/pogo_v4_defconfig
create mode 100644 include/configs/pogo_v4.h
diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig
new file mode 100644
index 00..5490067b9e
--- /dev/null
+++ b/configs/pogo_v4_defconfig
@@ -0,0 +1,79 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/cloudengines/pogo_v4/kwbimage.cfg"
+CONFIG_SYS_TEXT_BASE=0x60
+CONFIG_TARGET_POGO_V4=y
+CONFIG_ENV_SIZE=0x2
+CONFIG_ENV_OFFSET=0xC
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogoplug-series-4"
+CONFIG_IDENT_STRING="\nPogoplug V4"
+CONFIG_SYS_LOAD_ADDR=0x80
+CONFIG_BOOTSTAGE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="setenv bootargs ${bootargs_console}; run bootcmd_usb;
bootm 0x0080 0x0110 0x2c0"
+CONFIG_USE_PREBOOT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Pogo_V4> "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:2M(u-boot),3M(uImage),3M(uImage2),8M(failsafe),112M(root)"
+CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SATA_MV=y
+CONFIG_KIRKWOOD_GPIO=y
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MVEBU_MMC=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_DM_ETH=y
+CONFIG_MVGBE=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_NAND=y
diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h
new file mode 100644
index 00..d94d49505a
--- /dev/null
+++ b/include/configs/pogo_v4.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014-2022 Tony Dinh
+ *
+ * Based on
+ * Copyright (C) 2012
+ * David Purdy
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ * Written-by: Prafulla Wadaskar
+ */
+
+#ifndef _CONFIG_POGO_V4_H
+#define _CONFIG_POGO_V4_H
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "dtb_file=/boot/dts/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"\
+ "mtdids=nand0=orion_nand\0"\
+ "bootargs_console=console=ttyS0,115200\0" \
+ "bootcmd_usb=usb start; load usb 0:1 0x0080 /boot/uImage; " \
+ "load usb 0:1 0x0110 /boot/uInitrd; " \
+ "load usb 0:1 0x2c0 $dtb_file\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEATURE_COMMAND_EDITING /* for netconsole */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+
+/*
+ * Support large disk for SATA and USB
+ */
+#define CONFIG_SYS_64BIT_LBA
+#define CONFIG_LBA48
+
+#endif /* _CONFIG_POGO_V4_H */
--
2.30.2
[PATCH v3 1/4] arm: kirkwood: Pogoplug-V4 : Add DTS files
Add DTS files for Pogoplug V4 board
Reviewed-by: Stefan Roese
Signed-off-by: Tony Dinh
---
(no changes since v2)
Changes in v2:
- Use mainline Linux DTS version
arch/arm/dts/Makefile | 1 +
arch/arm/dts/kirkwood-pogoplug-series-4.dts | 180
2 files changed, 181 insertions(+)
create mode 100644 arch/arm/dts/kirkwood-pogoplug-series-4.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1b65e65eb8..ce33a4b52b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \
kirkwood-openrd-client.dtb \
kirkwood-openrd-ultimate.dtb \
kirkwood-pogo_e02.dtb \
+ kirkwood-pogoplug-series-4.dtb \
kirkwood-sheevaplug.dtb
dtb-$(CONFIG_MACH_S900) += \
diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4.dts
b/arch/arm/dts/kirkwood-pogoplug-series-4.dts
new file mode 100644
index 00..5aa4669ae2
--- /dev/null
+++ b/arch/arm/dts/kirkwood-pogoplug-series-4.dts
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4
+ * inspired by the board files made by Kevin Mihelich for ArchLinux,
+ * and their DTS file.
+ *
+ * Copyright (C) 2015 Linus Walleij
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6192.dtsi"
+#include
+
+/ {
+ model = "Cloud Engines PogoPlug Series 4";
+ compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192",
+"marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x 0x0800>;
+ };
+
+ chosen {
+ stdout-path = "uart0:115200n8";
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <_button_eject>;
+ pinctrl-names = "default";
+
+ eject {
+ debounce-interval = <50>;
+ wakeup-source;
+ linux,code = ;
+ label = "Eject Button";
+ gpios = < 29 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <_led_green _led_red>;
+ pinctrl-names = "default";
+
+ health {
+ label = "pogoplugv4:green:health";
+ gpios = < 22 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ fault {
+ label = "pogoplugv4:red:fault";
+ gpios = < 24 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+ {
+ pmx_sata0: pmx-sata0 {
+ marvell,pins = "mpp21";
+ marvell,function = "sata0";
+ };
+
+ pmx_sata1: pmx-sata1 {
+ marvell,pins = "mpp20";
+ marvell,function = "sata1";
+ };
+
+ pmx_sdio_cd: pmx-sdio-cd {
+ marvell,pins = "mpp27";
+ marvell,function = "gpio";
+ };
+
+ pmx_sdio_wp: pmx-sdio-wp {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+
+ pmx_button_eject: pmx-button-eject {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_green: pmx-led-green {
+ marvell,pins = "mpp22";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_red: pmx-led-red {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+/*
+ * This PCIE controller has a USB 3.0 XHCI controller at 1,0
+ */
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ pinctrl-0 = <_sata0 _sata1>;
+ pinctrl-names = "default";
+ nr-ports = <1>;
+};
+
+ {
+ status = "okay";
+ pinctrl-0 = <_sdio _sdio_cd _sdio_wp>;
+ pinctrl-names = "default";
+ cd-gpios = < 27 GPIO_ACTIVE_LOW>;
+ wp-gpios = < 28 GPIO_ACTIVE_HIGH>;
+};
+
+ {
+ /* 128 MiB of NAND flash */
+ chip-delay = <40>;
+ status = "okay";
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x 0x20>;
+ read-only;
+ };
+
+ partition@20 {
+ label = "uImage";
+ reg = <0x0020 0x30>;
+ };
+
+ partition@50 {
+ label = "uImage2";
+ reg = <0x0050 0x30>;
+ };
+
+ partition@80
[PATCH v3 0/4] arm: kirkwood: Add support for Pogoplug V4
Pogoplug V4 specifications: Kirkwood 88F6192 SoC 800 MHz CPU 1Gbs Ethernet 128 MB RAM 128 MB NAND 1x USB 2.0 2x USB 3.0 (on PCIe bus) 1 SDHC slot 1x External SATA port (USM enclosure form factor slot) Changes in v3: - Migrate config symbols from board include header to defconfig - Remove obsolete config symbols from header file - Don't use ifdefs for unselectable config symbols in header file - Migrate symbols from board include header to Kconfig - Squash board file small patches into one patch Changes in v2: - Use mainline Linux DTS version - Use canonical format for defconfig file - Move constants to .c file and remove header file Tony Dinh (4): arm: kirkwood: Pogoplug-V4 : Add DTS files arm: kirkwood: Pogoplug V4 : Add board include header and defconfig files arm: kirkwood: Pogoplug-V4 : Add Kconfig files arm: kirkwood: Pogoplug-V4 : Add board implementation files arch/arm/dts/Makefile | 1 + arch/arm/dts/kirkwood-pogoplug-series-4.dts | 180 arch/arm/mach-kirkwood/Kconfig | 6 + board/cloudengines/pogo_v4/Kconfig | 16 ++ board/cloudengines/pogo_v4/MAINTAINERS | 6 + board/cloudengines/pogo_v4/Makefile | 10 + board/cloudengines/pogo_v4/kwbimage.cfg | 148 + board/cloudengines/pogo_v4/pogo_v4.c| 220 configs/pogo_v4_defconfig | 79 +++ include/configs/pogo_v4.h | 56 + 10 files changed, 722 insertions(+) create mode 100644 arch/arm/dts/kirkwood-pogoplug-series-4.dts create mode 100644 board/cloudengines/pogo_v4/Kconfig create mode 100644 board/cloudengines/pogo_v4/MAINTAINERS create mode 100644 board/cloudengines/pogo_v4/Makefile create mode 100644 board/cloudengines/pogo_v4/kwbimage.cfg create mode 100644 board/cloudengines/pogo_v4/pogo_v4.c create mode 100644 configs/pogo_v4_defconfig create mode 100644 include/configs/pogo_v4.h -- 2.30.2
Re: [PATCH v2 01/20] remoteproc: k3_system_controller: Support optional boot_notification channel
Hi Tomi, On 17/01/22 7:24 pm, Tom Rini wrote: > On Mon, Jan 17, 2022 at 12:22:52PM +0530, Aswath Govindraju wrote: >> Hi Tom, >> >> On 17/01/22 11:01 am, Aswath Govindraju wrote: >>> Hi Tom, >>> >>> On 13/01/22 7:42 pm, Tom Rini wrote: On Tue, Jan 11, 2022 at 01:25:26PM +0530, Aswath Govindraju wrote: > From: Nishanth Menon > > If there is an optional boot notification channel that an SoC uses > separate from the rx path, use the same. > > Signed-off-by: Nishanth Menon > --- > .../remoteproc/k3-system-controller.txt | 3 +++ > drivers/remoteproc/k3_system_controller.c | 20 ++- > 2 files changed, 22 insertions(+), 1 deletion(-) Binding docs are rst these days, so we should sync with upstream and then this property is already there, right? >>> >>> I will create a followup patch to convert documentation to rst. Also, >>> about the property, mbox-names property is already present but >>> "boot_notify" is a newly added channel and not are required property. >>> So, this was additionally added. >>> >> >> One more question regarding documentation, should it be changed to rst >> or yaml, as this is a device tree binding? > > I mis-spoke, yeah. It should be yaml and pushed upstream first, then > brought back here. > I am sorry, I have one more question. This above documentation file is not present in kernel documentation, so I did not understand how can this be pushed there first. Also, as converting to yaml would be a different work. Wouldn't it be better to separate that work from this series? Thanks, Aswath
[PATCH v9 11/11] test/py: efi_capsule: check the results in case of CAPSULE_AUTHENTICATE
Before the capsule authentication is supported, this test script works
correctly, but with the feature enabled, most tests will fail due to
unsigned capsules.
So check the results depending on CAPSULE_AUTHENTICATE or not.
Signed-off-by: AKASHI Takahiro
Reviewed-by: Simon Glass
---
.../test_efi_capsule/test_capsule_firmware.py | 26 ---
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
index 9cc973560fa1..6e803f699f2f 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
@@ -148,6 +148,8 @@ class TestEfiCapsuleFirmwareFit(object):
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
+capsule_auth = u_boot_config.buildconfig.get(
+'config_efi_capsule_authenticate')
with u_boot_console.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
# make sure that dfu_alt_info exists even persistent variables
@@ -171,12 +173,18 @@ class TestEfiCapsuleFirmwareFit(object):
'sf probe 0:0',
'sf read 400 10 10',
'md.b 400 10'])
-assert 'u-boot:New' in ''.join(output)
+if capsule_auth:
+assert 'u-boot:Old' in ''.join(output)
+else:
+assert 'u-boot:New' in ''.join(output)
output = u_boot_console.run_command_list([
'sf read 400 15 10',
'md.b 400 10'])
-assert 'u-boot-env:New' in ''.join(output)
+if capsule_auth:
+assert 'u-boot-env:Old' in ''.join(output)
+else:
+assert 'u-boot-env:New' in ''.join(output)
def test_efi_capsule_fw3(
self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -215,6 +223,8 @@ class TestEfiCapsuleFirmwareFit(object):
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
+capsule_auth = u_boot_config.buildconfig.get(
+'config_efi_capsule_authenticate')
with u_boot_console.log.section('Test Case 3-b, after reboot'):
if not capsule_early:
# make sure that dfu_alt_info exists even persistent variables
@@ -246,7 +256,10 @@ class TestEfiCapsuleFirmwareFit(object):
'sf probe 0:0',
'sf read 400 10 10',
'md.b 400 10'])
-assert 'u-boot:New' in ''.join(output)
+if capsule_auth:
+assert 'u-boot:Old' in ''.join(output)
+else:
+assert 'u-boot:New' in ''.join(output)
def test_efi_capsule_fw4(
self, u_boot_config, u_boot_console, efi_capsule_data):
@@ -285,6 +298,8 @@ class TestEfiCapsuleFirmwareFit(object):
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
+capsule_auth = u_boot_config.buildconfig.get(
+'config_efi_capsule_authenticate')
with u_boot_console.log.section('Test Case 4-b, after reboot'):
if not capsule_early:
# make sure that dfu_alt_info exists even persistent variables
@@ -313,4 +328,7 @@ class TestEfiCapsuleFirmwareFit(object):
'sf probe 0:0',
'sf read 400 10 10',
'md.b 400 10'])
-assert 'u-boot:New' in ''.join(output)
+if capsule_auth:
+assert 'u-boot:Old' in ''.join(output)
+else:
+assert 'u-boot:New' in ''.join(output)
--
2.33.0
[PATCH v9 10/11] test/py: efi_capsule: add a test for "--guid" option
This test scenario tests a new feature of mkeficapsule, "--guid" option,
which allows us to specify FMP driver's guid explicitly at the command
line.
Signed-off-by: AKASHI Takahiro
---
test/py/tests/test_efi_capsule/conftest.py| 3 +
.../test_efi_capsule/test_capsule_firmware.py | 67 +++
2 files changed, 70 insertions(+)
diff --git a/test/py/tests/test_efi_capsule/conftest.py
b/test/py/tests/test_efi_capsule/conftest.py
index a5a25c53dcb4..9076087a12b7 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -86,6 +86,9 @@ def efi_capsule_data(request, u_boot_config):
check_call('cd %s; %s/tools/mkeficapsule --index 1 --raw
u-boot.bin.new Test02' %
(data_dir, u_boot_config.build_dir),
shell=True)
+check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid
E2BB9C06-70E9-4B14-97A3-5A7913176E3F u-boot.bin.new Test03' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
if capsule_auth_enabled:
# firmware signed with proper key
check_call('cd %s; '
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
index 9eeaae27d626..9cc973560fa1 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
@@ -247,3 +247,70 @@ class TestEfiCapsuleFirmwareFit(object):
'sf read 400 10 10',
'md.b 400 10'])
assert 'u-boot:New' in ''.join(output)
+
+def test_efi_capsule_fw4(
+self, u_boot_config, u_boot_console, efi_capsule_data):
+"""
+Test Case 4 - Test "--guid" option of mkeficapsule
+ The test scenario is the same as Case 3.
+"""
+disk_img = efi_capsule_data
+with u_boot_console.log.section('Test Case 4-a, before reboot'):
+output = u_boot_console.run_command_list([
+'host bind 0 %s' % disk_img,
+'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""',
+'efidebug boot order 1',
+'env set -e -nv -bs -rt OsIndications =0x0004',
+'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x10
0x5;u-boot-env raw 0x15 0x20"',
+'env save'])
+
+# initialize content
+output = u_boot_console.run_command_list([
+'sf probe 0:0',
+'fatload host 0:1 400 %s/u-boot.bin.old' %
CAPSULE_DATA_DIR,
+'sf write 400 10 10',
+'sf read 500 10 10',
+'md.b 500 10'])
+assert 'Old' in ''.join(output)
+
+# place a capsule file
+output = u_boot_console.run_command_list([
+'fatload host 0:1 400 %s/Test03' % CAPSULE_DATA_DIR,
+'fatwrite host 0:1 400 %s/Test03 $filesize' %
CAPSULE_INSTALL_DIR,
+'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+assert 'Test03' in ''.join(output)
+
+# reboot
+u_boot_console.restart_uboot()
+
+capsule_early = u_boot_config.buildconfig.get(
+'config_efi_capsule_on_disk_early')
+with u_boot_console.log.section('Test Case 4-b, after reboot'):
+if not capsule_early:
+# make sure that dfu_alt_info exists even persistent variables
+# are not available.
+output = u_boot_console.run_command_list([
+'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x10
0x5;u-boot-env raw 0x15 0x20"',
+'host bind 0 %s' % disk_img,
+'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+assert 'Test03' in ''.join(output)
+
+# need to run uefi command to initiate capsule handling
+output = u_boot_console.run_command(
+'env print -e Capsule')
+
+output = u_boot_console.run_command_list(['efidebug capsule esrt'])
+
+# ensure that EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID is in the
ESRT.
+assert 'E2BB9C06-70E9-4B14-97A3-5A7913176E3F' in ''.join(output)
+
+output = u_boot_console.run_command_list([
+'host bind 0 %s' % disk_img,
+'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+assert 'Test03' not in ''.join(output)
+
+output = u_boot_console.run_command_list([
+'sf probe 0:0',
+'sf read 400 10 10',
+'md.b 400 10'])
+assert 'u-boot:New' in ''.join(output)
--
2.33.0
[PATCH v9 09/11] test/py: efi_capsule: align with the syntax change of mkeficapsule
Since the syntax of mkeficapsule was changed in the previous commit,
we need to modify command line arguments in a pytest script.
Signed-off-by: AKASHI Takahiro
Reviewed-by: Simon Glass
---
test/py/tests/test_efi_capsule/conftest.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/test/py/tests/test_efi_capsule/conftest.py
b/test/py/tests/test_efi_capsule/conftest.py
index 27c05971ca32..a5a25c53dcb4 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -80,10 +80,10 @@ def efi_capsule_data(request, u_boot_config):
check_call('cd %s; %s/tools/mkimage -f uboot_bin_env.its
uboot_bin_env.itb' %
(data_dir, u_boot_config.build_dir),
shell=True)
-check_call('cd %s; %s/tools/mkeficapsule --fit uboot_bin_env.itb
--index 1 Test01' %
+check_call('cd %s; %s/tools/mkeficapsule --index 1 --fit
uboot_bin_env.itb Test01' %
(data_dir, u_boot_config.build_dir),
shell=True)
-check_call('cd %s; %s/tools/mkeficapsule --raw u-boot.bin.new --index
1 Test02' %
+check_call('cd %s; %s/tools/mkeficapsule --index 1 --raw
u-boot.bin.new Test02' %
(data_dir, u_boot_config.build_dir),
shell=True)
if capsule_auth_enabled:
--
2.33.0
[PATCH v9 08/11] tools: mkeficapsule: allow for specifying GUID explicitly
The existing options, "--fit" and "--raw," are only used to put a proper
GUID in a capsule header, where GUID identifies a particular FMP (Firmware
Management Protocol) driver which then would handle the firmware binary in
a capsule. In fact, mkeficapsule does the exact same job in creating
a capsule file whatever the firmware binary type is.
To prepare for the future extension, the command syntax will be a bit
modified to allow users to specify arbitrary GUID for their own FMP driver.
OLD:
[--fit | --raw ]
NEW:
[--fit | --raw | --guid ]
Signed-off-by: AKASHI Takahiro
Reviewed-by: Simon Glass
---
doc/develop/uefi/uefi.rst | 4 +-
doc/mkeficapsule.1| 26
tools/Makefile| 1 +
tools/mkeficapsule.c | 87 ---
4 files changed, 85 insertions(+), 33 deletions(-)
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index 7e1eb8256259..a1a2afd60bbc 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -375,8 +375,8 @@ and used by the steps highlighted below.
--private-key CRT.key \
--certificate CRT.crt \
--index 1 --instance 0 \
- [--fit | --raw ] \
-
+ [--fit | --raw | --guid
4. Insert the signature list into a device tree in the following format::
diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1
index 680362f5c4e9..8babb27ee8b2 100644
--- a/doc/mkeficapsule.1
+++ b/doc/mkeficapsule.1
@@ -8,7 +8,7 @@ mkeficapsule \- Generate EFI capsule file for U-Boot
.SH SYNOPSIS
.B mkeficapsule
-.RI [ options "] " capsule-file
+.RI [ options "] " image-blob " " capsule-file
.SH "DESCRIPTION"
.B mkeficapsule
@@ -24,7 +24,7 @@ In this case, the update will be authenticated by verifying
the signature
before applying.
.B mkeficapsule
-supports two different format of image files:
+takes any type of image files, including:
.TP
.I raw image
format is a single binary blob of any type of firmware.
@@ -36,18 +36,30 @@ multiple binary blobs in a single capsule file.
This type of image file can be generated by
.BR mkimage .
+.PP
+If you want to use other types than above two, you should explicitly
+specify a guid for the FMP driver.
+
.SH "OPTIONS"
One of
-.BR --fit " or " --raw
+.BR --fit ", " --raw " or " --guid
option must be specified.
.TP
-.BI "-f\fR,\fB --fit " fit-image-file
-Specify a FIT image file
+.BR -f ", " --fit
+Indicate that the blob is a FIT image file
.TP
-.BI "-r\fR,\fB --raw " raw-image-file
-Specify a raw image file
+.BR -r ", " --raw
+Indicate that the blob is a raw image file
+
+.TP
+.BI "-g\fR,\fB --guid " guid-string
+Specify guid for image blob type. The format is:
+----
+
+The first three elements are in little endian, while the rest
+is in big endian.
.TP
.BI "-i\fR,\fB --index " index
diff --git a/tools/Makefile b/tools/Makefile
index afca08e2941a..cbf83a252caa 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -242,6 +242,7 @@ ifeq ($(CONFIG_TOOLS_LIBCRYPTO),y)
HOSTLDLIBS_mkeficapsule += \
$(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl
-lcrypto")
endif
+HOSTLDLIBS_mkeficapsule += -luuid
hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
# We build some files with extra pedantic flags to try to minimize things
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 66dc2ee20912..161affdd15eb 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -15,7 +15,7 @@
#include
#include
-
+#include
#include
#ifdef CONFIG_TOOLS_LIBCRYPTO
#include
@@ -38,14 +38,15 @@ efi_guid_t efi_guid_image_type_uboot_raw =
efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
#ifdef CONFIG_TOOLS_LIBCRYPTO
-static const char *opts_short = "f:r:i:I:v:p:c:m:dh";
+static const char *opts_short = "frg:i:I:v:p:c:m:dh";
#else
-static const char *opts_short = "f:r:i:I:v:h";
+static const char *opts_short = "frg:i:I:v:h";
#endif
static struct option options[] = {
- {"fit", required_argument, NULL, 'f'},
- {"raw", required_argument, NULL, 'r'},
+ {"fit", no_argument, NULL, 'f'},
+ {"raw", no_argument, NULL, 'r'},
+ {"guid", required_argument, NULL, 'g'},
{"index", required_argument, NULL, 'i'},
{"instance", required_argument, NULL, 'I'},
#ifdef CONFIG_TOOLS_LIBCRYPTO
@@ -60,11 +61,12 @@ static struct option options[] = {
static void print_usage(void)
{
- fprintf(stderr, "Usage: %s [options] \n"
+ fprintf(stderr, "Usage: %s [options] \n"
"Options:\n"
- "\t-f, --fitnew FIT image file\n"
- "\t-r, --rawnew raw image file\n"
+ "\t-f, --fit FIT image type\n"
+ "\t-r, --raw raw image type\n"
+ "\t-g, --guid guid for image blob type\n"
"\t-i, --index update image index\n"
"\t-I,
[PATCH v9 07/11] test/py: efi_capsule: add image authentication test
Add a couple of test cases against capsule image authentication
for capsule-on-disk, where only a signed capsule file with the verified
signature will be applied to the system.
Due to the difficulty of embedding a public key (esl file) in U-Boot
binary during pytest setup time, all the keys/certificates are pre-created.
Signed-off-by: AKASHI Takahiro
Reviewed-by: Simon Glass
Acked-by: Ilias Apalodimas
---
.../py/tests/test_efi_capsule/capsule_defs.py | 5 +
test/py/tests/test_efi_capsule/conftest.py| 52 +++-
test/py/tests/test_efi_capsule/signature.dts | 10 +
.../test_capsule_firmware_signed.py | 254 ++
4 files changed, 318 insertions(+), 3 deletions(-)
create mode 100644 test/py/tests/test_efi_capsule/signature.dts
create mode 100644
test/py/tests/test_efi_capsule/test_capsule_firmware_signed.py
diff --git a/test/py/tests/test_efi_capsule/capsule_defs.py
b/test/py/tests/test_efi_capsule/capsule_defs.py
index 4fd6353c2040..59b40f11bd1d 100644
--- a/test/py/tests/test_efi_capsule/capsule_defs.py
+++ b/test/py/tests/test_efi_capsule/capsule_defs.py
@@ -3,3 +3,8 @@
# Directories
CAPSULE_DATA_DIR = '/EFI/CapsuleTestData'
CAPSULE_INSTALL_DIR = '/EFI/UpdateCapsule'
+
+# v1.5.1 or earlier of efitools has a bug in sha256 calculation, and
+# you need build a newer version on your own.
+# The path must terminate with '/' if it is not null.
+EFITOOLS_PATH = ''
diff --git a/test/py/tests/test_efi_capsule/conftest.py
b/test/py/tests/test_efi_capsule/conftest.py
index 6ad5608cd71c..27c05971ca32 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -10,13 +10,13 @@ import pytest
from capsule_defs import *
#
-# Fixture for UEFI secure boot test
+# Fixture for UEFI capsule test
#
-
@pytest.fixture(scope='session')
def efi_capsule_data(request, u_boot_config):
-"""Set up a file system to be used in UEFI capsule test.
+"""Set up a file system to be used in UEFI capsule and
+ authentication test.
Args:
request: Pytest request object.
@@ -40,6 +40,36 @@ def efi_capsule_data(request, u_boot_config):
check_call('mkdir -p %s' % data_dir, shell=True)
check_call('mkdir -p %s' % install_dir, shell=True)
+capsule_auth_enabled = u_boot_config.buildconfig.get(
+'config_efi_capsule_authenticate')
+if capsule_auth_enabled:
+# Create private key (SIGNER.key) and certificate (SIGNER.crt)
+check_call('cd %s; '
+ 'openssl req -x509 -sha256 -newkey rsa:2048 '
+'-subj /CN=TEST_SIGNER/ -keyout SIGNER.key '
+'-out SIGNER.crt -nodes -days 365'
+ % data_dir, shell=True)
+check_call('cd %s; %scert-to-efi-sig-list SIGNER.crt SIGNER.esl'
+ % (data_dir, EFITOOLS_PATH), shell=True)
+
+# Update dtb adding capsule certificate
+check_call('cd %s; '
+ 'cp %s/test/py/tests/test_efi_capsule/signature.dts .'
+ % (data_dir, u_boot_config.source_dir), shell=True)
+check_call('cd %s; '
+ 'dtc -@ -I dts -O dtb -o signature.dtbo signature.dts; '
+ 'fdtoverlay -i %s/arch/sandbox/dts/test.dtb '
+'-o test_sig.dtb signature.dtbo'
+ % (data_dir, u_boot_config.build_dir), shell=True)
+
+# Create *malicious* private key (SIGNER2.key) and certificate
+# (SIGNER2.crt)
+check_call('cd %s; '
+ 'openssl req -x509 -sha256 -newkey rsa:2048 '
+'-subj /CN=TEST_SIGNER/ -keyout SIGNER2.key '
+'-out SIGNER2.crt -nodes -days 365'
+ % data_dir, shell=True)
+
# Create capsule files
# two regions: one for u-boot.bin and the other for u-boot.env
check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n
u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old -> u-boot.env.old; echo -n
u-boot-env:New > u-boot.env.new' % data_dir,
@@ -56,6 +86,22 @@ def efi_capsule_data(request, u_boot_config):
check_call('cd %s; %s/tools/mkeficapsule --raw u-boot.bin.new --index
1 Test02' %
(data_dir, u_boot_config.build_dir),
shell=True)
+if capsule_auth_enabled:
+# firmware signed with proper key
+check_call('cd %s; '
+ '%s/tools/mkeficapsule --index 1 --monotonic-count 1 '
+'--private-key SIGNER.key --certificate SIGNER.crt
'
+'--raw u-boot.bin.new Test11'
+ % (data_dir, u_boot_config.build_dir),
+ shell=True)
+# firmware signed with *mal* key
+check_call('cd %s; '
+
[PATCH v9 06/11] doc: update UEFI document for usage of mkeficapsule
Now we can use mkeficapsule command instead of EDK-II's script to create a signed capsule file. So update the instruction for capsule authentication. Signed-off-by: AKASHI Takahiro Reviewed-by: Simon Glass Acked-by: Ilias Apalodimas --- doc/develop/uefi/uefi.rst | 147 +++--- 1 file changed, 74 insertions(+), 73 deletions(-) diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index 43fb10f7978e..7e1eb8256259 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -284,37 +284,56 @@ Support has been added for the UEFI capsule update feature which enables updating the U-Boot image using the UEFI firmware management protocol (FMP). The capsules are not passed to the firmware through the UpdateCapsule runtime service. Instead, capsule-on-disk -functionality is used for fetching the capsule from the EFI System -Partition (ESP) by placing the capsule file under the -\EFI\UpdateCapsule directory. - -The directory \EFI\UpdateCapsule is checked for capsules only within the -EFI system partition on the device specified in the active boot option -determined by reference to BootNext variable or BootOrder variable processing. -The active Boot Variable is the variable with highest priority BootNext or -within BootOrder that refers to a device found to be present. Boot variables -in BootOrder but referring to devices not present are ignored when determining -active boot variable. -Before starting a capsule update make sure your capsules are installed in the -correct ESP partition or set BootNext. +functionality is used for fetching capsules from the EFI System +Partition (ESP) by placing capsule files under the directory:: + +\EFI\UpdateCapsule + +The directory is checked for capsules only within the +EFI system partition on the device specified in the active boot option, +which is determined by Boot variable in BootNext, or if not, the highest +priority one within BootOrder. Any Boot variables referring to devices +not present are ignored when determining the active boot option. + +Please note that capsules will be applied in the alphabetic order of +capsule file names. + +Creating a capsule file +*** + +A capsule file can be created by using tools/mkeficapsule. +To build this tool, enable:: + +CONFIG_TOOLS_MKEFICAPSULE=y +CONFIG_TOOLS_LIBCRYPTO=y + +Run the following command:: + +.. code-block:: console + +$ mkeficapsule \ + --index 1 --instance 0 \ + [--fit | --raw ] \ + Performing the update * -Since U-boot doesn't currently support SetVariable at runtime there's a Kconfig -option (CONFIG_EFI_IGNORE_OSINDICATIONS) to disable the OsIndications variable -check. If that option is enabled just copy your capsule to \EFI\UpdateCapsule. +Put capsule files under the directory mentioned above. +Then, following the UEFI specification, you'll need to set +the EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED +bit in OsIndications variable with:: -If that option is disabled, you'll need to set the OsIndications variable with:: +.. code-block:: console => setenv -e -nv -bs -rt -v OsIndications =0x04 -Finally, the capsule update can be initiated either by rebooting the board, -which is the preferred method, or by issuing the following command:: +Since U-boot doesn't currently support SetVariable at runtime, its value +won't be taken over across the reboot. If this is the case, you can skip +this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS) +set. -=> efidebug capsule disk-update - -**The efidebug command is should only be used during debugging/development.** +Finally, the capsule update can be initiated by rebooting the board. Enabling Capsule Authentication *** @@ -324,82 +343,64 @@ be updated by verifying the capsule signature. The capsule signature is computed and prepended to the capsule payload at the time of capsule generation. This signature is then verified by using the public key stored as part of the X509 certificate. This certificate is -in the form of an efi signature list (esl) file, which is embedded as -part of U-Boot. +in the form of an efi signature list (esl) file, which is embedded in +a device tree. The capsule authentication feature can be enabled through the following config, in addition to the configs listed above for capsule update:: CONFIG_EFI_CAPSULE_AUTHENTICATE=y -CONFIG_EFI_CAPSULE_KEY_PATH= The public and private keys used for the signing process are generated -and used by the steps highlighted below:: +and used by the steps highlighted below. -1. Install utility commands on your host - * OPENSSL +1. Install utility commands on your host + * openssl * efitools -2. Create signing keys and certificate files on your host +2. Create signing keys and certificate files on your host:: + +.. code-block:: console
[PATCH v9 05/11] tools: mkeficapsule: add man page
Add a man page for mkeficapsule command. Signed-off-by: AKASHI Takahiro Reviewed-by: Simon Glass Acked-by: Ilias Apalodimas --- MAINTAINERS| 1 + doc/mkeficapsule.1 | 99 ++ 2 files changed, 100 insertions(+) create mode 100644 doc/mkeficapsule.1 diff --git a/MAINTAINERS b/MAINTAINERS index 90666ce376cd..2b73feffafe0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -726,6 +726,7 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git F: doc/api/efi.rst F: doc/develop/uefi/* +F: doc/mkeficapsule.1 F: doc/usage/bootefi.rst F: drivers/rtc/emul_rtc.c F: include/capitalization.h diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1 new file mode 100644 index ..680362f5c4e9 --- /dev/null +++ b/doc/mkeficapsule.1 @@ -0,0 +1,99 @@ +.\" SPDX-License-Identifier: GPL-2.0+ +.\" Copyright (c) 2021, Linaro Limited +.\"written by AKASHI Takahiro +.TH MAEFICAPSULE 1 "May 2021" + +.SH NAME +mkeficapsule \- Generate EFI capsule file for U-Boot + +.SH SYNOPSIS +.B mkeficapsule +.RI [ options "] " capsule-file + +.SH "DESCRIPTION" +.B mkeficapsule +command is used to create an EFI capsule file for use with the U-Boot +EFI capsule update. +A capsule file may contain various type of firmware blobs which +are to be applied to the system and must be placed in the specific +directory on the UEFI system partition. +An update will be automatically executed at next reboot. + +Optionally, a capsule file can be signed with a given private key. +In this case, the update will be authenticated by verifying the signature +before applying. + +.B mkeficapsule +supports two different format of image files: +.TP +.I raw image +format is a single binary blob of any type of firmware. + +.TP +.I FIT (Flattened Image Tree) image +format is the same as used in the new uImage format and allows for +multiple binary blobs in a single capsule file. +This type of image file can be generated by +.BR mkimage . + +.SH "OPTIONS" +One of +.BR --fit " or " --raw +option must be specified. + +.TP +.BI "-f\fR,\fB --fit " fit-image-file +Specify a FIT image file + +.TP +.BI "-r\fR,\fB --raw " raw-image-file +Specify a raw image file + +.TP +.BI "-i\fR,\fB --index " index +Specify an image index + +.TP +.BI "-I\fR,\fB --instance " instance +Specify a hardware instance + +.TP +.BR -h ", " --help +Print a help message + +.PP +With signing, +.BR --private-key ", " --certificate " and " --monotonic-count +are all mandatory. + +.TP +.BI "-p\fR,\fB --private-key " private-key-file +Specify signer's private key file in PEM + +.TP +.BI "-c\fR,\fB --certificate " certificate-file +Specify signer's certificate file in EFI certificate list format + +.TP +.BI "-m\fR,\fB --monotonic-count " count +Specify a monotonic count which is set to be monotonically incremented +at every firmware update. + +.TP +.B "-d\fR,\fB --dump_sig" +Dump signature data into *.p7 file + +.PP +.SH FILES +.TP +.I /EFI/UpdateCapsule +The directory in which all capsule files be placed + +.SH SEE ALSO +.BR mkimage (1) + +.SH AUTHORS +Written by AKASHI Takahiro + +.SH HOMEPAGE +http://www.denx.de/wiki/U-Boot/WebHome -- 2.33.0
[PATCH v9 04/11] tools: mkeficapsule: add firmware image signing
With this enhancement, mkeficapsule will be able to sign a capsule
file when it is created. A signature added will be used later
in the verification at FMP's SetImage() call.
To do that, we need specify additional command parameters:
-monotonic-cout : monotonic count
-private-key : private key file
-certificate : certificate file
Only when all of those parameters are given, a signature will be added
to a capsule file.
Users are expected to maintain and increment the monotonic count at
every time of the update for each firmware image.
Signed-off-by: AKASHI Takahiro
Reviewed-by: Simon Glass
Acked-by: Ilias Apalodimas
---
tools/Makefile | 4 +
tools/eficapsule.h | 115 +
tools/mkeficapsule.c | 398 +++
3 files changed, 487 insertions(+), 30 deletions(-)
create mode 100644 tools/eficapsule.h
diff --git a/tools/Makefile b/tools/Makefile
index 766c0674f4a0..afca08e2941a 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -238,6 +238,10 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs
hostprogs-$(CONFIG_ASN1_COMPILER) += asn1_compiler
HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include
+ifeq ($(CONFIG_TOOLS_LIBCRYPTO),y)
+HOSTLDLIBS_mkeficapsule += \
+ $(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl
-lcrypto")
+endif
hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
# We build some files with extra pedantic flags to try to minimize things
diff --git a/tools/eficapsule.h b/tools/eficapsule.h
new file mode 100644
index ..8c1560bb0671
--- /dev/null
+++ b/tools/eficapsule.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2021 Linaro Limited
+ * Author: AKASHI Takahiro
+ *
+ * derived from efi.h and efi_api.h to make the file POSIX-compliant
+ */
+
+#ifndef _EFI_CAPSULE_H
+#define _EFI_CAPSULE_H
+
+#include
+#include /* WIN_CERTIFICATE */
+
+/*
+ * Gcc's predefined attributes are not recognized by clang.
+ */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif
+
+#ifndef __aligned
+#define __aligned(x) __attribute__((__aligned__(x)))
+#endif
+
+typedef struct {
+ uint8_t b[16];
+} efi_guid_t __aligned(8);
+
+#define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
+ {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, \
+ ((a) >> 24) & 0xff, \
+ (b) & 0xff, ((b) >> 8) & 0xff, \
+ (c) & 0xff, ((c) >> 8) & 0xff, \
+ (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }
+
+#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \
+ EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \
+0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a)
+
+#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID \
+ EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \
+0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47)
+
+#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \
+ EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \
+0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f)
+
+#define EFI_CERT_TYPE_PKCS7_GUID \
+ EFI_GUID(0x4aafd29d, 0x68df, 0x49ee, 0x8a, 0xa9, \
+0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7)
+
+/* flags */
+#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x0001
+
+struct efi_capsule_header {
+ efi_guid_t capsule_guid;
+ uint32_t header_size;
+ uint32_t flags;
+ uint32_t capsule_image_size;
+} __packed;
+
+struct efi_firmware_management_capsule_header {
+ uint32_t version;
+ uint16_t embedded_driver_count;
+ uint16_t payload_item_count;
+ uint32_t item_offset_list[];
+} __packed;
+
+/* image_capsule_support */
+#define CAPSULE_SUPPORT_AUTHENTICATION 0x0001
+
+struct efi_firmware_management_capsule_image_header {
+ uint32_t version;
+ efi_guid_t update_image_type_id;
+ uint8_t update_image_index;
+ uint8_t reserved[3];
+ uint32_t update_image_size;
+ uint32_t update_vendor_code_size;
+ uint64_t update_hardware_instance;
+ uint64_t image_capsule_support;
+} __packed;
+
+/**
+ * win_certificate_uefi_guid - A certificate that encapsulates
+ * a GUID-specific signature
+ *
+ * @hdr: Windows certificate header
+ * @cert_type: Certificate type
+ * @cert_data: Certificate data
+ */
+struct win_certificate_uefi_guid {
+ WIN_CERTIFICATE hdr;
+ efi_guid_t cert_type;
+ uint8_t cert_data[];
+} __packed;
+
+/**
+ * efi_firmware_image_authentication - Capsule authentication method
+ * descriptor
+ *
+ * This structure describes an authentication information for
+ * a capsule with IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED set
+ * and should be included as part of the capsule.
+ * Only EFI_CERT_TYPE_PKCS7_GUID is accepted.
+ *
+ * @monotonic_count: Count to prevent replay
+ * @auth_info: Authentication info
+ */
+struct efi_firmware_image_authentication {
+ uint64_t monotonic_count;
+ struct
[PATCH v9 03/11] tools: build mkeficapsule with tools-only_defconfig
Add CONFIG_TOOLS_MKEFICAPSULE. Then we want to always build mkeficapsule if tools-only_defconfig is used. Signed-off-by: AKASHI Takahiro Reviewed-by: Simon Glass --- configs/tools-only_defconfig | 1 + tools/Kconfig| 8 tools/Makefile | 3 +-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index f482c9a1c1b0..5427797dd4c3 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -31,3 +31,4 @@ CONFIG_I2C_EDID=y # CONFIG_VIRTIO_MMIO is not set # CONFIG_VIRTIO_PCI is not set # CONFIG_VIRTIO_SANDBOX is not set +CONFIG_TOOLS_MKEFICAPSULE=y diff --git a/tools/Kconfig b/tools/Kconfig index 91ce8ae3e516..117c921da3fe 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -90,4 +90,12 @@ config TOOLS_SHA512 help Enable SHA512 support in the tools builds +config TOOLS_MKEFICAPSULE + bool "Build efimkcapsule command" + default y if EFI_CAPSULE_ON_DISK + help + This command allows users to create a UEFI capsule file and, + optionally sign that file. If you want to enable UEFI capsule + update feature on your target, you certainly need this. + endmenu diff --git a/tools/Makefile b/tools/Makefile index 1763f44cac43..766c0674f4a0 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -238,8 +238,7 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs hostprogs-$(CONFIG_ASN1_COMPILER) += asn1_compiler HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include -mkeficapsule-objs := mkeficapsule.o $(LIBFDT_OBJS) -hostprogs-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += mkeficapsule +hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule # We build some files with extra pedantic flags to try to minimize things # that won't build on some weird host compiler -- though there are lots of -- 2.33.0
[PATCH v9 02/11] tools: mkeficapsule: rework the code a little bit
Abstract common routines to make the code easily understandable.
No functional change.
Signed-off-by: AKASHI Takahiro
Reviewed-by: Simon Glass
---
tools/mkeficapsule.c | 239 ++-
1 file changed, 167 insertions(+), 72 deletions(-)
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 19d5eea3cb59..ee3e489c0b30 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -51,33 +52,36 @@ static struct option options[] = {
static void print_usage(void)
{
fprintf(stderr, "Usage: %s [options] \n"
- "Options:\n"
-
- "\t-f, --fitnew FIT image file\n"
- "\t-r, --rawnew raw image file\n"
- "\t-i, --index update image index\n"
- "\t-I, --instanceupdate hardware instance\n"
- "\t-h, --help print a help message\n",
- tool_name);
+ "Options:\n"
+
+ "\t-f, --fitnew FIT image file\n"
+ "\t-r, --rawnew raw image file\n"
+ "\t-i, --index update image index\n"
+ "\t-I, --instanceupdate hardware instance\n"
+ "\t-h, --help print a help message\n",
+ tool_name);
}
-static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
- unsigned long index, unsigned long instance)
+/**
+ * read_bin_file - read a firmware binary file
+ * @bin: Path to a firmware binary file
+ * @data: Pointer to pointer of allocated buffer
+ * @bin_size: Size of allocated buffer
+ *
+ * Read out a content of binary, @bin, into @data.
+ * A caller should free @data.
+ *
+ * Return:
+ * * 0 - on success
+ * * -1 - on failure
+ */
+static int read_bin_file(char *bin, void **data, off_t *bin_size)
{
- struct efi_capsule_header header;
- struct efi_firmware_management_capsule_header capsule;
- struct efi_firmware_management_capsule_image_header image;
- FILE *f, *g;
+ FILE *g;
struct stat bin_stat;
- u8 *data;
+ void *buf;
size_t size;
- u64 offset;
-
-#ifdef DEBUG
- fprintf(stderr, "For output: %s\n", path);
- fprintf(stderr, "\tbin: %s\n\ttype: %pUl\n", bin, guid);
- fprintf(stderr, "\tindex: %ld\n\tinstance: %ld\n", index, instance);
-#endif
+ int ret = 0;
g = fopen(bin, "r");
if (!g) {
@@ -86,19 +90,123 @@ static int create_fwbin(char *path, char *bin, efi_guid_t
*guid,
}
if (stat(bin, _stat) < 0) {
fprintf(stderr, "cannot determine the size of %s\n", bin);
- goto err_1;
+ ret = -1;
+ goto err;
+ }
+ if (bin_stat.st_size > SIZE_MAX) {
+ fprintf(stderr, "file size is too large for malloc: %s\n", bin);
+ ret = -1;
+ goto err;
}
- data = malloc(bin_stat.st_size);
- if (!data) {
+ buf = malloc(bin_stat.st_size);
+ if (!buf) {
fprintf(stderr, "cannot allocate memory: %zx\n",
(size_t)bin_stat.st_size);
- goto err_1;
+ ret = -1;
+ goto err;
+ }
+
+ size = fread(buf, 1, bin_stat.st_size, g);
+ if (size < bin_stat.st_size) {
+ fprintf(stderr, "read failed (%zx)\n", size);
+ ret = -1;
+ goto err;
}
+
+ *data = buf;
+ *bin_size = bin_stat.st_size;
+err:
+ fclose(g);
+
+ return ret;
+}
+
+/**
+ * write_capsule_file - write a capsule file
+ * @bin: FILE stream
+ * @data: Pointer to data
+ * @bin_size: Size of data
+ *
+ * Write out data, @data, with the size @bin_size.
+ *
+ * Return:
+ * * 0 - on success
+ * * -1 - on failure
+ */
+static int write_capsule_file(FILE *f, void *data, size_t size, const char
*msg)
+{
+ size_t size_written;
+
+ size_written = fwrite(data, 1, size, f);
+ if (size_written < size) {
+ fprintf(stderr, "%s: write failed (%zx != %zx)\n", msg,
+ size_written, size);
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * create_fwbin - create an uefi capsule file
+ * @path: Path to a created capsule file
+ * @bin: Path to a firmware binary to encapsulate
+ * @guid: GUID of related FMP driver
+ * @index: Index number in capsule
+ * @instance: Instance number in capsule
+ * @mcount:Monotonic count in authentication information
+ * @private_file: Path to a private key file
+ * @cert_file: Path to a certificate file
+ *
+ * This function actually does the job of creating an uefi capsule file.
+ * All the arguments must be supplied.
+ * If either @private_file ror @cert_file is NULL, the capsule file
+ * won't be signed.
+ *
+ *
[PATCH v9 01/11] tools: mkeficapsule: output messages to stderr instead of stdout
All the error messages should be printed out to stderr.
Signed-off-by: AKASHI Takahiro
---
tools/mkeficapsule.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 4995ba4e0c2a..19d5eea3cb59 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -50,7 +50,7 @@ static struct option options[] = {
static void print_usage(void)
{
- printf("Usage: %s [options] \n"
+ fprintf(stderr, "Usage: %s [options] \n"
"Options:\n"
"\t-f, --fitnew FIT image file\n"
@@ -74,28 +74,29 @@ static int create_fwbin(char *path, char *bin, efi_guid_t
*guid,
u64 offset;
#ifdef DEBUG
- printf("For output: %s\n", path);
- printf("\tbin: %s\n\ttype: %pUl\n", bin, guid);
- printf("\tindex: %ld\n\tinstance: %ld\n", index, instance);
+ fprintf(stderr, "For output: %s\n", path);
+ fprintf(stderr, "\tbin: %s\n\ttype: %pUl\n", bin, guid);
+ fprintf(stderr, "\tindex: %ld\n\tinstance: %ld\n", index, instance);
#endif
g = fopen(bin, "r");
if (!g) {
- printf("cannot open %s\n", bin);
+ fprintf(stderr, "cannot open %s\n", bin);
return -1;
}
if (stat(bin, _stat) < 0) {
- printf("cannot determine the size of %s\n", bin);
+ fprintf(stderr, "cannot determine the size of %s\n", bin);
goto err_1;
}
data = malloc(bin_stat.st_size);
if (!data) {
- printf("cannot allocate memory: %zx\n",
(size_t)bin_stat.st_size);
+ fprintf(stderr, "cannot allocate memory: %zx\n",
+ (size_t)bin_stat.st_size);
goto err_1;
}
f = fopen(path, "w");
if (!f) {
- printf("cannot open %s\n", path);
+ fprintf(stderr, "cannot open %s\n", path);
goto err_2;
}
header.capsule_guid = efi_guid_fm_capsule;
@@ -109,7 +110,7 @@ static int create_fwbin(char *path, char *bin, efi_guid_t
*guid,
size = fwrite(, 1, sizeof(header), f);
if (size < sizeof(header)) {
- printf("write failed (%zx)\n", size);
+ fprintf(stderr, "write failed (%zx)\n", size);
goto err_3;
}
@@ -118,13 +119,13 @@ static int create_fwbin(char *path, char *bin, efi_guid_t
*guid,
capsule.payload_item_count = 1;
size = fwrite(, 1, sizeof(capsule), f);
if (size < (sizeof(capsule))) {
- printf("write failed (%zx)\n", size);
+ fprintf(stderr, "write failed (%zx)\n", size);
goto err_3;
}
offset = sizeof(capsule) + sizeof(u64);
size = fwrite(, 1, sizeof(offset), f);
if (size < sizeof(offset)) {
- printf("write failed (%zx)\n", size);
+ fprintf(stderr, "write failed (%zx)\n", size);
goto err_3;
}
@@ -141,17 +142,17 @@ static int create_fwbin(char *path, char *bin, efi_guid_t
*guid,
size = fwrite(, 1, sizeof(image), f);
if (size < sizeof(image)) {
- printf("write failed (%zx)\n", size);
+ fprintf(stderr, "write failed (%zx)\n", size);
goto err_3;
}
size = fread(data, 1, bin_stat.st_size, g);
if (size < bin_stat.st_size) {
- printf("read failed (%zx)\n", size);
+ fprintf(stderr, "read failed (%zx)\n", size);
goto err_3;
}
size = fwrite(data, 1, bin_stat.st_size, f);
if (size < bin_stat.st_size) {
- printf("write failed (%zx)\n", size);
+ fprintf(stderr, "write failed (%zx)\n", size);
goto err_3;
}
@@ -194,7 +195,7 @@ int main(int argc, char **argv)
switch (c) {
case 'f':
if (file) {
- printf("Image already specified\n");
+ fprintf(stderr, "Image already specified\n");
return -1;
}
file = optarg;
@@ -202,7 +203,7 @@ int main(int argc, char **argv)
break;
case 'r':
if (file) {
- printf("Image already specified\n");
+ fprintf(stderr, "Image already specified\n");
return -1;
}
file = optarg;
@@ -234,7 +235,7 @@ int main(int argc, char **argv)
if (create_fwbin(argv[optind], file, guid, index, instance)
< 0) {
- printf("Creating firmware capsule failed\n");
+ fprintf(stderr, "Creating firmware capsule failed\n");
exit(EXIT_FAILURE);
[PATCH v9 00/11] efi_loader: capsule: improve capsule authentication support
As I proposed and discussed in [1] and [2], I have made a couple of improvements on the current implementation of capsule update in this patch set. * add signing feature to mkeficapsule * add "--guid" option to mkeficapsule * add man page of mkeficapsule * update uefi document regarding capsule update * revise pytests [1] https://lists.denx.de/pipermail/u-boot/2021-April/447918.html [2] https://lists.denx.de/pipermail/u-boot/2021-July/455292.html Prerequisite patches None Test * locally passed the pytest which is included in this patch series on sandbox built. (CONFIG_EFI_CAPSULE_AUTHENTICATE should explicitly be turned on in order to exercise the authentication code.) Changes === v9 (Jan 18, 2022) * rebased on v2022.01 * print the output messages to stderr (patch#1,#2, #4 and #6) * use SIZE_MAX instead of (u32)!0U (patch#2) * revise and re-format the man page of mkeficapsule (patch#5) * add "code-block:: console" directives for command line examples in a ReST document (patch#6) * describe the case when a trailing '/' in EFITOOLS_PATH is needed (patch#7) * describe UUID data as a binary rather than a string (patch#8) * drop fdtsig.sh-related patches (patch#12,#13 in v8) v8 (Dec 20, 2021) * rebase on v2022.01-rc3 * move the definition of CONFIG_TOOLS_MKEFICAPSULE to a proper patch (patch#2) v7 (Nov 16, 2021) * rebased on pre-v2022.01-rc2 * drop already-merged patch * check for a size of firmware binary file (patch#1) * enable mkeficapsule in tools-only_defconfig (patch#2) * define eficapsule.h and include it from mkeficapsule (patch#3) Hopefully, the tool can now compile on non-linux host. v6 (Nov 02, 2021) * rebased on pre-v2022.01-rc1 * add patch#2 to rework/refactor the code for better readability (patch#2) * use exit(EXIT_SUCCESS/FAILURE) (patch#3) * truncate >80chars lines in pytest scripts (patch#6) v5 (Oct 27, 2021) * rebased on pre-v2022.01-rc1 (WIP/26Oct2021) * drop already-merged patches * drop __weak from efi_get_public_key_data() (patch#1) * describe the format of public key node in device tree (patch#4) * re-order patches by grouping closely-related patches (patch#6-8) * modify pytest to make the test results correctly verified either with or without CONFIG_EFI_CAPSULE_AUTHENTICATE (patch#9) * add RFCs for embedding public keys during the build process (patch#10,11) v4 (Oct 7, 2021) * rebased on v2021.10 * align with "Revert "efi_capsule: Move signature from DTB to .rodata"" * add more missing *revert* commits (patch#1,#2,#3) * add fdtsig.sh, replacing dtb support in mkeficapsule (patch#4) * update/revise the man/uefi doc (patch#6,#7) * fix a bug in parsing guid string (patch#8) * add a test for "--guid" option (patch#10) * use dtb-based authentication test as done in v1 (patch#11) v3 (Aug 31, 2021) * rebased on v2021.10-rc3 * remove pytest-related patches * add function descriptions in mkeficapsule.c * correct format specifiers in printf() * let main() return 0 or -1 only * update doc/develop/uefi/uefi.rst for syntax change of mkeficapsule v2 (July 28, 2021) * rebased on v2021.10-rc* * removed dependency on target's configuration * removed fdtsig.sh and others * add man page * update the UEFI document * add dedicate defconfig for testing on sandbox * add gitlab CI support * add "--guid" option to mkeficapsule (yet rather RFC) Initial release (May 12, 2021) * based on v2021.07-rc2 AKASHI Takahiro (11): tools: mkeficapsule: output messages to stderr instead of stdout tools: mkeficapsule: rework the code a little bit tools: build mkeficapsule with tools-only_defconfig tools: mkeficapsule: add firmware image signing tools: mkeficapsule: add man page doc: update UEFI document for usage of mkeficapsule test/py: efi_capsule: add image authentication test tools: mkeficapsule: allow for specifying GUID explicitly test/py: efi_capsule: align with the syntax change of mkeficapsule test/py: efi_capsule: add a test for "--guid" option test/py: efi_capsule: check the results in case of CAPSULE_AUTHENTICATE MAINTAINERS | 1 + configs/tools-only_defconfig | 1 + doc/develop/uefi/uefi.rst | 147 ++-- doc/mkeficapsule.1| 111 +++ .../py/tests/test_efi_capsule/capsule_defs.py | 5 + test/py/tests/test_efi_capsule/conftest.py| 59 +- test/py/tests/test_efi_capsule/signature.dts | 10 + .../test_efi_capsule/test_capsule_firmware.py | 91 ++- .../test_capsule_firmware_signed.py | 254 +++ tools/Kconfig | 8 + tools/Makefile| 8 +- tools/eficapsule.h| 115 +++ tools/mkeficapsule.c | 707 +++--- 13 files changed, 1317 insertions(+), 200 deletions(-) create mode 100644 doc/mkeficapsule.1 create mode 100644 test/py/tests/test_efi_capsule/signature.dts create mode 100644
Re: [PATCH 2/8] lib: printf code %pUs for GUID text representation
On Sun, Jan 16, 2022 at 04:14:35PM +0100, Heinrich Schuchardt wrote:
> In different places text representations are used for GUIDs, e.g.
>
> * command efidebug
> * command part list for GPT partitions
>
> To allow reducing code duplication introduce a new printf code %pUs.
> It will call uuid_guid_get_str() to get a text representation. If none is
> found it will fallback to %pUl and print a hexadecimal representation.
I think the idea is good.
Moreover, when you add a new format specifier to printf() routine,
it would also be good to add a document so that people won't bustle
around the code to find an appropriate format string.
Not only to "%pU*", but also others including "%pD" and "%ls" that you added.
# See linux's Documentation/core-api/printk-formats.rst.
-Takahiro Akashi
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/vsprintf.c | 13 +++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/lib/vsprintf.c b/lib/vsprintf.c
> index de9f236b90..2c0cc1647e 100644
> --- a/lib/vsprintf.c
> +++ b/lib/vsprintf.c
> @@ -255,8 +255,8 @@ static char *number(char *buf, char *end, u64 num,
> return buf;
> }
>
> -static char *string(char *buf, char *end, char *s, int field_width,
> - int precision, int flags)
> +static char *string(char *buf, char *end, const char *s, int field_width,
> + int precision, int flags)
> {
> int len, i;
>
> @@ -387,12 +387,14 @@ static char *ip4_addr_string(char *buf, char *end, u8
> *addr, int field_width,
> * %pUB: 01020304-0506-0708-090A-0B0C0D0E0F10
> * %pUl: 04030201-0605-0807-090a-0b0c0d0e0f10
> * %pUL: 04030201-0605-0807-090A-0B0C0D0E0F10
> + * %pUs: GUID text representation if known or fallback to %pUl
> */
> static char *uuid_string(char *buf, char *end, u8 *addr, int field_width,
>int precision, int flags, const char *fmt)
> {
> char uuid[UUID_STR_LEN + 1];
> int str_format;
> + const char *str;
>
> switch (*(++fmt)) {
> case 'L':
> @@ -404,6 +406,13 @@ static char *uuid_string(char *buf, char *end, u8 *addr,
> int field_width,
> case 'B':
> str_format = UUID_STR_FORMAT_STD | UUID_STR_UPPER_CASE;
> break;
> + case 's':
> + str = uuid_guid_get_str(addr);
> + if (str)
> + return string(buf, end, str,
> + field_width, precision, flags);
> + str_format = UUID_STR_FORMAT_GUID;
> + break;
> default:
> str_format = UUID_STR_FORMAT_STD;
> break;
> --
> 2.33.1
>
Re: [PATCH V3] usb: ehci-mx6: Enable OTG detection on imx8mm and imx8mn
On Mon, Jan 17, 2022 at 7:46 PM Fabio Estevam wrote: > > Hi Adam, > > On Mon, Jan 17, 2022 at 9:21 PM Adam Ford wrote: > > > > The imx8mm and imx8mn appear compatible with imx7d-usb > > flags in the OTG driver. If the dr_mode is defined as > > host or peripheral, the device appears to operate correctly, > > however the auto host/peripheral detection results in an error. > > > > The solution isn't just adding checks for imx8mm and imx8mn to > > the check for imx7, because the USB clock needs to be running > > to read from the USBNC_PHY_STATUS_OFFSET register or it will hang. > > > > Marek requested that I not enable the clocks in ehci_usb_of_to_plat, > > so I modified that function to return an unknown state if the > > device tree does not explicitly state whether it is a host > > or a peripheral. > > > > When the driver probes, it looks to see if it's in the unknown > > state, and only then will it read the register to auto-detect. > > > > Signed-off-by: Adam Ford > > --- > > V3: Keep ehci_usb_of_to_plat but add the ability to return > > and unknown state instead of reading the register. > > If the probe determines the states is unknown, it will > > query the register after the clocks have been enabled. > > Because of the slight behavior change, I removed any > > review or tested tags. > > Unfortunately, v3 breaks 'ums 0 mmc 0' on the imx7s-warp board. Thanks for testing it. I am not really sure what's significantly different between them. Do you get any errors when you run UMS? > > The eMMC is no longer mounted and the board hangs.
Re: [PATCH V3] usb: ehci-mx6: Enable OTG detection on imx8mm and imx8mn
Hi Adam, On Mon, Jan 17, 2022 at 9:21 PM Adam Ford wrote: > > The imx8mm and imx8mn appear compatible with imx7d-usb > flags in the OTG driver. If the dr_mode is defined as > host or peripheral, the device appears to operate correctly, > however the auto host/peripheral detection results in an error. > > The solution isn't just adding checks for imx8mm and imx8mn to > the check for imx7, because the USB clock needs to be running > to read from the USBNC_PHY_STATUS_OFFSET register or it will hang. > > Marek requested that I not enable the clocks in ehci_usb_of_to_plat, > so I modified that function to return an unknown state if the > device tree does not explicitly state whether it is a host > or a peripheral. > > When the driver probes, it looks to see if it's in the unknown > state, and only then will it read the register to auto-detect. > > Signed-off-by: Adam Ford > --- > V3: Keep ehci_usb_of_to_plat but add the ability to return > and unknown state instead of reading the register. > If the probe determines the states is unknown, it will > query the register after the clocks have been enabled. > Because of the slight behavior change, I removed any > review or tested tags. Unfortunately, v3 breaks 'ums 0 mmc 0' on the imx7s-warp board. The eMMC is no longer mounted and the board hangs.
Re: [PATCH V3] usb: ehci-mx6: Enable OTG detection on imx8mm and imx8mn
On Mon, Jan 17, 2022 at 4:21 PM Adam Ford wrote:
>
> The imx8mm and imx8mn appear compatible with imx7d-usb
> flags in the OTG driver. If the dr_mode is defined as
> host or peripheral, the device appears to operate correctly,
> however the auto host/peripheral detection results in an error.
>
> The solution isn't just adding checks for imx8mm and imx8mn to
> the check for imx7, because the USB clock needs to be running
> to read from the USBNC_PHY_STATUS_OFFSET register or it will hang.
>
> Marek requested that I not enable the clocks in ehci_usb_of_to_plat,
> so I modified that function to return an unknown state if the
> device tree does not explicitly state whether it is a host
> or a peripheral.
>
> When the driver probes, it looks to see if it's in the unknown
> state, and only then will it read the register to auto-detect.
>
> Signed-off-by: Adam Ford
> ---
> V3: Keep ehci_usb_of_to_plat but add the ability to return
> and unknown state instead of reading the register.
> If the probe determines the states is unknown, it will
> query the register after the clocks have been enabled.
> Because of the slight behavior change, I removed any
> review or tested tags.
>
> V2: Rename ehci_usb_of_to_plat to ehci_usb_dr_mode and call it
> from the probe after the clocks are enabled, but before
> the data is needed.
>
> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
> index 1bd6147c76..cf44e53ff7 100644
> --- a/drivers/usb/host/ehci-mx6.c
> +++ b/drivers/usb/host/ehci-mx6.c
> @@ -543,7 +543,7 @@ static int ehci_usb_phy_mode(struct udevice *dev)
> plat->init_type = USB_INIT_DEVICE;
> else
> plat->init_type = USB_INIT_HOST;
> - } else if (is_mx7()) {
> + } else if (is_mx7() || is_imx8mm() || is_imx8mn()) {
> phy_status = (void __iomem *)(addr +
> USBNC_PHY_STATUS_OFFSET);
> val = readl(phy_status);
> @@ -573,9 +573,8 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
> case USB_DR_MODE_PERIPHERAL:
> plat->init_type = USB_INIT_DEVICE;
> break;
> - case USB_DR_MODE_OTG:
> - case USB_DR_MODE_UNKNOWN:
> - return ehci_usb_phy_mode(dev);
> + default:
> + plat->init_type = USB_INIT_UNKNOWN;
> };
>
> return 0;
> @@ -677,6 +676,20 @@ static int ehci_usb_probe(struct udevice *dev)
> mdelay(1);
> #endif
>
> + /*
> +* If the device tree didn't specify host or device,
> +* the default is USB_INIT_UNKNOWN, so we need to check
> +* the register. For imx8mm and imx8mn, the clocks need to be
> +* running first, so we defer the check until they are.
> +*/
> + if (priv->init_type == USB_INIT_UNKNOWN) {
> + ret = ehci_usb_phy_mode(dev);
> + if (ret)
> + goto err_clk;
> + else
> + priv->init_type = plat->init_type;
> + }
> +
> #if CONFIG_IS_ENABLED(DM_REGULATOR)
> ret = device_get_supply_regulator(dev, "vbus-supply",
> >vbus_supply);
> diff --git a/include/usb.h b/include/usb.h
> index b3851fdb4f..47d738a786 100644
> --- a/include/usb.h
> +++ b/include/usb.h
> @@ -163,7 +163,8 @@ struct int_queue;
> */
> enum usb_init_type {
> USB_INIT_HOST,
> - USB_INIT_DEVICE
> + USB_INIT_DEVICE,
> + USB_INIT_UNKNOWN,
> };
>
> /**
> --
> 2.32.0
>
Adam,
For v3:
tested on imx8mm_venice_defconfig as USB host with USB_ETHER_ASIX and
as gadget with CMD_USB_MASS_STORAGE (ums 0 mmc 2).
Tested-By: Tim Harvey
Best Regards,
Tim
Raw Kernel Image Support for Falcon Mode Boot Via SPI Devices
Hi All, While trying to bring up Falcon Mode boot on an ARM64 board, I've discovered that the SPL+SPI(spl_spi.c) driver does not allow us to load a raw kernel image and subsequently call the bootz_setup() function which resides in spl_parse_image_header(). I've added a new config option (CONFIG_SYS_SPI_KERNEL_SKIP_HEADER) which will skip the mkimage header check, allowing the subsequent spl_parse_image_header() call to successfully fall through to bootz_setup() and load/boot a raw kernel image. Sincerely, Nathan Barrett-Morrison From e5a15a8ad2fd007e6d8d48dd64767d194bbd1833 Mon Sep 17 00:00:00 2001 From: Nathan Barrett-Morrison Date: Mon, 17 Jan 2022 19:42:59 -0500 Subject: [PATCH] Allow Falcon Mode boot to use raw kernel image when booting via SPI. When using Falcon Mode boot with a raw, unwrapped kernel image, the bootz_setup() call inside of spl_parse_image_header() is unreachable because the mkimage header magic check will never pass. Adding CONFIG_SYS_SPI_KERNEL_SKIP_HEADER gives us the ability to pass through to the desired bootz_setup() call. Signed-off-by: Nathan Barrett-Morrison Cc: Tom Rini Cc: Aneesh V --- common/spl/spl_spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 4e20a23dea..62dad1d2fb 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -33,8 +33,10 @@ static int spi_load_image_os(struct spl_image_info *spl_image, spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(*header), (void *)header); +#ifndef CONFIG_SYS_SPI_KERNEL_SKIP_HEADER if (image_get_magic(header) != IH_MAGIC) return -1; +#endif err = spl_parse_image_header(spl_image, header); if (err) -- 2.34.1
Falcon Mode Support For Uncompressed Kernel Images
Hi All,
While trying to bring up Falcon Mode boot on an ARM64 board, I discovered
that there is no path which allows you to use an uncompressed kernel image
(booti). I've added this path and attached the relevant patch.
I've made this a separate if/else CONFIG option instead of allowing both
bootz+booti paths to coexist, as it seems unlikely to me that there would
be such a board which needs both. Most architectures use either bootz or
booti, but not both.
Sincerely,
Nathan Barrett-Morrison
From d5542ccc2d4f81ac0442be8ca772a99e1a13b6dd Mon Sep 17 00:00:00 2001
From: Nathan Barrett-Morrison
Date: Mon, 17 Jan 2022 19:42:10 -0500
Subject: [PATCH] Add in the ability to load and boot an uncompressed
kernel image during the Falcon Mode boot sequence. This is required for
architectures which do not support compressed kernel image booting (i.e.,
ARM64)
Signed-off-by: Nathan Barrett-Morrison
Cc: Tom Rini
Cc: Aneesh V
---
arch/arm/lib/Makefile | 2 +-
common/spl/Kconfig| 6 ++
common/spl/spl.c | 21 +
3 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index c48e1f622d..24c9e3c1e5 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -36,7 +36,7 @@ obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o
obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
else
obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o
-obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
+obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o image.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
endif
ifdef CONFIG_ARM64
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 4a739a7421..6d2c9f 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -917,6 +917,12 @@ config SYS_OS_BASE
Specify the address, where the OS image is found, which
gets booted.
+config SPL_OS_BOOT_UNCOMPRESSED
+ bool "Use uncompressed kernel image alongside Falcon Mode"
+ depends on SPL_SPI_LOAD
+ help
+ Use an uncompressed kernel image to boot. This is targetting
+ architectures which use booti instead of bootz (i.e, ARM64).
endif # SPL_OS_BOOT
config SPL_PAYLOAD
diff --git a/common/spl/spl.c b/common/spl/spl.c
index f51d1f3205..9a826971eb 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -104,6 +104,11 @@ int __weak bootz_setup(ulong image, ulong *start, ulong *end)
{
return 1;
}
+
+int __weak booti_setup(ulong image, ulong *relocated_addr, ulong *size, bool force_reloc)
+{
+ return 1;
+}
#endif
/* Weak default function for arch/board-specific fixups to the spl_image_info */
@@ -354,6 +359,21 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
#endif
#if CONFIG_IS_ENABLED(OS_BOOT)
+#if CONFIG_IS_ENABLED(OS_BOOT_UNCOMPRESSED)
+ ulong start, size;
+
+ if (!booti_setup((ulong)header, , , 0)) {
+ spl_image->name = "Linux";
+ spl_image->os = IH_OS_LINUX;
+ spl_image->load_addr = start;
+ spl_image->entry_point = start;
+ spl_image->size = size;
+ printf(SPL_TPL_PROMPT
+ "payload Image, load addr: 0x%lx size: %d\n",
+ spl_image->load_addr, spl_image->size);
+ return 0;
+ }
+#else
ulong start, end;
if (!bootz_setup((ulong)header, , )) {
@@ -367,6 +387,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
spl_image->load_addr, spl_image->size);
return 0;
}
+#endif
#endif
if (!spl_parse_board_header(spl_image, (const void *)header, sizeof(*header)))
--
2.34.1
Re: [PATCH] efidebug: avoid 'dfu_alt_info not defined' message
On Mon, Jan 17, 2022 at 01:33:51PM +0100, Heinrich Schuchardt wrote:
> On 1/17/22 01:45, AKASHI Takahiro wrote:
> > On Sat, Jan 15, 2022 at 02:18:21AM +0100, Heinrich Schuchardt wrote:
> > > If variable dfu_alt_info is not defined duplicate messages are displayed.
> > >
> > > => efidebug boot dump
> > > Scanning disk mmc2.blk...
> > > Scanning disk mmc1.blk...
> > > Scanning disk mmc0.blk...
> > > Found 3 disks
> > > No EFI system partition
> > > "dfu_alt_info" env variable not defined!
> > > Probably dfu_alt_info not defined
> > > "dfu_alt_info" env variable not defined!
> > > Probably dfu_alt_info not defined
> > >
> > > Remove the 'Probably dfu_alt_info not defined' message.
> > > Instead write a warning if the variable contains no entities.
> > >
> > > Signed-off-by: Heinrich Schuchardt
> > > ---
> > > lib/efi_loader/efi_firmware.c | 7 +--
> > > 1 file changed, 5 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
> > > index a1b88dbfc2..519a47267c 100644
> > > --- a/lib/efi_loader/efi_firmware.c
> > > +++ b/lib/efi_loader/efi_firmware.c
> > > @@ -128,8 +128,11 @@ static efi_status_t efi_get_dfu_info(
> > > size_t names_len, total_size;
> > > int dfu_num, i;
> > > u16 *name, *next;
> > > + int ret;
> > > - dfu_init_env_entities(NULL, NULL);
> > > + ret = dfu_init_env_entities(NULL, NULL);
> > > + if (ret)
> > > + return EFI_SUCCESS;
> >
> > Do you want to return EFI_SUCCESS here?
> > It is mandatory that "dfu_alt_info" be defined so that the current
> > FMP drivers should work.
> > So if the variable is not defined, I think,
> > efi_firmware_[fit|raw]_get_image_info() should fail.
> > Even if it returns EFI_SUCCESS, descriptor_count should be set to zero.
>
> This patch did not change the return value. It only removed superfluous
> messages that I saw everytime I used the sandbox.
The return value is the same, but
> For dfu_num == 0 we are returning EFI_SUCCESS. If the number is 0 due to the
> content of dfu_alt_info or due to its absence, should not make a difference
> in the return code. Writing a message if dfu_alt_info exists but contains no
> entity seems reasonable.
With your patch, the value of "descriptor_count", as well as the other
arguments, will remain uncertain even we see EFI_SUCCESS at return.
Since dfu_init_env_entities() returns -EINVAL in case "dfu_alt_info" is
not defined, efi_get_dfu_info(), hence efi_firmware_[fit|raw]_get_image_info(),
returns immediately without setting any value to "descriptor_count".
Have you ever tested your code?
> If you think EFI_SUCCESS is not correct in both cases, please, send a
> followup patch for review.
NAK.
We are discussing the issue against your patch.
Why not do so in this thread?
-Takahiro Akashi
> Best regards
>
> Heinrich
>
> >
> > -Takahiro Akashi
> >
> > > names_len = 0;
> > > dfu_num = 0;
> > > @@ -138,7 +141,7 @@ static efi_status_t efi_get_dfu_info(
> > > dfu_num++;
> > > }
> > > if (!dfu_num) {
> > > - log_warning("Probably dfu_alt_info not defined\n");
> > > + log_warning("No entities in dfu_alt_info\n");
> > > *image_info_size = 0;
> > > dfu_free_entities();
> > > --
> > > 2.33.1
> > >
>
[PATCH v8 15/15] doc: rockchip: add rk3066 Rikomagic MK808
Add rk3066 Rikomagic MK808 to the list of mainline supported Rockchip boards. Signed-off-by: Johan Jonker --- doc/board/rockchip/rockchip.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 144cb98e..a4fca88b 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -24,6 +24,8 @@ List of mainline supported Rockchip boards: * rk3036 - Rockchip Evb-RK3036 (evb-rk3036) - Kylin (kylin_rk3036) +* rk3066 + - Rikomagic MK808 (mk808) * rk3128 - Rockchip Evb-RK3128 (evb-rk3128) * rk3188 -- 2.20.1
[PATCH v8 11/15] rockchip: rk3066: add core support
Add the core architecture code for the rk3066.
Signed-off-by: Johan Jonker
---
arch/arm/mach-rockchip/Kconfig| 23
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3066/Kconfig | 30 ++
arch/arm/mach-rockchip/rk3066/Makefile| 5 ++
arch/arm/mach-rockchip/rk3066/clk_rk3066.c| 33 +++
arch/arm/mach-rockchip/rk3066/rk3066.c| 49 +
arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 55 +++
7 files changed, 196 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
create mode 100644 arch/arm/mach-rockchip/rk3066/rk3066.c
create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a3733e2f..6535d8dd 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -36,6 +36,28 @@ config ROCKCHIP_RK3036
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+config ROCKCHIP_RK3066
+ bool "Support Rockchip RK3066"
+ select CPU_V7A
+ select SPL_BOARD_INIT if SPL
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select SPL
+ select TPL
+ select TPL_ROCKCHIP_BACK_TO_BROM
+ select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
+ imply ROCKCHIP_COMMON_BOARD
+ imply SPL_ROCKCHIP_COMMON_BOARD
+ imply SPL_SERIAL
+ imply TPL_ROCKCHIP_COMMON_BOARD
+ imply TPL_SERIAL
+ help
+ The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
+ including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
+ video interfaces, several memory options and video codec support.
+ Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
+ UART, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3128
bool "Support Rockchip RK3128"
select CPU_V7A
@@ -420,6 +442,7 @@ config ROCKCHIP_SPI_IMAGE
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3066/Kconfig"
source "arch/arm/mach-rockchip/rk3128/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk322x/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 00aef0ec..6c1c7b8a 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
obj-$(CONFIG_ROCKCHIP_PX30) += px30/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig
b/arch/arm/mach-rockchip/rk3066/Kconfig
new file mode 100644
index ..335f49bc
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/Kconfig
@@ -0,0 +1,30 @@
+if ROCKCHIP_RK3066
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x20004040
+
+config SYS_SOC
+ default "rk3066"
+
+config SYS_MALLOC_F_LEN
+ default 0x0800
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_SERIAL
+ default y
+
+config TPL_LIBCOMMON_SUPPORT
+ default y
+
+config TPL_LIBGENERIC_SUPPORT
+ default y
+
+config TPL_SERIAL
+ default y
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3066/Makefile
b/arch/arm/mach-rockchip/rk3066/Makefile
new file mode 100644
index ..9e2a9d4b
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += clk_rk3066.o
+obj-y += rk3066.o
+obj-y += syscon_rk3066.o
diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
new file mode 100644
index ..c47526dc
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3066a_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3066_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk();
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c
b/arch/arm/mach-rockchip/rk3066/rk3066.c
new file mode 100644
index ..78c7d894
--- /dev/null
+++
[PATCH v8 13/15] rockchip: rk3066: add mk808_defconfig
This commit adds the default configuration file and relevant description for a MK808 board. Signed-off-by: Johan Jonker --- Changed V8: use default log level ENV_IS_NOWHERE --- configs/mk808_defconfig | 99 + 1 file changed, 99 insertions(+) create mode 100644 configs/mk808_defconfig diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig new file mode 100644 index ..a0e71d1f --- /dev/null +++ b/configs/mk808_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +# CONFIG_SPL_SYS_THUMB_BUILD is not set +# CONFIG_TPL_SYS_THUMB_BUILD is not set +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x60408000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808" +CONFIG_SPL_TEXT_BASE=0x6000 +CONFIG_ROCKCHIP_RK3066=y +CONFIG_TPL_TEXT_BASE=0x10080C04 +CONFIG_TPL_MAX_SIZE=32764 +CONFIG_TPL_STACK=0x1008 +CONFIG_TARGET_MK808=y +CONFIG_SPL_STACK_R_ADDR=0x7000 +CONFIG_DEBUG_UART_BASE=0x20064000 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_PAYLOAD="u-boot.bin" +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x70800800 +CONFIG_SD_BOOT=y +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2 +CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y +CONFIG_TPL_NEEDS_SEPARATE_STACK=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_SPL_OF_PLATDATA=y +CONFIG_TPL_OF_PLATDATA=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_TPL_DM=y +# CONFIG_DM_WARN is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +# CONFIG_SIMPLE_BUS is not set +# CONFIG_SPL_SIMPLE_BUS is not set +# CONFIG_TPL_BLK is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_TPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +# CONFIG_SPL_DM_I2C is not set +CONFIG_LED=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=2000 +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_TPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +# CONFIG_TPL_OF_LIBFDT is not set -- 2.20.1
[PATCH v8 14/15] rockchip: tools: add rk3066 support to rkcommon.c
Add rk3066 support to rkcommon.c
Signed-off-by: Johan Jonker
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 29f2676c..860785f8 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -123,6 +123,7 @@ struct spl_info {
static struct spl_info spl_infos[] = {
{ "px30", "RK33", 0x2800, false, RK_HEADER_V1 },
{ "rk3036", "RK30", 0x1000, false, RK_HEADER_V1 },
+ { "rk3066", "RK30", 0x8000 - 0x800, true, RK_HEADER_V1 },
{ "rk3128", "RK31", 0x1800, false, RK_HEADER_V1 },
{ "rk3188", "RK31", 0x8000 - 0x800, true, RK_HEADER_V1 },
{ "rk322x", "RK32", 0x8000 - 0x1000, false, RK_HEADER_V1 },
--
2.20.1
[PATCH v8 12/15] rockchip: rk3066: add Rikomagic MK808 board
MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, HDMI and a micro-SD card slot. It also includes on-board NAND and 1GB of SDRAM. Signed-off-by: Johan Jonker --- arch/arm/mach-rockchip/rk3066/Kconfig | 9 + board/rikomagic/mk808/Kconfig | 15 +++ board/rikomagic/mk808/MAINTAINERS | 6 ++ board/rikomagic/mk808/Makefile| 3 +++ board/rikomagic/mk808/mk808.c | 3 +++ 5 files changed, 36 insertions(+) create mode 100644 board/rikomagic/mk808/Kconfig create mode 100644 board/rikomagic/mk808/MAINTAINERS create mode 100644 board/rikomagic/mk808/Makefile create mode 100644 board/rikomagic/mk808/mk808.c diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig index 335f49bc..95d7fc8a 100644 --- a/arch/arm/mach-rockchip/rk3066/Kconfig +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -1,5 +1,12 @@ if ROCKCHIP_RK3066 +config TARGET_MK808 + bool "MK808" + help + MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, + HDMI and a micro-SD card slot. It also includes on-board NAND + and 1GB of SDRAM. + config ROCKCHIP_BOOT_MODE_REG default 0x20004040 @@ -27,4 +34,6 @@ config TPL_LIBGENERIC_SUPPORT config TPL_SERIAL default y +source "board/rikomagic/mk808/Kconfig" + endif diff --git a/board/rikomagic/mk808/Kconfig b/board/rikomagic/mk808/Kconfig new file mode 100644 index ..4abad7e7 --- /dev/null +++ b/board/rikomagic/mk808/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MK808 + +config SYS_BOARD + default "mk808" + +config SYS_VENDOR + default "rikomagic" + +config SYS_CONFIG_NAME + default "mk808" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rikomagic/mk808/MAINTAINERS b/board/rikomagic/mk808/MAINTAINERS new file mode 100644 index ..b3ef6adb --- /dev/null +++ b/board/rikomagic/mk808/MAINTAINERS @@ -0,0 +1,6 @@ +MK808 +M: Johan Jonker +S: Maintained +F: board/rikomagic/mk808 +F: configs/mk808_defconfig +F: include/configs/mk808.h diff --git a/board/rikomagic/mk808/Makefile b/board/rikomagic/mk808/Makefile new file mode 100644 index ..a4d16884 --- /dev/null +++ b/board/rikomagic/mk808/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += mk808.o diff --git a/board/rikomagic/mk808/mk808.c b/board/rikomagic/mk808/mk808.c new file mode 100644 index ..e0bfc6f3 --- /dev/null +++ b/board/rikomagic/mk808/mk808.c @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include -- 2.20.1
[PATCH v8 10/15] rockchip: rk3066: add rk3066_common.h include
Add rk3066_common.h include. Signed-off-by: Johan Jonker --- include/configs/mk808.h | 9 ++ include/configs/rk3066_common.h | 56 + 2 files changed, 65 insertions(+) create mode 100644 include/configs/mk808.h create mode 100644 include/configs/rk3066_common.h diff --git a/include/configs/mk808.h b/include/configs/mk808.h new file mode 100644 index ..e2ab2b51 --- /dev/null +++ b/include/configs/mk808.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include + +#endif diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h new file mode 100644 index ..b8dc0242 --- /dev/null +++ b/include/configs/rk3066_common.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_RK3066_COMMON_H +#define __CONFIG_RK3066_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include +#include "rockchip-common.h" + +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#define CONFIG_SYS_CBSIZE 256 + +#define CONFIG_SYS_INIT_SP_ADDR0x7800 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x1 - 0xC00) + +#define CONFIG_IRAM_BASE 0x1008 + +/* spl size max 200k */ +#define CONFIG_SPL_MAX_SIZE0x32000 + +#define CONFIG_SPL_STACK 0x1008 + +#define CONFIG_SYS_SDRAM_BASE 0x6000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE(1024UL << 20UL) +#define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE + +#ifndef CONFIG_SPL_BUILD +/* usb otg */ + +/* usb host support */ +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x6000\0" \ + "pxefile_addr_r=0x6010\0" \ + "fdt_addr_r=0x61f0\0" \ + "kernel_addr_r=0x6200\0" \ + "ramdisk_addr_r=0x6400\0" + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6fff\0" \ + "initrd_high=0x6fff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#endif -- 2.20.1
[PATCH v8 09/15] rockchip: rk3066: add include
Add include for rk3066. Signed-off-by: Johan Jonker --- arch/arm/include/asm/arch-rk3066/boot0.h | 8 arch/arm/include/asm/arch-rk3066/gpio.h | 8 arch/arm/include/asm/arch-rk3066/timer.h | 6 ++ 3 files changed, 22 insertions(+) create mode 100644 arch/arm/include/asm/arch-rk3066/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3066/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3066/timer.h diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h new file mode 100644 index ..28c0fb9a --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/gpio.h b/arch/arm/include/asm/arch-rk3066/gpio.h new file mode 100644 index ..a4a3b328 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/timer.h b/arch/arm/include/asm/arch-rk3066/timer.h new file mode 100644 index ..3bb39428 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/timer.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_TIMER_H__ +#define __ASM_ARCH_TIMER_H__ + +#endif -- 2.20.1
[PATCH v8 07/15] arm: dts: rockchip: add rk3066a.dtsi
In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. Add rk3066a.dtsi. Move U-boot specific
things in a rk3066a-u-boot.dtsi file.
Signed-off-by: Johan Jonker
---
Changed V8:
update dtsi
---
arch/arm/dts/rk3066a-u-boot.dtsi | 3 +
arch/arm/dts/rk3066a.dtsi| 880 +++
2 files changed, 883 insertions(+)
create mode 100644 arch/arm/dts/rk3066a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3066a.dtsi
diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi
new file mode 100644
index ..fefef42b
--- /dev/null
+++ b/arch/arm/dts/rk3066a-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rockchip-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi
new file mode 100644
index ..da16fa23
--- /dev/null
+++ b/arch/arm/dts/rk3066a.dtsi
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner
+ */
+
+#include
+#include
+#include
+#include
+#include "rk3xxx.dtsi"
+#include "rk3xxx-u-boot.dtsi"
+
+/ {
+ compatible = "rockchip,rk3066a";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "rockchip,rk3066-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <0x0>;
+ operating-points =
+ /* kHzuV */
+ <1416000 130>,
+ <120 1175000>,
+ <1008000 1125000>,
+ <816000 1125000>,
+ <60 110>,
+ <504000 110>,
+ <312000 1075000>;
+ clock-latency = <4>;
+ clocks = < ARMCLK>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <0x1>;
+ };
+ };
+
+ display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <_out>, <_out>;
+ };
+
+ sram: sram@1008 {
+ compatible = "mmio-sram";
+ reg = <0x1008 0x1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1008 0x1>;
+
+ smp-sram@0 {
+ compatible = "rockchip,rk3066-smp-sram";
+ reg = <0x0 0x50>;
+ };
+ };
+
+ vop0: vop@1010c000 {
+ compatible = "rockchip,rk3066-vop";
+ reg = <0x1010c000 0x19c>;
+ interrupts = ;
+ clocks = < ACLK_LCDC0>,
+< DCLK_LCDC0>,
+< HCLK_LCDC0>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ power-domains = < RK3066_PD_VIO>;
+ resets = < SRST_LCDC0_AXI>,
+< SRST_LCDC0_AHB>,
+< SRST_LCDC0_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "disabled";
+
+ vop0_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop0_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <_in_vop0>;
+ };
+ };
+ };
+
+ vop1: vop@1010e000 {
+ compatible = "rockchip,rk3066-vop";
+ reg = <0x1010e000 0x19c>;
+ interrupts = ;
+ clocks = < ACLK_LCDC1>,
+< DCLK_LCDC1>,
+< HCLK_LCDC1>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ power-domains = < RK3066_PD_VIO>;
+ resets = < SRST_LCDC1_AXI>,
+< SRST_LCDC1_AHB>,
+< SRST_LCDC1_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "disabled";
+
+ vop1_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop1_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <_in_vop1>;
+ };
+ };
+ };
+
+ hdmi: hdmi@10116000 {
+ compatible = "rockchip,rk3066-hdmi";
+ reg = <0x10116000 0x2000>;
+ interrupts = ;
+ clocks = <
[PATCH v8 08/15] arm: dts: rockchip: add rk3066a-mk808.dts
MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port,
HDMI and a micro-SD card slot. It also includes on-board NAND
and 1GB of SDRAM. Add rk3066a-mk808.dts. Move U-boot specific
things in a rk3066a-mk808-u-boot.dtsi file.
Signed-off-by: Johan Jonker
---
Changed V8:
update dts
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/rk3066a-mk808-u-boot.dtsi | 42 +
arch/arm/dts/rk3066a-mk808.dts | 216 +
3 files changed, 261 insertions(+)
create mode 100644 arch/arm/dts/rk3066a-mk808-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3066a-mk808.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b3e2a9c9..189f61bd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -89,6 +89,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3036) += \
dtb-$(CONFIG_ROCKCHIP_RK3128) += \
rk3128-evb.dtb
+dtb-$(CONFIG_ROCKCHIP_RK3066) += \
+ rk3066a-mk808.dtb
+
dtb-$(CONFIG_ROCKCHIP_RK3188) += \
rk3188-radxarock.dtb
diff --git a/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
new file mode 100644
index ..6e5990f9
--- /dev/null
+++ b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3066a-u-boot.dtsi"
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ compatible = "rockchip,rk3066-dmc", "syscon";
+ rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
+ 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4
+ 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0
+ 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0
+ 0x4 0x0>;
+ rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
+ 0x220 0x40 0x0 0x0>;
+ rockchip,sdram-params = <0x24716310 0 2 3 3 9 0>;
+};
+
+ {
+ fifo-mode;
+ max-frequency = <400>;
+ u-boot,dm-spl;
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ compatible = "rockchip,rk3066-noc", "syscon";
+};
+
+ {
+ clock-frequency = <2400>;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts
new file mode 100644
index ..667d57a4
--- /dev/null
+++ b/arch/arm/dts/rk3066a-mk808.dts
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Paweł Jarosz
+ */
+
+/dts-v1/;
+#include
+#include "rk3066a.dtsi"
+
+/ {
+ model = "Rikomagic MK808";
+ compatible = "rikomagic,mk808", "rockchip,rk3066a";
+
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@6000 {
+ reg = <0x6000 0x4000>;
+ device_type = "memory";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = < 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <250>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "recovery";
+ linux,code = ;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ blue_led: led-0 {
+ label = "mk808:blue:power";
+ gpios = < RK_PA3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ hdmi_con {
+ compatible = "hdmi-connector";
+ type = "c";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <_out_con>;
+ };
+ };
+ };
+
+ vcc_2v5: vcc-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_2v5";
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <250>;
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ vcc_host: usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <_drv>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-name = "host-pwr";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ startup-delay-us = <10>;
+ vin-supply =
[PATCH v8 05/15] rockchip: rk3066: add sdram driver
From: Paweł Jarosz
Add rockchip rk3066 sdram driver
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
---
Changed V7:
restyle
rename TEST_PATTERN
changed function prefix
changed #if where possible
restyle U_BOOT_DRIVER structure
remove rk3066_dmc_of_to_plat because dmc DT data
only used in TPL in combination with OF_PLATDATA
---
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3066.c | 892
2 files changed, 893 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram_rk3066.c
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index ca1c289b..6d530c29 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
+obj-$(CONFIG_ROCKCHIP_RK3066) = sdram_rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
diff --git a/drivers/ram/rockchip/sdram_rk3066.c
b/drivers/ram/rockchip/sdram_rk3066.c
new file mode 100644
index ..832154ee
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3066.c
@@ -0,0 +1,892 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * Adapted from the very similar rk3188 ddr init.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct rk3066_dmc_chan_info {
+ struct rk3288_ddr_pctl *pctl;
+ struct rk3288_ddr_publ *publ;
+ struct rk3188_msch *msch;
+};
+
+struct rk3066_dmc_dram_info {
+ struct rk3066_dmc_chan_info chan[1];
+ struct ram_info info;
+ struct clk ddr_clk;
+ struct rk3066_cru *cru;
+ struct rk3066_grf *grf;
+ struct rk3066_sgrf *sgrf;
+ struct rk3188_pmu *pmu;
+};
+
+struct rk3066_dmc_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_rockchip_rk3066_dmc of_plat;
+#endif
+ struct rk3288_sdram_channel ch[2];
+ struct rk3288_sdram_pctl_timing pctl_timing;
+ struct rk3288_sdram_phy_timing phy_timing;
+ struct rk3288_base_params base;
+ int num_channels;
+ struct regmap *map;
+};
+
+const int rk3066_dmc_ddrconf_table[] = {
+ /*
+* [5:4] row(13+n)
+* [1:0] col(9+n), assume bw=2
+* row col,bw
+*/
+ 0,
+ (2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+ (1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+ (0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+ (2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+ (1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+ (0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+ (1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+ (0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+};
+
+#define TEST_PATTERN 0x5aa5f00f
+#define DQS_GATE_TRAINING_ERROR_RANK0 BIT(4)
+#define DQS_GATE_TRAINING_ERROR_RANK1 BIT(5)
+
+static void rk3066_dmc_copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++) {
+ writel(*src, dest);
+ src++;
+ dest++;
+ }
+}
+
+static void rk3066_dmc_ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32
phy)
+{
+ u32 phy_ctl_srstn_shift = 13;
+ u32 ctl_psrstn_shift = 11;
+ u32 ctl_srstn_shift = 10;
+ u32 phy_psrstn_shift = 9;
+ u32 phy_srstn_shift = 8;
+
+ rk_clrsetreg(>cru_softrst_con[5],
+1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
+1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
+1 << phy_srstn_shift,
+phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
+ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
+phy << phy_srstn_shift);
+}
+
+static void rk3066_dmc_ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n)
+{
+ u32 phy_ctl_srstn_shift = 13;
+
+ rk_clrsetreg(>cru_softrst_con[5],
+1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
+}
+
+static void rk3066_dmc_phy_pctrl_reset(struct rk3066_cru *cru,
+ struct rk3288_ddr_publ *publ,
+ int channel)
+{
+ int i;
+
+ rk3066_dmc_ddr_reset(cru, channel, 1, 1);
+ udelay(1);
+ clrbits_le32(>acdllcr, ACDLLCR_DLLSRST);
+ for (i = 0; i < 4; i++)
+ clrbits_le32(>datx8[i].dxdllcr, DXDLLCR_DLLSRST);
+
+ udelay(10);
+
[PATCH v8 06/15] arm: dts: rockchip: fix rk3xxx-u-boot.dtsi
The file rk3xxx-u-boot.dtsi was original only for rk3188 and SPL.
With rk3066 added some nodes are also needed in TPL,
so change them to u-boot,dm-pre-reloc
Signed-off-by: Johan Jonker
---
arch/arm/dts/rk3xxx-u-boot.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi
index 581594c3..e67432fb 100644
--- a/arch/arm/dts/rk3xxx-u-boot.dtsi
+++ b/arch/arm/dts/rk3xxx-u-boot.dtsi
@@ -4,7 +4,7 @@
noc: syscon@10128000 {
compatible = "rockchip,rk3188-noc", "syscon";
reg = <0x10128000 0x2000>;
- u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
};
dmc: dmc@2002 {
@@ -18,16 +18,16 @@
rockchip,grf = <>;
rockchip,pmu = <>;
rockchip,noc = <>;
- u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
};
};
{
- u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
};
{
- u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
};
{
--
2.20.1
[PATCH v8 03/15] rockchip: rk3066: add clock driver for rk3066 soc
From: Paweł Jarosz
Add the clock driver for the rk3066 platform.
Derived from the rk3288 and rk3188 driver it
supports only a bare minimum to bring up the system
to reduce the TPL size for:
SDRAM clock configuration.
The boot devices NAND, EMMC, SDMMC, SPI.
A UART for the debug messages (fixed) at 115200n8.
A SARADC for the recovery button.
A TIMER for the delays (fixed).
There's support for two possible frequencies,
the safe 600MHz which will work with default pmic settings and
will be set to get away from the 24MHz default and
the maximum of 1.416Ghz, which boards can set if they
were able to get pmic support for it.
After the clock tree is set during the TPL probe
there's no parent update support.
In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c
obtain the (fixed) clk_get_rate from the clock driver
instead of platdata.
The rk3066 cru node has a number of assigned-clocks properties
that call the .set_rate() function. Add them to the list so that
they return a 0 instead of -ENOENT.
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
---
Changed V8:
add SCLK_TIMER[0..2]
add SCLK_UART[0..3]
fix assigned-clocks
use GENMASK, __bf_shf and REG defines
fix clk defines
add includes
fix bit position CRU_CLKSEL0_CON rk3066 vs rk3188
fix comments
rename PLL_MODE defines
use dev_bind
use dev_dbg
use a different variable name
Changed V7:
changed function prefix
changed #if where possible
restyle U_BOOT_DRIVER structure
---
.../include/asm/arch-rockchip/cru_rk3066.h| 157
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3066.c | 717 ++
3 files changed, 875 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
create mode 100644 drivers/clk/rockchip/clk_rk3066.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
new file mode 100644
index ..45937736
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Paweł Jarosz
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3066_H
+#define _ASM_ARCH_CRU_RK3066_H
+
+#include
+#include
+
+#define REG(name, h, l) \
+name##_MASK = GENMASK(h, l), \
+name##_SHIFT = __bf_shf(name##_MASK)
+
+#define OSC_HZ (24 * 1000 * 1000)
+
+#define APLL_HZ(1416 * 100)
+#define APLL_SAFE_HZ (600 * 100)
+#define GPLL_HZ(594 * 100)
+#define CPLL_HZ(384 * 100)
+
+/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
+#define CPU_ACLK_HZ29700
+#define CPU_HCLK_HZ14850
+#define CPU_PCLK_HZ7425
+#define CPU_H2P_HZ 7425
+
+#define PERI_ACLK_HZ 14850
+#define PERI_HCLK_HZ 14850
+#define PERI_PCLK_HZ 7425
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3066_clk_priv {
+ struct rk3066_grf *grf;
+ struct rk3066_cru *cru;
+ ulong rate;
+ bool has_bwadj;
+};
+
+struct rk3066_cru {
+ struct rk3066_pll {
+ u32 con0;
+ u32 con1;
+ u32 con2;
+ u32 con3;
+ } pll[4];
+ u32 cru_mode_con;
+ u32 cru_clksel_con[35];
+ u32 cru_clkgate_con[10];
+ u32 reserved1[2];
+ u32 cru_glb_srst_fst_value;
+ u32 cru_glb_srst_snd_value;
+ u32 reserved2[2];
+ u32 cru_softrst_con[9];
+ u32 cru_misc_con;
+ u32 reserved3[2];
+ u32 cru_glb_cnt_th;
+};
+
+check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
+
+/* CRU_CLKSEL0_CON */
+enum {
+ REG(CPU_ACLK_PLL, 8, 8),
+ CPU_ACLK_PLL_SELECT_APLL= 0,
+ CPU_ACLK_PLL_SELECT_GPLL,
+
+ REG(CORE_PERI_DIV, 7, 6),
+
+ REG(A9_CORE_DIV, 4, 0),
+};
+
+/* CRU_CLKSEL1_CON */
+enum {
+ REG(AHB2APB_DIV, 15, 14),
+
+ REG(CPU_PCLK_DIV, 13, 12),
+
+ REG(CPU_HCLK_DIV, 9, 8),
+
+ REG(CPU_ACLK_DIV, 2, 0),
+};
+
+/* CRU_CLKSEL10_CON */
+enum {
+ REG(PERI_SEL_PLL, 15, 15),
+ PERI_SEL_CPLL = 0,
+ PERI_SEL_GPLL,
+
+ REG(PERI_PCLK_DIV, 13, 12),
+
+ REG(PERI_HCLK_DIV, 9, 8),
+
+ REG(PERI_ACLK_DIV, 4, 0),
+};
+
+/* CRU_CLKSEL11_CON */
+enum {
+ REG(MMC0_DIV, 5, 0),
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+ REG(UART_PLL, 15, 15),
+ UART_PLL_SELECT_GENERAL = 0,
+ UART_PLL_SELECT_CODEC,
+
+ REG(EMMC_DIV, 13, 8),
+
+ REG(SDIO_DIV, 5, 0),
+};
+
+/* CRU_CLKSEL24_CON */
+enum {
+ REG(SARADC_DIV, 15, 8),
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+ REG(SPI1_DIV, 14, 8),
+
+ REG(SPI0_DIV, 6, 0),
+};
+
+/* CRU_CLKSEL34_CON */
+enum {
+ REG(TSADC_DIV, 15, 0),
+};
+
+/* CRU_MODE_CON */
+enum {
+ REG(GPLL_MODE, 13, 12),
+
+ REG(CPLL_MODE, 9, 8),
+
+ REG(DPLL_MODE, 5, 4),
+
+ REG(APLL_MODE, 1,
[PATCH v8 04/15] rockchip: rk3066: add rk3066 pinctrl driver
From: Paweł Jarosz
Add driver supporting pin multiplexing on rk3066 platform.
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
---
Changed V7:
restyle
changed function prefix.
restyle U_BOOT_DRIVER structure
use OF_REAL
use EOPNOTSUPP
---
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3066.c | 113 ++
2 files changed, 114 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3066.c
diff --git a/drivers/pinctrl/rockchip/Makefile
b/drivers/pinctrl/rockchip/Makefile
index fcf19f87..7d03f810 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -5,6 +5,7 @@
obj-y += pinctrl-rockchip-core.o
obj-$(CONFIG_ROCKCHIP_PX30) += pinctrl-px30.o
obj-$(CONFIG_ROCKCHIP_RK3036) += pinctrl-rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3066) += pinctrl-rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c
b/drivers/pinctrl/rockchip/pinctrl-rk3066.c
new file mode 100644
index ..c329dd45
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-rockchip.h"
+
+static int rk3066_pinctrl_set_mux(struct rockchip_pin_bank *bank, int pin, int
mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, , );
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3066_PULL_OFFSET 0x118
+#define RK3066_PULL_PINS_PER_REG 16
+#define RK3066_PULL_BANK_STRIDE8
+
+static void rk3066_pinctrl_calc_pull_reg_and_bit(struct rockchip_pin_bank
*bank,
+int pin_num, struct regmap
**regmap,
+int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ *reg = RK3066_PULL_OFFSET;
+ *reg += bank->bank_num * RK3066_PULL_BANK_STRIDE;
+ *reg += (pin_num / RK3066_PULL_PINS_PER_REG) * 4;
+
+ *bit = pin_num % RK3066_PULL_PINS_PER_REG;
+};
+
+static int rk3066_pinctrl_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit;
+ u32 data;
+
+ if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
+ pull != PIN_CONFIG_BIAS_DISABLE)
+ return -EOPNOTSUPP;
+
+ rk3066_pinctrl_calc_pull_reg_and_bit(bank, pin_num, , ,
);
+ data = BIT(bit + 16);
+ if (pull == PIN_CONFIG_BIAS_DISABLE)
+ data |= BIT(bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+static struct rockchip_pin_bank rk3066_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+ PIN_BANK(4, 32, "gpio4"),
+ PIN_BANK(6, 16, "gpio6"),
+};
+
+static struct rockchip_pin_ctrl rk3066_pin_ctrl = {
+ .pin_banks = rk3066_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3066_pin_banks),
+ .grf_mux_offset = 0xa8,
+ .set_mux= rk3066_pinctrl_set_mux,
+ .set_pull = rk3066_pinctrl_set_pull,
+};
+
+static const struct udevice_id rk3066_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3066a-pinctrl",
+ .data = (ulong)_pin_ctrl
+ },
+ {}
+};
+
+U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = {
+ .name = "rockchip_rk3066a_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .ops= _pinctrl_ops,
+ .probe = rockchip_pinctrl_probe,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .of_match = rk3066_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+};
--
2.20.1
[PATCH v8 02/15] rockchip: rk3066: add grf header file
From: Paweł Jarosz
grf is needed by various drivers for rk3066 soc.
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
---
Changed V8:
add GRF_GPIO3B_IOMUX for SDMMC0
use GENMASK, __bf_shf and REG defines
add includes
---
.../include/asm/arch-rockchip/grf_rk3066.h| 210 ++
1 file changed, 210 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
new file mode 100644
index ..9863560c
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Paweł Jarosz
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3066_H
+#define _ASM_ARCH_GRF_RK3066_H
+
+#include
+#include
+
+#define REG(name, h, l) \
+name##_MASK = GENMASK(h, l), \
+name##_SHIFT = __bf_shf(name##_MASK)
+
+struct rk3066_grf_gpio_lh {
+ u32 l;
+ u32 h;
+};
+
+struct rk3066_grf {
+ struct rk3066_grf_gpio_lh gpio_dir[7];
+ struct rk3066_grf_gpio_lh gpio_do[7];
+ struct rk3066_grf_gpio_lh gpio_en[7];
+
+ u32 gpio0a_iomux;
+ u32 gpio0b_iomux;
+ u32 gpio0c_iomux;
+ u32 gpio0d_iomux;
+
+ u32 gpio1a_iomux;
+ u32 gpio1b_iomux;
+ u32 gpio1c_iomux;
+ u32 gpio1d_iomux;
+
+ u32 gpio2a_iomux;
+ u32 gpio2b_iomux;
+ u32 gpio2c_iomux;
+ u32 gpio2d_iomux;
+
+ u32 gpio3a_iomux;
+ u32 gpio3b_iomux;
+ u32 gpio3c_iomux;
+ u32 gpio3d_iomux;
+
+ u32 gpio4a_iomux;
+ u32 gpio4b_iomux;
+ u32 gpio4c_iomux;
+ u32 gpio4d_iomux;
+
+ u32 reserved0[5];
+
+ u32 gpio6b_iomux;
+
+ u32 reserved1[2];
+
+ struct rk3066_grf_gpio_lh gpio_pull[7];
+
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+
+ u32 soc_status0;
+
+ u32 dmac1_con[3];
+ u32 dmac2_con[4];
+
+ u32 uoc0_con[3];
+ u32 uoc1_con[4];
+ u32 ddrc_con;
+ u32 ddrc_stat;
+
+ u32 reserved2[10];
+
+ u32 os_reg[4];
+};
+
+check_member(rk3066_grf, os_reg[3], 0x01d4);
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ REG(GPIO1B1, 2, 2),
+ GPIO1B1_GPIO= 0,
+ GPIO1B1_UART2_SOUT,
+
+ REG(GPIO1B0, 0, 0),
+ GPIO1B0_GPIO= 0,
+ GPIO1B0_UART2_SIN
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+ REG(GPIO3B6, 12, 12),
+ GPIO3B6_GPIO= 0,
+ GPIO3B6_SDMMC0_DECTN,
+
+ REG(GPIO3B5, 10, 10),
+ GPIO3B5_GPIO= 0,
+ GPIO3B5_SDMMC0_DATA3,
+
+ REG(GPIO3B4, 8, 8),
+ GPIO3B4_GPIO= 0,
+ GPIO3B4_SDMMC0_DATA2,
+
+ REG(GPIO3B3, 6, 6),
+ GPIO3B3_GPIO= 0,
+ GPIO3B3_SDMMC0_DATA1,
+
+ REG(GPIO3B2, 4, 4),
+ GPIO3B2_GPIO= 0,
+ GPIO3B2_SDMMC0_DATA0,
+
+ REG(GPIO3B1, 2, 2),
+ GPIO3B1_GPIO= 0,
+ GPIO3B1_SDMMC0_CMD,
+
+ REG(GPIO3B0, 0, 0),
+ GPIO3B0_GPIO= 0,
+ GPIO3B0_SDMMC0_CLKOUT,
+};
+
+/* GRF_SOC_CON0 */
+enum {
+ REG(SMC_MUX_CON, 13, 13),
+
+ REG(NOC_REMAP, 12, 12),
+
+ REG(EMMC_FLASH_SEL, 11, 11),
+
+ REG(TZPC_REVISION, 10, 7),
+
+ REG(L2CACHE_ACC, 6, 5),
+
+ REG(L2RD_WAIT, 4, 3),
+
+ REG(IMEMRD_WAIT, 2, 1),
+
+ REG(SOC_REMAP, 0, 0),
+};
+
+/* GRF_SOC_CON1 */
+enum {
+ REG(RKI2C4_SEL, 15, 15),
+
+ REG(RKI2C3_SEL, 14, 14),
+
+ REG(RKI2C2_SEL, 13, 13),
+
+ REG(RKI2C1_SEL, 12, 12),
+
+ REG(RKI2C0_SEL, 11, 11),
+
+ REG(VCODEC_SEL, 10, 10),
+
+ REG(PERI_EMEM_PAUSE, 9, 9),
+
+ REG(PERI_USB_PAUSE, 8, 8),
+
+ REG(SMC_MUX_MODE_0, 6, 6),
+
+ REG(SMC_SRAM_MW_0, 5, 4),
+
+ REG(SMC_REMAP_0, 3, 3),
+
+ REG(SMC_A_GT_M0_SYNC, 2, 2),
+
+ REG(EMAC_SPEED, 1, 1),
+
+ REG(EMAC_MODE, 0, 0),
+};
+
+/* GRF_SOC_CON2 */
+enum {
+ REG(MSCH4_MAINDDR3, 7, 7),
+ MSCH4_MAINDDR3_DDR3 = 1,
+
+ REG(EMAC_NEWRCV_EN, 6, 6),
+
+ REG(SW_ADDR15_EN, 5, 5),
+
+ REG(SW_ADDR16_EN, 4, 4),
+
+ REG(SW_ADDR17_EN, 3, 3),
+
+ REG(BANK2_TO_RANK_EN, 2, 2),
+
+ REG(RANK_TO_ROW15_EN, 1, 1),
+
+ REG(UPCTL_C_ACTIVE_IN, 0, 0),
+ UPCTL_C_ACTIVE_IN_MAY = 0,
+ UPCTL_C_ACTIVE_IN_WILL,
+};
+
+/* GRF_DDRC_CON0 */
+enum {
+ REG(DTO_LB, 12, 11),
+
+ REG(DTO_TE, 10, 9),
+
+ REG(DTO_PDR, 8, 7),
+
+ REG(DTO_PDD, 6, 5),
+
+ REG(DTO_IOM, 4, 3),
+
+ REG(DTO_OE, 2, 1),
+
+ REG(ATO_AE, 0, 0),
+};
+#endif
--
2.20.1
[PATCH v8 01/15] rockchip: rk3066-power: sync power domain dt-binding header from Linux
In order to update the DT for rk3066 sync the power domain dt-binding header. This is the state as of v5.12 in Linux. Signed-off-by: Johan Jonker --- include/dt-bindings/power/rk3066-power.h | 22 ++ 1 file changed, 22 insertions(+) create mode 100644 include/dt-bindings/power/rk3066-power.h diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h new file mode 100644 index ..acf9f310 --- /dev/null +++ b/include/dt-bindings/power/rk3066-power.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ +#define __DT_BINDINGS_POWER_RK3066_POWER_H__ + +/* VD_CORE */ +#define RK3066_PD_A9_0 0 +#define RK3066_PD_A9_1 1 +#define RK3066_PD_DBG 4 +#define RK3066_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3066_PD_VIDEO6 +#define RK3066_PD_VIO 7 +#define RK3066_PD_GPU 8 +#define RK3066_PD_PERI 9 +#define RK3066_PD_CPU 10 +#define RK3066_PD_ALIVE11 + +/* VD_PMU */ +#define RK3066_PD_RTC 12 + +#endif -- 2.20.1
[PATCH v8 00/15] Add Rikomagic MK808 board
MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, HDMI and a micro-SD card slot. It also includes on-board NAND and 1GB of SDRAM. === Boot procedure flow for a Rockchip rk3066 SoC: 1.Read 2K SDRAM initialization image code to internal SRAM 2.Run image code to do SDRAM initialization 3.Transfer boot image code to SDRAM 4.Run boot image code Supported system boot from the following devices: Nand Flash SPI nor Flash eMMC device UART interface If all boot options fail then enter into BootROM mode on the USB OTG port. Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support. The size of a full U-boot binary is too large for the internal SDRAM memory. Of that 64k size only 32kb sram - 2kb bootrom is available for the first stage. Similar to the already supported rk3188, the BootROM will attempt to load up the first stage image in two steps: first 1KB to offset 0x800 in the SRAM and then the remainder to offset 0xc00 in the SRAM. It always enters at offset 0x804 after a 4 ASCII character "RK30" header. With CONFIG_TPL_ROCKCHIP_EARLYRETURN_TO_BROM=y this first stage is combined with the U-boot TPL binary (u-boot-tpl.bin). For rk3066 with NAND flash and U-boot this gives the following stages: - TPL: init external SDRAM - SPL: init SDMMC and read U-boot from SD CARD. - U-boot: read Linux kernel from SD CARD. - Kernel Additionally the rk3066 requires everything the BootROM loads to be RC4-encrypted. === Boot solution with full U-boot stored on SD CARD: Compile commands(U-boot): ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make mk808_defconfig ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make menuconfig ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make all === Size of SPL and TPL must be aligned to 2kb. If bricked and no BootROM mode shows up then connect pin 8 and 9 of the NAND flash with a needle while reconnecting to the USB OTG port to a PC. === Show connected devices with: lsusb Bus 001 Device 004: ID 2207:300a Fuzhou Rockchip Electronics Company RK3066 in Mask ROM mode === Program commands with ./flash.sh: #!/bin/sh printf "RK30" > tplspl.bin dd if=u-boot-tpl.bin >> tplspl.bin truncate -s %2048 tplspl.bin truncate -s %2048 u-boot-spl.bin ../tools/boot_merger --verbose config-flash.ini ../tools/upgrade_tool ul ./RK30xxLoader_uboot.bin === config-flash.ini: [CHIP_NAME] NAME=RK30 [VERSION] MAJOR=2 MINOR=21 [CODE471_OPTION] NUM=1 Path1=30_LPDDR2_300MHz_DD.bin [CODE472_OPTION] NUM=1 Path1=rk30usbplug.bin [LOADER_OPTION] NUM=2 LOADER1=FlashData LOADER2=FlashBoot FlashData=tplspl.bin FlashBoot=u-boot-spl.bin [OUTPUT] PATH=RK30xxLoader_uboot.bin === Partition Map for MMC device 0 -- Partition Type: EFI PartStart LBA End LBA Name Attributes Type GUID Partition GUID 1 0x0040 0x1f7f "loader1" 2 0x4000 0x5fff "loader2" 3 0x6000 0x7fff "trust" 4 0x8000 0x0003 "boot" 5 0x0004 0x00ed7fde "rootfs" Make sure boot and esp flag are set for boot partition. Loader1 not used by === Boot partition: extlinux -- extlinux.conf zImage rk3066a-mk808.dtb === extlinux.conf: label kernel kernel /zImage fdt /rk3066a-mk808.dtb append root=LABEL=linuxroot init=/sbin/init rootfstype=ext4 rootwait === Program commands (SD CARD with GPT partition): sudo dd if=u-boot-dtb.img of=/dev/sda seek=16384 === TODO: Better program flow/tools USB NAND etc etc === Johan Jonker (11): rockchip: rk3066-power: sync power domain dt-binding header from Linux arm: dts: rockchip: fix rk3xxx-u-boot.dtsi arm: dts: rockchip: add rk3066a.dtsi arm: dts: rockchip: add rk3066a-mk808.dts rockchip: rk3066: add include rockchip: rk3066: add rk3066_common.h include rockchip: rk3066: add core support rockchip: rk3066: add Rikomagic MK808 board rockchip: rk3066: add mk808_defconfig rockchip: tools: add rk3066 support to rkcommon.c doc: rockchip: add rk3066 Rikomagic MK808 Paweł Jarosz (4): rockchip: rk3066: add grf header file rockchip: rk3066: add clock driver for rk3066 soc rockchip: rk3066: add rk3066 pinctrl driver rockchip: rk3066: add sdram driver arch/arm/dts/Makefile | 3 + arch/arm/dts/rk3066a-mk808-u-boot.dtsi| 42 + arch/arm/dts/rk3066a-mk808.dts| 216 + arch/arm/dts/rk3066a-u-boot.dtsi | 3 + arch/arm/dts/rk3066a.dtsi | 880 + arch/arm/dts/rk3xxx-u-boot.dtsi | 8 +- arch/arm/include/asm/arch-rk3066/boot0.h | 8 + arch/arm/include/asm/arch-rk3066/gpio.h | 8 + arch/arm/include/asm/arch-rk3066/timer.h | 6 + .../include/asm/arch-rockchip/cru_rk3066.h| 157 +++ .../include/asm/arch-rockchip/grf_rk3066.h| 210 + arch/arm/mach-rockchip/Kconfig| 23 + arch/arm/mach-rockchip/Makefile | 1 +
[PATCH V3] usb: ehci-mx6: Enable OTG detection on imx8mm and imx8mn
The imx8mm and imx8mn appear compatible with imx7d-usb
flags in the OTG driver. If the dr_mode is defined as
host or peripheral, the device appears to operate correctly,
however the auto host/peripheral detection results in an error.
The solution isn't just adding checks for imx8mm and imx8mn to
the check for imx7, because the USB clock needs to be running
to read from the USBNC_PHY_STATUS_OFFSET register or it will hang.
Marek requested that I not enable the clocks in ehci_usb_of_to_plat,
so I modified that function to return an unknown state if the
device tree does not explicitly state whether it is a host
or a peripheral.
When the driver probes, it looks to see if it's in the unknown
state, and only then will it read the register to auto-detect.
Signed-off-by: Adam Ford
---
V3: Keep ehci_usb_of_to_plat but add the ability to return
and unknown state instead of reading the register.
If the probe determines the states is unknown, it will
query the register after the clocks have been enabled.
Because of the slight behavior change, I removed any
review or tested tags.
V2: Rename ehci_usb_of_to_plat to ehci_usb_dr_mode and call it
from the probe after the clocks are enabled, but before
the data is needed.
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 1bd6147c76..cf44e53ff7 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -543,7 +543,7 @@ static int ehci_usb_phy_mode(struct udevice *dev)
plat->init_type = USB_INIT_DEVICE;
else
plat->init_type = USB_INIT_HOST;
- } else if (is_mx7()) {
+ } else if (is_mx7() || is_imx8mm() || is_imx8mn()) {
phy_status = (void __iomem *)(addr +
USBNC_PHY_STATUS_OFFSET);
val = readl(phy_status);
@@ -573,9 +573,8 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
case USB_DR_MODE_PERIPHERAL:
plat->init_type = USB_INIT_DEVICE;
break;
- case USB_DR_MODE_OTG:
- case USB_DR_MODE_UNKNOWN:
- return ehci_usb_phy_mode(dev);
+ default:
+ plat->init_type = USB_INIT_UNKNOWN;
};
return 0;
@@ -677,6 +676,20 @@ static int ehci_usb_probe(struct udevice *dev)
mdelay(1);
#endif
+ /*
+* If the device tree didn't specify host or device,
+* the default is USB_INIT_UNKNOWN, so we need to check
+* the register. For imx8mm and imx8mn, the clocks need to be
+* running first, so we defer the check until they are.
+*/
+ if (priv->init_type == USB_INIT_UNKNOWN) {
+ ret = ehci_usb_phy_mode(dev);
+ if (ret)
+ goto err_clk;
+ else
+ priv->init_type = plat->init_type;
+ }
+
#if CONFIG_IS_ENABLED(DM_REGULATOR)
ret = device_get_supply_regulator(dev, "vbus-supply",
>vbus_supply);
diff --git a/include/usb.h b/include/usb.h
index b3851fdb4f..47d738a786 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -163,7 +163,8 @@ struct int_queue;
*/
enum usb_init_type {
USB_INIT_HOST,
- USB_INIT_DEVICE
+ USB_INIT_DEVICE,
+ USB_INIT_UNKNOWN,
};
/**
--
2.32.0
Re: [PATCH V2] usb: ehci-mx6: Enable OTG detection on imx8mm and imx8mn
On Thu, Jan 13, 2022 at 6:49 PM Adam Ford wrote:
>
> On Thu, Jan 13, 2022 at 6:35 PM Adam Ford wrote:
> >
> > On Wed, Jan 12, 2022 at 2:17 AM Michael Walle wrote:
> > >
> > > Am 2022-01-11 17:52, schrieb Adam Ford:
> > > > On Tue, Jan 11, 2022 at 9:31 AM Michael Walle wrote:
> > > >>
> > > >> Hi,
> > > >>
> > > >> Am 2022-01-11 15:20, schrieb Adam Ford:
> > > >> > On Tue, Jan 4, 2022 at 2:32 AM Michael Walle
> > > >> > wrote:
> > > >> >> > The imx8mm and imx8mn appear compatible with imx7d-usb
> > > >> >> > flags in the OTG driver. If the dr_mode is defined as
> > > >> >> > host or peripheral, the device appears to operate correctly,
> > > >> >> > however the auto host/peripheral detection results in an error.
> > > >> >> >
> > > >> >> > The solution isn't just adding checks for imx8mm and imx8mn to
> > > >> >> > the check for imx7, because the USB clock needs to be running
> > > >> >> > to read from the USBNC_PHY_STATUS_OFFSET register or it will hang.
> > > >> >> >
> > > >> >> > The init_type in both priv and plat data are the same, so it
> > > >> >> > doesn't
> > > >> >> > make sense to configure the data in the plat data and copy the
> > > >> >> > data to priv when priv can be configured directly. Instead,
> > > >> >> > rename
> > > >> >> > ehci_usb_of_to_plat to ehci_usb_dr_mode and call it from the
> > > >> >> > probe functions after the clocks are enabled, but before the data
> > > >> >> > is required.
> > > >> >> >
> > > >> >> > With that added, the additional checks for imx8mm and imx8mn will
> > > >> >> > allow reading the register to automatically determine the state
> > > >> >> > (host or device) of the OTG controller.
> > > >> >> >
> > > >> >> > Signed-off-by: Adam Ford
> > > >> >> > ---
> > > >> >> > V2: Rename ehci_usb_of_to_plat to ehci_usb_dr_mode and call it
> > > >> >> > from the probe after the clocks are enabled, but before
> > > >> >> > the data is needed.
> > > >> >> >
> > > >> >> > diff --git a/drivers/usb/host/ehci-mx6.c
> > > >> >> > b/drivers/usb/host/ehci-mx6.c
> > > >> >> > index 1bd6147c76..f2a34b7f06 100644
> > > >> >> > --- a/drivers/usb/host/ehci-mx6.c
> > > >> >> > +++ b/drivers/usb/host/ehci-mx6.c
> > > >> >>
> > > >> >> ..
> > > >> >>
> > > >> >> > @@ -639,10 +639,8 @@ static int mx6_parse_dt_addrs(struct udevice
> > > >> >> > *dev)
> > > >> >> >
> > > >> >> > static int ehci_usb_probe(struct udevice *dev)
> > > >> >> > {
> > > >> >> > - struct usb_plat *plat = dev_get_plat(dev);
> > > >> >> > struct usb_ehci *ehci = dev_read_addr_ptr(dev);
> > > >> >> > struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
> > > >> >> > - enum usb_init_type type = plat->init_type;
> > > >> >> > struct ehci_hccr *hccr;
> > > >> >> > struct ehci_hcor *hcor;
> > > >> >> > int ret;
> > > >> >> > @@ -660,8 +658,6 @@ static int ehci_usb_probe(struct udevice *dev)
> > > >> >> > return ret;
> > > >> >> >
> > > >> >> > priv->ehci = ehci;
> > > >> >> > - priv->init_type = type;
> > > >> >>
> > > >> >
> > > >> > Michael,
> > > >> >
> > > >> >> I'm not sure this is correct. There is also this:
> > > >> >> https://elixir.bootlin.com/u-boot/v2022.01-rc4/source/drivers/usb/host/usb-uclass.c#L407
> > > >> >>
> > > >> >
> > > >> > Further down in the code, you should see:
> > > >> > priv->phy_type = usb_get_phy_mode(dev_ofnode(dev));
> > > >>
> > > >> But that is just fetching the mode from the device tree, the
> > > >> usb_setup_ehci_gadget() referenced above, change the mode during
> > > >> runtime by writing the plat->init_type and reprobing the device.
> > > >>
> > > >> >> Which won't work anymore. usb_setup_ehci_gadget() is called from
> > > >> >> usb_gadget_register_driver() in ci_udc.c. The latter is the one used
> > > >> >> on the imx, right? But I might be wrong. I'm still trying to figure
> > > >> >> out how this all works together, because I also try to get OTG
> > > >> >> running on the dwc3 driver. It looks like the ci_udc.c is special
> > > >> >> here, and I wonder how a transition to UCLASS_USB_GADGET_GENERIC
> > > >> >> might look like for this driver.
> > > >> >
> > > >> > This driver really isn't changing anything, it's just an order of
> > > >> > operations.
> > > >>
> > > >> It doesn't use the plat->init_type at all anymore, no?
> > > >
> > > > From what I could tell, the only thing that plat->init_type did was to
> > > > set priv->init_type.
> > > > The priv structure appears to do most of the work.
> > >
> > > but plat->init_type seems to change during runtime (by
> > > usb_setup_ehci_gadget()) and with this patch applied, it doesn't
> > > do that anymore.
> > >
> > > >> > Previously there was a separate that was being called to
> > > >> > determine the init_type as being either a peripheral or host. If it
> > > >> > wasn't explicitly set in the device tree, the helper function would
> > > >> > query a register, however, on the imx8mm and imx8mn platforms, the
> > > >> > clocks were not
[PATCH V2] phy: nop-phy: Enable reset-gpios support
Some usb-nop-xceiv devices use a gpio to put them in and
out of reset. Add a reset function to put them into that
state. This is similar to how Linux handles the
usb-nop-xceiv driver.
Signed-off-by: Adam Ford
---
V2: Only use the GPIO functions when DM_GPIO is enabled
Add error handling so if the GPIO fails, it will shutdown
the clocks and return with the error code.
Call nop_phy_reset() instead of repeating the same code.
diff --git a/drivers/phy/nop-phy.c b/drivers/phy/nop-phy.c
index 9f12ebc062..2be3d4039b 100644
--- a/drivers/phy/nop-phy.c
+++ b/drivers/phy/nop-phy.c
@@ -10,17 +10,47 @@
#include
#include
#include
+#include
struct nop_phy_priv {
struct clk_bulk bulk;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct gpio_desc reset_gpio;
+#endif
};
+#if CONFIG_IS_ENABLED(DM_GPIO)
+static int nop_phy_reset(struct phy *phy)
+{
+ struct nop_phy_priv *priv = dev_get_priv(phy->dev);
+
+ /* Return if there is no gpio since it's optional */
+ if (!dm_gpio_is_valid(>reset_gpio))
+ return 0;
+
+ return dm_gpio_set_value(>reset_gpio, false);
+}
+#endif
+
static int nop_phy_init(struct phy *phy)
{
struct nop_phy_priv *priv = dev_get_priv(phy->dev);
+ int ret = 0;
+
+ if (CONFIG_IS_ENABLED(CLK)) {
+ ret = clk_enable_bulk(>bulk);
+ if (ret)
+ return ret;
+ }
- if (CONFIG_IS_ENABLED(CLK))
- return clk_enable_bulk(>bulk);
+ if (CONFIG_IS_ENABLED(DM_GPIO)) {
+ ret = nop_phy_reset(phy);
+ if (ret) {
+ if (CONFIG_IS_ENABLED(CLK))
+ clk_disable_bulk(>bulk);
+ return ret;
+ }
+ }
return 0;
}
@@ -38,6 +68,12 @@ static int nop_phy_probe(struct udevice *dev)
}
}
+ ret = gpio_request_by_name(dev, "reset-gpios", 0,
+ >reset_gpio,
+ GPIOD_IS_OUT);
+ if (ret != -ENOENT)
+ return ret;
+
return 0;
}
@@ -49,6 +85,7 @@ static const struct udevice_id nop_phy_ids[] = {
static struct phy_ops nop_phy_ops = {
.init = nop_phy_init,
+ .reset = nop_phy_reset,
};
U_BOOT_DRIVER(nop_phy) = {
--
2.32.0
[PATCH] imx8mn-ddr4-evk: generate single bootable image
As suggested in commit 028abfd9b157 ("imx8mm-evk: Generate a single
bootable flash.bin again") for imx8mm_evk, it is possible to produce
single bootable image via binman. This restores the original behavior in
distros, where only one boot container is used to create target image.
Perform similar adaptions in order to provide single bootable image for
imx8mn-ddr4-evk derivate.
Update documentation to drop additional step of copying u-boot.itb
Fixes: 353dfe4b4359 ("imx8mn-ddr4-evk: switch to use binman")
Signed-off-by: Andrey Zhizhikin
---
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++-
.../imx8mn_evk/imximage-8mn-ddr4.cfg | 2 +-
doc/board/nxp/imx8mn_evk.rst | 1 -
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 1d3844437d..2e39790766 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -157,7 +157,9 @@
};
- flash {
+ spl {
+ filename = "spl.bin";
+
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x912000";
@@ -224,4 +226,19 @@
};
};
};
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl.bin";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x58000>;
+ filename = "u-boot.itb";
+ };
+ };
};
diff --git a/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg
b/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg
index 22aec26da7..7286b26494 100644
--- a/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg
+++ b/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg
@@ -7,4 +7,4 @@
ROM_VERSIONv2
BOOT_FROM sd
-LOADER mkimage.flash.mkimage 0x912000
+LOADER u-boot-spl-ddr.bin 0x912000
diff --git a/doc/board/nxp/imx8mn_evk.rst b/doc/board/nxp/imx8mn_evk.rst
index 9fbb947032..711545af89 100644
--- a/doc/board/nxp/imx8mn_evk.rst
+++ b/doc/board/nxp/imx8mn_evk.rst
@@ -50,7 +50,6 @@ Burn the flash.bin to MicroSD card offset 32KB:
.. code-block:: bash
$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
- $sudo dd if=u-boot.itb of=/dev/sd[x] bs=1024 seek=384 conv=notrunc
Boot
base-commit: 4e81f3be340072ad2c0aac093677333702f14f22
--
2.25.1
[PATCH] cmd: mmc: Consider GP partitions in mmc hwpartition user enh start -
In case the eMMC contains any GP partitions or user sets up new GP
partitions, the size of these GP partitions reduce the size of the
USER partition. Subtract the size of those GP partitions from the
calculated size of USER partition when using `user enh start -`.
The following test used to fail before:
```
u-boot=> mmc hwpartition gp1 524288 enh user enh 0 - wrrel on check
Partition configuration:
User Enhanced Start: 0 Bytes
User Enhanced Size: 1.8 GiB
User partition write reliability: on
GP1 Capacity: 256 MiB ENH
No GP2 partition
No GP3 partition
No GP4 partition
Total enhanced size exceeds maximum (261 > 229)
Failed!
```
The test now passes:
```
u-boot=> mmc hwpartition gp1 524288 enh user enh 0 - wrrel on check
Partition configuration:
User Enhanced Start: 0 Bytes
User Enhanced Size: 1.5 GiB
User partition write reliability: on
GP1 Capacity: 256 MiB ENH
No GP2 partition
No GP3 partition
No GP4 partition
```
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Jaehoon Chung
Cc: Peng Fan
Cc: Stefano Babic
---
cmd/mmc.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 96d81ffdf36..503dbb6199c 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -597,7 +597,7 @@ static void parse_hwpart_user_enh_size(struct mmc *mmc,
struct mmc_hwpart_conf *pconf,
char *argv)
{
- int ret;
+ int i, ret;
pconf->user.enh_size = 0;
@@ -606,7 +606,7 @@ static void parse_hwpart_user_enh_size(struct mmc *mmc,
ret = mmc_send_ext_csd(mmc, ext_csd);
if (ret)
return;
- /* This value is in 512B block units */
+ /* The enh_size value is in 512B block units */
pconf->user.enh_size =
((ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 2] << 16) +
(ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT + 1] << 8) +
@@ -614,6 +614,24 @@ static void parse_hwpart_user_enh_size(struct mmc *mmc,
ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
pconf->user.enh_size -= pconf->user.enh_start;
+ for (i = 0; i < ARRAY_SIZE(mmc->capacity_gp); i++) {
+ /*
+* If the eMMC already has GP partitions set,
+* subtract their size from the maximum USER
+* partition size.
+*
+* Else, if the command was used to configure new
+* GP partitions, subtract their size from maximum
+* USER partition size.
+*/
+ if (mmc->capacity_gp[i]) {
+ /* The capacity_gp is in 1B units */
+ pconf->user.enh_size -= mmc->capacity_gp[i] >>
9;
+ } else if (pconf->gp_part[i].size) {
+ /* The gp_part[].size is in 512B units */
+ pconf->user.enh_size -= pconf->gp_part[i].size;
+ }
+ }
} else {
pconf->user.enh_size = dectoul(argv, NULL);
}
--
2.34.1
[PATCH] arm: dts: imx8mq kernel dts updates
Update to the 5.16 imx8mq dts files and dt bindings
Signed-off-by: Angus Ainslie
---
arch/arm/dts/imx8mq.dtsi | 203 --
include/dt-bindings/interconnect/imx8mq.h | 48 +
include/dt-bindings/rfkill/rfkill.h | 21 +++
3 files changed, 259 insertions(+), 13 deletions(-)
create mode 100644 include/dt-bindings/interconnect/imx8mq.h
create mode 100644 include/dt-bindings/rfkill/rfkill.h
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index a44f729d0e..71bf497f99 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -11,6 +11,7 @@
#include "dt-bindings/input/input.h"
#include
#include
+#include
#include "imx8mq-pinfunc.h"
/ {
@@ -39,8 +40,6 @@
spi0 =
spi1 =
spi2 =
- usb0 = _dwc3_0;
- usb1 = _dwc3_1;
};
ckil: clock-ckil {
@@ -194,7 +193,6 @@
compatible = "arm,cortex-a53-pmu";
interrupts = ;
interrupt-parent = <>;
- interrupt-affinity = <_0>, <_1>, <_2>, <_3>;
};
psci {
@@ -288,11 +286,13 @@
};
soc@0 {
- compatible = "simple-bus";
+ compatible = "fsl,imx8mq-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e00>;
dma-ranges = <0x4000 0x0 0x4000 0xc000>;
+ nvmem-cells = <_uid>;
+ nvmem-cell-names = "soc_unique_id";
bus@3000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
@@ -557,9 +557,17 @@
#address-cells = <1>;
#size-cells = <1>;
+ imx8mq_uid: soc-uid@410 {
+ reg = <0x4 0x8>;
+ };
+
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
+
+ fec_mac_address: mac-address@90 {
+ reg = <0x90 6>;
+ };
};
anatop: syscon@3036 {
@@ -828,6 +836,8 @@
clocks = < IMX8MQ_CLK_ECSPI1_ROOT>,
< IMX8MQ_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
+ dmas = < 0 7 1>, < 1 7 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -840,6 +850,8 @@
clocks = < IMX8MQ_CLK_ECSPI2_ROOT>,
< IMX8MQ_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
+ dmas = < 2 7 1>, < 3 7 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -852,6 +864,8 @@
clocks = < IMX8MQ_CLK_ECSPI3_ROOT>,
< IMX8MQ_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
+ dmas = < 4 7 1>, < 5 7 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -1018,9 +1032,14 @@
reg = <0x30a00300 0x100>;
clocks = < IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "phy_ref";
- assigned-clocks = < IMX8MQ_CLK_DSI_PHY_REF>;
- assigned-clock-parents = <
IMX8MQ_VIDEO_PLL1_OUT>;
- assigned-clock-rates = <2400>;
+ assigned-clocks = <
IMX8MQ_VIDEO_PLL1_REF_SEL>,
+ <
IMX8MQ_VIDEO_PLL1_BYPASS>,
+ < IMX8MQ_CLK_DSI_PHY_REF>,
+ < IMX8MQ_VIDEO_PLL1>;
+ assigned-clock-parents = < IMX8MQ_CLK_25M>,
+ < IMX8MQ_VIDEO_PLL1>,
+ < IMX8MQ_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <0>, <0>, <2400>,
<59400>;
#phy-cells = <0>;
power-domains = <_mipi>;
status = "disabled";
@@ -1077,6 +1096,110 @@
status = "disabled";
};
+ mipi_csi1: csi@30a7 {
+
Re: [PATCH 1/1] mkimage: struct stat.st_size may not be long
> Date: Mon, 17 Jan 2022 21:20:58 +0100
> From: Milan P. Stanić
>
> It fixes these warnings below.
>
> On Sat, 2022-01-15 at 20:12, Heinrich Schuchardt wrote:
> > The component st_size of struct stat is of type off_t. Depending on the
> > system printing it it with %ld leads to a warning:
> >
> > tools/mkimage.c:438:54: warning: format '%ld' expects argument of type
> > 'long int', but argument 5 has type
> > 'off_t' {aka 'long long int'} [-Wformat=]
> > 438 | "%s: Bad size: \"%s\" is not valid image: size %ld < %u\n",
> > |~~^
> > | |
> > | long int
> > |%lld
> >
> > When comparing an off_t value to a 32bit integer we should not convert to
> > uint32_t but to off_t which may be wider.
> >
> > Reported-by: Milan P. Stanić
> > Fixes: 331f0800f1a3 ("mkimage: allow -l to work on block devices on Linux")
> > Signed-off-by: Heinrich Schuchardt
>
> Tested by: Milan P. Stanić
This will also fix a warning on OpenBSD. So:
Reviewed-by: Mark Kettenis
> > ---
> > tools/mkimage.c | 7 ---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/tools/mkimage.c b/tools/mkimage.c
> > index fbe883ce36..79042be828 100644
> > --- a/tools/mkimage.c
> > +++ b/tools/mkimage.c
> > @@ -433,11 +433,12 @@ int main(int argc, char **argv)
> > params.cmdname, params.imagefile);
> > exit (EXIT_FAILURE);
> > #endif
> > - } else if ((unsigned)sbuf.st_size < tparams->header_size) {
> > + } else if (sbuf.st_size < (off_t)tparams->header_size) {
> > fprintf (stderr,
> > - "%s: Bad size: \"%s\" is not valid image: size
> > %ld < %u\n",
> > + "%s: Bad size: \"%s\" is not valid image: size
> > %llu < %u\n",
> > params.cmdname, params.imagefile,
> > - sbuf.st_size, tparams->header_size);
> > + (unsigned long long) sbuf.st_size,
> > + tparams->header_size);
> > exit (EXIT_FAILURE);
> > } else {
> > size = sbuf.st_size;
> > --
> > 2.33.1
> >
>
Re: [PATCH 1/1] mkimage: struct stat.st_size may not be long
It fixes these warnings below.
On Sat, 2022-01-15 at 20:12, Heinrich Schuchardt wrote:
> The component st_size of struct stat is of type off_t. Depending on the
> system printing it it with %ld leads to a warning:
>
> tools/mkimage.c:438:54: warning: format '%ld' expects argument of type
> 'long int', but argument 5 has type
> 'off_t' {aka 'long long int'} [-Wformat=]
> 438 | "%s: Bad size: \"%s\" is not valid image: size %ld < %u\n",
> |~~^
> | |
> | long int
> |%lld
>
> When comparing an off_t value to a 32bit integer we should not convert to
> uint32_t but to off_t which may be wider.
>
> Reported-by: Milan P. Stanić
> Fixes: 331f0800f1a3 ("mkimage: allow -l to work on block devices on Linux")
> Signed-off-by: Heinrich Schuchardt
Tested by: Milan P. Stanić
> ---
> tools/mkimage.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/tools/mkimage.c b/tools/mkimage.c
> index fbe883ce36..79042be828 100644
> --- a/tools/mkimage.c
> +++ b/tools/mkimage.c
> @@ -433,11 +433,12 @@ int main(int argc, char **argv)
> params.cmdname, params.imagefile);
> exit (EXIT_FAILURE);
> #endif
> - } else if ((unsigned)sbuf.st_size < tparams->header_size) {
> + } else if (sbuf.st_size < (off_t)tparams->header_size) {
> fprintf (stderr,
> - "%s: Bad size: \"%s\" is not valid image: size
> %ld < %u\n",
> + "%s: Bad size: \"%s\" is not valid image: size
> %llu < %u\n",
> params.cmdname, params.imagefile,
> - sbuf.st_size, tparams->header_size);
> + (unsigned long long) sbuf.st_size,
> + tparams->header_size);
> exit (EXIT_FAILURE);
> } else {
> size = sbuf.st_size;
> --
> 2.33.1
>
Re: [PATCH v2] image-board: fix wrong implementation ram disk address setup from cmdline
On Thu, Nov 25, 2021 at 11:08:59AM +0800, Artem Lapkin wrote:
> Problem
>
> Wrong implementation logic: ramdisk cmdline image address always ignored!
> Next block { rd_addr = hextoul(select, NULL) } unusable for raw initrd.
>
> We have unbootable raw initrd images because, select_ramdisk for raw
> initrd images ignore submited select addr and setup rd_datap value to 0
>
> Signed-off-by: Artem Lapkin
> Reviewed-by: Simon Glass
> ---
> V2 changes
> _ rebase to master
> _ from
> https://patchwork.ozlabs.org/project/uboot/patch/20211016051915.4157293-1-...@khadas.com/
> ---
> boot/image-board.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/boot/image-board.c b/boot/image-board.c
> index bf8817165c..87a8f07432 100644
> --- a/boot/image-board.c
> +++ b/boot/image-board.c
> @@ -334,7 +334,7 @@ static int select_ramdisk(bootm_headers_t *images, const
> char *select, u8 arch,
>
> if (select) {
> ulong default_addr;
> - bool done = true;
> + bool done = false;
>
> if (CONFIG_IS_ENABLED(FIT)) {
> /*
> @@ -352,13 +352,13 @@ static int select_ramdisk(bootm_headers_t *images,
> const char *select, u8 arch,
> _uname_config)) {
> debug("* ramdisk: config '%s' from image at
> 0x%08lx\n",
> fit_uname_config, rd_addr);
> + done = true;
> } else if (fit_parse_subimage(select, default_addr,
> _addr,
> _uname_ramdisk)) {
> debug("* ramdisk: subimage '%s' from image at
> 0x%08lx\n",
> fit_uname_ramdisk, rd_addr);
> - } else {
> - done = false;
> + done = true;
> }
> }
> if (!done) {
I think we still need this? Can you please confirm and if so rebase to
master again, sorry, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH 02/13] arm: dts: add the Purism devicetree files
On Mon, Jan 17, 2022 at 10:52:42AM -0800, Angus Ainslie wrote: > On 2022-01-17 10:25, Tom Rini wrote: > > On Mon, Jan 17, 2022 at 09:51:24AM -0800, Angus Ainslie wrote: > > > > > > There's 2 ways to solve the this I think. > > > > > > 1) just use the latest librem5 dts file which is made up of 3 > > > different > > > dts(i) files. > > > 2) have a defconfig for each of the different PCB versions. > > > > > > Do you have a preference ? > > > > Can you tell the revision at run-time? We have examples of boards that > > can and will include revA.dtb and revB.dtb and select the correct one at > > run time (and start with something that works on revA and revB). > > Due to some changes by NXP in the fuse section of the imx8mq we can't > reliably detect some of the earlier revisions. > > Going forward we should be able to using this > > https://lists.denx.de/pipermail/u-boot/2021-November/468419.html > > But that will be post r4 boards. Ah "fun". I guess I'd lean towards #1 then if you think that'll be easy enough on the end users too. -- Tom signature.asc Description: PGP signature
Re: [PATCH 02/13] arm: dts: add the Purism devicetree files
On 2022-01-17 10:25, Tom Rini wrote: On Mon, Jan 17, 2022 at 09:51:24AM -0800, Angus Ainslie wrote: There's 2 ways to solve the this I think. 1) just use the latest librem5 dts file which is made up of 3 different dts(i) files. 2) have a defconfig for each of the different PCB versions. Do you have a preference ? Can you tell the revision at run-time? We have examples of boards that can and will include revA.dtb and revB.dtb and select the correct one at run time (and start with something that works on revA and revB). Due to some changes by NXP in the fuse section of the imx8mq we can't reliably detect some of the earlier revisions. Going forward we should be able to using this https://lists.denx.de/pipermail/u-boot/2021-November/468419.html But that will be post r4 boards.
Re: [PATCH] gpio: da8xx_gpio: Fix gpio name with address
On Fri, Jan 07, 2022 at 11:26:24AM +0800, chaochao2021...@163.com wrote: > From: chao zeng > > The GPIO bank numbers do not appear in the device tree, > so make the gpio name based on the address > (ie gpio@4211_25 vs 25) > > Signed-off-by: chao zeng Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 7/8] ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPL
On Fri, Dec 24, 2021 at 12:55:35PM +0530, Vignesh Raghavendra wrote: > Enable Second Ethernet port on which ROM support Ethboot. > > Signed-off-by: Vignesh Raghavendra Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 5/8] mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMAC
On Fri, Dec 24, 2021 at 12:55:33PM +0530, Vignesh Raghavendra wrote: > This is required to enables spl_net boot on AM64x > > Signed-off-by: Vignesh Raghavendra Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/8] mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL
On Fri, Dec 24, 2021 at 12:55:32PM +0530, Vignesh Raghavendra wrote: > In order to support Ethernet boot on AM64x, probe AM65 CPSW NUSS. > > Signed-off-by: Vignesh Raghavendra Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/8] board: ti: am64x: Init DRAM size in R5/A53 SPL
On Fri, Dec 24, 2021 at 12:55:31PM +0530, Vignesh Raghavendra wrote: > Call dram_init_banksize() from spl_board_init() otherwise TFTP download > fails due to lmb_get_free_size() not able to find unreserved region due > to lack of DRAM size info. Required to support Ethernet boot on AM64x. > > Signed-off-by: Vignesh Raghavendra Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/8] net: ti: am65-cpsw: Add support for multi port independent MAC mode
On Fri, Dec 24, 2021 at 12:55:30PM +0530, Vignesh Raghavendra wrote: > On certain TI SoC, like AM64x there is a CPSW3G which supports 2 > external independent MAC ports for single CPSW instance. > It is not possible for Ethernet driver to register more than one port > for given instance. > > This patch modifies top level CPSW NUSS as UCLASS_MISC and binds > UCLASS_ETH to individual ports so as to support bring up more than one > Ethernet interface in U-Boot. > > Note that there is no isolation in the since, CPSW NUSS is in promisc > mode and forwards all packets to host. > > Since top level driver is now UCLASS_MISC, board files would need to > instantiate this driver explicitly. > > Signed-off-by: Vignesh Raghavendra Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/8] mach-k3: common: Instantiate AM65 CPSW NUSS wrapper
On Fri, Dec 24, 2021 at 12:55:29PM +0530, Vignesh Raghavendra wrote: > Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver > is enabled. Since driver is modeled as UCLASS_MISC, we need to > explicitly probe the driver. Use common misc_init_r() that entire > K3 family of SoCs. > > Signed-off-by: Vignesh Raghavendra Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] dma: ti: k3-udma: Fix rflow reservation for PKTDMA
On Thu, Dec 23, 2021 at 07:27:30PM +0530, Vignesh Raghavendra wrote: > Driver has a bug in that it uses rflow_in_use bitmap when setting up free > rflow range > from TISCI but use rflow_map for reservation in __udma_reserve_rflow() > > Fix this by dropping rflow_in_use bitmap array and use rflow_map for > PKTDMA. BCDMA does not need rflow_in_use either. > > This fixes CPSW3g not able to get DMA channels at R5 SPL on AM64x > > Signed-off-by: Vignesh Raghavendra Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] ARM: mach-k3: sysfw-loader: Copy sysfw.itb to OCRAM in OSPI/SPI bootmode
On Thu, Dec 23, 2021 at 07:26:03PM +0530, Vignesh Raghavendra wrote: > In case of xSPI bootmode OSPI flash is in DDR mode and needs to be accessed > in multiple of 16bit accesses Hence we cannot parse sysfw.itb FIT image > directly on OSPI flash via MMIO window. So, copy the image to internal > on-chip RAM before parsing the image. > > Moreover, board cfg data maybe modified by ROM/TIFS in case of HS platform > and thus cannot reside in OSPI/xSPI and needs to be copied over to > internal OCRAM. > > This unblocks OSPI/xSPI boot on HS platforms > > Signed-off-by: Vignesh Raghavendra > Reviewed-by: Dave Gerlach > Tested-by: Keerthy > Acked-by: Pratyush Yadav Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] omap: timer: implement timer_get_boot_us
On Thu, Dec 16, 2021 at 10:57:29AM +0100, Christian Gmeiner wrote: > To make the OMAP DM timer driver useful for the timing of > bootstages, we need to implement timer_get_boot_us(..). > > Signed-off-by: Christian Gmeiner Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm: mach-k3: am642_init: Unlock MCU PADCFG regs
On Wed, Dec 15, 2021 at 04:14:28PM +0100, Christian Gmeiner wrote: > From: Michael Liebert > > Currently only the PADCFG registers of the main domain are unlocked. > Also unlock PADCFG registers of MCU domain, so MCU pin muxing can be > configured by u-boot or Linux. > > Signed-off-by: Michael Liebert > Tested-by: Christian Gmeiner > Acked-by: Nishanth Menon Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] configs: am43xx_hs_evm: Add SPL_USB_STORAGE Support
On Mon, Dec 06, 2021 at 06:22:00PM +0100, Amjad Ouled-Ameur wrote: > Enable CONFIG_SPL_USB_STORAGE to support UBS MSC boot support. > > Signed-off-by: Faiz Abbas > Signed-off-by: Amjad Ouled-Ameur Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372
On Tue, Nov 30, 2021 at 01:06:56AM +0100, Stefan Mätje wrote: > On AM4372 the SPI_GCLK input gets its clock from the PRCM module which > divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4. > See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration. > > The QSPI_FCLK therefore needs to take this factor into account and > becomes (19200 / 4). > > Signed-off-by: Stefan Mätje Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] nand: gpmc: Handle bitflips in erased pages when using BCH ECC engine
On Thu, Nov 18, 2021 at 01:25:24PM -0500, David Rivshin wrote: > From: David Rivshin > > In the case of an erased (sub)page both the data and ECC are all 0xFF > bytes. This fails the normal ECC verification, as the computed ECC of > all-0xFF is not also 0xFF. The GPMC NAND driver attempted to detect > erased pages by checking that the ECC bytes are all-0xFF, but this had > two problems: > 1) bitflips in the data were not corrected, so the data looked not-erased > 2) bitflips in the ECC bytes were reported as uncorrectable ECC errors > > The equivalent Linux driver [1] correctly handles this by counting the > number of 0-bits in the combination of data and ECC bytes. If the number > of 0-bits is less than the amount of bits correctable by the selected > ECC algorithm, then it is treated as an erased page with correctable > bitflips. > > Implement similar, though simplified, logic in omap_correct_data_bch(). > > [1] see omap_elm_correct_data() in omap2.c > > Signed-off-by: David Rivshin Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] board: ti: am335x: Choose CPSW or PRUSS configuration based on jumper setting
On Fri, Oct 29, 2021 at 04:08:17PM +0200, Amjad Ouled-Ameur wrote: > The am335x-ice-v2 board's Ethernet ports can be configured > in 'MII' or 'RMII' mode to be connected to 'PRUSS' or 'CPSW' > Ethernet subsystems. > > This patch sets the environment variable 'ice_mii' to > 'mii' or 'rmii' accordingly. Based on that we choose the > appropriate board devicetree i.e. 'am335x-ice-v2.dtb' or > 'am335x-ice-v2-prueth.dtb'. > > Since there are 2 Ethernet ports with 2 modes, there can be 4 > configurations but for now we consider both ports in different modes > to be an invalid configuration and prevent boot in that case. > > Signed-off-by: Roger Quadros > [Amjad: use overlay instead of using new am335x-ice-v2-prueth.dtb] > Signed-off-by: Amjad Ouled-Ameur > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 02/13] arm: dts: add the Purism devicetree files
On Mon, Jan 17, 2022 at 09:51:24AM -0800, Angus Ainslie wrote: > Hi Tom, > > On 2022-01-17 08:59, Tom Rini wrote: > > On Mon, Jan 17, 2022 at 07:07:24AM -0800, Angus Ainslie wrote: > > > > > Initial commit of Librem5 devicetree files > > > > > > Signed-off-by: Angus Ainslie > > > > Please note what kernel release the not -u-boot.dtsi files are a copy > > from, as they need to be copies and not modified, thanks. > > There's an issue with adding the devicetree from the 5.16 kernel. > > I get a compilation error due to a :missing .h in the devicetree files: > > In file included from arch/arm/dts/imx8mq-librem5-r3.dtsi:11, > from arch/arm/dts/.imx8mq-librem5.dtb.pre.tmp:6: > arch/arm/dts/imx8mq-librem5.dtsi:13:10: fatal error: > dt-bindings/rfkill/rfkill.h: No such file or directory >13 | #include "dt-bindings/rfkill/rfkill.h" > | ^ > > Should that get added to the u-boot source as well or should I modify the > dts to remove this ? Import the missing binding(s) in a separate commit first please. > For the kernel we also have 4 different dts files for the differences in PCB > versions. For u-boot we don't need the differentiation as it deals with > things like camera rotation and prox sensor sensitivity. > > There's 2 ways to solve the this I think. > > 1) just use the latest librem5 dts file which is made up of 3 different > dts(i) files. > 2) have a defconfig for each of the different PCB versions. > > Do you have a preference ? Can you tell the revision at run-time? We have examples of boards that can and will include revA.dtb and revB.dtb and select the correct one at run time (and start with something that works on revA and revB). -- Tom signature.asc Description: PGP signature
Re: [PATCH V3] sf: Querying write-protect status before operating the flash
On Thu, Jan 13, 2022 at 08:38:04AM +0100, Jan Kiszka wrote:
> On 17.11.21 12:59, Tom Rini wrote:
> > On Wed, Nov 17, 2021 at 01:43:28PM +0530, Jagan Teki wrote:
> > > On Wed, Nov 17, 2021 at 1:33 PM Michael Walle wrote:
> > > >
> > > > Hi,
> > > >
> > > > Am 2021-11-17 03:48, schrieb chaochao2021...@163.com:
> > > > > From: chao zeng
> > > > >
> > > > > When operating the write-protection flash,spi_flash_std_write() and
> > > > > spi_flash_std_erase() would return wrong result.The flash is
> > > > > protected,
> > > > > but write or erase the flash would show "OK".
> > > > >
> > > > > Check the flash write protection state before operating the flash
> > > > > and give a prompt to show it has been locked if the write-protection
> > > > > has enbale
> > > > >
> > > > > Signed-off-by: chao zeng
> > > > >
> > > > > ---
> > > > >
> > > > > Changes for V2:
> > > > > - Return 0 not ENOPROTOOPT to refelect the flash feature
> > > > > - Output prompt information
> > > > > Changes for V3:
> > > > > - Modify output information
> > > > > - Delete return statement
> > > > > ---
> > > > > drivers/mtd/spi/sf_probe.c | 6 ++
> > > > > 1 file changed, 6 insertions(+)
> > > > >
> > > > > diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> > > > > index f461082e03..f9e879aec5 100644
> > > > > --- a/drivers/mtd/spi/sf_probe.c
> > > > > +++ b/drivers/mtd/spi/sf_probe.c
> > > > > @@ -109,6 +109,9 @@ static int spi_flash_std_write(struct udevice
> > > > > *dev, u32 offset, size_t len,
> > > > >struct mtd_info *mtd = >mtd;
> > > > >size_t retlen;
> > > > >
> > > > > + if (flash->flash_is_locked && flash->flash_is_locked(flash,
> > > > > offset,
> > > > > len))
> > > > > + printf("SF: Operate on the protected area.Writes will be
> > > > > ignored\n");
> > > >
> > > > I don't think this is the correct place for this output. This could
> > > > also be called from a board file programmatically and then it might
> > > > display this error, which is annoying.
> > > >
> > > > Also, this is issuing an additional command "read SR" for every write.
> > > >
> > > > What is your intention here? To make the user aware that he is going
> > > > to write to a write-protected region when he is using the "sf" command?
> > > > If that is the case, this should be added to that command instead.
> > > >
> > > > > +
> > > > >return mtd->_write(mtd, offset, len, , buf);
> > > > > }
> > > > >
> > > > > @@ -127,6 +130,9 @@ static int spi_flash_std_erase(struct udevice
> > > > > *dev, u32 offset, size_t len)
> > > > >instr.addr = offset;
> > > > >instr.len = len;
> > > > >
> > > > > + if (flash->flash_is_locked && flash->flash_is_locked(flash,
> > > > > offset,
> > > > > len))
> > > > > + printf("SF: Operate on the protected area.Erase will be
> > > > > ignored\n");
> > >
> > > My fundamental question, why cannot we use 'sf protect' then 'sf write'?
> >
> > Where do we tell people to always run "sf protect" before "sf write" and
> > why is that at all user friendly? No, we shouldn't run this test more
> > than once per time we're told to write an image. But silently failing
> > in cases we can detect a problem is also not correct. If it's possible
> > to spot this easily with "sf protect" why not just do that as part of
> > "sf write" and add a flag to skip the check if you know it's not needed?
> > I assume it's a fairly cheap/quick operation to do this check.
> >
>
> What's the status here? Who should propose/implement what now?
Good question. Re-reading the quoted part here, the (valid!) concern I
see on the one hand is that today you can "sf write", see "OK" and have
had nothing written because the flash was protected, and that's
something we could have known at the start of "sf write". The change as
written is within the write API, rather than the CLI API, so could we
move that check to cmd/sf.c instead?
--
Tom
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Re: [PATCH 02/13] arm: dts: add the Purism devicetree files
Hi Tom, On 2022-01-17 08:59, Tom Rini wrote: On Mon, Jan 17, 2022 at 07:07:24AM -0800, Angus Ainslie wrote: Initial commit of Librem5 devicetree files Signed-off-by: Angus Ainslie Please note what kernel release the not -u-boot.dtsi files are a copy from, as they need to be copies and not modified, thanks. There's an issue with adding the devicetree from the 5.16 kernel. I get a compilation error due to a :missing .h in the devicetree files: In file included from arch/arm/dts/imx8mq-librem5-r3.dtsi:11, from arch/arm/dts/.imx8mq-librem5.dtb.pre.tmp:6: arch/arm/dts/imx8mq-librem5.dtsi:13:10: fatal error: dt-bindings/rfkill/rfkill.h: No such file or directory 13 | #include "dt-bindings/rfkill/rfkill.h" | ^ Should that get added to the u-boot source as well or should I modify the dts to remove this ? For the kernel we also have 4 different dts files for the differences in PCB versions. For u-boot we don't need the differentiation as it deals with things like camera rotation and prox sensor sensitivity. There's 2 ways to solve the this I think. 1) just use the latest librem5 dts file which is made up of 3 different dts(i) files. 2) have a defconfig for each of the different PCB versions. Do you have a preference ? Thanks Angus
Re: [PATCH 00/13] Add support for the Purism Librem5 Phone
On Mon, Jan 17, 2022 at 09:15:12AM -0800, Angus Ainslie wrote: > On 2022-01-17 09:14, Angus Ainslie wrote: > > Hi Toni > > > > Sorry Tom, somehow concatenated your 2 names. No worries. -- Tom signature.asc Description: PGP signature
Re: [PATCH 00/13] Add support for the Purism Librem5 Phone
On Mon, Jan 17, 2022 at 09:14:05AM -0800, Angus Ainslie wrote: > Hi Toni > > On 2022-01-17 08:59, Tom Rini wrote: > > On Mon, Jan 17, 2022 at 07:07:22AM -0800, Angus Ainslie wrote: > > > > > I sent this patchset as a single monolithic patch and did not see any > > > comment on it. > > > > > > https://lists.denx.de/pipermail/u-boot/2022-January/471087.html > > > > > > Here it is as a set of patches instead. > > > > > > This is all of the code required to boot the Librem5 Phone. > > > > > > It can boot the phone in uuu mode or directly from the eMMC > > > > Yes, sorry, we're a little behind on imx-related patches right now. In > > general yes, splitting this up a bit helps, but it's too split now. > > I'll reply with some specific questions / comments, but the way it was > > before is better really. > > Thanks for the review and I'll start making changes for v2. > > About how it should be split up. Should all of the "board/purism/librem5" > and config files be in one patch with the devicetree and documentation in > separate patches ? Since you've already split out driver/etc changes to other patches, one patch with board/ and include/configs/ and configs/ and dts files is fine. -- Tom signature.asc Description: PGP signature
Re: imx8mm-evk does not boot kernel 5.16
Hi Tim, On Mon, Jan 17, 2022 at 2:09 PM Tim Harvey wrote: > Interesting. Can you give us a breakdown of pros and cons of using > mainline TF-A vs NXP's? I'm not clear if NXP has been actively pushing > their changes up or not and haven't had time to follow the commits for > either project. I am not following TF-A i.MX development in upstream, so I cannot comment myself. Added Jacky on Cc, who is involved with i.MX TF-A development and could probably explain.
Re: [PATCH 00/13] Add support for the Purism Librem5 Phone
On 2022-01-17 09:14, Angus Ainslie wrote: Hi Toni Sorry Tom, somehow concatenated your 2 names.
