Re: [PATCH 3/3] imx: power-domain: Get rid of SMCCC dependency
On 4/17/22 03:01, Adam Ford wrote: Hi, After the patch: U-Boot SPL 2022.04-00822-gc2a24a7ce5 (Apr 16 2022 - 15:45:29 -0500) PMIC: PFUZE100 ID=0x10 SEC0: RNG instantiated Normal Boot Trying to boot from MMC2 There should be some sort of output from ATF here, which version did you use during your tests ? I used the version from the imx8mq_evk.rst: Note: srctree is U-Boot source directory Get ATF from: https://source.codeaurora.org/external/imx/imx-atf branch: imx_5.4.47_2.2.0 This works with U-Boot master. I realize it has the ATF power domain code, but with the SMCC stuff removed, it should be irrelevant. Did you set IMX_BOOT_UART_BASE correctly ? Did you set ATF_LOAD_ADDR correctly ? If I didn't build it right, I don't think 'master' would have booted, but it did. I think I built it correctly. I find it odd that there is no print from the ATF, do check these two variables, I have seen hangs in ATF like this when they were not set right. Do you get a hang when you revert only this specific patch ? When I reverted the series, it booted again, but I can do a bisect tomorrow to narrow down the specific patch in the series that causes the issue. Please do, thanks.
Re: [PATCH 3/3] imx: power-domain: Get rid of SMCCC dependency
On Sat, Apr 16, 2022 at 7:35 PM Marek Vasut wrote: > > On 4/16/22 22:49, Adam Ford wrote: > > On Thu, Apr 7, 2022 at 5:21 PM Tim Harvey wrote: > >> > >> On Wed, Mar 30, 2022 at 8:04 PM Marek Vasut wrote: > >>> > >>> This driver is the only SMCCC dependency in iMX8M U-Boot port. Rework > >>> the driver based on Linux GPCv2 driver to directly control the GPCv2 > >>> block instead of using SMCCC calls. This way, U-Boot can operate the > >>> i.MX8M power domains without depending on anything else. > >>> > >>> This is losely based on Linux GPCv2 driver. The GPU, VPU, MIPI power > >>> domains are not supported to save space, since they are not useful in > >>> the bootloader. The only domains kept are ones for HSIO, PCIe, USB. > >>> > >>> Signed-off-by: Marek Vasut > >>> Cc: Fabio Estevam > >>> Cc: Peng Fan > >>> Cc: Stefano Babic > >>> --- > >>> NOTE: So far this is tested on MX8MM and MX8MN. MX8MQ is not tested. > > > > Sorry for the delay, I tested positive for Covid and needed to recover a > > bit. > > > > I have confirmed this makes the 8MQ hang during boot. > > > > Before patch series: > > > > U-Boot SPL 2022.04-00812-g9859465bfe (Apr 16 2022 - 15:41:46 -0500) > > PMIC: PFUZE100 ID=0x10 > > SEC0: RNG instantiated > > Normal Boot > > Trying to boot from MMC2 > > > > > > U-Boot 2022.04-00812-g9859465bfe (Apr 16 2022 - 15:41:46 -0500) > > > > CPU: Freescale i.MX8MQ rev2.1 at 1000 MHz > > Reset cause: POR > > Model: NXP i.MX8MQ EVK > > DRAM: 3 GiB > > Core: 59 devices, 16 uclasses, devicetree: separate > > MMC: FSL_SDHC: 0, FSL_SDHC: 1 > > Loading Environment from MMC... *** Warning - bad CRC, using default > > environment > > > > In:serial > > Out: serial > > Err: serial > > SEC0: RNG instantiated > > Net: eth0: ethernet@30be > > Hit any key to stop autoboot: 0 > > u-boot=> > > > > After the patch: > > > > U-Boot SPL 2022.04-00822-gc2a24a7ce5 (Apr 16 2022 - 15:45:29 -0500) > > PMIC: PFUZE100 ID=0x10 > > SEC0: RNG instantiated > > Normal Boot > > Trying to boot from MMC2 > > There should be some sort of output from ATF here, which version did you > use during your tests ? I used the version from the imx8mq_evk.rst: Note: srctree is U-Boot source directory Get ATF from: https://source.codeaurora.org/external/imx/imx-atf branch: imx_5.4.47_2.2.0 This works with U-Boot master. I realize it has the ATF power domain code, but with the SMCC stuff removed, it should be irrelevant. > > Did you set IMX_BOOT_UART_BASE correctly ? > > Did you set ATF_LOAD_ADDR correctly ? > If I didn't build it right, I don't think 'master' would have booted, but it did. I think I built it correctly. > Do you get a hang when you revert only this specific patch ? When I reverted the series, it booted again, but I can do a bisect tomorrow to narrow down the specific patch in the series that causes the issue. adam > > The GPC is only used for USB and PCI on the MX8MQ, so you shouldn't be > getting hang so early as to get no output at all. > > > > > > > I can test it on 8MN and 8MM, but it sounds like that's already been done. > > [...]
Re: [PATCH 3/3] imx: power-domain: Get rid of SMCCC dependency
On 4/16/22 22:49, Adam Ford wrote: On Thu, Apr 7, 2022 at 5:21 PM Tim Harvey wrote: On Wed, Mar 30, 2022 at 8:04 PM Marek Vasut wrote: This driver is the only SMCCC dependency in iMX8M U-Boot port. Rework the driver based on Linux GPCv2 driver to directly control the GPCv2 block instead of using SMCCC calls. This way, U-Boot can operate the i.MX8M power domains without depending on anything else. This is losely based on Linux GPCv2 driver. The GPU, VPU, MIPI power domains are not supported to save space, since they are not useful in the bootloader. The only domains kept are ones for HSIO, PCIe, USB. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic --- NOTE: So far this is tested on MX8MM and MX8MN. MX8MQ is not tested. Sorry for the delay, I tested positive for Covid and needed to recover a bit. I have confirmed this makes the 8MQ hang during boot. Before patch series: U-Boot SPL 2022.04-00812-g9859465bfe (Apr 16 2022 - 15:41:46 -0500) PMIC: PFUZE100 ID=0x10 SEC0: RNG instantiated Normal Boot Trying to boot from MMC2 U-Boot 2022.04-00812-g9859465bfe (Apr 16 2022 - 15:41:46 -0500) CPU: Freescale i.MX8MQ rev2.1 at 1000 MHz Reset cause: POR Model: NXP i.MX8MQ EVK DRAM: 3 GiB Core: 59 devices, 16 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial SEC0: RNG instantiated Net: eth0: ethernet@30be Hit any key to stop autoboot: 0 u-boot=> After the patch: U-Boot SPL 2022.04-00822-gc2a24a7ce5 (Apr 16 2022 - 15:45:29 -0500) PMIC: PFUZE100 ID=0x10 SEC0: RNG instantiated Normal Boot Trying to boot from MMC2 There should be some sort of output from ATF here, which version did you use during your tests ? Did you set IMX_BOOT_UART_BASE correctly ? Did you set ATF_LOAD_ADDR correctly ? Do you get a hang when you revert only this specific patch ? The GPC is only used for USB and PCI on the MX8MQ, so you shouldn't be getting hang so early as to get no output at all. I can test it on 8MN and 8MM, but it sounds like that's already been done. [...]
[PATCH] Fix spelling of "followed" in kwboot.1
Signed-off-by: Vagrant Cascadian --- doc/kwboot.1 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/kwboot.1 b/doc/kwboot.1 index f555ff26a2..d663bf1f77 100644 --- a/doc/kwboot.1 +++ b/doc/kwboot.1 @@ -74,7 +74,7 @@ BootROM's standard input and BootROM's terminal echo are active and working fine. To workaround this BootROM bug with standard output, it is possible to manually overwrite BootROM variables stored in SRAM which BootROM use for checking if standard output is enabled or not. To enable BootROM -standard output on UART, type this command folled by ENTER key: +standard output on UART, type this command followed by ENTER key: .RS 1.2i .TP -- 2.35.1
[PATCH v3] Allow colon in PXE bootfile URLs
- U-boot's PXE flow supports prefixing your bootfile name with an
IP address to fetch from a server other than the DHCP server,
e.g. `hostIPaddr:bootfilename`:
https://github.com/u-boot/u-boot/commit/a93907c43f847f076dd0e34ee3b69b5e8e6d0d29
- However, this breaks bootfile paths which contain a colon, e.g.
`f0:ad:4e:10:1b:87/7/pxelinux.cfg/default`
- This patch checks whether the `hostIPaddr` prefix is a valid
IP address before overriding the serverIP otherwise the whole
bootfile path is preserved
Signed-off-by: Lyle Franklin
---
net/net.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/net/net.c b/net/net.c
index 072a82d8f9..034a5d6e67 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1538,14 +1538,19 @@ int is_serverip_in_cmd(void)
int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len)
{
char *colon;
+ struct in_addr ip;
+ ip.s_addr = 0;
if (net_boot_file_name[0] == '\0')
return 0;
colon = strchr(net_boot_file_name, ':');
if (colon) {
- if (ipaddr)
- *ipaddr = string_to_ip(net_boot_file_name);
+ ip = string_to_ip(net_boot_file_name);
+ if (ipaddr && ip.s_addr)
+ *ipaddr = ip;
+ }
+ if (ip.s_addr) {
strncpy(filename, colon + 1, max_len);
} else {
strncpy(filename, net_boot_file_name, max_len);
--
2.35.3
Re: [PATCH 3/3] imx: power-domain: Get rid of SMCCC dependency
On Thu, Apr 7, 2022 at 5:21 PM Tim Harvey wrote: > > On Wed, Mar 30, 2022 at 8:04 PM Marek Vasut wrote: > > > > This driver is the only SMCCC dependency in iMX8M U-Boot port. Rework > > the driver based on Linux GPCv2 driver to directly control the GPCv2 > > block instead of using SMCCC calls. This way, U-Boot can operate the > > i.MX8M power domains without depending on anything else. > > > > This is losely based on Linux GPCv2 driver. The GPU, VPU, MIPI power > > domains are not supported to save space, since they are not useful in > > the bootloader. The only domains kept are ones for HSIO, PCIe, USB. > > > > Signed-off-by: Marek Vasut > > Cc: Fabio Estevam > > Cc: Peng Fan > > Cc: Stefano Babic > > --- > > NOTE: So far this is tested on MX8MM and MX8MN. MX8MQ is not tested. Sorry for the delay, I tested positive for Covid and needed to recover a bit. I have confirmed this makes the 8MQ hang during boot. Before patch series: U-Boot SPL 2022.04-00812-g9859465bfe (Apr 16 2022 - 15:41:46 -0500) PMIC: PFUZE100 ID=0x10 SEC0: RNG instantiated Normal Boot Trying to boot from MMC2 U-Boot 2022.04-00812-g9859465bfe (Apr 16 2022 - 15:41:46 -0500) CPU: Freescale i.MX8MQ rev2.1 at 1000 MHz Reset cause: POR Model: NXP i.MX8MQ EVK DRAM: 3 GiB Core: 59 devices, 16 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial SEC0: RNG instantiated Net: eth0: ethernet@30be Hit any key to stop autoboot: 0 u-boot=> After the patch: U-Boot SPL 2022.04-00822-gc2a24a7ce5 (Apr 16 2022 - 15:45:29 -0500) PMIC: PFUZE100 ID=0x10 SEC0: RNG instantiated Normal Boot Trying to boot from MMC2 I can test it on 8MN and 8MM, but it sounds like that's already been done. adam > > --- > > drivers/power/domain/Kconfig | 1 + > > drivers/power/domain/imx8m-power-domain.c | 379 -- > > 2 files changed, 361 insertions(+), 19 deletions(-) > > > > diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig > > index 93d2599d83c..04fc0054323 100644 > > --- a/drivers/power/domain/Kconfig > > +++ b/drivers/power/domain/Kconfig > > @@ -35,6 +35,7 @@ config IMX8_POWER_DOMAIN > > config IMX8M_POWER_DOMAIN > > bool "Enable i.MX8M power domain driver" > > depends on POWER_DOMAIN && ARCH_IMX8M > > + select CLK > > help > > Enable support for manipulating NXP i.MX8M on-SoC power domains > > via > > requests to the ATF. > > diff --git a/drivers/power/domain/imx8m-power-domain.c > > b/drivers/power/domain/imx8m-power-domain.c > > index c32dbcc31ae..e2e41cf5fee 100644 > > --- a/drivers/power/domain/imx8m-power-domain.c > > +++ b/drivers/power/domain/imx8m-power-domain.c > > @@ -4,6 +4,7 @@ > > */ > > > > #include > > +#include > > #include > > #include > > #include > > @@ -12,52 +13,361 @@ > > #include > > #include > > #include > > +#include > > #include > > -#include > > +#include > > +#include > > + > > +#include > > +#include > > +#include > > > > DECLARE_GLOBAL_DATA_PTR; > > > > +#define GPC_PGC_CPU_MAPPING0x0ec > > + > > +#define IMX8M_PCIE2_A53_DOMAIN BIT(15) > > +#define IMX8M_OTG2_A53_DOMAIN BIT(5) > > +#define IMX8M_OTG1_A53_DOMAIN BIT(4) > > +#define IMX8M_PCIE1_A53_DOMAIN BIT(3) > > + > > +#define IMX8MM_OTG2_A53_DOMAIN BIT(5) > > +#define IMX8MM_OTG1_A53_DOMAIN BIT(4) > > +#define IMX8MM_PCIE_A53_DOMAIN BIT(3) > > + > > +#define IMX8MN_OTG1_A53_DOMAIN BIT(4) > > +#define IMX8MN_MIPI_A53_DOMAIN BIT(2) > > + > > +#define GPC_PU_PGC_SW_PUP_REQ 0x0f8 > > +#define GPC_PU_PGC_SW_PDN_REQ 0x104 > > + > > +#define IMX8M_PCIE2_SW_Pxx_REQ BIT(13) > > +#define IMX8M_OTG2_SW_Pxx_REQ BIT(3) > > +#define IMX8M_OTG1_SW_Pxx_REQ BIT(2) > > +#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1) > > + > > +#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3) > > +#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2) > > +#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1) > > + > > +#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2) > > +#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0) > > + > > +#define GPC_M4_PU_PDN_FLG 0x1bc > > + > > +#define GPC_PU_PWRHSK 0x1fc > > + > > +#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24)) > > +#define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6)) > > + > > +#define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23) > > +#define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5) > > + > > +/* > > + * The PGC offset values in Reference Manual > > + * (Rev. 1, 01/2018 and the older ones) GPC chapter's > > + * GPC_PGC memory
[PATCH v2] soc: xilinx: versal: fix out of bounds array access
The call to xilinx_pm_request requires an array of a larger size.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/soc/soc_xilinx_versal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c
index f8bcd9ab40..3d8c25c19b 100644
--- a/drivers/soc/soc_xilinx_versal.c
+++ b/drivers/soc/soc_xilinx_versal.c
@@ -45,7 +45,7 @@ static const struct soc_ops soc_xilinx_versal_ops = {
static int soc_xilinx_versal_probe(struct udevice *dev)
{
struct soc_xilinx_versal_priv *priv = dev_get_priv(dev);
- u32 ret_payload[4];
+ u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
priv->family = versal_family;
--
2.34.1
[PATCH] soc: xilinx: versal: fix out of bounds array access
The call to xilinx_pm_request requires an array of a larger size.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/soc/soc_xilinx_versal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c
index f8bcd9ab40..752a51a4b2 100644
--- a/drivers/soc/soc_xilinx_versal.c
+++ b/drivers/soc/soc_xilinx_versal.c
@@ -45,7 +45,7 @@ static const struct soc_ops soc_xilinx_versal_ops = {
static int soc_xilinx_versal_probe(struct udevice *dev)
{
struct soc_xilinx_versal_priv *priv = dev_get_priv(dev);
- u32 ret_payload[4];
+ u32 ret_payload[5];
int ret;
priv->family = versal_family;
--
2.34.1
Re: binman and faked blobs failures
On 12/04/2022 00:28, Tom Rini wrote: > [...] > > Note that nothing changed for the board but on the second build now the > faked blob is unhappy and causes a failure message that I don't see the > first time, and probably shouldn't see this time either? This is a > problem for me in that it's on most x86 boards and so makes it easier to > miss other real build failures in my testing. Yeah, the root cause here is that fake files created in the first build are interpreted as actual files in subsequent builds. Simon already added a TODO in binman.rst for cleaning them up, I intend to give it a try but didn't have the time to experiment.
[PATCH v11 14/16] doc: rockchip: restyle rockchip.rst
With more text coming to the rockchip.rst document, give it a restyle first. Changed: sort build examples alphabetically add git clone example fix bash examples fix phrases (grammer) fix typos Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- Changed V11: add # to bash example --- doc/board/rockchip/rockchip.rst | 140 1 file changed, 89 insertions(+), 51 deletions(-) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index a75e60b9fa..1a4de7ff1e 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -13,7 +13,7 @@ and it's usage steps. Rockchip boards --- -Rockchip is SoC solutions provider for tablets & PCs, streaming media +Rockchip is a SoC solutions provider for tablets & PCs, streaming media TV boxes, AI audio & vision, IoT hardware. A wide range of Rockchip SoCs with associated boards are supported in @@ -85,42 +85,58 @@ Building TF-A -TF-A would require to build for ARM64 Rockchip SoCs platforms. +TF-A is required when building ARM64 Rockchip SoCs images. -To build TF-A:: +To build TF-A: -git clone https://github.com/ARM-software/arm-trusted-firmware.git +.. code-block:: bash + +git clone --depth 1 https://github.com/ARM-software/arm-trusted-firmware.git cd arm-trusted-firmware make realclean make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 +cd .. Specify the PLAT= with desired Rockchip platform to build TF-A for. U-Boot ^^ -To build rk3328 boards:: +.. code-block:: bash -export BL31=/path/to/arm-trusted-firmware/to/bl31.elf -make evb-rk3328_defconfig -make +git clone --depth 1 https://source.denx.de/u-boot/u-boot.git +cd u-boot + +To build rk3288 boards: -To build rk3288 boards:: +.. code-block:: bash make evb-rk3288_defconfig -make +make CROSS_COMPILE=arm-linux-gnueabihf- + +To build rk3328 boards: + +.. code-block:: bash + +export BL31=../arm-trusted-firmware/build/rk3328/release/bl31/bl31.elf +make evb-rk3328_defconfig +make CROSS_COMPILE=aarch64-linux-gnu- + +To build rk3368 boards: -To build rk3368 boards:: +.. code-block:: bash -export BL31=/path/to/arm-trusted-firmware/to/bl31.elf +export BL31=../arm-trusted-firmware/build/rk3368/release/bl31/bl31.elf make evb-px5_defconfig -make +make CROSS_COMPILE=aarch64-linux-gnu- + +To build rk3399 boards: -To build rk3399 boards:: +.. code-block:: bash -export BL31=/path/to/arm-trusted-firmware/to/bl31.elf +export BL31=../arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf make evb-rk3399_defconfig -make +make CROSS_COMPILE=aarch64-linux-gnu- Flashing @@ -131,10 +147,12 @@ Flashing SD Card ^^^ -All Rockchip platforms, except rk3128 (which doesn't use SPL) are now -supporting single boot image using binman and pad_cat. +All Rockchip platforms (except rk3128 which doesn't use SPL) are now +supporting a single boot image using binman and pad_cat. -To write an image that boots from an SD card (assumed to be /dev/sda):: +To write an image that boots from a SD card (assumed to be /dev/sda): + +.. code-block:: bash sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64 sync @@ -144,45 +162,60 @@ eMMC eMMC flash would probe on mmc0 in most of the Rockchip platforms. -Create GPT partition layout as defined in configurations:: +Create GPT partition layout as defined in $partitions: + +.. code-block:: bash mmc dev 0 gpt write mmc 0 $partitions -Connect the USB-OTG cable between host and target device. +Connect the USB-OTG cable between the host and a target device. + +Launch fastboot on the target with: -Launch fastboot at target:: +.. code-block:: bash fastboot 0 -Upon successful gadget connection,host show the USB device like:: +Upon a successful gadget connection the host shows the USB device with: + +.. code-block:: bash lsusb -Bus 001 Device 020: ID 2207:330c Fuzhou Rockchip Electronics Company RK3399 in Mask ROM mode +# Bus 001 Device 020: ID 2207:330c Fuzhou Rockchip Electronics Company RK3399 in Mask ROM mode + +Program the flash with: -Program the flash:: +.. code-block:: bash sudo fastboot -i 0x2207 flash loader1 idbloader.img sudo fastboot -i 0x2207 flash loader2 u-boot.itb -Note: for Rockchip 32-bit platforms the U-Boot proper image +Note: + +For Rockchip 32-bit platforms the U-Boot proper image is u-boot-dtb.img SPI ^^^ -Generating idbloader for SPI boot would require to input a multi image -image format to mkimage tool instead of concerting (like for MMC boot). +The SPI boot method requires the generation of idbloader.img with help of the mkimage tool. + +SPL-alone SPI boot image: -SPL-alone SPI boot image::
[PATCH v11 03/16] rockchip: rk3066: add clock driver for rk3066 soc
From: Paweł Jarosz
Add the clock driver for the rk3066 platform.
Derived from the rk3288 and rk3188 driver it
supports only a bare minimum to bring up the system
to reduce the TPL size for:
SDRAM clock configuration.
The boot devices NAND, EMMC, SDMMC, SPI.
A UART for the debug messages (fixed) at 115200n8.
A SARADC for the recovery button.
A TIMER for the delays (fixed).
There's support for two possible frequencies,
the safe 600MHz which will work with default pmic settings and
will be set to get away from the 24MHz default and
the maximum of 1.416Ghz, which boards can set if they
were able to get pmic support for it.
After the clock tree is set during the TPL probe
there's no parent update support.
In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c
obtain the (fixed) clk_get_rate from the clock driver
instead of platdata.
The rk3066 cru node has a number of assigned-clocks properties
that call the .set_rate() function. Add them to the list so that
they return a 0 instead of -ENOENT.
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
Reviewed-by: Sean Anderson
Reviewed-by: Kever Yang
---
Changed V9:
fix TAB
fix space
Changed V8:
add SCLK_TIMER[0..2]
add SCLK_UART[0..3]
fix assigned-clocks
use GENMASK, __bf_shf and REG defines
fix clk defines
add includes
fix bit position CRU_CLKSEL0_CON rk3066 vs rk3188
fix comments
rename PLL_MODE defines
use dev_bind
use dev_dbg
use a different variable name
Changed V7:
changed function prefix
changed #if where possible
restyle U_BOOT_DRIVER structure
---
.../include/asm/arch-rockchip/cru_rk3066.h| 157
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3066.c | 717 ++
3 files changed, 875 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
create mode 100644 drivers/clk/rockchip/clk_rk3066.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
new file mode 100644
index 00..76a715a8e6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Paweł Jarosz
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3066_H
+#define _ASM_ARCH_CRU_RK3066_H
+
+#include
+#include
+
+#define REG(name, h, l) \
+ name##_MASK = GENMASK(h, l), \
+ name##_SHIFT = __bf_shf(name##_MASK)
+
+#define OSC_HZ (24 * 1000 * 1000)
+
+#define APLL_HZ(1416 * 100)
+#define APLL_SAFE_HZ (600 * 100)
+#define GPLL_HZ(594 * 100)
+#define CPLL_HZ(384 * 100)
+
+/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
+#define CPU_ACLK_HZ29700
+#define CPU_HCLK_HZ14850
+#define CPU_PCLK_HZ7425
+#define CPU_H2P_HZ 7425
+
+#define PERI_ACLK_HZ 14850
+#define PERI_HCLK_HZ 14850
+#define PERI_PCLK_HZ 7425
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3066_clk_priv {
+ struct rk3066_grf *grf;
+ struct rk3066_cru *cru;
+ ulong rate;
+ bool has_bwadj;
+};
+
+struct rk3066_cru {
+ struct rk3066_pll {
+ u32 con0;
+ u32 con1;
+ u32 con2;
+ u32 con3;
+ } pll[4];
+ u32 cru_mode_con;
+ u32 cru_clksel_con[35];
+ u32 cru_clkgate_con[10];
+ u32 reserved1[2];
+ u32 cru_glb_srst_fst_value;
+ u32 cru_glb_srst_snd_value;
+ u32 reserved2[2];
+ u32 cru_softrst_con[9];
+ u32 cru_misc_con;
+ u32 reserved3[2];
+ u32 cru_glb_cnt_th;
+};
+
+check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
+
+/* CRU_CLKSEL0_CON */
+enum {
+ REG(CPU_ACLK_PLL, 8, 8),
+ CPU_ACLK_PLL_SELECT_APLL= 0,
+ CPU_ACLK_PLL_SELECT_GPLL,
+
+ REG(CORE_PERI_DIV, 7, 6),
+
+ REG(A9_CORE_DIV, 4, 0),
+};
+
+/* CRU_CLKSEL1_CON */
+enum {
+ REG(AHB2APB_DIV, 15, 14),
+
+ REG(CPU_PCLK_DIV, 13, 12),
+
+ REG(CPU_HCLK_DIV, 9, 8),
+
+ REG(CPU_ACLK_DIV, 2, 0),
+};
+
+/* CRU_CLKSEL10_CON */
+enum {
+ REG(PERI_SEL_PLL, 15, 15),
+ PERI_SEL_CPLL = 0,
+ PERI_SEL_GPLL,
+
+ REG(PERI_PCLK_DIV, 13, 12),
+
+ REG(PERI_HCLK_DIV, 9, 8),
+
+ REG(PERI_ACLK_DIV, 4, 0),
+};
+
+/* CRU_CLKSEL11_CON */
+enum {
+ REG(MMC0_DIV, 5, 0),
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+ REG(UART_PLL, 15, 15),
+ UART_PLL_SELECT_GENERAL = 0,
+ UART_PLL_SELECT_CODEC,
+
+ REG(EMMC_DIV, 13, 8),
+
+ REG(SDIO_DIV, 5, 0),
+};
+
+/* CRU_CLKSEL24_CON */
+enum {
+ REG(SARADC_DIV, 15, 8),
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+ REG(SPI1_DIV, 14, 8),
+
+ REG(SPI0_DIV, 6, 0),
+};
+
+/* CRU_CLKSEL34_CON */
+enum {
+ REG(TSADC_DIV, 15, 0),
+};
+
+/* CRU_MODE_CON */
+enum {
+ REG(GPLL_MODE, 13, 12),
+
+
[PATCH v11 15/16] doc: rockchip: add px30/rk3326 boards and examples
There are several PX30/RK3326 boards in use without mentioning in rockchip.rst. Add boards and examples. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- doc/board/rockchip/rockchip.rst | 16 1 file changed, 16 insertions(+) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 1a4de7ff1e..9b94abe25e 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -21,6 +21,12 @@ mainline U-Boot. List of mainline supported Rockchip boards: +* px30 + - Rockchip Evb-PX30 (evb-px30) + - Engicam PX30.Core C.TOUCH 2.0 (px30-core-ctouch2-px30) + - Engicam PX30.Core C.TOUCH 2.0 10.1 (px30-core-ctouch2-of10-px30) + - Engicam PX30.Core EDIMM2.2 Starter Kit (px30-core-edimm2.2-px30) + - Firefly Core-PX30-JD4 (firefly-px30) * rk3036 - Rockchip Evb-RK3036 (evb-rk3036) - Kylin (kylin_rk3036) @@ -46,6 +52,8 @@ List of mainline supported Rockchip boards: * rk3308 - Rockchip Evb-RK3308 (evb-rk3308) - Roc-cc-RK3308 (roc-cc-rk3308) +* rk3326 + - ODROID-GO Advance (odroid-go2) * rk3328 - Rockchip Evb-RK3328 (evb-rk3328) - Pine64 Rock64 (rock64-rk3328) @@ -107,6 +115,14 @@ U-Boot git clone --depth 1 https://source.denx.de/u-boot/u-boot.git cd u-boot +To build px30 boards: + +.. code-block:: bash + +export BL31=../arm-trusted-firmware/build/px30/release/bl31/bl31.elf +make evb-px30_defconfig +make CROSS_COMPILE=aarch64-linux-gnu- + To build rk3288 boards: .. code-block:: bash -- 2.20.1
[PATCH v11 16/16] doc: rockchip: add rk3066 Rikomagic MK808
Add rk3066 Rikomagic MK808 to the list of mainline supported Rockchip boards. Include instructions for creating and programming images to NAND and SD card. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- Changed V11: align code examples Changed V10: add more info --- doc/board/rockchip/rockchip.rst | 108 1 file changed, 108 insertions(+) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9b94abe25e..4ca7b00b1f 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -30,6 +30,8 @@ List of mainline supported Rockchip boards: * rk3036 - Rockchip Evb-RK3036 (evb-rk3036) - Kylin (kylin_rk3036) +* rk3066 + - Rikomagic MK808 (mk808) * rk3128 - Rockchip Evb-RK3128 (evb-rk3128) * rk3188 @@ -123,6 +125,13 @@ To build px30 boards: make evb-px30_defconfig make CROSS_COMPILE=aarch64-linux-gnu- +To build rk3066 boards: + +.. code-block:: bash + +make mk808_defconfig +make CROSS_COMPILE=arm-linux-gnueabihf- + To build rk3288 boards: .. code-block:: bash @@ -281,6 +290,105 @@ Note: 1. rkbin binaries are regularly updated, so it would be recommended to use the latest version. 2. 0x20 is a load address and is an option for some platforms. +3. Package the RK3066 image with U-Boot TPL/SPL on NAND +--- + +Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support. +If all other boot options fail then it enters into a BootROM mode on the USB OTG port. +This method loads TPL/SPL on NAND with U-boot and kernel on SD card. + +SD Card +^^^ + +U-boot expects a GPT partition map and a boot directory structure with files on the SD card. + +.. code-block:: none + +Partition Map for MMC device 0 -- Partition Type: EFI +Part Start LBA End LBA Name +10x00400x1f7f"loader1" +20x40000x5fff"loader2" +30x60000x7fff"trust" +40x80000x0003"boot" +50x00040x00ed7fde"rootfs" + +Make sure boot and esp flag are set for the boot partition. +Loader1 partition is not used by RK3066. + +Boot partition: + +.. code-block:: none + +extlinux + extlinux.conf + +zImage +rk3066a-mk808.dtb + +To write a U-boot image to the SD card (assumed to be /dev/sda): + +.. code-block:: bash + +sudo dd if=u-boot-dtb.img of=/dev/sda seek=16384 +sync + +NAND + + +Bring device in BootROM mode: + +If bricked and no BootROM mode shows up then connect pin 8 and 9 of the NAND flash +with a needle while reconnecting to the USB OTG port to a PC. + +Show connected devices with: + +.. code-block:: bash + +lsusb +# Bus 001 Device 004: ID 2207:300a Fuzhou Rockchip Electronics Company RK3066 in Mask ROM mode + + +Create NAND image: + +Size of SPL and TPL must be aligned to 2kb. + +Program with commands in a bash script ./flash.sh: + +.. code-block:: bash + +#!/bin/sh + +printf "RK30" > tplspl.bin +dd if=u-boot-tpl.bin >> tplspl.bin +truncate -s %2048 tplspl.bin +truncate -s %2048 u-boot-spl.bin +../tools/boot_merger --verbose config-flash.ini +../tools/upgrade_tool ul ./RK30xxLoader_uboot.bin + +config-flash.ini: + +.. code-block:: none + +[CHIP_NAME] +NAME=RK30 +[VERSION] +MAJOR=2 +MINOR=21 +[CODE471_OPTION] +NUM=1 +Path1=30_LPDDR2_300MHz_DD.bin +[CODE472_OPTION] +NUM=1 +Path1=rk30usbplug.bin +[LOADER_OPTION] +NUM=2 +LOADER1=FlashData +LOADER2=FlashBoot +FlashData=tplspl.bin +FlashBoot=u-boot-spl.bin +[OUTPUT] +PATH=RK30xxLoader_uboot.bin + TODO -- 2.20.1
[PATCH v11 13/16] rockchip: rk3066: add mk808_defconfig
This commit adds the default configuration file and relevant description for a MK808 board. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- Changed V11: update from Kconfig Changed V9: enable led gpio disable STIMER Changed V8: use default log level ENV_IS_NOWHERE --- configs/mk808_defconfig | 102 1 file changed, 102 insertions(+) create mode 100644 configs/mk808_defconfig diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig new file mode 100644 index 00..20bca75adf --- /dev/null +++ b/configs/mk808_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y +# CONFIG_SPL_SYS_THUMB_BUILD is not set +# CONFIG_TPL_SYS_THUMB_BUILD is not set +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x60408000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808" +CONFIG_SPL_TEXT_BASE=0x6000 +CONFIG_ROCKCHIP_RK3066=y +# CONFIG_ROCKCHIP_STIMER is not set +CONFIG_TPL_TEXT_BASE=0x10080C04 +CONFIG_TPL_MAX_SIZE=32764 +CONFIG_TPL_STACK=0x1008 +CONFIG_TARGET_MK808=y +CONFIG_SPL_STACK_R_ADDR=0x7000 +CONFIG_DEBUG_UART_BASE=0x20064000 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_SPL_FS_FAT=y +CONFIG_SYS_LOAD_ADDR=0x70800800 +CONFIG_SPL_PAYLOAD="u-boot.bin" +CONFIG_DEBUG_UART=y +CONFIG_SD_BOOT=y +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2 +CONFIG_TPL_NEEDS_SEPARATE_STACK=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_SPL_OF_PLATDATA=y +CONFIG_TPL_OF_PLATDATA=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_TPL_DM=y +# CONFIG_DM_WARN is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +# CONFIG_SIMPLE_BUS is not set +# CONFIG_SPL_SIMPLE_BUS is not set +# CONFIG_TPL_BLK is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_TPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +# CONFIG_SPL_DM_I2C is not set +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=2000 +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_TPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +# CONFIG_TPL_OF_LIBFDT is not set -- 2.20.1
[PATCH v11 12/16] rockchip: rk3066: add Rikomagic MK808 board
MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, HDMI and a micro-SD card slot. It also includes on-board NAND and 1GB of SDRAM. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3066/Kconfig | 9 + board/rikomagic/mk808/Kconfig | 15 +++ board/rikomagic/mk808/MAINTAINERS | 6 ++ board/rikomagic/mk808/Makefile| 3 +++ board/rikomagic/mk808/mk808.c | 3 +++ 5 files changed, 36 insertions(+) create mode 100644 board/rikomagic/mk808/Kconfig create mode 100644 board/rikomagic/mk808/MAINTAINERS create mode 100644 board/rikomagic/mk808/Makefile create mode 100644 board/rikomagic/mk808/mk808.c diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig index 335f49bc55..95d7fc8a29 100644 --- a/arch/arm/mach-rockchip/rk3066/Kconfig +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -1,5 +1,12 @@ if ROCKCHIP_RK3066 +config TARGET_MK808 + bool "MK808" + help + MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, + HDMI and a micro-SD card slot. It also includes on-board NAND + and 1GB of SDRAM. + config ROCKCHIP_BOOT_MODE_REG default 0x20004040 @@ -27,4 +34,6 @@ config TPL_LIBGENERIC_SUPPORT config TPL_SERIAL default y +source "board/rikomagic/mk808/Kconfig" + endif diff --git a/board/rikomagic/mk808/Kconfig b/board/rikomagic/mk808/Kconfig new file mode 100644 index 00..4abad7e750 --- /dev/null +++ b/board/rikomagic/mk808/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MK808 + +config SYS_BOARD + default "mk808" + +config SYS_VENDOR + default "rikomagic" + +config SYS_CONFIG_NAME + default "mk808" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rikomagic/mk808/MAINTAINERS b/board/rikomagic/mk808/MAINTAINERS new file mode 100644 index 00..b3ef6adb91 --- /dev/null +++ b/board/rikomagic/mk808/MAINTAINERS @@ -0,0 +1,6 @@ +MK808 +M: Johan Jonker +S: Maintained +F: board/rikomagic/mk808 +F: configs/mk808_defconfig +F: include/configs/mk808.h diff --git a/board/rikomagic/mk808/Makefile b/board/rikomagic/mk808/Makefile new file mode 100644 index 00..a4d16884df --- /dev/null +++ b/board/rikomagic/mk808/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += mk808.o diff --git a/board/rikomagic/mk808/mk808.c b/board/rikomagic/mk808/mk808.c new file mode 100644 index 00..e0bfc6f331 --- /dev/null +++ b/board/rikomagic/mk808/mk808.c @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include -- 2.20.1
[PATCH v11 11/16] rockchip: rk3066: add core support
Add the core architecture code for the rk3066. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- Changed V11: remove defines --- arch/arm/include/asm/arch-rk3066/boot0.h | 8 +++ arch/arm/include/asm/arch-rk3066/gpio.h | 8 +++ arch/arm/include/asm/arch-rk3066/timer.h | 6 ++ arch/arm/mach-rockchip/Kconfig| 23 arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3066/Kconfig | 30 ++ arch/arm/mach-rockchip/rk3066/Makefile| 5 ++ arch/arm/mach-rockchip/rk3066/clk_rk3066.c| 33 +++ arch/arm/mach-rockchip/rk3066/rk3066.c| 49 + arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 55 +++ include/configs/mk808.h | 9 +++ include/configs/rk3066_common.h | 47 12 files changed, 274 insertions(+) create mode 100644 arch/arm/include/asm/arch-rk3066/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3066/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3066/timer.h create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c create mode 100644 arch/arm/mach-rockchip/rk3066/rk3066.c create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c create mode 100644 include/configs/mk808.h create mode 100644 include/configs/rk3066_common.h diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h new file mode 100644 index 00..28c0fb9a4c --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/gpio.h b/arch/arm/include/asm/arch-rk3066/gpio.h new file mode 100644 index 00..a4a3b3289c --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/timer.h b/arch/arm/include/asm/arch-rk3066/timer.h new file mode 100644 index 00..3bb39428cd --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/timer.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_TIMER_H__ +#define __ASM_ARCH_TIMER_H__ + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 811964973a..18aff5480b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -35,6 +35,28 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3066 + bool "Support Rockchip RK3066" + select CPU_V7A + select SPL_BOARD_INIT if SPL + select SUPPORT_SPL + select SUPPORT_TPL + select SPL + select TPL + select TPL_ROCKCHIP_BACK_TO_BROM + select TPL_ROCKCHIP_EARLYRETURN_TO_BROM + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SERIAL + imply TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SERIAL + help + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9 + including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two + video interfaces, several memory options and video codec support. + Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, + UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A @@ -405,6 +427,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3066/Kconfig" source "arch/arm/mach-rockchip/rk3128/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk322x/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 00aef0ecee..6c1c7b8a10 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o obj-$(CONFIG_ROCKCHIP_PX30) += px30/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig new file mode 100644 index 00..335f49bc55 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -0,0 +1,30 @@ +if ROCKCHIP_RK3066 + +config ROCKCHIP_BOOT_MODE_REG + default 0x20004040 + +config SYS_SOC + default "rk3066" + +config
[PATCH v11 10/16] rockchip: tools: add rk3066 support to rkcommon.c
Add rk3066 support to rkcommon.c
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 29f2676c19..860785f839 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -123,6 +123,7 @@ struct spl_info {
static struct spl_info spl_infos[] = {
{ "px30", "RK33", 0x2800, false, RK_HEADER_V1 },
{ "rk3036", "RK30", 0x1000, false, RK_HEADER_V1 },
+ { "rk3066", "RK30", 0x8000 - 0x800, true, RK_HEADER_V1 },
{ "rk3128", "RK31", 0x1800, false, RK_HEADER_V1 },
{ "rk3188", "RK31", 0x8000 - 0x800, true, RK_HEADER_V1 },
{ "rk322x", "RK32", 0x8000 - 0x1000, false, RK_HEADER_V1 },
--
2.20.1
[PATCH v11 08/16] arm: dts: rockchip: add rk3066a.dtsi
In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. Add rk3066a.dtsi. Move U-boot specific
things in a rk3066a-u-boot.dtsi file.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
Changed V9:
fix include rk3066a-u-boot.dtsi
Changed V8:
update dtsi
---
arch/arm/dts/rk3066a-u-boot.dtsi | 4 +
arch/arm/dts/rk3066a.dtsi| 879 +++
2 files changed, 883 insertions(+)
create mode 100644 arch/arm/dts/rk3066a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3066a.dtsi
diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi
new file mode 100644
index 00..bc6e609d02
--- /dev/null
+++ b/arch/arm/dts/rk3066a-u-boot.dtsi
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rockchip-u-boot.dtsi"
+#include "rk3xxx-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi
new file mode 100644
index 00..c25b9695db
--- /dev/null
+++ b/arch/arm/dts/rk3066a.dtsi
@@ -0,0 +1,879 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner
+ */
+
+#include
+#include
+#include
+#include
+#include "rk3xxx.dtsi"
+
+/ {
+ compatible = "rockchip,rk3066a";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "rockchip,rk3066-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <0x0>;
+ operating-points =
+ /* kHzuV */
+ <1416000 130>,
+ <120 1175000>,
+ <1008000 1125000>,
+ <816000 1125000>,
+ <60 110>,
+ <504000 110>,
+ <312000 1075000>;
+ clock-latency = <4>;
+ clocks = < ARMCLK>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <0x1>;
+ };
+ };
+
+ display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <_out>, <_out>;
+ };
+
+ sram: sram@1008 {
+ compatible = "mmio-sram";
+ reg = <0x1008 0x1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1008 0x1>;
+
+ smp-sram@0 {
+ compatible = "rockchip,rk3066-smp-sram";
+ reg = <0x0 0x50>;
+ };
+ };
+
+ vop0: vop@1010c000 {
+ compatible = "rockchip,rk3066-vop";
+ reg = <0x1010c000 0x19c>;
+ interrupts = ;
+ clocks = < ACLK_LCDC0>,
+< DCLK_LCDC0>,
+< HCLK_LCDC0>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ power-domains = < RK3066_PD_VIO>;
+ resets = < SRST_LCDC0_AXI>,
+< SRST_LCDC0_AHB>,
+< SRST_LCDC0_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "disabled";
+
+ vop0_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop0_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <_in_vop0>;
+ };
+ };
+ };
+
+ vop1: vop@1010e000 {
+ compatible = "rockchip,rk3066-vop";
+ reg = <0x1010e000 0x19c>;
+ interrupts = ;
+ clocks = < ACLK_LCDC1>,
+< DCLK_LCDC1>,
+< HCLK_LCDC1>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ power-domains = < RK3066_PD_VIO>;
+ resets = < SRST_LCDC1_AXI>,
+< SRST_LCDC1_AHB>,
+< SRST_LCDC1_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ status = "disabled";
+
+ vop1_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop1_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <_in_vop1>;
+ };
+ };
+ };
+
+ hdmi: hdmi@10116000 {
+ compatible = "rockchip,rk3066-hdmi";
+ reg =
[PATCH v11 09/16] arm: dts: rockchip: add rk3066a-mk808.dts
MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port,
HDMI and a micro-SD card slot. It also includes on-board NAND
and 1GB of SDRAM. Add rk3066a-mk808.dts. Move U-boot specific
things in a rk3066a-mk808-u-boot.dtsi file.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
Changed V10:
add u-boot,spl-fifo-mode property
Changed V9:
add led config
move dtb-$() in Makefile
Changed V8:
update dts
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/rk3066a-mk808-u-boot.dtsi | 49 ++
arch/arm/dts/rk3066a-mk808.dts | 216 +
3 files changed, 268 insertions(+)
create mode 100644 arch/arm/dts/rk3066a-mk808-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3066a-mk808.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 99dc7bc777..e8657bed09 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -90,6 +90,9 @@ dtb-$(CONFIG_ROCKCHIP_PX30) += \
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
+dtb-$(CONFIG_ROCKCHIP_RK3066) += \
+ rk3066a-mk808.dtb
+
dtb-$(CONFIG_ROCKCHIP_RK3128) += \
rk3128-evb.dtb
diff --git a/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
new file mode 100644
index 00..e0aa929fce
--- /dev/null
+++ b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3066a-u-boot.dtsi"
+
+/ {
+ config {
+ u-boot,boot-led = "mk808:blue:power";
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ compatible = "rockchip,rk3066-dmc", "syscon";
+ rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
+ 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4
+ 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0
+ 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0
+ 0x4 0x0>;
+ rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
+ 0x220 0x40 0x0 0x0>;
+ rockchip,sdram-params = <0x24716310 0 2 3 3 9 0>;
+};
+
+ {
+ fifo-mode;
+ max-frequency = <400>;
+ u-boot,dm-spl;
+ u-boot,spl-fifo-mode;
+};
+
+ {
+ status = "disabled";
+};
+
+ {
+ compatible = "rockchip,rk3066-noc", "syscon";
+};
+
+ {
+ clock-frequency = <2400>;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts
new file mode 100644
index 00..667d57a4ff
--- /dev/null
+++ b/arch/arm/dts/rk3066a-mk808.dts
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Paweł Jarosz
+ */
+
+/dts-v1/;
+#include
+#include "rk3066a.dtsi"
+
+/ {
+ model = "Rikomagic MK808";
+ compatible = "rikomagic,mk808", "rockchip,rk3066a";
+
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@6000 {
+ reg = <0x6000 0x4000>;
+ device_type = "memory";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = < 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <250>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "recovery";
+ linux,code = ;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ blue_led: led-0 {
+ label = "mk808:blue:power";
+ gpios = < RK_PA3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ hdmi_con {
+ compatible = "hdmi-connector";
+ type = "c";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <_out_con>;
+ };
+ };
+ };
+
+ vcc_2v5: vcc-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_2v5";
+ regulator-min-microvolt = <250>;
+ regulator-max-microvolt = <250>;
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ vcc_host: usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <_drv>;
+ pinctrl-names = "default";
+
[PATCH v11 05/16] rockchip: rk3066: add sdram driver
From: Paweł Jarosz
Add rockchip rk3066 sdram driver
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
Changed V7:
restyle
rename TEST_PATTERN
changed function prefix
changed #if where possible
restyle U_BOOT_DRIVER structure
remove rk3066_dmc_of_to_plat because dmc DT data
only used in TPL in combination with OF_PLATDATA
---
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3066.c | 892
2 files changed, 893 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram_rk3066.c
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index ca1c289b88..6d530c29af 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
+obj-$(CONFIG_ROCKCHIP_RK3066) = sdram_rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
diff --git a/drivers/ram/rockchip/sdram_rk3066.c
b/drivers/ram/rockchip/sdram_rk3066.c
new file mode 100644
index 00..832154ee3a
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3066.c
@@ -0,0 +1,892 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * Adapted from the very similar rk3188 ddr init.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct rk3066_dmc_chan_info {
+ struct rk3288_ddr_pctl *pctl;
+ struct rk3288_ddr_publ *publ;
+ struct rk3188_msch *msch;
+};
+
+struct rk3066_dmc_dram_info {
+ struct rk3066_dmc_chan_info chan[1];
+ struct ram_info info;
+ struct clk ddr_clk;
+ struct rk3066_cru *cru;
+ struct rk3066_grf *grf;
+ struct rk3066_sgrf *sgrf;
+ struct rk3188_pmu *pmu;
+};
+
+struct rk3066_dmc_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_rockchip_rk3066_dmc of_plat;
+#endif
+ struct rk3288_sdram_channel ch[2];
+ struct rk3288_sdram_pctl_timing pctl_timing;
+ struct rk3288_sdram_phy_timing phy_timing;
+ struct rk3288_base_params base;
+ int num_channels;
+ struct regmap *map;
+};
+
+const int rk3066_dmc_ddrconf_table[] = {
+ /*
+* [5:4] row(13+n)
+* [1:0] col(9+n), assume bw=2
+* row col,bw
+*/
+ 0,
+ (2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+ (1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+ (0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+ (2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+ (1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+ (0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+ (1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+ (0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+};
+
+#define TEST_PATTERN 0x5aa5f00f
+#define DQS_GATE_TRAINING_ERROR_RANK0 BIT(4)
+#define DQS_GATE_TRAINING_ERROR_RANK1 BIT(5)
+
+static void rk3066_dmc_copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++) {
+ writel(*src, dest);
+ src++;
+ dest++;
+ }
+}
+
+static void rk3066_dmc_ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32
phy)
+{
+ u32 phy_ctl_srstn_shift = 13;
+ u32 ctl_psrstn_shift = 11;
+ u32 ctl_srstn_shift = 10;
+ u32 phy_psrstn_shift = 9;
+ u32 phy_srstn_shift = 8;
+
+ rk_clrsetreg(>cru_softrst_con[5],
+1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
+1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
+1 << phy_srstn_shift,
+phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
+ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
+phy << phy_srstn_shift);
+}
+
+static void rk3066_dmc_ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n)
+{
+ u32 phy_ctl_srstn_shift = 13;
+
+ rk_clrsetreg(>cru_softrst_con[5],
+1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
+}
+
+static void rk3066_dmc_phy_pctrl_reset(struct rk3066_cru *cru,
+ struct rk3288_ddr_publ *publ,
+ int channel)
+{
+ int i;
+
+ rk3066_dmc_ddr_reset(cru, channel, 1, 1);
+ udelay(1);
+ clrbits_le32(>acdllcr, ACDLLCR_DLLSRST);
+ for (i = 0; i < 4; i++)
+ clrbits_le32(>datx8[i].dxdllcr,
[PATCH v11 07/16] arm: dts: rockchip: fix include rk3xxx-u-boot.dtsi
Move the include for rk3xxx-u-boot.dtsi to rk3188-u-boot.dtsi
to stay in line with U-boot dtsi files.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
arch/arm/dts/rk3188-u-boot.dtsi | 1 +
arch/arm/dts/rk3188.dtsi| 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi
index 43f05b9876..735776c16b 100644
--- a/arch/arm/dts/rk3188-u-boot.dtsi
+++ b/arch/arm/dts/rk3188-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include "rockchip-u-boot.dtsi"
+#include "rk3xxx-u-boot.dtsi"
_timer {
status = "okay";
diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi
index 6c1c2ff533..6764776cce 100644
--- a/arch/arm/dts/rk3188.dtsi
+++ b/arch/arm/dts/rk3188.dtsi
@@ -9,7 +9,6 @@
#include
#include
#include "rk3xxx.dtsi"
-#include "rk3xxx-u-boot.dtsi"
/ {
compatible = "rockchip,rk3188";
--
2.20.1
[PATCH v11 06/16] arm: dts: rockchip: fix rk3xxx-u-boot.dtsi
The file rk3xxx-u-boot.dtsi was original only for rk3188 and SPL.
With rk3066 added some nodes are also needed in TPL,
so change them to u-boot,dm-pre-reloc
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
arch/arm/dts/rk3xxx-u-boot.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi
index 581594c35d..e67432fb39 100644
--- a/arch/arm/dts/rk3xxx-u-boot.dtsi
+++ b/arch/arm/dts/rk3xxx-u-boot.dtsi
@@ -4,7 +4,7 @@
noc: syscon@10128000 {
compatible = "rockchip,rk3188-noc", "syscon";
reg = <0x10128000 0x2000>;
- u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
};
dmc: dmc@2002 {
@@ -18,16 +18,16 @@
rockchip,grf = <>;
rockchip,pmu = <>;
rockchip,noc = <>;
- u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
};
};
{
- u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
};
{
- u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
};
{
--
2.20.1
[PATCH v11 04/16] rockchip: rk3066: add rk3066 pinctrl driver
From: Paweł Jarosz
Add driver supporting pin multiplexing on rk3066 platform.
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
Changed V9:
change regmap source
Changed V7:
restyle
changed function prefix.
restyle U_BOOT_DRIVER structure
use OF_REAL
use EOPNOTSUPP
---
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3066.c | 112 ++
2 files changed, 113 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3066.c
diff --git a/drivers/pinctrl/rockchip/Makefile
b/drivers/pinctrl/rockchip/Makefile
index fcf19f877a..7d03f8101d 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -5,6 +5,7 @@
obj-y += pinctrl-rockchip-core.o
obj-$(CONFIG_ROCKCHIP_PX30) += pinctrl-px30.o
obj-$(CONFIG_ROCKCHIP_RK3036) += pinctrl-rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3066) += pinctrl-rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c
b/drivers/pinctrl/rockchip/pinctrl-rk3066.c
new file mode 100644
index 00..598b63223e
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-rockchip.h"
+
+static int rk3066_pinctrl_set_mux(struct rockchip_pin_bank *bank, int pin, int
mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data;
+
+ regmap = priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, , );
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3066_PULL_OFFSET 0x118
+#define RK3066_PULL_PINS_PER_REG 16
+#define RK3066_PULL_BANK_STRIDE8
+
+static void rk3066_pinctrl_calc_pull_reg_and_bit(struct rockchip_pin_bank
*bank,
+int pin_num, struct regmap
**regmap,
+int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ *reg = RK3066_PULL_OFFSET;
+ *reg += bank->bank_num * RK3066_PULL_BANK_STRIDE;
+ *reg += (pin_num / RK3066_PULL_PINS_PER_REG) * 4;
+
+ *bit = pin_num % RK3066_PULL_PINS_PER_REG;
+};
+
+static int rk3066_pinctrl_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit;
+ u32 data;
+
+ if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
+ pull != PIN_CONFIG_BIAS_DISABLE)
+ return -EOPNOTSUPP;
+
+ rk3066_pinctrl_calc_pull_reg_and_bit(bank, pin_num, , ,
);
+ data = BIT(bit + 16);
+ if (pull == PIN_CONFIG_BIAS_DISABLE)
+ data |= BIT(bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+static struct rockchip_pin_bank rk3066_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+ PIN_BANK(4, 32, "gpio4"),
+ PIN_BANK(6, 16, "gpio6"),
+};
+
+static struct rockchip_pin_ctrl rk3066_pin_ctrl = {
+ .pin_banks = rk3066_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3066_pin_banks),
+ .grf_mux_offset = 0xa8,
+ .set_mux= rk3066_pinctrl_set_mux,
+ .set_pull = rk3066_pinctrl_set_pull,
+};
+
+static const struct udevice_id rk3066_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3066a-pinctrl",
+ .data = (ulong)_pin_ctrl
+ },
+ {}
+};
+
+U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = {
+ .name = "rockchip_rk3066a_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .ops= _pinctrl_ops,
+ .probe = rockchip_pinctrl_probe,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .of_match = rk3066_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+};
--
2.20.1
[PATCH v11 01/16] rockchip: rk3066-power: sync power domain dt-binding header from Linux
In order to update the DT for rk3066 sync the power domain dt-binding header. This is the state as of v5.12 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- include/dt-bindings/power/rk3066-power.h | 22 ++ 1 file changed, 22 insertions(+) create mode 100644 include/dt-bindings/power/rk3066-power.h diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h new file mode 100644 index 00..acf9f310ac --- /dev/null +++ b/include/dt-bindings/power/rk3066-power.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ +#define __DT_BINDINGS_POWER_RK3066_POWER_H__ + +/* VD_CORE */ +#define RK3066_PD_A9_0 0 +#define RK3066_PD_A9_1 1 +#define RK3066_PD_DBG 4 +#define RK3066_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3066_PD_VIDEO6 +#define RK3066_PD_VIO 7 +#define RK3066_PD_GPU 8 +#define RK3066_PD_PERI 9 +#define RK3066_PD_CPU 10 +#define RK3066_PD_ALIVE11 + +/* VD_PMU */ +#define RK3066_PD_RTC 12 + +#endif -- 2.20.1
[PATCH v11 02/16] rockchip: rk3066: add grf header file
From: Paweł Jarosz
grf is needed by various drivers for rk3066 soc.
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
Changed V9:
fix TAB
Changed V8:
add GRF_GPIO3B_IOMUX for SDMMC0
use GENMASK, __bf_shf and REG defines
add includes
---
.../include/asm/arch-rockchip/grf_rk3066.h| 210 ++
1 file changed, 210 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
new file mode 100644
index 00..d8e0812cee
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Paweł Jarosz
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3066_H
+#define _ASM_ARCH_GRF_RK3066_H
+
+#include
+#include
+
+#define REG(name, h, l) \
+ name##_MASK = GENMASK(h, l), \
+ name##_SHIFT = __bf_shf(name##_MASK)
+
+struct rk3066_grf_gpio_lh {
+ u32 l;
+ u32 h;
+};
+
+struct rk3066_grf {
+ struct rk3066_grf_gpio_lh gpio_dir[7];
+ struct rk3066_grf_gpio_lh gpio_do[7];
+ struct rk3066_grf_gpio_lh gpio_en[7];
+
+ u32 gpio0a_iomux;
+ u32 gpio0b_iomux;
+ u32 gpio0c_iomux;
+ u32 gpio0d_iomux;
+
+ u32 gpio1a_iomux;
+ u32 gpio1b_iomux;
+ u32 gpio1c_iomux;
+ u32 gpio1d_iomux;
+
+ u32 gpio2a_iomux;
+ u32 gpio2b_iomux;
+ u32 gpio2c_iomux;
+ u32 gpio2d_iomux;
+
+ u32 gpio3a_iomux;
+ u32 gpio3b_iomux;
+ u32 gpio3c_iomux;
+ u32 gpio3d_iomux;
+
+ u32 gpio4a_iomux;
+ u32 gpio4b_iomux;
+ u32 gpio4c_iomux;
+ u32 gpio4d_iomux;
+
+ u32 reserved0[5];
+
+ u32 gpio6b_iomux;
+
+ u32 reserved1[2];
+
+ struct rk3066_grf_gpio_lh gpio_pull[7];
+
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+
+ u32 soc_status0;
+
+ u32 dmac1_con[3];
+ u32 dmac2_con[4];
+
+ u32 uoc0_con[3];
+ u32 uoc1_con[4];
+ u32 ddrc_con;
+ u32 ddrc_stat;
+
+ u32 reserved2[10];
+
+ u32 os_reg[4];
+};
+
+check_member(rk3066_grf, os_reg[3], 0x01d4);
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ REG(GPIO1B1, 2, 2),
+ GPIO1B1_GPIO= 0,
+ GPIO1B1_UART2_SOUT,
+
+ REG(GPIO1B0, 0, 0),
+ GPIO1B0_GPIO= 0,
+ GPIO1B0_UART2_SIN
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+ REG(GPIO3B6, 12, 12),
+ GPIO3B6_GPIO= 0,
+ GPIO3B6_SDMMC0_DECTN,
+
+ REG(GPIO3B5, 10, 10),
+ GPIO3B5_GPIO= 0,
+ GPIO3B5_SDMMC0_DATA3,
+
+ REG(GPIO3B4, 8, 8),
+ GPIO3B4_GPIO= 0,
+ GPIO3B4_SDMMC0_DATA2,
+
+ REG(GPIO3B3, 6, 6),
+ GPIO3B3_GPIO= 0,
+ GPIO3B3_SDMMC0_DATA1,
+
+ REG(GPIO3B2, 4, 4),
+ GPIO3B2_GPIO= 0,
+ GPIO3B2_SDMMC0_DATA0,
+
+ REG(GPIO3B1, 2, 2),
+ GPIO3B1_GPIO= 0,
+ GPIO3B1_SDMMC0_CMD,
+
+ REG(GPIO3B0, 0, 0),
+ GPIO3B0_GPIO= 0,
+ GPIO3B0_SDMMC0_CLKOUT,
+};
+
+/* GRF_SOC_CON0 */
+enum {
+ REG(SMC_MUX_CON, 13, 13),
+
+ REG(NOC_REMAP, 12, 12),
+
+ REG(EMMC_FLASH_SEL, 11, 11),
+
+ REG(TZPC_REVISION, 10, 7),
+
+ REG(L2CACHE_ACC, 6, 5),
+
+ REG(L2RD_WAIT, 4, 3),
+
+ REG(IMEMRD_WAIT, 2, 1),
+
+ REG(SOC_REMAP, 0, 0),
+};
+
+/* GRF_SOC_CON1 */
+enum {
+ REG(RKI2C4_SEL, 15, 15),
+
+ REG(RKI2C3_SEL, 14, 14),
+
+ REG(RKI2C2_SEL, 13, 13),
+
+ REG(RKI2C1_SEL, 12, 12),
+
+ REG(RKI2C0_SEL, 11, 11),
+
+ REG(VCODEC_SEL, 10, 10),
+
+ REG(PERI_EMEM_PAUSE, 9, 9),
+
+ REG(PERI_USB_PAUSE, 8, 8),
+
+ REG(SMC_MUX_MODE_0, 6, 6),
+
+ REG(SMC_SRAM_MW_0, 5, 4),
+
+ REG(SMC_REMAP_0, 3, 3),
+
+ REG(SMC_A_GT_M0_SYNC, 2, 2),
+
+ REG(EMAC_SPEED, 1, 1),
+
+ REG(EMAC_MODE, 0, 0),
+};
+
+/* GRF_SOC_CON2 */
+enum {
+ REG(MSCH4_MAINDDR3, 7, 7),
+ MSCH4_MAINDDR3_DDR3 = 1,
+
+ REG(EMAC_NEWRCV_EN, 6, 6),
+
+ REG(SW_ADDR15_EN, 5, 5),
+
+ REG(SW_ADDR16_EN, 4, 4),
+
+ REG(SW_ADDR17_EN, 3, 3),
+
+ REG(BANK2_TO_RANK_EN, 2, 2),
+
+ REG(RANK_TO_ROW15_EN, 1, 1),
+
+ REG(UPCTL_C_ACTIVE_IN, 0, 0),
+ UPCTL_C_ACTIVE_IN_MAY = 0,
+ UPCTL_C_ACTIVE_IN_WILL,
+};
+
+/* GRF_DDRC_CON0 */
+enum {
+ REG(DTO_LB, 12, 11),
+
+ REG(DTO_TE, 10, 9),
+
+ REG(DTO_PDR, 8, 7),
+
+ REG(DTO_PDD, 6, 5),
+
+ REG(DTO_IOM, 4, 3),
+
+ REG(DTO_OE, 2, 1),
+
+ REG(ATO_AE, 0, 0),
+};
+#endif
--
2.20.1
[PATCH v11 00/16] Add Rikomagic MK808 board
MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, HDMI and a micro-SD card slot. It also includes on-board NAND and 1GB of SDRAM. Changed V11: remove defines update defconfig align doc examples Changed V10: add u-boot,spl-fifo-mode property combine patches core support restyle doc rockchip.rst add more px30 doc info add more rk3066 doc info Changed V9: fix TABs and spaces add led config enable led gpio change pinctrl regmap source disable STIMER move include Changed V8: update clock driver update grf header file Changed V7: add board files enable boot from SD card restyle pinctrl driver restyle sdram driver === Boot procedure flow for a Rockchip rk3066 SoC: 1.Read 2K SDRAM initialization image code to internal SRAM 2.Run image code to do SDRAM initialization 3.Transfer boot image code to SDRAM 4.Run boot image code Supported system boot from the following devices: Nand Flash SPI nor Flash eMMC device UART interface If all boot options fail then enter into BootROM mode on the USB OTG port. Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support. The size of a full U-boot binary is too large for the internal SDRAM memory. Of that 64k size only 32kb sram - 2kb bootrom is available for the first stage. Similar to the already supported rk3188, the BootROM will attempt to load up the first stage image in two steps: first 1KB to offset 0x800 in the SRAM and then the remainder to offset 0xc00 in the SRAM. It always enters at offset 0x804 after a 4 ASCII character "RK30" header. With CONFIG_TPL_ROCKCHIP_EARLYRETURN_TO_BROM=y this first stage is combined with the U-boot TPL binary (u-boot-tpl.bin). For rk3066 with NAND flash and U-boot this gives the following stages: - TPL: init external SDRAM - SPL: init SDMMC and read U-boot from SD CARD. - U-boot: read Linux kernel from SD CARD. - Kernel Additionally the rk3066 requires everything the BootROM loads to be RC4-encrypted. === Boot solution with full U-boot stored on SD CARD: Compile commands(U-boot): ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make mk808_defconfig ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make menuconfig ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make all === Size of SPL and TPL must be aligned to 2kb. If bricked and no BootROM mode shows up then connect pin 8 and 9 of the NAND flash with a needle while reconnecting to the USB OTG port to a PC. === Show connected devices with: lsusb Bus 001 Device 004: ID 2207:300a Fuzhou Rockchip Electronics Company RK3066 in Mask ROM mode === Program commands with ./flash.sh: #!/bin/sh printf "RK30" > tplspl.bin dd if=u-boot-tpl.bin >> tplspl.bin truncate -s %2048 tplspl.bin truncate -s %2048 u-boot-spl.bin ../tools/boot_merger --verbose config-flash.ini ../tools/upgrade_tool ul ./RK30xxLoader_uboot.bin === config-flash.ini: [CHIP_NAME] NAME=RK30 [VERSION] MAJOR=2 MINOR=21 [CODE471_OPTION] NUM=1 Path1=30_LPDDR2_300MHz_DD.bin [CODE472_OPTION] NUM=1 Path1=rk30usbplug.bin [LOADER_OPTION] NUM=2 LOADER1=FlashData LOADER2=FlashBoot FlashData=tplspl.bin FlashBoot=u-boot-spl.bin [OUTPUT] PATH=RK30xxLoader_uboot.bin === Partition Map for MMC device 0 -- Partition Type: EFI PartStart LBA End LBA Name 1 0x0040 0x1f7f "loader1" 2 0x4000 0x5fff "loader2" 3 0x6000 0x7fff "trust" 4 0x8000 0x0003 "boot" 5 0x0004 0x00ed7fde "rootfs" Make sure boot and esp flag are set for boot partition. Loader1 partition is not used by RK3066. === Boot partition: extlinux -- extlinux.conf zImage rk3066a-mk808.dtb === extlinux.conf: label kernel kernel /zImage fdt /rk3066a-mk808.dtb append root=LABEL=linuxroot init=/sbin/init rootfstype=ext4 rootwait === Program commands (SD CARD with GPT partition): sudo dd if=u-boot-dtb.img of=/dev/sda seek=16384 === TODO: Better program flow/tools USB NAND etc etc === Johan Jonker (12): rockchip: rk3066-power: sync power domain dt-binding header from Linux arm: dts: rockchip: fix rk3xxx-u-boot.dtsi arm: dts: rockchip: fix include rk3xxx-u-boot.dtsi arm: dts: rockchip: add rk3066a.dtsi arm: dts: rockchip: add rk3066a-mk808.dts rockchip: tools: add rk3066 support to rkcommon.c rockchip: rk3066: add core support rockchip: rk3066: add Rikomagic MK808 board rockchip: rk3066: add mk808_defconfig doc: rockchip: restyle rockchip.rst doc: rockchip: add px30/rk3326 boards and examples doc: rockchip: add rk3066 Rikomagic MK808 Paweł Jarosz (4): rockchip: rk3066: add grf header file rockchip: rk3066: add clock driver for rk3066 soc rockchip: rk3066: add rk3066 pinctrl driver rockchip: rk3066: add sdram driver arch/arm/dts/Makefile | 3 + arch/arm/dts/rk3066a-mk808-u-boot.dtsi| 49 + arch/arm/dts/rk3066a-mk808.dts| 216 + arch/arm/dts/rk3066a-u-boot.dtsi
Re: [PATCH] crypto/fsl: Clear the memory when blob decapsulation fails
On Fri, Apr 15, 2022 at 8:23 AM Gaurav Jain wrote: > > issue: blob decapsulation operation store the decrypted data >in memory even if ICV check failed. > > fix: clear the blob data output memory. > > Fixes: c5de15cbc8 (crypto/fsl: Add command for encapsulating/decapsulating > blobs) > Signed-off-by: Gaurav Jain > Reviewed-by: Kshitiz Varshney > Tested-by: Kshitiz Varshney Reviewed-by: Fabio Estevam
Re: [PATCH] i.MX6SX: crypto/fsl: fix entropy delay value
On Fri, Apr 15, 2022 at 8:11 AM Gaurav Jain wrote:
>
> RNG Hardware error is reported due to incorrect entropy delay
Yes, I observe the RNG hardware error in the kernel too.
> rng self test are run to determine the correct ent_dly.
> test is executed with different voltage and temperature to identify the
> worst case value for ent_dly. after adding a margin value(1000),
> ent_dly should be at least 12000.
>
> Signed-off-by: Gaurav Jain
> ---
> drivers/crypto/fsl/jr.c | 11 ++-
> include/fsl_sec.h | 6 +-
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> index 1d951cf0a6..85a3dac796 100644
> --- a/drivers/crypto/fsl/jr.c
> +++ b/drivers/crypto/fsl/jr.c
> @@ -623,7 +623,7 @@ static void kick_trng(int ent_delay, ccsr_sec_t *sec)
>
> static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> {
> - int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> + int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY;
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)>rng;
> u32 inst_handles;
> @@ -652,6 +652,15 @@ static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> * the RNG.
> */
> ret = instantiate_rng(sec_idx, sec, gen_sk);
> + /*
> +* entropy delay is calculated via self-test method.
> +* self-test are run across different volatge, temp.
s/volatge/voltage
Reviewed-by: Fabio Estevam
Re: [PATCH V2] board: bsh: imx8mn_bsh_smm_s2/s2pro: enable DM_SERIAL
Hi Michael, On Fri, Apr 15, 2022 at 2:23 AM Michael Trimarchi wrote: > > Enable DM_SERIAL for both U_Boot and the SPL. The uart2 and its pinmux > are already marked with u-boot,dm-spl but we need to move the call to > preloader_console_init() after spl_init() to avoid a board hang > as dm can't be used until after spl_init(). > > Remove the manual config of the UART pinmux now that it is no longer > needed. > > Signed-off-by: Michael Trimarchi > Cc: Tim Harvey Reviewed-by: Fabio Estevam
Re: [PATCH v3] imx: add i.MX8MN DDR3L evk board support
Hi Heiko, On Fri, Apr 15, 2022 at 3:36 PM Heiko Thiery wrote: > > Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano > UltraLite Quad SoC and uses 1GB DDR3L memory. > > U-Boot 2022.04-00011-gf0e15e3761 (Apr 06 2022 - 13:54:41 +0200) > > CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz > Reset cause: WDOG > Model: NXP i.MX8MNano DDR3L EVK board > DRAM: 1 GiB > Core: 56 devices, 18 uclasses, devicetree: separate > WDT: Started watchdog@3028 with servicing (60s timeout) > MMC: FSL_SDHC: 1, FSL_SDHC: 2 > Loading Environment from MMC... OK > In:serial@3089 > Out: serial@3089 > Err: serial@3089 > > BuildInfo: > - ATF > > Net: eth0: ethernet@30be > u-boot=> > > Signed-off-by: Heiko Thiery Reviewed-by: Fabio Estevam
Re: [PATCH v3 2/2] board: gateworks: venice: add imx8mp-venice-gw740x support
Hi Tim, On Thu, Apr 14, 2022 at 5:00 PM Tim Harvey wrote: > +/* UART */ > +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR Since you use DM_SERIAL, this can be removed, right? Reviewed-by: Fabio Estevam
Re: [PATCH v3 1/2] board: gateworks: venice: add additional levels for dtb name match
On Thu, Apr 14, 2022 at 5:00 PM Tim Harvey wrote: > > Gateworks produces many products from a single PCB with subloaded > components. Add an additional two levels of dtb name matching so that > for example a GW7400-A matches the dtb name of gw74xx.dtb > > Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam
Re: [PATCH] arm: dts: imx8mp: add of-list support to common imx8mp-u-boot.dtsi
Hi Tim, On Fri, Apr 15, 2022 at 5:41 PM Tim Harvey wrote: > > Add support for OF-LIST to common imx8mp-u-boot.dtsi so that it can > be used with boards that have multiple DTB's. > > Signed-off-by: Tim Harvey > Cc: Fabio Estevam > Cc: NXP i.MX U-Boot Team > Cc: Peng Fan > Cc: Teresa Remmet > Cc: Ying-Chun Liu (PaulLiu) > Cc: Marcel Ziswiler Reviewed-by: Fabio Estevam
Re: [PATCH V4 0/4] imx: imx8m: enable DM SERIAL
Hi Peng, On Fri, Apr 15, 2022 at 12:54 AM Peng Fan (OSS) wrote: > > From: Peng Fan > > V4: > Rebased, update commit log Per Tim's comments > > V3: > Add missed Signed-off-by > Rebased to only add CONFIG_DM_SERIAL, not touch other config change in > defconfig > > V2: > Include imx8mq-evk in this patchset. > For i.MX8MN/M/P, drop board level uart pinmux settings, > move preloader_console_init after driver probe. > > Tested on all four boards. Note i.MX8MQ-EVK not have SPL_DM, so pinmux for > uart still there for spl usage. > > > Peng Fan (4): > imx: imx8mp_evk: enable CONFIG_DM_SERIAL > imx: imx8mm_evk: enable CONFIG_DM_SERIAL > imx: imx8mn_evk: enable CONFIG_DM_SERIAL > imx: imx8mq-evk: enable CONFIG_DM_SERIAL For the series: Reviewed-by: Fabio Estevam
Re: [PATCH v2 06/23] sunxi: Skip non-DM UART pin setup when PINCTRL=y
awm16...@gmail.com 從我的iPhone傳送 VIP
[PATCH] fdt: Fix TPL SEPARATE_BSS check when locating DTB
Commit 690af71850149bf242502f688eca80fb302d1f76 changed this condition
from an explicit
IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)
to
CONFIG_IS_ENABLED(SEPARATE_BSS)
The documentation for CONFIG_IS_ENABLED() in include/linux/kconfig.h
implies that we will get the correct behaviour, but the actual behaviour
differs such that this condition is now always false.
This stopped TPL being able to load the device tree blob at least on the
ROCKPro64 board (RK3399 SoC), since the wrong device tree location was
chosen.
The issues causing this behaviour with CONFIG_IS_ENABLED() are:
1. The documentation implies that CONFIG_SPL_BUILD =>
CONFIG_SPL_ is considered before the TPL equivalent.
Actually, the TPL options have higher priority - see definition of
_CONFIG_PREFIX.
2. The documentation implies a fallthrough, eg. if CONFIG_SPL_BUILD is
defined but the CONFIG_SPL_ is not, then it will proceed to
check if CONFIG_TPL_BUILD
Actually, if CONFIG_TPL_BUILD is defined, then it stops there
and CONFIG_SPL_BUILD is not considered - see definition of
_CONFIG_PREFIX.
During TPL build, at least for the ROCKPro64, both CONFIG_TPL_BUILD
and CONFIG_SPL_BUILD are defined, but because of the above, only TPL
options are considered. Since there is no CONFIG_TPL_SEPARATE_BSS,
this fails.
Fixes: 690af71850 ("fdt: Correct condition for SEPARATE_BSS")
Signed-off-by: Andrew Abbott
---
The serial output from a ROCKPro64 booting master (9859465bfe) is:
U-Boot TPL 2022.04-00787-g9859465bfe-dirty (Jan 01 1980 - 00:00:00)
Missing DTB
### ERROR ### Please RESET the board ###
I'm not 100% sure if this is the correct fix or if my analysis is right. This
issue affects the ROCKPro64 (rockpro64-rk3399_defconfig) but not the ROCK64
(rock64-rk3328_defconfig).
There may be differences in whether CONFIG_TPL_BUILD and
CONFIG_SPL_BUILD are defined for each during SPL or TPL build, or the
boards differ in what device tree operations they do when?
If this isn't the right fix, guidance on the correct approach would be
appreciated!
lib/fdtdec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 0c0ec034ec..e2208cb7d7 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1230,7 +1230,7 @@ static void *fdt_find_separate(void)
#ifdef CONFIG_SPL_BUILD
/* FDT is at end of BSS unless it is in a different memory region */
- if (CONFIG_IS_ENABLED(SEPARATE_BSS))
+ if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
fdt_blob = (ulong *)&_image_binary_end;
else
fdt_blob = (ulong *)&__bss_end;
--
2.35.1
[PATCH v1] rockchip: video: mipi: add more compatible strings for rk3288/rk3399
The rk3288/RK3399 DT synced from Linux contains some different
compatible strings in the mipi node then origanal used in U-boot.
Allow both options to be backwards compatible and to be able
to handle recent rk3288.dtsi and rk3399.dtsi files.
Signed-off-by: Johan Jonker
---
Fix for rk3288.dtsi and rk3399.dtsi sync from Linux.
Not tested with hardware.
---
drivers/video/rockchip/rk3288_mipi.c | 1 +
drivers/video/rockchip/rk3399_mipi.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/video/rockchip/rk3288_mipi.c
b/drivers/video/rockchip/rk3288_mipi.c
index 7e48dd83..c0dffa3c 100644
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -174,6 +174,7 @@ static const struct dm_display_ops rk_mipi_dsi_ops = {
};
static const struct udevice_id rk_mipi_dsi_ids[] = {
+ { .compatible = "rockchip,rk3288-mipi-dsi" },
{ .compatible = "rockchip,rk3288_mipi_dsi" },
{ }
};
diff --git a/drivers/video/rockchip/rk3399_mipi.c
b/drivers/video/rockchip/rk3399_mipi.c
index 91733504..7fc79ba9 100644
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -165,6 +165,7 @@ static const struct dm_display_ops rk_mipi_dsi_ops = {
};
static const struct udevice_id rk_mipi_dsi_ids[] = {
+ { .compatible = "rockchip,rk3399-mipi-dsi" },
{ .compatible = "rockchip,rk3399_mipi_dsi" },
{ }
};
--
2.20.1
[PATCH v1] rockchip: video: rk_edp: add more rk3288 edp node options
The rk3288 DT synced from Linux contains some different
properties in the edp node then origanal used in U-boot.
Allow both options to be backwards compatible and to be able
to handle recent rk3288.dtsi files.
Signed-off-by: Johan Jonker
---
Fix for rk3288.dtsi sync from Linux.
Not tested with hardware.
---
drivers/video/rockchip/rk_edp.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 0ddf5e02..3697d582 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -1070,8 +1070,11 @@ static int rk_edp_probe(struct udevice *dev)
ret = reset_get_by_name(dev, "dp", _rst);
if (ret) {
- dev_err(dev, "failed to get dp reset (ret=%d)\n", ret);
- return ret;
+ ret = reset_get_by_name(dev, "edp", _rst);
+ if (ret) {
+ dev_err(dev, "failed to get dp reset (ret=%d)\n", ret);
+ return ret;
+ }
}
ret = reset_assert(_rst);
@@ -1156,6 +1159,7 @@ static const struct rockchip_dp_data rk3288_dp = {
};
static const struct udevice_id rockchip_dp_ids[] = {
+ { .compatible = "rockchip,rk3288-dp", .data = (ulong)_dp },
{ .compatible = "rockchip,rk3288-edp", .data = (ulong)_dp },
{ .compatible = "rockchip,rk3399-edp", .data = (ulong)_edp },
{ }
--
2.20.1
Re: [PATCH v4 02/11] lib/charset: add u16_strlcat() function
On 3/24/22 14:54, Masahisa Kojima wrote:
Provide u16 string version of strlcat().
Signed-off-by: Masahisa Kojima
Reviewed-by: Simon Glass
---
Changes in v4:
- add blank line above the return statement
Changes in v2:
- implement u16_strlcat(with the destination buffer size in argument)
instead of u16_strcat
include/charset.h | 15 +++
lib/charset.c | 21 +
2 files changed, 36 insertions(+)
diff --git a/include/charset.h b/include/charset.h
index b93d023092..dc5fc275ec 100644
--- a/include/charset.h
+++ b/include/charset.h
@@ -259,6 +259,21 @@ u16 *u16_strcpy(u16 *dest, const u16 *src);
*/
u16 *u16_strdup(const void *src);
+/**
+ * u16_strlcat() - Append a length-limited, %NUL-terminated string to another
+ *
+ * Append the src string to the dest string, overwriting the terminating
+ * null word at the end of dest, and then adds a terminating null word.
+ * It will append at most size - u16_strlen(dst) - 1 bytes, NUL-terminating
the result.
Why "- 1"?
If size is even, we append up to size - u16_strlen(dst) - 2 bytes. The
two extra bytes used for 0x.
If size is odd, we append up to size - u16_strlen(dst) - 3 bytes leaving
one byte of the buffer unused.
+ *
+ * @dest: destination buffer (null terminated)
+ * @src: source buffer (null terminated)
+ * @size: destination buffer size in bytes
s/$/ including the trailing 0x/
+ * Return: total size of the created string in bytes.
+ * If return value >= size, truncation occurred.
+ */
+size_t u16_strlcat(u16 *dest, const u16 *src, size_t size);
+
/**
* utf16_to_utf8() - Convert an utf16 string to utf8
*
diff --git a/lib/charset.c b/lib/charset.c
index f44c58d9d8..47997eca7d 100644
--- a/lib/charset.c
+++ b/lib/charset.c
@@ -428,6 +428,27 @@ u16 *u16_strdup(const void *src)
return new;
}
+size_t u16_strlcat(u16 *dest, const u16 *src, size_t size)
+{
If you start the function with
size >>= 1;
or
size /= sizeof(u16);
this might simplify the code.
+ size_t dstrlen = u16_strnlen(dest, size >> 1);
+ size_t dlen = dstrlen * sizeof(u16);
+ size_t len = u16_strlen(src) * sizeof(u16);
+ size_t ret = dlen + len;
This misses the trailing 0x.
Best regards
Heinrich
+
+ if (dlen >= size)
+ return ret;
+
+ dest += dstrlen;
+ size -= dlen;
+ if (len >= size)
+ len = size - sizeof(u16);
+
+ memcpy(dest, src, len);
+ dest[len >> 1] = u'\0';
+
+ return ret;
+}
+
/* Convert UTF-16 to UTF-8. */
uint8_t *utf16_to_utf8(uint8_t *dest, const uint16_t *src, size_t size)
{
Re: [PATCH 04/11] arm: mach-k3: Introduce the basic files to support AM62
Hi, On 15/04/22 11:11 pm, Tom Rini wrote: > On Fri, Apr 15, 2022 at 10:08:32PM +0530, Vignesh Raghavendra wrote: >> >> >> On 15/04/22 9:57 pm, Tom Rini wrote: >>> On Fri, Apr 15, 2022 at 07:39:24PM +0530, Vignesh Raghavendra wrote: >>> >>> [snip] diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c new file mode 100644 index 00..ee902a774e --- /dev/null +++ b/arch/arm/mach-k3/am625_init.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM625: SoC specific initialization + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + *Suman Anna + */ + +#include +#include +#include +#include +#include +#include "common.h" +#include +#include +#include >>> >>> Er, common.h twice? >> >> Second one refers to arch/arm/mach-k3/common.h > > OK, lets rename that, and see what info there we can put elsewhere. arch/arm/mach-k3/common.c which contains set of helper functions that are used across the K3 family of devices and this header exports those helpers (and is local to arch/arm/mach-k3/). We may have split into multiple files according to functions in a separate series. > >>> Please re-check this, and then also drop common.h >>> (here and elsewhere) as it only includes other headers and we should >>> avoid it when possible. >> >> Sure, will do. >> >>> In fact, checkpatch.pl complains about both >>> dm.h and common.h so please address series-wide, thanks. >>> >> >> Unfortunately, it doesn't ;( > > Ah, right. It only checks for inside of headers. But still should be > avoided. > Yes, I will drop including in next version. Regards Vignesh
Re: [PATCH v4 00/11] enable menu-driven boot device selection
On 3/24/22 14:54, Masahisa Kojima wrote: This patch series adds the menu-driven boot device selection, by extending the existing "bootmenu" to include UEFI and distro_boot related entries, and supports menu-driven UEFI boot variable maintenance. This patch series also includes the removable media support that UEFI specification requires to support. The menu example is as follows. *** U-Boot Boot Menu *** bootmenu_00 : Boot 1. kernel bootmenu_01 : Boot 2. kernel bootmenu_02 : Reset board UEFI BOOT : debian UEFI BOOT0001 : ubuntu UEFI BOOT0002 : mmc0:1 UEFI BOOT0003 : mmc0:2 UEFI BOOT0004 : nvme0:1 UEFI BOOT0005 : nvme0:2 UEFI BOOT0006 : usb0:2 UEFI BOOT0007 : usb1:1 UEFI BOOT0008 : usb1:2 distro_boot : usb0 distro_boot : scsi0 distro_boot : virtio0 distro_boot : dhcp Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit [Major changes from RFC v3] - add Kconfig option to disable U-Boot console - add UEFI boot variable maintenance feature - support removable media support and user selection - app bootmenu enhancement documentation [How to run on QEMU(arm64)] 1) clone source code $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git \ -b kojima/bootmenu_v4_upstream_0324 --depth 1 2) prepare U-Boot .config $ make qemu_arm64_menuconfig then, enable CONFIG_CMD_BOOTMENU and CONFIG_AUTOBOOT_MENU_SHOW 3) run on QEMU(arm64) example $ qemu-system-aarch64 -machine virt,gic-version=3 -cpu cortex-a57 -m 4G -nographic \ -no-acpi -bios ./u-boot.bin -hda xxx.img I applied the series to origin/master and added the two config options. This is the output if the disk image does not have an EFI partition: Found 0 disks No EFI system partition Unable to find TPMv2 device Even if there is no EFI system partition on virtio 0 I would expect the menu to be shown. When having an image with an EFI system partition I get: *** U-Boot Boot Menu *** UEFI BOOT0003 : test3 UEFI BOOT00A0 : hello UEFI BOOT : virtio0:1 distro_boot : usb0 distro_boot : scsi0 distro_boot : virtio0 distro_boot : nvme0 distro_boot : dhcp UEFI Boot Manager Maintenance U-Boot console The entries usb0, scsi0, nvme0 should not exist as there is no such device. => lsblk Block Driver Devices - efi_blk : nvme-blk: scsi_blk: usb_storage_blk : virtio-blk : virtio 0 When I select "U-Boot console" the prompt is written in the middle of the screen. I would expect the screen to be cleared. If I disable networking, I get Missing RNG device for EFI_RNG_PROTOCOL No EFI system partition Unable to find TPMv2 device => though the disk has an EFI partition. So this series needs some rework. Best regards Heinrich AKASHI Takahiro (2): efi_loader: export efi_locate_device_handle() efi_loader: bootmgr: add booting from removable media Masahisa Kojima (9): bootmenu: fix menu API error handling lib/charset: add u16_strlcat() function test: unit test for u16_strlcat() menu: always show the menu regardless of the number or entry bootmenu: add UEFI and disto_boot entries bootmenu: factor out the user input handling efi_loader: add menu-driven UEFI Boot Variable maintenance bootmenu: add removable media entries doc:bootmenu: add UEFI boot variable and distro boot support cmd/Kconfig | 10 + cmd/bootmenu.c| 678 +++ common/menu.c | 139 ++- doc/usage/bootmenu.rst| 65 ++ include/charset.h | 15 + include/config_distro_bootcmd.h | 14 +- include/efi_default_filename.h| 26 + include/efi_loader.h | 63 ++ include/menu.h| 20 + lib/charset.c | 21 + lib/efi_loader/Makefile |1 + lib/efi_loader/efi_bootmenu_maintenance.c | 1244 + lib/efi_loader/efi_bootmgr.c | 50 +- lib/efi_loader/efi_boottime.c | 59 +- lib/efi_loader/efi_console.c | 81 ++ lib/efi_loader/efi_disk.c | 11 + lib/efi_loader/efi_file.c | 75 +- test/unicode_ut.c | 45 + 18 files changed, 2357 insertions(+), 260 deletions(-) create mode 100644 include/efi_default_filename.h create mode 100644 lib/efi_loader/efi_bootmenu_maintenance.c
