Re: [PATCH v2 8/8] ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig
Hi Jesse, On Fri, Jun 17, 2022 at 1:42 PM Jesse Taube wrote: > > Add a base defconfig for the i.MXRT1170 This should be part of the patch that adds support for the board (1/8). > +CONFIG_ARM=y > +CONFIG_SYS_DCACHE_OFF=y Any reason to turn off DCACHE?
Re: [PATCH 1/3] board: ti: common: Optimize boot when detecting consecutive bad records
On Fri, Jun 17, 2022 at 02:19:57PM -0500, Nishanth Menon wrote: > On 14:50-20220617, Tom Rini wrote: > > On Fri, Jun 17, 2022 at 01:26:10PM -0500, Nishanth Menon wrote: > > > > > The eeprom data area is much bigger than the data we intend to store, > > > however, with bad programming, we might end up reading bad records over > > > and over till we run out of eeprom space. instead just exit when 10 > > > consecutive records are read. > > > > > > Signed-off-by: Nishanth Menon > > > > Why not just stop at the first bad record? Otherwise 10 seems like a > > Because it could be just a couple of bad ones where the header.len > does'nt match up with record data. Some folks use a spreadsheet to > generate the records, some manually and some script it up - so, > attempting to get the best possible success chance while warning > invalid data to get people to fix things made sense. > > > fine, small, arbitrary number. If it's not arbitrary but number of > > total records, do we already enum the total number of records or > > something where we could say that we tried to read all possible records, > > everyone was bad, stop? > > It is arbitrary small value - for all practical purposes, we have 6 > types of records atm in u-boot, even looking ahead, we have'nt had > more than that I know of (I think display, camera and few other misc > types got added). The structure however, is by design flexible > with the END_LIST marker denoting the last record - and depending on > the eeprom size, you could theoretically have a large variation. > > Considering this is attempting to recover from bad programming, the > chances are better when attempting a few more entries, but I dont > think going aggressive with a single record or conservative (as it is > right now) in scanning the entire eeprom is necessary. That leaves us > with some sort of practical number. OK, thanks for explaining. Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
[PATCH 4/4] powerpc: Clean up CHAIN_OF_TRUST related options
As things stand currently, there is only one PowerPC platform that enables the options for CHAIN_OF_TRUST. From the board header files, remove a number of never-set options. Remove board specific values from arch/powerpc/include/asm/fsl_secure_boot.h as well. Rework include/config_fsl_chain_trust.h to not abuse the CONFIG namespace for constructing CHAIN_BOOT_CMD. Migrate all of the configurable addresses to Kconfig. If any platforms are re-introduced with secure boot support, everything required should still be here, but now in Kconfig, or requires migration of an option to Kconfig. Cc: Peng Fan Signed-off-by: Tom Rini --- arch/Kconfig.nxp| 40 +++ arch/powerpc/include/asm/fsl_secure_boot.h | 43 + board/freescale/common/fsl_chain_of_trust.c | 5 ++- configs/T2080QDS_SECURE_BOOT_defconfig | 1 + include/config_fsl_chain_trust.h| 35 +++-- include/configs/P1010RDB.h | 4 +- include/configs/T104xRDB.h | 8 include/configs/corenet_ds.h| 9 - 8 files changed, 61 insertions(+), 84 deletions(-) diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 5ec0ee076eb1..7a35560282fb 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -74,6 +74,46 @@ config SPL_UBOOT_KEY_HASH 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b. Otherwise leave this empty. +if PPC + +config BOOTSCRIPT_COPY_RAM + bool "Secure boot copies boot script to RAM" + help + On systems that support chain of trust booting, a number of addresses + are required to set variables that are used in the copying and then + verification of different parts of the system. If enabled, the subsequent + options are for what location to use in each step. + +config BS_ADDR_DEVICE + hex "Address in RAM for bs_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_SIZE + hex "The size of bs_size which is the amount read from bs_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_ADDR_RAM + hex "Address in RAM for bs_ram" + depends on BOOTSCRIPT_COPY_RAM + +config BS_HDR_ADDR_DEVICE + hex "Address in RAM for bs_hdr_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_HDR_SIZE + hex "The size of bs_hdr_size which is the amount read from bs_hdr_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_HDR_ADDR_RAM + hex "Address in RAM for bs_hdr_ram" + depends on BOOTSCRIPT_COPY_RAM + +config BOOTSCRIPT_HDR_ADDR + hex "CONFIG_BOOTSCRIPT_HDR_ADDR" + default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM + +endif + config SYS_FSL_SRK_LE def_bool y depends on ARM diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index c062fa5c191c..a96a1ac5d77e 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,19 +10,12 @@ #ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc000 -#elif defined(CONFIG_TARGET_BSC9132QDS) -#define CONFIG_SYS_PBI_FLASH_BASE 0xc800 -#elif defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_SYS_PBI_FLASH_BASE 0xcc00 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce00 #endif #define CONFIG_SYS_PBI_FLASH_WINDOW0xcff8 -#if defined(CONFIG_TARGET_B4860QDS) || \ - defined(CONFIG_TARGET_B4420QDS) || \ - defined(CONFIG_TARGET_T4240QDS) || \ - defined(CONFIG_TARGET_T2080QDS) || \ +#if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ defined(CONFIG_TARGET_T1042RDB) || \ defined(CONFIG_TARGET_T1042D4RDB) || \ @@ -78,40 +71,6 @@ #endif /* ifdef CONFIG_SPL_BUILD */ #ifndef CONFIG_SPL_BUILD -/* - * fsl_setenv_chain_of_trust() must be called from - * board_late_init() - */ - -/* If Boot Script is not on NOR and is required to be copied on RAM */ -#ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_HDR_ADDR_RAM 0x0001 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x0080 -#define CONFIG_BS_HDR_SIZE 0x2000 -#define CONFIG_BS_ADDR_RAM 0x00012000 -#define CONFIG_BS_ADDR_DEVICE 0x00802000 -#define CONFIG_BS_SIZE 0x1000 - -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM -#else - -/* The bootscript header address is different for B4860 because the NOR - * mapping is different on B4 due to reduced NOR size. - */ -#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc0 -#elif defined(CONFIG_FSL_CORENET) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e0 -#elif defined(CONFIG_TARGET_BSC9132QDS) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x8802 -#elif defined(CONFIG_TARGET_C29XPCIE) -#define
[PATCH 3/4] nxp: config_fsl_chain_trust.h: Clean up and remove unused portions
The way that secure boot is implemented today on NXP ARM platforms does not reuse the elements found in include/config_fsl_chain_trust.h to construct CONFIG_SECBOOT but instead board header files have their environment setup as needed and then fsl_setenv_chain_of_trust() will set secureboot in the environment. Remove a large number of unused defines here. Cc: Peng Fan Signed-off-by: Tom Rini --- arch/arm/include/asm/fsl_secure_boot.h | 71 -- include/config_fsl_chain_trust.h | 25 - 2 files changed, 96 deletions(-) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 9c9e1dab9a41..a4f4961fc877 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -24,76 +24,6 @@ #endif -#ifdef CONFIG_ARCH_LS2080A -#define CONFIG_EXTRA_ENV \ - "setenv fdt_high 0xa000;" \ - "setenv initrd_high 0xcfff;"\ - "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -#else -#define CONFIG_EXTRA_ENV \ - "setenv fdt_high 0x;" \ - "setenv initrd_high 0x;"\ - "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -#endif - -/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from - * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ - defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT) -#define CONFIG_BOOTSCRIPT_COPY_RAM -#endif -/* The address needs to be modified according to NOR, NAND, SD and - * DDR memory map - */ -#ifdef CONFIG_FSL_LSCH3 -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_BS_ADDR_DEVICE 0x2060 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x2064 -#else /* NOR BOOT */ -#define CONFIG_BS_ADDR_DEVICE 0x58060 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x58064 -#endif /*ifdef CONFIG_QSPI_BOOT */ -#define CONFIG_BS_SIZE 0x1000 -#define CONFIG_BS_HDR_SIZE 0x4000 -#define CONFIG_BS_ADDR_RAM 0xa060 -#define CONFIG_BS_HDR_ADDR_RAM 0xa064 -#else -#ifdef CONFIG_SD_BOOT -/* For SD boot address and size are assigned in terms of sector - * offset and no. of sectors respectively. - */ -#define CONFIG_BS_ADDR_DEVICE 0x3000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x3200 -#define CONFIG_BS_SIZE 0x0008 -#define CONFIG_BS_HDR_SIZE 0x0010 -#elif defined(CONFIG_NAND_BOOT) -#define CONFIG_BS_ADDR_DEVICE 0x0060 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x0064 -#define CONFIG_BS_SIZE 0x1000 -#define CONFIG_BS_HDR_SIZE 0x2000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_BS_ADDR_DEVICE 0x4060 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x4064 -#define CONFIG_BS_SIZE 0x1000 -#define CONFIG_BS_HDR_SIZE 0x2000 -#else /* Default NOR Boot */ -#define CONFIG_BS_ADDR_DEVICE 0x6060 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x6064 -#define CONFIG_BS_SIZE 0x1000 -#define CONFIG_BS_HDR_SIZE 0x2000 -#endif -#define CONFIG_BS_ADDR_RAM 0x8100 -#define CONFIG_BS_HDR_ADDR_RAM 0x8102 -#endif - -#ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM -#else -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE -/* BOOTSCRIPT_ADDR is not required */ -#endif - #ifdef CONFIG_FSL_LS_PPA /* Define the key hash here if SRK used for signing PPA image is * different from SRK hash put in SFP used for U-Boot. @@ -104,7 +34,6 @@ #define PPA_KEY_HASH NULL #endif /* ifdef CONFIG_FSL_LS_PPA */ -#include #endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 3922241be005..dd01e9668941 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -10,10 +10,6 @@ #ifdef CONFIG_CHAIN_OF_TRUST -#ifndef CONFIG_EXTRA_ENV -#define CONFIG_EXTRA_ENV "" -#endif - /* * Control should not reach back to uboot after validation of images * for secure boot flow and therefore bootscript should have @@ -21,14 +17,6 @@ * after validating images, core should just spin. */ -/* - * Define the key hash for boot script here if public/private key pair used to - * sign bootscript are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_BOOTSCRIPT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - */ - #ifdef CONFIG_USE_BOOTARGS #define CONFIG_SET_BOOTARGS"setenv bootargs \'" CONFIG_BOOTARGS" \';" #else @@ -36,25 +24,12 @@ "rw console=ttyS0,115200 ramdisk_size=60\';"
[PATCH 2/4] fsl_validate: Migrate SPL_UBOOT_KEY_HASH to Kconfig
Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig. As
part of this, change fsl_secboot_validate(...) to check that it is
passed a non-empty string, rather than non-NULL.
Cc: Peng Fan
Cc: Priyanka Jain
Cc: Kshitiz Varshney
Signed-off-by: Tom Rini
---
arch/Kconfig.nxp | 11 +++
arch/arm/include/asm/fsl_secure_boot.h | 13 -
arch/powerpc/include/asm/fsl_secure_boot.h | 10 --
board/freescale/common/fsl_validate.c | 2 +-
4 files changed, 12 insertions(+), 24 deletions(-)
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index f72c513aa6a8..5ec0ee076eb1 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -63,6 +63,17 @@ config SYS_FSL_SFP_VER_3_4
endchoice
+config SPL_UBOOT_KEY_HASH
+ string "Non-SRK key hash for U-Boot public/private key pair"
+ depends on SPL
+ default ""
+ help
+ Set the key hash for U-Boot here if public/private key pair used to
+ sign U-boot are different from the SRK hash put in the fuse. Example
+ of a key hash is
+ 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
+ Otherwise leave this empty.
+
config SYS_FSL_SRK_LE
def_bool y
depends on ARM
diff --git a/arch/arm/include/asm/fsl_secure_boot.h
b/arch/arm/include/asm/fsl_secure_boot.h
index 09c88841e0c0..9c9e1dab9a41 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -8,19 +8,6 @@
#define __FSL_SECURE_BOOT_H
#ifdef CONFIG_CHAIN_OF_TRUST
-#ifdef CONFIG_SPL_BUILD
-/*
- * Define the key hash for U-Boot here if public/private key pair used to
- * sign U-boot are different from the SRK hash put in the fuse
- * Example of defining KEY_HASH is
- * #define CONFIG_SPL_UBOOT_KEY_HASH \
- * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
- * else leave it defined as NULL
- */
-
-#define CONFIG_SPL_UBOOT_KEY_HASH NULL
-#endif /* ifdef CONFIG_SPL_BUILD */
-
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 9ae4c590f1d5..c062fa5c191c 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -75,16 +75,6 @@
#define CONFIG_SPL_SPAACT_ADDR 0x2f00
#define CONFIG_SPL_JR0_LIODN_S 454
#define CONFIG_SPL_JR0_LIODN_NS458
-/*
- * Define the key hash for U-Boot here if public/private key pair used to
- * sign U-boot are different from the SRK hash put in the fuse
- * Example of defining KEY_HASH is
- * #define CONFIG_SPL_UBOOT_KEY_HASH \
- * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
- * else leave it defined as NULL
- */
-
-#define CONFIG_SPL_UBOOT_KEY_HASH NULL
#endif /* ifdef CONFIG_SPL_BUILD */
#ifndef CONFIG_SPL_BUILD
diff --git a/board/freescale/common/fsl_validate.c
b/board/freescale/common/fsl_validate.c
index 34875d0b8f25..f1a0b0cfc34c 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -871,7 +871,7 @@ int fsl_secboot_validate(uintptr_t haddr, char
*arg_hash_str,
int ret, i, hash_cmd = 0;
u32 srk_hash[8];
- if (arg_hash_str != NULL) {
+ if (strlen(arg_hash_str) != 0) {
const char *cp = arg_hash_str;
int i = 0;
--
2.25.1
[PATCH 1/4] arch/Kconfig.nxp: Re-organize slightly
Make all of the CHAIN_OF_TRUST options be under a single menu and add a comment for the rest, so the resulting config file reads more clearly. Remove duplicate CHAIN_OF_TRUST options from board/congatec/common/Kconfig. Remove duplicate NXP_ESBC config questions and move to arch/Kconfig.nxp. Signed-off-by: Tom Rini --- arch/Kconfig.nxp | 30 +++-- arch/arm/cpu/armv7/ls102xa/Kconfig| 6 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 15 +++-- arch/powerpc/cpu/mpc85xx/Kconfig | 6 board/congatec/common/Kconfig | 41 --- 5 files changed, 24 insertions(+), 74 deletions(-) diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 1e26f1dc5372..f72c513aa6a8 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -1,7 +1,13 @@ -config CHAIN_OF_TRUST +config NXP_ESBC + bool "NXP ESBC (secure boot) functionality" + help + Enable Freescale Secure Boot feature. Normally selected by defconfig. + If unsure, do not change. + +menu "Chain of trust / secure boot options" depends on !FIT_SIGNATURE && NXP_ESBC - imply CMD_BLOB - imply CMD_HASH if ARM + +config CHAIN_OF_TRUST select FSL_CAAM select FSL_SEC_MON select SPL_BOARD_INIT if (ARM && SPL) @@ -11,12 +17,12 @@ config CHAIN_OF_TRUST select ENV_IS_NOWHERE select CMD_EXT4 if ARM select CMD_EXT4_WRITE if ARM - bool - default y + imply CMD_BLOB + imply CMD_HASH if ARM + def_bool y config CMD_ESBC_VALIDATE bool "Enable the 'esbc_validate' and 'esbc_halt' commands" - depends on CHAIN_OF_TRUST default y help This option enables two commands used for secure booting: @@ -35,15 +41,14 @@ config ESBC_ADDR_64BIT config SYS_FSL_SFP_BE def_bool y - depends on CHAIN_OF_TRUST && (PPC || FSL_LSCH2 || ARCH_LS1021A) + depends on PPC || FSL_LSCH2 || ARCH_LS1021A config SYS_FSL_SFP_LE def_bool y - depends on CHAIN_OF_TRUST && !SYS_FSL_SFP_BE + depends on !SYS_FSL_SFP_BE choice prompt "SFP IP revision" - depends on CHAIN_OF_TRUST default SYS_FSL_SFP_VER_3_0 if PPC default SYS_FSL_SFP_VER_3_4 @@ -60,11 +65,14 @@ endchoice config SYS_FSL_SRK_LE def_bool y - depends on CHAIN_OF_TRUST && ARM + depends on ARM config KEY_REVOCATION def_bool y - depends on CHAIN_OF_TRUST + +endmenu + +comment "Other functionality shared between NXP SoCs" config DEEP_SLEEP bool "Enable SoC deep sleep feature" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index c496e6439199..a901360fa7d8 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -41,12 +41,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config NXP_ESBC - bool"NXP_ESBC" - help - Enable Freescale Secure Boot feature. Normally selected - by defconfig. If unsure, do not change. - config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 7f08733a35b6..602b624dca52 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -26,7 +26,7 @@ config ARCH_LS1012A config ARCH_LS1028A bool select ARMV8_SET_SMPEN - select ESBC_HDR_LS + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_LAYERSCAPE select FSL_LSCH3 select GICV3 @@ -139,7 +139,7 @@ config ARCH_LS1088A bool select ARMV8_SET_SMPEN select ARM_ERRATA_855873 if !TFABOOT - select ESBC_HDR_LS + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_IFC select FSL_LAYERSCAPE select FSL_LSCH3 @@ -189,7 +189,7 @@ config ARCH_LS2080A select ARM_ERRATA_828024 select ARM_ERRATA_829520 select ARM_ERRATA_833471 - select ESBC_HDR_LS + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_IFC select FSL_LAYERSCAPE select FSL_LSCH3 @@ -242,7 +242,7 @@ config ARCH_LS2080A config ARCH_LX2162A bool select ARMV8_SET_SMPEN - select ESBC_HDR_LS + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_DDR_BIST select FSL_DDR_INTERACTIVE select FSL_LAYERSCAPE @@ -281,7 +281,7 @@ config ARCH_LX2162A config ARCH_LX2160A bool select ARMV8_SET_SMPEN - select ESBC_HDR_LS + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_DDR_BIST select FSL_DDR_INTERACTIVE select FSL_LAYERSCAPE @@ -461,11 +461,6 @@ config EMC2305 Enable the EMC2305 fan controller for configuration of
Re: [PATCH] firmware: ti_sci_static_data: Make file board agnostic
On 19:33-20220615, Vignesh Raghavendra wrote:
> Static DMA channel data for R5 SPL is mostly board agnostic so use SOC
> configs instead of EVM specific config to ease adding new board support.
>
> Drop J7200 EVM specific settings as its same as J721e
>
> Signed-off-by: Vignesh Raghavendra
Gee thanks.
Reviewed-by: Nishanth Menon
> ---
> drivers/firmware/ti_sci_static_data.h | 42 +++
> 1 file changed, 4 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/firmware/ti_sci_static_data.h
> b/drivers/firmware/ti_sci_static_data.h
> index 8529ef2900..5ae0556a9a 100644
> --- a/drivers/firmware/ti_sci_static_data.h
> +++ b/drivers/firmware/ti_sci_static_data.h
> @@ -16,7 +16,7 @@ struct ti_sci_resource_static_data {
>
> #if IS_ENABLED(CONFIG_K3_DM_FW)
>
> -#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM)
> +#if IS_ENABLED(CONFIG_SOC_K3_J721E)
> static struct ti_sci_resource_static_data rm_static_data[] = {
> /* Free rings */
> {
> @@ -48,43 +48,9 @@ static struct ti_sci_resource_static_data rm_static_data[]
> = {
> },
> { },
> };
> -#endif /* CONFIG_TARGET_J721E_R5_EVM */
> +#endif /* CONFIG_SOC_K3_J721E */
>
> -#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)
> -static struct ti_sci_resource_static_data rm_static_data[] = {
> - /* Free rings */
> - {
> - .dev_id = 235,
> - .subtype = 1,
> - .range_start = 124,
> - .range_num = 32,
> - },
> - /* TX channels */
> - {
> - .dev_id = 236,
> - .subtype = 13,
> - .range_start = 6,
> - .range_num = 2,
> - },
> - /* RX channels */
> - {
> - .dev_id = 236,
> - .subtype = 10,
> - .range_start = 6,
> - .range_num = 2,
> - },
> - /* RX Free flows */
> - {
> - .dev_id = 236,
> - .subtype = 0,
> - .range_start = 60,
> - .range_num = 8,
> - },
> - { },
> -};
> -#endif /* CONFIG_TARGET_J7200_R5_EVM */
> -
> -#if IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)
> +#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
> static struct ti_sci_resource_static_data rm_static_data[] = {
> /* Free rings */
> {
> @@ -116,7 +82,7 @@ static struct ti_sci_resource_static_data rm_static_data[]
> = {
> },
> { },
> };
> -#endif /* CONFIG_TARGET_J721S2_R5_EVM */
> +#endif /* CONFIG_SOC_K3_J721S2 */
>
> #if IS_ENABLED(CONFIG_SOC_K3_AM625)
> static struct ti_sci_resource_static_data rm_static_data[] = {
> --
> 2.36.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
849D 1736 249D
Re: [PATCH 1/3] board: ti: common: Optimize boot when detecting consecutive bad records
On 14:50-20220617, Tom Rini wrote: > On Fri, Jun 17, 2022 at 01:26:10PM -0500, Nishanth Menon wrote: > > > The eeprom data area is much bigger than the data we intend to store, > > however, with bad programming, we might end up reading bad records over > > and over till we run out of eeprom space. instead just exit when 10 > > consecutive records are read. > > > > Signed-off-by: Nishanth Menon > > Why not just stop at the first bad record? Otherwise 10 seems like a Because it could be just a couple of bad ones where the header.len does'nt match up with record data. Some folks use a spreadsheet to generate the records, some manually and some script it up - so, attempting to get the best possible success chance while warning invalid data to get people to fix things made sense. > fine, small, arbitrary number. If it's not arbitrary but number of > total records, do we already enum the total number of records or > something where we could say that we tried to read all possible records, > everyone was bad, stop? It is arbitrary small value - for all practical purposes, we have 6 types of records atm in u-boot, even looking ahead, we have'nt had more than that I know of (I think display, camera and few other misc types got added). The structure however, is by design flexible with the END_LIST marker denoting the last record - and depending on the eeprom size, you could theoretically have a large variation. Considering this is attempting to recover from bad programming, the chances are better when attempting a few more entries, but I dont think going aggressive with a single record or conservative (as it is right now) in scanning the entire eeprom is necessary. That leaves us with some sort of practical number. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Re: [PATCH 1/3] board: ti: common: Optimize boot when detecting consecutive bad records
On Fri, Jun 17, 2022 at 01:26:10PM -0500, Nishanth Menon wrote: > The eeprom data area is much bigger than the data we intend to store, > however, with bad programming, we might end up reading bad records over > and over till we run out of eeprom space. instead just exit when 10 > consecutive records are read. > > Signed-off-by: Nishanth Menon Why not just stop at the first bad record? Otherwise 10 seems like a fine, small, arbitrary number. If it's not arbitrary but number of total records, do we already enum the total number of records or something where we could say that we tried to read all possible records, everyone was bad, stop? -- Tom signature.asc Description: PGP signature
[PATCH 3/3] board: ti: common: board_detect: Do 1byte address checks first.
Do 1 byte address checks first prior to doing 2 byte address checks.
When performing 2 byte addressing on 1 byte addressing eeprom, the
second byte is taken in as a write operation and ends up erasing the
eeprom region we want to preserve.
While we could have theoretically handled this by ensuring the write
protect of the eeproms are properly managed, this is not true in case
where board are updated with 1 byte eeproms to handle supply status.
Flipping the checks by checking for 1 byte addressing prior to 2 byte
addressing check prevents this problem at the minor cost of additional
overhead for boards with 2 byte addressing eeproms.
Signed-off-by: Nishanth Menon
---
board/ti/common/board_detect.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index 0806dea11ed5..ed34991377ee 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -103,14 +103,14 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr,
int dev_addr,
/*
* Read the header first then only read the other contents.
*/
- rc = i2c_set_chip_offset_len(dev, 2);
+ rc = i2c_set_chip_offset_len(dev, 1);
if (rc)
return rc;
/*
* Skip checking result here since this could be a valid i2c read fail
-* on some boards that use 1 byte addressing.
-* We must allow for fall through to check the data if 1 byte
+* on some boards that use 2 byte addressing.
+* We must allow for fall through to check the data if 2 byte
* addressing works
*/
(void)dm_i2c_read(dev, 0, (uint8_t *)_read, 4);
@@ -119,9 +119,9 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr,
int dev_addr,
if (hdr_read != header) {
/*
* read the eeprom header using i2c again, but use only a
-* 1 byte address (some legacy boards need this..)
+* 2 byte address (some newer boards need this..)
*/
- rc = i2c_set_chip_offset_len(dev, 1);
+ rc = i2c_set_chip_offset_len(dev, 2);
if (rc)
return rc;
@@ -146,12 +146,12 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr,
int dev_addr,
/*
* Read the header first then only read the other contents.
*/
- byte = 2;
+ byte = 1;
/*
* Skip checking result here since this could be a valid i2c read fail
-* on some boards that use 1 byte addressing.
-* We must allow for fall through to check the data if 1 byte
+* on some boards that use 2 byte addressing.
+* We must allow for fall through to check the data if 2 byte
* addressing works
*/
(void)i2c_read(dev_addr, 0x0, byte, (uint8_t *)_read, 4);
@@ -160,9 +160,9 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr,
int dev_addr,
if (hdr_read != header) {
/*
* read the eeprom header using i2c again, but use only a
-* 1 byte address (some legacy boards need this..)
+* 2 byte address (some newer boards need this..)
*/
- byte = 1;
+ byte = 2;
rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)_read,
4);
if (rc)
--
2.31.1
[PATCH 1/3] board: ti: common: Optimize boot when detecting consecutive bad records
The eeprom data area is much bigger than the data we intend to store,
however, with bad programming, we might end up reading bad records over
and over till we run out of eeprom space. instead just exit when 10
consecutive records are read.
Signed-off-by: Nishanth Menon
---
board/ti/common/board_detect.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index de92eb0981f9..381cddc00ad1 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -434,6 +434,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int
dev_addr,
struct ti_am6_eeprom_record_board_id board_id;
struct ti_am6_eeprom_record record;
int rc;
+ int consecutive_bad_records = 0;
/* Initialize with a known bad marker for i2c fails.. */
memset(ep, 0, sizeof(*ep));
@@ -470,7 +471,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int
dev_addr,
*/
eeprom_addr = sizeof(board_id);
- while (true) {
+ while (consecutive_bad_records < 10) {
rc = dm_i2c_read(dev, eeprom_addr, (uint8_t *),
sizeof(record.header));
if (rc)
@@ -506,6 +507,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int
dev_addr,
pr_err("%s: EEPROM parsing error!\n", __func__);
return rc;
}
+ consecutive_bad_records = 0;
} else {
/*
* We may get here in case of larger records which
@@ -513,6 +515,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int
dev_addr,
*/
pr_err("%s: Ignoring record id %u\n", __func__,
record.header.id);
+ consecutive_bad_records++;
}
eeprom_addr += record.header.len;
--
2.31.1
[PATCH 2/3] board: ti: common: Handle the legacy eeprom address width properly
Due to supply chain issues, we are starting to see a mixture of eeprom
usage including the smaller 7-bit addressing eeproms such as 24c04
used for eeproms.
These eeproms don't respond well to 2 byte addressing and fail the
read operation. We do have a check to ensure that we are reading the
alternate addressing size, however the valid failure prevents us
from checking at 1 byte anymore.
Rectify the same by falling through and depend on header data comparison
to ensure that we have valid data.
Signed-off-by: Nishanth Menon
---
board/ti/common/board_detect.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index 381cddc00ad1..0806dea11ed5 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -86,7 +86,7 @@ __weak void gpi2c_init(void)
static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
u32 header, u32 size, uint8_t *ep)
{
- u32 hdr_read;
+ u32 hdr_read = 0xdeadbeef;
int rc;
#if CONFIG_IS_ENABLED(DM_I2C)
@@ -107,9 +107,13 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr,
int dev_addr,
if (rc)
return rc;
- rc = dm_i2c_read(dev, 0, (uint8_t *)_read, 4);
- if (rc)
- return rc;
+ /*
+* Skip checking result here since this could be a valid i2c read fail
+* on some boards that use 1 byte addressing.
+* We must allow for fall through to check the data if 1 byte
+* addressing works
+*/
+ (void)dm_i2c_read(dev, 0, (uint8_t *)_read, 4);
/* Corrupted data??? */
if (hdr_read != header) {
@@ -144,9 +148,13 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr,
int dev_addr,
*/
byte = 2;
- rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)_read, 4);
- if (rc)
- return rc;
+ /*
+* Skip checking result here since this could be a valid i2c read fail
+* on some boards that use 1 byte addressing.
+* We must allow for fall through to check the data if 1 byte
+* addressing works
+*/
+ (void)i2c_read(dev_addr, 0x0, byte, (uint8_t *)_read, 4);
/* Corrupted data??? */
if (hdr_read != header) {
--
2.31.1
[PATCH 0/3] board: ti: common: Fixups and optimizations for eeprom handling
Hi, These are few of the fixes picked up from U-boot tree done for BeagleBone-AI64 and others. Additional testing is much appreciated - my test environment is currently limited :( Nishanth Menon (3): board: ti: common: Optimize boot when detecting consecutive bad records board: ti: common: Handle the legacy eeprom address width properly board: ti: common: board_detect: Do 1byte address checks first. board/ti/common/board_detect.c | 39 ++ 1 file changed, 25 insertions(+), 14 deletions(-) -- 2.31.1
Re: Re: [Rock Pi 4+] Mainline LPDDR4 RAM initialisation is not sufficient to boot successfully
On Fri, 17 Jun 2022, c...@rock-chips.com wrote: > Could you help us to get the DRAM part number which initialization failures > on the Rock Pi 4+. I have tested 3 boards; one appears to be fully working, on another 1 of the 2 LPDDR4 (Channel 1) chips consistently fails with a Col and Cap Error and on the final one both chips (Channel 0 & 1) fail in the same way as the last (Col and Cap errors). All chips are: H9HCNNNBKUML > We have found that some LPDDR4 abnormal operation at 50MHz. > I think you can try that use 400MHz to detect capacity. Wonderful. This solves the problem. Thank you so much! Would you like to submit this into upstream U-boot yourself, or would you like me to do that for you? If the former, please Cc me on the patch and add my: Tested-by Lee Jones If the latter, please let me know and I'll do what I can to help. -- Lee Jones [李琼斯] Principal Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
[PATCH v2 7/8] ARM: dts: imx: add i.MXRT1170-EVK support
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and Cortex-M4 core.
The EVK provides 64 MB SDRAM, Micro SD card socket,
USB 2.0 OTG.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
SDRAM
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Remove unused constant clocks
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imxrt1170-evk-u-boot.dtsi | 94 +
arch/arm/dts/imxrt1170-evk.dts | 250
arch/arm/dts/imxrt1170.dtsi| 257 +
4 files changed, 603 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/dts/imxrt1170.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0a2713c06a..85d166b292 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -967,7 +967,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
- imxrt1020-evk.dtb
+ imxrt1020-evk.dtb \
+ imxrt1170-evk.dtb \
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
new file mode 100644
index 00..88ff986ba0
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ clocks {
+ u-boot,dm-spl;
+ };
+
+ soc {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ { /* console */
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+
+ bank1: bank@0 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+
+ imxrt1170-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ u-boot,dm-spl;
+ };
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts
new file mode 100644
index 00..c2fd0c0392
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk.dts
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/dts-v1/;
+#include "imxrt1170.dtsi"
+#include "imxrt1170-evk-u-boot.dtsi"
+#include "imxrt1170-pinfunc.h"
+
+/ {
+ model = "NXP imxrt1170-evk board";
+ compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ tick-timer =
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x2024 0xf 0x8000 0x400>;
+
+ ocram: ocram@2024 {
+ device_type = "memory";
+ reg = <0x2024 0xf>;
+ };
+
+ sdram: sdram@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x400>;
+ };
+ };
+};
+
+ { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <_lpuart1>;
+ status = "okay";
+};
+
+ {
+ /*
+* Memory configuration from sdram datasheet IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0xd
+0x0
+0x8
+0x7
+
+0x0d
+0x0b
+0x00
+0x00
+
+0x00
+0x0A
+0x08
+0x09>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x8000>;
+ fsl,memory-size = ;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_lpuart1>;
+
+
[PATCH v2 8/8] ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig
Add a base defconfig for the i.MXRT1170 Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done --- configs/imxrt1170-evk_defconfig | 67 + include/configs/imxrt1170-evk.h | 37 ++ 2 files changed, 104 insertions(+) create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 include/configs/imxrt1170-evk.h diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig new file mode 100644 index 00..a8de8ad18e --- /dev/null +++ b/configs/imxrt1170-evk_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_ARCH_IMXRT=y +CONFIG_SYS_TEXT_BASE=0x2024 +CONFIG_SYS_MALLOC_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x8 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imxrt1170-evk" +CONFIG_SPL_TEXT_BASE=0x202C +CONFIG_TARGET_IMXRT1170_EVK=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SIZE_LIMIT=0x2 +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x202C +CONFIG_SD_BOOT=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 +# CONFIG_SPL_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_MII is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_OF_TRANSLATE is not set +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMXRT1170=y +CONFIG_CLK_IMXRT1170=y +# CONFIG_SPL_DM_GPIO is not set +CONFIG_MXC_GPIO=y +# CONFIG_INPUT is not set +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMXRT=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_IMXRT_SDRAM=y +CONFIG_FSL_LPUART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h new file mode 100644 index 00..4ebeffd255 --- /dev/null +++ b/include/configs/imxrt1170-evk.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#ifndef __IMXRT1170_EVK_H +#define __IMXRT1170_EVK_H + +#include + +#define CONFIG_SYS_INIT_SP_ADDR0x2034 + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC1351 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +#define PHYS_SDRAM 0x8000 +#define PHYS_SDRAM_SIZE(64 * 1024 * 1024) + +#define DMAMEM_SZ_ALL (1 * 1024 * 1024) +#define DMAMEM_BASE(PHYS_SDRAM + PHYS_SDRAM_SIZE - \ +DMAMEM_SZ_ALL) + +/* + * Configuration of the external SDRAM memory + */ + +/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_LEN 0x8000 +#define CONFIG_SYS_UBOOT_START 0x202403FD +#endif +/* For SPL ends */ + +#endif /* __IMXRT1170_EVK_H */ -- 2.36.1
[PATCH v2 2/8] ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header
Add binding header for i.MXRT1170 pinctrl device tree. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done --- arch/arm/dts/imxrt1170-pinfunc.h | 1561 ++ 1 file changed, 1561 insertions(+) create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h diff --git a/arch/arm/dts/imxrt1170-pinfunc.h b/arch/arm/dts/imxrt1170-pinfunc.h new file mode 100644 index 00..fba5483a08 --- /dev/null +++ b/arch/arm/dts/imxrt1170-pinfunc.h @@ -0,0 +1,1561 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * Author(s): Jesse Taube + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H + +#define IMX_PAD_SION 0x4000 + +/* + * The pin function ID is a tuple of + * + */ + +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX0x000 0x040 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_00_MIC_CLK0x000 0x040 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO000x000 0x040 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX0x004 0x044 0x080 0x0 0x0 +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO010x004 0x044 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO020x008 0x048 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE000x008 0x048 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE010x00C 0x04C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS00x00C 0x04C 0x094 0x1 0x0 +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO030x00C 0x04C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT0x010 0x050 0x0A0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO040x010 0x050 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO050x014 0x054 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 +#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3
[PATCH v2 6/8] RAM: Add changes for i.MXRT11xx series
The i.MXRT11 series has different offsets for IOCR_MUX, it also can
address 64MiB of SDRAM so add a macro for that.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Nothing done
---
drivers/ram/imxrt_sdram.c| 9 +
include/dt-bindings/memory/imxrt-sdram.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
index ca2eec767d..d0a88845cf 100644
--- a/drivers/ram/imxrt_sdram.c
+++ b/drivers/ram/imxrt_sdram.c
@@ -87,12 +87,21 @@ struct imxrt_semc_regs {
u32 sts[16];
};
+#if !defined(TARGET_IMXRT1170_EVK)
#define SEMC_IOCR_MUX_A8_SHIFT 0
#define SEMC_IOCR_MUX_CSX0_SHIFT 3
#define SEMC_IOCR_MUX_CSX1_SHIFT 6
#define SEMC_IOCR_MUX_CSX2_SHIFT 9
#define SEMC_IOCR_MUX_CSX3_SHIFT 12
#define SEMC_IOCR_MUX_RDY_SHIFT15
+#else
+#define SEMC_IOCR_MUX_A8_SHIFT 0
+#define SEMC_IOCR_MUX_CSX0_SHIFT 4
+#define SEMC_IOCR_MUX_CSX1_SHIFT 8
+#define SEMC_IOCR_MUX_CSX2_SHIFT 12
+#define SEMC_IOCR_MUX_CSX3_SHIFT 16
+#define SEMC_IOCR_MUX_RDY_SHIFT20
+#endif
struct imxrt_sdram_mux {
u8 a8;
diff --git a/include/dt-bindings/memory/imxrt-sdram.h
b/include/dt-bindings/memory/imxrt-sdram.h
index acb35bce27..4b3b0c2f50 100644
--- a/include/dt-bindings/memory/imxrt-sdram.h
+++ b/include/dt-bindings/memory/imxrt-sdram.h
@@ -82,6 +82,7 @@
#define MEM_WIDTH_8BITS0x0
#define MEM_WIDTH_16BITS 0x1
+#define MEM_WIDTH_32BITS 0x2
#define BL_1 0x0
#define BL_2 0x1
--
2.36.1
[PATCH v2 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver
Add clock driver support for i.MXRT1170.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Use C file not dts for constant clock divider
---
drivers/clk/imx/Kconfig | 16 +++
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-imxrt1170.c | 221
3 files changed, 238 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 04d252a1e0..abcb19ce6d 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -124,3 +124,19 @@ config CLK_IMXRT1050
select CLK_COMPOSITE_CCF
help
This enables support clock driver for i.MXRT1050 platforms.
+
+config SPL_CLK_IMXRT1170
+ bool "SPL clock support for i.MXRT1170"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MXRT1170.
+
+config CLK_IMXRT1170
+ bool "Clock support for i.MXRT1170"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1170 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index c5766901f2..b9c197f952 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o
clk-pll14xx.o \
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) += clk-imxrt1170.o
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
new file mode 100644
index 00..077dd1bf02
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static ulong imxrt1170_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1170_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1170_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1170_clk_disable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 0);
+}
+
+static int imxrt1170_clk_enable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 1);
+}
+
+static int imxrt1170_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, );
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
+static struct clk_ops imxrt1170_clk_ops = {
+ .set_rate = imxrt1170_clk_set_rate,
+ .get_rate = imxrt1170_clk_get_rate,
+ .enable = imxrt1170_clk_enable,
+ .disable = imxrt1170_clk_disable,
+ .set_parent = imxrt1170_clk_set_parent,
+};
+
+static const char * const lpuart1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3"};
+static const char * const gpt1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3"};
+static const char * const usdhc1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
+static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"};
+
+static int imxrt1170_clk_probe(struct udevice *dev)
+{
+ void *base;
+
+ /* Anatop clocks */
+ base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
"fsl,imxrt-anatop"));
+
+
+
+ clk_dm(IMXRT1170_CLK_RCOSC_48M,
+ imx_clk_fixed_factor("rcosc48M", "rcosc16M", 3, 1));
+ clk_dm(IMXRT1170_CLK_RCOSC_400M,
+ imx_clk_fixed_factor("rcosc400M", "rcosc16M", 25, 1));
+ clk_dm(IMXRT1170_CLK_RCOSC_48M_DIV2,
+
[PATCH v2 4/8] clk: imx: Add i.MXRT11xx pllv3 variant
The i.MXRT11 series has two new pll types but are variants of existing.
This patch adds the ability to read one of the pll types' frequency
as it can't be changed unlike the generic pll it also has the
division factors swapped.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Change BM_PLL_POWER and BM_PLL_LOCK bit to variable
* Use different lock and power bit for new pll
---
drivers/clk/imx/clk-pllv3.c | 56 +++--
drivers/clk/imx/clk.h | 1 +
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 077757efcb..fad306aeed 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -21,19 +21,23 @@
#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
+#define UBOOT_DM_CLK_IMX_PLLV3_GENV2 "imx_clk_pllv3_genericv2"
#define PLL_NUM_OFFSET 0x10
#define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12)
+#define BM_PLL_POWER_V2(0x1 << 21)
#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_LOCK(0x1 << 31)
+#define BM_PLL_LOCK_V2 (0x1 << 29)
struct clk_pllv3 {
struct clk clk;
void __iomem*base;
u32 power_bit;
boolpowerup_set;
+ u32 lock_bit;
u32 enable_bit;
u32 div_mask;
u32 div_shift;
@@ -42,6 +46,30 @@ struct clk_pllv3 {
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
+static ulong clk_pllv3_genericv2_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+
+ return (div == 0) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static ulong clk_pllv3_genericv2_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+ u32 val = (div == 0) ? parent_rate * 22 : parent_rate * 20;
+
+ if (rate == val)
+ return 0;
+
+ return -EINVAL;
+}
+
static ulong clk_pllv3_generic_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
@@ -71,7 +99,7 @@ static ulong clk_pllv3_generic_set_rate(struct clk *clk,
ulong rate)
writel(val, pll->base);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -120,6 +148,13 @@ static const struct clk_ops clk_pllv3_generic_ops = {
.set_rate = clk_pllv3_generic_set_rate,
};
+static const struct clk_ops clk_pllv3_genericv2_ops = {
+ .get_rate = clk_pllv3_genericv2_get_rate,
+ .enable = clk_pllv3_generic_enable,
+ .disable= clk_pllv3_generic_disable,
+ .set_rate = clk_pllv3_genericv2_set_rate,
+};
+
static ulong clk_pllv3_sys_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(clk);
@@ -153,7 +188,7 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong
rate)
writel(val, pll->base);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -221,7 +256,7 @@ static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong
rate)
writel(mfd, pll->base + PLL_DENOM_OFFSET);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -262,6 +297,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->power_bit = BM_PLL_POWER;
pll->enable_bit = BM_PLL_ENABLE;
+ pll->lock_bit = BM_PLL_LOCK;
switch (type) {
case IMX_PLLV3_GENERIC:
@@ -269,6 +305,13 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->div_shift = 0;
pll->powerup_set = false;
break;
+ case IMX_PLLV3_GENERICV2:
+ pll->power_bit = BM_PLL_POWER_V2;
+ pll->lock_bit = BM_PLL_LOCK_V2;
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENV2;
+ pll->div_shift = 0;
+ pll->powerup_set = false;
+ break;
case IMX_PLLV3_SYS:
drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
pll->div_shift = 0;
@@ -313,6 +356,13 @@ U_BOOT_DRIVER(clk_pllv3_generic) = {
.flags = DM_FLAG_PRE_RELOC,
};
[PATCH v2 3/8] dt-bindings: imx: Add clock binding for i.MXRT1170
Add the clock binding doc for i.MXRT1170. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done --- include/dt-bindings/clock/imxrt1170-clock.h | 48 + 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h diff --git a/include/dt-bindings/clock/imxrt1170-clock.h b/include/dt-bindings/clock/imxrt1170-clock.h new file mode 100644 index 00..8ab8018a15 --- /dev/null +++ b/include/dt-bindings/clock/imxrt1170-clock.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + */ + +#ifndef __DT_BINDINGS_CLOCK_IMXRT1170_H +#define __DT_BINDINGS_CLOCK_IMXRT1170_H + +#define IMXRT1170_CLK_DUMMY0 +#define IMXRT1170_CLK_OSC 1 +#define IMXRT1170_CLK_OSC_32K 2 +#define IMXRT1170_CLK_RCOSC_16M3 +#define IMXRT1170_CLK_RCOSC_48M4 +#define IMXRT1170_CLK_RCOSC_48M_DIV2 5 +#define IMXRT1170_CLK_RCOSC_400M 6 +#define IMXRT1170_CLK_PLL_ARM 7 +#define IMXRT1170_CLK_PLL_AUDIO8 +#define IMXRT1170_CLK_PLL_VIDEO9 +#define IMXRT1170_CLK_PLL1 10 +#define IMXRT1170_CLK_PLL1_DIV211 +#define IMXRT1170_CLK_PLL1_DIV512 +#define IMXRT1170_CLK_PLL2 13 +#define IMXRT1170_CLK_PLL2_PFD014 +#define IMXRT1170_CLK_PLL2_PFD115 +#define IMXRT1170_CLK_PLL2_PFD216 +#define IMXRT1170_CLK_PLL2_PFD317 +#define IMXRT1170_CLK_PLL3 18 +#define IMXRT1170_CLK_PLL3_DIV219 +#define IMXRT1170_CLK_PLL3_PFD020 +#define IMXRT1170_CLK_PLL3_PFD121 +#define IMXRT1170_CLK_PLL3_PFD222 +#define IMXRT1170_CLK_PLL3_PFD323 +#define IMXRT1170_CLK_M7 24 +#define IMXRT1170_CLK_M4 25 +#define IMXRT1170_CLK_BUS 26 +#define IMXRT1170_CLK_BUS_LPSR 27 +#define IMXRT1170_CLK_LPUART1_SEL 28 +#define IMXRT1170_CLK_LPUART1 29 +#define IMXRT1170_CLK_USDHC1_SEL 30 +#define IMXRT1170_CLK_USDHC1 31 +#define IMXRT1170_CLK_GPT1_SEL 32 +#define IMXRT1170_CLK_GPT1 33 +#define IMXRT1170_CLK_SEMC_SEL 34 +#define IMXRT1170_CLK_SEMC 35 +#define IMXRT1170_CLK_END 36 + +#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */ -- 2.36.1
[PATCH v2 1/8] imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK
This commit adds board support for i.MXRT1170-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT117x processor family. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done --- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/mach-imx/imxrt/Kconfig | 9 +++ arch/arm/mach-imx/imxrt/soc.c | 2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS | 7 ++ board/freescale/imxrt1170-evk/Makefile| 6 ++ board/freescale/imxrt1170-evk/imximage.cfg| 32 board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 +++ 8 files changed, 159 insertions(+) create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 4f63803765..09767be1ca 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -56,6 +56,7 @@ #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ +#define MXC_CPU_IMXRT1170 0xBA /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index 8c89133965..c1d6b09e77 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -12,6 +12,10 @@ config IMXRT1050 bool select IMXRT +config IMXRT1170 + bool + select IMXRT + config SYS_SOC default "imxrt" @@ -27,9 +31,14 @@ config TARGET_IMXRT1050_EVK bool "Support imxrt1050 EVK board" select IMXRT1050 +config TARGET_IMXRT1170_EVK + bool "Support imxrt1170 EVK board" + select IMXRT1170 + endchoice source "board/freescale/imxrt1020-evk/Kconfig" source "board/freescale/imxrt1050-evk/Kconfig" +source "board/freescale/imxrt1170-evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index ba015992ee..34162a3976 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -43,6 +43,8 @@ u32 get_cpu_rev(void) return MXC_CPU_IMXRT1020 << 12; #elif defined(CONFIG_IMXRT1050) return MXC_CPU_IMXRT1050 << 12; +#elif defined(CONFIG_IMXRT1170) + return MXC_CPU_IMXRT1170 << 12; #else #error This IMXRT SoC is not supported #endif diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig new file mode 100644 index 00..c61fc57971 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Kconfig @@ -0,0 +1,22 @@ +if TARGET_IMXRT1170_EVK + +config SYS_BOARD + string + default "imxrt1170-evk" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "imxrt1170" + +config SYS_CONFIG_NAME + string + default "imxrt1170-evk" + +config IMX_CONFIG + default "board/freescale/imxrt1170-evk/imximage.cfg" + +endif diff --git a/board/freescale/imxrt1170-evk/MAINTAINERS b/board/freescale/imxrt1170-evk/MAINTAINERS new file mode 100644 index 00..1fc3179c00 --- /dev/null +++ b/board/freescale/imxrt1170-evk/MAINTAINERS @@ -0,0 +1,7 @@ +IMXRT1170 EVALUATION KIT +M: Giulio Benetti +M: Jesse Taube +S: Maintained +F: board/freescale/imxrt1170-evk +F: include/configs/imxrt1170-evk.h +F: configs/imxrt1170-evk_defconfig diff --git a/board/freescale/imxrt1170-evk/Makefile b/board/freescale/imxrt1170-evk/Makefile new file mode 100644 index 00..857a168b09 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# Author(s): Giulio Benetti + +obj-y := imxrt1170-evk.o diff --git a/board/freescale/imxrt1170-evk/imximage.cfg b/board/freescale/imxrt1170-evk/imximage.cfg new file mode 100644 index 00..3354672825 --- /dev/null +++ b/board/freescale/imxrt1170-evk/imximage.cfg @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ diff --git a/board/freescale/imxrt1170-evk/imxrt1170-evk.c
[PATCH v2 0/8] Add support for the i.MXRT1170
This patchset contains: - i.MXRT1170 clock driver adaption - i.MXRT1170-evk basic support Jesse Taube (8): imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header dt-bindings: imx: Add clock binding for i.MXRT1170 clk: imx: Add i.MXRT11xx pllv3 variant clk: imx: Add initial support for i.MXRT1170 clock driver RAM: Add changes for i.MXRT11xx series ARM: dts: imx: add i.MXRT1170-EVK support ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig arch/arm/dts/Makefile |3 +- arch/arm/dts/imxrt1170-evk-u-boot.dtsi| 94 + arch/arm/dts/imxrt1170-evk.dts| 250 +++ arch/arm/dts/imxrt1170-pinfunc.h | 1561 + arch/arm/dts/imxrt1170.dtsi | 257 +++ arch/arm/include/asm/arch-imx/cpu.h |1 + arch/arm/mach-imx/imxrt/Kconfig |9 + arch/arm/mach-imx/imxrt/soc.c |2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS |7 + board/freescale/imxrt1170-evk/Makefile|6 + board/freescale/imxrt1170-evk/imximage.cfg| 32 + board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 + configs/imxrt1170-evk_defconfig | 67 + drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile |1 + drivers/clk/imx/clk-imxrt1170.c | 221 +++ drivers/clk/imx/clk-pllv3.c | 56 +- drivers/clk/imx/clk.h |1 + drivers/ram/imxrt_sdram.c |9 + include/configs/imxrt1170-evk.h | 37 + include/dt-bindings/clock/imxrt1170-clock.h | 48 + include/dt-bindings/memory/imxrt-sdram.h |1 + 23 files changed, 2777 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h create mode 100644 arch/arm/dts/imxrt1170.dtsi create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1170.c create mode 100644 include/configs/imxrt1170-evk.h create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h -- 2.36.1
[PATCH v4 3/3] drivers: rng: optee_rng: register to CONFIG_OPTEE_SERVICE_DISCOVERY
Changes optee_rng driver to register itself has a OP-TEE service so
that a device is bound for the driver when OP-TEE enumerates the
PTA RNG service.
Cc: Sughosh Ganu
Cc: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
Changes since v3:
- Unconditionally register driver with OPTEE_SERVICE_DRIVER() since the
macro is now stubbed when CONFIG_OPTEE_SERVICE_DISCOVERY is disable.
No change since v2.
No change since v1.
---
drivers/rng/Kconfig | 1 +
drivers/rng/optee_rng.c | 7 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index c10f7d345b..14e95a6213 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -34,6 +34,7 @@ config RNG_MSM
config RNG_OPTEE
bool "OP-TEE based Random Number Generator support"
depends on DM_RNG && OPTEE
+ default y if OPTEE_SERVICE_DISCOVERY
help
This driver provides support for the OP-TEE based Random Number
Generator on ARM SoCs where hardware entropy sources are not
diff --git a/drivers/rng/optee_rng.c b/drivers/rng/optee_rng.c
index aa8ce864d3..410dfc053f 100644
--- a/drivers/rng/optee_rng.c
+++ b/drivers/rng/optee_rng.c
@@ -11,6 +11,9 @@
#include
#include
#include
+#include
+
+#define DRIVER_NAME"optee-rng"
#define TEE_ERROR_HEALTH_TEST_FAIL 0x0001
@@ -35,6 +38,8 @@
#define TA_HWRNG_UUID { 0xab7a617c, 0xb8e7, 0x4d8f, \
{ 0x83, 0x01, 0xd0, 0x9b, 0x61, 0x03, 0x6b, 0x64 } }
+OPTEE_SERVICE_DRIVER(optee_rng, TA_HWRNG_UUID, DRIVER_NAME);
+
/** open_session_ta_hwrng() - Open session with hwrng Trusted App
*
* @dev: device
@@ -177,7 +182,7 @@ static const struct dm_rng_ops optee_rng_ops = {
};
U_BOOT_DRIVER(optee_rng) = {
- .name = "optee-rng",
+ .name = DRIVER_NAME,
.id = UCLASS_RNG,
.ops = _rng_ops,
.probe = optee_rng_probe,
--
2.25.1
[PATCH v4 2/3] drivers: tee: optee: discover OP-TEE services
This change defines resources for OP-TEE service drivers to register
themselves for being bound to when OP-TEE firmware reports the related
service is supported. OP-TEE services are discovered during optee
driver probe sequence which mandates optee driver is always probe once
bound.
Discovery of optee services and binding to related U-Boot drivers is
embedded upon configuration switch CONFIG_OPTEE_SERVICE_DISCOVERY.
Cc: Jens Wiklander
Cc: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
Changes since v3:
- Stub OPTEE_SERVICE_DRIVER() macro when CONFIG_OPTEE_SERVICE_DISCOVERY
is disable.
Changes since v2:
- Release allocated shared memory from bind_service_drivers() only.
- Remove definition of useless macro OPTEE_SERVICE_DRIVER_GET().
Changes since v1:
- Remove all #ifdef CONFIG_OPTEE_SERVICE_DISCOVERY directives and replace
with if (IS_ENABLED()) where applicable.
- Incidentally rename local function open_session() to open_enum_session()
and remove local function close_session() for clarity.
- Update commit log to highlight that "optee driver is always probe once
bound" when CONFIG_OPTEE_SERVICE_DISCOVERY is enable.
---
drivers/tee/optee/Kconfig | 8 ++
drivers/tee/optee/core.c| 171 ++--
include/tee/optee_service.h | 34 +++
3 files changed, 208 insertions(+), 5 deletions(-)
create mode 100644 include/tee/optee_service.h
diff --git a/drivers/tee/optee/Kconfig b/drivers/tee/optee/Kconfig
index d03028070b..9dc65b0501 100644
--- a/drivers/tee/optee/Kconfig
+++ b/drivers/tee/optee/Kconfig
@@ -37,6 +37,14 @@ config OPTEE_TA_SCP03
help
Enables support for controlling (enabling, provisioning) the
Secure Channel Protocol 03 operation in the OP-TEE SCP03 TA.
+
+config OPTEE_SERVICE_DISCOVERY
+ bool "OP-TEE service discovery"
+ default y
+ help
+ This implements automated driver binding of OP-TEE service drivers by
+ requesting OP-TEE firmware to enumerate its hosted services.
+
endmenu
endif
diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
index c1f5fc4c7a..41fa615b35 100644
--- a/drivers/tee/optee/core.c
+++ b/drivers/tee/optee/core.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include "optee_smc.h"
#include "optee_msg.h"
@@ -22,6 +23,25 @@
#define PAGELIST_ENTRIES_PER_PAGE \
((OPTEE_MSG_NONCONTIG_PAGE_SIZE / sizeof(u64)) - 1)
+/*
+ * PTA_DEVICE_ENUM interface exposed by OP-TEE to discover enumerated services
+ */
+#define PTA_DEVICE_ENUM{ 0x7011a688, 0xddde, 0x4053, \
+ { 0xa5, 0xa9, 0x7b, 0x3c, 0x4d, 0xdf, 0x13,
0xb8 } }
+/*
+ * PTA_CMD_GET_DEVICES - List services without supplicant dependencies
+ *
+ * [out]memref[0]: List of the UUIDs of service enumerated by OP-TEE
+ */
+#define PTA_CMD_GET_DEVICES0x0
+
+/*
+ * PTA_CMD_GET_DEVICES_SUPP - List services depending on tee supplicant
+ *
+ * [out]memref[0]: List of the UUIDs of service enumerated by OP-TEE
+ */
+#define PTA_CMD_GET_DEVICES_SUPP 0x1
+
typedef void (optee_invoke_fn)(unsigned long, unsigned long, unsigned long,
unsigned long, unsigned long, unsigned long,
unsigned long, unsigned long,
@@ -42,6 +62,134 @@ struct rpc_param {
u32 a7;
};
+static struct optee_service *find_service_driver(const struct
tee_optee_ta_uuid *uuid)
+{
+ struct optee_service *service;
+ u8 loc_uuid[TEE_UUID_LEN];
+ size_t service_cnt, idx;
+
+ service_cnt = ll_entry_count(struct optee_service, optee_service);
+ service = ll_entry_start(struct optee_service, optee_service);
+
+ for (idx = 0; idx < service_cnt; idx++, service++) {
+ tee_optee_ta_uuid_to_octets(loc_uuid, >uuid);
+ if (!memcmp(uuid, loc_uuid, sizeof(uuid)))
+ return service;
+ }
+
+ return NULL;
+}
+
+static int bind_service_list(struct udevice *dev, struct tee_shm
*service_list, size_t count)
+{
+ const struct tee_optee_ta_uuid *service_uuid = (const void
*)service_list->addr;
+ struct optee_service *service;
+ size_t idx;
+ int ret;
+
+ for (idx = 0; idx < count; idx++) {
+ service = find_service_driver(service_uuid + idx);
+ if (!service)
+ continue;
+
+ ret = device_bind_driver(dev, service->driver_name,
service->driver_name, NULL);
+ if (ret) {
+ dev_warn(dev, "%s was not bound: %d, ignored\n",
service->driver_name, ret);
+ continue;
+ }
+ }
+
+ return 0;
+}
+
+static int __enum_services(struct udevice *dev, struct tee_shm *shm, u32
*shm_size, u32 tee_sess)
+{
+ struct tee_invoke_arg arg = { };
+ struct tee_param param = { };
+ int ret = 0;
+
+ arg.func = PTA_CMD_GET_DEVICES;
+
[PATCH v4 1/3] drivers: tee: optee: remove unused probe local variable
Removes local variable child in optee_probe() that is not used.
Cc: Patrick Delaunay
Reviewed-by: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
Changes since v3:
- Applied Patrick's R-b tag.
No change since v2.
New change not in v1 series.
---
drivers/tee/optee/core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
index a89d62aaf0..c1f5fc4c7a 100644
--- a/drivers/tee/optee/core.c
+++ b/drivers/tee/optee/core.c
@@ -642,7 +642,6 @@ static int optee_probe(struct udevice *dev)
{
struct optee_pdata *pdata = dev_get_plat(dev);
u32 sec_caps;
- struct udevice *child;
int ret;
if (!is_optee_api(pdata->invoke_fn)) {
@@ -673,7 +672,7 @@ static int optee_probe(struct udevice *dev)
* only bind the drivers associated to the supported OP-TEE TA
*/
if (IS_ENABLED(CONFIG_RNG_OPTEE)) {
- ret = device_bind_driver(dev, "optee-rng", "optee-rng", );
+ ret = device_bind_driver(dev, "optee-rng", "optee-rng", NULL);
if (ret)
return ret;
}
--
2.25.1
Re: Re: [Rock Pi 4+] Mainline LPDDR4 RAM initialisation is not sufficient to boot successfully
Could you help us to get the DRAM part number which initialization failures on
the Rock Pi 4+.
We have found that some LPDDR4 abnormal operation at 50MHz.
I think you can try that use 400MHz to detect capacity.
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index c0a06dcaed..810f9a98c9 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -2538,24 +2538,42 @@ static int lpddr4_set_ctl(struct dram_info *dram,
return 0;
}
-static int lpddr4_set_rate(struct dram_info *dram,
+static int lpddr4_set_rate_0(struct dram_info *dram,
struct rk3399_sdram_params *params)
{
- u32 ctl_fn;
+ u32 ctl_fn = 0;
u32 phy_fn;
- for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) {
- phy_fn = lpddr4_get_phy_fn(params, ctl_fn);
+ phy_fn = lpddr4_get_phy_fn(params, ctl_fn);
- lpddr4_set_phy(dram, params, phy_fn, _cfgs_lpddr4[ctl_fn]);
- lpddr4_set_ctl(dram, params, ctl_fn,
- dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
+ lpddr4_set_phy(dram, params, phy_fn, _cfgs_lpddr4[ctl_fn]);
+ lpddr4_set_ctl(dram, params, ctl_fn,
+ dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
- if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
- printf("%s: change freq to %d mhz %d, %d\n", __func__,
- dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq,
- ctl_fn, phy_fn);
- }
+ if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
+ printf("%s: change freq to %d mhz %d, %d\n", __func__,
+ dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq,
+ ctl_fn, phy_fn);
+
+ return 0;
+}
+
+static int lpddr4_set_rate_1(struct dram_info *dram,
+ struct rk3399_sdram_params *params)
+{
+ u32 ctl_fn = 1;
+ u32 phy_fn;
+
+ phy_fn = lpddr4_get_phy_fn(params, ctl_fn);
+
+ lpddr4_set_phy(dram, params, phy_fn, _cfgs_lpddr4[ctl_fn]);
+ lpddr4_set_ctl(dram, params, ctl_fn,
+ dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
+
+ if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
+ printf("%s: change freq to %d mhz %d, %d\n", __func__,
+ dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq,
+ ctl_fn, phy_fn);
return 0;
}
@@ -2955,6 +2973,11 @@ static int sdram_init(struct dram_info *dram,
params->ch[ch].cap_info.rank = rank;
}
+ #if defined(CONFIG_RAM_RK3399_LPDDR4)
+ lpddr4_set_rate_0(dram, params);
+ params->base.ddr_freq = dfs_cfgs_lpddr4[0].base.ddr_freq / MHz;
+ #endif
+
params->base.num_channels = 0;
for (channel = 0; channel < 2; channel++) {
const struct chan_info *chan = >chan[channel];
@@ -3058,7 +3081,7 @@ static const struct sdram_rk3399_ops rk3399_ops = {
.get_phy_index_params = get_phy_index_params,
#else
.data_training_first = lpddr4_mr_detect,
- .set_rate_index = lpddr4_set_rate,
+ .set_rate_index = lpddr4_set_rate_1,
.modify_param = lpddr4_modify_param,
.get_phy_index_params = lpddr4_get_phy_index_params,
#endif
From: Lee Jones
Date: 2022-06-17 03:15
To: u-boot; linux-rockchip
CC: wxt; kever.yang; zhangqing; derrick.huang; chenjh; hisping.lin; typ; cwz;
chenfen; jagan; sjg; cym; pgwipeout; adelva; rammuthiah
Subject: Re: [Rock Pi 4+] Mainline LPDDR4 RAM initialisation is not sufficient
to boot successfully
On Wed, 25 May 2022, Lee Jones wrote:
> Good afternoon,
>
>
>
> There appear to be a number of issues with the Rockchip rk3399 DDR RAM
>
> initialisation sequence in Mainline. Specifically, I'm seeing
>
> consistent failures on the Rock Pi 4+ during early boot.
Can anyone from Rockchip help with this please?
What does the binary blob [0] do differently to the U-boot
implementation.
Are you able to publish the source for the DDR binary blob?
Please help me fix U-boot.
[0]
https://github.com/rockchip-linux/rkbin/blob/master/bin/rk33/rk3399_ddr_933MHz_v1.25.bin
> A typical failure looks something like this:
>
>
>
> U-Boot TPL 2022.07-rc3-5-g1b04a961c6 (May 25 2022 - 11:09:19)
>
> Channel 0: LPDDR4, 50MHz
>
> BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
>
> Channel 1: col error
>
> Cap error!
>
> 256B stride
>
> lpddr4_set_rate: change freq to 4 mhz 0, 1
>
> lpddr4_set_rate: change freq to 8 mhz 1, 0
>
> Trying to boot from BOOTROM
>
> Returning to boot ROM...
Re: [RFC PATCH v4 00/28] Modernize U-Boot shell
On Fri, Jun 17, 2022 at 12:31:30AM +0200, Francis Laniel wrote: > Hi. > > > First I hope you are fine and the same for your relatives. > > During 2021 summer, Sean Anderson wrote a contribution to add a new shell, > based > on LIL, to U-Boot [1][2]. > While one of the goals of this contribution was to address the fact actual > U-Boot shell, which is based on Busybox hush, is old there was a discussion > about adding a new shell versus updating the actual one [3][4]. > > So, in this series, with Harald Seiler, we updated the actual U-Boot shell to > reflect what is currently in Busybox source code. > Basically, this contribution is about taking a snapshot of Busybox > shell/hush.c > file (as it exists in commit 37460f5da) and adapt it to suit U-Boot needs. > > This contribution was written to be as backward-compatible as possible to > avoid > breaking the existing. > So, the 2021 hush flavor offers the same as the actual, that is to say: > 1. Variable expansion. > 2. Instruction lists (;, && and ||). > 3. If, then and else. > 4. Loops (for, while and until). > No new features offered by Busybox hush were implemented (e.g. functions). > > It is possible to change the parser at runtime using the "parser" command: > => parser print > old > => parser set 2021 > 2021> parser print > 2021 > 2021> parser set old > => > The default parser is the old one. > > In terms of testing, new unit tests were added to ut to ensure the new > behavior > is the same as the old one and it does not add regression. > Nonetheless, if old behavior was buggy and fixed upstream, the fix is then > added > to U-Boot [5]. > In sandbox, all of these tests pass smoothly: > => printenv board > board=sandbox > => ut hush > Running 20 hush tests > ... > Failures: 0 > => parser set 2021 > 2021> ut hush > Running 20 hush tests > ... > Failures: 0 > > Thanks to the effort of Harald Seiler, I was successful booting a board: > 2021> printenv board_rev > board_rev=iMX8MP > 2021> boot > ... > root@iMX8MPboard:~# fw_printenv board_rev > board_rev=iMX8MP > > I also tested another board where both parser were successful to boot it: > => printenv fdtfile > fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb > => boot > ... > root@lepotato:~# > root@lepotato:~# reboot > ... > => parser set 2021 > 2021> printenv fdtfile > fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb > 2021> boot > ... > root@lepotato:~# > > Sadly, I was not able to have the CI passes smoothly... > To pass it and be aware of all the troubles, I added the 3 last commits as > "trick" commits. I've replied to those now. And generally I just want to say I'm very happy with the progress here in v3->v4. -- Tom signature.asc Description: PGP signature
Re: [RFC PATCH v4 27/28] for test purpose only: Comment out failed function which fails only in CI.
On Fri, Jun 17, 2022 at 12:31:57AM +0200, Francis Laniel wrote:
> Signed-off-by: Francis Laniel
> ---
> test/cmd/setexpr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c
> index 0dc94f7e61..71c751d766 100644
> --- a/test/cmd/setexpr.c
> +++ b/test/cmd/setexpr.c
> @@ -308,7 +308,7 @@ static int setexpr_test_str(struct unit_test_state *uts)
> start_mem = ut_check_free();
> ut_assertok(run_command("setexpr.s fred *0", 0));
> ut_asserteq_str("hello", env_get("fred"));
> - ut_assertok(ut_check_delta(start_mem));
> +// ut_assertok(ut_check_delta(start_mem));
>
> unmap_sysmem(buf);
Did you see doc/develop/tests_sandbox.rst and how to get things under
gdb, or did you have problems with that? Thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [RFC PATCH v4 28/28] board: keymile: common: Use environment to store IVM_* variables.
On Fri, Jun 17, 2022 at 12:31:58AM +0200, Francis Laniel wrote:
> These boards used set_local_var() to store some variables as local shell.
> They then used get_local_var() to retrieve the variables values.
>
> Instead of using local shell variables, they should use environment ones
> (like a
> majority of board).
> So, this patch converts using local variables to environment ones.
>
> Signed-off-by: Francis Laniel
> ---
> board/keymile/common/common.c | 8
> board/keymile/common/ivm.c| 9 +
> 2 files changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
> index 3999f48719..72939af36e 100644
> --- a/board/keymile/common/common.c
> +++ b/board/keymile/common/common.c
> @@ -219,7 +219,7 @@ static int do_setboardid(struct cmd_tbl *cmdtp, int flag,
> int argc,
> unsigned char buf[32];
> char *p;
>
> - p = get_local_var("IVM_BoardId");
> + p = env_get("IVM_BoardId");
> if (!p) {
> printf("can't get the IVM_Boardid\n");
> return 1;
> @@ -228,7 +228,7 @@ static int do_setboardid(struct cmd_tbl *cmdtp, int flag,
> int argc,
> env_set("boardid", (char *)buf);
> printf("set boardid=%s\n", buf);
>
> - p = get_local_var("IVM_HWKey");
> + p = env_get("IVM_HWKey");
> if (!p) {
> printf("can't get the IVM_HWKey\n");
> return 1;
> @@ -272,14 +272,14 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp,
> int flag, int argc,
>* first read out the real inventory values, these values are
>* already stored in the local hush variables
>*/
> - p = get_local_var("IVM_BoardId");
> + p = env_get("IVM_BoardId");
> if (!p) {
> printf("can't get the IVM_Boardid\n");
> return 1;
> }
> rc = strict_strtoul(p, 16, );
>
> - p = get_local_var("IVM_HWKey");
> + p = env_get("IVM_HWKey");
> if (!p) {
> printf("can't get the IVM_HWKey\n");
> return 1;
> diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
> index 67db0c50f4..e266d7ce81 100644
> --- a/board/keymile/common/ivm.c
> +++ b/board/keymile/common/ivm.c
> @@ -44,14 +44,7 @@ static int ivm_calc_crc(unsigned char *buf, int len)
>
> static int ivm_set_value(char *name, char *value)
> {
> - char tempbuf[256];
> -
> - if (value) {
> - sprintf(tempbuf, "%s=%s", name, value);
> - return set_local_var(tempbuf, 0);
> - }
> - unset_local_var(name);
> - return 0;
> + return env_set(name, value);
> }
>
> static int ivm_get_value(unsigned char *buf, int len, char *name, int off,
Adding in the maintainer, but seems reasonable to me.
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v10 00/13] fpga: zynqmp: Adding support of loading authenticated images
Hi Oleksandr, Thank you for the follow-up. I took the chance to test this patchset in the actual hardware. I focused on the encrypted bitfiles (not authenticated) and I confirm it works. Regads, Adrian On 12.06.2022 00:06, Oleksandr Suvorov wrote: This patchset introduces support for the authenticated and encrypted FPGA images on ZynqMP boards, besides that introducing common way to pass the compatible property to any fpga driver. It bases on the initial work by Jorge Ramirez-Ortiz https://patchwork.ozlabs.org/project/uboot/patch/20211015091506.2602-1-jo...@foundries.io/ https://patchwork.ozlabs.org/project/uboot/patch/20211005111324.19749-3-jo...@foundries.io/ Changes in v10: - move FPGA flags to macros; - initialize xilinx_desc structs directly, removing *_DESC macros; - initialize flags for mach-zynq; - fix mixed types of return value; - made the message about ignoring legacy compatibe option as debug - fix grammar; - Support DDR images only if FPGA_LOAD_SECURE enabled. - Support ENC images only if FPGA_LOAD_SECURE enabled. Changes in v9: - remove an alien commit from a patchset :) Changes in v8: - Michal Simek's suggestions addressed: -- introduce the compatible flags in xilinx_desc; -- pass a binary compatible flag instead of "compatible" property to an FPGA driver. - Optimize a zynqmp_load() function. Changes in v7: - apply Michal Simek's suggestions As I applied changes on Oleksandr's patches, I indicated it by specifying myself as co-author in the commits logs. I am not sure if that is the convention of marking it. Changes in v6: - add support for the encrypted bitfiles. Changes in v5: - replace ifdef with if() where it's possible. Changes in v4: - change interface to xilinx_desc->operations->open() callback. - fix a bug from previous version of the patchset in dereferencing of a parent fpga_desc structure. Changes in v3: - remove the patch which introduced CMD_SPL_FPGA_LOAD_SECURE. - fix mixing definitions/declarations. - replace strcmp() calls with more secure strncmp(). - document the "u-boot,zynqmp-fpga-ddrauth" compatible string. - fix code style by check-patch recommendations. Changes in v2: - add function fit_fpga_load() to simplify calls of fpga_load() from contexts without a compatible attribute. - move all ZynqMP-specific logic to drivers/fpga/zynqmppl.c - prepare for passing a "compatible" FDT property to any fpga driver. Adrian Fiergolski (1): fpga: zynqmp: support loading encrypted bitfiles Oleksandr Suvorov (12): fpga: add option for loading FPGA secure bitstreams fpga: xilinx: add missed identifier names fpga: xilinx: add bitstream flags to driver desc fpga: zynqmp: add str2flags call fpga: add fpga_compatible2flag fpga: xilinx: pass compatible flags to xilinx_load() fpga: pass compatible flags to fpga_load() spl: fit: pass real compatible flags to fpga_load() fpga: xilinx: pass compatible flags to load() callback fpga: zynqmp: optimize zynqmppl_load() code fpga: zynqmp: add bitstream compatible checking fpga: zynqmp: support loading authenticated images arch/arm/mach-zynq/cpu.c | 1 + board/xilinx/versal/board.c | 5 +- board/xilinx/zynqmp/zynqmp.c | 5 +- boot/Kconfig | 4 +- boot/image-board.c| 4 +- cmd/Kconfig | 3 +- cmd/fpga.c| 8 +-- common/spl/spl_fit.c | 16 +++-- doc/uImage.FIT/source_file_format.txt | 7 +- drivers/fpga/Kconfig | 14 drivers/fpga/fpga.c | 31 - drivers/fpga/spartan2.c | 2 +- drivers/fpga/spartan3.c | 2 +- drivers/fpga/versalpl.c | 2 +- drivers/fpga/virtex2.c| 2 +- drivers/fpga/xilinx.c | 8 +-- drivers/fpga/zynqmppl.c | 96 ++- drivers/fpga/zynqpl.c | 2 +- include/fpga.h| 4 +- include/versalpl.h| 3 - include/xilinx.h | 19 -- include/zynqmppl.h| 9 ++- 22 files changed, 191 insertions(+), 56 deletions(-)
Re: [PATCH v3 3/3] drivers: rng: optee_rng: register to CONFIG_OPTEE_SERVICE_DISCOVERY
Hi Patrick,
On Fri, 17 Jun 2022 at 14:06, Patrick DELAUNAY
wrote:
>
> Hi,
>
> a minor remark
>
> On 6/7/22 12:21, Etienne Carriere wrote:
> > Changes optee_rng driver to register itself has a OP-TEE service so
> > that a device is bound for the driver when OP-TEE enumerates the
> > PTA RNG service.
> >
> > Cc: Sughosh Ganu
> > Cc: Patrick Delaunay
> > Signed-off-by: Etienne Carriere
> > ---
> > No change since v2.
> >
> > No change since v1.
> > ---
> > drivers/rng/Kconfig | 1 +
> > drivers/rng/optee_rng.c | 12 +++-
> > 2 files changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
> > index c10f7d345b..14e95a6213 100644
> > --- a/drivers/rng/Kconfig
> > +++ b/drivers/rng/Kconfig
> > @@ -34,6 +34,7 @@ config RNG_MSM
> > config RNG_OPTEE
> > bool "OP-TEE based Random Number Generator support"
> > depends on DM_RNG && OPTEE
> > + default y if OPTEE_SERVICE_DISCOVERY
> > help
> > This driver provides support for the OP-TEE based Random Number
> > Generator on ARM SoCs where hardware entropy sources are not
> > diff --git a/drivers/rng/optee_rng.c b/drivers/rng/optee_rng.c
> > index aa8ce864d3..90d9434395 100644
> > --- a/drivers/rng/optee_rng.c
> > +++ b/drivers/rng/optee_rng.c
> > @@ -11,6 +11,9 @@
> > #include
> > #include
> > #include
> >
> >
> > a minor remark
> >
> > +#include
> > +
> > +#define DRIVER_NAME "optee-rng"
> >
> > #define TEE_ERROR_HEALTH_TEST_FAIL 0x0001
> >
> > @@ -35,6 +38,13 @@
> > #define TA_HWRNG_UUID { 0xab7a617c, 0xb8e7, 0x4d8f, \
> > { 0x83, 0x01, 0xd0, 0x9b, 0x61, 0x03, 0x6b, 0x64 } }
> >
> > +#ifdef CONFIG_OPTEE_SERVICE_DISCOVERY
> > +OPTEE_SERVICE_DRIVER(optee_rng) = {
> > + .uuid = TA_HWRNG_UUID,
> > + .driver_name = DRIVER_NAME,
> > +};
> > +#endif
> > +
>
> a minor remark
>
> I think '#ifdef CONFIG_OPTEE_SERVICE_DISCOVERY'
>
> can avoid here with the macro call:
>
> + OPTEE_SERVICE_DRIVER(optee_rng, TA_HWRNG_UUID, DRIVER_NAME);
>
> and a modified macro in patch 2:
>
> +#ifdef CONFIG_OPTEE_SERVICE_DISCOVERY
> +#define OPTEE_SERVICE_DRIVER(__name, __uuid, __drv_name) \
> +ll_entry_declare(struct optee_service, __name, optee_service) = {\
> +.uuid = __uuid,\
> +.driver_name = __drv_name}
> +#else
> +#define OPTEE_SERVICE_DRIVER(__name, __uuid, __drv_name)
> +#endif
>
Makes sense and the driver code would look better without this #ifdef.
I'll send a v4.
Best regards,
Etienne
>
> This code is inspired by
>
> include/image.h:1575
>
> #defineU_BOOT_FIT_LOADABLE_HANDLER(_type, _handler) \
> ll_entry_declare(struct fit_loadable_tbl, _function, fit_loadable) ={ \
> .type =_type, \
> .handler =_handler, \
> }
>
> or also include/env.h:55
>
> /*
> * Define a callback that can be associated with variables.
> * when associated through the ".callbacks" environment variable, the
> callback
> * will be executed any time the variable is inserted, overwritten, or
> deleted.
> *
> * For SPL these are silently dropped to reduce code size, since
> environment
> * callbacks are not supported with SPL.
> */
> #ifdef CONFIG_SPL_BUILD
> #define U_BOOT_ENV_CALLBACK(name, callback) \
> static inline __maybe_unused void _u_boot_env_noop_##name(void) \
> { \
> (void)callback; \
> }
> #else
> #define U_BOOT_ENV_CALLBACK(name, callback) \
> ll_entry_declare(struct env_clbk_tbl, name, env_clbk) = \
> {#name, callback}
> #endif
>
>
> > /** open_session_ta_hwrng() - Open session with hwrng Trusted App
> >*
> >* @dev:device
> > @@ -177,7 +187,7 @@ static const struct dm_rng_ops optee_rng_ops = {
> > };
> >
> > U_BOOT_DRIVER(optee_rng) = {
> > - .name = "optee-rng",
> > + .name = DRIVER_NAME,
> > .id = UCLASS_RNG,
> > .ops = _rng_ops,
> > .probe = optee_rng_probe,
>
>
> Regards
>
Re: [RFC PATCH v4 26/28] for test purpose only: Comment out dollar tests which prints error messages.
On Fri, Jun 17, 2022 at 12:31:56AM +0200, Francis Laniel wrote: > Error messages like "unknown command" will make the CI fails. > So, for the moment, we comment these tests. > > Signed-off-by: Francis Laniel Why don't we have the test expect "unknown command" as the output here, when on the newer shell? Or if both shells print that now, in both cases? We want tests for when things are expected to fail. -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 20/23] FWU: synquacer: Generate dfu_alt_info from devicetree partition
On 6/9/22 14:30, Sughosh Ganu wrote:
From: Masami Hiramatsu
Generate dfu_alt_info from the partition uuid information in the
devicetree, and record the mapping of partition uuid and the
index of dfu_alt_num.
This could be a reference implementation of the automatic DFU
generation for FWU multi-bank update for non GPT firmware
platforms.
Signed-off-by: Masami Hiramatsu
Signed-off-by: Sughosh Ganu
---
.../synquacer-sc2a11-developerbox-u-boot.dtsi | 3 +
board/socionext/developerbox/Kconfig | 1 +
board/socionext/developerbox/fwu_plat.c | 79
include/configs/synquacer.h | 6 +-
include/fwu.h | 6 +
lib/fwu_updates/Makefile | 1 +
lib/fwu_updates/fwu_mtd.c | 173 ++
7 files changed, 221 insertions(+), 48 deletions(-)
create mode 100644 lib/fwu_updates/fwu_mtd.c
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
index ab4e3d1c2b..c7ec8a0321 100644
--- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -36,6 +36,7 @@
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
+ uuid = "17e86d77-41f9-4fd7-87ec-a55df9842de5";
partition@0 {
label = "BootStrap-BL1";
@@ -88,10 +89,12 @@
partition@60 {
label = "FIP-Bank0";
reg = <0x60 0x40>;
+ uuid =
"5a66a702-99fd-4fef-a392-c26e261a2828";
};
partition@a0 {
label = "FIP-Bank1";
reg = <0xa0 0x40>;
+ uuid =
"a8f868a1-6e5c-4757-878d-ce63375ef2c0";
};
};
};
diff --git a/board/socionext/developerbox/Kconfig
b/board/socionext/developerbox/Kconfig
index 7df6750baf..ad2a284f13 100644
--- a/board/socionext/developerbox/Kconfig
+++ b/board/socionext/developerbox/Kconfig
@@ -38,6 +38,7 @@ config FWU_MULTI_BANK_UPDATE
select DM_SPI_FLASH
select DM_FWU_MDATA
select BOARD_LATE_INIT
+ select SET_DFU_ALT_INFO
config FWU_NUM_BANKS
default 2
diff --git a/board/socionext/developerbox/fwu_plat.c
b/board/socionext/developerbox/fwu_plat.c
index fd6d0e3659..ff06eade7d 100644
--- a/board/socionext/developerbox/fwu_plat.c
+++ b/board/socionext/developerbox/fwu_plat.c
@@ -10,8 +10,10 @@
#include
#include
#include
+#include
#include
#include
+#include
#include
#include
@@ -94,6 +96,36 @@ static int sf_save_data(u32 offs, u32 size, void *data)
return ret;
}
+#define DFU_ALT_BUF_LEN 256
+#define DFU_ALT_NUM_MAX (CONFIG_FWU_NUM_IMAGES_PER_BANK * CONFIG_FWU_NUM_BANKS)
+
+/* Generate dfu_alt_info from partitions */
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ int ret;
+ struct mtd_info *mtd;
+ static char *buf = NULL;
+
+ if (!buf) {
+ buf = malloc_cache_aligned(DFU_ALT_BUF_LEN);
+ memset(buf, 0, DFU_ALT_BUF_LEN);
+
+ mtd_probe_devices();
+
+ mtd = get_mtd_device_nm("nor1");
+ if (IS_ERR_OR_NULL(mtd))
+ return;
+
+ ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd);
+ if (ret < 0) {
+ log_err("Error: Failed to generate dfu_alt_info.
(%d)\n", ret);
+ return;
+ }
+ log_debug("Make dfu_alt_info: '%s'\n", buf);
+ }
+ env_set("dfu_alt_info", buf);
+}
+
#define PLAT_METADATA_OFFSET 0x51
#define PLAT_METADATA_SIZE(sizeof(struct devbox_metadata))
@@ -105,49 +137,7 @@ struct __packed devbox_metadata {
int fwu_plat_get_alt_num(struct udevice __always_unused *dev,
efi_guid_t *image_id, int *alt_num)
{
- struct fwu_image_bank_info *bank;
- struct fwu_mdata *mdata;
- int i, ret;
-
- ret = fwu_get_mdata();
- if (ret < 0)
- return ret;
-
- /*
-* DeveloperBox FWU expects Bank:Image = 1:1, and the dfu_alt_info
-* only has the entries for banks. Thus the alt_no should be equal
-* to the bank index number.
-*/
- ret = -ENOENT;
- for (i = 0; i < CONFIG_FWU_NUM_BANKS; i++) {
- bank = >img_entry[0].img_bank_info[i];
- if (guidcmp(image_id, >image_uuid) == 0) {
- *alt_num = i;
-
Re: [PATCH v5 19/23] FWU: synquacer: Add FWU Multi bank update support for DeveloperBox
On 6/9/22 14:30, Sughosh Ganu wrote:
From: Masami Hiramatsu
The DeveloperBox platform can support the FWU Multi bank
update. SCP firmware will switch the boot mode by DSW3-4
and load the Multi bank update supported TF-A BL2 from
0x60 offset on the SPI flash. Thus it can co-exist
with the legacy boot mode (legacy U-Boot or EDK2).
Signed-off-by: Masami Hiramatsu
---
Changes in v3:
- Change devicetree to add partitions.
- Update fwu_plat_get_alt_num() to find the alt number from the bank index.
- Use only 2 partitions for AB update.
- Clear platform-mdata's boot_count to finish platform trial boot.
Signed-off-by: Sughosh Ganu
---
.../synquacer-sc2a11-developerbox-u-boot.dtsi | 15 +-
board/socionext/developerbox/Kconfig | 13 ++
board/socionext/developerbox/Makefile | 1 +
board/socionext/developerbox/fwu_plat.c | 207 ++
include/configs/synquacer.h | 8 +
5 files changed, 241 insertions(+), 3 deletions(-)
create mode 100644 board/socionext/developerbox/fwu_plat.c
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
index 095727e03c..ab4e3d1c2b 100644
--- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -23,7 +23,7 @@
active_clk_edges;
chipselect_num = <1>;
- spi-flash@0 {
+ spi_flash: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -84,11 +84,15 @@
label = "UBoot-Env";
reg = <0x58 0x8>;
};
-
+ /* FWU Multi bank update partitions */
partition@60 {
- label = "FIP";
+ label = "FIP-Bank0";
reg = <0x60 0x40>;
};
+ partition@a0 {
+ label = "FIP-Bank1";
+ reg = <0xa0 0x40>;
+ };
};
};
};
@@ -114,6 +118,11 @@
optee {
status = "okay";
};
+ fwu-mdata {
+ compatible = "u-boot,fwu-mdata-mtd";
+ fwu-mdata-store = <_flash>;
+ mdata-offsets = <0x50 0x53>;
+ };
};
};
diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig
index c181d26a44..7df6750baf 100644
--- a/board/socionext/developerbox/Kconfig
+++ b/board/socionext/developerbox/Kconfig
@@ -32,4 +32,17 @@ config SYS_CONFIG_NAME
default "synquacer"
endif
+
+config FWU_MULTI_BANK_UPDATE
+ select FWU_MDATA_MTD
+ select DM_SPI_FLASH
+ select DM_FWU_MDATA
+ select BOARD_LATE_INIT
+
+config FWU_NUM_BANKS
+ default 2
+
+config FWU_NUM_IMAGES_PER_BANK
+ default 1
+
endif
diff --git a/board/socionext/developerbox/Makefile
b/board/socionext/developerbox/Makefile
index 4a46de995a..9b80ee38e7 100644
--- a/board/socionext/developerbox/Makefile
+++ b/board/socionext/developerbox/Makefile
@@ -7,3 +7,4 @@
#
obj-y := developerbox.o
+obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += fwu_plat.o
diff --git a/board/socionext/developerbox/fwu_plat.c
b/board/socionext/developerbox/fwu_plat.c
new file mode 100644
index 00..fd6d0e3659
--- /dev/null
+++ b/board/socionext/developerbox/fwu_plat.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+/* SPI Flash accessors */
+static struct spi_flash *plat_spi_flash;
+
+static int __plat_sf_get_flash(void)
+{
+ /* TODO: define platform spi-flash somewhere. */
+ plat_spi_flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+CONFIG_SF_DEFAULT_CS,
+CONFIG_SF_DEFAULT_SPEED,
+CONFIG_SF_DEFAULT_MODE);
+
+ return 0;
+}
+
+static int plat_sf_get_flash(struct spi_flash **flash)
+{
+ int ret = 0;
+
+ if (!plat_spi_flash)
+ ret = __plat_sf_get_flash();
+
+ *flash = plat_spi_flash;
+
+ return ret;
+}
+
+static int sf_load_data(u32 offs, u32 size, void **data)
+{
+ struct spi_flash *flash;
+ int ret;
+
+ ret = plat_sf_get_flash();
+ if (ret < 0)
+ return ret;
+
+ *data =
Re: [PATCH v5 21/23] doc: synquacer: Add how to enable FWU Multi Bank Update
On 6/9/22 14:30, Sughosh Ganu wrote: From: Masami Hiramatsu Add a section for the instruction of building the FWU Multi Bank Update supported U-Boot and installation. Signed-off-by: Masami Hiramatsu Signed-off-by: Sughosh Ganu --- doc/board/socionext/developerbox.rst | 110 +++ 1 file changed, 110 insertions(+) diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst index 2d943c23be..d9f38a3897 100644 --- a/doc/board/socionext/developerbox.rst +++ b/doc/board/socionext/developerbox.rst @@ -85,3 +85,113 @@ Once the flasher tool is running we are ready flash the UEFI image:: After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board. + +Enable FWU Multi Bank Update + + +DeveloperBox supports the FWU Multi Bank Update. You *MUST* update both *SCP firmware* and *TF-A* for this feature. This will change the layout and the boot process but you can switch back to the normal one by changing the DSW 1-4 off. + +Configure U-Boot + + +To enable the FWU Multi Bank Update on the DeveloperBox, you need to add following configurations to configs/synquacer_developerbox_defconfig :: + + CONFIG_FWU_MULTI_BANK_UPDATE=y + CONFIG_FWU_MDATA_MTD=y + CONFIG_CMD_FWU_METADATA=y + CONFIG_TOOLS_MKFWUMDATA=y + +And build it:: + + cd u-boot/ + export ARCH=arm64 + export CROSS_COMPILE=aarch64-linux-gnu- + make synqucer_developerbox_defconfig + make -j `noproc` + cd ../ + +By default, the CONFIG_FWU_NUM_BANKS and COFNIG_FWU_NUM_IMAGES_PER_BANKS are set to 2 and 1 respectively. This uses FIP (Firmware typo CONFIG_ Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] tools: binman: install btool
On Tue, Jun 14, 2022 at 06:42:07PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan > > btool is needed after install binman to system. > > Signed-off-by: Peng Fan > Reviewed-by: Alper Nebi Yasak Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] board: ti: am335x: eth_cpsw should depend on CONFIG_NET
On Tue, Jun 14, 2022 at 08:44:07AM +, Corentin LABBE wrote:
> The origin of this patch is the breaking of am335x-hs boot
> due to commit e41651fffda7 ("dm: Support parent devices with of-platdata")
> HS boards have less SRAM for SPL and so this commit increased memory usage
> beyond am335x limit.
> This commit added 10 driver binding pass and am335x boot only if one pass is
> done.
> SPL try to do more than one pass due to eth_cpsw failing.
> Since HS SPL does not need network (and NET is already disabled in config),
> the easiest fix is to "remove" eth_cpsw from SPL by testing if NET is enabled.
>
> Signed-off-by: Corentin LABBE
> Reviewed-by: Tom Rini
> Acked-by: Andrew Davis
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH v2] armv8: always use current exception level for TCR_ELx access
On Tue, Jun 14, 2022 at 12:11:10AM +0100, Andre Przywara wrote: > Currently get_tcr() takes an "el" parameter, to select the proper > version of the TCR_ELx system register. > This is problematic in case of the Apple M1, since it runs with > HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, > and we get the wrong version. > > For U-Boot's purposes the only sensible choice here is the current > exception level, and indeed most callers treat it like that, so let's > remove that parameter and read the current EL inside the function. > This allows us to check for the E2H bit, and pretend it's EL1 in this > case. > > There are two callers which don't care about the EL, and they pass 0, > which looks wrong, but is irrelevant in these two cases, since we don't > use the return value there. So the change cannot affect those two. > > Signed-off-by: Andre Przywara > Reviewed-by: Mark Kettenis > Tested-by: Mark Kettenis Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm64: dts: imx8mq-kontron-pitx-imx8m-u-boot.dtsi: disable assigned clocks
On Sat, Jun 11, 2022 at 08:09:04AM +0200, Heiko Thiery wrote: > With the move to use DM_CLK the boards uart stops working. The used > properties are not supported by the imx8mq clock driver. Thus > the correct baudrate cannot be selected. Remove this properties here and > the board can start with working uart. Keep it in the main dts because > linux handles these porperties fine. > > Signed-off-by: Heiko Thiery Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2] fs/squashfs: sqfs_read: Prevent arbitrary code execution
On Thu, Jun 09, 2022 at 04:02:06PM +0200, Miquel Raynal wrote: > Following Jincheng's report, an out-of-band write leading to arbitrary > code execution is possible because on one side the squashfs logic > accepts directory names up to 65535 bytes (u16), while U-Boot fs logic > accepts directory names up to 255 bytes long. > > Prevent such an exploit from happening by capping directory name sizes > to 255. Use a define for this purpose so that developers can link the > limitation to its source and eventually kill it some day by dynamically > allocating this array (if ever desired). > > Link: > https://lore.kernel.org/all/CALO=dhfb+yboxxvr5kcsk0ifdg+e7ywko4-e+72kjbcs8jb...@mail.gmail.com > Reported-by: Jincheng Wang > Signed-off-by: Miquel Raynal > Tested-by: Jincheng Wang Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] odroid_xu3: Fix board environment variable
On Wed, Jun 08, 2022 at 02:30:14PM -0400, Tom Rini wrote:
> When migrating CONFIG_CONS_INDEX to Kconfig, on this platform we changed
> what "board" evaluated to in the environment. This in turn meant that
> we would no longer try and find the correct fdtfile via the normal
> distro boot logic. Fix this by overriding board in the default
> environment, as done on other platforms where CONFIG_SYS_BOARD is not
> what we want to be in the board environment variable.
>
> Fixes: f76750d11133 ("Convert CONFIG_CONS_INDEX et al to Kconfig")
> Reported-by: Gabriel Hojda
> Tested-by: Gabriel Hojda
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH] usb: host: ehci-generic: Make resets and clocks optional
On Wed, Jun 08, 2022 at 12:42:22AM +0100, Andre Przywara wrote: > The generic EHCI binding does not *require* resets and clocks > properties, and indeed for instance the Allwinner A20 SoCs does not > need or define any resets in its DT. > > Don't easily give up if clk_get_bulk() or reset_get_bulk() return an > error, but check if that is due to the DT simply having no entries for > either of them. > > This fixes USB operation on all boards with an Allwinner A10 or A20 SoC, > which were reporting an error after commit ba96176ab70e2999: > === > Bus usb@1c14000: ehci_generic usb@1c14000: Failed to get resets (err=-2) > probe failed, error -2 > === > > Signed-off-by: Andre Przywara > Reviewed-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] .gitignore: add files produced by b4
On Tue, Jun 07, 2022 at 10:13:00AM +0200, Andrey Zhizhikin wrote: > b4 utility [1] is introduced by Linux Kernel developers and used to > fetch patches and patch series from lore.kernel.org and is proven > to be useful for U-Boot development. Detailed usage of the tool can be > read under post from the original author [2]. > > This tool fetches files from the list and populates the source folder > with additional files (*.cover and *.mbx) which are not ignored by git > and shown as newly added files. > > Add those file patterns into .gitignore file, so they can be safely > skipped during changes attestation. > > Link: [1]: https://pypi.org/project/b4/ > Link: [2]: > https://people.kernel.org/monsieuricon/introducing-b4-and-patch-attestation > Signed-off-by: Andrey Zhizhikin > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] Update email address and company name
On Thu, May 12, 2022 at 04:21:53PM +0200, Christophe Leroy wrote: > This patch updates my email address and company name. > > Signed-off-by: Christophe Leroy Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arch: arm: mach-k3: am642_init: bring back MCU_PADCFG_MMR1 unlock
On Thu, May 12, 2022 at 08:21:01AM +0200, Christian Gmeiner wrote:
> Without this register unlock it is not possible to configure the
> pinmux used for mcu spi0.
>
> Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes")
> Signed-off-by: Christian Gmeiner
> Reviewed-by: Nishanth Menon
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH] net: Fix discuss discard typo
On Sun, May 01, 2022 at 06:43:55PM +0200, Marek Vasut wrote:
> Replace discuss with discard, that is what happens with packet with
> incorrect checksum. Fix the typo.
>
> Fixes: 4b37fd146bb ("Convert CONFIG_UDP_CHECKSUM to Kconfig")
> Signed-off-by: Marek Vasut
> Cc: Ramon Fried
> Cc: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH] crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()
On Fri, Apr 29, 2022 at 03:34:44PM +0200, Stefan Roese wrote: > While working on an LX2160 based board and updating to latest mainline > I noticed problems using the HW accelerated hash functions on this > platform, when trying to boot a FIT Kernel image. Here the resulting > error message: > >Using 'conf-freescale_lx2160a.dtb' configuration >Trying 'kernel-1' kernel subimage >Verifying Hash Integrity ... sha256Error: Address arguments are not aligned > CAAM was not setup properly or it is faulty > error! > Bad hash value for 'hash-1' hash node in 'kernel-1' image node > Bad Data Hash > ERROR: can't get kernel image! > > Testing and checking with Gaurav Jain from NXP has revealed, that this > alignment check is not necessary here at all. So let's remove this > check completely. > > Signed-off-by: Stefan Roese > Cc: Gaurav Jain > Cc: dullf...@yahoo.com > Reviewed-by: Gaurav Jain Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] disk: part: change from hextoul to dectoul
On Fri, Jun 17, 2022 at 07:01:59PM +0900, Jaehoon Chung wrote: > When 'ls' command is running with partition number, it's passed by a hex > value. For example, if want to check a 15th partition, it has to input > as 0xf. > Before applied > - ls mmc 0:f > After applied > - ls mmc 0:15 > > The using decimal number is more readable than passed by a hex value. > > Signed-off-by: Jaehoon Chung NAK. I agree it's a more obvious way of interacting. But the CLI is our API with our users and there's lots of stuff out there today that knows (and then deals with) needing to pass hex not decimal for partitions. And given SoCs that have large numbers of partitions, you can't assume that "12" isn't in intentional and referring to partition 18 in decimal. We could maybe do this with a flag or environment variable to allow people to opt-in, since that would at least allow for multi-platform scripts to know what to expect and not have to guess / hard-code per platform. -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 3/3] drivers: rng: optee_rng: register to CONFIG_OPTEE_SERVICE_DISCOVERY
Hi,
a minor remark
On 6/7/22 12:21, Etienne Carriere wrote:
Changes optee_rng driver to register itself has a OP-TEE service so
that a device is bound for the driver when OP-TEE enumerates the
PTA RNG service.
Cc: Sughosh Ganu
Cc: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
No change since v2.
No change since v1.
---
drivers/rng/Kconfig | 1 +
drivers/rng/optee_rng.c | 12 +++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index c10f7d345b..14e95a6213 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -34,6 +34,7 @@ config RNG_MSM
config RNG_OPTEE
bool "OP-TEE based Random Number Generator support"
depends on DM_RNG && OPTEE
+ default y if OPTEE_SERVICE_DISCOVERY
help
This driver provides support for the OP-TEE based Random Number
Generator on ARM SoCs where hardware entropy sources are not
diff --git a/drivers/rng/optee_rng.c b/drivers/rng/optee_rng.c
index aa8ce864d3..90d9434395 100644
--- a/drivers/rng/optee_rng.c
+++ b/drivers/rng/optee_rng.c
@@ -11,6 +11,9 @@
#include
#include
#include
a minor remark
+#include
+
+#define DRIVER_NAME"optee-rng"
#define TEE_ERROR_HEALTH_TEST_FAIL 0x0001
@@ -35,6 +38,13 @@
#define TA_HWRNG_UUID { 0xab7a617c, 0xb8e7, 0x4d8f, \
{ 0x83, 0x01, 0xd0, 0x9b, 0x61, 0x03, 0x6b, 0x64 } }
+#ifdef CONFIG_OPTEE_SERVICE_DISCOVERY
+OPTEE_SERVICE_DRIVER(optee_rng) = {
+ .uuid = TA_HWRNG_UUID,
+ .driver_name = DRIVER_NAME,
+};
+#endif
+
a minor remark
I think '#ifdef CONFIG_OPTEE_SERVICE_DISCOVERY'
can avoid here with the macro call:
+ OPTEE_SERVICE_DRIVER(optee_rng, TA_HWRNG_UUID, DRIVER_NAME);
and a modified macro in patch 2:
+#ifdef CONFIG_OPTEE_SERVICE_DISCOVERY
+#define OPTEE_SERVICE_DRIVER(__name, __uuid, __drv_name) \
+ ll_entry_declare(struct optee_service, __name, optee_service) = {\
+ .uuid = __uuid,\
+ .driver_name = __drv_name}
+#else
+#define OPTEE_SERVICE_DRIVER(__name, __uuid, __drv_name)
+#endif
This code is inspired by
include/image.h:1575
#defineU_BOOT_FIT_LOADABLE_HANDLER(_type, _handler) \
ll_entry_declare(struct fit_loadable_tbl, _function, fit_loadable) ={ \
.type =_type, \
.handler =_handler, \
}
or also include/env.h:55
/*
* Define a callback that can be associated with variables.
* when associated through the ".callbacks" environment variable, the
callback
* will be executed any time the variable is inserted, overwritten, or
deleted.
*
* For SPL these are silently dropped to reduce code size, since
environment
* callbacks are not supported with SPL.
*/
#ifdef CONFIG_SPL_BUILD
#define U_BOOT_ENV_CALLBACK(name, callback) \
static inline __maybe_unused void _u_boot_env_noop_##name(void) \
{ \
(void)callback; \
}
#else
#define U_BOOT_ENV_CALLBACK(name, callback) \
ll_entry_declare(struct env_clbk_tbl, name, env_clbk) = \
{#name, callback}
#endif
/** open_session_ta_hwrng() - Open session with hwrng Trusted App
*
* @dev: device
@@ -177,7 +187,7 @@ static const struct dm_rng_ops optee_rng_ops = {
};
U_BOOT_DRIVER(optee_rng) = {
- .name = "optee-rng",
+ .name = DRIVER_NAME,
.id = UCLASS_RNG,
.ops = _rng_ops,
.probe = optee_rng_probe,
Regards
Re: [PATCH v3 3/3] drivers: rng: optee_rng: register to CONFIG_OPTEE_SERVICE_DISCOVERY
Hi, On 6/7/22 12:21, Etienne Carriere wrote: Changes optee_rng driver to register itself has a OP-TEE service so that a device is bound for the driver when OP-TEE enumerates the PTA RNG service. Cc: Sughosh Ganu Cc: Patrick Delaunay Signed-off-by: Etienne Carriere --- No change since v2. No change since v1. --- drivers/rng/Kconfig | 1 + drivers/rng/optee_rng.c | 12 +++- 2 files changed, 12 insertions(+), 1 deletion(-) Reviewed-by: Patrick Delaunay Thanks Patrick
Re: [PATCH v3 2/3] drivers: tee: optee: discover OP-TEE services
Hi, On 6/7/22 12:21, Etienne Carriere wrote: This change defines resources for OP-TEE service drivers to register themselves for being bound to when OP-TEE firmware reports the related service is supported. OP-TEE services are discovered during optee driver probe sequence which mandates optee driver is always probe once bound. Discovery of optee services and binding to related U-Boot drivers is embedded upon configuration switch CONFIG_OPTEE_SERVICE_DISCOVERY. Cc: Jens Wiklander Cc: Patrick Delaunay Signed-off-by: Etienne Carriere --- Changes since v2: - Release allocated shared memory from bind_service_drivers() only. - Remove definition of useless macro OPTEE_SERVICE_DRIVER_GET(). Changes since v1: - Remove all #ifdef CONFIG_OPTEE_SERVICE_DISCOVERY directives and replace with if (IS_ENABLED()) where applicable. - Incidentally rename local function open_session() to open_enum_session() and remove local function close_session() for clarity. - Update commit log to highlight that "optee driver is always probe once bound" when CONFIG_OPTEE_SERVICE_DISCOVERY is enable. --- drivers/tee/optee/Kconfig | 8 ++ drivers/tee/optee/core.c| 171 ++-- include/tee/optee_service.h | 26 ++ 3 files changed, 200 insertions(+), 5 deletions(-) create mode 100644 include/tee/optee_service.h Reviewed-by: Patrick Delaunay Thanks Patrick
Re: [PATCH v3 1/3] drivers: tee: optee: remove unused probe local variable
Hi Etienne,
On 6/7/22 12:21, Etienne Carriere wrote:
Removes local variable child in optee_probe() that is not used.
Cc: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
No change since v2.
New change not in v1 series.
---
drivers/tee/optee/core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
index a89d62aaf0..c1f5fc4c7a 100644
--- a/drivers/tee/optee/core.c
+++ b/drivers/tee/optee/core.c
@@ -642,7 +642,6 @@ static int optee_probe(struct udevice *dev)
{
struct optee_pdata *pdata = dev_get_plat(dev);
u32 sec_caps;
- struct udevice *child;
int ret;
if (!is_optee_api(pdata->invoke_fn)) {
@@ -673,7 +672,7 @@ static int optee_probe(struct udevice *dev)
* only bind the drivers associated to the supported OP-TEE TA
*/
if (IS_ENABLED(CONFIG_RNG_OPTEE)) {
- ret = device_bind_driver(dev, "optee-rng", "optee-rng", );
+ ret = device_bind_driver(dev, "optee-rng", "optee-rng", NULL);
if (ret)
return ret;
}
Reviewed-by: Patrick Delaunay
Thanks
Patrick
[PULL] Pull request for u-boot master / v2022.07 = u-boot-stm32-20220617
Hi Tom, Please pull the STM32 related fixes for u-boot/master, v2022.07: u-boot-stm32-20220617 - Fix the stm32prog command for stm32mp platform - Add stm32mp15x DHCOR based DRC Compact board CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/12387 Thanks, Patrick git request-pull origin/master https://source.denx.de/u-boot/custodians/u-boot-stm.git/ u-boot-stm32-20220617 The following changes since commit 9abfbef57f55f31e42940ac2a18ebccfb087e5c6: Merge tag 'u-boot-imx-20220616' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-06-16 08:38:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git/ tags/u-boot-stm32-20220617 for you to fetch changes up to 4f71c80b0d9e57d96df4462fbcd7d9c6a16f471d: ARM: dts: stm32: Add DHCOR based DRC Compact board (2022-06-17 09:31:19 +0200) - Fix the stm32prog command for stm32mp platform - Add stm32mp15x DHCOR based DRC Compact board Marek Vasut (6): ARM: dts: stm32: Add alternate pinmux for UART3 pins ARM: dts: stm32: Add alternate pinmux for UART4 pins ARM: dts: stm32: Add alternate pinmux for UART5 pins ARM: dts: stm32: Add alternate pinmux for CAN1 pins ARM: dts: stm32: Add alternate pinmux for SPI2 pins ARM: dts: stm32: Add DHCOR based DRC Compact board Patrick Delaunay (1): stm32mp: stm32prog: fix the last character of dfu_alt_add third parameter arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32mp15-pinctrl.dtsi | 119 + arch/arm/dts/stm32mp153c-dhcor-drc-compact.dts | 30 ++ arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi | 120 ++ arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts | 16 arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi | 326 + arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 +- board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its | 15 +++ configs/stm32mp15_dhcor_basic_defconfig | 1 + 9 files changed, 631 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/stm32mp153c-dhcor-drc-compact.dts create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi
Re: [PATCH 00/10] xilinx: zynqmp: Support foreign vendor boards
Hi, On 6/8/22 18:20, Stefan Herbrechtsmeier wrote: [CAUTION: External Email] From: Stefan Herbrechtsmeier At the moment the xilinx zynqmp soc is only supported by xilinx vendor boards. Rework the xilinx zynqmp board code to support reuse by foreign vendor boards. Stefan Herbrechtsmeier (10): firmware: firmware-zynqmp: Check if rx channel dev pointer is valid firmware: firmware-zynqmp: Probe driver before use soc: xilinx: zynqmp: Add machine identification support xilinx: zynqmp: Use soc machine function to get silicon idcode name xilinx: cpuinfo: Print soc machine xilinx: common: Separate display cpu info function xilinx: zynqmp: make spi flash support optional tools: zynqmp_psu_init_minimize: Remove low level uart settings tools: zynqmp_psu_init_minimize: Add serdes_illcalib forward declaration xilinx: zynqmp: Support vendor specific board_init board/xilinx/common/Makefile | 3 + board/xilinx/common/board.c| 30 +-- board/xilinx/common/board.h| 2 + board/xilinx/common/cpu-info.c | 35 board/xilinx/zynqmp/zynqmp.c | 291 ++--- drivers/firmware/firmware-zynqmp.c | 20 +- drivers/soc/soc_xilinx_zynqmp.c| 289 +++- tools/zynqmp_psu_init_minimize.sh | 22 +++ 8 files changed, 390 insertions(+), 302 deletions(-) create mode 100644 board/xilinx/common/cpu-info.c -- 2.30.2 The rest of patches are fine. Thanks, Michal
[PATCH v3 11/11] socfpga: arria10: Allow dcache_enable before relocation
Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).
Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
arch/arm/mach-socfpga/misc_arria10.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc_arria10.c
b/arch/arm/mach-socfpga/misc_arria10.c
index 0ed2adfd84..7ce888d197 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)
return 0;
}
#endif
+
+void dram_bank_mmu_setup(int bank)
+{
+ struct bd_info *bd = gd->bd;
+ u32 start, size;
+ int i;
+
+ /* If we're still in OCRAM, don't set the XN bit on it */
+ if (!(gd->flags & GD_FLG_RELOC)) {
+ set_section_dcache(
+ CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+ DCACHE_WRITETHROUGH);
+ }
+
+ /*
+* The default implementation of this function allows the DRAM dcache
+* to be enabled only after relocation. However, to speed up ECC
+* initialization, we want to be able to enable DRAM dcache before
+* relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+* is set first).
+*/
+ start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+ size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+ for (i = start; i < start + size; i++)
+ set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
--
2.36.1.476.g0c4daa206d-goog
[PATCH v3 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream
For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
drivers/fpga/socfpga_arria10.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 07bfe3060e..d8089122af 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -80,6 +80,13 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
}
+static int wait_for_fifo_empty(void)
+{
+ return wait_for_bit_le32(_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
+ 1, FPGA_TIMEOUT_MSEC, false);
+}
+
int is_fpgamgr_early_user_mode(void)
{
return (readl(_manager_base->imgcfg_stat) &
@@ -874,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
*buf, size_t bsize,
WATCHDOG_RESET();
}
+ wait_for_fifo_empty();
if (fpga_loadfs.rbfinfo.section == periph_section) {
if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
--
2.36.1.476.g0c4daa206d-goog
[PATCH v3 09/11] socfpga: arria10: Improve bitstream loading speed
Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):
* Change the size of the first fs read, so that all the subsequent
reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
This value was chosen so that in subsequent reads the fat fs driver
doesn't have to allocate a temporary buffer in get_contents
(assuming 8KiB clusters).
* Change the buffer size to a larger value when reading to ddr
(but not too large, because large transfers cause a stack overflow
in the dwmmc driver).
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
drivers/fpga/socfpga_arria10.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 798e3a3f90..07bfe3060e 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,6 +30,14 @@
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
#define FPGA_TIMEOUT_CNT 0x100
#define DEFAULT_DDR_LOAD_ADDRESS 0x400
+#define DDR_BUFFER_SIZE0x10
+
+/* When reading bitstream from a filesystem, the size of the first read is
+ * changed so that the subsequent reads are aligned to this value. This value
+ * was chosen so that in subsequent reads the fat fs driver doesn't have to
+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
+ */
+#define MAX_FIRST_LOAD_SIZE0x2000
DECLARE_GLOBAL_DATA_PTR;
@@ -526,7 +534,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16
*buffer)
#ifdef CONFIG_FS_LOADER
static int first_loading_rbf_to_buffer(struct udevice *dev,
struct fpga_loadfs_info *fpga_loadfs,
- u32 *buffer, size_t *buffer_bsize)
+ u32 *buffer, size_t *buffer_bsize,
+ size_t *buffer_bsize_ori)
{
u32 *buffer_p = (u32 *)*buffer;
u32 *loadable = buffer_p;
@@ -674,6 +683,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
}
buffer_size = rbf_size;
+ *buffer_bsize_ori = DDR_BUFFER_SIZE;
}
debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
@@ -686,11 +696,16 @@ static int first_loading_rbf_to_buffer(struct udevice
*dev,
* chunk by chunk transfer is required due to smaller buffer size
* compare to bitstream
*/
+
+ if (buffer_size > MAX_FIRST_LOAD_SIZE)
+ buffer_size = MAX_FIRST_LOAD_SIZE;
+
if (rbf_size <= buffer_size) {
/* Loading whole bitstream into buffer */
buffer_size = rbf_size;
fpga_loadfs->remaining = 0;
} else {
+ buffer_size -= rbf_offset % buffer_size;
fpga_loadfs->remaining -= buffer_size;
}
@@ -806,7 +821,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
*buf, size_t bsize,
* function below.
*/
ret = first_loading_rbf_to_buffer(dev, _loadfs, ,
- _sizebytes);
+ _sizebytes,
+ _sizebytes_ori);
if (ret == 1) {
printf("FPGA: Skipping configuration ...\n");
return 0;
--
2.36.1.476.g0c4daa206d-goog
[PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).
Signed-off-by: Paweł Anikiel
---
arch/arm/mach-socfpga/clock_manager_arria10.c | 31 +--
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 58d5d3fd8a..b48a2b47bc 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -15,6 +15,10 @@
#ifdef CONFIG_SPL_BUILD
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound);
+
static u32 eosc1_hz;
static u32 cb_intosc_hz;
static u32 f2s_free_hz;
@@ -551,13 +555,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
main_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
@@ -585,16 +589,25 @@ static void cm_pll_ramp_periph(struct mainpll_cfg
*main_cfg,
clk_hz),
socfpga_get_clkmgr_addr() +
CLKMGR_A10_PERPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
per_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
+/* function to poll in the fsm busy bit */
+static int cm_busy_wait_for_fsm(void)
+{
+ void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);
+
+ /* 20s timeout */
+ return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 1);
+}
+
/*
* Setup clocks while making no assumptions of the
* previous state of the clocks.
@@ -727,7 +740,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct
perpll_cfg *per_cfg)
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
/* Wait for at least 5 us */
- udelay(5);
+ sdelay(5000);
/* Now deassert BGPWRDN and PWRDN */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
@@ -738,7 +751,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct
perpll_cfg *per_cfg)
CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
/* Wait for at least 7 us */
- udelay(7);
+ sdelay(7000);
/* enable the VCO and disable the external regulator to PLL */
writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
@@ -878,19 +891,19 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg,
struct perpll_cfg *per_cfg)
writel(CLKMGR_MAINPLL_BYPASS_RESET,
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);
/* wait till Clock Manager is not busy */
- cm_wait_for_fsm();
+ cm_busy_wait_for_fsm();
/* release perpll from bypass */
writel(CLKMGR_PERPLL_BYPASS_RESET,
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);
/* wait till Clock Manager is not busy */
- cm_wait_for_fsm();
+ cm_busy_wait_for_fsm();
/* clear boot mode */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
/* wait till Clock Manager is not busy */
- cm_wait_for_fsm();
+ cm_busy_wait_for_fsm();
/* At here, we need to ramp to final value if needed */
if (pll_ramp_main_hz != 0)
--
2.36.1.476.g0c4daa206d-goog
[PATCH v3 07/11] sysreset: socfpga: Use parent device for reading base address
This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
drivers/sysreset/sysreset_socfpga.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/sysreset/sysreset_socfpga.c
b/drivers/sysreset/sysreset_socfpga.c
index e38296ac3f..9b62dd5eab 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
{
struct socfpga_sysreset_data *data = dev_get_priv(dev);
- data->rstmgr_base = dev_read_addr_ptr(dev);
+ data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
return 0;
}
--
2.36.1.476.g0c4daa206d-goog
[PATCH v3 06/11] misc: atsha204a: Increase wake delay by tWHI
>From the ATSHA204A datasheet (document DS40002025A):
Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.
tWHI value can be found in table 7-2.
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
drivers/misc/atsha204a-i2c.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index aa6acf0f9a..81ecb5b617 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -21,7 +21,8 @@
#include
#include
-#define ATSHA204A_TWLO 60
+#define ATSHA204A_TWLO_US 60
+#define ATSHA204A_TWHI_US 2500
#define ATSHA204A_TRANSACTION_TIMEOUT 10
#define ATSHA204A_TRANSACTION_RETRY5
#define ATSHA204A_EXECTIME 5000
@@ -109,7 +110,7 @@ int atsha204a_wakeup(struct udevice *dev)
continue;
}
- udelay(ATSHA204A_TWLO);
+ udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
res = atsha204a_recv_resp(dev, );
if (res) {
--
2.36.1.476.g0c4daa206d-goog
[PATCH v3 05/11] config: Add Chameleonv3 config
Add defconfig and Kconfig files for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
arch/arm/mach-socfpga/Kconfig | 7 +
configs/socfpga_chameleonv3_defconfig | 29 ++
include/configs/socfpga_chameleonv3.h | 44 +++
3 files changed, 80 insertions(+)
create mode 100644 configs/socfpga_chameleonv3_defconfig
create mode 100644 include/configs/socfpga_chameleonv3.h
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 78a7549a41..fe851f575e 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -143,6 +143,10 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
+config TARGET_SOCFPGA_CHAMELEONV3
+ bool "Google Chameleon v3 (Arria 10)"
+ select TARGET_SOCFPGA_ARRIA10
+
config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -194,6 +198,7 @@ config SYS_BOARD
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -219,6 +224,7 @@ config SYS_VENDOR
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "google" if TARGET_SOCFPGA_CHAMELEONV3
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -234,6 +240,7 @@ config SYS_CONFIG_NAME
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
diff --git a/configs/socfpga_chameleonv3_defconfig
b/configs/socfpga_chameleonv3_defconfig
new file mode 100644
index 00..7870d31b09
--- /dev/null
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x1
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_MMC_DW=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_MISC_INIT_R=y
+CONFIG_ATSHA204A=y
diff --git a/include/configs/socfpga_chameleonv3.h
b/include/configs/socfpga_chameleonv3.h
new file mode 100644
index 00..891b762946
--- /dev/null
+++ b/include/configs/socfpga_chameleonv3.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 Google LLC
+ */
+#ifndef __SOCFGPA_CHAMELEONV3_H__
+#define __SOCFGPA_CHAMELEONV3_H__
+
+#include
+
+#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x4000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=no\0" \
+ "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw
rootwait\0" \
+ "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
+ "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
+ "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/* SPL memory allocation configuration, this is for FAT implementation */
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
+
+/* The rest of the configuration is shared */
+#include
+
+#endif /* __SOCFGPA_CHAMELEONV3_H__ */
--
2.36.1.476.g0c4daa206d-goog
[PATCH v3 04/11] board: Add Chameleonv3 board dir
Add board directory for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
board/google/chameleonv3/Makefile | 5 +++
board/google/chameleonv3/board.c | 27 ++
board/google/chameleonv3/fpga.its | 28 ++
board/google/chameleonv3/fpga_early_io.its | 35 ++
board/google/chameleonv3/mercury_aa1.c | 43 ++
board/google/chameleonv3/mercury_aa1.h | 12 ++
6 files changed, 150 insertions(+)
create mode 100644 board/google/chameleonv3/Makefile
create mode 100644 board/google/chameleonv3/board.c
create mode 100644 board/google/chameleonv3/fpga.its
create mode 100644 board/google/chameleonv3/fpga_early_io.its
create mode 100644 board/google/chameleonv3/mercury_aa1.c
create mode 100644 board/google/chameleonv3/mercury_aa1.h
diff --git a/board/google/chameleonv3/Makefile
b/board/google/chameleonv3/Makefile
new file mode 100644
index 00..bb413fde83
--- /dev/null
+++ b/board/google/chameleonv3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright 2022 Google LLC
+
+obj-y := board.o mercury_aa1.o
diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c
new file mode 100644
index 00..4d3049689d
--- /dev/null
+++ b/board/google/chameleonv3/board.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include
+#include
+#include "mercury_aa1.h"
+
+int misc_init_r(void)
+{
+ u8 mac[ARP_HLEN];
+ int res;
+
+ if (env_get("ethaddr"))
+ return 0;
+
+ res = mercury_aa1_read_mac(mac);
+ if (res) {
+ printf("couldn't read mac address: %s\n", errno_str(res));
+ return 0;
+ }
+
+ if (is_valid_ethaddr(mac))
+ eth_env_set_enetaddr("ethaddr", mac);
+
+ return 0;
+}
diff --git a/board/google/chameleonv3/fpga.its
b/board/google/chameleonv3/fpga.its
new file mode 100644
index 00..85a830002f
--- /dev/null
+++ b/board/google/chameleonv3/fpga.its
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+ description = "FIT image with FPGA bistream";
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA full bitstream";
+ data = /incbin/("../../../fpga.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA config";
+ fpga = "fpga-periph-1";
+ };
+ };
+};
diff --git a/board/google/chameleonv3/fpga_early_io.its
b/board/google/chameleonv3/fpga_early_io.its
new file mode 100644
index 00..ebc7bcbaae
--- /dev/null
+++ b/board/google/chameleonv3/fpga_early_io.its
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+ description = "FIT image with FPGA bistream";
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA peripheral bitstream";
+ data = /incbin/("../../../periph.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ fpga-core-1 {
+ description = "FPGA core bitstream";
+ data = /incbin/("../../../core.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA config";
+ fpga = "fpga-periph-1", "fpga-core-1";
+ };
+ };
+};
diff --git a/board/google/chameleonv3/mercury_aa1.c
b/board/google/chameleonv3/mercury_aa1.c
new file mode 100644
index 00..ed447ec37c
--- /dev/null
+++ b/board/google/chameleonv3/mercury_aa1.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include
+#include
+#include
+#include
+#include "mercury_aa1.h"
+
+#define MERCURY_AA1_ATSHA204A_OTP_MAC0 4
+#define MERCURY_AA1_ATSHA204A_OTP_MAC1 5
+
+int mercury_aa1_read_mac(u8 *mac)
+{
+ struct udevice *dev;
+ u8 buf[8];
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", );
+ if (ret)
+ return ret;
+
+ ret = atsha204a_wakeup(dev);
+ if (ret)
+ return ret;
+
+ ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+
[PATCH v3 03/11] arm: dts: Add Chameleonv3 devicetrees
Add devicetrees for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
Signed-off-by: Alexandru M Stan
Reviewed-by: Simon Glass
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 +++
...fpga_arria10_chameleonv3_270_3-u-boot.dtsi | 8 ++
.../dts/socfpga_arria10_chameleonv3_270_3.dts | 5 ++
...fpga_arria10_chameleonv3_480_2-u-boot.dtsi | 8 ++
.../dts/socfpga_arria10_chameleonv3_480_2.dts | 5 ++
6 files changed, 118 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83630af4f6..910b6c3acd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -418,6 +418,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_agilex_socdk.dtb\
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
+ socfpga_arria10_chameleonv3_270_3.dtb \
+ socfpga_arria10_chameleonv3_480_2.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb\
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dts
b/arch/arm/dts/socfpga_arria10_chameleonv3.dts
new file mode 100644
index 00..988cc44543
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+ model = "Google Chameleon V3";
+ compatible = "google,chameleon-v3",
+"altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ serial0 =
+ i2c0 =
+ i2c1 =
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+
+ ssm2603: ssm2603@1a {
+ compatible = "adi,ssm2603";
+ reg = <0x1a>;
+ };
+};
+
+ {
+ status = "okay";
+
+ u80: u80@21 {
+ compatible = "nxp,pca9535";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SOM_AUD_MUTE",
+ "DP1_OUT_CEC_EN",
+ "DP2_OUT_CEC_EN",
+ "DP1_SOM_PS8469_CAD",
+ "DPD_SOM_PS8469_CAD",
+ "DP_OUT_PWR_EN",
+ "STM32_RST_L",
+ "STM32_BOOT0",
+
+ "FPGA_PROT",
+ "STM32_FPGA_COMM0",
+ "TP119",
+ "TP120",
+ "TP121",
+ "TP122",
+ "TP123",
+ "TP124";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
new file mode 100644
index 00..e789d49657
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_270_3_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
new file mode 100644
index 00..5f40af6eb9
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.dts"
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
new file mode 100644
index 00..7bbcc471c5
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include
[PATCH v3 02/11] arm: dts: Add Chameleonv3 handoff headers
Add handoff headers for the Google Chameleonv3 variants: 480-2 and 270-3. Both files were generated using qts-filter-a10.sh. Signed-off-by: Paweł Anikiel Reviewed-by: Simon Glass --- ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++ ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++ 2 files changed, 610 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h new file mode 100644 index 00..9d8f4a0dd3 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Intel Arria 10 SoCFPGA configuration + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +/* Clocks */ +#define CB_INTOSC_LS_CLK_HZ 6000 +#define EMAC0_CLK_HZ 25000 +#define EMAC1_CLK_HZ 25000 +#define EMAC2_CLK_HZ 25000 +#define EOSC1_CLK_HZ +#define F2H_FREE_CLK_HZ 2 +#define H2F_USER0_CLK_HZ 2 +#define H2F_USER1_CLK_HZ 1 +#define L3_MAIN_FREE_CLK_HZ 2 +#define SDMMC_CLK_HZ 2 +#define TPIU_CLK_HZ 1 +#define MAINPLLGRP_CNTR15CLK_CNT 900 +#define MAINPLLGRP_CNTR2CLK_CNT 900 +#define MAINPLLGRP_CNTR3CLK_CNT 900 +#define MAINPLLGRP_CNTR4CLK_CNT 900 +#define MAINPLLGRP_CNTR5CLK_CNT 900 +#define MAINPLLGRP_CNTR6CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_SRC 0 +#define MAINPLLGRP_CNTR8CLK_CNT 15 +#define MAINPLLGRP_CNTR9CLK_CNT 900 +#define MAINPLLGRP_CNTR9CLK_SRC 0 +#define MAINPLLGRP_MPUCLK_CNT 0 +#define MAINPLLGRP_MPUCLK_SRC 0 +#define MAINPLLGRP_NOCCLK_CNT 0 +#define MAINPLLGRP_NOCCLK_SRC 0 +#define MAINPLLGRP_NOCDIV_CSATCLK 0 +#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1 +#define MAINPLLGRP_NOCDIV_CSTRACECLK 0 +#define MAINPLLGRP_NOCDIV_L4MAINCLK 0 +#define MAINPLLGRP_NOCDIV_L4MPCLK 1 +#define MAINPLLGRP_NOCDIV_L4SPCLK 2 +#define MAINPLLGRP_VCO0_PSRC 0 +#define MAINPLLGRP_VCO1_DENOM 32 +#define MAINPLLGRP_VCO1_NUMER 1584 +#define PERPLLGRP_CNTR2CLK_CNT 5 +#define PERPLLGRP_CNTR2CLK_SRC 1 +#define PERPLLGRP_CNTR3CLK_CNT 900 +#define PERPLLGRP_CNTR3CLK_SRC 1 +#define PERPLLGRP_CNTR4CLK_CNT 14 +#define PERPLLGRP_CNTR4CLK_SRC 1 +#define PERPLLGRP_CNTR5CLK_CNT 374 +#define PERPLLGRP_CNTR5CLK_SRC 1 +#define PERPLLGRP_CNTR6CLK_CNT 900 +#define PERPLLGRP_CNTR6CLK_SRC 0 +#define PERPLLGRP_CNTR7CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_SRC 0 +#define PERPLLGRP_CNTR9CLK_CNT 900 +#define PERPLLGRP_EMACCTL_EMAC0SEL 0 +#define PERPLLGRP_EMACCTL_EMAC1SEL 0 +#define PERPLLGRP_EMACCTL_EMAC2SEL 0 +#define PERPLLGRP_GPIODIV_GPIODBCLK 32000 +#define PERPLLGRP_VCO0_PSRC 0 +#define PERPLLGRP_VCO1_DENOM 32 +#define PERPLLGRP_VCO1_NUMER 1485 +#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16 +#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8 +#define CLKMGR_TESTIOCTRL_PERICLKSEL 8 +#define ALTERAGRP_MPUCLK_MAINCNT 1 +#define ALTERAGRP_MPUCLK_PERICNT 900 +#define ALTERAGRP_NOCCLK_MAINCNT 7 +#define ALTERAGRP_NOCCLK_PERICNT 900 +#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \ + (ALTERAGRP_MPUCLK_MAINCNT)) +#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \ + (ALTERAGRP_NOCCLK_MAINCNT)) + +/* Pin Mux Configuration */ +#define CONFIG_IO_10_INPUT_BUF_EN 1 +#define CONFIG_IO_10_PD_DRV_STRG 10 +#define CONFIG_IO_10_PD_SLW_RT 1 +#define CONFIG_IO_10_PU_DRV_STRG 8 +#define CONFIG_IO_10_PU_SLW_RT 1 +#define CONFIG_IO_10_RTRIM 1 +#define CONFIG_IO_10_WK_PU_EN 0 +#define CONFIG_IO_11_INPUT_BUF_EN 1 +#define CONFIG_IO_11_PD_DRV_STRG 10 +#define CONFIG_IO_11_PD_SLW_RT 1 +#define CONFIG_IO_11_PU_DRV_STRG 8 +#define CONFIG_IO_11_PU_SLW_RT 1 +#define CONFIG_IO_11_RTRIM 1 +#define CONFIG_IO_11_WK_PU_EN 0 +#define CONFIG_IO_12_INPUT_BUF_EN 0 +#define CONFIG_IO_12_PD_DRV_STRG 0 +#define CONFIG_IO_12_PD_SLW_RT 0 +#define CONFIG_IO_12_PU_DRV_STRG 0 +#define CONFIG_IO_12_PU_SLW_RT 0 +#define CONFIG_IO_12_RTRIM 1 +#define CONFIG_IO_12_WK_PU_EN 1 +#define CONFIG_IO_13_INPUT_BUF_EN 0 +#define CONFIG_IO_13_PD_DRV_STRG 0 +#define CONFIG_IO_13_PD_SLW_RT 0 +#define CONFIG_IO_13_PU_DRV_STRG 0 +#define CONFIG_IO_13_PU_SLW_RT 0 +#define CONFIG_IO_13_RTRIM 1 +#define CONFIG_IO_13_WK_PU_EN 1 +#define CONFIG_IO_14_INPUT_BUF_EN 0 +#define CONFIG_IO_14_PD_DRV_STRG 0 +#define CONFIG_IO_14_PD_SLW_RT 0 +#define CONFIG_IO_14_PU_DRV_STRG 0 +#define CONFIG_IO_14_PU_SLW_RT 0 +#define CONFIG_IO_14_RTRIM 1 +#define CONFIG_IO_14_WK_PU_EN 1 +#define CONFIG_IO_15_INPUT_BUF_EN 0 +#define CONFIG_IO_15_PD_DRV_STRG 0 +#define CONFIG_IO_15_PD_SLW_RT 0 +#define CONFIG_IO_15_PU_DRV_STRG 0 +#define CONFIG_IO_15_PU_SLW_RT 0 +#define CONFIG_IO_15_RTRIM 1 +#define CONFIG_IO_15_WK_PU_EN 1 +#define CONFIG_IO_16_INPUT_BUF_EN 0 +#define CONFIG_IO_16_PD_DRV_STRG 10 +#define
[PATCH v3 01/11] arm: dts: Add Mercury+ AA1 devicetrees
Devicetree headers for Mercury+ AA1 module
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
.../socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 ++
arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++
2 files changed, 126 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
new file mode 100644
index 00..365e05100a
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = <_loader0>;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = < 1>;
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+_mgr {
+ u-boot,dm-pre-reloc;
+ altr,bitstream = "fpga.itb";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+_sdmmc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+_sdmmc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
new file mode 100644
index 00..fee1fc39bb
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10.dtsi"
+
+/ {
+ aliases {
+ ethernet0 =
+ serial1 =
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x8000>; /* 2GB */
+ };
+};
+
+ {
+ phy-mode = "rgmii";
+ phy-handle = <>;
+
+ max-frame-size = <3800>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+
+ {
+ atsha204a: atsha204a@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+
+ isl12022: isl12022@6f {
+ compatible = "isil,isl12022";
+ reg = <0x6f>;
+ };
+};
+
+ {
+ cap-sd-highspeed;
+ broken-cd;
+ bus-width = <4>;
+};
+
+ {
+ clock-frequency = <>;
+};
--
2.36.1.476.g0c4daa206d-goog
[PATCH v3 00/11] Add Chameleon v3 support
The Google Chameleon v3 is a board made for testing both video and audio interfaces of external devices. It has a connector compatible with the Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The AA1 module comes in a few different configurations, the Chameleon V3 supports ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E. This patchset adds support for the Chameleon v3 (both versions), as well as some bugfixes and optimizations, mostly in Arria 10 code. V3: Move clock manager changes out of socfpga-generic code (aarch64 compilation issue) V2: Adjust devicetrees so that they work both in u-boot and linux Put u-boot-specific parts of devicetrees into *-u-boot.dtsi files Minor changes in Kconfig, defconfig, and config.h Paweł Anikiel (11): arm: dts: Add Mercury+ AA1 devicetrees arm: dts: Add Chameleonv3 handoff headers arm: dts: Add Chameleonv3 devicetrees board: Add Chameleonv3 board dir config: Add Chameleonv3 config misc: atsha204a: Increase wake delay by tWHI sysreset: socfpga: Use parent device for reading base address socfpga: arria10: Replace delays with busy waiting in cm_full_cfg socfpga: arria10: Improve bitstream loading speed socfpga: arria10: Wait for fifo empty after writing bitstream socfpga: arria10: Allow dcache_enable before relocation arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 ++ ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi | 8 + .../dts/socfpga_arria10_chameleonv3_270_3.dts | 5 + ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++ ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi | 8 + .../dts/socfpga_arria10_chameleonv3_480_2.dts | 5 + ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++ .../socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 + arch/arm/mach-socfpga/Kconfig | 7 + arch/arm/mach-socfpga/clock_manager_arria10.c | 31 +- arch/arm/mach-socfpga/misc_arria10.c | 26 ++ board/google/chameleonv3/Makefile | 5 + board/google/chameleonv3/board.c | 27 ++ board/google/chameleonv3/fpga.its | 28 ++ board/google/chameleonv3/fpga_early_io.its| 35 ++ board/google/chameleonv3/mercury_aa1.c| 43 +++ board/google/chameleonv3/mercury_aa1.h| 12 + configs/socfpga_chameleonv3_defconfig | 29 ++ drivers/fpga/socfpga_arria10.c| 28 +- drivers/misc/atsha204a-i2c.c | 5 +- drivers/sysreset/sysreset_socfpga.c | 2 +- include/configs/socfpga_chameleonv3.h | 44 +++ 24 files changed, 1162 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi create mode 100644 board/google/chameleonv3/Makefile create mode 100644 board/google/chameleonv3/board.c create mode 100644 board/google/chameleonv3/fpga.its create mode 100644 board/google/chameleonv3/fpga_early_io.its create mode 100644 board/google/chameleonv3/mercury_aa1.c create mode 100644 board/google/chameleonv3/mercury_aa1.h create mode 100644 configs/socfpga_chameleonv3_defconfig create mode 100644 include/configs/socfpga_chameleonv3.h -- 2.36.1.476.g0c4daa206d-goog
Re: [PATCH 04/10] xilinx: zynqmp: Use soc machine function to get silicon idcode name
On 6/8/22 18:20, Stefan Herbrechtsmeier wrote:
[CAUTION: External Email]
From: Stefan Herbrechtsmeier
Use the soc_get_machine function of the soc uclass to get silicon idcode
name for the fpga init.
Signed-off-by: Stefan Herbrechtsmeier
---
board/xilinx/zynqmp/zynqmp.c | 287 ++-
1 file changed, 15 insertions(+), 272 deletions(-)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index e311aa772c..06f6dbab18 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -44,278 +45,10 @@
#include "pm_cfg_obj.h"
-#define ZYNQMP_VERSION_SIZE7
-#define EFUSE_VCU_DIS_MASK 0x100
-#define EFUSE_VCU_DIS_SHIFT8
-#define EFUSE_GPU_DIS_MASK 0x20
-#define EFUSE_GPU_DIS_SHIFT5
-#define IDCODE2_PL_INIT_MASK 0x200
-#define IDCODE2_PL_INIT_SHIFT 9
-
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
-
-enum {
- ZYNQMP_VARIANT_EG = BIT(0U),
- ZYNQMP_VARIANT_EV = BIT(1U),
- ZYNQMP_VARIANT_CG = BIT(2U),
- ZYNQMP_VARIANT_DR = BIT(3U),
-};
-
-static const struct {
- u32 id;
- u8 device;
- u8 variants;
-} zynqmp_devices[] = {
- {
- .id = 0x04688093,
- .device = 1,
- .variants = ZYNQMP_VARIANT_EG,
- },
- {
- .id = 0x04711093,
- .device = 2,
- .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
- },
- {
- .id = 0x04710093,
- .device = 3,
- .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
- },
- {
- .id = 0x04721093,
- .device = 4,
- .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
- ZYNQMP_VARIANT_EV,
- },
- {
- .id = 0x04720093,
- .device = 5,
- .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
- ZYNQMP_VARIANT_EV,
- },
- {
- .id = 0x04739093,
- .device = 6,
- .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
- },
- {
- .id = 0x04730093,
- .device = 7,
- .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
- ZYNQMP_VARIANT_EV,
- },
- {
- .id = 0x04738093,
- .device = 9,
- .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
- },
- {
- .id = 0x04740093,
- .device = 11,
- .variants = ZYNQMP_VARIANT_EG,
- },
- {
- .id = 0x04750093,
- .device = 15,
- .variants = ZYNQMP_VARIANT_EG,
- },
- {
- .id = 0x04759093,
- .device = 17,
- .variants = ZYNQMP_VARIANT_EG,
- },
- {
- .id = 0x04758093,
- .device = 19,
- .variants = ZYNQMP_VARIANT_EG,
- },
- {
- .id = 0x047E1093,
- .device = 21,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047E3093,
- .device = 23,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047E5093,
- .device = 25,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047E4093,
- .device = 27,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047E0093,
- .device = 28,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047E2093,
- .device = 29,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047E6093,
- .device = 39,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047FD093,
- .device = 43,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047F8093,
- .device = 46,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047FF093,
- .device = 47,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047FB093,
- .device = 48,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x047FE093,
- .device = 49,
- .variants = ZYNQMP_VARIANT_DR,
- },
- {
- .id = 0x046d0093,
- .device = 67,
- .variants = ZYNQMP_VARIANT_DR,
- },
-};
-
-static const struct {
- u32 id;
- char *name;
Re: [PATCH 03/10] soc: xilinx: zynqmp: Add machine identification support
On 6/8/22 18:20, Stefan Herbrechtsmeier wrote:
[CAUTION: External Email]
From: Stefan Herbrechtsmeier
Add machine identification support based on the
zynqmp_get_silicon_idcode_name function in board/xilinx/zynqmp/zynqmp.c.
Signed-off-by: Stefan Herbrechtsmeier
---
drivers/soc/soc_xilinx_zynqmp.c | 289 +++-
1 file changed, 286 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index a71115b17c..45592ed534 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -3,10 +3,15 @@
* Xilinx ZynqMP SOC driver
*
* Copyright (C) 2021 Xilinx, Inc.
+ * Michal Simek
+ *
+ * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
+ * Stefan Herbrechtsmeier
*/
#include
#include
+#include
#include
#include
#include
@@ -20,13 +25,260 @@
* v2 -> 2(XCZU7EV-ES1, XCZU9EG-ES2, XCZU19EG-ES1)
* v3 -> 3(Production Level)
*/
-static const char zynqmp_family[] = "ZynqMP";
please keep this in origin location.
+
+#define EFUSE_VCU_DIS_SHIFT8
+#define EFUSE_VCU_DIS_MASK BIT(EFUSE_VCU_DIS_SHIFT)
+#define EFUSE_GPU_DIS_SHIFT5
+#define EFUSE_GPU_DIS_MASK BIT(EFUSE_GPU_DIS_SHIFT)
+#define IDCODE2_PL_INIT_SHIFT 9
+#define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT)
+
+#define ZYNQMP_VERSION_SIZE7
+
+enum {
+ ZYNQMP_VARIANT_EG = BIT(0),
+ ZYNQMP_VARIANT_EV = BIT(1),
+ ZYNQMP_VARIANT_CG = BIT(2),
+ ZYNQMP_VARIANT_DR = BIT(3),
+};
+
+struct zynqmp_device {
+ u32 id;
+ u8 device;
+ u8 variants;
+};
struct soc_xilinx_zynqmp_priv {
const char *family;
+ char machine[ZYNQMP_VERSION_SIZE];
char revision;
};
+static struct zynqmp_device zynqmp_devices[] = {
+ {
+ .id = 0x04688093,
+ .device = 1,
+ .variants = ZYNQMP_VARIANT_EG,
+ },
+ {
+ .id = 0x04711093,
+ .device = 2,
+ .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+ },
+ {
+ .id = 0x04710093,
+ .device = 3,
+ .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+ },
+ {
+ .id = 0x04721093,
+ .device = 4,
+ .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+ ZYNQMP_VARIANT_EV,
+ },
+ {
+ .id = 0x04720093,
+ .device = 5,
+ .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+ ZYNQMP_VARIANT_EV,
+ },
+ {
+ .id = 0x04739093,
+ .device = 6,
+ .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+ },
+ {
+ .id = 0x04730093,
+ .device = 7,
+ .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+ ZYNQMP_VARIANT_EV,
+ },
+ {
+ .id = 0x04738093,
+ .device = 9,
+ .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+ },
+ {
+ .id = 0x04740093,
+ .device = 11,
+ .variants = ZYNQMP_VARIANT_EG,
+ },
+ {
+ .id = 0x04750093,
+ .device = 15,
+ .variants = ZYNQMP_VARIANT_EG,
+ },
+ {
+ .id = 0x04759093,
+ .device = 17,
+ .variants = ZYNQMP_VARIANT_EG,
+ },
+ {
+ .id = 0x04758093,
+ .device = 19,
+ .variants = ZYNQMP_VARIANT_EG,
+ },
+ {
+ .id = 0x047E1093,
+ .device = 21,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+ .id = 0x047E3093,
+ .device = 23,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+ .id = 0x047E5093,
+ .device = 25,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+ .id = 0x047E4093,
+ .device = 27,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+ .id = 0x047E0093,
+ .device = 28,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+ .id = 0x047E2093,
+ .device = 29,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+ .id = 0x047E6093,
+ .device = 39,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+ .id = 0x047FD093,
+ .device = 43,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+ .id = 0x047F8093,
+ .device = 46,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+ .id = 0x047FF093,
+ .device = 47,
+ .variants = ZYNQMP_VARIANT_DR,
+ },
+ {
+
[PATCH] disk: part: change from hextoul to dectoul
When 'ls' command is running with partition number, it's passed by a hex
value. For example, if want to check a 15th partition, it has to input
as 0xf.
Before applied
- ls mmc 0:f
After applied
- ls mmc 0:15
The using decimal number is more readable than passed by a hex value.
Signed-off-by: Jaehoon Chung
---
disk/part.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disk/part.c b/disk/part.c
index 79955c7fb000..31a42d8a2312 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -540,7 +540,7 @@ int blk_get_device_part_str(const char *ifname, const char
*dev_part_str,
part = PART_AUTO;
} else {
/* Something specified -> use exactly that */
- part = (int)hextoul(part_str, );
+ part = (int)dectoul(part_str, );
/*
* Less than whole string converted,
* or request for whole device, but caller requires partition.
--
2.25.1
Re: [PATCH] stm32mp1: fix reference for STMicroelectronics
Hi, On 5/20/22 18:38, Patrick Delaunay wrote: Replace reference to the correct name STMicroelectronics Signed-off-by: Patrick Delaunay --- arch/arm/Kconfig | 2 +- arch/arm/cpu/armv7/stv0991/lowlevel.S | 2 +- arch/arm/mach-sti/Kconfig | 2 +- drivers/i2c/designware_i2c.c | 2 +- drivers/i2c/designware_i2c.h | 2 +- drivers/i2c/designware_i2c_pci.c | 2 +- drivers/mtd/nand/raw/fsmc_nand.c | 4 ++-- drivers/mtd/spi/spi-nor-ids.c | 2 +- drivers/net/designware.c | 2 +- drivers/net/designware.h | 2 +- drivers/pinctrl/Kconfig | 2 +- drivers/spi/pl022_spi.c | 2 +- drivers/usb/gadget/designware_udc.c | 2 +- include/configs/stm32mp15_st_common.h | 2 +- include/elf.h | 4 ++-- include/linux/mtd/fsmc_nand.h | 2 +- include/usb/designware_udc.h | 2 +- 17 files changed, 19 insertions(+), 19 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH v2] configs: stm32mp: cleanup the stm32mp15 file
Hi, On 6/15/22 19:41, Patrick Delaunay wrote: Remove STM32_SYSRAM_END and clean the comments in stm32mp15_common.h file after moving some CONFIG to Kconfig: CONFIG_SYS_CBSIZE, CONFIG_SPL_MAX_FOOTPRINT, CONFIG_SYS_SPL_MALLOC_START and CONFIG_SYS_SPL_MALLOC_SIZE. Signed-off-by: Patrick Delaunay --- Changes in v2: - remove the define STM32_SYSRAM_END, no more used include/configs/stm32mp15_common.h | 11 --- 1 file changed, 11 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH] stm32mp: stpmic1: remove the debug unit request by debugger
Hi, On 6/1/22 18:33, Patrick Delaunay wrote: Depending on backup register value, U-Boot SPL maintains the debug unit powered-on for debugging purpose; only BUCK1 is required for powering the debug unit, so revert the setting for all the other power lanes, except BUCK3 that has to be always on. To be functional this patch requires a modification in the debugger ,openocd for example, to update the STM32MP15 backup register when it is required to debug SPL after reset. After deeper analysis this behavior will be never supported in tools so the associated code, will be never used and the associated code can be removed. Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/include/mach/stm32.h | 1 - board/st/common/stpmic1.c | 14 -- include/power/stpmic1.h| 3 --- 3 files changed, 18 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH v1 2/2] ARM: stm32: activate OF_LIVE for DHSOM
Hi, On 6/6/22 16:04, Patrick Delaunay wrote: Activate the live DT with CONFIG_OF_LIVE to reduce the DT parsing time. Tested-by: Marek Vasut Signed-off-by: Patrick Delaunay --- Changes in v1: - previously sent as RFC, Tested by Marek http://patchwork.ozlabs.org/project/uboot/list/?series=301157 configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_dhcor_basic_defconfig | 1 + 2 files changed, 2 insertions(+) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH v1 1/2] board: dhelectronics: stm32mp1: convert to livetree
Hi, On 6/6/22 16:04, Patrick Delaunay wrote: Replace call to fdt_*() functions and access to gd->fdt_blob with call to ofnode_*() functions to support a live tree. Tested-by: Marek Vasut Signed-off-by: Patrick Delaunay --- Changes in v1: - previously sent as RFC, Tested by Marek http://patchwork.ozlabs.org/project/uboot/list/?series=301157 board/dhelectronics/dh_stm32mp1/board.c | 38 +++-- 1 file changed, 16 insertions(+), 22 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 2/2] board: engicam: stm32mp1: convert to livetree
Hi, On 5/19/22 09:07, Patrick Delaunay wrote: Replace gd->fdt_blob access with fdt_getprop() function to the function ofnode_get_property() to support a live tree. Signed-off-by: Patrick Delaunay --- board/engicam/stm32mp1/stm32mp1.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 1/2] board: stm32mp1: convert to livetree
Hi, On 5/19/22 09:07, Patrick Delaunay wrote: Replace gd->fdt_blob access with fdt_getprop() function to the function ofnode_get_property() to support a live tree. Signed-off-by: Patrick Delaunay --- board/st/stm32mp1/stm32mp1.c | 13 - 1 file changed, 4 insertions(+), 9 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH v3 3/3] ARM: dts: stm32: add rcc node for STM32MP13
Hi, On 6/2/22 15:05, Patrick Delaunay wrote: Add the RCC node, not yet in Linux kernel device tree to handle the U-Boot RCC drivers with the needed U-Boot property "u-boot,dm-pre-reloc" property as the clock and reset drivers are required during pre-location. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- (no changes since v1) arch/arm/dts/stm32mp13-u-boot.dtsi | 4 arch/arm/dts/stm32mp131.dtsi | 7 +++ 2 files changed, 11 insertions(+) This patch is no more needed, it is dropped until final RCC clock driver support to avoid a probe issue on STM32MP13F-DK board : stm32-rcc rcc@5000: Cannot find driver 'stm32mp13_clk' Patrick
Re: [PATCH v3 2/3] misc: stm32mp13: introduce STM32MP13 RCC driver
Hi, On 6/2/22 15:05, Patrick Delaunay wrote: Add the MISC RCC driver for STM32MP13, and bind it to the RCC reset driver, required for initial support. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- (no changes since v1) drivers/misc/stm32_rcc.c | 6 ++ 1 file changed, 6 insertions(+) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH v3 1/3] clk: Add directory for STM32 clock drivers
Hi,
On 6/2/22 15:05, Patrick Delaunay wrote:
Add a directory in drivers/clk to regroup the clock drivers for all
STM32 SoCs with CONFIG_ARCH_STM32 (MCUs with Cortex-M) or
CONFIG_ARCH_STM32MP (MPUs with Cortex-A).
Signed-off-by: Patrick Delaunay
Reviewed-by: Grzegorz Szymaszek
Reviewed-by: Patrice Chotard
---
Changes in v3:
- Some nits in commit message (s/Soc/SoCs/ & s/cortex /Cortex-/)
Changes in v2:
- replace '_' by '-' in file names to be consistant with other clk drivers
and prepare introduction of new files for stm32mp13
MAINTAINERS | 2 +-
drivers/clk/Kconfig | 17 +-
drivers/clk/Makefile | 5 ++--
drivers/clk/stm32/Kconfig | 23 +++
drivers/clk/stm32/Makefile| 7 ++
.../clk/{clk_stm32f.c => stm32/clk-stm32f.c} | 0
.../{clk_stm32h7.c => stm32/clk-stm32h7.c}| 0
.../{clk_stm32mp1.c => stm32/clk-stm32mp1.c} | 0
8 files changed, 34 insertions(+), 20 deletions(-)
create mode 100644 drivers/clk/stm32/Kconfig
create mode 100644 drivers/clk/stm32/Makefile
rename drivers/clk/{clk_stm32f.c => stm32/clk-stm32f.c} (100%)
rename drivers/clk/{clk_stm32h7.c => stm32/clk-stm32h7.c} (100%)
rename drivers/clk/{clk_stm32mp1.c => stm32/clk-stm32mp1.c} (100%)
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Re: [PATCH 2/2] stm32mp: fdt: update etzpc for STM32MP13x
Hi, On 5/9/22 17:13, Patrick Delaunay wrote: Add support of STM32MP13x the ETZPC part of fdt.c Signed-off-by: Patrick Delaunay Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/fdt.c | 153 +++- 1 file changed, 151 insertions(+), 2 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 1/2] stm32mp: fdt: update etzpc for STM32MP15x
Hi, On 5/9/22 17:13, Patrick Delaunay wrote: Introduce STM32MP15 function and defines to prepare the STM32MP13 introduction. Signed-off-by: Patrick Delaunay Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/fdt.c | 123 1 file changed, 67 insertions(+), 56 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 16/16] doc: st: stm32mp1: add STM32MP13x support
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Add in U-Boot documentation the quick instruction for setup the STMicroelectronics STM32MP13x boards. Signed-off-by: Patrick Delaunay --- doc/board/st/stm32mp1.rst | 181 ++ 1 file changed, 125 insertions(+), 56 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 15/16] configs: add stm32mp13 defconfig
Hi some adaptation for Kconfig migration in next branch On 5/6/22 16:06, Patrick Delaunay wrote: Add a initial config for STM32M13x SOC family, using the stm32mp135f-dk device tree. Signed-off-by: Patrick Delaunay --- board/st/stm32mp1/MAINTAINERS | 1 + configs/stm32mp13_defconfig | 54 +++ 2 files changed, 55 insertions(+) create mode 100644 configs/stm32mp13_defconfig diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index c9252e90f4..d5a09cdc39 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -6,6 +6,7 @@ S: Maintained F:arch/arm/dts/stm32mp13* F:arch/arm/dts/stm32mp15* F:board/st/stm32mp1/ +F: configs/stm32mp13_defconfig F:configs/stm32mp15_defconfig F:configs/stm32mp15_basic_defconfig F:configs/stm32mp15_trusted_defconfig diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig new file mode 100644 index 00..877c020b4a --- /dev/null +++ b/configs/stm32mp13_defconfig @@ -0,0 +1,54 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_TFABOOT=y +CONFIG_SYS_MALLOC_F_LEN=0x18 +CONFIG_ENV_OFFSET=0x90 +CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk" +CONFIG_STM32MP13x=y +CONFIG_DDR_CACHEABLE_SIZE=0x1000 +CONFIG_TARGET_ST_STM32MP13x=y +CONFIG_ENV_OFFSET_REDUND=0x94 +# CONFIG_ARMV7_NONSEC is not set +CONFIG_SYS_LOAD_ADDR=0xc200 +CONFIG_SYS_MEMTEST_START=0xc000 +CONFIG_SYS_MEMTEST_END=0xc400 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=1 +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_CMD_ADTIMG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_LOG=y +CONFIG_OF_LIVE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_CLK_SCMI=y +CONFIG_STM32_SDMMC2=y +CONFIG_DM_ETH=y +CONFIG_PINCONF=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_SCMI=y +CONFIG_RESET_SCMI=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_SYSRESET_PSCI=y +CONFIG_TEE=y +CONFIG_OPTEE=y +# CONFIG_OPTEE_TA_AVB is not set +CONFIG_ERRNO_STR=y +# CONFIG_LMB_USE_MAX_REGIONS is not set +CONFIG_LMB_MEMORY_REGIONS=2 +CONFIG_LMB_RESERVED_REGIONS=16 with +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc040 Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 14/16] arm: dts: stm32mp: add stm32mp13 device tree for U-Boot
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Compile the device tree of STM32MP13x boards and add the needed U-Boot add-on. Signed-off-by: Patrick Delaunay --- arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp13-u-boot.dtsi | 91 + arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 30 3 files changed, 124 insertions(+) create mode 100644 arch/arm/dts/stm32mp13-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp135f-dk-u-boot.dtsi Applied to u-boot-stm/next, thanks! Regards Patrick
Pull request: SoCFPGA changes for commit c18e5fb055ab
Hi Tom, Please pull the SoCFPGA changes as shown in below. Thanks. Best regards, Tien Fong The following changes since commit c18e5fb055ab789f58434e3cb432582adee0134c: dtoc: Update test_src_scan.py for new tegra compatibles (2022-06-14 13:59:23 -0400) are available in the Git repository at: https://github.com/tienfong/uboot_mainline.git 32e0379143b433e29d76404f5f4c279067e48853 for you to fetch changes up to 32e0379143b433e29d76404f5f4c279067e48853: ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched (2022-06-17 16:27:05 +0800) Dinesh Maniyam (5): arch: arm: socfpga: timer_s10: Override udelay for secure section arm: dts: socfpga: agilex: Add freeze controller node arm: dts: socfpga: stratix10: Add freeze controller node drivers: cache: ncore: Disable snoop filter ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched Marek Vasut (1): arm: socfpga: vining: Unmount UBIFS and detach UBI in ubi_load script Tien Fong Chee (3): intel: n5x: ddr: update license ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS ddr: altera: Stratix10: Use phys_size_t for memory size Yau Wai Gan (1): arm: dts: socfpga: stratix10: Update MMC smplsel value arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi| 11 ++- arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11 ++- arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +- arch/arm/mach-socfpga/timer_s10.c| 34 +- drivers/cache/cache-ncore.c | 6 +++--- drivers/ddr/altera/sdram_n5x.c | 4 ++-- drivers/ddr/altera/sdram_s10.c | 4 ++-- drivers/ddr/altera/sdram_soc64.c | 5 +++-- drivers/ddr/altera/sdram_soc64.h | 2 +- include/configs/socfpga_vining_fpga.h| 3 ++- 10 files changed, 67 insertions(+), 15 deletions(-)
Re: [PATCH 13/16] mmc: stm32_sdmmc2: make reset property optional
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Although not recommended, the reset property could be made optional. This way the driver will probe even if no reset property is provided in an sdmmc node in DT. This reset is already optional in Linux. Signed-off-by: Yann Gautier Signed-off-by: Patrick Delaunay --- drivers/mmc/stm32_sdmmc2.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 12/16] ram: stm32mp1: add support of STM32MP13x
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Add support for new compatible "st,stm32mp13-ddr" to manage the DDR sub system (Controller and PHY) in STM32MP13x SOC: - only one AXI port - support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2) The STM32MP15x SOC have 2 AXI ports and 32 bits support. Signed-off-by: Patrick Delaunay --- .../memory-controllers/st,stm32mp1-ddr.txt| 49 +++ drivers/ram/stm32mp1/stm32mp1_ram.c | 28 +++ 2 files changed, 57 insertions(+), 20 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 11/16] board: stm32pm1: add stm32mp13 board support
Hi,
Accepted with minor modification.
On 5/6/22 16:06, Patrick Delaunay wrote:
Add stm32mp15x prefix to all STM32MP15x board specific function,
this patch is a preliminary step for STM32MP13x support.
This patch also add the RCC probe to avoid circular access with
usbphyc probe as clk provider.
Signed-off-by: Patrick Delaunay
---
board/st/stm32mp1/stm32mp1.c | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index fff1880e5b..4ba7201ffb 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -547,8 +547,7 @@ static void sysconf_init(void)
clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
}
-/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
-static int dk2_i2c1_fix(void)
+static int board_stm32mp15x_dk2_init(void)
{
ofnode node;
struct gpio_desc hdmi, audio;
@@ -557,6 +556,7 @@ static int dk2_i2c1_fix(void)
if (!IS_ENABLED(CONFIG_DM_REGULATOR))
return -ENODEV;
+ /* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
if (!ofnode_valid(node)) {
log_debug("no hdmi-transmitter@39 ?\n");
@@ -604,7 +604,7 @@ error:
return ret;
}
-static bool board_is_dk2(void)
+static bool board_is_stm32mp15x_dk2(void)
{
if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
of_machine_is_compatible("st,stm32mp157c-dk2"))
@@ -613,7 +613,7 @@ static bool board_is_dk2(void)
return false;
}
-static bool board_is_ev1(void)
+static bool board_is_stm32mp15x_ev1(void)
{
if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
(of_machine_is_compatible("st,stm32mp157a-ev1") ||
@@ -637,7 +637,7 @@ U_BOOT_DRIVER(goodix) = {
.of_match = goodix_ids,
};
-static void board_ev1_init(void)
+static void board_stm32mp15x_ev1_init(void)
{
struct udevice *dev;
@@ -648,13 +648,22 @@ static void board_ev1_init(void)
/* board dependent setup after realloc */
int board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ /* probe RCC to avoid circular access with usbphyc probe as clk
provider */
+ if (IS_ENABLED(CONFIG_CLK_STM32MP13)) {
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(stm32mp1_clock), );
+ log_debug("Clock init failed: %d\n", ret);
+ }
+
=> this force RCC probed removed to avoid issue when RCC node is not
present in
device tree
can be replaced by DM_FLAG_PROBE_AFTER_BIND managed in RCC driver.
board_key_check();
- if (board_is_ev1())
- board_ev1_init();
+ if (board_is_stm32mp15x_ev1())
+ board_stm32mp15x_ev1_init();
- if (board_is_dk2())
- dk2_i2c1_fix();
+ if (board_is_stm32mp15x_dk2())
+ board_stm32mp15x_dk2_init();
if (IS_ENABLED(CONFIG_DM_REGULATOR))
regulators_enable_boot_on(_DEBUG);
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Re: [PATCH 10/16] pinctrl: stm32: add support of STM32MP135
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Add support for "st,stm32mp135-pinctrl" for STM32MP13x Signed-off-by: Patrick Delaunay --- drivers/pinctrl/pinctrl_stm32.c | 1 + 1 file changed, 1 insertion(+) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 09/16] arm: stm32mp: support 2 MAC address for STM32MP13
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Add support of several MAC address in OTP (3 32bits OTP word for 2 MAC address) for SOCs in STM32MP13x family: STM32MP133 and STM32MP135. Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/cpu.c | 41 --- .../arm/mach-stm32mp/include/mach/sys_proto.h | 1 + arch/arm/mach-stm32mp/stm32mp13x.c| 20 + arch/arm/mach-stm32mp/stm32mp15x.c| 5 +++ 4 files changed, 52 insertions(+), 15 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 08/16] arm: stm32mp: add support of STM32MP13x
Hi,
Some ad
On 5/6/22 16:06, Patrick Delaunay wrote:
Introduce the code in mach-stm32mp and the configuration file
stm32mp13_defconfig for the new STM32MP family.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig | 21 +++-
arch/arm/mach-stm32mp/Kconfig.13x | 57 +
arch/arm/mach-stm32mp/Makefile| 1 +
arch/arm/mach-stm32mp/cpu.c | 3 +
arch/arm/mach-stm32mp/fdt.c | 3 +
arch/arm/mach-stm32mp/include/mach/stm32.h| 26
.../arm/mach-stm32mp/include/mach/sys_proto.h | 16 ++-
arch/arm/mach-stm32mp/stm32mp13x.c| 115 ++
board/st/stm32mp1/Kconfig | 15 +++
board/st/stm32mp1/MAINTAINERS | 2 +
configs/stm32mp15_basic_defconfig | 2 +-
configs/stm32mp15_defconfig | 2 +-
configs/stm32mp15_trusted_defconfig | 2 +-
include/configs/stm32mp13_common.h| 106
include/configs/stm32mp13_st_common.h | 17 +++
include/configs/stm32mp15_common.h| 4 +-
16 files changed, 385 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/mach-stm32mp/Kconfig.13x
create mode 100644 arch/arm/mach-stm32mp/stm32mp13x.c
create mode 100644 include/configs/stm32mp13_common.h
create mode 100644 include/configs/stm32mp13_st_common.h
[...]
diff --git a/include/configs/stm32mp13_common.h
b/include/configs/stm32mp13_common.h
new file mode 100644
index 00..799e3f053b
--- /dev/null
+++ b/include/configs/stm32mp13_common.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP15x CPU
+ */
+
+#ifndef __CONFIG_STM32MP13_COMMMON_H
+#define __CONFIG_STM32MP13_COMMMON_H
+#include
+#include
+
+/*
+ * Configuration of the external SRAM memory used by U-Boot
+ */
+#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
+#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE + SZ_4M)
=> CONFIG_SYS_INIT_SP_ADDR remove and moved in Kconfig
+
+/*
+ * Console I/O buffer size
+ */
+#define CONFIG_SYS_CBSIZE SZ_1K
=> CONFIG_SYS_CBSIZE removed and moved in Kconfig
+
+/*
+ * For booting Linux, use the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN SZ_32M
+
+/*MMC SD*/
+#define CONFIG_SYS_MMC_MAX_DEVICE 2
+
+/* NAND support */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/*/
+#ifdef CONFIG_DISTRO_DEFAULTS
+/*/
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0)
+#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1)
+#else
+#define BOOT_TARGET_MMC0(func)
+#define BOOT_TARGET_MMC1(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_MMC1(func) \
+ BOOT_TARGET_MMC0(func)
+
+/*
+ * default bootcmd for stm32mp13:
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ */
+#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
+ "echo \"Boot over ${boot_device}${boot_instance}!\";" \
+ "run env_check;" \
+ "if test ${boot_device} = mmc;" \
+ "then env set boot_targets \"mmc${boot_instance}\"; fi;" \
+ "run distro_bootcmd;" \
+ "fi;\0"
+
+#define STM32MP_EXTRA \
+ "env_check=if env info -p -d -q; then env save; fi\0" \
+ "boot_net_usb_start=true\0"
+
+#ifndef STM32MP_BOARD_EXTRA_ENV
+#define STM32MP_BOARD_EXTRA_ENV
+#endif
+
+#include
+
+/*
+ * memory layout for 32M uncompressed/compressed kernel,
+ * 1M fdt, 1M script, 1M pxe and 1M for overlay
+ * and the ramdisk at the end.
+ */
+#define __KERNEL_ADDR_R __stringify(0xc200)
+#define __FDT_ADDR_R__stringify(0xc400)
+#define __SCRIPT_ADDR_R __stringify(0xc410)
+#define __PXEFILE_ADDR_R__stringify(0xc420)
+#define __FDTOVERLAY_ADDR_R __stringify(0xc430)
+#define __RAMDISK_ADDR_R__stringify(0xc440)
+
+#define STM32MP_MEM_LAYOUT \
+ "kernel_addr_r=" __KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" __FDT_ADDR_R "\0" \
+ "scriptaddr=" __SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \
+ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \
+ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ STM32MP_MEM_LAYOUT \
+ STM32MP_BOOTCMD \
+ BOOTENV \
+ STM32MP_EXTRA \
+ STM32MP_BOARD_EXTRA_ENV
+
+#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
+
+#endif /* __CONFIG_STM32MP13_COMMMON_H */
Re: [PATCH 07/16] arm: stm32mp: add CONFIG_STM32MP15_PWR
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Add config CONFIG_STM32MP15_PWR to handle the access on regulators managed by the PWR driver defined in pwr_regulator.c This driver is only used in U-Boot by STM32MP15x family. Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/Kconfig.15x | 16 arch/arm/mach-stm32mp/Makefile| 2 +- 2 files changed, 17 insertions(+), 1 deletion(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 06/16] arm: stm32mp: add sub config Kconfig.15x
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Add sub Kconfig for each SOC in the STM32 CPU family. It is a preliminary step to introduce a new SOC in the STM32MP family. Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/Kconfig | 119 +--- arch/arm/mach-stm32mp/Kconfig.15x | 119 configs/stm32mp15_basic_defconfig | 2 +- configs/stm32mp15_defconfig | 4 +- configs/stm32mp15_trusted_defconfig | 4 +- 5 files changed, 125 insertions(+), 123 deletions(-) create mode 100644 arch/arm/mach-stm32mp/Kconfig.15x Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 05/16] arm: stm32mp: add choice for STM32MP SOC family
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Add mandatory choice for SOC support in ARCH_STM32MP. This patch is a preliminary step for new SOC introduction in STM32MP family. Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/Kconfig | 23 +-- configs/stm32mp15_basic_defconfig | 4 ++-- configs/stm32mp15_defconfig | 4 ++-- configs/stm32mp15_trusted_defconfig | 4 ++-- 4 files changed, 19 insertions(+), 16 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 04/16] arm: stm32mp: move code for STM32MP15x
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c when low level init without TFABOOT is supported. Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/Makefile| 2 + arch/arm/mach-stm32mp/cpu.c | 331 + arch/arm/mach-stm32mp/fdt.c | 8 +- .../arm/mach-stm32mp/include/mach/sys_proto.h | 14 +- arch/arm/mach-stm32mp/spl.c | 1 + arch/arm/mach-stm32mp/stm32mp15x.c| 345 ++ 6 files changed, 377 insertions(+), 324 deletions(-) create mode 100644 arch/arm/mach-stm32mp/stm32mp15x.c Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 03/16] arm: stm32mp: move the get_otp helper function in bsec
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: As the get_otp() helper function in bsec are common for all STM32MP family, move this function in bsec driver Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/bsec.c | 17 + arch/arm/mach-stm32mp/cpu.c| 17 - arch/arm/mach-stm32mp/include/mach/sys_proto.h | 3 +++ 3 files changed, 20 insertions(+), 17 deletions(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 02/16] configs: stm32mp1: move SUPPORT_SPL in STM32MP15x
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: The SPL is only supported by STM32MP15x not by all the SOC with STM32MP arch. Only TFABOOT is supported in next products. Signed-off-by: Patrick Delaunay Signed-off-by: Patrick Delaunay --- arch/arm/Kconfig | 1 - arch/arm/mach-stm32mp/Kconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH 01/16] ARM: dts: stm32: add STM32MP13 SoCs support
Hi, On 5/6/22 16:06, Patrick Delaunay wrote: Add initial support of STM32MP13 family based on v5.18-rc2 Signed-off-by: Patrick Delaunay --- arch/arm/dts/stm32mp13-pinctrl.dtsi | 123 ++ arch/arm/dts/stm32mp131.dtsi| 358 arch/arm/dts/stm32mp133.dtsi| 37 +++ arch/arm/dts/stm32mp135.dtsi| 12 + arch/arm/dts/stm32mp135f-dk.dts | 57 + arch/arm/dts/stm32mp13xc.dtsi | 17 ++ arch/arm/dts/stm32mp13xf.dtsi | 17 ++ board/st/stm32mp1/MAINTAINERS | 1 + 8 files changed, 622 insertions(+) create mode 100644 arch/arm/dts/stm32mp13-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp131.dtsi create mode 100644 arch/arm/dts/stm32mp133.dtsi create mode 100644 arch/arm/dts/stm32mp135.dtsi create mode 100644 arch/arm/dts/stm32mp135f-dk.dts create mode 100644 arch/arm/dts/stm32mp13xc.dtsi create mode 100644 arch/arm/dts/stm32mp13xf.dtsi Applied to u-boot-stm/next, thanks! Regards Patrick
Re: [PATCH v5 11/23] mkeficapsule: Add support for generating empty capsules
Takahiro, On Fri, 17 Jun 2022 at 06:16, Takahiro Akashi wrote: > > Sughosh, > > On Thu, Jun 16, 2022 at 12:42:08PM +0530, Sughosh Ganu wrote: > > hi Takahiro, > > > > On Thu, 16 Jun 2022 at 06:31, Takahiro Akashi > > wrote: > > > > > > Sughosh, > > > > > > On Wed, Jun 15, 2022 at 04:19:56PM +0530, Sughosh Ganu wrote: > > > > On Wed, 15 Jun 2022 at 10:41, Takahiro Akashi > > > > wrote: > > > > > > > > > > On Thu, Jun 09, 2022 at 05:59:58PM +0530, Sughosh Ganu wrote: > > > > > > The Dependable Boot specification[1] describes the structure of the > > > > > > firmware accept and revert capsules. These are empty capsules which > > > > > > are used for signalling the acceptance or rejection of the updated > > > > > > firmware by the OS. Add support for generating these empty capsules. > > > > > > > > > > > > [1] - > > > > > > https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf > > > > > > > > > > > > Signed-off-by: Sughosh Ganu > > > > > > --- > > > > > > doc/mkeficapsule.1 | 29 ++--- > > > > > > tools/eficapsule.h | 8 +++ > > > > > > tools/mkeficapsule.c | 139 > > > > > > +-- > > > > > > 3 files changed, 151 insertions(+), 25 deletions(-) > > > > > > > > > > > > diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1 > > > > > > index 09bdc24295..77ca061efd 100644 > > > > > > --- a/doc/mkeficapsule.1 > > > > > > +++ b/doc/mkeficapsule.1 > > > > > > @@ -8,7 +8,7 @@ mkeficapsule \- Generate EFI capsule file for U-Boot > > > > > > > > > > > > .SH SYNOPSIS > > > > > > .B mkeficapsule > > > > > > -.RI [ options "] " image-blob " " capsule-file > > > > > > +.RI [ options ] " " [ image-blob ] " " capsule-file > > > > > > > > > > > > .SH "DESCRIPTION" > > > > > > .B mkeficapsule > > > > > > @@ -23,8 +23,13 @@ Optionally, a capsule file can be signed with a > > > > > > given private key. > > > > > > In this case, the update will be authenticated by verifying the > > > > > > signature > > > > > > before applying. > > > > > > > > > > > > +Additionally, an empty capsule file can be generated for > > > > > > acceptance or > > > > > > +rejection of firmware images by a governing component like an > > > > > > Operating > > > > > > +System. The empty capsules do not require an image-blob input file. > > > > > > + > > > > > > + > > > > > > .B mkeficapsule > > > > > > -takes any type of image files, including: > > > > > > +takes any type of image files when generating non empty capsules, > > > > > > including: > > > > > > .TP > > > > > > .I raw image > > > > > > format is a single binary blob of any type of firmware. > > > > > > @@ -36,18 +41,16 @@ multiple binary blobs in a single capsule file. > > > > > > This type of image file can be generated by > > > > > > .BR mkimage . > > > > > > > > > > > > -.PP > > > > > > -If you want to use other types than above two, you should > > > > > > explicitly > > > > > > -specify a guid for the FMP driver. > > > > > > - > > > > > > .SH "OPTIONS" > > > > > > + > > > > > > .TP > > > > > > .BI "-g\fR,\fB --guid " guid-string > > > > > > Specify guid for image blob type. The format is: > > > > > > ---- > > > > > > > > > > > > The first three elements are in little endian, while the rest > > > > > > -is in big endian. > > > > > > +is in big endian. The option must be specified for all non empty > > > > > > and > > > > > > +image acceptance capsules > > > > > > > > > > "image acceptance" -> "firmware acceptance" > > > > > > > > Okay > > > > > > > > > > > > > > I don't still understand why we need a guid for acceptance > > > > > while revert doesn't require it. > > > > > I believe that firmware update is "all or nothing", isn't it? > > > > > > > > I believe this gives more flexibility in that different components > > > > might be required to accept the various firmware images. So, one > > > > component might accept the optee_os, while another might be > > > > responsible for accepting u-boot. In any case, we do check that all > > > > the components have their accepted bit set, and only if so, does the > > > > bank boot in the regular state. > > > > > > Probably I don't understand the behavior. > > > Let's assume that we have firmware A and firmware B and then > > > update both. > > > When the firmware A is accepted and B is not (not yet issuing > > > acceptance capsule) and I try to reboot the system, what happens? > > > From which bank does the system boot, old one or new one? > > > > Once any/all of the images have been updated, on subsequent reboot, > > the platform would boot in Trial State from the updated bank. I have > > introduced an EFI variable, TrialeStateCtr for counting the number of > > times the system is booting in the trial state. The system remains in > > trial state as long as all the images from the updated bank have not > > been accepted. The platform boots in trial state for a particular > > number of
