Re: [PATCH v1] usb: host: nuvoton: Add nuvoton NPCM7xx ehci/ohci driver
Hi Marek Thanks for your reply. The answer is yes. Our customer Dell is using our driver now. so need upstream uboot source to uboot master. On Sat, Jun 25, 2022 at 2:12 AM Marek Vasut wrote: > > On 6/21/22 11:09, Jim Liu wrote: > > Add nuvoton BMC NPCM750 ehci/ohci driver > > Is there going to be any user of this driver (soon) ?
Re: [PATCH] efi_loader: Allow overlapped extra data for PE hashing
On 6/27/22 05:43, Su, Bao Cheng wrote: On Fri, 2022-06-24 at 11:44 +0200, Jan Kiszka wrote: On 24.06.22 10:53, Heinrich Schuchardt wrote: On 6/24/22 07:32, Su, Bao Cheng wrote: During PE hashing, when holes exists between sections, the extra data calculated could be a dupulicated region of the last section. Such PE image with holes existing between sections may contain the symbol table for the kernel, for example. The Authenticode_PE spec does not rule how to deal with such scenario, however, other tools such as pesign and sbsign both have the overlapped Thanks for analyzing differences in hashing. Above you mention holes between sections. Here you talk about overlapping sections. These two cases are obviously distinct. Please, provide an accurate description. Yeah, I also gave that feedback internally already as it left me a bit confused. Examples (in text form) would be helpful. There is apparently no good PE dump tooling available, so I try to describe our scenario verbally: You could try https://github.com/xypron/efi_analyzer. We are generating a unified kernel image, similar to what systemd does, for ARM and ARM64 [1]. The stub has .text and .data sections, and then follows the symbol table (some versions of binutils allow to suppress it, other not, sigh). When appending the actual payload to that (kernel image, command line, initrd, dtbs), those sections are added right after the symbol table, creating an unhashed gap between the last stub section and the first appended one. That unified linux.efi is then signed and should be verifiable and bootable (as it is with EDK2). I will try to give a more straightforward description, considering below PE image: ## PE Header: @0x ... ### Section Header 1: ... @0x0108 : 0x8000 - SizeOfRawData @0x010C : 0x1000 - PointerToRawData ... ### Section Header 2: ... @0x0130 : 0x1C00 - SizeOfRawData @0x0134 : 0x9000 - PointerToRawData ... ### Section Header 3: ... @0x0158 : 0x1200 - SizeOfRawData @0x015C : 0xB200 - PointerToRawData ... From the section headers, the end offset of section 2 is 0x1C00 + 0x9000 = 0xAC00, however, the start offset of the section 3 is 0xB200, there is a `hole` here of size 0x600 bytes. In our case Jan has explained this is the symbol table. According to PE hasing spec, when finished the parsing of sections, the bytes_hashed should be calculated and compared to the (total PE size - auth size), and if the bytes_hashed is lesser, it means there are extra data need be hashed as well. According to spec, the offset of the extra data is set to bytes_hashed, this does not cause overlapping for a normal PE image without holes between sections, because the bytes_hashed is equal to the tail of the last section. However, for our case the extra data is the overlapped with the last section or sections, because the bytes_hashed is lesser than the tail of the last section due to the `hole`. U-Boot currently considers this part of data as overlapped and excludes them from the hashing, however other tools or BLs such as pesign/sbsign/EDK2 do not rule out the overlapped data, the hash result "Overlap" means that bytes of the image belong to two sections. An example of overlap would be: section 1: 0x1000 - 0x2000 section 2: 0x1800 - 0x2800 "Gap" means that bytes between two sections don't belong to any section: section1: 0x1000 - 0x2000 section2: 0x2800 - 0x3800 stays consistent among these tools, although the last part is hashed twice indeed. We will have to update U-Boot's unit tests to contain an example with a gap. How do you create these files with a gap? Best regards Heinrich Baocheng HTH, Jan [1] https://github.com/siemens/efibootguard/blob/master/docs/UNIFIED-KERNEL.md
Re: [PATCH] i2c: fix stack buffer overflow vulnerability in i2c md command
Hello Nicolas, On 21.06.22 16:04, Nicolas IOOSS wrote: > Hello, > > I sent some days ago the vulnerability fix below. I have not received any > reply yet. Could a maintainer take a look at it, please? Sorry for that, but I was on the road (embedded world in nuremberg). > Best regards, > Nicolas > > --- Original Message --- > Le vendredi 10 juin 2022 à 4:50 PM, a écrit : > > >> From: Nicolas Iooss nicolas.iooss+ub...@ledger.fr >> >> >> When running "i2c md 0 0 8100", the function do_i2c_md parses the >> length into an unsigned int variable named length. The value is then >> moved to a signed variable: >> >> int nbytes = length; >> #define DISP_LINE_LEN 16 >> int linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; >> >> ret = dm_i2c_read(dev, addr, linebuf, linebytes); >> >> On systems where integers are 32 bits wide, 0x8100 is a negative >> value to "nbytes > DISP_LINE_LEN" is false and linebytes gets assigned >> >> 0x8100 instead of 16. >> >> The consequence is that the function which reads from the i2c device >> (dm_i2c_read or i2c_read) is called with a 16-byte stack buffer to fill >> but with a size parameter which is too large. In some cases, this could >> trigger a crash. But with some i2c drivers, such as drivers/i2c/nx_i2c.c >> (used with "nexell,s5pxx18-i2c" bus), the size is actually truncated to >> a 16-bit integer. This is because function i2c_transfer expects an >> unsigned short length. In such a case, an attacker who can control the >> response of an i2c device can overwrite the return address of a function >> and execute arbitrary code through Return-Oriented Programming. >> >> Fix this issue by using unsigned integers types in do_i2c_md. While at >> it, make also alen unsigned, as signed sizes can cause vulnerabilities >> when people forgot to check that they can be negative. >> >> Signed-off-by: Nicolas Iooss nicolas.iooss+ub...@ledger.fr >> >> --- >> cmd/i2c.c | 24 >> 1 file changed, 12 insertions(+), 12 deletions(-) Reviewed-by: Heiko Schocher @Tom: Should we add this to 2022.07? If so, feel free to pick it up, thanks! bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
[PATCH V7 2/4] ddr: imx8m: helper: load ddr firmware according to binman symbols
From: Peng Fan
By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN after
we update the binman dtsi to drop 0x8000/0x4000 length for the firmware.
And that could save binary size for many KBs.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
Reviewed-by: Alper Nebi Yasak
[Alper: Check BINMAN_SYMS_OK instead]
Signed-off-by: Alper Nebi Yasak
---
drivers/ddr/imx/phy/helper.c | 47 +++-
1 file changed, 41 insertions(+), 6 deletions(-)
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c
index 60d650e3089..e9e0294f87d 100644
--- a/drivers/ddr/imx/phy/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -24,15 +25,30 @@ DECLARE_GLOBAL_DATA_PTR;
#define DMEM_OFFSET_ADDR 0x00054000
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+binman_sym_declare(ulong, ddr_1d_imem_fw, image_pos);
+binman_sym_declare(ulong, ddr_1d_imem_fw, size);
+
+binman_sym_declare(ulong, ddr_1d_dmem_fw, image_pos);
+binman_sym_declare(ulong, ddr_1d_dmem_fw, size);
+
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+binman_sym_declare(ulong, ddr_2d_imem_fw, image_pos);
+binman_sym_declare(ulong, ddr_2d_imem_fw, size);
+
+binman_sym_declare(ulong, ddr_2d_dmem_fw, image_pos);
+binman_sym_declare(ulong, ddr_2d_dmem_fw, size);
+#endif
+
/* We need PHY iMEM PHY is 32KB padded */
void ddr_load_train_firmware(enum fw_type type)
{
u32 tmp32, i;
u32 error = 0;
unsigned long pr_to32, pr_from32;
- unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+ uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0;
unsigned long imem_start = (unsigned long)&_end + fw_offset;
unsigned long dmem_start;
+ unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
#ifdef CONFIG_SPL_OF_CONTROL
if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
@@ -42,11 +58,30 @@ void ddr_load_train_firmware(enum fw_type type)
}
#endif
- dmem_start = imem_start + IMEM_LEN;
+ dmem_start = imem_start + imem_len;
+
+ if (BINMAN_SYMS_OK) {
+ switch (type) {
+ case FW_1D_IMAGE:
+ imem_start = binman_sym(ulong, ddr_1d_imem_fw,
image_pos);
+ imem_len = binman_sym(ulong, ddr_1d_imem_fw, size);
+ dmem_start = binman_sym(ulong, ddr_1d_dmem_fw,
image_pos);
+ dmem_len = binman_sym(ulong, ddr_1d_dmem_fw, size);
+ break;
+ case FW_2D_IMAGE:
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+ imem_start = binman_sym(ulong, ddr_2d_imem_fw,
image_pos);
+ imem_len = binman_sym(ulong, ddr_2d_imem_fw, size);
+ dmem_start = binman_sym(ulong, ddr_2d_dmem_fw,
image_pos);
+ dmem_len = binman_sym(ulong, ddr_2d_dmem_fw, size);
+#endif
+ break;
+ }
+ }
pr_from32 = imem_start;
pr_to32 = IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN; ) {
+ for (i = 0x0; i < imem_len; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x, DDR_TRAIN_CODE_BASE_ADDR +
ddrphy_addr_remap(pr_to32));
pr_to32 += 1;
@@ -59,7 +94,7 @@ void ddr_load_train_firmware(enum fw_type type)
pr_from32 = dmem_start;
pr_to32 = DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN; ) {
+ for (i = 0x0; i < dmem_len; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x, DDR_TRAIN_CODE_BASE_ADDR +
ddrphy_addr_remap(pr_to32));
pr_to32 += 1;
@@ -73,7 +108,7 @@ void ddr_load_train_firmware(enum fw_type type)
debug("check ddr_pmu_train_imem code\n");
pr_from32 = imem_start;
pr_to32 = IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN; ) {
+ for (i = 0x0; i < imem_len; ) {
tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR +
ddrphy_addr_remap(pr_to32)) & 0x);
pr_to32 += 1;
tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
@@ -95,7 +130,7 @@ void ddr_load_train_firmware(enum fw_type type)
debug("check ddr4_pmu_train_dmem code\n");
pr_from32 = dmem_start;
pr_to32 = DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN;) {
+ for (i = 0x0; i < dmem_len;) {
tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR +
ddrphy_addr_remap(pr_to32)) & 0x);
pr_to32 += 1;
tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
--
2.36.0
[PATCH V2 29/49] misc: fuse: support to access fuse on i.MX93
From: Alice Guo
i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables
for i.MX93. The offset address of FSB accessing OTP shadow registers is
different between i.MX8ULP and i.MX93, so use macro to define the offset
address instead of hardcode.
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 2 ++
drivers/misc/sentinel/fuse.c | 30 ++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 7b84b970b75..fa6951ebbe8 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -19,6 +19,8 @@
#define WDG4_BASE_ADDR 0x424aUL
#define WDG5_BASE_ADDR 0x424bUL
+#define FSB_BASE_ADDR 0x4751UL
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index 83d2c25731f..abb4c072f9b 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -31,6 +31,9 @@ struct s400_map_entry {
u32 s400_index;
};
+#if defined(CONFIG_IMX8ULP)
+#define FSB_OTP_SHADOW 0x800
+
struct fsb_map_entry fsb_mapping_table[] = {
{ 3, 8 },
{ 4, 8 },
@@ -65,6 +68,31 @@ struct s400_map_entry s400_api_mapping_table[] = {
{ 23, 1, 4, 2 }, /* OTFAD */
{ 25, 8 }, /* Test config2 */
};
+#elif defined(CONFIG_ARCH_IMX9)
+#define FSB_OTP_SHADOW 0x8000
+
+struct fsb_map_entry fsb_mapping_table[] = {
+ { 0, 8 },
+ { 1, 8 },
+ { 2, 8 },
+ { -1, 8 },
+ { 4, 8 },
+ { 5, 8 },
+ { 6, 8 }, /* UID */
+ { -1, 8 },
+ { 8, 8 },
+ { 9, 8 },
+ { 10, 8 },
+};
+
+struct s400_map_entry s400_api_mapping_table[] = {
+ { 3, 11 }, /* 24 .. 34 */
+ { 7, 8 },
+ { 16, 11 }, /* 128 .. 143 */
+ { 22, 8 },
+ { 23, 8 },
+};
+#endif
static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
{
@@ -128,7 +156,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
word_index = map_fsb_fuse_index(bank, word, );
if (word_index >= 0) {
- *val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2));
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW +
(word_index << 2));
if (redundancy)
*val = (*val >> ((word % 2) * 16)) & 0x;
--
2.36.0
[PATCH V2 47/49] net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr
From: Peng Fan
i.MX has specific hook to get MAC address, so introduce a hook and move
i.MX code to its own driver
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 9 ++---
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_imx.c | 12 +++-
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index a4380d17d9c..c1f2391d635 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -712,10 +712,13 @@ static int eqos_write_hwaddr(struct udevice *dev)
static int eqos_read_rom_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ ret = eqos->config->ops->eqos_get_enetaddr(dev);
+ if (ret < 0)
+ return ret;
-#ifdef CONFIG_ARCH_IMX8M
- imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
-#endif
return !is_valid_ethaddr(pdata->enetaddr);
}
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index f470189e8d4..b35e7742634 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -240,6 +240,7 @@ struct eqos_ops {
int (*eqos_calibrate_pads)(struct udevice *dev);
int (*eqos_disable_calibration)(struct udevice *dev);
int (*eqos_set_tx_clk_speed)(struct udevice *dev);
+ int (*eqos_get_enetaddr)(struct udevice *dev);
ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
};
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 2d1b5104af2..42cb164ad14 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -92,6 +92,15 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
return 0;
}
+static int eqos_get_enetaddr_imx(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
+ imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
+
+ return 0;
+}
+
static struct eqos_ops eqos_imx_ops = {
.eqos_inval_desc = eqos_inval_desc_generic,
.eqos_flush_desc = eqos_flush_desc_generic,
@@ -106,7 +115,8 @@ static struct eqos_ops eqos_imx_ops = {
.eqos_calibrate_pads = eqos_null_ops,
.eqos_disable_calibration = eqos_null_ops,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
+ .eqos_get_enetaddr = eqos_get_enetaddr_imx,
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx,
};
struct eqos_config __maybe_unused eqos_imx_config = {
--
2.36.0
[PATCH V7 4/4] imx: imx8mm-icore: migrate to use BINMAN
From: Peng Fan Use BINMAN instead of imx specific packing method. Signed-off-by: Peng Fan Reviewed-by: Alper Nebi Yasak --- arch/arm/mach-imx/imx8m/Kconfig | 1 + arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg | 10 +- configs/imx8mm-icore-mx8mm-ctouch2_defconfig| 2 +- configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 2 +- 4 files changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index ef8518c06bd..e01e9e8a96e 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -69,6 +69,7 @@ config TARGET_IMX8MM_EVK config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" + select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 diff --git a/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg index e06d53ef417..5dcb8ae72f0 100644 --- a/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg +++ b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg @@ -3,13 +3,5 @@ * Copyright 2019 NXP */ - -FIT BOOT_FROM sd -LOADER spl/u-boot-spl-ddr.bin 0x7E1000 -SECOND_LOADER u-boot.itb 0x4020 0x6 - -DDR_FW lpddr4_pmu_train_1d_imem.bin -DDR_FW lpddr4_pmu_train_1d_dmem.bin -DDR_FW lpddr4_pmu_train_2d_imem.bin -DDR_FW lpddr4_pmu_train_2d_dmem.bin +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index 7d08b244f2c..30f842aef3b 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -20,7 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb" CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index acc5d34659b..721c72c719c 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -20,7 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb" CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -- 2.36.0
[PATCH V7 3/4] arm: dts: imx8m: shrink ddr firmware size to actual file size
From: Peng Fan
After we switch to use BINMAN_SYMBOLS, there is no need to pad
the file size to 0x8000 and 0x4000. After we use BINMAN_SYMBOLS,
the u-boot-spl-ddr.bin shrink about 36KB with i.MX8MP-EVK.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
Reviewed-by: Alper Nebi Yasak
---
arch/arm/dts/imx8mm-u-boot.dtsi | 8
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 8
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 4 ++--
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 8
arch/arm/dts/imx8mn-evk-u-boot.dtsi | 8
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8
arch/arm/dts/imx8mn-venice-u-boot.dtsi| 8
arch/arm/dts/imx8mp-u-boot.dtsi | 8
arch/arm/dts/imx8mq-cm-u-boot.dtsi| 8
arch/arm/dts/imx8mq-u-boot.dtsi | 8
10 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 86f8e1a284b..8c48678625d 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -41,25 +41,25 @@
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index d28bb2b2ffe..5f839524028 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -149,26 +149,26 @@
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
- size = <0x8000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
- size = <0x4000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
- size = <0x8000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
- size = <0x4000>;
type = "blob-ext";
+ align-end = <4>;
};
};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index dc4cec250ef..c4ae7ca4f31 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -113,13 +113,13 @@
ddr-1d-imem-fw {
filename = "ddr3_imem_1d.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "ddr3_dmem_1d.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 30ef8bc47d9..78773c198e4 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -157,26 +157,26 @@
ddr-1d-imem-fw {
filename = "ddr4_imem_1d_201810.bin";
- size = <0x8000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-1d-dmem-fw {
filename = "ddr4_dmem_1d_201810.bin";
- size = <0x4000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-2d-imem-fw
[PATCH V7 0/4] arm64: binman: use binman symbols for imx
From: Peng Fan V7: Rebased with follwoing patchset applied. [1] i.MX93 patchset: https://patchwork.ozlabs.org/project/uboot/cover/20220627032455.28280-1-peng@oss.nxp.com/ [2] binman symbols fix: https://patchwork.ozlabs.org/project/uboot/cover/20220618121316.12061-1-alpernebiya...@gmail.com/ V6: Drop no-u-boot-any introduced in V5 Drop binman symbol replacement with @ to _, which is not needed Update imx8m config to not select RAM IMAGE and RAM DEVICE Update ddr firmware node name Introduce autoconf.h for binman test V5: Introduce no-u-boot-any property to drop the X86 guard patch 1 Add blob-ext type for ddr firmware node Include a missing dts change V4: Fix three boards build failure V3: Add R-b/T-b Fix build warning V2: resolve some CI failure include patch 7 binman symbol is a good feature, but only used on X86 for now. This patchset is to use it for i.MX8M platform. The current imx8m ddr phy firmware consumes lots of space, because we pad them to the largest 32KB and 16KB for IMEM and DMEM. With this patchset we use binman symbols to get firmware location and size, we could save near 36KB with i.MX8MP-EVK. Please help check and test Peng Fan (4): arm: dts: imx8m: update binman ddr firmware node name ddr: imx8m: helper: load ddr firmware according to binman symbols arm: dts: imx8m: shrink ddr firmware size to actual file size imx: imx8mm-icore: migrate to use BINMAN arch/arm/dts/imx8mm-u-boot.dtsi | 16 +++ arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 20 .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 8 ++-- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 20 arch/arm/dts/imx8mn-evk-u-boot.dtsi | 20 .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 16 +++ arch/arm/dts/imx8mn-venice-u-boot.dtsi| 16 +++ arch/arm/dts/imx8mp-u-boot.dtsi | 20 arch/arm/dts/imx8mq-cm-u-boot.dtsi| 20 arch/arm/dts/imx8mq-u-boot.dtsi | 16 +++ arch/arm/mach-imx/imx8m/Kconfig | 1 + .../mach-imx/imx8m/imximage-8mm-lpddr4.cfg| 10 +--- configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 2 +- configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 2 +- drivers/ddr/imx/phy/helper.c | 47 --- 15 files changed, 141 insertions(+), 93 deletions(-) -- 2.36.0
[PATCH V7 1/4] arm: dts: imx8m: update binman ddr firmware node name
From: Peng Fan
We are migrating to use binman symbols, the current names are
inconsistent across different boards, so unify them.
Also add `type = "blob-ext";`, since the new names are not valid binman
types.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
Reviewed-by: Alper Nebi Yasak
[Alper: Edit commit message]
Signed-off-by: Alper Nebi Yasak
---
arch/arm/dts/imx8mm-u-boot.dtsi | 8
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 12
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 4 ++--
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 12
arch/arm/dts/imx8mn-evk-u-boot.dtsi | 12
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8
arch/arm/dts/imx8mn-venice-u-boot.dtsi| 8
arch/arm/dts/imx8mp-u-boot.dtsi | 12
arch/arm/dts/imx8mq-cm-u-boot.dtsi| 12
arch/arm/dts/imx8mq-u-boot.dtsi | 8
10 files changed, 58 insertions(+), 38 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 9f66cdb65a9..86f8e1a284b 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -39,25 +39,25 @@
filename = "u-boot-spl.bin";
};
- 1d-imem {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 1d-dmem {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
};
- 2d-imem {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 2d-dmem {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index eb1dd8debba..d28bb2b2ffe 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -147,24 +147,28 @@
align-end = <4>;
};
- blob_1: blob-ext@1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_2: blob-ext@2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
+ type = "blob-ext";
};
- blob_3: blob-ext@3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_4: blob-ext@4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
+ type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index 46a9d7fd78b..dc4cec250ef 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -111,13 +111,13 @@
filename = "u-boot-spl.bin";
};
- 1d-imem {
+ ddr-1d-imem-fw {
filename = "ddr3_imem_1d.bin";
size = <0x8000>;
type = "blob-ext";
};
- 1d_dmem {
+ ddr-1d-dmem-fw {
filename = "ddr3_dmem_1d.bin";
size = <0x4000>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 4d0ecb07d4f..30ef8bc47d9 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -155,24 +155,28 @@
align-end = <4>;
};
- blob_1: blob-ext@1 {
+ ddr-1d-imem-fw {
filename = "ddr4_imem_1d_201810.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_2: blob-ext@2 {
+ ddr-1d-dmem-fw {
[PATCH V2 26/49] imx: imx9: Get the chip revision through S400 API
From: Peng Fan
Update the get chip revision methond to use S400 API, also record
other information like lifecycle and UID to global data.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/global_data.h | 3 ++
arch/arm/mach-imx/imx9/soc.c | 49 +-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 09f352269e5..6ee2a767615 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -92,6 +92,9 @@ struct arch_global_data {
#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
+ u32 soc_rev;
+ u32 lifecycle;
+ u32 uid[4];
#endif
};
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 7c71cbdd55a..c71a5a92504 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -67,9 +68,18 @@ int mmc_get_env_dev(void)
}
#endif
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+ gd->arch.soc_rev = info->soc;
+ gd->arch.lifecycle = info->lc;
+ memcpy((void *)>arch.uid, >uid, 4 * sizeof(u32));
+}
+
u32 get_cpu_rev(void)
{
- return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
+ u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+
+ return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev);
}
#define UNLOCK_WORD 0xD928C520 /* unlock word */
@@ -198,6 +208,17 @@ int ft_system_setup(void *blob, struct bd_info *bd)
return 0;
}
+#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
+ gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2],
gd->arch.uid[3]);
+
+ serialnr->low = gd->arch.uid[0];
+ serialnr->high = gd->arch.uid[3];
+}
+#endif
+
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
@@ -212,6 +233,32 @@ int arch_cpu_init(void)
return 0;
}
+int imx9_probe_mu(void *ctx, struct event *event)
+{
+ struct udevice *devp;
+ int node, ret;
+ u32 res;
+ struct sentinel_get_info_data info;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"fsl,imx93-mu-s4");
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, );
+ if (ret)
+ return ret;
+
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
+
+ ret = ahab_get_info(, );
+ if (ret)
+ return ret;
+
+ set_cpu_info();
+
+ return 0;
+}
+EVENT_SPY(EVT_DM_POST_INIT, imx9_probe_mu);
+
int timer_init(void)
{
#ifdef CONFIG_SPL_BUILD
--
2.36.0
[PATCH V2 25/49] imx: imx9: Add AHAB boot support
From: Ye Li
Add AHAB driver for iMX9 to do authentication by calling sentinel API
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Kconfig | 5 +
arch/arm/mach-imx/imx9/Makefile | 1 +
arch/arm/mach-imx/imx9/ahab.c | 346
3 files changed, 352 insertions(+)
create mode 100644 arch/arm/mach-imx/imx9/ahab.c
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index ce58e41428f..dae9f658e65 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -1,5 +1,10 @@
if ARCH_IMX9
+config AHAB_BOOT
+bool "Support i.MX9 AHAB features"
+help
+This option enables the support for AHAB secure boot.
+
config IMX9
bool
select HAS_CAAM
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 0124212f266..41a22500c95 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -4,3 +4,4 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
+obj-$(CONFIG_AHAB_BOOT) += ahab.o
diff --git a/arch/arm/mach-imx/imx9/ahab.c b/arch/arm/mach-imx/imx9/ahab.c
new file mode 100644
index 000..6aa949619b5
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/ahab.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_BASE (0x8000UL)
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xUL)
+
+#define AHAB_NO_AUTHENTICATION_IND 0xee
+#define AHAB_BAD_KEY_HASH_IND 0xfa
+#define AHAB_INVALID_KEY_IND 0xf9
+#define AHAB_BAD_SIGNATURE_IND 0xf0
+#define AHAB_BAD_HASH_IND 0xf1
+
+static void display_ahab_auth_ind(u32 event)
+{
+ u8 resp_ind = (event >> 8) & 0xff;
+
+ switch (resp_ind) {
+ case AHAB_NO_AUTHENTICATION_IND:
+ printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_KEY_HASH_IND:
+ printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_INVALID_KEY_IND:
+ printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_SIGNATURE_IND:
+ printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_HASH_IND:
+ printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ default:
+ printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
+ break;
+ }
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+ int err;
+ u32 resp;
+
+ memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
+ ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+ flush_dcache_range(IMG_CONTAINER_BASE,
+ IMG_CONTAINER_BASE + ALIGN(length,
CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+ err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, );
+ if (err) {
+ printf("Authenticate container hdr failed, return %d, resp
0x%x\n",
+ err, resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_auth_release(void)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_release_container();
+ if (err) {
+ printf("Error: release container failed, resp 0x%x!\n", resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_verify_image(image_index, );
+ if (err) {
+ printf("Authenticate img %d failed, return %d, resp 0x%x\n",
+ image_index, err, resp);
+ display_ahab_auth_ind(resp);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static inline bool check_in_dram(ulong addr)
+{
+ int i;
+ struct bd_info *bd = gd->bd;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ if (addr >= bd->bi_dram[i].start &&
+ addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+ return true;
+ }
+ }
+
+ return false;
+}
+
+int authenticate_os_container(ulong addr)
+{
+ struct container_hdr *phdr;
+ int i, ret = 0;
+ int err;
+ u16 length;
+ struct boot_img_t *img;
+ unsigned long s, e;
+
+ if (addr % 4) {
+ puts("Error: Image's address is not 4 byte aligned\n");
+ return -EINVAL;
+ }
+
+ if (!check_in_dram(addr)) {
+ puts("Error: Image's address is invalid\n");
+
[PATCH V2 16/49] imx: imx9: Add function to initialize timer
From: Jian Li
Add timer_init to update ARM arch timer with correct frequency
from system counter and enable system counter.
Signed-off-by: Jian Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 19 +++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 50ec902987d..32c76ce9c3b 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -11,6 +11,7 @@
#define IOMUXC_BASE_ADDR 0x443CUL
#define CCM_BASE_ADDR 0x4445UL
#define CCM_CCGR_BASE_ADDR 0x44458000UL
+#define SYSCNT_CTRL_BASE_ADDR 0x4429
#define ANATOP_BASE_ADDR0x4448UL
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index d4a97729c67..4b8f1ca30d5 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -128,3 +128,22 @@ int arch_cpu_init(void)
return 0;
}
+
+int timer_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+ unsigned long freq = readl(>cntfid0);
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
+
+ clrsetbits_le32(>cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+ SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+#endif
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
--
2.36.0
[PATCH V2 49/49] tools: image: support i.MX93
From: Peng Fan
Support build i.MX93 container image with mkimage
Signed-off-by: Peng Fan
---
include/imx8image.h | 15 +++--
tools/imx8image.c | 79 +
2 files changed, 78 insertions(+), 16 deletions(-)
diff --git a/include/imx8image.h b/include/imx8image.h
index 00c614ab6cc..32064bfeeb8 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -165,6 +165,7 @@ enum imx8image_core_type {
CFG_M40,
CFG_M41,
CFG_A35,
+ CFG_A55,
CFG_A53,
CFG_A72
};
@@ -180,7 +181,9 @@ enum imx8image_fld_types {
typedef enum SOC_TYPE {
NONE = 0,
QX,
- QM
+ QM,
+ ULP,
+ IMX9
} soc_type_t;
typedef enum option_type {
@@ -201,7 +204,9 @@ typedef enum option_type {
DATA,
PARTITION,
FILEOFF,
- MSG_BLOCK
+ MSG_BLOCK,
+ SENTINEL,
+ UPOWER
} option_type_t;
typedef struct {
@@ -221,6 +226,11 @@ typedef struct {
#define CORE_CA72 5
#define CORE_SECO 6
+#define CORE_ULP_CM33 0x1
+#define CORE_ULP_CA35 0x2
+#define CORE_ULP_UPOWER0x4
+#define CORE_ULP_SENTINEL 0x6
+
#define SC_R_OTP 357U
#define SC_R_DEBUG 354U
#define SC_R_ROM_0 236U
@@ -235,6 +245,7 @@ typedef struct {
#define IMG_TYPE_DATA0x04 /* Data image type */
#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */
#define IMG_TYPE_SECO0x06 /* SECO image type */
+#define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */
#define IMG_TYPE_PROV0x07 /* Provisioning image type */
#define IMG_TYPE_DEK 0x08 /* DEK validation type */
diff --git a/tools/imx8image.c b/tools/imx8image.c
index fa8f2274876..01e14869114 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -60,6 +60,7 @@ static table_entry_t imx8image_core_entries[] = {
{CFG_M40, "M40", "M4 core 0",},
{CFG_M41, "M41", "M4 core 1",},
{CFG_A35, "A35", "A35 core", },
+ {CFG_A55, "A55", "A55 core", },
{CFG_A53, "A53", "A53 core", },
{CFG_A72, "A72", "A72 core", },
{-1,"", "", },
@@ -117,6 +118,10 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t
cmd, char *token,
soc = QX;
} else if (!strncmp(token, "IMX8QM", 6)) {
soc = QM;
+ } else if (!strncmp(token, "ULP", 3)) {
+ soc = IMX9;
+ } else if (!strncmp(token, "IMX9", 4)) {
+ soc = IMX9;
} else {
fprintf(stderr, "Unknown CMD_SOC_TYPE");
exit(EXIT_FAILURE);
@@ -187,6 +192,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t
*cmd, char *token,
param_stack[p_idx].filename = token;
break;
case CFG_A35:
+ case CFG_A55:
param_stack[p_idx].ext = CORE_CA35;
param_stack[p_idx].option =
(*cmd == CMD_DATA) ? DATA : AP;
@@ -219,6 +225,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t
*cmd, char *token,
case CFG_M41:
case CFG_A35:
case CFG_A53:
+ case CFG_A55:
case CFG_A72:
param_stack[p_idx++].entry =
(uint32_t)strtoll(token, NULL, 0);
@@ -548,6 +555,18 @@ static void set_image_array_entry(flash_header_v3_t
*container,
img->dst = 0x20C0;
img->entry = 0x2000;
break;
+ case SENTINEL:
+ if (container->num_images > 0) {
+ fprintf(stderr, "Error: SENTINEL container only allows
1 image\n");
+ return;
+ }
+
+ img->hab_flags |= IMG_TYPE_SENTINEL;
+ img->hab_flags |= CORE_ULP_SENTINEL <<
BOOT_IMG_FLAGS_CORE_SHIFT;
+ tmp_name = "SENTINEL";
+ img->dst = 0xe400; /* S400 IRAM base */
+ img->entry = 0xe400;
+ break;
case AP:
if (soc == QX && core == CORE_CA35) {
meta = IMAGE_A35_DEFAULT_META(custom_partition);
@@ -555,6 +574,8 @@ static void set_image_array_entry(flash_header_v3_t
*container,
meta = IMAGE_A53_DEFAULT_META(custom_partition);
} else if (soc == QM && core == CORE_CA72) {
meta = IMAGE_A72_DEFAULT_META(custom_partition);
+ } else if (((soc == ULP) || (soc == IMX9)) && core ==
CORE_CA35) {
+ meta = 0;
} else {
[PATCH V2 48/49] board: freescale: imx93_evk: support ethernet
From: Peng Fan
Add ethernet support
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 7 +
board/freescale/imx93_evk/imx93_evk.c | 32 +++
configs/imx93_11x11_evk_defconfig | 9 +++
3 files changed, 48 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 049eca4f3a7..f575805c7da 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -7,6 +7,7 @@
#define __ASM_ARCH_IMX9_REGS_H__
#define ARCH_MXC
+#define FEC_QUIRK_ENET_MAC
#define IOMUXC_BASE_ADDR 0x443CUL
#define CCM_BASE_ADDR 0x4445UL
@@ -39,6 +40,12 @@
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASKGENMASK(3, 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII(0x1 << 1)
+#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN(0x1 << 0)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
diff --git a/board/freescale/imx93_evk/imx93_evk.c
b/board/freescale/imx93_evk/imx93_evk.c
index 77b92b35db4..f111b99fc2e 100644
--- a/board/freescale/imx93_evk/imx93_evk.c
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -38,8 +38,40 @@ int board_early_init_f(void)
return 0;
}
+static int setup_fec(void)
+{
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+static int setup_eqos(void)
+{
+ struct blk_ctrl_wakeupmix_regs *bctrl =
+ (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(>eqos_gpr,
+ BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
+ BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII |
BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+
int board_init(void)
{
+ if (CONFIG_IS_ENABLED(FEC_MXC))
+ setup_fec();
+
+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
+ setup_eqos();
+
return 0;
}
diff --git a/configs/imx93_11x11_evk_defconfig
b/configs/imx93_11x11_evk_defconfig
index 8a396ed1c13..1f59f7e365d 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -75,6 +75,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
@@ -89,6 +90,14 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y
--
2.36.0
[PATCH V2 45/49] net: dwc_eth_qos: move i.MX code out
From: Peng Fan
Move i.MX code to a standalone file to make it easy for adding new
platform support
Signed-off-by: Peng Fan
---
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 92 --
drivers/net/dwc_eth_qos.h | 2 +
drivers/net/dwc_eth_qos_imx.c | 121 ++
4 files changed, 124 insertions(+), 92 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos_imx.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 69fb3bbbf7c..9536af11946 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b69a9feb824..1f24f5cb0cf 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -506,20 +506,6 @@ static ulong eqos_get_tick_clk_rate_stm32(struct udevice
*dev)
#endif
}
-__weak u32 imx_get_eqos_csr_clk(void)
-{
- return 100 * 100;
-}
-__weak int imx_eqos_txclk_set_rate(unsigned long rate)
-{
- return 0;
-}
-
-static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
-{
- return imx_get_eqos_csr_clk();
-}
-
static int eqos_set_full_duplex(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -616,38 +602,6 @@ static int eqos_set_tx_clk_speed_tegra186(struct udevice
*dev)
return 0;
}
-static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
- ulong rate;
- int ret;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- switch (eqos->phy->speed) {
- case SPEED_1000:
- rate = 125 * 1000 * 1000;
- break;
- case SPEED_100:
- rate = 25 * 1000 * 1000;
- break;
- case SPEED_10:
- rate = 2.5 * 1000 * 1000;
- break;
- default:
- pr_err("invalid speed %d", eqos->phy->speed);
- return -EINVAL;
- }
-
- ret = imx_eqos_txclk_set_rate(rate);
- if (ret < 0) {
- pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
- return ret;
- }
-
- return 0;
-}
-
static int eqos_adjust_link(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1468,24 +1422,6 @@ static phy_interface_t eqos_get_interface_tegra186(const
struct udevice *dev)
return PHY_INTERFACE_MODE_MII;
}
-static int eqos_probe_resources_imx(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
- phy_interface_t interface;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- interface = eqos->config->interface(dev);
-
- if (interface == PHY_INTERFACE_MODE_NA) {
- pr_err("Invalid PHY interface\n");
- return -EINVAL;
- }
-
- debug("%s: OK\n", __func__);
- return 0;
-}
-
static int eqos_remove_resources_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1695,34 +1631,6 @@ static const struct eqos_config __maybe_unused
eqos_stm32_config = {
.ops = _stm32_ops
};
-static struct eqos_ops eqos_imx_ops = {
- .eqos_inval_desc = eqos_inval_desc_generic,
- .eqos_flush_desc = eqos_flush_desc_generic,
- .eqos_inval_buffer = eqos_inval_buffer_generic,
- .eqos_flush_buffer = eqos_flush_buffer_generic,
- .eqos_probe_resources = eqos_probe_resources_imx,
- .eqos_remove_resources = eqos_null_ops,
- .eqos_stop_resets = eqos_null_ops,
- .eqos_start_resets = eqos_null_ops,
- .eqos_stop_clks = eqos_null_ops,
- .eqos_start_clks = eqos_null_ops,
- .eqos_calibrate_pads = eqos_null_ops,
- .eqos_disable_calibration = eqos_null_ops,
- .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
-};
-
-struct eqos_config __maybe_unused eqos_imx_config = {
- .reg_access_always_ok = false,
- .mdio_wait = 10,
- .swr_wait = 50,
- .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
- .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .axi_bus_width = EQOS_AXI_WIDTH_64,
- .interface = dev_read_phy_mode,
- .ops = _imx_ops
-};
-
static const struct udevice_id eqos_ids[] = {
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
{
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 68b367b068a..ce90e1f1ce1 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -278,3 +278,5 @@ void eqos_flush_desc_generic(void *desc);
void eqos_inval_buffer_generic(void *buf, size_t
[PATCH V2 46/49] net: eqos: add function to get phy node and address
From: Ye Li
Since new atheros PHY driver needs to access its PHY node through
phy device, we have to assign the phy node in ethernet controller
driver. Otherwise the PHY driver will fail to get some nodes
and properties.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 23 ---
drivers/net/dwc_eth_qos.h | 1 +
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 1f24f5cb0cf..a4380d17d9c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -719,6 +719,24 @@ static int eqos_read_rom_hwaddr(struct udevice *dev)
return !is_valid_ethaddr(pdata->enetaddr);
}
+static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle_args;
+ int reg;
+
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args)) {
+ debug("Failed to find phy-handle");
+ return -ENODEV;
+ }
+
+ priv->phy_of_node = phandle_args.node;
+
+ reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+ return reg;
+}
+
static int eqos_start(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -767,9 +785,7 @@ static int eqos_start(struct udevice *dev)
*/
if (!eqos->phy) {
int addr = -1;
-#ifdef CONFIG_DM_ETH_PHY
- addr = eth_phy_get_addr(dev);
-#endif
+ addr = eqos_get_phy_addr(eqos, dev);
#ifdef DWC_NET_PHYADDR
addr = DWC_NET_PHYADDR;
#endif
@@ -788,6 +804,7 @@ static int eqos_start(struct udevice *dev)
}
}
+ eqos->phy->node = eqos->phy_of_node;
ret = phy_config(eqos->phy);
if (ret < 0) {
pr_err("phy_config() failed: %d", ret);
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index ce90e1f1ce1..f470189e8d4 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -261,6 +261,7 @@ struct eqos_priv {
struct clk clk_slave_bus;
struct mii_dev *mii;
struct phy_device *phy;
+ ofnode phy_of_node;
u32 max_speed;
void *descs;
int tx_desc_idx, rx_desc_idx;
--
2.36.0
[PATCH V2 09/49] imx: add basic i.MX9 support
From: Peng Fan
Add i.MX9 Kconfig and basic files for the new SoC
Signed-off-by: Peng Fan
---
arch/arm/Kconfig| 11 +
arch/arm/include/asm/arch-imx/cpu.h | 2 +
arch/arm/include/asm/arch-imx9/clock.h | 0
arch/arm/include/asm/arch-imx9/gpio.h | 0
arch/arm/include/asm/arch-imx9/imx-regs.h | 13 +
arch/arm/include/asm/arch-imx9/imx93_pins.h | 729
arch/arm/include/asm/arch-imx9/sys_proto.h | 11 +
arch/arm/include/asm/mach-imx/iomux-v3.h| 11 +-
arch/arm/include/asm/mach-imx/sys_proto.h | 3 +
arch/arm/mach-imx/Makefile | 11 +-
arch/arm/mach-imx/imx9/Kconfig | 17 +
arch/arm/mach-imx/imx9/Makefile | 6 +
arch/arm/mach-imx/imx9/clock.c | 27 +
arch/arm/mach-imx/imx9/lowlevel_init.S | 26 +
arch/arm/mach-imx/imx9/soc.c| 127
arch/arm/mach-imx/spl.c | 2 +-
16 files changed, 991 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx9/clock.h
create mode 100644 arch/arm/include/asm/arch-imx9/gpio.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx93_pins.h
create mode 100644 arch/arm/include/asm/arch-imx9/sys_proto.h
create mode 100644 arch/arm/mach-imx/imx9/Kconfig
create mode 100644 arch/arm/mach-imx/imx9/Makefile
create mode 100644 arch/arm/mach-imx/imx9/clock.c
create mode 100644 arch/arm/mach-imx/imx9/lowlevel_init.S
create mode 100644 arch/arm/mach-imx/imx9/soc.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dab785efad5..12ec661ac3b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -925,6 +925,15 @@ config ARCH_IMX8ULP
imply CMD_DM
imply DM_EVENT
+config ARCH_IMX9
+ bool "NXP i.MX9 platform"
+ select ARM64
+ select DM
+ select MACH_IMX
+ select SUPPORT_SPL
+ imply CMD_DM
+ imply DM_EVENT
+
config ARCH_IMXRT
bool "NXP i.MXRT platform"
select CPU_V7M
@@ -2251,6 +2260,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig"
source "arch/arm/mach-imx/imx8ulp/Kconfig"
+source "arch/arm/mach-imx/imx9/Kconfig"
+
source "arch/arm/mach-imx/imxrt/Kconfig"
source "arch/arm/mach-imx/mxs/Kconfig"
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index 4f63803765e..d54e6e63352 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -59,6 +59,7 @@
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
+#define MXC_CPU_IMX93 0xC1 /* dummy ID */
#define MXC_SOC_MX60x60
#define MXC_SOC_MX70x70
@@ -66,6 +67,7 @@
#define MXC_SOC_IMX8 0x90 /* dummy */
#define MXC_SOC_IMXRT 0xB0 /* dummy */
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
+#define MXC_SOC_IMX9 0xC0 /* dummy */
#define CHIP_REV_1_00x10
#define CHIP_REV_1_10x11
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
new file mode 100644
index 000..e69de29bb2d
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h
b/arch/arm/include/asm/arch-imx9/gpio.h
new file mode 100644
index 000..e69de29bb2d
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
new file mode 100644
index 000..2adbdadf03c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_REGS_H__
+#define __ASM_ARCH_IMX9_REGS_H__
+
+#define ARCH_MXC
+
+#define IOMUXC_BASE_ADDR 0x443CUL
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h
b/arch/arm/include/asm/arch-imx9/imx93_pins.h
new file mode 100644
index 000..f13aef5619c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h
@@ -0,0 +1,729 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX93_PINS_H__
+#define __ASM_ARCH_IMX93_PINS_H__
+
+#include
+
+enum {
+ MX93_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x1B0,
0x, 0, 0x3D8, 0, 0),
+ MX93_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x1B0,
0x, 1, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x1B0,
0x, 3, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x1B0,
0x, 4, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__GPIO3_IO28= IOMUX_PAD(0x1B0,
0x, 5, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__LPUART5_RX= IOMUX_PAD(0x1B0,
0x, 6, 0x430, 0, 0),
+
+ MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS= IOMUX_PAD(0x1B4,
0x0004, 0, 0x3DC, 0, 0),
+ MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31=
[PATCH V2 10/49] fsl_lpuart: add i.MX9 support
From: Peng Fan
i.MX9 shares same register layout as i.MX7ULP, so
add the i.MX9 define here.
Signed-off-by: Peng Fan
---
include/fsl_lpuart.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index 18e5cc15d61..93c996b764b 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -5,7 +5,7 @@
*/
#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
- defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP)
+ defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP) ||
defined(CONFIG_ARCH_IMX9)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
--
2.36.0
[PATCH V2 00/49] imx: support i.MX93
From: Peng Fan
V2:
Fix issue reported by CI build
- Enlarge SPL_MAX_SIZE for i.MX8MM
- Fix i.MX8ULP break
This patchset is to support i.MX93, during the development, there are some
code cleanup and restructure to make i.MX93 code porting cleaner.
i.MX9 is a new i.MX family and i.MX93 is the first one that we would support
in upstream. It features two Cortex-A55 core, one NPU, one M33 and others.
There are some driver changes that also included to make i.MX93 function well,
lpuart/mmc/network.
mkimage also included, but I have not enable BINMAN which is under development,
will post a follow patchset to switch to binman.
Alice Guo (3):
misc: imx8ulp: move fuse.c from imx8ulp to sentinel
misc: fuse: support to access fuse on i.MX93
misc: fuse: update the code for accessing fuse of i.MX93
Jian Li (1):
imx: imx9: Add function to initialize timer
Peng Fan (31):
spl: imx8mm: enlarge SPL_MAX_SIZE
arm: makefile: cleanup mach-imx usage
imx: simplify dependency with SPL_BOOTROM_SUPPORT
imx: move get_boot_device to common header
imx: move get_boot_device to common file
imx: add USB2_BOOT type
imx: add basic i.MX9 support
fsl_lpuart: add i.MX9 support
gpio: pca953x: support pcal6524
imx: pinctrl: add pinctrl and pinfunc file for i.MX93
imx: imx9: Add CCM and clock API support
mmc: fsl_esdhc_imx: Support i.MX9
spl: Use SPL_FIT_IMAGE_TINY for iMX9
imx: imx9: support romapi
misc: s4mu: Support iMX93 with Sentinel MU
misc: S400_API: New API for FW status and chip info
misc: s400_api: introduce ahab_release_m33_trout
imx: imx9: Get the chip revision through S400 API
imx: imx9: Add MIX power init
imx: imx9: Add M33 release prepare function
imx: imx9: Support booting m33 from Acore
arm: dts: Add i.MX93 SoC DTSi file
imx: imx93_evk: Add basic board support
imx: imx93_evk: Set ARM clock to 1.7Ghz
net: fec_mxc: support i.MX93
net: dwc_eth_qos: fix build break when CLK not enabled
net: dwc_eth_qos: public some functions
net: dwc_eth_qos: move i.MX code out
net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr
board: freescale: imx93_evk: support ethernet
tools: image: support i.MX93
Ye Li (14):
imx: Change USB boot device type
imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device
imx: imx9: disable watchdog
misc: imx: S400_API: Move S400 MU and API to a common place
misc: S400_API: Update release RDC API
imx: imx9: Add TRDC driver for TRDC init
imx: imx9: Add AHAB boot support
misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
imx: imx9: Add gpio registers structure
imx: imx9: Support multiple env storages at runtime
imx: imx9: clock: Add DDR clock support
ddr: imx: Add i.MX9 DDR controller driver
ddr: imx9: enable Performance monitor counter
net: eqos: add function to get phy node and address
arch/arm/Kconfig | 16 +
arch/arm/Makefile | 12 +-
arch/arm/dts/Makefile |3 +
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 ++
arch/arm/dts/imx93-11x11-evk.dts | 527 ++
arch/arm/dts/imx93-pinfunc.h | 625 +++
arch/arm/dts/imx93.dtsi | 688
arch/arm/include/asm/arch-imx/cpu.h |2 +
arch/arm/include/asm/arch-imx8/sys_proto.h|1 -
arch/arm/include/asm/arch-imx8m/ddr.h |6 +-
arch/arm/include/asm/arch-imx8m/sys_proto.h |2 +-
arch/arm/include/asm/arch-imx8ulp/sys_proto.h |5 -
arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 +++
arch/arm/include/asm/arch-imx9/clock.h| 244 +++
arch/arm/include/asm/arch-imx9/ddr.h | 126 ++
arch/arm/include/asm/arch-imx9/gpio.h | 20 +
arch/arm/include/asm/arch-imx9/imx-regs.h | 234 +++
arch/arm/include/asm/arch-imx9/imx93_pins.h | 729
arch/arm/include/asm/arch-imx9/sys_proto.h| 14 +
arch/arm/include/asm/arch-imx9/trdc.h | 19 +
arch/arm/include/asm/arch-mx7/sys_proto.h |1 -
arch/arm/include/asm/arch-mx7ulp/sys_proto.h |1 -
arch/arm/include/asm/global_data.h|5 +-
arch/arm/include/asm/mach-imx/boot_mode.h |1 +
arch/arm/include/asm/mach-imx/iomux-v3.h | 11 +-
.../asm/{arch-imx8ulp => mach-imx}/mu_hal.h |4 +-
.../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 18 +-
arch/arm/include/asm/mach-imx/sys_proto.h | 11 +-
arch/arm/mach-imx/Kconfig |3 +-
arch/arm/mach-imx/Makefile| 10 +-
arch/arm/mach-imx/imx8m/soc.c | 47 -
arch/arm/mach-imx/imx8ulp/ahab.c | 345
arch/arm/mach-imx/imx8ulp/rdc.c |6 +-
arch/arm/mach-imx/imx8ulp/soc.c | 48 +-
arch/arm/mach-imx/imx9/Kconfig| 34 +
arch/arm/mach-imx/imx9/Makefile | 11 +
arch/arm/mach-imx/imx9/ahab.c | 346
[PATCH V2 15/49] spl: Use SPL_FIT_IMAGE_TINY for iMX9
From: Peng Fan Select SPL_FIT_IMAGE_TINY for i.MX9 Signed-off-by: Peng Fan --- common/spl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 848237c1e85..06cbad2ca85 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -537,7 +537,7 @@ config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6 - default y if ARCH_IMX8M + default y if ARCH_IMX8M || ARCH_IMX9 help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. -- 2.36.0
[PATCH V2 04/49] imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device
From: Ye Li
Move the default mapping of spl_boot_device to weak function of
spl_board_boot_device. So that every board of iMX7/8/8M can overwrite
this function to implement specific mapping.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/spl.c | 80 -
1 file changed, 38 insertions(+), 42 deletions(-)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index e89e2277ef7..e5ad993b8d9 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -25,7 +25,43 @@ DECLARE_GLOBAL_DATA_PTR;
__weak int spl_board_boot_device(enum boot_device boot_dev_spl)
{
- return 0;
+ switch (boot_dev_spl) {
+#if defined(CONFIG_MX7)
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8)
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ return BOOT_DEVICE_MMC2_2;
+ case SD3_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case FLEXSPI_BOOT:
+ return BOOT_DEVICE_SPI;
+#elif defined(CONFIG_IMX8M)
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC2;
+#endif
+ case NAND_BOOT:
+ return BOOT_DEVICE_NAND;
+ case SPI_NOR_BOOT:
+ return BOOT_DEVICE_SPI;
+ case QSPI_BOOT:
+ return BOOT_DEVICE_NOR;
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
}
#if defined(CONFIG_MX6)
@@ -140,47 +176,7 @@ u32 spl_boot_device(void)
enum boot_device boot_device_spl = get_boot_device();
- if (IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) ||
- IS_ENABLED(CONFIG_IMX8MP))
- return spl_board_boot_device(boot_device_spl);
-
- switch (boot_device_spl) {
-#if defined(CONFIG_MX7)
- case SD1_BOOT:
- case MMC1_BOOT:
- case SD2_BOOT:
- case MMC2_BOOT:
- case SD3_BOOT:
- case MMC3_BOOT:
- return BOOT_DEVICE_MMC1;
-#elif defined(CONFIG_IMX8)
- case MMC1_BOOT:
- return BOOT_DEVICE_MMC1;
- case SD2_BOOT:
- return BOOT_DEVICE_MMC2_2;
- case SD3_BOOT:
- return BOOT_DEVICE_MMC1;
- case FLEXSPI_BOOT:
- return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_IMX8M)
- case SD1_BOOT:
- case MMC1_BOOT:
- return BOOT_DEVICE_MMC1;
- case SD2_BOOT:
- case MMC2_BOOT:
- return BOOT_DEVICE_MMC2;
-#endif
- case NAND_BOOT:
- return BOOT_DEVICE_NAND;
- case SPI_NOR_BOOT:
- return BOOT_DEVICE_SPI;
- case QSPI_BOOT:
- return BOOT_DEVICE_NOR;
- case USB_BOOT:
- return BOOT_DEVICE_BOARD;
- default:
- return BOOT_DEVICE_NONE;
- }
+ return spl_board_boot_device(boot_device_spl);
}
#endif /* CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */
--
2.36.0
[PATCH V2 44/49] net: dwc_eth_qos: public some functions
From: Peng Fan
Move macros and structures to header file and make some functions
public, so that could used by other files, this is to
prepare split platform specific config to one file.
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 280 +-
drivers/net/dwc_eth_qos.h | 280 ++
2 files changed, 287 insertions(+), 273 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos.h
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 6048d56ff8c..b69a9feb824 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -51,275 +51,9 @@
#include
#include
#endif
-#include
#include
-/* Core registers */
-
-#define EQOS_MAC_REGS_BASE 0x000
-struct eqos_mac_regs {
- uint32_t configuration; /* 0x000 */
- uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
- uint32_t q0_tx_flow_ctrl; /* 0x070 */
- uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
- uint32_t rx_flow_ctrl; /* 0x090 */
- uint32_t unused_094;/* 0x094 */
- uint32_t txq_prty_map0; /* 0x098 */
- uint32_t unused_09c;/* 0x09c */
- uint32_t rxq_ctrl0; /* 0x0a0 */
- uint32_t unused_0a4;/* 0x0a4 */
- uint32_t rxq_ctrl2; /* 0x0a8 */
- uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
- uint32_t us_tic_counter;/* 0x0dc */
- uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
- uint32_t hw_feature0; /* 0x11c */
- uint32_t hw_feature1; /* 0x120 */
- uint32_t hw_feature2; /* 0x124 */
- uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
- uint32_t mdio_address; /* 0x200 */
- uint32_t mdio_data; /* 0x204 */
- uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
- uint32_t address0_high; /* 0x300 */
- uint32_t address0_low; /* 0x304 */
-};
-
-#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
-#define EQOS_MAC_CONFIGURATION_CST BIT(21)
-#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
-#define EQOS_MAC_CONFIGURATION_WD BIT(19)
-#define EQOS_MAC_CONFIGURATION_JD BIT(17)
-#define EQOS_MAC_CONFIGURATION_JE BIT(16)
-#define EQOS_MAC_CONFIGURATION_PS BIT(15)
-#define EQOS_MAC_CONFIGURATION_FES BIT(14)
-#define EQOS_MAC_CONFIGURATION_DM BIT(13)
-#define EQOS_MAC_CONFIGURATION_LM BIT(12)
-#define EQOS_MAC_CONFIGURATION_TE BIT(1)
-#define EQOS_MAC_CONFIGURATION_RE BIT(0)
-
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0x
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
-
-#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
-
-#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
-#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
-
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
-
-#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
-#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
-
-#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
-#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
-#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
-#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
-
-#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
-#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
-#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
-#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
-
-#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
-#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
-
-#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
-#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT16
-#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
-#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
-#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
-#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
-#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT2
-#define EQOS_MAC_MDIO_ADDRESS_GOC_READ
[PATCH V2 40/49] imx: imx93_evk: Add basic board support
From: Peng Fan
Add basic board codes and defconfig for i.MX93 11x11 EVK board.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/dts/Makefile |3 +
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 +++
arch/arm/dts/imx93-11x11-evk.dts | 527 +++
arch/arm/mach-imx/imx9/Kconfig | 12 +
board/freescale/common/Makefile|2 +-
board/freescale/imx93_evk/Kconfig | 21 +
board/freescale/imx93_evk/MAINTAINERS |6 +
board/freescale/imx93_evk/Makefile | 12 +
board/freescale/imx93_evk/imx93_evk.c | 58 +
board/freescale/imx93_evk/lpddr4x_timing.c | 1486
board/freescale/imx93_evk/spl.c| 126 ++
configs/imx93_11x11_evk_defconfig | 108 ++
include/configs/imx93_evk.h| 149 ++
13 files changed, 2666 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx93-11x11-evk.dts
create mode 100644 board/freescale/imx93_evk/Kconfig
create mode 100644 board/freescale/imx93_evk/MAINTAINERS
create mode 100644 board/freescale/imx93_evk/Makefile
create mode 100644 board/freescale/imx93_evk/imx93_evk.c
create mode 100644 board/freescale/imx93_evk/lpddr4x_timing.c
create mode 100644 board/freescale/imx93_evk/spl.c
create mode 100644 configs/imx93_11x11_evk_defconfig
create mode 100644 include/configs/imx93_evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4b940f85169..1217f156bea 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -966,6 +966,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb
+dtb-$(CONFIG_ARCH_IMX9) += \
+ imx93-11x11-evk.dtb
+
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
new file mode 100644
index 000..6f02b389893
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ u-boot,dm-spl;
+ };
+
+ aliases {
+ usbgadget0 =
+ usbgadget1 =
+ };
+
+ usbg1: usbg1 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <>;
+ status = "okay";
+ };
+
+ usbg2: usbg2 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <>;
+ status = "okay";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <2>;
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart1 {
+ u-boot,dm-spl;
+};
+
+_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@4400/i2c@4435/pmic@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@4400/i2c@4435/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+_lpi2c2 {
+ u-boot,dm-spl;
+};
+
+ {
+ phy-reset-gpios = < 16 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+ {
+ compatible = "fsl,imx-eqos";
+};
+
+ {
+ reset-gpios = < 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <10>;
+};
+
+ {
+ status = "okay";
+ extcon = <>;
+};
+
+ {
+ status = "okay";
+ extcon = <_2>;
+};
+
+ {
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts
new file mode 100644
index 000..b3a5a3d71e2
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -0,0 +1,527 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/{
+ chosen {
+ stdout-path =
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+
[PATCH V2 43/49] net: dwc_eth_qos: fix build break when CLK not enabled
From: Peng Fan
When CONFIG_CLK is not enabled, there will be buil break:
"error: ‘eqos’ undeclared (first use in this function)"
Should not guard the eqos under CONFIG_CLK macro
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9d255cf95ff..6048d56ff8c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1774,11 +1774,11 @@ static int eqos_remove_resources_tegra186(struct
udevice *dev)
static int eqos_remove_resources_stm32(struct udevice *dev)
{
-#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
+#ifdef CONFIG_CLK
clk_free(>clk_tx);
clk_free(>clk_rx);
clk_free(>clk_master_bus);
--
2.36.0
[PATCH V2 42/49] net: fec_mxc: support i.MX93
From: Peng Fan
Support i.MX93 in fec_mxc driver
Signed-off-by: Peng Fan
---
drivers/net/Kconfig | 2 +-
drivers/net/fec_mxc.c | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 84d859c21eb..8cf8621467f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -340,7 +340,7 @@ config FEC_MXC_MDIO_BASE
config FEC_MXC
bool "FEC Ethernet controller"
- depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP ||
VF610
+ depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP ||
IMX93 || VF610
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index a623a5c45e4..8bc2b46d403 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -598,7 +598,8 @@ static int fecmxc_init(struct udevice *dev)
writel(0x, >eth->gaddr2);
/* Do not access reserved register */
- if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() &&
!is_imx8ulp()) {
+ if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() &&
!is_imx8ulp() &&
+ !is_imx93()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
@@ -1357,6 +1358,7 @@ static const struct udevice_id fecmxc_ids[] = {
{ .compatible = "fsl,imx53-fec" },
{ .compatible = "fsl,imx7d-fec" },
{ .compatible = "fsl,mvf600-fec" },
+ { .compatible = "fsl,imx93-fec" },
{ }
};
--
2.36.0
[PATCH V2 38/49] ddr: imx9: enable Performance monitor counter
From: Ye Li
Add Kconfig for enabling reference events counter in DDRC performance
monitor by default
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/ddr/imx/imx9/Kconfig| 6 ++
drivers/ddr/imx/imx9/ddr_init.c | 4
2 files changed, 10 insertions(+)
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
index a16ddc65e01..123ad173cfc 100644
--- a/drivers/ddr/imx/imx9/Kconfig
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -11,6 +11,12 @@ config IMX9_LPDDR4X
help
Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC.
+config IMX9_DRAM_PM_COUNTER
+ bool "imx9 DDRC performance monitor counter"
+ default y
+ help
+ Enable DDR controller performance monitor counter for reference
events.
+
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
help
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 16eac65105f..8b8ec7f8de3 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -112,6 +112,10 @@ int ddr_init(struct dram_timing_info *dram_timing)
ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
debug("DDRINFO: ddrc config done\n");
+#ifdef CONFIG_IMX9_DRAM_PM_COUNTER
+ writel(0x20, REG_DDR_DEBUG_19);
+#endif
+
check_dfi_init_complete();
regval = readl(REG_DDR_SDRAM_CFG);
--
2.36.0
[PATCH V2 41/49] imx: imx93_evk: Set ARM clock to 1.7Ghz
From: Peng Fan
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 4 +++-
arch/arm/mach-imx/imx9/clock.c | 9 +
board/freescale/imx93_evk/spl.c| 3 +++
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index d96f126a1d1..336d8613181 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -217,6 +217,8 @@ void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
+int configure_intpll(enum ccm_clk_src pll, u32 freq);
+
int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
@@ -238,5 +240,5 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool
user_mode, bool lock
void enable_usboh3_clk(unsigned char enable);
int set_clk_enet(enum enet_freq type);
int set_clk_eqos(enum enet_freq type);
-
+void set_arm_clk(ulong freq);
#endif
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 5d2bc0d2f8f..8240afc6172 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -665,6 +665,15 @@ void dram_disable_bypass(void)
/* Switch from DRAM clock root from CCM to PLL */
ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
}
+
+void set_arm_clk(ulong freq)
+{
+ /* Increase ARM clock to 1.7Ghz */
+ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
+ configure_intpll(ARM_PLL_CLK, 17);
+ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
+}
+
#endif
int clock_init(void)
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index ca33f943424..38cfbac6ea6 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -108,6 +108,9 @@ void board_init_f(ulong dummy)
}
power_init_board();
+ /* 1.7GHz */
+ set_arm_clk(17);
+
/* Init power of mix */
soc_power_init();
--
2.36.0
[PATCH V2 39/49] arm: dts: Add i.MX93 SoC DTSi file
From: Peng Fan
Add the DTSi file and DT header files for i.MX93 SoC
Signed-off-by: Ye Li
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
arch/arm/dts/imx93.dtsi | 688
include/dt-bindings/clock/imx93-clock.h | 203 +++
include/dt-bindings/power/imx93-power.h | 12 +
3 files changed, 903 insertions(+)
create mode 100644 arch/arm/dts/imx93.dtsi
create mode 100644 include/dt-bindings/clock/imx93-clock.h
create mode 100644 include/dt-bindings/power/imx93-power.h
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
new file mode 100644
index 000..28026ccecc8
--- /dev/null
+++ b/arch/arm/dts/imx93.dtsi
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "imx93-pinfunc.h"
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ ethernet0 =
+ ethernet1 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ serial5 =
+ serial6 =
+ serial7 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ usb0 =
+ usb1 =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ A55_1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+ clock-output-names = "clk_ext1";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <2400>;
+ arm,no-tick-in-suspend;
+ interrupt-parent = <>;
+ };
+
+ gic: interrupt-controller@4800 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x4800 0 0x1>,
+ <0 0x4804 0 0xc>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = ;
+ interrupt-parent = <>;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x8000>,
+<0x2800 0x0 0x2800 0x1000>;
+
+ aips1: bus@4400 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x4400 0x80>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mu1: mailbox@4423 {
+ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+ reg = <0x4423 0x1>;
+ interrupts = ;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ anomix_ns_gpr: blk-ctrl-anomix@4242 {
+ compatible = "syscon";
+ reg = <0x4421 0x1000>;
+ };
+
+ system_counter: timer@4429 {
+ compatible = "nxp,sysctr-timer";
+
[PATCH V2 37/49] ddr: imx: Add i.MX9 DDR controller driver
From: Ye Li
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.
The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/ddr.h | 6 +-
arch/arm/include/asm/arch-imx9/ddr.h | 126 +
drivers/Makefile | 1 +
drivers/ddr/imx/Kconfig | 2 +
drivers/ddr/imx/imx8m/Kconfig | 1 +
drivers/ddr/imx/imx8m/Makefile| 3 +-
drivers/ddr/imx/imx8m/ddr_init.c | 219
drivers/ddr/imx/imx9/Kconfig | 21 +
drivers/ddr/imx/imx9/Makefile | 10 +
drivers/ddr/imx/imx9/ddr_init.c | 485 ++
drivers/ddr/imx/phy/Kconfig | 4 +
drivers/ddr/imx/phy/Makefile | 9 +
drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c | 0
drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c | 1 -
drivers/ddr/imx/phy/ddrphy_utils.c| 169 ++
drivers/ddr/imx/{imx8m => phy}/helper.c | 45 +-
16 files changed, 1077 insertions(+), 25 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx9/ddr.h
create mode 100644 drivers/ddr/imx/imx9/Kconfig
create mode 100644 drivers/ddr/imx/imx9/Makefile
create mode 100644 drivers/ddr/imx/imx9/ddr_init.c
create mode 100644 drivers/ddr/imx/phy/Kconfig
create mode 100644 drivers/ddr/imx/phy/Makefile
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c (100%)
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c (98%)
create mode 100644 drivers/ddr/imx/phy/ddrphy_utils.c
rename drivers/ddr/imx/{imx8m => phy}/helper.c (79%)
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h
b/arch/arm/include/asm/arch-imx8m/ddr.h
index 2ce8a8f2d41..2f76e7d69b9 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -725,6 +725,8 @@ void update_umctl2_rank_space_setting(unsigned int
pstat_num);
void get_trained_CDD(unsigned int fsp);
unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr);
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr);
+
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);
@@ -741,9 +743,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
}
#define dwc_ddrphy_apb_wr(addr, data) \
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr),
data)
#define dwc_ddrphy_apb_rd(addr) \
- reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
+ reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
extern struct dram_cfg_param ddrphy_trained_csr[];
extern uint32_t ddrphy_trained_csr_num;
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h
b/arch/arm/include/asm/arch-imx9/ddr.h
new file mode 100644
index 000..62e6f7dda53
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_DDR_H
+#define __ASM_ARCH_IMX8M_DDR_H
+
+#include
+#include
+
+#define DDR_CTL_BASE 0x4E30
+#define DDR_PHY_BASE 0x4E10
+#define DDRMIX_BLK_CTRL_BASE 0x4E01
+
+#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
+#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
+#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
+
+#define SRC_BASE_ADDR (0x4446)
+#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
+#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20)
+#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24)
+
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + ((X) * 0x200))
+#define DDRPHY_MEM(X) (DDR_PHY_BASE + ((X) * 0x200) +
0x5)
+
+/* PHY State */
+enum pstate {
+ PS0,
+ PS1,
+ PS2,
+ PS3,
+};
+
+enum msg_response {
+ TRAIN_SUCCESS = 0x7,
+ TRAIN_STREAM_START = 0x8,
+ TRAIN_FAIL = 0xff,
+};
+
+/* user data type */
+enum fw_type {
+ FW_1D_IMAGE,
+ FW_2D_IMAGE,
+};
+
+struct dram_cfg_param {
+ unsigned int reg;
+ unsigned int val;
+};
+
+struct dram_fsp_msg {
+ unsigned int drate;
+ enum fw_type fw_type;
+ struct dram_cfg_param *fsp_cfg;
+ unsigned int fsp_cfg_num;
+};
+
+struct dram_timing_info {
+ /* umctl2 config */
+ struct dram_cfg_param *ddrc_cfg;
+ unsigned int ddrc_cfg_num;
+ /* ddrphy config */
+ struct dram_cfg_param *ddrphy_cfg;
+ unsigned int ddrphy_cfg_num;
+ /* ddr fsp
[PATCH V2 34/49] imx: imx9: Support booting m33 from Acore
From: Peng Fan
Add bootaux command to support on-demand booting M33 from u-boot.
It kicks M33 via ATF by "bootaux 0x201e 0"
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Makefile | 4 +
arch/arm/mach-imx/imx9/imx_bootaux.c | 133 +++
arch/arm/mach-imx/imx9/soc.c | 10 +-
include/imx_sip.h| 1 +
4 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-imx/imx9/imx_bootaux.c
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 41a22500c95..6d038a60c67 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -5,3 +5,7 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
obj-$(CONFIG_AHAB_BOOT) += ahab.o
+
+#ifndef CONFIG_SPL_BUILD
+obj-y += imx_bootaux.o
+#endif
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c
b/arch/arm/mach-imx/imx9/imx_bootaux.c
new file mode 100644
index 000..3b6662aeb81
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
+ 0, 0, 0, 0, );
+
+ return res.a0;
+}
+
+int arch_auxiliary_core_down(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ printf("## Stopping auxiliary core\n");
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
+ 0, 0, 0, 0, );
+
+ return 0;
+}
+
+int arch_auxiliary_core_up(u32 core_id, ulong addr)
+{
+ struct arm_smccc_res res;
+ u32 stack, pc;
+
+ if (!addr)
+ return -EINVAL;
+
+ stack = *(u32 *)addr;
+ pc = *(u32 *)(addr + 4);
+
+ printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n",
stack, pc);
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
+ 0, 0, 0, 0, );
+
+ return 0;
+}
+
+/*
+ * To i.MX6SX and i.MX7D, the image supported by bootaux needs
+ * the reset vector at the head for the image, with SP and PC
+ * as the first two words.
+ *
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset
+ * vector with getting the PC and SP from image and filling them to
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
+ */
+static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong addr;
+ int ret, up;
+ u32 core = 0;
+ u32 stop = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (argc > 2)
+ core = simple_strtoul(argv[2], NULL, 10);
+
+ if (argc > 3)
+ stop = simple_strtoul(argv[3], NULL, 10);
+
+ up = arch_auxiliary_core_check_up(core);
+ if (up) {
+ printf("## Auxiliary core is already up\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ if (!addr)
+ return CMD_RET_FAILURE;
+
+ ret = arch_auxiliary_core_up(core, addr);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret, up;
+
+ up = arch_auxiliary_core_check_up(0);
+ if (!up) {
+ printf("## Auxiliary core is already down\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ ret = arch_auxiliary_core_down(0);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ stopaux, CONFIG_SYS_MAXARGS, 1, do_stopaux,
+ "Stop auxiliary core",
+ " []\n"
+ " - start auxiliary core [] (default 0),\n"
+ " at address \n"
+);
+
+U_BOOT_CMD(
+ bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
+ "Start auxiliary core",
+ " []\n"
+ " - start auxiliary core [] (default 0),\n"
+ " at address \n"
+);
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 2a29454d1eb..ca88271564c 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -131,6 +131,14 @@ static struct mm_region imx93_mem_map[] = {
.size = 0x10UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* TCM */
+ .virt = 0x201cUL,
+ .phys = 0x201cUL,
+
[PATCH V2 36/49] imx: imx9: clock: Add DDR clock support
From: Ye Li
Implement the DDR driver clock interfaces for set DDR rate and
bypass DDR PLL
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 3 ++
arch/arm/mach-imx/imx9/clock.c | 41 ++
2 files changed, 44 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index fcf04d66f05..d96f126a1d1 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -213,6 +213,9 @@ void init_clk_usdhc(u32 index);
int enable_i2c_clk(unsigned char enable, u32 i2c_num);
u32 imx_get_i2cclk(u32 i2c_num);
u32 mxc_get_clock(enum mxc_clock clk);
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
+void dram_disable_bypass(void);
int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 55cbb40f328..5d2bc0d2f8f 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -626,6 +626,47 @@ void enable_usboh3_clk(unsigned char enable)
}
}
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
+{
+ configure_fracpll(DRAM_PLL_CLK, pll_val);
+}
+
+void dram_enable_bypass(ulong clk_val)
+{
+ switch (clk_val) {
+ case MHZ(400):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
+ break;
+ case MHZ(333):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3);
+ break;
+ case MHZ(200):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4);
+ break;
+ case MHZ(100):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8);
+ break;
+ default:
+ printf("No matched freq table %lu\n", clk_val);
+ return;
+ }
+
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from PLL to CCM */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM);
+}
+
+void dram_disable_bypass(void)
+{
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from CCM to PLL */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
+}
+#endif
+
int clock_init(void)
{
int i;
--
2.36.0
[PATCH V2 35/49] imx: imx9: Support multiple env storages at runtime
From: Ye Li
Select env storages according to boot device at runtime
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index ca88271564c..797d7a802ba 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -288,6 +288,40 @@ int timer_init(void)
return 0;
}
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ switch (dev) {
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+ case QSPI_BOOT:
+ env_loc = ENVL_SPI_FLASH;
+ break;
+#endif
+#if defined(CONFIG_ENV_IS_IN_MMC)
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+#endif
+ default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+ env_loc = ENVL_NOWHERE;
+#endif
+ break;
+ }
+
+ return env_loc;
+}
+
static int mix_power_init(enum mix_power_domain pd)
{
enum src_mix_slice_id mix_id;
--
2.36.0
[PATCH V2 33/49] imx: imx9: Add M33 release prepare function
From: Peng Fan
To support on-demand booting M33 image from A core. SPL needs
to follow M33 kick up sequence to release M33 firstly,
then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick
M33 to run.
The prepare function also works around the M33 TCM ECC issue by
clean the TCM. Also enable sentinel handshake and WDOG1 clock
for M33 stop and reset.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/sys_proto.h | 2 +
arch/arm/mach-imx/imx9/soc.c | 51 ++
2 files changed, 53 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h
b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 5ae7a043398..ba97f92f5ae 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -9,4 +9,6 @@
#include
void soc_power_init(void);
+bool m33_is_rom_kicked(void);
+int m33_prepare(void);
#endif
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 68f3ddd4287..2a29454d1eb 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -378,3 +379,53 @@ void soc_power_init(void)
disable_isolation();
}
+
+static bool m33_is_rom_kicked(void)
+{
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs
*)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+
+ if (!(readl(_regs->m33_cfg) & BIT(2)))
+ return true;
+
+ return false;
+}
+
+int m33_prepare(void)
+{
+ struct src_mix_slice_regs *mix_regs =
+ (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400
* (SRC_MIX_CM33 + 1));
+ struct src_general_regs *global_regs =
+ (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs
*)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+ u32 val;
+
+ if (m33_is_rom_kicked())
+ return -EPERM;
+
+ /* Release reset of M33 */
+ setbits_le32(_regs->scr, BIT(0));
+
+ /* Check the reset released in M33 MIX func stat */
+ val = readl(_regs->func_stat);
+ while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT))
+ val = readl(_regs->func_stat);
+
+ /* Release Sentinel TROUT */
+ ahab_release_m33_trout();
+
+ /* Mask WDOG1 IRQ from A55, we use it for M33 reset */
+ setbits_le32(_regs->ca55_irq_mask[1], BIT(6));
+
+ /* Turn on WDOG1 clock */
+ ccm_lpcg_on(CCGR_WDG1, 1);
+
+ /* Set sentinel LP handshake for M33 reset */
+ setbits_le32(_regs->lp_handshake[0], BIT(6));
+
+ /* Clear M33 TCM for ECC */
+ memset((void *)(ulong)0x201e, 0, 0x4);
+
+ return 0;
+}
--
2.36.0
[PATCH V2 32/49] imx: imx9: Add MIX power init
From: Peng Fan
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation
of MIPI DSI/CSI, USBPHY after the power up.
SPL should call the power init in its boot sequence before accessing
above three MIX and USB.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 173 +
arch/arm/include/asm/arch-imx9/sys_proto.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 101
3 files changed, 275 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index fa6951ebbe8..049eca4f3a7 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -21,6 +21,24 @@
#define FSB_BASE_ADDR 0x4751UL
+#define ANATOP_BASE_ADDR0x4448UL
+
+#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x4242
+#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f
+
+#define SRC_IPS_BASE_ADDR (0x4446)
+#define SRC_GLOBAL_RBASE (SRC_IPS_BASE_ADDR + 0x)
+
+#define SRC_DDR_RBASE (SRC_IPS_BASE_ADDR + 0x1000)
+#define SRC_ML_RBASE (SRC_IPS_BASE_ADDR + 0x1800)
+#define SRC_MEDIA_RBASE(SRC_IPS_BASE_ADDR + 0x2400)
+#define SRC_M33P_RBASE (SRC_IPS_BASE_ADDR + 0x2800)
+
+#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
+#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
+#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
@@ -49,6 +67,161 @@ struct mu_type {
u32 reserved5[14];
u32 mu_attr;
};
+
+enum mix_power_domain {
+ MIX_PD_MEDIAMIX,
+ MIX_PD_MLMIX,
+ MIX_PD_DDRMIX,
+};
+
+enum src_mix_slice_id {
+ SRC_MIX_EDGELOCK = 0,
+ SRC_MIX_AONMIX = 1,
+ SRC_MIX_WAKEUPMIX = 2,
+ SRC_MIX_DDRMIX = 3,
+ SRC_MIX_DDRPHY = 4,
+ SRC_MIX_ML = 5,
+ SRC_MIX_NIC = 6,
+ SRC_MIX_HSIO = 7,
+ SRC_MIX_MEDIA = 8,
+ SRC_MIX_CM33 = 9,
+ SRC_MIX_CA55C0 = 10,
+ SRC_MIX_CA55C1 = 11,
+ SRC_MIX_CA55CLUSTER = 12,
+};
+
+enum src_mem_slice_id {
+ SRC_MEM_AONMIX = 0,
+ SRC_MEM_WAKEUPMIX = 1,
+ SRC_MEM_DDRMIX = 2,
+ SRC_MEM_DDRPHY = 3,
+ SRC_MEM_ML = 4,
+ SRC_MEM_NIC = 5,
+ SRC_MEM_OCRAM = 6,
+ SRC_MEM_HSIO = 7,
+ SRC_MEM_MEDIA = 8,
+ SRC_MEM_CA55C0 = 9,
+ SRC_MEM_CA55C1 = 10,
+ SRC_MEM_CA55CLUSTER = 11,
+ SRC_MEM_L3 = 12,
+};
+
+struct blk_ctrl_s_aonmix_regs {
+ u32 cm33_irq_mask[7];
+ u32 initnsvtor;
+ u32 reserved1[8];
+ u32 ca55_irq_mask[7];
+ u32 initsvtor;
+ u32 m33_cfg;
+ u32 reserved2[11];
+ u32 axbs_aon_ctrl;
+ u32 reserved3[27];
+ u32 dap_access_stkybit;
+ u32 reserved4[3];
+ u32 lp_handshake[2];
+ u32 ca55_cpuwait;
+ u32 ca55_rvbaraddr0_l;
+ u32 ca55_rvbaraddr0_h;
+ u32 ca55_rvbaraddr1_l;
+ u32 ca55_rvbaraddr1_h;
+ u32 s401_irq_mask;
+ u32 s401_reset_req_mask;
+ u32 s401_halt_st;
+ u32 ca55_mode;
+ u32 nmi_mask;
+ u32 nmi_clr;
+ u32 wdog_any_mask;
+ u32 s4v1_ipi_noclk_ref1;
+};
+
+struct blk_ctrl_wakeupmix_regs {
+ u32 upper_addr;
+ u32 ipg_debug_cm33;
+ u32 reserved[2];
+ u32 qch_dis;
+ u32 ssi;
+ u32 reserved1[1];
+ u32 dexsc_err;
+ u32 mqs_setting;
+ u32 sai_clk_sel;
+ u32 eqos_gpr;
+ u32 enet_clk_sel;
+ u32 reserved2[1];
+ u32 volt_detect;
+ u32 i3c2_wakeup;
+ u32 ipg_debug_ca55c0;
+ u32 ipg_debug_ca55c1;
+ u32 axi_attr_cfg;
+ u32 i3c2_sda_irq;
+};
+
+struct src_general_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 scr;
+ u32 srtmr;
+ u32 srmask;
+ u32 reserved2[1];
+ u32 srmr[6];
+ u32 reserved3[2];
+ u32 sbmr[2];
+ u32 reserved4[2];
+ u32 srsr;
+ u32 gpr[19];
+ u32 reserved5[24];
+ u32 gpr20;
+ u32 cm_quiesce;
+ u32 cold_reset_ssar_ack_ctrl;
+ u32 sp_iso_ctrl;
+ u32 rom_lp_ctrl;
+ u32 a55_deny_stat;
+};
+
+struct src_mem_slice_regs {
+ u32 reserved[1];
+ u32 mem_ctrl;
+ u32 memlp_ctrl_0;
+ u32 reserved1[1];
+ u32 memlp_ctrl_1;
+ u32 memlp_ctrl_2;
+ u32 mem_stat;
+};
+
+struct src_mix_slice_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 lpm_setting[3];
+ u32 reserved2[1];
+ u32 slice_sw_ctrl;
+ u32 single_reset_sw_ctrl;
+ u32 reserved3[6];
+ u32 a55_hdsk_ack_ctrl;
+ u32 a55_hdsk_ack_stat;
+ u32 reserved4[2];
+ u32 ssar_ack_ctrl;
+ u32 ssar_ack_stat;
+ u32 reserved5[1];
+ u32 iso_off_dly_por;
+ u32 iso_on_dly;
+ u32 iso_off_dly;
+ u32 psw_off_lf_dly;
+
[PATCH V2 31/49] imx: imx9: Add gpio registers structure
From: Ye Li
Add GPIO registers structure for iMX93, so that we can enable lpgpio
driver
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arch-imx9/gpio.h | 20
2 files changed, 21 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 29b831422ff..7dcf5614e9b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -933,6 +933,7 @@ config ARCH_IMX9
select DM
select MACH_IMX
select SUPPORT_SPL
+ select GPIO_EXTRA_HEADER
select MISC
select IMX_SENTINEL
imply CMD_DM
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h
b/arch/arm/include/asm/arch-imx9/gpio.h
index e69de29bb2d..40732022e7e 100644
--- a/arch/arm/include/asm/arch-imx9/gpio.h
+++ b/arch/arm/include/asm/arch-imx9/gpio.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_GPIO_H
+#define __ASM_ARCH_IMX9_GPIO_H
+
+struct gpio_regs {
+ u32 gpio_pdor;
+ u32 gpio_psor;
+ u32 gpio_pcor;
+ u32 gpio_ptor;
+ u32 gpio_pdir;
+ u32 gpio_pddr;
+ u32 gpio_pidr;
+ u8 gpio_pxdr[32];
+};
+
+#endif
--
2.36.0
[PATCH V2 30/49] misc: fuse: update the code for accessing fuse of i.MX93
From: Alice Guo
Sentinel have read access of OTP shadow register 0-511, and fsb have
read access of shadow 0-51/312-511.
Reviewed-by: Ye Li
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
drivers/misc/sentinel/fuse.c | 86 +++-
1 file changed, 74 insertions(+), 12 deletions(-)
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index abb4c072f9b..e2b68757664 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -75,22 +75,44 @@ struct fsb_map_entry fsb_mapping_table[] = {
{ 0, 8 },
{ 1, 8 },
{ 2, 8 },
- { -1, 8 },
+ { 3, 8 },
{ 4, 8 },
{ 5, 8 },
- { 6, 8 }, /* UID */
- { -1, 8 },
- { 8, 8 },
- { 9, 8 },
- { 10, 8 },
+ { 6, 4 },
+ { -1, 260 },
+ { 39, 8 },
+ { 40, 8 },
+ { 41, 8 },
+ { 42, 8 },
+ { 43, 8 },
+ { 44, 8 },
+ { 45, 8 },
+ { 46, 8 },
+ { 47, 8 },
+ { 48, 8 },
+ { 49, 8 },
+ { 50, 8 },
+ { 51, 8 },
+ { 52, 8 },
+ { 53, 8 },
+ { 54, 8 },
+ { 55, 8 },
+ { 56, 8 },
+ { 57, 8 },
+ { 58, 8 },
+ { 59, 8 },
+ { 60, 8 },
+ { 61, 8 },
+ { 62, 8 },
+ { 63, 8 },
};
struct s400_map_entry s400_api_mapping_table[] = {
- { 3, 11 }, /* 24 .. 34 */
- { 7, 8 },
- { 16, 11 }, /* 128 .. 143 */
- { 22, 8 },
- { 23, 8 },
+ { 7, 1, 7, 63 },
+ { 16, 8, },
+ { 17, 8, },
+ { 22, 1, 6 },
+ { 23, 1, 4 },
};
#endif
@@ -102,7 +124,8 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool
*redundancy)
/* map the fuse from ocotp fuse map to FSB*/
for (i = 0; i < size; i++) {
if (fsb_mapping_table[i].fuse_bank != -1 &&
- fsb_mapping_table[i].fuse_bank == bank) {
+ fsb_mapping_table[i].fuse_bank == bank &&
+ fsb_mapping_table[i].fuse_words > word) {
break;
}
@@ -146,6 +169,7 @@ static s32 map_s400_fuse_index(u32 bank, u32 word)
return s400_api_mapping_table[i].fuse_bank * 8 + word;
}
+#if defined(CONFIG_IMX8ULP)
int fuse_sense(u32 bank, u32 word, u32 *val)
{
s32 word_index;
@@ -198,6 +222,44 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
return -ENOENT;
}
+#elif defined(CONFIG_ARCH_IMX9)
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ s32 word_index;
+ bool redundancy;
+
+ if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ word_index = map_fsb_fuse_index(bank, word, );
+ if (word_index >= 0) {
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW +
(word_index << 2));
+ if (redundancy)
+ *val = (*val >> ((word % 2) * 16)) & 0x;
+
+ return 0;
+ }
+
+ word_index = map_s400_fuse_index(bank, word);
+ if (word_index >= 0) {
+ u32 data;
+ u32 res, size = 1;
+ int ret;
+
+ ret = ahab_read_common_fuse(word_index, , size, );
+ if (ret) {
+ printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ *val = data;
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+#endif
int fuse_read(u32 bank, u32 word, u32 *val)
{
--
2.36.0
[PATCH V2 28/49] misc: imx8ulp: move fuse.c from imx8ulp to sentinel
From: Alice Guo
The i.MX93 platform wants to reuse drivers/misc/imx8ulp/fuse.c. Moving
fuse.c from the folder imx8ulp to sentinel makes it can be used by other
platforms.
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
drivers/misc/Makefile | 2 --
drivers/misc/imx8ulp/Makefile | 3 ---
drivers/misc/sentinel/Makefile| 1 +
drivers/misc/{imx8ulp => sentinel}/fuse.c | 0
4 files changed, 1 insertion(+), 5 deletions(-)
delete mode 100644 drivers/misc/imx8ulp/Makefile
rename drivers/misc/{imx8ulp => sentinel}/fuse.c (100%)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index dcba39a15fc..33ccaf04f6a 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -49,8 +49,6 @@ obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
-obj-$(CONFIG_IMX8ULP) += imx8ulp/
-obj-$(CONFIG_IMX8ULP) += imx8ulp/
obj-$(CONFIG_IMX_SENTINEL) += sentinel/
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile
deleted file mode 100644
index 450e615e645..000
--- a/drivers/misc/imx8ulp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/sentinel/Makefile b/drivers/misc/sentinel/Makefile
index 3e2f623b278..446154cb201 100644
--- a/drivers/misc/sentinel/Makefile
+++ b/drivers/misc/sentinel/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += s400_api.o s4mu.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/sentinel/fuse.c
similarity index 100%
rename from drivers/misc/imx8ulp/fuse.c
rename to drivers/misc/sentinel/fuse.c
--
2.36.0
[PATCH V2 24/49] imx: imx9: Add TRDC driver for TRDC init
From: Ye Li
Add TRDC driver to iMX9. The TRDC init splits to two phases:
1. Early init phase will release TRDC from Sentinel and open write
permission to the memory where SPL image runs. Sentinel will set
the memory to RX only after ROM authentication for the OEM
closed part.
2. Init phase will configure TRDC to allow non-secure master to
access DDR. So the peripherals can work in u-boot.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/trdc.h | 19 +
arch/arm/mach-imx/imx9/Makefile | 2 +-
arch/arm/mach-imx/imx9/soc.c | 3 +
arch/arm/mach-imx/imx9/trdc.c | 581 ++
4 files changed, 604 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx9/trdc.h
create mode 100644 arch/arm/mach-imx/imx9/trdc.c
diff --git a/arch/arm/include/asm/arch-imx9/trdc.h
b/arch/arm/include/asm/arch-imx9/trdc.h
new file mode 100644
index 000..1481ee375b7
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/trdc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_TRDC_H
+#define __ASM_ARCH_IMX9_TRDC_H
+
+int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32
glbac_val);
+int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32
blk_x,
+ bool sec_access, u32 glbac_id);
+int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32
glbac_val);
+int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32
addr_start,
+ u32 addr_end, bool sec_access, u32 glbac_id);
+
+void trdc_early_init(void);
+void trdc_init(void);
+
+#endif
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 7be0343d52e..0124212f266 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -3,4 +3,4 @@
# Copyright 2022 NXP
obj-y += lowlevel_init.o
-obj-y += soc.o clock.o clock_root.o
+obj-y += soc.o clock.o clock_root.o trdc.o
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 9ea2d51495b..7c71cbdd55a 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -204,6 +205,8 @@ int arch_cpu_init(void)
init_wdog();
clock_init();
+
+ trdc_early_init();
}
return 0;
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
new file mode 100644
index 000..b0881697a10
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DID_NUM 16
+#define MBC_MAX_NUM 4
+#define MRC_MAX_NUM 2
+#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
+#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+
+struct mbc_mem_dom {
+ u32 mem_glbcfg[4];
+ u32 nse_blk_index;
+ u32 nse_blk_set;
+ u32 nse_blk_clr;
+ u32 nsr_blk_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MBC */
+ u32 mem0_blk_cfg_w[64];
+ u32 mem0_blk_nse_w[16];
+ u32 mem1_blk_cfg_w[8];
+ u32 mem1_blk_nse_w[2];
+ u32 mem2_blk_cfg_w[8];
+ u32 mem2_blk_nse_w[2];
+ u32 mem3_blk_cfg_w[8];
+ u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+ u32 reserved[2];
+};
+
+struct mrc_rgn_dom {
+ u32 mrc_glbcfg[4];
+ u32 nse_rgn_indirect;
+ u32 nse_rgn_set;
+ u32 nse_rgn_clr;
+ u32 nse_rgn_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MRC */
+ u32 rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */
+ u32 rgn_nse;
+ u32 reserved2[15];
+};
+
+struct mda_inst {
+ u32 mda_w[8];
+};
+
+struct trdc_mgr {
+ u32 trdc_cr;
+ u32 res0[59];
+ u32 trdc_hwcfg0;
+ u32 trdc_hwcfg1;
+ u32 res1[450];
+ struct mda_inst mda[8];
+ u32 res2[15808];
+};
+
+struct trdc_mbc {
+ struct mbc_mem_dom mem_dom[DID_NUM];
+};
+
+struct trdc_mrc {
+ struct mrc_rgn_dom mrc_dom[DID_NUM];
+};
+
+int trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids,
+u8 did, u8 pe, u8 pidm, u8 pid)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 *mda_w = _base->mda[mda_inst].mda_w[mda_reg];
+ u32 val = readl(mda_w);
+
+ if (val & BIT(29)) /* non-cpu */
+ return -EINVAL;
+
+ val = BIT(31) | ((pid & 0x3f) << 16) | ((pidm & 0x3f) << 8) |
+ ((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) |
+ (did & 0xf);
+
+ writel(val, mda_w);
+
+ return 0;
+}
+
+int trdc_mda_set_noncpu(ulong
[PATCH V2 27/49] misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
From: Ye Li
Use more generic name for S40x msg structure
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 +-
arch/arm/mach-imx/imx8ulp/rdc.c | 2 +-
arch/arm/mach-imx/imx9/trdc.c| 2 +-
drivers/misc/sentinel/s400_api.c | 44
drivers/misc/sentinel/s4mu.c | 6 ++--
5 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index dc176e1f619..89fa373d06f 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -26,7 +26,7 @@
#define S400_MAX_MSG 255U
-struct imx8ulp_s400_msg {
+struct sentinel_msg {
u8 version;
u8 size;
u8 command;
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index cc47079d8f5..e24eeff8a20 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -184,7 +184,7 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32
perm)
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x2702UL;
- struct imx8ulp_s400_msg msg;
+ struct sentinel_msg msg;
int ret;
u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index b0881697a10..3f37ce712c0 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -315,7 +315,7 @@ bool trdc_mbc_enabled(ulong trdc_base)
int release_rdc(u8 xrdc)
{
ulong s_mu_base = 0x4752UL;
- struct imx8ulp_s400_msg msg;
+ struct sentinel_msg msg;
int ret;
u32 rdc_id;
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 01a673e5e13..65032f77362 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -17,8 +17,8 @@ DECLARE_GLOBAL_DATA_PTR;
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -62,8 +62,8 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -92,8 +92,8 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
int ahab_release_container(u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -120,8 +120,8 @@ int ahab_release_container(u32 *response)
int ahab_verify_image(u32 img_id, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -149,8 +149,8 @@ int ahab_verify_image(u32 img_id, u32 *response)
int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -178,8 +178,8 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32
*response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -226,8 +226,8 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32
fuse_num, u32 *respo
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -259,8 +259,8 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock,
u32 *response)
int ahab_release_caam(u32 core_did, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+
[PATCH V2 20/49] misc: s4mu: Support iMX93 with Sentinel MU
From: Peng Fan
Support iMX93 communicate with Sentinel
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 30 +++
drivers/misc/sentinel/s4mu.c | 1 +
2 files changed, 31 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index e4babed40fc..7b84b970b75 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -19,4 +19,34 @@
#define WDG4_BASE_ADDR 0x424aUL
#define WDG5_BASE_ADDR 0x424bUL
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include
+#include
+
+struct mu_type {
+ u32 ver;
+ u32 par;
+ u32 cr;
+ u32 sr;
+ u32 reserved0[60];
+ u32 fcr;
+ u32 fsr;
+ u32 reserved1[2];
+ u32 gier;
+ u32 gcr;
+ u32 gsr;
+ u32 reserved2;
+ u32 tcr;
+ u32 tsr;
+ u32 rcr;
+ u32 rsr;
+ u32 reserved3[52];
+ u32 tr[16];
+ u32 reserved4[16];
+ u32 rr[16];
+ u32 reserved5[14];
+ u32 mu_attr;
+};
+#endif
+
#endif
diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/sentinel/s4mu.c
index 121a81060a6..18aea27105e 100644
--- a/drivers/misc/sentinel/s4mu.c
+++ b/drivers/misc/sentinel/s4mu.c
@@ -219,6 +219,7 @@ static struct misc_ops imx8ulp_mu_ops = {
static const struct udevice_id imx8ulp_mu_ids[] = {
{ .compatible = "fsl,imx8ulp-mu" },
+ { .compatible = "fsl,imx93-mu-s4" },
{ }
};
--
2.36.0
[PATCH V2 23/49] misc: s400_api: introduce ahab_release_m33_trout
From: Peng Fan
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel
release M33 trout and make sure M33 could boot.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 1 +
drivers/misc/sentinel/s400_api.c | 25
2 files changed, 26 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index d95f8227b29..dc176e1f619 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -55,5 +55,6 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32
*response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
int ahab_get_fw_status(u32 *status, u32 *response);
+int ahab_release_m33_trout(void);
#endif
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index ca7903670ed..01a673e5e13 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -420,3 +420,28 @@ int ahab_get_fw_status(u32 *status, u32 *response)
return ret;
}
+
+int ahab_release_m33_trout(void)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = 0xd3;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ return ret;
+}
--
2.36.0
[PATCH V2 22/49] misc: S400_API: New API for FW status and chip info
From: Peng Fan
Add new API to get sentinel FW status and SoC chip info
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 13 +
drivers/misc/sentinel/s400_api.c | 61
2 files changed, 74 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index d09c078df01..d95f8227b29 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -19,8 +19,10 @@
#define AHAB_READ_FUSE_REQ_CID 0x97
#define AHAB_GET_FW_VERSION_CID0x9D
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_GET_FW_STATUS_CID 0xC5
#define AHAB_WRITE_FUSE_REQ_CID0xD6
#define AHAB_CAAM_RELEASE_CID 0xD7
+#define AHAB_GET_INFO_CID 0xDA
#define S400_MAX_MSG 255U
@@ -32,6 +34,15 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
+struct sentinel_get_info_data {
+ u32 hdr;
+ u32 soc;
+ u32 lc;
+ u32 uid[4];
+ u32 sha256_rom_patch[8];
+ u32 sha_fw[8];
+};
+
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
@@ -42,5 +53,7 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32
fuse_num, u32 *respo
int ahab_release_caam(u32 core_did, u32 *response);
int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
+int ahab_get_fw_status(u32 *status, u32 *response);
#endif
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 4e90171420f..ca7903670ed 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -359,3 +359,64 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
return i;
}
+
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 4;
+ msg.command = AHAB_GET_INFO_CID;
+ msg.data[0] = upper_32_bits((ulong)info);
+ msg.data[1] = lower_32_bits((ulong)info);
+ msg.data[2] = sizeof(struct sentinel_get_info_data);
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_get_fw_status(u32 *status, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_GET_FW_STATUS_CID;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ *status = msg.data[1] & 0xF;
+
+ return ret;
+}
--
2.36.0
[PATCH V2 21/49] misc: S400_API: Update release RDC API
From: Ye Li
To support more RDC instances on i.MX93, update API to latest
definition.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 +-
drivers/misc/sentinel/s400_api.c | 21 +
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index b3e6b3fa45d..d09c078df01 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -32,7 +32,7 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response);
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
int ahab_verify_image(u32 img_id, u32 *response);
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 3d791bc868e..4e90171420f 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
int size = sizeof(struct imx8ulp_s400_msg);
@@ -30,10 +30,23 @@ int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
- if (xrdc)
- msg.data[0] = (0x78 << 8) | core_id;
- else
+ switch (xrdc) {
+ case 0:
msg.data[0] = (0x74 << 8) | core_id;
+ break;
+ case 1:
+ msg.data[0] = (0x78 << 8) | core_id;
+ break;
+ case 2:
+ msg.data[0] = (0x82 << 8) | core_id;
+ break;
+ case 3:
+ msg.data[0] = (0x86 << 8) | core_id;
+ break;
+ default:
+ printf("Error: wrong xrdc index %u\n", xrdc);
+ return -EINVAL;
+ }
ret = misc_call(dev, false, , size, , size);
if (ret)
--
2.36.0
[PATCH V2 19/49] misc: imx: S400_API: Move S400 MU and API to a common place
From: Ye Li
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400
MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/Kconfig | 4 +
arch/arm/include/asm/global_data.h| 2 +-
.../asm/{arch-imx8ulp => mach-imx}/mu_hal.h | 4 +-
.../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 0
arch/arm/mach-imx/imx8ulp/ahab.c | 345 ++
arch/arm/mach-imx/imx8ulp/rdc.c | 4 +-
arch/arm/mach-imx/imx8ulp/soc.c | 4 +-
board/freescale/imx8ulp_evk/spl.c | 2 +-
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 2 +
drivers/misc/imx8ulp/Makefile | 1 -
drivers/misc/imx8ulp/fuse.c | 2 +-
drivers/misc/sentinel/Makefile| 3 +
drivers/misc/{imx8ulp => sentinel}/s400_api.c | 6 +-
.../{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} | 4 +-
15 files changed, 375 insertions(+), 15 deletions(-)
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/mu_hal.h (79%)
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/s400_api.h (100%)
create mode 100644 arch/arm/mach-imx/imx8ulp/ahab.c
create mode 100644 drivers/misc/sentinel/Makefile
rename drivers/misc/{imx8ulp => sentinel}/s400_api.c (98%)
rename drivers/misc/{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} (98%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 12ec661ac3b..29b831422ff 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -922,6 +922,8 @@ config ARCH_IMX8ULP
select OF_CONTROL
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
+ select MISC
+ select IMX_SENTINEL
imply CMD_DM
imply DM_EVENT
@@ -931,6 +933,8 @@ config ARCH_IMX9
select DM
select MACH_IMX
select SUPPORT_SPL
+ select MISC
+ select IMX_SENTINEL
imply CMD_DM
imply DM_EVENT
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 085e12b5d4d..09f352269e5 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -90,7 +90,7 @@ struct arch_global_data {
struct udevice *scu_dev;
#endif
-#ifdef CONFIG_ARCH_IMX8ULP
+#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
b/arch/arm/include/asm/mach-imx/mu_hal.h
similarity index 79%
rename from arch/arm/include/asm/arch-imx8ulp/mu_hal.h
rename to arch/arm/include/asm/mach-imx/mu_hal.h
index 10d966d5d43..5db559c1ac5 100644
--- a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
+++ b/arch/arm/include/asm/mach-imx/mu_hal.h
@@ -3,8 +3,8 @@
* Copyright 2021 NXP
*/
-#ifndef __IMX8ULP_MU_HAL_H__
-#define __IMX8ULP_MU_HAL_H__
+#ifndef __SNT_MU_HAL_H__
+#define __SNT_MU_HAL_H__
void mu_hal_init(ulong base);
int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg);
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
similarity index 100%
rename from arch/arm/include/asm/arch-imx8ulp/s400_api.h
rename to arch/arm/include/asm/mach-imx/s400_api.h
diff --git a/arch/arm/mach-imx/imx8ulp/ahab.c b/arch/arm/mach-imx/imx8ulp/ahab.c
new file mode 100644
index 000..87c4c66a087
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/ahab.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_BASE (0x2201UL)
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xUL)
+
+#define AHAB_NO_AUTHENTICATION_IND 0xee
+#define AHAB_BAD_KEY_HASH_IND 0xfa
+#define AHAB_INVALID_KEY_IND 0xf9
+#define AHAB_BAD_SIGNATURE_IND 0xf0
+#define AHAB_BAD_HASH_IND 0xf1
+
+static void display_ahab_auth_ind(u32 event)
+{
+ u8 resp_ind = (event >> 8) & 0xff;
+
+ switch (resp_ind) {
+ case AHAB_NO_AUTHENTICATION_IND:
+ printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_KEY_HASH_IND:
+ printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_INVALID_KEY_IND:
+ printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_SIGNATURE_IND:
+ printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_HASH_IND:
+ printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ default:
+ printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
+ break;
+ }
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16
[PATCH V2 18/49] imx: imx9: support romapi
From: Peng Fan
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function
prototype common and usable by i.MX9.
Also include mmc env functions that use ROM API.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 4 --
arch/arm/include/asm/mach-imx/sys_proto.h | 4 ++
arch/arm/mach-imx/imx9/soc.c | 37 +++
3 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 05859dfc2aa..a7869fbb573 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -8,10 +8,6 @@
#include
-extern unsigned long rom_pointer[];
-
-ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
-ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 05532ebea89..17c5f44b208 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -180,6 +180,10 @@ enum boot_dev_type_e {
#define ROM_API_OKAY 0xF0
extern struct rom_api *g_rom_api;
+extern unsigned long rom_pointer[];
+
+ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
+ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
/* For i.MX ULP */
#define BT0CFG_LPBOOT_MASK 0x1
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 8b620832b5d..9ea2d51495b 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -29,6 +29,43 @@
DECLARE_GLOBAL_DATA_PTR;
+struct rom_api *g_rom_api = (struct rom_api *)0x1980;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return devno; }
+
+int mmc_get_env_dev(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, ,
+ ((uintptr_t)) ^ QUERY_BT_DEV);
+ set_gd(pgd);
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ debug("boot_type %d, instance %d\n", boot_type, boot_instance);
+
+ /* If not boot from sd/mmc, use default value */
+ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
+ return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+
+ return board_mmc_get_env_dev(boot_instance);
+}
+#endif
+
u32 get_cpu_rev(void)
{
return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
--
2.36.0
[PATCH V2 17/49] imx: imx9: disable watchdog
From: Ye Li
Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 4 ++
arch/arm/mach-imx/imx9/soc.c | 45 ++-
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 32c76ce9c3b..e4babed40fc 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -15,4 +15,8 @@
#define ANATOP_BASE_ADDR0x4448UL
+#define WDG3_BASE_ADDR 0x4249UL
+#define WDG4_BASE_ADDR 0x424aUL
+#define WDG5_BASE_ADDR 0x424bUL
+
#endif
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 4b8f1ca30d5..8b620832b5d 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -34,6 +34,45 @@ u32 get_cpu_rev(void)
return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
}
+#define UNLOCK_WORD 0xD928C520 /* unlock word */
+#define REFRESH_WORD 0xB480A602 /* refresh word */
+
+static void disable_wdog(void __iomem *wdog_base)
+{
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ /* default is 32bits cmd */
+ writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */
+
+ if (!(val_cs & 0x800)) {
+ writel(UNLOCK_WORD, (wdog_base + 0x04));
+ while (!(readl(wdog_base + 0x00) & 0x800))
+ ;
+ }
+ writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+ writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */
+
+ while (!(readl(wdog_base + 0x00) & 0x400))
+ ;
+}
+
+void init_wdog(void)
+{
+ u32 src_val;
+
+ disable_wdog((void __iomem *)WDG3_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG4_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG5_BASE_ADDR);
+
+ src_val = readl(0x54460018); /* reset mask */
+ src_val &= ~0x1c;
+ writel(src_val, 0x54460018);
+}
+
static struct mm_region imx93_mem_map[] = {
{
/* ROM */
@@ -123,8 +162,12 @@ int ft_system_setup(void *blob, struct bd_info *bd)
int arch_cpu_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ /* Disable wdog */
+ init_wdog();
+
clock_init();
+ }
return 0;
}
--
2.36.0
[PATCH V2 12/49] imx: pinctrl: add pinctrl and pinfunc file for i.MX93
From: Peng Fan Add the pinctrl driver and pinfunc header file to support iMX93 Signed-off-by: Peng Fan --- arch/arm/dts/imx93-pinfunc.h| 625 drivers/pinctrl/nxp/Kconfig | 13 + drivers/pinctrl/nxp/Makefile| 1 + drivers/pinctrl/nxp/pinctrl-imx93.c | 37 ++ 4 files changed, 676 insertions(+) create mode 100644 arch/arm/dts/imx93-pinfunc.h create mode 100644 drivers/pinctrl/nxp/pinctrl-imx93.c diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h new file mode 100644 index 000..7f0136c70b6 --- /dev/null +++ b/arch/arm/dts/imx93-pinfunc.h @@ -0,0 +1,625 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DTS_IMX93_PINFUNC_H +#define __DTS_IMX93_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI0x 0x01B0 0x03E0 0x0 0x0 +#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x 0x01B0 0x 0x1 0x0 +#define MX93_PAD_DAP_TDI__CAN2_TX 0x 0x01B0 0x 0x3 0x0 +#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO300x 0x01B0 0x 0x4 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x 0x01B0 0x03CC 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x 0x01B0 0x0438 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03E4 0x0 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x 0x4 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO290x0004 0x01B4 0x03D0 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x 0x4 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x 0x5 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B0x0008 0x01B8 0x0434 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x 0x0 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x 0x1 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX0x000C 0x01BC 0x0364 0x3 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x 0x4 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x 0x5 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x043C 0x6 0x0 +#define MX93_PAD_GPIO_IO00__GPIO2_IO000x0010 0x01C0 0x 0x0 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA0x0010 0x01C0 0x03EC 0x1 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x 0x2 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x 0x3 0x0 +#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x 0x4 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX0x0010 0x01C0 0x043C 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA0x0010 0x01C0 0x03F4 0x6 0x0 +#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 +#define MX93_PAD_GPIO_IO01__GPIO2_IO010x0014 0x01C4 0x 0x0 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL0x0014 0x01C4 0x03E8 0x1 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x 0x2 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x 0x3 0x0 +#define MX93_PAD_GPIO_IO01__LPSPI6_SIN0x0014 0x01C4 0x 0x4 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX0x0014 0x01C4 0x0438 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL0x0014 0x01C4 0x03F0 0x6 0x0 +#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 +#define MX93_PAD_GPIO_IO02__GPIO2_IO020x0018 0x01C8 0x 0x0 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA0x0018 0x01C8 0x 0x1 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC0x0018 0x01C8 0x 0x2 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x 0x3 0x0 +#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x 0x4 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA0x0018
[PATCH V2 14/49] mmc: fsl_esdhc_imx: Support i.MX9
From: Peng Fan Support i.MX9 for fsl_esdhc_imx driver Signed-off-by: Peng Fan --- drivers/mmc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 5a87db6be08..4d31fbcd527 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -852,7 +852,7 @@ config FSL_ESDHC_IMX config FSL_USDHC bool "Freescale/NXP i.MX uSDHC controller support" - depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMXRT + depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT select FSL_ESDHC_IMX help This enables the Ultra Secured Digital Host Controller enhancements -- 2.36.0
[PATCH V2 13/49] imx: imx9: Add CCM and clock API support
From: Peng Fan Add clock API to support CCM root clock and LPCG setting Set the CCM AUTHEN register to allow non-secure world to set root clock and lpcg. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 arch/arm/include/asm/arch-imx9/clock.h| 239 +++ arch/arm/include/asm/arch-imx9/imx-regs.h | 6 +- arch/arm/mach-imx/imx9/Makefile | 2 +- arch/arm/mach-imx/imx9/clock.c| 769 +- arch/arm/mach-imx/imx9/clock_root.c | 438 arch/arm/mach-imx/imx9/soc.c | 3 + 7 files changed, 1720 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx9/ccm_regs.h create mode 100644 arch/arm/mach-imx/imx9/clock_root.c diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h new file mode 100644 index 000..d326a6ea516 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__ +#define __ASM_ARCH_IMX9_CCM_REGS_H__ +#define IMX93_CLK_ROOT_MAX 95 +#define IMX93_CLK_CCGR_MAX 127 + +#define ARM_A55_PERIPH_CLK_ROOT0 +#define ARM_A55_MTR_BUS_CLK_ROOT 1 +#define ARM_A55_CLK_ROOT 2 +#define M33_CLK_ROOT 3 +#define SENTINEL_CLK_ROOT 4 +#define BUS_WAKEUP_CLK_ROOT5 +#define BUS_AON_CLK_ROOT 6 +#define WAKEUP_AXI_CLK_ROOT7 +#define SWO_TRACE_CLK_ROOT 8 +#define M33_SYSTICK_CLK_ROOT 9 +#define FLEXIO1_CLK_ROOT 10 +#define FLEXIO2_CLK_ROOT 11 +#define LPIT1_CLK_ROOT 12 +#define LPIT2_CLK_ROOT 13 +#define LPTMR1_CLK_ROOT14 +#define LPTMR2_CLK_ROOT15 +#define TPM1_CLK_ROOT 16 +#define TPM2_CLK_ROOT 17 +#define TPM3_CLK_ROOT 18 +#define TPM4_CLK_ROOT 19 +#define TPM5_CLK_ROOT 20 +#define TPM6_CLK_ROOT 21 +#define FLEXSPI1_CLK_ROOT 22 +#define CAN1_CLK_ROOT 23 +#define CAN2_CLK_ROOT 24 +#define LPUART1_CLK_ROOT 25 +#define LPUART2_CLK_ROOT 26 +#define LPUART3_CLK_ROOT 27 +#define LPUART4_CLK_ROOT 28 +#define LPUART5_CLK_ROOT 29 +#define LPUART6_CLK_ROOT 30 +#define LPUART7_CLK_ROOT 31 +#define LPUART8_CLK_ROOT 32 +#define LPI2C1_CLK_ROOT33 +#define LPI2C2_CLK_ROOT34 +#define LPI2C3_CLK_ROOT35 +#define LPI2C4_CLK_ROOT36 +#define LPI2C5_CLK_ROOT37 +#define LPI2C6_CLK_ROOT38 +#define LPI2C7_CLK_ROOT39 +#define LPI2C8_CLK_ROOT40 +#define LPSPI1_CLK_ROOT41 +#define LPSPI2_CLK_ROOT42 +#define LPSPI3_CLK_ROOT43 +#define LPSPI4_CLK_ROOT44 +#define LPSPI5_CLK_ROOT45 +#define LPSPI6_CLK_ROOT46 +#define LPSPI7_CLK_ROOT47 +#define LPSPI8_CLK_ROOT48 +#define I3C1_CLK_ROOT 49 +#define I3C2_CLK_ROOT 50 +#define USDHC1_CLK_ROOT51 +#define USDHC2_CLK_ROOT52 +#define USDHC3_CLK_ROOT53 +#define SAI1_CLK_ROOT 54 +#define SAI2_CLK_ROOT 55 +#define SAI3_CLK_ROOT 56 +#define CCM_CKO1_CLK_ROOT 57 +#define CCM_CKO2_CLK_ROOT 58 +#define CCM_CKO3_CLK_ROOT 59 +#define CCM_CKO4_CLK_ROOT 60 +#define HSIO_CLK_ROOT 61 +#define HSIO_USB_TEST_60M_CLK_ROOT 62 +#define HSIO_ACSCAN_80M_CLK_ROOT 63 +#define HSIO_ACSCAN_480M_CLK_ROOT 64 +#define NIC_CLK_ROOT 65 +#define NIC_APB_CLK_ROOT 66 +#define ML_APB_CLK_ROOT67 +#define ML_CLK_ROOT68 +#define MEDIA_AXI_CLK_ROOT 69 +#define MEDIA_APB_CLK_ROOT 70 +#define MEDIA_LDB_CLK_ROOT 71 +#define MEDIA_DISP_PIX_CLK_ROOT72 +#define CAM_PIX_CLK_ROOT 73 +#define MIPI_TEST_BYTE_CLK_ROOT74 +#define MIPI_PHY_CFG_CLK_ROOT 75 +#define DRAM_ALT_CLK_ROOT 76 +#define DRAM_APB_CLK_ROOT 77 +#define ADC_CLK_ROOT 78 +#define PDM_CLK_ROOT 79 +#define TSTMR1_CLK_ROOT80 +#define TSTMR2_CLK_ROOT81 +#define MQS1_CLK_ROOT
[PATCH V2 08/49] imx: add USB2_BOOT type
From: Peng Fan
Add USB2_BOOT type for i.MX8ULP and i.MX9
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
arch/arm/mach-imx/imx_romapi.c| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h
b/arch/arm/include/asm/mach-imx/boot_mode.h
index 6dc58559680..a568c443722 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -29,6 +29,7 @@ enum boot_device {
QSPI_BOOT,
FLEXSPI_BOOT,
USB_BOOT,
+ USB2_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
};
diff --git a/arch/arm/mach-imx/imx_romapi.c b/arch/arm/mach-imx/imx_romapi.c
index 3b2cc6935dc..0f94091fc53 100644
--- a/arch/arm/mach-imx/imx_romapi.c
+++ b/arch/arm/mach-imx/imx_romapi.c
@@ -50,7 +50,7 @@ enum boot_device get_boot_device(void)
boot_dev = QSPI_BOOT;
break;
case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
+ boot_dev = boot_instance + USB_BOOT;
break;
default:
break;
--
2.36.0
[PATCH V2 11/49] gpio: pca953x: support pcal6524
From: Peng Fan
Support pcal6524 IO expander driver
Signed-off-by: Peng Fan
---
drivers/gpio/pca953x_gpio.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index e98e1e56dbc..4654f9e0989 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -43,6 +43,8 @@
#define PCA_GPIO_MASK 0x00FF
#define PCA_INT 0x0100
+#define PCA_PCAL BIT(9)
+#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
#define PCA953X_TYPE0x1000
#define PCA957X_TYPE0x2000
#define PCA_TYPE_MASK 0xF000
@@ -393,6 +395,8 @@ static const struct udevice_id pca953x_ids[] = {
{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+ { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
+
{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
--
2.36.0
[PATCH V2 07/49] imx: move get_boot_device to common file
From: Peng Fan
i.MX8MN/P/ULP supports ROM API, they have almost same get_boot_device
implementation, so move to a common file. And when support i.MX9,
no need to include the other function copy.
Since sys_proto.h is included in imx_romapi.c, there will be build
warning for i.MX8M because wdog_regs not defined, so include imx-regs.h
in i.MX8M sys_proro.h
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/sys_proto.h | 1 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/imx8m/soc.c | 47
arch/arm/mach-imx/imx8ulp/soc.c | 44 ---
arch/arm/mach-imx/imx_romapi.c | 60 +
5 files changed, 62 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/mach-imx/imx_romapi.c
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h
b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index f8854e77128..55b46afaf78 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -7,6 +7,7 @@
#define __ARCH_NMX8M_SYS_PROTO_H
#include
+#include
void set_wdog_reset(struct wdog_regs *wdog);
void enable_tzc380(void);
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index aa0b6447f14..c5be63dfe4f 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -242,4 +242,5 @@ obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
obj-$(CONFIG_ARCH_IMXRT) += imxrt/
+obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP) += imx_romapi.o
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 59335356b57..d2a856f5410 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -599,53 +599,6 @@ int arch_cpu_init(void)
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
struct rom_api *g_rom_api = (struct rom_api *)0x980;
-
-enum boot_device get_boot_device(void)
-{
- volatile gd_t *pgd = gd;
- int ret;
- u32 boot;
- u16 boot_type;
- u8 boot_instance;
- enum boot_device boot_dev = SD1_BOOT;
-
- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, ,
- ((uintptr_t)) ^ QUERY_BT_DEV);
- set_gd(pgd);
-
- if (ret != ROM_API_OKAY) {
- puts("ROMAPI: failure at query_boot_info\n");
- return -1;
- }
-
- boot_type = boot >> 16;
- boot_instance = (boot >> 8) & 0xff;
-
- switch (boot_type) {
- case BT_DEV_TYPE_SD:
- boot_dev = boot_instance + SD1_BOOT;
- break;
- case BT_DEV_TYPE_MMC:
- boot_dev = boot_instance + MMC1_BOOT;
- break;
- case BT_DEV_TYPE_NAND:
- boot_dev = NAND_BOOT;
- break;
- case BT_DEV_TYPE_FLEXSPINOR:
- boot_dev = QSPI_BOOT;
- break;
- case BT_DEV_TYPE_SPI_NOR:
- boot_dev = SPI_NOR_BOOT;
- break;
- case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
- break;
- default:
- break;
- }
-
- return boot_dev;
-}
#endif
#if defined(CONFIG_IMX8M)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 35020c9714d..529fda4594e 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -34,50 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
struct rom_api *g_rom_api = (struct rom_api *)0x1980;
-enum boot_device get_boot_device(void)
-{
- volatile gd_t *pgd = gd;
- int ret;
- u32 boot;
- u16 boot_type;
- u8 boot_instance;
- enum boot_device boot_dev = SD1_BOOT;
-
- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, ,
- ((uintptr_t)) ^ QUERY_BT_DEV);
- set_gd(pgd);
-
- if (ret != ROM_API_OKAY) {
- puts("ROMAPI: failure at query_boot_info\n");
- return -1;
- }
-
- boot_type = boot >> 16;
- boot_instance = (boot >> 8) & 0xff;
-
- switch (boot_type) {
- case BT_DEV_TYPE_SD:
- boot_dev = boot_instance + SD1_BOOT;
- break;
- case BT_DEV_TYPE_MMC:
- boot_dev = boot_instance + MMC1_BOOT;
- break;
- case BT_DEV_TYPE_NAND:
- boot_dev = NAND_BOOT;
- break;
- case BT_DEV_TYPE_FLEXSPINOR:
- boot_dev = QSPI_BOOT;
- break;
- case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
- break;
- default:
- break;
- }
-
- return boot_dev;
-}
-
bool is_usb_boot(void)
{
return get_boot_device() == USB_BOOT;
diff --git a/arch/arm/mach-imx/imx_romapi.c b/arch/arm/mach-imx/imx_romapi.c
new file mode 100644
index 000..3b2cc6935dc
--- /dev/null
+++ b/arch/arm/mach-imx/imx_romapi.c
@@
[PATCH V2 06/49] imx: move get_boot_device to common header
From: Peng Fan
Most i.MX implements get_boot_device, move it to common header to
simplify code
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8/sys_proto.h| 1 -
arch/arm/include/asm/arch-imx8m/sys_proto.h | 1 -
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 -
arch/arm/include/asm/arch-mx7/sys_proto.h | 1 -
arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 1 -
arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++
6 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h
b/arch/arm/include/asm/arch-imx8/sys_proto.h
index 6f1fc8f999d..d38f606e07e 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -23,7 +23,6 @@ struct pass_over_info_t {
extern unsigned long boot_pointer[];
void build_info(void);
-enum boot_device get_boot_device(void);
int print_bootinfo(void);
int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
int imx8_power_domain_lookup_name(const char *name,
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h
b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index d328542ece2..f8854e77128 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -12,6 +12,5 @@ void set_wdog_reset(struct wdog_regs *wdog);
void enable_tzc380(void);
void restore_boot_params(void);
extern unsigned long rom_pointer[];
-enum boot_device get_boot_device(void);
bool is_usb_boot(void);
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 5f030eaa0ad..05859dfc2aa 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -15,7 +15,6 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32
rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
-enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h
b/arch/arm/include/asm/arch-mx7/sys_proto.h
index e46a02198d6..634736cc09c 100644
--- a/arch/arm/include/asm/arch-mx7/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7/sys_proto.h
@@ -8,6 +8,5 @@
#include
void set_wdog_reset(struct wdog_regs *wdog);
-enum boot_device get_boot_device(void);
#endif /* __SYS_PROTO_IMX7_ */
diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
index 0daa922fad9..7adf4720fec 100644
--- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
@@ -8,5 +8,4 @@
#include
-enum boot_device get_boot_device(void);
#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index fc5e5c66aad..cd69384d8ef 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -243,4 +243,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
void enable_ca7_smp(void);
#endif
+enum boot_device get_boot_device(void);
+
#endif
--
2.36.0
[PATCH V2 05/49] imx: simplify dependency with SPL_BOOTROM_SUPPORT
From: Peng Fan
For SoCs support ROM API, CONFIG_SPL_BOOTROM_SUPPORT is needed,
so use this macro to guard the code to avoid extend the list.
And drop the guard with structure definition, there is no need.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 2 --
arch/arm/mach-imx/Kconfig | 3 ++-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index fdbbfb169cb..fc5e5c66aad 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -146,7 +146,6 @@ struct rproc_att {
u32 size; /* size of reg range */
};
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP)
struct rom_api {
u16 ver;
u16 tag;
@@ -178,7 +177,6 @@ enum boot_dev_type_e {
#define ROM_API_OKAY 0xF0
extern struct rom_api *g_rom_api;
-#endif
/* For i.MX ULP */
#define BT0CFG_LPBOOT_MASK 0x1
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ad0fb365023..5e9c4d9b355 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -166,7 +166,8 @@ config DDRMC_VF610_CALIBRATION
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
- depends on IMX8MN || IMX8MP || IMX8ULP
+ depends on SPL_BOOTROM_SUPPORT
+ default 0
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
--
2.36.0
[PATCH V2 03/49] imx: Change USB boot device type
From: Ye Li The SPL SDP is configured as BOOT_DEVICE_BOARD, so when booting from USB, change its type to BOOT_DEVICE_BOARD, so we can use SDP. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 64ca2967721..e89e2277ef7 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -177,7 +177,7 @@ u32 spl_boot_device(void) case QSPI_BOOT: return BOOT_DEVICE_NOR; case USB_BOOT: - return BOOT_DEVICE_USB; + return BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; } -- 2.36.0
[PATCH V2 02/49] arm: makefile: cleanup mach-imx usage
From: Peng Fan All the SoCs use mach-imx has CONFIG_MACH_IMX selected, so the macro could be the gate to build arch/arm/mach-imx to simplify the rules. Signed-off-by: Peng Fan --- arch/arm/Makefile | 12 ++-- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 64c58f4c4a3..a69cb1f610f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -96,6 +96,8 @@ machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5 +machine-$(CONFIG_MACH_IMX) += imx + machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) @@ -114,16 +116,6 @@ libs-y += arch/arm/cpu/$(CPU)/ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ -ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) -libs-y += arch/arm/mach-imx/ -endif -else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610)) -libs-y += arch/arm/mach-imx/ -endif -endif - ifneq (,$(filter $(SOC), kirkwood)) libs-y += arch/arm/mach-mvebu/ endif -- 2.36.0
[PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE
From: Peng Fan
The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
set to 0x7E1000.
Signed-off-by: Peng Fan
---
common/spl/Kconfig| 1 +
configs/imx8mm-cl-iot-gate-optee_defconfig| 1 -
configs/imx8mm-cl-iot-gate_defconfig | 1 -
configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
configs/imx8mm-mx8menlo_defconfig | 1 -
configs/imx8mm_beacon_defconfig | 1 -
configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
configs/imx8mm_evk_defconfig | 1 -
configs/imx8mm_venice_defconfig | 1 -
configs/phycore-imx8mm_defconfig | 1 -
configs/verdin-imx8mm_defconfig | 1 -
12 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2ad2351c6eb..848237c1e85 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -82,6 +82,7 @@ config SPL_MAX_SIZE
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x2 && !MACH_SUN50I_H616
default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+ default 0x27000 if IMX8MM && SPL_TEXT_BASE = 0x7E1000
default 0x0
help
Maximum size of the SPL image (text, data, rodata, and linker lists
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig
b/configs/imx8mm-cl-iot-gate-optee_defconfig
index 80055912096..a02010621ea 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-cl-iot-gate_defconfig
b/configs/imx8mm-cl-iot-gate_defconfig
index dae7ddc20e0..f05ac98326c 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -25,7 +25,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index 69ebc6fa325..7d08b244f2c 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index a3c142feb28..acc5d34659b 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-mx8menlo_defconfig
b/configs/imx8mm-mx8menlo_defconfig
index ec672f8764e..2a6f3b7c412 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -34,7 +34,6 @@ CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index bf2b6486347..fd21f9f6db8 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -25,7 +25,6 @@ CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run
loadbootscript; then run bootscript; else if run loadimage; then run mmcboot;
else run netboot; fi; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig
b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 399b388460f..1fae936bda5 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -41,7 +41,6 @@ CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
Re: [PATCH v5 2/2] board: mntre: imx8mq: Add MNT Reform 2 board support
On Sun, Jun 26, 2022 at 6:42 PM Patrick Wildt wrote:
> +static iomux_v3_cfg_t const uart_pads[] = {
> + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
As you use DM_SERIAL, this is no longer necessary.
> +int board_phy_config(struct phy_device *phydev)
> +{
> + int val;
> +
> + /*
> +* Ar803x phy SmartEEE feature cause link status generates glitch,
> +* which cause ethernet link down/up issue, so disable SmartEEE
> +*/
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
> + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val & ~(1 << 8));
> +
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
> + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
> + val &= ~0x11c;
> + val |= 0x80; /* 1/2 drive strength */
> + val |= 0x18; /* 125 MHz */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
> +
> + /* rgmii tx clock delay enable */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val | 0x0100);
It seems the PHY code could be removed in favor of DM.
> +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
With DM, this is not needed.
Re: [PATCH v5 1/2] arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3
On Sun, Jun 26, 2022 at 6:41 PM Patrick Wildt wrote: > > --- Commit log and Signed-off-by are missing.
RE: [v4 00/12] Add ASPEED SPI controller driver
Hi Cédric, > -Original Message- > From: Cédric Le Goater > Sent: Monday, June 27, 2022 12:16 AM > To: Chin-Ting Kuo ; ChiaWei Wang > ; lu...@denx.de; sean...@gmail.com; > Ryan Chen ; BMC-SW > ; ja...@amarulasolutions.com; vigne...@ti.com; > u-boot@lists.denx.de; p.ya...@ti.com > Cc: tr...@konsulko.com > Subject: Re: [v4 00/12] Add ASPEED SPI controller driver > > On 6/26/22 06:56, Chin-Ting Kuo wrote: > > Hi All, > > > > Are there any comments about this patch series?* > > Sorry, I haven't had time to take a look at the driver. I will try this week. Okay and thanks for the reply. Chin-Ting > > Thanks, > > C. > > > > > > > Thanks. > > > > Best Wishes, > > Chin-Ting > > > >> -Original Message- > >> From: Chin-Ting Kuo > >> Sent: Tuesday, May 24, 2022 1:57 PM > >> To: ChiaWei Wang ; lu...@denx.de; > >> sean...@gmail.com; Ryan Chen ; BMC-SW > >> ; ja...@amarulasolutions.com; > vigne...@ti.com; > >> c...@kaod.org; u-boot@lists.denx.de; p.ya...@ti.com > >> Subject: [v4 00/12] Add ASPEED SPI controller driver > >> > >> This patch series aims to porting ASPEED FMC/SPI memory controller > >> driver with spi-mem interface. spi-mem dirmap framework is also > >> synchronized from Linux. These patches have been verified on both > >> AST2600 and AST2500 EVBs. > >> > >> Changes in v2: > >>- Separate defconfig files from the SPI driver patch. > >>- Use "if (CONFIG_IS_ENABLED(SPI_DIRMAP))" to wrap > >> spi_dirmap related functions. > >>- Add Winbond w25q512jv flash ID. > >> > >> Changes in v3: > >>- Get AHB bus clock frequency from the function parameter. > >>- Fix a grammatical error in spi-mem.h. > >> > >> Changes in v4: > >>- Fix bug when SPI_NOR_4B_OPCODES flag is set. > >> > >> Chin-Ting Kuo (12): > >>clk: aspeed: Get HCLK frequency support > >>pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support > >>spi: aspeed: Add ASPEED SPI controller driver > >>configs: aspeed: Enable SPI flash features > >>MAINTAINERS: Add ASPEED SPI driver file > >>arm: dts: aspeed: Update SPI flash node settings > >>spi-mem: Add dirmap API from Linux > >>mtd: spi-nor: Use spi-mem dirmap API > >>spi: aspeed: SPI dirmap read support > >>configs: aspeed: Enable CONFIG_SPI_DIRMAP > >>mtd: spi-nor-ids: Add Winbond W25Q512JV ID > >>spi: aspeed: Fix bug when SPI_NOR_4B_OPCODES flag is set > >> > >> MAINTAINERS | 7 + > >> arch/arm/dts/ast2500-evb.dts | 33 + > >> arch/arm/dts/ast2500.dtsi| 23 +- > >> arch/arm/dts/ast2600-evb.dts | 8 - > >> arch/arm/dts/ast2600.dtsi| 34 +- > >> configs/evb-ast2500_defconfig| 14 + > >> configs/evb-ast2600_defconfig| 14 + > >> drivers/clk/aspeed/clk_ast2500.c | 23 + > >> drivers/mtd/spi/sf_probe.c | 76 ++ > >> drivers/mtd/spi/spi-nor-core.c | 55 +- > >> drivers/mtd/spi/spi-nor-ids.c| 5 + > >> drivers/pinctrl/aspeed/pinctrl_ast2500.c | 2 + > >> drivers/spi/Kconfig | 18 + > >> drivers/spi/Makefile | 1 + > >> drivers/spi/spi-aspeed.c | 914 > >> +++ > >> drivers/spi/spi-mem.c| 268 +++ > >> include/linux/mtd/spi-nor.h | 18 + > >> include/spi-mem.h| 79 ++ > >> 18 files changed, 1546 insertions(+), 46 deletions(-) create mode > >> 100644 drivers/spi/spi-aspeed.c > >> > >> -- > >> 2.25.1 > >
Re: [PATCH v2] sunxi: fix initial environment loading without MMC
Hi Andre,
On 6/24/22 11:12 AM, Andre Przywara wrote:
> From: Samuel Holland
>
> Commit e42dad4168fe ("sunxi: use boot source for determining environment
> location") changed our implementation of env_get_location() and enabled
> it for every board, even those without MMC support (like the C.H.I.P.
> boards). However the default fallback location of ENVL_FAT requires MMC
> support compiled in, so the board hangs when trying to initially load
> the environment.
>
> Change the algorithm to only return configured environment locations,
> and improve the fallback algorithm on the way.
>
> The env_init() routine calling this function here does not behave well
> if the return value is ENVL_UNKNOWN on the very first call: it will make
> U-Boot proper silently hang very early.
> Work around this issue by making sure we return some configured (dummy)
> environment location when prio is 0. This for instance happens when
> booting via FEL.
>
> This fixes U-Boot loading on the C.H.I.P. boards.
>
> Fixes: e42dad4168fe ("sunxi: use boot source for determining environment
> location")
> Reported-by: Chris Morgan
> Signed-off-by: Samuel Holland
> [Andre: fix FEL boot case by not returning ENVL_UNKNOWN when prio==0]
> Signed-off-by: Andre Przywara
> ---
> Hi Samuel,
>
> I cheekily added your Signed-off-by:, as I made this your patch (since
> you came up with it in that email reply some weeks ago). I hope that's
> fine.
Yes, this is fine with me.
Regards,
Samuel
Re: [PATCH 3/7] reset: sunxi: Get the reset count from the CCU descriptor
On Mon, 9 May 2022 00:29:33 -0500
Samuel Holland wrote:
> This allows all of the clock drivers to use a common bind function.
Looks good, and a nice cleanup. Added the F1C100s on the way.
> Signed-off-by: Samuel Holland
Reviewed-by: Andre Przywara
Thanks,
Andre
> ---
>
> drivers/clk/sunxi/clk_a10.c | 7 +--
> drivers/clk/sunxi/clk_a10s.c | 7 +--
> drivers/clk/sunxi/clk_a23.c | 7 +--
> drivers/clk/sunxi/clk_a31.c | 7 +--
> drivers/clk/sunxi/clk_a31_r.c | 7 +--
> drivers/clk/sunxi/clk_a64.c | 7 +--
> drivers/clk/sunxi/clk_a80.c | 12 +---
> drivers/clk/sunxi/clk_a83t.c | 7 +--
> drivers/clk/sunxi/clk_h3.c| 7 +--
> drivers/clk/sunxi/clk_h6.c| 7 +--
> drivers/clk/sunxi/clk_h616.c | 7 +--
> drivers/clk/sunxi/clk_h6_r.c | 7 +--
> drivers/clk/sunxi/clk_r40.c | 7 +--
> drivers/clk/sunxi/clk_sunxi.c | 5 +
> drivers/clk/sunxi/clk_v3s.c | 7 +--
> drivers/reset/reset-sunxi.c | 6 ++
> include/clk/sunxi.h | 9 +++--
> 17 files changed, 28 insertions(+), 95 deletions(-)
>
> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
> index 6b58cffc8a..e5374f6cf0 100644
> --- a/drivers/clk/sunxi/clk_a10.c
> +++ b/drivers/clk/sunxi/clk_a10.c
> @@ -69,11 +69,6 @@ static const struct ccu_desc a10_ccu_desc = {
> .num_resets = ARRAY_SIZE(a10_resets),
> };
>
> -static int a10_clk_bind(struct udevice *dev)
> -{
> - return sunxi_reset_bind(dev, ARRAY_SIZE(a10_resets));
> -}
> -
> static const struct udevice_id a10_ccu_ids[] = {
> { .compatible = "allwinner,sun4i-a10-ccu",
> .data = (ulong)_ccu_desc },
> @@ -89,5 +84,5 @@ U_BOOT_DRIVER(clk_sun4i_a10) = {
> .priv_auto = sizeof(struct ccu_priv),
> .ops= _clk_ops,
> .probe = sunxi_clk_probe,
> - .bind = a10_clk_bind,
> + .bind = sunxi_clk_bind,
> };
> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
> index 81b146ce1e..07d518c121 100644
> --- a/drivers/clk/sunxi/clk_a10s.c
> +++ b/drivers/clk/sunxi/clk_a10s.c
> @@ -54,11 +54,6 @@ static const struct ccu_desc a10s_ccu_desc = {
> .num_resets = ARRAY_SIZE(a10s_resets),
> };
>
> -static int a10s_clk_bind(struct udevice *dev)
> -{
> - return sunxi_reset_bind(dev, ARRAY_SIZE(a10s_resets));
> -}
> -
> static const struct udevice_id a10s_ccu_ids[] = {
> { .compatible = "allwinner,sun5i-a10s-ccu",
> .data = (ulong)_ccu_desc },
> @@ -74,5 +69,5 @@ U_BOOT_DRIVER(clk_sun5i_a10s) = {
> .priv_auto = sizeof(struct ccu_priv),
> .ops= _clk_ops,
> .probe = sunxi_clk_probe,
> - .bind = a10s_clk_bind,
> + .bind = sunxi_clk_bind,
> };
> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
> index c7c78bc7d8..9c0e5db07c 100644
> --- a/drivers/clk/sunxi/clk_a23.c
> +++ b/drivers/clk/sunxi/clk_a23.c
> @@ -73,11 +73,6 @@ static const struct ccu_desc a23_ccu_desc = {
> .num_resets = ARRAY_SIZE(a23_resets),
> };
>
> -static int a23_clk_bind(struct udevice *dev)
> -{
> - return sunxi_reset_bind(dev, ARRAY_SIZE(a23_resets));
> -}
> -
> static const struct udevice_id a23_clk_ids[] = {
> { .compatible = "allwinner,sun8i-a23-ccu",
> .data = (ulong)_ccu_desc },
> @@ -93,5 +88,5 @@ U_BOOT_DRIVER(clk_sun8i_a23) = {
> .priv_auto = sizeof(struct ccu_priv),
> .ops= _clk_ops,
> .probe = sunxi_clk_probe,
> - .bind = a23_clk_bind,
> + .bind = sunxi_clk_bind,
> };
> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
> index c8c7f4ecf5..3d0767e290 100644
> --- a/drivers/clk/sunxi/clk_a31.c
> +++ b/drivers/clk/sunxi/clk_a31.c
> @@ -94,11 +94,6 @@ static const struct ccu_desc a31_ccu_desc = {
> .num_resets = ARRAY_SIZE(a31_resets),
> };
>
> -static int a31_clk_bind(struct udevice *dev)
> -{
> - return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
> -}
> -
> static const struct udevice_id a31_clk_ids[] = {
> { .compatible = "allwinner,sun6i-a31-ccu",
> .data = (ulong)_ccu_desc },
> @@ -112,5 +107,5 @@ U_BOOT_DRIVER(clk_sun6i_a31) = {
> .priv_auto = sizeof(struct ccu_priv),
> .ops= _clk_ops,
> .probe = sunxi_clk_probe,
> - .bind = a31_clk_bind,
> + .bind = sunxi_clk_bind,
> };
> diff --git a/drivers/clk/sunxi/clk_a31_r.c b/drivers/clk/sunxi/clk_a31_r.c
> index 7bf1c4578c..04c238204d 100644
> --- a/drivers/clk/sunxi/clk_a31_r.c
> +++ b/drivers/clk/sunxi/clk_a31_r.c
> @@ -35,11 +35,6 @@ static const struct ccu_desc a31_r_ccu_desc = {
> .num_resets = ARRAY_SIZE(a31_r_resets),
> };
>
> -static int a31_r_clk_bind(struct udevice *dev)
> -{
> - return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
> -}
> -
> static const struct udevice_id
Re: [PATCH 2/7] clk: sunxi: Prevent out-of-bounds gate array access
On Mon, 9 May 2022 00:29:32 -0500
Samuel Holland wrote:
> Because the gate arrays are not given explicit sizes, the arrays are
> only as large as the highest-numbered gate described in the driver.
> However, only a subset of the CCU clocks are needed by U-Boot. So there
> are valid clock specifiers with indexes greater than the size of the
> arrays. Referencing any of these clocks causes out-of-bounds access.
> Fix this by checking the identifier against the size of the array.
>
> Fixes: 0d47bc705651 ("clk: Add Allwinner A64 CLK driver")
> Signed-off-by: Samuel Holland
That's a good addition! Amended the patch to cover CCU_CLK_F_DUMMY_GATE.
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
>
> drivers/clk/sunxi/clk_sunxi.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
> index 9673b58a49..3108e5b66d 100644
> --- a/drivers/clk/sunxi/clk_sunxi.c
> +++ b/drivers/clk/sunxi/clk_sunxi.c
> @@ -18,6 +18,9 @@
> static const struct ccu_clk_gate *priv_to_gate(struct ccu_priv *priv,
> unsigned long id)
> {
> + if (id >= priv->desc->num_gates)
> + return NULL;
> +
> return >desc->gates[id];
> }
>
> @@ -27,7 +30,7 @@ static int sunxi_set_gate(struct clk *clk, bool on)
> const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id);
> u32 reg;
>
> - if (!(gate->flags & CCU_CLK_F_IS_VALID)) {
> + if (!gate || !(gate->flags & CCU_CLK_F_IS_VALID)) {
> printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
> return 0;
> }
Re: [PATCH v2] ARM: dts: sun4i: Sync from Linux v5.18-rc1
On Wed, 25 May 2022 22:26:02 -0500
Samuel Holland wrote:
Hi,
> Copy the devicetree source for the A10 SoC and all existing boards
> verbatim from the Linux v5.18-rc1 tag.
>
> The previous version of this change was only partially applied.
Oops, indeed. Patchwork didn't pick this one patch up, and I misapplied
this to the tree I sent the other PR from.
Thanks for noticing and the patch!
> Fixes: 4746694cba74 ("ARM: dts: sun4i: Sync from Linux v5.18-rc1")
> Signed-off-by: Samuel Holland
Applied to sunxi/master, for v2022.07.
Cheers,
Andre
> ---
>
> Changes in v2:
> - Rebased. The commit that was sent in Andre's PR only contained
>changes from one file -- the one with the character set change.
>
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/axp209.dtsi | 6 +-
> arch/arm/dts/sun4i-a10-a1000.dts | 31 ++-
> arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 2 +-
> arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts| 20 +-
> arch/arm/dts/sun4i-a10-cubieboard.dts | 16 +-
> arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 21 +-
> arch/arm/dts/sun4i-a10-hackberry.dts | 2 +-
> arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 20 +-
> arch/arm/dts/sun4i-a10-inet1.dts | 21 +-
> arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 74 ++
> .../dts/sun4i-a10-itead-iteaduino-plus.dts| 2 +-
> arch/arm/dts/sun4i-a10-jesurun-q5.dts | 4 +-
> arch/arm/dts/sun4i-a10-marsboard.dts | 22 +-
> arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 33 +--
> arch/arm/dts/sun4i-a10-pcduino.dts| 20 +-
> arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 21 +-
> arch/arm/dts/sun4i-a10-topwise-a721.dts | 242 ++
> arch/arm/dts/sun4i-a10.dtsi | 135 +-
> 19 files changed, 459 insertions(+), 236 deletions(-)
> create mode 100644 arch/arm/dts/sun4i-a10-topwise-a721.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0a2713c06a3c..1bceae78c3c1 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -539,7 +539,8 @@ dtb-$(CONFIG_MACH_SUN4I) += \
> sun4i-a10-olinuxino-lime.dtb \
> sun4i-a10-pcduino.dtb \
> sun4i-a10-pcduino2.dtb \
> - sun4i-a10-pov-protab2-ips9.dtb
> + sun4i-a10-pov-protab2-ips9.dtb \
> + sun4i-a10-topwise-a721.dtb
> dtb-$(CONFIG_MACH_SUN5I) += \
> sun5i-a10s-auxtek-t003.dtb \
> sun5i-a10s-auxtek-t004.dtb \
> diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi
> index 0d9ff12bdf28..ca240cd6f6c3 100644
> --- a/arch/arm/dts/axp209.dtsi
> +++ b/arch/arm/dts/axp209.dtsi
> @@ -53,7 +53,7 @@
> interrupt-controller;
> #interrupt-cells = <1>;
>
> - ac_power_supply: ac-power-supply {
> + ac_power_supply: ac-power {
> compatible = "x-powers,axp202-ac-power-supply";
> status = "disabled";
> };
> @@ -69,7 +69,7 @@
> #gpio-cells = <2>;
> };
>
> - battery_power_supply: battery-power-supply {
> + battery_power_supply: battery-power {
> compatible = "x-powers,axp209-battery-power-supply";
> status = "disabled";
> };
> @@ -112,7 +112,7 @@
> };
> };
>
> - usb_power_supply: usb-power-supply {
> + usb_power_supply: usb-power {
> compatible = "x-powers,axp202-usb-power-supply";
> status = "disabled";
> };
> diff --git a/arch/arm/dts/sun4i-a10-a1000.dts
> b/arch/arm/dts/sun4i-a10-a1000.dts
> index 6c254ec4c85b..20f9ed244851 100644
> --- a/arch/arm/dts/sun4i-a10-a1000.dts
> +++ b/arch/arm/dts/sun4i-a10-a1000.dts
> @@ -60,15 +60,26 @@
> stdout-path = "serial0:115200n8";
> };
>
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <_out_con>;
> + };
> + };
> + };
> +
> leds {
> compatible = "gpio-leds";
>
> - red {
> + led-0 {
> label = "a1000:red:usr";
> gpios = < 7 10 GPIO_ACTIVE_HIGH>;
> };
>
> - blue {
> + led-1 {
> label = "a1000:blue:pwr";
> gpios = < 7 20 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -125,7 +136,7 @@
> };
>
> {
> - phy = <>;
> + phy-handle = <>;
> status = "okay";
> };
>
> @@ -133,6 +144,20 @@
> status = "okay";
> };
>
> + {
> + status = "okay";
> +};
> +
> + {
> + status = "okay";
> +};
> +
> +_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <_con_in>;
> + };
> +};
> +
> {
> status = "okay";
>
> diff --git a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
>
Re: [PATCH] sunxi: usb: convert PHY GPIO functions to DM
On Wed, 8 Jun 2022 01:06:04 +0100
Andre Przywara wrote:
> The Allwinner USB PHY driver is still using the legacy GPIO interface,
> which is now implemented by the DM_GPIO compat functions.
> Those seem to have some design flaws, as setting the direction, then
> later setting the value will not work, if the DM_GPIO driver is
> implementing set_flags.
>
> Fix this by using the dm_ version of the direct GPIO interface, which
> uses struct gpio_desc structs to handle requested GPIOs, and actually
> keeps the flags we set earlier.
>
> This fixes USB operation on boards which need to toggle the VBUS supply
> via a GPIO, like the Teres-I laptop or the BananaPi M2 Berry board.
>
> Signed-off-by: Andre Przywara
> Reported-by: Milan P. Stanić
Applied to sunxi/master, for v2022.07.
Cheers,
Andre
> ---
> drivers/phy/allwinner/phy-sun4i-usb.c | 59 +++
> 1 file changed, 33 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> b/drivers/phy/allwinner/phy-sun4i-usb.c
> index 86c589a65fd..aef2cb8f6f8 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -125,9 +125,9 @@ struct sun4i_usb_phy_info {
>
> struct sun4i_usb_phy_plat {
> void __iomem *pmu;
> - int gpio_vbus;
> - int gpio_vbus_det;
> - int gpio_id_det;
> + struct gpio_desc gpio_vbus;
> + struct gpio_desc gpio_vbus_det;
> + struct gpio_desc gpio_id_det;
> struct clk clocks;
> struct reset_ctl resets;
> int id;
> @@ -224,8 +224,8 @@ static int sun4i_usb_phy_power_on(struct phy *phy)
> initial_usb_scan_delay = 0;
> }
>
> - if (usb_phy->gpio_vbus >= 0)
> - gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
> + if (dm_gpio_is_valid(_phy->gpio_vbus))
> + dm_gpio_set_value(_phy->gpio_vbus, 1);
>
> return 0;
> }
> @@ -235,8 +235,8 @@ static int sun4i_usb_phy_power_off(struct phy *phy)
> struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
> struct sun4i_usb_phy_plat *usb_phy = >usb_phy[phy->id];
>
> - if (usb_phy->gpio_vbus >= 0)
> - gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
> + if (dm_gpio_is_valid(_phy->gpio_vbus))
> + dm_gpio_set_value(_phy->gpio_vbus, 0);
>
> return 0;
> }
> @@ -386,8 +386,8 @@ int sun4i_usb_phy_vbus_detect(struct phy *phy)
> struct sun4i_usb_phy_plat *usb_phy = >usb_phy[phy->id];
> int err = 1, retries = 3;
>
> - if (usb_phy->gpio_vbus_det >= 0) {
> - err = gpio_get_value(usb_phy->gpio_vbus_det);
> + if (dm_gpio_is_valid(_phy->gpio_vbus_det)) {
> + err = dm_gpio_get_value(_phy->gpio_vbus_det);
> /*
>* Vbus may have been provided by the board and just turned off
>* some milliseconds ago on reset. What we're measuring then is
> @@ -395,7 +395,7 @@ int sun4i_usb_phy_vbus_detect(struct phy *phy)
>*/
> while (err > 0 && retries--) {
> mdelay(100);
> - err = gpio_get_value(usb_phy->gpio_vbus_det);
> + err = dm_gpio_get_value(_phy->gpio_vbus_det);
> }
> } else if (data->vbus_power_supply) {
> err = regulator_get_enable(data->vbus_power_supply);
> @@ -409,10 +409,10 @@ int sun4i_usb_phy_id_detect(struct phy *phy)
> struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
> struct sun4i_usb_phy_plat *usb_phy = >usb_phy[phy->id];
>
> - if (usb_phy->gpio_id_det < 0)
> - return usb_phy->gpio_id_det;
> + if (!dm_gpio_is_valid(_phy->gpio_id_det))
> + return -1;
>
> - return gpio_get_value(usb_phy->gpio_id_det);
> + return dm_gpio_get_value(_phy->gpio_id_det);
> }
>
> void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
> @@ -454,35 +454,42 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
> if (data->cfg->missing_phys & BIT(i))
> continue;
>
> - phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
> - if (phy->gpio_vbus >= 0) {
> - ret = gpio_request(phy->gpio_vbus, "usb_vbus");
> + ret = dm_gpio_lookup_name(info->gpio_vbus, >gpio_vbus);
> + if (ret == 0) {
> + ret = dm_gpio_request(>gpio_vbus, "usb_vbus");
> if (ret)
> return ret;
> - ret = gpio_direction_output(phy->gpio_vbus, 0);
> + ret = dm_gpio_set_dir_flags(>gpio_vbus,
> + GPIOD_IS_OUT);
> + if (ret)
> + return ret;
> + ret = dm_gpio_set_value(>gpio_vbus, 0);
> if (ret)
> return ret;
> }
>
> -
Re: [PATCH v2] sunxi: fix initial environment loading without MMC
On Fri, 24 Jun 2022 17:12:09 +0100
Andre Przywara wrote:
> From: Samuel Holland
>
> Commit e42dad4168fe ("sunxi: use boot source for determining environment
> location") changed our implementation of env_get_location() and enabled
> it for every board, even those without MMC support (like the C.H.I.P.
> boards). However the default fallback location of ENVL_FAT requires MMC
> support compiled in, so the board hangs when trying to initially load
> the environment.
>
> Change the algorithm to only return configured environment locations,
> and improve the fallback algorithm on the way.
>
> The env_init() routine calling this function here does not behave well
> if the return value is ENVL_UNKNOWN on the very first call: it will make
> U-Boot proper silently hang very early.
> Work around this issue by making sure we return some configured (dummy)
> environment location when prio is 0. This for instance happens when
> booting via FEL.
>
> This fixes U-Boot loading on the C.H.I.P. boards.
>
> Fixes: e42dad4168fe ("sunxi: use boot source for determining environment
> location")
> Reported-by: Chris Morgan
> Signed-off-by: Samuel Holland
> [Andre: fix FEL boot case by not returning ENVL_UNKNOWN when prio==0]
> Signed-off-by: Andre Przywara
Applied to sunxi/master, for v2022.07.
Cheers,
Andre
> ---
> Hi Samuel,
>
> I cheekily added your Signed-off-by:, as I made this your patch (since
> you came up with it in that email reply some weeks ago). I hope that's
> fine.
> I tested this briefly on a Pine64-LTS, booting from FEL, SD card, eMMC
> and SPI. I also simulated a CHIP board, by just defining ENV_IS_NOWHERE,
> then booting, as this was the case that broke.
> If no one complains, I would like to push this ASAP, to make it into
> the 2022.07 release still.
>
> Cheers,
> Andre
>
> board/sunxi/board.c | 49 +++--
> 1 file changed, 29 insertions(+), 20 deletions(-)
>
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 806e3bcb69..21a2407e06 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -128,26 +128,37 @@ void i2c_init_board(void)
> * Try to use the environment from the boot source first.
> * For MMC, this means a FAT partition on the boot device (SD or eMMC).
> * If the raw MMC environment is also enabled, this is tried next.
> + * When booting from NAND we try UBI first, then NAND directly.
> * SPI flash falls back to FAT (on SD card).
> */
> enum env_location env_get_location(enum env_operation op, int prio)
> {
> - enum env_location boot_loc = ENVL_FAT;
> + if (prio > 1)
> + return ENVL_UNKNOWN;
>
> - gd->env_load_prio = prio;
> + /* NOWHERE is exclusive, no other option can be defined. */
> + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
> + return ENVL_NOWHERE;
>
> switch (sunxi_get_boot_device()) {
> case BOOT_DEVICE_MMC1:
> case BOOT_DEVICE_MMC2:
> - boot_loc = ENVL_FAT;
> + if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
> + return ENVL_FAT;
> + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
> + return ENVL_MMC;
> break;
> case BOOT_DEVICE_NAND:
> + if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
> + return ENVL_UBI;
> if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
> - boot_loc = ENVL_NAND;
> + return ENVL_NAND;
> break;
> case BOOT_DEVICE_SPI:
> - if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
> - boot_loc = ENVL_SPI_FLASH;
> + if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
> + return ENVL_SPI_FLASH;
> + if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
> + return ENVL_FAT;
> break;
> case BOOT_DEVICE_BOARD:
> break;
> @@ -155,21 +166,19 @@ enum env_location env_get_location(enum env_operation
> op, int prio)
> break;
> }
>
> - /* Always try to access the environment on the boot device first. */
> - if (prio == 0)
> - return boot_loc;
> -
> - if (prio == 1) {
> - switch (boot_loc) {
> - case ENVL_SPI_FLASH:
> + /*
> + * If we come here for the first time, we *must* return a valid
> + * environment location other than ENVL_UNKNOWN, or the setup sequence
> + * in board_f() will silently hang. This is arguably a bug in
> + * env_init(), but for now pick one environment for which we know for
> + * sure to have a driver for. For all defconfigs this is either FAT
> + * or UBI, or NOWHERE, which is already handled above.
> + */
> + if (prio == 0) {
> + if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
> return ENVL_FAT;
> - case ENVL_FAT:
> - if
Re: [PATCH v2] sunxi: psci: Fix sunxi_power_switch on sun8i-r40 platform
On Sat, 14 May 2022 11:52:01 +0800
Chen-Yu Tsai wrote:
Hi,
> On Sat, May 14, 2022 at 11:19 AM wrote:
> >
> > From: qianfan Zhao
> >
> > linux system will die if we offline one of the cpu on R40 based board:
> > eg: echo 0 > /sys/devices/system/cpu/cpu3/online
> >
> > Fixed sunxi_power_switch based on allwinner lichee 3.10 kernel driver.
> >
> > Signed-off-by: qianfan Zhao
>
> Please add a Fixes tag.
>
> > ---
> > v2 changes: Fix the commit message, the source code doesn't change.
> >
> > arch/arm/cpu/armv7/sunxi/psci.c | 24 +++-
> > 1 file changed, 19 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv7/sunxi/psci.c
> > b/arch/arm/cpu/armv7/sunxi/psci.c
> > index 1ac50f558a..63186a9388 100644
> > --- a/arch/arm/cpu/armv7/sunxi/psci.c
> > +++ b/arch/arm/cpu/armv7/sunxi/psci.c
> > @@ -79,8 +79,7 @@ static void __secure __mdelay(u32 ms)
> > static void __secure clamp_release(u32 __maybe_unused *clamp)
> > {
> > #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
> > - defined(CONFIG_MACH_SUN8I_H3) || \
> > - defined(CONFIG_MACH_SUN8I_R40)
> > + defined(CONFIG_MACH_SUN8I_H3)
> > u32 tmp = 0x1ff;
> > do {
> > tmp >>= 1;
> > @@ -88,15 +87,30 @@ static void __secure clamp_release(u32 __maybe_unused
> > *clamp)
> > } while (tmp);
> >
> > __mdelay(10);
> > +#elif defined(CONFIG_MACH_SUN8I_R40)
> > + u8 i, tmp = 0xfe;
> > +
> > + for (i = 0; i < 5; i++) { /* 0xfe, 0xf8, 0xe0, 0x80, 0x00 */
> > + writel(tmp, clamp);
> > + tmp <<= 2;
> > + }
> > +
> > + while (0x00 != readl(clamp)) {
> > + ;
> > + }
> > #endif
> > }
> >
> > static void __secure clamp_set(u32 __maybe_unused *clamp)
> > {
> > #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
> > - defined(CONFIG_MACH_SUN8I_H3) || \
> > - defined(CONFIG_MACH_SUN8I_R40)
> > + defined(CONFIG_MACH_SUN8I_H3)
> > writel(0xff, clamp);
> > +#elif defined(CONFIG_MACH_SUN8I_R40)
> > + writel(0xff, clamp);
> > + while (0xff != readl(clamp)) {
> > + ;
> > + }
> > #endif
> > }
> >
> > @@ -153,7 +167,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool
> > on)
> >
> > sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
> >(void *)cpucfg + SUN8I_R40_PWROFF,
> > - on, 0);
> > + on, cpu);
>
> I think this is the only change that is needed. Looking again at the
> R40 user manual, the original code turned off core 0 regardless of
> which core was being brought down.
Reduced the patch to this one change, adjusted and extended the commit
message, and applied to sunxi/master, for v2022.07.
Thanks,
Andre
>
> Could you give that a try? The power clamp stuff shouldn't change
> much, as the end result is the same. The readback might make a
> difference, but if it does, it should be applied to all SoCs.
>
>
> Regards
> ChenYu
>
> > }
> > #else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
> > static void __secure sunxi_cpu_set_power(int cpu, bool on)
> > --
> > 2.25.1
> >
Re: [PATCH 4/7] clk: sunxi: Use a single driver for all variants
On Mon, 9 May 2022 00:29:34 -0500
Samuel Holland wrote:
Hi,
> Now that all of the variants use the same bind/probe functions and ops,
> there is no need to have a separate driver for each variant. Since most
> SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit
> of firmware size and RAM.
>
> Signed-off-by: Samuel Holland
Nice one, I like that cleanup. Again I added support for the F1C100s.
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
>
> drivers/clk/sunxi/clk_a10.c | 20 +-
> drivers/clk/sunxi/clk_a10s.c | 20 +-
> drivers/clk/sunxi/clk_a23.c | 20 +-
> drivers/clk/sunxi/clk_a31.c | 18 +-
> drivers/clk/sunxi/clk_a31_r.c | 22 +--
> drivers/clk/sunxi/clk_a64.c | 18 +-
> drivers/clk/sunxi/clk_a80.c | 22 +--
> drivers/clk/sunxi/clk_a83t.c | 18 +-
> drivers/clk/sunxi/clk_h3.c| 20 +-
> drivers/clk/sunxi/clk_h6.c| 18 +-
> drivers/clk/sunxi/clk_h616.c | 18 +-
> drivers/clk/sunxi/clk_h6_r.c | 20 +-
> drivers/clk/sunxi/clk_r40.c | 18 +-
> drivers/clk/sunxi/clk_sunxi.c | 118 +-
> drivers/clk/sunxi/clk_v3s.c | 20 +-
> include/clk/sunxi.h | 12
> 16 files changed, 131 insertions(+), 271 deletions(-)
>
> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
> index e5374f6cf0..4752a1167b 100644
> --- a/drivers/clk/sunxi/clk_a10.c
> +++ b/drivers/clk/sunxi/clk_a10.c
> @@ -62,27 +62,9 @@ static struct ccu_reset a10_resets[] = {
> [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
> };
>
> -static const struct ccu_desc a10_ccu_desc = {
> +const struct ccu_desc a10_ccu_desc = {
> .gates = a10_gates,
> .resets = a10_resets,
> .num_gates = ARRAY_SIZE(a10_gates),
> .num_resets = ARRAY_SIZE(a10_resets),
> };
> -
> -static const struct udevice_id a10_ccu_ids[] = {
> - { .compatible = "allwinner,sun4i-a10-ccu",
> - .data = (ulong)_ccu_desc },
> - { .compatible = "allwinner,sun7i-a20-ccu",
> - .data = (ulong)_ccu_desc },
> - { }
> -};
> -
> -U_BOOT_DRIVER(clk_sun4i_a10) = {
> - .name = "sun4i_a10_ccu",
> - .id = UCLASS_CLK,
> - .of_match = a10_ccu_ids,
> - .priv_auto = sizeof(struct ccu_priv),
> - .ops= _clk_ops,
> - .probe = sunxi_clk_probe,
> - .bind = sunxi_clk_bind,
> -};
> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
> index 07d518c121..9619c5f935 100644
> --- a/drivers/clk/sunxi/clk_a10s.c
> +++ b/drivers/clk/sunxi/clk_a10s.c
> @@ -47,27 +47,9 @@ static struct ccu_reset a10s_resets[] = {
> [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
> };
>
> -static const struct ccu_desc a10s_ccu_desc = {
> +const struct ccu_desc a10s_ccu_desc = {
> .gates = a10s_gates,
> .resets = a10s_resets,
> .num_gates = ARRAY_SIZE(a10s_gates),
> .num_resets = ARRAY_SIZE(a10s_resets),
> };
> -
> -static const struct udevice_id a10s_ccu_ids[] = {
> - { .compatible = "allwinner,sun5i-a10s-ccu",
> - .data = (ulong)_ccu_desc },
> - { .compatible = "allwinner,sun5i-a13-ccu",
> - .data = (ulong)_ccu_desc },
> - { }
> -};
> -
> -U_BOOT_DRIVER(clk_sun5i_a10s) = {
> - .name = "sun5i_a10s_ccu",
> - .id = UCLASS_CLK,
> - .of_match = a10s_ccu_ids,
> - .priv_auto = sizeof(struct ccu_priv),
> - .ops= _clk_ops,
> - .probe = sunxi_clk_probe,
> - .bind = sunxi_clk_bind,
> -};
> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
> index 9c0e5db07c..5e19c11c23 100644
> --- a/drivers/clk/sunxi/clk_a23.c
> +++ b/drivers/clk/sunxi/clk_a23.c
> @@ -66,27 +66,9 @@ static struct ccu_reset a23_resets[] = {
> [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
> };
>
> -static const struct ccu_desc a23_ccu_desc = {
> +const struct ccu_desc a23_ccu_desc = {
> .gates = a23_gates,
> .resets = a23_resets,
> .num_gates = ARRAY_SIZE(a23_gates),
> .num_resets = ARRAY_SIZE(a23_resets),
> };
> -
> -static const struct udevice_id a23_clk_ids[] = {
> - { .compatible = "allwinner,sun8i-a23-ccu",
> - .data = (ulong)_ccu_desc },
> - { .compatible = "allwinner,sun8i-a33-ccu",
> - .data = (ulong)_ccu_desc },
> - { }
> -};
> -
> -U_BOOT_DRIVER(clk_sun8i_a23) = {
> - .name = "sun8i_a23_ccu",
> - .id = UCLASS_CLK,
> - .of_match = a23_clk_ids,
> - .priv_auto = sizeof(struct ccu_priv),
> - .ops= _clk_ops,
> - .probe = sunxi_clk_probe,
> - .bind = sunxi_clk_bind,
> -};
> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
> index 3d0767e290..0f58ea 100644
> --- a/drivers/clk/sunxi/clk_a31.c
> +++ b/drivers/clk/sunxi/clk_a31.c
> @@ -87,25 +87,9 @@ static struct ccu_reset a31_resets[] =
Re: [PATCH 1/2] clk: sunxi: Add additional RTC compatible strings
On Sat, 30 Apr 2022 22:38:36 -0500
Samuel Holland wrote:
> Compatible strings for some new RTC hardware variants were added to
> the binding. Add them to the driver in preparation for supporting
> those new SoCs.
>
> Signed-off-by: Samuel Holland
Applied to sunxi/master, for v2022.07.
Cheers,
Andre
> ---
>
> drivers/clk/sunxi/clk_sun6i_rtc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_sun6i_rtc.c
> b/drivers/clk/sunxi/clk_sun6i_rtc.c
> index 0c280d221b..697b187a82 100644
> --- a/drivers/clk/sunxi/clk_sun6i_rtc.c
> +++ b/drivers/clk/sunxi/clk_sun6i_rtc.c
> @@ -24,6 +24,8 @@ static const struct udevice_id sun6i_rtc_ids[] = {
> { .compatible = "allwinner,sun8i-v3-rtc" },
> { .compatible = "allwinner,sun50i-h5-rtc" },
> { .compatible = "allwinner,sun50i-h6-rtc" },
> + { .compatible = "allwinner,sun50i-h616-rtc" },
> + { .compatible = "allwinner,sun50i-r329-rtc" },
> { }
> };
>
Re: [PATCH 1/7] clk: sunxi: Store the array sizes in the CCU descriptor
On Mon, 9 May 2022 00:29:31 -0500
Samuel Holland wrote:
> The reset array size is currently used for bounds checking in the reset
> driver. The same bounds check should really be done in the clock driver.
>
> Currently, the array size is provided to the reset driver separately
> from the CCU descriptor, which is a bit strange. Let's do this the usual
> way, with the array sizes next to the arrays themselves.
Checked for typos, all fine. Added the F1C100s on the way.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Andre Przywara
Thanks,
Andre
> ---
>
> drivers/clk/sunxi/clk_a10.c | 2 ++
> drivers/clk/sunxi/clk_a10s.c | 2 ++
> drivers/clk/sunxi/clk_a23.c | 2 ++
> drivers/clk/sunxi/clk_a31.c | 2 ++
> drivers/clk/sunxi/clk_a31_r.c | 2 ++
> drivers/clk/sunxi/clk_a64.c | 2 ++
> drivers/clk/sunxi/clk_a80.c | 4
> drivers/clk/sunxi/clk_a83t.c | 2 ++
> drivers/clk/sunxi/clk_h3.c| 2 ++
> drivers/clk/sunxi/clk_h6.c| 2 ++
> drivers/clk/sunxi/clk_h616.c | 2 ++
> drivers/clk/sunxi/clk_h6_r.c | 2 ++
> drivers/clk/sunxi/clk_r40.c | 2 ++
> drivers/clk/sunxi/clk_v3s.c | 2 ++
> include/clk/sunxi.h | 2 ++
> 15 files changed, 32 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
> index 90b929d3d3..6b58cffc8a 100644
> --- a/drivers/clk/sunxi/clk_a10.c
> +++ b/drivers/clk/sunxi/clk_a10.c
> @@ -65,6 +65,8 @@ static struct ccu_reset a10_resets[] = {
> static const struct ccu_desc a10_ccu_desc = {
> .gates = a10_gates,
> .resets = a10_resets,
> + .num_gates = ARRAY_SIZE(a10_gates),
> + .num_resets = ARRAY_SIZE(a10_resets),
> };
>
> static int a10_clk_bind(struct udevice *dev)
> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
> index addf4f4d5c..81b146ce1e 100644
> --- a/drivers/clk/sunxi/clk_a10s.c
> +++ b/drivers/clk/sunxi/clk_a10s.c
> @@ -50,6 +50,8 @@ static struct ccu_reset a10s_resets[] = {
> static const struct ccu_desc a10s_ccu_desc = {
> .gates = a10s_gates,
> .resets = a10s_resets,
> + .num_gates = ARRAY_SIZE(a10s_gates),
> + .num_resets = ARRAY_SIZE(a10s_resets),
> };
>
> static int a10s_clk_bind(struct udevice *dev)
> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
> index c45d2c3529..c7c78bc7d8 100644
> --- a/drivers/clk/sunxi/clk_a23.c
> +++ b/drivers/clk/sunxi/clk_a23.c
> @@ -69,6 +69,8 @@ static struct ccu_reset a23_resets[] = {
> static const struct ccu_desc a23_ccu_desc = {
> .gates = a23_gates,
> .resets = a23_resets,
> + .num_gates = ARRAY_SIZE(a23_gates),
> + .num_resets = ARRAY_SIZE(a23_resets),
> };
>
> static int a23_clk_bind(struct udevice *dev)
> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
> index 251fc3b705..c8c7f4ecf5 100644
> --- a/drivers/clk/sunxi/clk_a31.c
> +++ b/drivers/clk/sunxi/clk_a31.c
> @@ -90,6 +90,8 @@ static struct ccu_reset a31_resets[] = {
> static const struct ccu_desc a31_ccu_desc = {
> .gates = a31_gates,
> .resets = a31_resets,
> + .num_gates = ARRAY_SIZE(a31_gates),
> + .num_resets = ARRAY_SIZE(a31_resets),
> };
>
> static int a31_clk_bind(struct udevice *dev)
> diff --git a/drivers/clk/sunxi/clk_a31_r.c b/drivers/clk/sunxi/clk_a31_r.c
> index 1f08ea956f..7bf1c4578c 100644
> --- a/drivers/clk/sunxi/clk_a31_r.c
> +++ b/drivers/clk/sunxi/clk_a31_r.c
> @@ -31,6 +31,8 @@ static struct ccu_reset a31_r_resets[] = {
> static const struct ccu_desc a31_r_ccu_desc = {
> .gates = a31_r_gates,
> .resets = a31_r_resets,
> + .num_gates = ARRAY_SIZE(a31_r_gates),
> + .num_resets = ARRAY_SIZE(a31_r_resets),
> };
>
> static int a31_r_clk_bind(struct udevice *dev)
> diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
> index 1004a79503..6da861ddc1 100644
> --- a/drivers/clk/sunxi/clk_a64.c
> +++ b/drivers/clk/sunxi/clk_a64.c
> @@ -76,6 +76,8 @@ static const struct ccu_reset a64_resets[] = {
> static const struct ccu_desc a64_ccu_desc = {
> .gates = a64_gates,
> .resets = a64_resets,
> + .num_gates = ARRAY_SIZE(a64_gates),
> + .num_resets = ARRAY_SIZE(a64_resets),
> };
>
> static int a64_clk_bind(struct udevice *dev)
> diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
> index 8a0834d83a..7025d3cbe6 100644
> --- a/drivers/clk/sunxi/clk_a80.c
> +++ b/drivers/clk/sunxi/clk_a80.c
> @@ -75,11 +75,15 @@ static const struct ccu_reset a80_mmc_resets[] = {
> static const struct ccu_desc a80_ccu_desc = {
> .gates = a80_gates,
> .resets = a80_resets,
> + .num_gates = ARRAY_SIZE(a80_gates),
> + .num_resets = ARRAY_SIZE(a80_resets),
> };
>
> static const struct ccu_desc a80_mmc_clk_desc = {
> .gates = a80_mmc_gates,
> .resets = a80_mmc_resets,
> + .num_gates = ARRAY_SIZE(a80_mmc_gates),
> + .num_resets = ARRAY_SIZE(a80_mmc_resets),
> };
>
> static int a80_clk_bind(struct udevice *dev)
> diff --git
Re: [PATCH] gpio: sunxi: Fix build with CONFIG_SPL_SERIAL=n
On Tue, 10 May 2022 19:03:34 -0500
Samuel Holland wrote:
> This driver uses simple_strtol(), so it needs SPL_STRTO. Before commit
> 88ca8e26958b6 ("disk: Add an option for partitions in SPL"), SPL_STRTO
> was always selected indirectly. Now it is not, so select it here.
>
> Signed-off-by: Samuel Holland
Applied to sunxi/master, for v2022.07.
Thanks,
Andre
> ---
>
> drivers/gpio/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 89068c7800..b955543e97 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -347,6 +347,7 @@ config SANDBOX_GPIO_COUNT
> config SUNXI_GPIO
> bool "Allwinner GPIO driver"
> depends on ARCH_SUNXI
> + select SPL_STRTO if SPL
> help
> Support the GPIO device in Allwinner SoCs.
>
RE: [PATCH 4/5] ast2600: Configure u-boot-with-spl.bin target
Reply again to leave record on mailing list. > From: joel.s...@gmail.com On Behalf Of Joel Stanley > Sent: Friday, June 24, 2022 10:50 AM > > For the u-boot-with-spl.bin target to be useful for the AST2600, set the > maximum SPL size which also sets the padding length. > > The normal way of loading u-boot is as a FIT, so configure u-boot.img as the > SPL playload. > > With this the following simple steps can be used to build and boot a > system: > > make u-boot-with-spl.bin > truncate -s 64M u-boot-with-spl.bin > qemu-system-arm -nographic -M ast2600-evb \ > -drive file=u-boot-with-spl.bin,if=mtd,format=raw > > Signed-off-by: Joel Stanley > --- > include/configs/evb_ast2600.h | 3 +++ > configs/evb-ast2600_defconfig | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h > index 3c2155da46df..f5ac88447b52 100644 > --- a/include/configs/evb_ast2600.h > +++ b/include/configs/evb_ast2600.h > @@ -10,6 +10,9 @@ > > #define CONFIG_SYS_UBOOT_BASECONFIG_SYS_TEXT_BASE > > +/* The maximum size the AST2600 bootrom can load is 64KB */ > +#define CONFIG_SPL_MAX_SIZE 65536 Please define this to the Kconfig option CONFIG_SPL_SIZE_LIMIT to avoid inconsistent definitions on SPL image size limitation. Chiawei
RE: [PATCH 3/5] config/ast2600: Disable hash hardware accel
Reply again to leave record on mailing list. > From: joel.s...@gmail.com On Behalf Of Joel Stanley > Sent: Friday, June 24, 2022 10:50 AM > > The Qemu model or the u-boot driver is unable to correctly compute the > SHA256 hash used in a FIT. Disable it by default while that issue is worked > out > to enable boot testing in Qemu. > > Signed-off-by: Joel Stanley > --- > configs/evb-ast2600_defconfig | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig > index f3a6cb222020..160bccff48e2 100644 > --- a/configs/evb-ast2600_defconfig > +++ b/configs/evb-ast2600_defconfig > @@ -59,9 +59,6 @@ CONFIG_REGMAP=y > CONFIG_SPL_OF_TRANSLATE=y > CONFIG_CLK=y > CONFIG_SPL_CLK=y > -CONFIG_DM_HASH=y > -CONFIG_HASH_ASPEED=y > -CONFIG_ASPEED_ACRY=y Per our previous discussion, SPL code size still exists if all of AST2600 features are upstream-ed. Therefore, HW-assisted crypto drivers are needed. In addition, the current drivers works fine on real EVB to verify Hash + RSA signature (including the SHA256 in question). This issue described in commit message should be attributed to incomplete QEMU emulation. Therefore, fixing QEMU should be the right way to go instead of disabling these options for real HW. Chiawei > CONFIG_ASPEED_GPIO=y > CONFIG_DM_I2C=y > CONFIG_MISC=y > -- > 2.35.1
[PATCH v5 2/2] board: mntre: imx8mq: Add MNT Reform 2 board support
The MNT Reform 2 is a modular DIY laptop. In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM. Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.
Signed-off-by: Patrick Wildt
---
arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi | 11 +
arch/arm/mach-imx/imx8m/Kconfig |7 +
board/mntre/imx8mq_reform2/Kconfig| 15 +
board/mntre/imx8mq_reform2/MAINTAINERS|7 +
board/mntre/imx8mq_reform2/Makefile | 12 +
board/mntre/imx8mq_reform2/imx8mq_reform2.c | 213
board/mntre/imx8mq_reform2/lpddr4_timing.c| 1014 +
.../mntre/imx8mq_reform2/lpddr4_timing_ch2.h | 95 ++
board/mntre/imx8mq_reform2/spl.c | 260 +
configs/imx8mq_reform2_defconfig | 94 ++
include/configs/imx8mq_reform2.h | 86 ++
11 files changed, 1814 insertions(+)
create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
create mode 100644 board/mntre/imx8mq_reform2/Kconfig
create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
create mode 100644 board/mntre/imx8mq_reform2/Makefile
create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
create mode 100644 board/mntre/imx8mq_reform2/spl.c
create mode 100644 configs/imx8mq_reform2_defconfig
create mode 100644 include/configs/imx8mq_reform2.h
diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
new file mode 100644
index 00..7efd82214d
--- /dev/null
+++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+_uart1 {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index ef8518c06b..b1a8c30e80 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -50,6 +50,12 @@ config TARGET_IMX8MQ_PHANBELL
select IMX8MQ
select IMX8M_LPDDR4
+config TARGET_IMX8MQ_REFORM2
+ bool "imx8mq_reform2"
+ select BINMAN
+ select IMX8MQ
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Mini"
select BINMAN
@@ -284,6 +290,7 @@ source "board/google/imx8mq_phanbell/Kconfig"
source "board/kontron/pitx_imx8m/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
source "board/menlo/mx8menlo/Kconfig"
+source "board/mntre/imx8mq_reform2/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"
diff --git a/board/mntre/imx8mq_reform2/Kconfig
b/board/mntre/imx8mq_reform2/Kconfig
new file mode 100644
index 00..f9260cb7f5
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MQ_REFORM2
+
+config SYS_BOARD
+ default "imx8mq_reform2"
+
+config SYS_VENDOR
+ default "mntre"
+
+config SYS_CONFIG_NAME
+ default "imx8mq_reform2"
+
+config IMX_CONFIG
+ default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS
b/board/mntre/imx8mq_reform2/MAINTAINERS
new file mode 100644
index 00..946f287ecf
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/MAINTAINERS
@@ -0,0 +1,7 @@
+REFORM2 IMX8MQ BOARD
+M: Lukas F. Hartmann
+M: Patrick Wildt
+S: Maintained
+F: board/mntre/imx8mq_reform2/
+F: include/configs/imx8mq_reform2.h
+F: configs/imx8mq_reform2_defconfig
diff --git a/board/mntre/imx8mq_reform2/Makefile
b/board/mntre/imx8mq_reform2/Makefile
new file mode 100644
index 00..2efd56bb4a
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mq_reform2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c
b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
new file mode 100644
index 00..f7cb32dd98
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright (C) 2018, Boundary Devices
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static
[PATCH v5 1/2] arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3
---
arch/arm/dts/imx8mq-mnt-reform2.dts | 145 +-
arch/arm/dts/imx8mq-nitrogen-som.dtsi | 15 +--
2 files changed, 152 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts
b/arch/arm/dts/imx8mq-mnt-reform2.dts
index 4f2db6197b..8956a46788 100644
--- a/arch/arm/dts/imx8mq-mnt-reform2.dts
+++ b/arch/arm/dts/imx8mq-mnt-reform2.dts
@@ -12,6 +12,31 @@
/ {
model = "MNT Reform 2";
compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som",
"fsl,imx8mq";
+ chassis-type = "laptop";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <_backlight>;
+ pwms = < 0 1 0>;
+ power-supply = <_main_usb>;
+ enable-gpios = < 10 GPIO_ACTIVE_HIGH>;
+ brightness-levels = <0 32 64 128 160 200 255>;
+ default-brightness-level = <6>;
+ };
+
+ panel {
+ compatible = "innolux,n125hce-gn1", "simple-panel";
+ power-supply = <_main_3v3>;
+ backlight = <>;
+ no-hpd;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <_bridge_out>;
+ };
+ };
+ };
pcie1_refclk: clock-pcie1-refclk {
compatible = "fixed-clock";
@@ -41,6 +66,22 @@
vin-supply = <_main_5v>;
};
+ reg_main_1v8: regulator-main-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1V8";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ vin-supply = <_main_3v3>;
+ };
+
+ reg_main_1v2: regulator-main-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1V2";
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ vin-supply = <_main_5v>;
+ };
+
sound {
compatible = "fsl,imx-audio-wm8960";
audio-cpu = <>;
@@ -60,6 +101,13 @@
};
};
+ {
+ assigned-clocks = < IMX8MQ_CLK_DSI_PHY_REF>;
+ assigned-clock-parents = < IMX8MQ_SYS1_PLL_800M>;
+ assigned-clock-rates = <2500>;
+ status = "okay";
+};
+
{
status = "okay";
};
@@ -83,6 +131,67 @@
};
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c4>;
+ clock-frequency = <40>;
+ status = "okay";
+
+ edp_bridge: bridge@2c {
+ compatible = "ti,sn65dsi86";
+ pinctrl-names = "default";
+ pinctrl-0 = <_edp_bridge>;
+ reg = <0x2c>;
+ enable-gpios = < 20 GPIO_ACTIVE_HIGH>;
+ vccio-supply = <_main_1v8>;
+ vpll-supply = <_main_1v8>;
+ vcca-supply = <_main_1v2>;
+ vcc-supply = <_main_1v2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ edp_bridge_in: endpoint {
+ remote-endpoint = <_dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ edp_bridge_out: endpoint {
+ remote-endpoint = <_in>;
+ };
+ };
+ };
+ };
+};
+
+ {
+ assigned-clocks = < IMX8MQ_CLK_LCDIF_PIXEL>;
+ assigned-clock-parents = < IMX8MQ_SYS1_PLL_800M>;
+ /delete-property/assigned-clock-rates;
+ status = "okay";
+};
+
+_dsi {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <_bridge_in>;
+ };
+ };
+ };
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pcie1>;
@@ -95,6 +204,13 @@
status = "okay";
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pwm2>;
+ status = "okay";
+};
+
+
_1p8v {
vin-supply = <_main_5v>;
};
@@ -168,10 +284,29 @@
};
{
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3
+ >;
+ };
+
+ pinctrl_edp_bridge: edpbridgegrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO200x1
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL
[PATCH v5 0/2] Add MNT Reform 2 board support
The MNT Reform 2 is a modular DIY laptop. In its initial version it is based on the BoundaryDevices i.MX8MQ SoM. Some parts have been lifted from BoundaryDevices official U-Boot downstream project. This U-Boot patchset supports the serial console, the SD card and eMMC, Gigabit Ethernet and USB. Changes since v4: - Adjusted to Kconfig conversions. - Removed U-Boot-specific device tree changes. - Synced device tree to Linux v5.19-rc3. Changes since v3: - Adjusted to Binman changes in main branch. - Cleaned up environment variables akin to i.MX8MM. - Added vendor-prefix to device tree filename. - Provided ramdisk_addr_r. Changes since v2: - Switched to Binman. Changes since v1: - Synced DTS with files in Linux git repo. - Added support for USB host ports. Patrick Wildt (2): arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3 board: mntre: imx8mq: Add MNT Reform 2 board support arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi | 11 + arch/arm/dts/imx8mq-mnt-reform2.dts | 145 ++- arch/arm/dts/imx8mq-nitrogen-som.dtsi | 15 +- arch/arm/mach-imx/imx8m/Kconfig |7 + board/mntre/imx8mq_reform2/Kconfig| 15 + board/mntre/imx8mq_reform2/MAINTAINERS|7 + board/mntre/imx8mq_reform2/Makefile | 12 + board/mntre/imx8mq_reform2/imx8mq_reform2.c | 213 board/mntre/imx8mq_reform2/lpddr4_timing.c| 1014 + .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h | 95 ++ board/mntre/imx8mq_reform2/spl.c | 260 + configs/imx8mq_reform2_defconfig | 94 ++ include/configs/imx8mq_reform2.h | 86 ++ 13 files changed, 1966 insertions(+), 8 deletions(-) create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi create mode 100644 board/mntre/imx8mq_reform2/Kconfig create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS create mode 100644 board/mntre/imx8mq_reform2/Makefile create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h create mode 100644 board/mntre/imx8mq_reform2/spl.c create mode 100644 configs/imx8mq_reform2_defconfig create mode 100644 include/configs/imx8mq_reform2.h -- 2.36.1
Re: [PATCH 20/20] Convert CONFIG_SYS_BOOTM_LEN to Kconfig
On 26.06.22 00:44, Tom Rini wrote: On Sun, Jun 26, 2022 at 12:01:23AM +0200, Soeren Moch wrote: diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 892d7c60d283..f0ecfd049d65 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x100 For tbs2910 there is another value set here - not the old default, not the new one. Why? This looks like a carefully chosen value, but very likely it is not. Probably also this value is fine for this board, but for me it makes no sense to set a board specific value here. I don't follow you, sorry. Since tbs2910 isn't X86 or PPC or ARM64, it's using the current value instead. Before this patch include/configs/tbs2910.h includes include/configs/mx6_common.h which sets it to 0x100. OK, I missed that part in the long patch, my bad. As I wrote, all possible values are probably good for this board. I just would prefer to use some default value (as before), since there is no special requirement for this board in particular. To keep the old value in this conversion of course makes sense. Which means I probably could put a || ARCH_MX6 in the Kconfig entry and drop out another 84 files (3 MX6 platforms set 0x400 instead today). That would make it more obvious that the old default is used for these boards. But if you prefer the board specific defconfig setting, that of course is also a valid solution. To be clear, here (and unless I otherwise note, all of the other conversions I've been doing) the intention is the same values on every platform, before and after. Many times the patches end up small because I can do a few default A if B lines and cover the vast majority if platforms. Sadly sometimes we get cases like this where in hindsight, a bigger default, or a more consistent default for every architecture should have been used, but wasn't. We can clean it up after but it needs to be separate so that someone can bisect a problem back to when the value was changed, not when it was migrated, if there's a problem. I totally agree. For me it looked like the default was changed for tbs2910, but it was not. My mistake. In your v2 it is obvious that we use the same defaults, great. So this isn't a super platform dependent value, and should probably be something like 96MiB for 32bit ARM (I forget what the practical maximum image size is, I know I talked with rmk about it about a decade ago I think), I _think_ the maximum text size (or image size?) is 16MiB for arm, but I'm not totally sure about this. But this would match with the mx6/mx7 defaults. and some other similar sane maximum for other platforms. But, a follow up to do that. Yes, changes should be done in a separate patch. But I do not see any need from my side. And I'm happy that there is no board specific defconfig entry for tbs2910 in your v2. Thanks, Soeren
Re: [v4 00/12] Add ASPEED SPI controller driver
On 6/26/22 06:56, Chin-Ting Kuo wrote: Hi All, Are there any comments about this patch series?* Sorry, I haven't had time to take a look at the driver. I will try this week. Thanks, C. Thanks. Best Wishes, Chin-Ting -Original Message- From: Chin-Ting Kuo Sent: Tuesday, May 24, 2022 1:57 PM To: ChiaWei Wang ; lu...@denx.de; sean...@gmail.com; Ryan Chen ; BMC-SW ; ja...@amarulasolutions.com; vigne...@ti.com; c...@kaod.org; u-boot@lists.denx.de; p.ya...@ti.com Subject: [v4 00/12] Add ASPEED SPI controller driver This patch series aims to porting ASPEED FMC/SPI memory controller driver with spi-mem interface. spi-mem dirmap framework is also synchronized from Linux. These patches have been verified on both AST2600 and AST2500 EVBs. Changes in v2: - Separate defconfig files from the SPI driver patch. - Use "if (CONFIG_IS_ENABLED(SPI_DIRMAP))" to wrap spi_dirmap related functions. - Add Winbond w25q512jv flash ID. Changes in v3: - Get AHB bus clock frequency from the function parameter. - Fix a grammatical error in spi-mem.h. Changes in v4: - Fix bug when SPI_NOR_4B_OPCODES flag is set. Chin-Ting Kuo (12): clk: aspeed: Get HCLK frequency support pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support spi: aspeed: Add ASPEED SPI controller driver configs: aspeed: Enable SPI flash features MAINTAINERS: Add ASPEED SPI driver file arm: dts: aspeed: Update SPI flash node settings spi-mem: Add dirmap API from Linux mtd: spi-nor: Use spi-mem dirmap API spi: aspeed: SPI dirmap read support configs: aspeed: Enable CONFIG_SPI_DIRMAP mtd: spi-nor-ids: Add Winbond W25Q512JV ID spi: aspeed: Fix bug when SPI_NOR_4B_OPCODES flag is set MAINTAINERS | 7 + arch/arm/dts/ast2500-evb.dts | 33 + arch/arm/dts/ast2500.dtsi| 23 +- arch/arm/dts/ast2600-evb.dts | 8 - arch/arm/dts/ast2600.dtsi| 34 +- configs/evb-ast2500_defconfig| 14 + configs/evb-ast2600_defconfig| 14 + drivers/clk/aspeed/clk_ast2500.c | 23 + drivers/mtd/spi/sf_probe.c | 76 ++ drivers/mtd/spi/spi-nor-core.c | 55 +- drivers/mtd/spi/spi-nor-ids.c| 5 + drivers/pinctrl/aspeed/pinctrl_ast2500.c | 2 + drivers/spi/Kconfig | 18 + drivers/spi/Makefile | 1 + drivers/spi/spi-aspeed.c | 914 +++ drivers/spi/spi-mem.c| 268 +++ include/linux/mtd/spi-nor.h | 18 + include/spi-mem.h| 79 ++ 18 files changed, 1546 insertions(+), 46 deletions(-) create mode 100644 drivers/spi/spi-aspeed.c -- 2.25.1
[RESEND PATCH 4/4] configs: imx8mn_bsh_smm_s2: add mtdparts to bootargs
Passing the mtdparts environment variable to the Linux kernel is
required to properly mount the UBI rootfs.
Co-developed-by: Michael Trimarchi
Signed-off-by: Michael Trimarchi
Signed-off-by: Dario Binacchi
---
include/configs/imx8mn_bsh_smm_s2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/imx8mn_bsh_smm_s2.h
b/include/configs/imx8mn_bsh_smm_s2.h
index 1eff8c43701c..d09c2ab01610 100644
--- a/include/configs/imx8mn_bsh_smm_s2.h
+++ b/include/configs/imx8mn_bsh_smm_s2.h
@@ -18,6 +18,7 @@
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"nandargs=setenv bootargs " \
"${optargs} " \
+ "mtdparts=${mtdparts} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"nandroot=ubi0:root rw ubi.mtd=nandrootfs\0" \
--
2.32.0
[RESEND PATCH 3/4] configs: imx8mn_bsh_smm_s2: remove console from bootargs
The Linux kernel device tree already specifies the device to be used for
boot console output with a stdout-path property under /chosen.
Co-developed-by: Michael Trimarchi
Signed-off-by: Michael Trimarchi
Signed-off-by: Dario Binacchi
---
include/configs/imx8mn_bsh_smm_s2.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/imx8mn_bsh_smm_s2.h
b/include/configs/imx8mn_bsh_smm_s2.h
index 098f23b206d1..1eff8c43701c 100644
--- a/include/configs/imx8mn_bsh_smm_s2.h
+++ b/include/configs/imx8mn_bsh_smm_s2.h
@@ -16,7 +16,7 @@
#define NANDARGS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "nandargs=setenv bootargs console=${console} " \
+ "nandargs=setenv bootargs " \
"${optargs} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
--
2.32.0
[RESEND PATCH 2/4] configs: imx8mn_bsh_smm_s2: add UBI commands
imx8mn_bsh_smm_s2 uses ubifs rootfs, UBI commands are required to flash it. Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- configs/imx8mn_bsh_smm_s2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 08f52e50609b..f8c75a2b237e 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),1m(nanddtb),8m(nandtee),-(nandrootfs)" +CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- 2.32.0
[RESEND PATCH 1/4] configs: imx8mn_bsh_smm_s2: add NAND driver
It allows to boot from NAND. Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- configs/imx8mn_bsh_smm_s2_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 49f425300151..08f52e50609b 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -30,8 +30,10 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="> " @@ -65,6 +67,9 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXS=y CONFIG_NAND_MXS_DT=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0xD8000 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x4058000 CONFIG_PHYLIB=y CONFIG_PHY_NXP_TJA11XX=y CONFIG_DM_ETH=y -- 2.32.0
[RESEND PATCH 0/4] imx8mn_bsh_smm_s2: fix NAND booting
The series contains all the patches required by the BSH smm s2 board for booting from NAND and properly mounting the UBI rootfs. Dario Binacchi (4): configs: imx8mn_bsh_smm_s2: add NAND driver configs: imx8mn_bsh_smm_s2: add UBI commands configs: imx8mn_bsh_smm_s2: remove console from bootargs configs: imx8mn_bsh_smm_s2: add mtdparts to bootargs configs/imx8mn_bsh_smm_s2_defconfig | 6 ++ include/configs/imx8mn_bsh_smm_s2.h | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) -- 2.32.0
[PATCH v3 2/2] ARM: imx: imx8mn-evk-common-u-boot.dtsi: cleanup
This cleanup implements several review comments and its target is to
prepare for a common imx8mn-common-u-boot.dtsi for all imx8mn boards.
It includes changes in node names to use only dashes instead of
underscores, improve the odd bloob-ext naming, use the atf-bl31 type and
the use of of-list for multiple DTB support.
Signed-off-by: Heiko Thiery
---
arch/arm/dts/imx8mn-evk-common-u-boot.dtsi | 48 ++
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/arch/arm/dts/imx8mn-evk-common-u-boot.dtsi
b/arch/arm/dts/imx8mn-evk-common-u-boot.dtsi
index d5ea2dcb4e..f512be095c 100644
--- a/arch/arm/dts/imx8mn-evk-common-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-evk-common-u-boot.dtsi
@@ -153,44 +153,52 @@
};
#ifdef CONFIG_IMX8M_DDR4
- blob_1: blob-ext@1 {
+ 1d-imem {
filename = "ddr4_imem_1d_201810.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_2: blob-ext@2 {
+ 1d-dmem {
filename = "ddr4_dmem_1d_201810.bin";
size = <0x4000>;
+ type = "blob-ext";
};
- blob_3: blob-ext@3 {
+ 2d-imem {
filename = "ddr4_imem_2d_201810.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_4: blob-ext@4 {
+ 2d-dmem {
filename = "ddr4_dmem_2d_201810.bin";
size = <0x4000>;
+ type = "blob-ext";
};
#elif CONFIG_IMX8M_LPDDR4
- blob_1: blob-ext@1 {
+ 1d-imem {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_2: blob-ext@2 {
+ 1d-dmem {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
+ type = "blob-ext";
};
- blob_3: blob-ext@3 {
+ 2d-imem {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_4: blob-ext@4 {
+ 2d-dmem {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
+ type = "blob-ext";
};
#else
#error "no valid ddr config selected"
@@ -216,6 +224,7 @@
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
+ fit,fdt-list = "of-list";
fit,external-offset = ;
images {
@@ -226,8 +235,9 @@
compression = "none";
load = ;
- uboot_blob: blob-ext {
+ uboot-blob {
filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
};
};
@@ -239,30 +249,32 @@
load = <0x96>;
entry = <0x96>;
- atf_blob: blob-ext {
+ atf-blob {
filename = "bl31.bin";
+ type = "atf-bl31";
};
};
- fdt {
+ @fdt-SEQ {
description = "NAME";
type = "flat_dt";
compression = "none";
- uboot_fdt_blob: blob-ext {
+ uboot-fdt-blob {
filename = "u-boot.dtb";
+ type = "blob-ext";
};
};
};
configurations {
- default = "conf";
+ default = "@config-DEFAULT-SEQ";
- conf {
+ binman_configuration: @config-SEQ {
description = "NAME";
firmware = "uboot";
[PATCH v3 1/2] ARM: imx: imx8mn-evk: use one common u-boot.dtsi for the evk boards
To have only one place to describe the common parts for all imx8mn evk
boards move this parts to imx8mn-evk-common-u-boot.dtsi.
To support the different DDR firmwares this nodes are included dependent
on the used DDR config option.
Signed-off-by: Heiko Thiery
---
v3:
- change name to imx8mn-evk-common-u-boot.dtsi
v2:
- sync with current master and fix merge conflict
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 260 +--
arch/arm/dts/imx8mn-evk-common-u-boot.dtsi | 286 +
arch/arm/dts/imx8mn-evk-u-boot.dtsi| 106 +---
3 files changed, 288 insertions(+), 364 deletions(-)
create mode 100644 arch/arm/dts/imx8mn-evk-common-u-boot.dtsi
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 4d0ecb07d4..a31e090391 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -3,262 +3,4 @@
* Copyright 2019, 2021 NXP
*/
-/ {
- binman: binman {
- multiple-images;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <>;
- u-boot,dm-spl;
- };
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-};
-
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
-_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
- {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
-_reg_usdhc2_vmmc {
- u-boot,dm-spl;
-};
-
-_usdhc2_vmmc {
- u-boot,off-on-delay-us = <2>;
-};
-
-_uart2 {
- u-boot,dm-spl;
-};
-
-_usdhc2_gpio {
- u-boot,dm-spl;
-};
-
-_usdhc2 {
- u-boot,dm-spl;
-};
-
-_usdhc3 {
- u-boot,dm-spl;
-};
-
-_wdog {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
-_jr0 {
- u-boot,dm-spl;
-};
-
-_jr1 {
- u-boot,dm-spl;
-};
-
-_jr2 {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
- u-boot,dm-spl;
- sd-uhs-sdr104;
- sd-uhs-ddr50;
-};
-
- {
- u-boot,dm-spl;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
-};
-
- {
- u-boot,dm-spl;
-};
-
- {
-u-boot-spl-ddr {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
-
- u-boot-spl {
- align-end = <4>;
- };
-
- blob_1: blob-ext@1 {
- filename = "ddr4_imem_1d_201810.bin";
- size = <0x8000>;
- };
-
- blob_2: blob-ext@2 {
- filename = "ddr4_dmem_1d_201810.bin";
- size = <0x4000>;
- };
-
- blob_3: blob-ext@3 {
- filename = "ddr4_imem_2d_201810.bin";
- size = <0x8000>;
- };
-
- blob_4: blob-ext@4 {
- filename = "ddr4_dmem_2d_201810.bin";
- size = <0x4000>;
- };
- };
-
-
- spl {
- filename = "spl.bin";
-
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x912000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- #address-cells = <1>;
- fit,external-offset = ;
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = ;
-
- uboot_blob: blob-ext {
- filename = "u-boot-nodtb.bin";
- };
- };
-
- atf {
- description = "ARM Trusted Firmware";
-
Re: [PATCH v2 2/2] ARM: imx: imx8mn-evk: use one common u-boot.dtsi for the evk boards
Hi Alper. Am Mi., 22. Juni 2022 um 20:18 Uhr schrieb Alper Nebi Yasak : > > On 09/06/2022 23:49, Heiko Thiery wrote: > > To have only one place to describe the binman images us the > > imx8mn-u-boot.dtsi. To have support for different DDR firmwares this > > nodes are included dependent on the used DDR config option. > > > > Signed-off-by: Heiko Thiery > > Reviewed-by: Fabio Estevam > > --- > > v2: sync with current master and fix merge conflict > > > > arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 125 +- > > arch/arm/dts/imx8mn-evk-u-boot.dtsi | 120 + > > arch/arm/dts/imx8mn-u-boot.dtsi | 156 +++ > > I see most of this is moving existing definitions, but I'm adding > comments in a general sense, partially for future reference. I have implemented your comments to prepare the dtb files for uniform use and will send an updated version. [SNIP] Thanks -- Heiko
Re: [PATCH v2 1/2] ARM: imx: imx8mn-evk: generate a single bootable flash.bin
Hi Alper
Am Mi., 22. Juni 2022 um 20:18 Uhr schrieb Alper Nebi Yasak
:
>
> On 09/06/2022 23:49, Heiko Thiery wrote:
> > To have a flash.bin file that also contains the U-Boot and TF-A/ATF
> > create this like already done for other imx8 boards.
> >
> > Signed-off-by: Heiko Thiery
> > Reviewed-by: Fabio Estevam
> > Reviewed-by: Peng Fan
> > ---
> > v2: sync with current master and fix merge conflict
> >
> > arch/arm/dts/imx8mn-evk-u-boot.dtsi | 19 ++-
> > 1 file changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> > b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> > index 3db46d4cbc..d1427941eb 100644
> > --- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> > +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> > @@ -58,7 +58,9 @@
> > };
> >
> >
> > - flash {
> > + spl {
> > + filename = "spl.bin";
> > +
> > mkimage {
> > args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
> > 0x912000";
> >
>
> This change got applied in the meantime via another patch [1].
ok
>
> [1] imx8mn_evk: Add the missing spl.bin entry
> https://lore.kernel.org/u-boot/20220503190304.413968-1-feste...@gmail.com/
>
> > @@ -125,4 +127,19 @@
> > };
> > };
> > };
> > +
> > + imx-boot {
> > + filename = "flash.bin";
> > + pad-byte = <0x00>;
> > +
> > + spl: blob-ext@1 {
> > + offset = <0x0>;
> > + filename = "spl.bin";
> > + };
> > +
> > + uboot: blob-ext@2 {
> > + offset = <0x58000>;
> > + filename = "u-boot.itb";
> > + };
> > + };
> > };
>
> This is already inherited from an #included dtsi, so not strictly
> necessary. I think it would be clearer to include this here as well, but
> since you're removing it in the next patch anyway you can drop this
> patch entirely.
You're right. This is not required. Therefore I set the state to
rejected in patchwork.
Thanks
Heiko
