Re: [PATCH v3] ddr: marvell: a38x: Add support for DDR4 from Marvell mv-ddr-marvell repository
On Thursday 26 January 2023 20:58:10 Tony Dinh wrote: > Hi Pali, > > On Thu, Jan 26, 2023 at 1:26 AM Stefan Roese wrote: > > > > On 1/19/23 04:03, Tony Dinh wrote: > > > This syncs drivers/ddr/marvell/a38x/ with the master branch of repository > > > https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git > > > > > > up to the commit "mv_ddr: a3700: Use the right size for memset to not > > > overflow" > > > d5acc10c287e40cc2feeb28710b92e45c93c702c > > > > > > This patch was created by following steps: > > > > > > 1. Replace all a38x files in U-Boot tree by files from upstream > > > github > > > Marvell mv-ddr-marvell repository. > > > > > > 2. Run following command to omit portions not relevant for a38x, > > > ddr3, and ddr4: > > > > > > files=drivers/ddr/marvell/a38x/* > > > unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \ > > > -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT > > > -UCONFIG_PHY_STATIC \ > > > -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \ > > > -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X > > > -UCONFIG_ARMADA_39X \ > > > -UCONFIG_64BIT $files > > > > > > 3. Manually change license to SPDX-License-Identifier > > > (upstream license in upstream github repository contains long > > > license > > > texts and U-Boot is using just SPDX-License-Identifier. > > > > > > After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell > > > github > > > repository and in U-Boot would be fully identical. So in future applying > > > above steps could be used to sync code again. > > > > > > The only change in this patch are: > > > 1. Some fixes with include files. > > > 2. Some function return and basic type defines changes in > > > mv_ddr_plat.c (to correct Marvell bug). > > > 3. Remove of dead code in newly copied files (as a result of the > > > filter script stripping out everything other than a38x, dd3, and > > > ddr4). > > > > > > Reference: > > > "ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell > > > repository" > > > > > > https://source.denx.de/u-boot/u-boot/-/commit/107c3391b95bcc2ba09a876da4fa0c31b6c1e460 > > > > > > Signed-off-by: Tony Dinh > > > > Applied to u-boot-marvell/master > > > > Thanks, > > Stefan > > Looking at the history of the work we've done to sync u-boot code back > to the mv-ddr-marvell repo, I think I should follow the same approach. > So I've pushed 2 commits to my GitHub repo. > https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/compare/master...mibodhi:mv-ddr-marvell:u-boot-ddr4-2023.01-fix Looks good! > Please review these 2 commits and create a pull request to Marvell, > like you did for others last year during DDR3 code sync. > > Thanks, > Tony
Re: [PATCH 1/3] Bump LMB_MAX_REGIONS default to 16
On Thu, 2023-01-26 at 13:28 -0500, Tom Rini wrote: > On Thu, Jan 19, 2023 at 09:38:17AM +0100, Sjoerd Simons wrote: > > > > As this is likely to impact more devices bump the default max > > regions to 16 so there is a bit more slack. > > > > Signed-off-by: Sjoerd Simons > > I prefer to use: > https://patchwork.ozlabs.org/project/uboot/patch/20230125230823.1567778-1-tr...@konsulko.com/ > in this case due to it being overall a smaller size increase. That's fine by me, achieves the same goal i was after for sure; The other 2 patches in this series are still required to fix the boot regressions i'm seeing ofcourse :) -- Sjoerd Simons Collabora Ltd.
Re: [PATCH] build_bug.h: Also define static_assert() when __CHECKER__ is defined
On 26/01/2023 19.17, Christophe Leroy wrote: > When doing a build with C=2, the following failure is encountered on > several files: > > CHECK arch/powerpc/cpu/mpc8xxx/fsl_lbc.c > arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: note: in included file (through > arch/powerpc/include/asm/global_data.h, include/init.h): > include/asm-generic/global_data.h:494:21: error: Expected ) in function > declarator > include/asm-generic/global_data.h:494:21: error: got ( > > And because of the error, the interesting part which are the > warnings don't appear. This is because static_assert() is defined > only when __CHECKER__ is not defined. > > Add a stub when __CHECKER__ is defined. With that fix, the expected > warnings are now seen: > So sparse has supported _Static_assert since basically forever, and in the linux version of build_bug.h, the static_assert definition is not inside #ifndef __CHECKER__. So I think a better fix is to synchronize build_bug.h with linux again, so that we actually also do those static_asserts with sparse (if nothing else then as a sanity check of sparse itself, it really should grok ICEs and barf at 'static_assert(sizeof(int) == 3)'). The __CHECKER__ guard around most of the file vanished from upstream in 527edbc18a70, just before the static_assert define was added in 6bab69c65013, and I didn't notice that discrepancy when porting that to U-Boot in ef0f4e834c66. Rasmus
Re: [PATCH] arm64: versal-net: Enable remaking ELF from bin
On 1/19/23 10:46, Michal Simek wrote: U-Boot is composing u-boot.bin from u-boot-nodtb.bin with appended dts/dt.dtb. It means U-Boot doesn't have DTB inside. When REMAKE_ELF is enabled make will also create u-boot.elf which is recreated from u-boot.bin. Below is build output for mini configuration how ELF is recreated. cat arch/arm/dts/versal-net-mini.dtb > dts/dt.dtb cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin cp dts/dt.dtb u-boot.dtb cp u-boot-dtb.bin u-boot.bin aarch64-linux-gnu-objcopy -I binary -B aarch64 -O elf64-littleaarch64 u-boot.bin u-boot-elf.o aarch64-linux-gnu-ld.bfd u-boot-elf.o -o u-boot.elf -EL -T u-boot-elf.lds --defsym="_start"=0xBBF0 -Ttext=0xBBF0 It is useful to have u-boot.elf present because Xilinx XSDB debugger can load ELF file and user doesn't need to specify loading address for u-boot.bin. Signed-off-by: Michal Simek --- configs/xilinx_versal_net_mini_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index 5bad1791964f..0ff5268bc342 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_MEMTEST_END=0x1000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF1 # CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set # CONFIG_AUTOBOOT is not set Applied. M
Re: [PATCH v2 1/3] microblaze: spl: wrap spl_start_uboot() in SPL_OS_BOOT ifdefs
On 1/25/23 17:41, Ovidiu Panait wrote:
Make spl_start_uboot() available only if CONFIG_SPL_OS_BOOT is enabled,
since it is only used for falcon mode.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
New patch.
arch/microblaze/cpu/spl.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index cea6d56f16..b9ff9c3702 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -41,17 +41,15 @@ void __noreturn jump_to_image_linux(struct spl_image_info
*spl_image)
image_entry(NULL, 0, (ulong)spl_image->arg);
}
-#endif /* CONFIG_SPL_OS_BOOT */
int spl_start_uboot(void)
{
-#ifdef CONFIG_SPL_OS_BOOT
if (boot_linux)
return 0;
-#endif
return 1;
}
+#endif /* CONFIG_SPL_OS_BOOT */
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
Applied all.
M
[PATCH] Revert "rockchip: Only call binman when TPL available"
This reverts commit f5315dd6290a588434e4f79bfd2886bb7df9210d.
[why]
TPL is not mandatory for not all Rockchip SoCs, some SoCs like
RK356x, and RK3588 still use mainline u-boot without TPL as
their ddr init programs are accessed via binaries provided by
Rockchip instead of ddr source code.
Marking TPL build makes it not able to build u-boot.itb on
RK356x targets so revert this so that it can build an SPL build
that would support all across Rockchip platforms.
Suggested-by: Quentin Schulz
Signed-off-by: Jagan Teki
---
arch/arm/dts/rockchip-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 234fc5df43..6d1fd7769e 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -11,7 +11,7 @@
};
};
-#ifdef CONFIG_TPL
+#ifdef CONFIG_SPL
&binman {
simple-bin {
filename = "u-boot-rockchip.bin";
--
2.25.1
[PATCH v7 3/3] ARM: tegra: include timer as default option
Enable TIMER as default option for all Tegra devices and enable TEGRA_TIMER for TEGRA_ARMV7_COMMON and TEGRA210. Additionally enable SPL_TIMER if build as SPL part and drop deprecated configs from common header. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Simon Glass --- arch/arm/Kconfig | 1 + arch/arm/mach-tegra/Kconfig| 3 +++ include/configs/tegra-common.h | 6 -- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c9a44ebc22..92cf509e97 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1284,6 +1284,7 @@ config ARCH_TEGRA select GPIO_EXTRA_HEADER imply DISTRO_DEFAULTS imply FAT_WRITE + imply SPL_TIMER if SPL config ARCH_VEXPRESS64 bool "Support ARMv8 Arm Ltd. VExpress based boards and models" diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 1b575cc0f4..b50eec5b8c 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -56,6 +56,7 @@ config TEGRA_COMMON select MISC select OF_CONTROL select SPI + select TIMER imply CMD_DM imply CRC32_VERIFY @@ -81,6 +82,7 @@ config TEGRA_ARMV7_COMMON select TEGRA_NO_BPMP select TEGRA_PINCTRL select TEGRA_PMC + select TEGRA_TIMER config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" @@ -134,6 +136,7 @@ config TEGRA210 select TEGRA_PINCTRL select TEGRA_PMC select TEGRA_PMC_SECURE + select TEGRA_TIMER config TEGRA186 bool "Tegra186 family" diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index bde7ffce00..c558679d04 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -15,12 +15,6 @@ #include /* get chip and board defs */ -/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ -#ifndef CONFIG_ARM64 -#define CFG_SYS_TIMER_RATE 100 -#define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE -#endif - /* Environment */ /* -- 2.37.2
[PATCH v7 1/3] ARM: tegra: remap clock_osc_freq for all Tegra family
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.
Tested-by: Andreas Westman Dorcsak # ASUS TF600T T30
Tested-by: Jonas Schwöbel # Surface RT T30
Tested-by: Robert Eckelmann # ASUS TF101 T20
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Thierry Reding # T30, T124, T210
Tested-by: Svyatoslav Ryhel # LG P895 T30
Signed-off-by: Svyatoslav Ryhel
Reviewed-by: Simon Glass
---
arch/arm/include/asm/arch-tegra/clock.h | 9 ++--
arch/arm/mach-tegra/clock.c | 17 --
arch/arm/mach-tegra/cpu.c | 70 -
arch/arm/mach-tegra/tegra114/clock.c| 13 ++---
arch/arm/mach-tegra/tegra124/clock.c| 13 ++---
arch/arm/mach-tegra/tegra20/clock.c | 4 +-
arch/arm/mach-tegra/tegra210/clock.c| 22 ++--
arch/arm/mach-tegra/tegra30/clock.c | 10 +---
drivers/usb/host/ehci-tegra.c | 46
9 files changed, 131 insertions(+), 73 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index 6586015fd2..1dd5d0742c 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -13,12 +13,13 @@ struct udevice;
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
/* All in MHz, so 13_0 is 13.0MHz */
- CLOCK_OSC_FREQ_13_0,
- CLOCK_OSC_FREQ_19_2,
- CLOCK_OSC_FREQ_12_0,
- CLOCK_OSC_FREQ_26_0,
+ CLOCK_OSC_FREQ_13_0 = 0,
+ CLOCK_OSC_FREQ_16_8,
+ CLOCK_OSC_FREQ_19_2 = 4,
CLOCK_OSC_FREQ_38_4,
+ CLOCK_OSC_FREQ_12_0 = 8,
CLOCK_OSC_FREQ_48_0,
+ CLOCK_OSC_FREQ_26_0 = 12,
CLOCK_OSC_FREQ_COUNT,
};
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 77c8ad978e..11bffc1701 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -28,16 +28,23 @@
static unsigned pll_rate[CLOCK_ID_COUNT];
/*
- * The oscillator frequency is fixed to one of four set values. Based on this
+ * The oscillator frequency is fixed to one of seven set values. Based on this
* the other clocks are set up appropriately.
*/
static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
1300,
+ 1680,
+ 0,
+ 0,
1920,
- 1200,
- 2600,
3840,
+ 0,
+ 0,
+ 1200,
4800,
+ 0,
+ 0,
+ 2600,
};
/* return 1 if a peripheral ID is in range */
@@ -766,6 +773,7 @@ void tegra30_set_up_pllp(void)
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
break;
@@ -776,10 +784,13 @@ void tegra30_set_up_pllp(void)
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
break;
+
case CLOCK_OSC_FREQ_19_2:
+ case CLOCK_OSC_FREQ_38_4:
default:
/*
* These are not supported. It is too early to print a
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index 65b15b79fe..59ca8aeaba 100644
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -55,11 +55,18 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
*/
{
{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
- { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz
(N/A) */
- { .n =0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz
(N/A) */
},
/*
[PATCH v7 2/3] drivers: timer: add driver for ARMv7 based Tegra devices and T210
Add timer support for T20/T30/T114/T124 and T210 based devices.
Driver is based on DM, has device tree support and can be
used on SPL and early boot stage.
Arm64 Tegra (apart T210) according to comment in tegra-common.h use
architected timer.
Tested-by: Andreas Westman Dorcsak # ASUS TF600T T30
Tested-by: Jonas Schwöbel # Surface RT T30
Tested-by: Robert Eckelmann # ASUS TF101 T20
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Svyatoslav Ryhel # LG P895 T30
Co-developed-by: Jonas Schwöbel
Signed-off-by: Jonas Schwöbel
Signed-off-by: Svyatoslav Ryhel
Reviewed-by: Simon Glass
---
drivers/timer/Kconfig | 8 +++
drivers/timer/Makefile | 1 +
drivers/timer/tegra-timer.c | 130
3 files changed, 139 insertions(+)
create mode 100644 drivers/timer/tegra-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 6d6665005c..f32bd16227 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -252,6 +252,14 @@ config STM32_TIMER
Select this to enable support for the timer found on
STM32 devices.
+config TEGRA_TIMER
+ bool "Tegra timer support"
+ depends on TIMER
+ select TIMER_EARLY
+ help
+ Select this to enable support for the timer found on
+ Tegra devices.
+
config X86_TSC_TIMER
bool "x86 Time-Stamp Counter (TSC) timer support"
depends on TIMER && X86
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 6470fd5426..3c92113fc6 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o
obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
+obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
obj-$(CONFIG_MCHP_PIT64B_TIMER)+= mchp-pit64b-timer.o
diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c
new file mode 100644
index 00..a867c649c3
--- /dev/null
+++ b/drivers/timer/tegra-timer.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Svyatoslav Ryhel
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define TEGRA_OSC_CLK_ENB_L_SET(NV_PA_CLK_RST_BASE + 0x320)
+#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5)
+
+#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0)
+#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4)
+
+#define TEGRA_TIMER_RATE 100 /* 1 MHz */
+
+/*
+ * On pre-DM stage timer should be left configured by
+ * previous bootloader for correct 1MHz clock.
+ * In the case of reset default value is set to 1/13 of
+ * CLK_M which should be decent enough to safely
+ * get to DM stage.
+ */
+u64 notrace timer_early_get_count(void)
+{
+ /* At this stage raw timer is used */
+ return readl(TEGRA_TIMER_USEC_CNTR);
+}
+
+unsigned long notrace timer_early_get_rate(void)
+{
+ return TEGRA_TIMER_RATE;
+}
+
+ulong timer_get_boot_us(void)
+{
+ return timer_early_get_count();
+}
+
+/*
+ * At moment of calling get_count, timer driver is already
+ * probed and is configured to have precise 1MHz clock.
+ * Tegra timer has a step of 1 microsecond which removes
+ * need of using adjusments involving uc_priv->clock_rate.
+ */
+static notrace u64 tegra_timer_get_count(struct udevice *dev)
+{
+ u32 val = timer_early_get_count();
+ return timer_conv_64(val);
+}
+
+static int tegra_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ u32 usec_config, value;
+
+ /* Timer rate has to be set unconditionally */
+ uc_priv->clock_rate = TEGRA_TIMER_RATE;
+
+ /*
+* Configure microsecond timers to have 1MHz clock
+* Config register is 0xqqww, where qq is "dividend", ww is "divisor"
+* Uses n+1 scheme
+*/
+ switch (clock_get_rate(CLOCK_ID_CLK_M)) {
+ case 1200:
+ usec_config = 0x000b; /* (11+1)/(0+1) */
+ break;
+ case 1280:
+ usec_config = 0x043f; /* (63+1)/(4+1) */
+ break;
+ case 1300:
+ usec_config = 0x000c; /* (12+1)/(0+1) */
+ break;
+ case 1680:
+ usec_config = 0x0453; /* (83+1)/(4+1) */
+ break;
+ case 1920:
+ usec_config = 0x045f; /* (95+1)/(4+1) */
+ break;
+ case 2600:
+ usec_config = 0x0019; /* (25+1)/(0+1) */
+ break;
+ case 3840:
+ usec_config = 0x04bf; /* (191+1)/(4+1) */
+ break;
+ case 4800:
+ usec_config = 0x002f; /* (47+1)/(0+1) */
+ break;
+ default:
+
[PATCH v7 0/3] Timer support for ARM Tegra
- ARM: tegra: remap clock_osc_freq for all Tegra family Enum clock_osc_freq was designed to use only with T20. This patch remaps it to use additional frequencies, added in T30+ SoC while maintaining backwards compatibility with T20. - drivers: timer: add timer driver for ARMv7 based Tegra devices Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. - ARM: tegra: include timer as default option Enable TIMER as default option for all Tegra devices and enable TEGRA_TIMER for TEGRA_ARMV7_COMMON and TEGRA210. Additionally enable SPL_TIMER if build as SPL part and drop deprecated configs from common header. P. S. I have no arm64 Tegra and according to comment in tegra-common.h Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. --- Changeog from V6 - use clk_m as timer calibration clock (this should properly fix T210) - enable timer for T210 Changed from v5: - added paz00 tester Changed from v4: - added comments Changed from v3: - removed BOOTSTAGE ifdefs - use early timer on boot stage unconditionally --- Svyatoslav Ryhel (3): ARM: tegra: remap clock_osc_freq for all Tegra family drivers: timer: add driver for ARMv7 based Tegra devices and T210 ARM: tegra: include timer as default option arch/arm/Kconfig| 1 + arch/arm/include/asm/arch-tegra/clock.h | 9 +- arch/arm/mach-tegra/Kconfig | 3 + arch/arm/mach-tegra/clock.c | 17 +++- arch/arm/mach-tegra/cpu.c | 70 ++--- arch/arm/mach-tegra/tegra114/clock.c| 13 +-- arch/arm/mach-tegra/tegra124/clock.c| 13 +-- arch/arm/mach-tegra/tegra20/clock.c | 4 +- arch/arm/mach-tegra/tegra210/clock.c| 22 +--- arch/arm/mach-tegra/tegra30/clock.c | 10 +- drivers/timer/Kconfig | 8 ++ drivers/timer/Makefile | 1 + drivers/timer/tegra-timer.c | 130 drivers/usb/host/ehci-tegra.c | 46 +++-- include/configs/tegra-common.h | 6 -- 15 files changed, 274 insertions(+), 79 deletions(-) create mode 100644 drivers/timer/tegra-timer.c -- 2.37.2
Re: [PATCH 1/1] efi_loader: don't use HandleProtocol
On Wed, 25 Jan 2023 at 19:19, Heinrich Schuchardt wrote: > > HandleProtocol() is deprecrated. According to the UEFI specification it > should be implemented as a call to OpenProtocolInterface() with a hard > coded agent handle. This implies that we would have to call > CloseProtocolInterfaces() after usage with the same handle. > > Getting rid of an EFI_CALL() is also appreciated. > > Signed-off-by: Heinrich Schuchardt > --- > lib/efi_loader/efi_boottime.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c > index e65ca6a4cb..ba28989f36 100644 > --- a/lib/efi_loader/efi_boottime.c > +++ b/lib/efi_loader/efi_boottime.c > @@ -1949,6 +1949,7 @@ efi_status_t efi_load_image_from_path(bool boot_policy, > efi_uintn_t buffer_size; > uint64_t addr, pages; > const efi_guid_t *guid; > + struct efi_handler *handler; > > /* In case of failure nothing is returned */ > *buffer = NULL; > @@ -1970,11 +1971,11 @@ efi_status_t efi_load_image_from_path(bool > boot_policy, > } > if (ret != EFI_SUCCESS) > return EFI_NOT_FOUND; > - ret = EFI_CALL(efi_handle_protocol(device, guid, > - (void **)&load_file_protocol)); > + ret = efi_search_protocol(device, guid, &handler); > if (ret != EFI_SUCCESS) > return EFI_NOT_FOUND; > buffer_size = 0; > + load_file_protocol = handler->protocol_interface; > ret = EFI_CALL(load_file_protocol->load_file( > load_file_protocol, rem, boot_policy, > &buffer_size, NULL)); > -- > 2.38.1 > Acked-by: Ilias Apalodimas
Re: DM_SERIAL is broken for Kirkwood boards
Hi all,
On Thu, Jan 26, 2023 at 3:38 PM Tony Dinh wrote:
>
> Hi all,
>
> I ran some tests today (Pogo V4 and NSA310S boards) with the latest
> master branch and saw the same behavior we've seen before. The boards
> hung, and the serial console was silent after kwboot finished
> transferring the u-boot image. I'm running with this DTSI patch below
> (to enable dm-pre-reloc for uart0).
>
> If I deselected DM_SERIAL then both boards booted OK with kwboot.
>
> diff --git a/arch/arm/dts/kirkwood-nsa310s.dts
> b/arch/arm/dts/kirkwood-nsa310s.dts
> index 09ee76c2a2..6c5a991fde 100644
> --- a/arch/arm/dts/kirkwood-nsa310s.dts
> +++ b/arch/arm/dts/kirkwood-nsa310s.dts
> @@ -317,3 +317,8 @@
> &pcie0 {
> status = "okay";
> };
> +
> +&uart0 {
> +u-boot,dm-pre-reloc;
> +status = "okay";
> +};
> diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4.dts
> b/arch/arm/dts/kirkwood-pogoplug-series-4.dts
> index 5aa4669ae2..ef495d69f5 100644
> --- a/arch/arm/dts/kirkwood-pogoplug-series-4.dts
> +++ b/arch/arm/dts/kirkwood-pogoplug-series-4.dts
> @@ -98,6 +98,7 @@
> };
>
> &uart0 {
> + u-boot,dm-pre-reloc;
> status = "okay";
> };
>
> @Michael, it would be great if you could try with your Buffalo board,
> and see if you will experience the same behavior.
Looks like this commit was the indirect cause of the problem.
Convert CONFIG_SYS_NS16550_MEM32 et al to Kconfig
https://github.com/u-boot/u-boot/commit/9591b63531fa5a34698ee7bb3800af6c4ea6ba2f
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
Later, when we enabled DM_SERIAL, CONFIG_SYS_NS16550_SERIAL and
CONFIG_SYS_NS16550_REG_SIZE got deselected. But CONFIG_SYS_NS16550 is
needed again. So bring it back and it will work.
diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig
index 3860ad30d3..f98e6cdc6e 100644
--- a/configs/pogo_v4_defconfig
+++ b/configs/pogo_v4_defconfig
@@ -70,8 +70,7 @@ CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SYS_NS16550_REG_SIZE=-4
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
All the best,
Tony
Re: [PATCH 1/1] cmd: move CONFIG_SYS_MEMTEST_START/END to cmd/Kconfig
Hello Heinrich, On 27.01.23 01:42, Heinrich Schuchardt wrote: > These symbols are not specific to Keymile boards. > > Signed-off-by: Heinrich Schuchardt > --- > board/keymile/km83xx/Kconfig | 6 -- > cmd/Kconfig | 8 > 2 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig > index f87a2e6416..014dde37cf 100644 > --- a/board/keymile/km83xx/Kconfig > +++ b/board/keymile/km83xx/Kconfig > @@ -14,12 +14,6 @@ config KM_ENABLE_FULL_DM_DTS_SUPPORT > select PHYLIB > endmenu > > -config SYS_MEMTEST_START > - default 0x0010 > - > -config SYS_MEMTEST_END > - default 0x00f0 > - > if TARGET_KMETER1 > > config SYS_BOARD > diff --git a/cmd/Kconfig b/cmd/Kconfig > index 4fe2c75de2..bffb19924d 100644 > --- a/cmd/Kconfig > +++ b/cmd/Kconfig > @@ -837,6 +837,14 @@ config CMD_MEMTEST > > if CMD_MEMTEST > > +config SYS_MEMTEST_START > + default 0x0010 if SYS_BOARD="km83xx" > + default TEXT_BASE > + > +config SYS_MEMTEST_END > + default 0x00f0 if SYS_BOARD="km83xx" > + default TEXT_BASE > + > config SYS_ALT_MEMTEST > bool "Alternative test" > help Hmm... for me with current HEAD: * b6904cc98a - (HEAD -> master, origin/master, origin/HEAD) Merge https://source.denx.de/u-boot/custodians/u-boot-spi This symbols are already in cmd/Kconfig file: 857 config SYS_MEMTEST_START 858 hex "default start address for mtest" 859 default 0x0 860 help 861 This is the default start address for mtest for simple read/write 862 test. If no arguments are given to mtest, default address is used 863 as start address. 864 865 config SYS_MEMTEST_END 866 hex "default end address for mtest" 867 default 0x1000 868 help 869 This is the default end address for mtest for simple read/write 870 test. If no arguments are given to mtest, default address is used 871 as end address. Please review, if with your patch they are not twice in cmd(Kconfig file, thanks! bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
[PATCH v2] powerpc/mpc85xx: use board env file for socrates board
as Tom suggested get rid of CFG_EXTRA_ENV_SETTINGS and
enable CONFIG_ENV_SOURCE_FILE and use text file
board/socrates/socrates.env
which contains the default environment. While at it,
cleanup the default Environment.
Signed-off-by: Heiko Schocher
Suggested-by: Tom Rini
---
This patch is a follow up as requested from Tom to socrates series
posted here:
https://lists.denx.de/pipermail/u-boot/2023-January/506030.html
Changes in v2:
add changes requested from Tom:
remove baudrate, bootcmd, bootdelay, mtdids and mtdpart setting in env file
remove CONFIG_ENV_SOURCE_FILE
board/socrates/socrates.env | 46 +++
configs/socrates_defconfig | 2 +-
include/configs/socrates.h | 62 -
3 files changed, 47 insertions(+), 63 deletions(-)
create mode 100644 board/socrates/socrates.env
diff --git a/board/socrates/socrates.env b/board/socrates/socrates.env
new file mode 100644
index 00..82e7ff8386
--- /dev/null
+++ b/board/socrates/socrates.env
@@ -0,0 +1,46 @@
+addcons=setenv bootargs $bootargs console=$consdev,$baudrate
+addip=setenv bootargs $bootargs
ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off panic=1
+addmtd=setenv bootargs ${bootargs} ${mtdparts}
+boot_nor=run ramargs addcons addmtd;
+ if test -n ${RescueSystemJumper} ;then
+ run rescueargs;
+ else
+ if imi ${system1_addr};then
+ bootm ${system1_addr};
+ else
+ setenv RescueSystemJumper 1;run rescueargs;
+ fi;
+ fi;
+ if imi ${system2_addr}; then
+ bootm ${system2_addr};
+ fi;
+boot_usb=usb start;
+ ext2load usb 0 ${usb_boot_script_r} ${usb_boot_script};
+ if imi ${usb_boot_script_r};then
+ source ${usb_boot_script_r}#conf;
+ fi;
+clean_data=era FFA0 FFFE
+clean_uboot_env=protect off FFF0 FFF3;era FFF0 FFF3
+consdev=ttyS0
+ethprime=eTSEC0
+initrd_high=0x0300
+loadaddr=0x0200
+loads_echo=1
+netdev=eth0
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath
+preboot=echo;echo Welcome on the Socrates Board;echo
+ramargs=setenv bootargs root=/dev/ram rw
+rescueargs=setenv bootargs $bootargs RescueSystemJumper=$RescueSystemJumper
+rootpath=/opt/poky/3.1.17
+system1_addr=FE00
+system1_file=system1.itb
+system2_addr=FED0
+system2_file=system2.itb
+uboot_addr=FFF4
+uboot_file=u-boot.bin
+update_system1=tftp 11 ${system1_file};era ${system1_addr} FECF;cp.b
11 ${system1_addr} ${filesize};setenv filesize
+update_system2=tftp 11 ${system2_file};era ${system2_addr} FF9F;cp.b
11 ${system2_addr} ${filesize};setenv filesize
+update_uboot=tftp 11 ${uboot_file};protect off ${uboot_addr} ;era
${uboot_addr} ;cp.b 11 ${uboot_addr} ${filesize};setenv filesize
+usb_boot_script=/boot/socrates_boot.autoscr
+usb_boot_script_r=10
+verify=1
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index e03c971b5e..312fda9ad0 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -31,7 +31,7 @@ CONFIG_BOOT_RETRY=y
CONFIG_BOOT_RETRY_TIME=120
CONFIG_RESET_TO_RETRY=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run boot_nor"
+CONFIG_BOOTCOMMAND="run boot_usb;run boot_nor"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 305914de85..64cc17ca7c 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -109,68 +109,6 @@
*/
#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux
*/
-#define SOCRATES_ENV_MTD \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"
-
-#defineCFG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consdev=ttyS0\0" \
- "initrd_high=0x0300\0" \
- "uboot_file=/home/tftp/syscon3/u-boot.bin\0"\
- "bootfile=/home/tftp/syscon3/uImage\0" \
- "fdt_file=/home/tftp/syscon3/socrates.dtb\0"\
- "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
- "uboot_addr=FFF4\0" \
- "kernel_addr=FE00\0"\
- "fdt_addr=FE1E\0" \
- "ramdisk_addr=FE20\0" \
- "fdt_addr_r=B0\0" \
- "kernel_addr_r=20\0"\
- "ram
Re: [PATCH] powerpc/mpc85xx: use board env file for socrates board
Hello Tom, On 26.01.23 15:30, Tom Rini wrote: > On Thu, Jan 26, 2023 at 08:46:21AM +0100, Heiko Schocher wrote: > >> as Tom suggested get rid of CFG_EXTRA_ENV_SETTINGS and >> enable CONFIG_ENV_SOURCE_FILE and use text file >> >> board/socrates/socrates.env >> >> which contains the default environment. While at it, >> cleanup the default Environment. >> >> Signed-off-by: Heiko Schocher >> Suggested-by: Tom Rini > [snip] >> +baudrate=CONFIG_BAUDRATE > [snip] >> +bootcmd=CONFIG_BOOTCOMMAND >> +bootdelay=CONFIG_BOOTDELAY > [snip] >> +mtdids=CONFIG_MTDIDS_DEFAULT >> +mtdparts=CONFIG_MTDPARTS_DEFAULT > > These aren't needed as they're in env_default.h Correct! I had tries with CONFIG_USE_DEFAULT_ENV_FILE, and whit it, the default settings in include/env_default.h are not active ... I rework the patch, thanks! >> @@ -70,6 +70,7 @@ >> CONFIG_MTDIDS_DEFAULT="nor0=fe00.nor_flash,nand0=socrates_nand" >> >> CONFIG_MTDPARTS_DEFAULT="mtdparts=fe00.nor_flash:13312k(system1),13312k(system2),5120k(data),128k(env),128k(env-red),768k(u-boot);socrates_nand:256M(ubi-data1),-(ubi-data2)" >> # CONFIG_CMD_IRQ is not set >> CONFIG_OF_CONTROL=y >> +CONFIG_ENV_SOURCE_FILE="socrates" >> CONFIG_ENV_IS_NOWHERE=y >> CONFIG_ENV_IS_IN_FLASH=y >> CONFIG_SYS_REDUNDAND_ENVIRONMENT=y > > And that shouldn't be needed as it's the default name I believe. Yep, I drop it. Thanks for the review. bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3] ddr: marvell: a38x: Add support for DDR4 from Marvell mv-ddr-marvell repository
Hi Pali, On Thu, Jan 26, 2023 at 1:26 AM Stefan Roese wrote: > > On 1/19/23 04:03, Tony Dinh wrote: > > This syncs drivers/ddr/marvell/a38x/ with the master branch of repository > > https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git > > > > up to the commit "mv_ddr: a3700: Use the right size for memset to not > > overflow" > > d5acc10c287e40cc2feeb28710b92e45c93c702c > > > > This patch was created by following steps: > > > > 1. Replace all a38x files in U-Boot tree by files from upstream github > > Marvell mv-ddr-marvell repository. > > > > 2. Run following command to omit portions not relevant for a38x, > > ddr3, and ddr4: > > > > files=drivers/ddr/marvell/a38x/* > > unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \ > > -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT > > -UCONFIG_PHY_STATIC \ > > -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \ > > -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X > > -UCONFIG_ARMADA_39X \ > > -UCONFIG_64BIT $files > > > > 3. Manually change license to SPDX-License-Identifier > > (upstream license in upstream github repository contains long license > > texts and U-Boot is using just SPDX-License-Identifier. > > > > After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell > > github > > repository and in U-Boot would be fully identical. So in future applying > > above steps could be used to sync code again. > > > > The only change in this patch are: > > 1. Some fixes with include files. > > 2. Some function return and basic type defines changes in > > mv_ddr_plat.c (to correct Marvell bug). > > 3. Remove of dead code in newly copied files (as a result of the > > filter script stripping out everything other than a38x, dd3, and > > ddr4). > > > > Reference: > > "ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository" > > > > https://source.denx.de/u-boot/u-boot/-/commit/107c3391b95bcc2ba09a876da4fa0c31b6c1e460 > > > > Signed-off-by: Tony Dinh > > Applied to u-boot-marvell/master > > Thanks, > Stefan Looking at the history of the work we've done to sync u-boot code back to the mv-ddr-marvell repo, I think I should follow the same approach. So I've pushed 2 commits to my GitHub repo. https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/compare/master...mibodhi:mv-ddr-marvell:u-boot-ddr4-2023.01-fix Please review these 2 commits and create a pull request to Marvell, like you did for others last year during DDR3 code sync. Thanks, Tony
Re: [PATCH v6 0/3] Timer support for ARM Tegra
Good point. U-Boot has instruments to get clk_m rate on time of timer
probe. I need some time to prepare this modification for testing.
пт, 27 січ. 2023 р. о 00:12 Dmitry Osipenko пише:
>
> 27.01.2023 01:00, Dmitry Osipenko пишет:
> > 26.01.2023 20:54, Thierry Reding пишет:
> >> On Thu, Jan 26, 2023 at 07:08:54PM +0200, Svyatoslav Ryhel wrote:
> >>> чт, 26 січ. 2023 р. о 12:35 Thierry Reding
> >>> пише:
>
> On Wed, Jan 25, 2023 at 05:41:08PM +0100, Thierry Reding wrote:
> > On Tue, Jan 24, 2023 at 08:57:48AM +0200, Svyatoslav Ryhel wrote:
> >> - ARM: tegra: remap clock_osc_freq for all Tegra family
> >> Enum clock_osc_freq was designed to use only with T20.
> >> This patch remaps it to use additional frequencies, added in
> >> T30+ SoC while maintaining backwards compatibility with T20.
> >>
> >> - drivers: timer: add timer driver for ARMv7 based Tegra devices
> >> Add timer support for T20/T30/T114 and T124 based devices.
> >> Driver is based on DM, has device tree support and can be
> >> used on SPL and early boot stage.
> >>
> >> - ARM: tegra: include timer as default option
> >> Enable TIMER as default option for all Tegra devices and
> >> enable TEGRA_TIMER for TEGRA_ARMV7_COMMON. Additionally
> >> enable SPL_TIMER if build as SPL part and drop deprecated
> >> configs from common header.
> >>
> >> P. S. I have no arm64 Tegra and according to comment in
> >> tegra-common.h
> >> Use the Tegra US timer on ARMv7, but the architected timer on ARMv8.
> >>
> >> Svyatoslav Ryhel (3):
> >> ARM: tegra: remap clock_osc_freq for all Tegra family
> >> drivers: timer: add timer driver for ARMv7 based Tegra devices
> >> ARM: tegra: include timer as default option
> >
> > This causes a regression on Tegra210 (Jetson TX1). I'm trying to
> > investigate, but it's complicated by the fact that I'm not getting out
> > any debug prints, so I suspect the issue is happening quite early.
>
> Alright, I managed to make this work on Tegra210 using the following
> patch on top of this series:
>
> >>>
> >>> Hello! Thanks for testing this on T210 SoC.
> >>>
> --- >8 ---
> diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi
> index a521a43d6cfd..ccb5a927da89 100644
> --- a/arch/arm/dts/tegra210.dtsi
> +++ b/arch/arm/dts/tegra210.dtsi
> @@ -318,7 +318,7 @@
> };
>
> timer@60005000 {
> - compatible = "nvidia,tegra210-timer",
> "nvidia,tegra20-timer";
> + compatible = "nvidia,tegra210-timer",
> "nvidia,tegra30-timer", "nvidia,tegra20-timer";
> >>>
> >>> This compatibe should not be needed since the driver will have t210
> >>> compatible included.
> >>
> >> Yes, it should be fine to leave this as-is. I had included this before
> >> updating the driver, to get the driver to bind to this. Upstream Linux
> >> doesn't include "nvidia,tegra20-timer", so it only has the compatible
> >> string for Tegra210. I think that's slightly better because the register
> >> interface isn't quite compatible. That's a separate issue and we can do
> >> that in a follow-up patch.
> >>
> >>>
> reg = <0x0 0x60005000 0x0 0x400>;
> interrupts = ,
> ,
> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> index cc3f00e50128..b50eec5b8c9b 100644
> --- a/arch/arm/mach-tegra/Kconfig
> +++ b/arch/arm/mach-tegra/Kconfig
> @@ -136,6 +136,7 @@ config TEGRA210
> select TEGRA_PINCTRL
> select TEGRA_PMC
> select TEGRA_PMC_SECURE
> + select TEGRA_TIMER
>
> config TEGRA186
> bool "Tegra186 family"
> diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c
> index d2d163cf3fef..235532ba8926 100644
> --- a/drivers/timer/tegra-timer.c
> +++ b/drivers/timer/tegra-timer.c
> @@ -58,17 +58,26 @@ static notrace u64 tegra_timer_get_count(struct
> udevice *dev)
> static int tegra_timer_probe(struct udevice *dev)
> {
> struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> + enum clock_osc_freq freq;
> u32 usec_config, value;
>
> /* Timer rate has to be set unconditionally */
> uc_priv->clock_rate = TEGRA_TIMER_RATE;
>
> + /*
> +* The microsecond timer runs off of clk_m on Tegra210, and clk_m
> +* runs at half the OSC, so fake this up.
> +*/
> + freq = clock_get_osc_freq();
> + if (freq == CLOCK_OSC_FREQ_38_4)
> + freq = CLOCK_OSC_FREQ_19_2;
> +
> >>>
> >>> May you confirm that ALL known T210 devices use 19.2MHz as calibration
> >>> clock for timer?
> >>
> >> According to the Tegra210 TRM
Please pull u-boot-dm
Hi Tom, https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/14897 The following changes since commit 27e0fb3b0823519aea2d42cd8bde20234dd87cef: Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2023-01-26 10:24:13 -0500) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-26jan23 for you to fetch changes up to 060a65e899859dcbf42049a18be20ce7118e7c0e: binman: Fix a test-coverage regression (2023-01-26 10:47:45 -0700) FIT improvements with split-elf, especially for Rockchip Binman positioning by ELF symbol Jonas Karlman (6): binman: Add support for align argument to mkimage tool rockchip: Align FIT image data to SD/MMC block length binman: Add special subnodes to the nodes generated by split-elf rockchip: Add sha256 hash to FIT images binman: Add support for selecting firmware to use with split-elf rockchip: Use atf as firmware and move u-boot to loadables in FIT Samuel Holland (2): binman: Add 'min-size' entry property dm: core: Use full printf() format when possible Simon Glass (1): binman: Fix a test-coverage regression arch/arm/dts/rockchip-u-boot.dtsi| 23 - drivers/core/dump.c | 2 +- tools/binman/binman.rst | 8 + tools/binman/btool/mkimage.py| 5 ++- tools/binman/elf_test.py | 13 +++- tools/binman/entries.rst | 35 +--- tools/binman/entry.py| 4 +++ tools/binman/entry_test.py | 19 +++ tools/binman/etype/fit.py| 93 ++-- tools/binman/ftest.py| 93 +--- tools/binman/test/009_pack_extra.dts | 7 tools/binman/test/226_fit_split_elf.dts | 6 tools/binman/test/275_fit_align.dts | 59 + tools/binman/test/276_fit_firmware_loadables.dts | 96 ++ tools/binman/test/embed_data.c | 1 + 15 files changed, 441 insertions(+), 23 deletions(-) create mode 100644 tools/binman/test/275_fit_align.dts create mode 100644 tools/binman/test/276_fit_firmware_loadables.dts Regards, Simon
Re: [PATCH v2 17/17] test/py: android: extend abootimg test
Hi Safae, On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > test_abootimg is extended to include the testing of boot images > version 4. For this, boot.img and vendor_boot.img have been > generated using mkbootimg tool with setting the header > version to 4. > > This tests: > - Getting the header version using abootimg > - Extracting the load address of the dtb > - Extracting the dtb start address in RAM > > Running test: > $ ./test/py/test.py --bd sandbox --build -k test_abootimg > > Signed-off-by: Safae Ouajih > --- > test/py/tests/test_android/test_abootimg.py | 135 ++-- > 1 file changed, 122 insertions(+), 13 deletions(-) > Reviewed-by: Simon Glass Question below > diff --git a/test/py/tests/test_android/test_abootimg.py > b/test/py/tests/test_android/test_abootimg.py > index 43a7099c46..a5c734b9c5 100644 > --- a/test/py/tests/test_android/test_abootimg.py > +++ b/test/py/tests/test_android/test_abootimg.py > @@ -32,6 +32,23 @@ Now one can obtain original boot.img from this hex dump > like this: > > $ xxd -r -p boot.img.gz.hex boot.img.gz > $ gunzip -9 boot.img.gz > + > +For boot image header version 4, these tests rely on two images that are > generated > +using the same steps above : > + > +1- boot.img : > +$ mkbootimg --kernel ./kernel --ramdisk ./ramdisk.img \ > +--cmdline "cmdline test" --dtb ./dtb.img \ > +--os_version R --os_patch_level 2019-06-05 \ > +--header_version 4 --output ./boot.img > + > +2- vendor_boot.img > +$ mkbootimg --kernel ./kernel --ramdisk ./ramdisk.img \ > +--cmdline "cmdline test" --dtb ./dtb.img \ > +--os_version R --os_patch_level 2019-06-05 \ > +--pagesize 4096 --vendor_ramdisk ./ramdisk.img \ > +--header_version 4 --vendor_boot ./vboot.img \ Is it possible for us to run these commands in the test, to avoid hassle when we want to change the disk image? See test_ut.py > + > """ > > # boot.img.gz hex dump > @@ -44,6 +61,24 @@ > b776207d345446c1281805e8a0868d81e117a45e111c0d8dc101b253 > 9c03c41a0c90f17fe85400986d82452b6c3680198a192a0ce17c3610ae34 > d4a9820881a70f3873f35352731892f3730b124b32937252a96bb9119ae5 > 463a5546f82c1f05a360148c8251300a462e85bf67f20020""" > + > +# boot img v4 hex dump > +boot_img_hex = > """1f8b080827b0cd630203626f6f742e696d6700edd8bd0d82601885d1d7c4 > +58d8c808b88195bd098d8d246e40e42b083f1aa0717be99d003d277916b8 > +e5bddc8a7b792d8e8788c896ce9b88d32ebe6c971e7ddd3543cae734cd01 > +c0ffc84cb0766d1a87d4e5afeadd3dab7a6f1000f84163d5d7cd > +d43a60c53e754499570040""" > + > +# vendor boot image v4 hex dump > +vboot_img_hex = > """1f8b0808baaecd63020376626f6f742e696d6700edd8310b824018c6f1b3 > +222a08f41b3436b4280dcdd19c11d16ee9109d18d59042d047ec8b04cd0d > +d19d5a4345534bf6ffc173ef29272f38e93b1d0ec67dd79d548462aa1cd2 > +d5d20bf8438678f90c18d584b8a4bbb3a557991ecb2af80d6b2f > +f4179b656be5c532f2fc066f0480e23936af2755f62a3d918df1 > +db2a7ab67f9ffdeb7df7cda3465ecb79c4ce7e5c577562bb9364b74449a5 > +1e467e20c53c0a57de763193c1779b3b4fcd9d4ee27c6a0ec0ff > +309ffea70140f1dc00412985540040""" > + [..] > -gtdi = None > +gtdi1 = None > @pytest.fixture(scope='function') > def abootimg_disk_image(u_boot_console): > """pytest fixture to provide a AbootimgTestDiskImage object to tests. > @@ -109,10 +148,36 @@ def abootimg_disk_image(u_boot_console): > function-scoped. However, we don't need to actually do any function-scope > work, so this simply returns the same object over and over each time.""" > > -global gtdi > -if not gtdi: > -gtdi = AbootimgTestDiskImage(u_boot_console) > -return gtdi > +global gtdi1 > +if not gtdi1: > +gtdi1 = AbootimgTestDiskImage(u_boot_console, 'boot.img', img_hex) > +return gtdi1 > + > +gtdi2 = None > +@pytest.fixture(scope='function') > +def abootimgv4_disk_image_vboot(u_boot_console): > +"""pytest fixture to provide a AbootimgTestDiskImage object to tests. > +This is function-scoped because it uses u_boot_console, which is also > +function-scoped. However, we don't need to actually do any function-scope > +work, so this simply returns the same object over and over each time.""" > + > +global gtdi2 > +if not gtdi2: > +gtdi2 = AbootimgTestDiskImage(u_boot_console, 'vendor_boot.img', > vboot_img_hex) > +return gtdi2 > + > +gtdi3 = None > +@pytest.fixture(scope='function') > +def abootimgv4_disk_image_boot(u_boot_console): > +"""pytest fixture to provide a AbootimgTestDiskImage object to tests. blank line here (please fix throughout) > +This is function-scoped because it uses u_boot_console, which is also > +function-scoped. However, we don't need to actually do any function-scope > +work, so this simply returns the same object over and over each time.""" > + > +global gtdi3 > +if not
Re: [PATCH] phy: add of_set_phy_supported() helper, call from phy_config()
Hi Rasmus,
On Tue, 9 Aug 2022 at 05:53, Rasmus Villemoes
wrote:
>
> Currently, U-Boot doesn't parse a "max-speed" DT property in a phy's
> DT node. That property is a standard binding which should be honoured,
> and in linux that is done by the core phy code via a call to an
> of_set_phy_supported() helper. (Some ethernet drivers support a
> max-speed property in their DT node, but that's orthogonal to what the
> phy supports.)
>
> Add a similar helper in U-Boot, and call it from phy_config().
>
> Signed-off-by: Rasmus Villemoes
> ---
> Resending, this time including the u-boot list in recipients. Sorry
> for the duplicate.
>
> drivers/net/phy/phy.c | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index e6e1755518..ec690361e6 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -599,6 +599,20 @@ int phy_register(struct phy_driver *drv)
> return 0;
> }
>
> +static int of_set_phy_supported(struct phy_device *phydev)
> +{
> + ofnode node = phy_get_ofnode(phydev);
> + u32 max_speed;
> +
> + if (!ofnode_valid(node))
> + return 0;
> +
> + if (!ofnode_read_u32(node, "max-speed", &max_speed))
> + return phy_set_supported(phydev, max_speed);
> +
> + return 0;
> +}
> +
> int phy_set_supported(struct phy_device *phydev, u32 max_speed)
> {
> /* The default values for phydev->supported are provided by the PHY
> @@ -1070,6 +1084,12 @@ __weak int board_phy_config(struct phy_device *phydev)
>
> int phy_config(struct phy_device *phydev)
> {
> + int ret;
> +
> + ret = of_set_phy_supported(phydev);
> + if (ret)
> + return ret;
> +
> /* Invoke an optional board-specific helper */
> return board_phy_config(phydev);
> }
> --
> 2.31.1
>
The only problem with this is that it is reading DT outside the
of_to_plat() method. Is it possible to call it from there?
Regards,
Simon
Re: [PATCH v2 16/17] android: boot: support bootconfig
Hi Safae,
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote:
>
> This adds support for Bootconfig feature.
> - The bootconfig feature replaces the androidboot.*
> kernel cmdline options.
>
> This was adapted from downstream [1] commit : 7af0a0506d4d ("cuttlefish:
> support bootconfig parameters").
>
> Link:[1] https://android.googlesource.com/platform/external/u-boot/
>
> Signed-off-by: Safae Ouajih
> ---
> boot/image-android.c| 58 +++--
> include/android_image.h | 11
> 2 files changed, 67 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass
nit below
[..]
> diff --git a/include/android_image.h b/include/android_image.h
> index 351e17750e..6e1afae4c0 100644
> --- a/include/android_image.h
> +++ b/include/android_image.h
> @@ -25,6 +25,14 @@
> #define ANDR_VENDOR_BOOT_ARGS_SIZE 2048
> #define ANDR_VENDOR_BOOT_NAME_SIZE 16
>
> +#define BOOTCONFIG_MAGIC "#BOOTCONFIG\n"
> +#define BOOTCONFIG_MAGIC_SIZE 12
> +#define BOOTCONFIG_SIZE_SIZE 4
> +#define BOOTCONFIG_CHECKSUM_SIZE 4
> +#define BOOTCONFIG_TRAILER_SIZE BOOTCONFIG_MAGIC_SIZE + \
> + BOOTCONFIG_SIZE_SIZE + \
> + BOOTCONFIG_CHECKSUM_SIZE
> +
> struct andr_boot_img_hdr_v3 {
> u8 magic[ANDR_BOOT_MAGIC_SIZE];
>
> @@ -333,6 +341,9 @@ struct andr_image_data {
> ulong recovery_dtbo_ptr;
> u32 recovery_dtbo_size;
>
> + ulong bootconfig_addr;
> + ulong bootconfig_size;
> +
> const char *kcmdline;
> const char *kcmdline_extra;
> const char *image_name;
> --
> 2.34.1
>
That struct needs a full comment
REgards,
Simon
Re: [PATCH v2 12/17] android: boot: support extra command line
Hi Safae,
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote:
>
> In version 3 and 4 of boot image header, the vendor specific
vendor-spefcific
> command line are located in vendor boot image. Thus, using
use the
> extra command line to add those cmd to bootargs.
>
> Signed-off-by: Safae Ouajih
> ---
> boot/image-android.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/boot/image-android.c b/boot/image-android.c
> index 5b270e4417..cb4fc22b00 100644
> --- a/boot/image-android.c
> +++ b/boot/image-android.c
> @@ -55,6 +55,7 @@ static void android_vendor_boot_image_v3_v4_parse_hdr(const
> struct andr_vendor_i
> * The header takes a full page, the remaining components are aligned
> * on page boundary.
> */
> + data->kcmdline_extra = hdr->cmdline;
> data->tags_addr = hdr->tags_addr;
> data->image_name = hdr->name;
> data->kernel_addr = hdr->kernel_addr;
> @@ -233,6 +234,11 @@ int android_image_get_kernel(const struct
> andr_boot_img_hdr_v0 *hdr,
> len += strlen(img_data.kcmdline);
> }
>
> + if (img_data.kcmdline_extra) {
> + printf("Kernel extra command line: %s\n",
> img_data.kcmdline_extra);
> + len += strlen(img_data.kcmdline_extra);
> + }
> +
> char *bootargs = env_get("bootargs");
> if (bootargs)
> len += strlen(bootargs);
> @@ -252,6 +258,11 @@ int android_image_get_kernel(const struct
> andr_boot_img_hdr_v0 *hdr,
> if (*img_data.kcmdline)
> strcat(newbootargs, img_data.kcmdline);
>
> + if (img_data.kcmdline_extra) {
> + strcat(newbootargs, " ");
> + strcat(newbootargs, img_data.kcmdline_extra);
Do we need to worry about overflow?
> + }
> +
> env_set("bootargs", newbootargs);
>
> if (os_data) {
> --
> 2.34.1
>
Regards,
Simon
Re: [PATCH v2 10/17] android: boot: update android_image_get_data to support v3,v4
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > Since boot image header version 3 and 4 introduced vendor boot image, > the following functions are used to fill the generic android > structure : andr_image_data: > > - android_boot_image_v3_v4_parse_hdr() > - android_vendor_boot_image_v3_v4_parse_hdr() > > android_image_get_data() is then updated to support v3 and v4 > > Signed-off-by: Safae Ouajih > --- > boot/image-android.c| 80 +++-- > include/android_image.h | 3 ++ > include/image.h | 1 + > 3 files changed, 81 insertions(+), 3 deletions(-) Comments again, for struct and image.h Otherwise: Reviewed-by: Simon Glass
Re: [PATCH v2 06/17] android: boot: move to andr_image_data structure
Hi Safae, On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > Move from andr_boot_img_hdr_v0 to andr_image_data > structure to prepare for boot image header > version 3 and 4. > > Signed-off-by: Safae Ouajih > --- > boot/image-android.c | 127 --- > cmd/abootimg.c | 31 ++- > include/image.h | 2 + > 3 files changed, 89 insertions(+), 71 deletions(-) > Do you need the #ifdef CONFIG_CMD_ABOOTIMG? We try to avoid adding those. Regards, Simon
Re: [PATCH] serial: s5p: Use IS_ENABLED where appropriate
On Thu, 26 Jan 2023 at 06:44, Mark Kettenis wrote: > > There are no SPL/TPL variants of CONFIG_CLK_EXYNOS and > CONFIG_ARCH_APPLE, so switch from CONFIG_IS_ENABLED to > IS_ENABLED. > > Signed-off-by: Mark Kettenis > --- > drivers/serial/serial_s5p.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Simon Glass
Re: [PATCH v2 08/17] android: boot: boot image header v3,v4 do not support recovery DTBO
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote:
>
> android_image_get_dtbo() is used to get recovery DTBO via abootimg cmd.
> This is not supported in boot image header v3 and v4. Thus, we print an
> error message when v1,v2 header version are not used.
>
> Signed-off-by: Safae Ouajih
> ---
> boot/image-android.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass
log_err() might be better
>
> diff --git a/boot/image-android.c b/boot/image-android.c
> index a6e7a7abb0..d797270a32 100644
> --- a/boot/image-android.c
> +++ b/boot/image-android.c
> @@ -316,8 +316,8 @@ bool android_image_get_dtbo(ulong hdr_addr, ulong *addr,
> u32 *size)
> goto exit;
> }
>
> - if (hdr->header_version < 1) {
> - printf("Error: header_version must be >= 1 to get dtbo\n");
> + if (hdr->header_version != 1 && hdr->header_version != 2) {
> + printf("Error: header version must be >= 1 and <= 2 to get
> dtbo\n");
> ret = false;
> goto exit;
> }
> --
> 2.34.1
>
Re: [PATCH v4 3/6] bootm: Support boot measurement
Hi Eddie, On Thu, 26 Jan 2023 at 07:41, Eddie James wrote: > > > On 1/25/23 19:41, Simon Glass wrote: > > Hi Eddie, > > > > On Wed, 25 Jan 2023 at 10:18, Eddie James wrote: > >> Add a configuration option to measure the boot through the bootm > >> function. Add the measurement state to the booti and bootz paths > >> as well. > >> > >> Signed-off-by: Eddie James > >> --- > >> boot/Kconfig| 23 > >> boot/bootm.c| 70 + > >> cmd/booti.c | 1 + > >> cmd/bootm.c | 2 ++ > >> cmd/bootz.c | 1 + > >> include/bootm.h | 2 ++ > >> include/image.h | 1 + > >> 7 files changed, 100 insertions(+) > > Can you please add a change log? I recall making comments but cannot > > see the changes here. > > > Sorry, sure. I put them all in the cover letter, but I can add them here > too. It makes it much easier for your reviewer. Sorry if I have mentioned this before, but patman does this automatically. Regards, Simon
Re: [PATCH v2 05/17] android: boot: kcomp: support andr_image_data
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote:
>
> andr_image_data structure is used as a global representation of
> boot image header structure. This new structure is introduced to
> support all boot header versions : v0,v1.v2.v3.v4 and will be used
> to support v3 and v4 while maitaining support for v0,v1,v2. The need
> of using andr_image_data comes from the change of header structure in
> both version 3 and 4.
>
> android_image_get_kcomp() is reworked to support this new struct.
nit: Your commit messages should be in imperative tense. See [1] for
some thoughts on this.
>
> Signed-off-by: Safae Ouajih
> ---
> boot/image-android.c| 75 -
> include/android_image.h | 27 +++
> include/image.h | 2 ++
> 3 files changed, 103 insertions(+), 1 deletion(-)
>
Reviewed-by: Simon Glass
But please comment struct andr_image_data.
[..]
> diff --git a/include/android_image.h b/include/android_image.h
> index 4fce363ff7..5b36f96d7b 100644
> --- a/include/android_image.h
> +++ b/include/android_image.h
> @@ -317,4 +317,31 @@ struct andr_boot_img_hdr_v0 {
> *contained outside boot and vendor boot partitions), otherwise
> *jump to kernel_addr
> */
> +
> +/* Private struct */
> +struct andr_image_data {
> + ulong kernel_ptr;
> + u32 kernel_size;
> + u32 ramdisk_size;
> + u32 boot_ramdisk_size;
> + ulong second_ptr;
> + u32 second_size;
> + ulong dtb_ptr;
> + u32 dtb_size;
> + ulong recovery_dtbo_ptr;
> + u32 recovery_dtbo_size;
> +
> + const char *kcmdline;
> + const char *kcmdline_extra;
> + const char *image_name;
> +
> + u32 kernel_addr;
> + ulong ramdisk_addr;
> + ulong ramdisk_ptr;
> + ulong dtb_load_addr;
> + ulong tags_addr;
> + u32 header_version;
> + u32 boot_img_total_size;
> +};
> +
> #endif
> diff --git a/include/image.h b/include/image.h
> index c1594ee169..9a0bd9d8f2 100644
> --- a/include/image.h
> +++ b/include/image.h
> @@ -1733,7 +1733,9 @@ struct cipher_algo {
> int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo);
>
> struct cipher_algo *image_get_cipher_algo(const char *full_name);
> +struct andr_image_data;
>
> +bool android_image_get_data(const void *boot_hdr, struct andr_image_data
> *data);
> struct andr_boot_img_hdr_v0;
> int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int
> verify,
> ulong *os_data, ulong *os_len);
> --
> 2.34.1
>
[1]
https://chromium.googlesource.com/chromiumos/docs/+/HEAD/contributing.md#commit-messages
Re: [PATCH v2 15/17] android: boot: support boot image header version 3 and 4
Hi Safae,
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote:
>
> This enables the support for boot image header version 3 and 4
> using abootimg command.
>
> In order to use version 3 or 4:
>
> 1- Vendor boot image address should be given to abootimg cmd.
>
> abootimg addr $1 $vendor_boot_load_addr
>
> 2- "ramdisk_addr_r" env variable (ramdisk address) should be set to host
> the ramdisk : generic ramdisk + vendor ramdisk
>
> "struct andr_boot_img_hdr_v0*" is replaced by "void *" in
> some functions since v3 and v4 are now supported as well.
>
> Signed-off-by: Safae Ouajih
> ---
> boot/bootm.c | 29 -
> boot/image-android.c | 16 ++--
> boot/image-board.c | 14 +++---
> boot/image-fdt.c | 2 +-
> cmd/abootimg.c | 24 ++--
> include/image.h | 14 --
> 6 files changed, 76 insertions(+), 23 deletions(-)
>
> diff --git a/boot/bootm.c b/boot/bootm.c
> index a58e6f391e..3e130c175c 100644
> --- a/boot/bootm.c
> +++ b/boot/bootm.c
> @@ -113,6 +113,10 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int
> flag, int argc,
> char *const argv[])
> {
> const void *os_hdr;
> +#ifdef CONFIG_ANDROID_BOOT_IMAGE
> + const void *vendor_boot_img;
> + const void *boot_img;
> +#endif
> bool ep_found = false;
> int ret;
>
> @@ -181,12 +185,17 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int
> flag, int argc,
> #endif
> #ifdef CONFIG_ANDROID_BOOT_IMAGE
> case IMAGE_FORMAT_ANDROID:
> + boot_img = os_hdr;
> + vendor_boot_img = NULL;
> + if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
> + boot_img = (void *)get_abootimg_addr();
> + vendor_boot_img = (void *)get_avendor_bootimg_addr();
map_sysmem() so it owrks on sandbox
> + }
> images.os.type = IH_TYPE_KERNEL;
> - images.os.comp = android_image_get_kcomp(os_hdr, NULL);
> + images.os.comp = android_image_get_kcomp(boot_img,
> vendor_boot_img);
> images.os.os = IH_OS_LINUX;
> -
> - images.os.end = android_image_get_end(os_hdr, NULL);
> - images.os.load = android_image_get_kload(os_hdr, NULL);
> + images.os.end = android_image_get_end(boot_img,
> vendor_boot_img);
> + images.os.load = android_image_get_kload(boot_img,
> vendor_boot_img);
> images.ep = images.os.load;
> ep_found = true;
> break;
> @@ -889,6 +898,10 @@ static const void *boot_get_kernel(struct cmd_tbl
> *cmdtp, int flag, int argc,
> int os_noffset;
> #endif
>
> +#ifdef CONFIG_ANDROID_BOOT_IMAGE
> + const void *boot_img;
> + const void *vendor_boot_img;
> +#endif
> img_addr = genimg_get_kernel_addr_fit(argc < 1 ? NULL : argv[0],
> &fit_uname_config,
> &fit_uname_kernel);
> @@ -964,8 +977,14 @@ static const void *boot_get_kernel(struct cmd_tbl
> *cmdtp, int flag, int argc,
> #endif
> #ifdef CONFIG_ANDROID_BOOT_IMAGE
> case IMAGE_FORMAT_ANDROID:
> + boot_img = buf;
> + vendor_boot_img = NULL;
> + if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) {
> + boot_img = (void *)get_abootimg_addr();
> + vendor_boot_img = (void *)get_avendor_bootimg_addr();
and here
> + }
> printf("## Booting Android Image at 0x%08lx ...\n", img_addr);
> - if (android_image_get_kernel(buf, NULL, images->verify,
> + if (android_image_get_kernel(boot_img, vendor_boot_img,
> images->verify,
> os_data, os_len))
> return NULL;
> break;
> diff --git a/boot/image-android.c b/boot/image-android.c
> index edeeaaaee0..dd06c09279 100644
> --- a/boot/image-android.c
> +++ b/boot/image-android.c
> @@ -201,7 +201,7 @@ static ulong android_image_get_kernel_addr(struct
> andr_image_data *img_data)
> * Return: Zero, os start address and length on success,
> * otherwise on failure.
> */
> -int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr,
> +int android_image_get_kernel(const void *hdr,
> const void *vendor_boot_img, int verify,
> ulong *os_data, ulong *os_len)
> {
> @@ -286,7 +286,7 @@ bool is_android_vendor_boot_image_header(const void
> *vendor_boot_img)
> return !memcmp(VENDOR_BOOT_MAGIC, vendor_boot_img,
> ANDR_VENDOR_BOOT_MAGIC_SIZE);
> }
>
> -bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr)
> +bool is_android_boot_image_header(const void *hdr)
> {
> return !memcmp(ANDR_BOOT_MAGIC, hdr, ANDR_BOOT_MAGIC_SIZE);
> }
>
Re: [PATCH v2 11/17] android: boot: ramdisk: support vendor ramdisk
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > Version 3 and 4 of boot image header introduced > vendor boot ramdisk: Please check include/android_image.h > for details. > > The ramdisk is now split into a generic ramdisk in boot image > and a vendor ramdisk in vendor boot image. > > Signed-off-by: Safae Ouajih > --- > boot/image-android.c | 13 +++-- > include/image.h | 4 ++-- > 2 files changed, 13 insertions(+), 4 deletions(-) > Some comment re comments With that: Reviewed-by: Simon Glass
Re: [PATCH v2 09/17] android: boot: add vendor boot image to prepare for v3,v4 support
Hi Safae, On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > This is done to prepare for boot image version 3 and 4 support. > > Signed-off-by: Safae Ouajih > --- > boot/bootm.c | 8 +++ > boot/image-android.c | 54 > boot/image-board.c | 3 +-- > boot/image-fdt.c | 3 ++- > cmd/abootimg.c | 4 ++-- > include/image.h | 22 +++--- > 6 files changed, 58 insertions(+), 36 deletions(-) > > diff --git a/include/image.h b/include/image.h > index 6264d13e0c..df8a9075fa 100644 > --- a/include/image.h > +++ b/include/image.h > @@ -1735,20 +1735,26 @@ int fit_image_cipher_get_algo(const void *fit, int > noffset, char **algo); > struct cipher_algo *image_get_cipher_algo(const char *full_name); > struct andr_image_data; > > -bool android_image_get_data(const void *boot_hdr, struct andr_image_data > *data); > +bool android_image_get_data(const void *boot_hdr, const void > *vendor_boot_hdr, > + struct andr_image_data *data); > + > struct andr_boot_img_hdr_v0; > -int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int > verify, > +int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, > +const void *vendor_boot_img, int verify, > ulong *os_data, ulong *os_len); > int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, > - ulong *rd_data, ulong *rd_len); > + const void *vendor_boot_img, ulong *rd_data, > ulong *rd_len); > int android_image_get_second(const struct andr_boot_img_hdr_v0 *hdr, > ulong *second_data, ulong *second_len); > bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size); > -bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, > - u32 *size); > -ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr); > -ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr); > -ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr); > +bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img, > + u32 index, ulong *addr, u32 *size); > +ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr, > + const void *vendor_boot_img); > +ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr, > + const void *vendor_boot_img); > +ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr, > + const void *vendor_boot_img); > void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr); > #ifdef CONFIG_CMD_ABOOTIMG > bool android_image_print_dtb_contents(ulong hdr_addr); > -- > 2.34.1 > Please add comments for those that you change. Really all of these should have proper comments. Regards, Simon
Re: [PATCH v2 13/17] android: boot: update android_image_get_dtb_img_addr to support v3,v4
Hi Safae,
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote:
>
> This adds support for boot image version 3 and 4
> in android_image_get_dtb_img_addr(). Since the dtb
> is now included in vendor_boot image instead of
> boot image, the dtb address should be extracted from
> vendor_boot image when a v3 or v4 is used.
>
> Signed-off-by: Safae Ouajih
> ---
> boot/image-android.c | 47 +++-
> 1 file changed, 33 insertions(+), 14 deletions(-)
>
Reviewed-by: Simon Glass
nits below
> diff --git a/boot/image-android.c b/boot/image-android.c
> index cb4fc22b00..edeeaaaee0 100644
> --- a/boot/image-android.c
> +++ b/boot/image-android.c
> @@ -459,6 +459,7 @@ exit:
> static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong vhdr_addr,
> ulong *addr)
> {
> const struct andr_boot_img_hdr_v0 *hdr;
> + const struct andr_vendor_img_hdr *v_hdr;
> ulong dtb_img_addr;
> bool ret = true;
>
> @@ -475,22 +476,40 @@ static bool android_image_get_dtb_img_addr(ulong
> hdr_addr, ulong vhdr_addr, ulon
> goto exit;
> }
>
> - if (hdr->dtb_size == 0) {
> - printf("Error: dtb_size is 0\n");
> - ret = false;
> - goto exit;
> + if (hdr->header_version == 2) {
> + if (hdr->dtb_size == 0) {
if (!hdr->dtb_size)
> + printf("Error: dtb_size is 0\n");
> + ret = false;
> + goto exit;
> + }
> + /* Calculate the address of DTB area in boot image */
> + dtb_img_addr = hdr_addr;
> + dtb_img_addr += hdr->page_size;
> + dtb_img_addr += ALIGN(hdr->kernel_size, hdr->page_size);
> + dtb_img_addr += ALIGN(hdr->ramdisk_size, hdr->page_size);
> + dtb_img_addr += ALIGN(hdr->second_size, hdr->page_size);
> + dtb_img_addr += ALIGN(hdr->recovery_dtbo_size,
> hdr->page_size);
> +
> + *addr = dtb_img_addr;
> }
>
> - /* Calculate the address of DTB area in boot image */
> - dtb_img_addr = hdr_addr;
> - dtb_img_addr += hdr->page_size;
> - dtb_img_addr += ALIGN(hdr->kernel_size, hdr->page_size);
> - dtb_img_addr += ALIGN(hdr->ramdisk_size, hdr->page_size);
> - dtb_img_addr += ALIGN(hdr->second_size, hdr->page_size);
> - dtb_img_addr += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
> -
> - *addr = dtb_img_addr;
> -
> + if (hdr->header_version > 2) {
> + v_hdr = map_sysmem(vhdr_addr, sizeof(*v_hdr));
> + if (v_hdr->dtb_size == 0) {
same here
> + printf("Error: dtb_size is 0\n");
> + ret = false;
> + unmap_sysmem(v_hdr);
> + goto exit;
> + }
> + /* Calculate the address of DTB area in boot image */
> + dtb_img_addr = vhdr_addr;
> + dtb_img_addr += v_hdr->page_size;
> + if (v_hdr->vendor_ramdisk_size)
> + dtb_img_addr += ALIGN(v_hdr->vendor_ramdisk_size,
> v_hdr->page_size);
> + *addr = dtb_img_addr;
> + unmap_sysmem(v_hdr);
> + goto exit;
> + }
> exit:
> unmap_sysmem(hdr);
> return ret;
> --
> 2.34.1
>
Regards,
Simon
Re: [PATCH v2 14/17] drivers: fastboot: zImage flashing is not supported for v3,v4
Hi Safae,
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote:
>
> Print an error message when the boot image header version is
> greater than 2 as this is not supported for v3 and v4.
But why is is not supported? Please add this here.
>
> Signed-off-by: Safae Ouajih
> ---
> drivers/fastboot/fb_mmc.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
> index 086e5f7843..9fb2ab3820 100644
> --- a/drivers/fastboot/fb_mmc.c
> +++ b/drivers/fastboot/fb_mmc.c
> @@ -370,6 +370,14 @@ static int fb_mmc_update_zimage(struct blk_desc
> *dev_desc,
> return -1;
> }
>
> + /* Check if boot image header version is 2 or less */
> + if (hdr->header_version > 2) {
> + pr_err("zImage flashing supported only for boot images v2 and
> less\n");
> + fastboot_fail("zImage flashing supported only for boot images
> v2 and less",
> + response);
> + return -1;
That is not an error message. Perhaps -ENOTSUPP ?
> + }
> +
> /* Check if boot image has second stage in it (we don't support it) */
> if (hdr->second_size > 0) {
> pr_err("moving second stage is not supported yet\n");
> --
> 2.34.1
>
Regards,
Simon
Re: [PATCH v2 07/17] android: boot: content print is not supported for v3,v4 header version
Hi Safae, On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > Content print is not supported for version 3 and 4 of boot image header. > Thus, only print that content when v2 is used. > > Update android_print_contents() to print an error message > when trying to print boot image header version 3 or 4 content. > > Signed-off-by: Safae Ouajih > --- > boot/image-android.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > Why is that? Regards, Simon
Re: [PATCH v2 04/17] android: boot: add boot image header v3 and v4 structures
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > This adds support for v3/v4 boot image format by adding > the following structures: > > - andr_boot_img_hdr_v3 : describes boot image header > - andr_vendor_img_hdr : describes vendor boot image header > > These definitions have been copied over from the AOSP documentation at > [1] and [2] > > Boot arg sizes are taken from [3]: > commit: 35fb6262bc3f (ANDROID: Support for vendor boot) > > This also adds documentation for boot image header v3/v4 structure > that was imported from [4], file: include/bootimg/bootimg.h > commit: 8d0922bfb932 (Adding GKI signature in boot.img v4) > > Link:[1] > https://source.android.com/docs/core/architecture/bootloader/boot-image-header > Link:[2] > https://source.android.com/docs/core/architecture/bootloader/partitions/vendor-boot-partitions#vendor-boot-header > Link:[3] https://android.googlesource.com/platform/external/u-boot > Link:[4] https://android.googlesource.com/platform/system/tools/mkbootimg > > Signed-off-by: Safae Ouajih > --- > include/android_image.h | 183 +++- > 1 file changed, 182 insertions(+), 1 deletion(-) Reviewed-by: Simon Glass You might consider using the sphinx style for struct comments so you can include this header file into the docs directly.
Re: [PATCH v2 01/17] android: boot: rename andr_img_hdr -> andr_boot_img_hdr_v0
Hi Safae, On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > Android introduced boot header version 3 or 4. > The header structure change with version 3 and 4 to support > the new updates such as: > - Introducing Vendor boot image: with a vendor ramdisk > - Bootconfig feature (v4) > > To maintain support for version v0, v1 and v2 while introducing > version 3 and 4, this struct name must change to refer to the header > structure before v3. > > Signed-off-by: Safae Ouajih > --- > boot/image-android.c | 26 +- > boot/image-fdt.c | 2 +- > cmd/abootimg.c| 4 ++-- > drivers/fastboot/fb_mmc.c | 8 > include/android_image.h | 4 ++-- > include/image.h | 18 +- > 6 files changed, 31 insertions(+), 31 deletions(-) Please add full comments to the functions you change in image.h With that: Reviewed-by: Simon Glass
Re: [PATCH v2 03/17] android: boot: replace android_image_check_header
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > With the new vendor boot image introduced in versions 3 and 4 > of boot image header, the header check must be done for both boot > image and vendor boot image. Thus, android_image_check_header() is > being replaced by is_android_boot_image_header() to only refer to > boot image header check. > > Signed-off-by: Safae Ouajih > --- > boot/image-android.c | 8 > boot/image-board.c| 2 +- > cmd/abootimg.c| 4 ++-- > drivers/fastboot/fb_mmc.c | 3 +-- > include/image.h | 2 +- > 5 files changed, 9 insertions(+), 10 deletions(-) > [..] > diff --git a/include/image.h b/include/image.h > index bcb24d92de..c1594ee169 100644 > --- a/include/image.h > +++ b/include/image.h > @@ -1735,7 +1735,6 @@ int fit_image_cipher_get_algo(const void *fit, int > noffset, char **algo); > struct cipher_algo *image_get_cipher_algo(const char *full_name); > > struct andr_boot_img_hdr_v0; > -int android_image_check_header(const struct andr_boot_img_hdr_v0 *hdr); > int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int > verify, > ulong *os_data, ulong *os_len); > int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, > @@ -1750,6 +1749,7 @@ ulong android_image_get_kload(const struct > andr_boot_img_hdr_v0 *hdr); > ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr); > void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr); > bool android_image_print_dtb_contents(ulong hdr_addr); > +bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr); Please add a full comment > > /** > * board_fit_config_name_match() - Check for a matching board name > -- > 2.34.1 > With that: Reviewed-by: Simon Glass Regards, SImon
Re: [PATCH v2 02/17] android: boot: support vendor boot image in abootimg
On Thu, 26 Jan 2023 at 09:05, Safae Ouajih wrote: > > Vendor boot image is introduced in boot image header > version 3 and 4. Please check [1] for more details. > > To prepare for boot image v3/v4 support, allow the abootimg command > to store the vendor_boot image address. > > Full support for this new format will be done in a future patch. > > Link:[1] > https://source.android.com/docs/core/architecture/bootloader/partitions/vendor-boot-partitions > > Signed-off-by: Safae Ouajih > --- > cmd/abootimg.c | 18 +++--- > 1 file changed, 15 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass
[PATCH 1/1] cmd: move CONFIG_SYS_MEMTEST_START/END to cmd/Kconfig
These symbols are not specific to Keymile boards. Signed-off-by: Heinrich Schuchardt --- board/keymile/km83xx/Kconfig | 6 -- cmd/Kconfig | 8 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index f87a2e6416..014dde37cf 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -14,12 +14,6 @@ config KM_ENABLE_FULL_DM_DTS_SUPPORT select PHYLIB endmenu -config SYS_MEMTEST_START - default 0x0010 - -config SYS_MEMTEST_END - default 0x00f0 - if TARGET_KMETER1 config SYS_BOARD diff --git a/cmd/Kconfig b/cmd/Kconfig index 4fe2c75de2..bffb19924d 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -837,6 +837,14 @@ config CMD_MEMTEST if CMD_MEMTEST +config SYS_MEMTEST_START + default 0x0010 if SYS_BOARD="km83xx" + default TEXT_BASE + +config SYS_MEMTEST_END + default 0x00f0 if SYS_BOARD="km83xx" + default TEXT_BASE + config SYS_ALT_MEMTEST bool "Alternative test" help -- 2.38.1
[PATCH 1/1] cmd: fix mtest on 64 bit systems
* Use 16 digits on 64 bit systems.
* Use 64 bit patterns on 64 bit systems.
* Expect the sign bit in bit 63 on 64 bit systems.
* Adjust the formatting of a constant.
Signed-off-by: Heinrich Schuchardt
---
cmd/mem.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/cmd/mem.c b/cmd/mem.c
index 1e39348195..cf5099253e 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -818,8 +818,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr,
ulong end_addr,
*
* Returns: 0 if the test succeeds, 1 if the test fails.
*/
- pattern = (vu_long) 0x;
- anti_pattern = (vu_long) 0x;
+ pattern = (vu_long)0x;
+ anti_pattern = (vu_long)0x;
debug("%s:%d: length = 0x%.8lx\n", __func__, __LINE__, num_words);
/*
@@ -970,7 +970,7 @@ static ulong test_bitflip_comparison(volatile unsigned long
*bufa,
max = sizeof(unsigned long) * 8;
for (k = 0; k < max; k++) {
- q = 0x0001L << k;
+ q = 1UL << k;
for (j = 0; j < 8; j++) {
schedule();
q = ~q;
@@ -1009,6 +1009,7 @@ static ulong mem_test_quick(vu_long *buf, ulong
start_addr, ulong end_addr,
ulong errs = 0;
ulong incr, length;
ulong val, readback;
+ const int plen = 2 * sizeof(ulong);
/* Alternate the pattern */
incr = 1;
@@ -1020,17 +1021,17 @@ static ulong mem_test_quick(vu_long *buf, ulong
start_addr, ulong end_addr,
* the "negative" patterns and increment the "positive"
* patterns to preserve this feature.
*/
- if (pattern & 0x8000)
+ if (pattern > (ulong)LONG_MAX)
pattern = -pattern; /* complement & increment */
else
pattern = ~pattern;
}
length = (end_addr - start_addr) / sizeof(ulong);
end = buf + length;
- printf("\rPattern %08lX Writing..."
+ printf("\rPattern %0*lX Writing..."
"%12s"
"\b\b\b\b\b\b\b\b\b\b",
- pattern, "");
+ plen, pattern, "");
for (addr = buf, val = pattern; addr < end; addr++) {
schedule();
@@ -1046,10 +1047,9 @@ static ulong mem_test_quick(vu_long *buf, ulong
start_addr, ulong end_addr,
if (readback != val) {
ulong offset = addr - buf;
- printf("\nMem error @ 0x%08X: "
- "found %08lX, expected %08lX\n",
- (uint)(uintptr_t)(start_addr +
offset*sizeof(vu_long)),
- readback, val);
+ printf("\nMem error @ 0x%0*lX: found %0*lX, expected
%0*lX\n",
+ plen, start_addr + offset * sizeof(vu_long),
+ plen, readback, plen, val);
errs++;
if (ctrlc())
return -1;
--
2.38.1
Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
On 2023-01-26 23:16, Jonas Karlman wrote: > Hi Jagan, > On 2023-01-26 20:17, Jagan Teki wrote: >> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman wrote: >>> >>> On 2023-01-26 19:26, Jagan Teki wrote: Hi Simon, On Thu, 26 Jan 2023 at 23:34, Simon Glass wrote: > > Hi Jagan, > > On Thu, 26 Jan 2023 at 10:42, Jagan Teki wrote: >> >> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman wrote: >>> >>> Hi Jagan, >>> On 2023-01-26 17:51, Jagan Teki wrote: Hi Jonas, On Thu, 26 Jan 2023 at 04:17, Jonas Karlman wrote: > > Hi Jagan, > > On 2023-01-25 23:27, Jagan Teki wrote: >> This series support Rockchip RK3588. All the device tree files are >> synced from linux-next with the proper SHA1 mentioned in the commit >> messages. >> >> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so >> it is failing to load ATF entry from SPL and hang. >> >> Verified below BL31 versions, >> bl31-v1.15 >> bl31-v1.21 >> bl31-v1.22 >> bl31-v1.23 >> bl31-v1.24 >> bl31-v1.25 >> bl31-v1.26 >> >> Rever-engineered with respect to rockchip u-boot by using the same >> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but >> mainline showing the same issue. >> >> Log: >> >> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 >> +0530) >> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 >> Size=4096MB >> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 >> Size=4096MB >> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 >> Size=4096MB >> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 >> Size=4096MB >> change to F1: 528MHz >> change to F2: 1068MHz >> change to F3: 1560MHz >> change to F0: 2112MHz >> out >> >> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 >> +0530) >> Trying to boot from MMC1 >> bl31_entry: atf_entry start >> << hang >> >> >> Any information on BL31 for RK3588 please share. > > I had a similar strange booing issue with RK3568 and mainline U-Boot, > turned out to be related to all parts of ATF not being properly loaded > into PMU SRAM. > > Using my series at [1] I managed to get ATF to be fully loaded into > PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that > the segment being loaded ended up corrupted. > > The use of 512 bytes alignment of the FIT helped mitigate that issue. > Vendor U-Boot use a bounce buffer for all parts that is written into > SRAM (anything loaded outside the gd->ram_base to gd->ram_top range). > > You can also find newer bl31 at [2], up to version v1.32. > > [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891 > [2] > https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35 > Thanks for the details. I did apply this set on the master. No change in the behavior, used BL31 and ddr from [2] as well as in rkbin/master. >>> >>> I did some tests on my Radxa ROCK 3 Model B with >>> CONFIG_SPL_FIT_SIGNATURE=y >>> and it looked like it failed to read data into memory, see below. >>> >>> It also looks like the sdhci compatible is not supported by the driver. >>> Something that may need to be added to driver to properly read data? >>> >>> >>> DDR V1.09 a930779e06 typ 22/11/21-17:50:56 >>> LPDDR4X, 2112MHz >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 >>> Size=2048MB >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 >>> Size=2048MB >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 >>> Size=2048MB >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 >>> Size=2048MB >>> Manufacturer ID:0x6 >>> CH0 RX Vref:31.7%, TX Vref:21.8%,20.8% >>> CH1 RX Vref:31.7%, TX Vref:21.8%,21.8% >>> CH2 RX Vref:32.7%, TX Vref:22.8%,21.8% >>> CH3 RX Vref:32.7%, TX Vref:21.8%,20.8% >>> change to F1: 528MHz >>> change to F2: 1068MHz >>> change to F3: 1560MHz >>> change to F0: 2112MHz >>> out >>> >>> U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +) >>> Trying to boot from MMC1 >>> ## Checking hash(es) for config config_1 ... OK >>> ## Checking hash(es) for Image atf_1 ... sha256 error! >>> Bad hash value for 'hash' hash node in 'atf_1' image node >>> mmc_load_image_raw_sector: mmc block read error
DM_SERIAL is broken for Kirkwood boards
Hi all,
I ran some tests today (Pogo V4 and NSA310S boards) with the latest
master branch and saw the same behavior we've seen before. The boards
hung, and the serial console was silent after kwboot finished
transferring the u-boot image. I'm running with this DTSI patch below
(to enable dm-pre-reloc for uart0).
If I deselected DM_SERIAL then both boards booted OK with kwboot.
diff --git a/arch/arm/dts/kirkwood-nsa310s.dts
b/arch/arm/dts/kirkwood-nsa310s.dts
index 09ee76c2a2..6c5a991fde 100644
--- a/arch/arm/dts/kirkwood-nsa310s.dts
+++ b/arch/arm/dts/kirkwood-nsa310s.dts
@@ -317,3 +317,8 @@
&pcie0 {
status = "okay";
};
+
+&uart0 {
+u-boot,dm-pre-reloc;
+status = "okay";
+};
diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4.dts
b/arch/arm/dts/kirkwood-pogoplug-series-4.dts
index 5aa4669ae2..ef495d69f5 100644
--- a/arch/arm/dts/kirkwood-pogoplug-series-4.dts
+++ b/arch/arm/dts/kirkwood-pogoplug-series-4.dts
@@ -98,6 +98,7 @@
};
&uart0 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
@Michael, it would be great if you could try with your Buffalo board,
and see if you will experience the same behavior.
Thanks,
Tony
Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
Hi Jagan, On 2023-01-26 20:17, Jagan Teki wrote: > On Fri, 27 Jan 2023 at 00:33, Jonas Karlman wrote: >> >> On 2023-01-26 19:26, Jagan Teki wrote: >>> Hi Simon, >>> >>> On Thu, 26 Jan 2023 at 23:34, Simon Glass wrote: Hi Jagan, On Thu, 26 Jan 2023 at 10:42, Jagan Teki wrote: > > On Thu, 26 Jan 2023 at 22:28, Jonas Karlman wrote: >> >> Hi Jagan, >> On 2023-01-26 17:51, Jagan Teki wrote: >>> Hi Jonas, >>> >>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman wrote: Hi Jagan, On 2023-01-25 23:27, Jagan Teki wrote: > This series support Rockchip RK3588. All the device tree files are > synced from linux-next with the proper SHA1 mentioned in the commit > messages. > > Unfortunately, the BL31 from rkbin is not compatible with U-Boot so > it is failing to load ATF entry from SPL and hang. > > Verified below BL31 versions, > bl31-v1.15 > bl31-v1.21 > bl31-v1.22 > bl31-v1.23 > bl31-v1.24 > bl31-v1.25 > bl31-v1.26 > > Rever-engineered with respect to rockchip u-boot by using the same > FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but > mainline showing the same issue. > > Log: > > LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 > +0530) > channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > Size=4096MB > channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > Size=4096MB > channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > Size=4096MB > channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > Size=4096MB > change to F1: 528MHz > change to F2: 1068MHz > change to F3: 1560MHz > change to F0: 2112MHz > out > > U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 > +0530) > Trying to boot from MMC1 > bl31_entry: atf_entry start > << hang >> > > Any information on BL31 for RK3588 please share. I had a similar strange booing issue with RK3568 and mainline U-Boot, turned out to be related to all parts of ATF not being properly loaded into PMU SRAM. Using my series at [1] I managed to get ATF to be fully loaded into PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that the segment being loaded ended up corrupted. The use of 512 bytes alignment of the FIT helped mitigate that issue. Vendor U-Boot use a bounce buffer for all parts that is written into SRAM (anything loaded outside the gd->ram_base to gd->ram_top range). You can also find newer bl31 at [2], up to version v1.32. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891 [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35 Thanks for the details. I did apply this set on the master. No change >>> in the behavior, used BL31 and ddr from [2] as well as in >>> rkbin/master. >> >> I did some tests on my Radxa ROCK 3 Model B with >> CONFIG_SPL_FIT_SIGNATURE=y >> and it looked like it failed to read data into memory, see below. >> >> It also looks like the sdhci compatible is not supported by the driver. >> Something that may need to be added to driver to properly read data? >> >> >> DDR V1.09 a930779e06 typ 22/11/21-17:50:56 >> LPDDR4X, 2112MHz >> channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 >> Size=2048MB >> channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 >> Size=2048MB >> channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 >> Size=2048MB >> channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 >> Size=2048MB >> Manufacturer ID:0x6 >> CH0 RX Vref:31.7%, TX Vref:21.8%,20.8% >> CH1 RX Vref:31.7%, TX Vref:21.8%,21.8% >> CH2 RX Vref:32.7%, TX Vref:22.8%,21.8% >> CH3 RX Vref:32.7%, TX Vref:21.8%,20.8% >> change to F1: 528MHz >> change to F2: 1068MHz >> change to F3: 1560MHz >> change to F0: 2112MHz >> out >> >> U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +) >> Trying to boot from MMC1 >> ## Checking hash(es) for config config_1 ... OK >> ## Checking hash(es) for Image atf_1 ... sha256 error! >> Bad hash value for 'hash' hash node in 'atf_1' image node >> mmc_load_image_raw_sector: mmc block read error >> Trying to boot from MMC1 >> ## Checking hash(es) for config config_1 ... OK >> ## Checking hash(es) for Image atf_1 ... sha256 error! >> Bad hash value for 'has
RE: [PATCH v6 0/3] Timer support for ARM Tegra
Using your existing patches and generating a v7 to fix the T210 boards sounds like the right approach to me. Tom -Original Message- From: Svyatoslav Ryhel Sent: Thursday, January 26, 2023 11:11 AM To: Thierry Reding Cc: Tom Warren ; Rayagonda Kokatanur ; Marek Vasut ; Maxim Schwalm ; Dmitry Osipenko ; Heinrich Schuchardt ; Michal Simek ; Stefan Roese ; Eugen Hristev ; Michael Walle ; Simon Glass ; Jim Liu ; William Zhang ; Rick Chen ; Stefan Herbrechtsmeier ; Andre Przywara ; Jaehoon Chung ; u-boot@lists.denx.de Subject: Re: [PATCH v6 0/3] Timer support for ARM Tegra External email: Use caution opening links or attachments чт, 26 січ. 2023 р. о 19:58 Thierry Reding пише: > > On Thu, Jan 26, 2023 at 07:12:34PM +0200, Svyatoslav Ryhel wrote: > > I may implement changes of Thierry Reding in a proper form as a > > separate patch or include in existing (depends on his choice). > > I think it's ultimately better if this is properly integrated into the > series because the series would remain bisectible. > > If the existing series is applied as-is, we have a few patches in the > middle during which Tegra210 is unusable. So if we ever have to track > down a regression that might be problematic. > > It's not a big deal since we've rarely had regressions in U-Boot. It's > ultimately up to Tom to decide how he wants to handle this. > > If you send out another series, can you please add me on Cc so I don't > miss it? > > Thanks, > Thierry Thierry Reding thanks for your clarification. If you and Tom Warren are ok, I will modify existing patches and send them as v7 in final form. Then you can check if T210 works as intended and if everything is correct. We can apply it. P. S. You may be sure that I will include you in all my patches for u-boot since it is explicitly hard to find a person with boards you own. Best Regards. Svyatoslav R. > > The only thing I need to know is if ALL known T210 devices use > > 19.2MHz as calibration clock for timer? > > > > Best regards. > > Svyatoslav R. > > > > чт, 26 січ. 2023 р. о 18:50 Tom Warren пише: > > > > > > Thanks for testing T210/T186, Thierry. > > > > > > I had Svyatoslav's patches ready to go for a PR yesterday, so I'll need > > > either a patch from you for the T210 changes that I can apply on top of > > > his, or I'll need Svyatoslav to adopt your changes as a 4th patch in his > > > series. Once I have that and can pass buildman OK, I'll be ready to send > > > a PR to TomR. > > > > > > Tom > > > > > > -Original Message- > > > From: Thierry Reding > > > Sent: Thursday, January 26, 2023 4:41 AM > > > To: Svyatoslav Ryhel > > > Cc: Rayagonda Kokatanur ; Tom > > > Warren ; Marek Vasut ; Maxim > > > Schwalm ; Dmitry Osipenko > > > ; Heinrich Schuchardt ; > > > Michal Simek ; Stefan Roese ; > > > Eugen Hristev ; Michael Walle > > > ; Simon Glass ; Jim Liu > > > ; William Zhang > > > ; Rick Chen ; > > > Stefan Herbrechtsmeier ; > > > Andre Przywara ; Jaehoon Chung > > > ; u-boot@lists.denx.de > > > Subject: Re: [PATCH v6 0/3] Timer support for ARM Tegra > > > > > > On Thu, Jan 26, 2023 at 11:34:59AM +0100, Thierry Reding wrote: > > > > On Wed, Jan 25, 2023 at 05:41:08PM +0100, Thierry Reding wrote: > > > > > On Tue, Jan 24, 2023 at 08:57:48AM +0200, Svyatoslav Ryhel wrote: > > > > > > - ARM: tegra: remap clock_osc_freq for all Tegra family Enum > > > > > > clock_osc_freq was designed to use only with T20. > > > > > > This patch remaps it to use additional frequencies, added in > > > > > > T30+ SoC while maintaining backwards compatibility with T20. > > > > > > > > > > > > - drivers: timer: add timer driver for ARMv7 based Tegra > > > > > > devices Add timer support for T20/T30/T114 and T124 based devices. > > > > > > Driver is based on DM, has device tree support and can be > > > > > > used on SPL and early boot stage. > > > > > > > > > > > > - ARM: tegra: include timer as default option Enable TIMER > > > > > > as default option for all Tegra devices and enable > > > > > > TEGRA_TIMER for TEGRA_ARMV7_COMMON. Additionally enable > > > > > > SPL_TIMER if build as SPL part and drop deprecated configs from > > > > > > common header. > > > > > > > > > > > > P. S. I have no arm64 Tegra and according to comment in > > > > > > tegra-common.h Use the Tegra US timer on ARMv7, but the > > > > > > architected timer on ARMv8. > > > > > > > > > > > > Svyatoslav Ryhel (3): > > > > > > ARM: tegra: remap clock_osc_freq for all Tegra family > > > > > > drivers: timer: add timer driver for ARMv7 based Tegra devices > > > > > > ARM: tegra: include timer as default option > > > > > > > > > > This causes a regression on Tegra210 (Jetson TX1). I'm trying > > > > > to investigate, but it's complicated by the fact that I'm not > > > > > getting out any debug prints, so I suspect the issue is happening > > > > > quite early. > > > > > > > > Alright, I managed to make this work on Tegra210 using the > > > > following pat
Re: CONFIG_IS_ENABLED vs IS_ENABLED
On Thu, Jan 26, 2023 at 02:29:53PM -0700, Simon Glass wrote:
> Hi Tom,
>
> On Thu, 26 Jan 2023 at 11:16, Tom Rini wrote:
> >
> > On Thu, Jan 26, 2023 at 11:04:21AM -0700, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Thu, 26 Jan 2023 at 10:21, Tom Rini wrote:
> > > >
> > > > On Tue, Jan 24, 2023 at 06:36:00PM -0700, Simon Glass wrote:
> > > > > Hi Troy,
> > > > >
> > > > > On Tue, 24 Jan 2023 at 16:31, Troy Kisky
> > > > > wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Troy Kisky
> > > > > > Sent: Tuesday, January 24, 2023 2:52 PM
> > > > > > To: u-boot@lists.denx.de ; sba...@denx.de
> > > > > > ; tr...@konsulko.com ;
> > > > > > feste...@gmail.com
> > > > > > Cc: s...@chromium.org ; ma...@denx.de
> > > > > >
> > > > > > Subject: CONFIG_IS_ENABLED vs IS_ENABLED
> > > > > >
> > > > > > Hi Guys
> > > > > >
> > > > > > In a recent debugging session, I stumbled across this line
> > > > > > drivers/mmc/mmc.c: if (CONFIG_IS_ENABLED(MMC_QUIRKS) &&
> > > > > > mmc->quirks & quirk)
> > > > > >
> > > > > > which prevents retries in SPL code, and was causing booting from an
> > > > > > SD card to fail.
> > > > > > So I wrote a little script to print uses of
> > > > > > CONFIG_IS_ENABLED(x) which might need to be
> > > > > > IS_ENABLED(CONFIG_x) like the above one.
> > > > > >
> > > > > > Here it is if you want to try it out.
> > > > > >
> > > > > > git grep CONFIG_IS_ENABLED|sed -n -e
> > > > > > "s/\(CONFIG_IS_ENABLED([0-9a-zA-Z_]*)\)/\n\1\n/gp"| \
> > > > > > sed -n -r "s/CONFIG_IS_ENABLED\(([0-9a-zA-Z_]+)\)/\1/p" |sort
> > > > > > -u|xargs -I {} \
> > > > > > sh -c "git grep -E 'config [ST]PL_{}' | grep -q -E -w '[ST]PL_{}'
> > > > > > || git grep 'CONFIG_IS_ENABLED({})'"
> > > > > >
> > > > > > It prints CONFIG_IS_ENABLED(x) uses where there is no SPL_x or
> > > > > > TPL_x.
> > > > > >
> > > > > > BR
> > > > > > Troy
> > > > > >
> > > > > > ___
> > > > > > And here is the opposite check
> > > > > >
> > > > > > git grep -w IS_ENABLED|sed -n -e
> > > > > > "s/\(IS_ENABLED(CONFIG_[0-9a-zA-Z_]*)\)/\n\1\n/gp"| \
> > > > > > sed -n -r "s/IS_ENABLED\(CONFIG_([0-9a-zA-Z_]+)\)/\1/p" |sort
> > > > > > -u|xargs -I {} \
> > > > > > sh -c "git grep -E 'config [ST]PL_{}' | grep -q -E -w '[ST]PL_{}'
> > > > > > && git grep 'IS_ENABLED(CONFIG_{})'"
> > > > > >
> > > > > >
> > > > > > It prints uses of IS_ENABLED(CONFIG_x) where CONFIG_SPL_x exists.
> > > > >
> > > > > Thank you for that. We definitely have quite a few of these.
> > > > >
> > > > > By a great coincidence I updated moveconfig.py to do something a
> > > > > little like that:.
> > > > >
> > > > > https://patchwork.ozlabs.org/project/uboot/patch/20230123220031.3540724-2-...@chromium.org/
> > > >
> > > > I think this also shows that we might really want to just drop the
> > > > checkpatch.pl note about IS_ENABLED / CONFIG_IS_ENABLED, it's getting
> > > > used in a lot of wrong places where it's not helpful. It's not the root
> > > > cause here (where a compile time check that allows for the rest of the
> > > > code to be statically checked still is OK), but it's part of the
> > > > problem.
> > >
> > > Firstly, we want to drop the use of #ifdef so what should we say instead?
> >
> > I'm not sure that dropping #ifdef in and of itself is a good goal.
> > #if IS_ENABLED(CONFIG_FOO)
> > does not read better
> > #ifdef CONFIG_FOO
>
> So far in my prototype I have implemented
>
> #if CONFIG(FOO)
>
> and
>
> if (CONFIG(FOO))
>
> which replaces direct use of CONFIG_FOO and also
> CONFIG_IS_ENABLED(FOO). We could ban use of CONFIG_FOO easily enough.
I'm not convinced #if CONFIG(FOO) is better, but OK.
> > And we have a lot of cases of the former that I'm not sure can
> > logically or helpfully be replaced with
> > if (IS_ENABLED(CONFIG_FOO))
> > either for functional / legibility reasons (ie it doesn't read better
> > and just getting static analysis isn't a great reasons, more indent
> > makes the code harder to follow) or isn't possible because things like:
> > #ifdef CONFIG_FOO
> > int i = CONFIG_BAZ;
> > ...
> > #endif
> >
> > Can't be replaced with if (IS_ENABLED(CONFIG_FOO)) { ... } when
> > CONFIG_BAZ is only ever asked when CONFIG_FOO is enabled. And we can't
> > define CONFIG_BAZ to 0 if not set (that leads back to introducing
> > CONFIG things being defined).
>
> We have IF_ENABLED_INT() so can do things like that
And could come up wit IF_ENABLED_STRING() I suppose. But I'm still not
sure it'll read better / more clearly.
> > > Secondly, I think we should fix all this by splitting the config,
> > > along the lines of my old series [1]. I hit similar problems to Troy
> > > and have modified moveconfig.py to detect these (hence my recent
> > > series [2]). I will see if I can get some sort of series out by
> > > Monday. I had something pretty close(TM) but it failed on a few qemu
> > > tests [3]
> >
> > I don't disagree with seeing what things loo
Re: CONFIG_IS_ENABLED vs IS_ENABLED
Hi Tom,
On Thu, 26 Jan 2023 at 11:16, Tom Rini wrote:
>
> On Thu, Jan 26, 2023 at 11:04:21AM -0700, Simon Glass wrote:
> > Hi Tom,
> >
> > On Thu, 26 Jan 2023 at 10:21, Tom Rini wrote:
> > >
> > > On Tue, Jan 24, 2023 at 06:36:00PM -0700, Simon Glass wrote:
> > > > Hi Troy,
> > > >
> > > > On Tue, 24 Jan 2023 at 16:31, Troy Kisky
> > > > wrote:
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > From: Troy Kisky
> > > > > Sent: Tuesday, January 24, 2023 2:52 PM
> > > > > To: u-boot@lists.denx.de ; sba...@denx.de
> > > > > ; tr...@konsulko.com ;
> > > > > feste...@gmail.com
> > > > > Cc: s...@chromium.org ; ma...@denx.de
> > > > >
> > > > > Subject: CONFIG_IS_ENABLED vs IS_ENABLED
> > > > >
> > > > > Hi Guys
> > > > >
> > > > > In a recent debugging session, I stumbled across this line
> > > > > drivers/mmc/mmc.c: if (CONFIG_IS_ENABLED(MMC_QUIRKS) &&
> > > > > mmc->quirks & quirk)
> > > > >
> > > > > which prevents retries in SPL code, and was causing booting from an
> > > > > SD card to fail.
> > > > > So I wrote a little script to print uses of
> > > > > CONFIG_IS_ENABLED(x) which might need to be
> > > > > IS_ENABLED(CONFIG_x) like the above one.
> > > > >
> > > > > Here it is if you want to try it out.
> > > > >
> > > > > git grep CONFIG_IS_ENABLED|sed -n -e
> > > > > "s/\(CONFIG_IS_ENABLED([0-9a-zA-Z_]*)\)/\n\1\n/gp"| \
> > > > > sed -n -r "s/CONFIG_IS_ENABLED\(([0-9a-zA-Z_]+)\)/\1/p" |sort
> > > > > -u|xargs -I {} \
> > > > > sh -c "git grep -E 'config [ST]PL_{}' | grep -q -E -w '[ST]PL_{}' ||
> > > > > git grep 'CONFIG_IS_ENABLED({})'"
> > > > >
> > > > > It prints CONFIG_IS_ENABLED(x) uses where there is no SPL_x or TPL_x.
> > > > >
> > > > > BR
> > > > > Troy
> > > > >
> > > > > ___
> > > > > And here is the opposite check
> > > > >
> > > > > git grep -w IS_ENABLED|sed -n -e
> > > > > "s/\(IS_ENABLED(CONFIG_[0-9a-zA-Z_]*)\)/\n\1\n/gp"| \
> > > > > sed -n -r "s/IS_ENABLED\(CONFIG_([0-9a-zA-Z_]+)\)/\1/p" |sort
> > > > > -u|xargs -I {} \
> > > > > sh -c "git grep -E 'config [ST]PL_{}' | grep -q -E -w '[ST]PL_{}' &&
> > > > > git grep 'IS_ENABLED(CONFIG_{})'"
> > > > >
> > > > >
> > > > > It prints uses of IS_ENABLED(CONFIG_x) where CONFIG_SPL_x exists.
> > > >
> > > > Thank you for that. We definitely have quite a few of these.
> > > >
> > > > By a great coincidence I updated moveconfig.py to do something a
> > > > little like that:.
> > > >
> > > > https://patchwork.ozlabs.org/project/uboot/patch/20230123220031.3540724-2-...@chromium.org/
> > >
> > > I think this also shows that we might really want to just drop the
> > > checkpatch.pl note about IS_ENABLED / CONFIG_IS_ENABLED, it's getting
> > > used in a lot of wrong places where it's not helpful. It's not the root
> > > cause here (where a compile time check that allows for the rest of the
> > > code to be statically checked still is OK), but it's part of the
> > > problem.
> >
> > Firstly, we want to drop the use of #ifdef so what should we say instead?
>
> I'm not sure that dropping #ifdef in and of itself is a good goal.
> #if IS_ENABLED(CONFIG_FOO)
> does not read better
> #ifdef CONFIG_FOO
So far in my prototype I have implemented
#if CONFIG(FOO)
and
if (CONFIG(FOO))
which replaces direct use of CONFIG_FOO and also
CONFIG_IS_ENABLED(FOO). We could ban use of CONFIG_FOO easily enough.
>
> And we have a lot of cases of the former that I'm not sure can
> logically or helpfully be replaced with
> if (IS_ENABLED(CONFIG_FOO))
> either for functional / legibility reasons (ie it doesn't read better
> and just getting static analysis isn't a great reasons, more indent
> makes the code harder to follow) or isn't possible because things like:
> #ifdef CONFIG_FOO
> int i = CONFIG_BAZ;
> ...
> #endif
>
> Can't be replaced with if (IS_ENABLED(CONFIG_FOO)) { ... } when
> CONFIG_BAZ is only ever asked when CONFIG_FOO is enabled. And we can't
> define CONFIG_BAZ to 0 if not set (that leads back to introducing
> CONFIG things being defined).
We have IF_ENABLED_INT() so can do things like that
>
> > Secondly, I think we should fix all this by splitting the config,
> > along the lines of my old series [1]. I hit similar problems to Troy
> > and have modified moveconfig.py to detect these (hence my recent
> > series [2]). I will see if I can get some sort of series out by
> > Monday. I had something pretty close(TM) but it failed on a few qemu
> > tests [3]
>
> I don't disagree with seeing what things look like with a "split" config
> again, but I think that fundamentally Yamada-san was right way back, and
> we really need to move towards separate config files for each stage and
> then combine them when applicable.
Well let's see what you think once I get this next version of the series out.
> That's also not easy, but I'm also
> not sure how to deal with the cases where we intentionally have
> CONFIG_FOO=n CONFIG_SPL_FOO=y without doing what we're doing today, at
> some l
[PATCH 21/35] clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.1.7
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux
6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7796-cpg-mssr.c | 33 +-
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index e318719033b..87b8c083522 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -1,13 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Renesas R8A7796 CPG MSSR driver
+ * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
+ * Reset
*
- * Copyright (C) 2017-2018 Marek Vasut
- *
- * Based on the following driver from Linux kernel:
- * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
- *
- * Copyright (C) 2016 Glider bvba
+ * Copyright (C) 2016-2019 Glider bvba
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
@@ -75,12 +72,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
- DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
-CLK_RPCSRC),
- DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-R8A7796_CLK_RPC),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -108,10 +101,17 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
- DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
+ DEF_GEN3_SDH("sd0h",R8A7796_CLK_SD0H, CLK_SDSRC,0x074),
+ DEF_GEN3_SDH("sd1h",R8A7796_CLK_SD1H, CLK_SDSRC,0x078),
+ DEF_GEN3_SDH("sd2h",R8A7796_CLK_SD2H, CLK_SDSRC,0x268),
+ DEF_GEN3_SDH("sd3h",R8A7796_CLK_SD3H, CLK_SDSRC,0x26c),
+ DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074),
+ DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078),
+ DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
+ DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
+
+ DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A7796_CLK_RPC),
DEF_FIXED("cl", R8A7796_CLK_CL,CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A7796_CLK_CR,CLK_PLL1_DIV4, 2, 1),
@@ -209,6 +209,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
+ DEF_MOD("mlp", 802, R8A7796_CLK_S2D1),
DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
--
2.39.0
[PATCH 09/13] clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
From: Hai Pham
Introduce new helper function to handle clock type that uses
clk_div_table struct. Based vaguely on Linux code. Make use
of clk_div_table in RPC clocks handling.
The E3/D3 RPCSRC need to be handled differently and will be addressed in
subsequence patch.
Based on Linux commit db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC
clocks") by Sergei Shtylyov.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
Marek: - Squash patches to avoid adding unused code:
clk: renesas: Make use of clk_div_table in RPC clocks handling
clk: renesas: Introduce rcar_clk_get_rate64_div_table function
- Move the new code to the beginning of clk-rcar-gen3 to avoid
tables mixed with code
- Use rcar_ prefix for get_table_div function
- Get rid of custom macros, use GENMASK. Use custom field_get
implementation as the generic FIELD_GET does not support
constant mask and u32_get_bits requires higher optimization level
- Pass in the register bit mask instead of width/shift combination
- Turn rcar_clk_get_rate64_div_table into s64, as it can return -EINVAL
---
drivers/clk/renesas/clk-rcar-gen3.c | 95 ++---
drivers/clk/renesas/rcar-gen3-cpg.h | 3 +
2 files changed, 64 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 3df6aaabf0f..84bd7fe8b00 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -33,10 +34,8 @@
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
-#define CPG_RPC_PREDIV_MASK0x3
-#define CPG_RPC_PREDIV_OFFSET 3
-#define CPG_RPC_POSTDIV_MASK 0x7
-#define CPG_RPC_POSTDIV_OFFSET 0
+/* Non-constant mask variant of FIELD_GET */
+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
/*
* SDn Clock
@@ -85,6 +84,45 @@ static const struct clk_div_table cpg_sd_div_table[] = {
CPG_SD_DIV_TABLE_DATA(1,0,4, 0, 32),
};
+static const struct clk_div_table cpg_rpcsrc_div_table[] = {
+ { 2, 5 }, { 3, 6 }, { 0, 0 },
+};
+
+static const struct clk_div_table cpg_rpc_div_table[] = {
+ { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
+};
+
+static unsigned int rcar_clk_get_table_div(const struct clk_div_table *table,
+ const u32 value)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val == value)
+ return clkt->div;
+ return 0;
+}
+
+static __always_inline s64
+rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate,
+ void __iomem *reg, const u32 mask,
+ const struct clk_div_table *table, char *name)
+{
+ u32 value, div;
+ u64 rate;
+
+ value = field_get(mask, readl(reg));
+ div = rcar_clk_get_table_div(table, value);
+ if (!div)
+ return -EINVAL;
+
+ rate = parent_rate / div;
+ debug("%s[%i] %s clk: parent=%i div=%u => rate=%llu\n",
+ __func__, __LINE__, name, parent, div, rate);
+
+ return rate;
+}
+
static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
struct cpg_mssr_info *info, struct clk *parent)
{
@@ -183,7 +221,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
const struct cpg_core_clk *core;
const struct rcar_gen3_cpg_pll_config *pll_config =
priv->cpg_pll_config;
- u32 value, div, prediv, postdiv;
+ u32 value, div;
u64 rate = 0;
int i, ret;
@@ -313,40 +351,29 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return -EINVAL;
+ case CLK_TYPE_GEN3_RPCSRC:
+ return rcar_clk_get_rate64_div_table(core->parent,
+
gen3_clk_get_rate64(&parent),
+priv->base + CPG_RPCCKCR,
+CPG_RPCCKCR_DIV_POST_MASK,
+cpg_rpcsrc_div_table,
"RPCSRC");
+
case CLK_TYPE_GEN3_RPC:
- case CLK_TYPE_GEN3_RPCD2:
case CLK_TYPE_GEN4_RPC:
- case CLK_TYPE_GEN4_RPCD2:
- rate = gen3_clk_get_rate64(&parent);
-
- value = readl(priv->base + CPG_RPCCKCR);
-
- prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
-CPG_RPC_PREDIV_MASK;
- if (prediv == 2)
- rate /= 5;
- else if (prediv == 3)
- rate /= 6;
- else
- return -EINVAL;
-
- postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
[PATCH 13/13] clk: renesas: rcar-gen3: Factor out CPG library
From: Hai Pham
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock and RPC clock handling and hook them to the generic Gen3
CPG driver so we have an equal state.
Based on Linux commit [1] and [2] by Wolfram Sang
[1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library")
[2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to
the library")
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
Marek: - Add rcar_clk_* prefix to all functions
- Rebase on changes to
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
- Use u32_encode_bits/GENMASK bitfield ops
---
drivers/clk/renesas/Kconfig | 4 +
drivers/clk/renesas/Makefile| 1 +
drivers/clk/renesas/clk-rcar-gen3.c | 145
drivers/clk/renesas/rcar-cpg-lib.c | 169
drivers/clk/renesas/rcar-cpg-lib.h | 33 ++
5 files changed, 230 insertions(+), 122 deletions(-)
create mode 100644 drivers/clk/renesas/rcar-cpg-lib.c
create mode 100644 drivers/clk/renesas/rcar-cpg-lib.h
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index a538e7e7aa0..1686410d6d3 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -4,6 +4,9 @@ config CLK_RENESAS
help
Enable support for clock present on Renesas RCar SoCs.
+config CLK_RCAR_CPG_LIB
+ bool "CPG/MSSR library functions"
+
config CLK_RCAR_GEN2
bool "Renesas RCar Gen2 clock driver"
def_bool y if RCAR_32
@@ -45,6 +48,7 @@ config CLK_RCAR_GEN3
bool "Renesas RCar Gen3 clock driver"
def_bool y if RCAR_GEN3
depends on CLK_RENESAS
+ select CLK_RCAR_CPG_LIB
help
Enable this to support the clocks on Renesas RCar Gen3 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index df6bbc20bc3..8f82a7aa3e0 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
+obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index f8a23623223..d778db6569d 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -29,34 +29,16 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
+#include "rcar-cpg-lib.h"
#define CPG_PLL0CR 0x00d8
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
-#define SDnSRCFC_SHIFT 2
-#define STPnHCK_TABLE (CPG_SDCKCR_STPnHCK >> SDnSRCFC_SHIFT)
-
-/* Non-constant mask variant of FIELD_GET/FIELD_PREP */
-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
-
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
{ 2, 5 }, { 3, 6 }, { 0, 0 },
};
-static const struct clk_div_table cpg_rpc_div_table[] = {
- { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
-};
-
-static const struct clk_div_table cpg_sdh_div_table[] = {
- { 0, 1 }, { 1, 2 }, { STPnHCK_TABLE | 2, 4 }, { STPnHCK_TABLE | 3, 8 },
- { STPnHCK_TABLE | 4, 16 }, { 0, 0 },
-};
-
-static const struct clk_div_table cpg_sd_div_table[] = {
- { 0, 2 }, { 1, 4 }, { 0, 0 },
-};
-
static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
@@ -69,48 +51,6 @@ static const struct clk_div_table
r8a77970_cpg_sd0_div_table[] = {
{ 0, 0 },
};
-static unsigned int rcar_clk_get_table_div(const struct clk_div_table *table,
- const u32 value)
-{
- const struct clk_div_table *clkt;
-
- for (clkt = table; clkt->div; clkt++)
- if (clkt->val == value)
- return clkt->div;
- return 0;
-}
-
-static int rcar_clk_get_table_val(const struct clk_div_table *table,
- unsigned int div)
-{
- const struct clk_div_table *clkt;
-
- for (clkt = table; clkt->div; clkt++)
- if (clkt->div == div)
- return clkt->val;
- return -EINVAL;
-}
-
-static __always_inline s64
-rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate,
- void __iomem *reg, const u32 mask,
- const struct clk_div_table *table, char *name)
-{
- u32 value, div;
- u64 rate;
-
- value = field_get(mask, readl(reg));
- div = rcar_clk_get_table_div(table, value);
- if (!div)
- return -EINVAL;
-
- rate = parent_rate / div;
- debug("%s[%i]
Re: Pull request: u-boot-spi/master
On Thu, Jan 26, 2023 at 11:22:30PM +0530, Jagan Teki wrote: > Hi Tom, > > Please pull this PR. > > Summary: > - fix return code of sf command (Heinrich) > - fix register reads in STIG Mode (Dhruva) > - Infineon s25fs256t support (Takahiro) > > CI: > https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/14893 > > thanks, > Jagan. > > The following changes since commit 17e8e58fe62c019b2cc26af221b6defc3368229f: > > Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi (2023-01-24 > 21:07:01 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-spi master > > for you to fetch changes up to 87a6d86571268be4e354fe030c53745a54f4ed8e: > > mtd: spi-nor: Add support for Infineon s25fs256t (2023-01-26 21:07:45 +0530) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH 08/13] clk: renesas: Convert Gen2/Gen3 clock tables to clk-provider struct clk_div_table
Replace custom local structure with matching one from clk-provider.h .
No functional change.
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen2.c | 6 +-
drivers/clk/renesas/clk-rcar-gen3.c | 8 ++--
2 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c
b/drivers/clk/renesas/clk-rcar-gen2.c
index 3a68c5ad0eb..850d6411190 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
@@ -26,11 +27,6 @@
#define CPG_PLL0CR 0x00d8
#define CPG_SDCKCR 0x0074
-struct clk_div_table {
- u8 val;
- u8 div;
-};
-
/* SDHI divisors */
static const struct clk_div_table cpg_sdh_div_table[] = {
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index dd61fe0c7cd..3df6aaabf0f 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include
@@ -55,11 +56,6 @@
.div = (sd_div), \
}
-struct sd_div_table {
- u32 val;
- unsigned int div;
-};
-
/* SDn divider
* sd_srcfc sd_fc div
* stp_hck stp_ck(div) (div) = sd_srcfc x sd_fc
@@ -75,7 +71,7 @@ struct sd_div_table {
* 1 0 3 (8) 0 (2) 16
* 1 0 4 (16) 0 (2) 32
*/
-static const struct sd_div_table cpg_sd_div_table[] = {
+static const struct clk_div_table cpg_sd_div_table[] = {
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
CPG_SD_DIV_TABLE_DATA(0,0,0, 1,4),
CPG_SD_DIV_TABLE_DATA(0,0,1, 1,8),
--
2.39.0
[PATCH 04/13] mmc: renesas-sdhi: Adjust HS400 calibration offsets for M3-W r1.3
From: Hai Pham
Still uses 0x3 for now, adjust the offset value to TMPPORT3 accordingly
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/mmc/renesas-sdhi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index f9155bc44de..90e8aaddb05 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -899,7 +899,7 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() > 2)) {
priv->adjust_hs400_enable = true;
- priv->adjust_hs400_offset = 0;
+ priv->adjust_hs400_offset = 3;
priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
priv->adjust_hs400_calib_table =
r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)];
--
2.39.0
[PATCH 06/13] mmc: renesas-sdhi: Drop R-Car H3 ES3.0 HS400 calibration table
From: Hai Pham
It is unnecessary, so clean it up.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut # update commit
message, mention ES3.0
---
drivers/mmc/renesas-sdhi.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 95db8aca931..f85ced26ed8 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -71,13 +71,6 @@
#define CALIB_TABLE_MAX(RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
-static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
- { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
-15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
- { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
-16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
-};
-
static const u8 r8a7796_rev13_calib_table[2][CALIB_TABLE_MAX] = {
{ 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
@@ -886,15 +879,6 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
- /* H3 ES3.0 can use HS400 with manual adjustment */
- if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
- (rmobile_get_cpu_rev_integer() >= 3)) {
- priv->adjust_hs400_enable = true;
- priv->adjust_hs400_offset = 0;
- priv->adjust_hs400_calib_table =
- r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
- }
-
/* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
--
2.39.0
[PATCH 01/13] mmc: renesas-sdhi: R-Car M3 r1.3 also uses 4 tuning taps
From: Hai Pham Early ES revisions of M3-W SoCs requires 4-tap HS400. Reflect the status from datasheet. Reviewed-by: Marek Vasut Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- drivers/mmc/renesas-sdhi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 9ad92648a34..9f8a272d03d 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -934,12 +934,12 @@ static void renesas_sdhi_filter_caps(struct udevice *dev) r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)]; } - /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */ + /* H3 ES1.x, ES2.0 and M3W ES1.[0123] uses 4 tuning taps */ if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && (rmobile_get_cpu_rev_integer() <= 2)) || ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() <= 2))) + (rmobile_get_cpu_rev_fraction() <= 3))) priv->nrtaps = 4; else priv->nrtaps = 8; -- 2.39.0
[PATCH 05/13] mmc: renesas-sdhi: Add R8A77961 M3-W+ support
From: Hai Pham
Support R8A77961 M3-W+ SoC.
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/mmc/renesas-sdhi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 90e8aaddb05..95db8aca931 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -836,6 +836,7 @@ static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
{ .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
+ { .compatible = "renesas,sdhi-r8a77961", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
@@ -905,6 +906,11 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
+ /* M3W+ bad taps */
+ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ (rmobile_get_cpu_rev_integer() == 3))
+ priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
+
/* M3N can use HS400 with manual adjustment */
if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
priv->adjust_hs400_enable = true;
--
2.39.0
[PATCH 03/13] mmc: renesas-sdhi: Adjust HS400 calibration tables
From: Hai Pham
Adjust HS400 calibration tables based on Linux settings
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/mmc/renesas-sdhi.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 3ec0444700e..f9155bc44de 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -79,24 +79,24 @@ static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
};
static const u8 r8a7796_rev13_calib_table[2][CALIB_TABLE_MAX] = {
- { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
-11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
- { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
-13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
+ { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
+16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
+ { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
+12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
};
static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
- { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
-16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
- { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
-16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
+ { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
+17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
+ { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
};
static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
- { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
-12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
+ { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
+11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
};
static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
--
2.39.0
[PATCH 07/13] mmc: renesas-sdhi: Flag non-standard SDnH handling for V3M
From: Hai Pham
V3M handles SDnH differently than other Gen3 SoCs, so let's add a
separate entry for that. This will allow better SDnH handling in the
future.
Based on Linux commit 627151b4966f ("mmc: renesas_sdhi: Flag
non-standard SDnH handling for V3M") by Wolfram Sang
Signed-off-by: Hai Pham
---
drivers/mmc/renesas-sdhi.c | 6 ++
drivers/mmc/tmio-common.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index f85ced26ed8..f30d7847bf2 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -930,6 +930,12 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
else
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
+
+ /* V3M handles SD0H differently than other Gen3 SoCs */
+ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970)
+ priv->needs_clkh_fallback = true;
+ else
+ priv->needs_clkh_fallback = false;
}
static int renesas_sdhi_probe(struct udevice *dev)
diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h
index 59d5a0e22e9..e517ed978bf 100644
--- a/drivers/mmc/tmio-common.h
+++ b/drivers/mmc/tmio-common.h
@@ -151,6 +151,7 @@ struct tmio_sd_priv {
u8 hs400_bad_tap;
const u8*adjust_hs400_calib_table;
u32 quirks;
+ boolneeds_clkh_fallback;
#endif
ulong (*clk_get_rate)(struct tmio_sd_priv *);
};
--
2.39.0
[PATCH 10/13] clk: renesas: Handle E3/D3 RPCSRC clock
From: Hai Pham
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent. Add a new
macro to describe it, reusing the existing clock type for R-Car E3.
As both E3/D3 RPCSRC clock divider are different from the rest of R-Car
Gen3, keep the original implementation from Linux.
Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC
clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add
RPC clocks") by Geert Uytterhoeven.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut # Add D3 tweaks
---
drivers/clk/renesas/clk-rcar-gen3.c | 31 +
1 file changed, 31 insertions(+)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 84bd7fe8b00..aea8b1e8390 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -358,6 +358,37 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
CPG_RPCCKCR_DIV_POST_MASK,
cpg_rpcsrc_div_table,
"RPCSRC");
+ case CLK_TYPE_GEN3_D3_RPCSRC:
+ case CLK_TYPE_GEN3_E3_RPCSRC:
+ /*
+* Register RPCSRC as fixed factor clock based on the
+* MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
+* which has been set prior to booting the kernel.
+*/
+ value = (readl(priv->base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
+
+ switch (value) {
+ case 0:
+ div = 5;
+ break;
+ case 1:
+ div = 3;
+ break;
+ case 2:
+ div = core->div;
+ break;
+ case 3:
+ default:
+ div = 2;
+ break;
+ }
+
+ rate = gen3_clk_get_rate64(&parent) / div;
+ debug("%s[%i] E3/D3 RPCSRC clk: parent=%i div=%u =>
rate=%llu\n",
+ __func__, __LINE__, (core->parent >> 16) & 0x, div,
rate);
+
+ return rate;
+
case CLK_TYPE_GEN3_RPC:
case CLK_TYPE_GEN4_RPC:
return rcar_clk_get_rate64_div_table(core->parent,
--
2.39.0
[PATCH 12/13] clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI
From: Hai Pham
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. Hence, new clock types are introduced
respectively.
Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0
clocks for SDHI") by Sergei Shtylyov
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
- Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types
which is now part of common clock types in rcar-gen3-cpg.h instead
---
drivers/clk/renesas/clk-rcar-gen3.c | 39 +
drivers/clk/renesas/r8a77970-cpg-mssr.c | 5
drivers/clk/renesas/rcar-gen3-cpg.h | 5
3 files changed, 44 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 53f16dfb1e0..f8a23623223 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -57,6 +57,18 @@ static const struct clk_div_table cpg_sd_div_table[] = {
{ 0, 2 }, { 1, 4 }, { 0, 0 },
};
+static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
+ { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
+ { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
+ { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
+};
+
+static const struct clk_div_table r8a77970_cpg_sd0_div_table[] = {
+ { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
+ { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
+ { 0, 0 },
+};
+
static unsigned int rcar_clk_get_table_div(const struct clk_div_table *table,
const u32 value)
{
@@ -205,6 +217,19 @@ static int gen3_clk_setup_sdif_div(struct clk *clk, ulong
rate)
debug("%s[%i] SD clk: parent=%i offset=%x div=%u rate=%lu =>
val=%u\n",
__func__, __LINE__, core->parent, core->offset, div,
rate, value);
break;
+
+ case CLK_TYPE_R8A77970_SD0:
+ div = gen3_clk_get_rate64(&grandparent) / rate;
+ value = rcar_clk_get_table_val(cpg_sd_div_table, div);
+ if (!value)
+ return -EINVAL;
+
+ clrsetbits_le32(priv->base + core->offset,
+ GENMASK(7, 4), value << 4);
+
+ debug("%s[%i] SD clk: parent=%i offset=%x div=%u rate=%lu =>
val=%u\n",
+ __func__, __LINE__, core->parent, core->offset, div,
rate, value);
+ break;
}
return 0;
@@ -358,6 +383,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
GENMASK(9, 5),
cpg_sdh_div_table, "SDH");
+ case CLK_TYPE_R8A77970_SD0H:
+ return rcar_clk_get_rate64_div_table(core->parent,
+
gen3_clk_get_rate64(&parent),
+priv->base + core->offset,
+CPG_SDCKCR_SDHFC_MASK,
+
r8a77970_cpg_sd0h_div_table, "SDH");
+
case CLK_TYPE_GEN3_SD:
fallthrough;
case CLK_TYPE_GEN4_SD:
@@ -367,6 +399,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
CPG_SDCKCR_FC_MASK,
cpg_sd_div_table, "SD");
+ case CLK_TYPE_R8A77970_SD0:
+ return rcar_clk_get_rate64_div_table(core->parent,
+
gen3_clk_get_rate64(&parent),
+priv->base + core->offset,
+CPG_SDCKCR_SD0FC_MASK,
+
r8a77970_cpg_sd0_div_table, "SD");
+
case CLK_TYPE_GEN3_RPCSRC:
return rcar_clk_get_rate64_div_table(core->parent,
gen3_clk_get_rate64(&parent),
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c
b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index 4d72ec1fae8..f5d77df4233 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -22,11 +22,6 @@
#define CPG_SD0CKCR0x0074
-enum r8a77970_clk_types {
- CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
- CLK_TYPE_R8A77970_SD0,
-};
-
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 008e8928e59..200e4adb906 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -18,7 +18,9 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PLL3,
CLK_TYP
[PATCH] net: ravb: Drop SoC-specific compatible support
The current set of U-Boot upstream R-Car Gen3 DTs all contain generic
"renesas,etheravb-rcar-gen3" compatible strings, drop the SoC specific
compatible string support from U-Boot to reduce size and duplication.
Signed-off-by: Marek Vasut
---
drivers/net/ravb.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index c28680565fc..5a835cc06ff 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -693,12 +693,6 @@ int ravb_of_to_plat(struct udevice *dev)
}
static const struct udevice_id ravb_ids[] = {
- { .compatible = "renesas,etheravb-r8a7795" },
- { .compatible = "renesas,etheravb-r8a7796" },
- { .compatible = "renesas,etheravb-r8a77965" },
- { .compatible = "renesas,etheravb-r8a77970" },
- { .compatible = "renesas,etheravb-r8a77990" },
- { .compatible = "renesas,etheravb-r8a77995" },
{ .compatible = "renesas,etheravb-rcar-gen3" },
{ }
};
--
2.39.0
[PATCH 02/13] mmc: renesas-sdhi: Filter out HS400 on M3-W r1.2, V3M, V3H r1.x, D3
From: Hai Pham
Further filter out HS400 support on certain SoCs.
Since M3-W r1.2 does not support HS400, drop the calibration table and
rename the one for M3-W r1.3 to r8a7796_rev13_calib_table
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/mmc/renesas-sdhi.c | 29 -
1 file changed, 8 insertions(+), 21 deletions(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 9f8a272d03d..3ec0444700e 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -78,14 +78,7 @@ static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
};
-static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
-15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
- 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
-};
-
-static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
+static const u8 r8a7796_rev13_calib_table[2][CALIB_TABLE_MAX] = {
{ 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
{ 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
@@ -871,12 +864,16 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
struct tmio_sd_plat *plat = dev_get_plat(dev);
- /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
+ /* HS400 is not supported on H3 ES1.x, M3W ES1.[012], V3M, V3H ES1.x,
D3 */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() < 2)))
+ (rmobile_get_cpu_rev_fraction() <= 2)) ||
+ (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) ||
+ ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) &&
+ (rmobile_get_cpu_rev_integer() <= 1)) ||
+ (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
plat->cfg.host_caps &= ~MMC_MODE_HS400;
/* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
@@ -897,16 +894,6 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
- /* M3W ES1.2 can use HS400 with manual adjustment */
- if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
- (rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() == 2)) {
- priv->adjust_hs400_enable = true;
- priv->adjust_hs400_offset = 3;
- priv->adjust_hs400_calib_table =
- r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
- }
-
/* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
@@ -915,7 +902,7 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
priv->adjust_hs400_offset = 0;
priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
priv->adjust_hs400_calib_table =
- r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
+ r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
/* M3N can use HS400 with manual adjustment */
--
2.39.0
[PATCH 33/35] clk: renesas: Add and enable CPG reset driver
Add trivial reset driver extension to the CPG clock driver. The change
turns current CPG UCLASS_CLK driver instance into an UCLASS_NOP proxy
driver, which in turn binds both generic rcar3_clk UCLASS_CLK clock
driver as well as generic rcar_rst UCLASS_RESET reset driver to the
CPG DT node. This way, any other drivers which use the 'reset' DT
property can now obtain valid reset handle backed by a reset driver.
The clock tables have been updated to represent the CPG driver and only
implement the generic CPG proxy driver bind call, which binds the clock
and reset drivers.
The DM_RESET is now enabled for all R-Car Gen3 platforms.
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Kconfig.64| 3 +
drivers/clk/renesas/clk-rcar-gen3.c | 82 -
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a774e1-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a7796-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a77965-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a77970-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a77980-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a77990-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a77995-cpg-mssr.c | 15 ++---
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 15 ++---
drivers/clk/renesas/rcar-gen3-cpg.h | 3 +-
15 files changed, 156 insertions(+), 112 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index bf12b21ecf4..8e617e58244 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -201,4 +201,7 @@ config MULTI_DTB_FIT_USER_DEF_ADDR
config SYS_MALLOC_F_LEN
default 0x8000 if RCAR_GEN3
+config DM_RESET
+ default y if RCAR_GEN3
+
endif
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 94715bb00ce..3611bdb06fc 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -13,12 +13,15 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
#include
#include
#include
+#include
#include
@@ -389,7 +392,7 @@ const struct clk_ops gen3_clk_ops = {
.of_xlate = gen3_clk_of_xlate,
};
-int gen3_clk_probe(struct udevice *dev)
+static int gen3_clk_probe(struct udevice *dev)
{
struct gen3_clk_priv *priv = dev_get_priv(dev);
struct cpg_mssr_info *info =
@@ -447,9 +450,84 @@ int gen3_clk_probe(struct udevice *dev)
return 0;
}
-int gen3_clk_remove(struct udevice *dev)
+static int gen3_clk_remove(struct udevice *dev)
{
struct gen3_clk_priv *priv = dev_get_priv(dev);
return renesas_clk_remove(priv->base, priv->info);
}
+
+U_BOOT_DRIVER(clk_gen3) = {
+ .name = "clk_gen3",
+ .id = UCLASS_CLK,
+ .priv_auto = sizeof(struct gen3_clk_priv),
+ .ops= &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
+
+static int gen3_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct udevice *cdev = (struct udevice
*)dev_get_driver_data(reset_ctl->dev);
+ struct gen3_clk_priv *priv = dev_get_priv(cdev);
+ unsigned int reg = reset_ctl->id / 32;
+ unsigned int bit = reset_ctl->id % 32;
+ u32 bitmask = BIT(bit);
+
+ writel(bitmask, priv->base + priv->info->reset_regs[reg]);
+
+ return 0;
+}
+
+static int gen3_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct udevice *cdev = (struct udevice
*)dev_get_driver_data(reset_ctl->dev);
+ struct gen3_clk_priv *priv = dev_get_priv(cdev);
+ unsigned int reg = reset_ctl->id / 32;
+ unsigned int bit = reset_ctl->id % 32;
+ u32 bitmask = BIT(bit);
+
+ writel(bitmask, priv->base + priv->info->reset_clear_regs[reg]);
+
+ return 0;
+}
+
+static const struct reset_ops rst_gen3_ops = {
+ .rst_assert = gen3_reset_assert,
+ .rst_deassert = gen3_reset_deassert,
+};
+
+U_BOOT_DRIVER(rst_gen3) = {
+ .name = "rst_gen3",
+ .id = UCLASS_RESET,
+ .ops = &rst_gen3_ops,
+};
+
+int gen3_cpg_bind(struct udevice *parent)
+{
+ struct cpg_mssr_info *info =
+ (struct cpg_mssr_info *)dev_get_driver_data(parent);
+ struct udevice *cdev, *rdev;
+ struct driver *drv;
+ int ret;
+
+ drv = lists_driver_lookup_name("clk_gen3");
+ if (!drv)
+ return -ENOENT;
+
+ ret = device_bind_with_driver_data(parent, drv, "clk_gen3", (ulong)info,
+ dev_ofnode(parent), &cdev);
+ if (ret)
+ return ret;
+
+ drv = lists_driver_lookup_name("rst_gen3");
+ if (!drv)
+ return -ENOENT;
+
+ ret = device_bind_with_driver_data(parent, drv, "rst_gen3", (ulong)cdev,
+
[PATCH 35/35] clk: renesas: Drop core param from gen3_clk_get_rate64_pll_mul_reg
Drop 'core' parameter from gen3_clk_get_rate64_pll_mul_reg() function
as it is only used in debug print. No functional change except for the
debug print, which is disabled by default.
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen3.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 812580475c6..dd61fe0c7cd 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -160,7 +160,6 @@ static u64 gen3_clk_get_rate64(struct clk *clk);
static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
struct clk *parent,
- const struct cpg_core_clk *core,
u32 mul_reg, u32 mult, u32 div,
char *name)
{
@@ -175,8 +174,8 @@ static u64 gen3_clk_get_rate64_pll_mul_reg(struct
gen3_clk_priv *priv,
rate = (gen3_clk_get_rate64(parent) * mult) / div;
- debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",
- __func__, __LINE__, name, core->parent, mult, div, rate);
+ debug("%s[%i] %s clk: mult=%u div=%u => rate=%llu\n",
+ __func__, __LINE__, name, mult, div, rate);
return rate;
}
@@ -230,56 +229,56 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return -EINVAL;
case CLK_TYPE_GEN3_MAIN:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, 1, pll_config->extal_div,
"MAIN");
case CLK_TYPE_GEN3_PLL0:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
CPG_PLL0CR, 0, 0, "PLL0");
case CLK_TYPE_GEN3_PLL1:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, pll_config->pll1_mult,
pll_config->pll1_div, "PLL1");
case CLK_TYPE_GEN3_PLL2:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
CPG_PLL2CR, 0, 0, "PLL2");
case CLK_TYPE_GEN3_PLL3:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, pll_config->pll3_mult,
pll_config->pll3_div, "PLL3");
case CLK_TYPE_GEN3_PLL4:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
CPG_PLL4CR, 0, 0, "PLL4");
case CLK_TYPE_GEN4_MAIN:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, 1, pll_config->extal_div,
"V3U_MAIN");
case CLK_TYPE_GEN4_PLL1:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, pll_config->pll1_mult,
pll_config->pll1_div,
"V3U_PLL1");
case CLK_TYPE_GEN4_PLL2X_3X:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
core->offset, 0, 0,
"V3U_PLL2X_3X");
case CLK_TYPE_GEN4_PLL5:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, pll_config->pll5_mult,
pll_config->pll5_div,
"V3U_PLL5");
case CLK_TYPE_FF:
- return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, core->mult, core->div,
"FIXED");
--
2.39.0
[PATCH 34/35] clk: renesas: Use pre-defined offset for RPC clocks
From: Hai Pham
Since commit f7b4e4c0949f ("clk: renesas: Synchronize R-Car Gen3 tables
with Linux 5.12"), the custom macros for RPC clocks were dropped.
Use pre-defined offset for RPC clocks, same as what Linux does, instead
of retrieving it from the macros
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen3.c | 2 +-
drivers/clk/renesas/rcar-gen3-cpg.h | 3 ---
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 3611bdb06fc..812580475c6 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -324,7 +324,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN4_RPCD2:
rate = gen3_clk_get_rate64(&parent);
- value = readl(priv->base + core->offset);
+ value = readl(priv->base + CPG_RPCCKCR);
prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
CPG_RPC_PREDIV_MASK;
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index a7074e2bcde..007610bb4d9 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -53,9 +53,6 @@ enum rcar_gen3_clk_types {
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
-#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset)
-
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
(_parent0) << 16 | (_parent1), \
--
2.39.0
[PATCH 32/35] clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
From: Hai Pham
Add support for the R-Car M3-W+ (R8A77961) SoC.
R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for
both SoCs to share a driver.
Based on Linux commit 2ba738d56db4 ("clk: renesas: r8a7796: Add R8A77961
CPG/MSSR support")
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Kconfig.64 | 1 +
drivers/clk/renesas/Kconfig| 6 ++
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a7796-cpg-mssr.c | 19 +++
4 files changed, 27 insertions(+)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index b84aae0c83a..bf12b21ecf4 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -36,6 +36,7 @@ config R8A7796
bool "Renesas SoC R8A7796"
select GICV2
imply CLK_R8A77960
+ imply CLK_R8A77961
imply PINCTRL_PFC_R8A77960
imply PINCTRL_PFC_R8A77961
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 939aa8d7e6a..a538e7e7aa0 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -85,6 +85,12 @@ config CLK_R8A77960
help
Enable this to support the clocks on Renesas R8A77960 SoC.
+config CLK_R8A77961
+ bool "Renesas R8A77961 clock driver"
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A77961 SoC.
+
config CLK_R8A77965
bool "Renesas R8A77965 clock driver"
depends on CLK_RCAR_GEN3
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 8c0354b7872..df6bbc20bc3 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 87b8c083522..a3fee158510 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -355,11 +355,30 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info =
{
.get_pll_config = r8a7796_get_pll_config,
};
+static const struct cpg_mssr_info r8a77961_cpg_mssr_info = {
+ .core_clk = r8a7796_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
+ .mod_clk= r8a7796_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
+ .mstp_table = r8a7796_mstp_table,
+ .mstp_table_size= ARRAY_SIZE(r8a7796_mstp_table),
+ .reset_node = "renesas,r8a77961-rst",
+ .extalr_node= "extalr",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extalr_id = CLK_EXTALR,
+ .get_pll_config = r8a7796_get_pll_config,
+};
+
static const struct udevice_id r8a7796_clk_ids[] = {
{
.compatible = "renesas,r8a7796-cpg-mssr",
.data = (ulong)&r8a7796_cpg_mssr_info,
},
+ {
+ .compatible = "renesas,r8a77961-cpg-mssr",
+ .data = (ulong)&r8a77961_cpg_mssr_info,
+ },
{ }
};
--
2.39.0
[PATCH 28/35] clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7
Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index 418c393a20c..a09f11d4334 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -2,7 +2,7 @@
/*
* r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
*
- * Copyright (C) 2020 Renesas Electronics Corp.
+ * Copyright (C) 2019 Renesas Electronics Corp.
*
* Based on r8a7796-cpg-mssr.c
*
@@ -65,12 +65,8 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
- DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
-CLK_RPCSRC),
- DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-R8A774B1_CLK_RPC),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -96,10 +92,17 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = {
DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1),
- DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
+ DEF_GEN3_SDH("sd0h",R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
+ DEF_GEN3_SDH("sd1h",R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
+ DEF_GEN3_SDH("sd2h",R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
+ DEF_GEN3_SDH("sd3h",R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
+ DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
+ DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
+ DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
+ DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
+
+ DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A774B1_CLK_RPC),
DEF_FIXED("cl", R8A774B1_CLK_CL,CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A774B1_CLK_CP,CLK_EXTAL, 2, 1),
@@ -205,7 +208,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
DEF_MOD("rpc-if",917, R8A774B1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
- DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
+ DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),
--
2.39.0
[PATCH 31/35] clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
From: Hai Pham
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_CLK_R8A77961.
Based on Linux commit 92d1ebae9abf ("clk: renesas: Rename CLK_R8A7796
to CLK_R8A77960")
Reviewed-by: Marek Vasut
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Kconfig.64 | 2 +-
drivers/clk/renesas/Kconfig | 6 +++---
drivers/clk/renesas/Makefile | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 3e73acce664..b84aae0c83a 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -35,7 +35,7 @@ config R8A7795
config R8A7796
bool "Renesas SoC R8A7796"
select GICV2
- imply CLK_R8A7796
+ imply CLK_R8A77960
imply PINCTRL_PFC_R8A77960
imply PINCTRL_PFC_R8A77961
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index f4d6ef9f938..939aa8d7e6a 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -79,11 +79,11 @@ config CLK_R8A7795
help
Enable this to support the clocks on Renesas R8A7795 SoC.
-config CLK_R8A7796
- bool "Renesas R8A7796 clock driver"
+config CLK_R8A77960
+ bool "Renesas R8A77960 clock driver"
depends on CLK_RCAR_GEN3
help
- Enable this to support the clocks on Renesas R8A7796 SoC.
+ Enable this to support the clocks on Renesas R8A77960 SoC.
config CLK_R8A77965
bool "Renesas R8A77965 clock driver"
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 36a5ca65f4b..8c0354b7872 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
-obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
--
2.39.0
[PATCH 29/35] clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7
Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index c1283d2614c..f2dce5d8853 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -2,12 +2,12 @@
/*
* r8a774c0 Clock Pulse Generator / Module Standby and Software Reset
*
- * Copyright (C) 2020 Renesas Electronics Corp.
+ * Copyright (C) 2018 Renesas Electronics Corp.
*
* Based on r8a77990-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
- * Copyright (C) 2020 Renesas Electronics Corp.
+ * Copyright (C) 2015 Renesas Electronics Corp.
*/
#include
@@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
- DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
-CLK_RPCSRC),
- DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-R8A774C0_CLK_RPC),
-
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO,8 * 1000 * 1000),
@@ -108,9 +103,15 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
- DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074),
- DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078),
- DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c),
+ DEF_BASE("rpc",R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A774C0_CLK_RPC),
+
+ DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074),
+ DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078),
+ DEF_GEN3_SDH("sd3h", R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c),
+ DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, R8A774C0_CLK_SD0H, 0x0074),
+ DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, R8A774C0_CLK_SD1H, 0x0078),
+ DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, R8A774C0_CLK_SD3H, 0x026c),
DEF_FIXED("cl",R8A774C0_CLK_CL,CLK_PLL1, 48, 1),
DEF_FIXED("cp",R8A774C0_CLK_CP,CLK_EXTAL, 2, 1),
@@ -210,7 +211,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
DEF_MOD("rpc-if",917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
- DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
+ DEF_MOD("iic-pmic", 926, R8A774C0_CLK_CP),
DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2),
DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2),
DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2),
--
2.39.0
[PATCH 27/35] clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7
Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 32 +
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 48da65cd3d0..445c58b88a0 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -1,11 +1,10 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
/*
- * Renesas R8A774A1 CPG MSSR driver
+ * r8a774a1 Clock Pulse Generator / Module Standby and Software Reset
*
- * Copyright (C) 2017-2019 Marek Vasut
+ * Copyright (C) 2018 Renesas Electronics Corp.
*
- * Based on the following driver from Linux kernel:
- * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ * Based on r8a7796-cpg-mssr.c
*
* Copyright (C) 2016 Glider bvba
*/
@@ -68,12 +67,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
- DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
-CLK_RPCSRC),
- DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-R8A774A1_CLK_RPC),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -100,10 +95,17 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1),
- DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
+ DEF_GEN3_SDH("sd0h",R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074),
+ DEF_GEN3_SDH("sd1h",R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078),
+ DEF_GEN3_SDH("sd2h",R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268),
+ DEF_GEN3_SDH("sd3h",R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c),
+ DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074),
+ DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078),
+ DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
+ DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
+
+ DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A774A1_CLK_RPC),
DEF_FIXED("cl", R8A774A1_CLK_CL,CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A774A1_CLK_CP,CLK_EXTAL, 2, 1),
@@ -210,7 +212,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
DEF_MOD("rpc-if",917, R8A774A1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
- DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
+ DEF_MOD("iic-pmic", 926, R8A774A1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2),
--
2.39.0
[PATCH 26/35] clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7
Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Rename CLK_TYPE_R8A779A0_ to CLK_TYPE_GEN4_ to match the new
clock tables. Add CLK_TYPE_GEN4_SD, CLK_TYPE_GEN4_RPC and
CLK_TYPE_GEN4_RPCD2 macros and handling into Gen3 CPG core.
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen3.c | 14 +++---
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 58 +
drivers/clk/renesas/rcar-gen3-cpg.h | 36 ---
3 files changed, 77 insertions(+), 31 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 84cf072cae6..94715bb00ce 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -253,23 +253,23 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
CPG_PLL4CR, 0, 0, "PLL4");
- case CLK_TYPE_R8A779A0_MAIN:
+ case CLK_TYPE_GEN4_MAIN:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, 1, pll_config->extal_div,
"V3U_MAIN");
- case CLK_TYPE_R8A779A0_PLL1:
+ case CLK_TYPE_GEN4_PLL1:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, pll_config->pll1_mult,
pll_config->pll1_div,
"V3U_PLL1");
- case CLK_TYPE_R8A779A0_PLL2X_3X:
+ case CLK_TYPE_GEN4_PLL2X_3X:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
core->offset, 0, 0,
"V3U_PLL2X_3X");
- case CLK_TYPE_R8A779A0_PLL5:
+ case CLK_TYPE_GEN4_PLL5:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, pll_config->pll5_mult,
pll_config->pll5_div,
@@ -290,11 +290,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return rate;
case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
+ fallthrough;
+ case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
return gen3_clk_get_rate64(&parent);
case CLK_TYPE_GEN3_SD: /* FIXME */
fallthrough;
- case CLK_TYPE_R8A779A0_SD:
+ case CLK_TYPE_GEN4_SD:
value = readl(priv->base + core->offset);
value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
@@ -315,6 +317,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_RPC:
case CLK_TYPE_GEN3_RPCD2:
+ case CLK_TYPE_GEN4_RPC:
+ case CLK_TYPE_GEN4_RPCD2:
rate = gen3_clk_get_rate64(&parent);
value = readl(priv->base + core->offset);
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index bda69952362..0c28477377e 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -53,29 +53,18 @@ enum clk_ids {
};
#define DEF_PLL(_name, _id, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
.offset = _offset)
-#define DEF_SD(_name, _id, _parent, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
-
-#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
- DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
-(_parent0) << 16 | (_parent1), \
-.div = (_div0) << 16 | (_div1), .offset = _md)
-
-#define DEF_OSC(_name, _id, _parent, _div) \
- DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
-
static const struct cpg_core_clk r8a779a0_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
- DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+ DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
DEF_PLL(".pll20", CLK_PLL20,0x0834),
DEF_PLL(".pll21", CLK_PLL21,0x0838),
DEF_PLL(".pll30", CLK_PLL30,0x083c),
@@ -91,9 +80,14 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
DEF_FIXED(".s1",
[PATCH 23/35] clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.1.7
Synchronize R-Car R8A77980 V3H clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77980-cpg-mssr.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c
b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index bd9d7c9be50..1f29e77da9d 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -65,13 +65,10 @@ static const struct cpg_core_clk r8a77980_core_clks[] = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
- DEF_RATE(".oco",CLK_OCO, 32768),
- DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
-CLK_RPCSRC),
- DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-R8A77980_CLK_RPC),
+ DEF_RATE(".oco",CLK_OCO, 32768),
/* Core Clock Outputs */
DEF_FIXED("ztr",R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
@@ -95,7 +92,11 @@ static const struct cpg_core_clk r8a77980_core_clks[] = {
DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
- DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC,0x0074),
+ DEF_GEN3_SDH("sd0h",R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074),
+ DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074),
+
+ DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A77980_CLK_RPC),
DEF_FIXED("cl", R8A77980_CLK_CL,CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A77980_CLK_CP,CLK_EXTAL, 2, 1),
--
2.39.0
[PATCH 24/35] clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.1.7
Synchronize R-Car R8A77990 E3 clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77990-cpg-mssr.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c
b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 67a1f586e2a..4d9b78ebab8 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -2,7 +2,7 @@
/*
* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
*
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
@@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
- DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC,
-CLK_RPCSRC),
- DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-R8A77990_CLK_RPC),
-
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO,8 * 1000 * 1000),
@@ -108,9 +103,15 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
- DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074),
- DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
- DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
+ DEF_GEN3_SDH("sd0h", R8A77990_CLK_SD0H, CLK_SDSRC, 0x0074),
+ DEF_GEN3_SDH("sd1h", R8A77990_CLK_SD1H, CLK_SDSRC, 0x0078),
+ DEF_GEN3_SDH("sd3h", R8A77990_CLK_SD3H, CLK_SDSRC, 0x026c),
+ DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, R8A77990_CLK_SD0H, 0x0074),
+ DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078),
+ DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c),
+
+ DEF_BASE("rpc",R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A77990_CLK_RPC),
DEF_FIXED("cl",R8A77990_CLK_CL,CLK_PLL1, 48, 1),
DEF_FIXED("cr",R8A77990_CLK_CR,CLK_PLL1D2, 2, 1),
@@ -205,6 +206,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
+ DEF_MOD("mlp", 802, R8A77990_CLK_S2D1),
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
@@ -219,7 +221,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("can-fd",914, R8A77990_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A77990_CLK_RPC),
+ DEF_MOD("rpc-if",917, R8A77990_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
@@ -241,6 +243,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("dab", 1016, R8A77990_CLK_S3D1),
DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
--
2.39.0
[PATCH 25/35] clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.1.7
Synchronize R-Car R8A77995 D3 clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77995-cpg-mssr.c | 17 +
drivers/clk/renesas/rcar-gen3-cpg.h | 5 +
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c
b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 83e8e9bfaa1..ee4061f9d82 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -71,18 +71,14 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
- DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
-
- DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
-CLK_RPCSRC),
- DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-R8A77995_CLK_RPC),
+ DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO,8 * 1000 * 1000),
/* Core Clock Outputs */
+ DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
DEF_FIXED("z2",R8A77995_CLK_Z2,CLK_PLL0D3, 1, 1),
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt",R8A77995_CLK_ZT,CLK_PLL1, 4, 1),
@@ -110,7 +106,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
- DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
+ DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
+ DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
+
+ DEF_BASE("rpc",R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A77995_CLK_RPC),
DEF_DIV6P1("canfd",R8A77995_CLK_CANFD, CLK_PLL0D3,0x244),
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2,0x014),
@@ -166,6 +166,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
+ DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
@@ -179,7 +180,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("can-fd",914, R8A77995_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A77995_CLK_RPC),
+ DEF_MOD("rpc-if",917, R8A77995_CLK_RPCD2),
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 9ca42c2dddb..9159071a2b5 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -25,6 +25,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
CLK_TYPE_GEN3_RPCSRC,
+ CLK_TYPE_GEN3_D3_RPCSRC,
CLK_TYPE_GEN3_E3_RPCSRC,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_RPCD2,
@@ -70,6 +71,10 @@ enum rcar_gen3_clk_types {
#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
+#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1)\
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_D3_RPCSRC, \
+(_parent0) << 16 | (_parent1), .div = 5)
+
#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1)\
DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
(_parent0) << 16 | (_parent1), .div = 8)
--
2.39.0
[PATCH 22/35] clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.1.7
Synchronize R-Car R8A77965 M3-N clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77965-cpg-mssr.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c
b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 0a15617da82..cd3bda9a39e 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -3,6 +3,7 @@
* r8a77965 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2018 Jacopo Mondi
+ * Copyright (C) 2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
@@ -68,12 +69,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
DEF_FIXED(".s2",CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
- DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
-CLK_RPCSRC),
- DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-R8A77965_CLK_RPC),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -100,10 +97,17 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1),
- DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
+ DEF_GEN3_SDH("sd0h",R8A77965_CLK_SD0H, CLK_SDSRC,
0x074),
+ DEF_GEN3_SDH("sd1h",R8A77965_CLK_SD1H, CLK_SDSRC,
0x078),
+ DEF_GEN3_SDH("sd2h",R8A77965_CLK_SD2H, CLK_SDSRC,
0x268),
+ DEF_GEN3_SDH("sd3h",R8A77965_CLK_SD3H, CLK_SDSRC,
0x26c),
+ DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H,
0x074),
+ DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H,
0x078),
+ DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H,
0x268),
+ DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H,
0x26c),
+
+ DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A77965_CLK_RPC),
DEF_FIXED("cl", R8A77965_CLK_CL,CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A77965_CLK_CR,CLK_PLL1_DIV4, 2, 1),
@@ -204,6 +208,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("lvds", 727,R8A77965_CLK_S2D1),
DEF_MOD("hdmi0",729,R8A77965_CLK_HDMI),
+ DEF_MOD("mlp", 802,R8A77965_CLK_S2D1),
DEF_MOD("vin7", 804,R8A77965_CLK_S0D2),
DEF_MOD("vin6", 805,R8A77965_CLK_S0D2),
DEF_MOD("vin5", 806,R8A77965_CLK_S0D2),
@@ -249,6 +254,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("dab", 1016, R8A77965_CLK_S0D6),
DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
--
2.39.0
[PATCH 20/35] clk: renesas: Synchronize R8A7795 H3 clock tables with Linux 6.1.7
Synchronize R-Car R8A7795 H3 clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 28 +-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 6ba796b98c3..31cd24ec127 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -3,6 +3,7 @@
* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on clk-rcar-gen3.c
*
@@ -69,12 +70,8 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
- DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
-CLK_RPCSRC),
- DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-R8A7795_CLK_RPC),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -102,10 +99,17 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
- DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
+ DEF_GEN3_SDH("sd0h",R8A7795_CLK_SD0H, CLK_SDSRC,0x074),
+ DEF_GEN3_SDH("sd1h",R8A7795_CLK_SD1H, CLK_SDSRC,0x078),
+ DEF_GEN3_SDH("sd2h",R8A7795_CLK_SD2H, CLK_SDSRC,0x268),
+ DEF_GEN3_SDH("sd3h",R8A7795_CLK_SD3H, CLK_SDSRC,0x26c),
+ DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074),
+ DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078),
+ DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
+ DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
+
+ DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A7795_CLK_RPC),
DEF_FIXED("cl", R8A7795_CLK_CL,CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A7795_CLK_CR,CLK_PLL1_DIV4, 2, 1),
@@ -126,6 +130,11 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("fdp1-2",117, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fdp1-1",118, R8A7795_CLK_S0D1),
DEF_MOD("fdp1-0",119, R8A7795_CLK_S0D1),
+ DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
+ DEF_MOD("tmu3", 122, R8A7795_CLK_S3D2),
+ DEF_MOD("tmu2", 123, R8A7795_CLK_S3D2),
+ DEF_MOD("tmu1", 124, R8A7795_CLK_S3D2),
+ DEF_MOD("tmu0", 125, R8A7795_CLK_CP),
DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
@@ -222,6 +231,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
+ DEF_MOD("mlp", 802, R8A7795_CLK_S2D1),
DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
--
2.39.0
[PATCH 19/35] clk: renesas: Add dummy SDnH clock
From: Hai Pham
Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.
Based on Linux series by Wolfram Sang:
commit a31cf51bf6b4b ("clk: renesas: rcar-gen3: Add dummy SDnH clock"),
commit 1abd04480866c ("clk: renesas: rcar-gen3: Add SDnH clock"),
commit 63494b6f98f26 ("clk: renesas: r8a779a0: Add SDnH clock to V3U")
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut # Switch to
gen3_clk_get_rate64
---
drivers/clk/renesas/clk-rcar-gen3.c | 3 +++
drivers/clk/renesas/rcar-gen3-cpg.h | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index bcf5865222f..84cf072cae6 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -289,6 +289,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
div, rate);
return rate;
+ case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
+ return gen3_clk_get_rate64(&parent);
+
case CLK_TYPE_GEN3_SD: /* FIXME */
fallthrough;
case CLK_TYPE_R8A779A0_SD:
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 7bf57013619..9ca42c2dddb 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -17,6 +17,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PLL2,
CLK_TYPE_GEN3_PLL3,
CLK_TYPE_GEN3_PLL4,
+ CLK_TYPE_GEN3_SDH,
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_MDSEL,/* Select parent/divider using mode pin */
@@ -40,6 +41,9 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_SOC_BASE,
};
+#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
+
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
--
2.39.0
[PATCH 15/35] pinctrl: renesas: Synchronize R8A77990 E3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A77990 E3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 606 +++--
1 file changed, 266 insertions(+), 340 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c
b/drivers/pinctrl/renesas/pfc-r8a77990.c
index 78b46de0417..c6c3d0988b0 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -26,12 +26,12 @@
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
@@ -57,10 +57,10 @@
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS),\
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),\
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS),\
- PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS),\
- PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS),\
- PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),\
- PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
/*
* F_() : just information
@@ -2343,6 +2343,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
+/* - MLB+ ---
*/
+static const unsigned int mlb_3pin_pins[] = {
+ RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
+};
+static const unsigned int mlb_3pin_mux[] = {
+ MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
+};
+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
+
/* - MSIOF0 -
*/
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
@@ -2821,23 +2831,6 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
-static const unsigned int qspi0_data2_pins[] = {
- /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
- RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-};
-static const unsigned int qspi0_data2_mux[] = {
- QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
- /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
- RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
- /* QSPI0_IO2, QSPI0_IO3 */
- RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-};
-static const unsigned int qspi0_data4_mux[] = {
- QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
- QSPI0_IO2_MARK, QSPI0_IO3_MARK,
-};
/* - QSPI1 --
*/
static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */
@@ -2846,23 +2839,51 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
-static const unsigned int qspi1_data2_pins[] = {
- /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
- RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+
+/* - RPC
*/
+static const unsigned int rpc_clk_pins[] = {
+ /* Octal-SPI flash: C/SCLK */
+ /* HyperFlash: CK, CK# */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 6),
};
-static const unsigned int qspi1_data2_mux[] = {
- QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+static const unsigned int rpc_clk_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
};
-static const unsigned int qspi1_data4_pins[] = {
- /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+static const unsigned int rpc_ctrl_pins[] = {
+ /* Octal-SPI flash: S#/CS, DQS */
+ /* HyperFlash: CS#, RDS */
+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int rpc_ctrl_mux[] = {
+ QSPI0_SSL_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int rpc_data_pins[] = {
+ /* DQ[0:7]
[PATCH 09/35] pinctrl: renesas: Synchronize R8A7794 E2 PFC tables with Linux 6.1.7
Synchronize R-Car R8A7794 E2 PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a7794.c | 671 +- 1 file changed, 455 insertions(+), 216 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 9495603f7c7..7ed54f0cfff 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -16,15 +16,66 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx)\ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_26(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_28(5, fn, sfx), \ - PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_1(6, 24, fn, sfx), \ - PORT_GP_1(6, 25, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(5, 7, fn, sfx), \ + PORT_GP_1(5, 8, fn, sfx), \ + PORT_GP_1(5, 9, fn, sfx), \ + PORT_GP_CFG_1(5, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(5, 24, fn, sfx), \ + PORT_GP_1(5, 25, fn, sfx), \ + PORT_GP_1(5, 26, fn, sfx), \ + PORT_GP_1(5, 27, fn, sfx), \ + PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),\ + PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),\ + PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
[PATCH 10/35] pinctrl: renesas: Synchronize R8A7795 H3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A7795 H3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Note that the Kconfig option name has been updated to match the
Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7795 to
PINCTRL_PFC_R8A77951 .
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Kconfig.64 | 2 +-
drivers/pinctrl/renesas/Kconfig | 2 +-
drivers/pinctrl/renesas/Makefile | 2 +-
drivers/pinctrl/renesas/pfc-r8a7795.c | 577 +-
drivers/pinctrl/renesas/pfc.c | 8 +-
5 files changed, 206 insertions(+), 385 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 007eaad251d..13f3f5fde43 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -30,7 +30,7 @@ config R8A7795
bool "Renesas SoC R8A7795"
select GICV2
imply CLK_R8A7795
- imply PINCTRL_PFC_R8A7795
+ imply PINCTRL_PFC_R8A77951
config R8A7796
bool "Renesas SoC R8A7796"
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 1fedf632528..f1761a87558 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -65,7 +65,7 @@ config PINCTRL_PFC_R8A774E1
help
Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs.
-config PINCTRL_PFC_R8A7795
+config PINCTRL_PFC_R8A77951
bool "Renesas RCar Gen3 R8A7795 pin control driver"
depends on PINCTRL_PFC
help
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1c65505eff0..e7607329d0e 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -8,7 +8,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c
b/drivers/pinctrl/renesas/pfc-r8a7795.c
index 015a50f1deb..d094bd7cc94 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7795.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7795.c
@@ -243,7 +243,7 @@
#define GPSR6_3F_(SSI_SDATA1_A,IP15_3_0)
#define GPSR6_2F_(SSI_SDATA0, IP14_31_28)
#define GPSR6_1F_(SSI_WS01239, IP14_27_24)
-#define GPSR6_0F_(SSI_SCK01239,IP14_23_20)
+#define GPSR6_0F_(SSI_SCK01239,IP14_23_20)
/* GPSR7 */
#define GPSR7_3FM(GP7_03)
@@ -670,7 +670,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,I2C_SEL_5_0,
SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0,
SEL_SCIF4_0),
- PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
+ PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -1827,7 +1827,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
-#ifdef CONFIG_PINCTRL_PFC_R8A7795
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
/* - DRIF0 --- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2042,7 +2042,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
-#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
+#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
/* - DU -
*/
static const unsigned int du_rgb666_pins[] = {
@@ -2455,6 +2455,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
+/* - MLB+ ---
*/
+static const unsigned int mlb_3pin_pins[] = {
+ RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
+};
+static const unsigned int mlb_3pin_mux[] = {
+ MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
+};
+#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
+
/* - MSIOF0 -
*/
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
@@ -3260,20 +3270,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
-static const unsigned int
[PATCH 11/35] pinctrl: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Note that the Kconfig option name has been updated to match the
Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7796 to
PINCTRL_PFC_R8A77960 .
Also note that a new Kconfig option has been added to enable support
for R8A77961 M3-W+ , the Kconfig option name is PINCTRL_PFC_R8A77961 .
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Kconfig.64 | 2 +-
drivers/pinctrl/renesas/Kconfig | 12 +-
drivers/pinctrl/renesas/Makefile | 2 +-
drivers/pinctrl/renesas/pfc-r8a7796.c | 601 ++
drivers/pinctrl/renesas/pfc.c | 23 +-
5 files changed, 254 insertions(+), 386 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 13f3f5fde43..248a9a84e5d 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -36,7 +36,7 @@ config R8A7796
bool "Renesas SoC R8A7796"
select GICV2
imply CLK_R8A7796
- imply PINCTRL_PFC_R8A7796
+ imply PINCTRL_PFC_R8A77960
config R8A77965
bool "Renesas SoC R8A77965"
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index f1761a87558..8f994d8d769 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -71,11 +71,17 @@ config PINCTRL_PFC_R8A77951
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.
-config PINCTRL_PFC_R8A7796
- bool "Renesas RCar Gen3 R8A7796 pin control driver"
+config PINCTRL_PFC_R8A77960
+ bool "Renesas RCar Gen3 R8A77960 pin control driver"
depends on PINCTRL_PFC
help
- Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs.
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77960 SoCs.
+
+config PINCTRL_PFC_R8A77961
+ bool "Renesas RCar Gen3 R8A77961 pin control driver"
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77961 SoCs.
config PINCTRL_PFC_R8A77965
bool "Renesas RCar Gen3 R8A77965 pin control driver"
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index e7607329d0e..721c7bdabbb 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a7795.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c
b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 06cae74fb51..3cc4a3b366a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -70,6 +70,7 @@
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),\
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),\
+ PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
@@ -1551,7 +1552,7 @@ static const u16 pinmux_data[] = {
* core will do the right thing and skip trying to mux the pin
* while still applying configuration to it.
*/
-#define FM(x) PINMUX_DATA(x##_MARK, 0),
+#define FM(x) PINMUX_DATA(x##_MARK, 0),
PINMUX_STATIC
#undef FM
};
@@ -1832,7 +1833,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) ||
defined(CONFIG_PINCTRL_PFC_R8A77961)
/* - DRIF0 --- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2047,7 +2048,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
-#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
/* - DU -
*/
static const unsigned int du_rgb666_pins[] = {
@@ -2460,6 +2461,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) ||
defined(CONFIG_PINCTRL_PFC_R8A77961)
+/* - MLB+ --
[PATCH 13/35] pinctrl: renesas: Synchronize R8A77970 V3M PFC tables with Linux 6.1.7
Synchronize R-Car R8A77970 V3M PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a77970.c | 478 + 1 file changed, 252 insertions(+), 226 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 8cf133a2baf..04f03452336 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -21,12 +21,23 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx)\ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_28(1, fn, sfx), \ - PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_6(4, fn, sfx), \ - PORT_GP_15(5, fn, sfx) + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -161,7 +172,7 @@ #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0)FM(A7) FM(PWMFSW0) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_3_0FM(DU_DG4) F_(0, 0) F_(0, 0)FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_7_4FM(DU_DG5) F_(0, 0) F_(0, 0)FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0)FM(A10) FM(FSO_TOE_N_A) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0)FM(A10) FM(FSO_TOE_N_A) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0)FM(A11) FM(IRQ1)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0)FM(A12) FM(IRQ2)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0)FM(A13) FM(FXR_CLKOUT1) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -222,7 +233,6 @@ #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_27_24 FM(DIGRF_CLKOUT)FM(DIGRF_CLKEN_OUT) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
[PATCH 16/35] pinctrl: renesas: Synchronize R8A77995 D3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A77995 D3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a77995.c | 746 ++---
1 file changed, 531 insertions(+), 215 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c
b/drivers/pinctrl/renesas/pfc-r8a77995.c
index 4ff1b76588c..06caf16c991 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -19,14 +19,24 @@
#include "sh_pfc.h"
-#define CPU_ALL_GP(fn, sfx)\
- PORT_GP_9(0, fn, sfx), \
- PORT_GP_32(1, fn, sfx), \
- PORT_GP_32(2, fn, sfx), \
- PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
- PORT_GP_32(4, fn, sfx), \
- PORT_GP_21(5, fn, sfx), \
- PORT_GP_14(6, fn, sfx)
+#define CPU_ALL_GP(fn, sfx)\
+ PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
+#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn,
SH_PFC_PIN_CFG_PULL_DOWN), \
+ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),
\
+ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),
\
+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn,
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
/*
* F_() : just information
@@ -933,8 +943,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
};
+/*
+ * Pins not associated with a GPIO port.
+ */
+enum {
+ GP_ASSIGN_LAST(),
+ NOGP_ALL(),
+};
+
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
+ PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK -
*/
@@ -1240,31 +1259,23 @@ static const unsigned int i2c3_b_mux[] = {
SCL3_B_MARK, SDA3_B_MARK,
};
-/* - MMC --- */
-static const unsigned int mmc_data1_pins[] = {
- /* D0 */
- RCAR_GP_PIN(3, 2),
+/* - MLB+ ---
*/
+static const unsigned int mlb_3pin_pins[] = {
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7),
};
-static const unsigned int mmc_data1_mux[] = {
- MMC_D0_MARK,
-};
-static const unsigned int mmc_data4_pins[] = {
- /* D[0:3] */
- RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
- RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int mmc_data4_mux[] = {
- MMC_D0_MARK, MMC_D1_MARK,
- MMC_D2_MARK, MMC_D3_MARK,
+static const unsigned int mlb_3pin_mux[] = {
+ MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
};
-static const unsigned int mmc_data8_pins[] = {
+
+/* - MMC --- */
+static const unsigned int mmc_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
};
-static const unsigned int mmc_data8_mux[] = {
+static const unsigned int mmc_data_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
@@ -1673,6 +1684,68 @@ static const unsigned int pwm3_c_mux[] = {
PWM3_C_MARK,
};
+/* - QSPI0 --
*/
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* QSPI0_SPCLK, QSPI0_SSL */
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+/* - QSPI1 --
*/
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+
+/* - RPC ---
[PATCH 17/35] pinctrl: renesas: Synchronize R8A779A0 V3U PFC tables with Linux 6.1.7
Synchronize R-Car R8A779A0 V3U PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a779a0.c | 400 + 1 file changed, 145 insertions(+), 255 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index d99b6e2e07c..544d7964442 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -392,7 +392,6 @@ #define IP3SR1_19_16 FM(GP1_28) F_(0, 0)F_(0, 0) F_(0, 0)F_(0, 0)FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3SR1_23_20 FM(GP1_29) F_(0, 0)F_(0, 0) F_(0, 0)F_(0, 0)FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3SR1_27_24 FM(GP1_30) F_(0, 0)F_(0, 0) F_(0, 0)F_(0, 0)FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_31_28 F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN)F_(0, 0)F_(0, 0)FM(DU_DOTCLKIN) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -423,11 +422,8 @@ #define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)FM(EX_WAIT0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ -#define IP0SR3_3_0 F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_11_8FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_15_12 F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_19_16 F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0)FM(PWM2) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -438,8 +434,6 @@ #define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0)F_(0, 0) FM(FXR_TXENA_N) F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0)F_(0, 0) FM(FXR_TXENB_N) F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0)F_(0, 0) FM(STPWT_EXTFXR)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_27_24 F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_31_28 F_(0, 0)F
[PATCH 07/35] pinctrl: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.1.7
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a7791.c | 820 +- 1 file changed, 529 insertions(+), 291 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index 7c8db5dc2cb..219333106fc 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -19,22 +19,50 @@ * which case they support both 3.3V and 1.8V signalling. */ #define CPU_ALL_GP(fn, sfx)\ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_26(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_32(5, fn, sfx), \ - PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_1(6, 24, fn, sfx), \ - PORT_GP_1(6, 25, fn, sfx), \ - PORT_GP_1(6, 26, fn, sfx), \ - PORT_GP_1(6, 27, fn, sfx), \ - PORT_GP_1(6, 28, fn, sfx), \ - PORT_GP_1(6, 29, fn, sfx), \ - PORT_GP_1(6, 30, fn, sfx), \ - PORT_GP_1(6, 31, fn, sfx), \ - PORT_GP_26(7, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(7, 7, fn, sfx), \ + PORT_GP_1(7, 8, fn, sfx), \ + PORT_GP_1(7, 9, fn, sfx), \ + PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN),\ + PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP
[PATCH 06/35] pinctrl: renesas: Synchronize R8A7790 H2 PFC tables with Linux 6.1.7
Synchronize R-Car R8A7790 H2 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a7790.c | 961 +++---
1 file changed, 555 insertions(+), 406 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c
b/drivers/pinctrl/renesas/pfc-r8a7790.c
index 1793000ab5c..432895ac55c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -21,18 +21,23 @@
* which case they support both 3.3V and 1.8V signalling.
*/
#define CPU_ALL_GP(fn, sfx)\
- PORT_GP_32(0, fn, sfx), \
- PORT_GP_30(1, fn, sfx), \
- PORT_GP_30(2, fn, sfx), \
- PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
- PORT_GP_32(4, fn, sfx), \
- PORT_GP_32(5, fn, sfx)
+ PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn,
SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP(IIC0_SDA, "AF15", fn), \
PIN_NOGP(IIC0_SCL, "AG15", fn), \
PIN_NOGP(IIC3_SDA, "AH15", fn), \
- PIN_NOGP(IIC3_SCL, "AJ15", fn)
+ PIN_NOGP(IIC3_SCL, "AJ15", fn), \
+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
@@ -189,24 +194,24 @@ enum {
FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
- FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+ FN_WE0_N, FN_IECLK, FN_CAN_CLK,
FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
- FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+ FN_IERX_C, FN_EX_WAIT0, FN_IRQ3,
FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
FN_SSI_WS78_B,
/* IPSR6 */
- FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+ FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B,
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
- FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+ FN_SSI_WS6_B, FN_SSI_SDATA8_C,
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
- FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+ FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2,
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
@@ -563,23 +568,23 @@ enum {
CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
- INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+ WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
- IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+ IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK,
VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
SSI_WS78_B_MARK,
- DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+ DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK,
VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
- INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+ SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
- MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+ MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK,
SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
ETH_C
[PATCH 12/35] pinctrl: renesas: Synchronize R8A77965 M3-N PFC tables with Linux 6.1.7
Synchronize R-Car R8A77965 M3-N PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a77965.c | 609 +
1 file changed, 210 insertions(+), 399 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c
b/drivers/pinctrl/renesas/pfc-r8a77965.c
index fae29d535c8..04e8371f51e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -669,14 +669,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
- PINMUX_IPSR_PHYS_MSEL(IP0_19_16,AVB_AVTP_MATCH_A,
I2C_SEL_5_0, SEL_ETHERAVB_0),
- PINMUX_IPSR_PHYS_MSEL(IP0_19_16,MSIOF2_RXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
- PINMUX_IPSR_PHYS_MSEL(IP0_19_16,CTS4_N_A, I2C_SEL_5_0,
SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0,
SEL_ETHERAVB_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0,
SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
- PINMUX_IPSR_PHYS_MSEL(IP0_23_20,AVB_AVTP_CAPTURE_A,
I2C_SEL_5_0, SEL_ETHERAVB_0),
- PINMUX_IPSR_PHYS_MSEL(IP0_23_20,MSIOF2_TXD_C,
I2C_SEL_5_0, SEL_MSIOF2_2),
- PINMUX_IPSR_PHYS_MSEL(IP0_23_20,RTS4_N_A,
I2C_SEL_5_0, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,I2C_SEL_5_0,
SEL_ETHERAVB_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0,
SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
@@ -730,16 +730,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
- PINMUX_IPSR_PHYS_MSEL(IP1_23_20,PWM1_A, I2C_SEL_3_0,
SEL_PWM1_0),
- PINMUX_IPSR_PHYS_MSEL(IP1_23_20,HRX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
- PINMUX_IPSR_PHYS_MSEL(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0,
SEL_VIN4_1),
- PINMUX_IPSR_PHYS_MSEL(IP1_23_20,IERX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
- PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,I2C_SEL_3_0,
SEL_PWM1_0),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,I2C_SEL_3_0,
SEL_HSCIF3_3),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0,
SEL_VIN4_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,I2C_SEL_3_0,
SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
- PINMUX_IPSR_PHYS_MSEL(IP1_27_24,PWM2_A, I2C_SEL_3_0,
SEL_PWM2_0),
- PINMUX_IPSR_PHYS_MSEL(IP1_27_24,HTX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
- PINMUX_IPSR_PHYS_MSEL(IP1_27_24,IETX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
- PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,I2C_SEL_3_0,
SEL_PWM2_0),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,I2C_SEL_3_0,
SEL_HSCIF3_3),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,I2C_SEL_3_0,
SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1174,13 +1174,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_15_12,SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_19_16,SD1_CD, I2C_SEL_0_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0,
SEL_NDF_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0,
SEL_SIMCARD_1),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0,
SEL_NDF_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0,
SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16,SCL0, I2C_SEL_0_1),
PINMUX_IPSR_MSEL(IP11_23_20,SD1_WP, I2C_SEL_0_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0,
SEL_NDF_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0,
SEL_SIMCARD_1),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_
[PATCH 08/35] pinctrl: renesas: Synchronize R8A7792 V2H PFC tables with Linux 6.1.7
Synchronize R-Car R8A7792 V2H PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a7792.c | 1206 -
1 file changed, 772 insertions(+), 434 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c
b/drivers/pinctrl/renesas/pfc-r8a7792.c
index 054c02a4ae0..81cfe81c7f5 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7792.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7792.c
@@ -15,18 +15,29 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx)\
- PORT_GP_29(0, fn, sfx), \
- PORT_GP_23(1, fn, sfx), \
- PORT_GP_32(2, fn, sfx), \
- PORT_GP_28(3, fn, sfx), \
- PORT_GP_17(4, fn, sfx), \
- PORT_GP_17(5, fn, sfx), \
- PORT_GP_17(6, fn, sfx), \
- PORT_GP_17(7, fn, sfx), \
- PORT_GP_17(8, fn, sfx), \
- PORT_GP_17(9, fn, sfx), \
- PORT_GP_32(10, fn, sfx),\
- PORT_GP_30(11, fn, sfx)
+ PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),\
+ PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
+
+#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP),
\
+ PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn,
SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP),
\
+ PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn,
SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
@@ -727,8 +738,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
};
+/*
+ * Pins not associated with a GPIO port.
+ */
+enum {
+ GP_ASSIGN_LAST(),
+ NOGP_ALL(),
+};
+
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
+ PINMUX_NOGP_ALL(),
};
/* - AVB
*/
@@ -1100,19 +1120,12 @@ static const unsigned int qspi_ctrl_pins[] = {
static const unsigned int qspi_ctrl_mux[] = {
SPCLK_MARK, SSL_MARK,
};
-static const unsigned int qspi_data2_pins[] = {
- /* MOSI_IO0, MISO_IO1 */
- RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
-};
-static const unsigned int qspi_data2_mux[] = {
- MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
+static const unsigned int qspi_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 24),
};
-static const unsigned int qspi_data4_mux[] = {
+static const unsigned int qspi_data_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
};
/* - SCIF0 --
*/
@@ -1190,19 +1203,12 @@ static const unsigned int scif3_clk_mux[] = {
SCK3_MARK,
};
/* - SDHI0 --
*/
-static const unsigned int sdhi0_data1_pins[] = {
- /* DAT0 */
- RCAR_GP_PIN(11, 7),
-};
-static const unsigned int sdhi0_data1_mux[] = {
- SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
/* DAT[0-3] */
RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
};
-static
[PATCH 14/35] pinctrl: renesas: Synchronize R8A77980 V3H PFC tables with Linux 6.1.7
Synchronize R-Car R8A77980 V3H PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a77980.c | 515 +++-- 1 file changed, 302 insertions(+), 213 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index 7cd4ef9830b..19bd46c9e48 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -21,12 +21,23 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx)\ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_28(1, fn, sfx), \ - PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_25(4, fn, sfx), \ - PORT_GP_15(5, fn, sfx) + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) /* * F_() : just information @@ -88,7 +99,7 @@ #define GPSR1_0F_(IRQ0,IP2_27_24) /* GPSR2 */ -#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) +#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12) #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8) #define GPSR2_26 F_(SDA3,IP10_7_4) @@ -253,11 +264,11 @@ #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_31_28 FM(DIGRF_CLKOUT)FM(DIGRF_CLKEN_OUT) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_3_0FM(IRQ4)F_(0, 0) F_(0, 0)FM(VI0_DATA12) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_7_4FM(IRQ5)F_(0, 0) F_(0, 0)FM(VI0_DATA13) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4FM(IRQ5)F_(0, 0) F_(0, 0)FM(VI0_DATA13) F_(0, 0)F_(0, 0)
[PATCH 18/35] pinctrl: renesas: r8a7796: Add R8A77961 PFC support
From: Hai Pham
R-Car M3-W+ (R8A77961) is pin compatible with R-Car M3-W (R8A77960),
which allows for both SoCs to share a driver.
Based on Linux commit 708c69e9eacc ("pinctrl: sh-pfc: r8a7796: Add
R8A77961 PFC support") and 74ce7a8044b0 ("pinctrl: renesas: r8a7796:
Optimize pinctrl image size for R8A774A1")
Signed-off-by: Hai Pham
---
arch/arm/mach-rmobile/Kconfig.64 | 1 +
drivers/pinctrl/renesas/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 248a9a84e5d..3e73acce664 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -37,6 +37,7 @@ config R8A7796
select GICV2
imply CLK_R8A7796
imply PINCTRL_PFC_R8A77960
+ imply PINCTRL_PFC_R8A77961
config R8A77965
bool "Renesas SoC R8A77965"
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 721c7bdabbb..1198c868557 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
--
2.39.0
[PATCH 05/35] pinctrl: renesas: Synchronize PFC core with Linux 6.1.7
Synchronize R-Car PFC core with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Parts picked from
pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.18.3
- Add pin groups for the green and high8 subsets of the Video IN pins
- Add MediaLB pins
- Add bias support for various SoCs
- Share more pin group data, to reduce size and ease review
- Miscellaneous cleanups, fixes and improvements.
This contains port of Linux kernel commit
6210905586ae ("pinctrl: renesas: Add shorthand for reserved register fields")
to handle negative entries in GROUP() macros correctly.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/gpio/sh_pfc.c| 2 +-
drivers/pinctrl/renesas/pfc.c| 84 --
drivers/pinctrl/renesas/sh_pfc.h | 258 +--
3 files changed, 211 insertions(+), 133 deletions(-)
diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c
index 0653171af48..988f7e9bbad 100644
--- a/drivers/gpio/sh_pfc.c
+++ b/drivers/gpio/sh_pfc.c
@@ -125,7 +125,7 @@ static void config_reg_helper(struct pinmux_info *gpioc,
*maskp = (1 << crp->var_field_width[in_pos]) - 1;
*posp = crp->reg_width;
for (k = 0; k <= in_pos; k++)
- *posp -= crp->var_field_width[k];
+ *posp -= abs(crp->var_field_width[k]);
}
}
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 490d34e56b8..0a887f6ad09 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -171,7 +171,7 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
*maskp = (1 << crp->var_field_width[in_pos]) - 1;
*posp = crp->reg_width;
for (k = 0; k <= in_pos; k++)
- *posp -= crp->var_field_width[k];
+ *posp -= abs(crp->var_field_width[k]);
}
}
@@ -219,14 +219,17 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16
enum_id,
if (!r_width)
break;
- for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
+ for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width,
m++) {
u32 ncomb;
u32 n;
- if (f_width)
+ if (f_width) {
curr_width = f_width;
- else
- curr_width = config_reg->var_field_width[m];
+ } else {
+ curr_width =
abs(config_reg->var_field_width[m]);
+ if (config_reg->var_field_width[m] < 0)
+ continue;
+ }
ncomb = 1 << curr_width;
for (n = 0; n < ncomb; n++) {
@@ -238,7 +241,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16
enum_id,
}
}
pos += ncomb;
- m++;
}
k++;
}
@@ -350,16 +352,16 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark,
int pinmux_type)
}
const struct pinmux_bias_reg *
-sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
- unsigned int *bit)
+rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin,
+unsigned int *bit)
{
unsigned int i, j;
- for (i = 0; pfc->info->bias_regs[i].puen; i++) {
- for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
- if (pfc->info->bias_regs[i].pins[j] == pin) {
+ for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) {
+ for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) {
+ if (info->bias_regs[i].pins[j] == pin) {
*bit = j;
- return &pfc->info->bias_regs[i];
+ return &info->bias_regs[i];
}
}
}
@@ -369,6 +371,64 @@ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned
int pin,
return NULL;
}
+unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+ const struct pinmux_bias_reg *reg;
+ unsigned int bit;
+
+ reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
+ if (!reg)
+ return PIN_CONFIG_BIAS_DISABLE;
+
+ if (reg->puen) {
+ if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
+ return PIN_CONFIG_BIAS_DISABLE;
+ else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
+ return PIN_CONFIG_BIAS_PULL_UP;
+ else
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+ } else {
+
[PATCH 03/35] dt-bindings: power: Pick R-Car Gen3 R8A77961 M3W+ header from Linux 6.1.7
From: Hai Pham Pick R-Car Gen3 R8A77961 M3W+ power domain header from Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Reviewed-by: Marek Vasut Signed-off-by: Hai Pham Signed-off-by: Marek Vasut # Update commit message --- include/dt-bindings/power/r8a77961-sysc.h | 32 +++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/r8a77961-sysc.h diff --git a/include/dt-bindings/power/r8a77961-sysc.h b/include/dt-bindings/power/r8a77961-sysc.h new file mode 100644 index 000..7a3800996f7 --- /dev/null +++ b/include/dt-bindings/power/r8a77961-sysc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Glider bvba + */ +#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77961_PD_CA57_CPU0 0 +#define R8A77961_PD_CA57_CPU1 1 +#define R8A77961_PD_CA53_CPU0 5 +#define R8A77961_PD_CA53_CPU1 6 +#define R8A77961_PD_CA53_CPU2 7 +#define R8A77961_PD_CA53_CPU3 8 +#define R8A77961_PD_CA57_SCU 12 +#define R8A77961_PD_CR713 +#define R8A77961_PD_A3VC 14 +#define R8A77961_PD_3DG_A 17 +#define R8A77961_PD_3DG_B 18 +#define R8A77961_PD_CA53_SCU 21 +#define R8A77961_PD_A3IR 24 +#define R8A77961_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77961_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */ -- 2.39.0
[PATCH 04/35] dt-bindings: clock: Pick R-Car Gen3 R8A77961 M3W+ header from Linux 6.1.7
From: Hai Pham Pick R-Car Gen3 R8A77961 M3W+ CPG Core Clock header from Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Reviewed-by: Marek Vasut Signed-off-by: Hai Pham Signed-off-by: Marek Vasut # Update commit message --- include/dt-bindings/clock/r8a77961-cpg-mssr.h | 65 +++ 1 file changed, 65 insertions(+) create mode 100644 include/dt-bindings/clock/r8a77961-cpg-mssr.h diff --git a/include/dt-bindings/clock/r8a77961-cpg-mssr.h b/include/dt-bindings/clock/r8a77961-cpg-mssr.h new file mode 100644 index 000..7921d785546 --- /dev/null +++ b/include/dt-bindings/clock/r8a77961-cpg-mssr.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ + +#include + +/* r8a77961 CPG Core Clocks */ +#define R8A77961_CLK_Z 0 +#define R8A77961_CLK_Z21 +#define R8A77961_CLK_ZR2 +#define R8A77961_CLK_ZG3 +#define R8A77961_CLK_ZTR 4 +#define R8A77961_CLK_ZTRD2 5 +#define R8A77961_CLK_ZT6 +#define R8A77961_CLK_ZX7 +#define R8A77961_CLK_S0D1 8 +#define R8A77961_CLK_S0D2 9 +#define R8A77961_CLK_S0D3 10 +#define R8A77961_CLK_S0D4 11 +#define R8A77961_CLK_S0D6 12 +#define R8A77961_CLK_S0D8 13 +#define R8A77961_CLK_S0D12 14 +#define R8A77961_CLK_S1D1 15 +#define R8A77961_CLK_S1D2 16 +#define R8A77961_CLK_S1D4 17 +#define R8A77961_CLK_S2D1 18 +#define R8A77961_CLK_S2D2 19 +#define R8A77961_CLK_S2D4 20 +#define R8A77961_CLK_S3D1 21 +#define R8A77961_CLK_S3D2 22 +#define R8A77961_CLK_S3D4 23 +#define R8A77961_CLK_LB24 +#define R8A77961_CLK_CL25 +#define R8A77961_CLK_ZB3 26 +#define R8A77961_CLK_ZB3D2 27 +#define R8A77961_CLK_ZB3D4 28 +#define R8A77961_CLK_CR29 +#define R8A77961_CLK_CRD2 30 +#define R8A77961_CLK_SD0H 31 +#define R8A77961_CLK_SD0 32 +#define R8A77961_CLK_SD1H 33 +#define R8A77961_CLK_SD1 34 +#define R8A77961_CLK_SD2H 35 +#define R8A77961_CLK_SD2 36 +#define R8A77961_CLK_SD3H 37 +#define R8A77961_CLK_SD3 38 +#define R8A77961_CLK_SSP2 39 +#define R8A77961_CLK_SSP1 40 +#define R8A77961_CLK_SSPRS 41 +#define R8A77961_CLK_RPC 42 +#define R8A77961_CLK_RPCD2 43 +#define R8A77961_CLK_MSO 44 +#define R8A77961_CLK_CANFD 45 +#define R8A77961_CLK_HDMI 46 +#define R8A77961_CLK_CSI0 47 +/* CLK_CSIREF was removed */ +#define R8A77961_CLK_CP49 +#define R8A77961_CLK_CPEX 50 +#define R8A77961_CLK_R 51 +#define R8A77961_CLK_OSC 52 + +#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */ -- 2.39.0
[PATCH 01/35] ARM: dts: rmobile: Synchronize DT headers with Linux 6.1.7
Synchronize R-Car device tree headers with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . This is only a copyright and SPDX identifier update, no functional change. The following script has been used for the synchronization: $ for i in $(cd include/dt-bindings/clock/ ; ls -1 r8a*) ; do cp /linux-2.6/include/dt-bindings/clock/$i include/dt-bindings/clock/ ; done $ for i in $(cd include/dt-bindings/power/ ; ls -1 r8a*) ; do cp /linux-2.6/include/dt-bindings/power/$i include/dt-bindings/power/ ; done Signed-off-by: Marek Vasut --- include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 6 +++--- include/dt-bindings/clock/r8a774b1-cpg-mssr.h | 2 +- include/dt-bindings/clock/r8a774c0-cpg-mssr.h | 2 +- include/dt-bindings/clock/r8a77970-cpg-mssr.h | 8 ++-- include/dt-bindings/power/r8a774a1-sysc.h | 6 +++--- include/dt-bindings/power/r8a774b1-sysc.h | 2 +- include/dt-bindings/power/r8a774c0-sysc.h | 2 +- include/dt-bindings/power/r8a7794-sysc.h | 5 + include/dt-bindings/power/r8a7795-sysc.h | 5 + include/dt-bindings/power/r8a7796-sysc.h | 5 + include/dt-bindings/power/r8a77970-sysc.h | 5 + include/dt-bindings/power/r8a77995-sysc.h | 5 + 12 files changed, 17 insertions(+), 36 deletions(-) diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h index 67bf8cdf496..e355363f40c 100644 --- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h index 28e0f8f76ca..1355451b74b 100644 --- a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2019 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h index 9db5c76e23f..8ad9cd6be8e 100644 --- a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2018 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h index 4146395595b..6145ebe6636 100644 --- a/include/dt-bindings/clock/r8a77970-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h @@ -1,11 +1,7 @@ -/* +/* SPDX-License-Identifier: GPL-2.0+ + * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h index d35183557c4..580f431cd32 100644 --- a/include/dt-bindings/power/r8a774a1-sysc.h +++ b/include/dt-bindings/power/r8a774a1-sysc.h @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ #define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ diff --git a/include/dt-bindings/power/r8a774b1-sysc.h b/include/dt-bindings/power/r8a774b1-sysc.h index 96afda0446b..373736402f0 100644 --- a/include/dt-bindings/power/r8a774b1-sysc.h +++ b/include/dt-bindings/power/r8a774b1-sysc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2019 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ #define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ diff --git a/include/dt-bindings/power/r8a774c0-sysc.h b/include/dt-bindings/power/r8a774c0-sysc.h index dd0cd656d90..9922d4c6f87 100644 --- a/include/dt-bindings/power/r8a774c0-sysc.h +++ b/include/dt-bindings/power/r8a774c0-sysc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2020 Renesas Electronics
[PATCH v2 1/1] cmd: ums: abort mounting by pressing any key
This patch introduses config which allows interrupt run of usb
mass storage with any key. This is especially useful on devices
with limited input capabilities like tablets and smatphones which
have only gpio keys in direct access.
Signed-off-by: Svyatoslav Ryhel
---
cmd/Kconfig| 6 ++
cmd/usb_mass_storage.c | 9 +
2 files changed, 15 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 4fe2c75de2..47d882e62f 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1536,6 +1536,12 @@ config CMD_USB_MASS_STORAGE
export a block device: U-Boot, the USB device, acts as a simple
external hard drive plugged on the host USB port.
+config CMD_UMS_ABORT_KEYED
+ bool "UMS abort with any key"
+ depends on CMD_USB_MASS_STORAGE
+ help
+ Allow interruption of usb mass storage run with any key pressed.
+
config CMD_PVBLOCK
bool "Xen para-virtualized block device"
depends on XEN
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index b7daaa6e8e..8a758b5884 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -231,6 +231,15 @@ static int do_usb_mass_storage(struct cmd_tbl *cmdtp, int
flag,
goto cleanup_register;
}
+ if (IS_ENABLED(CONFIG_CMD_UMS_ABORT_KEYED)) {
+ /* Abort by pressing any key */
+ if (getchar()) {
+ printf("\rOperation aborted.\n");
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
+ }
+ }
+
schedule();
}
--
2.25.1
[PATCH v2 0/1] CMD commands improvements
- add ability for 'ums' command to interrupt run of usb mass storage with any key. This is especially useful on devices with limited input capabilities like tablets and smatphones which have only gpio keys in direct access. Current implementation uses Kconfig entry. Changelog from V1 - 'continue' command commit was dropped as there already exists 'pause' command with same function. - UMS_ABORT_KEYED renamed to CMD_UMS_ABORT_KEYED Svyatoslav Ryhel (1): cmd: ums: abort mounting by pressing any key cmd/Kconfig| 6 ++ cmd/usb_mass_storage.c | 9 + 2 files changed, 15 insertions(+) -- 2.25.1
Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
Hi Simon, On Fri, 27 Jan 2023 at 00:45, Simon Glass wrote: > > Hi Jagan, > > On Thu, 26 Jan 2023 at 11:27, Jagan Teki wrote: > > > > Hi Simon, > > > > On Thu, 26 Jan 2023 at 23:34, Simon Glass wrote: > > > > > > Hi Jagan, > > > > > > On Thu, 26 Jan 2023 at 10:42, Jagan Teki wrote: > > > > > > > > On Thu, 26 Jan 2023 at 22:28, Jonas Karlman wrote: > > > > > > > > > > Hi Jagan, > > > > > On 2023-01-26 17:51, Jagan Teki wrote: > > > > > > Hi Jonas, > > > > > > > > > > > > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman wrote: > > > > > >> > > > > > >> Hi Jagan, > > > > > >> > > > > > >> On 2023-01-25 23:27, Jagan Teki wrote: > > > > > >>> This series support Rockchip RK3588. All the device tree files are > > > > > >>> synced from linux-next with the proper SHA1 mentioned in the > > > > > >>> commit > > > > > >>> messages. > > > > > >>> > > > > > >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot > > > > > >>> so > > > > > >>> it is failing to load ATF entry from SPL and hang. > > > > > >>> > > > > > >>> Verified below BL31 versions, > > > > > >>> bl31-v1.15 > > > > > >>> bl31-v1.21 > > > > > >>> bl31-v1.22 > > > > > >>> bl31-v1.23 > > > > > >>> bl31-v1.24 > > > > > >>> bl31-v1.25 > > > > > >>> bl31-v1.26 > > > > > >>> > > > > > >>> Rever-engineered with respect to rockchip u-boot by using the same > > > > > >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting > > > > > >>> but > > > > > >>> mainline showing the same issue. > > > > > >>> > > > > > >>> Log: > > > > > >>> > > > > > >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 > > > > > >>> ���3:44:34 +0530) > > > > > >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > > > > > >>> Size=4096MB > > > > > >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > > > > > >>> Size=4096MB > > > > > >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > > > > > >>> Size=4096MB > > > > > >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > > > > > >>> Size=4096MB > > > > > >>> change to F1: 528MHz > > > > > >>> change to F2: 1068MHz > > > > > >>> change to F3: 1560MHz > > > > > >>> change to F0: 2112MHz > > > > > >>> out > > > > > >>> > > > > > >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - > > > > > >>> 03:44:34 +0530) > > > > > >>> Trying to boot from MMC1 > > > > > >>> bl31_entry: atf_entry start > > > > > >>> << hang >> > > > > > >>> > > > > > >>> Any information on BL31 for RK3588 please share. > > > > > >> > > > > > >> I had a similar strange booing issue with RK3568 and mainline > > > > > >> U-Boot, > > > > > >> turned out to be related to all parts of ATF not being properly > > > > > >> loaded > > > > > >> into PMU SRAM. > > > > > >> > > > > > >> Using my series at [1] I managed to get ATF to be fully loaded into > > > > > >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out > > > > > >> that > > > > > >> the segment being loaded ended up corrupted. > > > > > >> > > > > > >> The use of 512 bytes alignment of the FIT helped mitigate that > > > > > >> issue. > > > > > >> Vendor U-Boot use a bounce buffer for all parts that is written > > > > > >> into > > > > > >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top > > > > > >> range). > > > > > >> > > > > > >> You can also find newer bl31 at [2], up to version v1.32. > > > > > >> > > > > > >> [1] > > > > > >> https://patchwork.ozlabs.org/project/uboot/list/?series=337891>>> > > > > > >> [2] > > > > > >> https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>> > > > > > > Thanks for the details. I did apply this set on the master. No > > > > > > change > > > > > > in the behavior, used BL31 and ddr from [2] as well as in > > > > > > rkbin/master. > > > > > > > > > > I did some tests on my Radxa ROCK 3 Model B with > > > > > CONFIG_SPL_FIT_SIGNATURE=y > > > > > and it looked like it failed to read data into memory, see below. > > > > > > > > > > It also looks like the sdhci compatible is not supported by the > > > > > driver. > > > > > Something that may need to be added to driver to properly read data? > > > > > > > > > > > > > > > DDR V1.09 a930779e06 typ 22/11/21-17:50:56 > > > > > LPDDR4X, 2112MHz > > > > > channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > > > > > Size=2048MB > > > > > channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > > > > > Size=2048MB > > > > > channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > > > > > Size=2048MB > > > > > channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > > > > > Size=2048MB > > > > > Manufacturer ID:0x6 > > > > > CH0 RX Vref:31.7%, TX Vref:21.8%,20.8% > > > > > CH1 RX Vref:31.7%, TX Vref:21.8%,21.8% > > > > > CH2 RX Vref:32.7%, TX Vref:22.8%,21.8% > > > > > CH3 RX Vref:32.7%, TX Vref:21.8%,20.8% > > > > > change to F1: 528MHz > > > > > change to F2: 1068MHz > > > > > change to F3: 1560MH
Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
On Fri, 27 Jan 2023 at 00:33, Jonas Karlman wrote: > > On 2023-01-26 19:26, Jagan Teki wrote: > > Hi Simon, > > > > On Thu, 26 Jan 2023 at 23:34, Simon Glass wrote: > >> > >> Hi Jagan, > >> > >> On Thu, 26 Jan 2023 at 10:42, Jagan Teki wrote: > >>> > >>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman wrote: > > Hi Jagan, > On 2023-01-26 17:51, Jagan Teki wrote: > > Hi Jonas, > > > > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman wrote: > >> > >> Hi Jagan, > >> > >> On 2023-01-25 23:27, Jagan Teki wrote: > >>> This series support Rockchip RK3588. All the device tree files are > >>> synced from linux-next with the proper SHA1 mentioned in the commit > >>> messages. > >>> > >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so > >>> it is failing to load ATF entry from SPL and hang. > >>> > >>> Verified below BL31 versions, > >>> bl31-v1.15 > >>> bl31-v1.21 > >>> bl31-v1.22 > >>> bl31-v1.23 > >>> bl31-v1.24 > >>> bl31-v1.25 > >>> bl31-v1.26 > >>> > >>> Rever-engineered with respect to rockchip u-boot by using the same > >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but > >>> mainline showing the same issue. > >>> > >>> Log: > >>> > >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 > >>> +0530) > >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > >>> Size=4096MB > >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > >>> Size=4096MB > >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > >>> Size=4096MB > >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > >>> Size=4096MB > >>> change to F1: 528MHz > >>> change to F2: 1068MHz > >>> change to F3: 1560MHz > >>> change to F0: 2112MHz > >>> out > >>> > >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 > >>> +0530) > >>> Trying to boot from MMC1 > >>> bl31_entry: atf_entry start > >>> << hang >> > >>> > >>> Any information on BL31 for RK3588 please share. > >> > >> I had a similar strange booing issue with RK3568 and mainline U-Boot, > >> turned out to be related to all parts of ATF not being properly loaded > >> into PMU SRAM. > >> > >> Using my series at [1] I managed to get ATF to be fully loaded into > >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that > >> the segment being loaded ended up corrupted. > >> > >> The use of 512 bytes alignment of the FIT helped mitigate that issue. > >> Vendor U-Boot use a bounce buffer for all parts that is written into > >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range). > >> > >> You can also find newer bl31 at [2], up to version v1.32. > >> > >> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891 [2] > >> https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>> > >> Thanks for the details. I did apply this set on the master. No change > > in the behavior, used BL31 and ddr from [2] as well as in > > rkbin/master. > > I did some tests on my Radxa ROCK 3 Model B with > CONFIG_SPL_FIT_SIGNATURE=y > and it looked like it failed to read data into memory, see below. > > It also looks like the sdhci compatible is not supported by the driver. > Something that may need to be added to driver to properly read data? > > > DDR V1.09 a930779e06 typ 22/11/21-17:50:56 > LPDDR4X, 2112MHz > channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > Size=2048MB > channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > Size=2048MB > channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > Size=2048MB > channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > Size=2048MB > Manufacturer ID:0x6 > CH0 RX Vref:31.7%, TX Vref:21.8%,20.8% > CH1 RX Vref:31.7%, TX Vref:21.8%,21.8% > CH2 RX Vref:32.7%, TX Vref:22.8%,21.8% > CH3 RX Vref:32.7%, TX Vref:21.8%,20.8% > change to F1: 528MHz > change to F2: 1068MHz > change to F3: 1560MHz > change to F0: 2112MHz > out > > U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +) > Trying to boot from MMC1 > ## Checking hash(es) for config config_1 ... OK > ## Checking hash(es) for Image atf_1 ... sha256 error! > Bad hash value for 'hash' hash node in 'atf_1' image node > mmc_load_image_raw_sector: mmc block read error > Trying to boot from MMC1 > ## Checking hash(es) for config config_1 ... OK > ## Checking hash(es) for Image atf_1 ... sha256 error! > Bad hash value for 'hash' hash node in 'atf_1' image node > >>> > >>>
Re: [PATCH v2 1/2] spl: spl_nor: add BOOT_DEVICE_NOR2 as alternative SPL_LOAD_IMAGE_METHOD
On Thu, Jan 19, 2023 at 04:28:21PM +0100, Mario Kicherer wrote: > Add BOOT_DEVICE_NOR2 as a second SPL_LOAD_IMAGE_METHOD to enable a > board-specific spl_nor_get_uboot_base() function to return an alternative > address in the NOR flash in case booting from BOOT_DEVICE_NOR fails. > > Signed-off-by: Mario Kicherer > --- > arch/arm/include/asm/spl.h | 1 + > arch/mips/include/asm/spl.h | 1 + > arch/riscv/include/asm/spl.h | 1 + > common/spl/spl_nor.c | 1 + > 4 files changed, 4 insertions(+) This breaks a lot of platforms, as it only covers a few of the cases where BOOT_DEVICE_NOR is listed. I would also really like to see how this ends up being used in the board specific case as I do wonder if we can't solve this some other way that won't have impact so many other platforms. Thanks! -- Tom signature.asc Description: PGP signature
Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
Hi Jagan, On Thu, 26 Jan 2023 at 11:27, Jagan Teki wrote: > > Hi Simon, > > On Thu, 26 Jan 2023 at 23:34, Simon Glass wrote: > > > > Hi Jagan, > > > > On Thu, 26 Jan 2023 at 10:42, Jagan Teki wrote: > > > > > > On Thu, 26 Jan 2023 at 22:28, Jonas Karlman wrote: > > > > > > > > Hi Jagan, > > > > On 2023-01-26 17:51, Jagan Teki wrote: > > > > > Hi Jonas, > > > > > > > > > > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman wrote: > > > > >> > > > > >> Hi Jagan, > > > > >> > > > > >> On 2023-01-25 23:27, Jagan Teki wrote: > > > > >>> This series support Rockchip RK3588. All the device tree files are > > > > >>> synced from linux-next with the proper SHA1 mentioned in the commit > > > > >>> messages. > > > > >>> > > > > >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so > > > > >>> it is failing to load ATF entry from SPL and hang. > > > > >>> > > > > >>> Verified below BL31 versions, > > > > >>> bl31-v1.15 > > > > >>> bl31-v1.21 > > > > >>> bl31-v1.22 > > > > >>> bl31-v1.23 > > > > >>> bl31-v1.24 > > > > >>> bl31-v1.25 > > > > >>> bl31-v1.26 > > > > >>> > > > > >>> Rever-engineered with respect to rockchip u-boot by using the same > > > > >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but > > > > >>> mainline showing the same issue. > > > > >>> > > > > >>> Log: > > > > >>> > > > > >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 > > > > >>> +0530) > > > > >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > > > > >>> Size=4096MB > > > > >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > > > > >>> Size=4096MB > > > > >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > > > > >>> Size=4096MB > > > > >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 > > > > >>> Size=4096MB > > > > >>> change to F1: 528MHz > > > > >>> change to F2: 1068MHz > > > > >>> change to F3: 1560MHz > > > > >>> change to F0: 2112MHz > > > > >>> out > > > > >>> > > > > >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 > > > > >>> +0530) > > > > >>> Trying to boot from MMC1 > > > > >>> bl31_entry: atf_entry start > > > > >>> << hang >> > > > > >>> > > > > >>> Any information on BL31 for RK3588 please share. > > > > >> > > > > >> I had a similar strange booing issue with RK3568 and mainline U-Boot, > > > > >> turned out to be related to all parts of ATF not being properly > > > > >> loaded > > > > >> into PMU SRAM. > > > > >> > > > > >> Using my series at [1] I managed to get ATF to be fully loaded into > > > > >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that > > > > >> the segment being loaded ended up corrupted. > > > > >> > > > > >> The use of 512 bytes alignment of the FIT helped mitigate that issue. > > > > >> Vendor U-Boot use a bounce buffer for all parts that is written into > > > > >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range). > > > > >> > > > > >> You can also find newer bl31 at [2], up to version v1.32. > > > > >> > > > > >> [1] > > > > >> https://patchwork.ozlabs.org/project/uboot/list/?series=337891>>> > > > > >> [2] > > > > >> https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>> > > > > > Thanks for the details. I did apply this set on the master. No change > > > > > in the behavior, used BL31 and ddr from [2] as well as in > > > > > rkbin/master. > > > > > > > > I did some tests on my Radxa ROCK 3 Model B with > > > > CONFIG_SPL_FIT_SIGNATURE=y > > > > and it looked like it failed to read data into memory, see below. > > > > > > > > It also looks like the sdhci compatible is not supported by the driver. > > > > Something that may need to be added to driver to properly read data? > > > > > > > > > > > > DDR V1.09 a930779e06 typ 22/11/21-17:50:56 > > > > LPDDR4X, 2112MHz > > > > channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > > > > Size=2048MB > > > > channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > > > > Size=2048MB > > > > channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > > > > Size=2048MB > > > > channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 > > > > Size=2048MB > > > > Manufacturer ID:0x6 > > > > CH0 RX Vref:31.7%, TX Vref:21.8%,20.8% > > > > CH1 RX Vref:31.7%, TX Vref:21.8%,21.8% > > > > CH2 RX Vref:32.7%, TX Vref:22.8%,21.8% > > > > CH3 RX Vref:32.7%, TX Vref:21.8%,20.8% > > > > change to F1: 528MHz > > > > change to F2: 1068MHz > > > > change to F3: 1560MHz > > > > change to F0: 2112MHz > > > > out > > > > > > > > U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +) > > > > Trying to boot from MMC1 > > > > ## Checking hash(es) for config config_1 ... OK > > > > ## Checking hash(es) for Image atf_1 ... sha256 error! > > > > Bad hash value for 'hash' hash node in 'atf_1' image node > > > > mmc_load_image_raw_sector: mmc block read error > > > > Trying to boot from MMC1 > > > > ## Checking
Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
On 2023-01-26 19:26, Jagan Teki wrote: > Hi Simon, > > On Thu, 26 Jan 2023 at 23:34, Simon Glass wrote: >> >> Hi Jagan, >> >> On Thu, 26 Jan 2023 at 10:42, Jagan Teki wrote: >>> >>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman wrote: Hi Jagan, On 2023-01-26 17:51, Jagan Teki wrote: > Hi Jonas, > > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman wrote: >> >> Hi Jagan, >> >> On 2023-01-25 23:27, Jagan Teki wrote: >>> This series support Rockchip RK3588. All the device tree files are >>> synced from linux-next with the proper SHA1 mentioned in the commit >>> messages. >>> >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so >>> it is failing to load ATF entry from SPL and hang. >>> >>> Verified below BL31 versions, >>> bl31-v1.15 >>> bl31-v1.21 >>> bl31-v1.22 >>> bl31-v1.23 >>> bl31-v1.24 >>> bl31-v1.25 >>> bl31-v1.26 >>> >>> Rever-engineered with respect to rockchip u-boot by using the same >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but >>> mainline showing the same issue. >>> >>> Log: >>> >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 >>> +0530) >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 >>> Size=4096MB >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 >>> Size=4096MB >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 >>> Size=4096MB >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 >>> Size=4096MB >>> change to F1: 528MHz >>> change to F2: 1068MHz >>> change to F3: 1560MHz >>> change to F0: 2112MHz >>> out >>> >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 >>> +0530) >>> Trying to boot from MMC1 >>> bl31_entry: atf_entry start >>> << hang >> >>> >>> Any information on BL31 for RK3588 please share. >> >> I had a similar strange booing issue with RK3568 and mainline U-Boot, >> turned out to be related to all parts of ATF not being properly loaded >> into PMU SRAM. >> >> Using my series at [1] I managed to get ATF to be fully loaded into >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that >> the segment being loaded ended up corrupted. >> >> The use of 512 bytes alignment of the FIT helped mitigate that issue. >> Vendor U-Boot use a bounce buffer for all parts that is written into >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range). >> >> You can also find newer bl31 at [2], up to version v1.32. >> >> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891 [2] >> https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>> >> Thanks for the details. I did apply this set on the master. No change > in the behavior, used BL31 and ddr from [2] as well as in > rkbin/master. I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y and it looked like it failed to read data into memory, see below. It also looks like the sdhci compatible is not supported by the driver. Something that may need to be added to driver to properly read data? DDR V1.09 a930779e06 typ 22/11/21-17:50:56 LPDDR4X, 2112MHz channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB Manufacturer ID:0x6 CH0 RX Vref:31.7%, TX Vref:21.8%,20.8% CH1 RX Vref:31.7%, TX Vref:21.8%,21.8% CH2 RX Vref:32.7%, TX Vref:22.8%,21.8% CH3 RX Vref:32.7%, TX Vref:21.8%,20.8% change to F1: 528MHz change to F2: 1068MHz change to F3: 1560MHz change to F0: 2112MHz out U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +) Trying to boot from MMC1 ## Checking hash(es) for config config_1 ... OK ## Checking hash(es) for Image atf_1 ... sha256 error! Bad hash value for 'hash' hash node in 'atf_1' image node mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 ## Checking hash(es) for config config_1 ... OK ## Checking hash(es) for Image atf_1 ... sha256 error! Bad hash value for 'hash' hash node in 'atf_1' image node >>> >>> Look like this is something wrong with your patch series or master >>> changes on binman, not with the driver. I have observed the same if I >>> enable CONFIG_SPL_FIT_SIGNATURE. >> >> There are some more changes in dm/master that I'm about to pull in. >> One of them from Jonas Karlman adds hash nodes so may be i
