Re: [PATCH] efi_selftests: fix protocol repeated selftesting
On 6/13/23 15:23, Ilias Apalodimas wrote: Running the protocols selftest more than one times fails with => setenv efi_selftest 'manage protocols' && bootefi selftest Testing EFI API implementation Selected test: 'manage protocols' Setting up 'manage protocols' Setting up 'manage protocols' succeeded Executing 'manage protocols' Executing 'manage protocols' succeeded Tearing down 'manage protocols' Tearing down 'manage protocols' succeeded Summary: 0 failures => bootefi selftest Testing EFI API implementation Selected test: 'manage protocols' Setting up 'manage protocols' lib/efi_selftest/efi_selftest_manageprotocols.c(88): ERROR: InstallProtocolInterface failed lib/efi_selftest/efi_selftest.c(89): ERROR: Setting up 'manage protocols' failed Tearing down 'manage protocols' Tearing down 'manage protocols' succeeded Summary: 1 failures The reason is that we don't set the handles to NULL after deleting and freeing them. As a result the subsequent protocol installation will try to use an existing handle which we just removed that from our object list. Signed-off-by: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt
Re: [PATCH 4/7] tools: mkeficapsule: Add support for parsing capsule params from config file
On Fri, Jun 16, 2023 at 10:37:01AM +0530, Sughosh Ganu wrote:
> hi Takahiro,
>
> On Fri, 16 Jun 2023 at 10:16, Takahiro Akashi
> wrote:
> >
> > Hi Sughosh,
> >
> > On Fri, Jun 16, 2023 at 09:56:33AM +0530, Sughosh Ganu wrote:
> > > On Thu, 15 Jun 2023 at 11:19, Takahiro Akashi
> > > wrote:
> > > >
> > > > On Thu, Jun 15, 2023 at 10:09:06AM +0530, Sughosh Ganu wrote:
> > > > > On Wed, 14 Jun 2023 at 11:23, Takahiro Akashi
> > > > > wrote:
> > > > > >
> > > > > > On Wed, Jun 14, 2023 at 10:56:23AM +0530, Sughosh Ganu wrote:
> > > > > > > hi Takahiro,
> > > > > > >
> > > > > > > On Wed, 14 Jun 2023 at 09:09, Takahiro Akashi
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > Hi Sughosh,
> > > > > > > >
> > > > > > > > I think this is a good extension to mkeficapsule, but
> > > > > > > >
> > > > > > > > On Tue, Jun 13, 2023 at 04:08:03PM +0530, Sughosh Ganu wrote:
> > > > > > > > > Add support for specifying the parameters needed for capsule
> > > > > > > > > generation through a config file, instead of passing them
> > > > > > > > > through
> > > > > > > > > command-line. Parameters for more than a single capsule file
> > > > > > > > > can be
> > > > > > > > > specified, resulting in generation of multiple capsules
> > > > > > > > > through a
> > > > > > > > > single invocation of the command.
> > > > > > > > >
> > > > > > > > > This path is to be used for generating capsules through a
> > > > > > > > > make target,
> > > > > > > > > with the parameters being parsed from the config file.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Sughosh Ganu
> > > > > > > > > ---
> > > > > > > > > tools/Kconfig | 9 +
> > > > > > > > > tools/Makefile | 1 +
> > > > > > > > > tools/eficapsule.h | 110
> > > > > > > > > tools/mkeficapsule.c | 106 +++-
> > > > > > > > > tools/mkeficapsule_parse.c | 345
> > > > > > > > > +
> > > > > > > > > 5 files changed, 531 insertions(+), 40 deletions(-)
> > > > > > > > > create mode 100644 tools/mkeficapsule_parse.c
> > > > > > > > >
> > > > > > > > > diff --git a/tools/Kconfig b/tools/Kconfig
> > > > > > > > > index 539708f277..95f27b7c45 100644
> > > > > > > > > --- a/tools/Kconfig
> > > > > > > > > +++ b/tools/Kconfig
> > > > > > > > > @@ -98,6 +98,15 @@ config TOOLS_MKEFICAPSULE
> > > > > > > > > optionally sign that file. If you want to enable UEFI
> > > > > > > > > capsule
> > > > > > > > > update feature on your target, you certainly need
> > > > > > > > > this.
> > > > > > > > >
> > > > > > > > > +config EFI_CAPSULE_CFG_FILE
> > > > > > > > > + string "Path to the EFI Capsule Config File"
> > > > > > > > > + default ""
> > > > > > > > > + help
> > > > > > > > > + Path to the EFI capsule config file which provides the
> > > > > > > > > + parameters needed to build capsule(s). Parameters can
> > > > > > > > > be
> > > > > > > > > + provided for multiple payloads resulting in
> > > > > > > > > corresponding
> > > > > > > > > + capsule images being generated.
> > > > > > > > > +
> > > > > > > > > menuconfig FSPI_CONF_HEADER
> > > > > > > > > bool "FlexSPI Header Configuration"
> > > > > > > > > help
> > > > > > > > > diff --git a/tools/Makefile b/tools/Makefile
> > > > > > > > > index d793cf3bec..ef366f3d61 100644
> > > > > > > > > --- a/tools/Makefile
> > > > > > > > > +++ b/tools/Makefile
> > > > > > > > > @@ -250,6 +250,7 @@ HOSTLDLIBS_mkeficapsule += \
> > > > > > > > > HOSTLDLIBS_mkeficapsule += \
> > > > > > > > > $(shell pkg-config --libs uuid 2> /dev/null || echo
> > > > > > > > > "-luuid")
> > > > > > > > > hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
> > > > > > > > > +mkeficapsule-objs := mkeficapsule.o mkeficapsule_parse.o
> > > > > > > > >
> > > > > > > > > # We build some files with extra pedantic flags to try to
> > > > > > > > > minimize things
> > > > > > > > > # that won't build on some weird host compiler -- though
> > > > > > > > > there are lots of
> > > > > > > > > diff --git a/tools/eficapsule.h b/tools/eficapsule.h
> > > > > > > > > index 072a4b5598..42e66c6d6a 100644
> > > > > > > > > --- a/tools/eficapsule.h
> > > > > > > > > +++ b/tools/eficapsule.h
> > > > > > > > > @@ -52,6 +52,38 @@ typedef struct {
> > > > > > > > > /* flags */
> > > > > > > > > #define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x0001
> > > > > > > > >
> > > > > > > > > +enum capsule_type {
> > > > > > > > > + CAPSULE_NORMAL_BLOB = 0,
> > > > > > > > > + CAPSULE_ACCEPT,
> > > > > > > > > + CAPSULE_REVERT,
> > > > > > > > > +};
> > > > > > > > > +
> > > > > > > > > +/**
> > > > > > > > > + * struct efi_capsule_params - Capsule parameters
> > > > > > > > > + * @image_guid: Guid value of the payload input image
> > > > > > > > > + * @image_index: Image index value
> > > > > > > > > + * @hardware_instance: Hardware instance to be used for the
> > > > > > > > >
Re: [PATCH 4/7] tools: mkeficapsule: Add support for parsing capsule params from config file
hi Takahiro,
On Fri, 16 Jun 2023 at 10:16, Takahiro Akashi
wrote:
>
> Hi Sughosh,
>
> On Fri, Jun 16, 2023 at 09:56:33AM +0530, Sughosh Ganu wrote:
> > On Thu, 15 Jun 2023 at 11:19, Takahiro Akashi
> > wrote:
> > >
> > > On Thu, Jun 15, 2023 at 10:09:06AM +0530, Sughosh Ganu wrote:
> > > > On Wed, 14 Jun 2023 at 11:23, Takahiro Akashi
> > > > wrote:
> > > > >
> > > > > On Wed, Jun 14, 2023 at 10:56:23AM +0530, Sughosh Ganu wrote:
> > > > > > hi Takahiro,
> > > > > >
> > > > > > On Wed, 14 Jun 2023 at 09:09, Takahiro Akashi
> > > > > > wrote:
> > > > > > >
> > > > > > > Hi Sughosh,
> > > > > > >
> > > > > > > I think this is a good extension to mkeficapsule, but
> > > > > > >
> > > > > > > On Tue, Jun 13, 2023 at 04:08:03PM +0530, Sughosh Ganu wrote:
> > > > > > > > Add support for specifying the parameters needed for capsule
> > > > > > > > generation through a config file, instead of passing them
> > > > > > > > through
> > > > > > > > command-line. Parameters for more than a single capsule file
> > > > > > > > can be
> > > > > > > > specified, resulting in generation of multiple capsules through
> > > > > > > > a
> > > > > > > > single invocation of the command.
> > > > > > > >
> > > > > > > > This path is to be used for generating capsules through a make
> > > > > > > > target,
> > > > > > > > with the parameters being parsed from the config file.
> > > > > > > >
> > > > > > > > Signed-off-by: Sughosh Ganu
> > > > > > > > ---
> > > > > > > > tools/Kconfig | 9 +
> > > > > > > > tools/Makefile | 1 +
> > > > > > > > tools/eficapsule.h | 110
> > > > > > > > tools/mkeficapsule.c | 106 +++-
> > > > > > > > tools/mkeficapsule_parse.c | 345
> > > > > > > > +
> > > > > > > > 5 files changed, 531 insertions(+), 40 deletions(-)
> > > > > > > > create mode 100644 tools/mkeficapsule_parse.c
> > > > > > > >
> > > > > > > > diff --git a/tools/Kconfig b/tools/Kconfig
> > > > > > > > index 539708f277..95f27b7c45 100644
> > > > > > > > --- a/tools/Kconfig
> > > > > > > > +++ b/tools/Kconfig
> > > > > > > > @@ -98,6 +98,15 @@ config TOOLS_MKEFICAPSULE
> > > > > > > > optionally sign that file. If you want to enable UEFI
> > > > > > > > capsule
> > > > > > > > update feature on your target, you certainly need this.
> > > > > > > >
> > > > > > > > +config EFI_CAPSULE_CFG_FILE
> > > > > > > > + string "Path to the EFI Capsule Config File"
> > > > > > > > + default ""
> > > > > > > > + help
> > > > > > > > + Path to the EFI capsule config file which provides the
> > > > > > > > + parameters needed to build capsule(s). Parameters can be
> > > > > > > > + provided for multiple payloads resulting in
> > > > > > > > corresponding
> > > > > > > > + capsule images being generated.
> > > > > > > > +
> > > > > > > > menuconfig FSPI_CONF_HEADER
> > > > > > > > bool "FlexSPI Header Configuration"
> > > > > > > > help
> > > > > > > > diff --git a/tools/Makefile b/tools/Makefile
> > > > > > > > index d793cf3bec..ef366f3d61 100644
> > > > > > > > --- a/tools/Makefile
> > > > > > > > +++ b/tools/Makefile
> > > > > > > > @@ -250,6 +250,7 @@ HOSTLDLIBS_mkeficapsule += \
> > > > > > > > HOSTLDLIBS_mkeficapsule += \
> > > > > > > > $(shell pkg-config --libs uuid 2> /dev/null || echo
> > > > > > > > "-luuid")
> > > > > > > > hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
> > > > > > > > +mkeficapsule-objs := mkeficapsule.o mkeficapsule_parse.o
> > > > > > > >
> > > > > > > > # We build some files with extra pedantic flags to try to
> > > > > > > > minimize things
> > > > > > > > # that won't build on some weird host compiler -- though there
> > > > > > > > are lots of
> > > > > > > > diff --git a/tools/eficapsule.h b/tools/eficapsule.h
> > > > > > > > index 072a4b5598..42e66c6d6a 100644
> > > > > > > > --- a/tools/eficapsule.h
> > > > > > > > +++ b/tools/eficapsule.h
> > > > > > > > @@ -52,6 +52,38 @@ typedef struct {
> > > > > > > > /* flags */
> > > > > > > > #define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x0001
> > > > > > > >
> > > > > > > > +enum capsule_type {
> > > > > > > > + CAPSULE_NORMAL_BLOB = 0,
> > > > > > > > + CAPSULE_ACCEPT,
> > > > > > > > + CAPSULE_REVERT,
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +/**
> > > > > > > > + * struct efi_capsule_params - Capsule parameters
> > > > > > > > + * @image_guid: Guid value of the payload input image
> > > > > > > > + * @image_index: Image index value
> > > > > > > > + * @hardware_instance: Hardware instance to be used for the
> > > > > > > > image
> > > > > > > > + * @monotonic_count: Monotonic count value to be used for
> > > > > > > > signed capsule
> > > > > > > > + * @privkey_file: Path to private key used in capsule signing
> > > > > > > > + * @cert_file: Path to public key certificate used in capsule
> > > > > > > > signing
> > > > > > > > + *
Re: [PATCH 4/7] tools: mkeficapsule: Add support for parsing capsule params from config file
Hi Sughosh,
On Fri, Jun 16, 2023 at 09:56:33AM +0530, Sughosh Ganu wrote:
> On Thu, 15 Jun 2023 at 11:19, Takahiro Akashi
> wrote:
> >
> > On Thu, Jun 15, 2023 at 10:09:06AM +0530, Sughosh Ganu wrote:
> > > On Wed, 14 Jun 2023 at 11:23, Takahiro Akashi
> > > wrote:
> > > >
> > > > On Wed, Jun 14, 2023 at 10:56:23AM +0530, Sughosh Ganu wrote:
> > > > > hi Takahiro,
> > > > >
> > > > > On Wed, 14 Jun 2023 at 09:09, Takahiro Akashi
> > > > > wrote:
> > > > > >
> > > > > > Hi Sughosh,
> > > > > >
> > > > > > I think this is a good extension to mkeficapsule, but
> > > > > >
> > > > > > On Tue, Jun 13, 2023 at 04:08:03PM +0530, Sughosh Ganu wrote:
> > > > > > > Add support for specifying the parameters needed for capsule
> > > > > > > generation through a config file, instead of passing them through
> > > > > > > command-line. Parameters for more than a single capsule file can
> > > > > > > be
> > > > > > > specified, resulting in generation of multiple capsules through a
> > > > > > > single invocation of the command.
> > > > > > >
> > > > > > > This path is to be used for generating capsules through a make
> > > > > > > target,
> > > > > > > with the parameters being parsed from the config file.
> > > > > > >
> > > > > > > Signed-off-by: Sughosh Ganu
> > > > > > > ---
> > > > > > > tools/Kconfig | 9 +
> > > > > > > tools/Makefile | 1 +
> > > > > > > tools/eficapsule.h | 110
> > > > > > > tools/mkeficapsule.c | 106 +++-
> > > > > > > tools/mkeficapsule_parse.c | 345
> > > > > > > +
> > > > > > > 5 files changed, 531 insertions(+), 40 deletions(-)
> > > > > > > create mode 100644 tools/mkeficapsule_parse.c
> > > > > > >
> > > > > > > diff --git a/tools/Kconfig b/tools/Kconfig
> > > > > > > index 539708f277..95f27b7c45 100644
> > > > > > > --- a/tools/Kconfig
> > > > > > > +++ b/tools/Kconfig
> > > > > > > @@ -98,6 +98,15 @@ config TOOLS_MKEFICAPSULE
> > > > > > > optionally sign that file. If you want to enable UEFI
> > > > > > > capsule
> > > > > > > update feature on your target, you certainly need this.
> > > > > > >
> > > > > > > +config EFI_CAPSULE_CFG_FILE
> > > > > > > + string "Path to the EFI Capsule Config File"
> > > > > > > + default ""
> > > > > > > + help
> > > > > > > + Path to the EFI capsule config file which provides the
> > > > > > > + parameters needed to build capsule(s). Parameters can be
> > > > > > > + provided for multiple payloads resulting in corresponding
> > > > > > > + capsule images being generated.
> > > > > > > +
> > > > > > > menuconfig FSPI_CONF_HEADER
> > > > > > > bool "FlexSPI Header Configuration"
> > > > > > > help
> > > > > > > diff --git a/tools/Makefile b/tools/Makefile
> > > > > > > index d793cf3bec..ef366f3d61 100644
> > > > > > > --- a/tools/Makefile
> > > > > > > +++ b/tools/Makefile
> > > > > > > @@ -250,6 +250,7 @@ HOSTLDLIBS_mkeficapsule += \
> > > > > > > HOSTLDLIBS_mkeficapsule += \
> > > > > > > $(shell pkg-config --libs uuid 2> /dev/null || echo
> > > > > > > "-luuid")
> > > > > > > hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
> > > > > > > +mkeficapsule-objs := mkeficapsule.o mkeficapsule_parse.o
> > > > > > >
> > > > > > > # We build some files with extra pedantic flags to try to
> > > > > > > minimize things
> > > > > > > # that won't build on some weird host compiler -- though there
> > > > > > > are lots of
> > > > > > > diff --git a/tools/eficapsule.h b/tools/eficapsule.h
> > > > > > > index 072a4b5598..42e66c6d6a 100644
> > > > > > > --- a/tools/eficapsule.h
> > > > > > > +++ b/tools/eficapsule.h
> > > > > > > @@ -52,6 +52,38 @@ typedef struct {
> > > > > > > /* flags */
> > > > > > > #define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x0001
> > > > > > >
> > > > > > > +enum capsule_type {
> > > > > > > + CAPSULE_NORMAL_BLOB = 0,
> > > > > > > + CAPSULE_ACCEPT,
> > > > > > > + CAPSULE_REVERT,
> > > > > > > +};
> > > > > > > +
> > > > > > > +/**
> > > > > > > + * struct efi_capsule_params - Capsule parameters
> > > > > > > + * @image_guid: Guid value of the payload input image
> > > > > > > + * @image_index: Image index value
> > > > > > > + * @hardware_instance: Hardware instance to be used for the image
> > > > > > > + * @monotonic_count: Monotonic count value to be used for signed
> > > > > > > capsule
> > > > > > > + * @privkey_file: Path to private key used in capsule signing
> > > > > > > + * @cert_file: Path to public key certificate used in capsule
> > > > > > > signing
> > > > > > > + * @input_file: Path to payload input image
> > > > > > > + * @capsule_file: Path to the output capsule file
> > > > > > > + * @oemflags: Oemflags to be populated in the capsule header
> > > > > > > + * @capsule: Capsule Type, normal or accept or revert
> > > > > > > + */
> > > > > > > +struct efi_capsule_params {
> > > > > > > + efi_guid_t
Re: [PATCH 4/7] tools: mkeficapsule: Add support for parsing capsule params from config file
On Thu, 15 Jun 2023 at 11:19, Takahiro Akashi
wrote:
>
> On Thu, Jun 15, 2023 at 10:09:06AM +0530, Sughosh Ganu wrote:
> > On Wed, 14 Jun 2023 at 11:23, Takahiro Akashi
> > wrote:
> > >
> > > On Wed, Jun 14, 2023 at 10:56:23AM +0530, Sughosh Ganu wrote:
> > > > hi Takahiro,
> > > >
> > > > On Wed, 14 Jun 2023 at 09:09, Takahiro Akashi
> > > > wrote:
> > > > >
> > > > > Hi Sughosh,
> > > > >
> > > > > I think this is a good extension to mkeficapsule, but
> > > > >
> > > > > On Tue, Jun 13, 2023 at 04:08:03PM +0530, Sughosh Ganu wrote:
> > > > > > Add support for specifying the parameters needed for capsule
> > > > > > generation through a config file, instead of passing them through
> > > > > > command-line. Parameters for more than a single capsule file can be
> > > > > > specified, resulting in generation of multiple capsules through a
> > > > > > single invocation of the command.
> > > > > >
> > > > > > This path is to be used for generating capsules through a make
> > > > > > target,
> > > > > > with the parameters being parsed from the config file.
> > > > > >
> > > > > > Signed-off-by: Sughosh Ganu
> > > > > > ---
> > > > > > tools/Kconfig | 9 +
> > > > > > tools/Makefile | 1 +
> > > > > > tools/eficapsule.h | 110
> > > > > > tools/mkeficapsule.c | 106 +++-
> > > > > > tools/mkeficapsule_parse.c | 345
> > > > > > +
> > > > > > 5 files changed, 531 insertions(+), 40 deletions(-)
> > > > > > create mode 100644 tools/mkeficapsule_parse.c
> > > > > >
> > > > > > diff --git a/tools/Kconfig b/tools/Kconfig
> > > > > > index 539708f277..95f27b7c45 100644
> > > > > > --- a/tools/Kconfig
> > > > > > +++ b/tools/Kconfig
> > > > > > @@ -98,6 +98,15 @@ config TOOLS_MKEFICAPSULE
> > > > > > optionally sign that file. If you want to enable UEFI
> > > > > > capsule
> > > > > > update feature on your target, you certainly need this.
> > > > > >
> > > > > > +config EFI_CAPSULE_CFG_FILE
> > > > > > + string "Path to the EFI Capsule Config File"
> > > > > > + default ""
> > > > > > + help
> > > > > > + Path to the EFI capsule config file which provides the
> > > > > > + parameters needed to build capsule(s). Parameters can be
> > > > > > + provided for multiple payloads resulting in corresponding
> > > > > > + capsule images being generated.
> > > > > > +
> > > > > > menuconfig FSPI_CONF_HEADER
> > > > > > bool "FlexSPI Header Configuration"
> > > > > > help
> > > > > > diff --git a/tools/Makefile b/tools/Makefile
> > > > > > index d793cf3bec..ef366f3d61 100644
> > > > > > --- a/tools/Makefile
> > > > > > +++ b/tools/Makefile
> > > > > > @@ -250,6 +250,7 @@ HOSTLDLIBS_mkeficapsule += \
> > > > > > HOSTLDLIBS_mkeficapsule += \
> > > > > > $(shell pkg-config --libs uuid 2> /dev/null || echo "-luuid")
> > > > > > hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
> > > > > > +mkeficapsule-objs := mkeficapsule.o mkeficapsule_parse.o
> > > > > >
> > > > > > # We build some files with extra pedantic flags to try to minimize
> > > > > > things
> > > > > > # that won't build on some weird host compiler -- though there are
> > > > > > lots of
> > > > > > diff --git a/tools/eficapsule.h b/tools/eficapsule.h
> > > > > > index 072a4b5598..42e66c6d6a 100644
> > > > > > --- a/tools/eficapsule.h
> > > > > > +++ b/tools/eficapsule.h
> > > > > > @@ -52,6 +52,38 @@ typedef struct {
> > > > > > /* flags */
> > > > > > #define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x0001
> > > > > >
> > > > > > +enum capsule_type {
> > > > > > + CAPSULE_NORMAL_BLOB = 0,
> > > > > > + CAPSULE_ACCEPT,
> > > > > > + CAPSULE_REVERT,
> > > > > > +};
> > > > > > +
> > > > > > +/**
> > > > > > + * struct efi_capsule_params - Capsule parameters
> > > > > > + * @image_guid: Guid value of the payload input image
> > > > > > + * @image_index: Image index value
> > > > > > + * @hardware_instance: Hardware instance to be used for the image
> > > > > > + * @monotonic_count: Monotonic count value to be used for signed
> > > > > > capsule
> > > > > > + * @privkey_file: Path to private key used in capsule signing
> > > > > > + * @cert_file: Path to public key certificate used in capsule
> > > > > > signing
> > > > > > + * @input_file: Path to payload input image
> > > > > > + * @capsule_file: Path to the output capsule file
> > > > > > + * @oemflags: Oemflags to be populated in the capsule header
> > > > > > + * @capsule: Capsule Type, normal or accept or revert
> > > > > > + */
> > > > > > +struct efi_capsule_params {
> > > > > > + efi_guid_t *image_guid;
> > > > > > + unsigned long image_index;
> > > > > > + unsigned long hardware_instance;
> > > > > > + uint64_t monotonic_count;
> > > > > > + char *privkey_file;
> > > > > > + char *cert_file;
> > > > > > + char *input_file;
> > > > > > + char *capsule_file;
> > > > > > +
Re: imx8m optee load address?
On 6/16/2023 9:56 AM, Tim Harvey wrote:
Greetings,
I've seen several IMX8M boards include a firmware/optee node in the
U-Boot dt (git grep optee arch/arm/dts/imx8m*.dtsi) yet but none that
I see configure binman to actually add the binary in the u-boot.dtsi,
do anything to keep U-Boot from accessing the OPTEE memory, or
document how to configure and build OPTEE for imx8m. I would like to
add such support but I find it odd that OPTEE needs to be built
differently depending on the dram size.
Prior to switching to binman (v2021.10)
arch/arm/mach-imx/mkimage_fit_atf.sh [1] would include tee.bin in the
FIT image if it was found in the current directory and it was expected
that you provide a proper TEE_LOAD_ADDR via the env (commit
a9eed6e1b8d8 ("imx: imx8m: introduce script to generate fit image").
According to the IMX OPTEE documentation [2] the size and location of
OPTEE is hard coded (CFG_TZDRAM_START and CFG_TZDRAM_SIZE) but looking
at the imx-optee source [3] this is calculated based off of
CFG_DDR_SIZE (which you can provide via env at build time or just
provide CFG_TZDRAM_START and CFG_TZDRAM_SIZE via env directly).
optee does not support PIE, it could only run at the address that built
time defined.
And the TZASC needs following it to protect the region properly.
This results in the OPTEE location of 0x7e00 for 1GiB systems,
0xbe00 for 2GiB systems, and 0x13e00 for 4GiB systems for
example. This dependence on dram size causes a couple of issues:
- OPTEE location depends on build-time configuration and several
boards have run-time identification of their memory size
- for 4GiB systems the address 0x13e00 crosses the 32bit address
boundary and U-Boot hangs
imx optee seems has this. But for overlapping with U-Boot, I doubt that.
Is there any reason OPTEE can't be located wherever you want and not
depend on dram size?
You could , just modify the imx *.mk file per my recall.
I've tried to set it to 0x7e00 (for a 1GiB
board) on a 4GiB board and U-Boot hangs near the DRAM banner which is
likely due to get_ram_size() stepping on OPTEE's memory range but then
You may give a try to disable TZASC settings in OP-TEE first.
And you also need to carve out the memory of OP-TEE from U-Boot MMU
to avoid prefetch.
I'm not clear why that doesn't occur when OPTEE is located at the top
of dram on a 1GiB and 2GiB system. How would I go about adding a
carevout for this?
Are u using upstream optee or NXP downstream optee release?
Regards,
Peng.
Best Regards,
Tim
[1]
https://elixir.bootlin.com/u-boot/v2021.10/source/arch/arm/mach-imx/mkimage_fit_atf.sh
[2] https://www.nxp.com/docs/en/user-guide/IMX_PORTING_GUIDE.pdf
[3] https://github.com/nxp-imx/imx-optee-os
imx8m optee load address?
Greetings,
I've seen several IMX8M boards include a firmware/optee node in the
U-Boot dt (git grep optee arch/arm/dts/imx8m*.dtsi) yet but none that
I see configure binman to actually add the binary in the u-boot.dtsi,
do anything to keep U-Boot from accessing the OPTEE memory, or
document how to configure and build OPTEE for imx8m. I would like to
add such support but I find it odd that OPTEE needs to be built
differently depending on the dram size.
Prior to switching to binman (v2021.10)
arch/arm/mach-imx/mkimage_fit_atf.sh [1] would include tee.bin in the
FIT image if it was found in the current directory and it was expected
that you provide a proper TEE_LOAD_ADDR via the env (commit
a9eed6e1b8d8 ("imx: imx8m: introduce script to generate fit image").
According to the IMX OPTEE documentation [2] the size and location of
OPTEE is hard coded (CFG_TZDRAM_START and CFG_TZDRAM_SIZE) but looking
at the imx-optee source [3] this is calculated based off of
CFG_DDR_SIZE (which you can provide via env at build time or just
provide CFG_TZDRAM_START and CFG_TZDRAM_SIZE via env directly).
This results in the OPTEE location of 0x7e00 for 1GiB systems,
0xbe00 for 2GiB systems, and 0x13e00 for 4GiB systems for
example. This dependence on dram size causes a couple of issues:
- OPTEE location depends on build-time configuration and several
boards have run-time identification of their memory size
- for 4GiB systems the address 0x13e00 crosses the 32bit address
boundary and U-Boot hangs
Is there any reason OPTEE can't be located wherever you want and not
depend on dram size? I've tried to set it to 0x7e00 (for a 1GiB
board) on a 4GiB board and U-Boot hangs near the DRAM banner which is
likely due to get_ram_size() stepping on OPTEE's memory range but then
I'm not clear why that doesn't occur when OPTEE is located at the top
of dram on a 1GiB and 2GiB system. How would I go about adding a
carevout for this?
Best Regards,
Tim
[1]
https://elixir.bootlin.com/u-boot/v2021.10/source/arch/arm/mach-imx/mkimage_fit_atf.sh
[2] https://www.nxp.com/docs/en/user-guide/IMX_PORTING_GUIDE.pdf
[3] https://github.com/nxp-imx/imx-optee-os
Re: [PATCH v2] mx8m: csf.sh: use vars for keys to avoid file edits when signing
On 6/15/2023 11:21 PM, Tim Harvey wrote:
Caution: This is an external email. Please take care when clicking links or
opening attachments. When in doubt, report the message using the 'Report this
email' button
The csf_spl.txt and csf_fit.txt templates contain file paths which must
be edited for the location of your NXP CST generated key files.
Streamline the process of signing an image by assigning unique var names
to these which can be expended from env variables in the csf.sh script.
The following vars are used:
SRK_TABLE - full path to SRK_1_2_3_4_table.bin
CSF_KEY - full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem
IMG_KEY - full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem
Additionally provide an example of running the csf.sh script.
Signed-off-by: Tim Harvey
Reviewed-by: Fabio Estevam
---
v2:
- fix typo: s/SKK_TABLE/SRK_TABLE
- add Fabio's rb tag
---
doc/imx/habv4/csf_examples/mx8m/csf.sh| 21 +++
doc/imx/habv4/csf_examples/mx8m/csf_fit.txt | 12 +--
doc/imx/habv4/csf_examples/mx8m/csf_spl.txt | 12 +--
doc/imx/habv4/guides/mx8m_spl_secure_boot.txt | 10 +
4 files changed, 43 insertions(+), 12 deletions(-)
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh
b/doc/imx/habv4/csf_examples/mx8m/csf.sh
index 7a9a05e63392..c4e610adf1c4 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf.sh
+++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh
@@ -22,6 +22,27 @@
cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp
cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp
+# update File Paths from env vars
+if ! [ -r $CSF_KEY ]; then
+ echo "Error: \$CSF_KEY not found"
+ exit 1
+fi
+if ! [ -r $IMG_KEY ]; then
+ echo "Error: \$IMG_KEY not found"
+ exit 1
+fi
+if ! [ -r $SRK_TABLE ]; then
+ echo "Error: \$SRK_TABLE not found"
+ exit 1
+fi
+sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp
+sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp
+sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp
+sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp
+sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp
+sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp
+
+# update SPL Blocks
spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/
s@.*=@@p" .config) - 0x40)) )
spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin))
sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size
\"flash.bin\"@" csf_spl.tmp
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
index cd1d4070a5e5..dfcfb777c248 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
@@ -7,21 +7,21 @@
Signature Format = CMS
[Install SRK]
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin"
+ # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
+ File = "$SRK_TABLE"
Source index = 0
[Install CSFK]
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+ # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
+ File = "$CSF_KEY"
[Authenticate CSF]
[Install Key]
Verification index = 0
Target Index = 2
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+ # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
+ File = "$IMG_KEY"
[Authenticate Data]
Verification index = 2
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
index 00e34f6b1b95..88fa420a5fa0 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
@@ -7,13 +7,13 @@
Signature Format = CMS
[Install SRK]
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin"
+ # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
+ File = "$SRK_TABLE"
Source index = 0
[Install CSFK]
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+ # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
+ File = "$CSF_KEY"
[Authenticate CSF]
@@ -24,8 +24,8 @@
[Install Key]
Verification index = 0
Target Index = 2
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+ # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
+ File = "$IMG_KEY"
[Authenticate Data]
Verification index = 2
diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
index 3e3d38440f94..e789bae55940 100644
--- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
@@ -251,6 +251,16 @@ dd if=csf_fit.bin of=flash.bin bs=1
seek=${csf_block_offset} conv=notrunc
```
The entire script is available in
Re: [PATCH] menu: Re-enable the ANSI codes
On 6/13/2023 4:14 AM, Simon Glass wrote:
Caution: This is an external email. Please take care when clicking links or
opening attachments. When in doubt, report the message using the 'Report this
email' button
The intent here was to allow ANSI codes to be disabled, since it was
proving impoosible to test operation of the menu code when it kept moving
the cursor. Unfortunately this ended up in the patch.
Typo: impoosible->impossible.
Correct this by enabling ANSI again.
Signed-off-by: Simon Glass
Reported-by: Pali Rohár
Reported-by: Mark Kettenis
Reported-by: Frank Wunderlich
Fixes: 32bab0eae51b ("menu: Make use of CLI character processing")
---
common/menu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/menu.c b/common/menu.c
index 94514177e4e9..b55cf7b99967 100644
--- a/common/menu.c
+++ b/common/menu.c
@@ -15,7 +15,7 @@
#include "menu.h"
-#define ansi 0
+#define ansi 1
/*
* Internally, each item in a menu is represented by a struct menu_item.
--
2.41.0.162.gfafddb0af9-goog
Re: [PATCH 5/7] arch: arm: dts: ls1046a: tag serial nodes with bootph-all
On 6/15/2023 8:37 PM, Camelia Groza wrote:
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all".
Add fsl-ls1046a-u-boot.dtsi for U-Boot specific changes.
Thanks,
Peng.
Signed-off-by: Camelia Groza
---
arch/arm/dts/fsl-ls1046a.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 9fdd398e2c4c..3986360c0c93 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -227,6 +227,7 @@
interrupts = ;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ bootph-all;
};
duart1: serial@21c0600 {
@@ -235,6 +236,7 @@
interrupts = ;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ bootph-all;
};
duart2: serial@21d0500 {
@@ -243,6 +245,7 @@
interrupts = ;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ bootph-all;
};
duart3: serial@21d0600 {
@@ -251,6 +254,7 @@
interrupts = ;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ bootph-all;
};
lpuart0: serial@295 {
--
2.17.1
Re: [PATCH 4/7] arch: arm: dts: ls1046a: sync serial nodes with Linux
On 6/15/2023 8:37 PM, Camelia Groza wrote:
Pick up the serial node descriptions from Linux for the ls1046ardb and
ls1046afrwy boards and their dependencies. Including the
fsl,qoriq-clockgen.h and arm-gic.h headers forces us to change the include
directives to explicitly go through the C preprocessor for all boards in
the ls1046a SoC family.
Add the tag or commit of linux kernel.
Regards,
Peng.
Signed-off-by: Camelia Groza
---
arch/arm/dts/fsl-ls1046a-frwy.dts | 22 +-
arch/arm/dts/fsl-ls1046a-qds.dtsi | 2 +-
arch/arm/dts/fsl-ls1046a-rdb.dts | 14 +-
arch/arm/dts/fsl-ls1046a.dtsi | 24 +++-
4 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts
b/arch/arm/dts/fsl-ls1046a-frwy.dts
index cda05411d881..f3ba2acd6d51 100644
--- a/arch/arm/dts/fsl-ls1046a-frwy.dts
+++ b/arch/arm/dts/fsl-ls1046a-frwy.dts
@@ -7,17 +7,37 @@
*/
/dts-v1/;
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
/ {
model = "LS1046A FRWY Board";
aliases {
spi0 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
status = "okay";
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi
index fec5c8ddb23a..d66824975c5e 100644
--- a/arch/arm/dts/fsl-ls1046a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -7,7 +7,7 @@
* Mingkai Hu
*/
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
/ {
model = "LS1046A QDS Board";
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index 464129291c91..66d718905c7d 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -9,17 +9,29 @@
*/
/dts-v1/;
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
/ {
model = "LS1046A RDB Board";
aliases {
spi0 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
status = "okay";
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 060dc399c2f6..9fdd398e2c4c 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -8,7 +8,9 @@
* Mingkai Hu
*/
-/include/ "skeleton64.dtsi"
+#include "skeleton64.dtsi"
+#include
+#include
/ {
compatible = "fsl,ls1046a";
@@ -222,29 +224,33 @@
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
- interrupts = <0 54 0x4>;
- clocks = < 4 0>;
+ interrupts = ;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
};
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
- interrupts = <0 54 0x4>;
- clocks = < 4 0>;
+ interrupts = ;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
};
duart2: serial@21d0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0500 0x0 0x100>;
- interrupts = <0 55 0x4>;
- clocks = < 4 0>;
+ interrupts = ;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
};
duart3: serial@21d0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0600 0x0 0x100>;
- interrupts = <0 55 0x4>;
- clocks = < 4 0>;
+ interrupts = ;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
};
lpuart0: serial@295 {
Re: [PATCH 2/7] arch: arm: dts: ls1043a: tag serial nodes with bootph-all
On 6/15/2023 8:37 PM, Camelia Groza wrote:
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all".
Please add fsl-ls1043a-u-boot.dtsi for U-Boot specific changes.
Regards,
Peng.
Signed-off-by: Camelia Groza
---
arch/arm/dts/fsl-ls1043a.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 21643a1d951f..79f67e7183c3 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -227,6 +227,7 @@
interrupts = <0 54 0x4>;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ bootph-all;
};
duart1: serial@21c0600 {
@@ -235,6 +236,7 @@
interrupts = <0 54 0x4>;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ bootph-all;
};
duart2: serial@21d0500 {
@@ -243,6 +245,7 @@
interrupts = <0 55 0x4>;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ bootph-all;
};
duart3: serial@21d0600 {
@@ -251,6 +254,7 @@
interrupts = <0 55 0x4>;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ bootph-all;
};
lpuart0: serial@295 {
--
2.17.1
Re: [PATCH 1/7] arch: arm: dts: ls1043a: sync serial nodes with Linux
On 6/15/2023 8:37 PM, Camelia Groza wrote:
Pick up the serial node descriptions from Linux for the ls1043ardb board
and its dependencies. Including the fsl,qoriq-clockgen.h and arm-gic.h
headers forces us to change the include directives to explicitly go through
the C preprocessor for all boards in the ls1043a SoC family.
Better add the tag or commit of linux kernel that you sync from.
Other than that, Acked-by: Peng Fan
Signed-off-by: Camelia Groza
---
arch/arm/dts/fsl-ls1043a-qds.dtsi | 2 +-
arch/arm/dts/fsl-ls1043a-rdb.dts | 6 +-
arch/arm/dts/fsl-ls1043a.dtsi | 16 +++-
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 884bdad196b3..5e02cd91d75f 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -7,7 +7,7 @@
* Mingkai Hu
*/
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
index 9e7c79fd2b98..f5b3bb68b3db 100644
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -9,13 +9,17 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
aliases {
spi1 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
};
};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 4960973a6035..21643a1d951f 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -8,7 +8,9 @@
* Mingkai Hu
*/
-/include/ "skeleton64.dtsi"
+#include "skeleton64.dtsi"
+#include
+#include
/ {
compatible = "fsl,ls1043a";
@@ -223,28 +225,32 @@
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <0 54 0x4>;
- clocks = < 4 0>;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(1)>;
};
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <0 54 0x4>;
- clocks = < 4 0>;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(1)>;
};
duart2: serial@21d0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0500 0x0 0x100>;
interrupts = <0 55 0x4>;
- clocks = < 4 0>;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(1)>;
};
duart3: serial@21d0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0600 0x0 0x100>;
interrupts = <0 55 0x4>;
- clocks = < 4 0>;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(1)>;
};
lpuart0: serial@295 {
Re: [PATCH] board_f: Relocate fdt if SKIP_RELOC and fdt is in bss
Hi Simon,
Thank you for your comment.
On 2023/06/13 6:17, Simon Glass wrote:
Hi Kunihiko,
On Thu, 8 Jun 2023 at 07:53, Kunihiko Hayashi
wrote:
There are cases that the devicetree blob is placed after _end, such as
fdt_find_separate() returns _end. This is in bss area cleared before
relocation.
When GD_FLG_SKIP_RELOC is set, the blob is still in bss, but will be
cleared. As a result, the devicetree become invalid.
To avoid this issue, should relocate it to the new fdt area using the
latter condition in reloc_fdt().
Signed-off-by: Kunihiko Hayashi
---
common/board_f.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/common/board_f.c b/common/board_f.c
index 51d2f3c365e9..9a245872d190 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -622,7 +622,8 @@ static int init_post(void)
static int reloc_fdt(void)
{
if (!IS_ENABLED(CONFIG_OF_EMBED)) {
- if (gd->flags & GD_FLG_SKIP_RELOC)
+ if (gd->flags & GD_FLG_SKIP_RELOC &&
+ gd->fdt_blob != &_end)
!IS_ENABLED(CONFIG_OF_EMBED) == IS_ENABLED(CONFIG_OF_SEPARATE)
reloc_fdt() is only called by U-Boot (not SP)
So the FDT was found by fdt_find_separate() and gd->fdt_blob == &_end
So, is there any case where:
gd->flags & GD_FLG_SKIP_RELO is true
gd->fdt_blob != &_end is true
?
Yes. But in fact,
if (gd->flags & GD_FLG_SKIP_RELOC is true) and (gd->fdt_blob overlaps .bss
section),
the fdt should be relocated because clear_bss() will clear the fdt after that.
I can't think of one.
If that is the case, then you could add a comment to this effect and
unconditionally relocate if !CONFIG_OF_EMBED.
I'm not sure if it is possible to unconditionally relocate the fdt,
I think we need to know if the fdt overlaps .bss section.
Of course the down size is that you would probably rather relocate it
to just after BSS (rather than to the top of memory) but it doesn't
much matter, I suspect.
Thank you,
---
Best Regards
Kunihiko Hayashi
Re: [GIT PULL] please pull fsl-qoriq-2023-6-15 for next
On Thu, Jun 15, 2023 at 09:46:48AM +, Peng Fan wrote: > Hi Tom, > > Please pull fsl-qoriq-2023-6-15 for next. > Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] usb: dwc3: core: fix clk_get_rate returning negative value
On 6/15/23 16:59, Eugen Hristev wrote:
Unlike it's Linux counterpart, clk_get_rate can return a negative value, -ve.
The driver does not take that into account, stores the rate into
an unsigned long, and if clk_get_rate fails, it will take into consideration
the actual value and wrongly program the hardware.
E.g. on error -2 (no such entry), the rate will be 18446744073709551614
and this will be subsequently used by the driver to program the DWC3
To fix this, exit the function if the value is negative.
Fixes: 6bae0eb5b8bd ("usb: dwc3: Calculate REFCLKPER based on reference clock")
Signed-off-by: Eugen Hristev
---
drivers/usb/dwc3/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 49f6a1900b01..5a8c29424578 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -138,7 +138,7 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc)
if (dwc->ref_clk) {
rate = clk_get_rate(dwc->ref_clk);
This ^ assigns to unsigned long .
Please just change the data type of the $rate to 'long' (drop the unsigned).
- if (!rate)
+ if (!rate || (long)rate < 0)
if (rate <= 0) will work too ^
Re: Trying to boot custom kernel on Wink Hub (i.MX28)
Hi Rogan, On Thu, Jun 15, 2023 at 9:00 AM Rogan Dawes wrote: > > Hi folks, > > I am trying to boot a custom kernel on a Wink Hub v1, which has an i.MX28 > CPU, and is running U-Boot (U-Boot 2014.01-14400-gda781c6-dirty (Apr 30 > 2014 - 22:35:38)). > > I have tried compiling my own modern kernel and putting it in place of the > vendor (Linux version 2.6.35.3-flex-dvt) kernel on the flash chip, but when > loading, I simply get the expected U-Boot loading messages, but then > nothing at all from the serial port after that. > > I'm trying to figure out where my problem is most likely to be. As far as I > am aware from long-ago poking at U-Boot, the way that U-Boot passes > arguments to the kernel has changed recently? Previously it was ATAGS, and > now it expects a Device Tree Blob? Might this explain the failure to boot > that I am seeing? And yes, I understand that given that Yes, to boot a modern kernel, you need to generate a devicetree for the Wink Hubv1 board. Then you build it and generate a .dtb file. To boot zImage + dtb using an old bootloader that does not support booting dtb, you would need to select the following options in the kernel: CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y And then: cat arch/arm/boot/zImage arch/arm/boot/dts/imx28-wink-hub-v1.dtb > zImage_with_dtb And then boot zImage_with_dtb as you do with 2.6.35. Ideally, you should also port a modern U-Boot version, which supports dtb by default and then you don't need the steps above. Take a look at board/freescale/mx28eevk support for a reference. Regards, Fabio Estevam
[PATCH v4 2/2] usb: musb-new: sunxi: clarify the purpose of SRAM initialization
This is largely a cosmetic change, with one functional distinction:
We are now only setting BIT(0), and no longer clearing BIT(1).
The A20 manual confirms the purpose and bitwidth of this field, and we
have also been doing it this way for a while in Linux-land: The prior
narrative about this initialization being about configuring a FIFO has
pretty much been debunked for years now.
Signed-off-by: Sam Edwards
Reviewed-by: Andre Przywara
---
drivers/usb/musb-new/sunxi.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index a67eaf..a8b1a8f870 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -171,15 +171,22 @@ static void USBC_ForceVbusValidToHigh(__iomem void *base)
musb_writel(base, USBC_REG_o_ISCR, reg_val);
}
-static void USBC_ConfigFIFO_Base(void)
-{
- u32 reg_value;
+/**
+ * Non-USBC register access needed for initialization
+
**/
- /* config usb fifo, 8kb mode */
- reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
- reg_value &= ~(0x03 << 0);
- reg_value |= BIT(0);
- writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
+/*
+ * A10(s), A13, GR8, A20:
+ * switch ownership of SRAM block 'D' to the USB-OTG controller
+ */
+static void sunxi_musb_claim_sram(uintptr_t syscon_base)
+{
+ /*
+* BIT(0) of SRAM_CTRL_REG1 (syscon+0x04) controls SRAM-D ownership:
+* '0' -> exclusive access by CPU
+* '1' -> exclusive access by USB0
+*/
+ setbits_le32(syscon_base + 0x04, BIT(0));
}
/**
@@ -313,7 +320,13 @@ static int sunxi_musb_init(struct musb *musb)
musb->isr = sunxi_musb_interrupt;
if (glue->cfg->has_sram) {
- USBC_ConfigFIFO_Base();
+ /*
+* This is an older USB-OTG controller that Allwinner did not
+* endow with a dedicated SRAM block; it instead uses SRAM
+* block 'D', ownership of which needs to be handed over by
+* the CPU
+*/
+ sunxi_musb_claim_sram(SUNXI_SRAMC_BASE);
}
USBC_EnableDpDmPullUp(musb->mregs);
--
2.39.2
[PATCH v4 1/2] usb: musb-new: sunxi: only perform SRAM initialization when necessary
Only the older (ca. A10, A20) sunxis need this poke for the MUSB to
function. Mimic the Linux kernel and add a `has_sram` flag to the config
structure that is only set for the specific compatibles that require
this initialization.
Signed-off-by: Sam Edwards
Reviewed-by: Andre Przywara
Tested-by: Andre Przywara
---
drivers/usb/musb-new/sunxi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index c5c63249aa..a67eaf 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -83,6 +83,7 @@
struct sunxi_musb_config {
struct musb_hdrc_config *config;
+ bool has_sram;
};
struct sunxi_glue {
@@ -311,7 +312,10 @@ static int sunxi_musb_init(struct musb *musb)
musb->isr = sunxi_musb_interrupt;
- USBC_ConfigFIFO_Base();
+ if (glue->cfg->has_sram) {
+ USBC_ConfigFIFO_Base();
+ }
+
USBC_EnableDpDmPullUp(musb->mregs);
USBC_EnableIdPullUp(musb->mregs);
@@ -517,6 +521,7 @@ static int musb_usb_remove(struct udevice *dev)
static const struct sunxi_musb_config sun4i_a10_cfg = {
.config = _config,
+ .has_sram = true,
};
static const struct sunxi_musb_config sun6i_a31_cfg = {
--
2.39.2
[PATCH v4 0/2] sunxi, usb: Clean up SRAM initialization code
Hi list, Only change from v4 is that I reworded the commit message in 2/2 not to mention the TODO comment block that I removed in v3. Cheers, Sam Sam Edwards (2): usb: musb-new: sunxi: only perform SRAM initialization when necessary usb: musb-new: sunxi: clarify the purpose of SRAM initialization drivers/usb/musb-new/sunxi.c | 36 +++- 1 file changed, 27 insertions(+), 9 deletions(-) -- 2.39.2
Re: [PATCH] riscv: add backtrace support
On 6/14/23 10:15 AM, Ben Dooks wrote: On 14/06/2023 07:25, Bo Gan wrote: On 5/25/23 4:05 AM, Ben Dooks wrote: On 15/05/2023 14:03, Ben Dooks wrote: When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous function (RA) may not have been the culprit. Since this adds size to the build, do not add it by default and avoid putting it in the SPL build if not needed. Hi, has anyone had time to review this? Hi Ben, this looks really useful. I'd like to use it in SPL, but I'm unable to enable CONFIG_SPL_FRAMEPOINTER=y. It's likely that you need to add a SPL_FRAMEPOINTER entry to Kconfig as well. I will have a look at this, but testing may not be easy as the setup we're using has limited SPL space. I did a hack (duplicate `config FRAMEPOINTER` to `config SPL_FRAMEPOINTER`) --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -63,6 +63,24 @@ config SPL_SYS_DCACHE_OFF +config SPL_FRAMEPOINTER + bool "Build with frame pointer for stack unwinding" + depends on SPL + help + Choose this option to use the frame pointer so the stack can be + unwound if needed. This is useful for tracing where faults came + from as the source may be several functions back + + If you say Y here, then the code size will be increased due to + having to store the fp. + This is sufficient for enabling CONFIG_SPL_FRAMEPOINTER=y. With this, I tested SPL on JH7110 (VisionFive 2), and observed your patch's working: Unhandled exception: Load access fault EPC: 0800335e RA: 080033e8 TVAL: 0040 SP: 080ff5b0 GP: 080dbda0 TP: T0: 080ffb20 T1: 0020 T2: S0: 080ffb20 S1: 080ff6d0 A0: A1: 080ff6d0 A2: 08020d83 A3: 080ffb20 A4: 0025 A5: 08040218 A6: 0020 A7: 0800 S2: 0013 S3: 0001 S4: 4000 S5: 0001 S6: 000a S7: 080ffb88 S8: 0200 S9: 0801bc60 S10: 080fff38 S11: T3: 0023 T4: 0006 T5: 0001869f T6: 080dd138 backtrace: backtrace 0: FP: 080ffb20 RA: 08005888 backtrace 1: FP: 080ffb80 RA: 08007046 backtrace 2: FP: 080ffc50 RA: 080024ec backtrace 3: FP: 080ffd00 RA: 080028e0 backtrace 4: FP: 080ffe00 RA: 08002cf6 backtrace 5: FP: 080fff30 RA: 08002144 backtrace 6: FP: 0810 RA: 08000178 Code: 6797 0002 b783 1ba7 050e 953e 6108 6422 (613c) Looks like you just need a `config SPL_FRAMEPOINTER` entry in Kconfig.
Re: [PATCH] menu: Re-enable the ANSI codes
On Thursday 15 June 2023 13:34:09 Simon Glass wrote:
> Hi Pali,
>
> On Mon, 12 Jun 2023 at 22:33, Pali Rohár wrote:
> >
> > On Monday 12 June 2023 22:17:48 Simon Glass wrote:
> > > Hi Pali,
> > >
> > > On Mon, 12 Jun 2023 at 21:22, Pali Rohár wrote:
> > > >
> > > > On Monday 12 June 2023 21:14:32 Simon Glass wrote:
> > > > > The intent here was to allow ANSI codes to be disabled, since it was
> > > > > proving impoosible to test operation of the menu code when it kept
> > > > > moving
> > > > > the cursor. Unfortunately this ended up in the patch.
> > > > >
> > > > > Correct this by enabling ANSI again.
> > > > >
> > > > > Signed-off-by: Simon Glass
> > > > > Reported-by: Pali Rohár
> > > > > Reported-by: Mark Kettenis
> > > > > Reported-by: Frank Wunderlich
> > > > > Fixes: 32bab0eae51b ("menu: Make use of CLI character processing")
> > > > > ---
> > > > >
> > > > > common/menu.c | 2 +-
> > > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/common/menu.c b/common/menu.c
> > > > > index 94514177e4e9..b55cf7b99967 100644
> > > > > --- a/common/menu.c
> > > > > +++ b/common/menu.c
> > > > > @@ -15,7 +15,7 @@
> > > > >
> > > > > #include "menu.h"
> > > > >
> > > > > -#define ansi 0
> > > > > +#define ansi 1
> > > > >
> > > > > /*
> > > > > * Internally, each item in a menu is represented by a struct
> > > > > menu_item.
> > > > > --
> > > > > 2.41.0.162.gfafddb0af9-goog
> > > > >
> > > >
> > > > Hello, I have tested this change but bootmenu still does not work. There
> > > > is still same issue which I reported month ago. When I press DOWN key
> > > > then bootmenu immediately quit instead of moving into the next entry.
> > >
> > > Thanks for testing this.
> > >
> > > Is there a way for me to test this with sandbox? Or does your Nokia
> > > test check it?
> >
> > I guess that bootmenu command could work in sandbox. But I have not
> > tried it.
> >
> > Nokia CI test does not try any terminal, keyboard or VGA interaction, so
> > broken rendering or broken keyboard input is not caught by CI.
> >
> > But it is possible to test it manually. See U-Boot documentation how to
> > run Nokia u-boot image in qemu. Bootmenu is automatically started.
> > https://u-boot.readthedocs.io/en/latest/board/nokia/rx51.html#run-in-qemu
>
> I tried to follow this but got stuck here:
>
> ./configure --enable-system --target-list=arm-softmmu --disable-werror
>
> ERROR: Cannot use 'python', Python 2.4 or later is required.
>Note that Python 3 or later is not yet supported.
>Use --python=/path/to/python to specify a supported Python.
>
> Python 2 has been deprecated for years and I think it was removed recently.
Ach :-( Is not there some configure option to disable python?
In U-Boot CI is qemu compiling without issues (but variant without GUI).
> >
> > Bootmenu is available on both VGA display and terminal output. Problem
> > with DOWN key is on the terminal.
> >
> > >
> > > I'm sure you have this commit:?
> > >
> > > 17b45e684af9 ("cli: Correct several bugs in cli_getch()")
> >
> > Yes, as it is in the master branch already.
>
> I tried the following with sandbox:
>
> setenv bootmenu_0 "my item=echo item 0"
> setenv bootmenu_1 "second item=echo item 1"
> setenv bootmenu_delay 10
> bootmenu
>
> I see that with the ANSI patch the 'press key' prompt now appears in
> the right place.
>
> When I press down key repeatedly, it goes down until the last item and
> then refuses to go any further.
>
> So I can't repeat this problem.
Hm... so it looks like some ARM or UART specific thing... or something
which is not triggered by sandbox.
Just some suggestions, could you try to add some more entries? Or trying
to wait e.g. 30s before pressing another key (qemu is slow so there can
be some delay issue?)? Or could you try to run bootmenu on some real
hardware via UART?
> I tried looking at the Nokia code. The keyboard driver should be in
> drivers/input, but I eventually found it in the board directory.
>
> Are you sure that rx51_kp_tstc() behaves correctly? Can you add
> debugging to see what codes it is emitting?
>
> Also you don't need to generate escape sequences in rx51_kp_fill().
> You can just use Ctrl-N, Ctrl-P, Ctrl-B and Ctrl-F (see cli_ch_esc()).
> That should simplify things a bit.
>
> If you can find a way to repeat this problem and have verified that
> the Nokia code is correct, I can take another look.
Problem with DOWN key is on the terminal, not on the screen or keyboard.
So all those rx51_kp_tstc() and rx51_kp_fill() should not be the cause
(unless some input/output multiplexing in u-boot takes a role).
Terminal to qemu is connected via qemu's UART emulation, so omap2 uart
driver in this case is the one which connects u-boot to the qemu's UART
emulation.
> Regards,
> Simon
>
> [1]
> https://patchwork.ozlabs.org/project/uboot/patch/20230612201434.861700-1-...@chromium.org/
Re: [PATCH 5/7] Makefile: Add a target for building capsules
hi Simon, On Thu, 15 Jun 2023 at 14:44, Simon Glass wrote: > > Hi Sughosh, > > On Tue, 13 Jun 2023 at 11:39, Sughosh Ganu wrote: > > > > Add a target for building EFI capsules. The capsule parameters are > > specified through a config file, and the path to the config file is > > specified through CONFIG_EFI_CAPSULE_CFG_FILE. When the config file is > > not specified, the command only builds tools. > > > > Signed-off-by: Sughosh Ganu > > --- > > Makefile | 9 + > > 1 file changed, 9 insertions(+) > > > > diff --git a/Makefile b/Makefile > > index 10bfaa52ad..96db29aa77 100644 > > --- a/Makefile > > +++ b/Makefile > > @@ -1151,6 +1151,15 @@ dtbs: dts/dt.dtb > > dts/dt.dtb: u-boot > > $(Q)$(MAKE) $(build)=dts dtbs > > > > +quiet_cmd_mkeficapsule = MKEFICAPSULE $@ > > +cmd_mkeficapsule = $(objtree)/tools/mkeficapsule $@ > > + > > +PHONY += capsule > > +capsule: tools > > +ifneq ($(CONFIG_EFI_CAPSULE_CFG_FILE),"") > > + $(call cmd,mkeficapsule) > > +endif > > + > > quiet_cmd_copy = COPY$@ > >cmd_copy = cp $< $@ > > > > -- > > 2.34.1 > > > > We should be using binman to build images...you seem to be building > something in parallel with that. Can you please take a look at binman? Again, I had explored using binman for this task. The one issue where I find the above flow better is that I can simply build my payload image(s) followed by 'make capsule' to generate the capsules for earlier generated images. In it's current form, I don't see an easy way to enforce this dependency in binman when I want to build the payload followed by generation of capsules. I did see the mention of encapsulating an entry within another dependent entry, but I think that makes the implementation more complex than it ought to be. I think it is much easier to use the make flow to generate the images followed by capsules, instead of tweaking the binman node to first generate the payload images, followed by enabling the capsule node to build the capsules. If there is an easy way of enforcing this dependency, please let me know. Thanks -sughosh
Re: [PATCH 1/7] capsule: authenticate: Embed capsule public key in platform's dtb
hi Simon,
On Thu, 15 Jun 2023 at 14:44, Simon Glass wrote:
>
> Hi Sughosh,
>
> On Tue, 13 Jun 2023 at 11:41, Sughosh Ganu wrote:
> >
> > The EFI capsule authentication logic in u-boot expects the public key
> > in the form of an EFI Signature List(ESL) to be provided as part of
> > the platform's dtb. Currently, the embedding of the ESL file into the
> > dtb needs to be done manually.
> >
> > Add a script for embedding the ESL used for capsule authentication in
> > the platform's dtb, and call this as part of building the dtb(s). This
> > brings the embedding of the ESL in the dtb into the u-boot build flow.
> >
> > The path to the ESL file is specified through the
> > CONFIG_EFI_CAPSULE_ESL_FILE symbol.
> >
> > Signed-off-by: Sughosh Ganu
> > ---
> > lib/efi_loader/Kconfig | 11 +++
> > scripts/Makefile.lib | 8
> > scripts/embed_capsule_key.sh | 25 +
> > 3 files changed, 44 insertions(+)
> > create mode 100755 scripts/embed_capsule_key.sh
> >
> > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> > index c5835e6ef6..1326a1d109 100644
> > --- a/lib/efi_loader/Kconfig
> > +++ b/lib/efi_loader/Kconfig
> > @@ -234,6 +234,17 @@ config EFI_CAPSULE_MAX
> > Select the max capsule index value used for capsule report
> > variables. This value is used to create CapsuleMax variable.
> >
> > +config EFI_CAPSULE_ESL_FILE
> > + string "Path to the EFI Signature List File"
> > + default ""
> > + depends on EFI_CAPSULE_AUTHENTICATE
> > + help
> > + Provides the absolute path to the EFI Signature List
> > + file which will be embedded in the platform's device
> > + tree and used for capsule authentication at the time
> > + of capsule update.
> > +
> > +
> > config EFI_DEVICE_PATH_TO_TEXT
> > bool "Device path to text protocol"
> > default y
> > diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
> > index 7b27224b5d..a4083d0a26 100644
> > --- a/scripts/Makefile.lib
> > +++ b/scripts/Makefile.lib
> > @@ -192,6 +192,8 @@ dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc
> > \
> > -D__ASSEMBLY__ \
> > -undef -D__DTS__
> >
> > +export dtc_cpp_flags
> > +
> > # Finds the multi-part object the current object will be linked into
> > modname-multi = $(sort $(foreach m,$(multi-used),\
> > $(if $(filter $(subst $(obj)/,,$*.o), $($(m:.o=-objs))
> > $($(m:.o=-y))),$(m:.o=
> > @@ -315,6 +317,9 @@ ifeq ($(CONFIG_OF_LIBFDT_OVERLAY),y)
> > DTC_FLAGS += -@
> > endif
> >
> > +quiet_cmd_embedcapsulekey = EMBEDCAPSULEKEY $@
> > +cmd_embedcapsulekey = $(srctree)/scripts/embed_capsule_key.sh $@
> > +
> > quiet_cmd_dtc = DTC $@
> > # Modified for U-Boot
> > # Bring in any U-Boot-specific include at the end of the file
> > @@ -333,6 +338,9 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
> >
> > $(obj)/%.dtb: $(src)/%.dts FORCE
> > $(call if_changed_dep,dtc)
> > +ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE),y)
> > + $(call cmd,embedcapsulekey,$@)
> > +endif
> >
> > pre-tmp = $(subst $(comma),_,$(dot-target).pre.tmp)
> > dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
> > diff --git a/scripts/embed_capsule_key.sh b/scripts/embed_capsule_key.sh
> > new file mode 100755
> > index 00..1c2e45f758
> > --- /dev/null
> > +++ b/scripts/embed_capsule_key.sh
> > @@ -0,0 +1,25 @@
> > +#! /bin/bash
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (C) 2023, Linaro Limited
> > +#
> > +
> > +gen_capsule_signature_file() {
> > +cat >> $1 << EOF
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +&{/} {
> > + signature {
> > + capsule-key = /incbin/(CONFIG_EFI_CAPSULE_ESL_FILE);
> > + };
> > +};
> > +EOF
> > +}
> > +
> > +gen_capsule_signature_file signature.$$.dts > /dev/null 2>&1
> > +$CPP $dtc_cpp_flags -x assembler-with-cpp -o signature.$$.tmp
> > signature.$$.dts > /dev/null 2>&1
> > +dtc -@ -O dtb -o signature.$$.dtbo signature.$$.tmp > /dev/null 2>&1
> > +fdtoverlay -i $1 -o temp.$$.dtb -v signature.$$.dtbo > /dev/null 2>&1
> > +mv temp.$$.dtb $1 > /dev/null 2>&1
> > +rm -f signature.$$.* > /dev/null 2>&1
> > --
> > 2.34.1
> >
>
> Can you please add this to binman instead?
I had looked at using binman for this work earlier because I very much
expected this comment from you :). Having said that, I am very much
open to using binman instead if it turns out to be the better way of
achieving this. What this patch does is that, with capsule
authentication enabled, it embeds the public key esl file into the
dtb's as they get built. As per my understanding, binman gets called
at the end of the u-boot build, once the constituent images( e..g
u-boot.bin = u-boot-no-dtb.bin + dtb) have been generated. So, if we
call binman _after_ the requisite image(s) have been generated, we
would need to 1) identify the dtb's in
[PATCH v2] mx8m: csf.sh: use vars for keys to avoid file edits when signing
The csf_spl.txt and csf_fit.txt templates contain file paths which must
be edited for the location of your NXP CST generated key files.
Streamline the process of signing an image by assigning unique var names
to these which can be expended from env variables in the csf.sh script.
The following vars are used:
SRK_TABLE - full path to SRK_1_2_3_4_table.bin
CSF_KEY - full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem
IMG_KEY - full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem
Additionally provide an example of running the csf.sh script.
Signed-off-by: Tim Harvey
Reviewed-by: Fabio Estevam
---
v2:
- fix typo: s/SKK_TABLE/SRK_TABLE
- add Fabio's rb tag
---
doc/imx/habv4/csf_examples/mx8m/csf.sh| 21 +++
doc/imx/habv4/csf_examples/mx8m/csf_fit.txt | 12 +--
doc/imx/habv4/csf_examples/mx8m/csf_spl.txt | 12 +--
doc/imx/habv4/guides/mx8m_spl_secure_boot.txt | 10 +
4 files changed, 43 insertions(+), 12 deletions(-)
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh
b/doc/imx/habv4/csf_examples/mx8m/csf.sh
index 7a9a05e63392..c4e610adf1c4 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf.sh
+++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh
@@ -22,6 +22,27 @@
cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp
cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp
+# update File Paths from env vars
+if ! [ -r $CSF_KEY ]; then
+ echo "Error: \$CSF_KEY not found"
+ exit 1
+fi
+if ! [ -r $IMG_KEY ]; then
+ echo "Error: \$IMG_KEY not found"
+ exit 1
+fi
+if ! [ -r $SRK_TABLE ]; then
+ echo "Error: \$SRK_TABLE not found"
+ exit 1
+fi
+sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp
+sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp
+sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp
+sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp
+sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp
+sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp
+
+# update SPL Blocks
spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p"
.config) - 0x40)) )
spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin))
sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size
\"flash.bin\"@" csf_spl.tmp
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
index cd1d4070a5e5..dfcfb777c248 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
@@ -7,21 +7,21 @@
Signature Format = CMS
[Install SRK]
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin"
+ # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
+ File = "$SRK_TABLE"
Source index = 0
[Install CSFK]
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+ # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
+ File = "$CSF_KEY"
[Authenticate CSF]
[Install Key]
Verification index = 0
Target Index = 2
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+ # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
+ File = "$IMG_KEY"
[Authenticate Data]
Verification index = 2
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
index 00e34f6b1b95..88fa420a5fa0 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
@@ -7,13 +7,13 @@
Signature Format = CMS
[Install SRK]
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin"
+ # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
+ File = "$SRK_TABLE"
Source index = 0
[Install CSFK]
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+ # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
+ File = "$CSF_KEY"
[Authenticate CSF]
@@ -24,8 +24,8 @@
[Install Key]
Verification index = 0
Target Index = 2
- # FIXME: Adjust path here
- File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+ # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
+ File = "$IMG_KEY"
[Authenticate Data]
Verification index = 2
diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
index 3e3d38440f94..e789bae55940 100644
--- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
@@ -251,6 +251,16 @@ dd if=csf_fit.bin of=flash.bin bs=1
seek=${csf_block_offset} conv=notrunc
```
The entire script is available in doc/imx/habv4/csf_examples/mx8m/csf.sh
+and can be used as follows to modify flash.bin to be signed
+(adjust paths as needed):
+```
+export CST_DIR=/usr/src/cst-3.3.1/
+export CSF_KEY=$CST_DIR/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem
+export
[PATCH] usb: dwc3: core: fix clk_get_rate returning negative value
Unlike it's Linux counterpart, clk_get_rate can return a negative value, -ve.
The driver does not take that into account, stores the rate into
an unsigned long, and if clk_get_rate fails, it will take into consideration
the actual value and wrongly program the hardware.
E.g. on error -2 (no such entry), the rate will be 18446744073709551614
and this will be subsequently used by the driver to program the DWC3
To fix this, exit the function if the value is negative.
Fixes: 6bae0eb5b8bd ("usb: dwc3: Calculate REFCLKPER based on reference clock")
Signed-off-by: Eugen Hristev
---
drivers/usb/dwc3/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 49f6a1900b01..5a8c29424578 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -138,7 +138,7 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc)
if (dwc->ref_clk) {
rate = clk_get_rate(dwc->ref_clk);
- if (!rate)
+ if (!rate || (long)rate < 0)
return;
period = NSEC_PER_SEC / rate;
} else {
--
2.34.1
[PATCH] lib/zlib: Fix a bug when getting a gzip header extra field
This fixes CVE-2022-37434 [1] and bases on 2 commits from Mark
Adler's zlib master repo - the original fix of CVE bug [2] and
the fix for the fix [3].
[1]
https://github.com/advisories/GHSA-cfmr-vrgj-vqwv
[2]
https://github.com/madler/zlib/commit/eff308af425b67093bab25f80f1ae950166bece1
[3]
https://github.com/madler/zlib/commit/1eb7682f845ac9e9bf9ae35bbfb3bad5dacbd91d
Fixes: e89516f031d ("zlib: split up to match original source tree")
Signed-off-by: Oleksandr Suvorov
---
lib/zlib/inflate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/lib/zlib/inflate.c b/lib/zlib/inflate.c
index 30dfe155995..8f767b7b9d2 100644
--- a/lib/zlib/inflate.c
+++ b/lib/zlib/inflate.c
@@ -455,8 +455,9 @@ int ZEXPORT inflate(z_streamp strm, int flush)
if (copy > have) copy = have;
if (copy) {
if (state->head != Z_NULL &&
-state->head->extra != Z_NULL) {
-len = state->head->extra_len - state->length;
+state->head->extra != Z_NULL &&
+(len = state->head->extra_len - state->length) <
+state->head->extra_max) {
zmemcpy(state->head->extra + len, next,
len + copy > state->head->extra_max ?
state->head->extra_max - len : copy);
--
2.40.1
[PATCH 5/5] efi_selftests: add extra testcases on controller handling
We recently fixed a few issues wrt to controller handling. Add a few
test cases to cover the new code.
- add a second driver in the same controller handle which will refuse to
unbind on the first protocol removal
- add tests to verify controllers are reconnected when uninstalling a
protocol fails
- add tests to make sure EFI_NOT_FOUND is returned if a non existent
interface is being removed
Signed-off-by: Ilias Apalodimas
---
lib/efi_selftest/efi_selftest_controllers.c | 221 ++--
1 file changed, 198 insertions(+), 23 deletions(-)
diff --git a/lib/efi_selftest/efi_selftest_controllers.c
b/lib/efi_selftest/efi_selftest_controllers.c
index 79bc86fb0c3a..d2a974079329 100644
--- a/lib/efi_selftest/efi_selftest_controllers.c
+++ b/lib/efi_selftest/efi_selftest_controllers.c
@@ -13,6 +13,8 @@
#include
#define NUMBER_OF_CHILD_CONTROLLERS 4
+#define CONTROLLER1_DRIVERS (1 + NUMBER_OF_CHILD_CONTROLLERS)
+#define CONTROLLER2_DRIVERS 1
static int interface1 = 1;
static int interface2 = 2;
@@ -22,24 +24,32 @@ const efi_guid_t guid_driver_binding_protocol =
static efi_guid_t guid_controller =
EFI_GUID(0xe6ab1d96, 0x6bff, 0xdb42,
0xaa, 0x05, 0xc8, 0x1f, 0x7f, 0x45, 0x26, 0x34);
+
+static efi_guid_t guid_controller2 =
+ EFI_GUID(0xe6ab1d96, 0x6bff, 0xdb42,
+0xaa, 0x50, 0x8c, 0xf1, 0xf7, 0x54, 0x62, 0x43);
+
static efi_guid_t guid_child_controller =
EFI_GUID(0x1d41f6f5, 0x2c41, 0xddfb,
0xe2, 0x9b, 0xb8, 0x0e, 0x2e, 0xe8, 0x3a, 0x85);
static efi_handle_t handle_controller;
static efi_handle_t handle_child_controller[NUMBER_OF_CHILD_CONTROLLERS];
static efi_handle_t handle_driver;
+static efi_handle_t handle_driver2;
+
+static bool allow_remove;
/*
- * Count child controllers
+ * Count controllers
*
- * @handle handle on which child controllers are installed
+ * @handle handle on which controllers and children are installed
* @protocol protocol for which the child controllers were installed
* @count number of child controllers
+ * @children: count children only
* Return: status code
*/
-static efi_status_t count_child_controllers(efi_handle_t handle,
- efi_guid_t *protocol,
- efi_uintn_t *count)
+static efi_status_t count_controllers(efi_handle_t handle, efi_guid_t
*protocol,
+ efi_uintn_t *count, bool children)
{
efi_status_t ret;
efi_uintn_t entry_count;
@@ -52,10 +62,14 @@ static efi_status_t count_child_controllers(efi_handle_t
handle,
return ret;
if (!entry_count)
return EFI_SUCCESS;
- while (entry_count) {
- if (entry_buffer[--entry_count].attributes &
- EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)
- ++*count;
+ if (!children) {
+ *count = entry_count;
+ } else {
+ while (entry_count) {
+ if (entry_buffer[--entry_count].attributes &
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)
+ ++*count;
+ }
}
ret = boottime->free_pool(entry_buffer);
if (ret != EFI_SUCCESS)
@@ -153,6 +167,22 @@ static efi_status_t EFIAPI start(
return EFI_ST_FAILURE;
}
}
+
+ /* Attach driver to controller */
+ ret = boottime->open_protocol(controller_handle, _controller2,
+ , handle_driver2,
+ controller_handle,
+ EFI_OPEN_PROTOCOL_BY_DRIVER);
+ switch (ret) {
+ case EFI_SUCCESS:
+ return EFI_SUCCESS;
+ case EFI_ALREADY_STARTED:
+ case EFI_ACCESS_DENIED:
+ return ret;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
return ret;
}
@@ -249,6 +279,50 @@ static efi_status_t EFIAPI stop(
return EFI_SUCCESS;
}
+/*
+ * Check if the driver supports the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @remaining_device_path path specifying the child controller
+ * Return: status code
+ */
+static efi_status_t EFIAPI supported2(struct efi_driver_binding_protocol *this,
+ efi_handle_t controller_handle,
+ struct efi_device_path *remaining_dp)
+{
+ return EFI_SUCCESS;
+}
+
+/*
+ * Refuse to disconnect the controller.
+ *
+ * @this driver binding protocol
+ * @controller_handle handle of the controller
+ * @number_of_children number of child controllers to remove
+ * @child_handle_bufferhandles of the child controllers to
remove
+ * Return:
[PATCH 2/5] efi_loader: reconnect drivers on failure
efi_disconnect_controller() doesn't reconnect drivers in case of
failure. Reconnect the disconnected drivers properly
Signed-off-by: Ilias Apalodimas
---
lib/efi_loader/efi_boottime.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 68198e6b5ff6..df675d0ad488 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -97,6 +97,12 @@ static efi_status_t EFIAPI efi_disconnect_controller(
efi_handle_t driver_image_handle,
efi_handle_t child_handle);
+static efi_status_t EFIAPI efi_connect_controller(
+ efi_handle_t controller_handle,
+ efi_handle_t *driver_image_handle,
+ struct efi_device_path *remain_device_path,
+ bool recursive);
+
/* Called on every callback entry */
int __efi_entry_check(void)
{
@@ -1298,7 +1304,7 @@ static efi_status_t efi_disconnect_all_drivers
const efi_guid_t *protocol,
efi_handle_t child_handle)
{
- efi_uintn_t number_of_drivers;
+ efi_uintn_t number_of_drivers, tmp;
efi_handle_t *driver_handle_buffer;
efi_status_t r, ret;
@@ -1308,15 +1314,30 @@ static efi_status_t efi_disconnect_all_drivers
return ret;
if (!number_of_drivers)
return EFI_SUCCESS;
- ret = EFI_NOT_FOUND;
+
+ tmp = number_of_drivers;
while (number_of_drivers) {
- r = EFI_CALL(efi_disconnect_controller(
+ ret = EFI_CALL(efi_disconnect_controller(
handle,
driver_handle_buffer[--number_of_drivers],
child_handle));
- if (r == EFI_SUCCESS)
- ret = r;
+ if (ret != EFI_SUCCESS)
+ goto reconnect;
}
+
+ free(driver_handle_buffer);
+ return ret;
+
+reconnect:
+ /* Reconnect all disconnected drivers */
+ for (; number_of_drivers < tmp; number_of_drivers++) {
+ r = EFI_CALL(efi_connect_controller(handle,
+
_handle_buffer[number_of_drivers],
+ NULL, true));
+ if (r != EFI_SUCCESS)
+ EFI_PRINT("Failed to reconnect controller\n");
+ }
+
free(driver_handle_buffer);
return ret;
}
--
2.39.2
[PATCH 3/5] efi_loader: disconnect all controllers when uninstalling a protocol
When we are trying to uninstall a protocol interface from a controller
handle we are trying to disconnect drivers related to that protocol.
However, when we call efi_disconnect_all_drivers() we pass the protocol
GUID. If 2 different drivers are using the same protocol interface and
one of them can't be stopped (e.g by returning EFI_DEVICE_ERROR) we
should stop uninstalling it.
Instead of explicitly passing the protocol GUID, pass NULL as an argument.
That will force efi_get_drivers() to return all drivers consuming the
interface regardless of the protocol GUID.
While at it call efi_disconnect_all_drivers() with a handle instead of
the efiobj
Signed-off-by: Ilias Apalodimas
---
lib/efi_loader/efi_boottime.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index df675d0ad488..b148824c7ec5 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1374,7 +1374,7 @@ static efi_status_t efi_uninstall_protocol
if (r != EFI_SUCCESS)
goto out;
/* Disconnect controllers */
- r = efi_disconnect_all_drivers(efiobj, protocol, NULL);
+ r = efi_disconnect_all_drivers(handle, NULL, NULL);
if (r != EFI_SUCCESS) {
r = EFI_DEVICE_ERROR;
goto out;
--
2.39.2
[PATCH 4/5] efi_loader: fix the return codes of UninstallProtocol
Up to now we did not check the return value of DisconnectController.
A previous patch is fixing that taking into account what happened during
the controller disconnect. But that check takes place before our code
is trying to figure out if the interface exists to begin with. In case a
driver is not allowed to unbind -- e.g returning EFI_DEVICE_ERROR, we
will end up returning that error instead of EFI_NOT_FOUND.
Add an extra check on the top of the function to make sure the protocol
interface exists before trying to disconnect any drivers
Signed-off-by: Ilias Apalodimas
---
lib/efi_loader/efi_boottime.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index b148824c7ec5..d6d52d4bbac8 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1373,6 +1373,8 @@ static efi_status_t efi_uninstall_protocol
r = efi_search_protocol(handle, protocol, );
if (r != EFI_SUCCESS)
goto out;
+ if (handler->protocol_interface != protocol_interface)
+ return EFI_NOT_FOUND;
/* Disconnect controllers */
r = efi_disconnect_all_drivers(handle, NULL, NULL);
if (r != EFI_SUCCESS) {
--
2.39.2
[PATCH 1/5] efi_loader: check the status of disconnected drivers
efi_uninstall_protocol() calls efi_disconnect_all_drivers() but never
checks the return value. Honor that and return an appropriate error
if the associated controllers failed to disconnect
Signed-off-by: Ilias Apalodimas
---
lib/efi_loader/efi_boottime.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 5006c0e1e4af..68198e6b5ff6 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1353,7 +1353,11 @@ static efi_status_t efi_uninstall_protocol
if (r != EFI_SUCCESS)
goto out;
/* Disconnect controllers */
- efi_disconnect_all_drivers(efiobj, protocol, NULL);
+ r = efi_disconnect_all_drivers(efiobj, protocol, NULL);
+ if (r != EFI_SUCCESS) {
+ r = EFI_DEVICE_ERROR;
+ goto out;
+ }
/* Close protocol */
list_for_each_entry_safe(item, pos, >open_infos, link) {
if (item->info.attributes ==
--
2.39.2
Re: [PATCH] arm: mx6: module_fuse: fix build failure due to wrong argument name
On Thu, Apr 6, 2023 at 1:17 PM Giulio Benetti wrote: > > nodeoff variable should be variable off returned by fdt_path_offset() so > let's rename it to off. > > Signed-off-by: Giulio Benetti Reviewed-by: Fabio Estevam
Re: [PATCH] arm: mx6: module_fuse: fix build failure due to wrong argument name
Hello All, On 07/04/23 03:52, Peng Fan wrote: On 4/7/2023 12:17 AM, Giulio Benetti wrote: nodeoff variable should be variable off returned by fdt_path_offset() so let's rename it to off. Signed-off-by: Giulio Benetti Reviewed-by: Peng Fan I kindly ping Best regards -- CEO/CTO@Benetti Engineering sas
[PATCH 6/7] configs: ls1046ardb: enable DM_SERIAL
As the serial devices are configured in the device tree, enable DM_SERIAL in the ls1046ardb defconfigs. Signed-off-by: Camelia Groza --- configs/ls1046ardb_emmc_defconfig | 3 ++- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 4 +++- configs/ls1046ardb_qspi_defconfig | 4 +++- configs/ls1046ardb_qspi_spl_defconfig | 3 ++- configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 4 +++- configs/ls1046ardb_sdcard_defconfig | 3 ++- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig| 4 +++- configs/ls1046ardb_tfa_defconfig| 4 +++- 8 files changed, 21 insertions(+), 8 deletions(-) diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 7be98df566fc..924ff78b4593 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -111,7 +111,8 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 3cefae092f34..bb278845e069 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -86,7 +86,9 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 02979dd2ff01..0fb1a6c281e5 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -90,7 +90,9 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 8f7d05fab976..eb0184c59276 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -118,7 +118,8 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 900e26be3be0..2813c79f5975 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -109,7 +109,9 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index ded6be50a3f6..a621859aa792 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -111,7 +111,8 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 3eaa985ec79b..fbcf294eb534 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -79,7 +79,9 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 7e8d86d03c4c..24a54230f8ee 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -85,7 +85,9 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y -- 2.17.1
[PATCH 7/7] configs: ls1046afrwy: enable DM_SERIAL
As the serial devices are configured in the device tree, enable DM_SERIAL in the ls1046afrwy defconfigs. Signed-off-by: Camelia Groza --- configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 4 +++- configs/ls1046afrwy_tfa_defconfig | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 8d6a1371acb7..e97092f2c9b7 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -67,7 +67,9 @@ CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x90 CONFIG_DM_PCI_COMPAT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index e5d2b556f783..fdf08ad3c63c 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -76,7 +76,9 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y -- 2.17.1
[PATCH 5/7] arch: arm: dts: ls1046a: tag serial nodes with bootph-all
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all".
Signed-off-by: Camelia Groza
---
arch/arm/dts/fsl-ls1046a.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 9fdd398e2c4c..3986360c0c93 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -227,6 +227,7 @@
interrupts = ;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ bootph-all;
};
duart1: serial@21c0600 {
@@ -235,6 +236,7 @@
interrupts = ;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ bootph-all;
};
duart2: serial@21d0500 {
@@ -243,6 +245,7 @@
interrupts = ;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ bootph-all;
};
duart3: serial@21d0600 {
@@ -251,6 +254,7 @@
interrupts = ;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ bootph-all;
};
lpuart0: serial@295 {
--
2.17.1
[PATCH 4/7] arch: arm: dts: ls1046a: sync serial nodes with Linux
Pick up the serial node descriptions from Linux for the ls1046ardb and
ls1046afrwy boards and their dependencies. Including the
fsl,qoriq-clockgen.h and arm-gic.h headers forces us to change the include
directives to explicitly go through the C preprocessor for all boards in
the ls1046a SoC family.
Signed-off-by: Camelia Groza
---
arch/arm/dts/fsl-ls1046a-frwy.dts | 22 +-
arch/arm/dts/fsl-ls1046a-qds.dtsi | 2 +-
arch/arm/dts/fsl-ls1046a-rdb.dts | 14 +-
arch/arm/dts/fsl-ls1046a.dtsi | 24 +++-
4 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts
b/arch/arm/dts/fsl-ls1046a-frwy.dts
index cda05411d881..f3ba2acd6d51 100644
--- a/arch/arm/dts/fsl-ls1046a-frwy.dts
+++ b/arch/arm/dts/fsl-ls1046a-frwy.dts
@@ -7,17 +7,37 @@
*/
/dts-v1/;
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
/ {
model = "LS1046A FRWY Board";
aliases {
spi0 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
status = "okay";
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi
b/arch/arm/dts/fsl-ls1046a-qds.dtsi
index fec5c8ddb23a..d66824975c5e 100644
--- a/arch/arm/dts/fsl-ls1046a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -7,7 +7,7 @@
* Mingkai Hu
*/
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
/ {
model = "LS1046A QDS Board";
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index 464129291c91..66d718905c7d 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -9,17 +9,29 @@
*/
/dts-v1/;
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
/ {
model = "LS1046A RDB Board";
aliases {
spi0 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
status = "okay";
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 060dc399c2f6..9fdd398e2c4c 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -8,7 +8,9 @@
* Mingkai Hu
*/
-/include/ "skeleton64.dtsi"
+#include "skeleton64.dtsi"
+#include
+#include
/ {
compatible = "fsl,ls1046a";
@@ -222,29 +224,33 @@
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
- interrupts = <0 54 0x4>;
- clocks = < 4 0>;
+ interrupts = ;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
};
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
- interrupts = <0 54 0x4>;
- clocks = < 4 0>;
+ interrupts = ;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
};
duart2: serial@21d0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0500 0x0 0x100>;
- interrupts = <0 55 0x4>;
- clocks = < 4 0>;
+ interrupts = ;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
};
duart3: serial@21d0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0600 0x0 0x100>;
- interrupts = <0 55 0x4>;
- clocks = < 4 0>;
+ interrupts = ;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
};
lpuart0: serial@295 {
--
2.17.1
[PATCH 3/7] configs: ls1043ardb: enable DM_SERIAL
As the serial devices are configured in the device tree, enable DM_SERIAL in the ls1043ardb defconfigs. Signed-off-by: Camelia Groza --- configs/ls1043ardb_SECURE_BOOT_defconfig| 4 +++- configs/ls1043ardb_defconfig| 4 +++- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 4 +++- configs/ls1043ardb_nand_defconfig | 3 ++- configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 4 +++- configs/ls1043ardb_sdcard_defconfig | 3 ++- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig| 4 +++- configs/ls1043ardb_tfa_defconfig| 4 +++- 8 files changed, 22 insertions(+), 8 deletions(-) diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 069a8dc0c3ce..ea195d7c5041 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -86,7 +86,9 @@ CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x6094 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index e796c0a9a2e0..ae8600ffd958 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -89,7 +89,9 @@ CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x6094 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index f5faa02e5920..d9ff0fd16a58 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -110,7 +110,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x90 CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index b75550b2d3ad..ad118187432e 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -117,7 +117,8 @@ CONFIG_SYS_FMAN_FW_ADDR=0x90 CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 3e0d16430e04..fe0dd04f1f90 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -110,7 +110,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x90 CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x94 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 04e66f1e6ca2..aa5404cbb50e 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -115,7 +115,8 @@ CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x94 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index cf4623eb631d..480e928936a9 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -84,7 +84,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x90 CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x94 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 15e2916538a1..e25904170858 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -90,7 +90,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x90 CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x94 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y -- 2.17.1
[PATCH 2/7] arch: arm: dts: ls1043a: tag serial nodes with bootph-all
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all".
Signed-off-by: Camelia Groza
---
arch/arm/dts/fsl-ls1043a.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 21643a1d951f..79f67e7183c3 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -227,6 +227,7 @@
interrupts = <0 54 0x4>;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ bootph-all;
};
duart1: serial@21c0600 {
@@ -235,6 +236,7 @@
interrupts = <0 54 0x4>;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ bootph-all;
};
duart2: serial@21d0500 {
@@ -243,6 +245,7 @@
interrupts = <0 55 0x4>;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ bootph-all;
};
duart3: serial@21d0600 {
@@ -251,6 +254,7 @@
interrupts = <0 55 0x4>;
clocks = < QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
+ bootph-all;
};
lpuart0: serial@295 {
--
2.17.1
[PATCH 1/7] arch: arm: dts: ls1043a: sync serial nodes with Linux
Pick up the serial node descriptions from Linux for the ls1043ardb board
and its dependencies. Including the fsl,qoriq-clockgen.h and arm-gic.h
headers forces us to change the include directives to explicitly go through
the C preprocessor for all boards in the ls1043a SoC family.
Signed-off-by: Camelia Groza
---
arch/arm/dts/fsl-ls1043a-qds.dtsi | 2 +-
arch/arm/dts/fsl-ls1043a-rdb.dts | 6 +-
arch/arm/dts/fsl-ls1043a.dtsi | 16 +++-
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 884bdad196b3..5e02cd91d75f 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -7,7 +7,7 @@
* Mingkai Hu
*/
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
index 9e7c79fd2b98..f5b3bb68b3db 100644
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -9,13 +9,17 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
aliases {
spi1 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
};
};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 4960973a6035..21643a1d951f 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -8,7 +8,9 @@
* Mingkai Hu
*/
-/include/ "skeleton64.dtsi"
+#include "skeleton64.dtsi"
+#include
+#include
/ {
compatible = "fsl,ls1043a";
@@ -223,28 +225,32 @@
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <0 54 0x4>;
- clocks = < 4 0>;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(1)>;
};
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <0 54 0x4>;
- clocks = < 4 0>;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(1)>;
};
duart2: serial@21d0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0500 0x0 0x100>;
interrupts = <0 55 0x4>;
- clocks = < 4 0>;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(1)>;
};
duart3: serial@21d0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0600 0x0 0x100>;
interrupts = <0 55 0x4>;
- clocks = < 4 0>;
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(1)>;
};
lpuart0: serial@295 {
--
2.17.1
[PATCH 0/7] Enable DM_SERIAL for the LS104xA RDB/FRWY boards
This series enables DM_SERIAL for ls1043ardb, ls1046ardb and ls1046afrwy. First, the device tree serial nodes are synced with their counterpart descriptions in Linux. Secondly, the serial nodes are tagged with 'bootph-all' to guarantee the drivers are initialized before relocation. Lastly, CONFIG_DM_SERIAL is enabled in the relevant defconfigs. Camelia Groza (7): arch: arm: dts: ls1043a: sync serial nodes with Linux arch: arm: dts: ls1043a: tag the serial nodes with bootph-all configs: ls1043ardb: enable DM_SERIAL arch: arm: dts: ls1046a: sync serial nodes with Linux arch: arm: dts: ls1046a: tag the serial nodes with bootph-all configs: ls1046ardb: enable DM_SERIAL configs: ls1046afrwy: enable DM_SERIAL arch/arm/dts/fsl-ls1043a-qds.dtsi | 2 +- arch/arm/dts/fsl-ls1043a-rdb.dts | 6 +++- arch/arm/dts/fsl-ls1043a.dtsi | 20 + arch/arm/dts/fsl-ls1046a-frwy.dts | 22 ++- arch/arm/dts/fsl-ls1046a-qds.dtsi | 2 +- arch/arm/dts/fsl-ls1046a-rdb.dts | 14 +- arch/arm/dts/fsl-ls1046a.dtsi | 28 +-- configs/ls1043ardb_SECURE_BOOT_defconfig | 4 ++- configs/ls1043ardb_defconfig | 4 ++- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 4 ++- configs/ls1043ardb_nand_defconfig | 3 +- .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 4 ++- configs/ls1043ardb_sdcard_defconfig | 3 +- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 4 ++- configs/ls1043ardb_tfa_defconfig | 4 ++- configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 4 ++- configs/ls1046afrwy_tfa_defconfig | 4 ++- configs/ls1046ardb_emmc_defconfig | 3 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 4 ++- configs/ls1046ardb_qspi_defconfig | 4 ++- configs/ls1046ardb_qspi_spl_defconfig | 3 +- .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 4 ++- configs/ls1046ardb_sdcard_defconfig | 3 +- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 4 ++- configs/ls1046ardb_tfa_defconfig | 4 ++- 25 files changed, 124 insertions(+), 37 deletions(-) -- 2.17.1
Re: [PATCH 1/1] bootm: don't call booti_setup for EFI images
Hi Heinrich,
On Thu, 15 Jun 2023 at 12:38, Heinrich Schuchardt
wrote:
>
> On 6/15/23 11:14, Simon Glass wrote:
> > On Tue, 13 Jun 2023 at 09:11, Heinrich Schuchardt
> > wrote:
> >>
> >> On the arm64 architecture booti_setup() is called for EFI FIT images.
> >> This function call fails because EFI images typically do not have a
> >> kernel signature.
> >>
> >> Check that the operating system property "os" of the image is "linux"
> >> before invoking booti_setup().
> >>
> >> Fixes: 487b5fa6deb1 ("bootm: Handle kernel_noload on arm64")
> >> Signed-off-by: Heinrich Schuchardt
> >> ---
> >> boot/bootm.c | 3 ++-
> >> 1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/boot/bootm.c b/boot/bootm.c
> >> index 4144ff3b03..75f0b4a9af 100644
> >> --- a/boot/bootm.c
> >> +++ b/boot/bootm.c
> >> @@ -240,7 +240,8 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int
> >> flag, int argc,
> >>
> >> if (images.os.type == IH_TYPE_KERNEL_NOLOAD) {
> >> if (IS_ENABLED(CONFIG_CMD_BOOTI) &&
> >> - images.os.arch == IH_ARCH_ARM64) {
> >> + images.os.arch == IH_ARCH_ARM64 &&
> >> + images.os.os == IH_OS_LINUX) {
> >> ulong image_addr;
> >> ulong image_size;
> >>
> >> --
> >> 2.40.1
> >>
> >
> > Reviewed-by: Simon Glass
> >
> > I'm a little wary of this since no tests change. What is needed to test
> > this?
>
> We test loading EFI FIT images with test/py/tests/test_efi_fit.py. The
> image we use for testing is lib/efi_loader/helloworld.efi.
>
> The its file used on arm64 has:
>
> arch = "arm";
>
> This is why booti_setup() was never executed. We should fix this.
>
> Furthermore all EFI binaries that we create in U-Boot have a kernel
> signature in the CRT header so booti_setup() will not fail. This is
> needed to run tools like initrddump.efi with GRUB's linux command.
>
> test_fit.py is skipped on qemu_arm64 but some other test_fit*.py tests
> are executed. This should ensure regression testing.
OK good.
Regards,
Simon
Re: [PATCH] menu: Re-enable the ANSI codes
Hi Pali,
On Mon, 12 Jun 2023 at 22:33, Pali Rohár wrote:
>
> On Monday 12 June 2023 22:17:48 Simon Glass wrote:
> > Hi Pali,
> >
> > On Mon, 12 Jun 2023 at 21:22, Pali Rohár wrote:
> > >
> > > On Monday 12 June 2023 21:14:32 Simon Glass wrote:
> > > > The intent here was to allow ANSI codes to be disabled, since it was
> > > > proving impoosible to test operation of the menu code when it kept
> > > > moving
> > > > the cursor. Unfortunately this ended up in the patch.
> > > >
> > > > Correct this by enabling ANSI again.
> > > >
> > > > Signed-off-by: Simon Glass
> > > > Reported-by: Pali Rohár
> > > > Reported-by: Mark Kettenis
> > > > Reported-by: Frank Wunderlich
> > > > Fixes: 32bab0eae51b ("menu: Make use of CLI character processing")
> > > > ---
> > > >
> > > > common/menu.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/common/menu.c b/common/menu.c
> > > > index 94514177e4e9..b55cf7b99967 100644
> > > > --- a/common/menu.c
> > > > +++ b/common/menu.c
> > > > @@ -15,7 +15,7 @@
> > > >
> > > > #include "menu.h"
> > > >
> > > > -#define ansi 0
> > > > +#define ansi 1
> > > >
> > > > /*
> > > > * Internally, each item in a menu is represented by a struct
> > > > menu_item.
> > > > --
> > > > 2.41.0.162.gfafddb0af9-goog
> > > >
> > >
> > > Hello, I have tested this change but bootmenu still does not work. There
> > > is still same issue which I reported month ago. When I press DOWN key
> > > then bootmenu immediately quit instead of moving into the next entry.
> >
> > Thanks for testing this.
> >
> > Is there a way for me to test this with sandbox? Or does your Nokia
> > test check it?
>
> I guess that bootmenu command could work in sandbox. But I have not
> tried it.
>
> Nokia CI test does not try any terminal, keyboard or VGA interaction, so
> broken rendering or broken keyboard input is not caught by CI.
>
> But it is possible to test it manually. See U-Boot documentation how to
> run Nokia u-boot image in qemu. Bootmenu is automatically started.
> https://u-boot.readthedocs.io/en/latest/board/nokia/rx51.html#run-in-qemu
I tried to follow this but got stuck here:
./configure --enable-system --target-list=arm-softmmu --disable-werror
ERROR: Cannot use 'python', Python 2.4 or later is required.
Note that Python 3 or later is not yet supported.
Use --python=/path/to/python to specify a supported Python.
Python 2 has been deprecated for years and I think it was removed recently.
>
> Bootmenu is available on both VGA display and terminal output. Problem
> with DOWN key is on the terminal.
>
> >
> > I'm sure you have this commit:?
> >
> > 17b45e684af9 ("cli: Correct several bugs in cli_getch()")
>
> Yes, as it is in the master branch already.
I tried the following with sandbox:
setenv bootmenu_0 "my item=echo item 0"
setenv bootmenu_1 "second item=echo item 1"
setenv bootmenu_delay 10
bootmenu
I see that with the ANSI patch the 'press key' prompt now appears in
the right place.
When I press down key repeatedly, it goes down until the last item and
then refuses to go any further.
So I can't repeat this problem.
I tried looking at the Nokia code. The keyboard driver should be in
drivers/input, but I eventually found it in the board directory.
Are you sure that rx51_kp_tstc() behaves correctly? Can you add
debugging to see what codes it is emitting?
Also you don't need to generate escape sequences in rx51_kp_fill().
You can just use Ctrl-N, Ctrl-P, Ctrl-B and Ctrl-F (see cli_ch_esc()).
That should simplify things a bit.
If you can find a way to repeat this problem and have verified that
the Nokia code is correct, I can take another look.
Regards,
Simon
[1]
https://patchwork.ozlabs.org/project/uboot/patch/20230612201434.861700-1-...@chromium.org/
Trying to boot custom kernel on Wink Hub (i.MX28)
Hi folks,
I am trying to boot a custom kernel on a Wink Hub v1, which has an i.MX28
CPU, and is running U-Boot (U-Boot 2014.01-14400-gda781c6-dirty (Apr 30
2014 - 22:35:38)).
I have tried compiling my own modern kernel and putting it in place of the
vendor (Linux version 2.6.35.3-flex-dvt) kernel on the flash chip, but when
loading, I simply get the expected U-Boot loading messages, but then
nothing at all from the serial port after that.
I'm trying to figure out where my problem is most likely to be. As far as I
am aware from long-ago poking at U-Boot, the way that U-Boot passes
arguments to the kernel has changed recently? Previously it was ATAGS, and
now it expects a Device Tree Blob? Might this explain the failure to boot
that I am seeing? And yes, I understand that given that
Many thanks!
Rogan
P.S. I have also tried to boot the OpenWrt Duckbill kernel (a few years
ago), with the same results (
https://forum.openwrt.org/t/porting-openwrt-to-winkhub-v1/56966):
U-Boot 2014.01-14400-gda781c6-dirty (Apr 30 2014 - 22:35:38)
CPU: Freescale i.MX28 rev1.2 at 454 MHz
BOOT: NAND, 3V3
DRAM: 64 MiB
NAND: 128 MiB
In:serial
Out: serial
Err: serial
Net: FEC0 [PRIME]
Hit any key to stop autoboot: 0
=> setenv bootargs 'noinitrd console=ttyS0,115200 rootfstype=ubifs
ubi.mtd=5 root=ubi0:rootfs rw gpmi'; mtdparts default && ubi part database
&& ubifsmount ubi0:database && ubifsload ${loadaddr}
openwrt-19.07.1-mxs-uImage 1799536 && bootm ${loadaddr}
UBI: attaching mtd1 to ubi0
UBI: physical eraseblock size: 131072 bytes (128 KiB)
UBI: logical eraseblock size:126976 bytes
UBI: smallest flash I/O unit:2048
UBI: VID header offset: 2048 (aligned 2048)
UBI: data offset:4096
UBI: attached mtd1 to ubi0
UBI: MTD device name:"mtd=3"
UBI: MTD device size:8 MiB
UBI: number of good PEBs:64
UBI: number of bad PEBs: 0
UBI: max. allowed volumes: 128
UBI: wear-leveling threshold:4096
UBI: number of internal volumes: 1
UBI: number of user volumes: 1
UBI: available PEBs: 6
UBI: total number of reserved PEBs: 58
UBI: number of PEBs reserved for bad PEB handling: 2
UBI: max/mean erase counter: 63/45
UBIFS: mounted UBI device 0, volume 0, name "database"
UBIFS: mounted read-only
UBIFS: file system size: 5459968 bytes (5332 KiB, 5 MiB, 43 LEBs)
UBIFS: journal size: 1015809 bytes (992 KiB, 0 MiB, 6 LEBs)
UBIFS: media format: w4/r0 (latest is w4/r0)
UBIFS: default compressor: LZO
UBIFS: reserved for root: 269835 bytes (263 KiB)
Loading file 'openwrt-19.07.1-mxs-uImage' to addr 0x4200 with size
1799536 (0x001b7570)...
Done
## Booting kernel from Legacy Image at 4200 ...
Image Name: ARM OpenWrt Linux-4.14.167
Created: 2020-01-29 16:05:35 UTC
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size:1799472 Bytes = 1.7 MiB
Load Address: 40008000
Entry Point: 40008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
Starting kernel ...
[PATCH 1/1] test: correct architecture in EFI FIT test
On arm64 the its we use to generate the test FIT image has
arch = "arm";
We should use "arm64" here which is mapped to IH_ARCH_ARM64 via
uimage_arch[].
Fixes: 8391f955494e ("test/py: Create a test for launching UEFI binaries from
FIT images")
Signed-off-by: Heinrich Schuchardt
---
test/py/tests/test_efi_fit.py | 5 +
1 file changed, 5 insertions(+)
diff --git a/test/py/tests/test_efi_fit.py b/test/py/tests/test_efi_fit.py
index 7b7c98fb04..0ad483500f 100644
--- a/test/py/tests/test_efi_fit.py
+++ b/test/py/tests/test_efi_fit.py
@@ -431,6 +431,11 @@ def test_efi_fit_launch(u_boot_console):
cons = u_boot_console
# Array slice removes leading/trailing quotes.
sys_arch = cons.config.buildconfig.get('config_sys_arch',
'"sandbox"')[1:-1]
+if sys_arch == 'arm':
+arm64 = cons.config.buildconfig.get('config_arm64')
+if arm64:
+sys_arch = 'arm64'
+
is_sandbox = sys_arch == 'sandbox'
if is_sandbox:
--
2.40.1
Re: [PATCH 1/3] binman: Allow to define custom arguments
On 15.06.23 13:38, Simon Glass wrote: > Hi Jan, > > On Thu, 15 Jun 2023 at 12:21, Jan Kiszka wrote: >> >> On 15.06.23 13:19, Simon Glass wrote: >>> Hi Jan, >>> >>> On Thu, 15 Jun 2023 at 12:09, Jan Kiszka wrote: On 15.06.23 12:55, Simon Glass wrote: > Hi Jan, > > On Thu, 15 Jun 2023 at 11:26, Jan Kiszka wrote: >> >> On 12.06.23 23:17, Simon Glass wrote: >>> Hi Jan, >>> >>> On Mon, 5 Jun 2023 at 15:39, Jan Kiszka wrote: From: Jan Kiszka Introduce BINMAN_EXTRA_ARGS that can be set per board, e.g., to inject specific settings. Will be used by IOT2050 first to define multiple of-lists. Signed-off-by: Jan Kiszka --- CC: Simon Glass --- Makefile | 1 + 1 file changed, 1 insertion(+) >>> >>> I'm really not keen on this, since it means that the Makefile (or some >>> vars it sets) are again involved in controlling the image generation. >>> It should really all be in the binman image description / .dtsi file >> >> binman does not allow me to unrole of-list inside the dts file, does it? >> With such a feature, I wouldn't need any custom -a of-list-X switches >> and, thus, no such EXTRA_ARGS. > > Can you explain a bit more about what you mean by 'unrole'? It is just > software, so anything should be possible. To use a DT sequence, I need to specify fit,ftd-list. But I can say fit,ftd-list = "first.dtb second.dtb" I rather need to go via the EntryArg indirection of the binman command line. >>> >>> Do you mean you would rather not use '-a CONFIG_OF_LIST'. Or are you >>> wanting to filter that list based on something else? >>> >>> I'm afraid I am really not following this at all. >> >> CONFIG_OF_LIST is not working here as we have two different boards with >> two different lists. > > But we only build one board at a time, don't we? No, this is about building two flash images for two different board generations in the same binman run (see patch 3). > > We could provide a way to select between different lists, but how does > Makefile get access to them? See patch 3: known lists, now put into board config.mk. Jan -- Siemens AG, Technology Competence Center Embedded Linux
Re: [PATCH 1/3] binman: Allow to define custom arguments
Hi Jan, On Thu, 15 Jun 2023 at 12:21, Jan Kiszka wrote: > > On 15.06.23 13:19, Simon Glass wrote: > > Hi Jan, > > > > On Thu, 15 Jun 2023 at 12:09, Jan Kiszka wrote: > >> > >> On 15.06.23 12:55, Simon Glass wrote: > >>> Hi Jan, > >>> > >>> On Thu, 15 Jun 2023 at 11:26, Jan Kiszka wrote: > > On 12.06.23 23:17, Simon Glass wrote: > > Hi Jan, > > > > On Mon, 5 Jun 2023 at 15:39, Jan Kiszka wrote: > >> > >> From: Jan Kiszka > >> > >> Introduce BINMAN_EXTRA_ARGS that can be set per board, e.g., to inject > >> specific settings. Will be used by IOT2050 first to define multiple > >> of-lists. > >> > >> Signed-off-by: Jan Kiszka > >> --- > >> CC: Simon Glass > >> --- > >> Makefile | 1 + > >> 1 file changed, 1 insertion(+) > > > > I'm really not keen on this, since it means that the Makefile (or some > > vars it sets) are again involved in controlling the image generation. > > It should really all be in the binman image description / .dtsi file > > binman does not allow me to unrole of-list inside the dts file, does it? > With such a feature, I wouldn't need any custom -a of-list-X switches > and, thus, no such EXTRA_ARGS. > >>> > >>> Can you explain a bit more about what you mean by 'unrole'? It is just > >>> software, so anything should be possible. > >> > >> To use a DT sequence, I need to specify fit,ftd-list. But I can say > >> > >> fit,ftd-list = "first.dtb second.dtb" > >> > >> I rather need to go via the EntryArg indirection of the binman command > >> line. > > > > Do you mean you would rather not use '-a CONFIG_OF_LIST'. Or are you > > wanting to filter that list based on something else? > > > > I'm afraid I am really not following this at all. > > CONFIG_OF_LIST is not working here as we have two different boards with > two different lists. But we only build one board at a time, don't we? We could provide a way to select between different lists, but how does Makefile get access to them? Regards, Simon
Re: [PATCH 1/1] bootm: don't call booti_setup for EFI images
On 6/15/23 11:14, Simon Glass wrote:
On Tue, 13 Jun 2023 at 09:11, Heinrich Schuchardt
wrote:
On the arm64 architecture booti_setup() is called for EFI FIT images.
This function call fails because EFI images typically do not have a
kernel signature.
Check that the operating system property "os" of the image is "linux"
before invoking booti_setup().
Fixes: 487b5fa6deb1 ("bootm: Handle kernel_noload on arm64")
Signed-off-by: Heinrich Schuchardt
---
boot/bootm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/boot/bootm.c b/boot/bootm.c
index 4144ff3b03..75f0b4a9af 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -240,7 +240,8 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag,
int argc,
if (images.os.type == IH_TYPE_KERNEL_NOLOAD) {
if (IS_ENABLED(CONFIG_CMD_BOOTI) &&
- images.os.arch == IH_ARCH_ARM64) {
+ images.os.arch == IH_ARCH_ARM64 &&
+ images.os.os == IH_OS_LINUX) {
ulong image_addr;
ulong image_size;
--
2.40.1
Reviewed-by: Simon Glass
I'm a little wary of this since no tests change. What is needed to test this?
We test loading EFI FIT images with test/py/tests/test_efi_fit.py. The
image we use for testing is lib/efi_loader/helloworld.efi.
The its file used on arm64 has:
arch = "arm";
This is why booti_setup() was never executed. We should fix this.
Furthermore all EFI binaries that we create in U-Boot have a kernel
signature in the CRT header so booti_setup() will not fail. This is
needed to run tools like initrddump.efi with GRUB's linux command.
test_fit.py is skipped on qemu_arm64 but some other test_fit*.py tests
are executed. This should ensure regression testing.
Best regards
Heinrich
Re: [PATCH 3/3] boards: siemens: iot2050: Unify PG1 and PG2/M.2 configurations again
On 12.06.23 23:17, Simon Glass wrote:
> Hi Jan,
>
> On Mon, 5 Jun 2023 at 15:40, Jan Kiszka wrote:
>>
>> From: Jan Kiszka
>>
>> This avoids having to maintain to defconfigs that are 99% equivalent.
>> The approach is to use binman to generate two flash images,
>> flash-pg1.bin and flash-pg2.bin. With the help of some macros, we can
>> avoid duplicating the common binman image definitions.
>>
>> Suggested-by: Andrew Davis
>> Signed-off-by: Jan Kiszka
>> ---
>> arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 299 ++
>> board/siemens/iot2050/Kconfig | 30 +-
>> board/siemens/iot2050/board.c | 14 +-
>> board/siemens/iot2050/config.mk | 6 +-
>> ...ot2050_pg1_defconfig => iot2050_defconfig} | 3 +-
>> configs/iot2050_pg2_defconfig | 150 -
>> doc/board/siemens/iot2050.rst | 29 +-
>> tools/iot2050-sign-fw.sh | 9 +-
>> 8 files changed, 202 insertions(+), 338 deletions(-)
>> rename configs/{iot2050_pg1_defconfig => iot2050_defconfig} (97%)
>> delete mode 100644 configs/iot2050_pg2_defconfig
>
> We need to find another way to do this... the macros are horrible.
>
> Could you put the common code in another .dtsi file and include it twice?
>
> Then in the 'main' .dtsi file refer to some anchors to set the properties:
>
> _boot {
>fit,fdt-list = "...";
> };
I can use some preprocessor defines in that template code which need to
be re-defined before the inclusions. Prototype is working already.
>
> Or do we need a new binman feature to handle this?
>
> BTW using #ifdef on a particular target is something we should avoid.
> Isn't there another Kconfig (for the feature itself) that you can use?
What are you referring to?
Jan
--
Siemens AG, Technology
Competence Center Embedded Linux
Re: [PATCH 1/3] binman: Allow to define custom arguments
On 15.06.23 13:19, Simon Glass wrote: > Hi Jan, > > On Thu, 15 Jun 2023 at 12:09, Jan Kiszka wrote: >> >> On 15.06.23 12:55, Simon Glass wrote: >>> Hi Jan, >>> >>> On Thu, 15 Jun 2023 at 11:26, Jan Kiszka wrote: On 12.06.23 23:17, Simon Glass wrote: > Hi Jan, > > On Mon, 5 Jun 2023 at 15:39, Jan Kiszka wrote: >> >> From: Jan Kiszka >> >> Introduce BINMAN_EXTRA_ARGS that can be set per board, e.g., to inject >> specific settings. Will be used by IOT2050 first to define multiple >> of-lists. >> >> Signed-off-by: Jan Kiszka >> --- >> CC: Simon Glass >> --- >> Makefile | 1 + >> 1 file changed, 1 insertion(+) > > I'm really not keen on this, since it means that the Makefile (or some > vars it sets) are again involved in controlling the image generation. > It should really all be in the binman image description / .dtsi file binman does not allow me to unrole of-list inside the dts file, does it? With such a feature, I wouldn't need any custom -a of-list-X switches and, thus, no such EXTRA_ARGS. >>> >>> Can you explain a bit more about what you mean by 'unrole'? It is just >>> software, so anything should be possible. >> >> To use a DT sequence, I need to specify fit,ftd-list. But I can say >> >> fit,ftd-list = "first.dtb second.dtb" >> >> I rather need to go via the EntryArg indirection of the binman command line. > > Do you mean you would rather not use '-a CONFIG_OF_LIST'. Or are you > wanting to filter that list based on something else? > > I'm afraid I am really not following this at all. CONFIG_OF_LIST is not working here as we have two different boards with two different lists. Jan -- Siemens AG, Technology Competence Center Embedded Linux
Re: [PATCH 1/3] binman: Allow to define custom arguments
Hi Jan, On Thu, 15 Jun 2023 at 12:09, Jan Kiszka wrote: > > On 15.06.23 12:55, Simon Glass wrote: > > Hi Jan, > > > > On Thu, 15 Jun 2023 at 11:26, Jan Kiszka wrote: > >> > >> On 12.06.23 23:17, Simon Glass wrote: > >>> Hi Jan, > >>> > >>> On Mon, 5 Jun 2023 at 15:39, Jan Kiszka wrote: > > From: Jan Kiszka > > Introduce BINMAN_EXTRA_ARGS that can be set per board, e.g., to inject > specific settings. Will be used by IOT2050 first to define multiple > of-lists. > > Signed-off-by: Jan Kiszka > --- > CC: Simon Glass > --- > Makefile | 1 + > 1 file changed, 1 insertion(+) > >>> > >>> I'm really not keen on this, since it means that the Makefile (or some > >>> vars it sets) are again involved in controlling the image generation. > >>> It should really all be in the binman image description / .dtsi file > >> > >> binman does not allow me to unrole of-list inside the dts file, does it? > >> With such a feature, I wouldn't need any custom -a of-list-X switches > >> and, thus, no such EXTRA_ARGS. > > > > Can you explain a bit more about what you mean by 'unrole'? It is just > > software, so anything should be possible. > > To use a DT sequence, I need to specify fit,ftd-list. But I can say > > fit,ftd-list = "first.dtb second.dtb" > > I rather need to go via the EntryArg indirection of the binman command line. Do you mean you would rather not use '-a CONFIG_OF_LIST'. Or are you wanting to filter that list based on something else? I'm afraid I am really not following this at all. Regards, Simon
Re: [PATCH 1/3] binman: Allow to define custom arguments
On 15.06.23 12:55, Simon Glass wrote: > Hi Jan, > > On Thu, 15 Jun 2023 at 11:26, Jan Kiszka wrote: >> >> On 12.06.23 23:17, Simon Glass wrote: >>> Hi Jan, >>> >>> On Mon, 5 Jun 2023 at 15:39, Jan Kiszka wrote: From: Jan Kiszka Introduce BINMAN_EXTRA_ARGS that can be set per board, e.g., to inject specific settings. Will be used by IOT2050 first to define multiple of-lists. Signed-off-by: Jan Kiszka --- CC: Simon Glass --- Makefile | 1 + 1 file changed, 1 insertion(+) >>> >>> I'm really not keen on this, since it means that the Makefile (or some >>> vars it sets) are again involved in controlling the image generation. >>> It should really all be in the binman image description / .dtsi file >> >> binman does not allow me to unrole of-list inside the dts file, does it? >> With such a feature, I wouldn't need any custom -a of-list-X switches >> and, thus, no such EXTRA_ARGS. > > Can you explain a bit more about what you mean by 'unrole'? It is just > software, so anything should be possible. To use a DT sequence, I need to specify fit,ftd-list. But I can say fit,ftd-list = "first.dtb second.dtb" I rather need to go via the EntryArg indirection of the binman command line. Jan -- Siemens AG, Technology Competence Center Embedded Linux
Re: [PATCH 1/3] binman: Allow to define custom arguments
Hi Jan, On Thu, 15 Jun 2023 at 11:26, Jan Kiszka wrote: > > On 12.06.23 23:17, Simon Glass wrote: > > Hi Jan, > > > > On Mon, 5 Jun 2023 at 15:39, Jan Kiszka wrote: > >> > >> From: Jan Kiszka > >> > >> Introduce BINMAN_EXTRA_ARGS that can be set per board, e.g., to inject > >> specific settings. Will be used by IOT2050 first to define multiple > >> of-lists. > >> > >> Signed-off-by: Jan Kiszka > >> --- > >> CC: Simon Glass > >> --- > >> Makefile | 1 + > >> 1 file changed, 1 insertion(+) > > > > I'm really not keen on this, since it means that the Makefile (or some > > vars it sets) are again involved in controlling the image generation. > > It should really all be in the binman image description / .dtsi file > > binman does not allow me to unrole of-list inside the dts file, does it? > With such a feature, I wouldn't need any custom -a of-list-X switches > and, thus, no such EXTRA_ARGS. Can you explain a bit more about what you mean by 'unrole'? It is just software, so anything should be possible. Regards, Simon > > Jan > > -- > Siemens AG, Technology > Competence Center Embedded Linux >
Re: [PATCH v3 2/2] usb: musb-new: sunxi: clarify the purpose of SRAM initialization
On Mon, 12 Jun 2023 14:03:02 -0600
Sam Edwards wrote:
> This is largely a cosmetic change, with one functional distinction:
> We are now only setting BIT(0), and no longer clearing BIT(1).
>
> The A20 manual confirms the purpose and bitwidth of this field, and we
> have also been doing it this way for a while in Linux-land: The prior
> narrative about this initialization being about configuring a FIFO has
> pretty much been debunked for years now.
>
> This cleanup also adds a TODO comment about runtime discovery
> of the SYSCON base, per discussion with Andre.
>
> Signed-off-by: Sam Edwards
Reviewed-by: Andre Przywara
Thanks for the changes!
Cheers,
Andre
> Cc: Andre Przywara
> ---
> drivers/usb/musb-new/sunxi.c | 31 ++-
> 1 file changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
> index a67eaf..a8b1a8f870 100644
> --- a/drivers/usb/musb-new/sunxi.c
> +++ b/drivers/usb/musb-new/sunxi.c
> @@ -171,15 +171,22 @@ static void USBC_ForceVbusValidToHigh(__iomem void
> *base)
> musb_writel(base, USBC_REG_o_ISCR, reg_val);
> }
>
> -static void USBC_ConfigFIFO_Base(void)
> -{
> - u32 reg_value;
> +/**
> + * Non-USBC register access needed for initialization
> +
> **/
>
> - /* config usb fifo, 8kb mode */
> - reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
> - reg_value &= ~(0x03 << 0);
> - reg_value |= BIT(0);
> - writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
> +/*
> + * A10(s), A13, GR8, A20:
> + * switch ownership of SRAM block 'D' to the USB-OTG controller
> + */
> +static void sunxi_musb_claim_sram(uintptr_t syscon_base)
> +{
> + /*
> + * BIT(0) of SRAM_CTRL_REG1 (syscon+0x04) controls SRAM-D ownership:
> + * '0' -> exclusive access by CPU
> + * '1' -> exclusive access by USB0
> + */
> + setbits_le32(syscon_base + 0x04, BIT(0));
> }
>
>
> /**
> @@ -313,7 +320,13 @@ static int sunxi_musb_init(struct musb *musb)
> musb->isr = sunxi_musb_interrupt;
>
> if (glue->cfg->has_sram) {
> - USBC_ConfigFIFO_Base();
> + /*
> + * This is an older USB-OTG controller that Allwinner did not
> + * endow with a dedicated SRAM block; it instead uses SRAM
> + * block 'D', ownership of which needs to be handed over by
> + * the CPU
> + */
> + sunxi_musb_claim_sram(SUNXI_SRAMC_BASE);
> }
>
> USBC_EnableDpDmPullUp(musb->mregs);
Re: [PATCH 1/3] binman: Allow to define custom arguments
On 12.06.23 23:17, Simon Glass wrote: > Hi Jan, > > On Mon, 5 Jun 2023 at 15:39, Jan Kiszka wrote: >> >> From: Jan Kiszka >> >> Introduce BINMAN_EXTRA_ARGS that can be set per board, e.g., to inject >> specific settings. Will be used by IOT2050 first to define multiple >> of-lists. >> >> Signed-off-by: Jan Kiszka >> --- >> CC: Simon Glass >> --- >> Makefile | 1 + >> 1 file changed, 1 insertion(+) > > I'm really not keen on this, since it means that the Makefile (or some > vars it sets) are again involved in controlling the image generation. > It should really all be in the binman image description / .dtsi file binman does not allow me to unrole of-list inside the dts file, does it? With such a feature, I wouldn't need any custom -a of-list-X switches and, thus, no such EXTRA_ARGS. Jan -- Siemens AG, Technology Competence Center Embedded Linux
[PATCH v2 2/3] riscv: dts: sync mpfs-icicle devicetree with linux
The "notable" disappearances are:
- the pac193x stanza - there's nothing in mainline linux w.r.t. bindings
for this & what is going to appear in mainline linux is going to be
incompatible with what is currently in U-Boot.
- operating points - these operating points should not be set at the
soc.dtsi level as they may not be possible depending on the design
programmed to the FPGA
- clock output names - there are defines for the clock indices, these
should not be needed
- the dt maintainers in linux NAKed using defines for IRQ numbers
- the qspi nand, which is not part of the icicle's default configuration
is removed.
Reviewed-by: Padmarao Begari
Tested-by: Padmarao Begari
Signed-off-by: Conor Dooley
---
arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi| 71 +++
arch/riscv/dts/mpfs-icicle-kit.dts| 190 +---
arch/riscv/dts/mpfs.dtsi | 442 --
.../dt-bindings/clock/microchip-mpfs-clock.h | 29 +-
.../microchip-mpfs-plic.h | 196
.../interrupt-controller/riscv-hart.h | 17 -
6 files changed, 420 insertions(+), 525 deletions(-)
create mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
delete mode 100644
include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h
delete mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
new file mode 100644
index 00..1069134f2e
--- /dev/null
+++ b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/ {
+ compatible = "microchip,mpfs-icicle-reference-rtlv2210",
"microchip,mpfs-icicle-kit",
+"microchip,mpfs";
+
+ core_pwm0: pwm@4000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ reg = <0x0 0x4000 0x0 0xF0>;
+ microchip,sync-update-mask = /bits/ 32 <0>;
+ #pwm-cells = <3>;
+ clocks = <_nw CLK_CCC_PLL0_OUT3>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@4200 {
+ compatible = "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x4200 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <_nw CLK_CCC_PLL0_OUT3>;
+ interrupt-parent = <>;
+ interrupts = <122>;
+ clock-frequency = <10>;
+ status = "disabled";
+ };
+
+ pcie: pcie@30 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x30 0x0 0x0 0x800>, <0x0 0x4300 0x0 0x1>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 _intc 0>,
+ <0 0 0 2 _intc 1>,
+ <0 0 0 3 _intc 2>,
+ <0 0 0 4 _intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <_nw CLK_CCC_PLL0_OUT1>, <_nw
CLK_CCC_PLL0_OUT3>;
+ clock-names = "fic1", "fic3";
+ ranges = <0x300 0x0 0x800 0x30 0x800 0x0
0x8000>;
+ dma-ranges = <0x0200 0x0 0x 0x0 0x 0x1
0x>;
+ msi-parent = <>;
+ msi-controller;
+ status = "disabled";
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ refclk_ccc: cccrefclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+};
+
+_nw {
+ clocks = <_ccc>, <_ccc>, <_ccc>, <_ccc>,
+<_ccc>, <_ccc>;
+ clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+ "dll0_ref", "dll1_ref";
+ status = "okay";
+};
diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts
b/arch/riscv/dts/mpfs-icicle-kit.dts
index 3c56400b92..8aa5fb17d6 100644
--- a/arch/riscv/dts/mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/mpfs-icicle-kit.dts
@@ -7,29 +7,63 @@
/dts-v1/;
#include "mpfs.dtsi"
+#include "mpfs-icicle-kit-fabric.dtsi"
+#include
+#include
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ100
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
- compatible = "microchip,mpfs-icicle-reference-rtlv2210",
-"microchip,mpfs-icicle-kit", "microchip,mpfs";
+ compatible = "microchip,mpfs-icicle-reference-rtlv2210",
[PATCH v2 3/3] board: microchip: set mac address for ethernet1 on icicle
The dts sync from Linux leaves mac0/ethernet1 enabled on icicle, but
U-Boot does not currently set a mac address for it. Expand on the code
which currently sets the mac for mac1/ethernet0 to optionally set the
mac address for the second ethernet.
Reviewed-by: Padmarao Begari
Tested-by: Padmarao Begari
Signed-off-by: Conor Dooley
---
board/microchip/mpfs_icicle/mpfs_icicle.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index e74c9fb03c..0f5f82924e 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -80,7 +80,7 @@ int board_late_init(void)
char icicle_mac_addr[20];
void *blob = (void *)gd->fdt_blob;
- node = fdt_path_offset(blob, "ethernet0");
+ node = fdt_path_offset(blob, "/soc/ethernet@20112000");
if (node < 0) {
printf("No ethernet0 path offset\n");
return -ENODEV;
@@ -88,7 +88,7 @@ int board_late_init(void)
ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr,
6);
if (ret) {
- printf("No local-mac-address property\n");
+ printf("No local-mac-address property for ethernet@20112000\n");
return -EINVAL;
}
@@ -104,7 +104,7 @@ int board_late_init(void)
ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
if (ret) {
- printf("Error setting local-mac-address property\n");
+ printf("Error setting local-mac-address property for
ethernet@20112000\n");
return -ENODEV;
}
@@ -123,6 +123,15 @@ int board_late_init(void)
mac_addr[5] = device_serial_number[0] + 1;
+ node = fdt_path_offset(blob, "/soc/ethernet@2011");
+ if (node >= 0) {
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting local-mac-address property for
ethernet@2011\n");
+ return -ENODEV;
+ }
+ }
+
icicle_mac_addr[0] = '[';
sprintf(_mac_addr[1], "%pM", mac_addr);
--
2.40.1
[PATCH v2 1/3] riscv: dts: drop microchip from dts filenames
The original names picked for the DT doesn't match Linux's naming scheme
and it was renamed there a while ago. Rename it in U-Boot to allow
easily syncing dts between the two projects.
Reviewed-by: Rick Chen
Reviewed-by: Padmarao Begari
Signed-off-by: Conor Dooley
---
arch/riscv/dts/Makefile | 2 +-
...s-icicle-kit-u-boot.dtsi => mpfs-icicle-kit-u-boot.dtsi} | 0
.../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 2 +-
arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} | 0
configs/microchip_mpfs_icicle_defconfig | 2 +-
doc/board/microchip/mpfs_icicle.rst | 6 +++---
6 files changed, 6 insertions(+), 6 deletions(-)
rename arch/riscv/dts/{microchip-mpfs-icicle-kit-u-boot.dtsi =>
mpfs-icicle-kit-u-boot.dtsi} (100%)
rename arch/riscv/dts/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts}
(98%)
rename arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} (100%)
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79a58694f5..1d61eb8020 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
-dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
similarity index 100%
rename from arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
rename to arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/mpfs-icicle-kit.dts
similarity index 98%
rename from arch/riscv/dts/microchip-mpfs-icicle-kit.dts
rename to arch/riscv/dts/mpfs-icicle-kit.dts
index c3f58e2d56..3c56400b92 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/mpfs-icicle-kit.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "microchip-mpfs.dtsi"
+#include "mpfs.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ100
diff --git a/arch/riscv/dts/microchip-mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi
similarity index 100%
rename from arch/riscv/dts/microchip-mpfs.dtsi
rename to arch/riscv/dts/mpfs.dtsi
diff --git a/configs/microchip_mpfs_icicle_defconfig
b/configs/microchip_mpfs_icicle_defconfig
index c03c8ec6ec..fa49d3865f 100644
--- a/configs/microchip_mpfs_icicle_defconfig
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
+CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit"
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_MEM_TOP_HIDE=0x40
CONFIG_SYS_LOAD_ADDR=0x8020
diff --git a/doc/board/microchip/mpfs_icicle.rst
b/doc/board/microchip/mpfs_icicle.rst
index 09c2c6a9c1..1464e536e9 100644
--- a/doc/board/microchip/mpfs_icicle.rst
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -134,7 +134,7 @@ Build OpenSBI
.. code-block:: none
make PLATFORM=generic FW_PAYLOAD_PATH=/u-boot.bin
- FW_FDT_PATH=/arch/riscv/dts/microchip-mpfs-icicle-kit-.dtb
+ FW_FDT_PATH=/arch/riscv/dts/mpfs-icicle-kit-.dtb
3. Output "fw_payload.bin" file available at
"/build/platform/generic/firmware/fw_payload.bin"
@@ -277,14 +277,14 @@ load uImage (with initramfs).
done
Bytes transferred = 14482480 (dcfc30 hex)
- RISC-V # tftpboot ${fdt_addr_r} microchip-mpfs-icicle-kit.dtb
+ RISC-V # tftpboot ${fdt_addr_r} mpfs-icicle-kit.dtb
ethernet@20112000: PHY present at 9
ethernet@20112000: Starting autonegotiation...
ethernet@20112000: Autonegotiation complete
ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800)
Using ethernet@20112000 device
TFTP from server 192.168.1.3; our IP address is 192.168.1.5
- Filename 'microchip-mpfs-icicle-kit.dtb'.
+ Filename 'mpfs-icicle-kit.dtb'.
Load address: 0x8220
Loading: #
2.5 MiB/s
--
2.40.1
[PATCH v2 0/3] Sync PolarFire SoC dts with Linux
Hey,
Couple of patches here that do a long-overdue sync of the Linux
devicetree for PolarFire SoC & the Icicle kit with Linux.
This wasn't possible for a while due to an incorrect dts & clock driver
that were based on a pre-upstream version of the dt-binding. That's
fixed now, so a complete re-sync is possible.
To elide complaints about the mac address not being set for the second
ethernet, the code which set it for ethernet0 has been changed to set it
for whichever (or both) of the macbs that are enabled.
Hopefully I'll have a follow-on bit of work soonTM that will rework the
mac address setting code as it'll be needed to support another board.
Cheers,
Conor.
Changes in v2:
- Fix address in error print in 3/3
Conor Dooley (3):
riscv: dts: drop microchip from dts filenames
riscv: dts: sync mpfs-icicle devicetree with linux
board: microchip: set mac address for ethernet1 on icicle
arch/riscv/dts/Makefile | 2 +-
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 136 --
arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi| 71 +++
...-boot.dtsi => mpfs-icicle-kit-u-boot.dtsi} | 0
arch/riscv/dts/mpfs-icicle-kit.dts| 208 +
.../dts/{microchip-mpfs.dtsi => mpfs.dtsi}| 442 --
board/microchip/mpfs_icicle/mpfs_icicle.c | 15 +-
configs/microchip_mpfs_icicle_defconfig | 2 +-
doc/board/microchip/mpfs_icicle.rst | 6 +-
.../dt-bindings/clock/microchip-mpfs-clock.h | 29 +-
.../microchip-mpfs-plic.h | 196
.../interrupt-controller/riscv-hart.h | 17 -
12 files changed, 514 insertions(+), 610 deletions(-)
delete mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
create mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
rename arch/riscv/dts/{microchip-mpfs-icicle-kit-u-boot.dtsi =>
mpfs-icicle-kit-u-boot.dtsi} (100%)
create mode 100644 arch/riscv/dts/mpfs-icicle-kit.dts
rename arch/riscv/dts/{microchip-mpfs.dtsi => mpfs.dtsi} (57%)
delete mode 100644
include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h
delete mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
--
2.40.1
[GIT PULL] please pull fsl-qoriq-2023-6-15 for next
Hi Tom, Please pull fsl-qoriq-2023-6-15 for next. DM_MDIO/CMD for ls1046afrwy sync APIs for fsl-mc ldpaa_eth update lx2160ardb recv support. net: dsa fix of fallback lookup CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/16597 Thanks, Peng. The following changes since commit cb4fe56eca1109780e97c68329e6b71ef33bf0e6: Merge tag 'tpm-for_tom-13062023' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next (2023-06-13 13:14:49 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git tags/fsl-qoriq-2023-6-15 for you to fetch changes up to b824212dc29b5b0354e84c7dadec21d75bacb349: configs: ls1046afrwy: enable DM_MDIO and DM_CMD (2023-06-15 17:58:53 +0800) Camelia Groza (3): arm: dts: ls1046afrwy: add the FMan Ethernet nodes board: freescale: ls1046afrwy: enumerate PCI devices configs: ls1046afrwy: enable DM_MDIO and DM_CMD Florin Chiculita (2): board: fsl: lx2160ardb: add api for obtaining board revision board: fsl: lx2160ardb: add dts fixup function for RevC and newer Ioana Ciornei (14): net: ldpaa_eth: fix the memory layout of the dpmac_get_counters() API net: ldpaa_eth: transform dpni_statistics from a struct to a union net: ldpaa_eth: extend debug capabilities with DPNI statistics net: ldpaa_eth: extend debug capabilities with DPMAC statistics cmd: net: add a 'net stats' command to dump network statistics net: ldpaa_eth: export DPNI and DPMAC counters through 'net stats' net: fsl-mc: remove unused MC APIs net: fsl-mc: sync DPBP MC APIs net: fsl-mc: sync DPMAC MC APIs net: fsl-mc: sync DPRC MC APIs net: fsl-mc: sync DPNI MC APIs net: fsl-mc: sync DPSPARSER MC APIs net: fsl-mc: sync DPIO MC APIs net: fsl-mc: sync remaining MC commands Marcus Comstedt (1): net: dsa: Fix OF fallback lookup for ports arch/arm/dts/fsl-ls1046a-frwy.dts | 48 ++- board/freescale/ls1046afrwy/ls1046afrwy.c |3 + board/freescale/lx2160a/eth_lx2160ardb.c | 107 +++ board/freescale/lx2160a/lx2160a.c | 22 +- board/freescale/lx2160a/lx2160a.h | 15 + cmd/net.c | 54 +++- configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig |2 + configs/ls1046afrwy_tfa_defconfig |2 + drivers/net/fsl-mc/dpbp.c | 180 --- drivers/net/fsl-mc/dpio/dpio.c| 194 +++ drivers/net/fsl-mc/dpmac.c| 274 drivers/net/fsl-mc/dpmng.c| 20 +- drivers/net/fsl-mc/dpni.c | 680 ++- drivers/net/fsl-mc/dprc.c | 405 +++ drivers/net/fsl-mc/dpsparser.c| 124 ++-- drivers/net/fsl-mc/fsl_dpmng_cmd.h| 17 +- drivers/net/fsl-mc/mc.c | 14 +- drivers/net/fsl-mc/mc_sys.c | 13 +- drivers/net/ldpaa_eth/ldpaa_eth.c | 268 drivers/net/ldpaa_eth/ldpaa_eth.h | 64 include/configs/lx2160ardb.h |5 + include/fsl-mc/fsl_dpbp.h | 207 ++-- include/fsl-mc/fsl_dpio.h | 266 +--- include/fsl-mc/fsl_dpmac.h| 365 + include/fsl-mc/fsl_dpmng.h| 13 +- include/fsl-mc/fsl_dpni.h | 1660 +++ include/fsl-mc/fsl_dprc.h | 935 ++--- include/fsl-mc/fsl_dpsparser.h| 139 ++-- include/fsl-mc/fsl_mc_cmd.h | 47 +-- include/net.h |6 + net/dsa-uclass.c |2 +- 31 files changed, 2593 insertions(+), 3558 deletions(-)
[PATCH v5 11/11] board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
The main difference between StarFive VisionFive 2 1.2A and 1.3B is gmac.
You can read the PCB version of the current board by
get_pcb_revision_from_eeprom(), and then dynamically configure the
difference of gmac in spl_perform_fixups() according to different PCB
versions, so that one DT and one defconfig can support both 1.2A and
1.3B versions, which is more user-friendly.
Signed-off-by: Yanhong Wang
---
board/starfive/visionfive2/spl.c | 157 +++
1 file changed, 157 insertions(+)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index db0b4cb433..7acd3995aa 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -5,16 +5,173 @@
*/
#include
+#include
#include
#include
#include
+#include
+#include
+#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
#define JH7110_CLK_CPU_ROOT_SHIFT 24
#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+struct starfive_vf2_pro {
+ const char *path;
+ const char *name;
+ const char *value;
+};
+
+static const struct starfive_vf2_pro starfive_vera[] = {
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "rx-internal-delay-ps",
+ "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "tx-internal-delay-ps",
+ "1350"}
+};
+
+static const struct starfive_vf2_pro starfive_verb[] = {
+ {"/soc/ethernet@1603", "starfive,tx-use-rgmii-clk", NULL},
+ {"/soc/ethernet@1604", "starfive,tx-use-rgmii-clk", NULL},
+
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-1000-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "rx-internal-delay-ps", "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "tx-internal-delay-ps", "1500"},
+
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ { "/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "rx-internal-delay-ps", "0"},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "tx-internal-delay-ps", "0"},
+};
+
+void spl_fdt_fixup_version_a(void *fdt)
+{
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "StarFive VisionFive 2 v1.2A");
+
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@1302");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@1604");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_TX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_RX);
+
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@1604"),
+ "phy-mode", "rmii");
+
+ for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
+ offset = fdt_path_offset(fdt, starfive_vera[i].path);
+
+ if (starfive_vera[i].value)
+ ret = fdt_setprop_u32(fdt, offset,
starfive_vera[i].name,
+ dectoul(starfive_vera[i].value,
NULL));
+ else
+ ret = fdt_setprop_empty(fdt, offset,
starfive_vera[i].name);
+
+ if (ret) {
+ pr_err("%s set prop %s fail.\n", __func__,
starfive_vera[i].name);
+ break;
+ }
+ }
+}
+
+void spl_fdt_fixup_version_b(void *fdt)
+{
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "StarFive VisionFive 2 v1.3B");
+
+ /* gmac0 */
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@1700");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@1603");
+
+
[PATCH v5 10/11] ram: starfive: Read memory size information from EEPROM
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.
If there is no information in EEPROM, it is initialized with the default
size defined in DT.
Signed-off-by: Yanhong Wang
---
arch/riscv/cpu/jh7110/spl.c | 32 -
drivers/ram/starfive/starfive_ddr.c | 2 --
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 104f0fe949..72adcefa0e 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,19 +3,49 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Author: Yanhong Wang
*/
-
+#include
+#include
#include
#include
#include
+#include
#include
+#include
#define CSR_U74_FEATURE_DISABLE0x7c1
#define L2_LIM_MEM_END 0x81FUL
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool check_ddr_size(phys_size_t size)
+{
+ switch (size) {
+ case SZ_2:
+ case SZ_4:
+ case SZ_8:
+ case SZ_16:
+ return true;
+ default:
+ return false;
+ }
+}
+
int spl_soc_init(void)
{
int ret;
struct udevice *dev;
+ phys_size_t size;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ /* Read the definition of the DDR size from eeprom, and if not,
+* use the definition in DT
+*/
+ size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
+ if (check_ddr_size(size))
+ gd->ram_size = size << 30;
/* DDR init */
ret = uclass_get_device(UCLASS_RAM, 0, );
diff --git a/drivers/ram/starfive/starfive_ddr.c
b/drivers/ram/starfive/starfive_ddr.c
index 553f2ce6f4..a0a3d6b33d 100644
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -72,8 +72,6 @@ static int starfive_ddr_probe(struct udevice *dev)
u64 rate;
int ret;
- /* Read memory base and size from DT */
- fdtdec_setup_mem_size_base();
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;
--
2.17.1
[PATCH v5 08/11] riscv: dts: starfive: Add support eeprom device tree node
Add support "atmel,24c04" eeprom for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 14 ++
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 ++
2 files changed, 20 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 2afcec30b8..13f69da31e 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -67,6 +67,20 @@
};
};
+_pins {
+ bootph-pre-ram;
+ i2c-pins {
+ bootph-pre-ram;
+ };
+};
+
+ {
+ bootph-pre-ram;
+ eeprom@50 {
+ bootph-pre-ram;
+ };
+};
+
{
itb {
fit {
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 3c1148ae2d..710b082766 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -120,6 +120,12 @@
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
{
--
2.17.1
[PATCH v5 09/11] configs: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM and I2C configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
.../visionfive2/starfive_visionfive2.c| 13 +
configs/starfive_visionfive2_defconfig| 19 ++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
index 613fe793c4..07dcca26b3 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -6,7 +6,9 @@
#include
#include
+#include
#include
+#include
#include
#define JH7110_L2_PREFETCHER_BASE_ADDR 0x203
@@ -38,3 +40,14 @@ int board_init(void)
return 0;
}
+
+void *board_fdt_blob_setup(int *err)
+{
+ *err = 0;
+ if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
+ if (gd->arch.firmware_fdt_addr)
+ return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+ }
+
+ return (ulong *)&_end;
+}
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index c57708199d..570a1f53a1 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="StarFive #"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x818
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -23,6 +24,7 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
+# CONFIG_OF_BOARD_FIXUP is not set
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
@@ -34,6 +36,8 @@ CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr
${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=5
CONFIG_SPL_MAX_SIZE=0x4
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_BSS_START_ADDR=0x804
@@ -45,21 +49,34 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
CONFIG_SYS_SPL_MALLOC_SIZE=0x40
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_SIZE=512
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
-# CONFIG_I2C is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0X50
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
--
2.17.1
[PATCH v5 07/11] eeprom: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
.../visionfive2/visionfive2-i2c-eeprom.c | 561 ++
3 files changed, 575 insertions(+)
create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h
b/arch/riscv/include/asm/arch-jh7110/eeprom.h
new file mode 100644
index 00..f354d5c60c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+u8 get_pcb_revision_from_eeprom(void);
+u32 get_ddr_size_from_eeprom(void);
+
+#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/board/starfive/visionfive2/Makefile
b/board/starfive/visionfive2/Makefile
index 66c854df39..c7ba4f7ed6 100644
--- a/board/starfive/visionfive2/Makefile
+++ b/board/starfive/visionfive2/Makefile
@@ -5,3 +5,4 @@
obj-y := starfive_visionfive2.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
new file mode 100644
index 00..befe7888c4
--- /dev/null
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define FORMAT_VERSION 0x2
+#define PCB_VERSION0xB1
+#define BOM_VERSION'A'
+/*
+ * BYTES_PER_EEPROM_PAGE: the 24FC04H datasheet says that data can
+ * only be written in page mode, which means 16 bytes at a time:
+ * 16-Byte Page Write Buffer
+ */
+#define BYTES_PER_EEPROM_PAGE 16
+
+/*
+ * EEPROM_WRITE_DELAY_MS: the 24FC04H datasheet says it takes up to
+ * 5ms to complete a given write:
+ * Write Cycle Time (byte or page) ro Page Write Time 5 ms, Maximum
+ */
+#define EEPROM_WRITE_DELAY_MS 5000
+/*
+ * StarFive OUI. Registration Date is 20xx-xx-xx
+ */
+#define STARFIVE_OUI_PREFIX"6C:CF:39:"
+#define STARFIVE_DEFAULT_MAC0 "6C:CF:39:6C:DE:AD"
+#define STARFIVE_DEFAULT_MAC1 "6C:CF:39:6C:DE:AE"
+
+/* Magic number at the first four bytes of EEPROM HATs */
+#define STARFIVE_EEPROM_HATS_SIG "SFVF" /* StarFive VisionFive */
+
+#define STARFIVE_EEPROM_HATS_SIZE_MAX 256 /* Header + Atom1&4(v1) */
+#define STARFIVE_EEPROM_WP_OFFSET 0 /* Read only field */
+#define STARFIVE_EEPROM_ATOM1_PSTR "VF7110A1-2228-D008E000-0001\0"
+#define STARFIVE_EEPROM_ATOM1_PSTR_SIZE32
+#define STARFIVE_EEPROM_ATOM1_SN_OFFSET23
+#define STARFIVE_EEPROM_ATOM1_VSTR "StarFive Technology Co., Ltd.\0\0\0"
+#define STARFIVE_EEPROM_ATOM1_VSTR_SIZE32
+
+#define MAGIC_NUMBER_BYTES 4
+#define MAC_ADDR_BYTES 6
+#define MAC_ADDR_STRLEN17
+
+/*
+ * Atom Types
+ * 0x = invalid
+ * 0x0001 = vendor info
+ * 0x0002 = GPIO map
+ * 0x0003 = Linux device tree blob
+ * 0x0004 = manufacturer custom data
+ * 0x0005-0xfffe = reserved for future use
+ * 0x = invalid
+ */
+
+#define HATS_ATOM_INVALID 0x
+#define HATS_ATOM_VENDOR 0x0001
+#define HATS_ATOM_GPIO 0x0002
+#define HATS_ATOM_DTB 0x0003
+#define HATS_ATOM_CUSTOM 0x0004
+#define HATS_ATOM_INVALID_END 0x
+
+struct eeprom_header {
+ char signature[MAGIC_NUMBER_BYTES]; /* ASCII table signature */
+ u8 version; /* EEPROM data format version */
+ /* (0x00 reserved, 0x01 = first version) */
+ u8 reversed;/* 0x00, Reserved field */
+ u16 numatoms; /* total atoms in EEPROM */
+ u32 eeplen; /* total length in bytes of all eeprom data */
+ /* (including this header) */
+};
+
+struct eeprom_atom_header {
+ u16 type;
+ u16 count;
+ u32 dlen;
+};
+
+struct eeprom_atom1_data {
+ u8 uuid[16];
+ u16 pid;
+ u16 pver;
+ u8 vslen;
+ u8 pslen;
+ uchar vstr[STARFIVE_EEPROM_ATOM1_VSTR_SIZE];
+ uchar pstr[STARFIVE_EEPROM_ATOM1_PSTR_SIZE]; /* product SN */
+};
+
+struct starfive_eeprom_atom1 {
+ struct eeprom_atom_header header;
+ struct eeprom_atom1_data data;
+ u16 crc;
+};
+
+struct eeprom_atom4_data {
+ u16 version;
+ u8 pcb_revision;/* PCB version */
+ u8 bom_revision;/* BOM version */
+ u8 mac0_addr[MAC_ADDR_BYTES]; /* Ethernet0 MAC */
+ u8 mac1_addr[MAC_ADDR_BYTES];
[PATCH v5 05/11] doc: board: starfive: Reword the make defconfig information
The defconfig file name for StarFive VisionFive2 has been changed, and
the documentation description has also changed.
Signed-off-by: Yanhong Wang
---
doc/board/starfive/visionfive2.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/doc/board/starfive/visionfive2.rst
b/doc/board/starfive/visionfive2.rst
index 4d43ac9729..951e0d80fb 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -62,7 +62,7 @@ Now build the U-Boot SPL and U-Boot proper
.. code-block:: console
cd
- make starfive_visionfive2_13b_defconfig
+ make starfive_visionfive2_defconfig
make
OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
@@ -118,7 +118,7 @@ Program the SD card
sudo cp u-boot.itb /mnt/
sudo cp Image.gz /mnt/
sudo cp initramfs.cpio.gz /mnt/
- sudo cp jh7110-starfive-visionfive-2-v1.3b.dtb /mnt/
+ sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
Booting
@@ -264,7 +264,7 @@ Sample boot log from StarFive VisionFive2 board
StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
6429424 bytes read in 394 ms (15.6 MiB/s)
- StarFive #fatload mmc 1:3 ${fdt_addr_r}
jh7110-starfive-visionfive-2-v1.3b.dtb
+ StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2.dtb
11285 bytes read in 5 ms (2.2 MiB/s)
StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
152848495 bytes read in 9271 ms (15.7 MiB/s)
--
2.17.1
[PATCH v5 06/11] configs: starfive: Enable ethernet configuration for StarFive VisionFive2
Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet function for StarFive VisionFive 2 board,including versions 1.2A and 1.3B. Signed-off-by: Yanhong Wang --- configs/starfive_visionfive2_defconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 566d2c3d0e..c57708199d 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -54,6 +54,8 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_MEMINFO=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_JH7110=y @@ -66,6 +68,13 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_STARFIVE=y +CONFIG_RGMII=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y -- 2.17.1
[PATCH v5 02/11] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang
Reviewed-by: Ramon Fried
---
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 +
5 files changed, 264 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09039a283e..5540f0ea18 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in Qcom QCS404 SoC.
+config DWC_ETH_QOS_STARFIVE
+ bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE JH7110 soc.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46a40e2ed9..d4af253b6f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9bbba6eed0..1e92bd9ca9 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1725,6 +1725,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)_qcom_config
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)_jh7110_config
+ },
+#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c
b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 00..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
+
+struct starfive_platform_data {
+ struct regmap *regmap;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ phy_interface_t interface;
+ u32 offset;
+ u32 shift;
+ bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+ struct ofnode_phandle_args args;
+ unsigned int mode;
+ int ret;
+
+ switch (data->interface) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+2, 0, );
+ if (ret)
+ return ret;
+
+ if (args.args_count != 2)
+ return -EINVAL;
+
+ data->offset = args.args[0];
+ data->shift = args.args[1];
+ data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+ if (IS_ERR(data->regmap)) {
+ ret = PTR_ERR(data->regmap);
+ pr_err("Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_update_bits(data->regmap, data->offset,
+ STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+ mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata =
[PATCH v5 04/11] riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B
The difference between 1.2A and 1.3B is dynamically configured according
to the PCB version, and there is no difference on the board device tree,
so the same DT file can be used.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 25 ++-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
configs/starfive_visionfive2_defconfig| 4 +-
6 files changed, 28 insertions(+), 88 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (66%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
jh7110-starfive-visionfive-2.dts} (65%)
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79a58694f5..7940fe466d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,8 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.3b.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.2a.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
similarity index 66%
rename from arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
rename to arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 3c322c5c97..2afcec30b8 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
*/
#include "binman.dtsi"
@@ -67,3 +67,26 @@
};
};
+ {
+ itb {
+ fit {
+ images {
+ fdt-1 {
+ description = "NAME";
+ load = <0x4040>;
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ conf-1 {
+ fdt = "fdt-1";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
deleted file mode 100644
index b9d26d7af7..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-/dts-v1/;
-#include "jh7110-starfive-visionfive-2.dtsi"
-
-/ {
- model = "StarFive VisionFive 2 v1.2A";
- compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
-};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
deleted file mode 100644
index 3c322c5c97..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-#include "binman.dtsi"
-#include "jh7110-u-boot.dtsi"
-/ {
- chosen {
- bootph-pre-ram;
- };
-
- firmware {
- spi0 =
- bootph-pre-ram;
- };
-
- config {
- bootph-pre-ram;
- u-boot,spl-payload-offset = <0x10>;
- };
-
- memory@4000 {
- bootph-pre-ram;
- };
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-
- nor-flash@0 {
- bootph-pre-ram;
- };
-};
-
- {
- bootph-pre-ram;
-};
-
-_pins {
- bootph-pre-ram;
- mmc0-pins-rest {
- bootph-pre-ram;
- };
-};
-
-_pins {
- bootph-pre-ram;
- mmc1-pins0 {
-
[PATCH v5 03/11] riscv: dts: jh7110: Add ethernet device tree nodes
Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 34 +
arch/riscv/dts/jh7110.dtsi| 69 +++
2 files changed, 103 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..3c1148ae2d 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
i2c2 =
i2c5 =
i2c6 =
+ ethernet0 =
+ ethernet1 =
};
chosen {
@@ -317,3 +319,35 @@
assigned-clock-parents = <>;
assigned-clock-rates = <0>;
};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..58e332e9d7 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
#clock-cells = <0>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <4>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -539,6 +546,68 @@
status = "disabled";
};
+ gmac0: ethernet@1603 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1603 0x0 0x1>;
+ clocks = < JH7110_AONCLK_GMAC0_AXI>,
+< JH7110_AONCLK_GMAC0_AHB>,
+< JH7110_SYSCLK_GMAC0_PTP>,
+< JH7110_AONCLK_GMAC0_TX_INV>,
+< JH7110_SYSCLK_GMAC0_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_AONRST_GMAC0_AXI>,
+< JH7110_AONRST_GMAC0_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <7>, <6>, <5>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <_syscon 0xc 0x12>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@1604 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1604 0x0 0x1>;
+ clocks = < JH7110_SYSCLK_GMAC1_AXI>,
+< JH7110_SYSCLK_GMAC1_AHB>,
+< JH7110_SYSCLK_GMAC1_PTP>,
+< JH7110_SYSCLK_GMAC1_TX_INV>,
+< JH7110_SYSCLK_GMAC1_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_SYSRST_GMAC1_AXI>,
+< JH7110_SYSRST_GMAC1_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <78>, <77>, <76>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
[PATCH v5 01/11] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have verified the driver on StarFive VisionFive2 board. Signed-off-by: Yanhong Wang Reviewed-by: Ramon Fried --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile| 1 + drivers/net/phy/motorcomm.c | 437 3 files changed, 444 insertions(+) create mode 100644 drivers/net/phy/motorcomm.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 24158776f5..0c3c39a550 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -220,6 +220,12 @@ config PHY_MICREL_KSZ8XXX endif # PHY_MICREL +config PHY_MOTORCOMM + tristate "Motorcomm PHYs" + help + Enables support for Motorcomm network PHYs. + Currently supports the YT8531 Gigabit Ethernet PHYs. + config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 85d17f109c..2487f366e1 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c new file mode 100644 index 00..e822fd76f2 --- /dev/null +++ b/drivers/net/phy/motorcomm.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Motorcomm 8531 PHY driver. + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include + +#define PHY_ID_YT8531 0x4f51e91b +#define PHY_ID_MASKGENMASK(31, 0) + +/* Extended Register's Address Offset Register */ +#define YTPHY_PAGE_SELECT 0x1E + +/* Extended Register's Data Register */ +#define YTPHY_PAGE_DATA0x1F + +#define YTPHY_SYNCE_CFG_REG0xA012 + +#define YTPHY_DTS_OUTPUT_CLK_DIS 0 +#define YTPHY_DTS_OUTPUT_CLK_25M 2500 +#define YTPHY_DTS_OUTPUT_CLK_125M 12500 + +#define YT8531_SCR_SYNCE_ENABLEBIT(6) +/* 1b0 output 25m clock *default* + * 1b1 output 125m clock + */ +#define YT8531_SCR_CLK_FRE_SEL_125MBIT(4) +#define YT8531_SCR_CLK_SRC_MASKGENMASK(3, 1) +#define YT8531_SCR_CLK_SRC_PLL_125M0 +#define YT8531_SCR_CLK_SRC_UTP_RX 1 +#define YT8531_SCR_CLK_SRC_SDS_RX 2 +#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 +#define YT8531_SCR_CLK_SRC_REF_25M 4 +#define YT8531_SCR_CLK_SRC_SSC_25M 5 + +/* 1b0 use original tx_clk_rgmii *default* + * 1b1 use inverted tx_clk_rgmii. + */ +#define YT8531_RC1R_TX_CLK_SEL_INVERTEDBIT(14) +#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10) +#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) +#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) +#define YT8531_RC1R_RGMII_0_000_NS 0 +#define YT8531_RC1R_RGMII_0_150_NS 1 +#define YT8531_RC1R_RGMII_0_300_NS 2 +#define YT8531_RC1R_RGMII_0_450_NS 3 +#define YT8531_RC1R_RGMII_0_600_NS 4 +#define YT8531_RC1R_RGMII_0_750_NS 5 +#define YT8531_RC1R_RGMII_0_900_NS 6 +#define YT8531_RC1R_RGMII_1_050_NS 7 +#define YT8531_RC1R_RGMII_1_200_NS 8 +#define YT8531_RC1R_RGMII_1_350_NS 9 +#define YT8531_RC1R_RGMII_1_500_NS 10 +#define YT8531_RC1R_RGMII_1_650_NS 11 +#define YT8531_RC1R_RGMII_1_800_NS 12 +#define YT8531_RC1R_RGMII_1_950_NS 13 +#define YT8531_RC1R_RGMII_2_100_NS 14 +#define YT8531_RC1R_RGMII_2_250_NS 15 + +/* Phy gmii clock gating Register */ +#define YT8531_CLOCK_GATING_REG0xC +#define YT8531_CGR_RX_CLK_EN BIT(12) + +/* Specific Status Register */ +#define YTPHY_SPECIFIC_STATUS_REG 0x11 +#define YTPHY_DUPLEX_MASK BIT(13) +#define YTPHY_DUPLEX_SHIFT 13 +#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14) +#define YTPHY_SPEED_MODE_SHIFT 14 + +#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27 +#define YT8531_ESC1R_SLEEP_SW BIT(15) +#define YT8531_ESC1R_PLLON_SLP BIT(14) + +#define YT8531_RGMII_CONFIG1_REG 0xA003 + +#define YT8531_CHIP_CONFIG_REG 0xA001 +#define YT8531_CCR_SW_RST BIT(15) +/* 1b0 disable 1.9ns rxc clock delay *default* + * 1b1 enable 1.9ns rxc clock delay + */ +#define YT8531_CCR_RXC_DLY_EN
[PATCH v5 00/11] Add ethernet driver for StarFive JH7110 SoC
This series of patches base on the latest branch/master,and
adds ethernet support for the StarFive JH7110 RISC-V SoC.
The series includes EEPROM, PHY and MAC drivers. The PHY model is
YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20
(from Synopsys DesignWare).
The implementation of the phy driver is ported from linux, but it
has been adjusted for the u-boot framework.
EEPROM stores board-related information, such as DDR capacity,
PCB version, MAC address, etc.
The main difference between StarFive VisionFive 2 1.2A and 1.3B is
gmac, but the difference in gmac is not defined in DT, but reads the
PCB version from EEPROM, and then dynamically configures the difference
of gmac according to different PCB versions, which is compatible
with 1.2A and 1.3B versions, which is more user-friendly.
The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A
and 1.3B boards and works normally.
For more information and support,you can visit RVspace wiki[1].
[1] https://wiki.rvspace.org/
v5:
- Reorder a series of patches to make each patch is independent.
- Move CONFIG_DEFAULT_FDT_FILE and CONFIG_DEFAULT_DEVICE_TREE changes to patch
4.
- Move the definition of 'board_fdt_blob_setup' to patch 9.
v4:
- Reworded the definition of the 'pbuf' variable in visionfive2-i2c-eeprom.c
from a const pointer to const union.
- Added the section (".data") attribute to the 'pbuf' and 'has_been_read'
global
variables in visionfive2-i2-eeprom.c.
v3:
- Added EEPROM support.
- Combine the board device tree of 1.2A and 1.3B into one.
- Removed the delay configuration of gmac phy clock from DT.
- Dynamically configure gmac differences of 1.2A and 1.3B to DT according to
the PCB version.
- DDR capacity information is read from EEPROM first, if not, it is defined by
default in DT.
v2:
- Reworded the phy driver. Added platform private data struct to save the
configuration data read from dts.
- Reworded the MAC driver. Added platform private data struct to save the
configuration data read from dts.
Previous versions:
v1 -
https://patchwork.ozlabs.org/project/uboot/cover/20230317010536.17860-1-yanhong.w...@starfivetech.com/
v2 -
https://patchwork.ozlabs.org/project/uboot/cover/20230329102720.25439-1-yanhong.w...@starfivetech.com/
v3 -
https://patchwork.ozlabs.org/project/uboot/cover/20230428022515.29393-1-yanhong.w...@starfivetech.com/
v4 -
https://patchwork.ozlabs.org/project/uboot/cover/20230525093637.31364-1-yanhong.w...@starfivetech.com/
Yanhong Wang (11):
net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
net: dwc_eth_qos: Add StarFive ethernet driver glue layer
riscv: dts: jh7110: Add ethernet device tree nodes
riscv: dts: jh7110: Combine the board device tree files of 1.2A and
1.3B
doc: board: starfive: Reword the make defconfig information
configs: starfive: Enable ethernet configuration for StarFive
VisionFive2
eeprom: starfive: Enable ID EEPROM configuration
riscv: dts: starfive: Add support eeprom device tree node
configs: starfive: Enable ID EEPROM configuration
ram: starfive: Read memory size information from EEPROM
board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
arch/riscv/cpu/jh7110/spl.c | 32 +-
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 39 +-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12 -
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
.../dts/jh7110-starfive-visionfive-2.dtsi | 40 ++
arch/riscv/dts/jh7110.dtsi| 69 +++
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
board/starfive/visionfive2/spl.c | 157 +
.../visionfive2/starfive_visionfive2.c| 13 +
.../visionfive2/visionfive2-i2c-eeprom.c | 561 ++
configs/starfive_visionfive2_defconfig| 32 +-
doc/board/starfive/visionfive2.rst| 6 +-
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c| 249
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 437 ++
drivers/ram/starfive/starfive_ddr.c | 2 -
24 files changed, 1665 insertions(+), 95 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (58%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
[PATCH V2 12/30] imx: ele_api: add DEK Blob generation
From: Peng Fan
- Add crc computation.
- Add ele_generate_dek_blob API for encrypted boot support.
Signed-off-by: Clement Faure
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/ele_api.h | 2 +-
drivers/misc/imx_ele/ele_api.c | 44 +
2 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-imx/ele_api.h
b/arch/arm/include/asm/mach-imx/ele_api.h
index 477cfe73ab0..053a23f030b 100644
--- a/arch/arm/include/asm/mach-imx/ele_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -142,11 +142,11 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words,
u32 fuse_num, u32 *respon
int ele_release_caam(u32 core_did, u32 *response);
int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ele_get_events(u32 *events, u32 *events_cnt, u32 *response);
+int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32
max_output_size);
int ele_dump_buffer(u32 *buffer, u32 buffer_length);
int ele_get_info(struct ele_get_info_data *info, u32 *response);
int ele_get_fw_status(u32 *status, u32 *response);
int ele_release_m33_trout(void);
int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response);
int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);
-
#endif
diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c
index 0ca0a94f08c..8a14cf6aa92 100644
--- a/drivers/misc/imx_ele/ele_api.c
+++ b/drivers/misc/imx_ele/ele_api.c
@@ -14,6 +14,18 @@
DECLARE_GLOBAL_DATA_PTR;
+static u32 compute_crc(const struct ele_msg *msg)
+{
+ u32 crc = 0;
+ size_t i = 0;
+ u32 *data = (u32 *)msg;
+
+ for (i = 0; i < (msg->size - 1); i++)
+ crc ^= data[i];
+
+ return crc;
+}
+
int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response)
{
struct udevice *dev = gd->arch.ele_dev;
@@ -552,3 +564,35 @@ int ele_return_lifecycle_update(ulong signed_msg_blk, u32
*response)
return ret;
}
+
+int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32
max_output_size)
+{
+ struct udevice *dev = gd->arch.ele_dev;
+ int size = sizeof(struct ele_msg);
+ struct ele_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("ele dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
+ msg.size = 8;
+ msg.command = ELE_GENERATE_DEK_BLOB;
+ msg.data[0] = key_id;
+ msg.data[1] = 0x0;
+ msg.data[2] = src_paddr;
+ msg.data[3] = 0x0;
+ msg.data[4] = dst_paddr;
+ msg.data[5] = max_output_size;
+ msg.data[6] = compute_crc();
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret 0x%x, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ return ret;
+}
--
2.40.0
[PATCH V2 30/30] imx: fsl_sec: preprocessor casting issue with addresses involving math
From: Utkarsh Gupta The sec_in32 preprocessor is defined as follows in include/fsl_sec.h file: When address "a" is calculated using math for ex: addition of base address and an offset, then casting is applied only to the first address which in this example is base address. caam_ccbvid_reg = sec_in32(CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET) resolves to: caam_ccbvid_reg = in_le32((ulong *)(ulong)CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET) instead it should resolve to: caam_ccbvid_reg = in_le32((ulong *)(ulong)(CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET)) Thus add parenthesis around the address "a" so that however the address is calculated, the casting is applied to the final calculated address. Reviewed-by: Horia Geanta Reviewed-by: Ye Li Signed-off-by: Utkarsh Gupta Signed-off-by: Peng Fan --- include/fsl_sec.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/fsl_sec.h b/include/fsl_sec.h index d8861d1d0b7..9dad1d1ec47 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -13,8 +13,8 @@ #include #ifdef CONFIG_SYS_FSL_SEC_LE -#define sec_in32(a) in_le32((ulong *)(ulong)a) -#define sec_out32(a, v) out_le32((ulong *)(ulong)a, v) +#define sec_in32(a) in_le32((ulong *)(ulong)(a)) +#define sec_out32(a, v) out_le32((ulong *)(ulong)(a), v) #define sec_in16(a) in_le16(a) #define sec_clrbits32 clrbits_le32 #define sec_setbits32 setbits_le32 -- 2.40.0
[PATCH V2 29/30] imx: priblob: Update to use structure
From: Maximus Sun
Use structure to avoid define CAAM_SCFGR for each platform
Signed-off-by: Maximus Sun
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/priblob.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c
index 9b92eae7818..5b022d5c820 100644
--- a/arch/arm/mach-imx/priblob.c
+++ b/arch/arm/mach-imx/priblob.c
@@ -13,12 +13,16 @@
#include
#include
#include
-#include "../drivers/crypto/fsl_caam_internal.h"
+#include
int do_priblob_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const
argv[])
{
- writel((readl(CAAM_SCFGR) & 0xFFFC) | 3, CAAM_SCFGR);
- printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3);
+ ccsr_sec_t *sec_regs = (ccsr_sec_t *)CAAM_BASE_ADDR;
+ u32 scfgr = sec_in32(_regs->scfgr);
+
+ scfgr |= 0x3;
+ sec_out32(_regs->scfgr, scfgr);
+ printf("New priblob setting = 0x%x\n", sec_in32(_regs->scfgr) &
0x3);
return 0;
}
--
2.40.0
[PATCH V2 28/30] imx: imx8m: add CAAM_BASE_ADDR
From: Peng Fan Add CAAM_BASE_ADDR which will be used by priblob.c Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 8632eddb530..f1b7526ac77 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -40,6 +40,7 @@ #define UART1_BASE_ADDR0x3086 #define UART3_BASE_ADDR0x3088 #define UART2_BASE_ADDR0x3089 +#define CAAM_BASE_ADDR 0x3090 #define I2C1_BASE_ADDR 0x30A2 #define I2C2_BASE_ADDR 0x30A3 #define I2C3_BASE_ADDR 0x30A4 -- 2.40.0
[PATCH V2 26/30] imx: ahab: Update AHAB for iMX8 and iMX8ULP
From: Ye Li
Abstract common interfaces for AHAB authentication operations.
Then share some common codes for AHAB and SPL container authentication
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/ahab.h | 15
arch/arm/mach-imx/imx8/ahab.c| 129 +--
arch/arm/mach-imx/imx8ulp/Makefile | 1 -
arch/arm/mach-imx/parse-container.c | 81 ++---
4 files changed, 103 insertions(+), 123 deletions(-)
create mode 100644 arch/arm/include/asm/mach-imx/ahab.h
diff --git a/arch/arm/include/asm/mach-imx/ahab.h
b/arch/arm/include/asm/mach-imx/ahab.h
new file mode 100644
index 000..4222e3db278
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/ahab.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __IMX_AHAB_H__
+#define __IMX_AHAB_H__
+
+#include
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
+int ahab_auth_release(void);
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index);
+
+#endif
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 86b0e0b755f..c878743feeb 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +26,84 @@ DECLARE_GLOBAL_DATA_PTR;
#define SECO_PT 2U
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+ int err;
+
+ memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
+ ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+ err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
+ SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
+ if (err)
+ printf("Authenticate container hdr failed, return %d\n", err);
+
+ return err;
+}
+
+int ahab_auth_release(void)
+{
+ int err;
+
+ err = sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0);
+ if (err)
+ printf("Error: release container failed!\n");
+
+ return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+ sc_faddr_t start, end;
+ sc_rm_mr_t mr;
+ int err;
+ int ret = 0;
+
+ debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n",
+ image_index, img->dst, img->offset, img->size);
+
+ /* Find the memreg and set permission for seco pt */
+ err = sc_rm_find_memreg(-1, ,
+ img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
+ ALIGN(img->dst + img->size,
CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+ if (err) {
+ printf("Error: can't find memreg for image load address 0x%llx,
error %d\n",
+ img->dst, err);
+ return -ENOMEM;
+ }
+
+ err = sc_rm_get_memreg_info(-1, mr, , );
+ if (!err)
+ debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
+
+ err = sc_rm_set_memreg_permissions(-1, mr,
+ SECO_PT, SC_RM_PERM_FULL);
+ if (err) {
+ printf("Set permission failed for img %d, error %d\n",
+ image_index, err);
+ return -EPERM;
+ }
+
+ err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
+ 1 << image_index);
+ if (err) {
+ printf("Authenticate img %d failed, return %d\n",
+ image_index, err);
+ ret = -EIO;
+ }
+
+ err = sc_rm_set_memreg_permissions(-1, mr,
+ SECO_PT, SC_RM_PERM_NONE);
+ if (err) {
+ printf("Remove permission failed for img %d, error %d\n",
+ image_index, err);
+ ret = -EPERM;
+ }
+
+ return ret;
+}
+
static inline bool check_in_dram(ulong addr)
{
int i;
@@ -46,8 +125,6 @@ int authenticate_os_container(ulong addr)
struct container_hdr *phdr;
int i, ret = 0;
int err;
- sc_rm_mr_t mr;
- sc_faddr_t start, end;
u16 length;
struct boot_img_t *img;
unsigned long s, e;
@@ -76,14 +153,9 @@ int authenticate_os_container(ulong addr)
length = phdr->length_lsb + (phdr->length_msb << 8);
debug("container length %u\n", length);
- memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr,
- ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
- err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
- SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
+ err = ahab_auth_cntr_hdr(phdr, length);
if (err) {
- printf("Authenticate container hdr failed, return %d\n",
- err);
ret = -EIO;
goto exit;
}
@@ -105,50 +177,13 @@ int authenticate_os_container(ulong
[PATCH V2 27/30] imx: imx8: ahab: sha256: enable image verification using ARMv8 crypto extension
From: Gaurav Jain
add support for SHA-256 secure hash algorithm using the ARM v8
SHA-256 instructions for verifying image hash.
Signed-off-by: Gaurav Jain
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8/ahab.c | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index c878743feeb..b58b14ca9b4 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2022 NXP
*/
#include
@@ -16,6 +16,7 @@
#include
#include
#include
+#include "u-boot/sha256.h"
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE (0x6000UL)
#define SECO_PT 2U
+#define AHAB_HASH_TYPE_MASK0x0700
+#define AHAB_HASH_TYPE_SHA256 0
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
{
@@ -128,6 +131,9 @@ int authenticate_os_container(ulong addr)
u16 length;
struct boot_img_t *img;
unsigned long s, e;
+#ifdef CONFIG_ARMV8_CE_SHA256
+ u8 hash_value[SHA256_SUM_LEN];
+#endif
if (addr % 4) {
puts("Error: Image's address is not 4 byte aligned\n");
@@ -177,9 +183,23 @@ int authenticate_os_container(ulong addr)
flush_dcache_range(s, e);
- ret = ahab_verify_cntr_image(img, i);
- if (ret)
- goto exit;
+#ifdef CONFIG_ARMV8_CE_SHA256
+ if (((img->hab_flags & AHAB_HASH_TYPE_MASK) >> 8) ==
AHAB_HASH_TYPE_SHA256) {
+ sha256_csum_wd((void *)img->dst, img->size, hash_value,
CHUNKSZ_SHA256);
+ err = memcmp(>hash, _value, SHA256_SUM_LEN);
+ if (err) {
+ printf("img %d hash comparison failed, error
%d\n", i, err);
+ ret = -EIO;
+ goto exit;
+ }
+ } else {
+#endif
+ ret = ahab_verify_cntr_image(img, i);
+ if (ret)
+ goto exit;
+#ifdef CONFIG_ARMV8_CE_SHA256
+ }
+#endif
}
exit:
--
2.40.0
[PATCH V2 25/30] imx: parse-container: Use malloc for container processing
From: Nitin Garg
If the container has image which conflicts with
spl_get_load_buffer address, there are processing failures.
Use malloc instead of spl_get_load_buffer.
Reviewed-by: Ye Li
Signed-off-by: Nitin Garg
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/parse-container.c | 38 -
1 file changed, 27 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-imx/parse-container.c
b/arch/arm/mach-imx/parse-container.c
index a0d1eb3831c..c5b3abc4f29 100644
--- a/arch/arm/mach-imx/parse-container.c
+++ b/arch/arm/mach-imx/parse-container.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -134,21 +135,27 @@ static int read_auth_container(struct spl_image_info
*spl_image,
* It will not override the ATF code, so safe to use it here,
* no need malloc
*/
- container = (struct container_hdr *)spl_get_load_buffer(-size, size);
+ container = malloc(size);
+ if (!container)
+ return -ENOMEM;
debug("%s: container: %p sector: %lu sectors: %u\n", __func__,
container, sector, sectors);
- if (info->read(info, sector, sectors, container) != sectors)
- return -EIO;
+ if (info->read(info, sector, sectors, container) != sectors) {
+ ret = -EIO;
+ goto end;
+ }
if (container->tag != 0x87 && container->version != 0x0) {
- printf("Wrong container header\n");
- return -ENOENT;
+ printf("Wrong container header");
+ ret = -ENOENT;
+ goto end;
}
if (!container->num_images) {
- printf("Wrong container, no image found\n");
- return -ENOENT;
+ printf("Wrong container, no image found");
+ ret = -ENOENT;
+ goto end;
}
length = container->length_lsb + (container->length_msb << 8);
@@ -158,13 +165,18 @@ static int read_auth_container(struct spl_image_info
*spl_image,
size = roundup(length, info->bl_len);
sectors = size / info->bl_len;
- container = (struct container_hdr *)spl_get_load_buffer(-size,
size);
+ free(container);
+ container = malloc(size);
+ if (!container)
+ return -ENOMEM;
debug("%s: container: %p sector: %lu sectors: %u\n",
__func__, container, sector, sectors);
if (info->read(info, sector, sectors, container) !=
- sectors)
- return -EIO;
+ sectors) {
+ ret = -EIO;
+ goto end;
+ }
}
#ifdef CONFIG_AHAB_BOOT
@@ -175,7 +187,7 @@ static int read_auth_container(struct spl_image_info
*spl_image,
SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
if (ret) {
printf("authenticate container hdr failed, return %d\n", ret);
- return ret;
+ goto end_auth;
}
#endif
@@ -200,6 +212,10 @@ end_auth:
if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0))
printf("Error: release container failed!\n");
#endif
+
+end:
+ free(container);
+
return ret;
}
--
2.40.0
[PATCH V2 24/30] imx: imx8m: clock: not configure reserved SRC register
From: Peng Fan i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 31c34b6031f..986870799d3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -90,7 +90,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) case ANATOP_DRAM_PLL: setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); - writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); pll_base = _pll->dram_pll_gnrl_ctl; break; -- 2.40.0
[PATCH V2 23/30] imx: imx8: bootaux: Add i.MX8 M4 boot support
From: Ye Li
1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download
M4 image to any DDR address first. Then use the
"bootaux [M4 core id]" to boot CM4_0
or CM4_1, the default core id is 0 for CM4_0.
Since current M4 only supports running in TCM. The bootaux will copy
the M4 image from DDR to its TCML.
2. Implment bootaux for HIFI on QXP
command: bootaux 0x8100 1
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
arch/arm/mach-imx/Kconfig | 2 +-
arch/arm/mach-imx/Makefile| 5 +
arch/arm/mach-imx/imx8/cpu.c | 174 ++
arch/arm/mach-imx/imx_bootaux.c | 15 +-
5 files changed, 192 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 85d9ca60b14..31ae179b211 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -236,6 +236,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
u64 *phys_sdram_2_start,
u64 *phys_sdram_2_size);
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
int arch_auxiliary_core_check_up(u32 core_id);
int board_mmc_get_env_dev(int devno);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 2cca89d4bb1..d94b5828d0d 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -31,7 +31,7 @@ config IMX_RDC
config IMX_BOOTAUX
bool "Support boot auxiliary core"
- depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8 || ARCH_IMX8M
help
bootaux [addr] to boot auxiliary core.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 906f538259a..9023b99f21d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -66,6 +66,11 @@ ifeq ($(SOC),$(filter $(SOC),vf610))
obj-y += ddrmc-vf610.o
obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
endif
+ifeq ($(SOC),$(filter $(SOC),imx8))
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
+endif
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 2b34077438f..c62357044e0 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -26,6 +26,8 @@
#include
#include
#include
+#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -107,6 +109,178 @@ int arch_misc_init(void)
}
#endif
+#ifdef CONFIG_IMX_BOOTAUX
+
+#ifdef CONFIG_IMX8QM
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+ sc_rsrc_t core_rsrc, mu_rsrc;
+ sc_faddr_t tcml_addr;
+ u32 tcml_size = SZ_128K;
+ ulong addr;
+
+ switch (core_id) {
+ case 0:
+ core_rsrc = SC_R_M4_0_PID0;
+ tcml_addr = 0x34FE;
+ mu_rsrc = SC_R_M4_0_MU_1A;
+ break;
+ case 1:
+ core_rsrc = SC_R_M4_1_PID0;
+ tcml_addr = 0x38FE;
+ mu_rsrc = SC_R_M4_1_MU_1A;
+ break;
+ default:
+ printf("Not support this core boot up, ID:%u\n", core_id);
+ return -EINVAL;
+ }
+
+ addr = (sc_faddr_t)boot_private_data;
+
+ if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) {
+ printf("Wrong image address 0x%lx, should not in TCML\n",
+ addr);
+ return -EINVAL;
+ }
+
+ printf("Power on M4 and MU\n");
+
+ if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) !=
SC_ERR_NONE)
+ return -EIO;
+
+ if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) !=
SC_ERR_NONE)
+ return -EIO;
+
+ printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr,
(ulong)tcml_addr);
+
+ if (addr != tcml_addr)
+ memcpy((void *)tcml_addr, (void *)addr, tcml_size);
+
+ printf("Start M4 %u\n", core_id);
+ if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
+ return -EIO;
+
+ printf("bootaux complete\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_IMX8QXP
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+ sc_rsrc_t core_rsrc, mu_rsrc = SC_R_NONE;
+ sc_faddr_t aux_core_ram;
+ u32 size;
+ ulong addr;
+
+ switch (core_id) {
+ case 0:
+ core_rsrc = SC_R_M4_0_PID0;
+ aux_core_ram = 0x34FE;
+ mu_rsrc = SC_R_M4_0_MU_1A;
+ size = SZ_128K;
+ break;
+ case 1:
+ core_rsrc = SC_R_DSP;
+ aux_core_ram =
[PATCH V2 22/30] imx: bootaux: Fix bootaux issue when running on ARM64
From: Ye Li
The bootaux uses ulong to read private data and write to M4 TCM,
this cause problem on ARM64 platform where the ulong is 8bytes.
Fix it by using u32 to replace ulong.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx_bootaux.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 2b97aae3a23..ab7a41fd11d 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -45,7 +45,7 @@ static const struct rproc_att *get_host_mapping(unsigned long
auxcore)
* is valid, returns the entry point address.
* Translates load addresses in the elf file to the U-Boot address space.
*/
-static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong
*stack)
+static u32 load_elf_image_m_core_phdr(unsigned long addr, u32 *stack)
{
Elf32_Ehdr *ehdr; /* ELF header structure pointer */
Elf32_Phdr *phdr; /* Program header structure pointer */
@@ -95,7 +95,7 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long
addr, ulong *stack
int arch_auxiliary_core_up(u32 core_id, ulong addr)
{
- ulong stack, pc;
+ u32 stack, pc;
if (!addr)
return -EINVAL;
@@ -121,7 +121,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
pc = *(u32 *)(addr + 4);
}
- printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
+ printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n",
stack, pc);
/* Set the stack and pc to MCU bootROM */
--
2.40.0
[PATCH V2 21/30] imx: bootaux: change names of MACROs used to boot MCU on iMX devices
From: Peng Fan
The current bootaux supports i.MX8M and i.MX93, but the name "_M4_"
implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4,
i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place
of "_M4_" to simplify the naming.
Signed-off-by: faqiang.zhu
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 +-
arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
arch/arm/include/asm/arch-mx7/imx-regs.h | 2 +-
arch/arm/mach-imx/imx9/imx_bootaux.c | 6 +++---
arch/arm/mach-imx/imx_bootaux.c| 24 +++---
board/kontron/sl-mx8mm/sl-mx8mm.c | 2 +-
board/kontron/sl-mx8mm/spl.c | 2 +-
board/technexion/pico-imx8mq/pico-imx8mq.c | 2 +-
board/technexion/pico-imx8mq/spl.c | 2 +-
include/imx_sip.h | 6 +++---
10 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 6e2fc82a0e4..8632eddb530 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -13,7 +13,7 @@
#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
-#define M4_BOOTROM_BASE_ADDR 0x007E
+#define MCU_BOOTROM_BASE_ADDR 0x007E
#define GPIO1_BASE_ADDR0X3020
#define GPIO2_BASE_ADDR0x3021
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 72944af18a4..8fd3dd2df3a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -23,7 +23,7 @@
#define GPU_ARB_END_ADDR0x01803FFF
#define APBH_DMA_ARB_BASE_ADDR 0x01804000
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
-#define M4_BOOTROM_BASE_ADDR 0x007F8000
+#define MCU_BOOTROM_BASE_ADDR 0x007F8000
#elif !defined(CONFIG_MX6SLL)
#define CAAM_ARB_BASE_ADDR 0x0010
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h
b/arch/arm/include/asm/arch-mx7/imx-regs.h
index c863cd9da36..6f5ae5173c0 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -18,7 +18,7 @@
#define GIC400_ARB_END_ADDR 0x31007FFF
#define APBH_DMA_ARB_BASE_ADDR 0x3300
#define APBH_DMA_ARB_END_ADDR 0x33007FFF
-#define M4_BOOTROM_BASE_ADDR0x0018
+#define MCU_BOOTROM_BASE_ADDR0x0018
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c
b/arch/arm/mach-imx/imx9/imx_bootaux.c
index 256e6fa1c54..6afb59e0515 100644
--- a/arch/arm/mach-imx/imx9/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -13,7 +13,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
{
struct arm_smccc_res res;
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0,
0, 0, 0, 0, );
return res.a0;
@@ -25,7 +25,7 @@ int arch_auxiliary_core_down(u32 core_id)
printf("## Stopping auxiliary core\n");
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0,
0, 0, 0, 0, );
return 0;
@@ -40,7 +40,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0,
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, addr, 0,
0, 0, 0, 0, );
return 0;
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 888c53d6901..2b97aae3a23 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -124,15 +124,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
stack, pc);
- /* Set the stack and pc to M4 bootROM */
- writel(stack, M4_BOOTROM_BASE_ADDR);
- writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+ /* Set the stack and pc to MCU bootROM */
+ writel(stack, MCU_BOOTROM_BASE_ADDR);
+ writel(pc, MCU_BOOTROM_BASE_ADDR + 4);
flush_dcache_all();
- /* Enable M4 */
+ /* Enable MCU */
if (IS_ENABLED(CONFIG_IMX8M)) {
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0,
0, NULL);
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, 0, 0,
0, 0, NULL);
} else {
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
[PATCH V2 20/30] imx: iamge-container: support secondary container
From: Peng Fan
Add the support for loading image from secondary container set on
iMX8QM B0, iMX8QXP C0.
Using the SCFW API to get container set index, if it is the secondary
boot, get the offset from fuse and apply to offset of current container
set beginning for loading.
Also override the emmc boot partition to check secondary boot and switch
to the other boot part.
This patch is modified from NXP downstream:
imx8: Fix the fuse used by secondary container offset
imx: container: Skip container set check for ROM API
imx8: spl: Support booting from secondary container set
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/image-container.c | 94 ++---
1 file changed, 87 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-imx/image-container.c
b/arch/arm/mach-imx/image-container.c
index 745de130630..5f188ab32d1 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -22,6 +22,25 @@
#define QSPI_NOR_DEV 3
#define ROM_API_DEV4
+/* The unit of second image offset number which provision by the fuse bits */
+#define SND_IMG_OFF_UNIT(0x10UL)
+
+/*
+ * If num = 0, off = (2 ^ 2) * 1MB
+ * else If num = 2, off = (2 ^ 0) * 1MB
+ * else off = (2 ^ num) * 1MB
+ */
+#define SND_IMG_NUM_TO_OFF(num) \
+ ((1UL << ((0 == (num)) ? 2 : (2 == (num)) ? 0 : (num))) *
SND_IMG_OFF_UNIT)
+
+#define GET_SND_IMG_NUM(fuse) (((fuse) >> 24) & 0x1F)
+
+#if defined(CONFIG_IMX8QM)
+#define FUSE_IMG_SET_OFF_WORD 464
+#elif defined(CONFIG_IMX8QXP)
+#define FUSE_IMG_SET_OFF_WORD 720
+#endif
+
int get_container_size(ulong addr, u16 *header_length)
{
struct container_hdr *phdr;
@@ -136,15 +155,53 @@ static int get_dev_container_size(void *dev, int
dev_type, unsigned long offset,
return ret;
}
+static bool check_secondary_cnt_set(unsigned long *set_off)
+{
+#if IS_ENABLED(CONFIG_ARCH_IMX8)
+ int ret;
+ u8 set_id = 1;
+ u32 fuse_val = 0;
+
+ if (!(is_imx8qxp() && is_soc_rev(CHIP_REV_B))) {
+ ret = sc_misc_get_boot_container(-1, _id);
+ if (ret)
+ return false;
+ /* Secondary boot */
+ if (set_id == 2) {
+ ret = sc_misc_otp_fuse_read(-1, FUSE_IMG_SET_OFF_WORD,
_val);
+ if (!ret) {
+ if (set_off)
+ *set_off =
SND_IMG_NUM_TO_OFF(GET_SND_IMG_NUM(fuse_val));
+ return true;
+ }
+ }
+ }
+#endif
+
+ return false;
+}
+
static unsigned long get_boot_device_offset(void *dev, int dev_type)
{
- unsigned long offset = 0;
+ unsigned long offset = 0, sec_set_off = 0;
+ bool sec_boot = false;
+
+ if (dev_type == ROM_API_DEV) {
+ offset = (unsigned long)dev;
+ return offset;
+ }
+
+ sec_boot = check_secondary_cnt_set(_set_off);
+ if (sec_boot)
+ printf("Secondary set selected\n");
+ else
+ printf("Primary set selected\n");
if (dev_type == MMC_DEV) {
struct mmc *mmc = (struct mmc *)dev;
if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
- offset = CONTAINER_HDR_MMCSD_OFFSET;
+ offset = sec_boot ? sec_set_off :
CONTAINER_HDR_MMCSD_OFFSET;
} else {
u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
@@ -154,19 +211,23 @@ static unsigned long get_boot_device_offset(void *dev,
int dev_type)
else
offset = CONTAINER_HDR_EMMC_OFFSET;
} else {
- offset = CONTAINER_HDR_MMCSD_OFFSET;
+ offset = sec_boot ? sec_set_off :
CONTAINER_HDR_MMCSD_OFFSET;
}
}
} else if (dev_type == QSPI_DEV) {
- offset = CONTAINER_HDR_QSPI_OFFSET;
+ offset = sec_boot ? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) :
+ CONTAINER_HDR_QSPI_OFFSET;
} else if (dev_type == NAND_DEV) {
- offset = CONTAINER_HDR_NAND_OFFSET;
+ offset = sec_boot ? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) :
+ CONTAINER_HDR_NAND_OFFSET;
} else if (dev_type == QSPI_NOR_DEV) {
offset = CONTAINER_HDR_QSPI_OFFSET + 0x0800;
- } else if (dev_type == ROM_API_DEV) {
- offset = (unsigned long)dev;
+ } else {
+ printf("Not supported dev_type: %d\n", dev_type);
}
+ debug("container set offset 0x%lx\n", offset);
+
return offset;
}
@@ -227,6 +288,25 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
return end / mmc->read_bl_len;
}
+
+int
[PATCH V2 19/30] imx: image-container: Fix container header checking
From: Ye Li
Checking container header tag and version is wrong, it causes to fail
to bypass invalid container
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/image-container.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/image-container.c
b/arch/arm/mach-imx/image-container.c
index 5b059a64292..745de130630 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -31,7 +31,7 @@ int get_container_size(ulong addr, u16 *header_length)
u32 max_offset = 0, img_end;
phdr = (struct container_hdr *)addr;
- if (phdr->tag != 0x87 && phdr->version != 0x0) {
+ if (phdr->tag != 0x87 || phdr->version != 0x0) {
debug("Wrong container header\n");
return -EFAULT;
}
--
2.40.0
[PATCH V2 18/30] imx: hab: Fix coverity issue in HAB event decoding
From: Ye Li
Fix below coverity issues caused by get_idx function where "-1" is
compared with uint8_t "element"
343336 Unsigned compared with neg
343337 Operands don't affect result
Additional, this function returns "-1" will cause overflow to
event string array.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/hab.c | 41 ++---
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index c6747b257c4..de8fcc7c27d 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -289,9 +289,10 @@ static char *rsn_str[] = {
};
static char *sts_str[] = {
- "STS = HAB_SUCCESS (0xF0)\n",
+ "STS = HAB_STS_ANY (0x00)\n",
"STS = HAB_FAILURE (0x33)\n",
"STS = HAB_WARNING (0x69)\n",
+ "STS = HAB_SUCCESS (0xF0)\n",
"STS = INVALID\n",
NULL
};
@@ -336,8 +337,7 @@ static uint8_t hab_statuses[5] = {
HAB_STS_ANY,
HAB_FAILURE,
HAB_WARNING,
- HAB_SUCCESS,
- -1
+ HAB_SUCCESS
};
static uint8_t hab_reasons[26] = {
@@ -365,8 +365,7 @@ static uint8_t hab_reasons[26] = {
HAB_UNS_ITEM,
HAB_UNS_KEY,
HAB_UNS_PROTOCOL,
- HAB_UNS_STATE,
- -1
+ HAB_UNS_STATE
};
static uint8_t hab_contexts[12] = {
@@ -380,8 +379,7 @@ static uint8_t hab_contexts[12] = {
HAB_CTX_COMMAND,
HAB_CTX_AUT_DAT,
HAB_CTX_ASSERT,
- HAB_CTX_EXIT,
- -1
+ HAB_CTX_EXIT
};
static uint8_t hab_engines[16] = {
@@ -399,30 +397,35 @@ static uint8_t hab_engines[16] = {
HAB_ENG_ROM,
HAB_ENG_HDCP,
HAB_ENG_RTL,
- HAB_ENG_SW,
- -1
+ HAB_ENG_SW
};
-static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
+static inline u32 get_idx(u8 *list, u8 tgt, u32 size)
{
- uint8_t idx = 0;
- uint8_t element = list[idx];
- while (element != -1) {
+ u32 idx = 0;
+ u8 element;
+
+ while (idx < size) {
+ element = list[idx];
if (element == tgt)
return idx;
- element = list[++idx];
+ ++idx;
}
- return -1;
+ return idx;
}
static void process_event_record(uint8_t *event_data, size_t bytes)
{
struct record *rec = (struct record *)event_data;
- printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
- printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
- printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
- printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
+ printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0],
+ ARRAY_SIZE(hab_statuses))]);
+ printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1],
+ ARRAY_SIZE(hab_reasons))]);
+ printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2],
+ ARRAY_SIZE(hab_contexts))]);
+ printf("%s", eng_str[get_idx(hab_engines, rec->contents[3],
+ ARRAY_SIZE(hab_engines))]);
}
static void display_event(uint8_t *event_data, size_t bytes)
--
2.40.0
[PATCH V2 17/30] imx: imx8ulp: start the ELE RNG at boot
From: Peng Fan
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started.
Signed-off-by: Clement Faure
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/ele_api.h | 1 +
board/freescale/imx8ulp_evk/spl.c | 10 ++
drivers/misc/imx_ele/ele_api.c | 25 +
3 files changed, 36 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/ele_api.h
b/arch/arm/include/asm/mach-imx/ele_api.h
index 053a23f030b..cfd4ecebb62 100644
--- a/arch/arm/include/asm/mach-imx/ele_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -149,4 +149,5 @@ int ele_get_fw_status(u32 *status, u32 *response);
int ele_release_m33_trout(void);
int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response);
int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);
+int ele_start_rng(void);
#endif
diff --git a/board/freescale/imx8ulp_evk/spl.c
b/board/freescale/imx8ulp_evk/spl.c
index b7c6ff092b1..66d0f68cc62 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -123,6 +123,16 @@ void spl_board_init(void)
ret = ele_release_caam(0x7, );
if (ret)
printf("ele release caam failed %d, 0x%x\n", ret, res);
+
+ /*
+* RNG start only available on the A1 soc revision.
+* Check some JTAG register for the SoC revision.
+*/
+ if (!is_soc_rev(CHIP_REV_1_0)) {
+ ret = ele_start_rng();
+ if (ret)
+ printf("Fail to start RNG: %d\n", ret);
+ }
}
void board_init_f(ulong dummy)
diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c
index 8a14cf6aa92..0c017734a49 100644
--- a/drivers/misc/imx_ele/ele_api.c
+++ b/drivers/misc/imx_ele/ele_api.c
@@ -503,6 +503,31 @@ int ele_get_events(u32 *events, u32 *events_cnt, u32
*response)
return ret;
}
+int ele_start_rng(void)
+{
+ struct udevice *dev = gd->arch.ele_dev;
+ int size = sizeof(struct ele_msg);
+ struct ele_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("ele dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
+ msg.size = 1;
+ msg.command = ELE_START_RNG;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ return ret;
+}
+
int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response)
{
struct udevice *dev = gd->arch.ele_dev;
--
2.40.0
[PATCH V2 16/30] imx: misc: ele_mu: Update ELE MU driver
From: Ye Li
Extend the RX timeout value to 10s, because when authentication is failed
the ELE needs long time (>2s for 28M image) to return the result. Print
rx wait info per 1s.
Also correct TX and RX status registers in debug.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/misc/imx_ele/ele_mu.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c
index 956f8a1eb2f..053cdcf0fe0 100644
--- a/drivers/misc/imx_ele/ele_mu.c
+++ b/drivers/misc/imx_ele/ele_mu.c
@@ -42,7 +42,7 @@ int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
assert(reg_index < MU_TR_COUNT);
- debug("sendmsg sr 0x%x\n", readl(_base->sr));
+ debug("sendmsg tsr 0x%x\n", readl(_base->tsr));
/* Wait TX register to be empty. */
ret = readl_poll_timeout(_base->tsr, val, val & mask, 1);
@@ -64,14 +64,24 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
u32 mask = MU_SR_RF0_MASK << reg_index;
u32 val;
int ret;
+ u32 count = 10;
assert(reg_index < MU_RR_COUNT);
- debug("receivemsg sr 0x%x\n", readl(_base->sr));
+ debug("receivemsg rsr 0x%x\n", readl(_base->rsr));
- /* Wait RX register to be full. */
- ret = readl_poll_timeout(_base->rsr, val, val & mask, 1);
- if (ret < 0) {
+ do {
+ /* Wait RX register to be full. */
+ ret = readl_poll_timeout(_base->rsr, val, val & mask,
100);
+ if (ret < 0) {
+ count--;
+ printf("mu receive msg wait %us\n", 10 - count);
+ } else {
+ break;
+ }
+ } while (count > 0);
+
+ if (count == 0) {
debug("%s timeout\n", __func__);
return -ETIMEDOUT;
}
--
2.40.0
[PATCH V2 14/30] imx: cmd_dek: add ELE DEK Blob generation support
From: Clement Faure
Add ELE DEK Blob generation for the cmd_dek command.
Signed-off-by: Clement Faure
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/Kconfig | 7
arch/arm/mach-imx/cmd_dek.c | 84 +
2 files changed, 91 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3266545c266..2cca89d4bb1 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -86,6 +86,7 @@ config CMD_DEKBLOB
select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP
select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M
select IMX_SECO_DEK_ENCAP if ARCH_IMX8
+ select IMX_ELE_DEK_ENCAP if ARCH_IMX8ULP || ARCH_IMX9
help
This enables the 'dek_blob' command which is used with the
Freescale secure boot mechanism. This command encapsulates and
@@ -113,6 +114,12 @@ config IMX_SECO_DEK_ENCAP
This enabled the DEK blob encapsulation with the SECO API. This option
is only available on imx8.
+config IMX_ELE_DEK_ENCAP
+ bool "Support the DEK blob encapsulation with ELE"
+ help
+ This enabled the DEK blob encapsulation with the ELE API. This option
+ is only available on imx8ulp and imx9.
+
config CMD_PRIBLOB
bool "Support the set_priblob_bitfield command"
depends on HAS_CAAM && IMX_HAB
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 0be9df521a5..6fa5b41fcd3 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2015 Freescale Semiconductor, Inc.
+ * Copyright 2022 NXP
*
* Command for encapsulating DEK blob
*/
@@ -20,6 +21,11 @@
#include
#include
#endif
+#ifdef CONFIG_IMX_ELE_DEK_ENCAP
+#include
+#include
+#endif
+
#include
/**
@@ -284,6 +290,84 @@ error:
}
#endif /* CONFIG_IMX_SECO_DEK_ENCAP */
+#ifdef CONFIG_IMX_ELE_DEK_ENCAP
+
+#define DEK_BLOB_HDR_SIZE 8
+#define AHAB_PRIVATE_KEY 0x81
+#define AHAB_DEK_BLOB 0x01
+#define AHAB_ALG_AES0x03
+#define AHAB_128_AES_KEY 0x10
+#define AHAB_192_AES_KEY 0x18
+#define AHAB_256_AES_KEY 0x20
+
+static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
+{
+ u8 in_size, out_size;
+ u8 *src_ptr, *dst_ptr;
+ struct generate_key_blob_hdr hdr;
+
+ /* Set sizes */
+ in_size = sizeof(struct generate_key_blob_hdr) + len / 8;
+ out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE;
+
+ /* Get src and dst virtual addresses */
+ src_ptr = map_sysmem(src_addr, in_size);
+ dst_ptr = map_sysmem(dst_addr, out_size);
+
+ /* Check addr input */
+ if (!(src_ptr && dst_ptr)) {
+ debug("src_addr or dst_addr invalid\n");
+ return -1;
+ }
+
+ /* Build key header */
+ hdr.version = 0x0;
+ hdr.length_lsb = in_size;
+ hdr.length_msb = 0x00;
+ hdr.tag = AHAB_PRIVATE_KEY;
+ hdr.flags = AHAB_DEK_BLOB;
+ hdr.algorithm = AHAB_ALG_AES;
+ hdr.mode = 0x0; /* Not used by the ELE */
+
+ switch (len) {
+ case 128:
+ hdr.size = AHAB_128_AES_KEY;
+ break;
+ case 192:
+ hdr.size = AHAB_192_AES_KEY;
+ break;
+ case 256:
+ hdr.size = AHAB_256_AES_KEY;
+ break;
+ default:
+ /* Not supported */
+ debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
+ return -1;
+ }
+
+ /* Move input key and append blob header */
+ memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)),
+ (void *)src_ptr, len / 8);
+ memcpy((void *)src_ptr, (void *),
+ sizeof(struct generate_key_blob_hdr));
+
+ /* Flush the cache */
+ flush_dcache_range(src_addr, src_addr + in_size);
+ flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
+ roundup(out_size, ARCH_DMA_MINALIGN)));
+
+ /* Call ELE */
+ if (ele_generate_dek_blob(0x00, src_addr, dst_addr, out_size))
+ return -1;
+
+ /* Invalidate output buffer */
+ invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
+ roundup(out_size, ARCH_DMA_MINALIGN)));
+
+ return 0;
+}
+#endif /* CONFIG_IMX_ELE_DEK_ENCAP */
+
/**
* do_dek_blob() - Handle the "dek_blob" command-line command
* @cmdtp: Command data struct pointer
--
2.40.0
[PATCH V2 15/30] imx: misc: ele_mu: Update MU TR registers count
From: Ye Li
According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All
of them are used for ELE message. So update TR count to 8 and fix a
typo in receive msg
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/misc/imx_ele/ele_mu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c
index 0d34b8c9010..956f8a1eb2f 100644
--- a/drivers/misc/imx_ele/ele_mu.c
+++ b/drivers/misc/imx_ele/ele_mu.c
@@ -22,7 +22,7 @@ struct imx8ulp_mu {
#define MU_SR_TE0_MASK BIT(0)
#define MU_SR_RF0_MASK BIT(0)
-#define MU_TR_COUNT4
+#define MU_TR_COUNT8
#define MU_RR_COUNT4
void mu_hal_init(ulong base)
@@ -65,7 +65,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
u32 val;
int ret;
- assert(reg_index < MU_TR_COUNT);
+ assert(reg_index < MU_RR_COUNT);
debug("receivemsg sr 0x%x\n", readl(_base->sr));
--
2.40.0
[PATCH V2 13/30] imx: cmd_dek: Fix Uninitialized pointer read
From: Ye Li
Fix Coverity (CID 21143558).
When tee_shm_register returns failure, the shm_input pointer is
invalid, should not free it. Same issue also exists on registering
shm_output.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/cmd_dek.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index d77a49df860..0be9df521a5 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -101,6 +101,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32
len)
0x0, _output);
if (ret < 0) {
printf("Cannot register output shared memory 0x%X\n", ret);
+ tee_shm_free(shm_input);
goto error;
}
@@ -122,11 +123,11 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32
len)
if (ret < 0)
printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret);
-error:
/* Free shared memory */
tee_shm_free(shm_input);
tee_shm_free(shm_output);
+error:
/* Close session */
ret = tee_close_session(dev, arg.session);
if (ret < 0)
--
2.40.0
[PATCH V2 08/30] imx: use generic name ele(EdgeLockSecure Enclave)
From: Peng Fan
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.
Signed-off-by: Peng Fan
---
arch/arm/Kconfig | 4 +-
arch/arm/include/asm/arch-imx9/ccm_regs.h | 2 +-
arch/arm/include/asm/global_data.h| 4 +-
.../asm/mach-imx/{s400_api.h => ele_api.h}| 48 +++--
arch/arm/mach-imx/ele_ahab.c | 15 +-
arch/arm/mach-imx/imx8ulp/rdc.c | 18 +-
arch/arm/mach-imx/imx8ulp/soc.c | 16 +-
arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 6 +-
arch/arm/mach-imx/imx9/clock.c| 8 +-
arch/arm/mach-imx/imx9/clock_root.c | 2 +-
arch/arm/mach-imx/imx9/soc.c | 16 +-
arch/arm/mach-imx/imx9/trdc.c | 14 +-
board/freescale/imx8ulp_evk/spl.c | 10 +-
board/freescale/imx93_evk/spl.c | 1 -
drivers/misc/Kconfig | 4 +-
drivers/misc/Makefile | 2 +-
drivers/misc/{sentinel => imx_ele}/Makefile | 2 +-
.../s400_api.c => imx_ele/ele_api.c} | 200 +-
.../{sentinel/s4mu.c => imx_ele/ele_mu.c} | 14 +-
drivers/misc/{sentinel => imx_ele}/fuse.c | 40 ++--
20 files changed, 213 insertions(+), 213 deletions(-)
rename arch/arm/include/asm/mach-imx/{s400_api.h => ele_api.h} (78%)
rename drivers/misc/{sentinel => imx_ele}/Makefile (71%)
rename drivers/misc/{sentinel/s400_api.c => imx_ele/ele_api.c} (63%)
rename drivers/misc/{sentinel/s4mu.c => imx_ele/ele_mu.c} (93%)
rename drivers/misc/{sentinel => imx_ele}/fuse.c (84%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 99264a64780..913bc0ae45a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -882,7 +882,7 @@ config ARCH_IMX8ULP
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
select MISC
- select IMX_SENTINEL
+ select IMX_ELE
imply CMD_DM
config ARCH_IMX9
@@ -894,7 +894,7 @@ config ARCH_IMX9
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
select MISC
- select IMX_SENTINEL
+ select IMX_ELE
imply CMD_DM
config ARCH_IMXRT
diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h
b/arch/arm/include/asm/arch-imx9/ccm_regs.h
index d326a6ea516..f6ec8fda3e6 100644
--- a/arch/arm/include/asm/arch-imx9/ccm_regs.h
+++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h
@@ -12,7 +12,7 @@
#define ARM_A55_MTR_BUS_CLK_ROOT 1
#define ARM_A55_CLK_ROOT 2
#define M33_CLK_ROOT 3
-#define SENTINEL_CLK_ROOT 4
+#define ELE_CLK_ROOT 4
#define BUS_WAKEUP_CLK_ROOT5
#define BUS_AON_CLK_ROOT 6
#define WAKEUP_AXI_CLK_ROOT7
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 0c130757110..2a222c53882 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -92,8 +92,8 @@ struct arch_global_data {
struct udevice *scu_dev;
#endif
-#ifdef CONFIG_IMX_SENTINEL
- struct udevice *s400_dev;
+#ifdef CONFIG_IMX_ELE
+ struct udevice *ele_dev;
u32 soc_rev;
u32 lifecycle;
u32 uid[4];
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/ele_api.h
similarity index 78%
rename from arch/arm/include/asm/mach-imx/s400_api.h
rename to arch/arm/include/asm/mach-imx/ele_api.h
index 5582ff1a254..120da0854e4 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -3,12 +3,12 @@
* Copyright 2021 NXP
*/
-#ifndef __S400_API_H__
-#define __S400_API_H__
+#ifndef __ELE_API_H__
+#define __ELE_API_H__
-#define AHAB_VERSION0x6
-#define AHAB_CMD_TAG0x17
-#define AHAB_RESP_TAG 0xe1
+#define ELE_VERSION0x6
+#define ELE_CMD_TAG0x17
+#define ELE_RESP_TAG 0xe1
/* ELE commands */
#define ELE_PING_REQ (0x01)
@@ -24,6 +24,8 @@
#define ELE_GET_FW_VERSION_REQ (0x9D)
#define ELE_RET_LIFECYCLE_UP_REQ (0xA0)
#define ELE_GET_EVENTS_REQ (0xA2)
+#define ELE_START_RNG (0xA3)
+#define ELE_GENERATE_DEK_BLOB (0xAF)
#define ELE_ENABLE_PATCH_REQ (0xC3)
#define ELE_RELEASE_RDC_REQ (0xC4)
#define ELE_GET_FW_STATUS_REQ (0xC5)
@@ -109,17 +111,17 @@
#define ELE_SUCCESS_IND (0xD6)
#define ELE_FAILURE_IND (0x29)
-#define S400_MAX_MSG 255U
+#define ELE_MAX_MSG 255U
-struct sentinel_msg {
+struct ele_msg {
u8 version;
u8 size;
u8 command;
u8 tag;
- u32 data[(S400_MAX_MSG - 1U)];
+ u32 data[(ELE_MAX_MSG - 1U)];
};
-struct sentinel_get_info_data {
+struct ele_get_info_data {
u32 hdr;
u32 soc;
u32 lc;
@@ -130,19 +132,19 @@ struct sentinel_get_info_data {
u32 state;
};
-int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
-int ahab_auth_oem_ctnr(ulong ctnr_addr, u32
[PATCH V2 11/30] imx: ele_api: support program secure fuse and return lifecycle
From: Peng Fan
Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse
Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/ele_api.h | 2 +
arch/arm/mach-imx/ele_ahab.c| 74 +
drivers/misc/imx_ele/ele_api.c | 64 -
3 files changed, 139 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-imx/ele_api.h
b/arch/arm/include/asm/mach-imx/ele_api.h
index 120da0854e4..477cfe73ab0 100644
--- a/arch/arm/include/asm/mach-imx/ele_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -146,5 +146,7 @@ int ele_dump_buffer(u32 *buffer, u32 buffer_length);
int ele_get_info(struct ele_get_info_data *info, u32 *response);
int ele_get_fw_status(u32 *status, u32 *response);
int ele_release_m33_trout(void);
+int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response);
+int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);
#endif
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 5f23486304c..785b0d6ec3c 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -563,6 +563,68 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag,
int argc, char *const
return 0;
}
+static int do_sec_fuse_prog(struct cmd_tbl *cmdtp, int flag, int argc, char
*const argv[])
+{
+ ulong addr;
+ u32 header, response;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ addr = hextoul(argv[1], NULL);
+ header = *(u32 *)addr;
+
+ if ((header & 0xffff) != 0x8900) {
+ printf("Wrong Signed message block format, header 0x%x\n",
header);
+ return CMD_RET_FAILURE;
+ }
+
+ header = (header & 0x00) >> 8;
+
+ printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header);
+ flush_dcache_range(addr, addr + header - 1);
+
+ if (ele_write_secure_fuse(addr, )) {
+ printf("Program secure fuse failed, response 0x%x\n", response);
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Program secure fuse completed, response 0x%x\n", response);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_ahab_return_lifecycle(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
+{
+ ulong addr;
+ u32 header, response;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ addr = hextoul(argv[1], NULL);
+ header = *(u32 *)addr;
+
+ if ((header & 0xffff) != 0x8900) {
+ printf("Wrong Signed message block format, header 0x%x\n",
header);
+ return CMD_RET_FAILURE;
+ }
+
+ header = (header & 0x00) >> 8;
+
+ printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header);
+ flush_dcache_range(addr, addr + header - 1);
+
+ if (ele_return_lifecycle_update(addr, )) {
+ printf("Return lifecycle failed, response 0x%x\n", response);
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Return lifecycle completed, response 0x%x\n", response);
+
+ return CMD_RET_SUCCESS;
+}
+
U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
"autenticate OS container via AHAB",
"addr\n"
@@ -583,3 +645,15 @@ U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1,
do_ahab_status,
"display AHAB lifecycle only",
""
);
+
+U_BOOT_CMD(ahab_sec_fuse_prog, CONFIG_SYS_MAXARGS, 1, do_sec_fuse_prog,
+ "Program secure fuse via signed message block",
+ "addr\n"
+ "addr - Signed message block for secure fuse\n"
+);
+
+U_BOOT_CMD(ahab_return_lifecycle, CONFIG_SYS_MAXARGS, 1,
do_ahab_return_lifecycle,
+ "Return lifecycle to OEM field return via signed message block",
+ "addr\n"
+ "addr - Return lifecycle message block signed by OEM SRK\n"
+);
diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c
index 56605714f44..0ca0a94f08c 100644
--- a/drivers/misc/imx_ele/ele_api.c
+++ b/drivers/misc/imx_ele/ele_api.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2020 NXP
+ * Copyright 2020, 2023 NXP
*
*/
@@ -490,3 +490,65 @@ int ele_get_events(u32 *events, u32 *events_cnt, u32
*response)
return ret;
}
+
+int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response)
+{
+ struct udevice *dev = gd->arch.ele_dev;
+ int size = sizeof(struct ele_msg);
+ struct ele_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("ele dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
+ msg.size = 3;
+ msg.command = ELE_WRITE_SECURE_FUSE_REQ;
+
+ msg.data[0] = upper_32_bits(signed_msg_blk);
+ msg.data[1] = lower_32_bits(signed_msg_blk);
+
+ ret = misc_call(dev, false, , size, ,
[PATCH V2 10/30] imx: ele_ahab: use hextoul
From: Peng Fan
Use hextoul which looks a bit simpler.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/ele_ahab.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 9bb37919638..5f23486304c 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -402,7 +402,7 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag,
int argc,
if (argc < 2)
return CMD_RET_USAGE;
- addr = simple_strtoul(argv[1], NULL, 16);
+ addr = hextoul(argv[1], NULL);
printf("Authenticate OS container at 0x%lx\n", addr);
--
2.40.0
[PATCH V2 09/30] imx: parse-container: fix build warning
From: Peng Fan
Fix build warning:
warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 3
has type ‘u64’ {aka ‘long long unsigned int’} [-Wformat=]
printf("can't find memreg for image %d load address 0x%x, error %d\n",
warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but
argument 3 has type ‘sc_faddr_t’ {aka ‘long long unsigned int’} [-Wformat=]
debug("memreg %u 0x%lx -- 0x%lx\n", mr, start, end);
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/parse-container.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/parse-container.c
b/arch/arm/mach-imx/parse-container.c
index f7582825d6d..a0d1eb3831c 100644
--- a/arch/arm/mach-imx/parse-container.c
+++ b/arch/arm/mach-imx/parse-container.c
@@ -35,14 +35,14 @@ static int authenticate_image(struct boot_img_t *img, int
image_index)
ALIGN(img->dst + img->size,
CONFIG_SYS_CACHELINE_SIZE) - 1);
if (err) {
- printf("can't find memreg for image %d load address 0x%x, error
%d\n",
+ printf("can't find memreg for image %d load address 0x%llx,
error %d\n",
image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE -
1), err);
return -ENOMEM;
}
err = sc_rm_get_memreg_info(-1, mr, , );
if (!err)
- debug("memreg %u 0x%x -- 0x%x\n", mr, start, end);
+ debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
err = sc_rm_set_memreg_permissions(-1, mr,
SECO_PT, SC_RM_PERM_FULL);
--
2.40.0
[PATCH V2 07/30] imx: scu_api: update to version 1.16 and add more APIs
From: Peng Fan
Upgrade SCFW API to 1.16
Add more APIs:
sc_misc_get_button_status
sc_pm_reboot
sc_seco_v2x_build_info
Signed-off-by: Peng Fan
---
drivers/misc/imx8/scu_api.c | 78
include/firmware/imx/sci/rpc.h | 27 ---
include/firmware/imx/sci/sci.h | 24 ++
include/firmware/imx/sci/svc/misc/api.h | 42 ---
include/firmware/imx/sci/svc/pm/api.h| 94
include/firmware/imx/sci/svc/rm/api.h| 14 ++--
include/firmware/imx/sci/svc/seco/api.h | 5 +-
include/firmware/imx/sci/svc/timer/api.h | 33 +
8 files changed, 287 insertions(+), 30 deletions(-)
create mode 100644 include/firmware/imx/sci/svc/timer/api.h
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index dfede7f1d5f..3e3002ba6df 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -481,6 +481,22 @@ int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
sc_misc_temp_t temp,
return 0;
}
+void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
+{
+ struct sc_rpc_msg_s msg;
+ struct udevice *dev = gd->arch.scu_dev;
+
+ RPC_VER() = SC_RPC_VERSION;
+ RPC_SIZE() = 1U;
+ RPC_SVC() = (u8)(SC_RPC_SVC_MISC);
+ RPC_FUNC() = (u8)(MISC_FUNC_GET_BUTTON_STATUS);
+
+ misc_call(dev, SC_FALSE, , 1U, , 1U);
+
+ if (status)
+ *status = (sc_bool_t)(!!(RPC_U8(, 0U)));
+}
+
/* RM */
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
{
@@ -851,6 +867,21 @@ int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource,
sc_bool_t enable,
return ret;
}
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ struct sc_rpc_msg_s msg;
+ int size = sizeof(struct sc_rpc_msg_s);
+
+ RPC_VER() = SC_RPC_VERSION;
+ RPC_SVC() = (u8)(SC_RPC_SVC_PM);
+ RPC_FUNC() = (u8)(PM_FUNC_REBOOT);
+ RPC_U8(, 0U) = (u8)(type);
+ RPC_SIZE() = 2U;
+
+ misc_call(dev, SC_TRUE, , size, , size);
+}
+
int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t *mode)
{
@@ -877,6 +908,28 @@ int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t
resource,
return ret;
}
+int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ struct sc_rpc_msg_s msg;
+ int size = sizeof(struct sc_rpc_msg_s);
+ int ret;
+
+ RPC_VER() = SC_RPC_VERSION;
+ RPC_SIZE() = 2U;
+ RPC_SVC() = (u8)(SC_RPC_SVC_TIMER);
+ RPC_FUNC() = (u8)(TIMER_FUNC_SET_WDOG_WINDOW);
+
+ RPC_U32(, 0U) = (u32)(window);
+
+ ret = misc_call(dev, SC_FALSE, , size, , size);
+ if (ret)
+ printf("%s: window:%u: res:%d\n",
+ __func__, window, RPC_R8());
+
+ return ret;
+}
+
int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
sc_faddr_t addr)
{
@@ -974,6 +1027,31 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32
*commit)
*commit = RPC_U32(, 4U);
}
+int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ struct sc_rpc_msg_s msg;
+ int size = sizeof(struct sc_rpc_msg_s);
+ int ret;
+
+ RPC_VER() = SC_RPC_VERSION;
+ RPC_SIZE() = 1U;
+ RPC_SVC() = (u8)(SC_RPC_SVC_SECO);
+ RPC_FUNC() = (u8)(SECO_FUNC_V2X_BUILD_INFO);
+
+ ret = misc_call(dev, SC_FALSE, , size, , size);
+ if (ret)
+ printf("%s: res:%d\n", __func__, RPC_R8());
+
+ if (version)
+ *version = RPC_U32(, 0U);
+
+ if (commit)
+ *commit = RPC_U32(, 4U);
+
+ return ret;
+}
+
int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event)
{
struct udevice *dev = gd->arch.scu_dev;
diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h
index 39de7f0e3e0..85af6f3996e 100644
--- a/include/firmware/imx/sci/rpc.h
+++ b/include/firmware/imx/sci/rpc.h
@@ -23,12 +23,12 @@
#define RPC_FUNC(MSG) ((MSG)->func)
#define RPC_R8(MSG) ((MSG)->func)
#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
- (s64)(RPC_U32((MSG), (IDX) + 4U))
+ (s64)(RPC_U32((MSG), (IDX) + 4U))
#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
#define RPC_I8(MSG, IDX)((MSG)->DATA.i8[(IDX)])
#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
- (u64)(RPC_U32((MSG), (IDX) + 4U))
+ (u64)(RPC_U32((MSG), (IDX) + 4U))
#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
#define RPC_U16(MSG, IDX)
[PATCH V2 06/30] imx: congatec/cgtqmx8: correct SCU API usage
From: Peng Fan
The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan
Tested-by: Oliver Graute
Reviewed-by: Oliver Graute
---
board/congatec/cgtqmx8/cgtqmx8.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c
index bedd1e03308..26189ff66f5 100644
--- a/board/congatec/cgtqmx8/cgtqmx8.c
+++ b/board/congatec/cgtqmx8/cgtqmx8.c
@@ -79,7 +79,7 @@ static void setup_iomux_uart(void)
int board_early_init_f(void)
{
/* sc_ipc_t ipcHndl = 0; */
- sc_err_t scierr = 0;
+ int scierr;
/* When start u-boot in XEN VM, directly return */
/* if (IS_ENABLED(CONFIG_XEN)) */
@@ -89,19 +89,19 @@ int board_early_init_f(void)
/* Power up UART0, this is very early while power domain is not working
*/
scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0,
SC_PM_PW_MODE_ON);
- if (scierr != SC_ERR_NONE)
+ if (scierr)
return 0;
/* Set UART0 clock root to 80 MHz */
sc_pm_clock_rate_t rate = 8000;
scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, );
- if (scierr != SC_ERR_NONE)
+ if (scierr)
return 0;
/* Enable UART0 clock root */
scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
- if (scierr != SC_ERR_NONE)
+ if (scierr)
return 0;
setup_iomux_uart();
--
2.40.0
[PATCH V2 05/30] imx: advantech: correct SCU API usage
From: Peng Fan
The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan
Tested-by: Oliver Graute
Reviewed-by: Oliver Graute
---
board/advantech/imx8qm_dmsse20_a1/spl.c | 6 +++---
board/advantech/imx8qm_rom7720_a1/spl.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c
b/board/advantech/imx8qm_dmsse20_a1/spl.c
index 7f2e972425b..f36caece7d7 100644
--- a/board/advantech/imx8qm_dmsse20_a1/spl.c
+++ b/board/advantech/imx8qm_dmsse20_a1/spl.c
@@ -111,7 +111,7 @@ int board_mmc_init(struct bd_info *bis)
switch (i) {
case 0:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0,
SC_PM_PW_MODE_ON);
- if (ret != SC_ERR_NONE)
+ if (ret)
return ret;
imx8_iomux_setup_multiple_pads(emmc0,
ARRAY_SIZE(emmc0));
@@ -120,10 +120,10 @@ int board_mmc_init(struct bd_info *bis)
break;
case 1:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2,
SC_PM_PW_MODE_ON);
- if (ret != SC_ERR_NONE)
+ if (ret)
return ret;
ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4,
SC_PM_PW_MODE_ON);
- if (ret != SC_ERR_NONE)
+ if (ret)
return ret;
imx8_iomux_setup_multiple_pads(usdhc2_sd,
ARRAY_SIZE(usdhc2_sd));
diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c
b/board/advantech/imx8qm_rom7720_a1/spl.c
index b602437c35b..922bb0b7d43 100644
--- a/board/advantech/imx8qm_rom7720_a1/spl.c
+++ b/board/advantech/imx8qm_rom7720_a1/spl.c
@@ -112,7 +112,7 @@ int board_mmc_init(struct bd_info *bis)
switch (i) {
case 0:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0,
SC_PM_PW_MODE_ON);
- if (ret != SC_ERR_NONE)
+ if (ret)
return ret;
imx8_iomux_setup_multiple_pads(emmc0,
ARRAY_SIZE(emmc0));
@@ -121,10 +121,10 @@ int board_mmc_init(struct bd_info *bis)
break;
case 1:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2,
SC_PM_PW_MODE_ON);
- if (ret != SC_ERR_NONE)
+ if (ret)
return ret;
ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4,
SC_PM_PW_MODE_ON);
- if (ret != SC_ERR_NONE)
+ if (ret)
return ret;
imx8_iomux_setup_multiple_pads(usdhc2_sd,
ARRAY_SIZE(usdhc2_sd));
--
2.40.0
[PATCH V2 04/30] imx: siemens/capricorn: correct SCU API usage
From: Peng Fan
The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan
---
board/siemens/capricorn/board.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c
index a0c62e0fc4c..924c88e8fab 100644
--- a/board/siemens/capricorn/board.c
+++ b/board/siemens/capricorn/board.c
@@ -147,7 +147,7 @@ static void enet_device_phy_reset(void)
int setup_gpr_fec(void)
{
sc_ipc_t ipc_handle = -1;
- sc_err_t err = 0;
+ int err = 0;
unsigned int test;
/*
@@ -175,35 +175,35 @@ int setup_gpr_fec(void)
*/
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1);
- if (err != SC_ERR_NONE)
+ if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, );
debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test);
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0);
- if (err != SC_ERR_NONE)
+ if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, );
debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test);
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0);
- if (err != SC_ERR_NONE)
+ if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, );
debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test);
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1);
- if (err != SC_ERR_NONE)
+ if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, );
debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test);
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1);
- if (err != SC_ERR_NONE)
+ if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, );
--
2.40.0
