Re: [GIT PULL] Please pull u-boot-imx-master-20240405

[Tom Rini]

On Fri, Apr 05, 2024 at 01:46:05PM -0300, Fabio Estevam wrote:

> Hi Tom,
> 
> Please pull this material for from u-boot-imx/master, thanks.
> 
> The following changes since commit cdfcc37428e06f4730ab9a17cc084eeb7676ea1a:
> 
>   Merge tag 'u-boot-dfu-next-20240402' of 
> https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-04-02 22:37:23 
> -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git 
> tags/u-boot-imx-master-20240405
> 
> for you to fetch changes up to f6be41c83c17c09dddfb1e29a7ca391b5190634d:
> 
>   arm: imx: fix signature_block_hdr struct fields order (2024-04-05 09:39:18 
> -0300)
> 
> u-boot-imx-master-20240405

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PULL] Please pull qcom-next-2024Apr04 (attempt 2)

[Tom Rini]

On Thu, Apr 04, 2024 at 11:52:57PM +0200, Caleb Connolly wrote:

> Hi Tom,
> 
> Sorry for the noise, totally fluffed that PR... Please ignore the previous
> email.
> 
> Some new Qualcomm features for you:
> 
> * Ethernet, i2c, and USB support are now enabled by default
> * The clock driver gets some bug fixes and cleanup
> * Invalid FDTs are now properly detected in board_fdt_blob_setup().
> * The pinctrl driver gains preparatory support for per-pin function muxes.
> * Support is added for two generations of Qualcomm HighSpeed USB PHY
> * A power domain driver is added for the Globall Distributed Switch 
> Controllers
>   on the GCC hardware block.
> * SDM845 gains USB host mode support.
> * OF_LIVE is enabled by default for Qualcomm platforms
> * Some U-Boot devicetree compatibility fixups are added during init to improve
>   compatbility with upstream DT.
> 
> The following changes since commit cdfcc37428e06f4730ab9a17cc084eeb7676ea1a:
> 
>   Merge tag 'u-boot-dfu-next-20240402' of 
> https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-04-02 22:37:23 
> -0400)
> 
> are available in the Git repository at:
> 
>   g...@source.denx.de:u-boot/custodians/u-boot-snapdragon.git 
> tags/qcom-next-2024Apr04
> 
> for you to fetch changes up to b2511143fba4c0631446c968fb4c0d962b01d850:
> 
>   qcom_defconfig: enable USB (2024-04-04 17:46:48 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [GIT PULL] Please pull u-boot-amlogic-next-20240404

[Tom Rini]

On Thu, Apr 04, 2024 at 06:52:53PM +0200, Neil Armstrong wrote:

> Hi Tom,
> 
> Please pull this migration to OF_UPSTREAM for all Amlogic SoCs family
> except the newer A1 family.
> In Addition, there's a few fixes & updates for the jethubj100 board.
> 
> Thanks,
> Neil
> 
> The following changes since commit cdfcc37428e06f4730ab9a17cc084eeb7676ea1a:
> 
>   Merge tag 'u-boot-dfu-next-20240402' of 
> https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-04-02 22:37:23 
> -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-amlogic.git 
> tags/u-boot-amlogic-20240404
> 
> for you to fetch changes up to 114df8b5339e503b50b6ac1a61bf1daac57c2e11:
> 
>   dts: meson: Drop redundant G12A, G12B & SM1 devicetree files (2024-04-04 
> 18:48:46 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: Please pull u-boot-marvell/master

[Tom Rini]

On Thu, Apr 04, 2024 at 02:08:15PM +0200, Stefan Roese wrote:

> Hi Tom,
> 
> please pull the first batch of mostly Marvell related patches:
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: Please pull u-boot-samsung master

[Tom Rini]

On Thu, Apr 04, 2024 at 05:54:10PM +0900, Minkyu Kang wrote:

> Dear Tom,
> 
> The following changes since commit dde373bde392c38649c8c4420e0c98ef8d38d9dc:
> 
>   Prepare v2024.04-rc5 (2024-03-25 21:56:50 -0400)
> 
> are available in the git repository at:
> 
>   g...@source.denx.de:u-boot/custodians/u-boot-samsung.git master
> 
> for you to fetch changes up to 1751ba9a3b79ea5083ff5c4de58fe3bd9588f32a:
> 
>   clk: exynos: Add CMU_CORE and CMU_HSI for Exynos850 (2024-03-26 18:56:55
> +0900)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v4 0/6] USB keyboard improvements for asahi / desktop systems

[Janne Grunau]

On Fri, Apr 05, 2024 at 04:52:32PM +0200, Marek Vasut wrote:
> On 4/4/24 8:25 AM, Janne Grunau via B4 Relay wrote:
> > Apple USB Keyboards from 2021 need quirks to be useable. The boot HID
> > keyboard protocol is unfortunately not described in the first interface
> > descriptor but the second. This needs several changes. The USB keyboard
> > driver has to look at all (2) interface descriptors during probing.
> > Since I didn't want to rebuild the USB driver probe code the Apple
> > keyboards are bound to the keyboard driver via USB vendor and product
> > IDs.
> > To make the keyboards useable on Apple silicon devices the xhci driver
> > needs to initializes rings for the endpoints of the first two interface
> > descriptors. If this is causes concerns regarding regressions or memory
> > use the USB_MAX_ACTIVE_INTERFACES define could be turned into a CONFIG
> > option.
> > Even after this changes the keyboards still do not probe successfully
> > since they apparently do not behave HID standard compliant. They only
> > generate reports on key events. This leads the final check whether the
> > keyboard is operational to fail unless the user presses keys during the
> > probe. Skip this check for known keyboards.
> > Keychron seems to emulate Apple keyboards (some models even "re-use"
> > Apple's USB vendor ID) so apply this quirk as well.
> > 
> > Some devices like Yubikeys emulate a keyboard. since u-boot only binds a
> > single keyboard block this kind of devices from the USB keyboard driver.
> > 
> > Signed-off-by: Janne Grunau 
> 
> I picked the series, but CI indicates build errors, can you have a look ?
> 
> https://source.denx.de/u-boot/custodians/u-boot-usb/-/pipelines/20215

The issue seems to be that the field dev in struct usb_device exists
only for DM_USB. That means we can't use dev_dbg.
Either take the following fixup patch or I can resend the series.

Thanks

Janne
>From 57d54303eb2b60e92bd478e4250a9cc63cfc277e Mon Sep 17 00:00:00 2001
From: Janne Grunau 
Date: Fri, 5 Apr 2024 21:00:44 +0200
Subject: [PATCH 1/1] fixup! usb: Add environment based device ignorelist

---
 common/usb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/usb.c b/common/usb.c
index 44db07742e..8bc85c58b2 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1146,7 +1146,7 @@ int usb_select_config(struct usb_device *dev)
err = usb_device_is_ignored(dev->descriptor.idVendor,
dev->descriptor.idProduct);
if (err == -ENODEV) {
-   dev_dbg(dev->dev, "Ignoring USB device 0x%x:0x%x\n",
+   debug("Ignoring USB device 0x%x:0x%x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
return err;
} else if (err == -EINVAL) {
-- 
2.44.0

Re: [PATCH] configs: imx8mp_beacon: Enable PCIe NVMe drives

[Fabio Estevam]

On Tue, Mar 26, 2024 at 6:25 PM Adam Ford  wrote:
>
> The baseboard supports and NVMe drives via the PCIe slot. This
> requires a few extra config options to be enabled.
>
> The NVMe can be enumerated with the following commands:
>
> u-boot=> pci enum
> PCIE-0: Link up (Gen1-x1, Bus0)
> u-boot=> nvme scan
> u-boot=> nvme info
> Device 0: Vendor: 0x15b7 Rev: 20120022 Prod: 184960441105
> Type: Hard Disk
> Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
> u-boot=>
>
> Signed-off-by: Adam Ford 

Applied, thanks.

Re: [PATCH v2] arm: imx: fix signature_block_hdr struct fields order

[Fabio Estevam]

On Thu, Apr 4, 2024 at 12:11 PM Javier Viguera  wrote:
>
> According to the documentation (for example NXP's AN13994 on encrypted
> boot on AHAB-enabled devices), the format of the signature block is:
>
>   +--+--+--+-+
>   | Tag  | Length - msb | Length - lsb | Version |
>   +--+--+--+-+
>   | SRK Table offset| Certificate offset |
>   +-++
>   | Blob offset | Signature offset   |
>   +-++
>
> There is no runtime error in the current u-boot code. The only user of
> struct signature_block_hdr is the "get_container_size" function in the
> "arch/arm/mach-imx/image-container.c" file, and it's only using the very
> first fields of the struct (which are in the correct position) and thus
> there is no runtime failure.
>
> On the other hand, extending the code to get the data encryption key
> blob offset on the signature header gives a wrong value as the field is
> in the wrong order.
>
> Signed-off-by: Javier Viguera 

Applied, thanks.

Re: [PATCH v1] verdin-imx8mm/verdin-imx8mp: move imx verdins to OF_UPSTREAM

[Fabio Estevam]

On Wed, Apr 3, 2024 at 4:16 AM Marcel Ziswiler  wrote:
>
> From: Marcel Ziswiler 
>
> Move verdin-imx8mm and verdin-imx8mp to OF_UPSTREAM:
> - handle the fact that dtbs now have a 'freescale/' prefix
> - imply OF_UPSTREAM
> - remove redundant files from arch/arm/dts leaving only the
>   *-u-boot.dtsi files
> - update MAINTAINERS files
>
> Signed-off-by: Marcel Ziswiler 

Applied, thanks.

Re: [PATCH v2 1/2] arm: imx9: Correct imx9_probe_mu prototype

[Fabio Estevam]

On Sun, Mar 31, 2024 at 10:41 PM Ye Li  wrote:
>
> Since the event callback imx9_probe_mu is re-defined, update
> its prototype.
>
> Signed-off-by: Ye Li 
> ---
> Changes in v2:
>  Fix imx93_var_som and phycore_imx93 as well

Applied both, thanks.

Re: [PATCH v2] mx6cuboxi: Fix Ethernet after DT sync with Linux

[Fabio Estevam]

On Sat, Mar 30, 2024 at 6:36 PM Fabio Estevam  wrote:
>
> From: Josua Mayer 
>
> The i.MX6 Cubox-i and HummingBoards can have different PHYs at varying
> addresses. U-Boot needs to auto-detect which phy is actually present,
> and at which address it is responding.
>
> Auto-detection from multiple phy nodes specified in device-tree does not
> currently work correct. As a work-around merge all three possible phys
> into one node with the special address 0x which indicates to the
> generic phy driver to probe all addresses.
>
> Signed-off-by: Josua Mayer 
> [fabio: Added the changes to imx6qdl-sr-som-u-boot.dtsi.]
> Signed-off-by: Fabio Estevam 
> Tested-by: Christian Gmeiner 

Applied, thanks.

Re: [PATCH v2] mx6cuboxi: Do not print devicetree model

[Fabio Estevam]

On Sat, Mar 30, 2024 at 6:03 PM Fabio Estevam  wrote:
>
> The mx6cuboxi_defconfig target supports several board
> variants. All of these variants use the hummingboard devicetree in U-Boot.
>
> Currently, the devicetree model as well as the board variant name
> are shown:
>
> ...
> Model: SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)
> Board: MX6 Cubox-i
> ...
>
> Printing the devicetree model that is used internally by U-Boot
> may confuse users.
>
> Unselect the CONFIG_DISPLAY_BOARDINFO option so that only the
> board name is printed in board_late_init() instead.
>
> Signed-off-by: Fabio Estevam 

Applied, thanks.

Re: [PATCH 1/3] arm64: imx: imx8mp-beacon: Migrate to OF_UPSTREAM

[Fabio Estevam]

On Wed, Apr 3, 2024 at 11:59 PM Adam Ford  wrote:
>
> The imx8mp-beacon boards can migrate to OF_UPSTREAM which also
> allows for the removal the device tree files.
>
> Signed-off-by: Adam Ford 

Applied, thanks.

Re: [PATCH] ARM: imx: stm32: Test whether ethernet node is enabled before reading MAC EEPROM on DHSOM

[Fabio Estevam]

On Tue, Mar 12, 2024 at 6:16 PM Marek Vasut  wrote:
>
> Check whether the ethernet interface is enabled at all before reading
> MAC EEPROM. As a cost saving measure, it can happen that the MAC EEPROM
> is not populated on SoMs which do not use ethernet.
>
> Signed-off-by: Marek Vasut 

Applied, thanks.

[GIT PULL] Please pull u-boot-imx-master-20240405

[Fabio Estevam]

Hi Tom,

Please pull this material for from u-boot-imx/master, thanks.

The following changes since commit cdfcc37428e06f4730ab9a17cc084eeb7676ea1a:

  Merge tag 'u-boot-dfu-next-20240402' of 
https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-04-02 22:37:23 -0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git 
tags/u-boot-imx-master-20240405

for you to fetch changes up to f6be41c83c17c09dddfb1e29a7ca391b5190634d:

  arm: imx: fix signature_block_hdr struct fields order (2024-04-05 09:39:18 
-0300)

u-boot-imx-master-20240405
--

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/20228

- Convert imx8mp-beacon and verdin-imx8mm/verdin-imx8mp to OF_UPSTREAM.
- Enable PCIe NVMe support on imx8mp_beacon.
- Fix Ethernet and board detection on mx6cuboxi.
- Fix signature_block_hdr struct fields.
- Fix imx9_probe_mu prototype and make it to get called in EVT_DM_POST_INIT_R.
- Test whether ethernet node is enabled before reading MAC EEPROM on DHSOM SoMs.

Adam Ford (4):
  arm64: imx: imx8mp-beacon: Migrate to OF_UPSTREAM
  arm64: imx: imx8mm-beacon: Migrate to OF_UPSTREAM
  arm64: imx: imx8mn-beacon: Migrate to OF_UPSTREAM
  configs: imx8mp_beacon: Enable PCIe NVMe drives

Fabio Estevam (1):
  mx6cuboxi: Do not print devicetree model

Javier Viguera (1):
  arm: imx: fix signature_block_hdr struct fields order

Josua Mayer (1):
  mx6cuboxi: Fix Ethernet after DT sync with Linux

Marcel Ziswiler (1):
  verdin-imx8mm/verdin-imx8mp: move imx verdins to OF_UPSTREAM

Marek Vasut (1):
  ARM: imx: stm32: Test whether ethernet node is enabled before reading MAC 
EEPROM on DHSOM

Ye Li (2):
  arm: imx9: Correct imx9_probe_mu prototype
  arm: imx9: Call imx9_probe_mu for DM post in board_r

 arch/arm/dts/Makefile  |5 -
 .../imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi |1 +
 arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi|   49 +
 arch/arm/dts/imx8mm-beacon-kit.dts |   19 -
 arch/arm/dts/imx8mm-beacon-som.dtsi|  461 ---
 arch/arm/dts/imx8mm-verdin-dev.dtsi|  160 ---
 arch/arm/dts/imx8mm-verdin-wifi-dev.dts|   18 -
 arch/arm/dts/imx8mm-verdin-wifi.dtsi   |   94 --
 arch/arm/dts/imx8mm-verdin.dtsi| 1319 --
 arch/arm/dts/imx8mn-beacon-kit.dts |   19 -
 arch/arm/dts/imx8mn-beacon-som.dtsi|  472 ---
 arch/arm/dts/imx8mp-beacon-kit.dts |  783 ---
 arch/arm/dts/imx8mp-beacon-som.dtsi|  487 ---
 arch/arm/dts/imx8mp-verdin-dev.dtsi|  165 ---
 arch/arm/dts/imx8mp-verdin-wifi-dev.dts|   18 -
 arch/arm/dts/imx8mp-verdin-wifi.dtsi   |   87 --
 arch/arm/dts/imx8mp-verdin.dtsi| 1438 
 arch/arm/include/asm/arch-imx9/mu.h|2 +-
 arch/arm/mach-imx/imx8m/Kconfig|5 +
 arch/arm/mach-imx/imx9/soc.c   |1 +
 board/dhelectronics/common/dh_common.c |   16 +
 board/dhelectronics/common/dh_common.h |8 +
 board/dhelectronics/dh_imx6/dh_imx6.c  |3 +
 board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c  |6 +
 board/dhelectronics/dh_stm32mp1/board.c|6 +
 board/freescale/imx93_evk/spl.c|2 +-
 board/phytec/phycore_imx93/spl.c   |2 +-
 board/solidrun/mx6cuboxi/mx6cuboxi.c   |   40 +-
 board/toradex/verdin-imx8mm/MAINTAINERS|4 -
 board/toradex/verdin-imx8mp/MAINTAINERS|4 -
 board/variscite/imx93_var_som/spl.c|2 +-
 configs/imx8mm_beacon_defconfig|2 +-
 configs/imx8mm_beacon_fspi_defconfig   |2 +-
 configs/imx8mn_beacon_2g_defconfig |2 +-
 configs/imx8mn_beacon_defconfig|2 +-
 configs/imx8mn_beacon_fspi_defconfig   |2 +-
 configs/imx8mp_beacon_defconfig|8 +-
 configs/mx6cuboxi_defconfig|1 +
 configs/verdin-imx8mm_defconfig|2 +-
 configs/verdin-imx8mp_defconfig|2 +-
 include/imx_container.h|4 +-
 41 files changed, 124 insertions(+), 5599 deletions(-)
 create mode 100644 arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi
 delete mode 100644 arch/arm/dts/imx8mm-beacon-kit.dts
 delete mode 100644 arch/arm/dts/imx8mm-beacon-som.dtsi
 delete mode 100644 arch/arm/dts/imx8mm-verdin-dev.dtsi
 delete mode 100644 arch/arm/dts/imx8mm-verdin-wifi-dev.dts
 delete mode 100644 arch/arm/dts/imx8mm-verdin-wifi.dtsi
 delete mode 100644 arch/arm/dts/imx8mm-verdin.dtsi
 delete mode 100644 arch/arm/dts/imx

[PATCH] net: dwc_eth_qos: Fix compilation warning in eqos_free_pkt()

[Patrice Chotard]

Fix compilation warning:

../arch/arm/include/asm/io.h: In function 'eqos_free_pkt':
../arch/arm/include/asm/io.h:103:32: warning: 'rx_desc' may be used 
uninitialized [-Wmaybe-uninitialized]
  103 | #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); 
__v; })
  |^~~
../drivers/net/dwc_eth_qos.c:1220:27: note: 'rx_desc' was declared here
 1220 | struct eqos_desc *rx_desc;
  |   ^~~

Signed-off-by: Patrice Chotard 
---

 drivers/net/dwc_eth_qos.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9b3bce1dc87..9df3dde14f1 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1217,7 +1217,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar 
*packet, int length)
struct eqos_priv *eqos = dev_get_priv(dev);
u32 idx, idx_mask = eqos->desc_per_cacheline - 1;
uchar *packet_expected;
-   struct eqos_desc *rx_desc;
+   struct eqos_desc *rx_desc = NULL;
 
debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
 
-- 
2.25.1

Re: [PATCH 0/3] qcom: add pinctrl driver for SM8550 and SM8650

[Caleb Connolly]

On 05/04/2024 10:15, Neil Armstrong wrote:

Add pinctrl driver for the TLMM block found in the SM8550 & SM8650 SoCs.

This driver only handles the gpio and qup debug uart pinmux, and makes sure
the pinconf applies on SDC2 pins.

Finally enable both drivers in the Qualcomm defconfig

Signed-off-by: Neil Armstrong 


Reviewed-by: Caleb Connolly 

---
Neil Armstrong (3):
   pinctrl: qcom: Add SM8550 pinctrl driver
   pinctrl: qcom: Add SM8650 pinctrl driver
   qcom_defconfig: enable SM8550 & SM8650 pinctrl driver

  configs/qcom_defconfig|  2 +
  drivers/pinctrl/qcom/Kconfig  | 14 +++
  drivers/pinctrl/qcom/Makefile |  2 +
  drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +++
  drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++
  5 files changed, 168 insertions(+)
---
base-commit: cec1c47bdaf84a643f318d480b1218bfff1041ff
change-id: 20240404-topic-sm8x50-pinctrl-101fac729d23

Best regards,


--
// Caleb (they/them)

Re: [PATCH 11/11] net: dwc_eth_qos: Add support of STM32MP13xx platform

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

From: Christophe Roullier 

Add compatible "st,stm32mp13-dwmac" to manage STM32MP13 boards.

Signed-off-by: Christophe Roullier 
Signed-off-by: Marek Vasut  # Rebase, reshuffle, squash
code
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos.c   |  4 
  drivers/net/dwc_eth_qos.h   |  1 +
  drivers/net/dwc_eth_qos_stm32.c | 11 +++
  3 files changed, 16 insertions(+)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 203bfc0848c..e02317905e5 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1505,6 +1505,10 @@ static const struct udevice_id eqos_ids[] = {
   },
  #endif
  #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32)
+ {
+ .compatible = "st,stm32mp13-dwmac",
+ .data = (ulong)&eqos_stm32mp13_config
+ },
   {
   .compatible = "st,stm32mp1-dwmac",
   .data = (ulong)&eqos_stm32mp15_config diff --git
a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index
bafd0d339fb..8b3d0d464d3 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -290,5 +290,6 @@ int eqos_null_ops(struct udevice *dev);  extern
struct eqos_config eqos_imx_config;  extern struct eqos_config
eqos_rockchip_config;  extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_stm32mp13_config;
  extern struct eqos_config eqos_stm32mp15_config;  extern struct
eqos_config eqos_jh7110_config; diff --git
a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
index 00bf6d45568..e167a7ba901 100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -314,6 +314,17 @@ static struct eqos_ops eqos_stm32_ops = {
   .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32  };

+struct eqos_config __maybe_unused eqos_stm32mp13_config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 1,
+ .swr_wait = 50,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
+ .axi_bus_width = EQOS_AXI_WIDTH_32,
+ .interface = dev_read_phy_mode,
+ .ops = &eqos_stm32_ops
+};
+
  struct eqos_config __maybe_unused eqos_stm32mp15_config = {
   .reg_access_always_ok = false,
   .mdio_wait = 1,


Reviewed-by: Christophe ROULLIER 

Re: [PATCH 10/11] net: dwc_eth_qos: Add DT parsing for STM32MP13xx platform

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

From: Christophe Roullier 

Manage 2 ethernet instances, select which instance to configure with
mask If mask is not present in DT, it is stm32mp15 platform.

Signed-off-by: Christophe Roullier 
Signed-off-by: Marek Vasut  # Rework the code
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos_stm32.c | 82
++---
  1 file changed, 66 insertions(+), 16 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_stm32.c
b/drivers/net/dwc_eth_qos_stm32.c index 4db18130765..00bf6d45568
100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -23,6 +23,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -33,11 +34,16 @@

  /* SYSCFG registers */
  #define SYSCFG_PMCSETR   0x04
-#define SYSCFG_PMCCLRR   0x44
+#define SYSCFG_PMCCLRR_MP13  0x08
+#define SYSCFG_PMCCLRR_MP15  0x44
+
+#define SYSCFG_PMCSETR_ETH1_MASK GENMASK(23, 16)
+#define SYSCFG_PMCSETR_ETH2_MASK GENMASK(31, 24)

  #define SYSCFG_PMCSETR_ETH_CLK_SEL   BIT(16)
  #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL   BIT(17)

+/* STM32MP15xx specific bit */
  #define SYSCFG_PMCSETR_ETH_SELMIIBIT(20)

  #define SYSCFG_PMCSETR_ETH_SEL_MASK  GENMASK(23, 21)
@@ -45,6 +51,11 @@
  #define SYSCFG_PMCSETR_ETH_SEL_RGMII 0x1
  #define SYSCFG_PMCSETR_ETH_SEL_RMII  0x4

+/* CLOCK feed to PHY */
+#define ETH_CK_F_25M 2500
+#define ETH_CK_F_50M 5000
+#define ETH_CK_F_125M12500
+
  static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)  {
   struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); @@
-130,34 +141,65 @@ static int eqos_probe_syscfg_stm32(struct udevice
*dev,  {
   /* Ethernet 50MHz RMII clock selection */
   const bool eth_ref_clk_sel = dev_read_bool(dev,
"st,eth-ref-clk-sel");
+ /* SoC is STM32MP13xx with two ethernet MACs */
+ const bool is_mp13 = device_is_compatible(dev,
+"st,stm32mp13-dwmac");
   /* Gigabit Ethernet 125MHz clock selection. */
   const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
- u8 *syscfg;
+ /* Ethernet PHY have no crystal */
+ const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk");
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct regmap *regmap;
+ u32 regmap_mask;
+ ulong rate = 0;
   u32 value;

- syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
- if (!syscfg)
- return -ENODEV;
+ regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon");
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ regmap_mask = dev_read_u32_index_default(dev, "st,syscon", 2,
+  SYSCFG_PMCSETR_ETH1_MASK);
+
+ if (clk_valid(&eqos->clk_ck))
+ rate = clk_get_rate(&eqos->clk_ck);

   switch (interface_type) {
   case PHY_INTERFACE_MODE_MII:
   dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
- value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
+ /*
+  * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
+  * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
+  * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
+  * supports only MII, ETH_SELMII is not present.
+  */
+ if (!is_mp13)   /* Select MII mode on STM32MP15xx */
+ value |= SYSCFG_PMCSETR_ETH_SELMII;
   break;
- case PHY_INTERFACE_MODE_GMII:
+ case PHY_INTERFACE_MODE_GMII:   /* STM32MP15xx only */
   dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
- if (eth_clk_sel)
+ /*
+  * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
+  * otherwise use external clock from IO pin (requires matching
+  * GPIO block AF setting of that pin).
+  */
+ if (rate == ETH_CK_F_25M && (eth_clk_sel || ext_phyclk))
   value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
   break;
   case PHY_INTERFACE_MODE_RMII:
   dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_RMII);
- if (eth_ref_clk_sel)
+ /*
+  * If eth_ref_clk_sel is set, use internal clock from RCC,
+  * otherwise use external clock from ETHn_RX_CLK/ETHn_REF_CLK
+  * IO pin (re

Re: [PATCH 09/11] net: dwc_eth_qos: Request clk-ck earlier in probe on STM32

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

From: Patrick Delaunay 

Request the clk-ck earlier in probe in preparation for obtaining the
clock rate from these clk-ck in eqos_probe_syscfg_stm32() in the
follow up patch.

Signed-off-by: Patrick Delaunay 
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos_stm32.c | 10 +-
  1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_stm32.c
b/drivers/net/dwc_eth_qos_stm32.c index 33477925ff1..4db18130765
100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -201,6 +201,11 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
   return -EINVAL;
   }

+ /* Get ETH_CLK clocks (optional) */
+ ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
+ if (ret)
+ dev_dbg(dev, "No phy clock provided %d", ret);
+
   ret = eqos_probe_syscfg_stm32(dev, interface);
   if (ret)
   return -EINVAL;
@@ -223,11 +228,6 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
   goto err_probe;
   }

- /*  Get ETH_CLK clocks (optional) */
- ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
- if (ret)
- dev_warn(dev, "No phy clock provided %d\n", ret);
-
   dev_dbg(dev, "%s: OK\n", __func__);

   return 0;


Reviewed-by: Christophe ROULLIER 

Re: [PATCH 08/11] net: dwc_eth_qos: Constify st,eth-* values parsed out of DT

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

Use const bool for the values parsed out of DT. Drop the duplicate
assignment of false into those bool variables, assign them directly
with the content parsed out of DT. Abbreviate the variable name too.

Signed-off-by: Marek Vasut
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc:u-b...@dh-electronics.com
Cc:uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos_stm32.c | 18 +++---
  1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_stm32.c
b/drivers/net/dwc_eth_qos_stm32.c index 72f65f80540..33477925ff1
100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -128,17 +128,13 @@ static int eqos_stop_clks_stm32(struct udevice
*dev)  static int eqos_probe_syscfg_stm32(struct udevice *dev,
  phy_interface_t interface_type)  {
- bool eth_ref_clk_sel_reg = false;
- bool eth_clk_sel_reg = false;
+ /* Ethernet 50MHz RMII clock selection */
+ const bool eth_ref_clk_sel = dev_read_bool(dev, "st,eth-ref-clk-sel");
+ /* Gigabit Ethernet 125MHz clock selection. */
+ const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
   u8 *syscfg;
   u32 value;

- /* Gigabit Ethernet 125MHz clock selection. */
- eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
-
- /* Ethernet 50Mhz RMII clock selection */
- eth_ref_clk_sel_reg = dev_read_bool(dev, "st,eth-ref-clk-sel");
-
   syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
   if (!syscfg)
   return -ENODEV;
@@ -154,14 +150,14 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
   dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
- if (eth_clk_sel_reg)
+ if (eth_clk_sel)
   value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
   break;
   case PHY_INTERFACE_MODE_RMII:
   dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_RMII);
- if (eth_ref_clk_sel_reg)
+ if (eth_ref_clk_sel)
   value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
   break;
   case PHY_INTERFACE_MODE_RGMII:
@@ -171,7 +167,7 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
   dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_RGMII);
- if (eth_clk_sel_reg)
+ if (eth_clk_sel)
   value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
   break;
   default:


Reviewed-by: Christophe ROULLIER

Re: [PATCH 07/11] net: dwc_eth_qos: Use consistent logging prints

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

Use dev_*() only to print all the logs from this glue code, instead of
mixing dev_*(), log_*(), pr_*() all in one code.

Signed-off-by: Marek Vasut 
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos_stm32.c | 52
++---
  1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_stm32.c
b/drivers/net/dwc_eth_qos_stm32.c index 38037c47954..72f65f80540
100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -63,36 +63,36 @@ static int eqos_start_clks_stm32(struct udevice *dev)
   if (!CONFIG_IS_ENABLED(CLK))
   return 0;

- debug("%s(dev=%p):\n", __func__, dev);
+ dev_dbg(dev, "%s:\n", __func__);

   ret = clk_enable(&eqos->clk_master_bus);
   if (ret < 0) {
- pr_err("clk_enable(clk_master_bus) failed: %d", ret);
+ dev_err(dev, "clk_enable(clk_master_bus) failed: %d\n", ret);
   goto err;
   }

   ret = clk_enable(&eqos->clk_rx);
   if (ret < 0) {
- pr_err("clk_enable(clk_rx) failed: %d", ret);
+ dev_err(dev, "clk_enable(clk_rx) failed: %d\n", ret);
   goto err_disable_clk_master_bus;
   }

   ret = clk_enable(&eqos->clk_tx);
   if (ret < 0) {
- pr_err("clk_enable(clk_tx) failed: %d", ret);
+ dev_err(dev, "clk_enable(clk_tx) failed: %d\n", ret);
   goto err_disable_clk_rx;
   }

   if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
   ret = clk_enable(&eqos->clk_ck);
   if (ret < 0) {
- pr_err("clk_enable(clk_ck) failed: %d", ret);
+ dev_err(dev, "clk_enable(clk_ck) failed: %d\n", ret);
   goto err_disable_clk_tx;
   }
   eqos->clk_ck_enabled = true;
   }

- debug("%s: OK\n", __func__);
+ dev_dbg(dev, "%s: OK\n", __func__);
   return 0;

  err_disable_clk_tx:
@@ -102,7 +102,8 @@ err_disable_clk_rx:
  err_disable_clk_master_bus:
   clk_disable(&eqos->clk_master_bus);
  err:
- debug("%s: FAILED: %d\n", __func__, ret);
+ dev_dbg(dev, "%s: FAILED: %d\n", __func__, ret);
+
   return ret;
  }

@@ -113,13 +114,14 @@ static int eqos_stop_clks_stm32(struct udevice *dev)
   if (!CONFIG_IS_ENABLED(CLK))
   return 0;

- debug("%s(dev=%p):\n", __func__, dev);
+ dev_dbg(dev, "%s:\n", __func__);

   clk_disable(&eqos->clk_tx);
   clk_disable(&eqos->clk_rx);
   clk_disable(&eqos->clk_master_bus);

- debug("%s: OK\n", __func__);
+ dev_dbg(dev, "%s: OK\n", __func__);
+
   return 0;
  }

@@ -143,20 +145,20 @@ static int eqos_probe_syscfg_stm32(struct
udevice *dev,

   switch (interface_type) {
   case PHY_INTERFACE_MODE_MII:
- log_debug("PHY_INTERFACE_MODE_MII\n");
+ dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
   value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
   break;
   case PHY_INTERFACE_MODE_GMII:
- log_debug("PHY_INTERFACE_MODE_GMII\n");
+ dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
   if (eth_clk_sel_reg)
   value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
   break;
   case PHY_INTERFACE_MODE_RMII:
- log_debug("PHY_INTERFACE_MODE_RMII\n");
+ dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_RMII);
   if (eth_ref_clk_sel_reg)
@@ -166,15 +168,15 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
   case PHY_INTERFACE_MODE_RGMII_ID:
   case PHY_INTERFACE_MODE_RGMII_RXID:
   case PHY_INTERFACE_MODE_RGMII_TXID:
- log_debug("PHY_INTERFACE_MODE_RGMII\n");
+ dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_RGMII);
   if (eth_clk_sel_reg)
   value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
   break;
   default:
- log_debug("Do not manage %d interface\n",
-   interface_type);
+ dev_dbg(dev, "Do not manage %d interface\n",
+ interface_type);
   /* Do not manage others interfaces */
   return -EINVAL;
   }
@@ -194,12 +196,12 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
   phy_

Re: [PATCH 06/11] net: dwc_eth_qos: Move log_debug statements on top of case block

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

Move the log_debug() calls on top of the bit manipulation code.
No functional change.

Signed-off-by: Marek Vasut 
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos_stm32.c | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_stm32.c
b/drivers/net/dwc_eth_qos_stm32.c index 7545026b158..38037c47954
100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -143,34 +143,34 @@ static int eqos_probe_syscfg_stm32(struct
udevice *dev,

   switch (interface_type) {
   case PHY_INTERFACE_MODE_MII:
+ log_debug("PHY_INTERFACE_MODE_MII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
   value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
- log_debug("PHY_INTERFACE_MODE_MII\n");
   break;
   case PHY_INTERFACE_MODE_GMII:
+ log_debug("PHY_INTERFACE_MODE_GMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
   if (eth_clk_sel_reg)
   value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
- log_debug("PHY_INTERFACE_MODE_GMII\n");
   break;
   case PHY_INTERFACE_MODE_RMII:
+ log_debug("PHY_INTERFACE_MODE_RMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_RMII);
   if (eth_ref_clk_sel_reg)
   value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
- log_debug("PHY_INTERFACE_MODE_RMII\n");
   break;
   case PHY_INTERFACE_MODE_RGMII:
   case PHY_INTERFACE_MODE_RGMII_ID:
   case PHY_INTERFACE_MODE_RGMII_RXID:
   case PHY_INTERFACE_MODE_RGMII_TXID:
+ log_debug("PHY_INTERFACE_MODE_RGMII\n");
   value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  SYSCFG_PMCSETR_ETH_SEL_RGMII);
   if (eth_clk_sel_reg)
   value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
- log_debug("PHY_INTERFACE_MODE_RGMII\n");
   break;
   default:
   log_debug("Do not manage %d interface\n",

Reviewed-by: Christophe ROULLIER 

Re: [PATCH 05/11] net: dwc_eth_qos: Use FIELD_PREP for ETH_SEL bitfield

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

Use FIELD_PREP to configure content of ETH_SEL bitfield in
SYSCFG_PMCSETR register. No functional change.

Signed-off-by: Marek Vasut 
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos_stm32.c | 33
-
  1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_stm32.c
b/drivers/net/dwc_eth_qos_stm32.c index d7ec0c9be36..7545026b158
100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -26,6 +26,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 

  #include "dwc_eth_qos.h"
@@ -40,9 +41,9 @@
  #define SYSCFG_PMCSETR_ETH_SELMIIBIT(20)

  #define SYSCFG_PMCSETR_ETH_SEL_MASK  GENMASK(23, 21)
-#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII  0
-#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
-#define SYSCFG_PMCSETR_ETH_SEL_RMII  BIT(23)
+#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII  0x0
+#define SYSCFG_PMCSETR_ETH_SEL_RGMII 0x1
+#define SYSCFG_PMCSETR_ETH_SEL_RMII  0x4

  static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)  { @@
-142,35 +143,33 @@ static int eqos_probe_syscfg_stm32(struct udevice
*dev,

   switch (interface_type) {
   case PHY_INTERFACE_MODE_MII:
- value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
- SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
+ value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
+SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
+ value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
   log_debug("PHY_INTERFACE_MODE_MII\n");
   break;
   case PHY_INTERFACE_MODE_GMII:
+ value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
+SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
   if (eth_clk_sel_reg)
- value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
- SYSCFG_PMCSETR_ETH_CLK_SEL;
- else
- value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
+ value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
   log_debug("PHY_INTERFACE_MODE_GMII\n");
   break;
   case PHY_INTERFACE_MODE_RMII:
+ value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
+SYSCFG_PMCSETR_ETH_SEL_RMII);
   if (eth_ref_clk_sel_reg)
- value = SYSCFG_PMCSETR_ETH_SEL_RMII |
- SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
- else
- value = SYSCFG_PMCSETR_ETH_SEL_RMII;
+ value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
   log_debug("PHY_INTERFACE_MODE_RMII\n");
   break;
   case PHY_INTERFACE_MODE_RGMII:
   case PHY_INTERFACE_MODE_RGMII_ID:
   case PHY_INTERFACE_MODE_RGMII_RXID:
   case PHY_INTERFACE_MODE_RGMII_TXID:
+ value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
+SYSCFG_PMCSETR_ETH_SEL_RGMII);
   if (eth_clk_sel_reg)
- value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
- SYSCFG_PMCSETR_ETH_CLK_SEL;
- else
- value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
+ value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
   log_debug("PHY_INTERFACE_MODE_RGMII\n");
   break;
   default:

Reviewed-by: Christophe ROULLIER 

Re: [PATCH 04/11] net: dwc_eth_qos: Scrub ifdeffery

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

Replace ifdef CONFIG_CLK with if (CONFIG_IS_ENABLED(CLK)) to improve
code build coverage. Some of the functions printed debug("%s: OK\n",
__func__); on exit with and without CLK enabled, some did not, make it
consistent and print nothing if CLK is disabled.

Signed-off-by: Marek Vasut 
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos_stm32.c | 25 -
  1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_stm32.c
b/drivers/net/dwc_eth_qos_stm32.c index 7520a136ed0..d7ec0c9be36
100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -46,21 +46,22 @@

  static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)  {
-#ifdef CONFIG_CLK
- struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
+
+ if (!CONFIG_IS_ENABLED(CLK))
+ return 0;

   return clk_get_rate(&eqos->clk_master_bus);
-#else
- return 0;
-#endif
  }

  static int eqos_start_clks_stm32(struct udevice *dev)  { -#ifdef
CONFIG_CLK
- struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
   int ret;

+ if (!CONFIG_IS_ENABLED(CLK))
+ return 0;
+
   debug("%s(dev=%p):\n", __func__, dev);

   ret = clk_enable(&eqos->clk_master_bus);
@@ -89,12 +90,10 @@ static int eqos_start_clks_stm32(struct udevice *dev)
   }
   eqos->clk_ck_enabled = true;
   }
-#endif

   debug("%s: OK\n", __func__);
   return 0;

-#ifdef CONFIG_CLK
  err_disable_clk_tx:
   clk_disable(&eqos->clk_tx);
  err_disable_clk_rx:
@@ -104,20 +103,20 @@ err_disable_clk_master_bus:
  err:
   debug("%s: FAILED: %d\n", __func__, ret);
   return ret;
-#endif
  }

  static int eqos_stop_clks_stm32(struct udevice *dev)  { -#ifdef
CONFIG_CLK
- struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev);
+
+ if (!CONFIG_IS_ENABLED(CLK))
+ return 0;

   debug("%s(dev=%p):\n", __func__, dev);

   clk_disable(&eqos->clk_tx);
   clk_disable(&eqos->clk_rx);
   clk_disable(&eqos->clk_master_bus);
-#endif

   debug("%s: OK\n", __func__);
   return 0;


Reviewed-by: Christophe ROULLIER 

Re: [PATCH 03/11] net: dwc_eth_qos: Fold board_interface_eth_init into STM32 glue code

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

Move board_interface_eth_init() into eqos_probe_syscfg_stm32() in
STM32 driver glue code. The eqos_probe_syscfg_stm32() parses STM32
specific DT properties of this MAC and configures SYSCFG registers
accordingly, there is nothing board specific happening in this
function, move it into generic driver code instead. Drop the now unused 
duplicates from board files.

Signed-off-by: Marek Vasut 
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  board/dhelectronics/dh_stm32mp1/board.c | 82 ---
  board/st/stm32mp1/stm32mp1.c| 82 ---
  drivers/net/dwc_eth_qos_stm32.c | 86 -
  3 files changed, 84 insertions(+), 166 deletions(-)

diff --git a/board/dhelectronics/dh_stm32mp1/board.c
b/board/dhelectronics/dh_stm32mp1/board.c
index d1f662d9701..f179c857116 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -48,12 +48,10 @@

  /* SYSCFG registers */
  #define SYSCFG_BOOTR 0x00
-#define SYSCFG_PMCSETR   0x04
  #define SYSCFG_IOCTRLSETR0x18
  #define SYSCFG_ICNR  0x1C
  #define SYSCFG_CMPCR 0x20
  #define SYSCFG_CMPENSETR 0x24
-#define SYSCFG_PMCCLRR   0x44

  #define SYSCFG_BOOTR_BOOT_MASK   GENMASK(2, 0)
  #define SYSCFG_BOOTR_BOOTPD_SHIFT4
@@ -69,16 +67,6 @@

  #define SYSCFG_CMPENSETR_MPU_EN  BIT(0)

-#define SYSCFG_PMCSETR_ETH_CLK_SEL   BIT(16)
-#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL   BIT(17)
-
-#define SYSCFG_PMCSETR_ETH_SELMIIBIT(20)
-
-#define SYSCFG_PMCSETR_ETH_SEL_MASK  GENMASK(23, 21)
-#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII  0
-#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
-#define SYSCFG_PMCSETR_ETH_SEL_RMII  BIT(23)
-
  #define KS_CCR   0x08
  #define KS_CCR_EEPROMBIT(9)
  #define KS_BE0   BIT(12)
@@ -679,76 +667,6 @@ void board_quiesce_devices(void)  #endif  }

-/* eth init function : weak called in eqos driver */ -int
board_interface_eth_init(struct udevice *dev,
-  phy_interface_t interface_type)
-{
- u8 *syscfg;
- u32 value;
- bool eth_clk_sel_reg = false;
- bool eth_ref_clk_sel_reg = false;
-
- /* Gigabit Ethernet 125MHz clock selection. */
- eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
-
- /* Ethernet 50Mhz RMII clock selection */
- eth_ref_clk_sel_reg =
- dev_read_bool(dev, "st,eth-ref-clk-sel");
-
- syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
-
- if (!syscfg)
- return -ENODEV;
-
- switch (interface_type) {
- case PHY_INTERFACE_MODE_MII:
- value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
- SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
- debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
- break;
- case PHY_INTERFACE_MODE_GMII:
- if (eth_clk_sel_reg)
- value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
- SYSCFG_PMCSETR_ETH_CLK_SEL;
- else
- value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
- debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
- break;
- case PHY_INTERFACE_MODE_RMII:
- if (eth_ref_clk_sel_reg)
- value = SYSCFG_PMCSETR_ETH_SEL_RMII |
- SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
- else
- value = SYSCFG_PMCSETR_ETH_SEL_RMII;
- debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
- break;
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- if (eth_clk_sel_reg)
- value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
- SYSCFG_PMCSETR_ETH_CLK_SEL;
- else
- value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
- debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
- break;
- default:
- debug("%s: Do not manage %d interface\n",
-   __func__, interface_type);
- /* Do not manage others interfaces */
- return -EINVAL;
- }
-
- /* clear and set ETH configuration bits */
- writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
-SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
-syscfg + SYSCFG_PMCCLRR);
- writel(value, syscfg + SYSCFG_PMCSETR);
-
- return 0;
-}
-
  #if defined(CONFIG_OF_BOARD_SETUP)
  int ft_board_setup(void *blob, struct bd_info *bd)  { diff --git
a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index
a17c314daeb..f284b0dfd28 100644
--- a/board/st/stm32mp1/stm32mp1.c
+

Re: [PATCH 03/11] net: dwc_eth_qos: Fold board_interface_eth_init into STM32 glue code

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

Move board_interface_eth_init() into eqos_probe_syscfg_stm32() in
STM32 driver glue code. The eqos_probe_syscfg_stm32() parses STM32
specific DT properties of this MAC and configures SYSCFG registers
accordingly, there is nothing board specific happening in this
function, move it into generic driver code instead. Drop the now unused 
duplicates from board files.

Signed-off-by: Marek Vasut 
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  board/dhelectronics/dh_stm32mp1/board.c | 82 ---
  board/st/stm32mp1/stm32mp1.c| 82 ---
  drivers/net/dwc_eth_qos_stm32.c | 86 -
  3 files changed, 84 insertions(+), 166 deletions(-)

diff --git a/board/dhelectronics/dh_stm32mp1/board.c
b/board/dhelectronics/dh_stm32mp1/board.c
index d1f662d9701..f179c857116 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -48,12 +48,10 @@

  /* SYSCFG registers */
  #define SYSCFG_BOOTR 0x00
-#define SYSCFG_PMCSETR   0x04
  #define SYSCFG_IOCTRLSETR0x18
  #define SYSCFG_ICNR  0x1C
  #define SYSCFG_CMPCR 0x20
  #define SYSCFG_CMPENSETR 0x24
-#define SYSCFG_PMCCLRR   0x44

  #define SYSCFG_BOOTR_BOOT_MASK   GENMASK(2, 0)
  #define SYSCFG_BOOTR_BOOTPD_SHIFT4
@@ -69,16 +67,6 @@

  #define SYSCFG_CMPENSETR_MPU_EN  BIT(0)

-#define SYSCFG_PMCSETR_ETH_CLK_SEL   BIT(16)
-#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL   BIT(17)
-
-#define SYSCFG_PMCSETR_ETH_SELMIIBIT(20)
-
-#define SYSCFG_PMCSETR_ETH_SEL_MASK  GENMASK(23, 21)
-#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII  0
-#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
-#define SYSCFG_PMCSETR_ETH_SEL_RMII  BIT(23)
-
  #define KS_CCR   0x08
  #define KS_CCR_EEPROMBIT(9)
  #define KS_BE0   BIT(12)
@@ -679,76 +667,6 @@ void board_quiesce_devices(void)  #endif  }

-/* eth init function : weak called in eqos driver */ -int
board_interface_eth_init(struct udevice *dev,
-  phy_interface_t interface_type)
-{
- u8 *syscfg;
- u32 value;
- bool eth_clk_sel_reg = false;
- bool eth_ref_clk_sel_reg = false;
-
- /* Gigabit Ethernet 125MHz clock selection. */
- eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
-
- /* Ethernet 50Mhz RMII clock selection */
- eth_ref_clk_sel_reg =
- dev_read_bool(dev, "st,eth-ref-clk-sel");
-
- syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
-
- if (!syscfg)
- return -ENODEV;
-
- switch (interface_type) {
- case PHY_INTERFACE_MODE_MII:
- value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
- SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
- debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
- break;
- case PHY_INTERFACE_MODE_GMII:
- if (eth_clk_sel_reg)
- value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
- SYSCFG_PMCSETR_ETH_CLK_SEL;
- else
- value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
- debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
- break;
- case PHY_INTERFACE_MODE_RMII:
- if (eth_ref_clk_sel_reg)
- value = SYSCFG_PMCSETR_ETH_SEL_RMII |
- SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
- else
- value = SYSCFG_PMCSETR_ETH_SEL_RMII;
- debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
- break;
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- if (eth_clk_sel_reg)
- value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
- SYSCFG_PMCSETR_ETH_CLK_SEL;
- else
- value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
- debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
- break;
- default:
- debug("%s: Do not manage %d interface\n",
-   __func__, interface_type);
- /* Do not manage others interfaces */
- return -EINVAL;
- }
-
- /* clear and set ETH configuration bits */
- writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
-SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
-syscfg + SYSCFG_PMCCLRR);
- writel(value, syscfg + SYSCFG_PMCSETR);
-
- return 0;
-}
-
  #if defined(CONFIG_OF_BOARD_SETUP)
  int ft_board_setup(void *blob, struct bd_info *bd)  { diff --git
a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index
a17c314daeb..f284b0dfd28 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ 

Re: [PATCH 02/11] net: dwc_eth_qos: Rename eqos_stm32_config to eqos_stm32mp15_config

[Christophe ROULLIER]

On 3/9/24 03:11, Marek Vasut wrote:

The current glue code is specific to STM32MP15xx, the upcoming
STM32MP13xx will introduce another entry specific to the STM32MP13xx.
Rename the current entry to eqos_stm32mp15_config in preparation for
STM32MP13xx addition. No functional change.

Signed-off-by: Marek Vasut
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc:u-b...@dh-electronics.com
Cc:uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos.c   | 2 +-
  drivers/net/dwc_eth_qos.h   | 2 +-
  drivers/net/dwc_eth_qos_stm32.c | 2 +-
  3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 533c2bf070b..203bfc0848c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1507,7 +1507,7 @@ static const struct udevice_id eqos_ids[] = {
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32)
   {
   .compatible = "st,stm32mp1-dwmac",
- .data = (ulong)&eqos_stm32_config
+ .data = (ulong)&eqos_stm32mp15_config
   },
  #endif
  #if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index a6087f191ab..bafd0d339fb 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -290,5 +290,5 @@ int eqos_null_ops(struct udevice *dev);  extern
struct eqos_config eqos_imx_config;  extern struct eqos_config
eqos_rockchip_config;  extern struct eqos_config eqos_qcom_config;
-extern struct eqos_config eqos_stm32_config;
+extern struct eqos_config eqos_stm32mp15_config;
  extern struct eqos_config eqos_jh7110_config; diff --git
a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
index cfda757133e..fd29a604987 100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -184,7 +184,7 @@ static struct eqos_ops eqos_stm32_ops = {
   .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32  };

-struct eqos_config __maybe_unused eqos_stm32_config = {
+struct eqos_config __maybe_unused eqos_stm32mp15_config = {
   .reg_access_always_ok = false,
   .mdio_wait = 1,
   .swr_wait = 50,

Reviewed-by: Christophe Roullier

Re: [PATCH 11/11] net: dwc_eth_qos: Add support of STM32MP13xx platform

[Marek Vasut]

On 4/5/24 4:56 PM, Christophe ROULLIER wrote:

On 3/9/24 03:11, Marek Vasut wrote:

From: Christophe Roullier 

Add compatible "st,stm32mp13-dwmac" to manage STM32MP13 boards.

Signed-off-by: Christophe Roullier 
Signed-off-by: Marek Vasut  # Rebase, reshuffle, squash
code
---
Cc: Christophe Roullier 
Cc: Joe Hershberger 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: Ramon Fried 
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  drivers/net/dwc_eth_qos.c   |  4 
  drivers/net/dwc_eth_qos.h   |  1 +
  drivers/net/dwc_eth_qos_stm32.c | 11 +++
  3 files changed, 16 insertions(+)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 203bfc0848c..e02317905e5 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1505,6 +1505,10 @@ static const struct udevice_id eqos_ids[] = {
   },
  #endif
  #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32)
+ {
+ .compatible = "st,stm32mp13-dwmac",
+ .data = (ulong)&eqos_stm32mp13_config
+ },
   {
   .compatible = "st,stm32mp1-dwmac",
   .data = (ulong)&eqos_stm32mp15_config diff --git
a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index
bafd0d339fb..8b3d0d464d3 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -290,5 +290,6 @@ int eqos_null_ops(struct udevice *dev);  extern
struct eqos_config eqos_imx_config;  extern struct eqos_config
eqos_rockchip_config;  extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_stm32mp13_config;
  extern struct eqos_config eqos_stm32mp15_config;  extern struct
eqos_config eqos_jh7110_config; diff --git
a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
index 00bf6d45568..e167a7ba901 100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -314,6 +314,17 @@ static struct eqos_ops eqos_stm32_ops = {
   .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32  };

+struct eqos_config __maybe_unused eqos_stm32mp13_config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 1,
+ .swr_wait = 50,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
+ .axi_bus_width = EQOS_AXI_WIDTH_32,
+ .interface = dev_read_phy_mode,
+ .ops = &eqos_stm32_ops
+};
+
  struct eqos_config __maybe_unused eqos_stm32mp15_config = {
   .reg_access_always_ok = false,
   .mdio_wait = 1,


Reviewed-by: Christophe ROULLIER 


Thank you. There is a V2 series submitted, can you add those tags there 
too ?

Re: [PATCH v4 0/6] USB keyboard improvements for asahi / desktop systems

[Marek Vasut]

On 4/4/24 8:25 AM, Janne Grunau via B4 Relay wrote:

Apple USB Keyboards from 2021 need quirks to be useable. The boot HID
keyboard protocol is unfortunately not described in the first interface
descriptor but the second. This needs several changes. The USB keyboard
driver has to look at all (2) interface descriptors during probing.
Since I didn't want to rebuild the USB driver probe code the Apple
keyboards are bound to the keyboard driver via USB vendor and product
IDs.
To make the keyboards useable on Apple silicon devices the xhci driver
needs to initializes rings for the endpoints of the first two interface
descriptors. If this is causes concerns regarding regressions or memory
use the USB_MAX_ACTIVE_INTERFACES define could be turned into a CONFIG
option.
Even after this changes the keyboards still do not probe successfully
since they apparently do not behave HID standard compliant. They only
generate reports on key events. This leads the final check whether the
keyboard is operational to fail unless the user presses keys during the
probe. Skip this check for known keyboards.
Keychron seems to emulate Apple keyboards (some models even "re-use"
Apple's USB vendor ID) so apply this quirk as well.

Some devices like Yubikeys emulate a keyboard. since u-boot only binds a
single keyboard block this kind of devices from the USB keyboard driver.

Signed-off-by: Janne Grunau 


I picked the series, but CI indicates build errors, can you have a look ?

https://source.denx.de/u-boot/custodians/u-boot-usb/-/pipelines/20215

Thanks !

Re: [PATCH 0/4] Simplefb and fb reservation related updates

[Devarsh Thakkar]

Gentle Reminder.

On 08/03/24 16:38, Devarsh Thakkar wrote:
> Hi Tom, Anatolij, Simon,
> 
> On 22/02/24 18:38, Devarsh Thakkar wrote:
>> This adds support for simple-framebuffer reservation using video handoff
>> when splash is enabled at SPL stage.
>>
>> Also adds helper function to only enable framebuffer reservation without
>> enabling simple-framebuffer in case user want to continue display
>> bootloader splash without displaying anything else in between until
>> kernel boots up.
>>
>> Lastly, it enables above support on AM62x.
>>
> 
> I saw a RB on first 3 patches so just wanted to check if it looks good to you
> too then is it possible to pull in the first 3 patches if no further comments 
> ?
> 
> Regards
> Devarsh
> 
>> Devarsh Thakkar (4):
>>   boot: fdt_simplefb: Enumerate framebuffer info from video handoff
>>   video: Assume video to be active if SPL is passing video hand-off
>>   boot: Move framebuffer reservation to separate helper
>>   board: ti: am62x: evm: Update simple-framebuffer node in device-tree
>>
>>  board/ti/am62x/evm.c | 19 +++
>>  boot/fdt_simplefb.c  | 46 
>>  boot/fdt_support.c   | 21 
>>  drivers/video/video-uclass.c |  4 
>>  include/fdt_support.h|  2 ++
>>  5 files changed, 72 insertions(+), 20 deletions(-)
>>

Re: [PATCH v3 6/6] board: add support for Schneider HMIBSC board

[Stephan Gerhold]

On Fri, Apr 05, 2024 at 02:37:42PM +0530, Sumit Garg wrote:
> Support for Schneider Electric HMIBSC. Features:
> - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
> - 2GiB RAM
> - 64GiB eMMC, SD slot
> - WiFi and Bluetooth
> - 2x Host, 1x Device USB port
> - HDMI
> - Discrete TPM2 chip over SPI
> 
> Features enabled in U-Boot:
> - RAUC updates
> - Environment protection
> - USB based ethernet adaptors
> 
> Signed-off-by: Sumit Garg 

I don't think this is a big deal but this patch would be a bit easier to
skim over if you move the (unmodified?) import of the Linux
apq8016-schneider-hmibsc.dts to a separate patch with a clear note in
the commit message

 - where it comes from (link to Linux patch), and
 - that it can be removed again with a future update of the upstream DTs
   in U-Boot (once it is applied upstream at least).

You kind of have that information in the cover letter but I think it
would be good to have it in the commit message.

> ---
>  arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++
>  board/schneider/hmibsc/MAINTAINERS|   6 +
>  configs/hmibsc_defconfig  |  86 
>  doc/board/index.rst   |   1 +
>  doc/board/schneider/hmibsc.rst|  45 ++
>  doc/board/schneider/index.rst |   9 +
>  include/configs/hmibsc.h  |  57 +++
>  7 files changed, 695 insertions(+)
>  create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts
>  create mode 100644 board/schneider/hmibsc/MAINTAINERS
>  create mode 100644 configs/hmibsc_defconfig
>  create mode 100644 doc/board/schneider/hmibsc.rst
>  create mode 100644 doc/board/schneider/index.rst
>  create mode 100644 include/configs/hmibsc.h
> 
> [...]
> diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h
> new file mode 100644
> index 000..66dfa549ce1
> --- /dev/null
> +++ b/include/configs/hmibsc.h
> @@ -0,0 +1,57 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Board configuration file for HMIBSC
> + *
> + * (C) Copyright 2024 Sumit Garg 
> + */
> +
> +#ifndef __CONFIGS_HMIBSC_H
> +#define __CONFIGS_HMIBSC_H
> +
> +/* PHY needs a longer aneg time */
> +#define PHY_ANEG_TIMEOUT 8000
> +
> +#define HMIBSC_BOOTCOMMAND \
> + "setenv devtype mmc; setenv devnum 0; " \
> + "test -n \"${BOOT_ORDER}\" || setenv BOOT_ORDER \"A B\"; " \
> + "test -n \"${BOOT_A_LEFT}\" || setenv BOOT_A_LEFT 3; " \
> + "test -n \"${BOOT_B_LEFT}\" || setenv BOOT_B_LEFT 3; " \
> + "setenv raucslot; " \
> + "for BOOT_SLOT in \"${BOOT_ORDER}\"; do " \
> + "  if test \"x${raucslot}\" != \"x\"; then " \
> + "  echo \"skip remaining slots...\"; " \
> + "  elif test \"x${BOOT_SLOT}\" = \"xA\"; then " \
> + "if test ${BOOT_A_LEFT} -gt 0; then " \
> + "  setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1; " \
> + "  echo \"Found valid RAUC slot A\"; " \
> + "  setenv raucslot \"rauc.slot=A\"; " \
> + "  setenv raucpart A; setenv distro_bootpart 6;" \
> + "fi; " \
> + "  elif test \"x${BOOT_SLOT}\" = \"xB\"; then " \
> + "if test ${BOOT_B_LEFT} -gt 0; then " \
> + "  setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1; " \
> + "  echo \"Found valid RAUC slot B\"; " \
> + "  setenv raucslot \"rauc.slot=B\"; " \
> + "  setenv raucpart B; setenv distro_bootpart 7;" \
> + "fi; " \
> + "  fi; " \
> + "done; " \
> + "if test -n \"${raucslot}\"; then " \
> + "  setenv bootargs console=ttyMSM1 root=PARTLABEL=rootfs_${raucpart} rw 
> rootwait ${raucslot}; " \
> + "  saveenv; " \
> + "else " \
> + "  echo \"No valid RAUC slot found. Resetting tries to 3\"; " \
> + "  setenv BOOT_A_LEFT 3; " \
> + "  setenv BOOT_B_LEFT 3; " \
> + "  saveenv; " \
> + "  reset; " \
> + "fi; " \
> + "load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} 
> /boot/fitImage && bootm"
> +
> +#define CFG_EXTRA_ENV_SETTINGS \
> + "loadaddr=0x9000\0" \
> + "bootcmd="  HMIBSC_BOOTCOMMAND  "\0"
> +

The "text-based environment" [1] is preferred nowadays, i.e. defining
these inside board/schneider/hmibsc/hmibsc.env instead (similar to how
DB410c has its environment defined in
board/qualcomm/dragonboard410c/dragonboard410c.env). This should also
avoid all the crazy escaping to encode it as C string. :D

However, I suspect that right now it would attempt to load this file
from board/qualcomm/hmibsc/hmibsc.env since you do not seem to have
CONFIG_SYS_VENDOR set correctly. It looks like Caleb removed the option
to customize CONFIG_SYS_VENDOR in commit 059d526af312 ("mach-snapdragon:
generalise board support"). It might be easiest to add a prompt in
arch/arm/mach-snapdragon/Kconfig to allow changing it (similar to
CONFIG_SYS_BOARD).

Thanks,
Stephan

[1]: 
https://docs.u-boot.org/en/latest/usage/environment.html#text-based-environment

Re: [PATCH] mtd: spi-nor: Add support for Infineon S25FS-S family

[Pratyush Yadav]

Hi,

Just a couple small comments. Looks good otherwise.

On Fri, Apr 05 2024, tkuw584...@gmail.com wrote:

> From: Takahiro Kuwano 
>
> The S25FS064S, S25FS128S, and S25FS256S are the same family of SPI NOR
> Flash devices with S25FS512S. Some difference depending on the device
> densities are taken care in fixup hooks.
>
> Signed-off-by: Takahiro Kuwano 
> ---
> Datasheets:
> https://www.infineon.com/dgdl/Infineon-S25FS064S_64_Mb_8_MB_FS-S_Flash_SPI_Multi-I_O_1-DataSheet-v10_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ed526b25412
> https://www.infineon.com/dgdl/Infineon-S25FS128S_S25FS256S_1.8_V_Serial_Peripheral_Interface_with_Multi-I_O_MirrorBit(R)_Non-Volatile_Flash-DataSheet-v15_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ed6b5ab5758
> ---
>  drivers/mtd/spi/spi-nor-core.c | 28 +---
>  drivers/mtd/spi/spi-nor-ids.c  |  7 +--
>  2 files changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index f86003ca8c..9b81b31e8e 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3299,8 +3299,10 @@ static int s25fs_s_quad_enable(struct spi_nor *nor)
>
>  static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr)
>  {
> + u8 opcode = nor->addr_width == 4 ? SPINOR_OP_BE_4K_4B : SPINOR_OP_BE_4K;
> +
>   /* Support 8 x 4KB sectors at bottom */
> - return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, 
> SZ_32K);
> + return spansion_erase_non_uniform(nor, addr, opcode, 0, SZ_32K);

Looks like an unrelated bugfix. Should this be a separate patch?

>  }
>
>  static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info,
> @@ -3354,12 +3356,24 @@ static int s25fs_s_post_bfpt_fixup(struct spi_nor 
> *nor,
>  static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor,
>   struct spi_nor_flash_parameter *params)
>  {
> - /* READ_1_1_2 is not supported */
> - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
> - /* READ_1_1_4 is not supported */
> - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4;
> - /* PP_1_1_4 is not supported */
> - params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
> + /*
> +  * The S25FS064S(8MB) supports 1-1-2 and 1-1-4 commands, but params for
> +  * read ops in SFDP are wrong. The other density parts do not support
> +  * 1-1-2 and 1-1-4 commands.
> +  */
> + if (params->size == SZ_8M) {
> + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
> +   0, 8, SPINOR_OP_READ_1_1_2,
> +   SNOR_PROTO_1_1_2);
> + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
> +   0, 8, SPINOR_OP_READ_1_1_4,
> +   SNOR_PROTO_1_1_4);
> + } else {
> + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
> + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4;
> + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
> + }
> +
>   /* Use volatile register to enable quad */
>   params->quad_enable = s25fs_s_quad_enable;
>  }
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 4e83b8c94c..9ca1f244f0 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -338,9 +338,12 @@ const struct flash_info spi_nor_ids[] = {
>*/
>   { INFO("s25sl032p",  0x010215, 0x4d00,  64 * 1024,  64, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>   { INFO("s25sl064p",  0x010216, 0x4d00,  64 * 1024, 128, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> - { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> - { INFO("s25fl256s1", 0x010219, 0x4d01,  64 * 1024, 512, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> + { INFO6("s25fl256s0", 0x010219, 0x4d0080, 256 * 1024, 128, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> + { INFO6("s25fl256s1", 0x010219, 0x4d0180,  64 * 1024, 512, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },

Unrelated change. Is this intentional? If so, please make it a separate
patch.

>   { INFO6("s25fl512s",  0x010220, 0x4d0080, 256 * 1024, 256, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> + { INFO6("s25fs064s",  0x010217, 0x4d0181,  64 * 1024, 128, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> + { INFO6("s25fs128s",  0x012018, 0x4d0181,  64 * 1024, 256, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> + { INFO6("s25fs256s",  0x010219, 0x4d0181,  64 * 1024, 512, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>   { INFO6("s25fs512s",  0x010220, 0x4d0081, 256 * 1024, 256, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>   { INFO("s25fl512s_256k",  0x010220, 0x4d00, 256 * 1024, 256, 
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_

Re: [RFC PATCH 13/15] arm: dts: Introduce J722S U-Boot dts files

[Andrew Davis]

On 4/5/24 2:18 AM, Jayesh Choudhary wrote:

Hi,

On 04/04/24 20:59, Andrew Davis wrote:

On 4/4/24 4:00 AM, Jayesh Choudhary wrote:

Include the uboot device tree files needed to boot the board.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
  arch/arm/dts/Makefile  |    2 +
  arch/arm/dts/k3-j722s-binman.dtsi  |  171 ++
  arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi | 2795 
  arch/arm/dts/k3-j722s-evm-u-boot.dtsi  |   36 +
  arch/arm/dts/k3-j722s-r5-evm.dts   |   82 +
  5 files changed, 3086 insertions(+)
  create mode 100644 arch/arm/dts/k3-j722s-binman.dtsi
  create mode 100644 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi
  create mode 100644 arch/arm/dts/k3-j722s-evm-u-boot.dtsi
  create mode 100644 arch/arm/dts/k3-j722s-r5-evm.dts



[...]


diff --git a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi 
b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi
new file mode 100644
index 00..056ef08455
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common J722S EVM dts file for SPLs
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-j722s-binman.dtsi"
+
+/ {
+    chosen {
+    stdout-path = "serial2:115200n8";
+    tick-timer = &main_timer0;
+    };
+};
+
+&main_pktdma {
+    reg = <0x00 0x485c 0x00 0x000100>,
+  <0x00 0x4a80 0x00 0x02>,
+  <0x00 0x4aa0 0x00 0x04>,
+  <0x00 0x4b80 0x00 0x40>,
+  <0x00 0x485e 0x00 0x02>,
+  <0x00 0x484a 0x00 0x004000>,
+  <0x00 0x484c 0x00 0x002000>,
+  <0x00 0x4843 0x00 0x004000>;
+    reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+    "cfg", "tchan", "rchan", "rflow";


Is this needed? Do we still not have the correct regs in
upstream kernel?


I missed this change when I was going through j722s dts changes.

u-boot dts currently does not have this fixed.
Tag v6.9-rc1-dts from devicetree-rebasing would have this fix.

Will keep this in mind.

Also from TRM memory map, the range is off for 'tchanrt'
Will send a fix patch for that after checking for all platforms
to linux upstream if required.




+};
+
+&dmsc {
+    bootph-pre-ram;
+
+    k3_sysreset: sysreset-controller {
+    compatible = "ti,sci-sysreset";
+    bootph-pre-ram;


This node won't be needed soon either[0]. Should mean an
almost empty -u-boot.dtsi file, which should be the goal.



Okay. I will remove the node.

Should I mark [0] as dependency or is it okay without it.
Impact would only be on U-Boot RESET I think. Base support
would still be functional.



That is correct, if this goes in before [0] without this node
the only thing that wouldn't work is reset, and it would start
working again when [0] goes in. So no real dependency.

Andrew


Thanks,
Jayesh


Andrew

[0] https://lore.kernel.org/all/20240402160908.508974-1-...@ti.com/


+    };


[...]

Re: [V1 PATCH 1/2] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588

[Quentin Schulz]

Hi Chris,

On 4/4/24 23:33, Chris Morgan wrote:

On Tue, Apr 02, 2024 at 06:38:59PM +0200, Quentin Schulz wrote:

Hi Chris,

On 4/1/24 20:14, Chris Morgan wrote:

From: Chris Morgan 

Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with

= 16GB of RAM. In the event that neither SOC is used and the

ROCKCHIP_TPL stage is not used, fall back to existing logic.

Signed-off-by: Chris Morgan 
---
   arch/arm/mach-rockchip/sdram.c | 100 +
   1 file changed, 100 insertions(+)

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f..e02fb03c5f 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -12,6 +12,7 @@
   #include 
   #include 
   #include 
+#include 
   DECLARE_GLOBAL_DATA_PTR;
@@ -35,11 +36,110 @@ struct tos_parameter_t {
s64 reserve[8];
   };
+/* Tag magic */
+#define ATAGS_CORE_MAGIC   0x54410001
+#define ATAGS_DDR_MEM_MAGIC0x54410052
+
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET   (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+
+/* ATAGS memory structure. */
+struct tag_ddr_mem {
+   u32 count;
+   u32 version;
+   u64 bank[20];
+   u32 flags;
+   u32 data[2];
+   u32 hash;
+} __packed;
+
+/**
+ * rockchip_dram_init_banksize() - Get RAM banks from Rockchip TPL
+ *
+ * Iterate through the defined ATAGS memory location to first find a
+ * valid core header, then find a valid ddr_info header. Sanity check
+ * the number of banks found. Then, iterate through the data to add
+ * each individual memory bank. Perform fixups on memory banks that
+ * overlap with a reserved space. If an error condition is received,
+ * it is expected that memory bank setup will fall back on existing
+ * logic. If ROCKCHIP_EXTERNAL_TPL is false then immediately return,
+ * and if neither ROCKCHIP_RK3588 or ROCKCHIP_RK3568 is enabled
+ * immediately return.
+ *
+ * Return number of banks found on success or negative on error.
+ */
+__weak int rockchip_dram_init_banksize(void)
+{
+   struct tag_ddr_mem *ddr_info;
+   size_t val;
+   size_t addr = ATAGS_PHYS_BASE;


I think this should be phys_addr_t instead of size_t?

size_t is an unsigned long on aarch64 and phys_addr_t is an unsigned long
long so 4B vs 8B.

This however would likely prevent us from reusing this code on aarch32
machines, but maybe it's a problem for the people who'll look into
supporting this :) (also, aarch32 and >= 3.75GiB may be a bit optimistic :)
).


Could I just specify a size and not worry about it? A u32 should be more
than enough to hold the maximum RAM address of an RK3588 board (32GB).
That would allow this to work on both 32 and 64 right? Otherwise I could
further restrict this code to the AARCH64 ifdef.



There's even a bigger issue here as phys_t is an 8B structure (on 
Aarch64) while the atags are actually 4B aligned, so that would 
unnecessarily increase the complexity for arithmetic on those addresses. 
So u32 would probably be fine then.





+   int i;
+


u8 is plenty enough here :)


I use it as a return value where there are negative numbers (though
obviously this should never be negative since it's an increment
counter). Does that matter?



You could return i still and let the compiler do the conversion.

No, it's not a blocker, but that may unnecessarily increase the size of 
the TPL.


[...]


+   break;
+   addr += 4;


This is an incorrect step size, addr is 4B, so this will result in 16B
increments, which may be too much. Additionally, we shouldn't read every 4B
as the tag is only ever guaranteed to be 4B aligned, not that we would have
a tag every 4B. This also means that it's possible somehow the content of a
tag at a 4B-aligned offset has the CORE_MAGIC for some reason, but we
shouldn't match on it.



I'm not quite sure I follow. Are you saying I need to increment every
4 * the value of size in the tag_header? The value I show is 0x5 in
my header meaning increment every 0x14?



What we have in memory is (each 4B) (correct me if I misread Rockchip's 
code)


tag1.size = 6
tag1.magic
data1[0]
data1[1]
data1[2]
data1[3]
tag2.size = 4
tag2.magic
data2[0]
data2[1]

...

You start with addr = &tag1.size
when you do addr +4, you now have addr= &data1[2]

By casting data1[2] into a tag struct, you would have

tagX.size = data1[2]
tagX.magic = data1[3]

If somehow data1[3] matches the magic, you'll detect tag data as a tag 
header, and that's no good. Also, you may be missing a tag by checking 
every 16B, which isn't guaranteed by Rockchip's ATAGS (only guaranteed 
to be 4B aligned)


tag1.size is the size of the tag1 in multiples

Re: [PATCH 0/3] qcom: add clock driver support for SM8550 and SM8650 SoCc

[Caleb Connolly]

Hi Neil,

On 04/04/2024 18:46, Neil Armstrong wrote:

Add the GCC and TCSRCC clock driver for the SM8550 & SM8650 SoCs.

The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.

The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.

The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.

In addition, the drivers are enabled in the Qualcomm defconfig.

Signed-off-by: Neil Armstrong 


Reviewed-by: Caleb Connolly 

---
Neil Armstrong (3):
   clk: qcom: Add SM8550 clock driver
   clk: qcom: Add SM8650 clock driver
   qcom_defconfig: enable SM8550 & SM8650 clock driver

  configs/qcom_defconfig  |   2 +
  drivers/clk/qcom/Kconfig|  16 ++
  drivers/clk/qcom/Makefile   |   2 +
  drivers/clk/qcom/clock-sm8550.c | 335 
  drivers/clk/qcom/clock-sm8650.c | 332 +++
  5 files changed, 687 insertions(+)
---
base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb
change-id: 20240404-topic-sm8x50-clock-a76f8359b5fb

Best regards,


--
// Caleb (they/them)

Re: [PATCH 3/3] button: qcom-pmic: add support for pmk8350 button configs

[Neil Armstrong]

On 05/04/2024 10:27, Neil Armstrong wrote:

Finally add the entries for the qcom,pmk8350-pwrkey and qcom,pmk8350-resin
found on PMICs used with SM8350 and later SoCs.

Signed-off-by: Neil Armstrong 
---
  drivers/button/button-qcom-pmic.c | 14 ++
  1 file changed, 14 insertions(+)

diff --git a/drivers/button/button-qcom-pmic.c 
b/drivers/button/button-qcom-pmic.c
index f6da958097c..6153601017b 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -36,6 +36,8 @@ struct qcom_pmic_btn_priv {
  #define PON_INT_RT_STS0x10
  #define  PON_KPDPWR_N_SET 0
  #define  PON_RESIN_N_SET  1
+#define  PON_GEN3_RESIN_N_SET  6
+#define  PON_GEN3_KPDPWR_N_SET 7
  
  static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)

  {
@@ -69,6 +71,18 @@ static const struct qcom_pmic_btn_data 
qcom_pmic_btn_data_table[] = {
.code = KEY_DOWN,
.label = "vol_down",
},
+   {
+   .compatible = "qcom,pmk8350-pwrkey",
+   .status_bit = PON_GEN3_KPDPWR_N_SET,
+   .code = KEY_ENTER,
+   .label = "pwrkey",
+   },
+   {
+   .compatible = "qcom,pmk8350-resin",
+   .status_bit = PON_GEN3_RESIN_N_SET,
+   .code = KEY_DOWN,
+   .label = "vol_down",
+   },
  };
  
  static const struct qcom_pmic_btn_data *button_qcom_pmic_match(ofnode node)




Missing change:

diff --git a/drivers/button/button-qcom-pmic.c 
b/drivers/button/button-qcom-pmic.c
index 6153601017b..ad7fed3ddaa 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -193,6 +193,7 @@ static const struct udevice_id qcom_pwrkey_ids[] = {
{ .compatible = "qcom,pm8916-pon" },
{ .compatible = "qcom,pm8941-pon" },
{ .compatible = "qcom,pm8998-pon" },
+   { .compatible = "qcom,pmk8350-pon" },
{ }
 };

Will send a v2 in a few days.

Neil

Re: [PATCH 1/2] phy: qcom: add Synopsys eUSB2 PHY driver

[Neil Armstrong]

On 05/04/2024 10:35, Neil Armstrong wrote:

Add a driver for the new Synopsys eUSB2 PHY found in the SM8550
and SM8650 SoCs.

Signed-off-by: Neil Armstrong 
---
  drivers/phy/qcom/Kconfig   |   8 +
  drivers/phy/qcom/Makefile  |   1 +
  drivers/phy/qcom/phy-qcom-snps-eusb2.c | 365 +
  3 files changed, 374 insertions(+)

diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
index b9fe608c279..3aae1813352 100644
--- a/drivers/phy/qcom/Kconfig
+++ b/drivers/phy/qcom/Kconfig
@@ -27,6 +27,14 @@ config PHY_QCOM_USB_SNPS_FEMTO_V2
  High-Speed PHY driver. This driver supports the Hi-Speed PHY which
  is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
  
+config PHY_QCOM_SNPS_EUSB2

+   tristate "Qualcomm Synopsys eUSB2 High-Speed PHY"
+   depends on PHY && ARCH_SNAPDRAGON
+   help
+ Enable this to support the Qualcomm Synopsys DesignWare eUSB2
+ High-Speed PHY driver. This driver supports the Hi-Speed PHY which
+ is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
+
  config PHY_QCOM_USB_HS_28NM
tristate "Qualcomm 28nm High-Speed PHY"
depends on PHY && ARCH_SNAPDRAGON
diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
index 5f4db4a5378..a5153061dfb 100644
--- a/drivers/phy/qcom/Makefile
+++ b/drivers/phy/qcom/Makefile
@@ -2,5 +2,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
  obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
  obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
  obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o
+obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
  obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
  obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
diff --git a/drivers/phy/qcom/phy-qcom-snps-eusb2.c 
b/drivers/phy/qcom/phy-qcom-snps-eusb2.c
new file mode 100644
index 000..853b88458b7
--- /dev/null
+++ b/drivers/phy/qcom/phy-qcom-snps-eusb2.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023-2024, Linaro Limited
+ *
+ * Based on the Linux phy-qcom-snps-eusb2.c driver
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define USB_PHY_UTMI_CTRL0 (0x3c)
+#define SLEEPM BIT(0)
+#define OPMODE_MASKGENMASK(4, 3)
+#define OPMODE_NONDRIVING  BIT(3)
+
+#define USB_PHY_UTMI_CTRL5 (0x50)
+#define PORBIT(1)
+
+#define USB_PHY_HS_PHY_CTRL_COMMON0(0x54)
+#define PHY_ENABLE BIT(0)
+#define SIDDQ_SEL  BIT(1)
+#define SIDDQ  BIT(2)
+#define RETENABLEN BIT(3)
+#define FSEL_MASK  GENMASK(6, 4)
+#define FSEL_19_2_MHZ_VAL  (0x0)
+#define FSEL_38_4_MHZ_VAL  (0x4)
+
+#define USB_PHY_CFG_CTRL_1 (0x58)
+#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK  GENMASK(7, 1)
+
+#define USB_PHY_CFG_CTRL_2 (0x5c)
+#define PHY_CFG_PLL_FB_DIV_7_0_MASKGENMASK(7, 0)
+#define DIV_7_0_19_2_MHZ_VAL   (0x90)
+#define DIV_7_0_38_4_MHZ_VAL   (0xc8)
+
+#define USB_PHY_CFG_CTRL_3 (0x60)
+#define PHY_CFG_PLL_FB_DIV_11_8_MASK   GENMASK(3, 0)
+#define DIV_11_8_19_2_MHZ_VAL  (0x1)
+#define DIV_11_8_38_4_MHZ_VAL  (0x0)
+
+#define PHY_CFG_PLL_REF_DIVGENMASK(7, 4)
+#define PLL_REF_DIV_VAL(0x0)
+
+#define USB_PHY_HS_PHY_CTRL2   (0x64)
+#define VBUSVLDEXT0BIT(0)
+#define USB2_SUSPEND_N BIT(2)
+#define USB2_SUSPEND_N_SEL BIT(3)
+#define VBUS_DET_EXT_SEL   BIT(4)
+
+#define USB_PHY_CFG_CTRL_4 (0x68)
+#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0)
+#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2)
+
+#define USB_PHY_CFG_CTRL_5 (0x6c)
+#define PHY_CFG_PLL_PROP_CNTRL_MASKGENMASK(4, 0)
+#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6)
+
+#define USB_PHY_CFG_CTRL_6 (0x70)
+#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0)
+
+#define USB_PHY_CFG_CTRL_7 (0x74)
+
+#define USB_PHY_CFG_CTRL_8 (0x78)
+#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0)
+#define PHY_CFG_TX_FSLS_VREG_BYPASSBIT(2)
+#define PHY_CFG_TX_HS_VREF_TUNE_MASK   GENMASK(5, 3)
+#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6)
+
+#define USB_PHY_CFG_CTRL_9 (0x7c)
+#define PHY_CFG_TX_PREEMP_TUNE_MASKGENMASK(2, 0)
+#define PHY_CFG_TX_RES_TUNE_MASK   GENMASK(4, 3)
+#define PHY_CFG_TX_RISE_TUNE_MASK  GENMASK(6, 5)
+#define PHY_CFG_RCAL_BYPASSBIT(7)
+
+#define USB_PHY_CFG_CTRL_10(0x80)
+
+#define USB_PHY_CFG0   (0x94)
+#define DATAPATH_CTRL_OVERRIDE_EN  BIT(0)
+#define CMN_C

Re: [RFC PATCH 01/15] DO-NOT-MERGE: dts: upstream: src: Necessary pulls from upstream dts

[Sumit Garg]

On Fri, 5 Apr 2024 at 11:17, Jayesh Choudhary  wrote:
>
> Hello Sumit,
>
> On 05/04/24 10:27, Sumit Garg wrote:
> > Hi Jayesh,
> >
> > On Thu, 4 Apr 2024 at 14:30, Jayesh Choudhary  wrote:
> >>
> >> j722s dts support that needs to be pulled from devicetree-rebasing
> >> tree. The whole series depends on this support.
> >>
> >
> > Which devicetree-rebasing tag does this patch depend upon? v6.8-dts
> > has already made its way to U-Boot mainline [1].
> >
> > [1] 
> > https://source.denx.de/u-boot/u-boot/-/commit/bc39e06778168a34bb4e0a34fbee4edbde4414d8
> >
>
> These patches are on top of the next branch (same commit)
> The required patches[0][2][3] are in tag v6.9-rc1-dts.
>

Okay, the next sync is expected to happen when U-Boot next branch
opens again and I suppose during that time frame only Linux kernel
v6.9 will be released. If you are targeting the U-Boot July release
then you have to opt out of OF_UPSTREAM.

-Sumit

> [0]:
> 
> [2]:
> 
> [3]:
> 
>
> -Jayesh
>
>
> > -Sumit
> >
> >> Signed-off-by: Jayesh Choudhary 
> >> ---
> >>   dts/upstream/Bindings/arm/ti/k3.yaml   |   6 +
> >>   dts/upstream/src/arm64/ti/k3-j722s-evm.dts | 383 +
> >>   dts/upstream/src/arm64/ti/k3-j722s.dtsi|  89 +
> >>   dts/upstream/src/arm64/ti/k3-pinctrl.h |   3 +
> >>   4 files changed, 481 insertions(+)
> >>   create mode 100644 dts/upstream/src/arm64/ti/k3-j722s-evm.dts
> >>   create mode 100644 dts/upstream/src/arm64/ti/k3-j722s.dtsi
> >>
> >> diff --git a/dts/upstream/Bindings/arm/ti/k3.yaml 
> >> b/dts/upstream/Bindings/arm/ti/k3.yaml
> >> index c6506bccfe..d526723484 100644
> >> --- a/dts/upstream/Bindings/arm/ti/k3.yaml
> >> +++ b/dts/upstream/Bindings/arm/ti/k3.yaml
> >> @@ -123,6 +123,12 @@ properties:
> >> - ti,j721s2-evm
> >> - const: ti,j721s2
> >>
> >> +  - description: K3 J722S SoC and Boards
> >> +items:
> >> +  - enum:
> >> +  - ti,j722s-evm
> >> +  - const: ti,j722s
> >> +
> >> - description: K3 J784s4 SoC
> >>   items:
> >> - enum:
>
> [...]

[PATCH v3 6/6] board: add support for Schneider HMIBSC board

[Sumit Garg]

Support for Schneider Electric HMIBSC. Features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI

Features enabled in U-Boot:
- RAUC updates
- Environment protection
- USB based ethernet adaptors

Signed-off-by: Sumit Garg 
---
 arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++
 board/schneider/hmibsc/MAINTAINERS|   6 +
 configs/hmibsc_defconfig  |  86 
 doc/board/index.rst   |   1 +
 doc/board/schneider/hmibsc.rst|  45 ++
 doc/board/schneider/index.rst |   9 +
 include/configs/hmibsc.h  |  57 +++
 7 files changed, 695 insertions(+)
 create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts
 create mode 100644 board/schneider/hmibsc/MAINTAINERS
 create mode 100644 configs/hmibsc_defconfig
 create mode 100644 doc/board/schneider/hmibsc.rst
 create mode 100644 doc/board/schneider/index.rst
 create mode 100644 include/configs/hmibsc.h

diff --git a/arch/arm/dts/apq8016-schneider-hmibsc.dts 
b/arch/arm/dts/apq8016-schneider-hmibsc.dts
new file mode 100644
index 000..75c6137e5a1
--- /dev/null
+++ b/arch/arm/dts/apq8016-schneider-hmibsc.dts
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   model = "Schneider Electric HMIBSC Board";
+   compatible = "schneider,apq8016-hmibsc", "qcom,apq8016";
+
+   aliases {
+   i2c1 = &blsp_i2c6;
+   i2c3 = &blsp_i2c4;
+   i2c4 = &blsp_i2c3;
+   mmc0 = &sdhc_1; /* eMMC */
+   mmc1 = &sdhc_2; /* SD card */
+   serial0 = &blsp_uart1;
+   serial1 = &blsp_uart2;
+   spi0 = &blsp_spi5;
+   usid0 = &pm8916_0;
+   };
+
+   chosen {
+   stdout-path = "serial0";
+   };
+
+   hdmi-out {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con: endpoint {
+   remote-endpoint = <&adv7533_out>;
+   };
+   };
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   autorepeat;
+   pinctrl-0 = <&msm_key_volp_n_default>;
+   pinctrl-names = "default";
+
+   button {
+   label = "Volume Up";
+   linux,code = ;
+   gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-0 = <&pm8916_mpps_leds>;
+   pinctrl-names = "default";
+
+   led-1 {
+   function = LED_FUNCTION_WLAN;
+   color = ;
+   gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "phy0tx";
+   default-state = "off";
+   };
+
+   led-2 {
+   function = LED_FUNCTION_BLUETOOTH;
+   color = ;
+   gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "bluetooth-power";
+   default-state = "off";
+   };
+   };
+
+   memory@8000 {
+   reg = <0 0x8000 0 0x4000>;
+   };
+
+   reserved-memory {
+   ramoops@bff0 {
+   compatible = "ramoops";
+   reg = <0x0 0xbff0 0x0 0x10>;
+   record-size = <0x2>;
+   console-size = <0x2>;
+   ftrace-size = <0x2>;
+   ecc-size = <16>;
+   };
+   };
+
+   usb-hub {
+   compatible = "smsc,usb3503";
+   reset-gpios = <&pm8916_gpios 1 GPIO_ACTIVE_LOW>;
+   initial-mode = <1>;
+   };
+
+   usb_id: usb-id {
+   compatible = "linux,extcon-usb-gpio";
+   id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
+   pinctrl-0 = <&usb_id_default>;
+   pinctrl-names = "default";
+   };
+};
+
+&blsp_i2c3 {
+   status = "okay";
+
+   eeprom@50 {
+   compatible = "atmel,24c32";
+   reg = <0x50>;
+   };
+};
+
+&blsp_i2c4 {
+   status = "okay";
+
+   adv_bridge: bridge@39 {
+   compatible = "adi,adv7533";
+   reg = <0x39>;
+   interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+
+   adi,dsi-lanes = <4>;
+   clocks = <&rpmcc RPM_SMD_BB_CLK2>;
+   

[PATCH v3 5/6] pinctrl: qcom: apq8016: Add GPIO pinctrl function

[Sumit Garg]

Add GPIO pinctrl function to enable driving GPIO pins as output low or
high.

Signed-off-by: Sumit Garg 
---
 drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c 
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 1ee8b7db1a2..b14a8921af4 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
 };
 
 static const struct pinctrl_function msm_pinctrl_functions[] = {
+   {"gpio", 0},
{"blsp_uart1", 2},
{"blsp_uart2", 2},
 };
-- 
2.34.1

[PATCH v3 4/6] pinctrl: qcom: Add support for driving GPIO pins output

[Sumit Garg]

Add support for driving the GPIO pins as output low or high.

Signed-off-by: Sumit Garg 
---
 drivers/pinctrl/qcom/pinctrl-qcom.c | 25 -
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c 
b/drivers/pinctrl/qcom/pinctrl-qcom.c
index 909e566acf5..e68971b37ff 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -29,15 +29,24 @@ struct msm_pinctrl_priv {
 #define GPIO_CONFIG_REG(priv, x) \
(qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
 
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
-#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
-#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_DISABLE BIT(9)
+#define GPIO_IN_OUT_REG(priv, x) \
+   (GPIO_CONFIG_REG(priv, x) + 0x4)
+
+#define TLMM_GPIO_PULL_MASKGENMASK(1, 0)
+#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
+#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
+#define TLMM_GPIO_OUTPUT_MASK  BIT(1)
+#define TLMM_GPIO_OE_MASK  BIT(9)
+
+/* GPIO register shifts. */
+#define GPIO_OUT_SHIFT 1
 
 static const struct pinconf_param msm_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
+   { "output-high", PIN_CONFIG_OUTPUT, 1, },
+   { "output-low", PIN_CONFIG_OUTPUT, 0, },
 };
 
 static int msm_get_functions_count(struct udevice *dev)
@@ -90,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int 
pin_selector,
return 0;
 
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
-   TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
+   TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2);
return 0;
 }
 
@@ -117,6 +126,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned 
int pin_selector,
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, 
pin_selector),
TLMM_GPIO_PULL_MASK, argument);
break;
+   case PIN_CONFIG_OUTPUT:
+   writel(argument << GPIO_OUT_SHIFT,
+  priv->base + GPIO_IN_OUT_REG(priv, pin_selector));
+   setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
+TLMM_GPIO_OE_MASK);
+   break;
default:
return 0;
}
-- 
2.34.1

[PATCH v3 3/6] serial_msm: Enable RS232 flow control

[Sumit Garg]

SE HMIBSC board debug console requires RS232 flow control, so enable
corresponding support if RS232 gpios are present.

Reviewed-by: Caleb Connolly 
Signed-off-by: Sumit Garg 
---
 drivers/serial/serial_msm.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 4de10e75191..3142ecf7362 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -53,10 +53,11 @@
 #define UARTDM_TF   0x100 /* UART Transmit FIFO register */
 #define UARTDM_RF   0x140 /* UART Receive FIFO register */
 
-#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
-#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
-#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
-#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define MSM_BOOT_UART_DM_8_N_1_MODE0x34
+#define MSM_BOOT_UART_DM_CMD_RESET_RX  0x10
+#define MSM_BOOT_UART_DM_CMD_RESET_TX  0x20
+#define MSM_UART_MR1_RX_RDY_CTLBIT(7)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -182,7 +183,9 @@ static void uart_dm_init(struct msm_serial_data *priv)
mdelay(5);
 
writel(priv->clk_bit_rate, priv->base + UARTDM_CSR);
-   writel(0x0, priv->base + UARTDM_MR1);
+
+   /* Enable RS232 flow control to support RS232 db9 connector */
+   writel(MSM_UART_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1);
writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
-- 
2.34.1

[PATCH v3 2/6] apq8016: Add support for UART1 clocks and pinmux

[Sumit Garg]

SE HMIBSC board uses UART1 as the main debug console, so add
corresponding clocks and pinmux support. Along with that update
instructions to enable clocks for debug UART support.

Signed-off-by: Sumit Garg 
---
 drivers/clk/qcom/clock-apq8016.c   | 38 ++
 drivers/pinctrl/qcom/pinctrl-apq8016.c |  1 +
 drivers/serial/serial_msm.c| 11 ++--
 3 files changed, 35 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index 5a5868169c8..9556b94774a 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -31,7 +31,8 @@
 #define BLSP1_AHB_CBCR 0x1008
 
 /* Uart clock control registers */
-#define BLSP1_UART2_BCR(0x3028)
+#define BLSP1_UART1_APPS_CBCR  (0x203C)
+#define BLSP1_UART1_APPS_CMD_RCGR  (0x2044)
 #define BLSP1_UART2_APPS_CBCR  (0x302C)
 #define BLSP1_UART2_APPS_CMD_RCGR  (0x3034)
 
@@ -52,7 +53,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
 };
 
 /* SDHCI */
-static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
+static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
 {
int div = 15; /* 100MHz default */
 
@@ -70,20 +71,35 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int 
slot, uint rate)
 }
 
 /* UART: 115200 */
-int apq8016_clk_init_uart(phys_addr_t base)
+int apq8016_clk_init_uart(phys_addr_t base, unsigned long id)
 {
+   u32 cmd_rcgr, apps_cbcr;
+
+   switch (id) {
+   case GCC_BLSP1_UART1_APPS_CLK:
+   cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR;
+   apps_cbcr = BLSP1_UART1_APPS_CBCR;
+   break;
+   case GCC_BLSP1_UART2_APPS_CLK:
+   cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR;
+   apps_cbcr = BLSP1_UART2_APPS_CBCR;
+   break;
+   default:
+   return 0;
+   }
+
/* Enable AHB clock */
clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk);
 
/* 7372800 uart block clock @ GPLL0 */
-   clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625,
-CFG_CLK_SRC_GPLL0, 16);
+   clk_rcg_set_rate_mnd(base, cmd_rcgr, 1, 144, 15625, CFG_CLK_SRC_GPLL0,
+16);
 
/* Vote for gpll0 clock */
clk_enable_gpll0(base, &gpll0_vote_clk);
 
/* Enable core clk */
-   clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR);
+   clk_enable_cbc(base + apps_cbcr);
 
return 0;
 }
@@ -94,14 +110,12 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong 
rate)
 
switch (clk->id) {
case GCC_SDCC1_APPS_CLK: /* SDC1 */
-   return clk_init_sdc(priv, 0, rate);
-   break;
+   return apq8016_clk_init_sdc(priv, 0, rate);
case GCC_SDCC2_APPS_CLK: /* SDC2 */
-   return clk_init_sdc(priv, 1, rate);
-   break;
+   return apq8016_clk_init_sdc(priv, 1, rate);
+   case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */
case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
-   return apq8016_clk_init_uart(priv->base);
-   break;
+   return apq8016_clk_init_uart(priv->base, clk->id);
default:
return 0;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c 
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index a9a00f4b081..1ee8b7db1a2 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
 };
 
 static const struct pinctrl_function msm_pinctrl_functions[] = {
+   {"blsp_uart1", 2},
{"blsp_uart2", 2},
 };
 
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index ac4280c6c4c..4de10e75191 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -248,12 +248,17 @@ static struct msm_serial_data init_serial_data = {
 #include 
 
 /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 
*/
-//int apq8016_clk_init_uart(phys_addr_t gcc_base);
+//int apq8016_clk_init_uart(phys_addr_t gcc_base, unsigned long id);
 
 static inline void _debug_uart_init(void)
 {
-   /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on 
MSM8916 */
-   //apq8016_clk_init_uart(0x180);
+   /*
+* Uncomment to turn on UART clocks when debugging U-Boot as aboot
+* on MSM8916. Supported debug UART clock IDs:
+*   - db410c: GCC_BLSP1_UART2_APPS_CLK
+*   - HMIBSC: GCC_BLSP1_UART1_APPS_CLK
+*/
+   //apq8016_clk_init_uart(0x180, );
uart_dm_init(&init_serial_data);
 }
 
-- 
2.34.1

[PATCH v3 1/6] qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default

[Sumit Garg]

Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow
ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is
loaded as a first stage bootloader. It leads to secondary CPUs bringup
failure and later causing the Linux kernel to freeze.

So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's
actually required.

Fixes: 059d526af312 ("mach-snapdragon: generalise board support")
Reviewed-by: Caleb Connolly 
Signed-off-by: Sumit Garg 
---
 arch/arm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4cdf08dd695..08ae7e51a6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1088,7 +1088,7 @@ config ARCH_SNAPDRAGON
select BOARD_LATE_INIT
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR
-   select LINUX_KERNEL_IMAGE_HEADER
+   select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
imply CMD_DM
 
 config ARCH_SOCFPGA
-- 
2.34.1

[PATCH v3 0/6] Add SE HMBSC board support

[Sumit Garg]

SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major
difference from db410c is serial port where HMIBSC board uses UART1 as
the debug console with an RS232 port, patch #2 - #5 adds corresponding
driver support.

Patch #6 adds main HMIBSC board specific bits, features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI

Features enabled in U-Boot:
- RAUC updates (refer [2] for more details)
- Environment protection
- USB based ethernet adaptors

Feedback is very much welcome.

Changes in v3:
- Rebased on top of qcom-next [1].
- Collected some review tags.
- Incorporated misc. comments from Caleb and Stephen.
- Split patch#4 as requested.
- Linux HMIBSC board DTS has already been reviewed here [3], I have
  incorporated that for U-Boot too.

Changes in v2:
- Rebased on top on qcom-next [1].
- Added patch#1 as a fix for generic qcom board support.
- Added patch#4 to enable driving GPIO pins based on pinctrl
  configuration. This replaces the custom GPIO configuration.
- Added proper DTS file for HMIBSC board based on Linux DT pattern.
- Merged board support patches into a single patch#5.

[1] 
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-next?ref_type=heads
[2] https://rauc.readthedocs.io/en/latest/
[3] 
https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.g...@linaro.org/

Sumit Garg (6):
  qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default
  apq8016: Add support for UART1 clocks and pinmux
  serial_msm: Enable RS232 flow control
  pinctrl: qcom: Add support for driving GPIO pins output
  pinctrl: qcom: apq8016: Add GPIO pinctrl function
  board: add support for Schneider HMIBSC board

 arch/arm/Kconfig  |   2 +-
 arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++
 board/schneider/hmibsc/MAINTAINERS|   6 +
 configs/hmibsc_defconfig  |  86 
 doc/board/index.rst   |   1 +
 doc/board/schneider/hmibsc.rst|  45 ++
 doc/board/schneider/index.rst |   9 +
 drivers/clk/qcom/clock-apq8016.c  |  38 +-
 drivers/pinctrl/qcom/pinctrl-apq8016.c|   2 +
 drivers/pinctrl/qcom/pinctrl-qcom.c   |  25 +-
 drivers/serial/serial_msm.c   |  24 +-
 include/configs/hmibsc.h  |  57 +++
 12 files changed, 760 insertions(+), 26 deletions(-)
 create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts
 create mode 100644 board/schneider/hmibsc/MAINTAINERS
 create mode 100644 configs/hmibsc_defconfig
 create mode 100644 doc/board/schneider/hmibsc.rst
 create mode 100644 doc/board/schneider/index.rst
 create mode 100644 include/configs/hmibsc.h

-- 
2.34.1

Re: [RFC PATCH v2 2/2] board: ad401: example of fastboot oem board realization

[Mattijs Korpershoek]

Hi Alexey,

On lun., mars 04, 2024 at 14:03, Alexey Romanov  
wrote:

> Hello Mattijs,
>
> On Thu, Feb 15, 2024 at 10:24:11AM +0100, Mattijs Korpershoek wrote:
>> On jeu., f'evr. 01, 2024 at 12:20, Alexey Romanov 
>>  wrote:
>> 
>> > An example of how we use fastboot oeam board subcommand
>> > for Sean Anderson.
>> >
>> > 1 - OEM_BOARD_WRITE_BOOTLOADER_CMD:
>> >
>> > We use it for custom Amlogic bootloader + tpl
>> > flashing protocol.
>> >
>> > 2 - OEM_BOARD_ERASE_CMD:
>> >
>> > Custom logic for erasing the env-emulated partition,
>> > which isn't in the mtd markup map.
>> >
>> > Example of the script which completely flashes the device:
>> >
>> >   $ fastboot erase bootloader
>> >   $ fastboot stage u-boot.bin
>> >   $ fastboot oem board:write_bootloader
>> >   $ fastboot reboot-bootloader
>> >   $ fastboot oem board:erase_env
>> >   $ fastboot erase misc
>> >   $ fastboot erase super
>> >   $ fastboot flash super rootfs
>> >   $ fastboot reboot
>> >
>> > Signed-off-by: Alexey Romanov 
>> > ---
>> >  board/amlogic/ad401/fastboot.c | 222 +
>> >  1 file changed, 222 insertions(+)
>> >  create mode 100644 board/amlogic/ad401/fastboot.c
>> >
>> > diff --git a/board/amlogic/ad401/fastboot.c 
>> > b/board/amlogic/ad401/fastboot.c
>> > new file mode 100644
>> > index 00..01da8efa5b
>> > --- /dev/null
>> > +++ b/board/amlogic/ad401/fastboot.c
>> > @@ -0,0 +1,222 @@
>> > +// SPDX-License-Identifier: GPL-2.0+
>> > +/*
>> > + * (C) Copyright 2023 SaluteDevices, Inc.
>> > + */
>> > +
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +#include 
>> > +
>> > +enum {
>> > +  OEM_BOARD_ERASE_CMD,
>> > +  OEM_BOARD_WRITE_BOOTLOADER_CMD,
>> > +};
>> > +
>> > +struct defenv {
>> > +  char *name;
>> > +  char value[256];
>> > +};
>> > +
>> > +static void save_defenv(struct defenv *e, size_t cnt)
>> > +{
>> > +  int i;
>> > +
>> > +  for (i = 0; i < cnt; i++) {
>> > +  const char *env_val = env_get(e[i].name);
>> > +
>> > +  if (env_val)
>> > +  strlcpy(e[i].value, env_val, sizeof(e[i].value));
>> > +  else
>> > +  e[i].value[0] = '\0';
>> > +  }
>> > +}
>> > +
>> > +static void set_defenv(struct defenv *e, size_t cnt)
>> > +{
>> > +  int i;
>> > +
>> > +  for (i = 0; i < cnt; i++)
>> > +  env_set(e[i].name, e[i].value);
>> > +}
>> > +
>> > +static int fastboot_erase_env(void)
>> > +{
>> > +  char *const defenv_names[] = { "lock", "mtdparts", "mtdids" };
>> > +  struct defenv env[ARRAY_SIZE(defenv_names)];
>> > +  int err, i;
>> > +
>> > +  for (i = 0; i < ARRAY_SIZE(env); i++)
>> > +  env[i].name = defenv_names[i];
>> > +
>> > +  printf("ENV is being erased...\n");
>> > +
>> > +  /*
>> > +   * Reset environment to the default, excluding 'lock' variable,
>> > +   * because it reflects the fastboot's state after execution of
>> > +   * 'flashing unlock' command, hence it must survive the env-erasing.
>> > +   * Otherwise, further erase commands will fail on check_lock().
>> > +   *
>> > +   * Also, we have to save 'mtdparts' and 'mtdids' variables
>> > +   * because they are necessary to obtain partition map.
>> > +   */
>> > +
>> > +  save_defenv(env, ARRAY_SIZE(env));
>> > +  env_set_default(NULL, 0);
>> > +  set_defenv(env, ARRAY_SIZE(env));
>> > +
>> > +  err = env_save();
>> > +  if (err) {
>> > +  pr_err("Can't overwrite ENV-partition\n");
>> > +  return err;
>> > +  }
>> 
>> Hmm so the fastboot locked state is saved in the U-Boot environment.
>> There is probably a good reason for this (no secure storage for
>> example). But this does not feel board specific.
>> 
>> Wouldn't it be better if we could just run "fastboot erase bootenv" and
>> that the generic fastboot code does the right thing?
>
> Are you proposing to modify the code of fastboot in such a way
> that if user send 'erase bootenv' string, then we call generic
> function to cleanup environment, instead of try to search (and erase)
> in partition schema 'bootenv' partition?

I would have liked to have a generic "erase bootenv" command yes, but
your solution seems fine so no need to do something different.

Thank you for your patience with this !

>
>> (which is env default, and ignoring some magic/specific variables)
>> 
>> > +
>> > +  return 0;
>> > +}
>> > +
>> > +static int fastboot_nand_write_tpl(struct mtd_info *mtd, void *buffer,
>> > + u32 offset, size_t size, int flags)
>> > +{
>> > +  int boot_cpy_num = meson_bootloader_copy_num(BOOT_TPL);
>> > +  u64 size_per_copy = meson_bootloader_copy_size(mtd, BOOT_TPL);
>> > +  int i;
>> > +
>> > +  for (i = 0; i < boot_cpy_num; i++) {
>> > +  size_t retlen, len = size;
>> > +  int ret;
>> > +
>> > +  ret = nand_write_skip_bad(mtd, offset + (i * size_per_copy),
>> > +&len, &retlen, offset + size_per_copy,
>> > +   

Re: [RFC PATCH v2 1/2] fastboot: introduce 'oem board' subcommand

[Mattijs Korpershoek]

Hi Alexey,

On lun., mars 04, 2024 at 14:11, Alexey Romanov  
wrote:

> Hello,
>
> On Thu, Feb 15, 2024 at 10:14:13AM +0100, Mattijs Korpershoek wrote:
>> Hi Alexey,
>> 
>> Thank you for the patch.
>> 
>> On jeu., f'evr. 01, 2024 at 12:20, Alexey Romanov 
>>  wrote:
>> 
>> > Currently, fastboot protocol in U-Boot has no opportunity
>> > to execute vendor custom code with verifed boot. This patch
>> > introduce new fastboot subcommand fastboot oem board:,
>> > which allow to run custom oem_board function.
>> >
>> > Default implementation is __weak. Vendor must redefine it in
>> > board/ folder with his own logic.
>> >
>> > For example, some vendors have their custom nand/emmc partition
>> > flashing or erasing. Here some typical command for such use cases:
>> >
>> > - flashing:
>> >
>> >   $ fastboot stage bootloader.img
>> >   $ fastboot oem board:write_bootloader
>> >
>> > - erasing:
>> >
>> >   $ fastboot oem board:erase_env
>> >
>> > Signed-off-by: Alexey Romanov 
>> 
>> Sorry for the delay. I needed time to give this some thoughts and I
>> waited for Sean to chime as well on this.
>> 
>> I've heard from Neil that this might be related to:
>> https://github.com/superna/pyamlboot/pull/20
>
> Yeah, pyamlboot also uses the same 'bootloader' partition flashing
> scheme as I present in the patch 2. This is custom Amlogic protocol.
>
>> 
>> I think this can be useful. Not necessarily for writing custom
>> partitions, but I see this could be used for other things:
>> 
>> 1. Provision SoC-specific fuses (serialno/mac addr) at the factory line
>>(for production devices)
>>Examples:
>>$ fastboot oem board:write_serialno ABCDEF
>>$ fastboot oem board:write_macaddr AA:BB:CC:DD:EE
>> 
>> 2. Access secure storage (via an Trusted Application)
>
> Agree, you are completely right.
>
>> 
>> But both examples could also be in a fastboot flash format:
>> $ fastboot flash serialno ABCDEF
>
> But this case requires to 'serialno' partition definition in schema?
> I didn't fully understand you.

I meant more in a "conceptual way". (from a end user perspective)

"fastboot flash" is generic command that's just supposed to write data
somewhere.

The back-end (partitioning etc) depends on the storage the device uses
so that's a "implementation detail".

In any case, I don't have a proper alternative to what you are proposing
so as send in [1], I'm okay picking this up after some minor review
comments are addressed.

[1] https://lore.kernel.org/all/87jzlcfang@baylibre.com/

>
>> 
>> One concern I have is that U-Boot forks might use this command as
>> an excuse to not makes things generic.
>> 
>> I hope that others will chime in on this as well.
>> I'd like to discuss this more because once this command is in we cannot
>> remove it later.
>> 
>> > ---
>> >  drivers/fastboot/Kconfig  |  7 +++
>> >  drivers/fastboot/fb_command.c | 15 +++
>> >  include/fastboot.h|  1 +
>> >  3 files changed, 23 insertions(+)
>> >
>> > diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
>> > index a4313d60a9..4d94391a76 100644
>> > --- a/drivers/fastboot/Kconfig
>> > +++ b/drivers/fastboot/Kconfig
>> > @@ -241,6 +241,13 @@ config FASTBOOT_OEM_RUN
>> >  this feature if you are using verified boot, as it will allow an
>> >  attacker to bypass any restrictions you have in place.
>> >  
>> > +config FASTBOOT_OEM_BOARD
>> > +  bool "Enable the 'oem board' command"
>> > +  help
>> > +This extends the fastboot protocol with an "oem board" command. This
>> > +command allows running vendor custom code defined in board/ files.
>> > +Otherwise, it will do nothing and send fastboot fail.
>> 
>> If we move forward with this, please also document the new command in:
>> doc/android/fastboot.rst
>> 
>> > +
>> >  endif # FASTBOOT
>> >  
>> >  endmenu
>> > diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
>> > index 5fcadcdf50..2298815770 100644
>> > --- a/drivers/fastboot/fb_command.c
>> > +++ b/drivers/fastboot/fb_command.c
>> > @@ -40,6 +40,7 @@ static void reboot_recovery(char *, char *);
>> >  static void oem_format(char *, char *);
>> >  static void oem_partconf(char *, char *);
>> >  static void oem_bootbus(char *, char *);
>> > +static void oem_board(char *, char *);
>> >  static void run_ucmd(char *, char *);
>> >  static void run_acmd(char *, char *);
>> >  
>> > @@ -107,6 +108,10 @@ static const struct {
>> >.command = "oem run",
>> >.dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_RUN, (run_ucmd), 
>> > (NULL))
>> >},
>> > +  [FASTBOOT_COMMAND_OEM_BOARD] = {
>> > +  .command = "oem board",
>> > +  .dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_BOARD, (oem_board), 
>> > (NULL))
>> > +  },
>> >[FASTBOOT_COMMAND_UCMD] = {
>> >.command = "UCmd",
>> >.dispatch = CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT, (run_ucmd), 
>> > (NULL))
>> > @@ -490,3 +495,13 @@ static void __maybe_unused oem_bootbus(

Re: [RFC PATCH v2 1/2] fastboot: introduce 'oem board' subcommand

[Mattijs Korpershoek]

Hi Alexey,

On mer., avril 03, 2024 at 08:49, Alexey Romanov  
wrote:

> Hello Mattijs,
> is there any feedback?

Sorry for the late reply. I was both swamped with other work and awaiting.
feedback from others.

I don't have strong enough arguments to state that this is not useful to
others, I have re-considered this and I'm willing to pick it up.

Please rebase, as this no longer applies.

Also see some review comments below

>
> On Thu, Feb 15, 2024 at 10:14:13AM +0100, Mattijs Korpershoek wrote:
>> Hi Alexey,
>> 
>> Thank you for the patch.
>> 
>> On jeu., f'evr. 01, 2024 at 12:20, Alexey Romanov 
>>  wrote:
>> 
>> > Currently, fastboot protocol in U-Boot has no opportunity
>> > to execute vendor custom code with verifed boot. This patch
>> > introduce new fastboot subcommand fastboot oem board:,
>> > which allow to run custom oem_board function.
>> >
>> > Default implementation is __weak. Vendor must redefine it in
>> > board/ folder with his own logic.
>> >
>> > For example, some vendors have their custom nand/emmc partition
>> > flashing or erasing. Here some typical command for such use cases:
>> >
>> > - flashing:
>> >
>> >   $ fastboot stage bootloader.img
>> >   $ fastboot oem board:write_bootloader
>> >
>> > - erasing:
>> >
>> >   $ fastboot oem board:erase_env
>> >
>> > Signed-off-by: Alexey Romanov 
>> 
>> Sorry for the delay. I needed time to give this some thoughts and I
>> waited for Sean to chime as well on this.
>> 
>> I've heard from Neil that this might be related to:
>> https://github.com/superna/pyamlboot/pull/20
>> 
>> I think this can be useful. Not necessarily for writing custom
>> partitions, but I see this could be used for other things:
>> 
>> 1. Provision SoC-specific fuses (serialno/mac addr) at the factory line
>>(for production devices)
>>Examples:
>>$ fastboot oem board:write_serialno ABCDEF
>>$ fastboot oem board:write_macaddr AA:BB:CC:DD:EE
>> 
>> 2. Access secure storage (via an Trusted Application)
>> 
>> But both examples could also be in a fastboot flash format:
>> $ fastboot flash serialno ABCDEF
>> 
>> One concern I have is that U-Boot forks might use this command as
>> an excuse to not makes things generic.
>> 
>> I hope that others will chime in on this as well.
>> I'd like to discuss this more because once this command is in we cannot
>> remove it later.
>> 
>> > ---
>> >  drivers/fastboot/Kconfig  |  7 +++
>> >  drivers/fastboot/fb_command.c | 15 +++
>> >  include/fastboot.h|  1 +
>> >  3 files changed, 23 insertions(+)
>> >
>> > diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
>> > index a4313d60a9..4d94391a76 100644
>> > --- a/drivers/fastboot/Kconfig
>> > +++ b/drivers/fastboot/Kconfig
>> > @@ -241,6 +241,13 @@ config FASTBOOT_OEM_RUN
>> >  this feature if you are using verified boot, as it will allow an
>> >  attacker to bypass any restrictions you have in place.
>> >  
>> > +config FASTBOOT_OEM_BOARD
>> > +  bool "Enable the 'oem board' command"
>> > +  help
>> > +This extends the fastboot protocol with an "oem board" command. This
>> > +command allows running vendor custom code defined in board/ files.
>> > +Otherwise, it will do nothing and send fastboot fail.
>> 
>> If we move forward with this, please also document the new command in:
>> doc/android/fastboot.rst

This still applies, document the command please.

>> 
>> > +
>> >  endif # FASTBOOT
>> >  
>> >  endmenu
>> > diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
>> > index 5fcadcdf50..2298815770 100644
>> > --- a/drivers/fastboot/fb_command.c
>> > +++ b/drivers/fastboot/fb_command.c
>> > @@ -40,6 +40,7 @@ static void reboot_recovery(char *, char *);
>> >  static void oem_format(char *, char *);
>> >  static void oem_partconf(char *, char *);
>> >  static void oem_bootbus(char *, char *);
>> > +static void oem_board(char *, char *);
>> >  static void run_ucmd(char *, char *);
>> >  static void run_acmd(char *, char *);
>> >  
>> > @@ -107,6 +108,10 @@ static const struct {
>> >.command = "oem run",
>> >.dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_RUN, (run_ucmd), 
>> > (NULL))
>> >},
>> > +  [FASTBOOT_COMMAND_OEM_BOARD] = {
>> > +  .command = "oem board",
>> > +  .dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_BOARD, (oem_board), 
>> > (NULL))
>> > +  },
>> >[FASTBOOT_COMMAND_UCMD] = {
>> >.command = "UCmd",
>> >.dispatch = CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT, (run_ucmd), 
>> > (NULL))
>> > @@ -490,3 +495,13 @@ static void __maybe_unused oem_bootbus(char 
>> > *cmd_parameter, char *response)
>> >else
>> >fastboot_okay(NULL, response);
>> >  }
>> > +
>> > +void __weak fastboot_oem_board(char *cmd_parameter, void *data, u32 size, 
>> > char *response)
>> > +{
>> > +  fastboot_fail("oem board function not defined", response);
>> > +}
>> > +
>> > +static void __maybe_unused oem_board(char *cmd_parameter, ch

[PATCH] ARM: uniphier: Move uniphier_mem_map_init() call into dram_init()

[Kunihiko Hayashi]

The function uniphier_mem_map_init() is to change global variable
'mem_map', which is referenced to get_page_table_size() to calculate
the size of page table.

However, uniphier_mem_map_init() is called after get_page_table_size(),
so the size of page table and 'mem_map' become inconsist each other.
After all, U-Boot fails to boot on chip with memory map different from
default map,

uniphier_mem_map_init() should be moved to dram_init(), which is
called before get_page_table_size().

Signed-off-by: Kunihiko Hayashi 
---
 arch/arm/mach-uniphier/dram_init.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram_init.c 
b/arch/arm/mach-uniphier/dram_init.c
index 7f2753190c23..e6f1286e71fd 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -265,14 +265,15 @@ int dram_init(void)
if (uniphier_get_soc_id() == UNIPHIER_LD20_ID)
gd->ram_size -= 64;
 
+   /* map all the DRAM regions */
+   uniphier_mem_map_init(gd->ram_base, prev_top - gd->ram_base);
+
return 0;
 }
 
 int dram_init_banksize(void)
 {
struct uniphier_dram_map dram_map[3] = {};
-   unsigned long base, top;
-   bool valid_bank_found = false;
int ret, i;
 
ret = uniphier_dram_map_get(dram_map);
@@ -287,18 +288,7 @@ int dram_init_banksize(void)
 
if (!dram_map[i].size)
continue;
-
-   if (!valid_bank_found)
-   base = dram_map[i].base;
-   top = dram_map[i].base + dram_map[i].size;
-   valid_bank_found = true;
}
 
-   if (!valid_bank_found)
-   return -EINVAL;
-
-   /* map all the DRAM regions */
-   uniphier_mem_map_init(base, top - base);
-
return 0;
 }
-- 
2.25.1

[PATCH 2/2] qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver

[Neil Armstrong]

Enable the Qualcomm Synopsys eUSB2 PHY driver in Qualcomm defconfig.

Signed-off-by: Neil Armstrong 
---
 configs/qcom_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 1abb57345ff..b0ae5eb4df3 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -63,6 +63,7 @@ CONFIG_RGMII=y
 CONFIG_PHY=y
 CONFIG_PHY_QCOM_QUSB2=y
 CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
+CONFIG_PHY_QCOM_SNPS_EUSB2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_QCOM_QCS404=y
 CONFIG_PINCTRL_QCOM_SDM845=y

-- 
2.34.1

[PATCH 1/2] phy: qcom: add Synopsys eUSB2 PHY driver

[Neil Armstrong]

Add a driver for the new Synopsys eUSB2 PHY found in the SM8550
and SM8650 SoCs.

Signed-off-by: Neil Armstrong 
---
 drivers/phy/qcom/Kconfig   |   8 +
 drivers/phy/qcom/Makefile  |   1 +
 drivers/phy/qcom/phy-qcom-snps-eusb2.c | 365 +
 3 files changed, 374 insertions(+)

diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
index b9fe608c279..3aae1813352 100644
--- a/drivers/phy/qcom/Kconfig
+++ b/drivers/phy/qcom/Kconfig
@@ -27,6 +27,14 @@ config PHY_QCOM_USB_SNPS_FEMTO_V2
  High-Speed PHY driver. This driver supports the Hi-Speed PHY which
  is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
 
+config PHY_QCOM_SNPS_EUSB2
+   tristate "Qualcomm Synopsys eUSB2 High-Speed PHY"
+   depends on PHY && ARCH_SNAPDRAGON
+   help
+ Enable this to support the Qualcomm Synopsys DesignWare eUSB2
+ High-Speed PHY driver. This driver supports the Hi-Speed PHY which
+ is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
+
 config PHY_QCOM_USB_HS_28NM
tristate "Qualcomm 28nm High-Speed PHY"
depends on PHY && ARCH_SNAPDRAGON
diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
index 5f4db4a5378..a5153061dfb 100644
--- a/drivers/phy/qcom/Makefile
+++ b/drivers/phy/qcom/Makefile
@@ -2,5 +2,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
 obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
 obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
 obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o
+obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
 obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
 obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
diff --git a/drivers/phy/qcom/phy-qcom-snps-eusb2.c 
b/drivers/phy/qcom/phy-qcom-snps-eusb2.c
new file mode 100644
index 000..853b88458b7
--- /dev/null
+++ b/drivers/phy/qcom/phy-qcom-snps-eusb2.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023-2024, Linaro Limited
+ *
+ * Based on the Linux phy-qcom-snps-eusb2.c driver
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define USB_PHY_UTMI_CTRL0 (0x3c)
+#define SLEEPM BIT(0)
+#define OPMODE_MASKGENMASK(4, 3)
+#define OPMODE_NONDRIVING  BIT(3)
+
+#define USB_PHY_UTMI_CTRL5 (0x50)
+#define PORBIT(1)
+
+#define USB_PHY_HS_PHY_CTRL_COMMON0(0x54)
+#define PHY_ENABLE BIT(0)
+#define SIDDQ_SEL  BIT(1)
+#define SIDDQ  BIT(2)
+#define RETENABLEN BIT(3)
+#define FSEL_MASK  GENMASK(6, 4)
+#define FSEL_19_2_MHZ_VAL  (0x0)
+#define FSEL_38_4_MHZ_VAL  (0x4)
+
+#define USB_PHY_CFG_CTRL_1 (0x58)
+#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK  GENMASK(7, 1)
+
+#define USB_PHY_CFG_CTRL_2 (0x5c)
+#define PHY_CFG_PLL_FB_DIV_7_0_MASKGENMASK(7, 0)
+#define DIV_7_0_19_2_MHZ_VAL   (0x90)
+#define DIV_7_0_38_4_MHZ_VAL   (0xc8)
+
+#define USB_PHY_CFG_CTRL_3 (0x60)
+#define PHY_CFG_PLL_FB_DIV_11_8_MASK   GENMASK(3, 0)
+#define DIV_11_8_19_2_MHZ_VAL  (0x1)
+#define DIV_11_8_38_4_MHZ_VAL  (0x0)
+
+#define PHY_CFG_PLL_REF_DIVGENMASK(7, 4)
+#define PLL_REF_DIV_VAL(0x0)
+
+#define USB_PHY_HS_PHY_CTRL2   (0x64)
+#define VBUSVLDEXT0BIT(0)
+#define USB2_SUSPEND_N BIT(2)
+#define USB2_SUSPEND_N_SEL BIT(3)
+#define VBUS_DET_EXT_SEL   BIT(4)
+
+#define USB_PHY_CFG_CTRL_4 (0x68)
+#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0)
+#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2)
+
+#define USB_PHY_CFG_CTRL_5 (0x6c)
+#define PHY_CFG_PLL_PROP_CNTRL_MASKGENMASK(4, 0)
+#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6)
+
+#define USB_PHY_CFG_CTRL_6 (0x70)
+#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0)
+
+#define USB_PHY_CFG_CTRL_7 (0x74)
+
+#define USB_PHY_CFG_CTRL_8 (0x78)
+#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0)
+#define PHY_CFG_TX_FSLS_VREG_BYPASSBIT(2)
+#define PHY_CFG_TX_HS_VREF_TUNE_MASK   GENMASK(5, 3)
+#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6)
+
+#define USB_PHY_CFG_CTRL_9 (0x7c)
+#define PHY_CFG_TX_PREEMP_TUNE_MASKGENMASK(2, 0)
+#define PHY_CFG_TX_RES_TUNE_MASK   GENMASK(4, 3)
+#define PHY_CFG_TX_RISE_TUNE_MASK  GENMASK(6, 5)
+#define PHY_CFG_RCAL_BYPASSBIT(7)
+
+#define USB_PHY_CFG_CTRL_10(0x80)
+
+#define USB_PHY_CFG0   (0x94)
+#define DATAPATH_CTRL_OVERRIDE_EN  BIT(0)
+#define CMN_CTRL_OVERRIDE_EN   BIT(1)
+
+#define UTMI_PHY_CMN_

[PATCH 0/2] phy: qcom: add support for the Qualcomm Synopsys eUSB2 PHY

[Neil Armstrong]

Add support for the new Qualcomm Synopsys eUSB2 PHY found in the
SM8550 and SM8650 SoCs.

Finally enable the driver in the Qualcomm defconfig.

Signed-off-by: Neil Armstrong 
---
Neil Armstrong (2):
  phy: qcom: add Synopsys eUSB2 PHY driver
  qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver

 configs/qcom_defconfig |   1 +
 drivers/phy/qcom/Kconfig   |   8 +
 drivers/phy/qcom/Makefile  |   1 +
 drivers/phy/qcom/phy-qcom-snps-eusb2.c | 365 +
 4 files changed, 375 insertions(+)
---
base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb
change-id: 20240404-topic-sm8x50-usb-phy-d09a98f72d1b

Best regards,
-- 
Neil Armstrong 

Re: [PATCH v5 4/5] net: ti: icssg: Add ICSSG ethernet driver

[Ravi Gunasekaran]

On 4/4/24 12:38 PM, MD Danish Anwar wrote:
> This is the PRUSS Ethernet driver for TI AM654 SR2.0 and later SoCs with
> the ICSSG PRU Sub-system running EMAC firmware. ICSSG Subsystem supports
> two slices per instance. This driver caters to both slices / ports of
> the icssg subsystem.
> 
> Since it is not possible for Ethernet driver to register more than one
> port for a given instance, this patch introduces top level PRUETH as
> UCLASS_MISC and binds UCLASS_ETH to individual ports in order to support
> bringing up more than one Ethernet interface in U-Boot.
> 
> Since top level driver is UCLASS_MISC, board files would need to
> instantiate the driver explicitly.
> 
> Signed-off-by: MD Danish Anwar 
> ---
>  arch/arm/mach-k3/common.c |  11 +
>  drivers/net/ti/Kconfig|  13 +
>  drivers/net/ti/Makefile   |   1 +
>  drivers/net/ti/icssg_prueth.c | 685 ++
>  drivers/net/ti/icssg_prueth.h |   3 +
>  5 files changed, 713 insertions(+)
>  create mode 100644 drivers/net/ti/icssg_prueth.c
> 

Reviewed-by: Ravi Gunasekaran 

-- 
Regards,
Ravi

u-boot@lists.denx.de

[Ilias Apalodimas]

On Fri, 5 Apr 2024 at 10:12, Heinrich Schuchardt
 wrote:
>
> On 4/4/24 08:35, Ilias Apalodimas wrote:
> > A symbol defined in a linker script (e.g. __efi_runtime_start = .;) is
> > only a symbol, not a variable and should not be dereferenced.
> > The common practice is either define it as
> > extern uint32_t __efi_runtime_start or
> > extern char __efi_runtime_start[] and access it as
> > &__efi_runtime_start or __efi_runtime_start respectively.
> >
> > So let's access it properly since we define it as an array
>
> Thanks for investigating this.
>
> Beyond this patch I guess we should eliminate these duplicate defintions:
>
> include/asm-generic/sections.h:38:extern char __efi_runtime_start[],
> __efi_runtime_stop[];
> include/efi_loader.h:348:extern char __efi_runtime_start[],
> __efi_runtime_stop[];

Yes, you've already sent a patch on this, thanks

>
> >
> > Signed-off-by: Ilias Apalodimas 
> > ---
> >   lib/efi_loader/efi_memory.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
> > index edfad2d95a1d..98f104390c8d 100644
> > --- a/lib/efi_loader/efi_memory.c
> > +++ b/lib/efi_loader/efi_memory.c
> > @@ -933,8 +933,8 @@ static void add_u_boot_and_runtime(void)
> >* Add Runtime Services. We mark surrounding boottime code as runtime 
> > as
> >* well to fulfill the runtime alignment constraints but avoid 
> > padding.
> >*/
> > - runtime_start = (ulong)&__efi_runtime_start & ~runtime_mask;
> > - runtime_end = (ulong)&__efi_runtime_stop;
> > + runtime_start = (ulong)__efi_runtime_start & ~runtime_mask;
>
> Using (uintptr_t) would make it clearer that we are converting from a
> pointer to an integer type.
>

Sure, I would prefer this to be on a followup with a commit message of
its own, but I am fine with amending it, if you merge this

Thanks
/Ilias
> Best regards
>
> Heinrich
>
> > + runtime_end = (ulong)__efi_runtime_stop;
> >   runtime_end = (runtime_end + runtime_mask) & ~runtime_mask;
> >   runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
> >   efi_add_memory_map_pg(runtime_start, runtime_pages,
>

Re: [PATCH v5 2/5] net: ti: icssg: Add Firmware config and classification APIs.

[Ravi Gunasekaran]

On 4/4/24 12:38 PM, MD Danish Anwar wrote:
> Add icssg_config.h / .c and icssg_classifier.c files. These are firmware
> configuration and classification related files. Add MII helper APIs and
> MACROs. These APIs and MACROs will be later used by ICSSG Ethernet driver.
> Also introduce icssg_prueth.h which has definition of prueth related
> structures.
> 
> Signed-off-by: MD Danish Anwar 
> ---
>  drivers/net/ti/icss_mii_rt.h  | 192 ++
>  drivers/net/ti/icssg_classifier.c | 376 +++
>  drivers/net/ti/icssg_config.c | 406 ++
>  drivers/net/ti/icssg_config.h | 177 +
>  drivers/net/ti/icssg_prueth.h |  83 ++
>  5 files changed, 1234 insertions(+)
>  create mode 100644 drivers/net/ti/icss_mii_rt.h
>  create mode 100644 drivers/net/ti/icssg_classifier.c
>  create mode 100644 drivers/net/ti/icssg_config.c
>  create mode 100644 drivers/net/ti/icssg_config.h
>  create mode 100644 drivers/net/ti/icssg_prueth.h
> 

Reviewed-by: Ravi Gunasekaran 

-- 
Regards,
Ravi

[PATCH 3/3] button: qcom-pmic: add support for pmk8350 button configs

[Neil Armstrong]

Finally add the entries for the qcom,pmk8350-pwrkey and qcom,pmk8350-resin
found on PMICs used with SM8350 and later SoCs.

Signed-off-by: Neil Armstrong 
---
 drivers/button/button-qcom-pmic.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/button/button-qcom-pmic.c 
b/drivers/button/button-qcom-pmic.c
index f6da958097c..6153601017b 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -36,6 +36,8 @@ struct qcom_pmic_btn_priv {
 #define PON_INT_RT_STS0x10
 #define  PON_KPDPWR_N_SET  0
 #define  PON_RESIN_N_SET   1
+#define  PON_GEN3_RESIN_N_SET  6
+#define  PON_GEN3_KPDPWR_N_SET 7
 
 static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
 {
@@ -69,6 +71,18 @@ static const struct qcom_pmic_btn_data 
qcom_pmic_btn_data_table[] = {
.code = KEY_DOWN,
.label = "vol_down",
},
+   {
+   .compatible = "qcom,pmk8350-pwrkey",
+   .status_bit = PON_GEN3_KPDPWR_N_SET,
+   .code = KEY_ENTER,
+   .label = "pwrkey",
+   },
+   {
+   .compatible = "qcom,pmk8350-resin",
+   .status_bit = PON_GEN3_RESIN_N_SET,
+   .code = KEY_DOWN,
+   .label = "vol_down",
+   },
 };
 
 static const struct qcom_pmic_btn_data *button_qcom_pmic_match(ofnode node)

-- 
2.34.1

[PATCH 2/3] button: qcom-pmic: move node name checks to btn_data struct

[Neil Armstrong]

Move node name checks to a proper data struct with all information
for the supported subnodes.

Replace the key offset defines with the Linux driver ones.

Signed-off-by: Neil Armstrong 
---
 drivers/button/button-qcom-pmic.c | 84 ++-
 1 file changed, 56 insertions(+), 28 deletions(-)

diff --git a/drivers/button/button-qcom-pmic.c 
b/drivers/button/button-qcom-pmic.c
index bad445efa86..f6da958097c 100644
--- a/drivers/button/button-qcom-pmic.c
+++ b/drivers/button/button-qcom-pmic.c
@@ -19,6 +19,13 @@
 #define REG_TYPE   0x4
 #define REG_SUBTYPE0x5
 
+struct qcom_pmic_btn_data {
+   char *compatible;
+   unsigned int status_bit;
+   int code;
+   char *label;
+};
+
 struct qcom_pmic_btn_priv {
u32 base;
u32 status_bit;
@@ -27,11 +34,8 @@ struct qcom_pmic_btn_priv {
 };
 
 #define PON_INT_RT_STS0x10
-#define KPDPWR_ON_INT_BIT 0
-#define RESIN_ON_INT_BIT  1
-
-#define NODE_IS_PWRKEY(node) (!strncmp(ofnode_get_name(node), "pwrkey", 
strlen("pwrkey")))
-#define NODE_IS_RESIN(node) (!strncmp(ofnode_get_name(node), "resin", 
strlen("resin")))
+#define  PON_KPDPWR_N_SET  0
+#define  PON_RESIN_N_SET   1
 
 static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
 {
@@ -52,10 +56,39 @@ static int qcom_pwrkey_get_code(struct udevice *dev)
return priv->code;
 }
 
+static const struct qcom_pmic_btn_data qcom_pmic_btn_data_table[] = {
+   {
+   .compatible = "qcom,pm8941-pwrkey",
+   .status_bit = PON_KPDPWR_N_SET,
+   .code = KEY_ENTER,
+   .label = "pwrkey",
+   },
+   {
+   .compatible = "qcom,pm8941-resin",
+   .status_bit = PON_RESIN_N_SET,
+   .code = KEY_DOWN,
+   .label = "vol_down",
+   },
+};
+
+static const struct qcom_pmic_btn_data *button_qcom_pmic_match(ofnode node)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(qcom_pmic_btn_data_table); ++i) {
+   if (ofnode_device_is_compatible(node,
+   
qcom_pmic_btn_data_table[i].compatible))
+   return &qcom_pmic_btn_data_table[i];
+   }
+
+   return NULL;
+}
+
 static int qcom_pwrkey_probe(struct udevice *dev)
 {
struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
+   const struct qcom_pmic_btn_data *btn_data;
ofnode node = dev_ofnode(dev);
int ret;
u64 base;
@@ -64,6 +97,14 @@ static int qcom_pwrkey_probe(struct udevice *dev)
if (!uc_plat->label)
return 0;
 
+   /* Get the data for the node compatible */
+   btn_data = button_qcom_pmic_match(node);
+   if (!btn_data)
+   return -EINVAL;
+
+   priv->status_bit = btn_data->status_bit;
+   priv->code = btn_data->code;
+
/* the pwrkey and resin nodes are children of the "pon" node, get the
 * PMIC device to use in pmic_reg_* calls.
 */
@@ -87,23 +128,10 @@ static int qcom_pwrkey_probe(struct udevice *dev)
 
ret = pmic_reg_read(priv->pmic, priv->base + REG_SUBTYPE);
if (ret < 0 || (ret & 0x7) == 0) {
-   printf("%s: unexpected PMCI function subtype %d\n", dev->name, 
ret);
+   printf("%s: unexpected PMIC function subtype %d\n", dev->name, 
ret);
return -ENXIO;
}
 
-   if (NODE_IS_PWRKEY(node)) {
-   priv->status_bit = 0;
-   priv->code = KEY_ENTER;
-   } else if (NODE_IS_RESIN(node)) {
-   priv->status_bit = 1;
-   priv->code = KEY_DOWN;
-   } else {
-   /* Should not get here! */
-   printf("Invalid pon node '%s' should be 'pwrkey' or 'resin'\n",
-  ofnode_get_name(node));
-   return -EINVAL;
-   }
-
return 0;
 }
 
@@ -114,12 +142,20 @@ static int button_qcom_pmic_bind(struct udevice *parent)
int ret;
 
dev_for_each_subnode(node, parent) {
+   const struct qcom_pmic_btn_data *btn_data;
struct button_uc_plat *uc_plat;
const char *label;
 
if (!ofnode_is_enabled(node))
continue;
 
+   /* Get the data for the node compatible */
+   btn_data = button_qcom_pmic_match(node);
+   if (!btn_data) {
+   debug("Unknown button node '%s'\n", 
ofnode_get_name(node));
+   continue;
+   }
+
ret = device_bind_driver_to_node(parent, "qcom_pwrkey",
 ofnode_get_name(node),
 node, &dev);
@@ -128,15 +164,7 @@ static int button_qcom_pmic_bind(struct udevice *parent)

[PATCH 1/3] gpio: qcom_pmic_gpio: add support for pm8550-gpio

[Neil Armstrong]

Add support for PM8550 GPIO controller variant, keep read-only
until the GPIO and Pinctrl setup is fixed for new PMICs.

Signed-off-by: Neil Armstrong 
---
 drivers/gpio/qcom_pmic_gpio.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 14a8210522b..dfb70faf94b 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -35,6 +35,8 @@
 #define REG_SUBTYPE_GPIOC_8CH  0xd
 #define REG_SUBTYPE_GPIO_LV0x10
 #define REG_SUBTYPE_GPIO_MV0x11
+#define REG_SUBTYPE_GPIO_LV_VIN2  0x12
+#define REG_SUBTYPE_GPIO_MV_VIN3  0x13
 
 #define REG_STATUS 0x08
 #define REG_STATUS_VAL_MASK0x1
@@ -322,9 +324,20 @@ static int qcom_gpio_probe(struct udevice *dev)
return log_msg_ret("bad type", -ENXIO);
 
val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
-   if (val != REG_SUBTYPE_GPIO_4CH && val != REG_SUBTYPE_GPIOC_4CH &&
-   val != REG_SUBTYPE_GPIO_LV && val != REG_SUBTYPE_GPIO_MV)
+   switch (val) {
+   case REG_SUBTYPE_GPIO_4CH:
+   case REG_SUBTYPE_GPIOC_4CH:
+   plat->lv_mv_type = false;
+   break;
+   case REG_SUBTYPE_GPIO_LV:
+   case REG_SUBTYPE_GPIO_MV:
+   case REG_SUBTYPE_GPIO_LV_VIN2:
+   case REG_SUBTYPE_GPIO_MV_VIN3:
+   plat->lv_mv_type = true;
+   break;
+   default:
return log_msg_ret("bad subtype", -ENXIO);
+   }
 
plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV ||
   val == REG_SUBTYPE_GPIO_MV;
@@ -351,6 +364,7 @@ static const struct udevice_id qcom_gpio_ids[] = {
{ .compatible = "qcom,pm8994-gpio" },   /* 22 GPIO's */
{ .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ .compatible = "qcom,pms405-gpio" },
+   { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ }
 };
 

-- 
2.34.1

[PATCH 0/3] qcom: support SPMI buttons on SM8550 and SM8650

[Neil Armstrong]

First add PMIC gpio variant on pm8550-gpio, then rework the
qcom-pmic button driver to support data structs for each PMIC
variant and finally add the data for the pmk8350 button configs.

Signed-off-by: Neil Armstrong 
---
Neil Armstrong (3):
  gpio: qcom_pmic_gpio: add support for pm8550-gpio
  button: qcom-pmic: move node name checks to btn_data struct
  button: qcom-pmic: add support for pmk8350 button configs

 drivers/button/button-qcom-pmic.c | 98 ---
 drivers/gpio/qcom_pmic_gpio.c | 18 ++-
 2 files changed, 86 insertions(+), 30 deletions(-)
---
base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb
change-id: 20240404-topic-sm8x50-spmi-clients-d9a085aae979

Best regards,
-- 
Neil Armstrong 

Re: [PATCH 1/1] efi_loader: eliminate duplicate runtime section definitions

[Ilias Apalodimas]

On Fri, 5 Apr 2024 at 11:13, Heinrich Schuchardt
 wrote:
>
> The following symbols are defined in two includes:
>
> * __efi_runtime_start[]
> * __efi_runtime_stop[]
> * __efi_runtime_rel_start[]
> * __efi_runtime_rel_stop[]
>
> Eliminate the definitions in efi_loader.h.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  include/efi_loader.h| 3 ---
>  lib/efi_loader/efi_memory.c | 1 +
>  2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/include/efi_loader.h b/include/efi_loader.h
> index 7daca0afba..bb51c02817 100644
> --- a/include/efi_loader.h
> +++ b/include/efi_loader.h
> @@ -345,9 +345,6 @@ extern const efi_guid_t smbios3_guid;
>  extern const efi_guid_t efi_guid_text_input_protocol;
>  extern const efi_guid_t efi_guid_text_output_protocol;
>
> -extern char __efi_runtime_start[], __efi_runtime_stop[];
> -extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
> -
>  /**
>   * struct efi_open_protocol_info_item - open protocol info item
>   *
> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
> index edfad2d95a..81f5f98a8a 100644
> --- a/lib/efi_loader/efi_memory.c
> +++ b/lib/efi_loader/efi_memory.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>
> --
> 2.43.0
>

Reviewed-by: Ilias Apalodimas 

[PATCH 4/4] spmi: msm: support controller version 7

[Neil Armstrong]

Add the defines and support for SPMI arbiters version 7,
which can handle up to 1024 peripherals, and can also drive
a secondary bus which is not implemented yet.

Signed-off-by: Neil Armstrong 
---
 drivers/spmi/spmi-msm.c | 33 +
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 46e2e09dc26..244de69b359 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -23,13 +23,17 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PMIC_ARB_VERSION_V2_MIN 0x2001
 #define PMIC_ARB_VERSION_V3_MIN 0x3000
 #define PMIC_ARB_VERSION_V5_MIN 0x5000
+#define PMIC_ARB_VERSION_V7_MIN0x7000
 
 #define APID_MAP_OFFSET_V1_V2_V3 (0x800)
 #define APID_MAP_OFFSET_V5 (0x900)
+#define APID_MAP_OFFSET_V7 (0x2000)
 #define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
 #define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
 #define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
+#define SPMI_V7_OBS_CH_OFFSET(chnl) ((chnl) * 0x20)
 #define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x1)
+#define SPMI_V7_RW_CH_OFFSET(chnl) ((chnl) * 0x1000)
 
 #define SPMI_OWNERSHIP_PERIPH2OWNER(x) ((x) & 0x7)
 
@@ -52,6 +56,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define SPMI_MAX_CHANNELS 128
 #define SPMI_MAX_CHANNELS_V5   512
+#define SPMI_MAX_CHANNELS_V7   1024
 #define SPMI_MAX_SLAVES 16
 #define SPMI_MAX_PERIPH 256
 
@@ -62,7 +67,8 @@ enum arb_ver {
V1 = 1,
V2,
V3,
-   V5 = 5
+   V5 = 5,
+   V7 = 7
 };
 
 /*
@@ -133,6 +139,12 @@ static int msm_spmi_write(struct udevice *dev, int usid, 
int pid, int off,
case V5:
ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
 
+   reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off);
+   break;
+
+   case V7:
+   ch_offset = SPMI_V7_RW_CH_OFFSET(channel);
+
reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off);
break;
}
@@ -196,6 +208,13 @@ static int msm_spmi_read(struct udevice *dev, int usid, 
int pid, int off)
case V5:
ch_offset = SPMI_V5_OBS_CH_OFFSET(channel);
 
+   /* Prepare read command */
+   reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off);
+   break;
+
+   case V7:
+   ch_offset = SPMI_V7_OBS_CH_OFFSET(channel);
+
/* Prepare read command */
reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off);
break;
@@ -250,10 +269,16 @@ static int msm_spmi_probe(struct udevice *dev)
priv->arb_ver = V3;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
priv->max_channels = SPMI_MAX_CHANNELS;
-   } else {
+   } else if (hw_ver < PMIC_ARB_VERSION_V7_MIN) {
priv->arb_ver = V5;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V5;
-   priv->max_channels = SPMI_MAX_CHANNELS_V5;
+   priv->max_channels = SPMI_MAX_CHANNELS;
+   priv->spmi_cnfg = dev_read_addr_name(dev, "cnfg");
+   } else {
+   /* TOFIX: handle second bus */
+   priv->arb_ver = V7;
+   priv->arb_chnl = core_addr + APID_MAP_OFFSET_V7;
+   priv->max_channels = SPMI_MAX_CHANNELS_V7;
priv->spmi_cnfg = dev_read_addr_name(dev, "cnfg");
}
 
@@ -276,7 +301,7 @@ static int msm_spmi_probe(struct udevice *dev)
priv->channel_map[slave_id][pid] = i;
 
/* Mark channels read-only when from different owner */
-   if (priv->arb_ver == V5) {
+   if (priv->arb_ver == V5 || priv->arb_ver == V7) {
uint32_t cnfg = readl(priv->spmi_cnfg + 
ARB_CHANNEL_OFFSET(i));
uint8_t owner = SPMI_OWNERSHIP_PERIPH2OWNER(cnfg);
 

-- 
2.34.1

[PATCH 3/4] spmi: msm: handle peripheral ownership

[Neil Armstrong]

The cnfg registers provides the owner id for each peripheral,
so we can use this id to check if we're allowed to write register
to each peripherals.

Since the v5 can handle more peripherals, add the max_channels to
scan more starting from version 5, make the channel_map store
32bit values and introduce the SPMI_CHANNEL_READ_ONLY flag to
mark a peripheral as read-only.

Signed-off-by: Neil Armstrong 
---
 drivers/spmi/spmi-msm.c | 33 +
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 68bb8a38c3c..46e2e09dc26 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -31,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
 #define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x1)
 
+#define SPMI_OWNERSHIP_PERIPH2OWNER(x) ((x) & 0x7)
+
 #define SPMI_REG_CMD0 0x0
 #define SPMI_REG_CONFIG 0x4
 #define SPMI_REG_STATUS 0x8
@@ -49,9 +51,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPMI_STATUS_DONE 0x1
 
 #define SPMI_MAX_CHANNELS 128
+#define SPMI_MAX_CHANNELS_V5   512
 #define SPMI_MAX_SLAVES 16
 #define SPMI_MAX_PERIPH 256
 
+#define SPMI_CHANNEL_READ_ONLY BIT(31)
+#define SPMI_CHANNEL_MASK  0x
+
 enum arb_ver {
V1 = 1,
V2,
@@ -72,8 +78,11 @@ struct msm_spmi_priv {
phys_addr_t arb_chnl;  /* ARB channel mapping base */
phys_addr_t spmi_chnls; /* SPMI channels */
phys_addr_t spmi_obs;  /* SPMI observer */
+   phys_addr_t spmi_cnfg;  /* SPMI config */
+   u32 owner;  /* Current owner */
+   unsigned int max_channels; /* Max channels */
/* SPMI channel map */
-   uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+   uint32_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
/* SPMI bus arbiter version */
u32 arb_ver;
 };
@@ -100,8 +109,10 @@ static int msm_spmi_write(struct udevice *dev, int usid, 
int pid, int off,
return -EIO;
if (pid >= SPMI_MAX_PERIPH)
return -EIO;
+   if (priv->channel_map[usid][pid] & SPMI_CHANNEL_READ_ONLY)
+   return -EPERM;
 
-   channel = priv->channel_map[usid][pid];
+   channel = priv->channel_map[usid][pid] & SPMI_CHANNEL_MASK;
 
dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
 
@@ -162,7 +173,7 @@ static int msm_spmi_read(struct udevice *dev, int usid, int 
pid, int off)
if (pid >= SPMI_MAX_PERIPH)
return -EIO;
 
-   channel = priv->channel_map[usid][pid];
+   channel = priv->channel_map[usid][pid] & SPMI_CHANNEL_MASK;
 
dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
 
@@ -227,18 +238,23 @@ static int msm_spmi_probe(struct udevice *dev)
core_addr = dev_read_addr_name(dev, "core");
priv->spmi_chnls = dev_read_addr_name(dev, "chnls");
priv->spmi_obs = dev_read_addr_name(dev, "obsrvr");
+   dev_read_u32(dev, "qcom,ee", &priv->owner);
 
hw_ver = readl(core_addr + PMIC_ARB_VERSION);
 
if (hw_ver < PMIC_ARB_VERSION_V3_MIN) {
priv->arb_ver = V2;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
+   priv->max_channels = SPMI_MAX_CHANNELS;
} else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) {
priv->arb_ver = V3;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
+   priv->max_channels = SPMI_MAX_CHANNELS;
} else {
priv->arb_ver = V5;
priv->arb_chnl = core_addr + APID_MAP_OFFSET_V5;
+   priv->max_channels = SPMI_MAX_CHANNELS_V5;
+   priv->spmi_cnfg = dev_read_addr_name(dev, "cnfg");
}
 
dev_dbg(dev, "PMIC Arb Version-%d (%#x)\n", hw_ver >> 28, hw_ver);
@@ -252,12 +268,21 @@ static int msm_spmi_probe(struct udevice *dev)
dev_dbg(dev, "priv->spmi_chnls address (%#08llx)\n", priv->spmi_chnls);
dev_dbg(dev, "priv->spmi_obs address (%#08llx)\n", priv->spmi_obs);
/* Scan peripherals connected to each SPMI channel */
-   for (i = 0; i < SPMI_MAX_PERIPH; i++) {
+   for (i = 0; i < priv->max_channels; i++) {
uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
uint8_t slave_id = (periph & 0xf) >> 16;
uint8_t pid = (periph & 0xff00) >> 8;
 
priv->channel_map[slave_id][pid] = i;
+
+   /* Mark channels read-only when from different owner */
+   if (priv->arb_ver == V5) {
+   uint32_t cnfg = readl(priv->spmi_cnfg + 
ARB_CHANNEL_OFFSET(i));
+   uint8_t owner = SPMI_OWNERSHIP_PERIPH2OWNER(cnfg);
+
+   if (owner != priv->owner)
+   priv->channel_map[slave_id][pid] |= 
SPMI_CHANNEL_READ_ONLY;
+   }
}
return 0;
 }

-- 
2.34.1

[PATCH 2/4] spmi: msm: properly format command

[Neil Armstrong]

Since version 2, the cmd format has changed, takes helpers
from Linux driver and use a switch/case to handle all
versions in msm_spmi_write/read() command.

Signed-off-by: Neil Armstrong 
---
 drivers/spmi/spmi-msm.c | 75 -
 1 file changed, 55 insertions(+), 20 deletions(-)

diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 97383d8c7b8..68bb8a38c3c 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -78,6 +78,16 @@ struct msm_spmi_priv {
u32 arb_ver;
 };
 
+static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u8 pid, u8 off)
+{
+   return (opc << 27) | (sid << 20) | (pid << 12) | (off << 4) | 1;
+}
+
+static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 off)
+{
+   return (opc << 27) | (off << 4) | 1;
+}
+
 static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
  uint8_t val)
 {
@@ -93,24 +103,35 @@ static int msm_spmi_write(struct udevice *dev, int usid, 
int pid, int off,
 
channel = priv->channel_map[usid][pid];
 
-   if (priv->arb_ver == V5)
-   ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
-   else
+   dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
+
+   switch (priv->arb_ver) {
+   case V1:
+   ch_offset = SPMI_CH_OFFSET(channel);
+
+   reg = pmic_arb_fmt_cmd_v1(SPMI_CMD_EXT_REG_WRITE_LONG,
+ usid, pid, off);
+   break;
+
+   case V2:
ch_offset = SPMI_CH_OFFSET(channel);
 
+   reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off);
+   break;
+
+   case V5:
+   ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+
+   reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_WRITE_LONG, off);
+   break;
+   }
+
/* Disable IRQ mode for the current channel*/
writel(0x0, priv->spmi_chnls + ch_offset + SPMI_REG_CONFIG);
 
/* Write single byte */
writel(val, priv->spmi_chnls + ch_offset + SPMI_REG_WDATA);
 
-   /* Prepare write command */
-   reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
-   reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
-   reg |= (pid << SPMI_CMD_ADDR_SHIFT);
-   reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
-   reg |= 1; /* byte count */
-
/* Send write command */
writel(reg, priv->spmi_chnls + ch_offset + SPMI_REG_CMD0);
 
@@ -143,21 +164,35 @@ static int msm_spmi_read(struct udevice *dev, int usid, 
int pid, int off)
 
channel = priv->channel_map[usid][pid];
 
-   if (priv->arb_ver == V5)
-   ch_offset = SPMI_V5_OBS_CH_OFFSET(channel);
-   else
+   dev_dbg(dev, "[%d:%d] %s: channel %d\n", usid, pid, __func__, channel);
+
+   switch (priv->arb_ver) {
+   case V1:
+   ch_offset = SPMI_CH_OFFSET(channel);
+
+   /* Prepare read command */
+   reg = pmic_arb_fmt_cmd_v1(SPMI_CMD_EXT_REG_READ_LONG,
+ usid, pid, off);
+   break;
+
+   case V2:
ch_offset = SPMI_CH_OFFSET(channel);
 
+   /* Prepare read command */
+   reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off);
+   break;
+
+   case V5:
+   ch_offset = SPMI_V5_OBS_CH_OFFSET(channel);
+
+   /* Prepare read command */
+   reg = pmic_arb_fmt_cmd_v2(SPMI_CMD_EXT_REG_READ_LONG, off);
+   break;
+   }
+
/* Disable IRQ mode for the current channel*/
writel(0x0, priv->spmi_obs + ch_offset + SPMI_REG_CONFIG);
 
-   /* Prepare read command */
-   reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
-   reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
-   reg |= (pid << SPMI_CMD_ADDR_SHIFT);
-   reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
-   reg |= 1; /* byte count */
-
/* Request read */
writel(reg, priv->spmi_obs + ch_offset + SPMI_REG_CMD0);
 

-- 
2.34.1

[PATCH 1/4] spmi: msm: fix version 5 support

[Neil Armstrong]

Properly use ch_offset in msm_spmi_write() reg access.

Fixes: f5a2d6b4b03 ("spmi: msm: add arbiter version 5 support")
Signed-off-by: Neil Armstrong 
---
 drivers/spmi/spmi-msm.c | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 5fe8a70abca..97383d8c7b8 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -93,12 +93,16 @@ static int msm_spmi_write(struct udevice *dev, int usid, 
int pid, int off,
 
channel = priv->channel_map[usid][pid];
 
+   if (priv->arb_ver == V5)
+   ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
+   else
+   ch_offset = SPMI_CH_OFFSET(channel);
+
/* Disable IRQ mode for the current channel*/
-   writel(0x0,
-  priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+   writel(0x0, priv->spmi_chnls + ch_offset + SPMI_REG_CONFIG);
 
/* Write single byte */
-   writel(val, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + 
SPMI_REG_WDATA);
+   writel(val, priv->spmi_chnls + ch_offset + SPMI_REG_WDATA);
 
/* Prepare write command */
reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
@@ -107,18 +111,13 @@ static int msm_spmi_write(struct udevice *dev, int usid, 
int pid, int off,
reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
reg |= 1; /* byte count */
 
-   if (priv->arb_ver == V5)
-   ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
-   else
-   ch_offset = SPMI_CH_OFFSET(channel);
-
/* Send write command */
-   writel(reg, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+   writel(reg, priv->spmi_chnls + ch_offset + SPMI_REG_CMD0);
 
/* Wait till CMD DONE status */
reg = 0;
while (!reg) {
-   reg = readl(priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
+   reg = readl(priv->spmi_chnls + ch_offset +
SPMI_REG_STATUS);
}
 

-- 
2.34.1

[PATCH 0/4] smpi: msm: fix version 5 and add version 7 support

[Neil Armstrong]

First, fix version 5 support by using the right ch_offset in
then msm_spmi_write() reg accesses.

Then:
- properly format command by importing helpers from Linux driver and
  use a switch/case to handle all versions in msm_spmi_write/read() command.
- handle peripheral ownership by poking into the cnfg registers and
  mark periperal as read-only when the owner id doesn't match
- finally add version 7 defines

SPMI Arbiter Version 7 is present on SM8450, SM8550 and SM8650 SoC.

Signed-off-by: Neil Armstrong 
---
Neil Armstrong (4):
  spmi: msm: fix version 5 support
  spmi: msm: properly format command
  spmi: msm: handle peripheral ownership
  spmi: msm: support controller version 7

 drivers/spmi/spmi-msm.c | 148 +---
 1 file changed, 116 insertions(+), 32 deletions(-)
---
base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb
change-id: 20240404-topic-sm8x50-spmi-fixes-aec9b392813b

Best regards,
-- 
Neil Armstrong 

Re: [PATCH 4/4] fastboot: integrate block flashing back-end

[Mattijs Korpershoek]

Hi Dmitrii,

Thank you for the patch and sorry for the review delay.

On mer., mars 06, 2024 at 18:59, Dmitrii Merkurev  wrote:

> 1. Get partition info/size
> 2. Erase partition
> 3. Flash partition
> 4. BCB
>
> Signed-off-by: Dmitrii Merkurev 
> Cc: Alex Kiernan 
> Cc: Patrick Delaunay 
> Cc: Simon Glass 
> Cc: Mattijs Korpershoek 
> Cc: Ying-Chun Liu (PaulLiu) 
> ---
>  drivers/fastboot/fb_command.c |  8 
>  drivers/fastboot/fb_common.c  | 15 +++
>  drivers/fastboot/fb_getvar.c  |  8 +++-
>  3 files changed, 26 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
> index f95f4e4ae1..67ebe02efa 100644
> --- a/drivers/fastboot/fb_command.c
> +++ b/drivers/fastboot/fb_command.c
> @@ -9,6 +9,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -331,6 +332,10 @@ void fastboot_data_complete(char *response)
>   */
>  static void __maybe_unused flash(char *cmd_parameter, char *response)
>  {
> + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_BLOCK))
> + fastboot_block_flash_write(cmd_parameter, fastboot_buf_addr,
> +image_size, response);
> +
>   if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC))
>   fastboot_mmc_flash_write(cmd_parameter, fastboot_buf_addr,
>image_size, response);
> @@ -351,6 +356,9 @@ static void __maybe_unused flash(char *cmd_parameter, 
> char *response)
>   */
>  static void __maybe_unused erase(char *cmd_parameter, char *response)
>  {
> + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_BLOCK))
> + fastboot_block_erase(cmd_parameter, response);
> +
>   if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC))
>   fastboot_mmc_erase(cmd_parameter, response);
>  
> diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
> index 3576b06772..7602653c0b 100644
> --- a/drivers/fastboot/fb_common.c
> +++ b/drivers/fastboot/fb_common.c
> @@ -97,16 +97,23 @@ int __weak fastboot_set_reboot_flag(enum 
> fastboot_reboot_reason reason)
>   [FASTBOOT_REBOOT_REASON_FASTBOOTD] = "boot-fastboot",
>   [FASTBOOT_REBOOT_REASON_RECOVERY] = "boot-recovery"
>   };
> - const int mmc_dev = config_opt_enabled(CONFIG_FASTBOOT_FLASH_MMC,
> -CONFIG_FASTBOOT_FLASH_MMC_DEV, 
> -1);
>  
> - if (!IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC))
> + int device = config_opt_enabled(CONFIG_FASTBOOT_FLASH_BLOCK,
> + CONFIG_FASTBOOT_FLASH_BLOCK_DEVICE_ID, 
> -1);
> + if (device == -1) {
> + device = config_opt_enabled(CONFIG_FASTBOOT_FLASH_MMC,
> + CONFIG_FASTBOOT_FLASH_MMC_DEV, -1);
> + }
> + char *bcb_iface = config_opt_enabled(CONFIG_FASTBOOT_FLASH_BLOCK,

Can this be made const?

With the above addressed:

Reviewed-by: Mattijs Korpershoek 

> +  
> CONFIG_FASTBOOT_FLASH_BLOCK_INTERFACE_NAME, "mmc");
> +
> + if (device == -1)
>   return -EINVAL;
>  
>   if (reason >= FASTBOOT_REBOOT_REASONS_COUNT)
>   return -EINVAL;
>  
> - ret = bcb_find_partition_and_load("mmc", mmc_dev, "misc");
> + ret = bcb_find_partition_and_load(bcb_iface, device, "misc");
>   if (ret)
>   goto out;
>  
> diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
> index f65519c57b..71507009ab 100644
> --- a/drivers/fastboot/fb_getvar.c
> +++ b/drivers/fastboot/fb_getvar.c
> @@ -8,6 +8,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -114,7 +115,12 @@ static int getvar_get_part_info(const char *part_name, 
> char *response,
>   struct disk_partition disk_part;
>   struct part_info *part_info;
>  
> - if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC)) {
> + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_BLOCK)) {
> + r = fastboot_block_get_part_info(part_name, &dev_desc, 
> &disk_part,
> +  response);
> + if (r >= 0 && size)
> + *size = disk_part.size * disk_part.blksz;
> + } else if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC)) {
>   r = fastboot_mmc_get_part_info(part_name, &dev_desc, &disk_part,
>  response);
>   if (r >= 0 && size)
> -- 
> 2.44.0.278.ge034bb2e1d-goog

Re: [PATCH] ARM: stm32: Jump to ep on successful resume in PSCI suspend code

[Patrice CHOTARD]

On 3/31/24 20:21, Marek Vasut wrote:
> In case the system has resumed successfully, the PSCI suspend resume
> code has to jump to the 'ep' successful resume entry point code path,
> otherwise the code has to jump to content of the LR register, which
> points to failed resume code path.
> 
> To implement this distinction, rewrite LR register stored on stack
> with 'ep' value in case of a successful resume, which is really in
> every case unless some catastrophic failure occurred during suspend.
> 
> Without this change, Linux counts every resume as failed in
> /sys/power/suspend_stats/fail
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Patrice Chotard 
> Cc: Patrick Delaunay 
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
>  arch/arm/mach-stm32mp/psci.c | 14 ++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
> index 8cdeb0ab3f2..4f2379df45f 100644
> --- a/arch/arm/mach-stm32mp/psci.c
> +++ b/arch/arm/mach-stm32mp/psci.c
> @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused 
> function_id,
>  {
>   u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr;
>   u32 gicd_addr = stm32mp_get_gicd_base_address();
> + u32 cpu = psci_get_cpu_id();
> + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT);
>   bool iwdg1_wake = false;
>   bool iwdg2_wake = false;
>   bool other_wake = false;
> @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused 
> function_id,
>  
>   writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
>   clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
> +
> + /*
> +  * The system has resumed successfully. Rewrite LR register stored
> +  * on stack with 'ep' value, so that on return from this PSCI call,
> +  * the code would jump to that 'ep' resume entry point code path
> +  * instead of the previous 'lr' register content which (e.g. with
> +  * Linux) points to resume failure code path.
> +  *
> +  * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout
> +  * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on.
> +  */
> + writel(ep, sp - 8);
>  }

Hi Marek

This patch is not based on last next or master branch, psci.c is now located in 
arch/arm/mach-stm32mp/stm32mp1/psci.c 

Nevertheless, you can add my RB on the V2.

Thanks
Patrice

[PATCH 2/3] pinctrl: qcom: Add SM8650 pinctrl driver

[Neil Armstrong]

Add pinctrl driver for the TLMM block found in the SM8650 SoC.

This driver only handles the gpio and qup2_se7 pinmux, and makes sure
the pinconf applies on SDC2 pins.

Signed-off-by: Neil Armstrong 
---
 drivers/pinctrl/qcom/Kconfig  |  7 
 drivers/pinctrl/qcom/Makefile |  1 +
 drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++
 3 files changed, 83 insertions(+)

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index f760bbcdd52..e0196a83e60 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -48,6 +48,13 @@ config PINCTRL_QCOM_SM8550
  Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC,
  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_SM8650
+   bool "Qualcomm SM8650 GCC"
+   select PINCTRL_QCOM
+   help
+ Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC,
+ as well as the associated GPIO driver.
+
 endmenu
 
 endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 970902e28c8..d83e89ef4f0 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
 obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
 obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
 obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o
+obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c 
b/drivers/pinctrl/qcom/pinctrl-sm8650.c
new file mode 100644
index 000..932132fa4a6
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm sm8650 pinctrl
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ *
+ */
+
+#include 
+#include 
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+   {"qup2_se7", 1},
+   {"gpio", 0},
+};
+
+static const char *sm8650_get_function_name(struct udevice *dev,
+unsigned int selector)
+{
+   return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sm8650_get_pin_name(struct udevice *dev,
+   unsigned int selector)
+{
+   static const char *special_pins_names[] = {
+   "ufs_reset",
+   "sdc2_clk",
+   "sdc2_cmd",
+   "sdc2_data",
+   };
+
+   if (selector >= 210 && selector <= 213)
+   snprintf(pin_name, MAX_PIN_NAME_LEN, 
special_pins_names[selector - 210]);
+   else
+   snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+   return pin_name;
+}
+
+static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin,
+   unsigned int selector)
+{
+   return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sm8650_data = {
+   .pin_data = {
+   .pin_count = 214,
+   .special_pins_start = 210,
+   },
+   .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+   .get_function_name = sm8650_get_function_name,
+   .get_function_mux = sm8650_get_function_mux,
+   .get_pin_name = sm8650_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+   { .compatible = "qcom,sm8650-tlmm", .data = (ulong)&sm8650_data },
+   { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sm8650) = {
+   .name   = "pinctrl_sm8650",
+   .id = UCLASS_NOP,
+   .of_match   = msm_pinctrl_ids,
+   .ops= &msm_pinctrl_ops,
+   .bind   = msm_pinctrl_bind,
+};
+

-- 
2.34.1

[PATCH 3/3] qcom_defconfig: enable SM8550 & SM8650 pinctrl driver

[Neil Armstrong]

Enable the SM8550 & SM8650 pinctrl drivers for Qualcomm defconfig.

Signed-off-by: Neil Armstrong 
---
 configs/qcom_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 222db6448ab..a92b6ef7911 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -43,6 +43,8 @@ CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_QCOM_QCS404=y
 CONFIG_PINCTRL_QCOM_SDM845=y
+CONFIG_PINCTRL_QCOM_SM8550=y
+CONFIG_PINCTRL_QCOM_SM8650=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_QCOM=y
 CONFIG_SCSI=y

-- 
2.34.1

[PATCH 1/3] pinctrl: qcom: Add SM8550 pinctrl driver

[Neil Armstrong]

Add pinctrl driver for the TLMM block found in the SM8550 SoC.

This driver only handles the gpio and qup1_se7 pinmux, and makes sure
the pinconf applies on SDC2 pins.

Signed-off-by: Neil Armstrong 
---
 drivers/pinctrl/qcom/Kconfig  |  7 
 drivers/pinctrl/qcom/Makefile |  1 +
 drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +++
 3 files changed, 83 insertions(+)

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 2fe63981478..f760bbcdd52 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -41,6 +41,13 @@ config PINCTRL_QCOM_SDM845
  Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_SM8550
+   bool "Qualcomm SM8550 GCC"
+   select PINCTRL_QCOM
+   help
+ Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC,
+ as well as the associated GPIO driver.
+
 endmenu
 
 endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 6d9aca6d7b7..970902e28c8 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
 obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
 obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
 obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
+obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c 
b/drivers/pinctrl/qcom/pinctrl-sm8550.c
new file mode 100644
index 000..d9a8a652111
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm sm8550 pinctrl
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ *
+ */
+
+#include 
+#include 
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+   {"qup1_se7", 1},
+   {"gpio", 0},
+};
+
+static const char *sm8550_get_function_name(struct udevice *dev,
+unsigned int selector)
+{
+   return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sm8550_get_pin_name(struct udevice *dev,
+   unsigned int selector)
+{
+   static const char *special_pins_names[] = {
+   "ufs_reset",
+   "sdc2_clk",
+   "sdc2_cmd",
+   "sdc2_data",
+   };
+
+   if (selector >= 210 && selector <= 213)
+   snprintf(pin_name, MAX_PIN_NAME_LEN, 
special_pins_names[selector - 210]);
+   else
+   snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+   return pin_name;
+}
+
+static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin,
+   unsigned int selector)
+{
+   return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sm8550_data = {
+   .pin_data = {
+   .pin_count = 214,
+   .special_pins_start = 210,
+   },
+   .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+   .get_function_name = sm8550_get_function_name,
+   .get_function_mux = sm8550_get_function_mux,
+   .get_pin_name = sm8550_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+   { .compatible = "qcom,sm8550-tlmm", .data = (ulong)&sm8550_data },
+   { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sm8550) = {
+   .name   = "pinctrl_sm8550",
+   .id = UCLASS_NOP,
+   .of_match   = msm_pinctrl_ids,
+   .ops= &msm_pinctrl_ops,
+   .bind   = msm_pinctrl_bind,
+};
+

-- 
2.34.1

[PATCH 0/3] qcom: add pinctrl driver for SM8550 and SM8650

[Neil Armstrong]

Add pinctrl driver for the TLMM block found in the SM8550 & SM8650 SoCs.

This driver only handles the gpio and qup debug uart pinmux, and makes sure
the pinconf applies on SDC2 pins.

Finally enable both drivers in the Qualcomm defconfig

Signed-off-by: Neil Armstrong 
---
Neil Armstrong (3):
  pinctrl: qcom: Add SM8550 pinctrl driver
  pinctrl: qcom: Add SM8650 pinctrl driver
  qcom_defconfig: enable SM8550 & SM8650 pinctrl driver

 configs/qcom_defconfig|  2 +
 drivers/pinctrl/qcom/Kconfig  | 14 +++
 drivers/pinctrl/qcom/Makefile |  2 +
 drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +++
 drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +++
 5 files changed, 168 insertions(+)
---
base-commit: cec1c47bdaf84a643f318d480b1218bfff1041ff
change-id: 20240404-topic-sm8x50-pinctrl-101fac729d23

Best regards,
-- 
Neil Armstrong 

[PATCH 1/1] efi_loader: eliminate duplicate runtime section definitions

[Heinrich Schuchardt]

The following symbols are defined in two includes:

* __efi_runtime_start[]
* __efi_runtime_stop[]
* __efi_runtime_rel_start[]
* __efi_runtime_rel_stop[]

Eliminate the definitions in efi_loader.h.

Signed-off-by: Heinrich Schuchardt 
---
 include/efi_loader.h| 3 ---
 lib/efi_loader/efi_memory.c | 1 +
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index 7daca0afba..bb51c02817 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -345,9 +345,6 @@ extern const efi_guid_t smbios3_guid;
 extern const efi_guid_t efi_guid_text_input_protocol;
 extern const efi_guid_t efi_guid_text_output_protocol;
 
-extern char __efi_runtime_start[], __efi_runtime_stop[];
-extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
-
 /**
  * struct efi_open_protocol_info_item - open protocol info item
  *
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index edfad2d95a..81f5f98a8a 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
-- 
2.43.0

Re: [PATCH 3/4] fastboot: blk: introduce fastboot block flashing support

[Mattijs Korpershoek]

Hi Dmitrii,

Thank you for the patch and sorry for the review delay.

On mer., mars 06, 2024 at 18:59, Dmitrii Merkurev  wrote:

> Reuse common logic between existing mmc and new introduced
> block implementation
>
> Signed-off-by: Dmitrii Merkurev 
> Cc: Alex Kiernan 
> Cc: Patrick Delaunay 
> Cc: Simon Glass 
> Cc: Mattijs Korpershoek 
> Cc: Ying-Chun Liu (PaulLiu) 

This change (when applied along with 1/4 and 2/4) introduces a build for
sandbox:

$ make sandbox_defconfig
$ make

[...]

drivers/fastboot/fb_mmc.c: In function 'fastboot_mmc_erase':
drivers/fastboot/fb_mmc.c:596:16: warning: implicit declaration of function 
'fb_block_write'; did you mean 'blk_write'? [-Wimplicit-function-declaration]
  596 | blks = fb_block_write(dev_desc, blks_start, blks_size, NULL);
  |^~
  |blk_write

[...]

LTO u-boot
/usr/bin/ld: /tmp/cczd5cS1.ltrans18.ltrans.o: in function `erase.lto_priv.0':
/mnt/work/upstream/u-boot/drivers/fastboot/fb_mmc.c:596: undefined reference to 
`fb_block_write'
collect2: error: ld returned 1 exit status
make: *** [Makefile:1798: u-boot] Error 1


> ---
>  drivers/fastboot/Makefile   |   4 +-
>  drivers/fastboot/fb_block.c | 200 
>  drivers/fastboot/fb_mmc.c   | 120 ++
>  include/fb_block.h  |  70 +
>  4 files changed, 281 insertions(+), 113 deletions(-)
>  create mode 100644 drivers/fastboot/fb_block.c
>  create mode 100644 include/fb_block.h
>
> diff --git a/drivers/fastboot/Makefile b/drivers/fastboot/Makefile
> index 048af5aa82..91e98763e8 100644
> --- a/drivers/fastboot/Makefile
> +++ b/drivers/fastboot/Makefile
> @@ -3,5 +3,7 @@
>  obj-y += fb_common.o
>  obj-y += fb_getvar.o
>  obj-y += fb_command.o
> -obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o
> +obj-$(CONFIG_FASTBOOT_FLASH_BLOCK) += fb_block.o
> +# MMC reuses block implementation
> +obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_block.o fb_mmc.o
>  obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o
> diff --git a/drivers/fastboot/fb_block.c b/drivers/fastboot/fb_block.c
> new file mode 100644
> index 00..908decd544
> --- /dev/null
> +++ b/drivers/fastboot/fb_block.c
> @@ -0,0 +1,200 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (C) 2024 The Android Open Source Project
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/**
> + * FASTBOOT_MAX_BLOCKS_ERASE - maximum blocks to erase per derase call
> + *
> + * in the ERASE case we can have much larger buffer size since
> + * we're not transferring an actual buffer
> + */
> +#define FASTBOOT_MAX_BLOCKS_ERASE 1048576
> +/**
> + * FASTBOOT_MAX_BLOCKS_WRITE - maximum blocks to write per dwrite call
> + */
> +#define FASTBOOT_MAX_BLOCKS_WRITE 65536
> +
> +struct fb_block_sparse {
> + struct blk_desc *dev_desc;
> +};
> +
> +static lbaint_t fb_block_write(struct blk_desc *block_dev, lbaint_t start,
> +lbaint_t blkcnt, const void *buffer)
> +{
> + lbaint_t blk = start;
> + lbaint_t blks_written = 0;
> + lbaint_t cur_blkcnt = 0;
> + lbaint_t blks = 0;
> + int step = buffer ? FASTBOOT_MAX_BLOCKS_WRITE : 
> FASTBOOT_MAX_BLOCKS_ERASE;
> + int i;
> +
> + for (i = 0; i < blkcnt; i += step) {
> + cur_blkcnt = min((int)blkcnt - i, step);
> + if (buffer) {
> + if (fastboot_progress_callback)
> + fastboot_progress_callback("writing");
> + blks_written = blk_dwrite(block_dev, blk, cur_blkcnt,
> +   buffer + (i * 
> block_dev->blksz));
> + } else {
> + if (fastboot_progress_callback)
> + fastboot_progress_callback("erasing");
> + blks_written = blk_derase(block_dev, blk, cur_blkcnt);
> + }
> + blk += blks_written;
> + blks += blks_written;
> + }
> + return blks;
> +}
> +
> +static lbaint_t fb_block_sparse_write(struct sparse_storage *info,
> +   lbaint_t blk, lbaint_t blkcnt,
> +   const void *buffer)
> +{
> + struct fb_block_sparse *sparse = info->priv;
> + struct blk_desc *dev_desc = sparse->dev_desc;
> +
> + return fb_block_write(dev_desc, blk, blkcnt, buffer);
> +}
> +
> +static lbaint_t fb_block_sparse_reserve(struct sparse_storage *info,
> + lbaint_t blk, lbaint_t blkcnt)
> +{
> + return blkcnt;
> +}
> +
> +int fastboot_block_get_part_info(const char *part_name,
> +  struct blk_desc **dev_desc,
> +  struct disk_partition *part_info,
> +  char *response)
> +{
> + int ret;
> + const char *interface = config_opt_enabled(CONFIG_FASTBOOT_FLASH_BLOCK,
> +

Re: [PATCH 33/33] doc: boards: amlogic: add documentation for ODROID-HC4

[Heinrich Schuchardt]

On 3/20/23 12:46, Christian Hewitt wrote:

Add separate documentation for the ODROID-HC4 board to ensure
users build U-Boot using the HC4 defconfig that enables PCIe
SATA boot. This avoids user frustration trying to boot after
using the C4 recipe which only works from SD card.

Signed-off-by: Christian Hewitt 
---
  doc/board/amlogic/index.rst  |   1 +
  doc/board/amlogic/odroid-hc4.rst | 141 +++
  2 files changed, 142 insertions(+)
  create mode 100644 doc/board/amlogic/odroid-hc4.rst

diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst
index 7c4c161e0d..9b76bca427 100644
--- a/doc/board/amlogic/index.rst
+++ b/doc/board/amlogic/index.rst
@@ -101,6 +101,7 @@ Board Documentation
 nanopi-k2
 odroid-c2
 odroid-c4
+   odroid-hc4
 odroid-n2
 odroid-n2l
 odroid-go-ultra
diff --git a/doc/board/amlogic/odroid-hc4.rst b/doc/board/amlogic/odroid-hc4.rst
new file mode 100644
index 00..94c3312022
--- /dev/null
+++ b/doc/board/amlogic/odroid-hc4.rst
@@ -0,0 +1,141 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for ODROID-HC4 (S905X3)
+==
+
+ODROID-HC4 is a variant of the ODROID-C4 single board computer manufactured by 
Hardkernel
+with the following specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - 16MB XT25F128B SPI-NOR flash
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 7-pin GPIO header for OLED display and RTC
+ - 1x USB 2.0 host (micro)
+ - 2x SATA ports via ASM1061 PCIe to SATA controller
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+U-Boot Compilation
+--
+
+.. code-block:: bash
+
+$ export CROSS_COMPILE=aarch64-none-elf-
+$ make odroid-hc4_defconfig
+$ make
+
+U-Boot Signing with Pre-Built FIP repo
+--
+
+.. code-block:: bash
+$ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+$ cd amlogic-boot-fip
+$ mkdir my-output-dir
+$ ./build-fip.sh odroid-hc4 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+-
+
+Amlogic does not provide sources for the firmware and tools needed to create a 
bootloader
+image so it is necessary to obtain binaries from sources published by the 
board vendor:
+
+.. code-block:: bash
+
+$ wget 
https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+$ wget 
https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+$ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+$ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+$ export 
PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+$ DIR=odroid-hc4
+$ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b 
odroidg12-v2015.01 $DIR
+
+$ cd odroid-hc4
+$ make odroidc4_defconfig
+$ make
+$ export UBOOTDIR=$PWD
+
+Go back to mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+$ mkdir fip


Thanks a lot for providing all these board descriptions.

Prefixing with $ makes copy-/pasting multiple commands impossible.

I personally feel distracted by the prompts. But if you really want 
those $ signs displayed, please, use


.. prompt:: bash $

  mkdir fip

Best regards

Heinrich


+
+$ wget 
https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh
 -O fip/blx_fix.sh
+$ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+$ cp $UBOOTDIR/build/board/hardkernel/odroidc4/firmware/acs.bin fip/
+$ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+$ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+$ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+$ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+$ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+$ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+$ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+$ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+$ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+$ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+$ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+$ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+$ cp u-boot.bin fip/bl33.bin
+
+$ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+$ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+--output 
fip/bl30_new.bin.g12a.enc \
+  

Re: [PATCH] doc: build: update docker image to latest

[Heinrich Schuchardt]

On 4/5/24 08:16, Mattijs Korpershoek wrote:

commit cacc0b2678c0 ("CI: Move to latest container image") updated the
docker container image.

Reflect the change in the documentation.

Signed-off-by: Mattijs Korpershoek 


Reviewed-by: Heinrich Schuchardt 


---
Note: maybe we can consider doing the doc change each time we update
.gitlab-ci.yml ?
---
  doc/build/docker.rst | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/build/docker.rst b/doc/build/docker.rst
index 953d1b28a063..45659b3b89dc 100644
--- a/doc/build/docker.rst
+++ b/doc/build/docker.rst
@@ -11,4 +11,4 @@ Or to use an existing container

  .. code-block:: bash

-sudo docker pull trini/u-boot-gitlab-ci-runner:bionic-20200807-02Sep2020
+sudo docker pull trini/u-boot-gitlab-ci-runner:jammy-20240227-14Mar2024

---
base-commit: cdfcc37428e06f4730ab9a17cc084eeb7676ea1a
change-id: 20240405-doc-container-img-904d56d5efcb

Best regards,

Re: [PATCH] doc: build: fix gen_compile_commands section level

[Heinrich Schuchardt]

On 4/5/24 08:18, Mattijs Korpershoek wrote:

The 2 subsections of this page ("Compatible IDEs" and "Usage") are using
the same header level as the title (with "===").
Because of this, they always appear in the HTML rendered ToC.

Drop the subsections one level lower by replacing "=" by "-".
This fixes the HTML rendering.

Signed-off-by: Mattijs Korpershoek 


Reviewed-by: Heinrich Schuchardt 


---
  doc/build/gen_compile_commands.rst | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/doc/build/gen_compile_commands.rst 
b/doc/build/gen_compile_commands.rst
index 50305cec4a83..d503764f9e3f 100644
--- a/doc/build/gen_compile_commands.rst
+++ b/doc/build/gen_compile_commands.rst
@@ -42,7 +42,7 @@ needed for it to be usable by the LSP, unless you set a name 
for the database
  other than it's default one (compile_commands.json).

  Compatible IDEs
-===
+---

  Several popular integrated development environments (IDEs) support the use
  of JSON compilation databases for C/C++ development, making it easier to
@@ -73,7 +73,7 @@ compile_commands.json in the root of the repository should 
suffice to enable
  code navigation.

  Usage
-=
+-

  For further details on the script's options, please refer to its help message,
  as in the example below.

---
base-commit: cdfcc37428e06f4730ab9a17cc084eeb7676ea1a
change-id: 20240405-doc-fix-headings-6109365355a3

Best regards,

Re: [PATCH 3/4] arm: dts: k3-*-binman.dtsi: Clean up and templatize boot binaries

[Michael Walle]

Hi,

On Thu Apr 4, 2024 at 11:10 AM CEST, Neha Malcom Francis wrote:
> But again in the interest of time... this would mean this cleaning up effort 
> be 
> kept on hold. If we can agree to move to using the generator later as the 
> final 
> solution, can we pick up this series for now?

Agreed. I just saw the new RFC for the j722s support. It should also
make use of this cleanup then, btw.

-michael

Re: [PATCH v2] efi_loader: move efi_var_collect to common functions

[Heinrich Schuchardt]

On 4/5/24 08:50, Ilias Apalodimas wrote:

From: Ilias Apalodimas 

efi_var_collect() was initially placed in efi_var_file.c, since back
then we only supported efi variables stored in a file. Since then we
support variables stored in an RPMB as well and use that function to
collect variables that should be present at runtime.

So let's move it around in efi_var_common.c which makes more sense

Suggested-by: Heinrich Schuchardt 
Signed-off-by: Ilias Apalodimas 


Reviewed-by: Heinrich Schuchardt 


---
Changes since v1:
- Clean up the makefile as well
- fix checkpatch error

  lib/efi_loader/Makefile |  2 +-
  lib/efi_loader/efi_var_common.c | 74 +
  lib/efi_loader/efi_var_file.c   | 64 
  3 files changed, 75 insertions(+), 65 deletions(-)

diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index fcb0af7e7d6d..6a0ce6c32c88 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -72,11 +72,11 @@ obj-y += efi_string.o
  obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += efi_unicode_collation.o
  obj-y += efi_var_common.o
  obj-y += efi_var_mem.o
-obj-y += efi_var_file.o
  ifeq ($(CONFIG_EFI_MM_COMM_TEE),y)
  obj-y += efi_variable_tee.o
  else
  obj-y += efi_variable.o
+obj-y += efi_var_file.o
  obj-$(CONFIG_EFI_VARIABLES_PRESEED) += efi_var_seed.o
  endif
  obj-y += efi_watchdog.o
diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c
index d528747f3fb4..4268850990f5 100644
--- a/lib/efi_loader/efi_var_common.c
+++ b/lib/efi_loader/efi_var_common.c
@@ -9,6 +9,7 @@
  #include 
  #include 
  #include 
+#include 

  enum efi_secure_mode {
EFI_MODE_SETUP,
@@ -416,3 +417,76 @@ void *efi_get_var(const u16 *name, const efi_guid_t 
*vendor, efi_uintn_t *size)

return buf;
  }
+
+/**
+ * efi_var_collect() - Copy EFI variables mstching attributes mask
+ *
+ * @bufp:  buffer containing variable collection
+ * @lenp:  buffer length
+ * @attr_mask: mask of matched attributes
+ *
+ * Return: Status code
+ */
+efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t 
*lenp,
+   u32 check_attr_mask)
+{
+   size_t len = EFI_VAR_BUF_SIZE;
+   struct efi_var_file *buf;
+   struct efi_var_entry *var, *old_var;
+   size_t old_var_name_length = 2;
+
+   *bufp = NULL; /* Avoid double free() */
+   buf = calloc(1, len);
+   if (!buf)
+   return EFI_OUT_OF_RESOURCES;
+   var = buf->var;
+   old_var = var;
+   for (;;) {
+   efi_uintn_t data_length, var_name_length;
+   u8 *data;
+   efi_status_t ret;
+
+   if ((uintptr_t)buf + len <=
+   (uintptr_t)var->name + old_var_name_length)
+   return EFI_BUFFER_TOO_SMALL;
+
+   var_name_length = (uintptr_t)buf + len - (uintptr_t)var->name;
+   memcpy(var->name, old_var->name, old_var_name_length);
+   guidcpy(&var->guid, &old_var->guid);
+   ret = efi_get_next_variable_name_int(
+   &var_name_length, var->name, &var->guid);
+   if (ret == EFI_NOT_FOUND)
+   break;
+   if (ret != EFI_SUCCESS) {
+   free(buf);
+   return ret;
+   }
+   old_var_name_length = var_name_length;
+   old_var = var;
+
+   data = (u8 *)var->name + old_var_name_length;
+   data_length = (uintptr_t)buf + len - (uintptr_t)data;
+   ret = efi_get_variable_int(var->name, &var->guid,
+  &var->attr, &data_length, data,
+  &var->time);
+   if (ret != EFI_SUCCESS) {
+   free(buf);
+   return ret;
+   }
+   if ((var->attr & check_attr_mask) == check_attr_mask) {
+   var->length = data_length;
+   var = (struct efi_var_entry *)ALIGN((uintptr_t)data + 
data_length, 8);
+   }
+   }
+
+   buf->reserved = 0;
+   buf->magic = EFI_VAR_FILE_MAGIC;
+   len = (uintptr_t)var - (uintptr_t)buf;
+   buf->crc32 = crc32(0, (u8 *)buf->var,
+  len - sizeof(struct efi_var_file));
+   buf->length = len;
+   *bufp = buf;
+   *lenp = len;
+
+   return EFI_SUCCESS;
+}
diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c
index 532b6b40eefe..413e1794e88c 100644
--- a/lib/efi_loader/efi_var_file.c
+++ b/lib/efi_loader/efi_var_file.c
@@ -52,70 +52,6 @@ static efi_status_t __maybe_unused 
efi_set_blk_dev_to_system_partition(void)
return EFI_SUCCESS;
  }

-efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t 
*lenp,
-   u32 check_attr_ma

Re: [PATCH] ARM: imx: stm32: Test whether ethernet node is enabled before reading MAC EEPROM on DHSOM

[Patrice CHOTARD]

On 3/12/24 22:15, Marek Vasut wrote:
> Check whether the ethernet interface is enabled at all before reading
> MAC EEPROM. As a cost saving measure, it can happen that the MAC EEPROM
> is not populated on SoMs which do not use ethernet.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: "NXP i.MX U-Boot Team" 
> Cc: Andreas Geisreiter 
> Cc: Christoph Niedermaier 
> Cc: Fabio Estevam 
> Cc: Patrice Chotard 
> Cc: Patrick Delaunay 
> Cc: Stefano Babic 
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply.com
> ---
> NOTE: It is probably best if this goes in via either imx or stm32 tree,
>   I can break the patch up, but that would introduce dependency
>   between two PRs in different trees. Let me know what you prefer.
> ---
>  board/dhelectronics/common/dh_common.c   | 16 
>  board/dhelectronics/common/dh_common.h   |  8 
>  board/dhelectronics/dh_imx6/dh_imx6.c|  3 +++
>  .../dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c  |  6 ++
>  board/dhelectronics/dh_stm32mp1/board.c  |  6 ++
>  5 files changed, 39 insertions(+)
> 
> diff --git a/board/dhelectronics/common/dh_common.c 
> b/board/dhelectronics/common/dh_common.c
> index 67e3d59b1f3..34094a020b0 100644
> --- a/board/dhelectronics/common/dh_common.c
> +++ b/board/dhelectronics/common/dh_common.c
> @@ -18,6 +18,19 @@ bool dh_mac_is_in_env(const char *env)
>   return eth_env_get_enetaddr(env, enetaddr);
>  }
>  
> +int dh_get_mac_is_enabled(const char *alias)
> +{
> + ofnode node = ofnode_path(alias);
> +
> + if (!ofnode_valid(node))
> + return -EINVAL;
> +
> + if (!ofnode_is_enabled(node))
> + return -ENODEV;
> +
> + return 0;
> +}
> +
>  int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
>  {
>   struct udevice *dev;
> @@ -57,6 +70,9 @@ __weak int dh_setup_mac_address(void)
>   if (dh_mac_is_in_env("ethaddr"))
>   return 0;
>  
> + if (dh_get_mac_is_enabled("ethernet0"))
> + return 0;
> +
>   if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
>   return eth_env_set_enetaddr("ethaddr", enetaddr);
>  
> diff --git a/board/dhelectronics/common/dh_common.h 
> b/board/dhelectronics/common/dh_common.h
> index 2b24637d96d..a2de5b1553e 100644
> --- a/board/dhelectronics/common/dh_common.h
> +++ b/board/dhelectronics/common/dh_common.h
> @@ -11,6 +11,14 @@
>   */
>  bool dh_mac_is_in_env(const char *env);
>  
> +/*
> + * dh_get_mac_is_enabled - Test if ethernet MAC is enabled in DT
> + *
> + * @alias: alias for ethernet MAC device tree node
> + * Return: 0 if OK, other value on error
> + */
> +int dh_get_mac_is_enabled(const char *alias);
> +
>  /*
>   * dh_get_mac_from_eeprom - Get MAC address from eeprom and write it to 
> enetaddr
>   *
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c 
> b/board/dhelectronics/dh_imx6/dh_imx6.c
> index 07fc9b1fe6d..0676587c38a 100644
> --- a/board/dhelectronics/dh_imx6/dh_imx6.c
> +++ b/board/dhelectronics/dh_imx6/dh_imx6.c
> @@ -92,6 +92,9 @@ int dh_setup_mac_address(void)
>   if (dh_mac_is_in_env("ethaddr"))
>   return 0;
>  
> + if (dh_get_mac_is_enabled("ethernet0"))
> + return 0;
> +
>   if (!dh_imx_get_mac_from_fuse(enetaddr))
>   goto out;
>  
> diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c 
> b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
> index 5f12d787d38..ff2c0e87215 100644
> --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
> +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
> @@ -47,6 +47,9 @@ static int dh_imx8_setup_ethaddr(void)
>   if (dh_mac_is_in_env("ethaddr"))
>   return 0;
>  
> + if (dh_get_mac_is_enabled("ethernet0"))
> + return 0;
> +
>   if (!dh_imx_get_mac_from_fuse(enetaddr))
>   goto out;
>  
> @@ -66,6 +69,9 @@ static int dh_imx8_setup_eth1addr(void)
>   if (dh_mac_is_in_env("eth1addr"))
>   return 0;
>  
> + if (dh_get_mac_is_enabled("ethernet1"))
> + return 0;
> +
>   if (!dh_imx_get_mac_from_fuse(enetaddr))
>   goto increment_out;
>  
> diff --git a/board/dhelectronics/dh_stm32mp1/board.c 
> b/board/dhelectronics/dh_stm32mp1/board.c
> index 88eb7d1b8d4..b3309c9d330 100644
> --- a/board/dhelectronics/dh_stm32mp1/board.c
> +++ b/board/dhelectronics/dh_stm32mp1/board.c
> @@ -129,6 +129,9 @@ static int dh_stm32_setup_ethaddr(void)
>   if (dh_mac_is_in_env("ethaddr"))
>   return 0;
>  
> + if (dh_get_mac_is_enabled("ethernet0"))
> + return 0;
> +
>   if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
>   return eth_env_set_enetaddr("ethaddr", enetaddr);
>  
> @@ -142,6 +145,9 @@ static int dh_stm32_setup_eth1addr(void)
>   if (dh_mac_is_in_env("eth1addr"))
>   return 0;
>  
> + if (dh_get_mac_is_enabled("ethernet1"))
> +   

Re: [PATCH] ARM: imx: stm32: Test whether ethernet node is enabled before reading MAC EEPROM on DHSOM

[Patrice CHOTARD]

On 3/13/24 01:52, Fabio Estevam wrote:
> Hi Marek,
> 
> On Tue, Mar 12, 2024 at 6:16 PM Marek Vasut  wrote:
> 
>> NOTE: It is probably best if this goes in via either imx or stm32 tree,
>>   I can break the patch up, but that would introduce dependency
>>   between two PRs in different trees. Let me know what you prefer.
> 

Hi Marek, Fabio

Sorry for the delay.

> I can apply it to u-boot-imx next if Patrice and Patrick are OK.

yes, you can apply it directly through u-boot-imx next.

Thanks
Patrice

Re: [PATCH 2/4] fastboot: blk: add block device flashing configuration

[Mattijs Korpershoek]

Hi Dmitrii,

Thank you for the patch and sorry for the review delay.

On mer., mars 06, 2024 at 18:59, Dmitrii Merkurev  wrote:

> Signed-off-by: Dmitrii Merkurev 
> Cc: Patrick Delaunay 
> Cc: Simon Glass 
> Cc: Mattijs Korpershoek 
> Cc: Ying-Chun Liu (PaulLiu) 
> ---
>  drivers/fastboot/Kconfig | 20 ++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> index 5e5855a76c..460c5e98d7 100644
> --- a/drivers/fastboot/Kconfig
> +++ b/drivers/fastboot/Kconfig
> @@ -87,7 +87,7 @@ config FASTBOOT_USB_DEV
>  config FASTBOOT_FLASH
>   bool "Enable FASTBOOT FLASH command"
>   default y if ARCH_SUNXI || ARCH_ROCKCHIP
> - depends on MMC || (MTD_RAW_NAND && CMD_MTDPARTS)
> + depends on MMC || (MTD_RAW_NAND && CMD_MTDPARTS) || BLK
>   select IMAGE_SPARSE
>   help
> The fastboot protocol includes a "flash" command for writing
> @@ -109,12 +109,16 @@ choice
>  
>  config FASTBOOT_FLASH_MMC
>   bool "FASTBOOT on MMC"
> - depends on MMC
> + depends on MMC && BLK
>  
>  config FASTBOOT_FLASH_NAND
>   bool "FASTBOOT on NAND"
>   depends on MTD_RAW_NAND && CMD_MTDPARTS
>  
> +config FASTBOOT_FLASH_BLOCK
> + bool "FASTBOOT on block device"
> + depends on BLK
> +

If we just apply this patch, then this KConfig option is unused. Can we
please squash this into patch 3/4?

>  endchoice
>  
>  config FASTBOOT_FLASH_MMC_DEV
> @@ -189,6 +193,18 @@ config FASTBOOT_MMC_USER_NAME
> defined here.
> The default target name for erasing EMMC_USER is "mmc0".
>  
> +config FASTBOOT_FLASH_BLOCK_INTERFACE_NAME
> + string "Define FASTBOOT block interface name"
> + depends on FASTBOOT_FLASH_BLOCK
> + help
> +   "Fastboot block interface name (mmc, virtio, etc)"

There is a finite list of supported options for this. Can we please
document all of them so that users know what is valid and what not?
If so, we can drop the "etc" part in the help string.

> +
> +config FASTBOOT_FLASH_BLOCK_DEVICE_ID
> + int "Define FASTBOOT block device id"
> + depends on FASTBOOT_FLASH_BLOCK
> + help
> +   "Fastboot block device id"

When FASTBOOT_FLASH_BLOCK=="mmc", how is FASTBOOT_FLASH_BLOCK_DEVICE_ID
different from FASTBOOT_FLASH_MMC_DEV?

If they are similar, are we sure this symbol really needed?

> +
>  config FASTBOOT_GPT_NAME
>   string "Target name for updating GPT"
>   depends on FASTBOOT_FLASH_MMC && EFI_PARTITION
> -- 
> 2.44.0.278.ge034bb2e1d-goog

Re: [RFC PATCH 13/15] arm: dts: Introduce J722S U-Boot dts files

[Jayesh Choudhary]

Hi,

On 04/04/24 20:59, Andrew Davis wrote:

On 4/4/24 4:00 AM, Jayesh Choudhary wrote:

Include the uboot device tree files needed to boot the board.

Co-developed-by: Vaishnav Achath 
Signed-off-by: Vaishnav Achath 
Signed-off-by: Jayesh Choudhary 
---
  arch/arm/dts/Makefile  |    2 +
  arch/arm/dts/k3-j722s-binman.dtsi  |  171 ++
  arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi | 2795 
  arch/arm/dts/k3-j722s-evm-u-boot.dtsi  |   36 +
  arch/arm/dts/k3-j722s-r5-evm.dts   |   82 +
  5 files changed, 3086 insertions(+)
  create mode 100644 arch/arm/dts/k3-j722s-binman.dtsi
  create mode 100644 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi
  create mode 100644 arch/arm/dts/k3-j722s-evm-u-boot.dtsi
  create mode 100644 arch/arm/dts/k3-j722s-r5-evm.dts



[...]

diff --git a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi 
b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi

new file mode 100644
index 00..056ef08455
--- /dev/null
+++ b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common J722S EVM dts file for SPLs
+ * Copyright (C) 2024 Texas Instruments Incorporated - 
https://www.ti.com/

+ */
+
+#include "k3-j722s-binman.dtsi"
+
+/ {
+    chosen {
+    stdout-path = "serial2:115200n8";
+    tick-timer = &main_timer0;
+    };
+};
+
+&main_pktdma {
+    reg = <0x00 0x485c 0x00 0x000100>,
+  <0x00 0x4a80 0x00 0x02>,
+  <0x00 0x4aa0 0x00 0x04>,
+  <0x00 0x4b80 0x00 0x40>,
+  <0x00 0x485e 0x00 0x02>,
+  <0x00 0x484a 0x00 0x004000>,
+  <0x00 0x484c 0x00 0x002000>,
+  <0x00 0x4843 0x00 0x004000>;
+    reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+    "cfg", "tchan", "rchan", "rflow";


Is this needed? Do we still not have the correct regs in
upstream kernel?


I missed this change when I was going through j722s dts changes.

u-boot dts currently does not have this fixed.
Tag v6.9-rc1-dts from devicetree-rebasing would have this fix.

Will keep this in mind.

Also from TRM memory map, the range is off for 'tchanrt'
Will send a fix patch for that after checking for all platforms
to linux upstream if required.




+};
+
+&dmsc {
+    bootph-pre-ram;
+
+    k3_sysreset: sysreset-controller {
+    compatible = "ti,sci-sysreset";
+    bootph-pre-ram;


This node won't be needed soon either[0]. Should mean an
almost empty -u-boot.dtsi file, which should be the goal.



Okay. I will remove the node.

Should I mark [0] as dependency or is it okay without it.
Impact would only be on U-Boot RESET I think. Base support
would still be functional.

Thanks,
Jayesh


Andrew

[0] https://lore.kernel.org/all/20240402160908.508974-1-...@ti.com/


+    };


[...]

Re: [PATCH 1/4] virtio: blk: introduce virtio-block erase support

[Mattijs Korpershoek]

Hi Dmitrii,

Thank you for the patch.

I'm not the virtio maintainer in U-Boot:

/mnt/work/upstream/u-boot/ $ ./scripts/get_maintainer.pl drivers/virtio/
Bin Meng  (maintainer:VirtIO)
[...]

I've added Bin to the Cc list, please include him if you re-submit.

On mer., mars 06, 2024 at 18:59, Dmitrii Merkurev  wrote:

> Co-developed-by: Cody Schuffelen 
> Signed-off-by: Cody Schuffelen 
> Signed-off-by: Dmitrii Merkurev 
> Cc: Tuomas Tynkkynen 
> Cc: Simon Glass 
> Cc: Mattijs Korpershoek 
> Cc: Ying-Chun Liu (PaulLiu) 

I'm not super familiar with virtio, so I've not reviewed this.

However, I tested the sandbox unit tests:

uboot@db35472a:/mnt/work/upstream/u-boot$ ./u-boot -T -c "ut dm virtio*"
Bloblist at b000 not found (err=-2)
sandbox_serial serial: pinctrl_select_state_full: 
uclass_get_device_by_phandle_id: err=-19


U-Boot 2024.04-00137-g075feb52299 (Apr 05 2024 - 07:12:35 +)

Reset Status: WARM Reset Status: COLD
Model: sandbox
DRAM:  256 MiB
[nvmxip-qspi1@0800]: the block device blk#2 ready for use
[nvmxip-qspi2@0820]: the block device blk#2 ready for use
Core:  286 devices, 101 uclasses, devicetree: board
WDT:   Not starting wdt-gpio-toggle
WDT:   Not starting wdt-gpio-level
WDT:   Not starting wdt@0
NAND:  4100 MiB
MMC:   mmc2: 2 (SD), mmc1: 1 (SD), mmc0: 0 (SD)
Loading Environment from nowhere... OK
In:serial,cros-ec-keyb,usbkbd
Out:   serial,vidconsole
Err:   serial,vidconsole
Model: sandbox
Net:   eth0: eth@10002000, eth5: eth@10003000, eth3: sbe5, eth6: eth@10004000, 
eth8: phy-test-eth, eth4: dsa-test-eth, eth2: lan0, eth7: lan1
Test: dm_test_virtio_all_ops: virtio_device.c
Test: dm_test_virtio_all_ops: virtio_device.c (flat tree)
Test: dm_test_virtio_base: virtio_device.c
Test: dm_test_virtio_base: virtio_device.c (flat tree)
Test: dm_test_virtio_missing_ops: virtio.c
Test: dm_test_virtio_missing_ops: virtio.c (flat tree)
Test: dm_test_virtio_remove: virtio_device.c
Test: dm_test_virtio_remove: virtio_device.c (flat tree)
Test: dm_test_virtio_ring: virtio_device.c
Test: dm_test_virtio_ring: virtio_device.c (flat tree)
Test: dm_test_virtio_rng_check_len: virtio_rng.c
Test: dm_test_virtio_rng_check_len: virtio_rng.c (flat tree)
Failures: 0

Tested-by: Mattijs Korpershoek  # sandbox

> ---
>  drivers/virtio/virtio_blk.c | 91 +++--
>  drivers/virtio/virtio_blk.h | 47 +++
>  2 files changed, 124 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c
> index 9581058286..225b65c4d1 100644
> --- a/drivers/virtio/virtio_blk.c
> +++ b/drivers/virtio/virtio_blk.c
> @@ -19,30 +19,82 @@ struct virtio_blk_priv {
>   struct virtqueue *vq;
>  };
>  
> +static const u32 feature[] = {
> + VIRTIO_BLK_F_WRITE_ZEROES
> +};
> +
> +static void virtio_blk_init_header_sg(struct udevice *dev, u64 sector, u32 
> type,
> +   struct virtio_blk_outhdr *out_hdr, struct 
> virtio_sg *sg)
> +{
> + const bool sector_is_needed = type == VIRTIO_BLK_T_IN ||
> +   type == VIRTIO_BLK_T_OUT;
> +
> + out_hdr->type = cpu_to_virtio32(dev, type);
> + out_hdr->sector = cpu_to_virtio64(dev, sector_is_needed ? sector : 0);
> +
> + sg->addr = out_hdr;
> + sg->length = sizeof(*out_hdr);
> +}
> +
> +static void virtio_blk_init_write_zeroes_sg(struct udevice *dev, u64 sector, 
> lbaint_t blkcnt,
> + struct 
> virtio_blk_discard_write_zeroes *wz,
> + struct virtio_sg *sg)
> +{
> + wz->sector = cpu_to_virtio64(dev, sector);
> + wz->num_sectors = cpu_to_virtio32(dev, blkcnt);
> + wz->flags = cpu_to_virtio32(dev, 0);
> +
> + sg->addr = wz;
> + sg->length = sizeof(*wz);
> +}
> +
> +static void virtio_blk_init_status_sg(u8 *status, struct virtio_sg *sg)
> +{
> + sg->addr = status;
> + sg->length = sizeof(*status);
> +}
> +
> +static void virtio_blk_init_data_sg(void *buffer, lbaint_t blkcnt, struct 
> virtio_sg *sg)
> +{
> + sg->addr = buffer;
> + sg->length = blkcnt * 512;
> +}
> +
>  static ulong virtio_blk_do_req(struct udevice *dev, u64 sector,
>  lbaint_t blkcnt, void *buffer, u32 type)
>  {
>   struct virtio_blk_priv *priv = dev_get_priv(dev);
> + struct virtio_blk_outhdr out_hdr;
> + struct virtio_blk_discard_write_zeroes wz_hdr;
>   unsigned int num_out = 0, num_in = 0;
> + struct virtio_sg hdr_sg, wz_sg, data_sg, status_sg;
>   struct virtio_sg *sgs[3];
>   u8 status;
>   int ret;
>  
> - struct virtio_blk_outhdr out_hdr = {
> - .type = cpu_to_virtio32(dev, type),
> - .sector = cpu_to_virtio64(dev, sector),
> - };
> - struct virtio_sg hdr_sg = { &out_hdr, sizeof(out_hdr) };
> - struct virtio_sg data_sg = { buffer, blkcnt * 512 };
> - struct virtio_sg status_sg = { &status, sizeof(status) };
> -
> + virtio_blk

u-boot@lists.denx.de

[Heinrich Schuchardt]

On 4/4/24 08:35, Ilias Apalodimas wrote:

A symbol defined in a linker script (e.g. __efi_runtime_start = .;) is
only a symbol, not a variable and should not be dereferenced.
The common practice is either define it as
extern uint32_t __efi_runtime_start or
extern char __efi_runtime_start[] and access it as
&__efi_runtime_start or __efi_runtime_start respectively.

So let's access it properly since we define it as an array


Thanks for investigating this.

Beyond this patch I guess we should eliminate these duplicate defintions:

include/asm-generic/sections.h:38:extern char __efi_runtime_start[], 
__efi_runtime_stop[];
include/efi_loader.h:348:extern char __efi_runtime_start[], 
__efi_runtime_stop[];




Signed-off-by: Ilias Apalodimas 
---
  lib/efi_loader/efi_memory.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index edfad2d95a1d..98f104390c8d 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -933,8 +933,8 @@ static void add_u_boot_and_runtime(void)
 * Add Runtime Services. We mark surrounding boottime code as runtime as
 * well to fulfill the runtime alignment constraints but avoid padding.
 */
-   runtime_start = (ulong)&__efi_runtime_start & ~runtime_mask;
-   runtime_end = (ulong)&__efi_runtime_stop;
+   runtime_start = (ulong)__efi_runtime_start & ~runtime_mask;


Using (uintptr_t) would make it clearer that we are converting from a 
pointer to an integer type.


Best regards

Heinrich


+   runtime_end = (ulong)__efi_runtime_stop;
runtime_end = (runtime_end + runtime_mask) & ~runtime_mask;
runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
efi_add_memory_map_pg(runtime_start, runtime_pages,