Re: [PATCH] env: mmc: print MMC device being read
On 2024-04-15 14:43, Quentin Schulz wrote:
From: Quentin Schulz
This prints the MMC device being read similar to how we print the MMC
device we write to when e.g. calling saveenv.
One of the side effects is that the boot log now shows from which MMC
device the env was loaded:
Loading Environment from MMC... Reading from MMC(1)... OK
This is useful to identify which MMC device the environment was loaded
from for boards where there are more than one (e.g. eMMC and SD card)
without adding some debug messages manually.
Sadly, there's no way to know which of the default or redundant
environment is being read from env_mmc_load before env_import_redund is
called so it is printing a bit later (and possibly after error/warning
messages).
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Looking great to me.
Reviewed-by: Dragan Simic
---
env/mmc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/env/mmc.c b/env/mmc.c
index da84cddd74f..7afb733e890 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -436,6 +436,7 @@ static int env_mmc_load(void)
ret = env_import_redund((char *)tmp_env1, read1_fail, (char
*)tmp_env2,
read2_fail, H_EXTERNAL);
+ printf("Reading from %sMMC(%d)... ", gd->env_valid == ENV_REDUND ?
"redundant " : "", dev);
fini:
fini_mmc_for_env(mmc);
@@ -475,6 +476,8 @@ static int env_mmc_load(void)
goto fini;
}
+ printf("Reading from MMC(%d)... ", dev);
+
ret = env_import(buf, 1, H_EXTERNAL);
if (!ret) {
ep = (env_t *)buf;
---
base-commit: b03b49046af5dfca599d2ce8f0aafed89b97aa91
change-id: 20240415-mmc-loadenv-dev-ced678171e98
Best regards,
Re: [PATCH 1/4] board: starfive: function to read eMMC size
On Mon, Apr 15, 2024 at 4:50 AM Heinrich Schuchardt
wrote:
>
> The EEPROM provides information about the size of the EEPROM.
"The EEPROM provides information about the size of the eMMC."
> Provide a new function get_mmc_size_from_eeprom() to read it.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/include/asm/arch-jh7110/eeprom.h| 7 +++
> board/starfive/visionfive2/Kconfig | 9 +
> .../visionfive2/visionfive2-i2c-eeprom.c | 18 ++
> 3 files changed, 34 insertions(+)
>
> diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h
> b/arch/riscv/include/asm/arch-jh7110/eeprom.h
> index 62d184aeb57..17395d4269e 100644
> --- a/arch/riscv/include/asm/arch-jh7110/eeprom.h
> +++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
> @@ -12,6 +12,13 @@
> u8 get_pcb_revision_from_eeprom(void);
> u32 get_ddr_size_from_eeprom(void);
>
> +/**
> + * get_mmc_size_from_eeprom() - read MMC size form EEPROM
> + *
> + * @return: size in GiB or 0 on error.
> + */
> +u32 get_mmc_size_from_eeprom(void);
> +
> /**
> * get_product_id_from_eeprom - get product ID string
> *
> diff --git a/board/starfive/visionfive2/Kconfig
> b/board/starfive/visionfive2/Kconfig
> index 2186a939646..d7e8a7a7d78 100644
> --- a/board/starfive/visionfive2/Kconfig
> +++ b/board/starfive/visionfive2/Kconfig
> @@ -50,4 +50,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> imply PHY_LIB
> imply PHY_MSCC
>
> +config STARFIVE_NO_EMMC
> + bool "Report eMMC size as zero"
> + help
> + The serial number string in the EEPROM is meant to report the
> + size of onboard eMMC. Unfortunately some Milk-V Mars CM Lite
> + modules without eMMC show a non-zero size here.
> +
> + Set to 'Y' if you have a Mars CM Lite module.
> +
> endif
> diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
> b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
> index ddef7d61235..cd3d8bd51a6 100644
> --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
> +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
> @@ -548,6 +548,24 @@ u32 get_ddr_size_from_eeprom(void)
> return hextoul([14], NULL);
> }
>
> +u32 get_mmc_size_from_eeprom(void)
> +{
> + u32 size;
> +
> + if (IS_ENABLED(CONFIG_STARFIVE_NO_EMMC))
> + return 0;
> +
> + if (read_eeprom())
> + return 0;
> +
> + size = dectoul([19], NULL);
> +
> + if (pbuf.eeprom.atom1.data.pstr[21] == 'T')
> + size <<= 10;
> +
> + return size;
> +}
> +
> U_BOOT_LONGHELP(mac,
> "\n"
> "- display EEPROM content\n"
> --
> 2.43.0
>
Fixed-position parsing on a data format of ordered variable length
hyphen-delimited fields. Notable is that some Pine64 Star64 and Milk-V
Mars CM Lite boards shipped with uninitialized or wrong EEPROM data;
further the EEPROM Write Protect can be trivially disabled and
arbitrary data written i.e. with a paperclip then `mac` command. Could
this code be generalized to split fields on hyphen character better
expressing the expected data format or is that unwanted complexity and
code size?
Re: [PATCH 1/1] net: wget: fix TCP sequence number wrap around issue
Hi Michael, On Mon, 15 Apr 2024 at 22:55, Michael Nazzareno Trimarchi wrote: > > Very good job ;) to fix it. Just add Suggest-by: ;) Thank you for your advice. I sent following v2 patch. https://lore.kernel.org/u-boot/20240416002624.1909-1-yasuharu.shib...@gmail.com/ -- Best regards, Yasuharu Shibata
Re: [PATCH 4/4] Kconfig: Make all Kconfig encoding ascii
On Mon, Apr 15, 2024 at 02:49:13PM +0200, Michal Simek wrote: > > > On 4/15/24 14:22, Heinrich Schuchardt wrote: > > On 15.04.24 13:35, Michal Simek wrote: > > > Some of Kconfigs are using utf-8 encoding because of used chars. Convert > > > all of them to ascii enconging. > > > > > > Signed-off-by: Michal Simek > > > --- > > > > > > There are other files which are using utf-8 enconding and pretty much I > > > think we should convert all of them because there is no reason to use > > > utf-8 > > > encoding. > > > > Hello Michal, > > > > The commit message does not explain why we should refrain from using UTF-8. > > that's a good point. I was thinking about the reason for it and pretty much > wanted to get feedback from Tom about it. > > In doc/develop/sending_patches.rst is said that patches should be sent as > plain text but encoding is not specified. Traditionally this was ASCII and I > pretty much don't see the reason to use UTF encoding (even my name has > special czech char which I am not using, the same is for Marek Vasut). My point of view is that I think ASCII should be used in general, with the exception being names (I won't force people to ASCII-ize their names, modern systems handle UTF-8 just fine). I actually don't know if we should also exclude rST doc files from this rule as well as UTF-8 should render fine and for example "°C" reads nicely in web/PDF/etc. -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/4] Kconfig: Make all Kconfig encoding ascii
On Mon, Apr 15, 2024 at 02:22:02PM +0200, Heinrich Schuchardt wrote: > On 15.04.24 13:35, Michal Simek wrote: > > Some of Kconfigs are using utf-8 encoding because of used chars. Convert > > all of them to ascii enconging. > > > > Signed-off-by: Michal Simek [snip] > > diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig > > b/arch/arm/mach-rockchip/rv1126/Kconfig > > index ae323ee91235..64a70f61f894 100644 > > --- a/arch/arm/mach-rockchip/rv1126/Kconfig > > +++ b/arch/arm/mach-rockchip/rv1126/Kconfig > > @@ -6,8 +6,8 @@ config TARGET_RV1126_NEU2 > > Neu2: > > Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module > > based on Rockchip RV1126 from Edgeble AI. > > - Neu2 powered with Consumer grade (0 to +80 °C) RV1126 SoC. > > - Neu2k powered with Industrial grade (-40 °C to +85 °C) RV1126K SoC. > > + Neu2 powered with Consumer grade (0 to +80 C) RV1126 SoC. > > + Neu2k powered with Industrial grade (-40 C to +85 C) RV1126K SoC. > > C is the sign for coulomb which is the unit of electric charge. How > about 'deg C'? I'll note that in Linux there's seemingly nothing consistent, and I'm fine with any of "deg C" or "degrees C" or "temperature range (-40 C to +85 C)" as all of those should be clear in context. -- Tom signature.asc Description: PGP signature
Re: [PATCH] env: mmc: print MMC device being read
On Mon, Apr 15, 2024 at 02:43:57PM +0200, Quentin Schulz wrote: > From: Quentin Schulz > > This prints the MMC device being read similar to how we print the MMC > device we write to when e.g. calling saveenv. > > One of the side effects is that the boot log now shows from which MMC > device the env was loaded: > > Loading Environment from MMC... Reading from MMC(1)... OK > > This is useful to identify which MMC device the environment was loaded > from for boards where there are more than one (e.g. eMMC and SD card) > without adding some debug messages manually. > > Sadly, there's no way to know which of the default or redundant > environment is being read from env_mmc_load before env_import_redund is > called so it is printing a bit later (and possibly after error/warning > messages). > > Cc: Quentin Schulz > Signed-off-by: Quentin Schulz Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [GIT PULL] Please pull u-boot-imx-master-20240415
On Mon, Apr 15, 2024 at 09:33:40AM -0300, Fabio Estevam wrote: > Hi Tom, > > Please pull from u-boot-imx/master, thanks. > > The following changes since commit b03b49046af5dfca599d2ce8f0aafed89b97aa91: > > Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2024-04-14 > 15:58:31 -0600) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git > tags/u-boot-imx-master-20240415 > > for you to fetch changes up to 8ecb0931940cc19728d686b9dba06585f4d93709: > > clk: imx93: fix anatop base (2024-04-15 08:09:41 -0300) > > u-boot-imx-master-20240415 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [GIT PULL] Please pull u-boot-mmc master
On Mon, Apr 15, 2024 at 06:52:30PM +0900, Jaehoon Chung wrote: > Dear Tom, > > Please pull u-boot-mmc master into u-boot master branch. > If there is any problem, let me know, plz. > > BTW, I'm checking other pending patches in more detail. > After checking, I will apply them into u-boot-mmc. Sorry for too late. > > Best Regards, > Jaehoon Chung > > CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/20345 > > The following changes since commit b03b49046af5dfca599d2ce8f0aafed89b97aa91: > > Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2024-04-14 > 15:58:31 -0600) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-mmc.git master > > for you to fetch changes up to 3657ef738ad6aa2c32c569e7ae67a5557343f7d0: > > mmc: cv1800b_sdhci: Remove the unused argument (2024-04-15 17:58:59 +0900) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Pull Request: Please pull u-boot-socfpga-next-20240415
On Mon, Apr 15, 2024 at 07:34:20AM +, Chee, Tien Fong wrote: > Dear Tom, > > Please pull the SoCFPGA changes for next from u-boot-socfpga, containing: > > 1. Add option to reprogram FPGA every reboot, enable this as default in > chameleonv3 defconfig. > 2. Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG, > so the driver can be built when CONFIG_SPL_SOCFPGA_DT_REG is set in defconfig. > > > Build-tested on SoC64 & SoC32 boards. > > Best regards, > Tien Fong > > The following changes since commit b03b49046af5dfca599d2ce8f0aafed89b97aa91: > > Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2024-04-14 > 15:58:31 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-socfpga.git > tags/u-boot-socfpga-next-20240415 > > for you to fetch changes up to 27ed98d491521a637f2b4468ac021511294f897f: > > drivers: misc: Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to > CONFIG_SPL_SOCFPGA_DT_REG (2024-04-15 11:16:06 +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH v2] net: wget: fix TCP sequence number wrap around issue
If tcp_seq_num is wrap around, tcp_seq_num >= initial_data_seq_num
isn't satisfied and store_block() isn't called.
The condition has a wrap around issue, so it is fixed in this patch.
Signed-off-by: Yasuharu Shibata
Reviewed-by: Michael Trimarchi
Suggested-by: Michael Trimarchi
Reported-by: Tim Harvey
Tested-by: Fabio Estevam
---
v1 -> v2:
- Add tags in commit message
- Link to v1:
https://lore.kernel.org/u-boot/20240415130013.26721-1-yasuharu.shib...@gmail.com/
---
net/wget.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/net/wget.c b/net/wget.c
index 71bac92d84..abab371e58 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -404,9 +404,7 @@ static void wget_handler(uchar *pkt, u16 dport,
}
next_data_seq_num = tcp_seq_num + len;
- if (tcp_seq_num >= initial_data_seq_num &&
- store_block(pkt, tcp_seq_num - initial_data_seq_num,
- len) != 0) {
+ if (store_block(pkt, tcp_seq_num - initial_data_seq_num, len)
!= 0) {
wget_fail("wget: store error\n",
tcp_seq_num, tcp_ack_num, action);
net_set_state(NETLOOP_FAIL);
--
2.25.1
Re: [PATCH u-boot-mvebu 00/10] Turris Omnia DDR training changes
Hi Marek, I'm running a regression test with this patch on another Armada 385 board (Synology DS116). And it is running without problem. I noticed that there is no version bump. Is this still 14.0.0? It's kind of hard to see which version we are using without a minor revision such as 14.0.1. All the best, Tony On Mon, Apr 15, 2024 at 9:39 AM Marek Behún wrote: > > Hi Stefan, > > this series adds some changes to DDR3 training for Armada 38x and > Turris Omnia. > > - patches 1-4 are meant to allow for reducing another 10 KiB in the > SPL binary. They were also sent to mv-ddr-marvell, via PR on github, > https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/45/ > but I am told that Armada team has left Marvell, so who knows if this > will ever be merged there > - patch 5 enables this reduction for Turris Omnia > - patches 6-8 import old DDR3 training code and make some changes so > that it works with U-Boot. The reason why this is being done is > explained in patch 6 > - patch 9 glues the old DDR3 training code to current U-Boot > - patch 10 allows for dynamic selection of old DDR3 training code on > Turris Omnia, via an U-Boot environment variable > > Marek > > Marek Behún (10): > ddr: marvell: a38x: debug: return from ddr3_tip_print_log() early if > we won't print anything > ddr: marvell: a38x: debug: Remove unused variables > ddr: marvell: a38x: debug: Define DDR_VIEWER_TOOL variables only if > needed, and make them static > ddr: marvell: a38x: debug: Allow compiling with immutable debug > settings to reduce binary size > arm: mvebu: turris_omnia: Enable immutable debug settings in DDR3 > training by default > ddr: marvell: a38x: Import old DDR training code from 2017 version of > U-Boot > ddr: marvell: a38x: old: Fix some compiler warning of the old code > ddr: marvell: a38x: old: Backport immutable debug settings > arm: mvebu: a38x: Add optional support for using old DDR3 training > code > arm: mvebu: turris_omnia: Support old DDR3 training, selectable via > env var > > arch/arm/mach-mvebu/Kconfig | 15 + > arch/arm/mach-mvebu/include/mach/cpu.h|1 + > arch/arm/mach-mvebu/spl.c | 37 +- > board/CZ.NIC/turris_omnia/Makefile|1 + > board/CZ.NIC/turris_omnia/old_ddr3_training.c | 79 + > board/CZ.NIC/turris_omnia/turris_omnia.c |2 +- > configs/turris_omnia_defconfig|1 + > drivers/ddr/marvell/a38x/Makefile |2 + > drivers/ddr/marvell/a38x/ddr3_debug.c | 30 +- > drivers/ddr/marvell/a38x/ddr3_init.c |3 +- > drivers/ddr/marvell/a38x/ddr3_init.h | 43 +- > drivers/ddr/marvell/a38x/old/Makefile | 29 + > drivers/ddr/marvell/a38x/old/ddr3_a38x.c | 738 + > drivers/ddr/marvell/a38x/old/ddr3_a38x.h | 93 + > .../marvell/a38x/old/ddr3_a38x_mc_static.h| 226 ++ > .../ddr/marvell/a38x/old/ddr3_a38x_topology.h | 22 + > .../ddr/marvell/a38x/old/ddr3_a38x_training.c | 40 + > drivers/ddr/marvell/a38x/old/ddr3_debug.c | 1545 ++ > .../marvell/a38x/old/ddr3_hws_hw_training.c | 148 + > .../marvell/a38x/old/ddr3_hws_hw_training.h | 49 + > .../a38x/old/ddr3_hws_hw_training_def.h | 464 +++ > .../marvell/a38x/old/ddr3_hws_sil_training.h | 17 + > drivers/ddr/marvell/a38x/old/ddr3_init.c | 770 + > drivers/ddr/marvell/a38x/old/ddr3_init.h | 405 +++ > .../ddr/marvell/a38x/old/ddr3_logging_def.h | 101 + > .../marvell/a38x/old/ddr3_patterns_64bit.h| 924 ++ > .../ddr/marvell/a38x/old/ddr3_topology_def.h | 76 + > drivers/ddr/marvell/a38x/old/ddr3_training.c | 2651 + > .../ddr/marvell/a38x/old/ddr3_training_bist.c | 289 ++ > .../a38x/old/ddr3_training_centralization.c | 712 + > .../ddr/marvell/a38x/old/ddr3_training_db.c | 652 > .../marvell/a38x/old/ddr3_training_hw_algo.c | 686 + > .../marvell/a38x/old/ddr3_training_hw_algo.h | 14 + > .../ddr/marvell/a38x/old/ddr3_training_ip.h | 178 ++ > .../marvell/a38x/old/ddr3_training_ip_bist.h | 54 + > .../old/ddr3_training_ip_centralization.h | 15 + > .../marvell/a38x/old/ddr3_training_ip_db.h| 34 + > .../marvell/a38x/old/ddr3_training_ip_def.h | 173 ++ > .../a38x/old/ddr3_training_ip_engine.c| 1355 + > .../a38x/old/ddr3_training_ip_engine.h| 85 + > .../marvell/a38x/old/ddr3_training_ip_flow.h | 349 +++ > .../marvell/a38x/old/ddr3_training_ip_pbs.h | 41 + > .../a38x/old/ddr3_training_ip_prv_if.h| 107 + > .../a38x/old/ddr3_training_ip_static.h| 31 + > .../marvell/a38x/old/ddr3_training_leveling.c | 1837 > .../marvell/a38x/old/ddr3_training_leveling.h | 17 + > .../ddr/marvell/a38x/old/ddr3_training_pbs.c | 995 +++ > .../marvell/a38x/old/ddr3_training_static.c | 538 >
[PATCH] imx93: Move SoC and lifeclycle information to debug level
From: Fabio Estevam
The following information printed on every boot is not very
helpful for the users:
SOC: 0xa0009300
LC: 0x40040
Move them to debug() level.
Signed-off-by: Fabio Estevam
---
board/freescale/imx93_evk/spl.c | 4 ++--
board/phytec/phycore_imx93/spl.c| 4 ++--
board/variscite/imx93_var_som/spl.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 7331a20f94c8..6d5e110b2776 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -120,8 +120,8 @@ void board_init_f(ulong dummy)
if (ret) {
printf("Fail to init Sentinel API\n");
} else {
- printf("SOC: 0x%x\n", gd->arch.soc_rev);
- printf("LC: 0x%x\n", gd->arch.lifecycle);
+ debug("SOC: 0x%x\n", gd->arch.soc_rev);
+ debug("LC: 0x%x\n", gd->arch.lifecycle);
}
power_init_board();
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index f03bfee9ffa8..5efa38a14427 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -126,8 +126,8 @@ void board_init_f(ulong dummy)
if (ret) {
printf("Fail to init ELE API\n");
} else {
- printf("SOC: 0x%x\n", gd->arch.soc_rev);
- printf("LC: 0x%x\n", gd->arch.lifecycle);
+ debug("SOC: 0x%x\n", gd->arch.soc_rev);
+ debug("LC: 0x%x\n", gd->arch.lifecycle);
}
clock_init();
diff --git a/board/variscite/imx93_var_som/spl.c
b/board/variscite/imx93_var_som/spl.c
index 71f346cf77bd..8852aea156b7 100644
--- a/board/variscite/imx93_var_som/spl.c
+++ b/board/variscite/imx93_var_som/spl.c
@@ -125,8 +125,8 @@ void board_init_f(ulong dummy)
if (ret) {
printf("Fail to init ELE API\n");
} else {
- printf("SOC: 0x%x\n", gd->arch.soc_rev);
- printf("LC: 0x%x\n", gd->arch.lifecycle);
+ debug("SOC: 0x%x\n", gd->arch.soc_rev);
+ debug("LC: 0x%x\n", gd->arch.lifecycle);
}
power_init_board();
--
2.34.1
Re: [PATCH] DRAM_SUN50I_H616_TRIM_SIZE
Dne ponedeljek, 15. april 2024 ob 02:22:45 GMT +2 je Andre Przywara napisal(a):
> On Sat, 13 Apr 2024 21:43:52 +0800
> da...@189.cn wrote:
>
> Hi,
>
> thanks for sending a patch!
>
> > From: lalakii
> >
> > Add "DRAM_SUN50I_H616_TRIM_SIZE" option for 1.5gb board.
> >
> > Signed-off-by: lalakii
> > ---
> > arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
> > arch/arm/mach-sunxi/Kconfig| 7 +++
> > arch/arm/mach-sunxi/dram_sun50i_h616.c | 11 ++-
> > 3 files changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> > b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> > index a8fdda124a..2d2526fead 100644
> > --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> > +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
> > @@ -166,6 +166,7 @@ struct dram_config {
> > u8 rows;
> > u8 ranks;
> > u8 bus_full_width;
> > + bool trim_size;
> > };
> >
> > static inline int ns_to_t(int nanoseconds)
> > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > index fe89aec6b9..255a498557 100644
> > --- a/arch/arm/mach-sunxi/Kconfig
> > +++ b/arch/arm/mach-sunxi/Kconfig
> > @@ -108,6 +108,13 @@ config DRAM_SUN50I_H616_TPR12
> > default 0x0
> > help
> > TPR12 value from vendor DRAM settings.
> > +
> > +config DRAM_SUN50I_H616_TRIM_SIZE
> > +bool "H616 DRAM trim size"
> > +help
> > + Due to unknown issue, some H616 based boards may need to trim
>
> Well, it's not really an unknown issue, is it? The problem seems to be
> that the auto detection code cannot deal with the topology of the 1.5GB
> DRAM chips.
>
> The general problem with this approach is that it would need to be
> enabled at build time, which means the generated image will always trim
> the DRAM size, and would not be universal for each board anymore.
>
> So we need something to auto-detect this situation. Can you describe
> the failure mode, without this patch? Does the DRAM init code hang or
> give up already, or does this all pass, and then later on the board
> hangs or crashes when we try access the missing DRAM area?
> Maybe a small test access beyond 1.5GB would be able to check for this
> particular case?
Vendor DRAM check for 1.5 GB is pretty simple. First, it's checked if 2 GB
of RAM is detected. If so, 3 different patterns are written to 0x7000,
0xa000 and 0x8000 (in that order). Then, pattern from 0xa000 is
read. If it doesn't match to pattern written to this location, 1.5 GB is
assumed.
Best regards,
Jernej
>
> Cheers,
> Andre
>
>
> > + size a bit.
> > +
> > endif
> >
> > config SUN6I_PRCM
> > diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> > b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> > index 37c139e0ee..4598d60a57 100644
> > --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> > +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> > @@ -1349,8 +1349,15 @@ static unsigned long mctl_calc_size(const struct
> > dram_config *config)
> > {
> > u8 width = config->bus_full_width ? 4 : 2;
> >
> > + unsigned long size;
> > +
> > + size = (1ULL << (config->cols + config->rows + 3)) * width *
> > config->ranks;
> > +
> > + if (config->trim_size)
> > + size = (size * 3) / (width == 4 ? 4 : 8);
> > +
> > /* 8 banks */
> > - return (1ULL << (config->cols + config->rows + 3)) * width *
> > config->ranks;
> > + return size;
> > }
> >
> > static const struct dram_para para = {
> > @@ -1379,6 +1386,8 @@ unsigned long sunxi_dram_init(void)
> > struct sunxi_prcm_reg *const prcm =
> > (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
> > struct dram_config config;
> > + if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_TRIM_SIZE))
> > + config.trim_size = true;
> > unsigned long size;
> >
> > setbits_le32(>res_cal_ctrl, BIT(8));
>
>
[PATCH 2/5] mmc: am654_sdhci: Fix OTAP/ITAP delay values
From: Nitin Yadav
U-Boot is failing to boot class U1 UHS SD cards due to incorrect
OTAP and ITAP delay select values. Update OTAP and ITAP delay select
values from DT.
Fixes: c7d106b4eb3 ("mmc: am654_sdhci: Update output tap delay writes")
Signed-off-by: Nitin Yadav
Signed-off-by: Judith Mendez
---
drivers/mmc/am654_sdhci.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index e5ad00e2531..1dd032e1e36 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -513,12 +513,27 @@ static int j721e_4bit_sdhci_set_ios_post(struct
sdhci_host *host)
{
struct udevice *dev = host->mmc->dev;
struct am654_sdhci_plat *plat = dev_get_plat(dev);
- u32 otap_del_sel, mask, val;
+ int mode = host->mmc->selected_mode;
+ u32 otap_del_sel;
+ u32 itap_del_sel;
+ u32 mask, val;
+
+ otap_del_sel = plat->otap_del_sel[mode];
- otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
- val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
+ val = (1 << OTAPDLYENA_SHIFT) |
+ (otap_del_sel << OTAPDLYSEL_SHIFT);
+
+ itap_del_sel = plat->itap_del_sel[mode];
+
+ mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
+ val = (1 << ITAPDLYENA_SHIFT) |
+ (itap_del_sel << ITAPDLYSEL_SHIFT);
+
+ regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
+ 1 << ITAPCHGWIN_SHIFT);
regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
+ regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
plat->clkbuf_sel);
@@ -572,7 +587,7 @@ static int sdhci_am654_get_otap_delay(struct udevice *dev,
* Remove the corresponding capability if an otap-del-sel
* value is not found
*/
- for (i = MMC_HS; i <= MMC_HS_400; i++) {
+ for (i = MMC_LEGACY; i <= MMC_HS_400; i++) {
ret = dev_read_u32(dev, td[i].otap_binding,
>otap_del_sel[i]);
if (ret) {
--
2.43.2
[PATCH 4/5] mmc: am654_sdhci: Set ENDLL=1 for DDR52 mode
According to the device datasheet [0], ENDLL=1 for
DDR52 mode, so call am654_sdhci_setup_dll() and write
itapdly after since we do not carry out tuning.
[0] https://www.ti.com/lit/ds/symlink/am62p.pdf
Fixes: c964447ea3d6 ("mmc: am654_sdhci: Add support for input tap delay")
Signed-off-by: Judith Mendez
---
drivers/mmc/am654_sdhci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 38f1ad28ec4..dee56dfdbaa 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -287,12 +287,14 @@ static int am654_sdhci_set_ios_post(struct sdhci_host
*host)
regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
- if (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) {
+ if ((mode > UHS_SDR25 || mode == MMC_DDR_52) && speed >=
CLOCK_TOO_SLOW_HZ) {
ret = am654_sdhci_setup_dll(plat, speed);
if (ret)
return ret;
plat->dll_enable = true;
+ am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode],
+ plat->itap_del_ena[mode]);
} else {
am654_sdhci_setup_delay_chain(plat, mode);
plat->dll_enable = false;
--
2.43.2
[PATCH 1/5] mmc: am654_sdhci: Add tuning algorithm for delay chain
Currently the sdhci_am654 driver only supports one tuning
algorithm which should be used only when DLL is enabled. The
ITAPDLY is selected from the largest passing window and the
buffer is viewed as a circular buffer.
The new tuning algorithm should be used when the delay chain
is enabled; the ITAPDLY is selected from the largest passing
window and the buffer is not viewed as a circular buffer.
This implementation is based off of the following paper: [1].
Also add support for multiple failing windows.
[1] https://www.ti.com/lit/an/spract9/spract9.pdf
Fixes: a759abf569d4 ("mmc: am654_sdhci: Add support for software tuning")
Signed-off-by: Judith Mendez
---
drivers/mmc/am654_sdhci.c | 107 +++---
1 file changed, 89 insertions(+), 18 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 05595bdac39..e5ad00e2531 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -97,6 +97,7 @@ struct am654_sdhci_plat {
u32 strb_sel;
u32 clkbuf_sel;
u32 flags;
+ bool dll_enable;
#define DLL_PRESENTBIT(0)
#define IOMUX_PRESENT BIT(1)
#define FREQSEL_2_BIT BIT(2)
@@ -110,6 +111,12 @@ struct timing_data {
u32 capability;
};
+struct window {
+ u8 start;
+ u8 end;
+ u8 length;
+};
+
static const struct timing_data td[] = {
[MMC_LEGACY]= {"ti,otap-del-sel-legacy",
"ti,itap-del-sel-legacy",
@@ -280,8 +287,11 @@ static int am654_sdhci_set_ios_post(struct sdhci_host
*host)
ret = am654_sdhci_setup_dll(plat, speed);
if (ret)
return ret;
+
+ plat->dll_enable = true;
} else {
am654_sdhci_setup_delay_chain(plat, mode);
+ plat->dll_enable = false;
}
regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
@@ -375,38 +385,99 @@ static void am654_sdhci_write_b(struct sdhci_host *host,
u8 val, int reg)
writeb(val, host->ioaddr + reg);
}
#ifdef MMC_SUPPORTS_TUNING
-#define ITAP_MAX 32
+#define ITAPDLY_LENGTH 32
+#define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
+
+static u32 am654_sdhci_calculate_itap(struct udevice *dev, struct window
+ *fail_window, u8 num_fails, bool circular_buffer)
+{
+ u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0;
+ u8 first_fail_start = 0, last_fail_end = 0;
+ struct window pass_window = {0, 0, 0};
+ int prev_fail_end = -1;
+ u8 i;
+
+ if (!num_fails)
+ return ITAPDLY_LAST_INDEX >> 1;
+
+ if (fail_window->length == ITAPDLY_LENGTH) {
+ dev_err(dev, "No passing ITAPDLY, return 0\n");
+ return 0;
+ }
+
+ first_fail_start = fail_window->start;
+ last_fail_end = fail_window[num_fails - 1].end;
+
+ for (i = 0; i < num_fails; i++) {
+ start_fail = fail_window[i].start;
+ end_fail = fail_window[i].end;
+ pass_length = start_fail - (prev_fail_end + 1);
+
+ if (pass_length > pass_window.length) {
+ pass_window.start = prev_fail_end + 1;
+ pass_window.length = pass_length;
+ }
+ prev_fail_end = end_fail;
+ }
+
+ if (!circular_buffer)
+ pass_length = ITAPDLY_LAST_INDEX - last_fail_end;
+ else
+ pass_length = ITAPDLY_LAST_INDEX - last_fail_end +
first_fail_start;
+
+ if (pass_length > pass_window.length) {
+ pass_window.start = last_fail_end + 1;
+ pass_window.length = pass_length;
+ }
+
+ if (!circular_buffer)
+ itap = pass_window.start + (pass_window.length >> 1);
+ else
+ itap = (pass_window.start + (pass_window.length >> 1)) %
ITAPDLY_LENGTH;
+
+ return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap;
+}
+
static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
{
struct udevice *dev = mmc->dev;
struct am654_sdhci_plat *plat = dev_get_plat(dev);
- int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
- u32 itap;
+ struct window fail_window[ITAPDLY_LENGTH];
+ u8 curr_pass, itap;
+ u8 fail_index = 0;
+ u8 prev_pass = 1;
+
+ memset(fail_window, 0, sizeof(fail_window));
/* Enable ITAPDLY */
regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
1 << ITAPDLYENA_SHIFT);
- for (itap = 0; itap < ITAP_MAX; itap++) {
+ for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
am654_sdhci_write_itapdly(plat, itap);
- cur_val = !mmc_send_tuning(mmc, opcode, NULL);
- if (cur_val && !prev_val)
- pass_window = itap;
+ curr_pass = !mmc_send_tuning(mmc, opcode, NULL);
-
[PATCH 0/5] Fix MMC tuning algorithm
The following patch series includes a MMC tuning algorithm fix according to the following published paper [0]. This seris also includes fixes for OTAP/ITAP delay values in j721e_4bit_sdhci_set_ios_post and for HS400 mode. For DDR52 mode, also set ENDLL=1 and call am654_sdhci_setup_dll() instead of am654_sdhci_setup_delay_chain() according to device datasheet[1]. [0] https://www.ti.com/lit/an/spract9/spract9.pdf [1] https://www.ti.com/lit/ds/symlink/am62p.pdf Judith Mendez (4): mmc: am654_sdhci: Add tuning algorithm for delay chain mmc: am654_sdhci: Add itap_del_ena[] to store itapdlyena bit mmc: am654_sdhci: Set ENDLL=1 for DDR52 mode mmc: am654_sdhci: Fix ITAPDLY for HS400 timing Nitin Yadav (1): mmc: am654_sdhci: Fix OTAP/ITAP delay values drivers/mmc/am654_sdhci.c | 170 +++--- 1 file changed, 138 insertions(+), 32 deletions(-) base-commit: 27795dd717dadc73091e1b4d6c50952b93aaa819 -- 2.43.2
[PATCH 5/5] mmc: am654_sdhci: Fix ITAPDLY for HS400 timing
At HS400 mode the ITAPDLY value is that from High Speed mode
which is incorrect and may cause boot failures.
The ITAPDLY for HS400 speed mode should be the same as ITAPDLY
as HS200 timing after tuning is executed. Add the functionality
to save ITAPDLY from HS200 tuning and save as HS400 ITAPDLY.
Fixes: c964447ea3d6 ("mmc: am654_sdhci: Add support for input tap delay")
Signed-off-by: Judith Mendez
---
drivers/mmc/am654_sdhci.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index dee56dfdbaa..ce3813ea3d0 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -293,6 +293,11 @@ static int am654_sdhci_set_ios_post(struct sdhci_host
*host)
return ret;
plat->dll_enable = true;
+ if (mode == MMC_HS_400) {
+ plat->itap_del_ena[mode] = 0x1;
+ plat->itap_del_sel[mode] = plat->itap_del_sel[mode - 1];
+ }
+
am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode],
plat->itap_del_ena[mode]);
} else {
@@ -484,6 +489,9 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
itap = am654_sdhci_calculate_itap(dev, fail_window, fail_index,
plat->dll_enable);
+ /* Save ITAPDLY */
+ plat->itap_del_sel[mode] = itap;
+
am654_sdhci_write_itapdly(plat, itap, plat->itap_del_ena[mode]);
return 0;
--
2.43.2
[PATCH 3/5] mmc: am654_sdhci: Add itap_del_ena[] to store itapdlyena bit
Set itap_del_ena if ITAPDLY is found in DT or if the tuning
algorithm was executed and found the optimal ITAPDLY. Add the
functionality to save ITAPDLYENA that can be referenced later
by storing the bit in array itap_del_ena[].
Signed-off-by: Judith Mendez
---
drivers/mmc/am654_sdhci.c | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 1dd032e1e36..38f1ad28ec4 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -92,6 +92,7 @@ struct am654_sdhci_plat {
bool non_removable;
u32 otap_del_sel[MMC_MODES_END];
u32 itap_del_sel[MMC_MODES_END];
+ u32 itap_del_ena[MMC_MODES_END];
u32 trm_icp;
u32 drv_strength;
u32 strb_sel;
@@ -223,8 +224,10 @@ static int am654_sdhci_setup_dll(struct am654_sdhci_plat
*plat,
}
static void am654_sdhci_write_itapdly(struct am654_sdhci_plat *plat,
- u32 itapdly)
+ u32 itapdly, u32 enable)
{
+ regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
+ enable << ITAPDLYENA_SHIFT);
/* Set ITAPCHGWIN before writing to ITAPDLY */
regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
1 << ITAPCHGWIN_SHIFT);
@@ -242,7 +245,8 @@ static void am654_sdhci_setup_delay_chain(struct
am654_sdhci_plat *plat,
mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
- am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode]);
+ am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode],
+ plat->itap_del_ena[mode]);
}
static int am654_sdhci_set_ios_post(struct sdhci_host *host)
@@ -443,6 +447,7 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
struct udevice *dev = mmc->dev;
struct am654_sdhci_plat *plat = dev_get_plat(dev);
struct window fail_window[ITAPDLY_LENGTH];
+ int mode = mmc->selected_mode;
u8 curr_pass, itap;
u8 fail_index = 0;
u8 prev_pass = 1;
@@ -450,11 +455,10 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
memset(fail_window, 0, sizeof(fail_window));
/* Enable ITAPDLY */
- regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
- 1 << ITAPDLYENA_SHIFT);
+ plat->itap_del_ena[mode] = 0x1;
for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
- am654_sdhci_write_itapdly(plat, itap);
+ am654_sdhci_write_itapdly(plat, itap, plat->itap_del_ena[mode]);
curr_pass = !mmc_send_tuning(mmc, opcode, NULL);
@@ -478,7 +482,7 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
itap = am654_sdhci_calculate_itap(dev, fail_window, fail_index,
plat->dll_enable);
- am654_sdhci_write_itapdly(plat, itap);
+ am654_sdhci_write_itapdly(plat, itap, plat->itap_del_ena[mode]);
return 0;
}
@@ -515,6 +519,7 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host
*host)
struct am654_sdhci_plat *plat = dev_get_plat(dev);
int mode = host->mmc->selected_mode;
u32 otap_del_sel;
+ u32 itap_del_ena;
u32 itap_del_sel;
u32 mask, val;
@@ -524,10 +529,11 @@ static int j721e_4bit_sdhci_set_ios_post(struct
sdhci_host *host)
val = (1 << OTAPDLYENA_SHIFT) |
(otap_del_sel << OTAPDLYSEL_SHIFT);
+ itap_del_ena = plat->itap_del_ena[mode];
itap_del_sel = plat->itap_del_sel[mode];
mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
- val = (1 << ITAPDLYENA_SHIFT) |
+ val = (itap_del_ena << ITAPDLYENA_SHIFT) |
(itap_del_sel << ITAPDLYSEL_SHIFT);
regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
@@ -599,9 +605,13 @@ static int sdhci_am654_get_otap_delay(struct udevice *dev,
cfg->host_caps &= ~td[i].capability;
}
- if (td[i].itap_binding)
- dev_read_u32(dev, td[i].itap_binding,
->itap_del_sel[i]);
+ if (td[i].itap_binding) {
+ ret = dev_read_u32(dev, td[i].itap_binding,
+ >itap_del_sel[i]);
+
+ if (!ret)
+ plat->itap_del_ena[i] = 0x1;
+ }
}
return 0;
--
2.43.2
Re: [PATCH v1] arm: dts: k3-am625-verdin: add tifsstub to tispl.bin
Hi Francesco
On Mon, 2024-04-15 at 09:54 +0200, Francesco Dolcini wrote:
> From: Parth Pancholi
>
> Adds tifsstub binaries, this is required for deepsleep functionality.
>
> This implements the same change as commit 128f81290b7d ("arm: dts: k3:
> binman: am625: add support for signing TIFSSTUB Images") did for TI AM62
> SK board.
>
> Signed-off-by: Parth Pancholi
> Signed-off-by: Francesco Dolcini
Acked-by: Marcel Ziswiler
Just one minor note in-lined further below.
> ---
> .../dts/k3-am625-verdin-wifi-dev-binman.dtsi | 140 +-
> 1 file changed, 138 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
> b/arch/arm/dts/k3-am625-verdin-wifi-dev-
> binman.dtsi
> index 6f5845024f27..a9b86b61e53e 100644
> --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
> +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
> @@ -150,12 +150,107 @@
> filename =
> "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
> };
> };
> +
> + tifsstub-hs {
> + filename = "tifsstub.bin_hs";
> + ti-secure-rom {
> + content = <_hs_cert>;
> + core = "secure";
> + load = <0x4>;
> + sw-rev = ;
> + keyfile = "custMpk.pem";
> + countersign;
> + tifsstub;
> + };
> + tifsstub_hs_cert: tifsstub-hs-cert.bin {
> + filename =
> "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin";
> + type = "blob-ext";
> + optional;
> + };
> + tifsstub_hs_enc: tifsstub-hs-enc.bin {
> + filename =
> "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin";
> + type = "blob-ext";
> + optional;
> + };
> + };
> +
> + tifsstub-fs {
> + filename = "tifsstub.bin_fs";
> + tifsstub_fs_cert: tifsstub-fs-cert.bin {
> + filename =
> "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin";
> + type = "blob-ext";
> + optional;
> + };
> + tifsstub_fs_enc: tifsstub-fs-enc.bin {
> + filename =
> "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin";
> + type = "blob-ext";
> + optional;
> + };
> +
> + };
> +
> + tifsstub-gp {
> + filename = "tifsstub.bin_gp";
> + ti-secure-rom {
> + content = <_gp>;
> + core = "secure";
> + load = <0x6>;
> + sw-rev = ;
> + keyfile = "ti-degenerate-key.pem";
> + tifsstub;
> + };
> + tifsstub_gp: tifsstub-gp.bin {
> + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin";
> + type = "blob-ext";
> + optional;
> + };
> + };
> +
> ti-spl {
> insert-template = <_spl_template>;
>
> fit {
>
We also might want to clean-up this spurious newline being a remnant of
commit 4509b9ff0b8c ("arm: dts: k3-*-binman: Move to using templated FITs").
> images {
> + tifsstub-hs {
> + description = "TIFSSTUB";
> + type = "firmware";
> + arch = "arm32";
> + compression = "none";
> + os = "tifsstub-hs";
> + load = <0x9dc0>;
> + entry = <0x9dc0>;
> + blob-ext {
> + filename = "tifsstub.bin_hs";
> + };
> + };
> +
> + tifsstub-fs {
> + description = "TIFSSTUB";
> + type = "firmware";
> + arch = "arm32";
> + compression = "none";
> + os = "tifsstub-fs";
> + load = <0x9dc0>;
> + entry = <0x9dc0>;
> + blob-ext {
> + filename = "tifsstub.bin_fs";
> + };
> + };
> +
> + tifsstub-gp {
> + description = "TIFSSTUB";
> + type = "firmware";
> + arch = "arm32";
Re: [PATCH 0/4] Cleanup K3 binman templating
Hi Tom, On 12-Apr-24 8:20 PM, Tom Rini wrote: On Fri, Mar 22, 2024 at 06:40:07PM +0530, Neha Malcom Francis wrote: This series does primarily three things: 1. Split out the common J721E defconfig for both EVM and SK 2. Cleanup k3-j721e-binman.dtsi to be SoC specific binman nodes and -u-boot.dtsi files of the respective boards can pick and edit according to their board. This is based on the discussion [1] and this is the primary goal of this series 3. Move J721E EVM and SK to using OF_UPSTREAM This series depends on series [2] and patch [3] which implement OF_UPSTREAM. Also received input from Nishanth to clean up the unnecessary artifacts in the final build directory (maybe populate them in another directory), working on that as well but didn't want to delay v1 further considering I'm modifying a bunch of board builds and would like some friendly build tests and boot tests for them. Please rebase this on top of current master, thanks. Will send out v2! -- Thanking You Neha Malcom Francis
Re: [PATCH v2 0/3] qcom: serial_msm: calculate UARTDM_CSR automatically
On Mon, 15 Apr 2024 16:03:37 +0100, Caleb Connolly wrote: > The msm serial UART controller has a bit clock divider register which > much be programmed based on the UART clock. This changes per soc and > currently is expected to be specified in DT or otherwise selected per > board. > > This series fixes the apq8016 and ipq4019 clock drivers to return the > programmed UART clock rate in clk_set_rate(), it then uses this clock > rate and the hardcoded baud rate supported by this driver to calculate > the correct value for the UARTDM_CSR register. > > [...] Applied, thanks! [1/3] clk/qcom: apq8016: return valid rate when setting UART clock commit: f191853d77899c8a845f20f62068c4ee68d2a020 [2/3] clk/qcom: ipq4019: return valid rate when setting UART clock commit: b49b68909b5f4030869051073857d086c5292461 [3/3] serial: msm: calculate bit clock divider commit: 1aadf1ebc32c8bf7f4eae9ab2abaf63c1fea7d4f Best regards, -- // Caleb (they/them)
Re: (subset) [PATCH 1/3] serial: allow selecting MSM debug UART with ARCH_IPQ40XX
On Mon, 15 Apr 2024 12:49:25 +0200, Robert Marko wrote: > Currently, DEBUG_UART_MSM depends on ARCH_SNAPDRAGON only, but IPQ40XX > devices also use the same UART HW so they can also use the debug UART. > > So, allow selecting DEBUG_UART_MSM when using ARCH_IPQ40XX as well. > > Applied, thanks! [1/3] serial: allow selecting MSM debug UART with ARCH_IPQ40XX commit: aa7fdad4c87d5c665e0f1b74cf7986768d452a4e [2/3] serial: msm_serial: remove .clk_rate from debug UART commit: aaba69b461ff7c3118272964d3a807a030277e28 Best regards, -- // Caleb (they/them)
Re: [PATCH v6 0/5] imx93: Conver to OF_UPSTREAM
Hey, > Do I need to switch back to only convert i.MX93 11x11 EVK to > OF_UPSTREM? That could be an idea. I can take over the switch for the other devices when I have some time to perform the debugging. Mathieu
[PATCH u-boot-mvebu 10/10] arm: mvebu: turris_omnia: Support old DDR3 training, selectable via env var
Support old DDR3 training code on Turris Omnia, selectable by U-Boot
enviroment variable.
Users experiencing DDR3 initialization failures or random crashes of the
operating system due to incorrect DDR3 configuration can select the old
DDR3 training implementation to fix those issues by setting the
environment variable
env set omnia_ddr3_training old
env save
Signed-off-by: Marek Behún
---
arch/arm/mach-mvebu/Kconfig | 1 +
board/CZ.NIC/turris_omnia/Makefile| 1 +
board/CZ.NIC/turris_omnia/old_ddr3_training.c | 79 +++
board/CZ.NIC/turris_omnia/turris_omnia.c | 2 +-
4 files changed, 82 insertions(+), 1 deletion(-)
create mode 100644 board/CZ.NIC/turris_omnia/old_ddr3_training.c
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e377e8a48a..4a8328760e 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -149,6 +149,7 @@ config TARGET_TURRIS_OMNIA
select SPL_SYS_MALLOC_SIMPLE
select SYS_I2C_MVTWSI
select ATSHA204A
+ select ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
config TARGET_TURRIS_MOX
bool "Support CZ.NIC's Turris Mox / RIPE Atlas Probe"
diff --git a/board/CZ.NIC/turris_omnia/Makefile
b/board/CZ.NIC/turris_omnia/Makefile
index 341378b4e5..28142cca7e 100644
--- a/board/CZ.NIC/turris_omnia/Makefile
+++ b/board/CZ.NIC/turris_omnia/Makefile
@@ -3,3 +3,4 @@
# Copyright (C) 2017 Marek Behún
obj-y := turris_omnia.o ../turris_atsha_otp.o ../turris_common.o
+obj-$(CONFIG_SPL_BUILD)+= old_ddr3_training.o
diff --git a/board/CZ.NIC/turris_omnia/old_ddr3_training.c
b/board/CZ.NIC/turris_omnia/old_ddr3_training.c
new file mode 100644
index 00..f7e89c58d4
--- /dev/null
+++ b/board/CZ.NIC/turris_omnia/old_ddr3_training.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Marek Behún
+ */
+
+#include
+#include
+#include
+
+#include "../drivers/ddr/marvell/a38x/old/ddr3_init.h"
+
+static struct hws_topology_map board_topology_map_1g = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1600K,/* speed_bin */
+ BUS_WIDTH_16, /* memory_width */
+ MEM_4G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_NORMAL,/* temperature */
+ HWS_TIM_2T} }, /* timing (force 2t) */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+static struct hws_topology_map board_topology_map_2g = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1600K,/* speed_bin */
+ BUS_WIDTH_16, /* memory_width */
+ MEM_8G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_NORMAL,/* temperature */
+ HWS_TIM_2T} }, /* timing (force 2t) */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+/* defined in turris_omnia.c */
+extern int omnia_get_ram_size_gb(void);
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+ if (omnia_get_ram_size_gb() == 2)
+ return _topology_map_2g;
+ else
+ return _topology_map_1g;
+}
+
+bool board_use_old_ddr3_training(void)
+{
+ const char *env_val = NULL;
+
+ if (CONFIG_IS_ENABLED(ENV_SUPPORT) && !env_init())
+ env_val = env_get("omnia_ddr3_training");
+
+ if (env_val && !strcmp(env_val, "old")) {
+ printf("Using old DDR3 training implementation\n");
+ return true;
+ }
+
+ return false;
+}
+
+__weak u32 sys_env_get_topology_update_info(struct topology_update_info *tui)
+{
+ return MV_OK;
+}
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 3b7a71bdad..225c6f4bc5 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -465,7 +465,7 @@ static bool omnia_read_eeprom(struct omnia_eeprom *oep)
return true;
}
-static int omnia_get_ram_size_gb(void)
+int omnia_get_ram_size_gb(void)
{
static int ram_size;
struct omnia_eeprom oep;
--
2.43.2
[PATCH u-boot-mvebu 09/10] arm: mvebu: a38x: Add optional support for using old DDR3 training code
Add optional support for using old DDR3 training code from 2017.
The code lives in drivers/ddr/marvell/a38x/old/. To prevent symbol
clashing with new DDR3 training code, a special header which renames all
clashing symbols via macros is included and the symbols are prefixed
with 'old_'.
If old DDR3 training support is selected for a board, then the SPL
initialization code calls a new function
board_use_old_ddr3_training()
to check whether it should use old DDR3 training code. The default
weak implementation returns false, defaulting to new DDR3 training code.
Boards that wish to support this need to select the
ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
config option and implement the old version of DDR topology provider,
ddr3_get_topology_map().
Signed-off-by: Marek Behún
---
arch/arm/mach-mvebu/Kconfig | 4 +
arch/arm/mach-mvebu/include/mach/cpu.h| 1 +
arch/arm/mach-mvebu/spl.c | 37 ++-
drivers/ddr/marvell/a38x/Makefile | 2 +
drivers/ddr/marvell/a38x/old/Makefile | 11 +
.../marvell/a38x/old/glue_symbol_renames.h| 247 ++
6 files changed, 293 insertions(+), 9 deletions(-)
create mode 100644 drivers/ddr/marvell/a38x/old/glue_symbol_renames.h
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index a320793a30..e377e8a48a 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -37,6 +37,10 @@ config ARMADA_38X_HS_IMPEDANCE_THRESH
default 0x6
range 0x0 0x7
+config ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
+ bool
+ depends on ARMADA_38X
+
config ARMADA_XP
bool
select ARMADA_32BIT
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h
b/arch/arm/mach-mvebu/include/mach/cpu.h
index 904e7157ba..af6ce2920e 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -174,6 +174,7 @@ int serdes_phy_config(void);
* drivers/ddr/marvell
*/
int ddr3_init(void);
+int old_ddr3_init(void);
/* Auto Voltage Scaling */
#if defined(CONFIG_ARMADA_38X)
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 79f8877745..fd1030b33b 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -314,6 +314,33 @@ int board_return_to_bootrom(struct spl_image_info
*spl_image,
hang();
}
+#if !defined(CONFIG_ARMADA_375)
+__weak bool board_use_old_ddr3_training(void)
+{
+ return false;
+}
+
+static void ddr3_init_or_fail(void)
+{
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING) &&
+ board_use_old_ddr3_training())
+ ret = old_ddr3_init();
+ else
+ ret = ddr3_init();
+
+ if (ret) {
+ printf("ddr3 init failed: %d\n", ret);
+ if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&
+ get_boot_device() != BOOT_DEVICE_UART)
+ reset_cpu();
+ else
+ hang();
+ }
+}
+#endif
+
void board_init_f(ulong dummy)
{
int ret;
@@ -348,15 +375,7 @@ void board_init_f(ulong dummy)
serdes_phy_config();
/* Setup DDR */
- ret = ddr3_init();
- if (ret) {
- printf("ddr3_init() failed: %d\n", ret);
- if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&
- get_boot_device() != BOOT_DEVICE_UART)
- reset_cpu();
- else
- hang();
- }
+ ddr3_init_or_fail();
#endif
/* Initialize Auto Voltage Scaling */
diff --git a/drivers/ddr/marvell/a38x/Makefile
b/drivers/ddr/marvell/a38x/Makefile
index fcfb615686..4e8a9d190d 100644
--- a/drivers/ddr/marvell/a38x/Makefile
+++ b/drivers/ddr/marvell/a38x/Makefile
@@ -18,6 +18,8 @@ obj-$(CONFIG_SPL_BUILD) += mv_ddr_spd.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_topology.o
obj-$(CONFIG_SPL_BUILD) += xor.o
+obj-$(CONFIG_ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING) += old/
+
ifdef CONFIG_DDR4
obj-$(CONFIG_SPL_BUILD) += mv_ddr4_mpr_pda_if.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training.o
diff --git a/drivers/ddr/marvell/a38x/old/Makefile
b/drivers/ddr/marvell/a38x/old/Makefile
index e7b723bb24..1645a79b40 100644
--- a/drivers/ddr/marvell/a38x/old/Makefile
+++ b/drivers/ddr/marvell/a38x/old/Makefile
@@ -16,3 +16,14 @@ obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_static.o
+
+define IncludeSymbolRename
+ CFLAGS_$(1) = -include
$(srctree)/drivers/ddr/marvell/a38x/old/glue_symbol_renames.h
+endef
+
+$(foreach obj,$(obj-y),$(eval $(call IncludeSymbolRename,$(obj
+
+# The old version of DDR training fails weirdly on some boards if the whole
+# driver is compiled with LTO. It seems to work if at least ddr3_init.c is
+# compiled without LTO.
[PATCH u-boot-mvebu 08/10] ddr: marvell: a38x: old: Backport immutable debug settings
Backport the option to compile with immutable debug settings also to
the old implementation of the DDR3 training code.
The original PR for mv-ddr-marvell can be seen at
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/45/
Signed-off-by: Marek Behún
---
drivers/ddr/marvell/a38x/old/ddr3_debug.c | 32 ++
drivers/ddr/marvell/a38x/old/ddr3_init.c | 3 +-
drivers/ddr/marvell/a38x/old/ddr3_init.h | 40 ++-
3 files changed, 52 insertions(+), 23 deletions(-)
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_debug.c
b/drivers/ddr/marvell/a38x/old/ddr3_debug.c
index a704a3e9d3..e1ae46dc82 100644
--- a/drivers/ddr/marvell/a38x/old/ddr3_debug.c
+++ b/drivers/ddr/marvell/a38x/old/ddr3_debug.c
@@ -13,13 +13,15 @@
#include "ddr3_init.h"
+#if !defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
u8 is_reg_dump = 0;
u8 debug_pbs = DEBUG_LEVEL_ERROR;
+#endif
/*
* API to change flags outside of the lib
*/
-#ifndef SILENT_LIB
+#if !defined(SILENT_LIB) && !defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
/* Debug flags for other Training modules */
u8 debug_training_static = DEBUG_LEVEL_ERROR;
u8 debug_training = DEBUG_LEVEL_ERROR;
@@ -84,12 +86,13 @@ void ddr3_hws_set_log_level(enum ddr_lib_debug_block block,
u8 level)
#endif
struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
-u8 is_default_centralization = 0;
-u8 is_tune_result = 0;
-u8 is_validate_window_per_if = 0;
-u8 is_validate_window_per_pup = 0;
-u8 sweep_cnt = 1;
-u32 is_bist_reset_bit = 1;
+
+#if 0
+static u8 is_validate_window_per_if = 0;
+static u8 is_validate_window_per_pup = 0;
+static u8 sweep_cnt = 1;
+#endif
+
static struct hws_xsb_info xsb_info[HWS_MAX_DEVICE_NUM];
/*
@@ -292,6 +295,7 @@ int print_device_info(u8 dev_num)
return MV_OK;
}
+#if 0
void hws_ddr3_tip_sweep_test(int enable)
{
if (enable) {
@@ -304,6 +308,7 @@ void hws_ddr3_tip_sweep_test(int enable)
}
}
#endif
+#endif
char *ddr3_tip_convert_tune_result(enum hws_result tune_result)
{
@@ -327,6 +332,7 @@ int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
u32 if_id = 0;
struct hws_topology_map *tm = ddr3_get_topology_map();
+#if 0
#ifndef EXCLUDE_SWITCH_DEBUG
if ((is_validate_window_per_if != 0) ||
(is_validate_window_per_pup != 0)) {
@@ -347,8 +353,18 @@ int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
ddr3_tip_reg_dump(dev_num);
}
+#endif
#endif
+ /* return early if we won't print anything anyway */
+ if (
+#if defined(SILENT_LIB)
+ 1 ||
+#endif
+ debug_training < DEBUG_LEVEL_INFO) {
+ return MV_OK;
+ }
+
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_ACTIVE(tm->if_act_mask, if_id);
@@ -789,6 +805,7 @@ int ddr3_tip_print_adll(void)
return MV_OK;
}
+#if 0
/*
* Set attribute value
*/
@@ -1156,6 +1173,7 @@ static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id,
u32 value, u32 **ptr)
return MV_OK;
}
+#endif
#ifndef EXCLUDE_SWITCH_DEBUG
/*
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_init.c
b/drivers/ddr/marvell/a38x/old/ddr3_init.c
index 55baad498a..7230bc2a86 100644
--- a/drivers/ddr/marvell/a38x/old/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/old/ddr3_init.c
@@ -386,7 +386,8 @@ int ddr3_init(void)
return status;
/* Set log level for training lib */
- ddr3_hws_set_log_level(DEBUG_BLOCK_ALL, DEBUG_LEVEL_ERROR);
+ if (!IS_ENABLED(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS))
+ ddr3_hws_set_log_level(DEBUG_BLOCK_ALL, DEBUG_LEVEL_ERROR);
/* Start New Training IP */
status = ddr3_hws_hw_training();
diff --git a/drivers/ddr/marvell/a38x/old/ddr3_init.h
b/drivers/ddr/marvell/a38x/old/ddr3_init.h
index ad95cc9ef8..5090cf97a7 100644
--- a/drivers/ddr/marvell/a38x/old/ddr3_init.h
+++ b/drivers/ddr/marvell/a38x/old/ddr3_init.h
@@ -152,17 +152,38 @@ enum log_level {
};
/* Globals */
-extern u8 debug_training;
+#if defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
+static const u8 is_reg_dump = 0;
+static const u8 debug_training_static = DEBUG_LEVEL_ERROR;
+static const u8 debug_training = DEBUG_LEVEL_ERROR;
+static const u8 debug_leveling = DEBUG_LEVEL_ERROR;
+static const u8 debug_centralization = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_ip = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_bist = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_hw_alg = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_access = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_a38x = DEBUG_LEVEL_ERROR;
+static const u8 debug_pbs = DEBUG_LEVEL_ERROR;
+#else /* !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
extern u8 is_reg_dump;
+extern u8 debug_training_static;
+extern u8 debug_training;
+extern u8 debug_leveling;
+extern u8 debug_centralization;
+extern u8
[PATCH u-boot-mvebu 07/10] ddr: marvell: a38x: old: Fix some compiler warning of the old code
Fix some compilation warning in the old DDR training code. Signed-off-by: Marek Behún --- drivers/ddr/marvell/a38x/old/ddr3_a38x.c | 1 + drivers/ddr/marvell/a38x/old/ddr3_init.h | 2 ++ drivers/ddr/marvell/a38x/old/ddr3_training.c | 1 + drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.c | 1 + drivers/ddr/marvell/a38x/old/ddr3_training_leveling.c | 1 + 5 files changed, 6 insertions(+) diff --git a/drivers/ddr/marvell/a38x/old/ddr3_a38x.c b/drivers/ddr/marvell/a38x/old/ddr3_a38x.c index c082122f25..32a14ca4c9 100644 --- a/drivers/ddr/marvell/a38x/old/ddr3_a38x.c +++ b/drivers/ddr/marvell/a38x/old/ddr3_a38x.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "ddr3_init.h" diff --git a/drivers/ddr/marvell/a38x/old/ddr3_init.h b/drivers/ddr/marvell/a38x/old/ddr3_init.h index 8cb08864c2..ad95cc9ef8 100644 --- a/drivers/ddr/marvell/a38x/old/ddr3_init.h +++ b/drivers/ddr/marvell/a38x/old/ddr3_init.h @@ -291,7 +291,9 @@ extern struct cl_val_per_freq cas_latency_table[]; extern u32 target_freq; extern struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM]; extern u32 clamp_tbl[]; +#if 0 extern u32 init_freq; +#endif /* list of allowed frequency listed in order of enum hws_ddr_freq */ extern u32 freq_val[]; extern u8 debug_training_static; diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training.c b/drivers/ddr/marvell/a38x/old/ddr3_training.c index e70ca4b425..572a69d45a 100644 --- a/drivers/ddr/marvell/a38x/old/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/old/ddr3_training.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "ddr3_init.h" diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.c index 011824ab42..ee789f0993 100644 --- a/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/old/ddr3_training_ip_engine.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "ddr3_init.h" diff --git a/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.c index 3c40f198e7..c5043eefa3 100644 --- a/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.c +++ b/drivers/ddr/marvell/a38x/old/ddr3_training_leveling.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "ddr3_init.h" -- 2.43.2
[PATCH u-boot-mvebu 05/10] arm: mvebu: turris_omnia: Enable immutable debug settings in DDR3 training by default
Save 10 KiB in Turris Omnia's SPL binary by enabling immutable debug settings for DDR3 training code. Signed-off-by: Marek Behún --- configs/turris_omnia_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index f2b39115fe..02edd335c1 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff CONFIG_TARGET_TURRIS_OMNIA=y +CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS=y CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y CONFIG_MVEBU_EFUSE_VHV_GPIO="mcu_56" CONFIG_MVEBU_EFUSE_VHV_GPIO_ACTIVE_LOW=y -- 2.43.2
[PATCH u-boot-mvebu 04/10] ddr: marvell: a38x: debug: Allow compiling with immutable debug settings to reduce binary size
Allow compiling with immutable debug settings:
- DEBUG_LEVEL is always set to DEBUG_LEVEL_ERROR
- register dumps are disabled
This can save around 10 KiB of space in the resulting binary, which is a
lot in U-Boot SPL.
Signed-off-by: Marek Behún
---
arch/arm/mach-mvebu/Kconfig | 10 +++
drivers/ddr/marvell/a38x/ddr3_debug.c | 9 --
drivers/ddr/marvell/a38x/ddr3_init.c | 3 +-
drivers/ddr/marvell/a38x/ddr3_init.h | 42 ++-
4 files changed, 53 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index f15d3cc5ed..a320793a30 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -250,6 +250,16 @@ config DDR_LOG_LEVEL
At level 3, rovides the windows margin of each DQ as a results of
DQS centeralization.
+config DDR_IMMUTABLE_DEBUG_SETTINGS
+ bool "Immutable DDR debug level (always DEBUG_LEVEL_ERROR)"
+ depends on ARMADA_38X
+ help
+ Makes the DDR training code debug level settings immutable.
+ The debug level setting from board topology definition is ignored.
+ The debug level is always set to DEBUG_LEVEL_ERROR and register
+ dumps are disabled.
+ This can save around 10 KiB of space in SPL binary.
+
config DDR_RESET_ON_TRAINING_FAILURE
bool "Reset the board on DDR training failure instead of hanging"
depends on ARMADA_38X || ARMADA_XP
diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c
b/drivers/ddr/marvell/a38x/ddr3_debug.c
index d32d42c408..0b65168d82 100644
--- a/drivers/ddr/marvell/a38x/ddr3_debug.c
+++ b/drivers/ddr/marvell/a38x/ddr3_debug.c
@@ -7,18 +7,21 @@
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
+#if !defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
u8 is_reg_dump = 0;
u8 debug_pbs = DEBUG_LEVEL_ERROR;
+#endif
/*
* API to change flags outside of the lib
*/
-#if defined(SILENT_LIB)
+#if defined(SILENT_LIB) || defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
{
/* do nothing */
}
-#else /* SILENT_LIB */
+#else /* !SILENT_LIB && !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
+
/* Debug flags for other Training modules */
u8 debug_training_static = DEBUG_LEVEL_ERROR;
u8 debug_training = DEBUG_LEVEL_ERROR;
@@ -104,7 +107,7 @@ void ddr3_hws_set_log_level(enum ddr_lib_debug_block block,
u8 level)
#endif /* CONFIG_DDR4 */
}
}
-#endif /* SILENT_LIB */
+#endif /* !SILENT_LIB && !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
#if defined(DDR_VIEWER_TOOL)
static char *convert_freq(enum mv_ddr_freq freq);
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c
b/drivers/ddr/marvell/a38x/ddr3_init.c
index 27eb3ac173..7c5147f474 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -41,7 +41,8 @@ int ddr3_init(void)
mv_ddr_pre_training_soc_config(ddr_type);
/* Set log level for training library */
- mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
+ if (!IS_ENABLED(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS))
+ mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
mv_ddr_early_init();
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h
b/drivers/ddr/marvell/a38x/ddr3_init.h
index 9288073a78..b513a13c53 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.h
+++ b/drivers/ddr/marvell/a38x/ddr3_init.h
@@ -45,15 +45,46 @@ enum log_level {
#define MISL_PHY_ODT_N_OFFS0x0
/* Globals */
-extern u8 debug_training, debug_calibration, debug_ddr4_centralization,
- debug_tap_tuning, debug_dm_tuning;
+#if defined(CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS)
+static const u8 is_reg_dump = 0;
+static const u8 debug_training_static = DEBUG_LEVEL_ERROR;
+static const u8 debug_training = DEBUG_LEVEL_ERROR;
+static const u8 debug_leveling = DEBUG_LEVEL_ERROR;
+static const u8 debug_centralization = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_ip = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_bist = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_hw_alg = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_access = DEBUG_LEVEL_ERROR;
+static const u8 debug_training_device = DEBUG_LEVEL_ERROR;
+static const u8 debug_pbs = DEBUG_LEVEL_ERROR;
+
+static const u8 debug_tap_tuning = DEBUG_LEVEL_ERROR;
+static const u8 debug_calibration = DEBUG_LEVEL_ERROR;
+static const u8 debug_ddr4_centralization = DEBUG_LEVEL_ERROR;
+static const u8 debug_dm_tuning = DEBUG_LEVEL_ERROR;
+#else /* !CONFIG_DDR_IMMUTABLE_DEBUG_SETTINGS */
extern u8 is_reg_dump;
+extern u8 debug_training_static;
+extern u8 debug_training;
+extern u8 debug_leveling;
+extern u8 debug_centralization;
+extern u8 debug_training_ip;
+extern u8 debug_training_bist;
+extern u8 debug_training_hw_alg;
+extern u8 debug_training_access;
+extern u8 debug_training_device;
+extern u8 debug_pbs;
+
+extern u8 debug_tap_tuning;
+extern u8 debug_calibration;
+extern u8
[PATCH u-boot-mvebu 03/10] ddr: marvell: a38x: debug: Define DDR_VIEWER_TOOL variables only if needed, and make them static
The variables is_validate_window_per_if, is_validate_window_per_pup, sweep_cnt and is_run_leveling_sweep_tests are only used if DDR_VIEWER_TOOL macro is defined, so define them only in that case. Make them static since they are only used in ddr3_debug.c. Signed-off-by: Marek Behún --- drivers/ddr/marvell/a38x/ddr3_debug.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c index c659ae92d8..d32d42c408 100644 --- a/drivers/ddr/marvell/a38x/ddr3_debug.c +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c @@ -114,13 +114,14 @@ u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM]; u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM]; u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM]; #endif /* EXCLUDE_SWITCH_DEBUG */ + +static u8 is_validate_window_per_if = 0; +static u8 is_validate_window_per_pup = 0; +static u8 sweep_cnt = 1; +static u8 is_run_leveling_sweep_tests; #endif /* DDR_VIEWER_TOOL */ struct hws_tip_config_func_db config_func_info[MAX_DEVICE_NUM]; -u8 is_validate_window_per_if = 0; -u8 is_validate_window_per_pup = 0; -u8 sweep_cnt = 1; -u8 is_run_leveling_sweep_tests; static struct hws_xsb_info xsb_info[MAX_DEVICE_NUM]; -- 2.43.2
[PATCH u-boot-mvebu 01/10] ddr: marvell: a38x: debug: return from ddr3_tip_print_log() early if we won't print anything
Return from ddr3_tip_print_log() early if we won't print anything
anyway.
This way the compiler can optimize away the VALIDATE_IF_ACTIVE() calls
in the for-loop, so if the SILENT_LIB macro is defined, no code is
generated for the rest of the function, which saves some space.
Signed-off-by: Marek Behún
---
drivers/ddr/marvell/a38x/ddr3_debug.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c
b/drivers/ddr/marvell/a38x/ddr3_debug.c
index 9e499cfb99..0374a84387 100644
--- a/drivers/ddr/marvell/a38x/ddr3_debug.c
+++ b/drivers/ddr/marvell/a38x/ddr3_debug.c
@@ -399,6 +399,15 @@ int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
}
#endif /* DDR_VIEWER_TOOL */
+ /* return early if we won't print anything anyway */
+ if (
+#if defined(SILENT_LIB)
+ 1 ||
+#endif
+ debug_training < DEBUG_LEVEL_INFO) {
+ return MV_OK;
+ }
+
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
--
2.43.2
[PATCH u-boot-mvebu 02/10] ddr: marvell: a38x: debug: Remove unused variables
The variables is_default_centralization, is_tune_result and is_bist_reset_bit are never used. Signed-off-by: Marek Behún --- drivers/ddr/marvell/a38x/ddr3_debug.c | 3 --- drivers/ddr/marvell/a38x/ddr3_init.h | 1 - 2 files changed, 4 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c index 0374a84387..c659ae92d8 100644 --- a/drivers/ddr/marvell/a38x/ddr3_debug.c +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c @@ -117,12 +117,9 @@ u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM]; #endif /* DDR_VIEWER_TOOL */ struct hws_tip_config_func_db config_func_info[MAX_DEVICE_NUM]; -u8 is_default_centralization = 0; -u8 is_tune_result = 0; u8 is_validate_window_per_if = 0; u8 is_validate_window_per_pup = 0; u8 sweep_cnt = 1; -u32 is_bist_reset_bit = 1; u8 is_run_leveling_sweep_tests; static struct hws_xsb_info xsb_info[MAX_DEVICE_NUM]; diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h index 6854bb49de..9288073a78 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.h +++ b/drivers/ddr/marvell/a38x/ddr3_init.h @@ -116,7 +116,6 @@ extern u32 clamp_tbl[]; extern u32 freq_mask[MAX_DEVICE_NUM][MV_DDR_FREQ_LAST]; extern u32 maxt_poll_tries; -extern u32 is_bist_reset_bit; extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM]; extern u32 effective_cs; -- 2.43.2
[PATCH u-boot-mvebu 00/10] Turris Omnia DDR training changes
Hi Stefan, this series adds some changes to DDR3 training for Armada 38x and Turris Omnia. - patches 1-4 are meant to allow for reducing another 10 KiB in the SPL binary. They were also sent to mv-ddr-marvell, via PR on github, https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/45/ but I am told that Armada team has left Marvell, so who knows if this will ever be merged there - patch 5 enables this reduction for Turris Omnia - patches 6-8 import old DDR3 training code and make some changes so that it works with U-Boot. The reason why this is being done is explained in patch 6 - patch 9 glues the old DDR3 training code to current U-Boot - patch 10 allows for dynamic selection of old DDR3 training code on Turris Omnia, via an U-Boot environment variable Marek Marek Behún (10): ddr: marvell: a38x: debug: return from ddr3_tip_print_log() early if we won't print anything ddr: marvell: a38x: debug: Remove unused variables ddr: marvell: a38x: debug: Define DDR_VIEWER_TOOL variables only if needed, and make them static ddr: marvell: a38x: debug: Allow compiling with immutable debug settings to reduce binary size arm: mvebu: turris_omnia: Enable immutable debug settings in DDR3 training by default ddr: marvell: a38x: Import old DDR training code from 2017 version of U-Boot ddr: marvell: a38x: old: Fix some compiler warning of the old code ddr: marvell: a38x: old: Backport immutable debug settings arm: mvebu: a38x: Add optional support for using old DDR3 training code arm: mvebu: turris_omnia: Support old DDR3 training, selectable via env var arch/arm/mach-mvebu/Kconfig | 15 + arch/arm/mach-mvebu/include/mach/cpu.h|1 + arch/arm/mach-mvebu/spl.c | 37 +- board/CZ.NIC/turris_omnia/Makefile|1 + board/CZ.NIC/turris_omnia/old_ddr3_training.c | 79 + board/CZ.NIC/turris_omnia/turris_omnia.c |2 +- configs/turris_omnia_defconfig|1 + drivers/ddr/marvell/a38x/Makefile |2 + drivers/ddr/marvell/a38x/ddr3_debug.c | 30 +- drivers/ddr/marvell/a38x/ddr3_init.c |3 +- drivers/ddr/marvell/a38x/ddr3_init.h | 43 +- drivers/ddr/marvell/a38x/old/Makefile | 29 + drivers/ddr/marvell/a38x/old/ddr3_a38x.c | 738 + drivers/ddr/marvell/a38x/old/ddr3_a38x.h | 93 + .../marvell/a38x/old/ddr3_a38x_mc_static.h| 226 ++ .../ddr/marvell/a38x/old/ddr3_a38x_topology.h | 22 + .../ddr/marvell/a38x/old/ddr3_a38x_training.c | 40 + drivers/ddr/marvell/a38x/old/ddr3_debug.c | 1545 ++ .../marvell/a38x/old/ddr3_hws_hw_training.c | 148 + .../marvell/a38x/old/ddr3_hws_hw_training.h | 49 + .../a38x/old/ddr3_hws_hw_training_def.h | 464 +++ .../marvell/a38x/old/ddr3_hws_sil_training.h | 17 + drivers/ddr/marvell/a38x/old/ddr3_init.c | 770 + drivers/ddr/marvell/a38x/old/ddr3_init.h | 405 +++ .../ddr/marvell/a38x/old/ddr3_logging_def.h | 101 + .../marvell/a38x/old/ddr3_patterns_64bit.h| 924 ++ .../ddr/marvell/a38x/old/ddr3_topology_def.h | 76 + drivers/ddr/marvell/a38x/old/ddr3_training.c | 2651 + .../ddr/marvell/a38x/old/ddr3_training_bist.c | 289 ++ .../a38x/old/ddr3_training_centralization.c | 712 + .../ddr/marvell/a38x/old/ddr3_training_db.c | 652 .../marvell/a38x/old/ddr3_training_hw_algo.c | 686 + .../marvell/a38x/old/ddr3_training_hw_algo.h | 14 + .../ddr/marvell/a38x/old/ddr3_training_ip.h | 178 ++ .../marvell/a38x/old/ddr3_training_ip_bist.h | 54 + .../old/ddr3_training_ip_centralization.h | 15 + .../marvell/a38x/old/ddr3_training_ip_db.h| 34 + .../marvell/a38x/old/ddr3_training_ip_def.h | 173 ++ .../a38x/old/ddr3_training_ip_engine.c| 1355 + .../a38x/old/ddr3_training_ip_engine.h| 85 + .../marvell/a38x/old/ddr3_training_ip_flow.h | 349 +++ .../marvell/a38x/old/ddr3_training_ip_pbs.h | 41 + .../a38x/old/ddr3_training_ip_prv_if.h| 107 + .../a38x/old/ddr3_training_ip_static.h| 31 + .../marvell/a38x/old/ddr3_training_leveling.c | 1837 .../marvell/a38x/old/ddr3_training_leveling.h | 17 + .../ddr/marvell/a38x/old/ddr3_training_pbs.c | 995 +++ .../marvell/a38x/old/ddr3_training_static.c | 538 .../ddr/marvell/a38x/old/ddr_topology_def.h | 121 + .../ddr/marvell/a38x/old/ddr_training_ip_db.h | 16 + .../marvell/a38x/old/glue_symbol_renames.h| 247 ++ drivers/ddr/marvell/a38x/old/silicon_if.h | 17 + drivers/ddr/marvell/a38x/old/xor.h| 92 + 53 files changed, 17138 insertions(+), 29 deletions(-) create mode 100644 board/CZ.NIC/turris_omnia/old_ddr3_training.c create mode 100644 drivers/ddr/marvell/a38x/old/Makefile create mode 100644 drivers/ddr/marvell/a38x/old/ddr3_a38x.c create mode 100644
Re: [PATCH 1/3] serial: allow selecting MSM debug UART with ARCH_IPQ40XX
On Mon, Apr 15, 2024 at 1:21 PM Caleb Connolly wrote: > > Hi Robert, > > Happy to see someone working on those IPQ platforms. If it makes sense > to then I'd be happy to adopt them under ARCH_SNAPDRAGON at some point? > I'm not hugely familiar with the usecase here (but eager to learn more!). Well, IPQ40xx is quite a popular WiSoC family and its cheap but the stock bootloader limits any kind of custom use case, so here we are. Regards, Robert > > On 15/04/2024 11:49, Robert Marko wrote: > > Currently, DEBUG_UART_MSM depends on ARCH_SNAPDRAGON only, but IPQ40XX > > devices also use the same UART HW so they can also use the debug UART. > > > > So, allow selecting DEBUG_UART_MSM when using ARCH_IPQ40XX as well. > > > > Signed-off-by: Robert Marko > > Reviewed-by: Caleb Connolly > > --- > > drivers/serial/Kconfig | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig > > index 8b19e2684e..1fe4607598 100644 > > --- a/drivers/serial/Kconfig > > +++ b/drivers/serial/Kconfig > > @@ -321,7 +321,7 @@ config DEBUG_UART_S5P > > > > config DEBUG_UART_MSM > > bool "Qualcomm QUP UART debug" > > - depends on ARCH_SNAPDRAGON > > + depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX > > help > > Select this to enable a debug UART using the serial_msm driver. You > > will need to provide parameters to make this work. The driver will > > -- > // Caleb (they/them) -- Robert Marko Staff Embedded Linux Engineer Sartura Ltd. Lendavska ulica 16a 1 Zagreb, Croatia Email: robert.ma...@sartura.hr Web: www.sartura.hr
[PATCH v2 3/3] serial: msm: calculate bit clock divider
The driver currently requires the bit clock divider be hardcoded in
devicetree (or use the hardcoded default from apq8016).
The bit clock divider is used to derive the baud rate from the core
clock:
baudrate = clk_rate / csr_div
clk_rate is the actual programmed core clock rate which is returned by
clk_set_rate(), and this UART driver only supports a baudrate of 115200.
We can therefore determine the appropriate value for UARTDM_CSR by
iterating over the possible values and finding the one where the
equation above holds true for a baudrate of 115200.
Implement this logic and drop the non-standard DT bindings for this
driver.
Tested on dragonboard410c.
Signed-off-by: Caleb Connolly
Tested-by: Robert Marko
---
Cc: Robert Marko
---
doc/device-tree-bindings/serial/msm-serial.txt | 10 ---
drivers/serial/serial_msm.c| 87 +-
2 files changed, 70 insertions(+), 27 deletions(-)
diff --git a/doc/device-tree-bindings/serial/msm-serial.txt
b/doc/device-tree-bindings/serial/msm-serial.txt
deleted file mode 100644
index dca995798a90..
--- a/doc/device-tree-bindings/serial/msm-serial.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Qualcomm UART (Data Mover mode)
-
-Required properties:
-- compatible: must be "qcom,msm-uartdm-v1.4"
-- reg: start address and size of the registers
-- clock: interface clock (must accept baudrate as a frequency)
-
-Optional properties:
-- bit-rate: Data Mover bit rate register value
- (If not defined then 0xCC is used as default)
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 8044d38518db..c05dda8bdb97 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -31,8 +31,18 @@
#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer
*/
#define UARTDM_RXFS_BUF_MASK0x7
#define UARTDM_MR1 0x00
#define UARTDM_MR2 0x04
+/*
+ * This is documented on page 1817 of the apq8016e technical reference manual.
+ * section 6.2.5.3.26
+ *
+ * The upper nybble contains the bit clock divider for the RX pin, the lower
+ * nybble defines the TX pin. In almost all cases these should be the same
value.
+ *
+ * The baud rate is the core clock frequency divided by the fixed divider value
+ * programmed into this register (defined in calc_csr_bitrate()).
+ */
#define UARTDM_CSR 0xA0
#define UARTDM_SR0xA4 /* Status register */
#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
@@ -52,9 +62,8 @@
#define UARTDM_TF 0x100 /* UART Transmit FIFO register */
#define UARTDM_RF 0x140 /* UART Receive FIFO register */
-#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
@@ -63,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR;
struct msm_serial_data {
phys_addr_t base;
unsigned chars_cnt; /* number of buffered chars */
uint32_t chars_buf; /* buffered chars */
- uint32_t clk_bit_rate; /* data mover mode bit rate register value */
+ uint32_t clk_rate; /* core clock rate */
};
static int msm_serial_fetch(struct udevice *dev)
{
@@ -155,34 +164,63 @@ static const struct dm_serial_ops msm_serial_ops = {
.pending = msm_serial_pending,
.getc = msm_serial_getc,
};
-static int msm_uart_clk_init(struct udevice *dev)
+static long msm_uart_clk_init(struct udevice *dev)
{
- uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "clock-frequency", 115200);
+ struct msm_serial_data *priv = dev_get_priv(dev);
struct clk clk;
int ret;
+ long rate;
ret = clk_get_by_name(dev, "core", );
if (ret < 0) {
pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
- return ret;
+ return 0;
}
- ret = clk_set_rate(, clk_rate);
- if (ret < 0)
- return ret;
+ rate = clk_set_rate(, priv->clk_rate);
- return 0;
+ return rate;
+}
+
+static int calc_csr_bitrate(struct msm_serial_data *priv)
+{
+ /* This table is from the TRE. See the definition of UARTDM_CSR */
+ unsigned int csr_div_table[] = {24576, 12288, 6144, 3072, 1536, 768,
512, 384,
+ 256, 192, 128, 96, 64, 48,
32, 16};
+ int i = ARRAY_SIZE(csr_div_table) - 1;
+ /* Currently we only support one baudrate */
+ int baud = 115200;
+
+ for (; i >= 0; i--) {
+ int x = priv->clk_rate / csr_div_table[i];
+
+ if (x == baud)
+ /* Duplicate the configuration for RX
+* as the lower nybble only configures TX
+*/
+ return i + (i <<
[PATCH v2 2/3] clk/qcom: ipq4019: return valid rate when setting UART clock
clk_set_rate() should return the clock rate that was set. The IPQ4019
clock driver doesn't set any rates yet but it should still return the
expected value so that drivers can work properly.
For a baud rate of 115200 with an expected bit clock divisor of 16, the
clock rate should be 1843200 so return that frequency.
Signed-off-by: Caleb Connolly
---
drivers/clk/qcom/clock-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c
index d693776d339d..72f235eab212 100644
--- a/drivers/clk/qcom/clock-ipq4019.c
+++ b/drivers/clk/qcom/clock-ipq4019.c
@@ -20,9 +20,9 @@ static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
{
switch (clk->id) {
case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
/* This clock is already initialized by SBL1 */
- return 0;
+ return 1843200;
default:
return -EINVAL;
}
}
--
2.44.0
[PATCH v2 1/3] clk/qcom: apq8016: return valid rate when setting UART clock
The clk_init_uart() helper always returns 0, but we're meant to return a real clock rate. Given that we hardcode 115200 baud, just return the clock rate that we set. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-apq8016.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 5a5868169c89..6210fba87984 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -99,10 +99,10 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) case GCC_SDCC2_APPS_CLK: /* SDC2 */ return clk_init_sdc(priv, 1, rate); break; case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ - return apq8016_clk_init_uart(priv->base); - break; + apq8016_clk_init_uart(priv->base); + return 7372800; default: return 0; } } -- 2.44.0
[PATCH v2 0/3] qcom: serial_msm: calculate UARTDM_CSR automatically
The msm serial UART controller has a bit clock divider register which much be programmed based on the UART clock. This changes per soc and currently is expected to be specified in DT or otherwise selected per board. This series fixes the apq8016 and ipq4019 clock drivers to return the programmed UART clock rate in clk_set_rate(), it then uses this clock rate and the hardcoded baud rate supported by this driver to calculate the correct value for the UARTDM_CSR register. --- Changes in v2: - use CONFIG_VAL(DEBUG_UART_CLOCK) for debug uart clk_rate. - Link to v1: https://lore.kernel.org/r/20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd...@linaro.org --- Caleb Connolly (3): clk/qcom: apq8016: return valid rate when setting UART clock clk/qcom: ipq4019: return valid rate when setting UART clock serial: msm: calculate bit clock divider doc/device-tree-bindings/serial/msm-serial.txt | 10 --- drivers/clk/qcom/clock-apq8016.c | 4 +- drivers/clk/qcom/clock-ipq4019.c | 2 +- drivers/serial/serial_msm.c| 87 +- 4 files changed, 73 insertions(+), 30 deletions(-) --- base-commit: 42f6978987336cff3d98d9cc4643c54a1eb0f36d // Caleb (they/them)
Re: [PATCH] mmc: sdhci: programmable clock calculation needs multiplier +1
On 4/12/24 15:26, curtis.mach...@intel.com wrote:
> [You don't often get email from curtis.mach...@intel.com. Learn why this is
> important at
> https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2faka.ms%2fLearnAboutSenderIdentification=4f25273f-b33b-4eb3-8643-c1f6eff8842b=d807158c60b7d2502abde8a2fc01f40662980862-c95c2e418b830130ad99c91e42b2732e3f7e44ee
> ]
>
> From: cmachida
>
> According to the SD Host Controller Simplified Specification v4.20,
> the multiplier value M is one more than the Clock Multiplier field.
>
> Copied code from Linux project. drivers/mmc/host/sdhci.c line 4405
>
> Signed-off-by: cmachida
> ---
>
> drivers/mmc/sdhci.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index 0178ed8a11..a8476ec4e9 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -929,6 +929,15 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct
> sdhci_host *host,
> debug("%s, caps_1: 0x%x\n", __func__, caps_1);
> host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
> SDHCI_CLOCK_MUL_SHIFT;
> +
> + /*
> +* In case the value in Clock Multiplier is 0, then
> programmable
> +* clock mode is not supported, otherwise the actual clock
> +* multiplier is one more than the value of Clock Multiplier
> +* in the Capabilities Register.
> +*/
> + if (host->clk_mul)
> + host->clk_mul += 1;
> }
>
> if (host->max_clk == 0) {
> --
> 2.43.2
>
Reviewed-by: Sean Anderson
Re: [PATCH 3/3] serial: msm: calculate bit clock divider
On Mon, Apr 15, 2024 at 4:18 PM Caleb Connolly
wrote:
>
>
>
> On 15/04/2024 14:05, Robert Marko wrote:
> > On Mon, Apr 15, 2024 at 2:44 PM Caleb Connolly
> > wrote:
> >>
> >> The driver currently requires the bit clock divider be hardcoded in
> >> devicetree (or use the hardcoded default from apq8016).
> >>
> >> The bit clock divider is used to derive the baud rate from the core
> >> clock:
> >>
> >> baudrate = clk_rate / csr_div
> >>
> >> clk_rate is the actual programmed core clock rate which is returned by
> >> clk_set_rate(), and this UART driver only supports a baudrate of 115200.
> >> We can therefore determine the appropriate value for UARTDM_CSR by
> >> iterating over the possible values and finding the one where the
> >> equation above holds true for a baudrate of 115200.
> >>
> >> Implement this logic and drop the non-standard DT bindings for this
> >> driver.
> >>
> >> Tested on dragonboard410c.
> >>
> >> Signed-off-by: Caleb Connolly
> >
> > Works on Alfa AP120C (IPQ4018) with full DM UART, but debug UART
> > prints junk since .clk_rate = 7372800 is not correct for IPQ40xx.
> > I would suggest using .clk_rate = CONFIG_VAL(DEBUG_UART_CLOCK) instead
> > to populate the value per board, this also avoids per ARCH ifdefs.
>
> Ok awesome, thanks for trying this out. I'll send a v2 with your suggestion.
>
> Can I add your Tested-by?
Sure,
Tested-by: Robert Marko
Regards,
Robert
> >
> > Regards,
> > Robert
> >> ---
> >> Cc: Robert Marko
> >> ---
> >> doc/device-tree-bindings/serial/msm-serial.txt | 10 ---
> >> drivers/serial/serial_msm.c| 87
> >> +-
> >> 2 files changed, 70 insertions(+), 27 deletions(-)
> >>
> >> diff --git a/doc/device-tree-bindings/serial/msm-serial.txt
> >> b/doc/device-tree-bindings/serial/msm-serial.txt
> >> deleted file mode 100644
> >> index dca995798a90..
> >> --- a/doc/device-tree-bindings/serial/msm-serial.txt
> >> +++ /dev/null
> >> @@ -1,10 +0,0 @@
> >> -Qualcomm UART (Data Mover mode)
> >> -
> >> -Required properties:
> >> -- compatible: must be "qcom,msm-uartdm-v1.4"
> >> -- reg: start address and size of the registers
> >> -- clock: interface clock (must accept baudrate as a frequency)
> >> -
> >> -Optional properties:
> >> -- bit-rate: Data Mover bit rate register value
> >> - (If not defined then 0xCC is used as default)
> >> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> >> index 8044d38518db..e461929b4338 100644
> >> --- a/drivers/serial/serial_msm.c
> >> +++ b/drivers/serial/serial_msm.c
> >> @@ -31,8 +31,18 @@
> >> #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing
> >> buffer */
> >> #define UARTDM_RXFS_BUF_MASK0x7
> >> #define UARTDM_MR1 0x00
> >> #define UARTDM_MR2 0x04
> >> +/*
> >> + * This is documented on page 1817 of the apq8016e technical reference
> >> manual.
> >> + * section 6.2.5.3.26
> >> + *
> >> + * The upper nybble contains the bit clock divider for the RX pin, the
> >> lower
> >> + * nybble defines the TX pin. In almost all cases these should be the
> >> same value.
> >> + *
> >> + * The baud rate is the core clock frequency divided by the fixed divider
> >> value
> >> + * programmed into this register (defined in calc_csr_bitrate()).
> >> + */
> >> #define UARTDM_CSR 0xA0
> >>
> >> #define UARTDM_SR0xA4 /* Status register */
> >> #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
> >> @@ -52,9 +62,8 @@
> >>
> >> #define UARTDM_TF 0x100 /* UART Transmit FIFO register */
> >> #define UARTDM_RF 0x140 /* UART Receive FIFO register */
> >>
> >> -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
> >> #define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
> >> #define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
> >> #define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
> >>
> >> @@ -63,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR;
> >> struct msm_serial_data {
> >> phys_addr_t base;
> >> unsigned chars_cnt; /* number of buffered chars */
> >> uint32_t chars_buf; /* buffered chars */
> >> - uint32_t clk_bit_rate; /* data mover mode bit rate register value
> >> */
> >> + uint32_t clk_rate; /* core clock rate */
> >> };
> >>
> >> static int msm_serial_fetch(struct udevice *dev)
> >> {
> >> @@ -155,34 +164,63 @@ static const struct dm_serial_ops msm_serial_ops = {
> >> .pending = msm_serial_pending,
> >> .getc = msm_serial_getc,
> >> };
> >>
> >> -static int msm_uart_clk_init(struct udevice *dev)
> >> +static long msm_uart_clk_init(struct udevice *dev)
> >> {
> >> - uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
> >> - "clock-frequency", 115200);
> >> + struct msm_serial_data *priv = dev_get_priv(dev);
> >> struct clk clk;
> >> int ret;
> >> + long rate;
Re: [PATCH 4/4] arm: apple: Switch to standard boot
> From: Janne Grunau via B4 Relay > Date: Sun, 17 Mar 2024 15:54:50 +0100 > > From: Janne Grunau > > Use standard boot instead of the distro boot scripts. > > Signed-off-by: Janne Grunau As per a somewhat recent discussion about this for the rockchip SoCs, I think we want BOOTSTD_FULL instead of BOOTSTD_DEFAULT. Even though I think that BOOTSTD_FULL is a bit too chatty at the moment. That also solves the issue that BOOTSTD_DEFAULTS doesn't run the EFI bootmgr (which does happen with distroboot). Although Heinrich has a diff to fix that. > --- > arch/arm/Kconfig| 2 +- > include/configs/apple.h | 20 ++-- > 2 files changed, 3 insertions(+), 19 deletions(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 01d6556c42..ad89abde41 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1034,7 +1034,7 @@ config ARCH_APPLE > select USB > imply CMD_DM > imply CMD_GPT > - imply DISTRO_DEFAULTS > + imply BOOTSTD_DEFAULTS > imply OF_HAS_PRIOR_STAGE > > config ARCH_OWL > diff --git a/include/configs/apple.h b/include/configs/apple.h > index a70440b3ad..1e08b11448 100644 > --- a/include/configs/apple.h > +++ b/include/configs/apple.h > @@ -9,26 +9,10 @@ > "stdout=vidconsole,serial\0" \ > "stderr=vidconsole,serial\0" > > -#if IS_ENABLED(CONFIG_CMD_NVME) > - #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) > -#else > - #define BOOT_TARGET_NVME(func) > -#endif > - > -#if IS_ENABLED(CONFIG_CMD_USB) > - #define BOOT_TARGET_USB(func) func(USB, usb, 0) > -#else > - #define BOOT_TARGET_USB(func) > -#endif > - > -#define BOOT_TARGET_DEVICES(func) \ > - BOOT_TARGET_NVME(func) \ > - BOOT_TARGET_USB(func) > - > -#include > +#define BOOT_TARGETS "nvme usb" > > #define CFG_EXTRA_ENV_SETTINGS \ > ENV_DEVICE_SETTINGS \ > - BOOTENV > + "boot_targets=" BOOT_TARGETS "\0" > > #endif > > -- > 2.44.0 > > >
Re: [PATCH 3/3] serial: msm: calculate bit clock divider
On 15/04/2024 14:05, Robert Marko wrote:
> On Mon, Apr 15, 2024 at 2:44 PM Caleb Connolly
> wrote:
>>
>> The driver currently requires the bit clock divider be hardcoded in
>> devicetree (or use the hardcoded default from apq8016).
>>
>> The bit clock divider is used to derive the baud rate from the core
>> clock:
>>
>> baudrate = clk_rate / csr_div
>>
>> clk_rate is the actual programmed core clock rate which is returned by
>> clk_set_rate(), and this UART driver only supports a baudrate of 115200.
>> We can therefore determine the appropriate value for UARTDM_CSR by
>> iterating over the possible values and finding the one where the
>> equation above holds true for a baudrate of 115200.
>>
>> Implement this logic and drop the non-standard DT bindings for this
>> driver.
>>
>> Tested on dragonboard410c.
>>
>> Signed-off-by: Caleb Connolly
>
> Works on Alfa AP120C (IPQ4018) with full DM UART, but debug UART
> prints junk since .clk_rate = 7372800 is not correct for IPQ40xx.
> I would suggest using .clk_rate = CONFIG_VAL(DEBUG_UART_CLOCK) instead
> to populate the value per board, this also avoids per ARCH ifdefs.
Ok awesome, thanks for trying this out. I'll send a v2 with your suggestion.
Can I add your Tested-by?
>
> Regards,
> Robert
>> ---
>> Cc: Robert Marko
>> ---
>> doc/device-tree-bindings/serial/msm-serial.txt | 10 ---
>> drivers/serial/serial_msm.c| 87
>> +-
>> 2 files changed, 70 insertions(+), 27 deletions(-)
>>
>> diff --git a/doc/device-tree-bindings/serial/msm-serial.txt
>> b/doc/device-tree-bindings/serial/msm-serial.txt
>> deleted file mode 100644
>> index dca995798a90..
>> --- a/doc/device-tree-bindings/serial/msm-serial.txt
>> +++ /dev/null
>> @@ -1,10 +0,0 @@
>> -Qualcomm UART (Data Mover mode)
>> -
>> -Required properties:
>> -- compatible: must be "qcom,msm-uartdm-v1.4"
>> -- reg: start address and size of the registers
>> -- clock: interface clock (must accept baudrate as a frequency)
>> -
>> -Optional properties:
>> -- bit-rate: Data Mover bit rate register value
>> - (If not defined then 0xCC is used as default)
>> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
>> index 8044d38518db..e461929b4338 100644
>> --- a/drivers/serial/serial_msm.c
>> +++ b/drivers/serial/serial_msm.c
>> @@ -31,8 +31,18 @@
>> #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing
>> buffer */
>> #define UARTDM_RXFS_BUF_MASK0x7
>> #define UARTDM_MR1 0x00
>> #define UARTDM_MR2 0x04
>> +/*
>> + * This is documented on page 1817 of the apq8016e technical reference
>> manual.
>> + * section 6.2.5.3.26
>> + *
>> + * The upper nybble contains the bit clock divider for the RX pin, the lower
>> + * nybble defines the TX pin. In almost all cases these should be the same
>> value.
>> + *
>> + * The baud rate is the core clock frequency divided by the fixed divider
>> value
>> + * programmed into this register (defined in calc_csr_bitrate()).
>> + */
>> #define UARTDM_CSR 0xA0
>>
>> #define UARTDM_SR0xA4 /* Status register */
>> #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
>> @@ -52,9 +62,8 @@
>>
>> #define UARTDM_TF 0x100 /* UART Transmit FIFO register */
>> #define UARTDM_RF 0x140 /* UART Receive FIFO register */
>>
>> -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
>> #define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
>> #define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
>> #define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
>>
>> @@ -63,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR;
>> struct msm_serial_data {
>> phys_addr_t base;
>> unsigned chars_cnt; /* number of buffered chars */
>> uint32_t chars_buf; /* buffered chars */
>> - uint32_t clk_bit_rate; /* data mover mode bit rate register value */
>> + uint32_t clk_rate; /* core clock rate */
>> };
>>
>> static int msm_serial_fetch(struct udevice *dev)
>> {
>> @@ -155,34 +164,63 @@ static const struct dm_serial_ops msm_serial_ops = {
>> .pending = msm_serial_pending,
>> .getc = msm_serial_getc,
>> };
>>
>> -static int msm_uart_clk_init(struct udevice *dev)
>> +static long msm_uart_clk_init(struct udevice *dev)
>> {
>> - uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
>> - "clock-frequency", 115200);
>> + struct msm_serial_data *priv = dev_get_priv(dev);
>> struct clk clk;
>> int ret;
>> + long rate;
>>
>> ret = clk_get_by_name(dev, "core", );
>> if (ret < 0) {
>> pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
>> - return ret;
>> + return 0;
>> }
>>
>> - ret = clk_set_rate(, clk_rate);
>> - if (ret < 0)
>> - return ret;
>> + rate = clk_set_rate(,
Re: [PATCH v2 15/23] rockchip: rk3588-toybrick: Add missing Kconfig options
Hi Quentin and Dragan, On 2024-04-15 11:10, Quentin Schulz wrote: > Hi Dragan, > > On 4/15/24 11:04, Dragan Simic wrote: >> On 2024-04-15 10:58, Quentin Schulz wrote: >>> On 4/13/24 20:13, Jonas Karlman wrote: Add .dtb-file entry to Makefile and enable Kconfig options required to configure pinctrl in SPL. Also add missing PHY_ROCKCHIP_NANENG_COMBOPHY. >>> >>> Separate commits please. >> >> Perhaps the Makefile changes from a couple of different patches >> could be put together into another, separate patch. Those are all >> related changes, and it would result in one less patch in the v3 >> of this series. >> > > That would be fine with me. > > But always better have too many patches than too few, it's easier to > later squash than separate them :) Sure, I will split these patches into smaller single purpose patches in v3. Regards, Jonas > > Cheers, > Quentin
[PATCH v3 11/11] rockchip: rk356x: use DRAM banks from ATAGS
From: Quentin Schulz RK356x-based devices now support creating DRAM banks with proper holes by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism instead. The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for reading banks from ATAGS, so let's use the default value instead. Co-developed-by: Chris Morgan Signed-off-by: Chris Morgan Signed-off-by: Quentin Schulz --- configs/anbernic-rgxx3-rk3566_defconfig | 1 - configs/bpi-r2-pro-rk3568_defconfig | 1 - configs/evb-rk3568_defconfig | 1 - configs/generic-rk3568_defconfig | 1 - configs/lubancat-2-rk3568_defconfig | 1 - configs/nanopi-r5c-rk3568_defconfig | 1 - configs/nanopi-r5s-rk3568_defconfig | 1 - configs/odroid-m1-rk3568_defconfig| 1 - configs/pinetab2-rk3566_defconfig | 1 - configs/quartz64-a-rk3566_defconfig | 1 - configs/quartz64-b-rk3566_defconfig | 1 - configs/radxa-cm3-io-rk3566_defconfig | 1 - configs/radxa-e25-rk3568_defconfig| 1 - configs/rock-3a-rk3568_defconfig | 1 - configs/soquartz-blade-rk3566_defconfig | 1 - configs/soquartz-cm4-rk3566_defconfig | 1 - configs/soquartz-model-a-rk3566_defconfig | 1 - 17 files changed, 17 deletions(-) diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index c8c9238f96f..aa3809e00c1 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig index 5cc95241ba4..0f85dc63c55 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index 6e8061f5f48..f2f429d33c4 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index e7d5e55bbfd..8f4a6259a27 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig index 1c50a0ccbe6..ea67b6a7286 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index 0f1a9461a0c..00743b7f926 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 4ebf0cc9ee8..91e3a19dea6 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig index b5ed9e4bc98..e749f9af9d2 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=2400 CONFIG_SF_DEFAULT_MODE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1" diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig index
[PATCH v3 10/11] rockchip: rk3588: use DRAM banks from ATAGS
From: Quentin Schulz RK3588-based devices now support creating DRAM banks with proper holes by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism instead. The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for reading banks from ATAGS, so let's use the default value instead. Co-developed-by: Chris Morgan Signed-off-by: Chris Morgan Signed-off-by: Quentin Schulz --- configs/jaguar-rk3588_defconfig | 1 - configs/neu6a-io-rk3588_defconfig | 1 - configs/neu6b-io-rk3588_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 3233b75cee9..f29505ea150 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=2400 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_ENV_SIZE=0x1f000 diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index 307a540f424..2b939e6795f 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index 9ef2bb21fff..d0fa0dca7ac 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y -- 2.44.0
[PATCH v3 09/11] rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the turing-rk1-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/turing/turing-rk1-rk3588/Makefile| 6
board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c | 39 --
configs/turing-rk1-rk3588_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/turing/turing-rk1-rk3588/Makefile
b/board/turing/turing-rk1-rk3588/Makefile
deleted file mode 100644
index a979d8023aa..000
--- a/board/turing/turing-rk1-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += turing-rk1-rk3588.o
diff --git a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
deleted file mode 100644
index e2338a2a35a..000
--- a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return turing_rk1_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/turing-rk1-rk3588_defconfig
b/configs/turing-rk1-rk3588_defconfig
index 07f7b848529..2195b03d57a 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 08/11] rockchip: toybrick_rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the toybrick_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/rockchip/toybrick_rk3588/Makefile | 6
board/rockchip/toybrick_rk3588/toybrick-rk3588.c | 39
configs/toybrick-rk3588_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/rockchip/toybrick_rk3588/Makefile
b/board/rockchip/toybrick_rk3588/Makefile
deleted file mode 100644
index 75d4d9438f7..000
--- a/board/rockchip/toybrick_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += toybrick-rk3588.o
diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
deleted file mode 100644
index e3217f70b50..000
--- a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/toybrick-rk3588_defconfig
b/configs/toybrick-rk3588_defconfig
index 6ee92e94313..675e7d89e12 100644
--- a/configs/toybrick-rk3588_defconfig
+++ b/configs/toybrick-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 06/11] rockchip: rock5b-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the rock5b-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/radxa/rock5b-rk3588/Makefile| 6 -
board/radxa/rock5b-rk3588/rock5b-rk3588.c | 39 ---
configs/rock5b-rk3588_defconfig | 2 --
3 files changed, 47 deletions(-)
diff --git a/board/radxa/rock5b-rk3588/Makefile
b/board/radxa/rock5b-rk3588/Makefile
deleted file mode 100644
index 95d813596da..000
--- a/board/radxa/rock5b-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2022 Collabora Ltd.
-#
-
-obj-y += rock5b-rk3588.o
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
deleted file mode 100644
index 5c3b52b9489..000
--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5b_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rock5b_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 58c7c44fb4f..3603e175a0b 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 07/11] rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the evb_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
All defconfigs using the CONFIG_TARGET_EVB_RK3588 are updated at once
since they are impacted by this change.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/rockchip/evb_rk3588/Makefile | 6 -
board/rockchip/evb_rk3588/evb-rk3588.c | 39
configs/coolpi-4b-rk3588s_defconfig | 2 --
configs/coolpi-cm5-evb-rk3588_defconfig | 2 --
configs/evb-rk3588_defconfig | 2 --
configs/generic-rk3588_defconfig | 2 --
configs/orangepi-5-plus-rk3588_defconfig | 2 --
configs/orangepi-5-rk3588s_defconfig | 2 --
8 files changed, 57 deletions(-)
diff --git a/board/rockchip/evb_rk3588/Makefile
b/board/rockchip/evb_rk3588/Makefile
deleted file mode 100644
index 240d2ec597e..000
--- a/board/rockchip/evb_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += evb-rk3588.o
diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c
b/board/rockchip/evb_rk3588/evb-rk3588.c
deleted file mode 100644
index caf94d8d29c..000
--- a/board/rockchip/evb_rk3588/evb-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/coolpi-4b-rk3588s_defconfig
b/configs/coolpi-4b-rk3588s_defconfig
index a0fe3708344..2608bb67679 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig
b/configs/coolpi-cm5-evb-rk3588_defconfig
index fc17660da2a..c5bb7a42957 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index c8db04c076e..187cf26a5c9 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
[PATCH v3 05/11] rockchip: rock5a-rk3588s: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the rock5a-rk3588s.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/radxa/rock5a-rk3588s/Makefile | 6 -
board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 -
configs/rock5a-rk3588s_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/radxa/rock5a-rk3588s/Makefile
b/board/radxa/rock5a-rk3588s/Makefile
deleted file mode 100644
index 48dd5124550..000
--- a/board/radxa/rock5a-rk3588s/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Collabora Ltd.
-#
-
-obj-y += rock5a-rk3588s.o
diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
deleted file mode 100644
index 2d7a8c07dc5..000
--- a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5a_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rock5a_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index ebe2d4a2d81..01df911d9dc 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 04/11] rockchip: quartzpro64-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the quartzpro64-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/pine64/quartzpro64-rk3588/Makefile | 3 --
.../pine64/quartzpro64-rk3588/quartzpro64-rk3588.c | 39 --
configs/quartzpro64-rk3588_defconfig | 2 --
3 files changed, 44 deletions(-)
diff --git a/board/pine64/quartzpro64-rk3588/Makefile
b/board/pine64/quartzpro64-rk3588/Makefile
deleted file mode 100644
index 47819d9be93..000
--- a/board/pine64/quartzpro64-rk3588/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += quartzpro64-rk3588.o
diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
deleted file mode 100644
index bda804a89e2..000
--- a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2023 Google, Inc
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return quartzpro64_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/quartzpro64-rk3588_defconfig
b/configs/quartzpro64-rk3588_defconfig
index b2a66d3f2db..e398c7c2c0e 100644
--- a/configs/quartzpro64-rk3588_defconfig
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -19,7 +18,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 03/11] rockchip: nanopc-t6-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the nanopc-t6-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/friendlyelec/nanopc-t6-rk3588/Makefile | 6
.../nanopc-t6-rk3588/nanopc-t6-rk3588.c| 39 --
configs/nanopc-t6-rk3588_defconfig | 2 --
3 files changed, 47 deletions(-)
diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile
b/board/friendlyelec/nanopc-t6-rk3588/Makefile
deleted file mode 100644
index c1c49b19708..000
--- a/board/friendlyelec/nanopc-t6-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += nanopc-t6-rk3588.o
diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
deleted file mode 100644
index 99bbef964e0..000
--- a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int nanopc_t6_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return nanopc_t6_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/nanopc-t6-rk3588_defconfig
b/configs/nanopc-t6-rk3588_defconfig
index 5c7bc0b7196..738dda026b0 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 02/11] rockchip: NR_DRAM_BANKS now defaults to 10 when Rockchip TPL blob is used
From: Quentin Schulz When Rockchip TPL blob is used, the memory areas that can be used for DRAM is gotten from ATAGS passed through the DRAM at a specific address. The DDR_MEM tag contains at most 10 areas, so we should default to 10 if Rockchip TPL blob is used. Note that it is technically possible we need more if one of those 10 areas overlaps with reserved memory area, forcing us to split it in two. But a default doesn't need to handle all cases, only most. Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f68a0a48949..b7a6f100d41 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -573,6 +573,9 @@ config ROCKCHIP_COMMON_STACK_ADDR imply TPL_SYS_MALLOC_F if TPL imply TPL_SYS_MALLOC_SIMPLE if TPL +config NR_DRAM_BANKS + default 10 if ROCKCHIP_EXTERNAL_TPL + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3066/Kconfig" -- 2.44.0
[PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
From: Quentin Schulz
Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
more than 16GB of RAM. In the event that neither SoC is used or the
ROCKCHIP_TPL stage is not used, fall back to existing logic.
The logic handles creating memory holes from reserved memory areas
defined in mem_map data struct in SoC C files, but only if the DRAM area
overlaps with one reserved memory area.
Since mem_map data struct is used, it should be rather straightforward
to add support for other SoCs if needed.
The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1
(e08e32143dd).
Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as
well, but the DDR_MEM tag seems to be pretty much stable (though BL31
seems to be reserving only 1MB for itself at the moment).
u32 for ATAGS is used because it simplifies the pointer arithmetic and
it's expected that ATAGS are always below the 4GB limit allowed by u32.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/sdram.c | 240 +
1 file changed, 240 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f5..5b1ff1e5495 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -35,12 +36,251 @@ struct tos_parameter_t {
s64 reserve[8];
};
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE)
+
+/* ATAGS memory structures */
+
+enum tag_magic {
+ ATAG_NONE,
+ ATAG_CORE = 0x54410001,
+ ATAG_SERIAL = 0x54410050,
+ ATAG_DDR_MEM = 0x54410052,
+ ATAG_MAX = 0x544100ff,
+};
+
+/*
+ * An ATAG contains the following data:
+ * - header
+ *u32 size // sizeof(header + tag data) / sizeof(u32)
+ *u32 magic
+ * - tag data
+ */
+
+struct tag_header {
+ u32 size;
+ u32 magic;
+} __packed;
+
+/*
+ * DDR_MEM tag bank is storing data this way:
+ * - address0
+ * - address1
+ * - [...]
+ * - addressX
+ * - size0
+ * - size1
+ * - [...]
+ * - sizeX
+ *
+ * with X being tag_ddr_mem.count - 1.
+ */
+struct tag_ddr_mem {
+ u32 count;
+ u32 version;
+ u64 bank[20];
+ u32 flags;
+ u32 data[2];
+ u32 hash;
+} __packed;
+
+static u32 js_hash(const void *buf, u32 len)
+{
+ u32 i, hash = 0x47C6A7E6;
+
+ if (!buf || !len)
+ return hash;
+
+ for (i = 0; i < len; i++)
+ hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
+
+ return hash;
+}
+
+static int rockchip_dram_init_banksize(void)
+{
+ const struct tag_header *tag_h = NULL;
+ u32 *addr = (void *)ATAGS_PHYS_BASE;
+ struct tag_ddr_mem *ddr_info;
+ u32 calc_hash;
+ u8 i, j;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ return -ENOTSUPP;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+ return -ENOTSUPP;
+
+ /* Find DDR_MEM tag */
+ while (addr < (u32 *)ATAGS_PHYS_END) {
+ tag_h = (const struct tag_header *)addr;
+
+ if (!tag_h->size) {
+ debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ if (tag_h->magic == ATAG_DDR_MEM)
+ break;
+
+ switch (tag_h->magic) {
+ case ATAG_NONE:
+ case ATAG_CORE:
+ case ATAG_SERIAL ... ATAG_MAX:
+ addr += tag_h->size;
+ continue;
+ default:
+ debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
+ tag_h->magic, addr);
+ return -EINVAL;
+ }
+ }
+
+ if (addr >= (u32 *)ATAGS_PHYS_END ||
+ (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
+ debug("End of ATAGS, no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ /* Data is right after the magic member of the tag_header struct */
+ ddr_info = (struct tag_ddr_mem *)(_h->magic + 1);
+ if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS) {
+ debug("Too many ATAG banks, got (%d) but max allowed (%d)\n",
+ ddr_info->count, CONFIG_NR_DRAM_BANKS);
+ return -ENOMEM;
+ }
+
+ if
[PATCH v3 00/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
s/coolpi-4b-rk3588s_defconfig| 2 - configs/coolpi-cm5-evb-rk3588_defconfig| 2 - configs/evb-rk3568_defconfig | 1 - configs/evb-rk3588_defconfig | 2 - configs/generic-rk3568_defconfig | 1 - configs/generic-rk3588_defconfig | 2 - configs/jaguar-rk3588_defconfig| 1 - configs/lubancat-2-rk3568_defconfig| 1 - configs/nanopc-t6-rk3588_defconfig | 2 - configs/nanopi-r5c-rk3568_defconfig| 1 - configs/nanopi-r5s-rk3568_defconfig| 1 - configs/neu6a-io-rk3588_defconfig | 1 - configs/neu6b-io-rk3588_defconfig | 1 - configs/odroid-m1-rk3568_defconfig | 1 - configs/orangepi-5-plus-rk3588_defconfig | 2 - configs/orangepi-5-rk3588s_defconfig | 2 - configs/pinetab2-rk3566_defconfig | 1 - configs/quartz64-a-rk3566_defconfig| 1 - configs/quartz64-b-rk3566_defconfig| 1 - configs/quartzpro64-rk3588_defconfig | 2 - configs/radxa-cm3-io-rk3566_defconfig | 1 - configs/radxa-e25-rk3568_defconfig | 1 - configs/rock-3a-rk3568_defconfig | 1 - configs/rock5a-rk3588s_defconfig | 2 - configs/rock5b-rk3588_defconfig| 2 - configs/soquartz-blade-rk3566_defconfig| 1 - configs/soquartz-cm4-rk3566_defconfig | 1 - configs/soquartz-model-a-rk3566_defconfig | 1 - configs/toybrick-rk3588_defconfig | 2 - configs/turing-rk1-rk3588_defconfig| 2 - 48 files changed, 243 insertions(+), 356 deletions(-) --- base-commit: b03b49046af5dfca599d2ce8f0aafed89b97aa91 change-id: 20240415-rk35xx-dram-atags-35c9f19f4c38 Best regards, -- Quentin Schulz
Re: [PATCH v2 14/23] rockchip: rk3588-coolpi: Add boards to documentation
Hi Quentin and Dragan, On 2024-04-15 10:58, Dragan Simic wrote: > Hello Quentin, > > On 2024-04-15 10:56, Quentin Schulz wrote: >> Hi Jonas, >> >> On 4/13/24 20:13, Jonas Karlman wrote: >>> Add the CoolPi 4 Model B and CoolPi CM5 EVB board to the >>> documentation. >>> Also fix .dtb-file entries in Makefile. >>> >> >> When one needs to use a list or say "also", "moreover", etc... it >> usually is a tell the commit should be split. >> >> Here the changes are not related, so please have two separate patches. > > Agreed. I will split this patch for v3. Regards, Jonas > >> The sum of changes is fine though, thanks.
Re: [PATCH 1/1] net: wget: fix TCP sequence number wrap around issue
Hi Yasuharu, On Mon, Apr 15, 2024 at 10:01 AM Yasuharu Shibata wrote: > > If tcp_seq_num is wrap around, tcp_seq_num >= initial_data_seq_num > isn't satisfied and store_block() isn't called. > The condition has a wrap around issue, so it is fixed in this patch. > > Signed-off-by: Yasuharu Shibata Great work! I applied your previous patch: https://lore.kernel.org/u-boot/20240414104607.5966-1-yasuharu.shib...@gmail.com/ and this one against top-of-tree U-Boot and I no longer observe the wget corruption. Reported-by: Tim Harvey Tested-by: Fabio Estevam Thanks a lot for fixing this long-standing wget bug. Cheers, Fabio Estevam
Re: [PATCH 1/1] net: wget: fix TCP sequence number wrap around issue
Hi On Mon, Apr 15, 2024 at 3:55 PM Michael Nazzareno Trimarchi wrote: > > Hi > > On Mon, Apr 15, 2024 at 3:48 PM Yasuharu Shibata > wrote: > > > > Hi Michael, > > > > On Mon, 15 Apr 2024 at 22:03, Michael Nazzareno Trimarchi > > wrote: > > > > > > I think I have sent some time ago ;) > > > > > > Anyway look sane. I was having the same feeling on code inspection > > > > > > Reviewed-by: Michael Trimarchi > > > > Thank you for your review. > > I already checked the thread, sorry I couldn't find your patch and > > I couldn't see whether it is the same. > > In any case, I consider there is a potential issue about > > wrap around, so I submitted a patch. > > > > Very good job ;) to fix it. Just add Suggest-by: ;) > https://lore.kernel.org/all/caomzo5ao5x3ahr0ayriijya309usua0hj6okrhtqqvhw7i8...@mail.gmail.com/T/ Mine was here Michael > Michael > > > -- > > Best regards, > > Yasuharu Shibata > > > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > mich...@amarulasolutions.com > __ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > i...@amarulasolutions.com > www.amarulasolutions.com -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH] ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
On 4/15/24 11:48 AM, Patrice CHOTARD wrote: On 4/14/24 20:39, Marek Vasut wrote: In case of an OTP-CLOSED STM32MP15xx system, the CPU core 1 cannot be released from endless loop in BootROM only by populating TAMP BKPxR 4 and 5 with magic and branch address and sending SGI0 interrupt from core 0 to core 1 twice. TAMP_SMCR BKP..PROT fields must be initialized as well to release the core 1 from endless loop during the second SGI0 handling on core 1. Initialize TAMP_SMCR to protect the first 16 backup registers, the ones which contain the core 1 magic, branch address and boot information. This requirement seems to be undocumented, therefore it was necessary to trace and analyze the STM32MP15xx BootROM using OpenOCD and objdump. Ultimately, it turns out that a certain BootROM function reads out the TAMP_SMCR register and tests whether the BKP..PROT fields are non-zero. If they are zero, the BootROM code again waits for SGI0 using WFI, else the execution moves forward until it reaches handoff to the TAMP BKPxR 5 branch address. This fixes CPU core 1 release using U-Boot PSCI implementation on an OTP-CLOSED system, i.e. system with fuse 0 bit 6 set. Signed-off-by: Marek Vasut --- Cc: Igor Opaniuk Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Tom Rini Cc: u-b...@dh-electronics.com Cc: uboot-st...@st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index dd99150fbc2..138a6d6b614 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include #include #include +#include /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROTGENMASK(23, 16) #define PWR_CR1 (STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* +* TAMP: Configure non-zero secure protection settings. This is +* checked by BootROM function 35ac on OTP-CLOSED device during +* CPU core 1 release from endless loop. If secure protection +* fields are zero, the core 1 is not released from endless +* loop on second SGI0. +*/ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPRWDPROT, Hi Marek there is a typo, you used twice TAMP_SMCR_BKPRWDPROT : TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPRWDPROT => TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT ^ Fixed in V2, thanks. btw are there any other such undocumented surprises in the BootROM ?
Re: [PATCH 1/1] net: wget: fix TCP sequence number wrap around issue
Hi On Mon, Apr 15, 2024 at 3:48 PM Yasuharu Shibata wrote: > > Hi Michael, > > On Mon, 15 Apr 2024 at 22:03, Michael Nazzareno Trimarchi > wrote: > > > > I think I have sent some time ago ;) > > > > Anyway look sane. I was having the same feeling on code inspection > > > > Reviewed-by: Michael Trimarchi > > Thank you for your review. > I already checked the thread, sorry I couldn't find your patch and > I couldn't see whether it is the same. > In any case, I consider there is a potential issue about > wrap around, so I submitted a patch. > Very good job ;) to fix it. Just add Suggest-by: ;) Michael > -- > Best regards, > Yasuharu Shibata -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH 3/4] configs: apple: Enable CMD_SELECT_FONT and FONT_16X32
> From: Janne Grunau via B4 Relay > Date: Sun, 17 Mar 2024 15:54:49 +0100 > > From: Janne Grunau > > Apple devices have high DPI displays so the larger fonts are preferable > for improved readability. This does not yet change the used font based > on the display's pixel density so the standard 8x16 font is still used > by default. > > Signed-off-by: Janne Grunau Reviewed-by: Mark Kettenis > --- > configs/apple_m1_defconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig > index 31d966f0ab..c30aec7c55 100644 > --- a/configs/apple_m1_defconfig > +++ b/configs/apple_m1_defconfig > @@ -9,6 +9,7 @@ CONFIG_SYS_PBSIZE=276 > # CONFIG_DISPLAY_CPUINFO is not set > CONFIG_DISPLAY_BOARDINFO_LATE=y > CONFIG_BOARD_LATE_INIT=y > +CONFIG_CMD_SELECT_FONT=y > # CONFIG_NET is not set > CONFIG_SYS_64BIT_LBA=y > CONFIG_APPLE_SPI_KEYB=y > @@ -19,6 +20,7 @@ CONFIG_USB_XHCI_DWC3=y > CONFIG_USB_XHCI_PCI=y > CONFIG_USB_DWC3=y > CONFIG_USB_KEYBOARD=y > +CONFIG_VIDEO_FONT_16X32=y > CONFIG_SYS_WHITE_ON_BLACK=y > CONFIG_NO_FB_CLEAR=y > CONFIG_VIDEO_SIMPLE=y > > -- > 2.44.0 > > >
Re: [PATCH 2/4] configs: apple: Use "vidconsole,serial" as stdout/stderr
> From: Janne Grunau via B4 Relay > Date: Sun, 17 Mar 2024 15:54:48 +0100 > > From: Janne Grunau > > The display size querying in efi_console relies on this order. The > display should be the primary output device and should be used to > display more than 80x25 chars. > > Signed-off-by: Janne Grunau Reviewed-by: Mark Kettenis > --- > include/configs/apple.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/configs/apple.h b/include/configs/apple.h > index 0576bc04c9..a70440b3ad 100644 > --- a/include/configs/apple.h > +++ b/include/configs/apple.h > @@ -6,8 +6,8 @@ > /* Environment */ > #define ENV_DEVICE_SETTINGS \ > "stdin=serial,usbkbd,spikbd\0" \ > - "stdout=serial,vidconsole\0" \ > - "stderr=serial,vidconsole\0" > + "stdout=vidconsole,serial\0" \ > + "stderr=vidconsole,serial\0" > > #if IS_ENABLED(CONFIG_CMD_NVME) > #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) > > -- > 2.44.0 > > >
Re: [PATCH 1/1] net: wget: fix TCP sequence number wrap around issue
Hi Michael, On Mon, 15 Apr 2024 at 22:03, Michael Nazzareno Trimarchi wrote: > > I think I have sent some time ago ;) > > Anyway look sane. I was having the same feeling on code inspection > > Reviewed-by: Michael Trimarchi Thank you for your review. I already checked the thread, sorry I couldn't find your patch and I couldn't see whether it is the same. In any case, I consider there is a potential issue about wrap around, so I submitted a patch. -- Best regards, Yasuharu Shibata
Re: [PATCH 1/4] apple_m1_defconfig: Turn on CONFIG_SYS_64BIT_LBA
> From: Janne Grunau via B4 Relay > Date: Sun, 17 Mar 2024 15:54:47 +0100 > > From: Hector Martin > > This makes USB HDDs >2TiB work. The only reason this hasn't bitten us > for the internal NVMe yet is the 4K sector size, because the largest SSD > Apple sells is 8TB and we can handle up to 16TiB with that sector size. > Close call. > > Signed-off-by: Hector Martin > Signed-off-by: Janne Grunau Reviewed-by: Mark Kettenis > --- > configs/apple_m1_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig > index e00d72e8be..31d966f0ab 100644 > --- a/configs/apple_m1_defconfig > +++ b/configs/apple_m1_defconfig > @@ -10,6 +10,7 @@ CONFIG_SYS_PBSIZE=276 > CONFIG_DISPLAY_BOARDINFO_LATE=y > CONFIG_BOARD_LATE_INIT=y > # CONFIG_NET is not set > +CONFIG_SYS_64BIT_LBA=y > CONFIG_APPLE_SPI_KEYB=y > # CONFIG_MMC is not set > CONFIG_NVME_APPLE=y > > -- > 2.44.0 > > >
Re: [PATCH 3/3] serial: msm: calculate bit clock divider
On Mon, Apr 15, 2024 at 2:44 PM Caleb Connolly
wrote:
>
> The driver currently requires the bit clock divider be hardcoded in
> devicetree (or use the hardcoded default from apq8016).
>
> The bit clock divider is used to derive the baud rate from the core
> clock:
>
> baudrate = clk_rate / csr_div
>
> clk_rate is the actual programmed core clock rate which is returned by
> clk_set_rate(), and this UART driver only supports a baudrate of 115200.
> We can therefore determine the appropriate value for UARTDM_CSR by
> iterating over the possible values and finding the one where the
> equation above holds true for a baudrate of 115200.
>
> Implement this logic and drop the non-standard DT bindings for this
> driver.
>
> Tested on dragonboard410c.
>
> Signed-off-by: Caleb Connolly
Works on Alfa AP120C (IPQ4018) with full DM UART, but debug UART
prints junk since .clk_rate = 7372800 is not correct for IPQ40xx.
I would suggest using .clk_rate = CONFIG_VAL(DEBUG_UART_CLOCK) instead
to populate the value per board, this also avoids per ARCH ifdefs.
Regards,
Robert
> ---
> Cc: Robert Marko
> ---
> doc/device-tree-bindings/serial/msm-serial.txt | 10 ---
> drivers/serial/serial_msm.c| 87
> +-
> 2 files changed, 70 insertions(+), 27 deletions(-)
>
> diff --git a/doc/device-tree-bindings/serial/msm-serial.txt
> b/doc/device-tree-bindings/serial/msm-serial.txt
> deleted file mode 100644
> index dca995798a90..
> --- a/doc/device-tree-bindings/serial/msm-serial.txt
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -Qualcomm UART (Data Mover mode)
> -
> -Required properties:
> -- compatible: must be "qcom,msm-uartdm-v1.4"
> -- reg: start address and size of the registers
> -- clock: interface clock (must accept baudrate as a frequency)
> -
> -Optional properties:
> -- bit-rate: Data Mover bit rate register value
> - (If not defined then 0xCC is used as default)
> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> index 8044d38518db..e461929b4338 100644
> --- a/drivers/serial/serial_msm.c
> +++ b/drivers/serial/serial_msm.c
> @@ -31,8 +31,18 @@
> #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing
> buffer */
> #define UARTDM_RXFS_BUF_MASK0x7
> #define UARTDM_MR1 0x00
> #define UARTDM_MR2 0x04
> +/*
> + * This is documented on page 1817 of the apq8016e technical reference
> manual.
> + * section 6.2.5.3.26
> + *
> + * The upper nybble contains the bit clock divider for the RX pin, the lower
> + * nybble defines the TX pin. In almost all cases these should be the same
> value.
> + *
> + * The baud rate is the core clock frequency divided by the fixed divider
> value
> + * programmed into this register (defined in calc_csr_bitrate()).
> + */
> #define UARTDM_CSR 0xA0
>
> #define UARTDM_SR0xA4 /* Status register */
> #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
> @@ -52,9 +62,8 @@
>
> #define UARTDM_TF 0x100 /* UART Transmit FIFO register */
> #define UARTDM_RF 0x140 /* UART Receive FIFO register */
>
> -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
> #define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
> #define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
> #define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
>
> @@ -63,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR;
> struct msm_serial_data {
> phys_addr_t base;
> unsigned chars_cnt; /* number of buffered chars */
> uint32_t chars_buf; /* buffered chars */
> - uint32_t clk_bit_rate; /* data mover mode bit rate register value */
> + uint32_t clk_rate; /* core clock rate */
> };
>
> static int msm_serial_fetch(struct udevice *dev)
> {
> @@ -155,34 +164,63 @@ static const struct dm_serial_ops msm_serial_ops = {
> .pending = msm_serial_pending,
> .getc = msm_serial_getc,
> };
>
> -static int msm_uart_clk_init(struct udevice *dev)
> +static long msm_uart_clk_init(struct udevice *dev)
> {
> - uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
> - "clock-frequency", 115200);
> + struct msm_serial_data *priv = dev_get_priv(dev);
> struct clk clk;
> int ret;
> + long rate;
>
> ret = clk_get_by_name(dev, "core", );
> if (ret < 0) {
> pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
> - return ret;
> + return 0;
> }
>
> - ret = clk_set_rate(, clk_rate);
> - if (ret < 0)
> - return ret;
> + rate = clk_set_rate(, priv->clk_rate);
>
> - return 0;
> + return rate;
> +}
> +
> +static int calc_csr_bitrate(struct msm_serial_data *priv)
> +{
> + /* This table is from the TRE. See the definition of UARTDM_CSR */
> + unsigned int csr_div_table[] = {24576, 12288, 6144, 3072, 1536,
Re: [PATCH 1/1] net: wget: fix TCP sequence number wrap around issue
Hi
On Mon, Apr 15, 2024 at 3:01 PM Yasuharu Shibata
wrote:
>
> If tcp_seq_num is wrap around, tcp_seq_num >= initial_data_seq_num
> isn't satisfied and store_block() isn't called.
> The condition has a wrap around issue, so it is fixed in this patch.
>
> Signed-off-by: Yasuharu Shibata
> ---
> net/wget.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/net/wget.c b/net/wget.c
> index 71bac92d84..abab371e58 100644
> --- a/net/wget.c
> +++ b/net/wget.c
> @@ -404,9 +404,7 @@ static void wget_handler(uchar *pkt, u16 dport,
> }
> next_data_seq_num = tcp_seq_num + len;
>
> - if (tcp_seq_num >= initial_data_seq_num &&
> - store_block(pkt, tcp_seq_num - initial_data_seq_num,
> - len) != 0) {
> + if (store_block(pkt, tcp_seq_num - initial_data_seq_num, len)
> != 0) {
> wget_fail("wget: store error\n",
> tcp_seq_num, tcp_ack_num, action);
> net_set_state(NETLOOP_FAIL);
I think I have sent some time ago ;)
Anyway look sane. I was having the same feeling on code inspection
Reviewed-by: Michael Trimarchi
> --
> 2.25.1
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
[PATCH 1/1] net: wget: fix TCP sequence number wrap around issue
If tcp_seq_num is wrap around, tcp_seq_num >= initial_data_seq_num
isn't satisfied and store_block() isn't called.
The condition has a wrap around issue, so it is fixed in this patch.
Signed-off-by: Yasuharu Shibata
---
net/wget.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/net/wget.c b/net/wget.c
index 71bac92d84..abab371e58 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -404,9 +404,7 @@ static void wget_handler(uchar *pkt, u16 dport,
}
next_data_seq_num = tcp_seq_num + len;
- if (tcp_seq_num >= initial_data_seq_num &&
- store_block(pkt, tcp_seq_num - initial_data_seq_num,
- len) != 0) {
+ if (store_block(pkt, tcp_seq_num - initial_data_seq_num, len)
!= 0) {
wget_fail("wget: store error\n",
tcp_seq_num, tcp_ack_num, action);
net_set_state(NETLOOP_FAIL);
--
2.25.1
[PATCH 0/1] net: wget: fix TCP sequence number wrap around issue
Hi,
I send a patch fixing the wget issue.
There is a wrap around issue as already mentioned in [1].
The log in [2] indicates the following packets.
- Success packet
Packets received 64368, Transfer Successful
Bytes transferred = 93198937 (58e1a59 hex)
- Failed packet
Packets received 64368, Transfer Successful
Bytes transferred = 26984682 (19bc0ea hex)
"Bytes transferred" are different, but "Packets received" are same.
First one output by net_boot_file_size that is assigned at store_block().
Second one output by packets that is incremented at wget_handler().
Those differences are caused by the following line.
If tcp_seq_num is wrap around, store_block() isn't called.
```
static void wget_handler(uchar *pkt, u16 dport,
...
if (tcp_seq_num >= initial_data_seq_num &&
store_block(pkt, tcp_seq_num - initial_data_seq_num,
len) != 0) {
wget_fail("wget: store error\n",
tcp_seq_num, tcp_ack_num, action);
net_set_state(NETLOOP_FAIL);
return;
}
```
I reproduced the issue and fixed it with the following patch.
Please check this patch.
I will recommend to apply patch in [3] with this patch,
if packets may drop.
[1]:
https://lore.kernel.org/u-boot/caof5uwmb0vjowsj81kvfwpk6yobyz0ozm5vdgca9k0rzejb...@mail.gmail.com/
[2]:
https://lore.kernel.org/u-boot/caj+vnu2u9w2nrt6hf1caeq_56sdqviuezudd1iyopdf1cna...@mail.gmail.com/
[3]:
https://lore.kernel.org/u-boot/20240414104607.5966-1-yasuharu.shib...@gmail.com/
Yasuharu Shibata (1):
net: wget: fix TCP sequence number wrap around issue
net/wget.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
--
2.25.1
[PATCH v2] ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
In case of an OTP-CLOSED STM32MP15xx system, the CPU core 1 cannot be released from endless loop in BootROM only by populating TAMP BKPxR 4 and 5 with magic and branch address and sending SGI0 interrupt from core 0 to core 1 twice. TAMP_SMCR BKP..PROT fields must be initialized as well to release the core 1 from endless loop during the second SGI0 handling on core 1. Initialize TAMP_SMCR to protect the first 16 backup registers, the ones which contain the core 1 magic, branch address and boot information. This requirement seems to be undocumented, therefore it was necessary to trace and analyze the STM32MP15xx BootROM using OpenOCD and objdump. Ultimately, it turns out that a certain BootROM function reads out the TAMP_SMCR register and tests whether the BKP..PROT fields are non-zero. If they are zero, the BootROM code again waits for SGI0 using WFI, else the execution moves forward until it reaches handoff to the TAMP BKPxR 5 branch address. This fixes CPU core 1 release using U-Boot PSCI implementation on an OTP-CLOSED system, i.e. system with fuse 0 bit 6 set. Signed-off-by: Marek Vasut --- Cc: Igor Opaniuk Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Tom Rini Cc: u-b...@dh-electronics.com Cc: uboot-st...@st-md-mailman.stormreply.com --- V2: Fix up the BKPRWD/BKPWD mask typo --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index dd99150fbc2..a2496361e01 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include #include #include +#include /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROTGENMASK(23, 16) #define PWR_CR1(STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* +* TAMP: Configure non-zero secure protection settings. This is +* checked by BootROM function 35ac on OTP-CLOSED device during +* CPU core 1 release from endless loop. If secure protection +* fields are zero, the core 1 is not released from endless +* loop on second SGI0. +*/ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x10) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x10)); + /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); -- 2.43.0
RE: [PATCH v6 0/5] imx93: Conver to OF_UPSTREAM
> Subject: Re: [PATCH v6 0/5] imx93: Conver to OF_UPSTREAM > > Hi Peng, > > On Fri, Apr 12, 2024 at 10:40 AM Fabio Estevam > wrote: > > > > On Fri, Apr 12, 2024 at 10:24 AM Peng Fan (OSS) > wrote: > > > > > > A few nodes were added to soc and board u-boot.dtsi(lpi2c, usbotg), > > > those nodes could be dropped after upstream linux supports them. > > > > > > To support OF_UPSTREAM, a few driver changes are included. > > > For TMU, still use U-Boot node, I will prepare a kernel update, then > > > back to U-Boot support. > > > > > > Mathieu: please help test the boards you maintain when you have time. > > > > The series looks good. > > > > I will apply it after Mathieu or the Phytec folks confirm this series > > does not break imx93-phyboard-segin. > > I applied patches 1 to 4, thanks. > > I dropped the last OF_UPSTREAM patch as it is causing boot issues on > Mathieu's tests. ok. Do I need to switch back to only convert i.MX93 11x11 EVK to OF_UPSTREM? Thanks, Peng.
Re: [PATCH v2] usb: dwc3-generic: fix support without DM_REGULATOR
On 15/04/2024 12:56, Robert Marko wrote:
> Recent addition of vbus-supply support has broke platform which dont use
> controllable regulators for USB.
>
> Issue is that even withou DM_REGULATOR being enabled regulator related
> functions will still build as there is a stub in regulator.h but they will
> simply return -ENOSYS which will then make dwc3_generic_host_probe()
> return the same error thus breaking probe.
>
> So, check whether return code is -ENOSYS before erroring out.
>
> Fixes: de451d5d5b6f ("usb: dwc3-generic: support external vbus regulator")
> Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
> ---
> Changes in v2:
> * Drop #ifdefs and check for -ENOSYS that regulator stub returns
>
> drivers/usb/dwc3/dwc3-generic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> index 7a00529a2a..df0b0b8c02 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -248,7 +248,7 @@ static int dwc3_generic_host_probe(struct udevice *dev)
>
> /* Only returns an error if regulator is valid and failed to enable due
> to a driver issue */
> rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
> - if (rc)
> + if (rc && rc != -ENOSYS)
> return rc;
>
> hccr = (struct xhci_hccr *)priv->gen_priv.base;
--
// Caleb (they/them)
Re: [PATCH 4/4] Kconfig: Make all Kconfig encoding ascii
On 4/15/24 14:22, Heinrich Schuchardt wrote: On 15.04.24 13:35, Michal Simek wrote: Some of Kconfigs are using utf-8 encoding because of used chars. Convert all of them to ascii enconging. Signed-off-by: Michal Simek --- There are other files which are using utf-8 enconding and pretty much I think we should convert all of them because there is no reason to use utf-8 encoding. Hello Michal, The commit message does not explain why we should refrain from using UTF-8. that's a good point. I was thinking about the reason for it and pretty much wanted to get feedback from Tom about it. In doc/develop/sending_patches.rst is said that patches should be sent as plain text but encoding is not specified. Traditionally this was ASCII and I pretty much don't see the reason to use UTF encoding (even my name has special czech char which I am not using, the same is for Marek Vasut). Thanks, Michal
Re: [PATCH 2/4] Kconfig: Add missing quotes around source file
On 4/15/24 14:44, Heinrich Schuchardt wrote: On 15.04.24 13:35, Michal Simek wrote: All errors are generated by ./tools/qconfig.py -b -j8 -i whatever. Error look like this: drivers/crypto/Kconfig:9: warning: style: quotes recommended around 'drivers/crypto/nuvoton/Kconfig' in 'source drivers/crypto/nuvoton/Kconfig' Should we add a qconfig.py test to our CI? When things are without warnings that would be the best. M
Re: [PATCH 2/4] Kconfig: Add missing quotes around source file
On 15.04.24 13:35, Michal Simek wrote: All errors are generated by ./tools/qconfig.py -b -j8 -i whatever. Error look like this: drivers/crypto/Kconfig:9: warning: style: quotes recommended around 'drivers/crypto/nuvoton/Kconfig' in 'source drivers/crypto/nuvoton/Kconfig' Should we add a qconfig.py test to our CI? Best regards Heinrich Signed-off-by: Michal Simek --- arch/arm/mach-rockchip/rk3588/Kconfig | 18 +- arch/arm/mach-rockchip/rv1108/Kconfig | 4 ++-- arch/arm/mach-rockchip/rv1126/Kconfig | 4 ++-- cmd/Kconfig | 2 +- drivers/crypto/Kconfig| 8 lib/Kconfig | 18 +- 6 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index d7e4af31f24c..eb956b097c74 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -221,14 +221,14 @@ config ROCKCHIP_COMMON_STACK_ADDR config TEXT_BASE default 0x00a0 -source board/edgeble/neural-compute-module-6/Kconfig -source board/friendlyelec/nanopc-t6-rk3588/Kconfig -source board/pine64/quartzpro64-rk3588/Kconfig -source board/turing/turing-rk1-rk3588/Kconfig -source board/radxa/rock5a-rk3588s/Kconfig -source board/radxa/rock5b-rk3588/Kconfig -source board/rockchip/evb_rk3588/Kconfig -source board/rockchip/toybrick_rk3588/Kconfig -source board/theobroma-systems/jaguar_rk3588/Kconfig +source "board/edgeble/neural-compute-module-6/Kconfig" +source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" +source "board/pine64/quartzpro64-rk3588/Kconfig" +source "board/turing/turing-rk1-rk3588/Kconfig" +source "board/radxa/rock5a-rk3588s/Kconfig" +source "board/radxa/rock5b-rk3588/Kconfig" +source "board/rockchip/evb_rk3588/Kconfig" +source "board/rockchip/toybrick_rk3588/Kconfig" +source "board/theobroma-systems/jaguar_rk3588/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index a12216dccf66..28ed0b245812 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -36,7 +36,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -source board/rockchip/evb_rv1108/Kconfig -source board/elgin/elgin_rv1108/Kconfig +source "board/rockchip/evb_rv1108/Kconfig" +source "board/elgin/elgin_rv1108/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig index 55b11121203b..ae323ee91235 100644 --- a/arch/arm/mach-rockchip/rv1126/Kconfig +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -64,7 +64,7 @@ config SYS_MALLOC_F_LEN config TEXT_BASE default 0x60 -source board/edgeble/neural-compute-module-2/Kconfig -source board/itead/sonoff-ihost/Kconfig +source "board/edgeble/neural-compute-module-2/Kconfig" +source "board/itead/sonoff-ihost/Kconfig" endif diff --git a/cmd/Kconfig b/cmd/Kconfig index 8eeb99eea5ed..45c206369518 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -398,7 +398,7 @@ config CMD_BOOTEFI_HELLO for testing that EFI is working at a basic level, and for bringing up EFI support on a new architecture. -source lib/efi_selftest/Kconfig +source "lib/efi_selftest/Kconfig" endif config CMD_BOOTMENU diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 12ef84ca05ca..8b49997030b4 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -1,11 +1,11 @@ menu "Hardware crypto devices" -source drivers/crypto/hash/Kconfig +source "drivers/crypto/hash/Kconfig" -source drivers/crypto/fsl/Kconfig +source "drivers/crypto/fsl/Kconfig" -source drivers/crypto/aspeed/Kconfig +source "drivers/crypto/aspeed/Kconfig" -source drivers/crypto/nuvoton/Kconfig +source "drivers/crypto/nuvoton/Kconfig" endmenu diff --git a/lib/Kconfig b/lib/Kconfig index efb77978a652..189e6eb31aa1 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -416,7 +416,7 @@ config TRACE_EARLY_ADDR config CIRCBUF bool "Enable circular buffer support" -source lib/dhry/Kconfig +source "lib/dhry/Kconfig" menu "Security support" @@ -429,10 +429,10 @@ config AES supported by the algorithm but only a 128-bit key is supported at present. -source lib/ecdsa/Kconfig -source lib/rsa/Kconfig -source lib/crypto/Kconfig -source lib/crypt/Kconfig +source "lib/ecdsa/Kconfig" +source "lib/rsa/Kconfig" +source "lib/crypto/Kconfig" +source "lib/crypt/Kconfig" config TPM bool "Trusted Platform Module (TPM) Support" @@ -1081,9 +1081,9 @@ config SMBIOS_PARSER help A simple parser for SMBIOS data. -source lib/efi/Kconfig -source lib/efi_loader/Kconfig -source lib/optee/Kconfig +source "lib/efi/Kconfig" +source "lib/efi_loader/Kconfig" +source "lib/optee/Kconfig" config TEST_FDTDEC bool "enable fdtdec test" @@ -1148,4 +1148,4 @@ config PHANDLE_CHECK_SEQ endmenu -source
[PATCH 3/3] serial: msm: calculate bit clock divider
The driver currently requires the bit clock divider be hardcoded in
devicetree (or use the hardcoded default from apq8016).
The bit clock divider is used to derive the baud rate from the core
clock:
baudrate = clk_rate / csr_div
clk_rate is the actual programmed core clock rate which is returned by
clk_set_rate(), and this UART driver only supports a baudrate of 115200.
We can therefore determine the appropriate value for UARTDM_CSR by
iterating over the possible values and finding the one where the
equation above holds true for a baudrate of 115200.
Implement this logic and drop the non-standard DT bindings for this
driver.
Tested on dragonboard410c.
Signed-off-by: Caleb Connolly
---
Cc: Robert Marko
---
doc/device-tree-bindings/serial/msm-serial.txt | 10 ---
drivers/serial/serial_msm.c| 87 +-
2 files changed, 70 insertions(+), 27 deletions(-)
diff --git a/doc/device-tree-bindings/serial/msm-serial.txt
b/doc/device-tree-bindings/serial/msm-serial.txt
deleted file mode 100644
index dca995798a90..
--- a/doc/device-tree-bindings/serial/msm-serial.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Qualcomm UART (Data Mover mode)
-
-Required properties:
-- compatible: must be "qcom,msm-uartdm-v1.4"
-- reg: start address and size of the registers
-- clock: interface clock (must accept baudrate as a frequency)
-
-Optional properties:
-- bit-rate: Data Mover bit rate register value
- (If not defined then 0xCC is used as default)
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 8044d38518db..e461929b4338 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -31,8 +31,18 @@
#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer
*/
#define UARTDM_RXFS_BUF_MASK0x7
#define UARTDM_MR1 0x00
#define UARTDM_MR2 0x04
+/*
+ * This is documented on page 1817 of the apq8016e technical reference manual.
+ * section 6.2.5.3.26
+ *
+ * The upper nybble contains the bit clock divider for the RX pin, the lower
+ * nybble defines the TX pin. In almost all cases these should be the same
value.
+ *
+ * The baud rate is the core clock frequency divided by the fixed divider value
+ * programmed into this register (defined in calc_csr_bitrate()).
+ */
#define UARTDM_CSR 0xA0
#define UARTDM_SR0xA4 /* Status register */
#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
@@ -52,9 +62,8 @@
#define UARTDM_TF 0x100 /* UART Transmit FIFO register */
#define UARTDM_RF 0x140 /* UART Receive FIFO register */
-#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
@@ -63,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR;
struct msm_serial_data {
phys_addr_t base;
unsigned chars_cnt; /* number of buffered chars */
uint32_t chars_buf; /* buffered chars */
- uint32_t clk_bit_rate; /* data mover mode bit rate register value */
+ uint32_t clk_rate; /* core clock rate */
};
static int msm_serial_fetch(struct udevice *dev)
{
@@ -155,34 +164,63 @@ static const struct dm_serial_ops msm_serial_ops = {
.pending = msm_serial_pending,
.getc = msm_serial_getc,
};
-static int msm_uart_clk_init(struct udevice *dev)
+static long msm_uart_clk_init(struct udevice *dev)
{
- uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "clock-frequency", 115200);
+ struct msm_serial_data *priv = dev_get_priv(dev);
struct clk clk;
int ret;
+ long rate;
ret = clk_get_by_name(dev, "core", );
if (ret < 0) {
pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
- return ret;
+ return 0;
}
- ret = clk_set_rate(, clk_rate);
- if (ret < 0)
- return ret;
+ rate = clk_set_rate(, priv->clk_rate);
- return 0;
+ return rate;
+}
+
+static int calc_csr_bitrate(struct msm_serial_data *priv)
+{
+ /* This table is from the TRE. See the definition of UARTDM_CSR */
+ unsigned int csr_div_table[] = {24576, 12288, 6144, 3072, 1536, 768,
512, 384,
+ 256, 192, 128, 96, 64, 48,
32, 16};
+ int i = ARRAY_SIZE(csr_div_table) - 1;
+ /* Currently we only support one baudrate */
+ int baud = 115200;
+
+ for (; i >= 0; i--) {
+ int x = priv->clk_rate / csr_div_table[i];
+
+ if (x == baud)
+ /* Duplicate the configuration for RX
+* as the lower nybble only configures TX
+*/
+ return i + (i << 4);
+ }
+
+
[PATCH 2/3] clk/qcom: ipq4019: return valid rate when setting UART clock
clk_set_rate() should return the clock rate that was set. The IPQ4019
clock driver doesn't set any rates yet but it should still return the
expected value so that drivers can work properly.
For a baud rate of 115200 with an expected bit clock divisor of 16, the
clock rate should be 1843200 so return that frequency.
Signed-off-by: Caleb Connolly
---
drivers/clk/qcom/clock-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c
index d693776d339d..72f235eab212 100644
--- a/drivers/clk/qcom/clock-ipq4019.c
+++ b/drivers/clk/qcom/clock-ipq4019.c
@@ -20,9 +20,9 @@ static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
{
switch (clk->id) {
case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
/* This clock is already initialized by SBL1 */
- return 0;
+ return 1843200;
default:
return -EINVAL;
}
}
--
2.44.0
[PATCH 1/3] clk/qcom: apq8016: return valid rate when setting UART clock
The clk_init_uart() helper always returns 0, but we're meant to return a real clock rate. Given that we hardcode 115200 baud, just return the clock rate that we set. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-apq8016.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 5a5868169c89..6210fba87984 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -99,10 +99,10 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) case GCC_SDCC2_APPS_CLK: /* SDC2 */ return clk_init_sdc(priv, 1, rate); break; case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ - return apq8016_clk_init_uart(priv->base); - break; + apq8016_clk_init_uart(priv->base); + return 7372800; default: return 0; } } -- 2.44.0
[PATCH 0/3] qcom: serial_msm: calculate UARTDM_CSR automatically
The msm serial UART controller has a bit clock divider register which much be programmed based on the UART clock. This changes per soc and currently is expected to be specified in DT or otherwise selected per board. This series fixes the apq8016 and ipq4019 clock drivers to return the programmed UART clock rate in clk_set_rate(), it then uses this clock rate and the hardcoded baud rate supported by this driver to calculate the correct value for the UARTDM_CSR register. --- Caleb Connolly (3): clk/qcom: apq8016: return valid rate when setting UART clock clk/qcom: ipq4019: return valid rate when setting UART clock serial: msm: calculate bit clock divider doc/device-tree-bindings/serial/msm-serial.txt | 10 --- drivers/clk/qcom/clock-apq8016.c | 4 +- drivers/clk/qcom/clock-ipq4019.c | 2 +- drivers/serial/serial_msm.c| 87 +- 4 files changed, 73 insertions(+), 30 deletions(-) --- base-commit: 42f6978987336cff3d98d9cc4643c54a1eb0f36d // Caleb (they/them)
[PATCH] env: mmc: print MMC device being read
From: Quentin Schulz
This prints the MMC device being read similar to how we print the MMC
device we write to when e.g. calling saveenv.
One of the side effects is that the boot log now shows from which MMC
device the env was loaded:
Loading Environment from MMC... Reading from MMC(1)... OK
This is useful to identify which MMC device the environment was loaded
from for boards where there are more than one (e.g. eMMC and SD card)
without adding some debug messages manually.
Sadly, there's no way to know which of the default or redundant
environment is being read from env_mmc_load before env_import_redund is
called so it is printing a bit later (and possibly after error/warning
messages).
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
env/mmc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/env/mmc.c b/env/mmc.c
index da84cddd74f..7afb733e890 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -436,6 +436,7 @@ static int env_mmc_load(void)
ret = env_import_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2,
read2_fail, H_EXTERNAL);
+ printf("Reading from %sMMC(%d)... ", gd->env_valid == ENV_REDUND ?
"redundant " : "", dev);
fini:
fini_mmc_for_env(mmc);
@@ -475,6 +476,8 @@ static int env_mmc_load(void)
goto fini;
}
+ printf("Reading from MMC(%d)... ", dev);
+
ret = env_import(buf, 1, H_EXTERNAL);
if (!ret) {
ep = (env_t *)buf;
---
base-commit: b03b49046af5dfca599d2ce8f0aafed89b97aa91
change-id: 20240415-mmc-loadenv-dev-ced678171e98
Best regards,
--
Quentin Schulz
Re: [PATCH 3/4] Kconfig: Add missing quotes around default string value
On 15.04.24 13:35, Michal Simek wrote: All errors are generated by ./tools/qconfig.py -b -j8 -i whatever. Error look like this: warning: style: quotes recommended around default value for string symbol EFI_VAR_SEED_FILE (defined at lib/efi_loader/Kconfig:130) Signed-off-by: Michal Simek --- lib/efi_loader/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index e13a6f9f4c3a..a5ab7d1b262f 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -129,7 +129,7 @@ if EFI_VARIABLES_PRESEED config EFI_VAR_SEED_FILE string "File with initial values of non-volatile UEFI variables" - default ubootefi.var + default "ubootefi.var" help File with initial values of non-volatile UEFI variables. The file must be in the same format as the storage in the EFI system partition. The Reviewed-by: Heinrich Schuchardt
Re: [PATCH v2 12/23] rockchip: rk3588: Update bootph props
Hi Quentin,
On 2024-04-15 10:55, Quentin Schulz wrote:
> Hi Jonas,
>
> On 4/13/24 20:13, Jonas Karlman wrote:
>> After the commit aca95282c1b7 ("Makefile: Use the fdtgrep -u flag")
>> bootph props is propagating to parent nodes.
>>
>> Update bootph props to ensure eMMC, SD-card and SPI flash is available
>> in SPL and U-Boot proper pre-reloc phase also remove unneeded bootph
>> props that automatically is propagated to parent nodes.
>>
>> Also adjust pinctrl nodes to only be included in boot phases where they
>> are needed and add any missing pinctrl node needed in SPL.
>>
>> Signed-off-by: Jonas Karlman
>> ---
>> v2: Add bootph-some-ram props and follow kernel sort order
>>
>> Following bootph props have been applied:
>>
>> CRU, GRF and UART nodes:
>> - bootph-all - needed at all or most stages
>>
>> SD-card regulator related nodes:
>> - bootph-pre-ram (SPL) - regulator pinctrl may be needed to read FIT
>>from SD-card on some boards
>>
>> eMMC/SD-card/SPI flash related nodes:
>> - bootph-pre-ram (SPL)
>> - bootph-some-ram (U-Boot proper pre-reloc)
>> ---
>> .../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi | 8 +--
>> arch/arm/dts/rk3588-generic.dts | 1 +
>> arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi | 12 ++---
>> .../dts/rk3588-orangepi-5-plus-u-boot.dtsi| 7 ++-
>> arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 8 +--
>> arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi| 6 ++-
>> arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi| 8 +--
>> arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi | 9 ++--
>> arch/arm/dts/rk3588s-u-boot.dtsi | 50 ++-
>> configs/evb-rk3588_defconfig | 4 +-
>> 10 files changed, 71 insertions(+), 42 deletions(-)
>>
>> diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
>> b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
>> index ed15b14ea0ee..f0ef0164664e 100644
>> --- a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
>> +++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
>> @@ -3,7 +3,8 @@
>> #include "rk3588-u-boot.dtsi"
>>
>> _pins {
>> -bootph-all;
>> +bootph-pre-ram;
>> +bootph-some-ram;
>> };
>>
>>{
>> @@ -12,16 +13,15 @@
>> };
>>
>>{
>> -bootph-pre-ram;
>> -u-boot,spl-sfc-no-dma;
>> pinctrl-names = "default";
>> pinctrl-0 = <_pins>;
>> status = "okay";
>>
>> flash@0 {
>> -bootph-pre-ram;
>> compatible = "jedec,spi-nor";
>> reg = <0>;
>> +bootph-pre-ram;
>> +bootph-some-ram;
>> spi-max-frequency = <2400>;
>> spi-rx-bus-width = <4>;
>> spi-tx-bus-width = <1>;
>> diff --git a/arch/arm/dts/rk3588-generic.dts
>> b/arch/arm/dts/rk3588-generic.dts
>> index e4721d97a87d..baafe7463f1b 100644
>> --- a/arch/arm/dts/rk3588-generic.dts
>> +++ b/arch/arm/dts/rk3588-generic.dts
>> @@ -40,5 +40,6 @@
>> };
>>
>>{
>> +pinctrl-0 = <_xfer>;
>
> I think this should be its own patch.
Sure, will move this to its own patch in v3.
>
> [...]
>> diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
>> index 68ecbc54b807..610a8d740fbb 100644
>> --- a/configs/evb-rk3588_defconfig
>> +++ b/configs/evb-rk3588_defconfig
>> @@ -33,7 +33,8 @@ CONFIG_CMD_REGULATOR=y
>> # CONFIG_SPL_DOS_PARTITION is not set
>> CONFIG_SPL_OF_CONTROL=y
>> CONFIG_OF_LIVE=y
>> -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names
>> interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
>> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
>> assigned-clock-rates assigned-clock-parents"
>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>> CONFIG_SPL_REGMAP=y
>> CONFIG_SPL_SYSCON=y
>> CONFIG_SPL_CLK=y
>> @@ -52,6 +53,7 @@ CONFIG_DWC_ETH_QOS_ROCKCHIP=y
>> CONFIG_PHY_ROCKCHIP_INNO_USB2=y
>> CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
>> CONFIG_PHY_ROCKCHIP_USBDP=y
>> +CONFIG_SPL_PINCTRL=y
>
> I have a feeling the changes to the defconfig aren't entirely related to
> this patch? Specifically, I think at least CONFIG_SPL_DM_SEQ_ALIAS isn't
> related?
My original intent of this entire series was to fix/align bootph props
and pinctrl use across boards, but after more and more testing it has
grown a little bit out of control ;-)
For proper handling in SPL we also need the SPL_DM_SEQ_ALIAS enabled.
In the future I would like to see a ROCKCHIP_COMMON_OPTIONS or similar
that imply all these common options, for now this and my other series
just tries to get more boards to using all these common options.
Will split out to a evb specific patch in v3.
Regards,
Jonas
>
> Otherwise,
>
> Reviewed-by: Quentin Schulz
>
> Thanks,
> Quentin
Re: [PATCH v6 0/5] imx93: Conver to OF_UPSTREAM
Hi Peng, On Fri, Apr 12, 2024 at 10:40 AM Fabio Estevam wrote: > > On Fri, Apr 12, 2024 at 10:24 AM Peng Fan (OSS) wrote: > > > > A few nodes were added to soc and board u-boot.dtsi(lpi2c, usbotg), those > > nodes > > could be dropped after upstream linux supports them. > > > > To support OF_UPSTREAM, a few driver changes are included. > > For TMU, still use U-Boot node, I will prepare a kernel update, > > then back to U-Boot support. > > > > Mathieu: please help test the boards you maintain when you have time. > > The series looks good. > > I will apply it after Mathieu or the Phytec folks confirm this series > does not break imx93-phyboard-segin. I applied patches 1 to 4, thanks. I dropped the last OF_UPSTREAM patch as it is causing boot issues on Mathieu's tests.
[GIT PULL] Please pull u-boot-imx-master-20240415
Hi Tom, Please pull from u-boot-imx/master, thanks. The following changes since commit b03b49046af5dfca599d2ce8f0aafed89b97aa91: Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2024-04-14 15:58:31 -0600) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-master-20240415 for you to fetch changes up to 8ecb0931940cc19728d686b9dba06585f4d93709: clk: imx93: fix anatop base (2024-04-15 08:09:41 -0300) u-boot-imx-master-20240415 -- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/20348 - Update the imx_rgpio2p to only access one address as per the dt-schema. - Remove unused imx9_cpu.c file. - Only use the LPUART ipg clk for i.MX7ULP. - Use the correct anatop base for accessing the PLL clocks on i.MX93. Peng Fan (4): gpio: imx_rgpio2p: support one address serial: lpuart: use ipg clk for i.MX7ULP cpu: drop imx9_cpu clk: imx93: fix anatop base drivers/clk/imx/clk-imx93.c| 2 +- drivers/cpu/imx9_cpu.c | 224 - drivers/gpio/imx_rgpio2p.c | 42 +++- drivers/serial/serial_lpuart.c | 42 +--- 4 files changed, 65 insertions(+), 245 deletions(-) delete mode 100644 drivers/cpu/imx9_cpu.c
Re: [PATCH 4/4] Kconfig: Make all Kconfig encoding ascii
On 15.04.24 13:35, Michal Simek wrote: Some of Kconfigs are using utf-8 encoding because of used chars. Convert all of them to ascii enconging. Signed-off-by: Michal Simek --- There are other files which are using utf-8 enconding and pretty much I think we should convert all of them because there is no reason to use utf-8 encoding. Hello Michal, The commit message does not explain why we should refrain from using UTF-8. --- arch/arm/mach-rockchip/px30/Kconfig | 4 ++-- arch/arm/mach-rockchip/rk3588/Kconfig | 6 +++--- arch/arm/mach-rockchip/rv1126/Kconfig | 4 ++-- drivers/mtd/spi/Kconfig | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 41893920cb4d..23f8f430c4ae 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -36,9 +36,9 @@ config TARGET_PX30_CORE 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. config TARGET_RINGNECK_PX30 - bool "Theobroma Systems PX30-µQ7 (Ringneck)" + bool "Theobroma Systems PX30-uQ7 (Ringneck)" help - The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, + The PX30-uQ7 (Ringneck) SoM is a uQseven-compatible (40mmx70mm, MXM-230 connector) system-on-module from Theobroma Systems[1], featuring the Rockchip PX30. diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index eb956b097c74..39049ab35a9c 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -66,7 +66,7 @@ config TARGET_NANOPCT6_RK3588 HDMI2.0, and HDMI1.4 2x 4-lane MIPI-DSI, compatible with MIPI DPHY 2.0 or CPHY 1.1 USB-A: USB 3.0, Type A - USB-C: Full function USB Type‑C port, DP display up to 4Kp60, USB 3.0 + USB-C: Full function USB Type-C port, DP display up to 4Kp60, USB 3.0 40-pin 2.54mm header connector: up to 2x SPIs, 6x UARTs, 1x I2Cs, 8x PWMs, 2x I2Ss, 28x GPIOs Debug UART: 3 Pin 2.54mm header, 3V level, 150bps @@ -117,7 +117,7 @@ config TARGET_ROCK5A_RK3588 Mali G610MC4 GPU MIPI CSI 2 multiple lanes connector 4-lane MIPI DSI connector - Audio – 3.5mm earphone jack + Audio - 3.5mm earphone jack eMMC module connector uSD slot (up to 128GB) 2x USB 2.0, 2x USB 3.0 @@ -197,7 +197,7 @@ config TARGET_TOYBRICK_RK3588 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB Memory LPDDR4x Mali G610MC4 GPU - 2× MIPI-CSI0 Connector + 2x MIPI-CSI0 Connector 1x 2Lanes PCIe3.0 Connector 1x SATA3.0 Connector 32GB eMMC Module diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig index ae323ee91235..64a70f61f894 100644 --- a/arch/arm/mach-rockchip/rv1126/Kconfig +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -6,8 +6,8 @@ config TARGET_RV1126_NEU2 Neu2: Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module based on Rockchip RV1126 from Edgeble AI. - Neu2 powered with Consumer grade (0 to +80 °C) RV1126 SoC. - Neu2k powered with Industrial grade (-40 °C to +85 °C) RV1126K SoC. + Neu2 powered with Consumer grade (0 to +80 C) RV1126 SoC. + Neu2k powered with Industrial grade (-40 C to +85 C) RV1126K SoC. C is the sign for coulomb which is the unit of electric charge. How about 'deg C'? Best regards Heinrich Neu2-IO: Neural Compute Module 2(Neu2) IO board is an industrial form factor diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d068b7860e1c..bedc4e970e43 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -246,7 +246,7 @@ config SPI_FLASH_USE_4K_SECTORS to erasing whole blocks (32/64 KiB). Changing a small part of the flash's contents is usually faster with small sectors. On the other hand erasing should be faster when using - 64 KiB block instead of 16 × 4 KiB sectors. + 64 KiB block instead of 16 x 4 KiB sectors. Please note that some tools/drivers/filesystems may not work with 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
[PATCH 0/4] Kconfig: some cleanups
I looked as cleaning up some dependencies and I found that qconfig is reporting some issues. This series is fixing some of them. But there are still some other pending. That's why please go and fix them if they are related to your board. Thanks, Michal drivers/pinctrl/intel/Kconfig:12: warning: style: quotes recommended around 'n' in 'bool n' warning: the choice symbol CPU_ARCEM6 (defined at arch/arc/Kconfig:46) is selected by the following symbols, but select/imply has no effect on choice symbols - TARGET_EMSDP (defined at arch/arc/Kconfig:173) - TARGET_IOT_DEVKIT (defined at arch/arc/Kconfig:180) warning: the choice symbol ARC_MMU_ABSENT (defined at arch/arc/Kconfig:77) is selected by the following symbols, but select/imply has no effect on choice symbols - CPU_ARCEM6 (defined at arch/arc/Kconfig:46) - CPU_ARCHS36 (defined at arch/arc/Kconfig:53) warning: the choice symbol ARC_MMU_V2 (defined at arch/arc/Kconfig:82) is selected by the following symbols, but select/imply has no effect on choice symbols - CPU_ARC750D (defined at arch/arc/Kconfig:32) warning: the choice symbol ARC_MMU_V3 (defined at arch/arc/Kconfig:89) is selected by the following symbols, but select/imply has no effect on choice symbols - CPU_ARC770D (defined at arch/arc/Kconfig:39) warning: the choice symbol ARC_MMU_V4 (defined at arch/arc/Kconfig:97) is selected by the following symbols, but select/imply has no effect on choice symbols - CPU_ARCHS38 (defined at arch/arc/Kconfig:60) warning: the choice symbol FSP_VERSION2 (defined at arch/x86/Kconfig:396) is selected by the following symbols, but select/imply has no effect on choice symbols - INTEL_APOLLOLAKE (defined at arch/x86/cpu/apollolake/Kconfig:6) warning: the choice symbol SPL_RISCV_MMODE (defined at arch/riscv/Kconfig:184) is implied by the following symbols, but select/imply has no effect on choice symbols - BOARD_SPECIFIC_OPTIONS (defined at board/bsh/imx8mn_smm_s2/Kconfig:21, board/bsh/imx8mn_smm_s2/Kconfig:41, board/engicam/px30_core/Kconfig:12, board/theobroma-systems/ringneck_px30/Kconfig:12, board/radxa/rockpi4-rk3399/Kconfig:12, board/theobroma-systems/puma_rk3399/Kconfig:12, board/theobroma-systems/jaguar_rk3588/Kconfig:12, board/edgeble/neural-compute-module-2/Kconfig:12, board/itead/sonoff-ihost/Kconfig:12, board/emulation/qemu-arm/Kconfig:6, board/emulation/qemu-arm/Kconfig:22, board/freescale/ls1012aqds/Kconfig:27, board/freescale/ls1012ardb/Kconfig:27, board/freescale/ls1012ardb/Kconfig:76, board/freescale/ls1012afrdm/Kconfig:27, board/advantech/som-db5800-som-6867/Kconfig:18, board/congatec/conga-qeval20-qa3-e3845/Kconfig:17, board/coreboot/coreboot/Kconfig:15, board/dfi/dfi-bt700/Kconfig:17, board/efi/efi-x86_app/Kconfig:12, board/efi/efi-x86_payload/Kconfig:15, board/emulation/qemu-x86/Kconfig:16, board/google/chromebook_coral/Kconfig:18, board/google/chromebook_link/Kconfig:19, board/google/chromebox_panther/Kconfig:19, board/google/chromebook_samus/Kconfig:19, board/intel/bayleybay/Kconfig:15, board/intel/cherryhill/Kconfig:15, board/intel/cougarcanyon2/Kconfig:15, board/intel/crownbay/Kconfig:15, board/intel/edison/Kconfig:24, board/intel/galileo/Kconfig:15, board/intel/minnowmax/Kconfig:15, board/intel/slimbootloader/Kconfig:19, board/AndesTech/ae350/Kconfig:34, board/emulation/qemu-riscv/Kconfig:32, board/microchip/mpfs_icicle/Kconfig:19, board/openpiton/riscv64/Kconfig:26, board/sifive/unleashed/Kconfig:26, board/sifive/unmatched/Kconfig:26, board/sipeed/maix/Kconfig:30, board/sophgo/milkv_duo/Kconfig:24, board/starfive/visionfive2/Kconfig:26, board/thead/th1520_lpi4a/Kconfig:30, board/xilinx/mbv/Kconfig:22, board/keymile/km83xx/Kconfig:34, board/keymile/km83xx/Kconfig:54, board/keymile/km83xx/Kconfig:74, board/keymile/km83xx/Kconfig:93, board/keymile/km83xx/Kconfig:112, board/keymile/km83xx/Kconfig:131, board/keymile/km83xx/Kconfig:150, board/keymile/kmcent2/Kconfig:12, board/keymile/pg-wcom-ls102xa/Kconfig:15, board/keymile/pg-wcom-ls102xa/Kconfig:35) warning: the choice symbol SYS_BIG_ENDIAN (defined at arch/Kconfig:528) is selected by the following symbols, but select/imply has no effect on choice symbols - ARC (defined at arch/Kconfig:53) warning: the choice symbol SYS_LITTLE_ENDIAN (defined at arch/Kconfig:532) is selected by the following symbols, but select/imply has no effect on choice symbols - ARC (defined at arch/Kconfig:53) warning: the choice symbol OF_SEPARATE (defined at dts/Kconfig:108) is selected by the following symbols, but select/imply has no effect on choice symbols - ARCH_MVEBU (defined at arch/arm/Kconfig:620) - ARCH_SNAPDRAGON (defined at arch/arm/Kconfig:1074) - ARCH_SUNXI (defined at arch/arm/Kconfig:1143) - ARCH_S5P4418 (defined at arch/arm/mach-nexell/Kconfig:3) warning: the choice symbol MULTI_DTB_FIT_USER_DEFINED_AREA (defined at dts/Kconfig:242) is implied by the following symbols, but select/imply has no effect on choice symbols - RZG2L (defined at
Re: [PATCH 3/4] mtd: spi-nor-core: Rework default_init() to take flash_parameter
On 4/15/24 08:09, Takahiro Kuwano wrote: > Hi Tudor, Hi! > > On 4/15/2024 3:47 PM, Tudor Ambarus wrote: >> >> >> On 4/15/24 05:33, tkuw584...@gmail.com wrote: >>> From: Takahiro Kuwano >>> >>> default_init() fixup hook should be used to initialize flash parameters >>> when its information is not provided in SFDP. To support that case, it >>> needs to take flash_parameter structure like as other hooks. >>> >>> Signed-off-by: Takahiro Kuwano >>> --- >> >> I'd like to get rid of the default_init hook, let's not extend it if >> possible. Can you use the late_init hook instead? >> > It looks easy to migrate from default_init to late_init so I will do it. > Could you provide the links to related discussion in Linux MTD side so that > I can summarize it in commit message? > I can't, I don't remember if I brought this up or when, but I can explain why. default_init() is wrong, it contributes to the maze of initializing flash parameters. We'd like to get rid of it because the flash parameters that it initializes are not really used at SFDP parsing time, thus they can be initialized later. Ideally we want SFDP to initialize all the flash parameters. If (when) SFDP tables are wrong, we fix them with the post_sfdp/bfpt hooks, to emphasize that SFDP is indeed wrong. When there are parameters that are not covered by SFDP, we initialize them in late_init() - these parameters have nothing to do with SFDP and they are not needed earlier. With this we'll have a clearer view of who initializes what. Feel free to use this in the commit message if you think it helps. Cheers, ta
Re: [PATCH 0/4] mtd: Make sure UBIFS does not do multi-pass page programming on flashes that don't support it
On 4/15/24 05:33, tkuw584...@gmail.com wrote: > From: Takahiro Kuwano > > This series is equivalent to the one for Linux MTD submitted by > Pratyush Yadav. > > https://patchwork.ozlabs.org/project/linux-mtd/list/?series=217759=* Ah, I see you specified it here. I'd argue it's better to mention it in the commit message itself, it spares people searching on the ml archive. > > Takahiro Kuwano (4): > mtd: ubi: Do not zero out EC and VID on ECC-ed NOR flashes > mtd: spi-nor: Allow flashes to specify MTD writesize > mtd: spi-nor-core: Rework default_init() to take flash_parameter > mtd: spi-nor: Set ECC unit size to MTD writesize in Infineon SEMPER > flashes > > drivers/mtd/spi/spi-nor-core.c | 45 +- > drivers/mtd/ubi/build.c| 4 +-- > drivers/mtd/ubi/io.c | 9 ++- > include/linux/mtd/spi-nor.h| 1 + > 4 files changed, 44 insertions(+), 15 deletions(-) >
Re: [PATCH 4/4] mtd: spi-nor: Set ECC unit size to MTD writesize in Infineon SEMPER flashes
On 4/15/24 05:33, tkuw584...@gmail.com wrote:
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index 8f371a5213..773afd4040 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3459,6 +3459,13 @@ static void s25_default_init(struct spi_nor *nor,
>struct spi_nor_flash_parameter *params)
> {
> nor->setup = s25_s28_setup;
> +
> + /*
> + * Programming is supported only in 16-byte ECC data unit granularity.
> + * Byte-programming, bit-walking, or multiple program operations to the
> + * same ECC data unit without an erase are not allowed.
> + */
> + params->writesize = 16;
> }
Use late_init() please. Looks good.
ta
Re: [PATCH 2/4] mtd: spi-nor: Allow flashes to specify MTD writesize
Hi, Takahiro!
On 4/15/24 05:33, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> Some flashes like the Infineon SEMPER NOR flash family use ECC. Under
> this ECC scheme, multi-pass writes to an ECC block is not allowed.
> In other words, once data is programmed to an ECC block, it can't be
> programmed again without erasing it first.
>
> Upper layers like file systems need to be given this information so they
> do not cause error conditions on the flash by attempting multi-pass
> programming. This can be done by setting 'writesize' in 'struct
> mtd_info'.
>
> Set the default to 1 but allow flashes to modify it in fixup hooks. If
> more flashes show up with this constraint in the future it might be
> worth it to add it to 'struct flash_info', but for now increasing its
> size is not worth it.
>
> Signed-off-by: Takahiro Kuwano
Please specify when a patch follows linux upstream. This follows the
following upstream linux commit:
afd473e85827 ("mtd: spi-nor: core: Allow flashes to specify MTD writesize")
Acked-by: Tudor Ambarus
Re: [PATCH 3/4] mtd: spi-nor-core: Rework default_init() to take flash_parameter
On 4/15/24 05:33, tkuw584...@gmail.com wrote: > From: Takahiro Kuwano > > default_init() fixup hook should be used to initialize flash parameters > when its information is not provided in SFDP. To support that case, it > needs to take flash_parameter structure like as other hooks. > > Signed-off-by: Takahiro Kuwano > --- I'd like to get rid of the default_init hook, let's not extend it if possible. Can you use the late_init hook instead? Cheers, ta
Re: [PATCH 1/4] mtd: ubi: Do not zero out EC and VID on ECC-ed NOR flashes
Hi, Takahiro,
On 4/15/24 05:33, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> For NOR flashes EC and VID are zeroed out before an erase is issued to
> make sure UBI does not mistakenly treat the PEB as used and associate it
> with an LEB.
>
> But on some flashes, like the Infineon Semper NOR flash family,
> multi-pass page programming is not allowed on the default ECC scheme.
> This means zeroing out these magic numbers will result in the flash
> throwing a page programming error.
>
> Do not zero out EC and VID for such flashes. A writesize > 1 is an
> indication of an ECC-ed flash.
>
I'm not familiar with the u-boot requirements, but I think a good
practice would be to specify if/when a commit follows the upstream linux
implementation. It helps reviewers, gives a peace of mind to the
maintainer(s), and gives credit to the author. If something breaks all
parties can be involved.
This patch replicates the following upstream linux commit:
f669e74be820 ("ubi: Do not zero out EC and VID on ECC-ed NOR flashes")
Acked-by: Tudor Ambarus
Cheers,
ta
[PATCH v2] usb: dwc3-generic: fix support without DM_REGULATOR
Recent addition of vbus-supply support has broke platform which dont use
controllable regulators for USB.
Issue is that even withou DM_REGULATOR being enabled regulator related
functions will still build as there is a stub in regulator.h but they will
simply return -ENOSYS which will then make dwc3_generic_host_probe()
return the same error thus breaking probe.
So, check whether return code is -ENOSYS before erroring out.
Fixes: de451d5d5b6f ("usb: dwc3-generic: support external vbus regulator")
Signed-off-by: Robert Marko
---
Changes in v2:
* Drop #ifdefs and check for -ENOSYS that regulator stub returns
drivers/usb/dwc3/dwc3-generic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 7a00529a2a..df0b0b8c02 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -248,7 +248,7 @@ static int dwc3_generic_host_probe(struct udevice *dev)
/* Only returns an error if regulator is valid and failed to enable due
to a driver issue */
rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
- if (rc)
+ if (rc && rc != -ENOSYS)
return rc;
hccr = (struct xhci_hccr *)priv->gen_priv.base;
--
2.44.0
[PATCH 3/4] doc: Milk-V Mars CM and Milk-V Mars CM Lite
Provide a man-page describing the usage of U-Boot on the Milk-V Mars CM and Milk-V Mars CM Lite boards. Signed-off-by: Heinrich Schuchardt --- doc/board/starfive/index.rst | 1 + doc/board/starfive/milk-v_mars_cm.rst | 125 ++ 2 files changed, 126 insertions(+) create mode 100644 doc/board/starfive/milk-v_mars_cm.rst diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst index 2762bf74c11..afa85ad2540 100644 --- a/doc/board/starfive/index.rst +++ b/doc/board/starfive/index.rst @@ -7,4 +7,5 @@ StarFive :maxdepth: 1 milk-v_mars.rst + milk-v_mars_cm.rst visionfive2 diff --git a/doc/board/starfive/milk-v_mars_cm.rst b/doc/board/starfive/milk-v_mars_cm.rst new file mode 100644 index 000..4cd6034281c --- /dev/null +++ b/doc/board/starfive/milk-v_mars_cm.rst @@ -0,0 +1,125 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Milk-V Mars CM +== + +U-Boot for the Milk-V Mars CM uses the same U-Boot binaries as the VisionFive 2 +board. In U-Boot SPL the actual board is detected and the device-tree patched +accordingly. + +The Milk-V Mars CM Lite comes without eMMC it needs a different pin muxing. +The size of the eMMC shows up in the serial number shown by the *mac* command, +e.g. MARC-V10-2340-D002E016-0304. The number after the E is the MMC size +in GB. U-Boot takes a value of E000 as an indicator for the Lite version. +Unfortunately the vendor has not set this value correctly on some Lite boards. +Please, use CONFIG_STARFIVE_NO_EMMC=y to indicate a Milk-V Mars CM Lite in this +case. Otherwise you will not be able to read from eMMC + +Building + + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE= + +The M-mode software OpenSBI provides the supervisor binary interface (SBI) and +is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot. +Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use +a current release. + +.. code-block:: console + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=generic FW_TEXT_START=0x4000 FW_OPTIONS=0 + +Now build the U-Boot SPL and U-Boot proper. + +.. code-block:: console + + cd + make starfive_visionfive2_defconfig + make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin + +This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well +as the FIT image (u-boot.itb) with OpenSBI and U-Boot. + +Device-tree selection +~ + +Depending on the board version U-Boot sets variable $fdtfile to either +starfive/jh7110-milkv-mars-cm-emmc.dtb (for the generic version or +starfive/jh7110-milkv-mars-cm-sdcard.dtb (for the Lite version). + +To overrule this selection the variable can be set manually and saved in the +environment + +:: + +setenv fdtfile my_device-tree.dtb +env save + +or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to +provide a default value. + +Boot source selection +~ + +The low speed connector nRPIBOOT line is used to switch the boot source. + +* If nRPIBOOT is connected to ground, the board boots from UART. +* If nRPIBOOT is not connected, the board boots from SPI flash. + +Flashing a new U-Boot version +~ + +U-Boot SPL is provided as file spl/u-boot-spl.bin.normal.out. Main U-Boot is +in file u-boot.itb. + +Assuming your new U-Boot version is on partition 1 of an SD-card you could +install to the SPI flash with: + +:: + +sf probe +load mmc 1:1 $kernel_addr_r u-boot-spl.bin.normal.out +sf update $kernel_addr_r 0 $filesize +load mmc 1:1 $kernel_addr_r u-boot.itb +sf update $kernel_addr_r 0x10 $filesize + +After updating U-Boot you may want to reboot and reset the environment to the +default. + +:: + +env default -f -a +env save + +Booting from UART +~ + +For booting via UART U-Boot must be built with CONFIG_SPL_YMODEM_SUPPORT=y. + +Upload u-boot-spl.bin.normal.out via XMODEM. Then upload u-boot.itb via +YMODEM. + +The XMODEM implementation in the boot ROM is not fully specification compliant. +It sends too many NAKs in a row. Some tolerant terminal implementations exist. +Or use a dedicated recovery tool e.g. +https://github.com/xypron/JH71xx-tools/tree/VisionFive2: + +.. code-block:: bash + +# send U-Boot SPL via XMODEM +vf2-recover -D /dev/ttyUSB0 -r u-boot-spl.bin.normal.out +# connect to board to transfer main U-Boot via YMODEM +picocom --send-cmd 'sz -b -vv' --baud 115200 /dev/ttyUSB0 +# In Picocom use , to send u-boot.itb + +Booting from SPI flash +~~ + +Once you power up, you should see the U-Boot prompt on the serial console. -- 2.43.0
[PATCH 4/4] configs: visionfive2: enable SPL_YMODEM_SUPPORT
We can use U-Boot for recovering JH7110 based boards via UART if CONFIG_SPL_YMODEM_SUPPORT=y. * Send u-boot-spl.normal.out via XMODEM. * Send u-boot.itb via YMODEM. Signed-off-by: Heinrich Schuchardt --- configs/starfive_visionfive2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index fa80d489f5e..e2d83c62b28 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -62,6 +62,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="StarFive # " CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_SIZE=512 -- 2.43.0
[PATCH 2/4] board: add support for Milk-V Mars CM
We already support the VisionFive 2 and the Milk-V Mars board by
patching the VisionFive 2 device tree. With this patch the same
is done for the Milk-V Mars CM.
Signed-off-by: Heinrich Schuchardt
---
board/starfive/visionfive2/spl.c | 27 ++-
.../visionfive2/starfive_visionfive2.c| 11 +++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 45848db6d8b..bb0f28d7aad 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -129,6 +129,29 @@ void spl_fdt_fixup_mars(void *fdt)
}
}
+void spl_fdt_fixup_marc(void *fdt)
+{
+ const char *compat;
+ const char *model;
+
+ spl_fdt_fixup_mars(fdt);
+
+ if (!get_mmc_size_from_eeprom()) {
+ int offset;
+
+ model = "Milk-V Mars CM SDCard";
+ compat = "milkv,mars-cm-sdcard\0starfive,jh7110";
+
+ offset = fdt_path_offset(fdt,
"/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
+ fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
+ } else {
+ model = "Milk-V Mars CM eMMC";
+ compat = "milkv,mars-cm-emmc\0starfive,jh7110";
+ }
+ fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat,
sizeof(compat));
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
+}
+
void spl_fdt_fixup_version_a(void *fdt)
{
static const char compat[] =
"starfive,visionfive-2-v1.2a\0starfive,jh7110";
@@ -236,7 +259,9 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
pr_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
+ if (!strncmp(product_id, "MARC", 4)) {
+ spl_fdt_fixup_marc(spl_image->fdt_addr);
+ } else if (!strncmp(product_id, "MARS", 4)) {
spl_fdt_fixup_mars(spl_image->fdt_addr);
} else if (!strncmp(product_id, "VF7110", 6)) {
version = get_pcb_revision_from_eeprom();
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
index a86bca533b2..be6ca85b030 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -17,6 +17,10 @@
DECLARE_GLOBAL_DATA_PTR;
#define JH7110_L2_PREFETCHER_BASE_ADDR 0x203
#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
+#define FDTFILE_MILK_V_MARC_SD \
+ "starfive/jh7110-milkv-mars-cm-sdcard.dtb"
+#define FDTFILE_MILK_V_MARC_MMC \
+ "starfive/jh7110-milkv-mars-cm-emmc.dtb"
#define FDTFILE_MILK_V_MARS \
"starfive/jh7110-milkv-mars.dtb"
#define FDTFILE_VISIONFIVE2_1_2A \
@@ -61,7 +65,12 @@ static void set_fdtfile(void)
log_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
+ if (!strncmp(product_id, "MARC", 4)) {
+ if (get_mmc_size_from_eeprom())
+ fdtfile = FDTFILE_MILK_V_MARC_MMC;
+ else
+ fdtfile = FDTFILE_MILK_V_MARC_SD;
+ } else if (!strncmp(product_id, "MARS", 4)) {
fdtfile = FDTFILE_MILK_V_MARS;
} else if (!strncmp(product_id, "VF7110", 6)) {
version = get_pcb_revision_from_eeprom();
--
2.43.0
[PATCH 1/4] board: starfive: function to read eMMC size
The EEPROM provides information about the size of the EEPROM.
Provide a new function get_mmc_size_from_eeprom() to read it.
Signed-off-by: Heinrich Schuchardt
---
arch/riscv/include/asm/arch-jh7110/eeprom.h| 7 +++
board/starfive/visionfive2/Kconfig | 9 +
.../visionfive2/visionfive2-i2c-eeprom.c | 18 ++
3 files changed, 34 insertions(+)
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h
b/arch/riscv/include/asm/arch-jh7110/eeprom.h
index 62d184aeb57..17395d4269e 100644
--- a/arch/riscv/include/asm/arch-jh7110/eeprom.h
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -12,6 +12,13 @@
u8 get_pcb_revision_from_eeprom(void);
u32 get_ddr_size_from_eeprom(void);
+/**
+ * get_mmc_size_from_eeprom() - read MMC size form EEPROM
+ *
+ * @return: size in GiB or 0 on error.
+ */
+u32 get_mmc_size_from_eeprom(void);
+
/**
* get_product_id_from_eeprom - get product ID string
*
diff --git a/board/starfive/visionfive2/Kconfig
b/board/starfive/visionfive2/Kconfig
index 2186a939646..d7e8a7a7d78 100644
--- a/board/starfive/visionfive2/Kconfig
+++ b/board/starfive/visionfive2/Kconfig
@@ -50,4 +50,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply PHY_LIB
imply PHY_MSCC
+config STARFIVE_NO_EMMC
+ bool "Report eMMC size as zero"
+ help
+ The serial number string in the EEPROM is meant to report the
+ size of onboard eMMC. Unfortunately some Milk-V Mars CM Lite
+ modules without eMMC show a non-zero size here.
+
+ Set to 'Y' if you have a Mars CM Lite module.
+
endif
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
index ddef7d61235..cd3d8bd51a6 100644
--- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -548,6 +548,24 @@ u32 get_ddr_size_from_eeprom(void)
return hextoul([14], NULL);
}
+u32 get_mmc_size_from_eeprom(void)
+{
+ u32 size;
+
+ if (IS_ENABLED(CONFIG_STARFIVE_NO_EMMC))
+ return 0;
+
+ if (read_eeprom())
+ return 0;
+
+ size = dectoul([19], NULL);
+
+ if (pbuf.eeprom.atom1.data.pstr[21] == 'T')
+ size <<= 10;
+
+ return size;
+}
+
U_BOOT_LONGHELP(mac,
"\n"
"- display EEPROM content\n"
--
2.43.0
[PATCH 0/4] board: starfive: add Milk-V Mars CM support
With this series the Milk-V Mars CM board can be booted. NVMe, SD-card, Ethernet, UART are working but not USB. The first series Milk-V Mars CM Lite board (the version without eMMC) uses incorrect series numbers indicating eMMC presence. For these CONFIG_STARFIVE_NO_EMMC=y must be set to indicate that eMMC is not present. Thanks to E. Shattow for all the helpful discussions. He figured out what needed to be patched in the device-tree. Heinrich Schuchardt (4): board: starfive: function to read eMMC size board: add support for MARS CM SD doc: Milk-V Mars CM and Milk-V Mars CM Lite configs: visionfive2: enable SPL_YMODEM_SUPPORT arch/riscv/include/asm/arch-jh7110/eeprom.h | 7 + board/starfive/visionfive2/Kconfig| 9 ++ board/starfive/visionfive2/spl.c | 27 +++- .../visionfive2/starfive_visionfive2.c| 11 +- .../visionfive2/visionfive2-i2c-eeprom.c | 18 +++ configs/starfive_visionfive2_defconfig| 1 + doc/board/starfive/index.rst | 1 + doc/board/starfive/milk-v_mars_cm.rst | 125 ++ 8 files changed, 197 insertions(+), 2 deletions(-) create mode 100644 doc/board/starfive/milk-v_mars_cm.rst -- 2.43.0
Re: [PATCH 3/3] serial: msm_serial: set .clk_bit_rate in debug UART
On Mon, Apr 15, 2024 at 1:46 PM Caleb Connolly
wrote:
>
>
>
> On 15/04/2024 11:49, Robert Marko wrote:
> > Currently, .clk_bit_rate is not being set in init_serial_data for debug
> > UART, but its then used uart_dm_init() and this breaks debug UART on
> > IPQ40xx.
> >
> > So, lets populate .clk_bit_rate for debug UART as well.
> > IPQ40xx requires special value of 0xff, so set it if ARCH_IPQ40XX is
> > selected, otherwise default to the same value that regular DM UART
> > will use.
>
> Ah, I have a patch lying around to configure this automatically, but
> didn't get around to sending it. Could you give it a test on your IPQ
> board if I send it your way?
Sure, that would be great.
Regards,
Robert
>
> Kind regards,
> >
> > Signed-off-by: Robert Marko
> > ---
> > drivers/serial/serial_msm.c | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> > index 8044d38518..80069f5cfb 100644
> > --- a/drivers/serial/serial_msm.c
> > +++ b/drivers/serial/serial_msm.c
> > @@ -242,6 +242,11 @@ U_BOOT_DRIVER(serial_msm) = {
> >
> > static struct msm_serial_data init_serial_data = {
> > .base = CONFIG_VAL(DEBUG_UART_BASE),
> > +#ifdef CONFIG_ARCH_IPQ40XX
> > + .clk_bit_rate = 0xff,
> > +#else
> > + .clk_bit_rate = UART_DM_CLK_RX_TX_BIT_RATE,
> > +#endif
> > };
> >
> > #include
>
> --
> // Caleb (they/them)
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
1 Zagreb, Croatia
Email: robert.ma...@sartura.hr
Web: www.sartura.hr
Re: [PATCH 3/3] serial: msm_serial: set .clk_bit_rate in debug UART
On 15/04/2024 11:49, Robert Marko wrote:
> Currently, .clk_bit_rate is not being set in init_serial_data for debug
> UART, but its then used uart_dm_init() and this breaks debug UART on
> IPQ40xx.
>
> So, lets populate .clk_bit_rate for debug UART as well.
> IPQ40xx requires special value of 0xff, so set it if ARCH_IPQ40XX is
> selected, otherwise default to the same value that regular DM UART
> will use.
Ah, I have a patch lying around to configure this automatically, but
didn't get around to sending it. Could you give it a test on your IPQ
board if I send it your way?
Kind regards,
>
> Signed-off-by: Robert Marko
> ---
> drivers/serial/serial_msm.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> index 8044d38518..80069f5cfb 100644
> --- a/drivers/serial/serial_msm.c
> +++ b/drivers/serial/serial_msm.c
> @@ -242,6 +242,11 @@ U_BOOT_DRIVER(serial_msm) = {
>
> static struct msm_serial_data init_serial_data = {
> .base = CONFIG_VAL(DEBUG_UART_BASE),
> +#ifdef CONFIG_ARCH_IPQ40XX
> + .clk_bit_rate = 0xff,
> +#else
> + .clk_bit_rate = UART_DM_CLK_RX_TX_BIT_RATE,
> +#endif
> };
>
> #include
--
// Caleb (they/them)
