Re: [PATCH v2 3/5] usb: xhci-mtk: modify the SOF/ITP interval for mt8195
Hi Marek, On Fri, 2023-02-17 at 14:35 +0100, Marek Vasut wrote: > On 2/17/23 10:04, Chunfeng Yun wrote: > > There are 4 USB controllers on MT8195, the controllers (IP1~IP3, > > exclude IP0) have a wrong default SOF/ITP interval which is > > calculated from the frame counter clock 24Mhz by default, but > > in fact, the frame counter clock is 48Mhz, so we shall set the > > accurate interval according to 48Mhz for those controllers. > > > > Note: > > The first controller no need set it, but if set it, shall change > > tphy's pll at the same time. > > > > Signed-off-by: Chunfeng Yun > > Reviewed-by: Marek Vasut > > Feel free to pull the entire series via mediatek tree, so it would go > in > together. Could you help to apply this series patch, seems no mediatek tree, thanks a lot
Re: [PATCH 2/4] usb: xhci-mtk: modify the SOF/ITP interval for mt8195
On Mon, 2023-02-13 at 22:00 +0100, Marek Vasut wrote: > On 2/13/23 02:46, Chunfeng Yun (云春峰) wrote: > > On Fri, 2023-02-10 at 11:32 +0100, Marek Vasut wrote: > > > On 2/10/23 09:33, Chunfeng Yun wrote: > > > [...] > > > > @@ -50,6 +50,27 @@ > > > >#define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * > > > > 0x08)) > > > >#define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * > > > > 0x08)) > > > > > > > > +/* xHCI CSR */ > > > > +#define LS_EOF_CFG 0x930 > > > > +#define LSEOF_OFFSET 0x89 > > > > + > > > > +#define FS_EOF_CFG 0x934 > > > > +#define FSEOF_OFFSET 0x2e > > > > + > > > > +#define SS_GEN1_EOF_CFG0x93c > > > > +#define SSG1EOF_OFFSET 0x78 > > > > + > > > > +#define HFCNTR_CFG 0x944 > > > > +#define ITP_DELTA_CLK (0xa << 1) > > > > +#define ITP_DELTA_CLK_MASK GENMASK(5, 1) > > > > +#define FRMCNT_LEV1_RANG (0x12b << 8) > > > > > > Look at FIELD_PREP() macro, that should let you avoid the (0x12b > > > << > > > 8) . Sorry, misunderstood you > > > > Seems not use FIELD_PREP() macro here. > > It's not a mask, it's the value set in below mask > > FRMCNT_LEV1_RANG_MASK. > > So that would be > > FIELD_PREP(FRMCNT_LEV1_RANG_MASK, 0x12b) > > I think ? Sure, I'll use it instead Thanks a lot > > > > > +#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) > > > > + > > > > +#define SS_GEN2_EOF_CFG0x990 > > > > +#define SSG2EOF_OFFSET 0x3c > > > > + > > > > +#define XSEOF_OFFSET_MASK GENMASK(11, 0) > > > > > > [...] > > > > > > > @@ -308,6 +354,7 @@ static int xhci_mtk_remove(struct udevice > > > > *dev) > > > > > > > >static const struct udevice_id xhci_mtk_ids[] = { > > > > { .compatible = "mediatek,mtk-xhci" }, > > > > + { .compatible = "mediatek,mt8195-xhci" }, > > > > > > Is the extra compatible string really needed, can't the driver > > > match > > > on > > > the generic one ? > > > > These settings are a workaround only for mt8195 to fix HW issue, > > can't > > use generic compatible. > > Ah, I see, OK
Re: [PATCH 2/4] usb: xhci-mtk: modify the SOF/ITP interval for mt8195
On Fri, 2023-02-10 at 11:32 +0100, Marek Vasut wrote: > On 2/10/23 09:33, Chunfeng Yun wrote: > [...] > > @@ -50,6 +50,27 @@ > > #define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * 0x08)) > > #define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * 0x08)) > > > > +/* xHCI CSR */ > > +#define LS_EOF_CFG 0x930 > > +#define LSEOF_OFFSET 0x89 > > + > > +#define FS_EOF_CFG 0x934 > > +#define FSEOF_OFFSET 0x2e > > + > > +#define SS_GEN1_EOF_CFG0x93c > > +#define SSG1EOF_OFFSET 0x78 > > + > > +#define HFCNTR_CFG 0x944 > > +#define ITP_DELTA_CLK (0xa << 1) > > +#define ITP_DELTA_CLK_MASK GENMASK(5, 1) > > +#define FRMCNT_LEV1_RANG (0x12b << 8) > > Look at FIELD_PREP() macro, that should let you avoid the (0x12b << > 8) . Seems not use FIELD_PREP() macro here. It's not a mask, it's the value set in below mask FRMCNT_LEV1_RANG_MASK. > > > +#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) > > + > > +#define SS_GEN2_EOF_CFG0x990 > > +#define SSG2EOF_OFFSET 0x3c > > + > > +#define XSEOF_OFFSET_MASK GENMASK(11, 0) > > [...] > > > @@ -308,6 +354,7 @@ static int xhci_mtk_remove(struct udevice *dev) > > > > static const struct udevice_id xhci_mtk_ids[] = { > > { .compatible = "mediatek,mtk-xhci" }, > > + { .compatible = "mediatek,mt8195-xhci" }, > > Is the extra compatible string really needed, can't the driver match > on > the generic one ? These settings are a workaround only for mt8195 to fix HW issue, can't use generic compatible. Thanks a lot
Re: [PATCH v3 1/2] arm: mediatek: add mt8195 SOC support
On Thu, 2022-11-10 at 15:34 +0800, Macpaul Lin wrote: > From: Fabien Parent > > The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 > and > a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and > hosts, > SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 > and LPDDR4 options. > > Signed-off-by: Fabien Parent > Signed-off-by: Macpaul Lin > > --- > MAINTAINERS| 2 + > arch/arm/dts/mt8195.dtsi | 370 > + > arch/arm/mach-mediatek/Kconfig | 13 +- > arch/arm/mach-mediatek/Makefile| 1 + > arch/arm/mach-mediatek/mt8195/Makefile | 3 + > arch/arm/mach-mediatek/mt8195/init.c | 81 ++ > 6 files changed, 469 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/mt8195.dtsi > create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile > create mode 100644 arch/arm/mach-mediatek/mt8195/init.c > > Changes for v2: > - Correct node name to t-phy for u3phy0. > - Add platform compatible string "mediatek,mt8195-tphy" to all usb > phy nodes. > - remove clock nodes that software cannot controlled in phy nodes. > - Test and add back "mac" for HOST only xhci nodes. > > Changes for v3: > - Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@". > > diff --git a/MAINTAINERS b/MAINTAINERS > index 1cf99c1393..5528dd28c3 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -362,8 +362,10 @@ ARM MEDIATEK > M: Ryder Lee > M: Weijie Gao > M: Chunfeng Yun > +M: Macpaul Lin > R: GSS_MTK_Uboot_upstream > S: Maintained > +F: arch/arm/dts/mt8195.dtsi > F: arch/arm/mach-mediatek/ > F: arch/arm/include/asm/arch-mediatek/ > F: board/mediatek/ > diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi > new file mode 100644 > index 00..33282d21d1 > --- /dev/null > +++ b/arch/arm/dts/mt8195.dtsi > @@ -0,0 +1,370 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2022 MediaTek Inc. > + * Copyright (C) 2022 BayLibre, SAS > + * Author: Ben Ho > + * Erin Lo > + * Fabien Parent > + * Macpaul Lin > + */ > + > +#include > +#include > +#include > +#include > + > +/ { > + compatible = "mediatek,mt8195"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x000>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x001>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x002>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x003>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > +
Re: [PATCH v2 1/2] arm: mediatek: add mt8195 SOC support
On Wed, 2022-11-09 at 17:50 +0800, Macpaul Lin wrote: > From: Fabien Parent > > The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 > and > a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and > hosts, > SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 > and LPDDR4 options. > > Signed-off-by: Fabien Parent > Signed-off-by: Macpaul Lin > > --- > MAINTAINERS| 2 + > arch/arm/dts/mt8195.dtsi | 370 > + > arch/arm/mach-mediatek/Kconfig | 13 +- > arch/arm/mach-mediatek/Makefile| 1 + > arch/arm/mach-mediatek/mt8195/Makefile | 3 + > arch/arm/mach-mediatek/mt8195/init.c | 81 ++ > 6 files changed, 469 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/mt8195.dtsi > create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile > create mode 100644 arch/arm/mach-mediatek/mt8195/init.c > > Changes for v2: > - Correct node name to t-phy for u3phy0. > - Add platform compatible string "mediatek,mt8195-tphy" to all usb > phy nodes. > - remove clock nodes that software cannot controlled in phy nodes. > - Test and add back "mac" for HOST only xhci nodes. > > diff --git a/MAINTAINERS b/MAINTAINERS > index 1cf99c1393..5528dd28c3 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -362,8 +362,10 @@ ARM MEDIATEK > M: Ryder Lee > M: Weijie Gao > M: Chunfeng Yun > +M: Macpaul Lin > R: GSS_MTK_Uboot_upstream > S: Maintained > +F: arch/arm/dts/mt8195.dtsi > F: arch/arm/mach-mediatek/ > F: arch/arm/include/asm/arch-mediatek/ > F: board/mediatek/ > diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi > new file mode 100644 > index 00..33282d21d1 > --- /dev/null > +++ b/arch/arm/dts/mt8195.dtsi > @@ -0,0 +1,370 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2022 MediaTek Inc. > + * Copyright (C) 2022 BayLibre, SAS > + * Author: Ben Ho > + * Erin Lo > + * Fabien Parent > + * Macpaul Lin > + */ > + > +#include > +#include > +#include > +#include > + > +/ { > + compatible = "mediatek,mt8195"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x000>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x001>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x002>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x003>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x100>; > + enable-method = "psci"; > +
Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
On Wed, 2022-11-09 at 17:33 +0800, Macpaul Lin wrote: > On 11/9/22 15:32, Macpaul Lin wrote: > > > > On 11/9/22 10:07, Chunfeng Yun (云春峰) wrote: > > > On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote: > > > > From: Fabien Parent > > > > > > > > The MediaTek MT8195 is a ARM64-based SoC with a quad-core > > > > Cortex-A73 > > > > and > > > > a quad-core Cortex-A53. It is including UART, SPI, USB3.0 > > > > device and > > > > hosts, > > > > SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several > > > > LPDDR3 > > > > and LPDDR4 options. > > > > > > > > Signed-off-by: Fabien Parent > > > > Signed-off-by: Macpaul Lin > > > > --- > > > > MAINTAINERS| 2 + > > > > arch/arm/dts/mt8195.dtsi | 317 > > > > + > > > > arch/arm/mach-mediatek/Kconfig | 13 +- > > > > arch/arm/mach-mediatek/Makefile| 1 + > > > > arch/arm/mach-mediatek/mt8195/Makefile | 3 + > > > > arch/arm/mach-mediatek/mt8195/init.c | 81 +++ > > > > 6 files changed, 416 insertions(+), 1 deletion(-) > > > > create mode 100644 arch/arm/dts/mt8195.dtsi > > > > create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile > > > > create mode 100644 arch/arm/mach-mediatek/mt8195/init.c > > [deleted] > > > > > +xhci3: xhci3@112b { > > > > > > change node name as xhci? prefer to use the same name > > > > > > > Since there are other board manufacturers will use the > > other HOST ports, like xhci1 or xhci2 with USB mass storage > > function by their needs. > > I'll add these 2 node in dtsi in next version. > > > > > > +compatible = "mediatek,mt8195-xhci", > > > > + "mediatek,mtk-xhci"; > > > > +reg = <0 0x112b 0 0x1000>, > > > > + <0 0x112b3e00 0 0x0100>; > > > > +reg-names = "mac", "ippc"; > > > > > > remove "mac" > > > > Will fix it in next version. > > > > Dear Chunfeng, > > Unfortunately, if we remove "mac" register here for HOST only node > like > xhci3, the driver will complain about probing fail. Please check the > following log. My bad, do need it for host only mode, sorry > > => usb start > starting USB... > Bus xhci3@112b: xhci-mtk xhci3@112b: failed to get xHCI base > address > probe failed, error -6 > No working controllers found > > I'll add "mac" back to HOST only nodes. > > Thanks! > Macpaul Lin
Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote: > From: Fabien Parent > > The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 > and > a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and > hosts, > SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 > and LPDDR4 options. > > Signed-off-by: Fabien Parent > Signed-off-by: Macpaul Lin > --- > MAINTAINERS| 2 + > arch/arm/dts/mt8195.dtsi | 317 > + > arch/arm/mach-mediatek/Kconfig | 13 +- > arch/arm/mach-mediatek/Makefile| 1 + > arch/arm/mach-mediatek/mt8195/Makefile | 3 + > arch/arm/mach-mediatek/mt8195/init.c | 81 +++ > 6 files changed, 416 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/mt8195.dtsi > create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile > create mode 100644 arch/arm/mach-mediatek/mt8195/init.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 1cf99c1393..5528dd28c3 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -362,8 +362,10 @@ ARM MEDIATEK > M: Ryder Lee > M: Weijie Gao > M: Chunfeng Yun > +M: Macpaul Lin > R: GSS_MTK_Uboot_upstream > S: Maintained > +F: arch/arm/dts/mt8195.dtsi > F: arch/arm/mach-mediatek/ > F: arch/arm/include/asm/arch-mediatek/ > F: board/mediatek/ > diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi > new file mode 100644 > index 00..d28b038d57 > --- /dev/null > +++ b/arch/arm/dts/mt8195.dtsi > @@ -0,0 +1,317 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2022 MediaTek Inc. > + * Copyright (C) 2022 BayLibre, SAS > + * Author: Ben Ho > + * Erin Lo > + * Fabien Parent > + * Macpaul Lin > + */ > + > +#include > +#include > +#include > +#include > + > +/ { > + compatible = "mediatek,mt8195"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x000>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x001>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x002>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x003>; > + enable-method = "psci"; > + capacity-dmips-mhz = <741>; > + }; > + > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x100>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x101>; > + enable-method = "psci"