Re: [PATCH v4 1/1] arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support
HI Vasily,
I just tried now adding emmc module and able to access it.
Also Added CMD_REGULATOR support and tried command as you suggested.
Pasting logs at https://paste.ubuntu.com/p/Cx6x3CNj9w/
Let me know if I am missing anything here.
Thanks,
Akash
On 23-02-2023 06:01, Vasily Khoruzhick wrote:
On Tue, Feb 14, 2023 at 12:11 PM Akash Gajjar wrote:
Hi Akash,
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7
Board Specifications
- Rockchip RK3568
- 2/4/8GB LPDDR4 3200MT/s
- eMMC socket, SD card slot
Have you actually tested eMMC support? It seems to be broken when the
system boots off SD card, "mmc info" returns "unable to select a mode
: -70". I have a strong suspicion that it's due to rk_i2c being broken
for rk3568, with debug enabled it complains "I2C Send Start Bit
Timeout" on every i2c transaction.
Could you please share "mmc info" and "regulator status -a" output
from your build?
Regards,
Vasily
- GbE LAN,
- PCIe 3.0/2.0
- M.2 Connector
- 3.5mm Audio jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host/OTG, USB 2.0 Host
- 40-pin GPIO expansion ports
- USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A
Refer Linux commit <22a442e6586c>
("arm64: dts: rockchip: add basic dts for the radxa rock3 model a")
Signed-off-by: Akash Gajjar
---
Changes in v2:
- Ammend the commit message, Replace Rock Pi 3a with ROCK3A Model A. Update the
specs from https://wiki.radxa.com/Rock3/3a
- Sync missing node in dts, still some of the nodes like vop, vop mmu, i2s2_2ch
gpu, hdmi removed as there is no driver support present in u-boot.
- Duplicated sdmmc node removed from dts.
Changes in v3:
- Replace rock-pi-3a-rk3568_defconfig with rock-3a-rk3568_defconfig
Changes in v4:
- Add maintainer for the board
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 +
arch/arm/dts/rk3568-rock-3a.dts | 609
board/rockchip/evb_rk3568/MAINTAINERS | 7 +
configs/rock-3a-rk3568_defconfig| 74 +++
5 files changed, 716 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
create mode 100644 configs/rock-3a-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9d647b9639..945843bebc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -165,7 +165,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
- rk3568-evb.dtb
+ rk3568-evb.dtb \
+ rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
new file mode 100644
index 00..ae23ae8587
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Akash Gajjar
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ u-boot,spl-boot-order = "same-as-spl",
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2400>;
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts
new file mode 100644
index 00..a2f2baa4ea
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -0,0 +1,609 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Akash Gajjar
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3568.dtsi"
+
+/ {
+ model = "Radxa ROCK3 Model A";
+ compatible = "radxa,rock3a", "rockchip,rk3568";
+
+ chosen: chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-m
[PATCH v2 1/1] arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S support
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from
Linux 6.2.0-rc7.
ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a,
- 256MB/512MB DDR3 RAM
- SD, NAND flash (optional on board 1/2/4/8Gb)
- 100MB ethernet, PoE (optional)
- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module
- USB2.0 Type-A HOST x1
- USB3.0 Type-C OTG x1
- 26-pin expansion header
- USB Type-C DC 5V Power Supply
Linux commit commit for the same,
<2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support")
Signed-off-by: Akash Gajjar
---
Changes in v2:
- Add MAINTAINER for the board
---
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 17 ++
arch/arm/dts/rk3308-rock-pi-s.dts | 228 ++
board/rockchip/evb_rk3308/MAINTAINERS | 7 +
configs/rock-pi-s-rk3308_defconfig| 89 +
4 files changed, 341 insertions(+)
create mode 100644 arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3308-rock-pi-s.dts
create mode 100644 configs/rock-pi-s-rk3308_defconfig
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
new file mode 100644
index 00..27735c49dd
--- /dev/null
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl",
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <2400>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-rock-pi-s.dts
b/arch/arm/dts/rk3308-rock-pi-s.dts
new file mode 100644
index 00..b5a8691b3f
--- /dev/null
+++ b/arch/arm/dts/rk3308-rock-pi-s.dts
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2023 Akash Gajjar
+ * Copyright (c) 2023 Jagan Teki
+ */
+
+/dts-v1/;
+#include
+#include "rk3308.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi S";
+ compatible = "radxa,rockpis", "rockchip,rk3308";
+
+ aliases {
+ ethernet0 =
+ mmc0 =
+ mmc1 =
+ };
+
+ chosen {
+ stdout-path = "serial0:150n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led_gio>, <_led_gpio>;
+
+ green-led {
+ default-state = "on";
+ gpios = < RK_PA6 GPIO_ACTIVE_HIGH>;
+ label = "rockpis:green:power";
+ linux,default-trigger = "default-on";
+ };
+
+ blue-led {
+ default-state = "on";
+ gpios = < RK_PA5 GPIO_ACTIVE_HIGH>;
+ label = "rockpis:blue:user";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-0 = <_enable_h>;
+ pinctrl-names = "default";
+ reset-gpios = < RK_PA2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_1v8: vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ vin-supply = <_io>;
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_sys>;
+ };
+
+ vcc_ddr: vcc-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <150>;
+ vin-supply = <_sys>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_vbus_drv>;
+ regulator-name = "vcc
[PATCH v2 0/1] Add Radxa ROCK Pi S support in U-boot
ROCK Pi S is rk3308 soc based board from Radxa. Add board support in u-boot. Booting logs is accessible at https://paste.ubuntu.com/p/cJDRzBRdXq/ Akash Gajjar (1): arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S support arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 17 ++ arch/arm/dts/rk3308-rock-pi-s.dts | 228 ++ board/rockchip/evb_rk3308/MAINTAINERS | 7 + configs/rock-pi-s-rk3308_defconfig| 89 + 4 files changed, 341 insertions(+) create mode 100644 arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3308-rock-pi-s.dts create mode 100644 configs/rock-pi-s-rk3308_defconfig -- 2.25.1
[PATCH v4 1/1] arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7
Board Specifications
- Rockchip RK3568
- 2/4/8GB LPDDR4 3200MT/s
- eMMC socket, SD card slot
- GbE LAN
- PCIe 3.0/2.0
- M.2 Connector
- 3.5mm Audio jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host/OTG, USB 2.0 Host
- 40-pin GPIO expansion ports
- USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A
Refer Linux commit <22a442e6586c>
("arm64: dts: rockchip: add basic dts for the radxa rock3 model a")
Signed-off-by: Akash Gajjar
---
Changes in v2:
- Ammend the commit message, Replace Rock Pi 3a with ROCK3A Model A. Update the
specs from https://wiki.radxa.com/Rock3/3a
- Sync missing node in dts, still some of the nodes like vop, vop mmu, i2s2_2ch
gpu, hdmi removed as there is no driver support present in u-boot.
- Duplicated sdmmc node removed from dts.
Changes in v3:
- Replace rock-pi-3a-rk3568_defconfig with rock-3a-rk3568_defconfig
Changes in v4:
- Add maintainer for the board
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 +
arch/arm/dts/rk3568-rock-3a.dts | 609
board/rockchip/evb_rk3568/MAINTAINERS | 7 +
configs/rock-3a-rk3568_defconfig| 74 +++
5 files changed, 716 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
create mode 100644 configs/rock-3a-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9d647b9639..945843bebc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -165,7 +165,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
- rk3568-evb.dtb
+ rk3568-evb.dtb \
+ rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
new file mode 100644
index 00..ae23ae8587
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Akash Gajjar
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ u-boot,spl-boot-order = "same-as-spl",
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2400>;
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts
new file mode 100644
index 00..a2f2baa4ea
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -0,0 +1,609 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Akash Gajjar
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3568.dtsi"
+
+/ {
+ model = "Radxa ROCK3 Model A";
+ compatible = "radxa,rock3a", "rockchip,rk3568";
+
+ chosen: chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+
[PATCH v4 0/1] Add Radxa ROCK 3 Model A support in U-boot.
ROCK 3 Model A is rk3568 based soc board from Radxa, Add board support in u-boot. Booting logs available at https://paste.ubuntu.com/p/v9BNrB7MdM/ Akash Gajjar (1): arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 + arch/arm/dts/rk3568-rock-3a.dts | 609 board/rockchip/evb_rk3568/MAINTAINERS | 7 + configs/rock-3a-rk3568_defconfig| 74 +++ 5 files changed, 716 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-rock-3a.dts create mode 100644 configs/rock-3a-rk3568_defconfig -- 2.25.1
[PATCH 1/1] arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S support
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from
Linux 6.2.0-rc7.
ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a,
- 256MB/512MB DDR3 RAM
- SD, NAND flash (optional on board 1/2/4/8Gb)
- 100MB ethernet, PoE (optional)
- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module
- USB2.0 Type-A HOST x1
- USB3.0 Type-C OTG x1
- 26-pin expansion header
- USB Type-C DC 5V Power Supply
Linux commit commit for the same,
<2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support")
Signed-off-by: Akash Gajjar
---
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 17 ++
arch/arm/dts/rk3308-rock-pi-s.dts | 228 ++
configs/rock-pi-s-rk3308_defconfig| 89 +
3 files changed, 334 insertions(+)
create mode 100644 arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3308-rock-pi-s.dts
create mode 100644 configs/rock-pi-s-rk3308_defconfig
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
new file mode 100644
index 00..27735c49dd
--- /dev/null
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl",
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <2400>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-rock-pi-s.dts
b/arch/arm/dts/rk3308-rock-pi-s.dts
new file mode 100644
index 00..b5a8691b3f
--- /dev/null
+++ b/arch/arm/dts/rk3308-rock-pi-s.dts
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2023 Akash Gajjar
+ * Copyright (c) 2023 Jagan Teki
+ */
+
+/dts-v1/;
+#include
+#include "rk3308.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi S";
+ compatible = "radxa,rockpis", "rockchip,rk3308";
+
+ aliases {
+ ethernet0 =
+ mmc0 =
+ mmc1 =
+ };
+
+ chosen {
+ stdout-path = "serial0:150n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led_gio>, <_led_gpio>;
+
+ green-led {
+ default-state = "on";
+ gpios = < RK_PA6 GPIO_ACTIVE_HIGH>;
+ label = "rockpis:green:power";
+ linux,default-trigger = "default-on";
+ };
+
+ blue-led {
+ default-state = "on";
+ gpios = < RK_PA5 GPIO_ACTIVE_HIGH>;
+ label = "rockpis:blue:user";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-0 = <_enable_h>;
+ pinctrl-names = "default";
+ reset-gpios = < RK_PA2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_1v8: vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ vin-supply = <_io>;
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_sys>;
+ };
+
+ vcc_ddr: vcc-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <150>;
+ vin-supply = <_sys>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ vin-supply = <_sys>;
+
[PATCH 0/1] Add Radxa ROCK Pi S support in U-boot
ROCK Pi S is rk3308 soc based board from Radxa. Add board support in u-boot. Booting logs is accessible at https://paste.ubuntu.com/p/cJDRzBRdXq/ Akash Gajjar (1): arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S support arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 17 ++ arch/arm/dts/rk3308-rock-pi-s.dts | 228 ++ configs/rock-pi-s-rk3308_defconfig| 89 + 3 files changed, 334 insertions(+) create mode 100644 arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3308-rock-pi-s.dts create mode 100644 configs/rock-pi-s-rk3308_defconfig -- 2.25.1
[PATCH v3 1/1] arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7
Board Specifications
- Rockchip RK3568
- 2/4/8GB LPDDR4 3200MT/s
- eMMC socket, SD card slot
- GbE LAN
- PCIe 3.0/2.0
- M.2 Connector
- 3.5mm Audio jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host/OTG, USB 2.0 Host
- 40-pin GPIO expansion ports
- USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A
Signed-off-by: Akash Gajjar
---
Changes in v2:
* Ammend the commit message, Replace Rock Pi 3a with ROCK3A Model A. Update the
specs from https://wiki.radxa.com/Rock3/3a
* Sync missing node in dts, still some of the nodes like vop, vop mmu, i2s2_2ch
gpu, hdmi removed as there is no driver support present in u-boot.
* Duplicated sdmmc node removed from dts.
Changes in v3:
* Replace rock-pi-3a-rk3568_defconfig with rock-3a-rk3568_defconfig
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 +
arch/arm/dts/rk3568-rock-3a.dts | 609
configs/rock-3a-rk3568_defconfig| 74 +++
4 files changed, 709 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
create mode 100644 configs/rock-3a-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d9b719f85d..7c28418c82 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -165,7 +165,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
- rk3568-evb.dtb
+ rk3568-evb.dtb \
+ rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
new file mode 100644
index 00..ae23ae8587
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Akash Gajjar
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ u-boot,spl-boot-order = "same-as-spl",
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2400>;
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts
new file mode 100644
index 00..a2f2baa4ea
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -0,0 +1,609 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Akash Gajjar
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3568.dtsi"
+
+/ {
+ model = "Radxa ROCK3 Model A";
+ compatible = "radxa,rock3a", "rockchip,rk3568";
+
+ chosen: chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed
[PATCH v3 0/1] Add Radxa ROCK 3 Model A support in U-boot.
ROCK 3 Model A is rk3568 based soc board from Radxa, Add board support in u-boot. Booting logs is accessible at https://paste.ubuntu.com/p/v9BNrB7MdM/ Akash Gajjar (1): arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 + arch/arm/dts/rk3568-rock-3a.dts | 609 configs/rock-3a-rk3568_defconfig| 74 +++ 4 files changed, 709 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-rock-3a.dts create mode 100644 configs/rock-3a-rk3568_defconfig -- 2.25.1
[PATCH 1/1 v2] arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7
Board Specifications
- Rockchip RK3568
- 2/4/8GB LPDDR4 3200MT/s
- eMMC socket, SD card slot
- GbE LAN
- PCIe 3.0/2.0
- M.2 Connector
- 3.5mm Audio jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host/OTG, USB 2.0 Host
- 40-pin GPIO expansion ports
- USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A
Signed-off-by: Akash Gajjar
---
Changes in v2:
* Ammend the commit message, Replace rockpis with ROCK3A Model A. Update the
specs from https://wiki.radxa.com/Rock3/3a
* Sync missing node in dts, still some of the nodes like vop, vop mmu, i2s2_2ch
gpu, hdmi removed as there is no driver support present in u-boot.
* Duplicated sdmmc node removed from dts.
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 +
arch/arm/dts/rk3568-rock-3a.dts | 609
configs/rock-pi-3a-rk3568_defconfig | 74 +++
4 files changed, 709 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
create mode 100644 configs/rock-pi-3a-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d9b719f85d..7c28418c82 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -165,7 +165,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
- rk3568-evb.dtb
+ rk3568-evb.dtb \
+ rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
new file mode 100644
index 00..42c5b6a6c5
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ * (c) Copyright 2023 Akash Gajjar
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ u-boot,spl-boot-order = "same-as-spl",
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2400>;
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts
new file mode 100644
index 00..a2f2baa4ea
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -0,0 +1,609 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Akash Gajjar
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3568.dtsi"
+
+/ {
+ model = "Radxa ROCK3 Model A";
+ compatible = "radxa,rock3a", "rockchip,rk3568";
+
+ chosen: chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA6 GPIO_ACTIVE
[PATCH 0/1 v2] Add Radxa ROCK 3 Model A support in U-boot.
ROCK 3 Model A is rk3568 based soc board from Radxa, Add board support in u-boot. Booting logs is accessible at https://paste.ubuntu.com/p/v9BNrB7MdM/ Akash Gajjar (1): arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 + arch/arm/dts/rk3568-rock-3a.dts | 609 configs/rock-pi-3a-rk3568_defconfig | 74 +++ 4 files changed, 709 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-rock-3a.dts create mode 100644 configs/rock-pi-3a-rk3568_defconfig -- 2.25.1
Re: [PATCH 1/1] rockchip: rk3568: Add Radxa Rock Pi 3A board support
Hi FUKAUMI,
Thanks for the review comments, I will correct this in the next revision.
@marek.vasut+rene...@mailbox.org ,
@feste...@denx.de , @Simon Glass , @Kever
Yang , @Philipp Tomsich
Any comments from your side?
Best Regards,
Akash
On Tue, Feb 7, 2023 at 8:32 AM FUKAUMI Naoki wrote:
> sorry, few more corrections...
>
> On 2/7/23 10:07, FUKAUMI Naoki wrote:
> > hi
> >
> > thank you very much for your work!
> >
> > On 2/7/23 02:56, Akash Gajjar wrote:
> >> Add Radxa Rock Pi 3A support.
> > "ROCK 3 Model A" or "ROCK 3A". uppercase "ROCK", no "Pi" please.
> >
> > > sync rk3568-rock-3a.dts from Linux 6.2.0-rc7
> >
> > it seems several parts of dts are omitted. why?
> >
> >> Board Specification
> >> - Rockchip RK3568
> >> - 2/4/8 GB Dual-Channel LPDDR4
>
> no "Dual-Channel"
>
> >> - eMMC socket,SD card slot
> >> - GbE LAN
> >> - PCIe 3.0/2.0
> >> - M.2 Connector
> >> - HDMI In/Out, DP, MIPI DSI/CSI
> >
> > no "HDMI In".
>
> no "DP"
>
>
> --
> FUKAUMI Naoki
>
> >> - USB 3.0, 2.0
> >> - 40-pin GPIO expansion ports
> >> - DC 12V/2A
> >
> > Type-C PD 2.0 or QC 3.0/2.0, 9V/2A - 20V/2A.
> >
> >> Signed-off-by: Akash Gajjar
> >> ---
> >> arch/arm/dts/Makefile | 3 +-
> >> arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 +++
> >> arch/arm/dts/rk3568-rock-3a.dts | 214
> >> configs/rock-pi-3a-rk3568_defconfig | 69
> >> 4 files changed, 309 insertions(+), 1 deletion(-)
> >> create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> >> create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
> >> create mode 100644 configs/rock-pi-3a-rk3568_defconfig
> >>
> >> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> >> index d9b719f85d..7c28418c82 100644
> >> --- a/arch/arm/dts/Makefile
> >> +++ b/arch/arm/dts/Makefile
> >> @@ -165,7 +165,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
> >> rk3399pro-rock-pi-n10.dtb
> >> dtb-$(CONFIG_ROCKCHIP_RK3568) += \
> >> -rk3568-evb.dtb
> >> +rk3568-evb.dtb \
> >> +rk3568-rock-3a.dtb
> >> dtb-$(CONFIG_ROCKCHIP_RV1108) += \
> >> rv1108-elgin-r1.dtb \
> >> diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> >> b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> >> new file mode 100644
> >> index 00..42c5b6a6c5
> >> --- /dev/null
> >> +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> >> @@ -0,0 +1,24 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd
> >> + * (c) Copyright 2023 Akash Gajjar
> >> + */
> >> +
> >> +#include "rk356x-u-boot.dtsi"
> >> +
> >> +/ {
> >> +chosen {
> >> +stdout-path =
> >> +u-boot,spl-boot-order = "same-as-spl",
> >> +};
> >> +};
> >> +
> >> + {
> >> +status = "okay";
> >> +};
> >
> > redundant?
> >
> >
> > Best regards,
> >
> > --
> > FUKAUMI Naoki
> >
> >> + {
> >> +clock-frequency = <2400>;
> >> +u-boot,dm-spl;
> >> +status = "okay";
> >> +};
> >> diff --git a/arch/arm/dts/rk3568-rock-3a.dts
> >> b/arch/arm/dts/rk3568-rock-3a.dts
> >> new file mode 100644
> >> index 00..0ff511d6a2
> >> --- /dev/null
> >> +++ b/arch/arm/dts/rk3568-rock-3a.dts
> >> @@ -0,0 +1,214 @@
> >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >> +/*
> >> + * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
> >> + * Copyright (c) 2023 Akash Gajjar
> >> + */
> >> +
> >> +/dts-v1/;
> >> +#include
> >> +#include
> >> +#include "rk3568.dtsi"
> >> +
> >> +/ {
> >> +model = "Radxa ROCK3 Model A";
> >> +compatible = "radxa,rock3a", "rockchip,rk3568";
> >> +
> >> +chosen: chosen {
> >> +stdout-path = "serial2:150n8";
> >> +};
> >> +
> >> +gmac1_clkin: external-gmac1-clock {
> >> +compatible = "fixed-clock";
> >> +clock-fr
[PATCH 1/1] rockchip: rk3568: Add Radxa Rock Pi 3A board support
Add Radxa Rock Pi 3A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7
Board Specification
- Rockchip RK3568
- 2/4/8 GB Dual-Channel LPDDR4
- eMMC socket,SD card slot
- GbE LAN
- PCIe 3.0/2.0
- M.2 Connector
- HDMI In/Out, DP, MIPI DSI/CSI
- USB 3.0, 2.0
- 40-pin GPIO expansion ports
- DC 12V/2A
Signed-off-by: Akash Gajjar
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 +++
arch/arm/dts/rk3568-rock-3a.dts | 214
configs/rock-pi-3a-rk3568_defconfig | 69
4 files changed, 309 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
create mode 100644 configs/rock-pi-3a-rk3568_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d9b719f85d..7c28418c82 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -165,7 +165,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
- rk3568-evb.dtb
+ rk3568-evb.dtb \
+ rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
new file mode 100644
index 00..42c5b6a6c5
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ * (c) Copyright 2023 Akash Gajjar
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ u-boot,spl-boot-order = "same-as-spl",
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2400>;
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts
new file mode 100644
index 00..0ff511d6a2
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Akash Gajjar
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3568.dtsi"
+
+/ {
+ model = "Radxa ROCK3 Model A";
+ compatible = "radxa,rock3a", "rockchip,rk3568";
+
+ chosen: chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_usb>;
+ };
+
+ vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
+ compatible = "r
[PATCH 0/1] Add Radxa Rock Pi 3A board support
Radxa Rock 3A is rk3568 based soc board, Add board support in u-boot. Booting log available at https://paste.ubuntu.com/p/SXKTm4FFhk/ Akash Gajjar (1): rockchip: rk3568: Add Radxa Rock Pi 3A board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 24 +++ arch/arm/dts/rk3568-rock-3a.dts | 214 configs/rock-pi-3a-rk3568_defconfig | 69 4 files changed, 309 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-rock-3a.dts create mode 100644 configs/rock-pi-3a-rk3568_defconfig -- 2.25.1
Re: [PATCH 1/1] i2c: mvtwsi: Add compatible string for allwinner, sun4i-a10-i2c
Acked-by: Akash Gajjar
On Fri, Jan 7, 2022, 11:23 PM Chris Morgan wrote:
> From: Chris Morgan
>
> This adds a compatible string for the Allwinner Sun4i-A10 I2C
> controller. Without this, boards based on the R8 and A13 (at a
> minimum) fail to boot.
>
> Signed-off-by: Chris Morgan
> ---
> drivers/i2c/mvtwsi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
> index ff21e3c52b..979b825eec 100644
> --- a/drivers/i2c/mvtwsi.c
> +++ b/drivers/i2c/mvtwsi.c
> @@ -900,6 +900,7 @@ static const struct dm_i2c_ops mvtwsi_i2c_ops = {
> static const struct udevice_id mvtwsi_i2c_ids[] = {
> { .compatible = "marvell,mv64xxx-i2c", },
> { .compatible = "marvell,mv78230-i2c", },
> + { .compatible = "allwinner,sun4i-a10-i2c", },
> { .compatible = "allwinner,sun6i-a31-i2c", },
> { /* sentinel */ }
> };
> --
> 2.30.2
>
>
Re: [U-Boot] [PATCH] board: rockchip: rk3399: add Rockpro64 board support
On 14/11/18 01:10, Alexander Graf wrote: On 05.11.18 08:42, akash wrote: Hi Jagan, On 05/11/18 12:40 PM, Jagan Teki wrote: On 03/11/18 4:58 PM, Akash Gajjar wrote: Rockpro64 is rk3399 based board from pine64.org. add initial board support for Rockpro64. complete board support will be added later in upcoming patchsets. Signed-off-by: Akash Gajjar --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rockpro64.dts | 519 +++ Does it pure Linux sync file? if yes mention the commit id details on commit message. Nope, it is not pure Linux sync file. though dts support is queued for Linux 4.20. Please make sure to reuse the Linux dts. That way we can in the distro boot path just not load yet another DT and simply reuse the U-Boot one. For stable SoCs (and rk3399 should be one of them) this has worked quite well in the past. arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi | 1535 Send this separately, more convenient to review ddr changes separately. Will do this in v2 changes. arch/arm/mach-rockchip/rk3399/Kconfig | 10 + board/rockchip/rockpro64/Kconfig | 15 + board/rockchip/rockpro64/MAINTAINERS | 6 + board/rockchip/rockpro64/Makefile | 7 + board/rockchip/rockpro64/rockpro64.c | 94 ++ configs/rockpro64-rk3399_defconfig | 78 + include/configs/rockpro64.h | 15 + 10 files changed, 2280 insertions(+) create mode 100644 arch/arm/dts/rk3399-rockpro64.dts create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi create mode 100644 board/rockchip/rockpro64/Kconfig create mode 100644 board/rockchip/rockpro64/MAINTAINERS create mode 100644 board/rockchip/rockpro64/Makefile create mode 100644 board/rockchip/rockpro64/rockpro64.c create mode 100644 configs/rockpro64-rk3399_defconfig create mode 100644 include/configs/rockpro64.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d36447d18d..8a84cf55a3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ + rk3399-rockpro64.dtb \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts new file mode 100644 index 00..8497a1124b --- /dev/null +++ b/arch/arm/dts/rk3399-rockpro64.dts @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018 Akash Gajjar + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-sdram-lpddr4-1600.dtsi" if this change related to u-boot, just sync Linux dts file and create -u-boot.dtsi and include this on that. Just to understand, what has been tested with this support? This initial phase patchsets are just to notify community that board support is in progress. In V2 changes will add complete support of u-boot for Rockpro64. When can we expect v2? The merge window is opening :) Hi Alex, I took little long to update the status of this development. Firmware provided by Rock-chip bringing up the DDR4 and starting it with 50Mhz, 400Mhz, and 800Mhz respectively. Long ago I have extracted parameters from rk3399_ddr_933MHz_v1.13.bin for 50Mhz, 400Mhz and 800Mhz. I tested those timing data and it fails in write leveling. I took hex-dump of DDR CTL, PHY and PI address from working U-boot and found similar parameters like hex-dump of DDR firmware with the difference in few parameters. but this plain parameters is not helpful as out of box bring up of lpddr4 ram, as the firmware itself tunes these parameters at runtime. As of now, so I have kept this task on hold until I arrange for the HW debugger. Akash Alex ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] board: rockchip: rk3399: add Rockpro64 board support
Hi Alexander Graf,
On 11/14/2018 1:17 AM, Alexander Graf wrote:
On 03.11.18 12:28, Akash Gajjar wrote:
Rockpro64 is rk3399 based board from pine64.org. add initial board support for
Rockpro64. complete board support will be added later in upcoming patchsets.
Signed-off-by: Akash Gajjar
---
[...]
diff --git a/board/rockchip/rockpro64/rockpro64.c
b/board/rockchip/rockpro64/rockpro64.c
new file mode 100644
index 00..74c7a56bd5
--- /dev/null
+++ b/board/rockchip/rockpro64/rockpro64.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Akash Gajjar
Given the file is copied from another copyrighted file, you can not just
go and replace the (c) with yours.
Thanks for correction, will add original copyrights.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int board_init(void)
+{
+ struct udevice *pinctrl, *regulator;
+ int ret;
+
+ /*
+* The PWM do not have decicated interrupt number in dts and can
dedicated?
This whole file seems to just be a copy of
board/rockchip/evb_rk3399/evb-rk3399.c. Maybe you can abstract and share
code?
But please double check if what they do is actually necessary on
RockPro64 first.
yes, we have taken evb rk3399 bsp support for reference.
will add only necessary support in v2 patch-sets and submit in couple of
days.
Alex
+* not get periph_id by pinctrl framework, so let's init them here.
+* The PWM2 and PWM3 are for pwm regulater.
+*/
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, );
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ goto out;
+ }
+
+ /* Enable pwm0 for panel backlight */
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0);
+ if (ret) {
+ debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret);
+ goto out;
+ }
+
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
+ if (ret) {
+ debug("%s PWM2 pinctrl init fail!\n", __func__);
+ goto out;
+ }
+
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3);
+ if (ret) {
+ debug("%s PWM3 pinctrl init fail!\n", __func__);
+ goto out;
+ }
+
+ ret = regulators_enable_boot_on(false);
+ if (ret)
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+
+ ret = regulator_get_by_platname("vcc5v0_host", );
+ if (ret) {
+ debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
+ goto out;
+ }
+
+ ret = regulator_set_enable(regulator, true);
+ if (ret) {
+ debug("%s vcc5v0-host-en set fail!\n", __func__);
+ goto out;
+ }
+
+out:
+ return 0;
+}
+
+void spl_board_init(void)
+{
+ struct udevice *pinctrl;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, );
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ goto err;
+ }
+
+ /* Enable debug UART */
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+ if (ret) {
+ debug("%s: Failed to set up console UART\n", __func__);
+ goto err;
+ }
+
+ preloader_console_init();
+ return;
+err:
+ printf("%s: Error %d\n", __func__, ret);
+
+ /* No way to report error here */
+ hang();
+}
diff --git a/configs/rockpro64-rk3399_defconfig
b/configs/rockpro64-rk3399_defconfig
new file mode 100644
index 00..88422f2db4
--- /dev/null
+++ b/configs/rockpro64-rk3399_defconfig
@@ -0,0 +1,78 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_ROCKPRO64_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_DEBUG_UART_BASE=0xFF1A
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent
assigned-clocks assigned-clock-rates assigned-c
Re: [U-Boot] [PATCH] board: rockchip: rk3399: add Rockpro64 board support
Hi Jagan, On 05/11/18 12:40 PM, Jagan Teki wrote: On 03/11/18 4:58 PM, Akash Gajjar wrote: Rockpro64 is rk3399 based board from pine64.org. add initial board support for Rockpro64. complete board support will be added later in upcoming patchsets. Signed-off-by: Akash Gajjar --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rockpro64.dts | 519 +++ Does it pure Linux sync file? if yes mention the commit id details on commit message. Nope, it is not pure Linux sync file. though dts support is queued for Linux 4.20. arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi | 1535 Send this separately, more convenient to review ddr changes separately. Will do this in v2 changes. arch/arm/mach-rockchip/rk3399/Kconfig | 10 + board/rockchip/rockpro64/Kconfig | 15 + board/rockchip/rockpro64/MAINTAINERS | 6 + board/rockchip/rockpro64/Makefile | 7 + board/rockchip/rockpro64/rockpro64.c | 94 ++ configs/rockpro64-rk3399_defconfig | 78 + include/configs/rockpro64.h | 15 + 10 files changed, 2280 insertions(+) create mode 100644 arch/arm/dts/rk3399-rockpro64.dts create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi create mode 100644 board/rockchip/rockpro64/Kconfig create mode 100644 board/rockchip/rockpro64/MAINTAINERS create mode 100644 board/rockchip/rockpro64/Makefile create mode 100644 board/rockchip/rockpro64/rockpro64.c create mode 100644 configs/rockpro64-rk3399_defconfig create mode 100644 include/configs/rockpro64.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d36447d18d..8a84cf55a3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ + rk3399-rockpro64.dtb \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts new file mode 100644 index 00..8497a1124b --- /dev/null +++ b/arch/arm/dts/rk3399-rockpro64.dts @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018 Akash Gajjar + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-sdram-lpddr4-1600.dtsi" if this change related to u-boot, just sync Linux dts file and create -u-boot.dtsi and include this on that. Just to understand, what has been tested with this support? This initial phase patchsets are just to notify community that board support is in progress. In V2 changes will add complete support of u-boot for Rockpro64. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] board: rockchip: rk3399: add Rockpro64 board support
Rockpro64 is rk3399 based board from pine64.org. add initial board support for
Rockpro64. complete board support will be added later in upcoming patchsets.
Signed-off-by: Akash Gajjar
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/rk3399-rockpro64.dts | 519 +++
arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi | 1535
arch/arm/mach-rockchip/rk3399/Kconfig | 10 +
board/rockchip/rockpro64/Kconfig | 15 +
board/rockchip/rockpro64/MAINTAINERS |6 +
board/rockchip/rockpro64/Makefile |7 +
board/rockchip/rockpro64/rockpro64.c | 94 ++
configs/rockpro64-rk3399_defconfig | 78 +
include/configs/rockpro64.h| 15 +
10 files changed, 2280 insertions(+)
create mode 100644 arch/arm/dts/rk3399-rockpro64.dts
create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi
create mode 100644 board/rockchip/rockpro64/Kconfig
create mode 100644 board/rockchip/rockpro64/MAINTAINERS
create mode 100644 board/rockchip/rockpro64/Makefile
create mode 100644 board/rockchip/rockpro64/rockpro64.c
create mode 100644 configs/rockpro64-rk3399_defconfig
create mode 100644 include/configs/rockpro64.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d36447d18d..8a84cf55a3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
+ rk3399-rockpro64.dtb \
rv1108-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-nanopi-k2.dtb \
diff --git a/arch/arm/dts/rk3399-rockpro64.dts
b/arch/arm/dts/rk3399-rockpro64.dts
new file mode 100644
index 00..8497a1124b
--- /dev/null
+++ b/arch/arm/dts/rk3399-rockpro64.dts
@@ -0,0 +1,519 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Akash Gajjar
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3399.dtsi"
+#include "rk3399-sdram-lpddr4-1600.dtsi"
+
+/ {
+ model = "Pine64 Rockpro64-RK3399 Board";
+ compatible = "pine64,rockpro64", "rockchip,rk3399";
+
+ chosen {
+ stdout-path =
+ u-boot,spl-boot-order = ,
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_vbus_drv>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = < 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <43>;
+ regulator-max-microvolt = <140>;
+ regulator-init-microvolt = <95>;
+ };
+
+ vccadc_ref: vccadc-ref {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ };
+};
+
+_l0 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l1 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l2 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l3 {
+ cpu-supply = <_cpu_l>;
+};
+
+_b0 {
+ cpu-supply = <_cpu_b>;
+};
+
+_b1 {
+ cpu-supply = &l
Re: [U-Boot] [PATCH v3 3/3] spi: mxs_spi: DM conversion
Hello Marek,
On Fri, May 11, 2018 at 4:09 PM, Marek Vasut <marek.va...@gmail.com> wrote:
> On 05/11/2018 12:08 PM, Gajjar Akash wrote:
> > Hi Marek,
> >
> > Thanks for the review comments.
> >
> > > -struct mxs_spi_slave {
> > > - struct spi_slaveslave;
> > > - uint32_tmax_khz;
> > > - uint32_tmode;
> > > - struct mxs_ssp_regs *regs;
> > > +struct mxs_spi_priv {
> > > + struct mxs_ssp_regs *regs;
> > > + u32 max_khz;
> > > + u32 mode;
> > > + u32 bus;
> > > + u32 cs;
> >
> > Type cleanup should be a separate patch
> >
> >
> > Okay, I will prepare seperate patch for type cleanup.
> >
> >
> > > };
> > > if (mxs_wait_mask_set(_regs->hw_ssp_ctrl0_reg,
> > > SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
> > > - printf("MXS SPI: Timeout waiting for
> start\n");
> > > + debug("MXS SPI: Timeout waiting for
> start\n");
> >
> > printf , we don't want to hide errors
> >
> >
> > okay, will revert it back to printf.
> >
> >
> > > return -ETIMEDOUT;
> > > }
> >
> > > +
> > > +#ifndef __SPI_MXS_H
> > > +#define __SPI_MXS_H
> > > +
> > > +struct mxs_spi_platdata {
> > > + struct mxs_ssp_regs *regs;
> > > + u32 bus;
> > > + u32 max_hz;
> > > + u32 cs;
> >
> > Why is this header here at all ?
> >
> >
> > I didnt get this comment. do I need to place it somewhere else?
>
> See the beginning of this email, it seems the same structure exists twice.
>
My intention was to have two individual structure for private and platform
data.
But now I could use one structre and access its members using two structure
variables(one for private and one for platadata).
Is That looks okay?
>
> --
> Best regards,
> Marek Vasut
>
Thanks,
*Akash Gajjar*
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/3] spi: mxs_spi: DM conversion
Hi Marek,
Thanks for the review comments.
> -struct mxs_spi_slave {
> > - struct spi_slaveslave;
> > - uint32_tmax_khz;
> > - uint32_tmode;
> > - struct mxs_ssp_regs *regs;
> > +struct mxs_spi_priv {
> > + struct mxs_ssp_regs *regs;
> > + u32 max_khz;
> > + u32 mode;
> > + u32 bus;
> > + u32 cs;
>
> Type cleanup should be a separate patch
>
Okay, I will prepare seperate patch for type cleanup.
> > };
> > if (mxs_wait_mask_set(_regs->hw_ssp_ctrl0_reg,
> > SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
> > - printf("MXS SPI: Timeout waiting for start\n");
> > + debug("MXS SPI: Timeout waiting for start\n");
>
> printf , we don't want to hide errors
>
okay, will revert it back to printf.
> > return -ETIMEDOUT;
> > }
> +
> > +#ifndef __SPI_MXS_H
> > +#define __SPI_MXS_H
> > +
> > +struct mxs_spi_platdata {
> > + struct mxs_ssp_regs *regs;
> > + u32 bus;
> > + u32 max_hz;
> > + u32 cs;
>
> Why is this header here at all ?
>
I didnt get this comment. do I need to place it somewhere else?
> +};
> > +
> > +#endif /* __SPI_MXS_H */
> >
>
>
> --
> Best regards,
> Marek Vasut
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>
Thanks,
Akash
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/3] spi: mxs_spi: DM conversion
This patch adds support for DM driver model to the mxs spi driver. Some TODOs
are left over for later. These would be enhancements to the original
functionality, and can come later. The legacy functionality is removed in
this version.
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
changes in v2:
Register cs_info method
Remove unused function __mxs_spi_setup
Merged __spi_xfer function to spi_xfer
printf replaced by debug
changes in v3:
changes made on top of previous patch is merged in v3
---
drivers/spi/Kconfig| 12 +-
drivers/spi/mxs_spi.c | 258 +++--
include/dm/platform_data/spi_mxs.h | 18 +++
3 files changed, 183 insertions(+), 105 deletions(-)
create mode 100644 include/dm/platform_data/spi_mxs.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ec92b84..5d3e152 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -106,6 +106,12 @@ config MVEBU_A3700_SPI
used to access the SPI NOR flash on platforms embedding this
Marvell IP core.
+config MXS_SPI
+ bool "MXS SPI Driver"
+ help
+ Enable the MXS SPI controller driver. This driver can be used
+ on the i.MX23 and i.MX28 SoCs.
+
config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32
@@ -299,12 +305,6 @@ config MXC_SPI
Enable the MXC SPI controller driver. This driver can be used
on various i.MX SoCs such as i.MX31/35/51/6/7.
-config MXS_SPI
- bool "MXS SPI Driver"
- help
- Enable the MXS SPI controller driver. This driver can be used
- on the i.MX23 and i.MX28 SoCs.
-
config OMAP3_SPI
bool "McSPI driver for OMAP"
help
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 790db78..3054438 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -1,6 +1,9 @@
/*
* Freescale i.MX28 SPI driver
*
+ * Support for device model:
+ * Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
+ *
* Copyright (C) 2011 Marek Vasut <marek.va...@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
@@ -20,6 +23,8 @@
#include
#include
#include
+#include
+#include
#defineMXS_SPI_MAX_TIMEOUT 100
#defineMXS_SPI_PORT_OFFSET 0x2000
@@ -28,93 +33,14 @@
#define MXSSSP_SMALL_TRANSFER 512
-struct mxs_spi_slave {
- struct spi_slaveslave;
- uint32_tmax_khz;
- uint32_tmode;
- struct mxs_ssp_regs *regs;
+struct mxs_spi_priv {
+ struct mxs_ssp_regs *regs;
+ u32 max_khz;
+ u32 mode;
+ u32 bus;
+ u32 cs;
};
-static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct mxs_spi_slave, slave);
-}
-
-void spi_init(void)
-{
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- /* MXS SPI: 4 ports and 3 chip selects maximum */
- if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
- return 0;
- else
- return 1;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct mxs_spi_slave *mxs_slave;
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
- return NULL;
- }
-
- mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
- if (!mxs_slave)
- return NULL;
-
- if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
- goto err_init;
-
- mxs_slave->max_khz = max_hz / 1000;
- mxs_slave->mode = mode;
- mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
-
- return _slave->slave;
-
-err_init:
- free(mxs_slave);
- return NULL;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- free(mxs_slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
- uint32_t reg = 0;
-
- mxs_reset_block(_regs->hw_ssp_ctrl0_reg);
-
- writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
- SSP_CTRL0_BUS_WIDTH_ONE_BIT,
- _regs->hw_ssp_ctrl0);
-
- reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
- reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
- reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
- writel(reg, _regs->hw_ssp_ctrl1);
-
- writel(0, _regs->hw_ssp_cmd0);
-
- mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
-
- return 0;
-}
-
-void spi_release_bus(stru
[U-Boot] [PATCH v3 2/3] spi: sh_spi: DM conversion
This patch adds support for DM to the sh_spi driver. legacy driver support is
removed. Some TODOs are left over for later, These would be enhancements to
the original functionality, and can come later. The legacy functionality is
removed in this version.
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
Changes in v2:
Add cs_info method
Remove fixed regs address
Add missing platform struct missing member
Moved priv struct into sh_spi.c
Remove unnecessary space and comments
Changes in v3:
Changes made on top of previous patch is merged in v3
---
drivers/spi/Kconfig | 12 +-
drivers/spi/sh_spi.c | 235 +++---
drivers/spi/sh_spi.h | 5 -
include/dm/platform_data/spi_sh.h | 15 +++
4 files changed, 164 insertions(+), 103 deletions(-)
create mode 100644 include/dm/platform_data/spi_sh.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ec92b84..be6ad22 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -155,6 +155,12 @@ config SANDBOX_SPI
};
};
+config SH_SPI
+ bool "SuperH SPI driver"
+ help
+ Enable the SuperH SPI controller driver. This driver can be used
+ on various SuperH SoCs, such as SH7757.
+
config STM32_QSPI
bool "STM32F7 QSPI driver"
depends on STM32F7
@@ -253,12 +259,6 @@ config DAVINCI_SPI
help
Enable the Davinci SPI driver
-config SH_SPI
- bool "SuperH SPI driver"
- help
- Enable the SuperH SPI controller driver. This driver can be used
- on various SuperH SoCs, such as SH7757.
-
config SH_QSPI
bool "Renesas Quad SPI driver"
help
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
index fe394e3..ba92bfb 100644
--- a/drivers/spi/sh_spi.c
+++ b/drivers/spi/sh_spi.c
@@ -1,6 +1,9 @@
/*
* SH SPI driver
*
+ * Support for device model:
+ * Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
+ *
* Copyright (C) 2011-2012 Renesas Solutions Corp.
*
* SPDX-License-Identifier:GPL-2.0
@@ -11,8 +14,15 @@
#include
#include
#include
+#include
+#include
#include "sh_spi.h"
+struct sh_spi_priv {
+ struct sh_spi_regs *regs;
+ u32 cs;
+};
+
static void sh_spi_write(unsigned long data, unsigned long *reg)
{
writel(data, reg);
@@ -41,15 +51,15 @@ static void sh_spi_clear_bit(unsigned long val, unsigned
long *reg)
sh_spi_write(tmp, reg);
}
-static void clear_fifo(struct sh_spi *ss)
+static void clear_fifo(struct sh_spi_regs *regs)
{
- sh_spi_set_bit(SH_SPI_RSTF, >regs->cr2);
- sh_spi_clear_bit(SH_SPI_RSTF, >regs->cr2);
+ sh_spi_set_bit(SH_SPI_RSTF, >cr2);
+ sh_spi_clear_bit(SH_SPI_RSTF, >cr2);
}
-static int recvbuf_wait(struct sh_spi *ss)
+static int recvbuf_wait(struct sh_spi_regs *regs)
{
- while (sh_spi_read(>regs->cr1) & SH_SPI_RBE) {
+ while (sh_spi_read(>cr1) & SH_SPI_RBE) {
if (ctrlc())
return 1;
udelay(10);
@@ -57,9 +67,9 @@ static int recvbuf_wait(struct sh_spi *ss)
return 0;
}
-static int write_fifo_empty_wait(struct sh_spi *ss)
+static int write_fifo_empty_wait(struct sh_spi_regs *regs)
{
- while (!(sh_spi_read(>regs->cr1) & SH_SPI_TBE)) {
+ while (!(sh_spi_read(>cr1) & SH_SPI_TBE)) {
if (ctrlc())
return 1;
udelay(10);
@@ -67,11 +77,7 @@ static int write_fifo_empty_wait(struct sh_spi *ss)
return 0;
}
-void spi_init(void)
-{
-}
-
-static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
+static void sh_spi_set_cs(struct sh_spi_regs *regs, unsigned int cs)
{
unsigned long val = 0;
@@ -80,85 +86,54 @@ static void sh_spi_set_cs(struct sh_spi *ss, unsigned int
cs)
if (cs & 0x02)
val |= SH_SPI_SSS1;
- sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, >regs->cr4);
- sh_spi_set_bit(val, >regs->cr4);
+ sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, >cr4);
+ sh_spi_set_bit(val, >cr4);
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static void spi_setup(struct sh_spi_priv *priv)
{
- struct sh_spi *ss;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- ss = spi_alloc_slave(struct sh_spi, bus, cs);
- if (!ss)
- return NULL;
-
- ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
+ struct sh_spi_regs *regs = priv->regs;
+ u32 cs = priv->cs;
/* SPI sycle stop */
- sh_spi_write(0xfe, >regs->cr1);
+ sh_spi_write(0xfe, >cr1);
/* CR1 init */
- sh_spi_write(0x00, >regs->cr1);
+ sh_spi_write(0x00, >c
[U-Boot] [PATCH v3 1/3] spi: sh_qspi: DM conversion
This patch adds support for DM to the sh_qspi SPI driver.
The legacy functionality is removed in this version, so old boards in the tree
is not working with legacy SPI driver functionality. Some TODOs are left over
for later, These would be enhancements to the original functionality, and can
come later.
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
changes in v2:
Update Kconfig
Replace __sh_qspi_setup to sh_qspi_setup
Add missing memeber of platform data
changes in v3:
Changes made on top of previous patch is merged in v3
---
drivers/spi/Kconfig| 12 +--
drivers/spi/sh_qspi.c | 199 ++---
include/dm/platform_data/qspi_sh.h | 15 +++
3 files changed, 120 insertions(+), 106 deletions(-)
create mode 100644 include/dm/platform_data/qspi_sh.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ec92b84..81079c5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -155,6 +155,12 @@ config SANDBOX_SPI
};
};
+config SH_QSPI
+ bool "Renesas Quad SPI driver"
+ help
+ Enable the Renesas Quad SPI controller driver. This driver can be
+ used on Renesas SoCs.
+
config STM32_QSPI
bool "STM32F7 QSPI driver"
depends on STM32F7
@@ -259,12 +265,6 @@ config SH_SPI
Enable the SuperH SPI controller driver. This driver can be used
on various SuperH SoCs, such as SH7757.
-config SH_QSPI
- bool "Renesas Quad SPI driver"
- help
- Enable the Renesas Quad SPI controller driver. This driver can be
- used on Renesas SoCs.
-
config TI_QSPI
bool "TI QSPI driver"
help
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 5075be3..1ea24ce 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -1,6 +1,9 @@
/*
* SH QSPI (Quad SPI) driver
*
+ * Support for device model:
+ * Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
+ *
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu...@renesas.com>
*
@@ -14,6 +17,8 @@
#include
#include
#include
+#include
+#include
/* SH QSPI register bit masks _ */
#define SPCR_MSTR 0x08
@@ -67,151 +72,89 @@ struct sh_qspi_regs {
u32 spbmul3;
};
-struct sh_qspi_slave {
- struct spi_slaveslave;
- struct sh_qspi_regs *regs;
+struct sh_qspi_priv {
+ struct sh_qspi_regs *regs;
};
-static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
+static void sh_qspi_setup(struct sh_qspi_priv *priv)
{
- return container_of(slave, struct sh_qspi_slave, slave);
-}
+ struct sh_qspi_regs *regs = priv->regs;
-static void sh_qspi_init(struct sh_qspi_slave *ss)
-{
- /* QSPI initialize */
/* Set master mode only */
- writeb(SPCR_MSTR, >regs->spcr);
+ writeb(SPCR_MSTR, >spcr);
/* Set SSL signal level */
- writeb(0x00, >regs->sslp);
+ writeb(0x00, >sslp);
/* Set MOSI signal value when transfer is in idle state */
- writeb(SPPCR_IO3FV|SPPCR_IO2FV, >regs->sppcr);
+ writeb(SPPCR_IO3FV | SPPCR_IO2FV, >sppcr);
/* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
- writeb(0x01, >regs->spbr);
+ writeb(0x01, >spbr);
/* Disable Dummy Data Transmission */
- writeb(0x00, >regs->spdcr);
+ writeb(0x00, >spdcr);
/* Set clock delay value */
- writeb(0x00, >regs->spckd);
+ writeb(0x00, >spckd);
/* Set SSL negation delay value */
- writeb(0x00, >regs->sslnd);
+ writeb(0x00, >sslnd);
/* Set next-access delay value */
- writeb(0x00, >regs->spnd);
+ writeb(0x00, >spnd);
/* Set equence command */
- writew(SPCMD_INIT2, >regs->spcmd0);
-
- /* Reset transfer and receive Buffer */
- setbits_8(>regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
-
- /* Clear transfer and receive Buffer control bit */
- clrbits_8(>regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
-
- /* Set equence control method. Use equence0 only */
- writeb(0x00, >regs->spscr);
-
- /* Enable SPI function */
- setbits_8(>regs->spcr, SPCR_SPE);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct sh_qspi_slave *ss = to_sh_qspi(slave);
-
- /* Set master mode only */
- writeb(SPCR_MSTR, >regs->spcr);
-
- /* Set command */
- writew(SPCMD_INIT1, >regs->spcmd0);
+ writew(SPCMD_INIT2, >spcmd0);
/* Reset transfer and receive Buffer */
- setbits_8(>regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
+ setbits_8(>spbfcr, SPBFC
[U-Boot] [PATCH v2 3/3] spi: mxs_spi: full dm conversion
v1->v2
register cs_info method
remove unused function __mxs_spi_setup
merged __spi_xfer function to spi_xfer
printf replaced by debug
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
drivers/spi/mxs_spi.c | 169 --
1 file changed, 81 insertions(+), 88 deletions(-)
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 0af2eee..3054438 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -82,7 +82,7 @@ static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
if (mxs_wait_mask_set(_regs->hw_ssp_ctrl0_reg,
SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
- printf("MXS SPI: Timeout waiting for start\n");
+ debug("MXS SPI: Timeout waiting for start\n");
return -ETIMEDOUT;
}
@@ -94,7 +94,7 @@ static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
if (!write) {
if (mxs_wait_mask_clr(_regs->hw_ssp_status_reg,
SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
- printf("MXS SPI: Timeout waiting for data\n");
+ debug("MXS SPI: Timeout waiting for data\n");
return -ETIMEDOUT;
}
@@ -104,7 +104,7 @@ static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
if (mxs_wait_mask_clr(_regs->hw_ssp_ctrl0_reg,
SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
- printf("MXS SPI: Timeout waiting for finish\n");
+ debug("MXS SPI: Timeout waiting for finish\n");
return -ETIMEDOUT;
}
}
@@ -233,78 +233,6 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
return ret;
}
-static int __spi_xfer(struct mxs_spi_priv *priv, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
- struct mxs_ssp_regs *ssp_regs = priv->regs;
- int len = bitlen / 8;
- char dummy;
- int write = 0;
- char *data = NULL;
- int dma = 1;
-
- if (bitlen == 0) {
- if (flags & SPI_XFER_END) {
- din = (void *)
- len = 1;
- } else
- return 0;
- }
-
- /* Half-duplex only */
- if (din && dout)
- return -EINVAL;
- /* No data */
- if (!din && !dout)
- return 0;
-
- if (dout) {
- data = (char *)dout;
- write = 1;
- } else if (din) {
- data = (char *)din;
- write = 0;
- }
-
- /*
-* Check for alignment, if the buffer is aligned, do DMA transfer,
-* PIO otherwise. This is a temporary workaround until proper bounce
-* buffer is in place.
-*/
- if (dma) {
- if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
- dma = 0;
- if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
- dma = 0;
- }
-
- if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
- writel(SSP_CTRL1_DMA_ENABLE, _regs->hw_ssp_ctrl1_clr);
- return mxs_spi_xfer_pio(priv, data, len, write, flags);
- } else {
- writel(SSP_CTRL1_DMA_ENABLE, _regs->hw_ssp_ctrl1_set);
- return mxs_spi_xfer_dma(priv, data, len, write, flags);
- }
-}
-
-static int __mxs_spi_setup(struct mxs_spi_priv *mxs_spi, uint bus)
-{
- struct mxs_spi_priv *priv = mxs_spi;
- int err;
-
- priv->max_khz = max_hz / 1000;
- priv->mode = mode;
- priv->regs = mxs_ssp_regs_by_bus(bus);
- priv->bus = bus;
-
- if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->bus)) {
- printf("%s: DMA init channel error %d\n", __func__, err);
- return err;
- }
-
- return 0;
-}
-
static int mxs_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
@@ -321,8 +249,6 @@ static int mxs_spi_claim_bus(struct udevice *dev)
static int mxs_spi_release_bus(struct udevice *dev)
{
- /* TODO */
-
return 0;
}
@@ -335,7 +261,7 @@ static int mxs_spi_set_speed(struct udevice *bus, uint
speed)
speed = plat->max_khz;
priv->max_khz = speed;
- printf("%s speed %u\n", __func__, speed);
+ debug("%s speed %u\n", __func__, speed);
mxs_set_ssp_busclock(plat->bus, priv->max_khz);
@@ -348,8 +274,8 @@ static int mxs_spi_set_mode(struct udevice *bus, uint mode)
struct mxs_ssp_regs *ssp_regs = priv->regs;
u32 reg;
- printf(&q
[U-Boot] [PATCH v1 1/1] spi: lpc32xx_ssp: DM conversion
From: Akash Gajjar <gajjar04ak...@gmail.com>
This patch adds support for DM to the LPC32xx SSP SPI driver.
Some TODOs are left over for later, These would be enhancements to the
original functionality, and can come later. The legacy functionality is
removed in this version.
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
drivers/spi/Kconfig| 10 +-
drivers/spi/lpc32xx_ssp.c | 145 +++--
include/dm/platform_data/spi_lpc32xx_ssp.h | 15 +++
3 files changed, 93 insertions(+), 77 deletions(-)
create mode 100644 include/dm/platform_data/spi_lpc32xx_ssp.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ec92b84..2297d4a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -99,6 +99,11 @@ config ICH_SPI
access the SPI NOR flash on platforms embedding this Intel
ICH IP core.
+config LPC32XX_SSP
+ bool "LPC32XX SPI Driver"
+ help
+ Enable support for SPI on LPC32xx
+
config MVEBU_A3700_SPI
bool "Marvell Armada 3700 SPI driver"
help
@@ -277,11 +282,6 @@ config KIRKWOOD_SPI
Enable support for SPI on various Marvell SoCs, such as
Kirkwood and Armada 375.
-config LPC32XX_SSP
- bool "LPC32XX SPI Driver"
- help
- Enable support for SPI on LPC32xx
-
config MPC8XX_SPI
bool "MPC8XX SPI Driver"
depends on MPC8xx
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
index e2a593b..ae41b57 100644
--- a/drivers/spi/lpc32xx_ssp.c
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -4,6 +4,9 @@
* (C) Copyright 2014 DENX Software Engineering GmbH
* Written-by: Albert ARIBAUD <albert.arib...@3adev.fr>
*
+ * Support for device model:
+ * Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -13,6 +16,8 @@
#include
#include
#include
+#include
+#include
/* SSP chip registers */
struct ssp_regs {
@@ -36,90 +41,36 @@ struct ssp_regs {
/* SSP status RX FIFO not empty bit */
#define SSP_SR_RNE 0x0004
-/* lpc32xx spi slave */
-struct lpc32xx_spi_slave {
- struct spi_slave slave;
+struct lpc32xx_ssp_spi_priv {
struct ssp_regs *regs;
};
-static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave(
- struct spi_slave *slave)
+static int lpc32xx_ssp_spi_claim_bus(struct udevice *dev)
{
- return container_of(slave, struct lpc32xx_spi_slave, slave);
-}
-
-/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
-void spi_init(void)
-{
- /*
-* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
-* and configuration will be done in spi_setup_slave()
- */
+ return 0;
}
-/* the following is called in sequence by do_spi_xfer() */
-
-struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+static int lpc32xx_ssp_spi_release_bus(struct udevice *dev)
{
- struct lpc32xx_spi_slave *lslave;
-
- /* we only set up SSP0 for now, so ignore bus */
-
- if (mode & SPI_3WIRE) {
- pr_err("3-wire mode not supported");
- return NULL;
- }
-
- if (mode & SPI_SLAVE) {
- pr_err("slave mode not supported\n");
- return NULL;
- }
-
- if (mode & SPI_PREAMBLE) {
- pr_err("preamble byte skipping not supported\n");
- return NULL;
- }
-
- lslave = spi_alloc_slave(struct lpc32xx_spi_slave, bus, cs);
- if (!lslave) {
- printf("SPI_error: Fail to allocate lpc32xx_spi_slave\n");
- return NULL;
- }
-
- lslave->regs = (struct ssp_regs *)SSP0_BASE;
-
- /*
-* 8 bit frame, SPI fmt, 500kbps -> clock divider is 26.
-* Set SCR to 0 and CPSDVSR to 26.
-*/
-
- writel(0x7, >regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */
- writel(26, >regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */
- writel(0, >regs->imsc); /* do not raise any interrupts */
- writel(0, >regs->icr); /* clear any pending interrupt */
- writel(0, >regs->dmacr); /* do not do DMAs */
- writel(SSP_CR1_SSP_ENABLE, >regs->cr1); /* enable SSP0 */
- return >slave;
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int lpc32xx_ssp_spi_set_speed(struct udevice *bus, uint hz)
{
- struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave);
-
- debug("(lpc32xx) spi_free_slave: 0x%08x\n", (u32)lslave);
- free(lslave);
+ return 0;
}
-int spi_claim_bus(struct spi_slave *slave)
+static int lpc32xx_ssp_spi_set_mode(struct udevice *bus, uint mode)
{
- /* only one bus and slave so far, always available */
return 0;
}
-int spi_xfe
[U-Boot] [PATCH v2 2/3] spi: sh_spi: full DM conversion
v1->v2
New in v2
add cs_info method
remove fixed regs address
add missing platform struct missing member
moved priv struct into sh_spi.c
remove unnecessary space and comments
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
drivers/spi/sh_spi.c | 44 +++
drivers/spi/sh_spi.h | 4
include/dm/platform_data/spi_sh.h | 5 -
3 files changed, 35 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
index b308ec8..db14031 100644
--- a/drivers/spi/sh_spi.c
+++ b/drivers/spi/sh_spi.c
@@ -2,7 +2,7 @@
* SH SPI driver
*
* Support for device model:
- * Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
+ * Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
* Harshit Shah <shahharsh...@gmail.com>
*
* Copyright (C) 2011-2012 Renesas Solutions Corp.
@@ -19,6 +19,11 @@
#include
#include "sh_spi.h"
+struct sh_spi_priv {
+ struct sh_spi_regs *regs;
+ u32 cs;
+};
+
static void sh_spi_write(unsigned long data, unsigned long *reg)
{
writel(data, reg);
@@ -86,10 +91,11 @@ static void sh_spi_set_cs(struct sh_spi_regs *regs,
unsigned int cs)
sh_spi_set_bit(val, >cr4);
}
-static void __spi_setup(struct sh_spi_regs *regs, uint cs)
+static void spi_setup(struct sh_spi_priv *priv)
{
- /* initialize spi */
- regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
+ struct sh_spi_regs *regs = priv->regs;
+ u32 cs = priv->cs;
+
/* SPI sycle stop */
sh_spi_write(0xfe, >cr1);
/* CR1 init */
@@ -106,7 +112,7 @@ static void __spi_setup(struct sh_spi_regs *regs, uint cs)
}
static int sh_spi_send(struct sh_spi_regs *regs, const unsigned char *tx_data,
- unsigned int len, unsigned long flags)
+ unsigned int len, unsigned long flags)
{
int i, cur_len, ret = 0;
int remain = (int)len;
@@ -151,7 +157,7 @@ static int sh_spi_send(struct sh_spi_regs *regs, const
unsigned char *tx_data,
}
static int sh_spi_receive(struct sh_spi_regs *regs, unsigned char *rx_data,
- unsigned int len, unsigned long flags)
+ unsigned int len, unsigned long flags)
{
int i;
@@ -227,12 +233,29 @@ static int sh_spi_xfer(struct udevice *dev, unsigned int
bitlen,
return ret;
}
+static int sh_spi_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+{
+ struct sh_spi_priv *priv = dev_get_priv(bus);
+
+ if (cs >= priv->cs) {
+ printf("no cs %u\n", cs);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
static int sh_spi_probe(struct udevice *bus)
{
+ struct sh_spi_platdata *plat = bus->platdata;
struct sh_spi_priv *priv = dev_get_priv(bus);
struct sh_spi_regs *regs = priv->regs;
- __spi_setup(regs, priv->cs);
+ priv->regs = plat->regs;
+ priv->cs = plat->cs;
+
+ spi_setup(priv);
return 0;
}
@@ -248,8 +271,9 @@ static int sh_spi_ofdata_to_platadata(struct udevice *bus)
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
+ plat->regs = (struct sh_spi_regs *regs)addr;
plat->cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
- "num-cs", 4);
+ "num-cs", 4);
return 0;
}
@@ -259,10 +283,12 @@ static const struct dm_spi_ops mvebu_spi_ops = {
.xfer = sh_spi_xfer,
.set_speed = sh_spi_set_speed,
.set_mode = sh_spi_set_mode,
+ .cs_info= sh_spi_cs_info,
};
+/* TODO: update compatible device tree */
static const struct udevice_id sh_spi_ids[] = {
- { .compatible = "sh,sh_spi" },
+ { .compatible = " " },
};
#endif
diff --git a/drivers/spi/sh_spi.h b/drivers/spi/sh_spi.h
index 87a253f..f945744 100644
--- a/drivers/spi/sh_spi.h
+++ b/drivers/spi/sh_spi.h
@@ -55,10 +55,6 @@ struct sh_spi_regs {
#define SH_SPI_FIFO_SIZE 32
#define SH_SPI_NUM_CS 4
-struct sh_spi_priv {
- struct sh_spi_regs *regs;
-};
-
static inline struct sh_spi *to_sh_spi(struct spi_slave *slave)
{
return container_of(slave, struct sh_spi, slave);
diff --git a/include/dm/platform_data/spi_sh.h
b/include/dm/platform_data/spi_sh.h
index b4d63dc..c6d0ac5 100644
--- a/include/dm/platform_data/spi_sh.h
+++ b/include/dm/platform_data/spi_sh.h
@@ -2,16 +2,11 @@
* Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
*
* SPDX-License-Identifier:GPL-2.0+
- *
*/
#ifndef __spi_sh_h
#define __spi_sh_h
-/*
- * struct sh_sp
[U-Boot] [PATCH v2 1/3] spi: sh_qspi: full DM conversion
v1->v2
New in v2
update Kconfig
replace __sh_qspi_setup to sh_qspi_setup
add missing memeber of platform data
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
drivers/spi/Kconfig| 12 +-
drivers/spi/sh_qspi.c | 49 +++---
include/dm/platform_data/qspi_sh.h | 4
3 files changed, 31 insertions(+), 34 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ec92b84..81079c5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -155,6 +155,12 @@ config SANDBOX_SPI
};
};
+config SH_QSPI
+ bool "Renesas Quad SPI driver"
+ help
+ Enable the Renesas Quad SPI controller driver. This driver can be
+ used on Renesas SoCs.
+
config STM32_QSPI
bool "STM32F7 QSPI driver"
depends on STM32F7
@@ -259,12 +265,6 @@ config SH_SPI
Enable the SuperH SPI controller driver. This driver can be used
on various SuperH SoCs, such as SH7757.
-config SH_QSPI
- bool "Renesas Quad SPI driver"
- help
- Enable the Renesas Quad SPI controller driver. This driver can be
- used on Renesas SoCs.
-
config TI_QSPI
bool "TI QSPI driver"
help
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 5fdd52e..b81cee5 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -77,49 +77,48 @@ struct sh_qspi_priv {
struct sh_qspi_regs *regs;
};
-static int __sh_qspi_setup(struct sh_qspi_priv *priv)
+static void sh_qspi_setup(struct sh_qspi_priv *priv)
{
- /* QSPI initialize */
- priv->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
+ struct sh_qspi_regs *regs = priv->regs;
/* Set master mode only */
- writeb(SPCR_MSTR, >regs->spcr);
+ writeb(SPCR_MSTR, >spcr);
/* Set SSL signal level */
- writeb(0x00, >regs->sslp);
+ writeb(0x00, >sslp);
/* Set MOSI signal value when transfer is in idle state */
- writeb(SPPCR_IO3FV | SPPCR_IO2FV, >regs->sppcr);
+ writeb(SPPCR_IO3FV | SPPCR_IO2FV, >sppcr);
/* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
- writeb(0x01, >regs->spbr);
+ writeb(0x01, >spbr);
/* Disable Dummy Data Transmission */
- writeb(0x00, >regs->spdcr);
+ writeb(0x00, >spdcr);
/* Set clock delay value */
- writeb(0x00, >regs->spckd);
+ writeb(0x00, >spckd);
/* Set SSL negation delay value */
- writeb(0x00, >regs->sslnd);
+ writeb(0x00, >sslnd);
/* Set next-access delay value */
- writeb(0x00, >regs->spnd);
+ writeb(0x00, >spnd);
/* Set equence command */
- writew(SPCMD_INIT2, >regs->spcmd0);
+ writew(SPCMD_INIT2, >spcmd0);
/* Reset transfer and receive Buffer */
- setbits_8(>regs->spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
+ setbits_8(>spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
/* Clear transfer and receive Buffer control bit */
- clrbits_8(>regs->spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
+ clrbits_8(>spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
/* Set equence control method. Use equence0 only */
- writeb(0x00, >regs->spscr);
+ writeb(0x00, >spscr);
/* Enable SPI function */
- setbits_8(>regs->spcr, SPCR_SPE);
+ setbits_8(>spcr, SPCR_SPE);
}
static int sh_qspi_set_speed(struct udevice *bus, uint hz)
@@ -156,7 +155,7 @@ static int sh_qspi_xfer(struct udevice *dev, unsigned int
bitlen,
if (dout == NULL && din == NULL) {
if (flags & SPI_XFER_END)
- spi_cs_deactivate(regs);
+ spi_cs_deactivate(regs);/* TODO */
return 0;
}
@@ -168,7 +167,7 @@ static int sh_qspi_xfer(struct udevice *dev, unsigned int
bitlen,
nbyte = bitlen / 8;
if (flags & SPI_XFER_BEGIN) {
- spi_cs_activate(regs);
+ spi_cs_activate(regs); /* TODO */
/* Set 1048576 byte */
writel(0x10, spbmul0);
@@ -219,7 +218,7 @@ static int sh_qspi_xfer(struct udevice *dev, unsigned int
bitlen,
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(regs);
+ spi_cs_deactivate(regs);/* TODO */
return ret;
}
@@ -229,7 +228,9 @@ static int sh_qspi_probe(struct udevice *bus)
struct sh_qspi_platdata *plat = bus->platdata;
struct sh_qspi_priv *priv = dev_get_priv(bus);
- __sh_qspi_setup(priv);
+ priv->regs = plat->regs;
+
+ sh_qspi_setup(priv);
return 0;
}
@@ -252,14 +253,14 @@ static int sh_qspi_ofdata_to_platadata(struct udevice
[U-Boot] [PATCH v1 2/3] spi: sh_spi: DM conversion
This patch adds support for DM to the sh_spi driver. legacy driver support is
removed.
Some TODOs are left over for later, These would be enhancements to the
original functionality, and can come later. The legacy functionality is
removed in this version.
This patch is not tested on board as well compile tested yet.
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
drivers/spi/Kconfig | 12 +--
drivers/spi/sh_spi.c | 214 +-
drivers/spi/sh_spi.h | 3 +-
include/dm/platform_data/spi_sh.h | 20
4 files changed, 147 insertions(+), 102 deletions(-)
create mode 100644 include/dm/platform_data/spi_sh.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ec92b84..be6ad22 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -155,6 +155,12 @@ config SANDBOX_SPI
};
};
+config SH_SPI
+ bool "SuperH SPI driver"
+ help
+ Enable the SuperH SPI controller driver. This driver can be used
+ on various SuperH SoCs, such as SH7757.
+
config STM32_QSPI
bool "STM32F7 QSPI driver"
depends on STM32F7
@@ -253,12 +259,6 @@ config DAVINCI_SPI
help
Enable the Davinci SPI driver
-config SH_SPI
- bool "SuperH SPI driver"
- help
- Enable the SuperH SPI controller driver. This driver can be used
- on various SuperH SoCs, such as SH7757.
-
config SH_QSPI
bool "Renesas Quad SPI driver"
help
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
index fe394e3..b308ec8 100644
--- a/drivers/spi/sh_spi.c
+++ b/drivers/spi/sh_spi.c
@@ -1,6 +1,10 @@
/*
* SH SPI driver
*
+ * Support for device model:
+ * Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
+ * Harshit Shah <shahharsh...@gmail.com>
+ *
* Copyright (C) 2011-2012 Renesas Solutions Corp.
*
* SPDX-License-Identifier:GPL-2.0
@@ -11,6 +15,8 @@
#include
#include
#include
+#include
+#include
#include "sh_spi.h"
static void sh_spi_write(unsigned long data, unsigned long *reg)
@@ -41,15 +47,15 @@ static void sh_spi_clear_bit(unsigned long val, unsigned
long *reg)
sh_spi_write(tmp, reg);
}
-static void clear_fifo(struct sh_spi *ss)
+static void clear_fifo(struct sh_spi_regs *regs)
{
- sh_spi_set_bit(SH_SPI_RSTF, >regs->cr2);
- sh_spi_clear_bit(SH_SPI_RSTF, >regs->cr2);
+ sh_spi_set_bit(SH_SPI_RSTF, >cr2);
+ sh_spi_clear_bit(SH_SPI_RSTF, >cr2);
}
-static int recvbuf_wait(struct sh_spi *ss)
+static int recvbuf_wait(struct sh_spi_regs *regs)
{
- while (sh_spi_read(>regs->cr1) & SH_SPI_RBE) {
+ while (sh_spi_read(>cr1) & SH_SPI_RBE) {
if (ctrlc())
return 1;
udelay(10);
@@ -57,9 +63,9 @@ static int recvbuf_wait(struct sh_spi *ss)
return 0;
}
-static int write_fifo_empty_wait(struct sh_spi *ss)
+static int write_fifo_empty_wait(struct sh_spi_regs *regs)
{
- while (!(sh_spi_read(>regs->cr1) & SH_SPI_TBE)) {
+ while (!(sh_spi_read(>cr1) & SH_SPI_TBE)) {
if (ctrlc())
return 1;
udelay(10);
@@ -67,11 +73,7 @@ static int write_fifo_empty_wait(struct sh_spi *ss)
return 0;
}
-void spi_init(void)
-{
-}
-
-static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
+static void sh_spi_set_cs(struct sh_spi_regs *regs, unsigned int cs)
{
unsigned long val = 0;
@@ -80,85 +82,53 @@ static void sh_spi_set_cs(struct sh_spi *ss, unsigned int
cs)
if (cs & 0x02)
val |= SH_SPI_SSS1;
- sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, >regs->cr4);
- sh_spi_set_bit(val, >regs->cr4);
+ sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, >cr4);
+ sh_spi_set_bit(val, >cr4);
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static void __spi_setup(struct sh_spi_regs *regs, uint cs)
{
- struct sh_spi *ss;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- ss = spi_alloc_slave(struct sh_spi, bus, cs);
- if (!ss)
- return NULL;
-
- ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
-
+ /* initialize spi */
+ regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
/* SPI sycle stop */
- sh_spi_write(0xfe, >regs->cr1);
+ sh_spi_write(0xfe, >cr1);
/* CR1 init */
- sh_spi_write(0x00, >regs->cr1);
+ sh_spi_write(0x00, >cr1);
/* CR3 init */
- sh_spi_write(0x00, >regs->cr3);
- sh_spi_set_cs(ss, cs);
+ sh_spi_write(0x00, >cr3);
+ sh_spi_set_cs(regs, cs);
- clear_fifo(ss);
+ clear_fif
[U-Boot] [PATCH v1 3/3] spi: mxs_spi: DM conversion
This patch adds support for DM to the mxs spi driver.
Some TODOs are left over for later, These would be enhancements to the
original functionality, and can come later.
The legacy functionality is present in this version, so old boards in the tree
is working with legacy SPI driver functionality.
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
drivers/spi/Kconfig| 12 +-
drivers/spi/mxs_spi.c | 257 +++--
include/dm/platform_data/spi_mxs.h | 18 +++
3 files changed, 186 insertions(+), 101 deletions(-)
create mode 100644 include/dm/platform_data/spi_mxs.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ec92b84..5d3e152 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -106,6 +106,12 @@ config MVEBU_A3700_SPI
used to access the SPI NOR flash on platforms embedding this
Marvell IP core.
+config MXS_SPI
+ bool "MXS SPI Driver"
+ help
+ Enable the MXS SPI controller driver. This driver can be used
+ on the i.MX23 and i.MX28 SoCs.
+
config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32
@@ -299,12 +305,6 @@ config MXC_SPI
Enable the MXC SPI controller driver. This driver can be used
on various i.MX SoCs such as i.MX31/35/51/6/7.
-config MXS_SPI
- bool "MXS SPI Driver"
- help
- Enable the MXS SPI controller driver. This driver can be used
- on the i.MX23 and i.MX28 SoCs.
-
config OMAP3_SPI
bool "McSPI driver for OMAP"
help
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 790db78..b48ecbf 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -1,6 +1,9 @@
/*
* Freescale i.MX28 SPI driver
*
+ * Support for device model:
+ * Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
+ *
* Copyright (C) 2011 Marek Vasut <marek.va...@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
@@ -20,6 +23,8 @@
#include
#include
#include
+#include
+#include
#defineMXS_SPI_MAX_TIMEOUT 100
#defineMXS_SPI_PORT_OFFSET 0x2000
@@ -28,93 +33,14 @@
#define MXSSSP_SMALL_TRANSFER 512
-struct mxs_spi_slave {
- struct spi_slaveslave;
- uint32_tmax_khz;
- uint32_tmode;
- struct mxs_ssp_regs *regs;
+struct mxs_spi_priv {
+ struct mxs_ssp_regs *regs;
+ u32 max_khz;
+ u32 mode;
+ u32 bus;
+ u32 cs;
};
-static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct mxs_spi_slave, slave);
-}
-
-void spi_init(void)
-{
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- /* MXS SPI: 4 ports and 3 chip selects maximum */
- if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
- return 0;
- else
- return 1;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct mxs_spi_slave *mxs_slave;
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
- return NULL;
- }
-
- mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
- if (!mxs_slave)
- return NULL;
-
- if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
- goto err_init;
-
- mxs_slave->max_khz = max_hz / 1000;
- mxs_slave->mode = mode;
- mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
-
- return _slave->slave;
-
-err_init:
- free(mxs_slave);
- return NULL;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- free(mxs_slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
- uint32_t reg = 0;
-
- mxs_reset_block(_regs->hw_ssp_ctrl0_reg);
-
- writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
- SSP_CTRL0_BUS_WIDTH_ONE_BIT,
- _regs->hw_ssp_ctrl0);
-
- reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
- reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
- reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
- writel(reg, _regs->hw_ssp_ctrl1);
-
- writel(0, _regs->hw_ssp_cmd0);
-
- mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
{
writel(SSP_CTRL0_LOCK_CS, _regs->hw_ssp_ctrl0
[U-Boot] [PATCH v1 1/3] spi: sh_qspi: DM conversion
This patch adds support for DM to the sh_qspi SPI driver.
The legacy functionality is removed in this version, so old boards in
the tree is not working with legacy SPI driver functionality.
Some TODOs are left over for later, These would be enhancements to the
original functionality, and can come later.
This patch is not tested on board as well compile tested yet.
Signed-off-by: Akash Gajjar <ak...@openedev.com>
---
drivers/spi/sh_qspi.c | 199 ++---
include/dm/platform_data/qspi_sh.h | 20
2 files changed, 119 insertions(+), 100 deletions(-)
create mode 100644 include/dm/platform_data/qspi_sh.h
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 5075be3..5fdd52e 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -1,6 +1,10 @@
/*
* SH QSPI (Quad SPI) driver
*
+ * Support for device model:
+ * Copyright (C) 2018 Akash Gajjar <ak...@openedev.com>
+ * Harshit Shah <shahharsh...@gmail.com>
+ *
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu...@renesas.com>
*
@@ -14,6 +18,8 @@
#include
#include
#include
+#include
+#include
/* SH QSPI register bit masks _ */
#define SPCR_MSTR 0x08
@@ -67,151 +73,90 @@ struct sh_qspi_regs {
u32 spbmul3;
};
-struct sh_qspi_slave {
- struct spi_slaveslave;
- struct sh_qspi_regs *regs;
+struct sh_qspi_priv {
+ struct sh_qspi_regs *regs;
};
-static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
-{
- return container_of(slave, struct sh_qspi_slave, slave);
-}
-
-static void sh_qspi_init(struct sh_qspi_slave *ss)
+static int __sh_qspi_setup(struct sh_qspi_priv *priv)
{
/* QSPI initialize */
+ priv->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
+
/* Set master mode only */
- writeb(SPCR_MSTR, >regs->spcr);
+ writeb(SPCR_MSTR, >regs->spcr);
/* Set SSL signal level */
- writeb(0x00, >regs->sslp);
+ writeb(0x00, >regs->sslp);
/* Set MOSI signal value when transfer is in idle state */
- writeb(SPPCR_IO3FV|SPPCR_IO2FV, >regs->sppcr);
+ writeb(SPPCR_IO3FV | SPPCR_IO2FV, >regs->sppcr);
/* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
- writeb(0x01, >regs->spbr);
+ writeb(0x01, >regs->spbr);
/* Disable Dummy Data Transmission */
- writeb(0x00, >regs->spdcr);
+ writeb(0x00, >regs->spdcr);
/* Set clock delay value */
- writeb(0x00, >regs->spckd);
+ writeb(0x00, >regs->spckd);
/* Set SSL negation delay value */
- writeb(0x00, >regs->sslnd);
+ writeb(0x00, >regs->sslnd);
/* Set next-access delay value */
- writeb(0x00, >regs->spnd);
+ writeb(0x00, >regs->spnd);
/* Set equence command */
- writew(SPCMD_INIT2, >regs->spcmd0);
+ writew(SPCMD_INIT2, >regs->spcmd0);
/* Reset transfer and receive Buffer */
- setbits_8(>regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
+ setbits_8(>regs->spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
/* Clear transfer and receive Buffer control bit */
- clrbits_8(>regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
+ clrbits_8(>regs->spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
/* Set equence control method. Use equence0 only */
- writeb(0x00, >regs->spscr);
+ writeb(0x00, >regs->spscr);
/* Enable SPI function */
- setbits_8(>regs->spcr, SPCR_SPE);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct sh_qspi_slave *ss = to_sh_qspi(slave);
-
- /* Set master mode only */
- writeb(SPCR_MSTR, >regs->spcr);
-
- /* Set command */
- writew(SPCMD_INIT1, >regs->spcmd0);
-
- /* Reset transfer and receive Buffer */
- setbits_8(>regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
-
- /* Clear transfer and receive Buffer control bit */
- clrbits_8(>regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
-
- /* Set equence control method. Use equence0 only */
- writeb(0x00, >regs->spscr);
-
- /* Enable SPI function */
- setbits_8(>regs->spcr, SPCR_SPE);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct sh_qspi_slave *ss = to_sh_qspi(slave);
-
- /* Disable SPI Function */
- clrbits_8(>regs->spcr, SPCR_SPE);
-}
-
-void spi_init(void)
-{
- /* nothing to do */
+ setbits_8(>regs->spcr, SPCR_SPE);
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int sh_qspi_
Re: [U-Boot] [PATCH v2 2/3] spi: davinci: Full dm conversion
Hi Jagan,
> +#if CONFIG_IS_ENABLED(OF_CONTROL)
> static int davinci_ofdata_to_platadata(struct udevice *bus)
> {
> - struct davinci_spi_slave *ds = dev_get_priv(bus);
> - const void *blob = gd->fdt_blob;
> - int node = dev_of_offset(bus);
> + struct davinci_spi_platdata *plat = bus->platdata;
> + fdt_addr_t addr;
>
> - ds->regs = devfdt_map_physmem(bus, sizeof(struct
> davinci_spi_regs));
> - if (!ds->regs) {
> - printf("%s: could not map device address\n", __func__);
> + addr = devfdt_get_addr(bus);
> + if (addr == FDT_ADDR_T_NONE)
> return -EINVAL;
> - }
> - ds->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
> +
> + plat->regs = (struct davinci_spi_regs *)addr;
> + plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
> "num-cs", 4);
>
> return 0;
> }
> @@ -566,14 +426,17 @@ static const struct udevice_id davinci_spi_ids[] = {
> { .compatible = "ti,da830-spi" },
> { }
> };
> +#endif
>
> U_BOOT_DRIVER(davinci_spi) = {
> .name = "davinci_spi",
> .id = UCLASS_SPI,
> +#if CONFIG_IS_ENABLED(OF_CONTROL)
> .of_match = davinci_spi_ids,
> - .ops = _spi_ops,
> .ofdata_to_platdata = davinci_ofdata_to_platadata,
> - .priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
> +.platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata),
> +#endif
> .probe = davinci_spi_probe,
> + .ops = _spi_ops,
>
In this patch definition of davinci_spi_ops is being guarded by OF_CONTROL,
It should be out side of OF_CONTROL.
> + .priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
> };
>
>
Thanks,
Akash
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH RFC] spi: mxs spi: DM conversion
This is to announce that I have started working on DM driver support for
mxs spi driver that adds basic skeleton of DM driver functionality along with
legacy driver support.
This is compilation tested only.
Signed-off-by: Akash Gajjar <gajjar04ak...@gmail.com>
---
drivers/spi/mxs_spi.c | 74 +++
1 file changed, 74 insertions(+)
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 790db78..94e9ab3 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -20,6 +20,9 @@
#include
#include
#include
+#ifdef CONFIG_DM_SPI
+#include
+#endif
#defineMXS_SPI_MAX_TIMEOUT 100
#defineMXS_SPI_PORT_OFFSET 0x2000
@@ -361,3 +364,74 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
}
}
+
+#ifdef CONFIG_DM_SPI
+struct mxs_spi_priv {
+ struct spi_slaveslave;
+ struct mxs_ssp_regs *regs;
+ u32 max_khz;
+ u32 mode;
+};
+
+struct mxs_spi_platdata {
+ struct spi_slaveslave;
+ struct mxs_ssp_regs *regs;
+ u32 bus;
+};
+
+static int mxs_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct mxs_spi_platdata *plat = dev_get_platdata(bus);
+ struct mxs_ssp_regs *ssp_regs = plat->regs;
+ u32 reg = 0;
+
+ writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
+ SSP_CTRL0_BUS_WIDTH_ONE_BIT,
+ _regs->hw_ssp_ctrl0);
+
+ return 0;
+}
+
+static int mxs_spi_release_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ return 0;
+}
+
+static int mxs_spi_set_speed(struct udevice *bus, uint speed)
+{
+ return 0;
+}
+
+static int mxs_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static int mxs_spi_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct dm_spi_ops mxs_spi_ops = {
+ .claim_bus = mxs_spi_claim_bus,
+ .release_bus= mxs_spi_release_bus,
+ .xfer = mxs_spi_xfer,
+ .set_speed = mxs_spi_set_speed,
+ .set_mode = mxs_spi_set_mode,
+};
+
+U_BOOT_DRIVER(mxs_spi) = {
+ .name = "mxs_spi",
+ .id = UCLASS_SPI,
+ .ops= _spi_ops,
+ .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
+ .probe = mxs_spi_probe,
+};
+#endif
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH RFC] spi: mxs spi: DM conversion
This is to announce that I have started working on DM driver support for
mxs spi driver that adds basic skeleton of DM driver functionality along with
legacy driver support.
This is compilation tested only.
Signed-off-by: Akash Gajjar <gajjar04ak...@gmail.com>
---
drivers/spi/mxs_spi.c | 144 ++
1 file changed, 144 insertions(+)
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 790db78..ef970c0 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -20,6 +20,9 @@
#include
#include
#include
+#ifdef CONFIG_DM_SPI
+#include
+#endif
#defineMXS_SPI_MAX_TIMEOUT 100
#defineMXS_SPI_PORT_OFFSET 0x2000
@@ -361,3 +364,144 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
}
}
+
+#ifdef CONFIG_DM_SPI
+struct mxs_spi_priv {
+ struct spi_slaveslave;
+ uint32_tmax_khz;
+ uint32_tmode;
+ struct mxs_ssp_regs *regs;
+};
+
+struct mxs_spi_platdata {
+ struct spi_slaveslave;
+ uint32_tbus;
+ struct mxs_ssp_regs *regs;
+};
+
+/* review */
+static int mxs_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct mxs_spi_platdata *plat = dev_get_platdata(bus);
+ struct mxs_ssp_regs *ssp_regs = plat->regs;
+ uint32_t reg = 0;
+
+ writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
+ SSP_CTRL0_BUS_WIDTH_ONE_BIT,
+ _regs->hw_ssp_ctrl0);
+
+ return 0;
+}
+
+static int mxs_spi_release_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+/* review */
+static int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct mxs_spi_platdata *plat = dev_get_platdata(bus);
+ struct mxs_ssp_regs *ssp_regs = plat->regs;
+ int len = bitlen / 8;
+ char dummy;
+ int write = 0;
+ char *data = NULL;
+ int dma = 1;
+
+ if (bitlen == 0) {
+ if (flags & SPI_XFER_END) {
+ din = (void *)
+ len = 1;
+ } else
+ return 0;
+ }
+
+ /* Half-duplex only */
+ if (din && dout)
+ return -EINVAL;
+ /* No data */
+ if (!din && !dout)
+ return 0;
+
+ if (dout) {
+ data = (char *)dout;
+ write = 1;
+ } else if (din) {
+ data = (char *)din;
+ write = 0;
+ }
+
+ /*
+* Check for alignment, if the buffer is aligned, do DMA transfer,
+* PIO otherwise. This is a temporary workaround until proper bounce
+* buffer is in place.
+*/
+ if (dma) {
+ if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
+ dma = 0;
+ if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
+ dma = 0;
+ }
+
+ if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
+ writel(SSP_CTRL1_DMA_ENABLE, _regs->hw_ssp_ctrl1_clr);
+ return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
+ } else {
+ writel(SSP_CTRL1_DMA_ENABLE, _regs->hw_ssp_ctrl1_set);
+ return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
+ }
+
+ return 0;
+}
+
+static int mxs_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct mxs_spi_platdata *plat = dev_get_platdata(bus);
+
+ debug("%s mode %u\n", __func__, mode);
+ priv->max_khz = speed;
+
+ return 0;
+}
+
+static int mxs_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct mxs_spi_priv *priv = dev_get_priv(bus);
+
+ debug("%s mode %u\n", __func__, mode);
+ priv->mode = mode;
+
+ return 0;
+}
+
+static int mxs_spi_probe(struct udevice *dev)
+{
+ struct mxs_spi_platdata *plat = dev_get_platdata(dev);
+ struct mxs_spi_priv *priv;
+
+
+ priv->regs = mxs_ssp_regs_by_bus(plat->bus);
+
+ return 0;
+}
+
+static const struct dm_spi_ops mxs_spi_ops = {
+ .claim_bus = mxs_spi_claim_bus,
+ .release_bus= mxs_spi_release_bus,
+ .xfer = mxs_spi_xfer,
+ .set_speed = mxs_spi_set_speed,
+ .set_mode = mxs_spi_set_mode,
+};
+
+U_BOOT_DRIVER(mxs_spi) = {
+ .name = "mxs_spi",
+ .id = UCLASS_SPI,
+ .ops= _spi_ops,
+ .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
+ .probe = mxs_spi_probe,
+};
+#endif
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] compilation issue pine64
Thank you Peter, The issue was there because of an older version of gcc. Now it has been resolved. Thank you once again. On Thu, Jan 11, 2018 at 7:33 AM, Peter Robinson <pbrobin...@gmail.com> wrote: > On Wed, Jan 10, 2018 at 3:58 PM, Akash Gajjar <gajjar04ak...@gmail.com> > wrote: > > Hi All, > > > > Facing compilation issue building pine64 mainline u-boot. > > Please see below build log. > > > > user]$ export CROSS_COMPILE=aarch64-linux-gnu- > > > > user]$ make pine64_plus_defconfig > > HOSTCC scripts/basic/fixdep > > HOSTCC scripts/kconfig/conf.o > > HOSTCC scripts/kconfig/zconf.tab.o > > HOSTLD scripts/kconfig/conf > > # > > # configuration written to .config > > # > > > > user]$ make > > . > > . > > . > > LDS spl/u-boot-spl.lds > > LD spl/u-boot-spl > > aarch64-linux-gnu-ld.bfd: u-boot-spl section `.rodata' will not fit in > > region `.sram' > > aarch64-linux-gnu-ld.bfd: region `.sram' overflowed by 6032 bytes > > make[1]: *** [spl/u-boot-spl] Error 1 > > make: *** [spl/u-boot-spl] Error 2 > > It works fine for me on Fedora 27 with gcc 7.2.1 on both the latest > master head and 2018.01 GA > > mkdir -p builds/pine64_plus/ > cp ~/arm-trusted-firmware/sun50iw1p1/bl31.bin builds/pine64_plus/ > make pine64_plus_defconfig V=1 O=builds/pine64_plus/ > make CROSS_COMPILE="/usr/bin/aarch64-linux-gnu-" V=1 O=builds/pine64_plus/ > -- Regards, *Akash Gajjar* Mobile: 9724719708 Skype: gajjar04akash ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] compilation issue pine64
Hi All, Facing compilation issue building pine64 mainline u-boot. Please see below build log. user]$ export CROSS_COMPILE=aarch64-linux-gnu- user]$ make pine64_plus_defconfig HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o HOSTCC scripts/kconfig/zconf.tab.o HOSTLD scripts/kconfig/conf # # configuration written to .config # user]$ make . . . LDS spl/u-boot-spl.lds LD spl/u-boot-spl aarch64-linux-gnu-ld.bfd: u-boot-spl section `.rodata' will not fit in region `.sram' aarch64-linux-gnu-ld.bfd: region `.sram' overflowed by 6032 bytes make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 ** - *Akash Gajjar* ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
