[U-Boot] [PATCH] pcm052: fix DDR initialization sequence
The sequence erroneously launched the DDR controller initialization before the pad muxing was done, causing DRAM size computation to hang. Configuring the pads first then launching DDR controller initialization prevents the DRAM hanging. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr> --- board/phytec/pcm052/pcm052.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index e75ff4fc3a..54a4e4f9c3 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -258,8 +258,7 @@ int dram_init(void) .wldqsen = 25, }; - ddrmc_ctrl_init_ddr3(_ddr_timings, pcm052_cr_settings, -pcm052_phy_settings, 1, 2); +const int row_diff = 2; #elif defined(CONFIG_TARGET_BK4R1) @@ -314,8 +313,7 @@ int dram_init(void) .wldqsen = 25, }; - ddrmc_ctrl_init_ddr3(_ddr_timings, pcm052_cr_settings, -pcm052_phy_settings, 1, 1); +const int row_diff = 1; #else /* Unknown PCM052 variant */ @@ -325,6 +323,9 @@ int dram_init(void) imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); + ddrmc_ctrl_init_ddr3(_ddr_timings, pcm052_cr_settings, +pcm052_phy_settings, 1, row_diff); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/6] Add support for the BK4R1 variant of PCM052
BK4R1 is basically PCM052 with the following differences or quirks: 1) it has 512MB of DDR using MT41K256M16HA_125IT, while the PCM052 has 256MB using MT41J128M16HA_15EIT; 2) it has 1GB of NAND. The size increase is supported by the env directly; 3) its Ethernet ports are physicaly tied together until GPIO 122 is raised. As this is a safety feature U-Boot does not untie the ports except if it needs networking, for instance when doing NAND updates via TFTP; 4) it has a USB hub which may remain in reset if GPIO 130 is not raised. This is done unconditionally at boot; 5) It has two NOR SPI flash chips on QSPI. This series has been run through checkpatch and has no errors or warning except the following one: warning: arch/arm/Kconfig,681: please write a paragraph that describes the config symbol fully Which I believe does not apply, as target configs in this file never have descriptions. Albert ARIBAUD (3ADEV) (6): pcm052: fix MTD partitioning pcm052: remove target-specific dtb name from env pcm052: add 'm4go' command tools: mkimage: add support for Vybrid image format pcm052: allow specifying onboard DDR size in configs pcm052: add new BK4r1 target based on PCM052 SoM Makefile | 6 ++ arch/arm/Kconfig | 4 + arch/arm/config.mk| 3 + arch/arm/cpu/armv7/vf610/Makefile | 5 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/bk4r1.dts| 48 + arch/arm/dts/vf.dtsi | 4 +- board/phytec/pcm052/Kconfig | 24 + board/phytec/pcm052/pcm052.c | 206 -- common/image.c| 1 + configs/bk4r1_defconfig | 32 ++ include/configs/bk4r1.h | 33 ++ include/configs/pcm052.h | 78 ++- include/image.h | 1 + tools/Makefile| 1 + tools/vybridimage.c | 164 ++ 16 files changed, 535 insertions(+), 78 deletions(-) create mode 100644 arch/arm/dts/bk4r1.dts create mode 100644 configs/bk4r1_defconfig create mode 100644 include/configs/bk4r1.h create mode 100644 tools/vybridimage.c -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/6] pcm052: add new BK4r1 target based on PCM052 SoM
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr>
---
arch/arm/Kconfig | 4 ++
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/bk4r1.dts | 48 +
arch/arm/dts/vf.dtsi | 4 +-
board/phytec/pcm052/Kconfig | 20 ++
board/phytec/pcm052/pcm052.c | 168 +--
configs/bk4r1_defconfig | 32 +
include/configs/bk4r1.h | 33 +
include/configs/pcm052.h | 45 ++--
9 files changed, 297 insertions(+), 60 deletions(-)
create mode 100644 arch/arm/dts/bk4r1.dts
create mode 100644 configs/bk4r1_defconfig
create mode 100644 include/configs/bk4r1.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0083bf9..3c2d33a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -678,6 +678,10 @@ config TARGET_PCM052
bool "Support pcm-052"
select CPU_V7
+config TARGET_BK4R1
+ bool "Support BK4r1"
+ select CPU_V7
+
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
select CPU_V7
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index df57288..3e3b5c3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -274,7 +274,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \
dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-colibri.dtb \
vf610-twr.dtb \
- pcm052.dtb
+ pcm052.dtb \
+ bk4r1.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
k2l-evm.dtb \
diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts
new file mode 100644
index 000..197e5ab
--- /dev/null
+++ b/arch/arm/dts/bk4r1.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "vf.dtsi"
+
+/ {
+ model = "Phytec phyCORE-Vybrid";
+ compatible = "phytec,pcm052", "fsl,vf610";
+
+ chosen {
+ stdout-path =
+ };
+
+ aliases {
+ spi0 =
+ };
+
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ bus-num = <0>;
+ num-cs = <2>;
+ status = "okay";
+
+ qflash0: spi_flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <10800>;
+ reg = <0>;
+ };
+
+ qflash1: spi_flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <6600>;
+ reg = <1>;
+ };
+};
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index 1530d2f..404dfe9 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -80,7 +80,9 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
- reg = <0x40044000 0x1000>;
+ reg = <0x40044000 0x1000>,
+ <0x2000 0x1000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
status = "disabled";
};
diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig
index 88524a3..212f994 100644
--- a/board/phytec/pcm052/Kconfig
+++ b/board/phytec/pcm052/Kconfig
@@ -17,3 +17,23 @@ config PCM052_DDR_SIZE
default 256
endif
+
+if TARGET_BK4R1
+
+config SYS_BOARD
+ default "pcm052"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_SOC
+ default "vf610"
+
+config SYS_CONFIG_NAME
+ default "bk4r1"
+
+config PCM052_DDR_SIZE
+ int
+ default 512
+
+endif
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index 7341899..e75ff4f 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -152,57 +152,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = {
int dram_init(void)
{
- static const struct ddr3_jedec_timings pcm052_ddr_timings = {
- .tinit = 5,
- .trst_pwron= 8,
- .cke_inactive = 20,
- .wrlat = 5,
- .caslat_lin= 12,
- .trc = 6,
- .trrd = 4,
- .tccd = 4,
- .tbst_int_interval = 4,
- .tfaw = 18,
- .trp = 6,
- .twtr = 4,
- .tras_min = 15,
- .tmrd = 4,
- .trtp = 4
[U-Boot] [PATCH 4/6] tools: mkimage: add support for Vybrid image format
This format can be flashed directly at address 0 of
the NAND FLASH, as it contains all necessary headers.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr>
---
Makefile | 6 ++
arch/arm/config.mk| 3 +
arch/arm/cpu/armv7/vf610/Makefile | 5 ++
common/image.c| 1 +
include/configs/pcm052.h | 14 ++--
include/image.h | 1 +
tools/Makefile| 1 +
tools/vybridimage.c | 164 ++
8 files changed, 187 insertions(+), 8 deletions(-)
create mode 100644 tools/vybridimage.c
diff --git a/Makefile b/Makefile
index c30f90a..75c74d5 100644
--- a/Makefile
+++ b/Makefile
@@ -844,6 +844,12 @@ endif
%.imx: %.bin
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+%.vyb: %.imx
+ $(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
+
+quiet_cmd_copy = COPY$@
+ cmd_copy = cp $< $@
+
u-boot.dtb: dts/dt.dtb
$(call cmd,copy)
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 8f85862..542b897 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -144,4 +144,7 @@ else
ALL-y += u-boot.imx
endif
endif
+ifneq ($(CONFIG_VF610),)
+ALL-y += u-boot.vyb
+endif
endif
diff --git a/arch/arm/cpu/armv7/vf610/Makefile
b/arch/arm/cpu/armv7/vf610/Makefile
index 68cb756..2945377 100644
--- a/arch/arm/cpu/armv7/vf610/Makefile
+++ b/arch/arm/cpu/armv7/vf610/Makefile
@@ -6,3 +6,8 @@
obj-y += generic.o
obj-y += timer.o
+
+MKIMAGEFLAGS_u-boot.vyb = -T vybridimage
+
+u-boot.vyb: u-boot.imx
+ $(call if_changed,mkimage)
diff --git a/common/image.c b/common/image.c
index a5d19ab..c0ad36a 100644
--- a/common/image.c
+++ b/common/image.c
@@ -161,6 +161,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_RKIMAGE,"rkimage","Rockchip Boot Image" },
{ IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" },
{ IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" },
+ { IH_TYPE_VYBRIDIMAGE, "vybridimage", "Vybrid Boot Image", },
{ IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" },
{ IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image"
},
{ IH_TYPE_FPGA, "fpga", "FPGA Image" },
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 1858662..cd235cc 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -120,9 +120,8 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x\0" \
"initrd_high=0x\0" \
- "blimg_file=u-boot.imx\0" \
- "blsec_addr=0x8100\0" \
- "blimg_addr=0x81000400\0" \
+ "blimg_file=u-boot.vyb\0" \
+ "blimg_addr=0x8100\0" \
"kernel_file=zImage\0" \
"kernel_addr=0x8200\0" \
"fdt_file=zImage.dtb\0" \
@@ -164,12 +163,11 @@
"nand read ${kernel_addr} kernel; " \
"nand read ${ram_addr} root; " \
"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
- "update_bootloader_from_tftp=mtdparts default; " \
- "nand read ${blsec_addr} bootloader; " \
- "mw.b ${blimg_addr} 0xff 0x5FC00; " \
- "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \
+ "update_bootloader_from_tftp=if tftp ${blimg_addr} "\
+ "${tftpdir}${blimg_file}; then " \
+ "mtdparts default; " \
"nand erase.part bootloader; " \
- "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \
+ "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
"${kernel_file}; " \
"then mtdparts default; " \
diff --git a/include/image.h b/include/image.h
index 64da722..2b1296c 100644
--- a/include/image.h
+++ b/include/image.h
@@ -278,6 +278,7 @@ enum {
IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */
IH_TYPE_ZYNQMPIMAGE,/* Xilinx ZynqMP Boot Image */
IH_TYPE_FPGA, /* FPGA Image */
+ IH_TYPE_VYBRIDIMAGE,/* VYBRID .vyb Image */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/tools/Makefile b/tools/Makefile
index 421414b..e6f7993 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -89,6 +89,7 @@ dumpimage-mkimage-objs := aisimage.o \
os_support.o \
pblimage.o \
[U-Boot] [PATCH 5/6] pcm052: allow specifying onboard DDR size in configs
PCM052 SoMs may be equipped with various sizes of DDR.
Keep default of 256MB; new PCM052-based targets will
specify their actual DDR size.
Linux command line is auto-adjusted to DDR size.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr>
---
board/phytec/pcm052/Kconfig | 4
include/configs/pcm052.h| 5 +++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig
index d67a69a..88524a3 100644
--- a/board/phytec/pcm052/Kconfig
+++ b/board/phytec/pcm052/Kconfig
@@ -12,4 +12,8 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "pcm052"
+config PCM052_DDR_SIZE
+ int
+ default 256
+
endif
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index cd235cc..b3e5054 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -135,7 +135,8 @@
"tftptimeout=1000\0" \
"tftptimeoutcountmax=100\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
- "bootargs_base=setenv bootargs rw mem=256M " \
+ "bootargs_base=setenv bootargs rw " \
+ " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \
"console=ttyLP1,115200n8\0" \
"bootargs_sd=setenv bootargs ${bootargs} " \
"root=/dev/mmcblk0p2 rootwait\0" \
@@ -219,7 +220,7 @@
/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM (0x8000)
-#define PHYS_SDRAM_SIZE(256 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE(CONFIG_PCM052_DDR_SIZE * 1024
* 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
--
2.9.3
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[U-Boot] [PATCH 2/6] pcm052: remove target-specific dtb name from env
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr> --- include/configs/pcm052.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 302c7dd..1858662 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -125,7 +125,7 @@ "blimg_addr=0x81000400\0" \ "kernel_file=zImage\0" \ "kernel_addr=0x8200\0" \ - "fdt_file=vf610-pcm052.dtb\0" \ + "fdt_file=zImage.dtb\0" \ "fdt_addr=0x8100\0" \ "ram_file=uRamdisk\0" \ "ram_addr=0x8300\0" \ -- 2.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/6] pcm052: add 'm4go' command
Add the 'm4go' command to pcm052-based targets.
It loads scatter file images.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr>
---
board/phytec/pcm052/pcm052.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index e4f61e1..7341899 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -513,3 +513,41 @@ int checkboard(void)
return 0;
}
+
+static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ ulong addr;
+
+ /* Consume 'm4go' */
+ argc--; argv++;
+
+ /*
+* Parse provided address - default to load_addr in case not provided.
+*/
+
+ if (argc)
+ addr = simple_strtoul(argv[0], NULL, 16);
+ else
+ addr = load_addr;
+
+ /*
+* Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0]
+*/
+ writel(addr + 0x401, 0x4006E028);
+
+ /*
+* Start secondary processor by enabling its clock
+*/
+ writel(0x15a5a, 0x4006B08C);
+
+ return 1;
+}
+
+U_BOOT_CMD(
+ m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go,
+ "start the secondary Cortex-M4 from scatter file image",
+ "[]\n"
+ "- start secondary Cortex-M4 core using a scatter file image\n"
+ "The argument needs to be a scatter file\n"
+);
--
2.9.3
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[U-Boot] [PATCH 1/6] pcm052: fix MTD partitioning
Merge 'spare' into 'bootloader' partition
Use same partition for ramdisk and rootfs boot scenarios.
Remove 'ramdisk' partition, use 'rootfs' for ramdisk
(ramdisk and nand boot scenarios are mutually exclusive).
Expand last partition to end of actual NAND size.
Adjust UBIFS rootfs boot kernel arguments.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr>
---
include/configs/pcm052.h | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 57a7630..302c7dd 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -54,14 +54,12 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define MTDIDS_DEFAULT "nand0=NAND"
-#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
- ",384k(bootloader)"\
+#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\
",128k(env1)"\
",128k(env2)"\
",128k(dtb)"\
",6144k(kernel)"\
- ",65536k(ramdisk)"\
- ",450944k(root)"
+ ",-(root)"
#endif
#define CONFIG_MMC
@@ -145,7 +143,7 @@
"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
"bootargs_nand=setenv bootargs ${bootargs} " \
- "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \
+ "ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
"bootargs_ram=setenv bootargs ${bootargs} " \
"root=/dev/ram rw initrd=${ram_addr}\0" \
"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
@@ -164,7 +162,7 @@
"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
"nand read ${fdt_addr} dtb; " \
"nand read ${kernel_addr} kernel; " \
- "nand read ${ram_addr} ramdisk; " \
+ "nand read ${ram_addr} root; " \
"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
"update_bootloader_from_tftp=mtdparts default; " \
"nand read ${blsec_addr} bootloader; " \
@@ -196,8 +194,8 @@
"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
"update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
"then mtdparts default; " \
- "nand erase.part ramdisk; " \
- "nand write ${ram_addr} ramdisk ${filesize}; fi\0"
+ "nand erase.part root; " \
+ "nand write ${ram_addr} root ${filesize}; fi\0"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP/* undef to save memory */
--
2.9.3
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Re: [U-Boot] [PATCH] mtd: nand: vf610_nfc: resync with upstream Linux version
Hello Stefan, On Tue, 13 Oct 2015 22:11:42 -0700, Stefan Agner <ste...@agner.ch> wrote: > This resyncs the driver changes with the Linux version of the > driver. The driver received some feedback in the LKML and got > recently acceppted, the latest version can be found here: > https://lkml.org/lkml/2015/9/2/678 > > Notable changes are: > - On ECC error, reread OOB and count bit flips in OOB too. > If flipped bits are below threshold, also return an empty > OOB buffer. > - Return the amount of bit flips in vf610_nfc_read_page. > - Use endianness aware vf610_nfc_read to read ECC status. > - Do not enable IDLE IRQ (since we do not operate with an > interrupt service routine). > - Use type safe struct for buffer variants (vf610_nfc_alt_buf). > - Renamed variables in struct vf610_nfc (column and page_sz) > to reflect better what they really representing. > > The U-Boot version currently does not support RAW NAND write > when using the HW ECC engine. > > Signed-off-by: Bhuvanchandra DV <bhuvanchandra...@toradex.com> > Signed-off-by: Stefan Agner <ste...@agner.ch> Tested-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr> Works on pcm052. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] pcm052: fix MTD partitioning
MTD partitioning in current pcm052 configuration is inconsistent.
Fix it across MTDPARTS_DEFAULT, CONFIG_EXTRA_ENV_SETTINGS, and
CONFIG_ENV_OFFSET[_REDUND].
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr>
---
include/configs/pcm052.h | 120 +--
1 file changed, 85 insertions(+), 35 deletions(-)
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 903f94c..150698e 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -60,14 +60,15 @@
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
-#define MTDIDS_DEFAULT "nand0=NAND,nor0=qspi0-a,nor1=qspi0-b"
+#define MTDIDS_DEFAULT "nand0=NAND"
#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
",384k(bootloader)"\
",128k(env1)"\
",128k(env2)"\
- ",3840k(kernel)"\
- ",-(rootfs)"\
- ",qspi0-a:-(jffs2),qspio0-b:-(jffs2)"
+ ",128k(dtb)"\
+ ",6144k(kernel)"\
+ ",65536k(ramdisk)"\
+ ",450944k(root)"
#endif
#define CONFIG_MMC
@@ -135,36 +136,85 @@
#define CONFIG_BOARD_SIZE_LIMIT524288
#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootfile=uImage\0" \
- "bootargs_base=setenv bootargs rw mem=256M "\
- "console=ttymxc1,115200n8\0"\
- "bootargs_sd=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p2 rootwait\0"\
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x\0" \
+ "initrd_high=0x\0" \
+ "blimg_file=u-boot.imx\0" \
+ "blsec_addr=0x8100\0" \
+ "blimg_addr=0x81000400\0" \
+ "kernel_file=zImage\0" \
+ "kernel_addr=0x8200\0" \
+ "fdt_file=vf610-pcm052.dtb\0" \
+ "fdt_addr=0x8100\0" \
+ "ram_file=uRamdisk\0" \
+ "ram_addr=0x8300\0" \
+ "filesys=rootfs.ubifs\0" \
+ "sys_addr=0x8100\0" \
+ "tftploc=/path/to/tftp/directory/\0" \
+ "nfs_root=/path/to/nfs/root\0" \
+ "tftptimeout=1000\0" \
+ "tftptimeoutcountmax=100\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "bootargs_base=setenv bootargs rw mem=256M " \
+ "console=ttyLP1,115200n8\0" \
+ "bootargs_sd=setenv bootargs ${bootargs} " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
- "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
- "bootargs_nand=setenv bootargs ${bootargs} "\
- "root=/dev/mtdblock2 rootfstype=jffs2\0"\
- "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0"\
- "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; mmc rescan; " \
- "fatload mmc 0:1 ${loadaddr} ${bootfile}; bootm ${loadaddr}\0" \
- "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
- "tftpboot ${loadaddr} ${tftploc}${bootfile}; bootm\0" \
- "bootcmd_nand='run bootargs_base bootargs_nand bootargs_mtd; " \
- "nand read ${loadaddr} 0x000E 0x3C; " \
- "bootm ${loadaddr}\0" \
- "tftploc=/path/to/tftp/directory/\0"\
- "nfs_root=/path/to/nfs/root\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "update_kernel_from_sd=mw.b $(loadaddr) 0xff 0x3C; "\
- "mmc rescan; fatload mmc 0:2 ${loadaddr} ${bootfile}; " \
- "nand erase 0xE 0x3C; " \
- "nand write.i ${loadaddr} 0xE 0x3C\0" \
- "update_rootfs_from_tftp=mw.b ${loadaddr} 0xff
[U-Boot] [PATCH v4] net: TFTP: variables cleanup and addition
TFTP source and destination port variable names are
'tftpsrcp' and 'tftpdstp' in the code, but 'tftpsrcport'
and 'tftpdstport' in the README file. Fix the README.
Add environment variable 'tftptimeoutcountmax'. As per the
comments about the global variable tftp_timeout_count_max,
make sure tftptimeoutcountmax is nonnegative.
Introduce configuration option CONFIG_NET_TFTP_VARS,
which controls whether environment variables tftpblocksize,
tftptimeout, and tftptimoueoutcountmax are read by the TFTP
client code. CONFIG_NET_TFTP_VARS defaults to y but can be
set to n by targets with to tight size contraints.
Make bf527-ezkit set CONFIG_NET_TFTP_VARS to n to keep the
target size below limit.
---
Changes in v4:
- fixed tftp{src,dst}port name typo in README
- added control option CONFIG_NET_TFTP_VARS (default y)
- made bf527-ezkit set option to n
Changes in v3:
- fixed mixup between tctp_timeout_count_max and timeout_count_max.
Changes in v2:
- fixed env var name in commit message
README| 12 ++--
configs/bf527-ezkit_defconfig | 1 +
net/Kconfig | 10 ++
net/tftp.c| 17 +++--
4 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/README b/README
index c22b60b..57f25eb 100644
--- a/README
+++ b/README
@@ -5456,10 +5456,10 @@ List of environment variables (most likely not
complete):
unset, then it will be made silent if the U-Boot console
is silent.
- tftpsrcport - If this is set, the value is used for TFTP's
+ tftpsrcp - If this is set, the value is used for TFTP's
UDP source port.
- tftpdstport - If this is set, the value is used for TFTP's UDP
+ tftpdstp - If this is set, the value is used for TFTP's UDP
destination port instead of the Well Know Port 69.
tftpblocksize - Block size to use for TFTP transfers; if not set,
@@ -5473,6 +5473,14 @@ List of environment variables (most likely not complete):
faster in networks with high packet loss rates or
with unreliable TFTP servers.
+ tftptimeoutcountmax - maximum count of TFTP timeouts (no
+ unit, minimum value = 0). Defines how many timeouts
+ can happen during a single file transfer before that
+ transfer is aborted. The default is 10, and 0 means
+ 'no timeouts allowed'. Increasing this value may help
+ downloads succeed with high packet loss rates, or with
+ unreliable TFTP servers or client hardware.
+
vlan - When set to a value < 4095 the traffic over
Ethernet is encapsulated/received over 802.1q
VLAN tagged frames.
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
index 2e75225..0cc81cc 100644
--- a/configs/bf527-ezkit_defconfig
+++ b/configs/bf527-ezkit_defconfig
@@ -4,3 +4,4 @@ CONFIG_TARGET_BF527_EZKIT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+CONFIG_NET_TFTP_VARS=n
diff --git a/net/Kconfig b/net/Kconfig
index 77a2f7e..a44a783 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -22,4 +22,14 @@ config NETCONSOLE
Support the 'nc' input/output device for networked console.
See README.NetConsole for details.
+config NET_TFTP_VARS
+ bool "Control TFTP timeout and count through environment"
+ default y
+ help
+ If set, allows controlling the TFTP timeout through the
+ environment variable tftptimeout, and the TFTP maximum
+ timeout count through the variable tftptimeoutcountmax.
+ If unset, timeout and maximum are hard-defined as 1 second
+ and 10 timouts per TFTP transfer.
+
endif # if NET
diff --git a/net/tftp.c b/net/tftp.c
index 1a51131..f2889fe 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -602,7 +602,7 @@ static void tftp_handler(uchar *pkt, unsigned dest, struct
in_addr sip,
}
tftp_prev_block = tftp_cur_block;
- timeout_count_max = TIMEOUT_COUNT;
+ timeout_count_max = tftp_timeout_count_max;
net_set_timeout_handler(timeout_ms, tftp_timeout_handler);
store_block(tftp_cur_block - 1, pkt + 2, len);
@@ -697,12 +697,14 @@ static void tftp_timeout_handler(void)
void tftp_start(enum proto_t protocol)
{
+#if CONFIG_NET_TFTP_VARS
char *ep; /* Environment pointer */
/*
* Allow the user to choose TFTP blocksize and timeout.
* TFTP protocol has a minimal timeout of 1 second.
*/
+
ep = getenv("tftpblocksize");
if (ep != NULL)
tftp_block_size_option = simple_strtol(ep, NULL, 10);
@@ -717,6 +719,17 @@ void tftp_start(enum proto_t protocol)
timeout_ms = 1000;
}
+ ep = getenv("tftptimeoutcountmax");
+ if (ep != NULL)
+
[U-Boot] [PATCH v2 2/3] I2C: mxc_i2c: make I2C1 and I2C2 optional
The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel. Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are. To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC. Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr> --- Changes in v2: - Make MXC I2C1 and I2C2 optional README| 8 ++-- drivers/i2c/mxc_i2c.c | 6 ++ include/configs/apf27.h | 2 ++ include/configs/aristainetos-common.h | 2 ++ include/configs/cgtqmx6eval.h | 2 ++ include/configs/cm_fx6.h | 2 ++ include/configs/embestmx6boards.h | 2 ++ include/configs/flea3.h | 2 ++ include/configs/gw_ventana.h | 2 ++ include/configs/imx31_phycore.h | 2 ++ include/configs/ls1021aqds.h | 2 ++ include/configs/ls1021atwr.h | 2 ++ include/configs/ls2085a_common.h | 2 ++ include/configs/m53evk.h | 2 ++ include/configs/mx25pdk.h | 2 ++ include/configs/mx35pdk.h | 2 ++ include/configs/mx53ard.h | 2 ++ include/configs/mx53evk.h | 2 ++ include/configs/mx53loco.h| 2 ++ include/configs/mx53smd.h | 2 ++ include/configs/mx6qsabreauto.h | 2 ++ include/configs/mx6sabresd.h | 2 ++ include/configs/mx6slevk.h| 2 ++ include/configs/mx6sxsabresd.h| 2 ++ include/configs/mx6ul_14x14_evk.h | 2 ++ include/configs/mx7dsabresd.h | 2 +- include/configs/nitrogen6x.h | 2 ++ include/configs/novena.h | 2 ++ include/configs/ot1200.h | 2 ++ include/configs/platinum.h| 2 ++ include/configs/tbs2910.h | 2 ++ include/configs/titanium.h| 2 ++ include/configs/tqma6.h | 2 ++ include/configs/usbarmory.h | 2 ++ include/configs/vf610twr.h| 2 ++ include/configs/wandboard.h | 2 ++ include/configs/warp.h| 2 ++ include/configs/woodburn_common.h | 2 ++ 38 files changed, 83 insertions(+), 3 deletions(-) diff --git a/README b/README index a13705a..c22b60b 100644 --- a/README +++ b/README @@ -2359,16 +2359,20 @@ CBFS (Coreboot Filesystem) support - drivers/i2c/i2c_mxc.c - activate this driver with CONFIG_SYS_I2C_MXC + - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1 + - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2 + - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 + - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE + - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED + - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE If those defines are not set, default value is 10 for speed, and 0 for slave. - - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 - - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - drivers/i2c/rcar_i2c.c: - activate this driver with CONFIG_SYS_I2C_RCAR diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index f1056e2..0f977d7 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -612,16 +612,22 @@ static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) /* * Register mxc i2c adapters */ +#ifdef CONFIG_SYS_I2C_MXC_I2C1 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, mxc_i2c_set_bus_speed, CONFIG_SYS_MXC_I2C1_SPEED, CONFIG_SYS_MXC_I2C1_SLAVE, 0) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C2 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, mxc_i2c_set_bus_speed, CONFIG_SYS_MXC_I2C2_SPEED, CONFIG_SYS_MXC_I2C2_SLAVE, 1) +#endif + #ifdef CONFIG_SYS_I2C_MXC_I2C3 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, mxc_i2
[U-Boot] [PATCH v2 3/3] vf610: add support for Phytec PCM052
Devices supported are:
- NFC (NAND FLASH)
- MMC
- QSPI (SPI NOR FLASH)
- I2C (only bus 2)
- I2C RTC
- I2C EEPROM
- FEC
Patch-series: 2
- remove useless CONFIG_SYS_SPD_BUS_NUM from config
- remove include of config_cmd_default.h
- remove duplicate CONFIG_CMD_NET
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr>
---
Changes in v2: None
arch/arm/Kconfig | 5 +
board/phytec/pcm052/Kconfig | 15 ++
board/phytec/pcm052/MAINTAINERS | 6 +
board/phytec/pcm052/Makefile | 7 +
board/phytec/pcm052/imximage.cfg | 17 ++
board/phytec/pcm052/pcm052.c | 515 +++
configs/pcm052_defconfig | 6 +
include/configs/pcm052.h | 231 ++
8 files changed, 802 insertions(+)
create mode 100644 board/phytec/pcm052/Kconfig
create mode 100644 board/phytec/pcm052/MAINTAINERS
create mode 100644 board/phytec/pcm052/Makefile
create mode 100644 board/phytec/pcm052/imximage.cfg
create mode 100644 board/phytec/pcm052/pcm052.c
create mode 100644 configs/pcm052_defconfig
create mode 100644 include/configs/pcm052.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c4371c7..341320c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -538,6 +538,10 @@ config TARGET_COLIBRI_VF
bool "Support Colibri VF50/61"
select CPU_V7
+config TARGET_PCM052
+ bool "Support pcm-052"
+ select CPU_V7
+
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
select CPU_V7
@@ -751,6 +755,7 @@ source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/phytec/pcm051/Kconfig"
+source "board/phytec/pcm052/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig
new file mode 100644
index 000..d67a69a
--- /dev/null
+++ b/board/phytec/pcm052/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PCM052
+
+config SYS_BOARD
+ default "pcm052"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_SOC
+ default "vf610"
+
+config SYS_CONFIG_NAME
+ default "pcm052"
+
+endif
diff --git a/board/phytec/pcm052/MAINTAINERS b/board/phytec/pcm052/MAINTAINERS
new file mode 100644
index 000..a877436
--- /dev/null
+++ b/board/phytec/pcm052/MAINTAINERS
@@ -0,0 +1,6 @@
+PCM052 BOARD
+M: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr>
+S: Maintained
+F: board/phytec/pcm052/
+F: include/configs/pcm052.h
+F: configs/pcm052_defconfig
diff --git a/board/phytec/pcm052/Makefile b/board/phytec/pcm052/Makefile
new file mode 100644
index 000..144f4e7
--- /dev/null
+++ b/board/phytec/pcm052/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pcm052.o
diff --git a/board/phytec/pcm052/imximage.cfg b/board/phytec/pcm052/imximage.cfg
new file mode 100644
index 000..f5a9747
--- /dev/null
+++ b/board/phytec/pcm052/imximage.cfg
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2015 3ADEV <http://www.3adev.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include
+
+/* image version */
+IMAGE_VERSION 2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSETFLASH_OFFSET_STANDARD
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
new file mode 100644
index 000..e4f61e1
--- /dev/null
+++ b/board/phytec/pcm052/pcm052.c
@@ -0,0 +1,515 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h
+ * do not match our settings. Let us (re)define our own settings here.
+ */
+
+#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm
+#define PCM052_VF610_DDR_PAD_CTRL_1(PAD_CTL_DSE_20ohm | \
+ PAD_CTL_INPUT_DIFFERENTIAL)
+#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \
+ PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_INPUT_DIFFERENTIAL)
+
+enum {
+ PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c,
__NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL),
+ PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220,
__NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A1
[U-Boot] [PATCH v2 1/3] vf610: refactor DDRMC code
The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.arib...@3adev.fr>
---
Changes in v2:
- reverted from all-custom to JEDEC+PHY+custom settings
arch/arm/imx-common/ddrmc-vf610.c | 193 ++
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 40 --
arch/arm/include/asm/arch-vf610/imx-regs.h| 6 +-
board/freescale/vf610twr/vf610twr.c | 156 ++---
board/toradex/colibri_vf/colibri_vf.c | 144 +--
5 files changed, 314 insertions(+), 225 deletions(-)
diff --git a/arch/arm/imx-common/ddrmc-vf610.c
b/arch/arm/imx-common/ddrmc-vf610.c
index e462631..daf3c7e 100644
--- a/arch/arm/imx-common/ddrmc-vf610.c
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -12,9 +12,9 @@
#include
#include
-void ddrmc_setup_iomux(void)
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
{
- static const iomux_v3_cfg_t ddr_pads[] = {
+ static const iomux_v3_cfg_t default_pads[] = {
VF610_PAD_DDR_A15__DDR_A_15,
VF610_PAD_DDR_A14__DDR_A_14,
VF610_PAD_DDR_A13__DDR_A_13,
@@ -65,76 +65,54 @@ void ddrmc_setup_iomux(void)
VF610_PAD_DDR_RESETB,
};
- imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
-}
+ if ((pads == NULL) || (pads_count == 0)) {
+ pads = default_pads;
+ pads_count = ARRAY_SIZE(default_pads);
+ }
-void ddrmc_phy_init(void)
-{
- struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+ imx_iomux_v3_setup_multiple_pads(pads, pads_count);
+}
- writel(DDRMC_PHY_DQ_TIMING, >phy[0]);
- writel(DDRMC_PHY_DQ_TIMING, >phy[16]);
- writel(DDRMC_PHY_DQ_TIMING, >phy[32]);
+static struct ddrmc_phy_setting default_phy_settings[] = {
+ { DDRMC_PHY_DQ_TIMING, 0 },
+ { DDRMC_PHY_DQ_TIMING, 16 },
+ { DDRMC_PHY_DQ_TIMING, 32 },
- writel(DDRMC_PHY_DQS_TIMING, >phy[1]);
- writel(DDRMC_PHY_DQS_TIMING, >phy[17]);
+ { DDRMC_PHY_DQS_TIMING, 1 },
+ { DDRMC_PHY_DQS_TIMING, 17 },
- writel(DDRMC_PHY_CTRL, >phy[2]);
- writel(DDRMC_PHY_CTRL, >phy[18]);
- writel(DDRMC_PHY_CTRL, >phy[34]);
+ { DDRMC_PHY_CTRL, 2 },
+ { DDRMC_PHY_CTRL, 18 },
+ { DDRMC_PHY_CTRL, 34 },
- writel(DDRMC_PHY_MASTER_CTRL, >phy[3]);
- writel(DDRMC_PHY_MASTER_CTRL, >phy[19]);
- writel(DDRMC_PHY_MASTER_CTRL, >phy[35]);
+ { DDRMC_PHY_MASTER_CTRL, 3 },
+ { DDRMC_PHY_MASTER_CTRL, 19 },
+ { DDRMC_PHY_MASTER_CTRL, 35 },
- writel(DDRMC_PHY_SLAVE_CTRL, >phy[4]);
- writel(DDRMC_PHY_SLAVE_CTRL, >phy[20]);
- writel(DDRMC_PHY_SLAVE_CTRL, >phy[36]);
+ { DDRMC_PHY_SLAVE_CTRL, 4 },
+ { DDRMC_PHY_SLAVE_CTRL, 20 },
+ { DDRMC_PHY_SLAVE_CTRL, 36 },
/* LPDDR2 only parameter */
- writel(DDRMC_PHY_OFF, >phy[49]);
+ { DDRMC_PHY_OFF, 49 },
- writel(DDRMC_PHY50_DDR3_MODE |
- DDRMC_PHY50_EN_SW_HALF_CYCLE, >phy[50]);
+ { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
/* Processor Pad ODT settings */
- writel(DDRMC_PHY_PROC_PAD_ODT, >phy[52]);
-}
-
-static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
-{
- struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
- u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
+ { DDRMC_PHY_PROC_PAD_ODT, 52 },
- if (lvl->wrlvl_reg_en) {
- writel(DDRMC_CR97_WRLVL_EN, >cr[97]);
- writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), >cr[98]);
- writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), >cr[99]);
- }
-
- if (lvl->rdlvl_reg_en) {
- cr102 |= DDRMC_CR102_RDLVL_REG_EN;
- cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
- cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
- }
-
- if (lvl->rdlvl_gt_reg_en) {
- cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
- cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
- cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
- }
-
- writel(cr102, >cr[102]);
- writel(cr105, >cr[105]);
- writel(cr106, >cr[106]);
- writel(cr110, >cr[110]);
-}
+ /* end marker */
+ { 0, -1 }
+};
void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
- struct ddrmc_lvl_info *lvl,
- int col_diff, int row_diff)
+ struct ddrmc_cr_setting *board_cr_settings,
+ struct ddrmc_phy_setting *boar
[U-Boot] [PATCH] net: TFTP: add timer count environment variable
There already is an environment variable 'tftptimeout'
for setting individuabl block query timeout value, but
there is none for setting the maximum TFTP timeout count,
which can also help with unreliable network, TFTP server,
or client hardware.
Add environment variable 'tftptimeoutcount'. As per the
comments about the global variable tftp_timeout_count_max,
make sure tftptimeoutcount is nonnegative.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
README | 8
net/tftp.c | 10 ++
2 files changed, 18 insertions(+)
diff --git a/README b/README
index b564640..c9dea37 100644
--- a/README
+++ b/README
@@ -5474,6 +5474,14 @@ List of environment variables (most likely not complete):
faster in networks with high packet loss rates or
with unreliable TFTP servers.
+ tftptimeoutcountmax - maximum count of TFTP timeouts (no
+ unit, minimum value = 0). Defines how many timeouts
+ can happen during a single file transfer before that
+ transfer is aborted. The default is 10, and 0 means
+ 'no timeouts allowed'. Increasing this value may help
+ downloads succeed with high packet loss rates, or with
+ unreliable TFTP servers or client hardware.
+
vlan - When set to a value 4095 the traffic over
Ethernet is encapsulated/received over 802.1q
VLAN tagged frames.
diff --git a/net/tftp.c b/net/tftp.c
index 3e99e73..fd44eb2 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -715,6 +715,16 @@ void tftp_start(enum proto_t protocol)
timeout_ms = 1000;
}
+ ep = getenv(tftptimeoutcountmax);
+ if (ep != NULL)
+ timeout_count_max = simple_strtol(ep, NULL, 10);
+
+ if (timeout_count_max 0) {
+ printf(TFTP timeout count max (%d ms) negative, set to 0\n,
+ timeout_count_max);
+ timeout_count_max = 0;
+ }
+
debug(TFTP blocksize = %i, timeout = %ld ms\n,
tftp_block_size_option, timeout_ms);
--
2.1.4
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[U-Boot] [PATCH v2] net: TFTP: add timer count environment variable
There already is an environment variable 'tftptimeout'
for setting individuabl block query timeout value, but
there is none for setting the maximum TFTP timeout count,
which can also help with unreliable network, TFTP server,
or client hardware.
Add environment variable 'tftptimeoutcountmax'. As per the
comments about the global variable tftp_timeout_count_max,
make sure tftptimeoutcountmax is nonnegative.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2: fixed env var name in commit message
README | 8
net/tftp.c | 10 ++
2 files changed, 18 insertions(+)
diff --git a/README b/README
index b564640..c9dea37 100644
--- a/README
+++ b/README
@@ -5474,6 +5474,14 @@ List of environment variables (most likely not complete):
faster in networks with high packet loss rates or
with unreliable TFTP servers.
+ tftptimeoutcountmax - maximum count of TFTP timeouts (no
+ unit, minimum value = 0). Defines how many timeouts
+ can happen during a single file transfer before that
+ transfer is aborted. The default is 10, and 0 means
+ 'no timeouts allowed'. Increasing this value may help
+ downloads succeed with high packet loss rates, or with
+ unreliable TFTP servers or client hardware.
+
vlan - When set to a value 4095 the traffic over
Ethernet is encapsulated/received over 802.1q
VLAN tagged frames.
diff --git a/net/tftp.c b/net/tftp.c
index 3e99e73..fd44eb2 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -715,6 +715,16 @@ void tftp_start(enum proto_t protocol)
timeout_ms = 1000;
}
+ ep = getenv(tftptimeoutcountmax);
+ if (ep != NULL)
+ timeout_count_max = simple_strtol(ep, NULL, 10);
+
+ if (timeout_count_max 0) {
+ printf(TFTP timeout count max (%d ms) negative, set to 0\n,
+ timeout_count_max);
+ timeout_count_max = 0;
+ }
+
debug(TFTP blocksize = %i, timeout = %ld ms\n,
tftp_block_size_option, timeout_ms);
--
2.1.4
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[U-Boot] [PATCH v3] net: TFTP: add timer count environment variable
There already is an environment variable 'tftptimeout'
for setting individuabl block query timeout value, but
there is none for setting the maximum TFTP timeout count,
which can also help with unreliable network, TFTP server,
or client hardware.
Add environment variable 'tftptimeoutcountmax'. As per the
comments about the global variable tftp_timeout_count_max,
make sure tftptimeoutcountmax is nonnegative.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v3:
- fixed mixup between tctp_timeout_count_max and timeout_count_max.
Changes in v2:
- fixed env var name in commit message
README | 8
net/tftp.c | 14 --
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/README b/README
index 4e0ff9f..56784b1 100644
--- a/README
+++ b/README
@@ -5477,6 +5477,14 @@ List of environment variables (most likely not complete):
faster in networks with high packet loss rates or
with unreliable TFTP servers.
+ tftptimeoutcountmax - maximum count of TFTP timeouts (no
+ unit, minimum value = 0). Defines how many timeouts
+ can happen during a single file transfer before that
+ transfer is aborted. The default is 10, and 0 means
+ 'no timeouts allowed'. Increasing this value may help
+ downloads succeed with high packet loss rates, or with
+ unreliable TFTP servers or client hardware.
+
vlan - When set to a value 4095 the traffic over
Ethernet is encapsulated/received over 802.1q
VLAN tagged frames.
diff --git a/net/tftp.c b/net/tftp.c
index 3e99e73..715fe04 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -600,7 +600,7 @@ static void tftp_handler(uchar *pkt, unsigned dest, struct
in_addr sip,
}
tftp_prev_block = tftp_cur_block;
- timeout_count_max = TIMEOUT_COUNT;
+ timeout_count_max = tftp_timeout_count_max;
net_set_timeout_handler(timeout_ms, tftp_timeout_handler);
store_block(tftp_cur_block - 1, pkt + 2, len);
@@ -715,6 +715,16 @@ void tftp_start(enum proto_t protocol)
timeout_ms = 1000;
}
+ ep = getenv(tftptimeoutcountmax);
+ if (ep != NULL)
+ tftp_timeout_count_max = simple_strtol(ep, NULL, 10);
+
+ if (tftp_timeout_count_max 0) {
+ printf(TFTP timeout count max (%d ms) negative, set to 0\n,
+ tftp_timeout_count_max);
+ tftp_timeout_count_max = 0;
+ }
+
debug(TFTP blocksize = %i, timeout = %ld ms\n,
tftp_block_size_option, timeout_ms);
@@ -840,7 +850,7 @@ void tftp_start_server(void)
puts(Loading: *\b);
- timeout_count_max = TIMEOUT_COUNT;
+ timeout_count_max = tftp_timeout_count_max;
timeout_count = 0;
timeout_ms = TIMEOUT;
net_set_timeout_handler(timeout_ms, tftp_timeout_handler);
--
2.1.4
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Re: [U-Boot] [PATCH 0/2] net: lpc32xx: add support to RMII phy
Hello Vladimir, On Mon, 6 Jul 2015 07:22:09 +0300, Vladimir Zapolskiy v...@mleia.com wrote: This is an update to LPC32xx MAC driver, which needs to have small quirks in order to properly work with an external phy connected by RMII interface. RMII mode of MAC operation is selected, if CONFIG_RMII is defined, this option is aligned with a number of boards, which already have the same config value. Also hopefully the first change from the series speeds up auto negotiation due to corrected configuration of MAC on intialization. Tested with SMSC LAN8700 phy. Vladimir Zapolskiy (2): net: lpc32xx: improve MAC configuration on reset and initialization net: lpc32xx: add RMII phy mode support This series actually requires two other lpc32xx patches that you posted earlier but which are not yet in u-boot/master or u-boot-arm/master: http://patchwork.ozlabs.org/patch/489100/ http://patchwork.ozlabs.org/patch/489190/ In the future, please indicate when such a dependency is required, so that testers know how to apply your patchs beforehand. This point aside, I've tested the four patches above u-boot-arm/master on a work_92105 target which has CONFIG_MII, and found no regression... and a dramatic increase in TFTP throughput, so thanks. :) (not adding my Tested-by because I don't want to mislead anyone: I haven't tested RMII) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] cairo: add missing MAINTAINERS file
This removes the following two warnings from buildman: WARNING: no status info for 'cairo' WARNING: no maintainers for 'cairo' Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- board/quipos/cairo/MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) create mode 100644 board/quipos/cairo/MAINTAINERS diff --git a/board/quipos/cairo/MAINTAINERS b/board/quipos/cairo/MAINTAINERS new file mode 100644 index 000..01332da --- /dev/null +++ b/board/quipos/cairo/MAINTAINERS @@ -0,0 +1,6 @@ +CAIRO BOARD +M: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr +S: Maintained +F: board/quipos/cairo/ +F: include/configs/omap3_cairo.h +F: configs/cairo_defconfig -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/5] Add support for Vybrid VF610-based PCM052
This patch series introduces the vf610-based PCM052 target after a few fixes to the vf610 code. As indicated in the last patch in the series, there is a bug in the FEC whereby it wrongly reports having sent out a packet. This bug does not seem specific to PCM052, and it also seems to appear in the TimeSys U-Boot deliveries and also in Linux, with varying frequencies. NOTE: this series is not checkpatch-clean. It has: - 51 line over 80 characters warnings. These lines are in a block for which the line lenght limit was obviously waived. arch/arm/include/asm/arch-vf610/iomux-vf610.h has 5 of these; board/phytec/pcm052/pcm052.c has the remaining 50. - 1 please write a paragraph that describes the config symbol fully warning for arch/arm/Kconfig. There are no such descriptions for any target in this file. - 1 need consistent spacing around '|' (ctx:WxV) error in board/phytec/pcm052/pcm052.c at line 98. It seems spurious to me, as this construct has the exact same spacing as all others in the file. Albert ARIBAUD (3ADEV) (5): net: fec_mxc: remove useless struct nbuf vf610: refactor DDRMC code i2c: fix vf610 support tools: mkimage: fix imximage header size vf610: add support for Phytec PCM052 arch/arm/Kconfig | 5 + arch/arm/imx-common/ddrmc-vf610.c | 239 +++- arch/arm/include/asm/arch-vf610/crm_regs.h| 3 + arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 60 +-- arch/arm/include/asm/arch-vf610/imx-regs.h| 3 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 11 +- arch/arm/include/asm/imx-common/iomux-v3.h| 2 + board/freescale/vf610twr/vf610twr.c | 181 ++--- board/phytec/pcm052/Kconfig | 15 + board/phytec/pcm052/MAINTAINERS | 6 + board/phytec/pcm052/Makefile | 7 + board/phytec/pcm052/imximage.cfg | 17 + board/phytec/pcm052/pcm052.c | 530 ++ board/toradex/colibri_vf/colibri_vf.c | 169 ++-- configs/pcm052_defconfig | 6 + drivers/i2c/mxc_i2c.c | 3 +- drivers/net/fec_mxc.c | 20 +- include/configs/pcm052.h | 234 tools/imximage.h | 1 + 19 files changed, 1155 insertions(+), 357 deletions(-) create mode 100644 board/phytec/pcm052/Kconfig create mode 100644 board/phytec/pcm052/MAINTAINERS create mode 100644 board/phytec/pcm052/Makefile create mode 100644 board/phytec/pcm052/imximage.cfg create mode 100644 board/phytec/pcm052/pcm052.c create mode 100644 configs/pcm052_defconfig create mode 100644 include/configs/pcm052.h -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] vf610: add support for Phytec PCM052
Devices supported are: - NFC (NAND FLASH) - MMC - QSPI (SPI NOR FLASH) - I2C (only bus 2) - I2C RTC - I2C EEPROM - FEC NOTES: 1. The NAND partitioning is different from the TimeSys U-Boot deliveries' for the following reasons: - mainline U-Boot is bigger than TimeSys', even though it now builds for Thumb state, which forces the bootloader area size to increase by 128KB; - The redundant environment definition in the TimeSys deliveries is erroneous, as both environments are in the same Flash sector. Here each environment gest its own sector, which increases the size needed for the environments by 128KB; - The kernel area was consequently reduced by 256KB, and the rootfs area left unchanged (depending on the actual kernel size, the kernel and rootfs area sizes may need to change again in the future). 2. The FEC presents a bug whereby it will indicate a packet as sent but will not actually have sent it. Caches are not the cause. Erratum e6358 is not the cause, and implementing this erratum's workaround does not fix the bug. The FEC's observable state is strictly the same (and correct) whether the packet was actually sent or not, i.e., there is no way to detect a bug occurrence, apart from the higher layer failure (e.g. TFTP timeout). At this point I suspect this to be a silicon bug. Patch-series: 1 Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- arch/arm/Kconfig | 5 + board/phytec/pcm052/Kconfig | 15 ++ board/phytec/pcm052/MAINTAINERS | 6 + board/phytec/pcm052/Makefile | 7 + board/phytec/pcm052/imximage.cfg | 17 ++ board/phytec/pcm052/pcm052.c | 530 +++ configs/pcm052_defconfig | 6 + include/configs/pcm052.h | 234 + 8 files changed, 820 insertions(+) create mode 100644 board/phytec/pcm052/Kconfig create mode 100644 board/phytec/pcm052/MAINTAINERS create mode 100644 board/phytec/pcm052/Makefile create mode 100644 board/phytec/pcm052/imximage.cfg create mode 100644 board/phytec/pcm052/pcm052.c create mode 100644 configs/pcm052_defconfig create mode 100644 include/configs/pcm052.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ac86518..27a5a04 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -661,6 +661,10 @@ config TARGET_COLIBRI_VF bool Support Colibri VF50/61 select CPU_V7 +config TARGET_PCM052 + bool Support pcm-052 + select CPU_V7 + config ARCH_ZYNQ bool Xilinx Zynq Platform select CPU_V7 @@ -936,6 +940,7 @@ source board/palmld/Kconfig source board/palmtc/Kconfig source board/palmtreo680/Kconfig source board/phytec/pcm051/Kconfig +source board/phytec/pcm052/Kconfig source board/ppcag/bg0900/Kconfig source board/pxa255_idp/Kconfig source board/samsung/smdk2410/Kconfig diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig new file mode 100644 index 000..d67a69a --- /dev/null +++ b/board/phytec/pcm052/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PCM052 + +config SYS_BOARD + default pcm052 + +config SYS_VENDOR + default phytec + +config SYS_SOC + default vf610 + +config SYS_CONFIG_NAME + default pcm052 + +endif diff --git a/board/phytec/pcm052/MAINTAINERS b/board/phytec/pcm052/MAINTAINERS new file mode 100644 index 000..a877436 --- /dev/null +++ b/board/phytec/pcm052/MAINTAINERS @@ -0,0 +1,6 @@ +PCM052 BOARD +M: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr +S: Maintained +F: board/phytec/pcm052/ +F: include/configs/pcm052.h +F: configs/pcm052_defconfig diff --git a/board/phytec/pcm052/Makefile b/board/phytec/pcm052/Makefile new file mode 100644 index 000..144f4e7 --- /dev/null +++ b/board/phytec/pcm052/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pcm052.o diff --git a/board/phytec/pcm052/imximage.cfg b/board/phytec/pcm052/imximage.cfg new file mode 100644 index 000..f5a9747 --- /dev/null +++ b/board/phytec/pcm052/imximage.cfg @@ -0,0 +1,17 @@ +/* + * Copyright 2015 3ADEV http://www.3adev.com + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include asm/imx-common/imximage.cfg + +/* image version */ +IMAGE_VERSION 2 + +/* Boot Offset 0x400, valid for both SD and NAND boot */ +BOOT_OFFSETFLASH_OFFSET_STANDARD diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c new file mode 100644 index 000..0607f1c --- /dev/null +++ b/board/phytec/pcm052/pcm052.c @@ -0,0 +1,530 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include common.h +#include asm/io.h +#include asm/arch/imx-regs.h +#include asm/arch/iomux-vf610.h +#include asm/arch/ddrmc-vf610.h
[U-Boot] [PATCH 4/5] tools: mkimage: fix imximage header size
imximage header size is 4-byte, not 8-byte aligned.
This produces .imx images that a Vybrid cannot boot
on.
Fix by adding a padding field in header.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
tools/imximage.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/imximage.h b/tools/imximage.h
index 36fe095..a913329 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -129,6 +129,7 @@ typedef struct {
ivt_header_t header;
write_dcd_command_t write_dcd_command;
dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
+ uint32_t padding[1]; /* end up on an 8-byte boundary */
} dcd_v2_t;
typedef struct {
--
2.1.0
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[U-Boot] [PATCH 2/5] vf610: refactor DDRMC code
The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/imx-common/ddrmc-vf610.c | 239 ++
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 60 +--
board/freescale/vf610twr/vf610twr.c | 181 +--
board/toradex/colibri_vf/colibri_vf.c | 169 +-
4 files changed, 312 insertions(+), 337 deletions(-)
diff --git a/arch/arm/imx-common/ddrmc-vf610.c
b/arch/arm/imx-common/ddrmc-vf610.c
index e462631..44b9a0f 100644
--- a/arch/arm/imx-common/ddrmc-vf610.c
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -12,9 +12,9 @@
#include asm/arch/iomux-vf610.h
#include asm/arch/ddrmc-vf610.h
-void ddrmc_setup_iomux(void)
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
{
- static const iomux_v3_cfg_t ddr_pads[] = {
+ static const iomux_v3_cfg_t default_pads[] = {
VF610_PAD_DDR_A15__DDR_A_15,
VF610_PAD_DDR_A14__DDR_A_14,
VF610_PAD_DDR_A13__DDR_A_13,
@@ -65,212 +65,77 @@ void ddrmc_setup_iomux(void)
VF610_PAD_DDR_RESETB,
};
- imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
-}
+ if ((pads == NULL) || (pads_count == 0)) {
+ pads = default_pads;
+ pads_count = ARRAY_SIZE(default_pads);
+ }
-void ddrmc_phy_init(void)
-{
- struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+ imx_iomux_v3_setup_multiple_pads(pads, pads_count);
+}
- writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[0]);
- writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[16]);
- writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[32]);
+static struct ddrmc_reg_setting default_phy_settings[] = {
+ { DDRMC_PHY_DQ_TIMING, 0 },
+ { DDRMC_PHY_DQ_TIMING, 16 },
+ { DDRMC_PHY_DQ_TIMING, 32 },
- writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[1]);
- writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[17]);
+ { DDRMC_PHY_DQS_TIMING, 1 },
+ { DDRMC_PHY_DQS_TIMING, 17 },
- writel(DDRMC_PHY_CTRL, ddrmr-phy[2]);
- writel(DDRMC_PHY_CTRL, ddrmr-phy[18]);
- writel(DDRMC_PHY_CTRL, ddrmr-phy[34]);
+ { DDRMC_PHY_CTRL, 2 },
+ { DDRMC_PHY_CTRL, 18 },
+ { DDRMC_PHY_CTRL, 34 },
- writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[3]);
- writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[19]);
- writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[35]);
+ { DDRMC_PHY_MASTER_CTRL, 3 },
+ { DDRMC_PHY_MASTER_CTRL, 19 },
+ { DDRMC_PHY_MASTER_CTRL, 35 },
- writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[4]);
- writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[20]);
- writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[36]);
+ { DDRMC_PHY_SLAVE_CTRL, 4 },
+ { DDRMC_PHY_SLAVE_CTRL, 20 },
+ { DDRMC_PHY_SLAVE_CTRL, 36 },
/* LPDDR2 only parameter */
- writel(DDRMC_PHY_OFF, ddrmr-phy[49]);
+ { DDRMC_PHY_OFF, 49 },
- writel(DDRMC_PHY50_DDR3_MODE |
- DDRMC_PHY50_EN_SW_HALF_CYCLE, ddrmr-phy[50]);
+ { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
/* Processor Pad ODT settings */
- writel(DDRMC_PHY_PROC_PAD_ODT, ddrmr-phy[52]);
-}
+ { DDRMC_PHY_PROC_PAD_ODT, 52 },
-static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
-{
- struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
- u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
+ /* end marker */
+ { 0, -1 }
+};
- if (lvl-wrlvl_reg_en) {
- writel(DDRMC_CR97_WRLVL_EN, ddrmr-cr[97]);
- writel(DDRMC_CR98_WRLVL_DL_0(lvl-wrlvl_dl_0), ddrmr-cr[98]);
- writel(DDRMC_CR99_WRLVL_DL_1(lvl-wrlvl_dl_1), ddrmr-cr[99]);
- }
-
- if (lvl-rdlvl_reg_en) {
- cr102 |= DDRMC_CR102_RDLVL_REG_EN;
- cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl-rdlvl_dl_0);
- cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl-rdlvl_dl_1);
- }
-
- if (lvl-rdlvl_gt_reg_en) {
- cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
- cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl-rdlvl_gt_dl_0);
- cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl-rdlvl_gt_dl_1);
- }
-
- writel(cr102, ddrmr-cr[102]);
- writel(cr105, ddrmr-cr[105]);
- writel(cr106, ddrmr-cr[106]);
- writel(cr110, ddrmr-cr[110]);
-}
-
-void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
- struct ddrmc_lvl_info *lvl,
- int col_diff, int row_diff)
+void ddrmc_ctrl_init_ddr3(struct ddrmc_reg_setting const *cr_settings,
+ struct ddrmc_reg_setting const *phy_settings)
{
struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+ struct
[U-Boot] [PATCH 3/5] i2c: fix vf610 support
Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four
I2C instances available in VF610.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/include/asm/arch-vf610/crm_regs.h| 3 +++
arch/arm/include/asm/arch-vf610/imx-regs.h| 3 +++
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 11 +++
arch/arm/include/asm/imx-common/iomux-v3.h| 2 ++
drivers/i2c/mxc_i2c.c | 3 ++-
5 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index fdb45e9..a46e396 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -207,6 +207,7 @@ struct anadig_reg {
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 24)
#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 12)
+#define CCM_CCGR4_I2C1_CTRL_MASK (0x3 14)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 10)
#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 24)
#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 26)
@@ -216,6 +217,8 @@ struct anadig_reg {
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
+#define CCM_CCGR10_I2C2_CTRL_MASK (0x3 12)
+#define CCM_CCGR10_I2C3_CTRL_MASK (0x3 14)
#define ANADIG_PLL7_CTRL_BYPASS (1 16)
#define ANADIG_PLL7_CTRL_ENABLE (1 13)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 7df3b1e..4366985 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -75,6 +75,9 @@
#define ESAI_FIFO_BASE_ADDR(AIPS0_BASE_ADDR + 0x00063000)
#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
#define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
+#define I2C2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00067000)
+#define I2C3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E6000)
+#define I2C4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E7000)
#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 019307b..0e2bd53 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -20,7 +20,8 @@
#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \
PAD_CTL_INPUT_DIFFERENTIAL)
#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
+ PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | \
+ PAD_CTL_OBE_IBE_ENABLE)
#define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \
PAD_CTL_OBE_IBE_ENABLE)
@@ -110,6 +111,8 @@ enum {
VF610_PAD_PTA29__ESDHC1_DAT3= IOMUX_PAD(0x004c, 0x004c, 5,
__NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2,
0x033c, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2,
0x0340, 1, VF610_I2C_PAD_CTRL),
+ VF610_PAD_PTA22__I2C2_SCL = IOMUX_PAD(0x0030, 0x0030, 6,
0x034c, 0, VF610_I2C_PAD_CTRL),
+ VF610_PAD_PTA23__I2C2_SDA = IOMUX_PAD(0x0034, 0x0034, 6,
0x0350, 0, VF610_I2C_PAD_CTRL),
VF610_PAD_PTD31__NF_IO15= IOMUX_PAD(0x00fc, 0x00fc, 2,
__NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD31__GPIO_63= IOMUX_PAD(0x00fc, 0x00fc, 0,
__NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD30__NF_IO14= IOMUX_PAD(0x0100, 0x0100, 2,
__NA_, 0, VF610_NFC_IO_PAD_CTRL),
@@ -146,10 +149,10 @@ enum {
VF610_PAD_PTD12__GPIO_91= IOMUX_PAD(0x016c, 0x016c, 0,
__NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD13__GPIO_92= IOMUX_PAD(0x0170, 0x0170, 0,
__NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2,
__NA_, 0, VF610_NFC_IO_PAD_CTRL),
- VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2,
__NA_, 0, VF610_NFC_IO_PAD_CTRL),
- VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2,
__NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2,
__NA_, 0, VF610_NFC_IO_PAD_CTRL),
+ VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128
[U-Boot] [PATCH 1/5] net: fec_mxc: remove useless struct nbuf
This locally defined struct is actually only used once
and as an opaque type. Remove it for clarity.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
drivers/net/fec_mxc.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 9225d37..c5dcbbb 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -67,13 +67,6 @@ DECLARE_GLOBAL_DATA_PTR;
#undef DEBUG
-struct nbuf {
- uint8_t data[1500]; /** actual data */
- int length; /** actual length */
- int used; /** buffer in use or not */
- uint8_t head[16]; /** MAC header(6 + 6 + 2) + 2(aligned) */
-};
-
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
static void swap_packet(uint32_t *packet, int length)
{
@@ -775,7 +768,6 @@ static int fec_recv(struct eth_device *dev)
struct fec_bd *rbd = fec-rbd_base[fec-rbd_index];
unsigned long ievent;
int frame_length, len = 0;
- struct nbuf *frame;
uint16_t bd_status;
uint32_t addr, size, end;
int i;
@@ -835,12 +827,11 @@ static int fec_recv(struct eth_device *dev)
/*
* Get buffer address and size
*/
- frame = (struct nbuf *)readl(rbd-data_pointer);
+ addr = readl(rbd-data_pointer);
frame_length = readw(rbd-data_length) - 4;
/*
* Invalidate data cache over the buffer
*/
- addr = (uint32_t)frame;
end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
addr = ~(ARCH_DMA_MINALIGN - 1);
invalidate_dcache_range(addr, end);
@@ -849,16 +840,15 @@ static int fec_recv(struct eth_device *dev)
* Fill the buffer and pass it to upper layers
*/
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
- swap_packet((uint32_t *)frame-data, frame_length);
+ swap_packet((uint32_t *)addr, frame_length);
#endif
- memcpy(buff, frame-data, frame_length);
+ memcpy(buff, (char *)addr, frame_length);
net_process_received_packet(buff, frame_length);
len = frame_length;
} else {
if (bd_status FEC_RBD_ERR)
- printf(error frame: 0x%08lx 0x%08x\n,
- (ulong)rbd-data_pointer,
- bd_status);
+ printf(error frame: 0x%08x 0x%08x\n,
+ addr, bd_status);
}
/*
--
2.1.0
___
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[U-Boot] [PATCH v7 1/9] lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v7:
- removed SRAM section and custom linker script
Changes in v6:
- added some missing readl() wraps
- moved descriptors and buffers to SRAM
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 9 +
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 +
arch/arm/include/asm/arch-lpc32xx/config.h| 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/net/Makefile | 1 +
drivers/net/lpc32xx_eth.c | 637 ++
include/netdev.h | 1 +
7 files changed, 659 insertions(+)
create mode 100644 drivers/net/lpc32xx_eth.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..eec4d9e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include netdev.h
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/wdt.h
@@ -55,3 +56,11 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..062db8d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -37,3 +37,10 @@ void lpc32xx_uart_init(unsigned int uart_id)
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
clk-u3clk + (uart_id - 3));
}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+ | CLK_MAC_MII, clk-macclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h
b/arch/arm/include/asm/arch-lpc32xx/config.h
index 564441c..d57bc48 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -52,6 +52,9 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
/* NOR Flash */
#if defined(CONFIG_SYS_FLASH_CFI)
#define CONFIG_FLASH_CFI_DRIVER
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 28812be..a6b8826 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -8,5 +8,6 @@
#define _LPC32XX_SYS_PROTO_H
void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 3ff86b7..5a5269a 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_GRETH) += greth.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
+obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
new file mode 100644
index 000..fcadf0c
--- /dev/null
+++ b/drivers/net/lpc32xx_eth.c
@@ -0,0 +1,637 @@
+/*
+ * LPC32xx Ethernet MAC interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include net.h
+#include malloc.h
+#include miiphy.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/types.h
+#include asm/system.h
+#include asm/byteorder.h
+#include asm/arch/cpu.h
+#include asm/arch/config.h
+
+/*
+ * Notes:
+ *
+ * 1. Unless specified otherwise, all references to tables or paragraphs
+ *are to UM10326, LPC32x0 and LPC32x0/01 User manual.
+ *
+ * 2. Only bitfield masks/values which are actually used by the driver
+ *are defined.
+ */
+
+/* a single RX descriptor. The controller has an array of these */
+struct lpc32xx_eth_rxdesc {
+ u32 packet; /* Receive packet pointer */
+ u32 control;/* Descriptor command status */
+};
+
+#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
+
+/* RX control bitfields/masks (see Table 330) */
+#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x07FF
+#define LPC32XX_ETH_RX_CTRL_UNUSED0x7800
+#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x8000
+
+/* a single RX status. The controller has an array of these */
+struct lpc32xx_eth_rxstat {
+ u32 statusinfo; /* Transmit Descriptor status */
+ u32 statushashcrc; /* Transmit Descriptor CRCs */
+};
+
+#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
+
+/* RX
[U-Boot] [PATCH v7 2/9] lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v7:
- rewrite SPL image load logic
Changes in v6:
- rewrite timeout loops
- fix bad block skipping in SPL chainload loop
Changes in v5:
- switch to CONFIG_SYS_NAND_SELF_INIT
Changes in v4:
- remove two debugging statements
- add __iomem to regs struct
- remove useless 'else return;'
- take BB marker out of free OOB area
- replace magic numbers in OOB reads/writes
- add timeouts in NAND loops
- use DIV_ROUND_UP where applicable
- fix erroneous comment
- skip bad blocks in SPL chainload loop
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/lpc32xx_nand_mlc.c | 764 ++
5 files changed, 776 insertions(+)
create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 062db8d..be4c93d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -44,3 +44,9 @@ void lpc32xx_mac_init(void)
writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
| CLK_MAC_MII, clk-macclk_ctrl);
}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15..bc7d33d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -147,6 +147,10 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 1)
+#define CLK_NAND_MLC_INT (1 5)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a6b8826..0c4e712 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -9,5 +9,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f02bfc..347ea62 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 000..8156fe9
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -0,0 +1,764 @@
+/*
+ * LPC32xx MLC NAND flash controller driver
+ *
+ * (C) Copyright 2014 3ADEV http://3adev.com
+ * Written by Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * NOTE:
+ *
+ * The MLC NAND flash controller provides hardware Reed-Solomon ECC
+ * covering in- and out-of-band data together. Therefore, in- and out-
+ * of-band data must be written together in order to have a valid ECC.
+ *
+ * Consequently, pages with meaningful in-band data are written with
+ * blank (all-ones) out-of-band data and a valid ECC, and any later
+ * out-of-band data write will void the ECC.
+ *
+ * Therefore, code which reads such late-written out-of-band data
+ * should not rely on the ECC validity.
+ */
+
+#include common.h
+#include nand.h
+#include asm/errno.h
+#include asm/io.h
+#include nand.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+
+/*
+ * MLC NAND controller registers.
+ */
+struct lpc32xx_nand_mlc_registers {
+ u8 buff[32768]; /* controller's serial data buffer */
+ u8 data[32768]; /* NAND's raw data buffer */
+ u32 cmd;
+ u32 addr;
+ u32 ecc_enc_reg;
+ u32 ecc_dec_reg;
+ u32 ecc_auto_enc_reg;
+ u32 ecc_auto_dec_reg;
+ u32 rpr;
+ u32 wpr;
+ u32 rubp;
+ u32 robp;
+ u32 sw_wp_add_low;
+ u32 sw_wp_add_hig;
+ u32 icr;
+ u32 time_reg;
+ u32 irq_mr;
+ u32 irq_sr;
+ u32 lock_pr;
+ u32 isr;
+ u32 ceh;
+};
+
+/* LOCK_PR register defines
[U-Boot] [PATCH v7 0/9] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: A - I2C driver remains non-DM During v2 review, it was suggested to move to DM for I2C. However, this caused issues with the 'date', 'dtt' and 'eeprom' commands which are configured in this board. Therefore the I2C move to DM was not done. B - Some checkpatch diagnostics are not fixed The following warnings checkpatch warnings and checks were not fixed: 1. warning: arch/arm/Kconfig,135: please write a paragraph that describes the config symbol fully Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. check: include/configs/work_92105.h,187: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v7: - removed SRAM section and custom linker script - rewrite SPL image load logic - fixed erroneous 'zynq' comment - fixed 128MB support Changes in v6: - added some missing readl() wraps - moved descriptors and buffers to SRAM - rewrite timeout loops - fix bad block skipping in SPL chainload loop - remove '+S:' prefixes from defconfig - use custom LPC32XX linker script - reset peripherals at startup - support 128MB boards Changes in v5: - switch to CONFIG_SYS_NAND_SELF_INIT - switched board NAND config to CONFIG_SYS_NAND_SELF_INIT Changes in v4: - remove two debugging statements - add __iomem to regs struct - remove useless 'else return;' - take BB marker out of free OOB area - replace magic numbers in OOB reads/writes - add timeouts in NAND loops - use DIV_ROUND_UP where applicable - fix erroneous comment - skip bad blocks in SPL chainload loop Changes in v3: - move DM dependency constraint into Kconfig - move regs pointer and function cache into private struct - discourage readers from using functions implementation as an example - move regs and functions in private struct - remove script/Makefile.spl change - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (9): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target Introduce CONFIG_SPL_PANIC_ON_RAW_IMAGE lpc32xx: add support for board work_92105 Makefile | 20 + README | 10 + arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 + arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 10 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 77 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h| 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 3 + arch/arm/include/asm/arch-lpc32xx/emc.h| 21 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h| 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 10 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 +++ board/work-microwave/work_92105/work_92105.c | 77 +++ .../work-microwave/work_92105/work_92105_display.c | 349 ++ .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 85 +++ common/image.c | 1 + common/spl/spl.c | 12 + configs/work_92105_defconfig | 6 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c| 293 drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 ++ drivers/i2c/Makefile
[U-Boot] [PATCH v7 4/9] lpc32xx: add GPIO support
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- move DM dependency constraint into Kconfig
- move regs pointer and function cache into private struct
- discourage readers from using functions implementation as an example
Changes in v2:
- move from legacy to Driver Model support
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 +
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 293 +++
5 files changed, 349 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..a407098 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include asm/arch/clk.h
#include asm/arch/uart.h
#include asm/io.h
+#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = gpio_lpc32xx
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b609e73..7b5178a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -7,3 +7,10 @@ config DM_GPIO
the GPIO uclass. Drivers provide methods to query the
particular GPIOs that they provide. The uclass interface
is defined in include/asm-generic/gpio.h.
+
+config LPC32XX_GPIO
+ bool LPC32XX GPIO driver
+ depends on DM
+ default n
+ help
+ Support for the LPC32XX GPIO driver.
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fe9a3b2..85f71c5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..96b3125
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,293 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+#include asm-generic/gpio.h
+#include dm.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING #1 **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where a single physical GPIO has differing numbers
+ * for setting its direction, reading it and/or writing to it.
+ *
+ * ** WARNING #2
[U-Boot] [PATCH v7 6/9] dtt: add ds620 support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- cosmetic: added a blank line before copyright
drivers/hwmon/Makefile | 1 +
drivers/hwmon/ds620.c | 65 ++
include/dtt.h | 15 ++--
3 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 drivers/hwmon/ds620.c
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 25b8e8a..b4fb057 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_DTT_ADT7460) += adt7460.o
obj-$(CONFIG_DTT_DS1621) += ds1621.o
obj-$(CONFIG_DTT_DS1722) += ds1722.o
obj-$(CONFIG_DTT_DS1775) += ds1775.o
+obj-$(CONFIG_DTT_DS620) += ds620.o
obj-$(CONFIG_DTT_LM63) += lm63.o
obj-$(CONFIG_DTT_LM73) += lm73.o
obj-$(CONFIG_DTT_LM75) += lm75.o
diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c
new file mode 100644
index 000..1ecc3da
--- /dev/null
+++ b/drivers/hwmon/ds620.c
@@ -0,0 +1,65 @@
+/*
+ * DS620 DTT support
+ *
+ * (C) Copyright 2014 3ADEV http://www.3adev.com
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
+ */
+
+#include common.h
+#include i2c.h
+#include dtt.h
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48
+#define DTT_START_CONVERT 0x51
+#define DTT_TEMP 0xAA
+#define DTT_CONFIG 0xAC
+
+/*
+ * Config register MSB bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_AUTOC 0x02
+#define DTT_CONFIG_R0 0x04 /* always 1 */
+#define DTT_CONFIG_R1 0x08 /* always 1 */
+#define DTT_CONFIG_TLF 0x10
+#define DTT_CONFIG_THF 0x20
+#define DTT_CONFIG_NVB 0x40
+#define DTT_CONFIG_DONE0x80
+
+#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor 0x07))
+
+int dtt_init_one(int sensor)
+{
+ uint8_t config = DTT_CONFIG_1SHOT
+ | DTT_CONFIG_R0
+ | DTT_CONFIG_R1;
+ return i2c_write(CHIP(sensor), DTT_CONFIG, 1, config, 1);
+}
+
+int dtt_get_temp(int sensor)
+{
+ uint8_t status;
+ uint8_t temp[2];
+
+ /* Start a conversion, may take up to 1 second. */
+ i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0);
+ do {
+ if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, status, 1))
+ /* bail out if I2C error */
+ status |= DTT_CONFIG_DONE;
+ } while (!(status DTT_CONFIG_DONE));
+ if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2))
+ /* bail out if I2C error */
+ return -274; /* below absolute zero == error */
+
+ return ((int16_t)(temp[1] | (temp[0] 8))) 7;
+}
diff --git a/include/dtt.h b/include/dtt.h
index 058bca4..173159d 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -12,13 +12,14 @@
#define _DTT_H_
#if defined(CONFIG_DTT_ADM1021)|| \
-defined(CONFIG_DTT_ADT7460)|| \
-defined(CONFIG_DTT_DS1621) || \
-defined(CONFIG_DTT_DS1775) || \
-defined(CONFIG_DTT_LM63) || \
-defined(CONFIG_DTT_LM73) || \
-defined(CONFIG_DTT_LM75) || \
-defined(CONFIG_DTT_LM81)
+ defined(CONFIG_DTT_ADT7460) || \
+ defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
+ defined(CONFIG_DTT_DS620) || \
+ defined(CONFIG_DTT_LM63)|| \
+ defined(CONFIG_DTT_LM73)|| \
+ defined(CONFIG_DTT_LM75)|| \
+ defined(CONFIG_DTT_LM81)
#define CONFIG_DTT /* We have a DTT */
--
2.1.0
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v7 5/9] lpc32xx: add LPC32xx SSP support (SPI mode)
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v7:
- fixed erroneous 'zynq' comment
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- move regs and functions in private struct
Changes in v2:
- added MUX setting for SSP0
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/lpc32xx_ssp.c | 144 ++
5 files changed, 163 insertions(+)
create mode 100644 drivers/spi/lpc32xx_ssp.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index a407098..5a453e3 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -8,11 +8,13 @@
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/uart.h
+#include asm/arch/mux.h
#include asm/io.h
#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
void lpc32xx_uart_init(unsigned int uart_id)
{
@@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum)
U_BOOT_DEVICE(lpc32xx_gpios) = {
.name = gpio_lpc32xx
};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, clk-ssp_ctrl);
+ /* Mux SSP0 pins */
+ writel(P_MUX_SET_SSP0, mux-p_mux_set);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 781ac07..2cb5703 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -155,6 +155,9 @@ struct clk_pm_regs {
#define CLK_NAND_MLC (1 1)
#define CLK_NAND_MLC_INT (1 5)
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 0)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a4a05d1..86d5ee9 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..ce6f1cc 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
new file mode 100644
index 000..c5b766c
--- /dev/null
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -0,0 +1,144 @@
+/*
+ * LPC32xx SSP interface (SPI mode)
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/compat.h
+#include asm/io.h
+#include malloc.h
+#include spi.h
+#include asm/arch/clk.h
+
+/* SSP chip registers */
+struct ssp_regs {
+ u32 cr0;
+ u32 cr1;
+ u32 data;
+ u32 sr;
+ u32 cpsr;
+ u32 imsc;
+ u32 ris;
+ u32 mis;
+ u32 icr;
+ u32 dmacr;
+};
+
+/* CR1 register defines */
+#define SSP_CR1_SSP_ENABLE 0x0002
+
+/* SR register defines */
+#define SSP_SR_TNF 0x0002
+/* SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE 0x0004
+
+/* lpc32xx spi slave */
+struct lpc32xx_spi_slave {
+ struct spi_slave slave;
+ struct ssp_regs *regs;
+};
+
+static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave(
+ struct spi_slave *slave)
+{
+ return container_of(slave, struct lpc32xx_spi_slave, slave);
+}
+
+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
+void spi_init(void)
+{
+ /*
+* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
+* and configuration will be done in spi_setup_slave()
+ */
+}
+
+/* the following is called in sequence by do_spi_xfer() */
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+ struct lpc32xx_spi_slave *lslave
[U-Boot] [PATCH v7 3/9] lpc32xx: i2c: add LPC32xx I2C interface support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/i2c/Makefile | 1 +
drivers/i2c/lpc32xx_i2c.c | 249 ++
6 files changed, 268 insertions(+)
create mode 100644 drivers/i2c/lpc32xx_i2c.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index be4c93d..81b53ea 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void)
/* Enable NAND interface */
writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(clk-i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, clk-i2cclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index bc7d33d..781ac07 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -123,6 +123,10 @@ struct clk_pm_regs {
#define CLK_MAC_SLAVE (1 1)
#define CLK_MAC_REG(1 0)
+/* I2C Clock Control Register bits */
+#define CLK_I2C2_ENABLE(1 1)
+#define CLK_I2C1_ENABLE(1 0)
+
/* Timer Clock Control1 Register bits */
#define CLK_TIMCLK_MOTOR (1 6)
#define CLK_TIMCLK_TIMER3 (1 5)
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h
b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a0..1067107 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -37,6 +37,8 @@
#define UART4_BASE 0x40088000 /* UART 4 registers base*/
#define UART5_BASE 0x4009 /* UART 5 registers base*/
#define UART6_BASE 0x40098000 /* UART 6 registers base*/
+#define I2C1_BASE 0x400A /* I2C 1 registers base*/
+#define I2C2_BASE 0x400A8000 /* I2C 2 registers base*/
/* External SDRAM Memory Bank base addresses */
#define EMC_DYCS0_BASE 0x8000 /* SDRAM DYCS0 base address */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 0c4e712..a4a05d1 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -10,5 +10,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 774bc94..26ea854 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
new file mode 100644
index 000..78d26e4
--- /dev/null
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -0,0 +1,249 @@
+/*
+ * LPC32xx I2C interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include i2c.h
+#include asm/errno.h
+#include asm/arch/clk.h
+
+/*
+ * Provide default speed and slave if target did not
+ */
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
+#define CONFIG_SYS_I2C_LPC32XX_SPEED 35
+#endif
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
+#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
+#endif
+
+/* i2c register set */
+struct lpc32xx_i2c_registers {
+ union {
+ u32 rx;
+ u32 tx;
+ };
+ u32 stat;
+ u32 ctrl;
+ u32 clk_hi;
+ u32 clk_lo;
+ u32 adr;
+ u32 rxfl;
+ u32 txfl;
+ u32 rxb;
+ u32 txb;
+ u32 stx;
+ u32 stxfl;
+};
+
+/* TX register fields */
+#define LPC32XX_I2C_TX_START 0x0100
+#define LPC32XX_I2C_TX_STOP0x0200
+
+/* Control register values */
+#define LPC32XX_I2C_SOFT_RESET 0x0100
+
+/* Status register values
[U-Boot] [PATCH v7 8/9] Introduce CONFIG_SPL_PANIC_ON_RAW_IMAGE
introduce CONFIG_SPL_PANIC_ON_RAW_IMAGE.
An SPL which define this will panic() if the
image it has loaded does not have a mkimage
signature.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
README | 10 ++
common/spl/spl.c | 12
2 files changed, 22 insertions(+)
diff --git a/README b/README
index 5d57eb9..204f2c3 100644
--- a/README
+++ b/README
@@ -3610,6 +3610,16 @@ FIT uImage format:
CONFIG_SPL_STACK
Adress of the start of the stack SPL will use
+ CONFIG_SPL_PANIC_ON_RAW_IMAGE
+ When defined, SPL will panic() if the image it has
+ loaded does not have a signature.
+ Defining this is useful when code which loads images
+ in SPL cannot guarantee that absolutely all read errors
+ will be caught.
+ An example is the LPC32XX MLC NAND driver, which will
+ consider that a completely unreadable NAND block is bad,
+ and thus should be skipped silently.
+
CONFIG_SPL_RELOC_STACK
Adress of the start of the stack SPL will use after
relocation. If unspecified, this is equal to
diff --git a/common/spl/spl.c b/common/spl/spl.c
index cd75bbc..8e1fb40 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -101,10 +101,22 @@ void spl_parse_image_header(const struct image_header
*header)
(int)sizeof(spl_image.name), spl_image.name,
spl_image.load_addr, spl_image.size);
} else {
+#ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE
+ /*
+* CONFIG_SPL_PANIC_ON_RAW_IMAGE is defined when the
+* code which loads images in SPL cannot guarantee that
+* absolutely all read errors will be reported.
+* An example is the LPC32XX MLC NAND driver, which
+* will consider that a completely unreadable NAND block
+* is bad, and thus should be skipped silently.
+*/
+ panic(** no mkimage signature but raw image not supported);
+#else
/* Signature not found - assume u-boot.bin */
debug(mkimage signature not found - ih_magic = %x\n,
header-ih_magic);
spl_set_header_raw_uboot();
+#endif
}
}
--
2.1.0
___
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[U-Boot] [PATCH v7 9/9] lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB or 128MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- Changes in v7: - fixed 128MB support Changes in v6: - remove '+S:' prefixes from defconfig - use custom LPC32XX linker script - reset peripherals at startup - support 128MB boards Changes in v5: - switched board NAND config to CONFIG_SYS_NAND_SELF_INIT Changes in v4: None Changes in v3: - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: None Makefile | 20 ++ arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 1 + arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 77 + arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 +++ arch/arm/include/asm/arch-lpc32xx/clk.h| 5 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 1 + arch/arm/include/asm/arch-lpc32xx/emc.h| 21 ++ arch/arm/include/asm/arch-lpc32xx/mux.h| 18 ++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 6 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 ++ board/work-microwave/work_92105/work_92105.c | 77 + .../work-microwave/work_92105/work_92105_display.c | 349 + .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 85 + configs/work_92105_defconfig | 6 + include/configs/work_92105.h | 241 ++ 22 files changed, 1129 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 board/work-microwave/work_92105/work_92105_spl.c create mode 100644 configs/work_92105_defconfig create mode 100644 include/configs/work_92105.h diff --git a/Makefile b/Makefile index 0d160c9..d889b15 100644 --- a/Makefile +++ b/Makefile @@ -905,6 +905,26 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) +MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) + +lpc32xx-spl.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-0.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-1.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img + $(call if_changed,cat) + +CLEAN_FILES += lpc32xx-* + OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ --pad-to=$(CONFIG_TPL_PAD_TO) tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9292e98..1290f53 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -132,6 +132,11 @@ config TARGET_DEVKIT3250 bool Support devkit3250 select CPU_ARM926EJS +config TARGET_WORK_92105 + bool Support work_92105 + select CPU_ARM926EJS + select SUPPORT_SPL + config TARGET_MX25PDK bool Support mx25pdk select CPU_ARM926EJS @@ -864,6 +869,7 @@ source board/vpac270/Kconfig source board/wandboard/Kconfig source board
[U-Boot] [PATCH v7 7/9] lpc32xx: add lpc32xx-spl.bin boot image target
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- remove script/Makefile.spl change
Changes in v2:
- move boot image generation to mkimage framework
common/image.c | 1 +
include/image.h | 1 +
tools/Makefile | 1 +
tools/lpc32xximage.c | 178 +++
4 files changed, 181 insertions(+)
create mode 100644 tools/lpc32xximage.c
diff --git a/common/image.c b/common/image.c
index a911aa9..162b682 100644
--- a/common/image.c
+++ b/common/image.c
@@ -149,6 +149,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_MXSIMAGE, mxsimage, Freescale MXS Boot Image,},
{ IH_TYPE_ATMELIMAGE, atmelimage, ATMEL ROM-Boot Image,},
{ IH_TYPE_X86_SETUP, x86_setup, x86 setup.bin,},
+ { IH_TYPE_LPC32XXIMAGE, lpc32xximage, LPC32XX Boot Image, },
{ -1, , , },
};
diff --git a/include/image.h b/include/image.h
index 0e6af00..3844be6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -242,6 +242,7 @@ struct lmb;
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */
+#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
/*
* Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 88770b0..4bbb153 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -83,6 +83,7 @@ dumpimage-mkimage-objs := aisimage.o \
imximage.o \
kwbimage.o \
lib/md5.o \
+ lpc32xximage.o \
mxsimage.o \
omapimage.o \
os_support.o \
diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c
new file mode 100644
index 000..6b3865f
--- /dev/null
+++ b/tools/lpc32xximage.c
@@ -0,0 +1,178 @@
+/*
+ * Image manipulator for LPC32XX SoCs
+ *
+ * (C) Copyright 2015 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Derived from omapimage.c:
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby john.ri...@linaro.org
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sba...@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include imagetool.h
+#include compiler.h
+#include image.h
+
+/*
+ * NAND page 0 boot header
+ */
+
+struct nand_page_0_boot_header {
+ uint32_t data[129];
+ uint32_t pad[383];
+};
+
+/*
+ * Default ICC (interface configuration data [sic]) if none specified
+ * in board config
+ */
+
+#ifndef LPC32XX_BOOT_ICR
+#define LPC32XX_BOOT_ICR 0x0096
+#endif
+
+/*
+ * Default boot NAND page size if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGESIZE
+#define LPC32XX_BOOT_NAND_PAGESIZE 2048
+#endif
+
+/*
+ * Default boot NAND pages per sector if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR
+#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64
+#endif
+
+/*
+ * Maximum size for boot code is 56K unless defined in board config
+ */
+
+#ifndef LPC32XX_BOOT_CODESIZE
+#define LPC32XX_BOOT_CODESIZE (56*1024)
+#endif
+
+/* signature byte for a readable block */
+
+#define LPC32XX_BOOT_BLOCK_OK 0xaa
+
+static struct nand_page_0_boot_header lpc32xximage_header;
+
+static int lpc32xximage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_LPC32XXIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int lpc32xximage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+
+ /* turn image size from bytes to NAND pages, page 0 included */
+ int image_size_in_pages = ((image_size - 1)
+ / LPC32XX_BOOT_NAND_PAGESIZE);
+
+ if (hdr-data[0] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[1] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[2] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[3] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[4] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[5] != (0xff ~image_size_in_pages))
+ return -1;
+ if (hdr-data[6] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[7] != (0xff ~image_size_in_pages
[U-Boot] [PATCH v6 1/8] lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v6:
- added some missing readl() wraps
- moved descriptors and buffers to SRAM
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 9 +
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 +
arch/arm/cpu/arm926ejs/lpc32xx/u-boot.lds | 161 +++
arch/arm/include/asm/arch-lpc32xx/config.h| 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/net/Makefile | 1 +
drivers/net/lpc32xx_eth.c | 639 ++
include/netdev.h | 1 +
8 files changed, 822 insertions(+)
create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/u-boot.lds
create mode 100644 drivers/net/lpc32xx_eth.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..eec4d9e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include netdev.h
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/wdt.h
@@ -55,3 +56,11 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..062db8d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -37,3 +37,10 @@ void lpc32xx_uart_init(unsigned int uart_id)
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
clk-u3clk + (uart_id - 3));
}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+ | CLK_MAC_MII, clk-macclk_ctrl);
+}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/u-boot.lds
b/arch/arm/cpu/arm926ejs/lpc32xx/u-boot.lds
new file mode 100644
index 000..84cc4dc
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/u-boot.lds
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, ga...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * .sram0 = first 4K of SRAM, for exception vectors
+ * .sram = next 124K of SRAM, for buffers etc
+ * .sdram = all 128MB of SDRAM (even though mabybe only 64M exist }
+ */
+
+MEMORY { .sram0 : ORIGIN = 0x, LENGTH = 0x1000 }
+MEMORY { .sram : ORIGIN = 0x1000, LENGTH = 0x0001F000 }
+MEMORY { .sdram : ORIGIN = 0x8000, LENGTH = 0x0800 }
+
+#include config.h
+
+OUTPUT_FORMAT(elf32-littlearm, elf32-littlearm, elf32-littlearm)
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+/*
+ * All sections starting in .sram go to... SRAM.
+ */
+ .sram (NOLOAD) : { *(.sram*) } .sram
+/*
+ * The rest goes to SDRAM
+ */
+
+ .text :
+ {
+ *(.__image_copy_start)
+ *(.vectors)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ } .sdram
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) ||
defined(CONFIG_ARMV7_PSCI)
+
+#ifndef CONFIG_ARMV7_SECURE_BASE
+#define CONFIG_ARMV7_SECURE_BASE
+#endif
+
+ .__secure_start : {
+ . = ALIGN(0x1000);
+ *(.__secure_start)
+ } .sdram
+
+ .secure_text CONFIG_ARMV7_SECURE_BASE :
+ AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+ {
+ *(._secure.text)
+ } .sdram
+
+ . = LOADADDR(.__secure_start) +
+ SIZEOF(.__secure_start) +
+ SIZEOF(.secure_text);
+
+ __secure_end_lma = .;
+ .__secure_end : AT(__secure_end_lma) {
+ *(.__secure_end)
+ LONG(0x1d1071c);/* Must output something to reset LMA */
+ } .sdram
+#endif
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } .sdram
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ } .sdram
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } .sdram
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ } .sdram
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ } .sdram
+
+ .rel.dyn : {
+ *(.rel*)
+ } .sdram
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ } .sdram
+
+ .hash : { *(.hash*) } .sdram
+
+ .got.plt : { *(.got*) } .sdram
+
+ .end :
+ {
+ *(.__end)
+ } .sdram
+
+ _image_binary_end = .;
+
+ /*
+* Deprecated: this MMU section is used by pxa
[U-Boot] [PATCH v6 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: A - I2C driver remains non-DM During v2 review, it was suggested to move to DM for I2C. However, this caused issues with the 'date', 'dtt' and 'eeprom' commands which are configured in this board. Therefore the I2C move to DM was not done. B - Some checkpatch diagnostics are not fixed The following warnings checkpatch warnings and checks were not fixed: 1. warning: arch/arm/Kconfig,135: please write a paragraph that describes the config symbol fully Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. check: include/configs/work_92105.h,187: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v6: - added some missing readl() wraps - moved descriptors and buffers to SRAM - rewrite timeout loops - fix bad block skipping in SPL chainload loop - remove '+S:' prefixes from defconfig - use custom LPC32XX linker script - reset peripherals at startup - support 128MB boards Changes in v5: - switch to CONFIG_SYS_NAND_SELF_INIT - switched board NAND config to CONFIG_SYS_NAND_SELF_INIT Changes in v4: - remove two debugging statements - add __iomem to regs struct - remove useless 'else return;' - take BB marker out of free OOB area - replace magic numbers in OOB reads/writes - add timeouts in NAND loops - use DIV_ROUND_UP where applicable - fix erroneous comment - skip bad blocks in SPL chainload loop Changes in v3: - move DM dependency constraint into Kconfig - move regs pointer and function cache into private struct - discourage readers from using functions implementation as an example - move regs and functions in private struct - remove script/Makefile.spl change - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 Makefile | 20 + arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 + arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/cpu/arm926ejs/lpc32xx/u-boot.lds | 161 + arch/arm/include/asm/arch-lpc32xx/clk.h| 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h| 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 +++ board/work-microwave/work_92105/work_92105.c | 77 +++ .../work-microwave/work_92105/work_92105_display.c | 349 ++ .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 + common/image.c | 1 + configs/work_92105_defconfig | 6 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c| 293 + drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 ++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 +++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c| 718 + drivers/net/Makefile | 1 + drivers/net
[U-Boot] [PATCH v6 4/8] lpc32xx: add GPIO support
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- move DM dependency constraint into Kconfig
- move regs pointer and function cache into private struct
- discourage readers from using functions implementation as an example
Changes in v2:
- move from legacy to Driver Model support
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 +
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 293 +++
5 files changed, 349 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..a407098 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include asm/arch/clk.h
#include asm/arch/uart.h
#include asm/io.h
+#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = gpio_lpc32xx
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b609e73..7b5178a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -7,3 +7,10 @@ config DM_GPIO
the GPIO uclass. Drivers provide methods to query the
particular GPIOs that they provide. The uclass interface
is defined in include/asm-generic/gpio.h.
+
+config LPC32XX_GPIO
+ bool LPC32XX GPIO driver
+ depends on DM
+ default n
+ help
+ Support for the LPC32XX GPIO driver.
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fe9a3b2..85f71c5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..96b3125
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,293 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+#include asm-generic/gpio.h
+#include dm.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING #1 **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where a single physical GPIO has differing numbers
+ * for setting its direction, reading it and/or writing to it.
+ *
+ * ** WARNING #2 **
+ *
+ * Please read NOTE
[U-Boot] [PATCH v6 7/8] lpc32xx: add lpc32xx-spl.bin boot image target
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- remove script/Makefile.spl change
Changes in v2:
- move boot image generation to mkimage framework
common/image.c | 1 +
include/image.h | 1 +
tools/Makefile | 1 +
tools/lpc32xximage.c | 178 +++
4 files changed, 181 insertions(+)
create mode 100644 tools/lpc32xximage.c
diff --git a/common/image.c b/common/image.c
index a911aa9..162b682 100644
--- a/common/image.c
+++ b/common/image.c
@@ -149,6 +149,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_MXSIMAGE, mxsimage, Freescale MXS Boot Image,},
{ IH_TYPE_ATMELIMAGE, atmelimage, ATMEL ROM-Boot Image,},
{ IH_TYPE_X86_SETUP, x86_setup, x86 setup.bin,},
+ { IH_TYPE_LPC32XXIMAGE, lpc32xximage, LPC32XX Boot Image, },
{ -1, , , },
};
diff --git a/include/image.h b/include/image.h
index 0e6af00..3844be6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -242,6 +242,7 @@ struct lmb;
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */
+#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
/*
* Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 88770b0..4bbb153 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -83,6 +83,7 @@ dumpimage-mkimage-objs := aisimage.o \
imximage.o \
kwbimage.o \
lib/md5.o \
+ lpc32xximage.o \
mxsimage.o \
omapimage.o \
os_support.o \
diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c
new file mode 100644
index 000..6b3865f
--- /dev/null
+++ b/tools/lpc32xximage.c
@@ -0,0 +1,178 @@
+/*
+ * Image manipulator for LPC32XX SoCs
+ *
+ * (C) Copyright 2015 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Derived from omapimage.c:
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby john.ri...@linaro.org
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sba...@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include imagetool.h
+#include compiler.h
+#include image.h
+
+/*
+ * NAND page 0 boot header
+ */
+
+struct nand_page_0_boot_header {
+ uint32_t data[129];
+ uint32_t pad[383];
+};
+
+/*
+ * Default ICC (interface configuration data [sic]) if none specified
+ * in board config
+ */
+
+#ifndef LPC32XX_BOOT_ICR
+#define LPC32XX_BOOT_ICR 0x0096
+#endif
+
+/*
+ * Default boot NAND page size if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGESIZE
+#define LPC32XX_BOOT_NAND_PAGESIZE 2048
+#endif
+
+/*
+ * Default boot NAND pages per sector if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR
+#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64
+#endif
+
+/*
+ * Maximum size for boot code is 56K unless defined in board config
+ */
+
+#ifndef LPC32XX_BOOT_CODESIZE
+#define LPC32XX_BOOT_CODESIZE (56*1024)
+#endif
+
+/* signature byte for a readable block */
+
+#define LPC32XX_BOOT_BLOCK_OK 0xaa
+
+static struct nand_page_0_boot_header lpc32xximage_header;
+
+static int lpc32xximage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_LPC32XXIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int lpc32xximage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+
+ /* turn image size from bytes to NAND pages, page 0 included */
+ int image_size_in_pages = ((image_size - 1)
+ / LPC32XX_BOOT_NAND_PAGESIZE);
+
+ if (hdr-data[0] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[1] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[2] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[3] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[4] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[5] != (0xff ~image_size_in_pages))
+ return -1;
+ if (hdr-data[6] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[7] != (0xff ~image_size_in_pages))
+ return -1
[U-Boot] [PATCH v6 2/8] lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v6:
- rewrite timeout loops
- fix bad block skipping in SPL chainload loop
Changes in v5:
- switch to CONFIG_SYS_NAND_SELF_INIT
Changes in v4:
- remove two debugging statements
- add __iomem to regs struct
- remove useless 'else return;'
- take BB marker out of free OOB area
- replace magic numbers in OOB reads/writes
- add timeouts in NAND loops
- use DIV_ROUND_UP where applicable
- fix erroneous comment
- skip bad blocks in SPL chainload loop
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/lpc32xx_nand_mlc.c | 718 ++
5 files changed, 730 insertions(+)
create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 062db8d..be4c93d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -44,3 +44,9 @@ void lpc32xx_mac_init(void)
writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
| CLK_MAC_MII, clk-macclk_ctrl);
}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15..bc7d33d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -147,6 +147,10 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 1)
+#define CLK_NAND_MLC_INT (1 5)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a6b8826..0c4e712 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -9,5 +9,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f02bfc..347ea62 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 000..67dd67b
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -0,0 +1,718 @@
+/*
+ * LPC32xx MLC NAND flash controller driver
+ *
+ * (C) Copyright 2014 3ADEV http://3adev.com
+ * Written by Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * NOTE:
+ *
+ * The MLC NAND flash controller provides hardware Reed-Solomon ECC
+ * covering in- and out-of-band data together. Therefore, in- and out-
+ * of-band data must be written together in order to have a valid ECC.
+ *
+ * Consequently, pages with meaningful in-band data are written with
+ * blank (all-ones) out-of-band data and a valid ECC, and any later
+ * out-of-band data write will void the ECC.
+ *
+ * Therefore, code which reads such late-written out-of-band data
+ * should not rely on the ECC validity.
+ */
+
+#include common.h
+#include nand.h
+#include asm/errno.h
+#include asm/io.h
+#include nand.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+
+/*
+ * MLC NAND controller registers.
+ */
+struct lpc32xx_nand_mlc_registers {
+ u8 buff[32768]; /* controller's serial data buffer */
+ u8 data[32768]; /* NAND's raw data buffer */
+ u32 cmd;
+ u32 addr;
+ u32 ecc_enc_reg;
+ u32 ecc_dec_reg;
+ u32 ecc_auto_enc_reg;
+ u32 ecc_auto_dec_reg;
+ u32 rpr;
+ u32 wpr;
+ u32 rubp;
+ u32 robp;
+ u32 sw_wp_add_low;
+ u32 sw_wp_add_hig;
+ u32 icr;
+ u32 time_reg;
+ u32 irq_mr;
+ u32 irq_sr;
+ u32 lock_pr;
+ u32 isr;
+ u32 ceh;
+};
+
+/* LOCK_PR register defines */
+#define LOCK_PR_UNLOCK_KEY 0xA25E /* Magic
[U-Boot] [PATCH v6 3/8] lpc32xx: i2c: add LPC32xx I2C interface support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/i2c/Makefile | 1 +
drivers/i2c/lpc32xx_i2c.c | 249 ++
6 files changed, 268 insertions(+)
create mode 100644 drivers/i2c/lpc32xx_i2c.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index be4c93d..81b53ea 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void)
/* Enable NAND interface */
writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(clk-i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, clk-i2cclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index bc7d33d..781ac07 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -123,6 +123,10 @@ struct clk_pm_regs {
#define CLK_MAC_SLAVE (1 1)
#define CLK_MAC_REG(1 0)
+/* I2C Clock Control Register bits */
+#define CLK_I2C2_ENABLE(1 1)
+#define CLK_I2C1_ENABLE(1 0)
+
/* Timer Clock Control1 Register bits */
#define CLK_TIMCLK_MOTOR (1 6)
#define CLK_TIMCLK_TIMER3 (1 5)
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h
b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a0..1067107 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -37,6 +37,8 @@
#define UART4_BASE 0x40088000 /* UART 4 registers base*/
#define UART5_BASE 0x4009 /* UART 5 registers base*/
#define UART6_BASE 0x40098000 /* UART 6 registers base*/
+#define I2C1_BASE 0x400A /* I2C 1 registers base*/
+#define I2C2_BASE 0x400A8000 /* I2C 2 registers base*/
/* External SDRAM Memory Bank base addresses */
#define EMC_DYCS0_BASE 0x8000 /* SDRAM DYCS0 base address */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 0c4e712..a4a05d1 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -10,5 +10,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 774bc94..26ea854 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
new file mode 100644
index 000..78d26e4
--- /dev/null
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -0,0 +1,249 @@
+/*
+ * LPC32xx I2C interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include i2c.h
+#include asm/errno.h
+#include asm/arch/clk.h
+
+/*
+ * Provide default speed and slave if target did not
+ */
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
+#define CONFIG_SYS_I2C_LPC32XX_SPEED 35
+#endif
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
+#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
+#endif
+
+/* i2c register set */
+struct lpc32xx_i2c_registers {
+ union {
+ u32 rx;
+ u32 tx;
+ };
+ u32 stat;
+ u32 ctrl;
+ u32 clk_hi;
+ u32 clk_lo;
+ u32 adr;
+ u32 rxfl;
+ u32 txfl;
+ u32 rxb;
+ u32 txb;
+ u32 stx;
+ u32 stxfl;
+};
+
+/* TX register fields */
+#define LPC32XX_I2C_TX_START 0x0100
+#define LPC32XX_I2C_TX_STOP0x0200
+
+/* Control register values */
+#define LPC32XX_I2C_SOFT_RESET 0x0100
+
+/* Status register values */
+#define
[U-Boot] [PATCH v6 5/8] lpc32xx: add LPC32xx SSP support (SPI mode)
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- move regs and functions in private struct
Changes in v2:
- added MUX setting for SSP0
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/lpc32xx_ssp.c | 144 ++
5 files changed, 163 insertions(+)
create mode 100644 drivers/spi/lpc32xx_ssp.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index a407098..5a453e3 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -8,11 +8,13 @@
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/uart.h
+#include asm/arch/mux.h
#include asm/io.h
#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
void lpc32xx_uart_init(unsigned int uart_id)
{
@@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum)
U_BOOT_DEVICE(lpc32xx_gpios) = {
.name = gpio_lpc32xx
};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, clk-ssp_ctrl);
+ /* Mux SSP0 pins */
+ writel(P_MUX_SET_SSP0, mux-p_mux_set);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 781ac07..2cb5703 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -155,6 +155,9 @@ struct clk_pm_regs {
#define CLK_NAND_MLC (1 1)
#define CLK_NAND_MLC_INT (1 5)
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 0)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a4a05d1..86d5ee9 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..ce6f1cc 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
new file mode 100644
index 000..0fc44a0
--- /dev/null
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -0,0 +1,144 @@
+/*
+ * LPC32xx SSP interface (SPI mode)
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/compat.h
+#include asm/io.h
+#include malloc.h
+#include spi.h
+#include asm/arch/clk.h
+
+/* SSP chip registers */
+struct ssp_regs {
+ u32 cr0;
+ u32 cr1;
+ u32 data;
+ u32 sr;
+ u32 cpsr;
+ u32 imsc;
+ u32 ris;
+ u32 mis;
+ u32 icr;
+ u32 dmacr;
+};
+
+/* CR1 register defines */
+#define SSP_CR1_SSP_ENABLE 0x0002
+
+/* SR register defines */
+#define SSP_SR_TNF 0x0002
+/* SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE 0x0004
+
+/* zynq spi slave */
+struct lpc32xx_spi_slave {
+ struct spi_slave slave;
+ struct ssp_regs *regs;
+};
+
+static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave(
+ struct spi_slave *slave)
+{
+ return container_of(slave, struct lpc32xx_spi_slave, slave);
+}
+
+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
+void spi_init(void)
+{
+ /*
+* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
+* and configuration will be done in spi_setup_slave()
+ */
+}
+
+/* the following is called in sequence by do_spi_xfer() */
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+ struct lpc32xx_spi_slave *lslave;
+
+ /* we only set up SSP0 for now, so ignore bus */
+
+ if (mode SPI_3WIRE) {
+ error(3-wire mode
[U-Boot] [PATCH v6 6/8] dtt: add ds620 support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- cosmetic: added a blank line before copyright
drivers/hwmon/Makefile | 1 +
drivers/hwmon/ds620.c | 65 ++
include/dtt.h | 15 ++--
3 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 drivers/hwmon/ds620.c
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 25b8e8a..b4fb057 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_DTT_ADT7460) += adt7460.o
obj-$(CONFIG_DTT_DS1621) += ds1621.o
obj-$(CONFIG_DTT_DS1722) += ds1722.o
obj-$(CONFIG_DTT_DS1775) += ds1775.o
+obj-$(CONFIG_DTT_DS620) += ds620.o
obj-$(CONFIG_DTT_LM63) += lm63.o
obj-$(CONFIG_DTT_LM73) += lm73.o
obj-$(CONFIG_DTT_LM75) += lm75.o
diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c
new file mode 100644
index 000..1ecc3da
--- /dev/null
+++ b/drivers/hwmon/ds620.c
@@ -0,0 +1,65 @@
+/*
+ * DS620 DTT support
+ *
+ * (C) Copyright 2014 3ADEV http://www.3adev.com
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
+ */
+
+#include common.h
+#include i2c.h
+#include dtt.h
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48
+#define DTT_START_CONVERT 0x51
+#define DTT_TEMP 0xAA
+#define DTT_CONFIG 0xAC
+
+/*
+ * Config register MSB bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_AUTOC 0x02
+#define DTT_CONFIG_R0 0x04 /* always 1 */
+#define DTT_CONFIG_R1 0x08 /* always 1 */
+#define DTT_CONFIG_TLF 0x10
+#define DTT_CONFIG_THF 0x20
+#define DTT_CONFIG_NVB 0x40
+#define DTT_CONFIG_DONE0x80
+
+#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor 0x07))
+
+int dtt_init_one(int sensor)
+{
+ uint8_t config = DTT_CONFIG_1SHOT
+ | DTT_CONFIG_R0
+ | DTT_CONFIG_R1;
+ return i2c_write(CHIP(sensor), DTT_CONFIG, 1, config, 1);
+}
+
+int dtt_get_temp(int sensor)
+{
+ uint8_t status;
+ uint8_t temp[2];
+
+ /* Start a conversion, may take up to 1 second. */
+ i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0);
+ do {
+ if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, status, 1))
+ /* bail out if I2C error */
+ status |= DTT_CONFIG_DONE;
+ } while (!(status DTT_CONFIG_DONE));
+ if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2))
+ /* bail out if I2C error */
+ return -274; /* below absolute zero == error */
+
+ return ((int16_t)(temp[1] | (temp[0] 8))) 7;
+}
diff --git a/include/dtt.h b/include/dtt.h
index 058bca4..173159d 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -12,13 +12,14 @@
#define _DTT_H_
#if defined(CONFIG_DTT_ADM1021)|| \
-defined(CONFIG_DTT_ADT7460)|| \
-defined(CONFIG_DTT_DS1621) || \
-defined(CONFIG_DTT_DS1775) || \
-defined(CONFIG_DTT_LM63) || \
-defined(CONFIG_DTT_LM73) || \
-defined(CONFIG_DTT_LM75) || \
-defined(CONFIG_DTT_LM81)
+ defined(CONFIG_DTT_ADT7460) || \
+ defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
+ defined(CONFIG_DTT_DS620) || \
+ defined(CONFIG_DTT_LM63)|| \
+ defined(CONFIG_DTT_LM73)|| \
+ defined(CONFIG_DTT_LM75)|| \
+ defined(CONFIG_DTT_LM81)
#define CONFIG_DTT /* We have a DTT */
--
2.1.0
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[U-Boot] [PATCH v6 8/8] lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- Changes in v6: - remove '+S:' prefixes from defconfig - use custom LPC32XX linker script - reset peripherals at startup - support 128MB boards Changes in v5: - switched board NAND config to CONFIG_SYS_NAND_SELF_INIT Changes in v4: None Changes in v3: - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: None Makefile | 20 ++ arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 4 + arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 + arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 +++ arch/arm/include/asm/arch-lpc32xx/clk.h| 5 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 1 + arch/arm/include/asm/arch-lpc32xx/mux.h| 18 ++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 4 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 ++ board/work-microwave/work_92105/work_92105.c | 77 + .../work-microwave/work_92105/work_92105_display.c | 349 + .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 ++ configs/work_92105_defconfig | 6 + include/configs/work_92105.h | 268 21 files changed, 1086 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 board/work-microwave/work_92105/work_92105_spl.c create mode 100644 configs/work_92105_defconfig create mode 100644 include/configs/work_92105.h diff --git a/Makefile b/Makefile index 1b3ebe7..98b3cd8 100644 --- a/Makefile +++ b/Makefile @@ -896,6 +896,26 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) +MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) + +lpc32xx-spl.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-0.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-1.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img + $(call if_changed,cat) + +CLEAN_FILES += lpc32xx-* + OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ --pad-to=$(CONFIG_TPL_PAD_TO) tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b9ebee1..10d9280 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -132,6 +132,11 @@ config TARGET_DEVKIT3250 bool Support devkit3250 select CPU_ARM926EJS +config TARGET_WORK_92105 + bool Support work_92105 + select CPU_ARM926EJS + select SUPPORT_SPL + config TARGET_MX25PDK bool Support mx25pdk select CPU_ARM926EJS @@ -871,6 +876,7 @@ source board/vpac270/Kconfig source board/wandboard/Kconfig source board/warp/Kconfig source board/woodburn/Kconfig +source board/work-microwave/work_92105/Kconfig source board
[U-Boot] [PATCH v5 5/8] lpc32xx: add LPC32xx SSP support (SPI mode)
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- move regs and functions in private struct
Changes in v2:
- added MUX setting for SSP0
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/lpc32xx_ssp.c | 144 ++
5 files changed, 163 insertions(+)
create mode 100644 drivers/spi/lpc32xx_ssp.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index a407098..5a453e3 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -8,11 +8,13 @@
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/uart.h
+#include asm/arch/mux.h
#include asm/io.h
#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
void lpc32xx_uart_init(unsigned int uart_id)
{
@@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum)
U_BOOT_DEVICE(lpc32xx_gpios) = {
.name = gpio_lpc32xx
};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, clk-ssp_ctrl);
+ /* Mux SSP0 pins */
+ writel(P_MUX_SET_SSP0, mux-p_mux_set);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 781ac07..2cb5703 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -155,6 +155,9 @@ struct clk_pm_regs {
#define CLK_NAND_MLC (1 1)
#define CLK_NAND_MLC_INT (1 5)
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 0)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a4a05d1..86d5ee9 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..ce6f1cc 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
new file mode 100644
index 000..0fc44a0
--- /dev/null
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -0,0 +1,144 @@
+/*
+ * LPC32xx SSP interface (SPI mode)
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/compat.h
+#include asm/io.h
+#include malloc.h
+#include spi.h
+#include asm/arch/clk.h
+
+/* SSP chip registers */
+struct ssp_regs {
+ u32 cr0;
+ u32 cr1;
+ u32 data;
+ u32 sr;
+ u32 cpsr;
+ u32 imsc;
+ u32 ris;
+ u32 mis;
+ u32 icr;
+ u32 dmacr;
+};
+
+/* CR1 register defines */
+#define SSP_CR1_SSP_ENABLE 0x0002
+
+/* SR register defines */
+#define SSP_SR_TNF 0x0002
+/* SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE 0x0004
+
+/* zynq spi slave */
+struct lpc32xx_spi_slave {
+ struct spi_slave slave;
+ struct ssp_regs *regs;
+};
+
+static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave(
+ struct spi_slave *slave)
+{
+ return container_of(slave, struct lpc32xx_spi_slave, slave);
+}
+
+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
+void spi_init(void)
+{
+ /*
+* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
+* and configuration will be done in spi_setup_slave()
+ */
+}
+
+/* the following is called in sequence by do_spi_xfer() */
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+ struct lpc32xx_spi_slave *lslave;
+
+ /* we only set up SSP0 for now, so ignore bus */
+
+ if (mode SPI_3WIRE) {
+ error(3-wire mode not supported
[U-Boot] [PATCH v5 4/8] lpc32xx: add GPIO support
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- move DM dependency constraint into Kconfig
- move regs pointer and function cache into private struct
- discourage readers from using functions implementation as an example
Changes in v2:
- move from legacy to Driver Model support
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 +
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 293 +++
5 files changed, 349 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..a407098 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include asm/arch/clk.h
#include asm/arch/uart.h
#include asm/io.h
+#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = gpio_lpc32xx
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b609e73..7b5178a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -7,3 +7,10 @@ config DM_GPIO
the GPIO uclass. Drivers provide methods to query the
particular GPIOs that they provide. The uclass interface
is defined in include/asm-generic/gpio.h.
+
+config LPC32XX_GPIO
+ bool LPC32XX GPIO driver
+ depends on DM
+ default n
+ help
+ Support for the LPC32XX GPIO driver.
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fe9a3b2..85f71c5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..96b3125
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,293 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+#include asm-generic/gpio.h
+#include dm.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING #1 **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where a single physical GPIO has differing numbers
+ * for setting its direction, reading it and/or writing to it.
+ *
+ * ** WARNING #2 **
+ *
+ * Please read NOTE in description
[U-Boot] [PATCH v5 1/8] lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 9 +
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 +
arch/arm/include/asm/arch-lpc32xx/config.h| 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/net/Makefile | 1 +
drivers/net/lpc32xx_eth.c | 636 ++
include/netdev.h | 1 +
7 files changed, 658 insertions(+)
create mode 100644 drivers/net/lpc32xx_eth.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..eec4d9e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include netdev.h
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/wdt.h
@@ -55,3 +56,11 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..062db8d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -37,3 +37,10 @@ void lpc32xx_uart_init(unsigned int uart_id)
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
clk-u3clk + (uart_id - 3));
}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+ | CLK_MAC_MII, clk-macclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h
b/arch/arm/include/asm/arch-lpc32xx/config.h
index 564441c..d57bc48 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -52,6 +52,9 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
/* NOR Flash */
#if defined(CONFIG_SYS_FLASH_CFI)
#define CONFIG_FLASH_CFI_DRIVER
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 28812be..a6b8826 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -8,5 +8,6 @@
#define _LPC32XX_SYS_PROTO_H
void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b8b0803..af8941f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_GRETH) += greth.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
+obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
new file mode 100644
index 000..16c8ef0
--- /dev/null
+++ b/drivers/net/lpc32xx_eth.c
@@ -0,0 +1,636 @@
+/*
+ * LPC32xx Ethernet MAC interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include net.h
+#include malloc.h
+#include miiphy.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/types.h
+#include asm/system.h
+#include asm/byteorder.h
+#include asm/arch/cpu.h
+#include asm/arch/config.h
+
+/*
+ * Notes:
+ *
+ * 1. Unless specified otherwise, all references to tables or paragraphs
+ *are to UM10326, LPC32x0 and LPC32x0/01 User manual.
+ *
+ * 2. Only bitfield masks/values which are actually used by the driver
+ *are defined.
+ */
+
+/* a single RX descriptor. The controller has an array of these */
+struct lpc32xx_eth_rxdesc {
+ u32 packet; /* Receive packet pointer */
+ u32 control;/* Descriptor command status */
+};
+
+#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
+
+/* RX control bitfields/masks (see Table 330) */
+#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x07FF
+#define LPC32XX_ETH_RX_CTRL_UNUSED0x7800
+#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x8000
+
+/* a single RX status. The controller has an array of these */
+struct lpc32xx_eth_rxstat {
+ u32 statusinfo; /* Transmit Descriptor status */
+ u32 statushashcrc; /* Transmit Descriptor CRCs */
+};
+
+#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
+
+/* RX statusinfo bitfields/masks (see Table 333) */
+#define RX_STAT_RXSIZE 0x07FF
+/* Helper: OR of all errors except RANGE */
+#define RX_STAT_ERRORS
[U-Boot] [PATCH v5 3/8] lpc32xx: i2c: add LPC32xx I2C interface support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/i2c/Makefile | 1 +
drivers/i2c/lpc32xx_i2c.c | 249 ++
6 files changed, 268 insertions(+)
create mode 100644 drivers/i2c/lpc32xx_i2c.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index be4c93d..81b53ea 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void)
/* Enable NAND interface */
writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(clk-i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, clk-i2cclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index bc7d33d..781ac07 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -123,6 +123,10 @@ struct clk_pm_regs {
#define CLK_MAC_SLAVE (1 1)
#define CLK_MAC_REG(1 0)
+/* I2C Clock Control Register bits */
+#define CLK_I2C2_ENABLE(1 1)
+#define CLK_I2C1_ENABLE(1 0)
+
/* Timer Clock Control1 Register bits */
#define CLK_TIMCLK_MOTOR (1 6)
#define CLK_TIMCLK_TIMER3 (1 5)
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h
b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a0..1067107 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -37,6 +37,8 @@
#define UART4_BASE 0x40088000 /* UART 4 registers base*/
#define UART5_BASE 0x4009 /* UART 5 registers base*/
#define UART6_BASE 0x40098000 /* UART 6 registers base*/
+#define I2C1_BASE 0x400A /* I2C 1 registers base*/
+#define I2C2_BASE 0x400A8000 /* I2C 2 registers base*/
/* External SDRAM Memory Bank base addresses */
#define EMC_DYCS0_BASE 0x8000 /* SDRAM DYCS0 base address */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 0c4e712..a4a05d1 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -10,5 +10,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 774bc94..26ea854 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
new file mode 100644
index 000..78d26e4
--- /dev/null
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -0,0 +1,249 @@
+/*
+ * LPC32xx I2C interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include i2c.h
+#include asm/errno.h
+#include asm/arch/clk.h
+
+/*
+ * Provide default speed and slave if target did not
+ */
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
+#define CONFIG_SYS_I2C_LPC32XX_SPEED 35
+#endif
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
+#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
+#endif
+
+/* i2c register set */
+struct lpc32xx_i2c_registers {
+ union {
+ u32 rx;
+ u32 tx;
+ };
+ u32 stat;
+ u32 ctrl;
+ u32 clk_hi;
+ u32 clk_lo;
+ u32 adr;
+ u32 rxfl;
+ u32 txfl;
+ u32 rxb;
+ u32 txb;
+ u32 stx;
+ u32 stxfl;
+};
+
+/* TX register fields */
+#define LPC32XX_I2C_TX_START 0x0100
+#define LPC32XX_I2C_TX_STOP0x0200
+
+/* Control register values */
+#define LPC32XX_I2C_SOFT_RESET 0x0100
+
+/* Status register values */
+#define LPC32XX_I2C_STAT_TFF
[U-Boot] [PATCH v5 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: A - I2C driver remains non-DM During v2 review, it was suggested to move to DM for I2C. However, this caused issues with the 'date', 'dtt' and 'eeprom' commands which are configured in this board. Therefore the I2C move to DM was not done. B - Some checkpatch diagnostics are not fixed The following warnings checkpatch warnings and checks were not fixed: 1. warning: arch/arm/Kconfig,135: please write a paragraph that describes the config symbol fully Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. check: include/configs/work_92105.h,187: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v5: - switch to CONFIG_SYS_NAND_SELF_INIT - switched board NAND config to CONFIG_SYS_NAND_SELF_INIT Changes in v4: - remove two debugging statements - add __iomem to regs struct - remove useless 'else return;' - take BB marker out of free OOB area - replace magic numbers in OOB reads/writes - add timeouts in NAND loops - use DIV_ROUND_UP where applicable - fix erroneous comment - skip bad blocks in SPL chainload loop Changes in v3: - move DM dependency constraint into Kconfig - move regs pointer and function cache into private struct - discourage readers from using functions implementation as an example - move regs and functions in private struct - remove script/Makefile.spl change - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 Makefile | 20 + arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h| 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h| 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 +++ board/work-microwave/work_92105/work_92105.c | 62 ++ .../work-microwave/work_92105/work_92105_display.c | 349 +++ .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 + common/image.c | 1 + configs/work_92105_defconfig | 5 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c| 293 + drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 ++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c| 674 + drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 636 +++ drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 144 + include/configs/work_92105.h | 268 include/dtt.h | 15 +- include/image.h
[U-Boot] [PATCH v5 2/8] lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v5:
- switch to CONFIG_SYS_NAND_SELF_INIT
Changes in v4:
- remove two debugging statements
- add __iomem to regs struct
- remove useless 'else return;'
- take BB marker out of free OOB area
- replace magic numbers in OOB reads/writes
- add timeouts in NAND loops
- use DIV_ROUND_UP where applicable
- fix erroneous comment
- skip bad blocks in SPL chainload loop
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/lpc32xx_nand_mlc.c | 674 ++
5 files changed, 686 insertions(+)
create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 062db8d..be4c93d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -44,3 +44,9 @@ void lpc32xx_mac_init(void)
writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
| CLK_MAC_MII, clk-macclk_ctrl);
}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15..bc7d33d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -147,6 +147,10 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 1)
+#define CLK_NAND_MLC_INT (1 5)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a6b8826..0c4e712 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -9,5 +9,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f02bfc..347ea62 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 000..6b376c4
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -0,0 +1,674 @@
+/*
+ * LPC32xx MLC NAND flash controller driver
+ *
+ * (C) Copyright 2014 3ADEV http://3adev.com
+ * Written by Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * NOTE:
+ *
+ * The MLC NAND flash controller provides hardware Reed-Solomon ECC
+ * covering in- and out-of-band data together. Therefore, in- and out-
+ * of-band data must be written together in order to have a valid ECC.
+ *
+ * Consequently, pages with meaningful in-band data are written with
+ * blank (all-ones) out-of-band data and a valid ECC, and any later
+ * out-of-band data write will void the ECC.
+ *
+ * Therefore, code which reads such late-written out-of-band data
+ * should not rely on the ECC validity.
+ */
+
+#include common.h
+#include nand.h
+#include asm/errno.h
+#include asm/io.h
+#include nand.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+
+/*
+ * MLC NAND controller registers.
+ */
+struct lpc32xx_nand_mlc_registers {
+ u8 buff[32768]; /* controller's serial data buffer */
+ u8 data[32768]; /* NAND's raw data buffer */
+ u32 cmd;
+ u32 addr;
+ u32 ecc_enc_reg;
+ u32 ecc_dec_reg;
+ u32 ecc_auto_enc_reg;
+ u32 ecc_auto_dec_reg;
+ u32 rpr;
+ u32 wpr;
+ u32 rubp;
+ u32 robp;
+ u32 sw_wp_add_low;
+ u32 sw_wp_add_hig;
+ u32 icr;
+ u32 time_reg;
+ u32 irq_mr;
+ u32 irq_sr;
+ u32 lock_pr;
+ u32 isr;
+ u32 ceh;
+};
+
+/* LOCK_PR register defines */
+#define LOCK_PR_UNLOCK_KEY 0xA25E /* Magic unlock value */
+
+/* ICR defines */
+#define ICR_LARGE_BLOCKS 0x0004
[U-Boot] [PATCH v5 8/8] lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- Changes in v5: - switched board NAND config to CONFIG_SYS_NAND_SELF_INIT Changes in v4: None Changes in v3: - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: None Makefile | 20 ++ arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 4 + arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 + arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 +++ arch/arm/include/asm/arch-lpc32xx/clk.h| 5 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 1 + arch/arm/include/asm/arch-lpc32xx/mux.h| 18 ++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 4 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 ++ board/work-microwave/work_92105/work_92105.c | 62 .../work-microwave/work_92105/work_92105_display.c | 349 + .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 ++ configs/work_92105_defconfig | 5 + include/configs/work_92105.h | 268 21 files changed, 1070 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 board/work-microwave/work_92105/work_92105_spl.c create mode 100644 configs/work_92105_defconfig create mode 100644 include/configs/work_92105.h diff --git a/Makefile b/Makefile index 9747bd2..6013712 100644 --- a/Makefile +++ b/Makefile @@ -896,6 +896,26 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) +MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) + +lpc32xx-spl.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-0.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-1.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img + $(call if_changed,cat) + +CLEAN_FILES += lpc32xx-* + OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ --pad-to=$(CONFIG_TPL_PAD_TO) tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b9ebee1..10d9280 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -132,6 +132,11 @@ config TARGET_DEVKIT3250 bool Support devkit3250 select CPU_ARM926EJS +config TARGET_WORK_92105 + bool Support work_92105 + select CPU_ARM926EJS + select SUPPORT_SPL + config TARGET_MX25PDK bool Support mx25pdk select CPU_ARM926EJS @@ -871,6 +876,7 @@ source board/vpac270/Kconfig source board/wandboard/Kconfig source board/warp/Kconfig source board/woodburn/Kconfig +source board/work-microwave/work_92105/Kconfig source board/xaeniax/Kconfig source board/xilinx/zynqmp/Kconfig source board/zipitz2/Kconfig diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu
[U-Boot] [PATCH v5 7/8] lpc32xx: add lpc32xx-spl.bin boot image target
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- remove script/Makefile.spl change
Changes in v2:
- move boot image generation to mkimage framework
common/image.c | 1 +
include/image.h | 1 +
tools/Makefile | 1 +
tools/lpc32xximage.c | 178 +++
4 files changed, 181 insertions(+)
create mode 100644 tools/lpc32xximage.c
diff --git a/common/image.c b/common/image.c
index a911aa9..162b682 100644
--- a/common/image.c
+++ b/common/image.c
@@ -149,6 +149,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_MXSIMAGE, mxsimage, Freescale MXS Boot Image,},
{ IH_TYPE_ATMELIMAGE, atmelimage, ATMEL ROM-Boot Image,},
{ IH_TYPE_X86_SETUP, x86_setup, x86 setup.bin,},
+ { IH_TYPE_LPC32XXIMAGE, lpc32xximage, LPC32XX Boot Image, },
{ -1, , , },
};
diff --git a/include/image.h b/include/image.h
index 0e6af00..3844be6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -242,6 +242,7 @@ struct lmb;
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */
+#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
/*
* Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 88770b0..4bbb153 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -83,6 +83,7 @@ dumpimage-mkimage-objs := aisimage.o \
imximage.o \
kwbimage.o \
lib/md5.o \
+ lpc32xximage.o \
mxsimage.o \
omapimage.o \
os_support.o \
diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c
new file mode 100644
index 000..6b3865f
--- /dev/null
+++ b/tools/lpc32xximage.c
@@ -0,0 +1,178 @@
+/*
+ * Image manipulator for LPC32XX SoCs
+ *
+ * (C) Copyright 2015 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Derived from omapimage.c:
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby john.ri...@linaro.org
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sba...@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include imagetool.h
+#include compiler.h
+#include image.h
+
+/*
+ * NAND page 0 boot header
+ */
+
+struct nand_page_0_boot_header {
+ uint32_t data[129];
+ uint32_t pad[383];
+};
+
+/*
+ * Default ICC (interface configuration data [sic]) if none specified
+ * in board config
+ */
+
+#ifndef LPC32XX_BOOT_ICR
+#define LPC32XX_BOOT_ICR 0x0096
+#endif
+
+/*
+ * Default boot NAND page size if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGESIZE
+#define LPC32XX_BOOT_NAND_PAGESIZE 2048
+#endif
+
+/*
+ * Default boot NAND pages per sector if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR
+#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64
+#endif
+
+/*
+ * Maximum size for boot code is 56K unless defined in board config
+ */
+
+#ifndef LPC32XX_BOOT_CODESIZE
+#define LPC32XX_BOOT_CODESIZE (56*1024)
+#endif
+
+/* signature byte for a readable block */
+
+#define LPC32XX_BOOT_BLOCK_OK 0xaa
+
+static struct nand_page_0_boot_header lpc32xximage_header;
+
+static int lpc32xximage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_LPC32XXIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int lpc32xximage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+
+ /* turn image size from bytes to NAND pages, page 0 included */
+ int image_size_in_pages = ((image_size - 1)
+ / LPC32XX_BOOT_NAND_PAGESIZE);
+
+ if (hdr-data[0] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[1] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[2] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[3] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[4] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[5] != (0xff ~image_size_in_pages))
+ return -1;
+ if (hdr-data[6] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[7] != (0xff ~image_size_in_pages))
+ return -1;
+ if (hdr-data
[U-Boot] [PATCH v5 6/8] dtt: add ds620 support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- cosmetic: added a blank line before copyright
drivers/hwmon/Makefile | 1 +
drivers/hwmon/ds620.c | 65 ++
include/dtt.h | 15 ++--
3 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 drivers/hwmon/ds620.c
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 25b8e8a..b4fb057 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_DTT_ADT7460) += adt7460.o
obj-$(CONFIG_DTT_DS1621) += ds1621.o
obj-$(CONFIG_DTT_DS1722) += ds1722.o
obj-$(CONFIG_DTT_DS1775) += ds1775.o
+obj-$(CONFIG_DTT_DS620) += ds620.o
obj-$(CONFIG_DTT_LM63) += lm63.o
obj-$(CONFIG_DTT_LM73) += lm73.o
obj-$(CONFIG_DTT_LM75) += lm75.o
diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c
new file mode 100644
index 000..1ecc3da
--- /dev/null
+++ b/drivers/hwmon/ds620.c
@@ -0,0 +1,65 @@
+/*
+ * DS620 DTT support
+ *
+ * (C) Copyright 2014 3ADEV http://www.3adev.com
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
+ */
+
+#include common.h
+#include i2c.h
+#include dtt.h
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48
+#define DTT_START_CONVERT 0x51
+#define DTT_TEMP 0xAA
+#define DTT_CONFIG 0xAC
+
+/*
+ * Config register MSB bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_AUTOC 0x02
+#define DTT_CONFIG_R0 0x04 /* always 1 */
+#define DTT_CONFIG_R1 0x08 /* always 1 */
+#define DTT_CONFIG_TLF 0x10
+#define DTT_CONFIG_THF 0x20
+#define DTT_CONFIG_NVB 0x40
+#define DTT_CONFIG_DONE0x80
+
+#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor 0x07))
+
+int dtt_init_one(int sensor)
+{
+ uint8_t config = DTT_CONFIG_1SHOT
+ | DTT_CONFIG_R0
+ | DTT_CONFIG_R1;
+ return i2c_write(CHIP(sensor), DTT_CONFIG, 1, config, 1);
+}
+
+int dtt_get_temp(int sensor)
+{
+ uint8_t status;
+ uint8_t temp[2];
+
+ /* Start a conversion, may take up to 1 second. */
+ i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0);
+ do {
+ if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, status, 1))
+ /* bail out if I2C error */
+ status |= DTT_CONFIG_DONE;
+ } while (!(status DTT_CONFIG_DONE));
+ if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2))
+ /* bail out if I2C error */
+ return -274; /* below absolute zero == error */
+
+ return ((int16_t)(temp[1] | (temp[0] 8))) 7;
+}
diff --git a/include/dtt.h b/include/dtt.h
index 058bca4..173159d 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -12,13 +12,14 @@
#define _DTT_H_
#if defined(CONFIG_DTT_ADM1021)|| \
-defined(CONFIG_DTT_ADT7460)|| \
-defined(CONFIG_DTT_DS1621) || \
-defined(CONFIG_DTT_DS1775) || \
-defined(CONFIG_DTT_LM63) || \
-defined(CONFIG_DTT_LM73) || \
-defined(CONFIG_DTT_LM75) || \
-defined(CONFIG_DTT_LM81)
+ defined(CONFIG_DTT_ADT7460) || \
+ defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
+ defined(CONFIG_DTT_DS620) || \
+ defined(CONFIG_DTT_LM63)|| \
+ defined(CONFIG_DTT_LM73)|| \
+ defined(CONFIG_DTT_LM75)|| \
+ defined(CONFIG_DTT_LM81)
#define CONFIG_DTT /* We have a DTT */
--
2.1.0
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[U-Boot] [PATCH v4 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: A - I2C driver remains non-DM During v2 review, it was suggested to move to DM for I2C. However, this caused issues with the 'date', 'dtt' and 'eeprom' commands which are configured in this board. Therefore the I2C move to DM was not done. B - Some checkpatch diagnostics are not fixed The following warnings checkpatch warnings and checks were not fixed: 1. warning: arch/arm/Kconfig,135: please write a paragraph that describes the config symbol fully Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. check: include/configs/work_92105.h,185: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v4: - remove two debugging statements - add __iomem to regs struct - remove useless 'else return;' - take BB marker out of free OOB area - replace magic numbers in OOB reads/writes - add timeouts in NAND loops - use DIV_ROUND_UP where applicable - fix erroneous comment - skip bad blocks in SPL chainload loop Changes in v3: - move DM dependency constraint into Kconfig - move regs pointer and function cache into private struct - discourage readers from using functions implementation as an example - move regs and functions in private struct - remove script/Makefile.spl change - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 Makefile | 20 + arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h| 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h| 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 +++ board/work-microwave/work_92105/work_92105.c | 62 ++ .../work-microwave/work_92105/work_92105_display.c | 349 +++ .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 ++ common/image.c | 1 + configs/work_92105_defconfig | 5 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c| 293 ++ drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 +++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c| 644 + drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 636 drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 144 + include/configs/work_92105.h | 266 + include/dtt.h | 15 +- include/image.h| 1 + include/netdev.h | 1 + tools/Makefile
[U-Boot] [PATCH v4 1/8] lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 9 +
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 +
arch/arm/include/asm/arch-lpc32xx/config.h| 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/net/Makefile | 1 +
drivers/net/lpc32xx_eth.c | 636 ++
include/netdev.h | 1 +
7 files changed, 658 insertions(+)
create mode 100644 drivers/net/lpc32xx_eth.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..eec4d9e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include netdev.h
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/wdt.h
@@ -55,3 +56,11 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..062db8d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -37,3 +37,10 @@ void lpc32xx_uart_init(unsigned int uart_id)
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
clk-u3clk + (uart_id - 3));
}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+ | CLK_MAC_MII, clk-macclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h
b/arch/arm/include/asm/arch-lpc32xx/config.h
index 564441c..d57bc48 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -52,6 +52,9 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
/* NOR Flash */
#if defined(CONFIG_SYS_FLASH_CFI)
#define CONFIG_FLASH_CFI_DRIVER
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 28812be..a6b8826 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -8,5 +8,6 @@
#define _LPC32XX_SYS_PROTO_H
void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b8b0803..af8941f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_GRETH) += greth.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
+obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
new file mode 100644
index 000..16c8ef0
--- /dev/null
+++ b/drivers/net/lpc32xx_eth.c
@@ -0,0 +1,636 @@
+/*
+ * LPC32xx Ethernet MAC interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include net.h
+#include malloc.h
+#include miiphy.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/types.h
+#include asm/system.h
+#include asm/byteorder.h
+#include asm/arch/cpu.h
+#include asm/arch/config.h
+
+/*
+ * Notes:
+ *
+ * 1. Unless specified otherwise, all references to tables or paragraphs
+ *are to UM10326, LPC32x0 and LPC32x0/01 User manual.
+ *
+ * 2. Only bitfield masks/values which are actually used by the driver
+ *are defined.
+ */
+
+/* a single RX descriptor. The controller has an array of these */
+struct lpc32xx_eth_rxdesc {
+ u32 packet; /* Receive packet pointer */
+ u32 control;/* Descriptor command status */
+};
+
+#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
+
+/* RX control bitfields/masks (see Table 330) */
+#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x07FF
+#define LPC32XX_ETH_RX_CTRL_UNUSED0x7800
+#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x8000
+
+/* a single RX status. The controller has an array of these */
+struct lpc32xx_eth_rxstat {
+ u32 statusinfo; /* Transmit Descriptor status */
+ u32 statushashcrc; /* Transmit Descriptor CRCs */
+};
+
+#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
+
+/* RX statusinfo bitfields/masks (see Table 333) */
+#define RX_STAT_RXSIZE 0x07FF
+/* Helper: OR of all errors except RANGE */
+#define RX_STAT_ERRORS 0x1B80
+
+/* a single
[U-Boot] [PATCH v4 6/8] dtt: add ds620 support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- cosmetic: added a blank line before copyright
drivers/hwmon/Makefile | 1 +
drivers/hwmon/ds620.c | 65 ++
include/dtt.h | 15 ++--
3 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 drivers/hwmon/ds620.c
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 25b8e8a..b4fb057 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_DTT_ADT7460) += adt7460.o
obj-$(CONFIG_DTT_DS1621) += ds1621.o
obj-$(CONFIG_DTT_DS1722) += ds1722.o
obj-$(CONFIG_DTT_DS1775) += ds1775.o
+obj-$(CONFIG_DTT_DS620) += ds620.o
obj-$(CONFIG_DTT_LM63) += lm63.o
obj-$(CONFIG_DTT_LM73) += lm73.o
obj-$(CONFIG_DTT_LM75) += lm75.o
diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c
new file mode 100644
index 000..1ecc3da
--- /dev/null
+++ b/drivers/hwmon/ds620.c
@@ -0,0 +1,65 @@
+/*
+ * DS620 DTT support
+ *
+ * (C) Copyright 2014 3ADEV http://www.3adev.com
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
+ */
+
+#include common.h
+#include i2c.h
+#include dtt.h
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48
+#define DTT_START_CONVERT 0x51
+#define DTT_TEMP 0xAA
+#define DTT_CONFIG 0xAC
+
+/*
+ * Config register MSB bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_AUTOC 0x02
+#define DTT_CONFIG_R0 0x04 /* always 1 */
+#define DTT_CONFIG_R1 0x08 /* always 1 */
+#define DTT_CONFIG_TLF 0x10
+#define DTT_CONFIG_THF 0x20
+#define DTT_CONFIG_NVB 0x40
+#define DTT_CONFIG_DONE0x80
+
+#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor 0x07))
+
+int dtt_init_one(int sensor)
+{
+ uint8_t config = DTT_CONFIG_1SHOT
+ | DTT_CONFIG_R0
+ | DTT_CONFIG_R1;
+ return i2c_write(CHIP(sensor), DTT_CONFIG, 1, config, 1);
+}
+
+int dtt_get_temp(int sensor)
+{
+ uint8_t status;
+ uint8_t temp[2];
+
+ /* Start a conversion, may take up to 1 second. */
+ i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0);
+ do {
+ if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, status, 1))
+ /* bail out if I2C error */
+ status |= DTT_CONFIG_DONE;
+ } while (!(status DTT_CONFIG_DONE));
+ if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2))
+ /* bail out if I2C error */
+ return -274; /* below absolute zero == error */
+
+ return ((int16_t)(temp[1] | (temp[0] 8))) 7;
+}
diff --git a/include/dtt.h b/include/dtt.h
index 058bca4..173159d 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -12,13 +12,14 @@
#define _DTT_H_
#if defined(CONFIG_DTT_ADM1021)|| \
-defined(CONFIG_DTT_ADT7460)|| \
-defined(CONFIG_DTT_DS1621) || \
-defined(CONFIG_DTT_DS1775) || \
-defined(CONFIG_DTT_LM63) || \
-defined(CONFIG_DTT_LM73) || \
-defined(CONFIG_DTT_LM75) || \
-defined(CONFIG_DTT_LM81)
+ defined(CONFIG_DTT_ADT7460) || \
+ defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
+ defined(CONFIG_DTT_DS620) || \
+ defined(CONFIG_DTT_LM63)|| \
+ defined(CONFIG_DTT_LM73)|| \
+ defined(CONFIG_DTT_LM75)|| \
+ defined(CONFIG_DTT_LM81)
#define CONFIG_DTT /* We have a DTT */
--
2.1.0
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[U-Boot] [PATCH v4 2/8] lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v4:
- remove two debugging statements
- add __iomem to regs struct
- remove useless 'else return;'
- take BB marker out of free OOB area
- replace magic numbers in OOB reads/writes
- add timeouts in NAND loops
- use DIV_ROUND_UP where applicable
- fix erroneous comment
- skip bad blocks in SPL chainload loop
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/lpc32xx_nand_mlc.c | 644 ++
5 files changed, 656 insertions(+)
create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 062db8d..be4c93d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -44,3 +44,9 @@ void lpc32xx_mac_init(void)
writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
| CLK_MAC_MII, clk-macclk_ctrl);
}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15..bc7d33d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -147,6 +147,10 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 1)
+#define CLK_NAND_MLC_INT (1 5)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a6b8826..0c4e712 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -9,5 +9,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f02bfc..347ea62 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 000..389989d
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -0,0 +1,644 @@
+/*
+ * LPC32xx MLC NAND flash controller driver
+ *
+ * (C) Copyright 2014 3ADEV http://3adev.com
+ * Written by Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * NOTE:
+ *
+ * The MLC NAND flash controller provides hardware Reed-Solomon ECC
+ * covering in- and out-of-band data together. Therefore, in- and out-
+ * of-band data must be written together in order to have a valid ECC.
+ *
+ * Consequently, pages with meaningful in-band data are written with
+ * blank (all-ones) out-of-band data and a valid ECC, and any later
+ * out-of-band data write will void the ECC.
+ *
+ * Therefore, code which reads such late-written out-of-band data
+ * should not rely on the ECC validity.
+ */
+
+#include common.h
+#include nand.h
+#include asm/errno.h
+#include asm/io.h
+#include nand.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+
+/*
+ * MLC NAND controller registers.
+ */
+struct lpc32xx_nand_mlc_registers {
+ u8 buff[32768]; /* controller's serial data buffer */
+ u8 data[32768]; /* NAND's raw data buffer */
+ u32 cmd;
+ u32 addr;
+ u32 ecc_enc_reg;
+ u32 ecc_dec_reg;
+ u32 ecc_auto_enc_reg;
+ u32 ecc_auto_dec_reg;
+ u32 rpr;
+ u32 wpr;
+ u32 rubp;
+ u32 robp;
+ u32 sw_wp_add_low;
+ u32 sw_wp_add_hig;
+ u32 icr;
+ u32 time_reg;
+ u32 irq_mr;
+ u32 irq_sr;
+ u32 lock_pr;
+ u32 isr;
+ u32 ceh;
+};
+
+/* LOCK_PR register defines */
+#define LOCK_PR_UNLOCK_KEY 0xA25E /* Magic unlock value */
+
+/* ICR defines */
+#define ICR_LARGE_BLOCKS 0x0004/* configure for 2KB blocks */
+#define ICR_ADDR4
[U-Boot] [PATCH v4 5/8] lpc32xx: add LPC32xx SSP support (SPI mode)
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v4: None
Changes in v3:
- move regs and functions in private struct
Changes in v2:
- added MUX setting for SSP0
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/lpc32xx_ssp.c | 144 ++
5 files changed, 163 insertions(+)
create mode 100644 drivers/spi/lpc32xx_ssp.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index a407098..5a453e3 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -8,11 +8,13 @@
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/uart.h
+#include asm/arch/mux.h
#include asm/io.h
#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
void lpc32xx_uart_init(unsigned int uart_id)
{
@@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum)
U_BOOT_DEVICE(lpc32xx_gpios) = {
.name = gpio_lpc32xx
};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, clk-ssp_ctrl);
+ /* Mux SSP0 pins */
+ writel(P_MUX_SET_SSP0, mux-p_mux_set);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 781ac07..2cb5703 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -155,6 +155,9 @@ struct clk_pm_regs {
#define CLK_NAND_MLC (1 1)
#define CLK_NAND_MLC_INT (1 5)
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 0)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a4a05d1..86d5ee9 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..ce6f1cc 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
new file mode 100644
index 000..0fc44a0
--- /dev/null
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -0,0 +1,144 @@
+/*
+ * LPC32xx SSP interface (SPI mode)
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/compat.h
+#include asm/io.h
+#include malloc.h
+#include spi.h
+#include asm/arch/clk.h
+
+/* SSP chip registers */
+struct ssp_regs {
+ u32 cr0;
+ u32 cr1;
+ u32 data;
+ u32 sr;
+ u32 cpsr;
+ u32 imsc;
+ u32 ris;
+ u32 mis;
+ u32 icr;
+ u32 dmacr;
+};
+
+/* CR1 register defines */
+#define SSP_CR1_SSP_ENABLE 0x0002
+
+/* SR register defines */
+#define SSP_SR_TNF 0x0002
+/* SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE 0x0004
+
+/* zynq spi slave */
+struct lpc32xx_spi_slave {
+ struct spi_slave slave;
+ struct ssp_regs *regs;
+};
+
+static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave(
+ struct spi_slave *slave)
+{
+ return container_of(slave, struct lpc32xx_spi_slave, slave);
+}
+
+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
+void spi_init(void)
+{
+ /*
+* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
+* and configuration will be done in spi_setup_slave()
+ */
+}
+
+/* the following is called in sequence by do_spi_xfer() */
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+ struct lpc32xx_spi_slave *lslave;
+
+ /* we only set up SSP0 for now, so ignore bus */
+
+ if (mode SPI_3WIRE) {
+ error(3-wire mode not supported);
+ return NULL
[U-Boot] [PATCH v4 3/8] lpc32xx: i2c: add LPC32xx I2C interface support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/i2c/Makefile | 1 +
drivers/i2c/lpc32xx_i2c.c | 249 ++
6 files changed, 268 insertions(+)
create mode 100644 drivers/i2c/lpc32xx_i2c.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index be4c93d..81b53ea 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void)
/* Enable NAND interface */
writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(clk-i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, clk-i2cclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index bc7d33d..781ac07 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -123,6 +123,10 @@ struct clk_pm_regs {
#define CLK_MAC_SLAVE (1 1)
#define CLK_MAC_REG(1 0)
+/* I2C Clock Control Register bits */
+#define CLK_I2C2_ENABLE(1 1)
+#define CLK_I2C1_ENABLE(1 0)
+
/* Timer Clock Control1 Register bits */
#define CLK_TIMCLK_MOTOR (1 6)
#define CLK_TIMCLK_TIMER3 (1 5)
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h
b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a0..1067107 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -37,6 +37,8 @@
#define UART4_BASE 0x40088000 /* UART 4 registers base*/
#define UART5_BASE 0x4009 /* UART 5 registers base*/
#define UART6_BASE 0x40098000 /* UART 6 registers base*/
+#define I2C1_BASE 0x400A /* I2C 1 registers base*/
+#define I2C2_BASE 0x400A8000 /* I2C 2 registers base*/
/* External SDRAM Memory Bank base addresses */
#define EMC_DYCS0_BASE 0x8000 /* SDRAM DYCS0 base address */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 0c4e712..a4a05d1 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -10,5 +10,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 774bc94..26ea854 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
new file mode 100644
index 000..78d26e4
--- /dev/null
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -0,0 +1,249 @@
+/*
+ * LPC32xx I2C interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include i2c.h
+#include asm/errno.h
+#include asm/arch/clk.h
+
+/*
+ * Provide default speed and slave if target did not
+ */
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
+#define CONFIG_SYS_I2C_LPC32XX_SPEED 35
+#endif
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
+#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
+#endif
+
+/* i2c register set */
+struct lpc32xx_i2c_registers {
+ union {
+ u32 rx;
+ u32 tx;
+ };
+ u32 stat;
+ u32 ctrl;
+ u32 clk_hi;
+ u32 clk_lo;
+ u32 adr;
+ u32 rxfl;
+ u32 txfl;
+ u32 rxb;
+ u32 txb;
+ u32 stx;
+ u32 stxfl;
+};
+
+/* TX register fields */
+#define LPC32XX_I2C_TX_START 0x0100
+#define LPC32XX_I2C_TX_STOP0x0200
+
+/* Control register values */
+#define LPC32XX_I2C_SOFT_RESET 0x0100
+
+/* Status register values */
+#define LPC32XX_I2C_STAT_TFF 0x0400
+#define
[U-Boot] [PATCH v4 8/8] lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- Changes in v4: None Changes in v3: - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: None Makefile | 20 ++ arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 4 + arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 + arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 +++ arch/arm/include/asm/arch-lpc32xx/clk.h| 5 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 1 + arch/arm/include/asm/arch-lpc32xx/mux.h| 18 ++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 4 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 ++ board/work-microwave/work_92105/work_92105.c | 62 .../work-microwave/work_92105/work_92105_display.c | 349 + .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 ++ configs/work_92105_defconfig | 5 + include/configs/work_92105.h | 266 21 files changed, 1068 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 board/work-microwave/work_92105/work_92105_spl.c create mode 100644 configs/work_92105_defconfig create mode 100644 include/configs/work_92105.h diff --git a/Makefile b/Makefile index 9747bd2..6013712 100644 --- a/Makefile +++ b/Makefile @@ -896,6 +896,26 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) +MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) + +lpc32xx-spl.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-0.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-1.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img + $(call if_changed,cat) + +CLEAN_FILES += lpc32xx-* + OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ --pad-to=$(CONFIG_TPL_PAD_TO) tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b9ebee1..10d9280 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -132,6 +132,11 @@ config TARGET_DEVKIT3250 bool Support devkit3250 select CPU_ARM926EJS +config TARGET_WORK_92105 + bool Support work_92105 + select CPU_ARM926EJS + select SUPPORT_SPL + config TARGET_MX25PDK bool Support mx25pdk select CPU_ARM926EJS @@ -871,6 +876,7 @@ source board/vpac270/Kconfig source board/wandboard/Kconfig source board/warp/Kconfig source board/woodburn/Kconfig +source board/work-microwave/work_92105/Kconfig source board/xaeniax/Kconfig source board/xilinx/zynqmp/Kconfig source board/zipitz2/Kconfig diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile index 314f004..4837377 100644 --- a/arch/arm
[U-Boot] [PATCH v4 4/8] lpc32xx: add GPIO support
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v4: None
Changes in v3:
- move DM dependency constraint into Kconfig
- move regs pointer and function cache into private struct
- discourage readers from using functions implementation as an example
Changes in v2:
- move from legacy to Driver Model support
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 +
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 293 +++
5 files changed, 349 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..a407098 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include asm/arch/clk.h
#include asm/arch/uart.h
#include asm/io.h
+#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = gpio_lpc32xx
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b609e73..7b5178a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -7,3 +7,10 @@ config DM_GPIO
the GPIO uclass. Drivers provide methods to query the
particular GPIOs that they provide. The uclass interface
is defined in include/asm-generic/gpio.h.
+
+config LPC32XX_GPIO
+ bool LPC32XX GPIO driver
+ depends on DM
+ default n
+ help
+ Support for the LPC32XX GPIO driver.
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fe9a3b2..85f71c5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..96b3125
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,293 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+#include asm-generic/gpio.h
+#include dm.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING #1 **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where a single physical GPIO has differing numbers
+ * for setting its direction, reading it and/or writing to it.
+ *
+ * ** WARNING #2 **
+ *
+ * Please read NOTE in description of lpc32xx_gpio_get_function
[U-Boot] [PATCH v4 7/8] lpc32xx: add lpc32xx-spl.bin boot image target
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v4: None
Changes in v3:
- remove script/Makefile.spl change
Changes in v2:
- move boot image generation to mkimage framework
common/image.c | 1 +
include/image.h | 1 +
tools/Makefile | 1 +
tools/lpc32xximage.c | 178 +++
4 files changed, 181 insertions(+)
create mode 100644 tools/lpc32xximage.c
diff --git a/common/image.c b/common/image.c
index a911aa9..162b682 100644
--- a/common/image.c
+++ b/common/image.c
@@ -149,6 +149,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_MXSIMAGE, mxsimage, Freescale MXS Boot Image,},
{ IH_TYPE_ATMELIMAGE, atmelimage, ATMEL ROM-Boot Image,},
{ IH_TYPE_X86_SETUP, x86_setup, x86 setup.bin,},
+ { IH_TYPE_LPC32XXIMAGE, lpc32xximage, LPC32XX Boot Image, },
{ -1, , , },
};
diff --git a/include/image.h b/include/image.h
index 0e6af00..3844be6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -242,6 +242,7 @@ struct lmb;
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */
+#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
/*
* Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 88770b0..4bbb153 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -83,6 +83,7 @@ dumpimage-mkimage-objs := aisimage.o \
imximage.o \
kwbimage.o \
lib/md5.o \
+ lpc32xximage.o \
mxsimage.o \
omapimage.o \
os_support.o \
diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c
new file mode 100644
index 000..6b3865f
--- /dev/null
+++ b/tools/lpc32xximage.c
@@ -0,0 +1,178 @@
+/*
+ * Image manipulator for LPC32XX SoCs
+ *
+ * (C) Copyright 2015 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Derived from omapimage.c:
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby john.ri...@linaro.org
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sba...@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include imagetool.h
+#include compiler.h
+#include image.h
+
+/*
+ * NAND page 0 boot header
+ */
+
+struct nand_page_0_boot_header {
+ uint32_t data[129];
+ uint32_t pad[383];
+};
+
+/*
+ * Default ICC (interface configuration data [sic]) if none specified
+ * in board config
+ */
+
+#ifndef LPC32XX_BOOT_ICR
+#define LPC32XX_BOOT_ICR 0x0096
+#endif
+
+/*
+ * Default boot NAND page size if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGESIZE
+#define LPC32XX_BOOT_NAND_PAGESIZE 2048
+#endif
+
+/*
+ * Default boot NAND pages per sector if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR
+#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64
+#endif
+
+/*
+ * Maximum size for boot code is 56K unless defined in board config
+ */
+
+#ifndef LPC32XX_BOOT_CODESIZE
+#define LPC32XX_BOOT_CODESIZE (56*1024)
+#endif
+
+/* signature byte for a readable block */
+
+#define LPC32XX_BOOT_BLOCK_OK 0xaa
+
+static struct nand_page_0_boot_header lpc32xximage_header;
+
+static int lpc32xximage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_LPC32XXIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int lpc32xximage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+
+ /* turn image size from bytes to NAND pages, page 0 included */
+ int image_size_in_pages = ((image_size - 1)
+ / LPC32XX_BOOT_NAND_PAGESIZE);
+
+ if (hdr-data[0] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[1] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[2] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[3] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[4] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[5] != (0xff ~image_size_in_pages))
+ return -1;
+ if (hdr-data[6] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[7] != (0xff ~image_size_in_pages))
+ return -1;
+ if (hdr-data[8] != (0xff
[U-Boot] [PATCH v3 2/8] lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/lpc32xx_nand_mlc.c | 589 ++
5 files changed, 601 insertions(+)
create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 062db8d..be4c93d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -44,3 +44,9 @@ void lpc32xx_mac_init(void)
writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
| CLK_MAC_MII, clk-macclk_ctrl);
}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15..bc7d33d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -147,6 +147,10 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 1)
+#define CLK_NAND_MLC_INT (1 5)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a6b8826..0c4e712 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -9,5 +9,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f02bfc..347ea62 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 000..cb23972
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -0,0 +1,589 @@
+/*
+ * LPC32xx MLC NAND flash controller driver
+ *
+ * (C) Copyright 2014 3ADEV http://3adev.com
+ * Written by Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * NOTE:
+ *
+ * The MLC NAND flash controller provides hardware Reed-Solomon ECC
+ * covering in- and out-of-band data together. Therefore, in- and out-
+ * of-band data must be written together in order to have a valid ECC.
+ *
+ * Consequently, pages with meaningful in-band data are written with
+ * blank (all-ones) out-of-band data and a valid ECC, and any later
+ * out-of-band data write will void the ECC.
+ *
+ * Therefore, code which reads such late-written out-of-band data
+ * should not rely on the ECC validity.
+ */
+
+#include common.h
+#include nand.h
+#include asm/errno.h
+#include asm/io.h
+#include nand.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+
+/*
+ * MLC NAND controller registers.
+ */
+struct lpc32xx_nand_mlc_registers {
+ u8 buff[32768]; /* controller's serial data buffer */
+ u8 data[32768]; /* NAND's raw data buffer */
+ u32 cmd;
+ u32 addr;
+ u32 ecc_enc_reg;
+ u32 ecc_dec_reg;
+ u32 ecc_auto_enc_reg;
+ u32 ecc_auto_dec_reg;
+ u32 rpr;
+ u32 wpr;
+ u32 rubp;
+ u32 robp;
+ u32 sw_wp_add_low;
+ u32 sw_wp_add_hig;
+ u32 icr;
+ u32 time_reg;
+ u32 irq_mr;
+ u32 irq_sr;
+ u32 lock_pr;
+ u32 isr;
+ u32 ceh;
+};
+
+/* LOCK_PR register defines */
+#define LOCK_PR_UNLOCK_KEY 0xA25E /* Magic unlock value */
+
+/* ICR defines */
+#define ICR_LARGE_BLOCKS 0x0004/* configure for 2KB blocks */
+#define ICR_ADDR40x0002/* configure for 4-word addrs */
+
+/* CEH defines */
+#define CEH_NORMAL_CE 0x0001 /* do not force CE ON */
+
+/* ISR register defines */
+#define ISR_NAND_READY0x0001
+#define ISR_CONTROLLER_READY 0x0002
+#define ISR_ECC_READY 0x0004
+#define ISR_DECODER_ERRORS(s) s) 4
[U-Boot] [PATCH v3 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: A - I2C driver remains non-DM During v2 review, it was suggested to move to DM for I2C. However, this caused issues with the 'date', 'dtt' and 'eeprom' commands which are configured in this board. Therefore the I2C move to DM was not done. B - Some checkpatch diagnostics are not fixed The following warnings checkpatch warnings and checks were not fixed: 1. warning: arch/arm/Kconfig,135: please write a paragraph that describes the config symbol fully Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. check: include/configs/work_92105.h,185: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v3: - move DM dependency constraint into Kconfig - move regs pointer and function cache into private struct - discourage readers from using functions implementation as an example - move regs and functions in private struct - remove script/Makefile.spl change - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 Makefile | 20 + arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h| 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h| 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 +++ board/work-microwave/work_92105/work_92105.c | 62 ++ .../work-microwave/work_92105/work_92105_display.c | 349 +++ .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 ++ common/image.c | 1 + configs/work_92105_defconfig | 5 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c| 293 ++ drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 +++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c| 589 +++ drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 636 + drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 144 + include/configs/work_92105.h | 266 + include/dtt.h | 15 +- include/image.h| 1 + include/netdev.h | 1 + tools/Makefile | 1 + tools/lpc32xximage.c | 178 ++ 43 files changed, 3362 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch
[U-Boot] [PATCH v3 1/8] lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 9 +
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 +
arch/arm/include/asm/arch-lpc32xx/config.h| 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/net/Makefile | 1 +
drivers/net/lpc32xx_eth.c | 636 ++
include/netdev.h | 1 +
7 files changed, 658 insertions(+)
create mode 100644 drivers/net/lpc32xx_eth.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..eec4d9e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include netdev.h
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/wdt.h
@@ -55,3 +56,11 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..062db8d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -37,3 +37,10 @@ void lpc32xx_uart_init(unsigned int uart_id)
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
clk-u3clk + (uart_id - 3));
}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+ | CLK_MAC_MII, clk-macclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h
b/arch/arm/include/asm/arch-lpc32xx/config.h
index 564441c..d57bc48 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -52,6 +52,9 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
/* NOR Flash */
#if defined(CONFIG_SYS_FLASH_CFI)
#define CONFIG_FLASH_CFI_DRIVER
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 28812be..a6b8826 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -8,5 +8,6 @@
#define _LPC32XX_SYS_PROTO_H
void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b8b0803..af8941f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_GRETH) += greth.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
+obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
new file mode 100644
index 000..16c8ef0
--- /dev/null
+++ b/drivers/net/lpc32xx_eth.c
@@ -0,0 +1,636 @@
+/*
+ * LPC32xx Ethernet MAC interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include net.h
+#include malloc.h
+#include miiphy.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/types.h
+#include asm/system.h
+#include asm/byteorder.h
+#include asm/arch/cpu.h
+#include asm/arch/config.h
+
+/*
+ * Notes:
+ *
+ * 1. Unless specified otherwise, all references to tables or paragraphs
+ *are to UM10326, LPC32x0 and LPC32x0/01 User manual.
+ *
+ * 2. Only bitfield masks/values which are actually used by the driver
+ *are defined.
+ */
+
+/* a single RX descriptor. The controller has an array of these */
+struct lpc32xx_eth_rxdesc {
+ u32 packet; /* Receive packet pointer */
+ u32 control;/* Descriptor command status */
+};
+
+#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
+
+/* RX control bitfields/masks (see Table 330) */
+#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x07FF
+#define LPC32XX_ETH_RX_CTRL_UNUSED0x7800
+#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x8000
+
+/* a single RX status. The controller has an array of these */
+struct lpc32xx_eth_rxstat {
+ u32 statusinfo; /* Transmit Descriptor status */
+ u32 statushashcrc; /* Transmit Descriptor CRCs */
+};
+
+#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
+
+/* RX statusinfo bitfields/masks (see Table 333) */
+#define RX_STAT_RXSIZE 0x07FF
+/* Helper: OR of all errors except RANGE */
+#define RX_STAT_ERRORS 0x1B80
+
+/* a single TX descriptor
[U-Boot] [PATCH v3 8/8] lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- Changes in v3: - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: None Makefile | 20 ++ arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 4 + arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 + arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 +++ arch/arm/include/asm/arch-lpc32xx/clk.h| 5 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 1 + arch/arm/include/asm/arch-lpc32xx/mux.h| 18 ++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 4 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 ++ board/work-microwave/work_92105/work_92105.c | 62 .../work-microwave/work_92105/work_92105_display.c | 349 + .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 ++ configs/work_92105_defconfig | 5 + include/configs/work_92105.h | 266 21 files changed, 1068 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 board/work-microwave/work_92105/work_92105_spl.c create mode 100644 configs/work_92105_defconfig create mode 100644 include/configs/work_92105.h diff --git a/Makefile b/Makefile index 9747bd2..6013712 100644 --- a/Makefile +++ b/Makefile @@ -896,6 +896,26 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) +MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) + +lpc32xx-spl.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-0.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-1.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img + $(call if_changed,cat) + +CLEAN_FILES += lpc32xx-* + OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ --pad-to=$(CONFIG_TPL_PAD_TO) tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bc55e5b..50636b0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -132,6 +132,11 @@ config TARGET_DEVKIT3250 bool Support devkit3250 select CPU_ARM926EJS +config TARGET_WORK_92105 + bool Support work_92105 + select CPU_ARM926EJS + select SUPPORT_SPL + config TARGET_MX25PDK bool Support mx25pdk select CPU_ARM926EJS @@ -843,6 +848,7 @@ source board/udoo/Kconfig source board/vpac270/Kconfig source board/wandboard/Kconfig source board/woodburn/Kconfig +source board/work-microwave/work_92105/Kconfig source board/xaeniax/Kconfig source board/xilinx/zynqmp/Kconfig source board/zipitz2/Kconfig diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile index 314f004..4837377 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx
[U-Boot] [PATCH v3 7/8] lpc32xx: add lpc32xx-spl.bin boot image target
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v3:
- remove script/Makefile.spl change
Changes in v2:
- move boot image generation to mkimage framework
common/image.c | 1 +
include/image.h | 1 +
tools/Makefile | 1 +
tools/lpc32xximage.c | 178 +++
4 files changed, 181 insertions(+)
create mode 100644 tools/lpc32xximage.c
diff --git a/common/image.c b/common/image.c
index a911aa9..162b682 100644
--- a/common/image.c
+++ b/common/image.c
@@ -149,6 +149,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_MXSIMAGE, mxsimage, Freescale MXS Boot Image,},
{ IH_TYPE_ATMELIMAGE, atmelimage, ATMEL ROM-Boot Image,},
{ IH_TYPE_X86_SETUP, x86_setup, x86 setup.bin,},
+ { IH_TYPE_LPC32XXIMAGE, lpc32xximage, LPC32XX Boot Image, },
{ -1, , , },
};
diff --git a/include/image.h b/include/image.h
index 0e6af00..3844be6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -242,6 +242,7 @@ struct lmb;
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */
+#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
/*
* Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 88770b0..4bbb153 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -83,6 +83,7 @@ dumpimage-mkimage-objs := aisimage.o \
imximage.o \
kwbimage.o \
lib/md5.o \
+ lpc32xximage.o \
mxsimage.o \
omapimage.o \
os_support.o \
diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c
new file mode 100644
index 000..6b3865f
--- /dev/null
+++ b/tools/lpc32xximage.c
@@ -0,0 +1,178 @@
+/*
+ * Image manipulator for LPC32XX SoCs
+ *
+ * (C) Copyright 2015 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Derived from omapimage.c:
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby john.ri...@linaro.org
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sba...@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include imagetool.h
+#include compiler.h
+#include image.h
+
+/*
+ * NAND page 0 boot header
+ */
+
+struct nand_page_0_boot_header {
+ uint32_t data[129];
+ uint32_t pad[383];
+};
+
+/*
+ * Default ICC (interface configuration data [sic]) if none specified
+ * in board config
+ */
+
+#ifndef LPC32XX_BOOT_ICR
+#define LPC32XX_BOOT_ICR 0x0096
+#endif
+
+/*
+ * Default boot NAND page size if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGESIZE
+#define LPC32XX_BOOT_NAND_PAGESIZE 2048
+#endif
+
+/*
+ * Default boot NAND pages per sector if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR
+#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64
+#endif
+
+/*
+ * Maximum size for boot code is 56K unless defined in board config
+ */
+
+#ifndef LPC32XX_BOOT_CODESIZE
+#define LPC32XX_BOOT_CODESIZE (56*1024)
+#endif
+
+/* signature byte for a readable block */
+
+#define LPC32XX_BOOT_BLOCK_OK 0xaa
+
+static struct nand_page_0_boot_header lpc32xximage_header;
+
+static int lpc32xximage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_LPC32XXIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int lpc32xximage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+
+ /* turn image size from bytes to NAND pages, page 0 included */
+ int image_size_in_pages = ((image_size - 1)
+ / LPC32XX_BOOT_NAND_PAGESIZE);
+
+ if (hdr-data[0] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[1] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[2] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[3] != (0xff ~LPC32XX_BOOT_ICR))
+ return -1;
+ if (hdr-data[4] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[5] != (0xff ~image_size_in_pages))
+ return -1;
+ if (hdr-data[6] != (0xff image_size_in_pages))
+ return -1;
+ if (hdr-data[7] != (0xff ~image_size_in_pages))
+ return -1;
+ if (hdr-data[8] != (0xff image_size_in_pages
[U-Boot] [PATCH v3 4/8] lpc32xx: add GPIO support
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v3:
- move DM dependency constraint into Kconfig
- move regs pointer and function cache into private struct
- discourage readers from using functions implementation as an example
Changes in v2:
- move from legacy to Driver Model support
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 +
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 293 +++
5 files changed, 349 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..a407098 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include asm/arch/clk.h
#include asm/arch/uart.h
#include asm/io.h
+#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = gpio_lpc32xx
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b609e73..7b5178a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -7,3 +7,10 @@ config DM_GPIO
the GPIO uclass. Drivers provide methods to query the
particular GPIOs that they provide. The uclass interface
is defined in include/asm-generic/gpio.h.
+
+config LPC32XX_GPIO
+ bool LPC32XX GPIO driver
+ depends on DM
+ default n
+ help
+ Support for the LPC32XX GPIO driver.
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fe9a3b2..85f71c5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..96b3125
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,293 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+#include asm-generic/gpio.h
+#include dm.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING #1 **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where a single physical GPIO has differing numbers
+ * for setting its direction, reading it and/or writing to it.
+ *
+ * ** WARNING #2 **
+ *
+ * Please read NOTE in description of lpc32xx_gpio_get_function().
+ */
+
+#define
[U-Boot] [PATCH v3 3/8] lpc32xx: i2c: add LPC32xx I2C interface support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/i2c/Makefile | 1 +
drivers/i2c/lpc32xx_i2c.c | 249 ++
6 files changed, 268 insertions(+)
create mode 100644 drivers/i2c/lpc32xx_i2c.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index be4c93d..81b53ea 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void)
/* Enable NAND interface */
writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(clk-i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, clk-i2cclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index bc7d33d..781ac07 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -123,6 +123,10 @@ struct clk_pm_regs {
#define CLK_MAC_SLAVE (1 1)
#define CLK_MAC_REG(1 0)
+/* I2C Clock Control Register bits */
+#define CLK_I2C2_ENABLE(1 1)
+#define CLK_I2C1_ENABLE(1 0)
+
/* Timer Clock Control1 Register bits */
#define CLK_TIMCLK_MOTOR (1 6)
#define CLK_TIMCLK_TIMER3 (1 5)
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h
b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a0..1067107 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -37,6 +37,8 @@
#define UART4_BASE 0x40088000 /* UART 4 registers base*/
#define UART5_BASE 0x4009 /* UART 5 registers base*/
#define UART6_BASE 0x40098000 /* UART 6 registers base*/
+#define I2C1_BASE 0x400A /* I2C 1 registers base*/
+#define I2C2_BASE 0x400A8000 /* I2C 2 registers base*/
/* External SDRAM Memory Bank base addresses */
#define EMC_DYCS0_BASE 0x8000 /* SDRAM DYCS0 base address */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 0c4e712..a4a05d1 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -10,5 +10,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 774bc94..26ea854 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
new file mode 100644
index 000..78d26e4
--- /dev/null
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -0,0 +1,249 @@
+/*
+ * LPC32xx I2C interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include i2c.h
+#include asm/errno.h
+#include asm/arch/clk.h
+
+/*
+ * Provide default speed and slave if target did not
+ */
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
+#define CONFIG_SYS_I2C_LPC32XX_SPEED 35
+#endif
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
+#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
+#endif
+
+/* i2c register set */
+struct lpc32xx_i2c_registers {
+ union {
+ u32 rx;
+ u32 tx;
+ };
+ u32 stat;
+ u32 ctrl;
+ u32 clk_hi;
+ u32 clk_lo;
+ u32 adr;
+ u32 rxfl;
+ u32 txfl;
+ u32 rxb;
+ u32 txb;
+ u32 stx;
+ u32 stxfl;
+};
+
+/* TX register fields */
+#define LPC32XX_I2C_TX_START 0x0100
+#define LPC32XX_I2C_TX_STOP0x0200
+
+/* Control register values */
+#define LPC32XX_I2C_SOFT_RESET 0x0100
+
+/* Status register values */
+#define LPC32XX_I2C_STAT_TFF 0x0400
+#define
[U-Boot] [PATCH v3 5/8] lpc32xx: add LPC32xx SSP support (SPI mode)
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v3:
- move regs and functions in private struct
Changes in v2:
- added MUX setting for SSP0
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/lpc32xx_ssp.c | 144 ++
5 files changed, 163 insertions(+)
create mode 100644 drivers/spi/lpc32xx_ssp.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index a407098..5a453e3 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -8,11 +8,13 @@
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/uart.h
+#include asm/arch/mux.h
#include asm/io.h
#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
void lpc32xx_uart_init(unsigned int uart_id)
{
@@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum)
U_BOOT_DEVICE(lpc32xx_gpios) = {
.name = gpio_lpc32xx
};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, clk-ssp_ctrl);
+ /* Mux SSP0 pins */
+ writel(P_MUX_SET_SSP0, mux-p_mux_set);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 781ac07..2cb5703 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -155,6 +155,9 @@ struct clk_pm_regs {
#define CLK_NAND_MLC (1 1)
#define CLK_NAND_MLC_INT (1 5)
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 0)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a4a05d1..86d5ee9 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..ce6f1cc 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
new file mode 100644
index 000..0fc44a0
--- /dev/null
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -0,0 +1,144 @@
+/*
+ * LPC32xx SSP interface (SPI mode)
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/compat.h
+#include asm/io.h
+#include malloc.h
+#include spi.h
+#include asm/arch/clk.h
+
+/* SSP chip registers */
+struct ssp_regs {
+ u32 cr0;
+ u32 cr1;
+ u32 data;
+ u32 sr;
+ u32 cpsr;
+ u32 imsc;
+ u32 ris;
+ u32 mis;
+ u32 icr;
+ u32 dmacr;
+};
+
+/* CR1 register defines */
+#define SSP_CR1_SSP_ENABLE 0x0002
+
+/* SR register defines */
+#define SSP_SR_TNF 0x0002
+/* SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE 0x0004
+
+/* zynq spi slave */
+struct lpc32xx_spi_slave {
+ struct spi_slave slave;
+ struct ssp_regs *regs;
+};
+
+static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave(
+ struct spi_slave *slave)
+{
+ return container_of(slave, struct lpc32xx_spi_slave, slave);
+}
+
+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
+void spi_init(void)
+{
+ /*
+* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
+* and configuration will be done in spi_setup_slave()
+ */
+}
+
+/* the following is called in sequence by do_spi_xfer() */
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+ struct lpc32xx_spi_slave *lslave;
+
+ /* we only set up SSP0 for now, so ignore bus */
+
+ if (mode SPI_3WIRE) {
+ error(3-wire mode not supported);
+ return NULL
[U-Boot] [PATCH v3 6/8] dtt: add ds620 support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v3: None
Changes in v2:
- cosmetic: added a blank line before copyright
drivers/hwmon/Makefile | 1 +
drivers/hwmon/ds620.c | 65 ++
include/dtt.h | 15 ++--
3 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 drivers/hwmon/ds620.c
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 25b8e8a..b4fb057 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_DTT_ADT7460) += adt7460.o
obj-$(CONFIG_DTT_DS1621) += ds1621.o
obj-$(CONFIG_DTT_DS1722) += ds1722.o
obj-$(CONFIG_DTT_DS1775) += ds1775.o
+obj-$(CONFIG_DTT_DS620) += ds620.o
obj-$(CONFIG_DTT_LM63) += lm63.o
obj-$(CONFIG_DTT_LM73) += lm73.o
obj-$(CONFIG_DTT_LM75) += lm75.o
diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c
new file mode 100644
index 000..1ecc3da
--- /dev/null
+++ b/drivers/hwmon/ds620.c
@@ -0,0 +1,65 @@
+/*
+ * DS620 DTT support
+ *
+ * (C) Copyright 2014 3ADEV http://www.3adev.com
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
+ */
+
+#include common.h
+#include i2c.h
+#include dtt.h
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48
+#define DTT_START_CONVERT 0x51
+#define DTT_TEMP 0xAA
+#define DTT_CONFIG 0xAC
+
+/*
+ * Config register MSB bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_AUTOC 0x02
+#define DTT_CONFIG_R0 0x04 /* always 1 */
+#define DTT_CONFIG_R1 0x08 /* always 1 */
+#define DTT_CONFIG_TLF 0x10
+#define DTT_CONFIG_THF 0x20
+#define DTT_CONFIG_NVB 0x40
+#define DTT_CONFIG_DONE0x80
+
+#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor 0x07))
+
+int dtt_init_one(int sensor)
+{
+ uint8_t config = DTT_CONFIG_1SHOT
+ | DTT_CONFIG_R0
+ | DTT_CONFIG_R1;
+ return i2c_write(CHIP(sensor), DTT_CONFIG, 1, config, 1);
+}
+
+int dtt_get_temp(int sensor)
+{
+ uint8_t status;
+ uint8_t temp[2];
+
+ /* Start a conversion, may take up to 1 second. */
+ i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0);
+ do {
+ if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, status, 1))
+ /* bail out if I2C error */
+ status |= DTT_CONFIG_DONE;
+ } while (!(status DTT_CONFIG_DONE));
+ if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2))
+ /* bail out if I2C error */
+ return -274; /* below absolute zero == error */
+
+ return ((int16_t)(temp[1] | (temp[0] 8))) 7;
+}
diff --git a/include/dtt.h b/include/dtt.h
index 058bca4..173159d 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -12,13 +12,14 @@
#define _DTT_H_
#if defined(CONFIG_DTT_ADM1021)|| \
-defined(CONFIG_DTT_ADT7460)|| \
-defined(CONFIG_DTT_DS1621) || \
-defined(CONFIG_DTT_DS1775) || \
-defined(CONFIG_DTT_LM63) || \
-defined(CONFIG_DTT_LM73) || \
-defined(CONFIG_DTT_LM75) || \
-defined(CONFIG_DTT_LM81)
+ defined(CONFIG_DTT_ADT7460) || \
+ defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
+ defined(CONFIG_DTT_DS620) || \
+ defined(CONFIG_DTT_LM63)|| \
+ defined(CONFIG_DTT_LM73)|| \
+ defined(CONFIG_DTT_LM75)|| \
+ defined(CONFIG_DTT_LM81)
#define CONFIG_DTT /* We have a DTT */
--
2.1.0
___
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[U-Boot] [PATCH v2 7/8] lpc32xx: add lpc32xx-spl.bin boot image target
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- move boot image generation to mkimage framework
common/image.c | 1 +
include/image.h | 1 +
scripts/Makefile.spl | 9 +++
tools/Makefile | 1 +
tools/lpc32xximage.c | 178 +++
5 files changed, 190 insertions(+)
create mode 100644 tools/lpc32xximage.c
diff --git a/common/image.c b/common/image.c
index a911aa9..162b682 100644
--- a/common/image.c
+++ b/common/image.c
@@ -149,6 +149,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_MXSIMAGE, mxsimage, Freescale MXS Boot Image,},
{ IH_TYPE_ATMELIMAGE, atmelimage, ATMEL ROM-Boot Image,},
{ IH_TYPE_X86_SETUP, x86_setup, x86 setup.bin,},
+ { IH_TYPE_LPC32XXIMAGE, lpc32xximage, LPC32XX Boot Image, },
{ -1, , , },
};
diff --git a/include/image.h b/include/image.h
index 0e6af00..3844be6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -242,6 +242,7 @@ struct lmb;
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */
+#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
/*
* Compression Types
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index e4b9881..55d8b6f 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -147,6 +147,11 @@ endif
boot.bin: $(obj)/u-boot-spl.bin
$(call if_changed,mkimage)
+MKIMAGEFLAGS_lpc32xx-boot.bin = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE)
+
+lpc32xx-boot.bin: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkimage)
+
ALL-y += $(obj)/$(SPL_BIN).bin
ifdef CONFIG_SAMSUNG
@@ -159,6 +164,10 @@ ALL-y += $(obj)/sunxi-spl.bin
endif
endif
+ifdef CONFIG_LPC32XX_SPL
+ALL-y += lpc32xx-boot.bin
+endif
+
ifeq ($(CONFIG_SYS_SOC),at91)
ALL-y += boot.bin
endif
diff --git a/tools/Makefile b/tools/Makefile
index e4b23eb..c34c448 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -83,6 +83,7 @@ dumpimage-mkimage-objs := aisimage.o \
imximage.o \
kwbimage.o \
lib/md5.o \
+ lpc32xximage.o \
mxsimage.o \
omapimage.o \
os_support.o \
diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c
new file mode 100644
index 000..6b3865f
--- /dev/null
+++ b/tools/lpc32xximage.c
@@ -0,0 +1,178 @@
+/*
+ * Image manipulator for LPC32XX SoCs
+ *
+ * (C) Copyright 2015 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Derived from omapimage.c:
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby john.ri...@linaro.org
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sba...@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include imagetool.h
+#include compiler.h
+#include image.h
+
+/*
+ * NAND page 0 boot header
+ */
+
+struct nand_page_0_boot_header {
+ uint32_t data[129];
+ uint32_t pad[383];
+};
+
+/*
+ * Default ICC (interface configuration data [sic]) if none specified
+ * in board config
+ */
+
+#ifndef LPC32XX_BOOT_ICR
+#define LPC32XX_BOOT_ICR 0x0096
+#endif
+
+/*
+ * Default boot NAND page size if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGESIZE
+#define LPC32XX_BOOT_NAND_PAGESIZE 2048
+#endif
+
+/*
+ * Default boot NAND pages per sector if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR
+#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64
+#endif
+
+/*
+ * Maximum size for boot code is 56K unless defined in board config
+ */
+
+#ifndef LPC32XX_BOOT_CODESIZE
+#define LPC32XX_BOOT_CODESIZE (56*1024)
+#endif
+
+/* signature byte for a readable block */
+
+#define LPC32XX_BOOT_BLOCK_OK 0xaa
+
+static struct nand_page_0_boot_header lpc32xximage_header;
+
+static int lpc32xximage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_LPC32XXIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int lpc32xximage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+
+ /* turn image size from bytes to NAND pages, page 0 included */
+ int image_size_in_pages = ((image_size - 1)
+ / LPC32XX_BOOT_NAND_PAGESIZE);
+
+ if (hdr-data[0] != (0xff LPC32XX_BOOT_ICR))
+ return -1
[U-Boot] [PATCH v2 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: The series is not entirely checkpatch-clean. The following warnings and checks were not fixed: 1. warning: arch/arm/Kconfig,241: please write a paragraph that describes the config symbol fully Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. check: include/configs/work_92105.h,177: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 80 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h| 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h| 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 8 + board/work-microwave/work_92105/README | 23 + board/work-microwave/work_92105/work_92105.c | 86 +++ .../work-microwave/work_92105/work_92105_display.c | 349 +++ .../work-microwave/work_92105/work_92105_display.h | 14 + common/image.c | 1 + configs/work_92105_defconfig | 5 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c| 268 + drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 +++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c| 589 +++ drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 636 + drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 132 + include/configs/work_92105.h | 259 + include/dtt.h | 15 +- include/image.h| 1 + include/netdev.h | 1 + scripts/Makefile.spl | 9 + tools/Makefile | 1 + tools/lpc32xximage.c | 178 ++ 41 files changed, 3222 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 configs/work_92105_defconfig create mode 100644 drivers/gpio/lpc32xx_gpio.c create mode 100644 drivers/hwmon/ds620.c create mode 100644 drivers/i2c/lpc32xx_i2c.c create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c create mode 100644 drivers/net/lpc32xx_eth.c create mode 100644 drivers/spi/lpc32xx_ssp.c create mode 100644 include/configs/work_92105.h create
[U-Boot] [PATCH v2 3/8] lpc32xx: i2c: add LPC32xx I2C interface support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/i2c/Makefile | 1 +
drivers/i2c/lpc32xx_i2c.c | 249 ++
6 files changed, 268 insertions(+)
create mode 100644 drivers/i2c/lpc32xx_i2c.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index be4c93d..81b53ea 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void)
/* Enable NAND interface */
writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(clk-i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, clk-i2cclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index bc7d33d..781ac07 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -123,6 +123,10 @@ struct clk_pm_regs {
#define CLK_MAC_SLAVE (1 1)
#define CLK_MAC_REG(1 0)
+/* I2C Clock Control Register bits */
+#define CLK_I2C2_ENABLE(1 1)
+#define CLK_I2C1_ENABLE(1 0)
+
/* Timer Clock Control1 Register bits */
#define CLK_TIMCLK_MOTOR (1 6)
#define CLK_TIMCLK_TIMER3 (1 5)
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h
b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a0..1067107 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -37,6 +37,8 @@
#define UART4_BASE 0x40088000 /* UART 4 registers base*/
#define UART5_BASE 0x4009 /* UART 5 registers base*/
#define UART6_BASE 0x40098000 /* UART 6 registers base*/
+#define I2C1_BASE 0x400A /* I2C 1 registers base*/
+#define I2C2_BASE 0x400A8000 /* I2C 2 registers base*/
/* External SDRAM Memory Bank base addresses */
#define EMC_DYCS0_BASE 0x8000 /* SDRAM DYCS0 base address */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 0c4e712..a4a05d1 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -10,5 +10,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 774bc94..26ea854 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
new file mode 100644
index 000..78d26e4
--- /dev/null
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -0,0 +1,249 @@
+/*
+ * LPC32xx I2C interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include i2c.h
+#include asm/errno.h
+#include asm/arch/clk.h
+
+/*
+ * Provide default speed and slave if target did not
+ */
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
+#define CONFIG_SYS_I2C_LPC32XX_SPEED 35
+#endif
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
+#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
+#endif
+
+/* i2c register set */
+struct lpc32xx_i2c_registers {
+ union {
+ u32 rx;
+ u32 tx;
+ };
+ u32 stat;
+ u32 ctrl;
+ u32 clk_hi;
+ u32 clk_lo;
+ u32 adr;
+ u32 rxfl;
+ u32 txfl;
+ u32 rxb;
+ u32 txb;
+ u32 stx;
+ u32 stxfl;
+};
+
+/* TX register fields */
+#define LPC32XX_I2C_TX_START 0x0100
+#define LPC32XX_I2C_TX_STOP0x0200
+
+/* Control register values */
+#define LPC32XX_I2C_SOFT_RESET 0x0100
+
+/* Status register values */
+#define LPC32XX_I2C_STAT_TFF 0x0400
+#define LPC32XX_I2C_STAT_RFE
[U-Boot] [PATCH v2 4/8] lpc32xx: add GPIO support
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- move from legacy to Driver Model support
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 +
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 268 +++
4 files changed, 317 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..a407098 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include asm/arch/clk.h
#include asm/arch/uart.h
#include asm/io.h
+#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = gpio_lpc32xx
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index aa11f15..559894a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..861975e
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,268 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * We only support driver model
+ */
+#ifndef CONFIG_DM_GPIO
+#error Please enable Driver Model GPIO in your target configuration.
+#endif
+
+#include asm/io.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+#include asm-generic/gpio.h
+#include dm.h
+#include malloc.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where a single physical GPIO has differing numbers
+ * for setting its direction, reading it and/or writing to it.
+ */
+
+#define LPC32XX_GPIOS 128
+
+static struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+
+/**
+ * We have 4 GPIO ports of 32 bits each
+ */
+
+#define MAX_GPIO 128
+
+#define GPIO_TO_PORT(gpio) ((gpio / 32) 3)
+#define GPIO_TO_RANK(gpio) (gpio % 32)
+#define GPIO_TO_MASK(gpio) (1 (gpio % 32))
+
+/**
+ * Array of current GPIO functions. Allocated as unsigned chars to
+ * limit memory consumption.
+ */
+
+static signed char lpc32xx_function[LPC32XX_GPIOS];
+
+/**
+ * Configure a GPIO number 'offset' as input
+ */
+
+static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ int port, mask;
+
+ port = GPIO_TO_PORT(offset);
+ mask = GPIO_TO_MASK
[U-Boot] [PATCH v2 1/8] lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 9 +
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 +
arch/arm/include/asm/arch-lpc32xx/config.h| 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/net/Makefile | 1 +
drivers/net/lpc32xx_eth.c | 636 ++
include/netdev.h | 1 +
7 files changed, 658 insertions(+)
create mode 100644 drivers/net/lpc32xx_eth.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..eec4d9e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include netdev.h
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/wdt.h
@@ -55,3 +56,11 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..062db8d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -37,3 +37,10 @@ void lpc32xx_uart_init(unsigned int uart_id)
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
clk-u3clk + (uart_id - 3));
}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+ | CLK_MAC_MII, clk-macclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h
b/arch/arm/include/asm/arch-lpc32xx/config.h
index 8f6426b..6c9526d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -50,6 +50,9 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
/* NOR Flash */
#if defined(CONFIG_SYS_FLASH_CFI)
#define CONFIG_FLASH_CFI_DRIVER
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 28812be..a6b8826 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -8,5 +8,6 @@
#define _LPC32XX_SYS_PROTO_H
void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46c4ac6..35fdb51 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
+obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
new file mode 100644
index 000..16c8ef0
--- /dev/null
+++ b/drivers/net/lpc32xx_eth.c
@@ -0,0 +1,636 @@
+/*
+ * LPC32xx Ethernet MAC interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include net.h
+#include malloc.h
+#include miiphy.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/types.h
+#include asm/system.h
+#include asm/byteorder.h
+#include asm/arch/cpu.h
+#include asm/arch/config.h
+
+/*
+ * Notes:
+ *
+ * 1. Unless specified otherwise, all references to tables or paragraphs
+ *are to UM10326, LPC32x0 and LPC32x0/01 User manual.
+ *
+ * 2. Only bitfield masks/values which are actually used by the driver
+ *are defined.
+ */
+
+/* a single RX descriptor. The controller has an array of these */
+struct lpc32xx_eth_rxdesc {
+ u32 packet; /* Receive packet pointer */
+ u32 control;/* Descriptor command status */
+};
+
+#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
+
+/* RX control bitfields/masks (see Table 330) */
+#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x07FF
+#define LPC32XX_ETH_RX_CTRL_UNUSED0x7800
+#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x8000
+
+/* a single RX status. The controller has an array of these */
+struct lpc32xx_eth_rxstat {
+ u32 statusinfo; /* Transmit Descriptor status */
+ u32 statushashcrc; /* Transmit Descriptor CRCs */
+};
+
+#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
+
+/* RX statusinfo bitfields/masks (see Table 333) */
+#define RX_STAT_RXSIZE 0x07FF
+/* Helper: OR of all errors except RANGE */
+#define RX_STAT_ERRORS 0x1B80
+
+/* a single TX descriptor
[U-Boot] [PATCH v2 2/8] lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/lpc32xx_nand_mlc.c | 589 ++
5 files changed, 601 insertions(+)
create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 062db8d..be4c93d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -44,3 +44,9 @@ void lpc32xx_mac_init(void)
writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
| CLK_MAC_MII, clk-macclk_ctrl);
}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15..bc7d33d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -147,6 +147,10 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 1)
+#define CLK_NAND_MLC_INT (1 5)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a6b8826..0c4e712 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -9,5 +9,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f02bfc..347ea62 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 000..cb23972
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -0,0 +1,589 @@
+/*
+ * LPC32xx MLC NAND flash controller driver
+ *
+ * (C) Copyright 2014 3ADEV http://3adev.com
+ * Written by Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * NOTE:
+ *
+ * The MLC NAND flash controller provides hardware Reed-Solomon ECC
+ * covering in- and out-of-band data together. Therefore, in- and out-
+ * of-band data must be written together in order to have a valid ECC.
+ *
+ * Consequently, pages with meaningful in-band data are written with
+ * blank (all-ones) out-of-band data and a valid ECC, and any later
+ * out-of-band data write will void the ECC.
+ *
+ * Therefore, code which reads such late-written out-of-band data
+ * should not rely on the ECC validity.
+ */
+
+#include common.h
+#include nand.h
+#include asm/errno.h
+#include asm/io.h
+#include nand.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+
+/*
+ * MLC NAND controller registers.
+ */
+struct lpc32xx_nand_mlc_registers {
+ u8 buff[32768]; /* controller's serial data buffer */
+ u8 data[32768]; /* NAND's raw data buffer */
+ u32 cmd;
+ u32 addr;
+ u32 ecc_enc_reg;
+ u32 ecc_dec_reg;
+ u32 ecc_auto_enc_reg;
+ u32 ecc_auto_dec_reg;
+ u32 rpr;
+ u32 wpr;
+ u32 rubp;
+ u32 robp;
+ u32 sw_wp_add_low;
+ u32 sw_wp_add_hig;
+ u32 icr;
+ u32 time_reg;
+ u32 irq_mr;
+ u32 irq_sr;
+ u32 lock_pr;
+ u32 isr;
+ u32 ceh;
+};
+
+/* LOCK_PR register defines */
+#define LOCK_PR_UNLOCK_KEY 0xA25E /* Magic unlock value */
+
+/* ICR defines */
+#define ICR_LARGE_BLOCKS 0x0004/* configure for 2KB blocks */
+#define ICR_ADDR40x0002/* configure for 4-word addrs */
+
+/* CEH defines */
+#define CEH_NORMAL_CE 0x0001 /* do not force CE ON */
+
+/* ISR register defines */
+#define ISR_NAND_READY0x0001
+#define ISR_CONTROLLER_READY 0x0002
+#define ISR_ECC_READY 0x0004
+#define ISR_DECODER_ERRORS(s) s) 4) 3)+1)
+#define
[U-Boot] [PATCH v2 5/8] lpc32xx: add LPC32xx SSP support (SPI mode)
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- added MUX setting for SSP0
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/lpc32xx_ssp.c | 132 ++
5 files changed, 151 insertions(+)
create mode 100644 drivers/spi/lpc32xx_ssp.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index a407098..5a453e3 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -8,11 +8,13 @@
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/uart.h
+#include asm/arch/mux.h
#include asm/io.h
#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
void lpc32xx_uart_init(unsigned int uart_id)
{
@@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum)
U_BOOT_DEVICE(lpc32xx_gpios) = {
.name = gpio_lpc32xx
};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, clk-ssp_ctrl);
+ /* Mux SSP0 pins */
+ writel(P_MUX_SET_SSP0, mux-p_mux_set);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 781ac07..2cb5703 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -155,6 +155,9 @@ struct clk_pm_regs {
#define CLK_NAND_MLC (1 1)
#define CLK_NAND_MLC_INT (1 5)
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 0)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a4a05d1..86d5ee9 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..ce6f1cc 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
new file mode 100644
index 000..40270df
--- /dev/null
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -0,0 +1,132 @@
+/*
+ * LPC32xx SSP interface (SPI mode)
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/compat.h
+#include asm/io.h
+#include malloc.h
+#include spi.h
+#include asm/arch/clk.h
+
+/* SSP chip registers */
+struct ssp_regs {
+ u32 cr0;
+ u32 cr1;
+ u32 data;
+ u32 sr;
+ u32 cpsr;
+ u32 imsc;
+ u32 ris;
+ u32 mis;
+ u32 icr;
+ u32 dmacr;
+};
+
+/* CR1 register defines */
+#define SSP_CR1_SSP_ENABLE 0x0002
+
+/* SR register defines */
+#define SSP_SR_TNF 0x0002
+/* SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE 0x0004
+
+static struct ssp_regs *ssp0_regs = (struct ssp_regs *)SSP0_BASE;
+
+static struct spi_slave ssp0_slave = {
+ .bus = 0,
+ .cs = 0,
+ .op_mode_rx = 0,
+ .op_mode_tx = 0,
+ .wordlen = 8,
+ .max_write_size = 1, /* this is for SPI FLASHes -- don't care */
+ .memory_map = NULL, /* for SPI FLASHes too */
+ .option = 0,
+ .flags = 0
+};
+
+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
+void spi_init(void)
+{
+ /*
+* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
+* and configuration will be done in spi_setup_slave()
+ */
+}
+
+/* the following is called in sequence by do_spi_xfer() */
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+ /* we only set up SSP0 for now, so ignore bus */
+
+ if (mode SPI_3WIRE) {
+ error(3-wire mode not supported);
+ return NULL
[U-Boot] [PATCH v2 6/8] dtt: add ds620 support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- cosmetic: added a blank line before copyright
drivers/hwmon/Makefile | 1 +
drivers/hwmon/ds620.c | 65 ++
include/dtt.h | 15 ++--
3 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 drivers/hwmon/ds620.c
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 25b8e8a..b4fb057 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_DTT_ADT7460) += adt7460.o
obj-$(CONFIG_DTT_DS1621) += ds1621.o
obj-$(CONFIG_DTT_DS1722) += ds1722.o
obj-$(CONFIG_DTT_DS1775) += ds1775.o
+obj-$(CONFIG_DTT_DS620) += ds620.o
obj-$(CONFIG_DTT_LM63) += lm63.o
obj-$(CONFIG_DTT_LM73) += lm73.o
obj-$(CONFIG_DTT_LM75) += lm75.o
diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c
new file mode 100644
index 000..1ecc3da
--- /dev/null
+++ b/drivers/hwmon/ds620.c
@@ -0,0 +1,65 @@
+/*
+ * DS620 DTT support
+ *
+ * (C) Copyright 2014 3ADEV http://www.3adev.com
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
+ */
+
+#include common.h
+#include i2c.h
+#include dtt.h
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48
+#define DTT_START_CONVERT 0x51
+#define DTT_TEMP 0xAA
+#define DTT_CONFIG 0xAC
+
+/*
+ * Config register MSB bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_AUTOC 0x02
+#define DTT_CONFIG_R0 0x04 /* always 1 */
+#define DTT_CONFIG_R1 0x08 /* always 1 */
+#define DTT_CONFIG_TLF 0x10
+#define DTT_CONFIG_THF 0x20
+#define DTT_CONFIG_NVB 0x40
+#define DTT_CONFIG_DONE0x80
+
+#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor 0x07))
+
+int dtt_init_one(int sensor)
+{
+ uint8_t config = DTT_CONFIG_1SHOT
+ | DTT_CONFIG_R0
+ | DTT_CONFIG_R1;
+ return i2c_write(CHIP(sensor), DTT_CONFIG, 1, config, 1);
+}
+
+int dtt_get_temp(int sensor)
+{
+ uint8_t status;
+ uint8_t temp[2];
+
+ /* Start a conversion, may take up to 1 second. */
+ i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0);
+ do {
+ if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, status, 1))
+ /* bail out if I2C error */
+ status |= DTT_CONFIG_DONE;
+ } while (!(status DTT_CONFIG_DONE));
+ if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2))
+ /* bail out if I2C error */
+ return -274; /* below absolute zero == error */
+
+ return ((int16_t)(temp[1] | (temp[0] 8))) 7;
+}
diff --git a/include/dtt.h b/include/dtt.h
index 058bca4..173159d 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -12,13 +12,14 @@
#define _DTT_H_
#if defined(CONFIG_DTT_ADM1021)|| \
-defined(CONFIG_DTT_ADT7460)|| \
-defined(CONFIG_DTT_DS1621) || \
-defined(CONFIG_DTT_DS1775) || \
-defined(CONFIG_DTT_LM63) || \
-defined(CONFIG_DTT_LM73) || \
-defined(CONFIG_DTT_LM75) || \
-defined(CONFIG_DTT_LM81)
+ defined(CONFIG_DTT_ADT7460) || \
+ defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
+ defined(CONFIG_DTT_DS620) || \
+ defined(CONFIG_DTT_LM63)|| \
+ defined(CONFIG_DTT_LM73)|| \
+ defined(CONFIG_DTT_LM75)|| \
+ defined(CONFIG_DTT_LM81)
#define CONFIG_DTT /* We have a DTT */
--
2.1.0
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 8/8] lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
- EEPROM (24M01-compatible)
- RTC (DS1374-compatible)
- Temperature sensor (DS620)
- DACs (2 x MAX518)
- SPI (through SSP interface)
- Port expander MAX6957
- LCD display (HD44780-compatible), controlled
through the port expander and DACs
This board has SPL support, and uses the LPC32XX boot
image format.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2: None
arch/arm/Kconfig | 6 +
arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 +
arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 4 +
arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 80 +
arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 +++
arch/arm/include/asm/arch-lpc32xx/clk.h| 5 +
arch/arm/include/asm/arch-lpc32xx/cpu.h| 1 +
arch/arm/include/asm/arch-lpc32xx/mux.h| 18 ++
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 4 +-
board/work-microwave/work_92105/Kconfig| 15 +
board/work-microwave/work_92105/MAINTAINERS| 6 +
board/work-microwave/work_92105/Makefile | 8 +
board/work-microwave/work_92105/README | 23 ++
board/work-microwave/work_92105/work_92105.c | 86 +
.../work-microwave/work_92105/work_92105_display.c | 349 +
.../work-microwave/work_92105/work_92105_display.h | 14 +
configs/work_92105_defconfig | 5 +
include/configs/work_92105.h | 259 +++
19 files changed, 963 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c
create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h
create mode 100644 board/work-microwave/work_92105/Kconfig
create mode 100644 board/work-microwave/work_92105/MAINTAINERS
create mode 100644 board/work-microwave/work_92105/Makefile
create mode 100644 board/work-microwave/work_92105/README
create mode 100644 board/work-microwave/work_92105/work_92105.c
create mode 100644 board/work-microwave/work_92105/work_92105_display.c
create mode 100644 board/work-microwave/work_92105/work_92105_display.h
create mode 100644 configs/work_92105_defconfig
create mode 100644 include/configs/work_92105.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 47806f8..42983a3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -247,6 +247,11 @@ config TARGET_DEVKIT3250
bool Support devkit3250
select CPU_ARM926EJS
+config TARGET_WORK_92105
+ bool Support work_92105
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
config TARGET_JADECPU
bool Support jadecpu
select CPU_ARM926EJS
@@ -999,6 +1004,7 @@ source board/udoo/Kconfig
source board/vpac270/Kconfig
source board/wandboard/Kconfig
source board/woodburn/Kconfig
+source board/work-microwave/work_92105/Kconfig
source board/xaeniax/Kconfig
source board/zipitz2/Kconfig
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
index 314f004..4837377 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
@@ -6,3 +6,5 @@
#
obj-y = cpu.o clk.o devices.o timer.o
+
+obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index b7a44d5..1ef8a36 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -98,6 +98,40 @@ unsigned int get_periph_clk_rate(void)
return get_hclk_pll_rate() / get_periph_clk_div();
}
+unsigned int get_sdram_clk_rate(void)
+{
+ unsigned int src_clk;
+
+ if (!(readl(clk-pwr_ctrl) CLK_PWR_NORMAL_RUN))
+ return get_sys_clk_rate();
+
+ src_clk = get_hclk_pll_rate();
+
+ if (readl(clk-sdramclk_ctrl) CLK_SDRAM_DDR_SEL) {
+ /* using DDR */
+ switch (readl(clk-hclkdiv_ctrl) CLK_HCLK_DDRAM_MASK) {
+ case CLK_HCLK_DDRAM_HALF:
+ return src_clk/2;
+ case CLK_HCLK_DDRAM_NOMINAL:
+ return src_clk;
+ default:
+ return 0;
+ }
+ } else {
+ /* using SDR */
+ switch (readl(clk-hclkdiv_ctrl) CLK_HCLK_ARM_PLL_DIV_MASK) {
+ case CLK_HCLK_ARM_PLL_DIV_4:
+ return src_clk/4;
+ case CLK_HCLK_ARM_PLL_DIV_2:
+ return src_clk/2;
+ case CLK_HCLK_ARM_PLL_DIV_1:
+ return src_clk;
+ default:
+ return 0
[U-Boot] [PATCH v2] omap3: add support for QUIPOS Cairo board.
This patch extends OMAP3 support for AM/DM37xx and
introduces the AM3703-based Quipos Cairo board.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
NOTES:
Two checkpatch diagnostics are left uncorrected:
1. warning: arch/arm/cpu/armv7/omap3/Kconfig,94: please write
a paragraph that describes the config symbol fully
No other symbol of the same nature has such a paragraph,
so I left it out.
2. check: board/quipos/cairo/cairo.c,87: Avoid CamelCase:
SDP_3430_SDRC_RFR_CTRL_165MHz
Symbol was not defined in this patch. If requested, I will
post a separate change to fix the symbol.
Changes in v2:
- removed v1 patches 1..5 applied to mainline
- corrected serial device name from ttyS1 to ttyO1
- rewrote config file based on omap3_beagle's
- moved serial support to DM
- fixed environment
arch/arm/cpu/armv7/omap3/Kconfig | 5 +
board/quipos/cairo/Kconfig | 12 ++
board/quipos/cairo/Makefile | 8 +
board/quipos/cairo/cairo.c | 110 ++
board/quipos/cairo/cairo.h | 319 +++
configs/cairo_defconfig | 4 +
include/configs/omap3_cairo.h| 286 +++
7 files changed, 744 insertions(+)
create mode 100644 board/quipos/cairo/Kconfig
create mode 100644 board/quipos/cairo/Makefile
create mode 100644 board/quipos/cairo/cairo.c
create mode 100644 board/quipos/cairo/cairo.h
create mode 100644 configs/cairo_defconfig
create mode 100644 include/configs/omap3_cairo.h
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index a029379..88a9544 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -91,6 +91,10 @@ config TARGET_TWISTER
bool Twister
select SUPPORT_SPL
+config TARGET_OMAP3_CAIRO
+ bool QUIPOS CAIRO
+ select SUPPORT_SPL
+
endchoice
config SYS_SOC
@@ -118,5 +122,6 @@ source board/matrix_vision/mvblx/Kconfig
source board/nokia/rx51/Kconfig
source board/technexion/tao3530/Kconfig
source board/technexion/twister/Kconfig
+source board/quipos/cairo/Kconfig
endif
diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig
new file mode 100644
index 000..8df9421
--- /dev/null
+++ b/board/quipos/cairo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_CAIRO
+
+config SYS_BOARD
+ default cairo
+
+config SYS_VENDOR
+ default quipos
+
+config SYS_CONFIG_NAME
+ default omap3_cairo
+
+endif
diff --git a/board/quipos/cairo/Makefile b/board/quipos/cairo/Makefile
new file mode 100644
index 000..445088f
--- /dev/null
+++ b/board/quipos/cairo/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014 DENX Software Engineering
+# Written-By: Albert ARIBAUD albert.arib...@3adev.fr
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cairo.o
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
new file mode 100644
index 000..b97a09a
--- /dev/null
+++ b/board/quipos/cairo/cairo.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014 DENX
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Derived from code written by Robert Aigner (r...@spiid.net)
+ *
+ * Itself derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff r-woodru...@ti.com
+ * Syed Mohammed Khasim kha...@ti.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include dm.h
+#include netdev.h
+#include ns16550.h
+#include asm/io.h
+#include asm/arch/mem.h
+#include asm/arch/mux.h
+#include asm/arch/sys_proto.h
+#include i2c.h
+#include asm/mach-types.h
+#include asm/omap_mmc.h
+#include cairo.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * MUSB port on OMAP3EVM Rev = E requires extvbus programming.
+ */
+u8 omap3_evm_need_extvbus(void)
+{
+ u8 retval = 0;
+
+ /* TODO: verify if cairo handheld platform needs extvbus programming */
+
+ return retval;
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd-bd-bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
+ /* boot param addr */
+ gd-bd-bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_CAIRO();
+}
+
+#if defined(CONFIG_GENERIC_MMC) !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory
Re: [U-Boot] [PATCH v1 6/6] omap3: add support for QUIPOS Cairo board.
Hello Simon, On Fri, 16 Jan 2015 10:20:15 -0700, Simon Glass s...@chromium.org wrote: Hi Albert, On 16 January 2015 at 01:09, Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr wrote: Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- arch/arm/cpu/armv7/omap3/Kconfig | 5 + board/quipos/cairo/Kconfig | 12 ++ board/quipos/cairo/Makefile | 8 + board/quipos/cairo/cairo.c | 90 board/quipos/cairo/cairo.h | 321 configs/cairo_defconfig | 4 + include/configs/omap3_cairo.h| 437 +++ 7 files changed, 877 insertions(+) create mode 100644 board/quipos/cairo/Kconfig create mode 100644 board/quipos/cairo/Makefile create mode 100644 board/quipos/cairo/cairo.c create mode 100644 board/quipos/cairo/cairo.h create mode 100644 configs/cairo_defconfig create mode 100644 include/configs/omap3_cairo.h Can this use driver model for serial? We are just creating problems for future otherwise. Will do in v2. Regards, Simon Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 7/8] lpc32xx: add lpc32xx-spl.bin boot image target
Hello Marek, On Fri, 16 Jan 2015 14:08:58 +0100, Marek Vasut ma...@denx.de wrote: On Friday, January 16, 2015 at 08:19:19 AM, Albert ARIBAUD (3ADEV) wrote: Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- Makefile | 3 + scripts/Makefile.spl | 11 tools/.gitignore | 1 + tools/Makefile| 2 + tools/mklpc32xxboot.c | 169 ++ 5 files changed, 186 insertions(+) create mode 100644 tools/mklpc32xxboot.c Hi! Are you positive this shouldn't be part of mkimage please ? No, I'm not positive. :) I'll move this to mkimage in v2. Best regards, Marek Vasut Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 4/8] lpc32xx: add GPIO support
Hello Simon, On Fri, 16 Jan 2015 10:17:52 -0700, Simon Glass s...@chromium.org wrote: Hi Albert, On 16 January 2015 at 00:19, Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr wrote: Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ drivers/gpio/Makefile| 1 + drivers/gpio/lpc32xx_gpio.c | 223 +++ 3 files changed, 267 insertions(+) create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h create mode 100644 drivers/gpio/lpc32xx_gpio.c This should be done with driver model these days. I'll move it to DM in v2. Regards, Simon Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 2/6] omap3: make SDRC SHARING setting configurable
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/cpu/armv7/omap3/sdrc.c | 6 +-
arch/arm/include/asm/arch-omap3/sys_proto.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 7a29131..4f15ac9 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -135,6 +135,9 @@ void do_sdrc_init(u32 cs, u32 early)
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+ /* set some default timings */
+ timings.sharing = SDRC_SHARING;
+
/*
* When called in the early context this may be SPL and we will
* need to set all of the timings. This ends up being board
@@ -145,6 +148,7 @@ void do_sdrc_init(u32 cs, u32 early)
* setup CS1.
*/
#ifdef CONFIG_SPL_BUILD
+ /* set/modify board-specific timings */
get_board_mem_timings(timings);
#endif
if (early) {
@@ -155,7 +159,7 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, sdrc_base-sysconfig);
/* setup sdrc to ball mux */
- writel(SDRC_SHARING, sdrc_base-sharing);
+ writel(timings.sharing, sdrc_base-sharing);
/* Disable Power Down of CKE because of 1 CKE on combo part */
writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h
b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 34bd8c5..bcf92fb 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -23,6 +23,7 @@ struct emu_hal_params {
/* Board SDRC timing values */
struct board_sdrc_timings {
+ u32 sharing;
u32 mcfg;
u32 ctrla;
u32 ctrlb;
--
2.1.0
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[U-Boot] [PATCH v1 1/6] omap3: enable GP9 timer and UART2
These are needed for the upcoming Cairo board support. Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- arch/arm/cpu/armv7/omap3/clock.c | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 529ad9a..006969e 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -732,11 +732,20 @@ void per_clocks_enable(void) setbits_le32(prcm_base-iclken_per, 0x08); /* ICKen GPT2 */ setbits_le32(prcm_base-fclken_per, 0x08); /* FCKen GPT2 */ + /* Enable GP9 timer. */ + setbits_le32(prcm_base-clksel_per, 0x80); /* GPT9 = 32kHz clk */ + setbits_le32(prcm_base-iclken_per, 0x400);/* ICKen GPT9 */ + setbits_le32(prcm_base-fclken_per, 0x400);/* FCKen GPT9 */ + #ifdef CONFIG_SYS_NS16550 /* Enable UART1 clocks */ setbits_le32(prcm_base-fclken1_core, 0x2000); setbits_le32(prcm_base-iclken1_core, 0x2000); + /* Enable UART2 clocks */ + setbits_le32(prcm_base-fclken1_core, 0x4000); + setbits_le32(prcm_base-iclken1_core, 0x4000); + /* UART 3 Clocks */ setbits_le32(prcm_base-fclken_per, 0x0800); setbits_le32(prcm_base-iclken_per, 0x0800); -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 0/6] This series extends OMAP3 support for AM/DM37xx and
introduces the AM3703-based Quipos Cairo board. NOTES: Two checkpatch diagnostics are left uncorrected: 1. warning: arch/arm/cpu/armv7/omap3/Kconfig,94: please write a paragraph that describes the config symbol fully No other symbol of the same nature has such a paragraph, so I left it out. 2. check: board/quipos/cairo/cairo.c,87: Avoid CamelCase: SDP_3430_SDRC_RFR_CTRL_165MHz Symbol was not defined in this patch. If requested, I will post a separate change to fix the symbol. Albert ARIBAUD (3ADEV) (6): omap3: enable GP9 timer and UART2 omap3: make SDRC SHARING setting configurable omap3: add SDRC settings for Samsung K4X51163PG omap3: mmc: add 1.8v bias setting for MMC1 omap3: add some MUX definitions for upcoming cairo omap3: add support for QUIPOS Cairo board. arch/arm/cpu/armv7/omap3/Kconfig | 5 + arch/arm/cpu/armv7/omap3/clock.c | 9 + arch/arm/cpu/armv7/omap3/sdrc.c| 6 +- arch/arm/include/asm/arch-omap3/mem.h | 43 +++ arch/arm/include/asm/arch-omap3/mmc_host_def.h | 1 + arch/arm/include/asm/arch-omap3/mux.h | 51 ++- arch/arm/include/asm/arch-omap3/sys_proto.h| 1 + board/quipos/cairo/Kconfig | 12 + board/quipos/cairo/Makefile| 8 + board/quipos/cairo/cairo.c | 90 + board/quipos/cairo/cairo.h | 321 ++ configs/cairo_defconfig| 4 + drivers/mmc/omap_hsmmc.c | 4 + include/configs/omap3_cairo.h | 437 + 14 files changed, 989 insertions(+), 3 deletions(-) create mode 100644 board/quipos/cairo/Kconfig create mode 100644 board/quipos/cairo/Makefile create mode 100644 board/quipos/cairo/cairo.c create mode 100644 board/quipos/cairo/cairo.h create mode 100644 configs/cairo_defconfig create mode 100644 include/configs/omap3_cairo.h -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 5/6] omap3: add some MUX definitions for upcoming cairo
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- arch/arm/include/asm/arch-omap3/mux.h | 51 +-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index eba4a5c..3277b40 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -15,6 +15,12 @@ * PTU - Pull type Up * DIS - Pull type selection is inactive * EN - Pull type selection is active + * SB_LOW - Standby mode configuration: Output low-level + * SB_HI - Standby mode configuration: Output high-level + * SB_HIZ - Standby mode configuration: Output hi-impedence + * SB_PD - Standby mode pull-down enabled + * SB_PU - Standby mode pull-up enabled + * WKEN - Wakeup input enabled * M0 - Mode 0 */ @@ -26,6 +32,13 @@ #define EN (1 3) #define DIS(0 3) +#define SB_LOW (1 9) +#define SB_HI (5 9) +#define SB_HIZ (2 9) +#define SB_PD (1 12) +#define SB_PU (3 12) +#define WKEN (1 14) + #define M0 0 #define M1 1 #define M2 2 @@ -36,8 +49,8 @@ #define M7 7 /* - * To get the actual address the offset has to added - * with OMAP34XX_CTRL_BASE to get the actual address + * To get the actual address the offset has to be added + * to OMAP34XX_CTRL_BASE */ /*SDRC*/ @@ -78,6 +91,33 @@ #define CONTROL_PADCONF_SDRC_DQS1 0x0074 #define CONTROL_PADCONF_SDRC_DQS2 0x0076 #define CONTROL_PADCONF_SDRC_DQS3 0x0078 +#define CONTROL_PADCONF_SDRC_BA0 0x05A0 +#define CONTROL_PADCONF_SDRC_BA1 0x05A2 +#define CONTROL_PADCONF_SDRC_A00x05A4 +#define CONTROL_PADCONF_SDRC_A10x05A6 +#define CONTROL_PADCONF_SDRC_A20x05A8 +#define CONTROL_PADCONF_SDRC_A30x05AA +#define CONTROL_PADCONF_SDRC_A40x05AC +#define CONTROL_PADCONF_SDRC_A50x05AE +#define CONTROL_PADCONF_SDRC_A60x05B0 +#define CONTROL_PADCONF_SDRC_A70x05B2 +#define CONTROL_PADCONF_SDRC_A80x05B4 +#define CONTROL_PADCONF_SDRC_A90x05B6 +#define CONTROL_PADCONF_SDRC_A10 0x05B8 +#define CONTROL_PADCONF_SDRC_A11 0x05BA +#define CONTROL_PADCONF_SDRC_A12 0x05BC +#define CONTROL_PADCONF_SDRC_A13 0x05BE +#define CONTROL_PADCONF_SDRC_A14 0x05C0 +#define CONTROL_PADCONF_SDRC_NCS0 0x05C2 +#define CONTROL_PADCONF_SDRC_NCS1 0x05C4 +#define CONTROL_PADCONF_SDRC_NCLK 0x05C6 +#define CONTROL_PADCONF_SDRC_NRAS 0x05C8 +#define CONTROL_PADCONF_SDRC_NCAS 0x05CA +#define CONTROL_PADCONF_SDRC_NWE 0x05CC +#define CONTROL_PADCONF_SDRC_DM0 0x05CE +#define CONTROL_PADCONF_SDRC_DM1 0x05D0 +#define CONTROL_PADCONF_SDRC_DM2 0x05D2 +#define CONTROL_PADCONF_SDRC_DM3 0x05D4 /*GPMC*/ #define CONTROL_PADCONF_GPMC_A10x007A #define CONTROL_PADCONF_GPMC_A20x007C @@ -89,6 +129,7 @@ #define CONTROL_PADCONF_GPMC_A80x0088 #define CONTROL_PADCONF_GPMC_A90x008A #define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_A11 0x0264 #define CONTROL_PADCONF_GPMC_D00x008E #define CONTROL_PADCONF_GPMC_D10x0090 #define CONTROL_PADCONF_GPMC_D20x0092 @@ -323,6 +364,8 @@ #define CONTROL_PADCONF_ETK_D13_ES20x05F6 #define CONTROL_PADCONF_ETK_D14_ES20x05F8 #define CONTROL_PADCONF_ETK_D15_ES20x05FA +#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E +#define CONTROL_PADCONF_JTAG_TDO 0x0A50 /*Die to Die */ #define CONTROL_PADCONF_D2D_MCAD0 0x01E4 #define CONTROL_PADCONF_D2D_MCAD1 0x01E6 @@ -433,6 +476,10 @@ #define CONTROL_PADCONF_SYS_BOOT8 0x0226 /* AM/DM37xx specific */ +#define CONTROL_PADCONF_GPIO1120x0134 +#define CONTROL_PADCONF_GPIO1130x0136 +#define CONTROL_PADCONF_GPIO1140x0138 +#define CONTROL_PADCONF_GPIO1150x013A #define CONTROL_PADCONF_GPIO1270x0A54 #define CONTROL_PADCONF_GPIO1260x0A56 #define CONTROL_PADCONF_GPIO1280x0A58 -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 4/6] omap3: mmc: add 1.8v bias setting for MMC1
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/include/asm/arch-omap3/mmc_host_def.h | 1 +
drivers/mmc/omap_hsmmc.c | 4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index 0ba621a..9f2896c 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -51,6 +51,7 @@ typedef struct t2 {
#define PBIASLITEPWRDNZ0 (1 1)
#define PBIASSPEEDCTRL0(1 2)
#define PBIASLITEPWRDNZ1 (1 9)
+#define PBIASLITEVMODE0(1 0)
#define CTLPROGIO1SPEEDCTRL(1 20)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index c880ced..dc725cb 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -134,6 +134,10 @@ static unsigned char mmc_board_init(struct mmc *mmc)
pbias_lite = readl(t2_base-pbias_lite);
pbias_lite = ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
+#ifdef CONFIG_TARGET_OMAP3_CAIRO
+ /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
+ pbias_lite = ~PBIASLITEVMODE0;
+#endif
writel(pbias_lite, t2_base-pbias_lite);
writel(pbias_lite | PBIASLITEPWRDNZ1 |
--
2.1.0
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[U-Boot] [PATCH v1 6/6] omap3: add support for QUIPOS Cairo board.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/cpu/armv7/omap3/Kconfig | 5 +
board/quipos/cairo/Kconfig | 12 ++
board/quipos/cairo/Makefile | 8 +
board/quipos/cairo/cairo.c | 90
board/quipos/cairo/cairo.h | 321
configs/cairo_defconfig | 4 +
include/configs/omap3_cairo.h| 437 +++
7 files changed, 877 insertions(+)
create mode 100644 board/quipos/cairo/Kconfig
create mode 100644 board/quipos/cairo/Makefile
create mode 100644 board/quipos/cairo/cairo.c
create mode 100644 board/quipos/cairo/cairo.h
create mode 100644 configs/cairo_defconfig
create mode 100644 include/configs/omap3_cairo.h
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index a029379..88a9544 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -91,6 +91,10 @@ config TARGET_TWISTER
bool Twister
select SUPPORT_SPL
+config TARGET_OMAP3_CAIRO
+ bool QUIPOS CAIRO
+ select SUPPORT_SPL
+
endchoice
config SYS_SOC
@@ -118,5 +122,6 @@ source board/matrix_vision/mvblx/Kconfig
source board/nokia/rx51/Kconfig
source board/technexion/tao3530/Kconfig
source board/technexion/twister/Kconfig
+source board/quipos/cairo/Kconfig
endif
diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig
new file mode 100644
index 000..8df9421
--- /dev/null
+++ b/board/quipos/cairo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_CAIRO
+
+config SYS_BOARD
+ default cairo
+
+config SYS_VENDOR
+ default quipos
+
+config SYS_CONFIG_NAME
+ default omap3_cairo
+
+endif
diff --git a/board/quipos/cairo/Makefile b/board/quipos/cairo/Makefile
new file mode 100644
index 000..445088f
--- /dev/null
+++ b/board/quipos/cairo/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014 DENX Software Engineering
+# Written-By: Albert ARIBAUD albert.arib...@3adev.fr
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cairo.o
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
new file mode 100644
index 000..f769016
--- /dev/null
+++ b/board/quipos/cairo/cairo.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2014 DENX
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Derived from code written by Robert Aigner (r...@spiid.net)
+ *
+ * Itself derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff r-woodru...@ti.com
+ * Syed Mohammed Khasim kha...@ti.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include netdev.h
+#include ns16550.h
+#include asm/io.h
+#include asm/arch/mem.h
+#include asm/arch/mux.h
+#include asm/arch/sys_proto.h
+#include i2c.h
+#include asm/mach-types.h
+#include asm/omap_mmc.h
+#include cairo.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * MUSB port on OMAP3EVM Rev = E requires extvbus programming.
+ */
+u8 omap3_evm_need_extvbus(void)
+{
+ u8 retval = 0;
+
+ /* TODO: verify if cairo handheld platform needs extvbus programming */
+
+ return retval;
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd-bd-bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
+ /* boot param addr */
+ gd-bd-bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_CAIRO();
+}
+
+#if defined(CONFIG_GENERIC_MMC) !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory.
+ *
+ * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings-sharing = SAMSUNG_SHARING;
+ timings-mcfg = SAMSUNG_V_MCFG_165(128 20);
+ timings-ctrla = SAMSUNG_V_ACTIMA_165;
+ timings-ctrlb = SAMSUNG_V_ACTIMB_165;
+ timings-rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings-mr = SAMSUNG_V_MR_165;
+}
+#endif
diff --git a/board/quipos/cairo/cairo.h b/board/quipos/cairo/cairo.h
new file mode 100644
index 000..d67e932
--- /dev/null
+++ b/board/quipos/cairo/cairo.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (C) DENX
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Original code (C) Copyright 2010
+ * Robert Aigner (r...@spiid.net)
+ *
+ * SPDX-License-Identifier:GPL-2.0
[U-Boot] [PATCH v1 3/6] omap3: add SDRC settings for Samsung K4X51163PG
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/include/asm/arch-omap3/mem.h | 43 +++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/include/asm/arch-omap3/mem.h
b/arch/arm/include/asm/arch-omap3/mem.h
index 0b78c1c..3ce270c 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -249,6 +249,49 @@ enum {
#define MICRON_RASWIDTH_20014
#define MICRON_V_MCFG_200(size)MCFG((size), MICRON_RASWIDTH_200)
+/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
+#define SAMSUNG_TDAL_165 5
+#define SAMSUNG_TDPL_165 2
+#define SAMSUNG_TRRD_165 2
+#define SAMSUNG_TRCD_165 3
+#define SAMSUNG_TRP_1653
+#define SAMSUNG_TRAS_165 7
+#define SAMSUNG_TRC_16510
+#define SAMSUNG_TRFC_165 12
+
+#define SAMSUNG_V_ACTIMA_165 \
+ ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
+ SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
+ SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
+ SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
+
+#define SAMSUNG_TWTR_165 1
+#define SAMSUNG_TCKE_165 2
+#define SAMSUNG_XSR_16520
+#define SAMSUNG_TXP_1655
+
+#define SAMSUNG_V_ACTIMB_165 \
+ ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
+ SAMSUNG_TXP_165, SAMSUNG_XSR_165)
+
+#define SAMSUNG_RASWIDTH_165 14
+#define SAMSUNG_V_MCFG_165(size) \
+ V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
+ V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
+ V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
+
+/* TODO: find which register these were taken from */
+
+#define SAMSUNG_BL_165 0x2
+#define SAMSUNG_SIL_1650x0
+#define SAMSUNG_CASL_165 0x3
+#define SAMSUNG_WBST_165 0x0
+#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 9) | \
+ (SAMSUNG_CASL_165 4) | (SAMSUNG_SIL_165 3) | \
+ (SAMSUNG_BL_165))
+
+#define SAMSUNG_SHARING 0x3700
+
/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck*/
/* 15/6 + 18/6 = 5.5 - 6 */
--
2.1.0
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[U-Boot] [PATCH v1 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: The series is not entirely checkpatch-clean. The following warnings and checks were not fixed: 1. warning: tools/mklpc32xxboot.c,81: quoted string split across lines There seems to be no way to remove this error without making the line longer than 80 characters, which causes checkpatch to complain. 2. warning: arch/arm/Kconfig,241: please write a paragraph that describes the config symbol fully Other symbols in the same file have no description either. For consistency, I did not add the requested description. 3. check: include/configs/work_92105.h,177: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 Makefile | 3 + arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 30 + arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 80 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h| 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 2 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 8 + board/work-microwave/work_92105/README | 23 + board/work-microwave/work_92105/work_92105.c | 85 +++ .../work-microwave/work_92105/work_92105_display.c | 345 +++ .../work-microwave/work_92105/work_92105_display.h | 14 + configs/work_92105_defconfig | 3 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c| 223 drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 +++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c| 589 +++ drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 636 + drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 132 + include/configs/work_92105.h | 257 + include/dtt.h | 15 +- include/netdev.h | 1 + scripts/Makefile.spl | 11 + tools/.gitignore | 1 + tools/Makefile | 2 + tools/mklpc32xxboot.c | 169 ++ 40 files changed, 3132 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 configs/work_92105_defconfig create mode 100644 drivers/gpio/lpc32xx_gpio.c create mode 100644 drivers/hwmon/ds620.c create mode 100644 drivers/i2c/lpc32xx_i2c.c create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c create mode 100644 drivers/net/lpc32xx_eth.c create mode 100644 drivers/spi/lpc32xx_ssp.c create mode 100644 include/configs/work_92105.h create mode 100644 tools/mklpc32xxboot.c -- 2.1.0 ___ U
[U-Boot] [PATCH v1 3/8] lpc32xx: i2c: add LPC32xx I2C interface support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/i2c/Makefile | 1 +
drivers/i2c/lpc32xx_i2c.c | 249 ++
6 files changed, 268 insertions(+)
create mode 100644 drivers/i2c/lpc32xx_i2c.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index be4c93d..81b53ea 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void)
/* Enable NAND interface */
writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(clk-i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, clk-i2cclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index bc7d33d..781ac07 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -123,6 +123,10 @@ struct clk_pm_regs {
#define CLK_MAC_SLAVE (1 1)
#define CLK_MAC_REG(1 0)
+/* I2C Clock Control Register bits */
+#define CLK_I2C2_ENABLE(1 1)
+#define CLK_I2C1_ENABLE(1 0)
+
/* Timer Clock Control1 Register bits */
#define CLK_TIMCLK_MOTOR (1 6)
#define CLK_TIMCLK_TIMER3 (1 5)
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h
b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a0..1067107 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -37,6 +37,8 @@
#define UART4_BASE 0x40088000 /* UART 4 registers base*/
#define UART5_BASE 0x4009 /* UART 5 registers base*/
#define UART6_BASE 0x40098000 /* UART 6 registers base*/
+#define I2C1_BASE 0x400A /* I2C 1 registers base*/
+#define I2C2_BASE 0x400A8000 /* I2C 2 registers base*/
/* External SDRAM Memory Bank base addresses */
#define EMC_DYCS0_BASE 0x8000 /* SDRAM DYCS0 base address */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 0c4e712..a4a05d1 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -10,5 +10,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 6f3c86c..b7b45b1 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
new file mode 100644
index 000..78d26e4
--- /dev/null
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -0,0 +1,249 @@
+/*
+ * LPC32xx I2C interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include i2c.h
+#include asm/errno.h
+#include asm/arch/clk.h
+
+/*
+ * Provide default speed and slave if target did not
+ */
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
+#define CONFIG_SYS_I2C_LPC32XX_SPEED 35
+#endif
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
+#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
+#endif
+
+/* i2c register set */
+struct lpc32xx_i2c_registers {
+ union {
+ u32 rx;
+ u32 tx;
+ };
+ u32 stat;
+ u32 ctrl;
+ u32 clk_hi;
+ u32 clk_lo;
+ u32 adr;
+ u32 rxfl;
+ u32 txfl;
+ u32 rxb;
+ u32 txb;
+ u32 stx;
+ u32 stxfl;
+};
+
+/* TX register fields */
+#define LPC32XX_I2C_TX_START 0x0100
+#define LPC32XX_I2C_TX_STOP0x0200
+
+/* Control register values */
+#define LPC32XX_I2C_SOFT_RESET 0x0100
+
+/* Status register values */
+#define LPC32XX_I2C_STAT_TFF 0x0400
+#define LPC32XX_I2C_STAT_RFE 0x0200
+#define
[U-Boot] [PATCH v1 1/8] lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 9 +
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 +
arch/arm/include/asm/arch-lpc32xx/config.h| 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/net/Makefile | 1 +
drivers/net/lpc32xx_eth.c | 636 ++
include/netdev.h | 1 +
7 files changed, 658 insertions(+)
create mode 100644 drivers/net/lpc32xx_eth.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..eec4d9e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include netdev.h
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/wdt.h
@@ -55,3 +56,11 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..062db8d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -37,3 +37,10 @@ void lpc32xx_uart_init(unsigned int uart_id)
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
clk-u3clk + (uart_id - 3));
}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+ | CLK_MAC_MII, clk-macclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h
b/arch/arm/include/asm/arch-lpc32xx/config.h
index 8f6426b..6c9526d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -50,6 +50,9 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
/* NOR Flash */
#if defined(CONFIG_SYS_FLASH_CFI)
#define CONFIG_FLASH_CFI_DRIVER
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 28812be..a6b8826 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -8,5 +8,6 @@
#define _LPC32XX_SYS_PROTO_H
void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index fb0cf8c..61197fb 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
+obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
new file mode 100644
index 000..16c8ef0
--- /dev/null
+++ b/drivers/net/lpc32xx_eth.c
@@ -0,0 +1,636 @@
+/*
+ * LPC32xx Ethernet MAC interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include net.h
+#include malloc.h
+#include miiphy.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/types.h
+#include asm/system.h
+#include asm/byteorder.h
+#include asm/arch/cpu.h
+#include asm/arch/config.h
+
+/*
+ * Notes:
+ *
+ * 1. Unless specified otherwise, all references to tables or paragraphs
+ *are to UM10326, LPC32x0 and LPC32x0/01 User manual.
+ *
+ * 2. Only bitfield masks/values which are actually used by the driver
+ *are defined.
+ */
+
+/* a single RX descriptor. The controller has an array of these */
+struct lpc32xx_eth_rxdesc {
+ u32 packet; /* Receive packet pointer */
+ u32 control;/* Descriptor command status */
+};
+
+#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
+
+/* RX control bitfields/masks (see Table 330) */
+#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x07FF
+#define LPC32XX_ETH_RX_CTRL_UNUSED0x7800
+#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x8000
+
+/* a single RX status. The controller has an array of these */
+struct lpc32xx_eth_rxstat {
+ u32 statusinfo; /* Transmit Descriptor status */
+ u32 statushashcrc; /* Transmit Descriptor CRCs */
+};
+
+#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
+
+/* RX statusinfo bitfields/masks (see Table 333) */
+#define RX_STAT_RXSIZE 0x07FF
+/* Helper: OR of all errors except RANGE */
+#define RX_STAT_ERRORS 0x1B80
+
+/* a single TX descriptor. The controller has an array
[U-Boot] [PATCH v1 2/8] lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/lpc32xx_nand_mlc.c | 589 ++
5 files changed, 601 insertions(+)
create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 062db8d..be4c93d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -44,3 +44,9 @@ void lpc32xx_mac_init(void)
writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
| CLK_MAC_MII, clk-macclk_ctrl);
}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15..bc7d33d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -147,6 +147,10 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 1)
+#define CLK_NAND_MLC_INT (1 5)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a6b8826..0c4e712 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -9,5 +9,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f02bfc..347ea62 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 000..cb23972
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -0,0 +1,589 @@
+/*
+ * LPC32xx MLC NAND flash controller driver
+ *
+ * (C) Copyright 2014 3ADEV http://3adev.com
+ * Written by Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * NOTE:
+ *
+ * The MLC NAND flash controller provides hardware Reed-Solomon ECC
+ * covering in- and out-of-band data together. Therefore, in- and out-
+ * of-band data must be written together in order to have a valid ECC.
+ *
+ * Consequently, pages with meaningful in-band data are written with
+ * blank (all-ones) out-of-band data and a valid ECC, and any later
+ * out-of-band data write will void the ECC.
+ *
+ * Therefore, code which reads such late-written out-of-band data
+ * should not rely on the ECC validity.
+ */
+
+#include common.h
+#include nand.h
+#include asm/errno.h
+#include asm/io.h
+#include nand.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+
+/*
+ * MLC NAND controller registers.
+ */
+struct lpc32xx_nand_mlc_registers {
+ u8 buff[32768]; /* controller's serial data buffer */
+ u8 data[32768]; /* NAND's raw data buffer */
+ u32 cmd;
+ u32 addr;
+ u32 ecc_enc_reg;
+ u32 ecc_dec_reg;
+ u32 ecc_auto_enc_reg;
+ u32 ecc_auto_dec_reg;
+ u32 rpr;
+ u32 wpr;
+ u32 rubp;
+ u32 robp;
+ u32 sw_wp_add_low;
+ u32 sw_wp_add_hig;
+ u32 icr;
+ u32 time_reg;
+ u32 irq_mr;
+ u32 irq_sr;
+ u32 lock_pr;
+ u32 isr;
+ u32 ceh;
+};
+
+/* LOCK_PR register defines */
+#define LOCK_PR_UNLOCK_KEY 0xA25E /* Magic unlock value */
+
+/* ICR defines */
+#define ICR_LARGE_BLOCKS 0x0004/* configure for 2KB blocks */
+#define ICR_ADDR40x0002/* configure for 4-word addrs */
+
+/* CEH defines */
+#define CEH_NORMAL_CE 0x0001 /* do not force CE ON */
+
+/* ISR register defines */
+#define ISR_NAND_READY0x0001
+#define ISR_CONTROLLER_READY 0x0002
+#define ISR_ECC_READY 0x0004
+#define ISR_DECODER_ERRORS(s) s) 4) 3)+1)
+#define ISR_DECODER_FAILURE
[U-Boot] [PATCH v1 4/8] lpc32xx: add GPIO support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 223 +++
3 files changed, 267 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index aa11f15..559894a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..0c08b00
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,223 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where reading back a GPIO is done on a different
+ * register and bit than writing it.
+ */
+
+static struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+
+/**
+ * We have 4 GPIO ports of 32 bits each
+ */
+
+#define MAX_GPIO 128
+
+#define GPIO_TO_PORT(gpio) ((gpio / 32) 3)
+#define GPIO_TO_RANK(gpio) (gpio % 32)
+#define GPIO_TO_MASK(gpio) (1 (gpio % 32))
+
+/**
+ * GPIO requesting and freeing are not implemented
+ */
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ debug(%s: GPIO %d requested as \%s\\n, __func__, gpio, label);
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ debug(%s: GPIO %d freed\n, __func__, gpio);
+ return 0;
+}
+
+/**
+ * Configure a GPIO as input
+ */
+
+int gpio_direction_input(unsigned gpio)
+{
+ int port, mask;
+
+ port = GPIO_TO_PORT(gpio);
+ mask = GPIO_TO_MASK(gpio);
+
+ switch (port) {
+ case 0:
+ writel(mask, regs-p0_dir_clr);
+ break;
+ case 1:
+ writel(mask, regs-p1_dir_clr);
+ break;
+ case 2:
+ /* ports 2 and 3 share a common direction */
+ case 3:
+ writel(mask, regs-p2_p3_dir_clr);
+ break;
+ default:
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * Configure a GPIO as output
+ */
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ int port, mask;
+
+ port = GPIO_TO_PORT(gpio);
+ mask = GPIO_TO_MASK(gpio);
+
+ switch (port) {
+ case 0:
+ writel(mask, regs-p0_dir_set);
+ break;
+ case 1:
+ writel(mask, regs-p1_dir_set);
+ break;
+ case 2:
+ /* ports 2 and 3 share a common direction */
+ case 3:
+ writel(mask, regs-p2_p3_dir_set
[U-Boot] [PATCH v1 5/8] lpc32xx: add LPC32xx SSP support (SPI mode)
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/lpc32xx_ssp.c | 132 ++
5 files changed, 143 insertions(+)
create mode 100644 drivers/spi/lpc32xx_ssp.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..56ce9ab 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -61,3 +61,9 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, clk-ssp_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 781ac07..2cb5703 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -155,6 +155,9 @@ struct clk_pm_regs {
#define CLK_NAND_MLC (1 1)
#define CLK_NAND_MLC_INT (1 5)
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 0)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a4a05d1..86d5ee9 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..ce6f1cc 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
new file mode 100644
index 000..40270df
--- /dev/null
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -0,0 +1,132 @@
+/*
+ * LPC32xx SSP interface (SPI mode)
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/compat.h
+#include asm/io.h
+#include malloc.h
+#include spi.h
+#include asm/arch/clk.h
+
+/* SSP chip registers */
+struct ssp_regs {
+ u32 cr0;
+ u32 cr1;
+ u32 data;
+ u32 sr;
+ u32 cpsr;
+ u32 imsc;
+ u32 ris;
+ u32 mis;
+ u32 icr;
+ u32 dmacr;
+};
+
+/* CR1 register defines */
+#define SSP_CR1_SSP_ENABLE 0x0002
+
+/* SR register defines */
+#define SSP_SR_TNF 0x0002
+/* SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE 0x0004
+
+static struct ssp_regs *ssp0_regs = (struct ssp_regs *)SSP0_BASE;
+
+static struct spi_slave ssp0_slave = {
+ .bus = 0,
+ .cs = 0,
+ .op_mode_rx = 0,
+ .op_mode_tx = 0,
+ .wordlen = 8,
+ .max_write_size = 1, /* this is for SPI FLASHes -- don't care */
+ .memory_map = NULL, /* for SPI FLASHes too */
+ .option = 0,
+ .flags = 0
+};
+
+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
+void spi_init(void)
+{
+ /*
+* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
+* and configuration will be done in spi_setup_slave()
+ */
+}
+
+/* the following is called in sequence by do_spi_xfer() */
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+ /* we only set up SSP0 for now, so ignore bus */
+
+ if (mode SPI_3WIRE) {
+ error(3-wire mode not supported);
+ return NULL;
+ }
+
+ if (mode SPI_SLAVE) {
+ error(slave mode not supported\n);
+ return NULL;
+ }
+
+ if (mode SPI_PREAMBLE) {
+ error(preamble byte skipping not supported\n);
+ return NULL;
+ }
+
+ /*
+* 8 bit frame, SPI fmt, 500kbps - clock divider is 26.
+* Set SCR to 0 and CPSDVSR to 26.
+*/
+
+ writel(0x7, ssp0_regs-cr0); /* 8-bit chunks, SPI, 1 clk/bit */
+ writel(26, ssp0_regs-cpsr); /* SSP clock = HCLK/26 = 500kbps */
+ writel(0, ssp0_regs-imsc); /* do not raise any interrupts */
+ writel(0
[U-Boot] [PATCH v1 8/8] lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
- EEPROM (24M01-compatible)
- RTC (DS1374-compatible)
- Temperature sensor (DS620)
- DACs (2 x MAX518)
- SPI (through SSP interface)
- Port expander MAX6957
- LCD display (HD44780-compatible), controlled
through the port expander and DACs
This board has SPL support, and uses the LPC32XX boot
image format.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
arch/arm/Kconfig | 6 +
arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 +
arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 4 +
arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 80 +
arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 +++
arch/arm/include/asm/arch-lpc32xx/clk.h| 5 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 4 +-
board/work-microwave/work_92105/Kconfig| 15 +
board/work-microwave/work_92105/MAINTAINERS| 6 +
board/work-microwave/work_92105/Makefile | 8 +
board/work-microwave/work_92105/README | 23 ++
board/work-microwave/work_92105/work_92105.c | 85 +
.../work-microwave/work_92105/work_92105_display.c | 345 +
.../work-microwave/work_92105/work_92105_display.h | 14 +
configs/work_92105_defconfig | 3 +
drivers/hwmon/ds620.c | 1 +
include/configs/work_92105.h | 257 +++
18 files changed, 936 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c
create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
create mode 100644 board/work-microwave/work_92105/Kconfig
create mode 100644 board/work-microwave/work_92105/MAINTAINERS
create mode 100644 board/work-microwave/work_92105/Makefile
create mode 100644 board/work-microwave/work_92105/README
create mode 100644 board/work-microwave/work_92105/work_92105.c
create mode 100644 board/work-microwave/work_92105/work_92105_display.c
create mode 100644 board/work-microwave/work_92105/work_92105_display.h
create mode 100644 configs/work_92105_defconfig
create mode 100644 include/configs/work_92105.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5eb1d03..0907136 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -238,6 +238,11 @@ config TARGET_DEVKIT3250
bool Support devkit3250
select CPU_ARM926EJS
+config TARGET_WORK_92105
+ bool Support work_92105
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
config TARGET_JADECPU
bool Support jadecpu
select CPU_ARM926EJS
@@ -981,6 +986,7 @@ source board/udoo/Kconfig
source board/vpac270/Kconfig
source board/wandboard/Kconfig
source board/woodburn/Kconfig
+source board/work-microwave/work_92105/Kconfig
source board/xaeniax/Kconfig
source board/zipitz2/Kconfig
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
index 314f004..4837377 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
@@ -6,3 +6,5 @@
#
obj-y = cpu.o clk.o devices.o timer.o
+
+obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index b7a44d5..1ef8a36 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -98,6 +98,40 @@ unsigned int get_periph_clk_rate(void)
return get_hclk_pll_rate() / get_periph_clk_div();
}
+unsigned int get_sdram_clk_rate(void)
+{
+ unsigned int src_clk;
+
+ if (!(readl(clk-pwr_ctrl) CLK_PWR_NORMAL_RUN))
+ return get_sys_clk_rate();
+
+ src_clk = get_hclk_pll_rate();
+
+ if (readl(clk-sdramclk_ctrl) CLK_SDRAM_DDR_SEL) {
+ /* using DDR */
+ switch (readl(clk-hclkdiv_ctrl) CLK_HCLK_DDRAM_MASK) {
+ case CLK_HCLK_DDRAM_HALF:
+ return src_clk/2;
+ case CLK_HCLK_DDRAM_NOMINAL:
+ return src_clk;
+ default:
+ return 0;
+ }
+ } else {
+ /* using SDR */
+ switch (readl(clk-hclkdiv_ctrl) CLK_HCLK_ARM_PLL_DIV_MASK) {
+ case CLK_HCLK_ARM_PLL_DIV_4:
+ return src_clk/4;
+ case CLK_HCLK_ARM_PLL_DIV_2:
+ return src_clk/2;
+ case CLK_HCLK_ARM_PLL_DIV_1:
+ return src_clk;
+ default:
+ return 0;
+ }
+ }
+}
+
int get_serial_clock(void)
{
return get_periph_clk_rate();
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx
[U-Boot] [PATCH v1 6/8] dtt: add ds620 support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
drivers/hwmon/Makefile | 1 +
drivers/hwmon/ds620.c | 64 ++
include/dtt.h | 15 ++--
3 files changed, 73 insertions(+), 7 deletions(-)
create mode 100644 drivers/hwmon/ds620.c
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 25b8e8a..b4fb057 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_DTT_ADT7460) += adt7460.o
obj-$(CONFIG_DTT_DS1621) += ds1621.o
obj-$(CONFIG_DTT_DS1722) += ds1722.o
obj-$(CONFIG_DTT_DS1775) += ds1775.o
+obj-$(CONFIG_DTT_DS620) += ds620.o
obj-$(CONFIG_DTT_LM63) += lm63.o
obj-$(CONFIG_DTT_LM73) += lm73.o
obj-$(CONFIG_DTT_LM75) += lm75.o
diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c
new file mode 100644
index 000..b9a60fc
--- /dev/null
+++ b/drivers/hwmon/ds620.c
@@ -0,0 +1,64 @@
+/*
+ * DS620 DTT support
+ * (C) Copyright 2014 3ADEV http://www.3adev.com
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
+ */
+
+#include common.h
+#include i2c.h
+#include dtt.h
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48
+#define DTT_START_CONVERT 0x51
+#define DTT_TEMP 0xAA
+#define DTT_CONFIG 0xAC
+
+/*
+ * Config register MSB bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_AUTOC 0x02
+#define DTT_CONFIG_R0 0x04 /* always 1 */
+#define DTT_CONFIG_R1 0x08 /* always 1 */
+#define DTT_CONFIG_TLF 0x10
+#define DTT_CONFIG_THF 0x20
+#define DTT_CONFIG_NVB 0x40
+#define DTT_CONFIG_DONE0x80
+
+#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor 0x07))
+
+int dtt_init_one(int sensor)
+{
+ uint8_t config = DTT_CONFIG_1SHOT
+ | DTT_CONFIG_R0
+ | DTT_CONFIG_R1;
+ return i2c_write(CHIP(sensor), DTT_CONFIG, 1, config, 1);
+}
+
+int dtt_get_temp(int sensor)
+{
+ uint8_t status;
+ uint8_t temp[2];
+
+ /* Start a conversion, may take up to 1 second. */
+ i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0);
+ do {
+ if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, status, 1))
+ /* bail out if I2C error */
+ status |= DTT_CONFIG_DONE;
+ } while (!(status DTT_CONFIG_DONE));
+ if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2))
+ /* bail out if I2C error */
+ return -274; /* below absolute zero == error */
+
+ return ((int16_t)(temp[1] | (temp[0] 8))) 7;
+}
diff --git a/include/dtt.h b/include/dtt.h
index 058bca4..173159d 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -12,13 +12,14 @@
#define _DTT_H_
#if defined(CONFIG_DTT_ADM1021)|| \
-defined(CONFIG_DTT_ADT7460)|| \
-defined(CONFIG_DTT_DS1621) || \
-defined(CONFIG_DTT_DS1775) || \
-defined(CONFIG_DTT_LM63) || \
-defined(CONFIG_DTT_LM73) || \
-defined(CONFIG_DTT_LM75) || \
-defined(CONFIG_DTT_LM81)
+ defined(CONFIG_DTT_ADT7460) || \
+ defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
+ defined(CONFIG_DTT_DS620) || \
+ defined(CONFIG_DTT_LM63)|| \
+ defined(CONFIG_DTT_LM73)|| \
+ defined(CONFIG_DTT_LM75)|| \
+ defined(CONFIG_DTT_LM81)
#define CONFIG_DTT /* We have a DTT */
--
2.1.0
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 7/8] lpc32xx: add lpc32xx-spl.bin boot image target
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Makefile | 3 +
scripts/Makefile.spl | 11
tools/.gitignore | 1 +
tools/Makefile| 2 +
tools/mklpc32xxboot.c | 169 ++
5 files changed, 186 insertions(+)
create mode 100644 tools/mklpc32xxboot.c
diff --git a/Makefile b/Makefile
index 36a9a28..f5c9da5 100644
--- a/Makefile
+++ b/Makefile
@@ -1198,6 +1198,9 @@ spl/u-boot-spl: tools prepare
spl/sunxi-spl.bin: spl/u-boot-spl
@:
+spl/lpc32xx-spl.bin: spl/u-boot-spl
+ @:
+
tpl/u-boot-tpl.bin: tools prepare
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ecf3037..4020383 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -158,6 +158,10 @@ ALL-y += $(obj)/sunxi-spl.bin
endif
endif
+ifdef CONFIG_LPC32XX_SPL
+ALL-y += $(obj)/lpc32xx-spl.bin
+endif
+
ifeq ($(CONFIG_SYS_SOC),at91)
ALL-y += boot.bin
endif
@@ -196,6 +200,13 @@ $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin
$(call if_changed,mksunxiboot)
endif
+ifdef CONFIG_LPC32XX_SPL
+quiet_cmd_mklpc32xxboot = MKLPC32XX $@
+cmd_mklpc32xxboot = $(objtree)/tools/mklpc32xxboot $ $@
+$(obj)/lpc32xx-spl.bin: $(obj)/$(SPL_BIN).bin
+ $(call if_changed,mklpc32xxboot)
+endif
+
quiet_cmd_u-boot-spl = LD $@
cmd_u-boot-spl = (cd $(obj) $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
$(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
diff --git a/tools/.gitignore b/tools/.gitignore
index 9bc9fec..79a5d75 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -11,6 +11,7 @@
/mkenvimage
/mkimage
/mkexynosspl
+/mklpc32xxboot
/mpc86x_clk
/mxsboot
/mksunxiboot
diff --git a/tools/Makefile b/tools/Makefile
index e549f8e..6fe21b0 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -135,6 +135,8 @@ HOSTCFLAGS_mxsboot.o := -pedantic
hostprogs-$(CONFIG_SUNXI) += mksunxiboot
+hostprogs-$(CONFIG_LPC32XX_SPL) += mklpc32xxboot
+
hostprogs-$(CONFIG_NETCONSOLE) += ncb
hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1
diff --git a/tools/mklpc32xxboot.c b/tools/mklpc32xxboot.c
new file mode 100644
index 000..9f7d72e
--- /dev/null
+++ b/tools/mklpc32xxboot.c
@@ -0,0 +1,169 @@
+/*
+ * LPC32XX NAND boot image generator
+ *
+ * For details on NAND boot, see LPC32XX UM chapter 35 (boot process)
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include fcntl.h
+#include stdio.h
+#include unistd.h
+#include stdlib.h
+#include string.h
+#include errno.h
+#include sys/types.h
+#include sys/stat.h
+
+/*
+ * NAND page 0 boot header
+ */
+
+struct nand_page_0_boot_header {
+ uint32_t data[129];
+ uint32_t pad[383];
+};
+
+/*
+ * Default ICC (interface configuration data [sic]) if none specified
+ * in board config
+ */
+
+#ifndef LPC32XX_BOOT_ICR
+#define LPC32XX_BOOT_ICR 0x0096
+#endif
+
+/*
+ * Default boot NAND page size if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGESIZE
+#define LPC32XX_BOOT_NAND_PAGESIZE 2048
+#endif
+
+/*
+ * Default boot NAND pages per sector if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR
+#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64
+#endif
+
+/*
+ * Maximum size for boot code is 56K unless defined in board config
+ */
+
+#ifndef LPC32XX_BOOT_CODESIZE
+#define LPC32XX_BOOT_CODESIZE (56*1024)
+#endif
+
+/* signature byte for a readable block */
+
+#define LPC32XX_BOOT_BLOCK_OK 0xaa
+
+/*
+ * Output boot data for both sectors 0 and 1
+ */
+
+int main(int argc, char *argv[])
+{
+ int fd_in, fd_out;
+ struct nand_page_0_boot_header header;
+ uint8_t page[LPC32XX_BOOT_NAND_PAGESIZE];
+ unsigned file_size_b;
+ unsigned file_size_p;
+ int sectors_left, pages_left, bytes_left, bytes_read;
+
+ if (argc 2) {
+ printf(\tThis program takes an u-boot-spl.bin file
+ as input and produces an LPC32XX boot image.\n
+ \tUsage: %s input_file output_file\n, argv[0]);
+ return EXIT_FAILURE;
+ }
+
+ fd_in = open(argv[1], O_RDONLY);
+ if (fd_in 0) {
+ perror(argv[1]);
+ return 1;
+ }
+
+ /* get input file size in bytes */
+ file_size_b = lseek(fd_in, 0, SEEK_END);
+
+ /* check maximum size */
+ if (file_size_b LPC32XX_BOOT_CODESIZE) {
+ fprintf(stderr, ERROR: File too large!\n);
+ return 2;
+ }
+
+ /* turn filesize from bytes to NAND pages, page 0 included */
+ file_size_p = ((file_size_b + (2 * LPC32XX_BOOT_NAND_PAGESIZE) - 1)
+ / LPC32XX_BOOT_NAND_PAGESIZE);
+
+ /* fill header -- default byte value is 0x00, not 0xFF */
+ memset(header, 0, sizeof(header
