Re: [PATCH v6 1/6] usb: tcpm: add core framework

[Anand Moon]

Hi Sebastian,

On Thu, 5 Sept 2024 at 21:06, Sebastian Reichel
 wrote:
>
> This adds TCPM framework in preparation for fusb302 support, which can
> handle USB power delivery messages. This is needed to solve issues with
> devices, that are running from a USB-C port supporting USB-PD, but not
> having a battery.
>
> Such a device currently boots to the kernel without interacting with
> the power-supply at all. If there are no USB-PD message replies within
> 5 seconds, the power-supply assumes the peripheral is not capable of
> USB-PD. It usually takes more than 5 seconds for the system to reach
> the kernel and probe the I2C based fusb302 chip driver. Thus the
> system always runs into this state. The power-supply's solution to
> fix this error state is a hard reset, which involves removing the
> power from VBUS. Boards without a battery (or huge capacitors) will
> reset at this point resulting in a boot loop.
>
> This imports the TCPM framework from the kernel. The porting has
> originally been done by Rockchip using hardware timers and the Linux
> kernel's TCPM code from some years ago.
>
> I had a look at upgrading to the latest TCPM kernel code, but that
> beast became a lot more complex due to adding more USB-C features.
> I believe these features are not needed in U-Boot and with multiple
> kthreads and hrtimers being involved it is non-trivial to port them.
> Instead I worked on stripping down features from the Rockchip port
> to an even more basic level. Also the TCPM code has been reworked
> to avoid complete use of any timers (Rockchip used SoC specific
> hardware timers + IRQ to implement delayed work mechanism). Instead
> the delayed state changes are handled directly from the poll loop.
>
> Note, that (in contrast to the original Rockchip port) the state
> machine has the same hard reset quirk, that the kernel has - i.e.
> it avoids disabling the CC pin resistors for devices that are not
> self-powered. Without that quirk, the Radxa Rock 5B will not just
> end up doing a machine reset when a hard reset is triggered, but will
> not even recover, because the CPU will loose power and the FUSB302
> will keep this state because of leak voltage arriving through the RX
> serial pin (assuming a serial adapter is connected).
>
> This also includes a 'tcpm' command, which can be used to get
> information about the current state and the negotiated voltage
> and current.
>
> Co-developed-by: Wang Jie 
> Signed-off-by: Wang Jie 
> Tested-by: Soeren Moch 
> Signed-off-by: Sebastian Reichel 

For the whole series.

Tested-by: Anand Moon 

> ---
>  Makefile |1 +
>  cmd/Kconfig  |7 +
>  cmd/Makefile |1 +
>  cmd/tcpm.c   |  136 ++
>  doc/usage/cmd/tcpm.rst   |   66 +
>  doc/usage/index.rst  |1 +
>  drivers/usb/Kconfig  |2 +
>  drivers/usb/tcpm/Kconfig |8 +
>  drivers/usb/tcpm/Makefile|3 +
>  drivers/usb/tcpm/tcpm-internal.h |  173 +++
>  drivers/usb/tcpm/tcpm-uclass.c   |  149 ++
>  drivers/usb/tcpm/tcpm.c  | 2288 ++
>  include/dm/uclass-id.h   |1 +
>  include/usb/pd.h |  516 +++
>  include/usb/tcpm.h   |   99 ++
>  15 files changed, 3451 insertions(+)
>  create mode 100644 cmd/tcpm.c
>  create mode 100644 doc/usage/cmd/tcpm.rst
>  create mode 100644 drivers/usb/tcpm/Kconfig
>  create mode 100644 drivers/usb/tcpm/Makefile
>  create mode 100644 drivers/usb/tcpm/tcpm-internal.h
>  create mode 100644 drivers/usb/tcpm/tcpm-uclass.c
>  create mode 100644 drivers/usb/tcpm/tcpm.c
>  create mode 100644 include/usb/pd.h
>  create mode 100644 include/usb/tcpm.h
>
> diff --git a/Makefile b/Makefile
> index 74df5d177c1f..5a581199c170 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -879,6 +879,7 @@ libs-y += drivers/usb/musb/
>  libs-y += drivers/usb/musb-new/
>  libs-y += drivers/usb/isp1760/
>  libs-y += drivers/usb/phy/
> +libs-y += drivers/usb/tcpm/
>  libs-y += drivers/usb/ulpi/
>  ifdef CONFIG_POST
>  libs-y += post/
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 978f44eda426..7710bee22ace 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -221,6 +221,13 @@ config CMD_REGINFO
> help
>   Register dump
>
> +config CMD_TCPM
> +   bool "tcpm"
> +   depends on TYPEC_TCPM
> +   help
> + Show voltage and current negotiated via USB PD as well as the
> + current state of the Type C Port Manager (TCPM) state machine.
> +
>  config CMD_TLV_EEPROM
> bool "tlv_eeprom"
> depends on I2C_EEPR

Re: [PATCH v1 00/12] Bind Syscon driver with OF_REAL

[Anand Moon]

Hi Kever,

On Sat, 14 Sept 2024 at 15:30, Kever Yang  wrote:
>
> Hi Anand,
>
> On 2024/8/6 12:38, Anand Moon wrote:
>
> Bind syscon driver with dm_scan_fdt_dev
> As OF_PLATDATA is no longer enabled, the related
> code is removed.
>
> The OF_PLATDATA is no removed, basically it's use in TPL/SPL for code size,
>
> and the SPL_OF_PLATDATA and TPL_PLATDAT still available,
>
> The OF_REAL is only to replace "OF_CONTROL && !OF_PLATDATA."
>

Thanks, for this update.
.
> Thanks,
> - Kever
>

Thanks

-Anand

> Compiled and tested on RK3399 and RV1126 board.
>
> Thanks
> -Anand
>
> Anand Moon (12):
>   arm: rockchip: rk3399: Remove unused syscon drivers code
>   arch: rockchip: rv1126: Update syscon driver binding method
>   arm: rockchip: rv1126: Remove unused syscon drivers code
>   arm: rockchip: px30: Remove unused syscon drivers code
>   arch: rockchip: rk3066: Update syscon driver binding method
>   arm: rockchip: rk3066: Remove unused syscon drivers code
>   arch: rockchip: rk3368: Update syscon driver binding method
>   arm: rockchip: rk3368: Remove unused syscon drivers code
>   arch: rockchip: rk3188: Update syscon driver binding method
>   arm: rockchip: rk3188: Remove unused syscon drivers code
>   arch: rockchip: rk3288: Update syscon driver binding method
>   arm: rockchip: rk3288: Remove unused syscon drivers code
>
>  arch/arm/mach-rockchip/px30/syscon_px30.c |  31 
>  arch/arm/mach-rockchip/rk3066/syscon_rk3066.c |  34 +---
>  arch/arm/mach-rockchip/rk3188/syscon_rk3188.c |  34 +---
>  arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 157 +-
>  arch/arm/mach-rockchip/rk3368/syscon_rk3368.c |  41 +
>  arch/arm/mach-rockchip/rk3399/syscon_rk3399.c |  45 -
>  arch/arm/mach-rockchip/rv1126/syscon_rv1126.c |  27 +--
>  7 files changed, 14 insertions(+), 355 deletions(-)
>
>
> base-commit: 6becf9ba1ab82af6f4fcf9f4d0da38f9c75212d2

[PATCH v1 12/12] arm: rockchip: rk3288: Remove unused syscon drivers code

[Anand Moon]

Since commit 95397385091d ("treewide: Use OF_REAL instead of !OF_PLATDATA"),
the OF_PLATDATA code. As OF_PLATDATA is no longer enabled, the related
code is removed.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 156 --
 1 file changed, 156 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
index 4030e919134..e2e1eb624ec 100644
--- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
@@ -28,159 +28,3 @@ U_BOOT_DRIVER(syscon_rk3288) = {
 #endif
.of_match = rk3288_syscon_ids,
 };
-
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-#if IS_ENABLED(CONFIG_FDT_64BIT)
-struct rockchip_rk3288_noc_plat {
-   struct dtd_rockchip_rk3288_noc dtplat;
-};
-
-struct rockchip_rk3288_grf_plat {
-   struct dtd_rockchip_rk3288_grf dtplat;
-};
-
-struct rockchip_rk3288_sgrf_plat {
-   struct dtd_rockchip_rk3288_sgrf dtplat;
-};
-
-struct rockchip_rk3288_pmu_plat {
-   struct dtd_rockchip_rk3288_pmu dtplat;
-};
-
-static int rk3288_noc_bind_of_plat(struct udevice *dev)
-{
-   struct rockchip_rk3288_noc_plat *plat = dev_get_plat(dev);
-   struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
-   int size = dev->uclass->uc_drv->per_device_auto;
-
-   if (size && !priv) {
-   priv = calloc(1, size);
-   if (!priv)
-   return -ENOMEM;
-   dev_set_uclass_priv(dev, priv);
-   }
-
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return regmap_init_mem_plat(dev, plat->dtplat.reg, 
sizeof(plat->dtplat.reg[0]),
-   ARRAY_SIZE(plat->dtplat.reg) / 2, 
&priv->regmap);
-}
-
-static int rk3288_grf_bind_of_plat(struct udevice *dev)
-{
-   struct rockchip_rk3288_grf_plat *plat = dev_get_plat(dev);
-   struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
-   int size = dev->uclass->uc_drv->per_device_auto;
-
-   if (size && !priv) {
-   priv = calloc(1, size);
-   if (!priv)
-   return -ENOMEM;
-   dev_set_uclass_priv(dev, priv);
-   }
-
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return regmap_init_mem_plat(dev, plat->dtplat.reg, 
sizeof(plat->dtplat.reg[0]),
-   ARRAY_SIZE(plat->dtplat.reg) / 2, 
&priv->regmap);
-}
-
-static int rk3288_sgrf_bind_of_plat(struct udevice *dev)
-{
-   struct rockchip_rk3288_sgrf_plat *plat = dev_get_plat(dev);
-   struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
-   int size = dev->uclass->uc_drv->per_device_auto;
-
-   if (size && !priv) {
-   priv = calloc(1, size);
-   if (!priv)
-   return -ENOMEM;
-   dev_set_uclass_priv(dev, priv);
-   }
-
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return regmap_init_mem_plat(dev, plat->dtplat.reg, 
sizeof(plat->dtplat.reg[0]),
-   ARRAY_SIZE(plat->dtplat.reg) / 2, 
&priv->regmap);
-}
-
-static int rk3288_pmu_bind_of_plat(struct udevice *dev)
-{
-   struct rockchip_rk3288_pmu_plat *plat = dev_get_plat(dev);
-   struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
-   int size = dev->uclass->uc_drv->per_device_auto;
-
-   if (size && !priv) {
-   priv = calloc(1, size);
-   if (!priv)
-   return -ENOMEM;
-   dev_set_uclass_priv(dev, priv);
-   }
-
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return regmap_init_mem_plat(dev, plat->dtplat.reg, 
sizeof(plat->dtplat.reg[0]),
-   ARRAY_SIZE(plat->dtplat.reg) / 2, 
&priv->regmap);
-}
-#else
-static int rk3288_syscon_bind_of_plat(struct udevice *dev)
-{
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return 0;
-}
-#endif
-
-U_BOOT_DRIVER(rockchip_rk3288_noc) = {
-   .name = "rockchip_rk3288_noc",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3288_syscon_ids,
-#if IS_ENABLED(CONFIG_FDT_64BIT)
-   .bind = rk3288_noc_bind_of_plat,
-   .plat_auto = sizeof(struct rockchip_rk3288_noc_plat),
-#else
-   .bind = rk3288_syscon_bind_of_plat,
-#endif
-};
-
-U_BOOT_DRIVER(r

[PATCH v1 11/12] arch: rockchip: rk3288: Update syscon driver binding method

[Anand Moon]

Updated the binding method to use `dm_scan_fdt_dev` when
`OF_REAL` is enabled.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
index 6413d0a88a1..4030e919134 100644
--- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
@@ -23,6 +23,9 @@ static const struct udevice_id rk3288_syscon_ids[] = {
 U_BOOT_DRIVER(syscon_rk3288) = {
.name = "rk3288_syscon",
.id = UCLASS_SYSCON,
+#if CONFIG_IS_ENABLED(OF_REAL)
+   .bind = dm_scan_fdt_dev,
+#endif
.of_match = rk3288_syscon_ids,
 };
 
-- 
2.46.0

[PATCH v1 10/12] arm: rockchip: rk3188: Remove unused syscon drivers code

[Anand Moon]

Since commit 95397385091d ("treewide: Use OF_REAL instead of !OF_PLATDATA"),
the OF_PLATDATA code. As OF_PLATDATA is no longer enabled, the related
code is removed.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rk3188/syscon_rk3188.c | 31 ---
 1 file changed, 31 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c 
b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
index bcd7870c503..94dbd6f8644 100644
--- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
@@ -24,34 +24,3 @@ U_BOOT_DRIVER(syscon_rk3188) = {
 #endif
.of_match = rk3188_syscon_ids,
 };
-
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3188_syscon_bind_of_plat(struct udevice *dev)
-{
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return 0;
-}
-
-U_BOOT_DRIVER(rockchip_rk3188_noc) = {
-   .name = "rockchip_rk3188_noc",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3188_syscon_ids,
-   .bind = rk3188_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3188_grf) = {
-   .name = "rockchip_rk3188_grf",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3188_syscon_ids + 1,
-   .bind = rk3188_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
-   .name = "rockchip_rk3188_pmu",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3188_syscon_ids + 2,
-   .bind = rk3188_syscon_bind_of_plat,
-};
-#endif
-- 
2.46.0

[PATCH v1 09/12] arch: rockchip: rk3188: Update syscon driver binding method

[Anand Moon]

Updated the binding method to use `dm_scan_fdt_dev` when
OF_REAL` is enabled.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rk3188/syscon_rk3188.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c 
b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
index 6df054e5b27..bcd7870c503 100644
--- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
@@ -19,6 +19,9 @@ static const struct udevice_id rk3188_syscon_ids[] = {
 U_BOOT_DRIVER(syscon_rk3188) = {
.name = "rk3188_syscon",
.id = UCLASS_SYSCON,
+#if CONFIG_IS_ENABLED(OF_REAL)
+   .bind = dm_scan_fdt_dev,
+#endif
.of_match = rk3188_syscon_ids,
 };
 
-- 
2.46.0

[PATCH v1 08/12] arm: rockchip: rk3368: Remove unused syscon drivers code

[Anand Moon]

Since commit 95397385091d ("treewide: Use OF_REAL instead of !OF_PLATDATA"),
the OF_PLATDATA code. As OF_PLATDATA is no longer enabled, the related
code is removed.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 38 ---
 1 file changed, 38 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c 
b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
index 89caa6c310c..0381a22453f 100644
--- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
@@ -30,41 +30,3 @@ U_BOOT_DRIVER(syscon_rk3368) = {
 #endif
.of_match = rk3368_syscon_ids,
 };
-
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3368_syscon_bind_of_plat(struct udevice *dev)
-{
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return 0;
-}
-
-U_BOOT_DRIVER(rockchip_rk3368_grf) = {
-   .name = "rockchip_rk3368_grf",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3368_syscon_ids,
-   .bind = rk3368_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
-   .name = "rockchip_rk3368_pmugrf",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3368_syscon_ids + 1,
-   .bind = rk3368_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3368_msch) = {
-   .name = "rockchip_rk3368_msch",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3368_syscon_ids + 2,
-   .bind = rk3368_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
-   .name = "rockchip_rk3368_sgrf",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3368_syscon_ids + 3,
-   .bind = rk3368_syscon_bind_of_plat,
-};
-#endif
-- 
2.46.0

[PATCH v1 07/12] arch: rockchip: rk3368: Update syscon driver binding method

[Anand Moon]

Updated the binding method to use `dm_scan_fdt_dev` when
OF_REAL` is enabled.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c 
b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
index 7389c028364..89caa6c310c 100644
--- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
@@ -25,6 +25,9 @@ static const struct udevice_id rk3368_syscon_ids[] = {
 U_BOOT_DRIVER(syscon_rk3368) = {
.name = "rk3368_syscon",
.id = UCLASS_SYSCON,
+#if CONFIG_IS_ENABLED(OF_REAL)
+   .bind = dm_scan_fdt_dev,
+#endif
.of_match = rk3368_syscon_ids,
 };
 
-- 
2.46.0

[PATCH v1 06/12] arm: rockchip: rk3066: Remove unused syscon drivers code

[Anand Moon]

Since commit 95397385091d ("treewide: Use OF_REAL instead of !OF_PLATDATA"),
the OF_PLATDATA code. As OF_PLATDATA is no longer enabled, the related
code is removed.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 31 ---
 1 file changed, 31 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c 
b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
index 4e13aeca03e..18f006610d0 100644
--- a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
+++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
@@ -24,34 +24,3 @@ U_BOOT_DRIVER(syscon_rk3066) = {
 #endif
.of_match = rk3066_syscon_ids,
 };
-
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3066_syscon_bind_of_plat(struct udevice *dev)
-{
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return 0;
-}
-
-U_BOOT_DRIVER(rockchip_rk3066_noc) = {
-   .name = "rockchip_rk3066_noc",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3066_syscon_ids,
-   .bind = rk3066_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3066_grf) = {
-   .name = "rockchip_rk3066_grf",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3066_syscon_ids + 1,
-   .bind = rk3066_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
-   .name = "rockchip_rk3066_pmu",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3066_syscon_ids + 2,
-   .bind = rk3066_syscon_bind_of_plat,
-};
-#endif
-- 
2.46.0

[PATCH v1 05/12] arch: rockchip: rk3066: Update syscon driver binding method

[Anand Moon]

Updated the binding method to use `dm_scan_fdt_dev` when
OF_REAL` is enabled.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c 
b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
index ff269b53b54..4e13aeca03e 100644
--- a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
+++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
@@ -19,6 +19,9 @@ static const struct udevice_id rk3066_syscon_ids[] = {
 U_BOOT_DRIVER(syscon_rk3066) = {
.name = "rk3066_syscon",
.id = UCLASS_SYSCON,
+#if CONFIG_IS_ENABLED(OF_REAL)
+   .bind = dm_scan_fdt_dev,
+#endif
.of_match = rk3066_syscon_ids,
 };
 
-- 
2.46.0

[PATCH v1 04/12] arm: rockchip: px30: Remove unused syscon drivers code

[Anand Moon]

Since commit 95397385091d ("treewide: Use OF_REAL instead of !OF_PLATDATA"),
the OF_PLATDATA code. As OF_PLATDATA is no longer enabled, the related
code is removed.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/px30/syscon_px30.c | 31 ---
 1 file changed, 31 deletions(-)

diff --git a/arch/arm/mach-rockchip/px30/syscon_px30.c 
b/arch/arm/mach-rockchip/px30/syscon_px30.c
index 893a5234baa..cc5adc71569 100644
--- a/arch/arm/mach-rockchip/px30/syscon_px30.c
+++ b/arch/arm/mach-rockchip/px30/syscon_px30.c
@@ -23,34 +23,3 @@ U_BOOT_DRIVER(syscon_px30) = {
 #endif
.of_match = px30_syscon_ids,
 };
-
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int px30_syscon_bind_of_plat(struct udevice *dev)
-{
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return 0;
-}
-
-U_BOOT_DRIVER(rockchip_px30_pmu) = {
-   .name = "rockchip_px30_pmu",
-   .id = UCLASS_SYSCON,
-   .of_match = px30_syscon_ids,
-   .bind = px30_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_px30_pmugrf) = {
-   .name = "rockchip_px30_pmugrf",
-   .id = UCLASS_SYSCON,
-   .of_match = px30_syscon_ids + 1,
-   .bind = px30_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_px30_grf) = {
-   .name = "rockchip_px30_grf",
-   .id = UCLASS_SYSCON,
-   .of_match = px30_syscon_ids + 2,
-   .bind = px30_syscon_bind_of_plat,
-};
-#endif
-- 
2.46.0

[PATCH v1 03/12] arm: rockchip: rv1126: Remove unused syscon drivers code

[Anand Moon]

Since commit 95397385091d ("treewide: Use OF_REAL instead of !OF_PLATDATA"),
the OF_PLATDATA code, As OF_PLATDATA is no longer enabled, the related
code is removed.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rv1126/syscon_rv1126.c | 24 ---
 1 file changed, 24 deletions(-)

diff --git a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c 
b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c
index d66d84c836d..4c0690f1ba2 100644
--- a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c
+++ b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c
@@ -23,27 +23,3 @@ U_BOOT_DRIVER(syscon_rv1126) = {
 #endif
.of_match = rv1126_syscon_ids,
 };
-
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rv1126_syscon_bind_of_plat(struct udevice *dev)
-{
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return 0;
-}
-
-U_BOOT_DRIVER(rockchip_rv1126_pmu) = {
-   .name = "rockchip_rv1126_pmu",
-   .id = UCLASS_SYSCON,
-   .of_match = rv1126_syscon_ids,
-   .bind = rv1126_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rv1126_pmugrf) = {
-   .name = "rockchip_rv1126_pmugrf",
-   .id = UCLASS_SYSCON,
-   .of_match = rv1126_syscon_ids + 1,
-   .bind = rv1126_syscon_bind_of_plat,
-};
-#endif
-- 
2.46.0

[PATCH v1 02/12] arch: rockchip: rv1126: Update syscon driver binding method

[Anand Moon]

Updated the binding method to use `dm_scan_fdt_dev` when
`OF_REAL` is enabled.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rv1126/syscon_rv1126.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c 
b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c
index 67d2f18a8d0..d66d84c836d 100644
--- a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c
+++ b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c
@@ -18,6 +18,9 @@ static const struct udevice_id rv1126_syscon_ids[] = {
 U_BOOT_DRIVER(syscon_rv1126) = {
.name = "rv1126_syscon",
.id = UCLASS_SYSCON,
+#if CONFIG_IS_ENABLED(OF_REAL)
+   .bind = dm_scan_fdt_dev,
+#endif
.of_match = rv1126_syscon_ids,
 };
 
-- 
2.46.0

[PATCH v1 01/12] arm: rockchip: rk3399: Remove unused syscon drivers code

[Anand Moon]

Since commit 95397385091d ("treewide: Use OF_REAL instead of !OF_PLATDATA"),
the OF_PLATDATA code, As OF_PLATDATA is no longer enabled, the related
code is removed.

Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 45 ---
 1 file changed, 45 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c 
b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
index b92ad54ede5..5895fa373ec 100644
--- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
@@ -25,48 +25,3 @@ U_BOOT_DRIVER(syscon_rk3399) = {
 #endif
.of_match = rk3399_syscon_ids,
 };
-
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3399_syscon_bind_of_plat(struct udevice *dev)
-{
-   dev->driver_data = dev->driver->of_match->data;
-   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
-
-   return 0;
-}
-
-U_BOOT_DRIVER(rockchip_rk3399_grf) = {
-   .name = "rockchip_rk3399_grf",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3399_syscon_ids,
-   .bind = rk3399_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = {
-   .name = "rockchip_rk3399_pmugrf",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3399_syscon_ids + 1,
-   .bind = rk3399_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = {
-   .name = "rockchip_rk3399_pmusgrf",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3399_syscon_ids + 2,
-   .bind = rk3399_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3399_cic) = {
-   .name = "rockchip_rk3399_cic",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3399_syscon_ids + 3,
-   .bind = rk3399_syscon_bind_of_plat,
-};
-
-U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
-   .name = "rockchip_rk3399_pmu",
-   .id = UCLASS_SYSCON,
-   .of_match = rk3399_syscon_ids + 4,
-   .bind = rk3399_syscon_bind_of_plat,
-};
-#endif
-- 
2.46.0

[PATCH v1 00/12] Bind Syscon driver with OF_REAL

[Anand Moon]

Bind syscon driver with dm_scan_fdt_dev
As OF_PLATDATA is no longer enabled, the related
code is removed.

Compiled and tested on RK3399 and RV1126 board.

Thanks
-Anand

Anand Moon (12):
  arm: rockchip: rk3399: Remove unused syscon drivers code
  arch: rockchip: rv1126: Update syscon driver binding method
  arm: rockchip: rv1126: Remove unused syscon drivers code
  arm: rockchip: px30: Remove unused syscon drivers code
  arch: rockchip: rk3066: Update syscon driver binding method
  arm: rockchip: rk3066: Remove unused syscon drivers code
  arch: rockchip: rk3368: Update syscon driver binding method
  arm: rockchip: rk3368: Remove unused syscon drivers code
  arch: rockchip: rk3188: Update syscon driver binding method
  arm: rockchip: rk3188: Remove unused syscon drivers code
  arch: rockchip: rk3288: Update syscon driver binding method
  arm: rockchip: rk3288: Remove unused syscon drivers code

 arch/arm/mach-rockchip/px30/syscon_px30.c |  31 
 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c |  34 +---
 arch/arm/mach-rockchip/rk3188/syscon_rk3188.c |  34 +---
 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 157 +-
 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c |  41 +
 arch/arm/mach-rockchip/rk3399/syscon_rk3399.c |  45 -
 arch/arm/mach-rockchip/rv1126/syscon_rv1126.c |  27 +--
 7 files changed, 14 insertions(+), 355 deletions(-)


base-commit: 6becf9ba1ab82af6f4fcf9f4d0da38f9c75212d2
-- 
2.46.0

Re: [PATCH RFC v2 01/23] rockchip: RK3328: Read the reset cause from clock reset unit for RK3328 SoC

[Anand Moon]

Hi Kever,

On Tue, 16 Jul 2024 at 07:58, Kever Yang  wrote:
>
> Hi Anand,
>
> On 2024/5/31 22:18, Anand Moon wrote:
>
> From: Anand Moon 
>
> Read the reset cause from clock reset unit for RK3328 SoC.
>
> Cc: Jagan Teki 
> Signed-off-by: Anand Moon 
> Signed-off-by: Anand Moon 
>
> I thing one signature is enough for you, right?

Ok, earlier the emails were bouncing back
>
> ---
>  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>  arch/arm/mach-rockchip/cpu-info.c| 4 +++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
> b/arch/arm/include/asm/arch-rockchip/cru.h
> index 9778790f34..a1499e9652 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -13,6 +13,8 @@
>
>  #if defined(CONFIG_ROCKCHIP_RK3288)
>  # include 
> +#elif defined(CONFIG_ROCKCHIP_RK3328)
> +#include 
>  #elif defined(CONFIG_ROCKCHIP_RK3399)
>  # include 
>  #elif defined(CONFIG_ROCKCHIP_RK3568)
> diff --git a/arch/arm/mach-rockchip/cpu-info.c 
> b/arch/arm/mach-rockchip/cpu-info.c
> index a62ff53c6a..86b0c02970 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -14,7 +14,9 @@
>
>  char *get_reset_cause(void)
>  {
> - struct rockchip_cru *cru = rockchip_get_cru();
> +#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
> + struct rk3328_cru *cru = rockchip_get_cru();
> +#endif
>
> I think we can use "rockchip_cru" for all the SoC with below define in 
> cru_rk3568.h?
>
> #define rockchip_cru rk3328_cru
>
Ok, I will follow this in the next version.
>
> Thanks,
> - Kever
Thanks
-Anand

Re: [PATCH v1 1/2] dm: exynos: Correct CONFIG_SYS_BOARD setting for Odroid XU3 boards

[Anand Moon]

Hi All,

On Wed, 26 Jun 2024 at 21:07, Sam Protsenko  wrote:
>
> On Wed, Jun 26, 2024 at 10:15 AM Anand Moon  wrote:
> >
> > Fix the issue where CONFIG_SYS_BOARD was incorrectly set on
> > Odroid XU3 boards, causing boot failure. This was resolved by
> > correcting the SYS_BOARD entry in Kconfig to load the correct
> > device tree source (dts) for the Odroid Exynos5422 Platforms.
> >
> > Fixes: f76750d11133 ("Convert CONFIG_CONS_INDEX et al to Kconfig")
> > Signed-off-by: Anand Moon 
> > ---
> > U-Boot 2024.07-rc5-00042-g80a111f426 (Jun 26 2024 - 15:03:09 +0530) for 
> > ODROID-XU3/XU4/HC1/HC2
> >
> > CPU:   Exynos5422 @ 800 MHz
> > DRAM:  2 GiB
> > Core:  74 devices, 12 uclasses, devicetree: separate
> > MMC:   mmc@1220: 0, mmc@1222: 2
> > Loading Environment from MMC... Reading from MMC(2)... *** Warning - bad 
> > CRC, using default environment
> >
> > In:serial
> > Out:   serial
> > Err:   serial
> > Model: Odroid XU3/XU4/HC1/HC2 based on Exynos5422
> > Type:  xu4
> > Boot device: MMC(2)
> > Net:   No ethernet found.
> > Hit any key to stop autoboot:  0
> > switch to partitions #0, OK
> > mmc2 is current device
> > Scanning mmc 2:1...
> > Found U-Boot script /boot/boot.scr
> > 2046 bytes read in 22 ms (90.8 KiB/s)
> > 8104280 bytes read in 519 ms (14.9 MiB/s)
> > Failed to load '/boot/dtbs/exynos5422-smdk5420xu4.dtb'
> > SCRIPT FAILED: continuing...
> > No EFI system partition
> > No EFI system partition
> > Failed to persist EFI variables
> > No EFI system partition
> > Failed to persist EFI variables
> > No EFI system partition
> > Failed to persist EFI variables
> > Loading Boot 'mmc 2' failed
> > EFI boot manager: Cannot load any image
> > MMC Device 1 not found
> > no mmc device at slot 1
> > ---
>
> Reviewed-by: Sam Protsenko 
>
Thanks

Gentle ping?

Thanks
-Anand

Re: [PATCH v2 00/40] mmc: dw_mmc: Enable eMMC on E850-96 board

[Anand Moon]

Hi Sam,

On Wed, 19 Jun 2024 at 02:26, Sam Protsenko  wrote:
>
> If there are no new comments on this series, can you please apply it?
>
> Thanks!

Tested on Odroid XU4 and Odrroid U3 boards

Please add my

Reviewed-by: Anand Moon 
Tested-by: Anand Moon 

Thanks
-Anand

[PATCH v1 2/2] odroid: Fix target platform compilation issue on Odroid-XU3

[Anand Moon]

Resolved a compilation issue where the build system attempted
to compile for the Odroid-XU3 platform instead of the specified
Exynos4412 platform due to an incorrect CONFIG_SYS_BOARD setting.
Updated the Makefile to ensure that compilation only occurs for
the Odroid-XU3 specified target platform.

Now, object files will be generated only when building for the
TARGET_ODROID platform.

Signed-off-by: Anand Moon 
---
Tested om Odroid-U3 and Odroid-XU4.
---
 board/samsung/odroid/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile
index 5bf48313de..615c99f501 100644
--- a/board/samsung/odroid/Makefile
+++ b/board/samsung/odroid/Makefile
@@ -3,4 +3,4 @@
 # Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
 # Przemyslaw Marczak 
 
-obj-y  := odroid.o
+obj-$(CONFIG_TARGET_ODROID):= odroid.o
-- 
2.44.0

[PATCH v1 1/2] dm: exynos: Correct CONFIG_SYS_BOARD setting for Odroid XU3 boards

[Anand Moon]

Fix the issue where CONFIG_SYS_BOARD was incorrectly set on
Odroid XU3 boards, causing boot failure. This was resolved by
correcting the SYS_BOARD entry in Kconfig to load the correct
device tree source (dts) for the Odroid Exynos5422 Platforms.

Fixes: f76750d11133 ("Convert CONFIG_CONS_INDEX et al to Kconfig")
Signed-off-by: Anand Moon 
---
U-Boot 2024.07-rc5-00042-g80a111f426 (Jun 26 2024 - 15:03:09 +0530) for 
ODROID-XU3/XU4/HC1/HC2

CPU:   Exynos5422 @ 800 MHz
DRAM:  2 GiB
Core:  74 devices, 12 uclasses, devicetree: separate
MMC:   mmc@1220: 0, mmc@1222: 2
Loading Environment from MMC... Reading from MMC(2)... *** Warning - bad CRC, 
using default environment

In:serial
Out:   serial
Err:   serial
Model: Odroid XU3/XU4/HC1/HC2 based on Exynos5422
Type:  xu4
Boot device: MMC(2)
Net:   No ethernet found.
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc2 is current device
Scanning mmc 2:1...
Found U-Boot script /boot/boot.scr
2046 bytes read in 22 ms (90.8 KiB/s)
8104280 bytes read in 519 ms (14.9 MiB/s)
Failed to load '/boot/dtbs/exynos5422-smdk5420xu4.dtb'
SCRIPT FAILED: continuing...
No EFI system partition
No EFI system partition
Failed to persist EFI variables
No EFI system partition
Failed to persist EFI variables
No EFI system partition
Failed to persist EFI variables
Loading Boot 'mmc 2' failed
EFI boot manager: Cannot load any image
MMC Device 1 not found
no mmc device at slot 1
---
 board/samsung/smdk5420/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig
index a9d62fffa5..37d6bbbed1 100644
--- a/board/samsung/smdk5420/Kconfig
+++ b/board/samsung/smdk5420/Kconfig
@@ -1,7 +1,7 @@
 if TARGET_ODROID_XU3
 
 config SYS_BOARD
-   default "smdk5420"
+   default "odroid"
 
 config SYS_VENDOR
default "samsung"

base-commit: c53b344475734d0d29f522b7b1d80c5b8204442d
-- 
2.44.0

[PATCH] Fix Kconfig coding style from spaces to tab

[Anand Moon]

Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^/\t/' -i */Kconfig

Signed-off-by: Anand Moon 
---
 boot/Kconfig |  8 
 cmd/Kconfig  | 20 ++--
 disk/Kconfig |  2 +-
 lib/Kconfig  |  2 +-
 net/Kconfig  |  4 ++--
 5 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/boot/Kconfig b/boot/Kconfig
index 6f3096c15a..12148ac3f2 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -150,10 +150,10 @@ config FIT_IMAGE_POST_PROCESS
  processed before being added to the FIT image).
 
 config FIT_PRINT
-bool "Support FIT printing"
-default y
-help
-  Support printing the content of the fitImage in a verbose manner.
+   bool "Support FIT printing"
+   default y
+   help
+ Support printing the content of the fitImage in a verbose manner.
 
 config SPL_FIT
bool "Support Flattened Image Tree within SPL"
diff --git a/cmd/Kconfig b/cmd/Kconfig
index b026439c77..011f4ad429 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -271,7 +271,7 @@ config CMD_BOOTM_PRE_LOAD
depends on CMD_BOOTM
depends on IMAGE_PRE_LOAD
help
- Enable support of stage pre-load for the bootm command.
+Enable support of stage pre-load for the bootm command.
 This stage allow to check or modify the image provided
 to the bootm command.
 
@@ -897,9 +897,9 @@ config CMD_MX_CYCLIC
bool "Enable cyclic md/mw commands"
depends on CMD_MEMORY
help
-  Add the "mdc" and "mwc" memory commands. These are cyclic
-  "md/mw" commands.
-  Examples:
+ Add the "mdc" and "mwc" memory commands. These are cyclic
+ "md/mw" commands.
+ Examples:
 
  => mdc.b 10 4 500
  This command will print 4 bytes (10,11,12,13) each 500 ms.
@@ -2150,12 +2150,12 @@ config CMD_BLKMAP
 
  Example use-cases:
  - Treat a region of RAM as a block device, i.e. a RAM disk. This let's
-you extract files from filesystem images stored in RAM (perhaps as 
a
-result of a TFTP transfer).
+   you extract files from filesystem images stored in RAM (perhaps as a
+   result of a TFTP transfer).
  - Create a virtual partition on an existing device. This let's you
-access filesystems that aren't stored at an exact partition
-boundary. A common example is a filesystem image embedded in an FIT
-image.
+   access filesystems that aren't stored at an exact partition
+   boundary. A common example is a filesystem image embedded in an FIT
+   image.
 
 config CMD_BUTTON
bool "button"
@@ -2934,7 +2934,7 @@ config CMD_UBI_RENAME
bool "Enable rename"
depends on CMD_UBI
help
- Enable a "ubi" command to rename ubi volume:
+Enable a "ubi" command to rename ubi volume:
   ubi rename  
 
 config CMD_UBIFS
diff --git a/disk/Kconfig b/disk/Kconfig
index 8549695807..ffa835eb35 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -116,7 +116,7 @@ config EFI_PARTITION_ENTRIES_NUMBERS
  number.
 
 config EFI_PARTITION_ENTRIES_OFF
-int "Offset (in bytes) of the EFI partition entries"
+   int "Offset (in bytes) of the EFI partition entries"
depends on EFI_PARTITION
default 0
help
diff --git a/lib/Kconfig b/lib/Kconfig
index 189e6eb31a..b8e4f516f9 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -1143,7 +1143,7 @@ config PHANDLE_CHECK_SEQ
bool "Enable phandle check while getting sequence number"
help
  When there are multiple device tree nodes with same name,
-  enable this config option to distinguish them using
+ enable this config option to distinguish them using
  phandles in fdtdec_get_alias_seq() function.
 
 endmenu
diff --git a/net/Kconfig b/net/Kconfig
index 5dff633629..7cb80b880a 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -42,8 +42,8 @@ config BOOTP_SEND_HOSTNAME
  DNS server. To do this, they need the hostname of the DHCP
  requester.
  If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
-  of the "hostname" environment variable is passed as
-  option 12 to the DHCP server.
+ of the "hostname" environment variable is passed as
+ option 12 to the DHCP server.
 
 config NET_RANDOM_ETHADDR
bool "Random ethaddr if unset"
-- 
2.44.0

Re: [PATCH 0/3] rockchip: rk8xx: fix broken [np]ldo callbacks

[Anand Moon]

Hi Quentin,

On Wed, 5 Jun 2024 at 15:03, Quentin Schulz  wrote:
>
> This is for master branch, merge ASAP as it's known to break at least
> Chromebook Jerry.
>
> @Simon, can you please check that this fixes your CB?
>
> The wrong udevice was passed to the functions, making them call the
> pmic callbacks on the parent of the pmic udevice instead of the pmic
> udevice itself.
>
> While at it, ensure consistency by having all internal functions use
> pmic udevice instead of the regulator udevice.
>
> Finally, clarify operator precedence in ternary condition as reported by
> my linter.
>
> Signed-off-by: Quentin Schulz 

I see we have not been able to follow configs on a few of the board's for RK3588

CONFIG_CMD_REGULATOR=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y

could you enable the options with imply for all the rockchip boards?

Thanks
-Anand

> ---
> Quentin Schulz (3):
>   regulator: rk8xx: fix incorrect device used for 
> _ldo_[sg]et_suspend_value
>   regulator: rk8xx: pass pmic udevice instead of regulator to all 
> internal functions
>   regulator: rk8xx: clarify operator precedence
>
>  drivers/power/regulator/rk8xx.c | 54 
> -
>  1 file changed, 27 insertions(+), 27 deletions(-)
> ---
> base-commit: c0ea27bccfb7d2d37fd36806ac2a2f7389099420
> change-id: 20240605-pmic-rk8xx-52f2286be334
>
> Best regards,
> --
> Quentin Schulz 
>

Re: [PATCH RFC v2 20/23] rockchip: RV1126: Read the reset cause from clock reset unit for RV1126 SoC

[Anand Moon]

Hi Dragan,

On Sat, 1 Jun 2024 at 03:23, Dragan Simic  wrote:
>
> Hello Anand,
>
> On 2024-05-31 16:18, Anand Moon wrote:
> > From: Anand Moon 
> >
> > Read the reset cause from clock reset unit for RV1126 SoC.
> >
> > Cc: Jagan Teki 
> > Signed-off-by: Anand Moon 
> > Signed-off-by: Anand Moon 
> > ---
> >  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
> >  arch/arm/mach-rockchip/cpu-info.c| 2 ++
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
> > b/arch/arm/include/asm/arch-rockchip/cru.h
> > index e886adf515..e1a8d8adad 100644
> > --- a/arch/arm/include/asm/arch-rockchip/cru.h
> > +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> > @@ -29,6 +29,8 @@
> >  #include 
>
> Although not related to this patch directly, a single space character
> should be added between "#" and "include", for consistency.
>
Not sure of this.
> >  #elif defined(CONFIG_ROCKCHIP_RV1108)
> >  #include 
>
> The same comment as above.
>
> > +#elif defined(CONFIG_ROCKCHIP_RV1126)
> > +#include 
>
> The same comment as above, but this time related to this patch.
>
> >  #endif

Let me check this again if needed. I will update in the next version.

Thanks
-Anand

Re: [PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC

[Anand Moon]

Hi Jonas

On Fri, 31 May 2024 at 22:14, Jonas Karlman  wrote:
>
> Hi Anand and Kever,
>
> On 2024-05-31 16:18, Anand Moon wrote:
> > From: Kever Yang 
> >
> > Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.
>
> What is this trying to fix? And what SoCs is affected?
>
> My arm64 RK SoCs seem to reset using warm reset (second global reset).
>
I found this patch related to CRU so it was added in this series.
My goal is to test all the remaining SoC and see if any thing is missing
in my testing.

> >
> > Cc: Jagan Teki 
> > Signed-off-by: Kever Yang 
> > ---
> >  drivers/sysreset/sysreset_rockchip.c | 5 +
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/sysreset/sysreset_rockchip.c 
> > b/drivers/sysreset/sysreset_rockchip.c
> > index f353f9b4c7..17aa191349 100644
> > --- a/drivers/sysreset/sysreset_rockchip.c
> > +++ b/drivers/sysreset/sysreset_rockchip.c
> > @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum 
> > sysreset_t type)
> >
> >   switch (type) {
> >   case SYSRESET_WARM:
> > +#ifdef CONFIG_ARM64
> > + /* Rockchip 64bit SOC need fst reset for cpu reset entry */
> > + writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
> > +#else
> >   writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> > +#endif
>
> If this is needed maybe use something like this and let it fall through
> to SYSRESET_COLD?
>
>   if (!IS_ENABLED(CONFIG_ARM64)) {
> writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> break;
>   }
>

Ok I will update this in next version

> Regards,
> Jonas
Thanks
-Anand

[PATCH RFC v2 23/23] sysreset: rockchip: use dev_read_addr_ptr get cru base

[Anand Moon]

From: Andy Yan 

Use system api dev_read_addr_ptr to get cru reg base,
rather than rockchip private api rockchip_get_cru, which
will be cleanup later.

Cc: Jagan Teki 
Signed-off-by: Andy Yan 
---
 drivers/sysreset/sysreset_rockchip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/sysreset/sysreset_rockchip.c 
b/drivers/sysreset/sysreset_rockchip.c
index 17aa191349..df6422c08b 100644
--- a/drivers/sysreset/sysreset_rockchip.c
+++ b/drivers/sysreset/sysreset_rockchip.c
@@ -8,14 +8,14 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 
 int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
struct sysreset_reg *offset = dev_get_priv(dev);
-   unsigned long cru_base = (unsigned long)rockchip_get_cru();
+   unsigned long cru_base = (unsigned long)dev_read_addr_ptr(dev->parent);
 
if (IS_ERR_VALUE(cru_base))
return (int)cru_base;
-- 
2.44.0

[PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC

[Anand Moon]

From: Kever Yang 

Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.

Cc: Jagan Teki 
Signed-off-by: Kever Yang 
---
 drivers/sysreset/sysreset_rockchip.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/sysreset/sysreset_rockchip.c 
b/drivers/sysreset/sysreset_rockchip.c
index f353f9b4c7..17aa191349 100644
--- a/drivers/sysreset/sysreset_rockchip.c
+++ b/drivers/sysreset/sysreset_rockchip.c
@@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum 
sysreset_t type)
 
switch (type) {
case SYSRESET_WARM:
+#ifdef CONFIG_ARM64
+   /* Rockchip 64bit SOC need fst reset for cpu reset entry */
+   writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
+#else
writel(0xeca8, cru_base + offset->glb_srst_snd_value);
+#endif
break;
case SYSRESET_COLD:
writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
-- 
2.44.0

[PATCH RFC v2 21/23] rockchip: RV1126: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all RV1126 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/neu2-io-rv1126_defconfig  | 1 -
 configs/sonoff-ihost-rv1126_defconfig | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/neu2-io-rv1126_defconfig b/configs/neu2-io-rv1126_defconfig
index 2a4c9b45a0..0bca5dfffb 100644
--- a/configs/neu2-io-rv1126_defconfig
+++ b/configs/neu2-io-rv1126_defconfig
@@ -16,7 +16,6 @@ CONFIG_DEBUG_UART=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_BOOTM_LEN=0x400
 CONFIG_DEFAULT_FDT_FILE="rv1126-edgeble-neu2-io.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
diff --git a/configs/sonoff-ihost-rv1126_defconfig 
b/configs/sonoff-ihost-rv1126_defconfig
index 4890644c7e..aa77ff3be4 100644
--- a/configs/sonoff-ihost-rv1126_defconfig
+++ b/configs/sonoff-ihost-rv1126_defconfig
@@ -17,7 +17,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SYS_BOOTM_LEN=0x400
 CONFIG_DEFAULT_FDT_FILE="rv1126-sonoff-ihost.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
-- 
2.44.0

[PATCH RFC v2 20/23] rockchip: RV1126: Read the reset cause from clock reset unit for RV1126 SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for RV1126 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c| 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h
index e886adf515..e1a8d8adad 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -29,6 +29,8 @@
 #include 
 #elif defined(CONFIG_ROCKCHIP_RV1108)
 #include 
+#elif defined(CONFIG_ROCKCHIP_RV1126)
+#include 
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index b2cfdade13..cb4ac39884 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -32,6 +32,8 @@ char *get_reset_cause(void)
struct rk3368_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RV1108)
struct rv1108_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RV1126)
+   struct rv1126_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 19/23] rockchip: RV1108: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all RV1108 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/elgin-rv1108_defconfig | 1 -
 configs/evb-rv1108_defconfig   | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig
index 454ed9e0a6..1fffa99793 100644
--- a/configs/elgin-rv1108_defconfig
+++ b/configs/elgin-rv1108_defconfig
@@ -17,7 +17,6 @@ CONFIG_SYS_LOAD_ADDR=0x6200
 CONFIG_DEBUG_UART=y
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig
index 6204cb4b96..8bff3a99e5 100644
--- a/configs/evb-rv1108_defconfig
+++ b/configs/evb-rv1108_defconfig
@@ -14,7 +14,6 @@ CONFIG_SYS_LOAD_ADDR=0x6200
 CONFIG_DEBUG_UART=y
 CONFIG_BOOTCOMMAND="sf probe;sf read 0x6200 0x140800 0x50;dcache 
off;go 0x6200"
 CONFIG_DEFAULT_FDT_FILE="rv1108-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_CMD_USB=y
-- 
2.44.0

[PATCH RFC v2 18/23] rockchip: RV1108: Read the reset cause from clock reset unit for RV1108 SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for RV1108 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c| 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h
index 9cdd960fb1..e886adf515 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -27,6 +27,8 @@
 #include 
 #elif defined(CONFIG_ROCKCHIP_RK3368)
 #include 
+#elif defined(CONFIG_ROCKCHIP_RV1108)
+#include 
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index b9d2756a70..b2cfdade13 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -30,6 +30,8 @@ char *get_reset_cause(void)
struct rk3308_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3368)
struct rk3368_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RV1108)
+   struct rv1108_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 17/23] rockchip: RK3368: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all RK3368 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/evb-px5_defconfig  | 1 -
 configs/geekbox_defconfig  | 1 -
 configs/lion-rk3368_defconfig  | 1 -
 configs/sheep-rk3368_defconfig | 1 -
 4 files changed, 4 deletions(-)

diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index ccd3883153..9be143487e 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -37,7 +37,6 @@ CONFIG_SPL_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
index 8f4be79831..de526ae14d 100644
--- a/configs/geekbox_defconfig
+++ b/configs/geekbox_defconfig
@@ -15,7 +15,6 @@ CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_REGMAP=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index a4a7f1a5cb..e5bcc13038 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -34,7 +34,6 @@ CONFIG_SPL_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-lion-haikou.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
index a591b2741d..5e58877012 100644
--- a/configs/sheep-rk3368_defconfig
+++ b/configs/sheep-rk3368_defconfig
@@ -15,7 +15,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-sheep.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-- 
2.44.0

[PATCH RFC v2 16/23] rockchip: RK3368: Read the reset cause from clock reset unit for RK3368 SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for RK3368 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c| 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h
index 6fe73ad0cc..9cdd960fb1 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -25,6 +25,8 @@
 #include 
 #elif defined(CONFIG_ROCKCHIP_RK3308)
 #include 
+#elif defined(CONFIG_ROCKCHIP_RK3368)
+#include 
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index dbc126c862..b9d2756a70 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -28,6 +28,8 @@ char *get_reset_cause(void)
struct rockchip_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3308)
struct rk3308_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3368)
+   struct rk3368_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 15/23] rockchip: RK3308: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all RK3308 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/evb-rk3308_defconfig   | 1 -
 configs/roc-cc-rk3308_defconfig| 1 -
 configs/rock-pi-s-rk3308_defconfig | 1 -
 3 files changed, 3 deletions(-)

diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index f4c2ea12ad..4622b2b2d4 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -16,7 +16,6 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 862ea4301f..cb5a868944 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -16,7 +16,6 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
diff --git a/configs/rock-pi-s-rk3308_defconfig 
b/configs/rock-pi-s-rk3308_defconfig
index c15ba3d8a4..d888cfaa36 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -16,7 +16,6 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-- 
2.44.0

[PATCH RFC v2 14/23] rockchip: RK3308: Read the reset cause from clock reset unit for RK3308 SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for RK3308 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c| 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h
index 7a69a839e6..6fe73ad0cc 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -23,6 +23,8 @@
 #include 
 #elif defined(CONFIG_ROCKCHIP_PX30)
 #include 
+#elif defined(CONFIG_ROCKCHIP_RK3308)
+#include 
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index 383aa3d2ee..dbc126c862 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -26,6 +26,8 @@ char *get_reset_cause(void)
struct px30_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3288)
struct rockchip_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3308)
+   struct rk3308_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 13/23] rockchip: RK3288: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all RK3288 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/chromebit_mickey_defconfig  | 1 -
 configs/chromebook_jerry_defconfig  | 1 -
 configs/chromebook_minnie_defconfig | 1 -
 configs/chromebook_speedy_defconfig | 1 -
 4 files changed, 4 deletions(-)

diff --git a/configs/chromebit_mickey_defconfig 
b/configs/chromebit_mickey_defconfig
index e5d805d7da..e1d31d0b4c 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -31,7 +31,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 9bc59539dc..dba1466689 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -30,7 +30,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/chromebook_minnie_defconfig 
b/configs/chromebook_minnie_defconfig
index 26fa05e543..e6cf734b14 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -31,7 +31,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/chromebook_speedy_defconfig 
b/configs/chromebook_speedy_defconfig
index 5deb09b28e..90364dfc48 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -31,7 +31,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_SPL_PAD_TO=0x7f8000
-- 
2.44.0

[PATCH RFC v2 12/23] rockchip: RK3288: Read the reset cause from clock reset unit for RK3288 SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for RK3288 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/cpu-info.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index 9be28754fd..383aa3d2ee 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -24,6 +24,8 @@ char *get_reset_cause(void)
struct rk3588_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_PX30)
struct px30_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3288)
+   struct rockchip_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 11/23] rockchip: PX30: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all PX30 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/evb-px30_defconfig| 1 -
 configs/firefly-px30_defconfig| 1 -
 configs/px30-core-ctouch2-of10-px30_defconfig | 1 -
 configs/px30-core-ctouch2-px30_defconfig  | 1 -
 configs/px30-core-edimm2.2-px30_defconfig | 1 -
 configs/ringneck-px30_defconfig   | 1 -
 6 files changed, 6 deletions(-)

diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 73a3c6120e..72b562ed69 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -32,7 +32,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-evb.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x2
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 0a14b39366..2310c0bdc5 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -33,7 +33,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-firefly.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x2
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig 
b/configs/px30-core-ctouch2-of10-px30_defconfig
index 87a39e115d..3c9b9b8493 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -33,7 +33,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2-of10.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x2
diff --git a/configs/px30-core-ctouch2-px30_defconfig 
b/configs/px30-core-ctouch2-px30_defconfig
index 7162c117be..3040fc5405 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -33,7 +33,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x2
diff --git a/configs/px30-core-edimm2.2-px30_defconfig 
b/configs/px30-core-edimm2.2-px30_defconfig
index 1182f60358..7431bedf7a 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -33,7 +33,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x2
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 94179dca3a..f571eb6b11 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -21,7 +21,6 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x2
-- 
2.44.0

[PATCH RFC v2 10/23] rockchip: PX30: Read the reset cause from clock reset unit for PX30 SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for PX30 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c| 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h
index 19bd2b405b..7a69a839e6 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -21,6 +21,8 @@
 #include 
 #elif defined(CONFIG_ROCKCHIP_RK3588)
 #include 
+#elif defined(CONFIG_ROCKCHIP_PX30)
+#include 
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index 113a03acdf..9be28754fd 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -22,6 +22,8 @@ char *get_reset_cause(void)
struct rk3568_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3588)
struct rk3588_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_PX30)
+   struct px30_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 09/23] rockchip: RK3588: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all RK3588 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/coolpi-4b-rk3588s_defconfig  | 1 -
 configs/coolpi-cm5-evb-rk3588_defconfig  | 1 -
 configs/evb-rk3588_defconfig | 1 -
 configs/generic-rk3588_defconfig | 1 -
 configs/jaguar-rk3588_defconfig  | 1 -
 configs/nanopc-t6-rk3588_defconfig   | 1 -
 configs/neu6a-io-rk3588_defconfig| 1 -
 configs/neu6b-io-rk3588_defconfig| 1 -
 configs/orangepi-5-plus-rk3588_defconfig | 1 -
 configs/orangepi-5-rk3588s_defconfig | 1 -
 configs/quartzpro64-rk3588_defconfig | 1 -
 configs/rock5a-rk3588s_defconfig | 1 -
 configs/rock5b-rk3588_defconfig  | 1 -
 configs/toybrick-rk3588_defconfig| 1 -
 configs/turing-rk1-rk3588_defconfig  | 1 -
 15 files changed, 15 deletions(-)

diff --git a/configs/coolpi-4b-rk3588s_defconfig 
b/configs/coolpi-4b-rk3588s_defconfig
index 3d45d939ab..b094224f6e 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig 
b/configs/coolpi-cm5-evb-rk3588_defconfig
index 5190d69c1c..382ee97fc9 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 1d5585677a..bfc505a4b7 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
index 42bc2c9a76..ddb23b035b 100644
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index b69cf4cd05..712a936539 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -22,7 +22,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CYCLIC=y
 CONFIG_SPL_MAX_SIZE=0x4
diff --git a/configs/nanopc-t6-rk3588_defconfig 
b/configs/nanopc-t6-rk3588_defconfig
index 926267f93a..978c62aee6 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/neu6a-io-rk3588_defconfig 
b/configs/neu6a-io-rk3588_defconfig
index ac281e6539..6f2765c640 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/neu6b-io-rk3588_defconfig 
b/configs/neu6b-io-rk3588_defconfig
index c01e5fb0d0..13b542a752 100644
--- a/configs/neu6b-io-rk3588_defconfig
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/orangepi-5-plus-rk3588_defconfig 
b/configs/orangepi-5-pl

[PATCH RFC v2 08/23] rockchip: RK3588: Read the reset cause from clock reset unit for RK3588 SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for RK3588 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c| 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h
index a1499e9652..19bd2b405b 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -19,6 +19,8 @@
 # include 
 #elif defined(CONFIG_ROCKCHIP_RK3568)
 #include 
+#elif defined(CONFIG_ROCKCHIP_RK3588)
+#include 
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index e12f84a1d2..113a03acdf 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -20,6 +20,8 @@ char *get_reset_cause(void)
struct rockchip_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3568)
struct rk3568_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3588)
+   struct rk3588_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 07/23] rockchip: RK3568: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all RK3568 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/anbernic-rgxx3-rk3566_defconfig   | 1 -
 configs/bpi-r2-pro-rk3568_defconfig   | 1 -
 configs/evb-rk3568_defconfig  | 1 -
 configs/generic-rk3568_defconfig  | 1 -
 configs/lubancat-2-rk3568_defconfig   | 1 -
 configs/nanopi-r5c-rk3568_defconfig   | 1 -
 configs/nanopi-r5s-rk3568_defconfig   | 1 -
 configs/odroid-m1-rk3568_defconfig| 1 -
 configs/pinetab2-rk3566_defconfig | 1 -
 configs/quartz64-a-rk3566_defconfig   | 1 -
 configs/quartz64-b-rk3566_defconfig   | 1 -
 configs/radxa-cm3-io-rk3566_defconfig | 1 -
 configs/radxa-e25-rk3568_defconfig| 1 -
 configs/rock-3a-rk3568_defconfig  | 1 -
 configs/soquartz-blade-rk3566_defconfig   | 1 -
 configs/soquartz-cm4-rk3566_defconfig | 1 -
 configs/soquartz-model-a-rk3566_defconfig | 1 -
 17 files changed, 17 deletions(-)

diff --git a/configs/anbernic-rgxx3-rk3566_defconfig 
b/configs/anbernic-rgxx3-rk3566_defconfig
index a03509bf46..95f7cf0739 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -21,7 +21,6 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_RNG_SEED=y
 CONFIG_SPL_MAX_SIZE=0x4
diff --git a/configs/bpi-r2-pro-rk3568_defconfig 
b/configs/bpi-r2-pro-rk3568_defconfig
index eccc15a0ae..4955fd907c 100644
--- a/configs/bpi-r2-pro-rk3568_defconfig
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 2076f55122..e6da8fd246 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index 66a33afbba..ba2d995cdc 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/lubancat-2-rk3568_defconfig 
b/configs/lubancat-2-rk3568_defconfig
index 88593bfa70..384d0ecfc5 100644
--- a/configs/lubancat-2-rk3568_defconfig
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r5c-rk3568_defconfig 
b/configs/nanopi-r5c-rk3568_defconfig
index 4a6c320faf..b83796083d 100644
--- a/configs/nanopi-r5c-rk3568_defconfig
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r5s-rk3568_defconfig 
b/configs/nanopi-r5s-rk3568_defconfig
index 7ab12e619a..5d500963a2 100644
--- a/configs/nanopi-r5s-rk3568_defconfig
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/odroid-m1-rk3568_defconfig 
b/configs/odroid-m1-rk3568_defconfig
index b5263caff6..7bea6e6851 100644
--- a/configs/odroid-m1-rk3568_defconfig
+++ b/configs/odroid-m1-rk3568_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-odroid-m1.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDI

[PATCH RFC v2 06/23] rockchip: RK3568: Read the reset cause from clock reset unit for RK356x SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for RK356x SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/cpu-info.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index e7cbcf5090..e12f84a1d2 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -18,6 +18,8 @@ char *get_reset_cause(void)
struct rk3328_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
struct rockchip_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3568)
+   struct rk3568_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 05/23] arm: rockchip: Enable display cpuinfo to be build with SPL_BUILD

[Anand Moon]

From: Anand Moon 

Changes help enable CONFIG_DISPLAY_CPUINFO to build with SPL_BUILD for
SoC RK356x and RK3588.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/Makefile | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c07bdaee4c..254c26034f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -23,9 +23,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 # meaning "turn it off".
 obj-y += boot_mode.o
 obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
-endif
-
-ifeq ($(CONFIG_TPL_BUILD),)
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
 endif
 
-- 
2.44.0

[PATCH RFC v2 04/23] rockchip: RK3399: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all RK3399 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/chromebook_bob_defconfig   | 1 -
 configs/chromebook_kevin_defconfig | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index acfe393410..2c1a8141c0 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -30,7 +30,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 # CONFIG_SPL_FIT_SIGNATURE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BLOBLIST=y
diff --git a/configs/chromebook_kevin_defconfig 
b/configs/chromebook_kevin_defconfig
index 95fdb418d8..f6649804c7 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -31,7 +31,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 # CONFIG_SPL_FIT_SIGNATURE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BLOBLIST=y
-- 
2.44.0

[PATCH RFC v2 03/23] rockchip: RK3399: Read the reset cause from clock reset unit for RK3399 SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for RK3399 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/cpu-info.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index 86b0c02970..e7cbcf5090 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -16,6 +16,8 @@ char *get_reset_cause(void)
 {
 #if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
struct rk3328_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
+   struct rockchip_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 02/23] rockchip: RK3328: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon 

Enable DISPLAY_CPUINFO options to support on all RK3328 boards,
Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 configs/evb-rk3328_defconfig  | 1 -
 configs/nanopi-r2c-plus-rk3328_defconfig  | 1 -
 configs/nanopi-r2c-rk3328_defconfig   | 1 -
 configs/nanopi-r2s-rk3328_defconfig   | 1 -
 configs/orangepi-r1-plus-lts-rk3328_defconfig | 1 -
 configs/orangepi-r1-plus-rk3328_defconfig | 1 -
 configs/roc-cc-rk3328_defconfig   | 1 -
 configs/rock-pi-e-rk3328_defconfig| 1 -
 configs/rock64-rk3328_defconfig   | 1 -
 9 files changed, 9 deletions(-)

diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index bfb8522343..e1c2016cb3 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig 
b/configs/nanopi-r2c-plus-rk3328_defconfig
index f311a0a80b..700ce47696 100644
--- a/configs/nanopi-r2c-plus-rk3328_defconfig
+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r2c-rk3328_defconfig 
b/configs/nanopi-r2c-rk3328_defconfig
index 533dc1029f..a594f329bf 100644
--- a/configs/nanopi-r2c-rk3328_defconfig
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r2s-rk3328_defconfig 
b/configs/nanopi-r2s-rk3328_defconfig
index 2591a9cc8a..c1d0a1f396 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig 
b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index 14cdbd813c..7e0b1b2773 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig 
b/configs/orangepi-r1-plus-rk3328_defconfig
index 7fe58e7a14..4525c99ca2 100644
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 91b9422e26..c1eb03c5e8 100644
--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/rock-pi-e-rk3328_defconfig 
b/configs/rock-pi-e-rk3328_defconfig
index 5cc54af3ca..bb99670b8c 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 9d77dfb709..836f18a806 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -22,7 +22,6 @@

[PATCH RFC v2 01/23] rockchip: RK3328: Read the reset cause from clock reset unit for RK3328 SoC

[Anand Moon]

From: Anand Moon 

Read the reset cause from clock reset unit for RK3328 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c| 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h 
b/arch/arm/include/asm/arch-rockchip/cru.h
index 9778790f34..a1499e9652 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -13,6 +13,8 @@
 
 #if defined(CONFIG_ROCKCHIP_RK3288)
 # include 
+#elif defined(CONFIG_ROCKCHIP_RK3328)
+#include 
 #elif defined(CONFIG_ROCKCHIP_RK3399)
 # include 
 #elif defined(CONFIG_ROCKCHIP_RK3568)
diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index a62ff53c6a..86b0c02970 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -14,7 +14,9 @@
 
 char *get_reset_cause(void)
 {
-   struct rockchip_cru *cru = rockchip_get_cru();
+#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
+   struct rk3328_cru *cru = rockchip_get_cru();
+#endif
char *cause = NULL;
 
if (IS_ERR(cru))
-- 
2.44.0

[PATCH RFC v2 00/23] Enable display cpuinfo to get the reset cause

[Anand Moon]

All the Rockchip SoC support reset cauee like POR_RST, GLB_RST,
TSADC_RST, WD_RST by reading the clock reset unit register.

V2: with the feedback from Jonas Karlman and Quentin Schulz
drop the inply for CONFIG_DISPLAY_CPUINFO as it defaault enabled.
re-organized the code.

As pointed only as of now RK3328, RK3399 supports this feature for POR
and RST.

On RK3568 and RK3588 SoC it only return POR, for all the case of reboot 
and poweroff. I have tried to debug this issue, found Clock Reset Unit 
will bind to rockchip_sysreset to determine the reset cause.
if there is ant input on this please share.

I have update two new patches from u-boot-radxa, but with no success.

[0] 
https://elixir.bootlin.com/u-boot/v2024.07-rc3/source/drivers/clk/rockchip/clk_rk3568.c#L2945

# dm tree # RK3568
 clk   5  [ + ]   rockchip_rk3588_cru   |-- clock-controller@fd7c
 sysreset  0  [   ]   rockchip_sysreset |   |-- sysreset
 reset 0  [ + ]   rockchip_reset|   `-- reset

[1] 
https://elixir.bootlin.com/u-boot/v2024.07-rc3/source/drivers/clk/rockchip/clk_rk3588.c#L2006

# dm tree  # RK3588
 clk   5  [ + ]   rockchip_rk3588_cru   |-- clock-controller@fd7c
 sysreset  0  [   ]   rockchip_sysreset |   |-- sysreset
 reset 0  [   ]   rockchip_reset|   `-- reset


Tested on Rock64, Rock-3a, Rock-5b boards.

I have update few Rockchip SoC to verify this feature,
Only Build to since I dont have the hardware.

Thanks
-Anand

Anand Moon (21):
  rockchip: RK3328: Read the reset cause from clock reset unit for
RK3328 SoC
  rockchip: RK3328: Enable display cpuinfo support on all boards
  rockchip: RK3399: Read the reset cause from clock reset unit for
RK3399 SoC
  rockchip: RK3399: Enable display cpuinfo support on all boards
  arm: rockchip: Enable display cpuinfo to be build with SPL_BUILD
  rockchip: RK3568: Read the reset cause from clock reset unit for
RK356x SoC
  rockchip: RK3568: Enable display cpuinfo support on all boards
  rockchip: RK3588: Read the reset cause from clock reset unit for
RK3588 SoC
  rockchip: RK3588: Enable display cpuinfo support on all boards
  rockchip: PX30: Read the reset cause from clock reset unit for PX30
SoC
  rockchip: PX30: Enable display cpuinfo support on all boards
  rockchip: RK3288: Read the reset cause from clock reset unit for
RK3288 SoC
  rockchip: RK3288: Enable display cpuinfo support on all boards
  rockchip: RK3308: Read the reset cause from clock reset unit for
RK3308 SoC
  rockchip: RK3308: Enable display cpuinfo support on all boards
  rockchip: RK3368: Read the reset cause from clock reset unit for
RK3368 SoC
  rockchip: RK3368: Enable display cpuinfo support on all boards
  rockchip: RV1108: Read the reset cause from clock reset unit for
RV1108 SoC
  rockchip: RV1108: Enable display cpuinfo support on all boards
  rockchip: RV1126: Read the reset cause from clock reset unit for
RV1126 SoC
  rockchip: RV1126: Enable display cpuinfo support on all boards

Andy Yan (1):
  sysreset: rockchip: use dev_read_addr_ptr get cru base

Kever Yang (1):
  sysreset: rockchip: use fst reset for ARM64 SOC

 arch/arm/include/asm/arch-rockchip/cru.h  | 14 +
 arch/arm/mach-rockchip/Makefile   |  3 ---
 arch/arm/mach-rockchip/cpu-info.c | 20 +++
 configs/anbernic-rgxx3-rk3566_defconfig   |  1 -
 configs/bpi-r2-pro-rk3568_defconfig   |  1 -
 configs/chromebit_mickey_defconfig|  1 -
 configs/chromebook_bob_defconfig  |  1 -
 configs/chromebook_jerry_defconfig|  1 -
 configs/chromebook_kevin_defconfig|  1 -
 configs/chromebook_minnie_defconfig   |  1 -
 configs/chromebook_speedy_defconfig   |  1 -
 configs/coolpi-4b-rk3588s_defconfig   |  1 -
 configs/coolpi-cm5-evb-rk3588_defconfig   |  1 -
 configs/elgin-rv1108_defconfig|  1 -
 configs/evb-px30_defconfig|  1 -
 configs/evb-px5_defconfig |  1 -
 configs/evb-rk3308_defconfig  |  1 -
 configs/evb-rk3328_defconfig  |  1 -
 configs/evb-rk3568_defconfig  |  1 -
 configs/evb-rk3588_defconfig  |  1 -
 configs/evb-rv1108_defconfig  |  1 -
 configs/firefly-px30_defconfig|  1 -
 configs/geekbox_defconfig |  1 -
 configs/generic-rk3568_defconfig  |  1 -
 configs/generic-rk3588_defconfig  |  1 -
 configs/jaguar-rk3588_defconfig   |  1 -
 configs/lion-rk3368_defconfig |  1 -
 configs/lubancat-2-rk3568_defconfig   |  1 -
 configs/nanopc-t6-rk3588_defconfig|  1 -
 configs/nanopi-r2c-plus-rk3328_defconfig  |  1 -
 configs/nanopi-r2c-rk3328_defconfig   |  1 -
 configs/nanopi-r2s-rk3328_defconfig   |  1 -
 configs/nanopi-r5c-rk3568_defconfig   |  1

[PATCH RFC v2 00/23] Enable display cpuinfo to get the reset cause

[Anand Moon]

All the Rockchip SoC support reset cauee like POR_RST, GLB_RST,
TSADC_RST, WD_RST by reading the clock reset unit register.

V2: with the feedback from Jonas Karlman and Quentin Schulz
drop the inply for CONFIG_DISPLAY_CPUINFO as it defaault enabled.
re-organized the code.

As pointed only as of now RK3328, RK3399 supports this feature for POR
and RST.

On RK3568 and RK3588 SoC it only return POR, for all the case of reboot 
and poweroff. I have tried to debug this issue, found Clock Reset Unit 
will bind to rockchip_sysreset to determine the reset cause.
if there is ant input on this please share.

I have update two new patches from u-boot-radxa, but with no success.

[0] 
https://elixir.bootlin.com/u-boot/v2024.07-rc3/source/drivers/clk/rockchip/clk_rk3568.c#L2945

# dm tree # RK3568
 clk   5  [ + ]   rockchip_rk3588_cru   |-- clock-controller@fd7c
 sysreset  0  [   ]   rockchip_sysreset |   |-- sysreset
 reset 0  [ + ]   rockchip_reset|   `-- reset

[1] 
https://elixir.bootlin.com/u-boot/v2024.07-rc3/source/drivers/clk/rockchip/clk_rk3588.c#L2006

# dm tree  # RK3588
 clk   5  [ + ]   rockchip_rk3588_cru   |-- clock-controller@fd7c
 sysreset  0  [   ]   rockchip_sysreset |   |-- sysreset
 reset 0  [   ]   rockchip_reset|   `-- reset


Tested on Rock64, Rock-3a, Rock-5b boards.

I have update few Rockchip SoC to verify this feature,
Only Build to since I dont have the hardware.

Thanks
-Anand

Anand Moon (21):
  rockchip: RK3328: Read the reset cause from clock reset unit for
RK3328 SoC
  rockchip: RK3328: Enable display cpuinfo support on all boards
  rockchip: RK3399: Read the reset cause from clock reset unit for
RK3399 SoC
  rockchip: RK3399: Enable display cpuinfo support on all boards
  arm: rockchip: Enable display cpuinfo to be build with SPL_BUILD
  rockchip: RK3568: Read the reset cause from clock reset unit for
RK356x SoC
  rockchip: RK3568: Enable display cpuinfo support on all boards
  rockchip: RK3588: Read the reset cause from clock reset unit for
RK3588 SoC
  rockchip: RK3588: Enable display cpuinfo support on all boards
  rockchip: PX30: Read the reset cause from clock reset unit for PX30
SoC
  rockchip: PX30: Enable display cpuinfo support on all boards
  rockchip: RK3288: Read the reset cause from clock reset unit for
RK3288 SoC
  rockchip: RK3288: Enable display cpuinfo support on all boards
  rockchip: RK3308: Read the reset cause from clock reset unit for
RK3308 SoC
  rockchip: RK3308: Enable display cpuinfo support on all boards
  rockchip: RK3368: Read the reset cause from clock reset unit for
RK3368 SoC
  rockchip: RK3368: Enable display cpuinfo support on all boards
  rockchip: RV1108: Read the reset cause from clock reset unit for
RV1108 SoC
  rockchip: RV1108: Enable display cpuinfo support on all boards
  rockchip: RV1126: Read the reset cause from clock reset unit for
RV1126 SoC
  rockchip: RV1126: Enable display cpuinfo support on all boards

Andy Yan (1):
  sysreset: rockchip: use dev_read_addr_ptr get cru base

Kever Yang (1):
  sysreset: rockchip: use fst reset for ARM64 SOC

 arch/arm/include/asm/arch-rockchip/cru.h  | 14 +
 arch/arm/mach-rockchip/Makefile   |  3 ---
 arch/arm/mach-rockchip/cpu-info.c | 20 +++
 configs/anbernic-rgxx3-rk3566_defconfig   |  1 -
 configs/bpi-r2-pro-rk3568_defconfig   |  1 -
 configs/chromebit_mickey_defconfig|  1 -
 configs/chromebook_bob_defconfig  |  1 -
 configs/chromebook_jerry_defconfig|  1 -
 configs/chromebook_kevin_defconfig|  1 -
 configs/chromebook_minnie_defconfig   |  1 -
 configs/chromebook_speedy_defconfig   |  1 -
 configs/coolpi-4b-rk3588s_defconfig   |  1 -
 configs/coolpi-cm5-evb-rk3588_defconfig   |  1 -
 configs/elgin-rv1108_defconfig|  1 -
 configs/evb-px30_defconfig|  1 -
 configs/evb-px5_defconfig |  1 -
 configs/evb-rk3308_defconfig  |  1 -
 configs/evb-rk3328_defconfig  |  1 -
 configs/evb-rk3568_defconfig  |  1 -
 configs/evb-rk3588_defconfig  |  1 -
 configs/evb-rv1108_defconfig  |  1 -
 configs/firefly-px30_defconfig|  1 -
 configs/geekbox_defconfig |  1 -
 configs/generic-rk3568_defconfig  |  1 -
 configs/generic-rk3588_defconfig  |  1 -
 configs/jaguar-rk3588_defconfig   |  1 -
 configs/lion-rk3368_defconfig |  1 -
 configs/lubancat-2-rk3568_defconfig   |  1 -
 configs/nanopc-t6-rk3588_defconfig|  1 -
 configs/nanopi-r2c-plus-rk3328_defconfig  |  1 -
 configs/nanopi-r2c-rk3328_defconfig   |  1 -
 configs/nanopi-r2s-rk3328_defconfig   |  1 -
 configs/nanopi-r5c-rk3568_defconfig   |  1

Re: [PATCH 2/2] rockchip: rk3588-edgeble: Add USB OTG support

[Anand Moon]

hi Jagan,

On Mon, 27 May 2024 at 12:09, Jagan Teki  wrote:
>
> Add support for USB OTG with UMS to program eMMC.
>
> Add it for Edgeble NCM6A, NCM6B.
>
> Signed-off-by: Jagan Teki 

Reviewed-by: Anand Moon 


> ---
>  .../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi| 18 ++
>  .../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi| 18 ++
>  configs/neu6a-io-rk3588_defconfig  |  9 +
>  configs/neu6b-io-rk3588_defconfig  |  9 +
>  4 files changed, 54 insertions(+)
>
> diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi 
> b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> index 88f3f7eee2..534d9f8a2c 100644
> --- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> @@ -15,3 +15,21 @@
> bus-width = <4>;
> status = "okay";
>  };
> +
> +&u2phy0 {
> +   status = "okay";
> +};
> +
> +&u2phy0_otg {
> +   status = "okay";
> +};
> +
> +&usbdp_phy0 {
> +   status = "okay";
> +};
> +
> +&usb_host0_xhci {
> +   dr_mode = "peripheral";
> +   maximum-speed = "high-speed";
> +   status = "okay";
> +};
> diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi 
> b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> index 289578803e..b3d17a60ce 100644
> --- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> @@ -15,3 +15,21 @@
> bus-width = <4>;
> status = "okay";
>  };
> +
> +&u2phy0 {
> +   status = "okay";
> +};
> +
> +&u2phy0_otg {
> +   status = "okay";
> +};
> +
> +&usbdp_phy0 {
> +   status = "okay";
> +};
> +
> +&usb_host0_xhci {
> +   dr_mode = "peripheral";
> +   maximum-speed = "high-speed";
> +   status = "okay";
> +};
> diff --git a/configs/neu6a-io-rk3588_defconfig 
> b/configs/neu6a-io-rk3588_defconfig
> index ac281e6539..6e50d06458 100644
> --- a/configs/neu6a-io-rk3588_defconfig
> +++ b/configs/neu6a-io-rk3588_defconfig
> @@ -24,6 +24,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
>  CONFIG_SPL_ATF=y
>  CONFIG_CMD_GPT=y
>  CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
>  # CONFIG_CMD_SETEXPR is not set
>  # CONFIG_SPL_DOS_PARTITION is not set
>  CONFIG_SPL_OF_CONTROL=y
> @@ -33,6 +34,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
>  CONFIG_SPL_REGMAP=y
>  CONFIG_SPL_SYSCON=y
>  CONFIG_SPL_CLK=y
> +# CONFIG_USB_FUNCTION_FASTBOOT is not set
>  CONFIG_ROCKCHIP_GPIO=y
>  CONFIG_SYS_I2C_ROCKCHIP=y
>  CONFIG_MISC=y
> @@ -42,6 +44,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
>  CONFIG_MMC_SDHCI=y
>  CONFIG_MMC_SDHCI_SDMA=y
>  CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_USBDP=y
>  CONFIG_SPL_PINCTRL=y
>  CONFIG_PWM_ROCKCHIP=y
>  CONFIG_SPL_RAM=y
> @@ -49,4 +53,9 @@ CONFIG_BAUDRATE=150
>  CONFIG_DEBUG_UART_SHIFT=2
>  CONFIG_SYS_NS16550_MEM32=y
>  CONFIG_SYSRESET=y
> +CONFIG_USB=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DOWNLOAD=y
>  CONFIG_ERRNO_STR=y
> diff --git a/configs/neu6b-io-rk3588_defconfig 
> b/configs/neu6b-io-rk3588_defconfig
> index c01e5fb0d0..f2eb650f19 100644
> --- a/configs/neu6b-io-rk3588_defconfig
> +++ b/configs/neu6b-io-rk3588_defconfig
> @@ -24,6 +24,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
>  CONFIG_SPL_ATF=y
>  CONFIG_CMD_GPT=y
>  CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
>  # CONFIG_CMD_SETEXPR is not set
>  # CONFIG_SPL_DOS_PARTITION is not set
>  CONFIG_SPL_OF_CONTROL=y
> @@ -33,6 +34,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
>  CONFIG_SPL_REGMAP=y
>  CONFIG_SPL_SYSCON=y
>  CONFIG_SPL_CLK=y
> +# CONFIG_USB_FUNCTION_FASTBOOT is not set
>  CONFIG_ROCKCHIP_GPIO=y
>  CONFIG_SYS_I2C_ROCKCHIP=y
>  CONFIG_MISC=y
> @@ -42,6 +44,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
>  CONFIG_MMC_SDHCI=y
>  CONFIG_MMC_SDHCI_SDMA=y
>  CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_USBDP=y
>  CONFIG_SPL_PINCTRL=y
>  CONFIG_PWM_ROCKCHIP=y
>  CONFIG_SPL_RAM=y
> @@ -49,4 +53,9 @@ CONFIG_BAUDRATE=150
>  CONFIG_DEBUG_UART_SHIFT=2
>  CONFIG_SYS_NS16550_MEM32=y
>  CONFIG_SYSRESET=y
> +CONFIG_USB=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DOWNLOAD=y
>  CONFIG_ERRNO_STR=y
> --
> 2.34.1
>

Re: [PATCH 1/2] arm64: dts: rockchip: Fix spl-boot-order for edgeble-ncm6b

[Anand Moon]

Hi Jagan,

On Mon, 27 May 2024 at 12:09, Jagan Teki  wrote:
>
> Edgeble NCM6B SoM has built-in eMMC so make sdhci has first boot
> priority.
>
> Fix it for NCM6A, NCM6B SoM.
>
> Signed-off-by: Jagan Teki 

Reviewed-by: Anand Moon 



> ---
>  arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi |  6 +-
>  arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 11 ++-
>  2 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi 
> b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> index dd0058262b..88f3f7eee2 100644
> --- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> @@ -6,12 +6,8 @@
>  #include "rk3588-u-boot.dtsi"
>
>  / {
> -   aliases {
> -   mmc0 = &sdmmc;
> -   };
> -
> chosen {
> -   u-boot,spl-boot-order = &sdmmc;
> +   u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
> };
>  };
>
> diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi 
> b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> index a45b3f5e86..289578803e 100644
> --- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
> @@ -6,11 +6,12 @@
>  #include "rk3588j-u-boot.dtsi"
>
>  / {
> -   aliases {
> -   mmc0 = &sdmmc;
> -   };
> -
> chosen {
> -   u-boot,spl-boot-order = &sdmmc;
> +   u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
> };
>  };
> +
> +&sdmmc {
> +   bus-width = <4>;
> +   status = "okay";
> +};
> --
> 2.34.1
>

Re: [PATCH v1 6/9] rockchip: RK3568: Read the reset cause from clock reset unit for RK356x SoC

[Anand Moon]

Hi Jonas,

On Fri, 17 May 2024 at 13:15, Anand Moon  wrote:
>
> Hi Jonas,
>
> Dropping @edgeble.ai email ID as it is not working
>
> On Thu, 16 May 2024 at 19:48, Jonas Karlman  wrote:
> >
> > Hi Anand,
> >
> > On 2024-05-16 10:59, Anand Moon wrote:
> > > Read the reset cause from the clock reset unit for RK356x SoC.
> > >
> > > Cc: Jagan Teki 
> > > Signed-off-by: Anand Moon 
> > > ---
> > >  arch/arm/mach-rockchip/cpu-info.c | 4 
> > >  1 file changed, 4 insertions(+)
> > >
> > > diff --git a/arch/arm/mach-rockchip/cpu-info.c 
> > > b/arch/arm/mach-rockchip/cpu-info.c
> > > index 77833c8fce..114608b506 100644
> > > --- a/arch/arm/mach-rockchip/cpu-info.c
> > > +++ b/arch/arm/mach-rockchip/cpu-info.c
> > > @@ -12,6 +12,8 @@
> > >  #include 
> > >  #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
> > >  #include 
> > > +#elif IS_ENABLED(CONFIG_ROCKCHIP_RK33568)
> > > +#include 
> > >  #endif
> > >  #include 
> > >  #include 
> > > @@ -22,6 +24,8 @@ char *get_reset_cause(void)
> > >   struct rk3328_cru *cru = rockchip_get_cru();
> > >  #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
> > >   struct rockchip_cru *cru = rockchip_get_cru();
> > > +#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3568)
> > > + struct rk3568_cru *cru = rockchip_get_cru();
> >
> > This is strictly not needed for RK3568 after the commit 6e710897aa31
> > ("rockchip: cru: Enable cpu info support for rk3568").
>
> Ok, thanks for this input.
> >
> > Suggest you use same/similar workaround or cleanup the include/define
> > statement in arch/arm/include/asm/arch-rockchip/cru.h for all SoCs.
> >

I have made changes for all the SoC that supports this reading of CRU
only build these SoCs,I don't have all the boards to test.

On rock64 with reboot command, it shows (RST)

U-Boot 2024.07-rc3-00021-gb23d5619e6-dirty (May 24 2024 - 12:55:26 +0530)

SoC: Rockchip rk3328
Reset cause: RST
Model: Pine64 Rock64

with poweroff command, it shows (POR)

U-Boot 2024.07-rc3-00021-gb23d5619e6-dirty (May 24 2024 - 12:55:26 +0530)

SoC: Rockchip rk3328
Reset cause: POR

> > Also at least one RK SoC have other bits set in the glb_rst_st reg.
> >
> > Suggest you add following:
> >
> >   GLB_RST_MASK  = GENMASK(5, 0),
> >
> > and use something like:
> >
> >   switch (cru->glb_rst_st & GLB_RST_MASK) {
> >
> > or "unknown reset" is reported on affected SoCs.
> >
> > I have also seen POR always being reported even after a reboot so please
> > confirm that reset reason works on the SoCs/boards you enable this on.
> >

Actually, for RK3568 and RK3688 SoC, we are not able to read the reset
cause via CRU
glb_rst_st is always set to zero.

Either the user space with poweroff and reboot command not updating the CRU
or the u-boot is not registering the sysreset to read the reset cause.

# dm tree
 clk   5  [ + ]   rockchip_rk3588_cru   |-- clock-controller@fd7c
 sysreset  0  [   ]   rockchip_sysreset |   |-- sysreset
 reset 0  [ + ]   rockchip_reset|   `-- reset

>
> Ok, I will check this and update you on this.
>

Thanks
-Anand

Re: [PATCH v1 6/9] rockchip: RK3568: Read the reset cause from clock reset unit for RK356x SoC

[Anand Moon]

Hi Jonas,

Dropping @edgeble.ai email ID as it is not working

On Thu, 16 May 2024 at 19:48, Jonas Karlman  wrote:
>
> Hi Anand,
>
> On 2024-05-16 10:59, Anand Moon wrote:
> > Read the reset cause from the clock reset unit for RK356x SoC.
> >
> > Cc: Jagan Teki 
> > Signed-off-by: Anand Moon 
> > ---
> >  arch/arm/mach-rockchip/cpu-info.c | 4 
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/mach-rockchip/cpu-info.c 
> > b/arch/arm/mach-rockchip/cpu-info.c
> > index 77833c8fce..114608b506 100644
> > --- a/arch/arm/mach-rockchip/cpu-info.c
> > +++ b/arch/arm/mach-rockchip/cpu-info.c
> > @@ -12,6 +12,8 @@
> >  #include 
> >  #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
> >  #include 
> > +#elif IS_ENABLED(CONFIG_ROCKCHIP_RK33568)
> > +#include 
> >  #endif
> >  #include 
> >  #include 
> > @@ -22,6 +24,8 @@ char *get_reset_cause(void)
> >   struct rk3328_cru *cru = rockchip_get_cru();
> >  #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
> >   struct rockchip_cru *cru = rockchip_get_cru();
> > +#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3568)
> > + struct rk3568_cru *cru = rockchip_get_cru();
>
> This is strictly not needed for RK3568 after the commit 6e710897aa31
> ("rockchip: cru: Enable cpu info support for rk3568").

Ok, thanks for this input.
>
> Suggest you use same/similar workaround or cleanup the include/define
> statement in arch/arm/include/asm/arch-rockchip/cru.h for all SoCs.
>
> Also at least one RK SoC have other bits set in the glb_rst_st reg.
>
> Suggest you add following:
>
>   GLB_RST_MASK  = GENMASK(5, 0),
>
> and use something like:
>
>   switch (cru->glb_rst_st & GLB_RST_MASK) {
>
> or "unknown reset" is reported on affected SoCs.
>
> I have also seen POR always being reported even after a reboot so please
> confirm that reset reason works on the SoCs/boards you enable this on.
>

Ok, I will check this and update you on this.

> Regards,
> Jonas
>
Thanks
-Anand

[PATCH v1 9/9] rockchip: RK3588: Enable display cpuinfo support on all boards

[Anand Moon]

Imply DISPLAY_CPUINFO Kconfig options to support on all RK3588s and
RK3588 boards, Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/Kconfig   | 1 +
 configs/coolpi-4b-rk3588s_defconfig  | 1 -
 configs/coolpi-cm5-evb-rk3588_defconfig  | 1 -
 configs/evb-rk3588_defconfig | 1 -
 configs/generic-rk3588_defconfig | 1 -
 configs/jaguar-rk3588_defconfig  | 1 -
 configs/nanopc-t6-rk3588_defconfig   | 1 -
 configs/neu6a-io-rk3588_defconfig| 1 -
 configs/neu6b-io-rk3588_defconfig| 1 -
 configs/orangepi-5-plus-rk3588_defconfig | 1 -
 configs/orangepi-5-rk3588s_defconfig | 1 -
 configs/quartzpro64-rk3588_defconfig | 1 -
 configs/rock5a-rk3588s_defconfig | 1 -
 configs/rock5b-rk3588_defconfig  | 1 -
 configs/toybrick-rk3588_defconfig| 1 -
 configs/turing-rk1-rk3588_defconfig  | 1 -
 16 files changed, 1 insertion(+), 15 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 2e9c71138e..1b5cc34f99 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -366,6 +366,7 @@ config ROCKCHIP_RK3588
imply SCMI_FIRMWARE
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+   imply DISPLAY_CPUINFO
help
  The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
  quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
diff --git a/configs/coolpi-4b-rk3588s_defconfig 
b/configs/coolpi-4b-rk3588s_defconfig
index 3d45d939ab..b094224f6e 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig 
b/configs/coolpi-cm5-evb-rk3588_defconfig
index 5190d69c1c..382ee97fc9 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 1d5585677a..bfc505a4b7 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
index 42bc2c9a76..ddb23b035b 100644
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index b69cf4cd05..712a936539 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -22,7 +22,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CYCLIC=y
 CONFIG_SPL_MAX_SIZE=0x4
diff --git a/configs/nanopc-t6-rk3588_defconfig 
b/configs/nanopc-t6-rk3588_defconfig
index 926267f93a..978c62aee6 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/neu6a-io-rk3588_defconfig 
b/configs/neu6a-io-rk3588_defconfig
index ac281e6539..6f2765c640 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_

[PATCH v1 8/9] rockchip: RK3588: Read the reset cause from clock reset unit for RK3588 SoC

[Anand Moon]

Read the reset cause from clock reset unit for RK3588 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/cpu-info.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index 114608b506..8415009fc5 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -14,6 +14,8 @@
 #include 
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK33568)
 #include 
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3588)
+#include 
 #endif
 #include 
 #include 
@@ -26,6 +28,8 @@ char *get_reset_cause(void)
struct rockchip_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3568)
struct rk3568_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3588)
+   struct rk3588_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.45.0

[PATCH v1 7/9] rockchip: RK356x: Enable display cpuinfo support on all boards

[Anand Moon]

Imply DISPLAY_CPUINFO Kconfig options to support on all RK3566 and
RK3568 boards, Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/Kconfig| 1 +
 configs/anbernic-rgxx3-rk3566_defconfig   | 1 -
 configs/bpi-r2-pro-rk3568_defconfig   | 1 -
 configs/evb-rk3568_defconfig  | 1 -
 configs/generic-rk3568_defconfig  | 1 -
 configs/lubancat-2-rk3568_defconfig   | 1 -
 configs/nanopi-r5c-rk3568_defconfig   | 1 -
 configs/nanopi-r5s-rk3568_defconfig   | 1 -
 configs/odroid-m1-rk3568_defconfig| 1 -
 configs/pinetab2-rk3566_defconfig | 1 -
 configs/quartz64-a-rk3566_defconfig   | 1 -
 configs/quartz64-b-rk3566_defconfig   | 1 -
 configs/radxa-cm3-io-rk3566_defconfig | 1 -
 configs/radxa-e25-rk3568_defconfig| 1 -
 configs/rock-3a-rk3568_defconfig  | 1 -
 configs/soquartz-blade-rk3566_defconfig   | 1 -
 configs/soquartz-cm4-rk3566_defconfig | 1 -
 configs/soquartz-model-a-rk3566_defconfig | 1 -
 18 files changed, 1 insertion(+), 17 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 1fd482e43b..2e9c71138e 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -331,6 +331,7 @@ config ROCKCHIP_RK3568
imply ROCKCHIP_OTP
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+   imply DISPLAY_CPUINFO
help
  The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
  including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
diff --git a/configs/anbernic-rgxx3-rk3566_defconfig 
b/configs/anbernic-rgxx3-rk3566_defconfig
index a03509bf46..95f7cf0739 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -21,7 +21,6 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_RNG_SEED=y
 CONFIG_SPL_MAX_SIZE=0x4
diff --git a/configs/bpi-r2-pro-rk3568_defconfig 
b/configs/bpi-r2-pro-rk3568_defconfig
index eccc15a0ae..4955fd907c 100644
--- a/configs/bpi-r2-pro-rk3568_defconfig
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 2076f55122..e6da8fd246 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index 66a33afbba..ba2d995cdc 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/lubancat-2-rk3568_defconfig 
b/configs/lubancat-2-rk3568_defconfig
index 88593bfa70..384d0ecfc5 100644
--- a/configs/lubancat-2-rk3568_defconfig
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r5c-rk3568_defconfig 
b/configs/nanopi-r5c-rk3568_defconfig
index 4a6c320faf..b83796083d 100644
--- a/configs/nanopi-r5c-rk3568_defconfig
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r5s-rk3568_defconfig 
b/configs/nanopi-r5s-rk3568_defconfig
index 7ab12e619a..5d500963a2 100644
--- a/configs/nanopi-r5s-rk3568_defconfig
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMA

[PATCH v1 6/9] rockchip: RK3568: Read the reset cause from clock reset unit for RK356x SoC

[Anand Moon]

Read the reset cause from clock reset unit for RK356x SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/cpu-info.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index 77833c8fce..114608b506 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -12,6 +12,8 @@
 #include 
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
 #include 
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK33568)
+#include 
 #endif
 #include 
 #include 
@@ -22,6 +24,8 @@ char *get_reset_cause(void)
struct rk3328_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
struct rockchip_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3568)
+   struct rk3568_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.45.0

[PATCH v1 5/9] arm: rockchip: Enable display cpuinfo to be build with SPL_BUILD

[Anand Moon]

Changes help enable CONFIG_DISPLAY_CPUINFO to build with SPL_BUILD for
SoC RK356x and RK3588.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c07bdaee4c..6722e7c9ea 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -25,7 +25,7 @@ obj-y += boot_mode.o
 obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
 endif
 
-ifeq ($(CONFIG_TPL_BUILD),)
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
 endif
 
-- 
2.45.0

[PATCH v1 4/9] rockchip: RK3399: Enable display cpuinfo support on all boards

[Anand Moon]

Imply DISPLAY_CPUINFO Kconfig options to support on all RK3399
boards, Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/Kconfig | 1 +
 configs/chromebook_bob_defconfig   | 1 -
 configs/chromebook_kevin_defconfig | 1 -
 3 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ba1474bb9e..1fd482e43b 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -297,6 +297,7 @@ config ROCKCHIP_RK3399
imply TPL_SYS_MALLOC_SIMPLE
imply TPL_SYSCON
imply TPL_TINY_MEMSET
+   imply DISPLAY_CPUINFO
help
  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
  and quad-core Cortex-A53.
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index acfe393410..2c1a8141c0 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -30,7 +30,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 # CONFIG_SPL_FIT_SIGNATURE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BLOBLIST=y
diff --git a/configs/chromebook_kevin_defconfig 
b/configs/chromebook_kevin_defconfig
index 95fdb418d8..f6649804c7 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -31,7 +31,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 # CONFIG_SPL_FIT_SIGNATURE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BLOBLIST=y
-- 
2.45.0

[PATCH v1 3/9] rockchip: RK3399: Read the reset cause from clock reset unit for RK3399 SoC

[Anand Moon]

Read the reset cause from clock reset unit for RK3399 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/cpu-info.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index fce4bd7541..77833c8fce 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -10,6 +10,8 @@
 #include 
 #if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
 #include 
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
+#include 
 #endif
 #include 
 #include 
@@ -18,6 +20,8 @@ char *get_reset_cause(void)
 {
 #if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
struct rk3328_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
+   struct rockchip_cru *cru = rockchip_get_cru();
 #endif
char *cause = NULL;
 
-- 
2.45.0

[PATCH v1 2/9] rockchip: RK3328: Enable display cpuinfo support on all boards

[Anand Moon]

Imply DISPLAY_CPUINFO Kconfig options to support on all RK3328
boards, Its used to determine the reset cause of the board.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/Kconfig| 1 +
 configs/evb-rk3328_defconfig  | 1 -
 configs/nanopi-r2c-plus-rk3328_defconfig  | 1 -
 configs/nanopi-r2c-rk3328_defconfig   | 1 -
 configs/nanopi-r2s-rk3328_defconfig   | 1 -
 configs/orangepi-r1-plus-lts-rk3328_defconfig | 1 -
 configs/orangepi-r1-plus-rk3328_defconfig | 1 -
 configs/roc-cc-rk3328_defconfig   | 1 -
 configs/rock-pi-e-rk3328_defconfig| 1 -
 configs/rock64-rk3328_defconfig   | 1 -
 10 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ec3697f358..ba1474bb9e 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -206,6 +206,7 @@ config ROCKCHIP_RK3328
imply SPL_SEPARATE_BSS
imply SPL_SERIAL
imply TPL_SERIAL
+   imply DISPLAY_CPUINFO
help
  The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index bfb8522343..e1c2016cb3 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig 
b/configs/nanopi-r2c-plus-rk3328_defconfig
index f311a0a80b..700ce47696 100644
--- a/configs/nanopi-r2c-plus-rk3328_defconfig
+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r2c-rk3328_defconfig 
b/configs/nanopi-r2c-rk3328_defconfig
index 533dc1029f..a594f329bf 100644
--- a/configs/nanopi-r2c-rk3328_defconfig
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r2s-rk3328_defconfig 
b/configs/nanopi-r2s-rk3328_defconfig
index 2591a9cc8a..c1d0a1f396 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig 
b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index 14cdbd813c..7e0b1b2773 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig 
b/configs/orangepi-r1-plus-rk3328_defconfig
index 7fe58e7a14..4525c99ca2 100644
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 91b9422e26..c1eb03c5e8 100644
--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/rock-pi-e-rk3328_defconfig 
b/configs/rock-pi-e-rk3328_defconfig
index 5cc54af3ca..bb99670b8c 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/r

[PATCH v1 1/9] rockchip: RK3328: Read the reset cause from clock reset unit for RK3328 SoC

[Anand Moon]

Read the reset cause from clock reset unit for RK3328 SoC.

Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
 arch/arm/mach-rockchip/cpu-info.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/cpu-info.c 
b/arch/arm/mach-rockchip/cpu-info.c
index 14c7331e1a..fce4bd7541 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -8,12 +8,17 @@
 #include 
 #include 
 #include 
+#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
+#include 
+#endif
 #include 
 #include 
 
 char *get_reset_cause(void)
 {
-   struct rockchip_cru *cru = rockchip_get_cru();
+#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
+   struct rk3328_cru *cru = rockchip_get_cru();
+#endif
char *cause = NULL;
 
if (IS_ERR(cru))
-- 
2.45.0

Re: [PATCH v1 9/9] rockchip: RK3588: Enable display cpuinfo support on all boards

[Anand Moon]

Hi Quentin

On Thu, 16 May 2024 at 16:13, Quentin Schulz  wrote:
>
> Hi Anand,
>
> On 5/16/24 12:12 PM, Anand Moon wrote:
> > Hi Quentin
> >
> > On Thu, 16 May 2024 at 14:52, Quentin Schulz  
> > wrote:
> >>
> >> Hi Anand,
> >>
> >> This is patch 9/9 but somehow I didn't receive any other patch, nor did
> >> the mailing list? c.f.
> >> https://lists.denx.de/pipermail/u-boot/2024-May/thread.html and
> >> https://lore.kernel.org/u-boot/. Are you registered on the ML?
> >>
> >
> > Thanks for your  review comments.
> >
> > Something went wrong with git sendmail,
> > Your message have not reached my email client (gmail)
> >
>
> A mail server rejected the mail to edgeble.ai domain (both you and
> Jagan) /me shrugs.
>

Yeah, something went wrong. It's Gmail server or u-boot mail server blocked
I don't know the reason for this.

Remove me and Jagan (edgeble.ai) for now as of now.

> >> On 5/16/24 10:59 AM, Anand Moon wrote:
> >>> Imply DISPLAY_CPUINFO Kconfig options to support on all RK3588s and
> >>> RK3588 boards, Its used to determine the reset cause of the board.
> >>>
> >>> diff --git a/arch/arm/mach-rockchip/Kconfig 
> >>> b/arch/arm/mach-rockchip/Kconfig
> >>> index 2e9c71138e..1b5cc34f99 100644
> >>> --- a/arch/arm/mach-rockchip/Kconfig
> >>> +++ b/arch/arm/mach-rockchip/Kconfig
> >>> @@ -366,6 +366,7 @@ config ROCKCHIP_RK3588
> >>>imply SCMI_FIRMWARE
> >>>imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
> >>>imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
> >>> + imply DISPLAY_CPUINFO
> >>
> >> This is unnecessary, it's already defaulting to y if building for ARM
> >> boards: https://elixir.bootlin.com/u-boot/latest/source/common/Kconfig#L596
> >>
> > See below...
> >> I also don't think this is SO useful that we need to enable it on all
> >> rk3588 boards? But also, doesn't hurt, so... whatever I guess :) ?
> >>
> >> While looking at the code, I think we can remove the ifdef in
> >> https://elixir.bootlin.com/u-boot/latest/source/arch/arm/mach-rockchip/cpu-info.c#L47
> >> because this file is anyway only compiled when CONFIG_DISPLAY_CPUINFO is
> >> set, c.f.
> >
> > Oops I missed this changes, my bad
> > I will dop my changes over here.
> >
> >> https://elixir.bootlin.com/u-boot/latest/source/arch/arm/mach-rockchip/Makefile#L30
> >>
> > On Rockchip SoC CONFIG_DISPLAY_CPUINFO is been disable on most of the
> > configs files.
> >
> > -# CONFIG_DISPLAY_CPUINFO is not set
> >
> > My changes are related to determine the reset cause of the board and
> > display the results.
> > its only enable on selected SoC hence I have to used this logic.
> >
>
> It's enabled for all Aarch64/Aarch32 SoCs by default. People explicitly
> disabled them in their own defconfig, either because the first person
> who added a board based on rk3588 didn't know or didn't care and
> everybody just copied it as a base, or because they don't care about
> it/don't want it.
>
My series focuses on determining the reset cause of the boards
Do we need to enable this feature ?

We are not compiling DISPLAY_CPUINFO for all for RK3568 and RK3588
But with the following changes enable this to be built for SPL_BUILD ( patch v5)
in this series. wow it is built for all SoC.

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c07bdaee4c..6722e7c9ea 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -25,7 +25,7 @@ obj-y += boot_mode.o
 obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
 endif

-ifeq ($(CONFIG_TPL_BUILD),)
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
 endif

> In any case, you only need to change the defconfigs, nothing else.
>
> > U-Boot 2024.07-rc2-00397-g0370324feb-dirty (May 16 2024 - 13:11:14 +0530)
> >
> > SoC: Rockchip rk3568
> > Reset cause: POR <---
> > Model: Radxa ROCK3 Model A
> > DRAM:  8 GiB (effective 7.7 GiB)
> > PMIC:  RK8090 (on=0x40, off=0x00)
> > Core:  344 devices, 31 uclasses,
> >  >> which also means...
> >>
> >> https://elixir.bootlin.com/u-boot/latest/source/arch/arm/include/asm/arch-rockchip/cru.h#L35
> >> should probably be ifdef'ed
> >>
> >> which means...
> >>
> >> https://elixir.bootlin.com/u-boot/latest/source/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c#L64
> >> should probably also be ifdef'ed (but the config is enabled already
> >> (well... it wouldn't compile otherwsie), so I guess this is fine?).
> >
> > This code changes will not affect this feature by default its enable
> > on RK3399 boards.
> >
>
> Yes, but if you disable it, it won't compile anymore. (I'm not asking
> you to fix anything I've reported here though).
>
Ok I will check this.
> Cheers,
> Quentin
Thanks
-Anand

Re: [PATCH v1 9/9] rockchip: RK3588: Enable display cpuinfo support on all boards

[Anand Moon]

Hi Quentin

On Thu, 16 May 2024 at 14:52, Quentin Schulz  wrote:
>
> Hi Anand,
>
> This is patch 9/9 but somehow I didn't receive any other patch, nor did
> the mailing list? c.f.
> https://lists.denx.de/pipermail/u-boot/2024-May/thread.html and
> https://lore.kernel.org/u-boot/. Are you registered on the ML?
>

Thanks for your  review comments.

Something went wrong with git sendmail,
Your message have not reached my email client (gmail)

> On 5/16/24 10:59 AM, Anand Moon wrote:
> > Imply DISPLAY_CPUINFO Kconfig options to support on all RK3588s and
> > RK3588 boards, Its used to determine the reset cause of the board.
> >
> > Cc: Jagan Teki 
> > Signed-off-by: Anand Moon 
> > ---
> >   arch/arm/mach-rockchip/Kconfig   | 1 +
> >   configs/coolpi-4b-rk3588s_defconfig  | 1 -
> >   configs/coolpi-cm5-evb-rk3588_defconfig  | 1 -
> >   configs/evb-rk3588_defconfig | 1 -
> >   configs/generic-rk3588_defconfig | 1 -
> >   configs/jaguar-rk3588_defconfig  | 1 -
> >   configs/nanopc-t6-rk3588_defconfig   | 1 -
> >   configs/neu6a-io-rk3588_defconfig| 1 -
> >   configs/neu6b-io-rk3588_defconfig| 1 -
> >   configs/orangepi-5-plus-rk3588_defconfig | 1 -
> >   configs/orangepi-5-rk3588s_defconfig | 1 -
> >   configs/quartzpro64-rk3588_defconfig | 1 -
> >   configs/rock5a-rk3588s_defconfig | 1 -
> >   configs/rock5b-rk3588_defconfig  | 1 -
> >   configs/toybrick-rk3588_defconfig| 1 -
> >   configs/turing-rk1-rk3588_defconfig  | 1 -
> >   16 files changed, 1 insertion(+), 15 deletions(-)
> >
> > diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> > index 2e9c71138e..1b5cc34f99 100644
> > --- a/arch/arm/mach-rockchip/Kconfig
> > +++ b/arch/arm/mach-rockchip/Kconfig
> > @@ -366,6 +366,7 @@ config ROCKCHIP_RK3588
> >   imply SCMI_FIRMWARE
> >   imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
> >   imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
> > + imply DISPLAY_CPUINFO
>
> This is unnecessary, it's already defaulting to y if building for ARM
> boards: https://elixir.bootlin.com/u-boot/latest/source/common/Kconfig#L596
>
See below...
> I also don't think this is SO useful that we need to enable it on all
> rk3588 boards? But also, doesn't hurt, so... whatever I guess :) ?
>
> While looking at the code, I think we can remove the ifdef in
> https://elixir.bootlin.com/u-boot/latest/source/arch/arm/mach-rockchip/cpu-info.c#L47
> because this file is anyway only compiled when CONFIG_DISPLAY_CPUINFO is
> set, c.f.

Oops I missed this changes, my bad
I will dop my changes over here.

> https://elixir.bootlin.com/u-boot/latest/source/arch/arm/mach-rockchip/Makefile#L30
>
On Rockchip SoC CONFIG_DISPLAY_CPUINFO is been disable on most of the
configs files.

-# CONFIG_DISPLAY_CPUINFO is not set

My changes are related to determine the reset cause of the board and
display the results.
its only enable on selected SoC hence I have to used this logic.

U-Boot 2024.07-rc2-00397-g0370324feb-dirty (May 16 2024 - 13:11:14 +0530)

SoC: Rockchip rk3568
Reset cause: POR <---
Model: Radxa ROCK3 Model A
DRAM:  8 GiB (effective 7.7 GiB)
PMIC:  RK8090 (on=0x40, off=0x00)
Core:  344 devices, 31 uclasses,

> which also means...
>
> https://elixir.bootlin.com/u-boot/latest/source/arch/arm/include/asm/arch-rockchip/cru.h#L35
> should probably be ifdef'ed
>
> which means...
>
> https://elixir.bootlin.com/u-boot/latest/source/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c#L64
> should probably also be ifdef'ed (but the config is enabled already
> (well... it wouldn't compile otherwsie), so I guess this is fine?).

This code changes will not affect this feature by default its enable
on RK3399 boards.

>
> Cheers,
> Quentin

Thanks

-Anand

Re: [PATCH v3] rockchip: rv1126: Migrate to OF_UPSTREAM

[Anand Moon]

Hi Quentin

On Tue, 14 May 2024 at 00:01, Quentin Schulz  wrote:
>
> Hi Anand,
>
> On 5/13/24 2:07 PM, Anand Moon wrote:
> > [You don't often get email from an...@edgeble.ai. Learn why this is 
> > important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > Hi Quentin,
> >
> > On Mon, 13 May 2024 at 16:10, Quentin Schulz  
> > wrote:
> >>
> >> Hi Anand,
> >>
> >> On 5/11/24 6:12 PM, Anand Moon wrote:
> >>> [You don't often get email from an...@edgeble.ai. Learn why this is 
> >>> important at https://aka.ms/LearnAboutSenderIdentification ]
> >>>
> >>> Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.
> >>>
> >>> Following targets is migrated to use OF_UPSTREAM:
> >>>
> >>> - rv1126-edgeble-neu2 : Board is an industrial form factor
> >>>   IO board.
> >>> - sonoff-ihost-rv1126 : Gateway device designed to provide a
> >>>   Smart Home Hub.
> >>>
> >>> Cc: Tim Lunn 
> >>> Cc: Jagan Teki 
> >>> Reviewed-By: Tim Lunn 
> >>> Tested-By: Tim Lunn 
> >>> Reviewed-by: Kever Yang 
> >>> Signed-off-by: Anand Moon 
> >>
> >> Doesn't match the mail address sending this patch :)
> >>
> > Earlier I sent this patch with my email ID,
> > Since I am testing these new boards,
> > I will use this edgable.ai email ID for source code changes to boards.
> > if needed I could send this with From: Anand Moon 
> >
>
> Up to you, it is just particularly odd that there's only one letter
> difference between those two mail addresses, which very much looks like
> a typo:
> edgeble.ai and
> edgable.ai
>
> But if this was on purpose, nothing against it :)
>
> (I made a similar typo in a kernel patch recently, hence why I brought
> this up :) )
>
Thanks, I will take care in the future.

> Cheers,
> Quentin

Thanks
-Anand

[PATCH v4] rockchip: rv1126: Migrate to OF_UPSTREAM

[Anand Moon]

From: Anand Moon 

Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.

Following targets is migrated to use OF_UPSTREAM:

- rv1126-edgeble-neu2 : Board is an industrial form factor
IO board.
- sonoff-ihost-rv1126 : Gateway device designed to provide a
Smart Home Hub.

Cc: Tim Lunn 
Cc: Jagan Teki 
Reviewed-By: Tim Lunn 
Tested-By: Tim Lunn 
Reviewed-by: Kever Yang 
Signed-off-by: Anand Moon 
Signed-off-by: Anand Moon 
---
v4: re-submited wit modified From tag
fix the typo in the signed-off

v3: change the Signed off to edgeble id.
collcted Reviewd-By and Tested-By

v2: remove the dt-bindings for clock and power
fix the typo in commit message
---
 arch/arm/dts/Makefile |   3 -
 arch/arm/dts/rv1126-edgeble-neu2-io.dts   | 112 
 arch/arm/dts/rv1126-edgeble-neu2.dtsi | 345 --
 arch/arm/dts/rv1126-pinctrl.dtsi  | 341 --
 arch/arm/dts/rv1126-sonoff-ihost.dts  |  29 -
 arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 ---
 arch/arm/dts/rv1126.dtsi  | 623 -
 arch/arm/mach-rockchip/Kconfig|   1 +
 configs/neu2-io-rv1126_defconfig  |   2 +-
 configs/sonoff-ihost-rv1126_defconfig |   2 +-
 .../dt-bindings/clock/rockchip,rv1126-cru.h   | 632 --
 .../dt-bindings/power/rockchip,rv1126-power.h |  35 -
 12 files changed, 3 insertions(+), 2526 deletions(-)
 delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts
 delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2.dtsi
 delete mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
 delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
 delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
 delete mode 100644 arch/arm/dts/rv1126.dtsi
 delete mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h
 delete mode 100644 include/dt-bindings/power/rockchip,rv1126-power.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a5c82ebf7a..f77a80b7dd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,9 +97,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
 
-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
-   rv1126-edgeble-neu2-io.dtb
-
 dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
 
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts 
b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
deleted file mode 100644
index 0c2396b8f8..00
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
-   model = "Edgeble Neu2 IO Board";
-   compatible = "edgeble,neural-compute-module-2-io",
-"edgeble,neural-compute-module-2", "rockchip,rv1126";
-
-   aliases {
-   serial2 = &uart2;
-   };
-
-   chosen {
-   stdout-path = "serial2:150n8";
-   };
-
-   vcc12v_dcin: vcc12v-dcin-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc12v_dcin";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <1200>;
-   regulator-max-microvolt = <1200>;
-   };
-
-   vcc5v0_sys: vcc5v0-sys-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc5v0_sys";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <500>;
-   regulator-max-microvolt = <500>;
-   vin-supply = <&vcc12v_dcin>;
-   };
-
-   v3v3_sys: v3v3-sys-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "v3v3_sys";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <330>;
-   regulator-max-microvolt = <330>;
-   vin-supply = <&vcc5v0_sys>;
-   };
-};
-
-&gmac {
-   assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_ETHERNET_OUT>;
-   assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
-   assigned-clock-rates = <12500>, <0>, <2500>;
-   clock_in_out = "input";
-   phy-handle = <&phy>;
-   phy-mode = "rgmii";
-   phy-supply = <&vcc_3v3>;
- 

Re: [PATCH v3] rockchip: rv1126: Migrate to OF_UPSTREAM

[Anand Moon]

Hi Quentin,

On Mon, 13 May 2024 at 16:10, Quentin Schulz  wrote:
>
> Hi Anand,
>
> On 5/11/24 6:12 PM, Anand Moon wrote:
> > [You don't often get email from an...@edgeble.ai. Learn why this is 
> > important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.
> >
> > Following targets is migrated to use OF_UPSTREAM:
> >
> > - rv1126-edgeble-neu2 : Board is an industrial form factor
> >  IO board.
> > - sonoff-ihost-rv1126 : Gateway device designed to provide a
> >  Smart Home Hub.
> >
> > Cc: Tim Lunn 
> > Cc: Jagan Teki 
> > Reviewed-By: Tim Lunn 
> > Tested-By: Tim Lunn 
> > Reviewed-by: Kever Yang 
> > Signed-off-by: Anand Moon 
>
> Doesn't match the mail address sending this patch :)
>
Earlier I sent this patch with my email ID,
Since I am testing these new boards,
I will use this edgable.ai email ID for source code changes to boards.
if needed I could send this with From: Anand Moon 

> Cheers,
> Quentin

Thanks
-Anand

[PATCH v3] rockchip: rv1126: Migrate to OF_UPSTREAM

[Anand Moon]

Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.

Following targets is migrated to use OF_UPSTREAM:

- rv1126-edgeble-neu2 : Board is an industrial form factor
IO board.
- sonoff-ihost-rv1126 : Gateway device designed to provide a
Smart Home Hub.

Cc: Tim Lunn 
Cc: Jagan Teki 
Reviewed-By: Tim Lunn 
Tested-By: Tim Lunn 
Reviewed-by: Kever Yang 
Signed-off-by: Anand Moon 
---
v3: change the Signed off to edgeble id.
collcted Reviewd-By and Tested-By

v2: remove the dt-bindings for clock and power
fix the typo in commit message
---
 arch/arm/dts/Makefile |   3 -
 arch/arm/dts/rv1126-edgeble-neu2-io.dts   | 112 
 arch/arm/dts/rv1126-edgeble-neu2.dtsi | 345 --
 arch/arm/dts/rv1126-pinctrl.dtsi  | 341 --
 arch/arm/dts/rv1126-sonoff-ihost.dts  |  29 -
 arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 ---
 arch/arm/dts/rv1126.dtsi  | 623 -
 arch/arm/mach-rockchip/Kconfig|   1 +
 configs/neu2-io-rv1126_defconfig  |   2 +-
 configs/sonoff-ihost-rv1126_defconfig |   2 +-
 .../dt-bindings/clock/rockchip,rv1126-cru.h   | 632 --
 .../dt-bindings/power/rockchip,rv1126-power.h |  35 -
 12 files changed, 3 insertions(+), 2526 deletions(-)
 delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts
 delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2.dtsi
 delete mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
 delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
 delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
 delete mode 100644 arch/arm/dts/rv1126.dtsi
 delete mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h
 delete mode 100644 include/dt-bindings/power/rockchip,rv1126-power.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 087645f354..79fc100dce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,9 +97,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
 
-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
-   rv1126-edgeble-neu2-io.dtb
-
 dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
 
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts 
b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
deleted file mode 100644
index 0c2396b8f8..00
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
-   model = "Edgeble Neu2 IO Board";
-   compatible = "edgeble,neural-compute-module-2-io",
-"edgeble,neural-compute-module-2", "rockchip,rv1126";
-
-   aliases {
-   serial2 = &uart2;
-   };
-
-   chosen {
-   stdout-path = "serial2:150n8";
-   };
-
-   vcc12v_dcin: vcc12v-dcin-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc12v_dcin";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <1200>;
-   regulator-max-microvolt = <1200>;
-   };
-
-   vcc5v0_sys: vcc5v0-sys-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc5v0_sys";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <500>;
-   regulator-max-microvolt = <500>;
-   vin-supply = <&vcc12v_dcin>;
-   };
-
-   v3v3_sys: v3v3-sys-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "v3v3_sys";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <330>;
-   regulator-max-microvolt = <330>;
-   vin-supply = <&vcc5v0_sys>;
-   };
-};
-
-&gmac {
-   assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_ETHERNET_OUT>;
-   assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
-   assigned-clock-rates = <12500>, <0>, <2500>;
-   clock_in_out = "input";
-   phy-handle = <&phy>;
-   phy-mode = "rgmii";
-   phy-supply = <&vcc_3v3>;
-   pinctrl-names = "default";
-   pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 
&clk_out_ethernetm1_pins>;
-

Re: [PATCH v2] rockchip: rv1126: Migrate to OF_UPSTREAM

[Anand Moon]

Hi Kever,

On Sat, 11 May 2024 at 12:09, Kever Yang  wrote:
>
>
> On 2024/5/10 12:43, Anand Moon wrote:
> > Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.
> >
> > Following targets is migrated to use OF_UPSTREAM:
> >
> > - rv1126-edgeble-neu2 : Board is an industrial form factor
> >  IO board.
> > - sonoff-ihost-rv1126 : Gateway device designed to provide a
> >  Smart Home Hub.
> >
> > Cc: Tim Lunn 
> > Cc: Jagan Teki 
> > Signed-off-by: Anand Moon 
> Reviewed-by: Kever Yang 
>
It looks like I have used the my personal Signed-off-by
send v3 with correct Signed-off-by with edegeble.ai id.
can you apply the modified patch?

> Thanks,
> - Kever

Thanks
-Anand

[PATCH v2] rockchip: rv1126: Migrate to OF_UPSTREAM

[Anand Moon]

Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.

Following targets is migrated to use OF_UPSTREAM:

- rv1126-edgeble-neu2 : Board is an industrial form factor
IO board.
- sonoff-ihost-rv1126 : Gateway device designed to provide a
Smart Home Hub.

Cc: Tim Lunn 
Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
v2: remove the dt-bindings for clock and power
fix the typo in commit message

Tested on neu2 board.
---
 arch/arm/dts/Makefile |   3 -
 arch/arm/dts/rv1126-edgeble-neu2-io.dts   | 112 
 arch/arm/dts/rv1126-edgeble-neu2.dtsi | 345 --
 arch/arm/dts/rv1126-pinctrl.dtsi  | 341 --
 arch/arm/dts/rv1126-sonoff-ihost.dts  |  29 -
 arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 ---
 arch/arm/dts/rv1126.dtsi  | 623 -
 arch/arm/mach-rockchip/Kconfig|   1 +
 configs/neu2-io-rv1126_defconfig  |   2 +-
 configs/sonoff-ihost-rv1126_defconfig |   2 +-
 .../dt-bindings/clock/rockchip,rv1126-cru.h   | 632 --
 .../dt-bindings/power/rockchip,rv1126-power.h |  35 -
 12 files changed, 3 insertions(+), 2526 deletions(-)
 delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts
 delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2.dtsi
 delete mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
 delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
 delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
 delete mode 100644 arch/arm/dts/rv1126.dtsi
 delete mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h
 delete mode 100644 include/dt-bindings/power/rockchip,rv1126-power.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 087645f354..79fc100dce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,9 +97,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
 
-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
-   rv1126-edgeble-neu2-io.dtb
-
 dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
 
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts 
b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
deleted file mode 100644
index 0c2396b8f8..00
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
-   model = "Edgeble Neu2 IO Board";
-   compatible = "edgeble,neural-compute-module-2-io",
-"edgeble,neural-compute-module-2", "rockchip,rv1126";
-
-   aliases {
-   serial2 = &uart2;
-   };
-
-   chosen {
-   stdout-path = "serial2:150n8";
-   };
-
-   vcc12v_dcin: vcc12v-dcin-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc12v_dcin";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <1200>;
-   regulator-max-microvolt = <1200>;
-   };
-
-   vcc5v0_sys: vcc5v0-sys-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc5v0_sys";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <500>;
-   regulator-max-microvolt = <500>;
-   vin-supply = <&vcc12v_dcin>;
-   };
-
-   v3v3_sys: v3v3-sys-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "v3v3_sys";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <330>;
-   regulator-max-microvolt = <330>;
-   vin-supply = <&vcc5v0_sys>;
-   };
-};
-
-&gmac {
-   assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_ETHERNET_OUT>;
-   assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
-   assigned-clock-rates = <12500>, <0>, <2500>;
-   clock_in_out = "input";
-   phy-handle = <&phy>;
-   phy-mode = "rgmii";
-   phy-supply = <&vcc_3v3>;
-   pinctrl-names = "default";
-   pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 
&clk_out_ethernetm1_pins>;
-   tx_delay = <0x2a>;
-   rx_delay = <0x1a>;
-   status = "okay";
-};

Re: [PATCH v1] rockchip: rv1126: Migrate to OF_UPSTREAM

[Anand Moon]

Hi Jonas

On Thu, 9 May 2024 at 21:38, Jonas Karlman  wrote:
>
> Hi,
>
> On 2024-05-09 17:26, Anand Moon wrote:
> > Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.
> >
> > Following targets is not migrated to use OF_UPSTREAM:
>

Ok, will update the commit message in the future.

> At first I got a little bit confused about the "not migrated", but see
> now that these are the boards that is migrated.
>
> > - rv1126-edgeble-neu2 : Board is an industrial form factor
> > IO board.
> > - sonoff-ihost-rv1126 : Gateway device designed to provide a
> > Smart Home Hub.
> >
> > Cc: Tim Lunn 
> > Cc: Jagan Teki 
> > Signed-off-by: Anand Moon 
> > ---
> > Tested on neu2 edgable board.
> > ---
> >  arch/arm/dts/Makefile   |   3 -
> >  arch/arm/dts/rv1126-edgeble-neu2-io.dts | 112 -
> >  arch/arm/dts/rv1126-edgeble-neu2.dtsi   | 345 -
> >  arch/arm/dts/rv1126-pinctrl.dtsi| 341 -
> >  arch/arm/dts/rv1126-sonoff-ihost.dts|  29 --
> >  arch/arm/dts/rv1126-sonoff-ihost.dtsi   | 404 ---
> >  arch/arm/dts/rv1126.dtsi| 623 
> >  arch/arm/mach-rockchip/Kconfig  |   1 +
> >  configs/neu2-io-rv1126_defconfig|   2 +-
> >  configs/sonoff-ihost-rv1126_defconfig   |   2 +-
> >  10 files changed, 3 insertions(+), 1859 deletions(-)
> >  delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts
> >  delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2.dtsi
> >  delete mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
> >  delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
> >  delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
> >  delete mode 100644 arch/arm/dts/rv1126.dtsi
>
> Following should also be removed:
> - include/dt-bindings/clock/rockchip,rv1126-cru.h
> - include/dt-bindings/power/rockchip,rv1126-power.h
>
> Side note, following is remaining after the rv1108 migration and should
> probably also be removed:
> - include/dt-bindings/clock/rv1108-cru.h
>

I will check if any drivers are using this if not I will remove them.
will address this in V2.

> Regards,
> Jonas

Thanks
-Anand

[PATCH v1] rockchip: rv1126: Migrate to OF_UPSTREAM

[Anand Moon]

Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.

Following targets is not migrated to use OF_UPSTREAM:
- rv1126-edgeble-neu2 : Board is an industrial form factor
IO board.
- sonoff-ihost-rv1126 : Gateway device designed to provide a
Smart Home Hub.

Cc: Tim Lunn 
Cc: Jagan Teki 
Signed-off-by: Anand Moon 
---
Tested on neu2 edgable board.
---
 arch/arm/dts/Makefile   |   3 -
 arch/arm/dts/rv1126-edgeble-neu2-io.dts | 112 -
 arch/arm/dts/rv1126-edgeble-neu2.dtsi   | 345 -
 arch/arm/dts/rv1126-pinctrl.dtsi| 341 -
 arch/arm/dts/rv1126-sonoff-ihost.dts|  29 --
 arch/arm/dts/rv1126-sonoff-ihost.dtsi   | 404 ---
 arch/arm/dts/rv1126.dtsi| 623 
 arch/arm/mach-rockchip/Kconfig  |   1 +
 configs/neu2-io-rv1126_defconfig|   2 +-
 configs/sonoff-ihost-rv1126_defconfig   |   2 +-
 10 files changed, 3 insertions(+), 1859 deletions(-)
 delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts
 delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2.dtsi
 delete mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
 delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
 delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
 delete mode 100644 arch/arm/dts/rv1126.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 087645f354..79fc100dce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,9 +97,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
 
-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
-   rv1126-edgeble-neu2-io.dtb
-
 dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
 
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts 
b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
deleted file mode 100644
index 0c2396b8f8..00
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
-   model = "Edgeble Neu2 IO Board";
-   compatible = "edgeble,neural-compute-module-2-io",
-"edgeble,neural-compute-module-2", "rockchip,rv1126";
-
-   aliases {
-   serial2 = &uart2;
-   };
-
-   chosen {
-   stdout-path = "serial2:150n8";
-   };
-
-   vcc12v_dcin: vcc12v-dcin-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc12v_dcin";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <1200>;
-   regulator-max-microvolt = <1200>;
-   };
-
-   vcc5v0_sys: vcc5v0-sys-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc5v0_sys";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <500>;
-   regulator-max-microvolt = <500>;
-   vin-supply = <&vcc12v_dcin>;
-   };
-
-   v3v3_sys: v3v3-sys-regulator {
-   compatible = "regulator-fixed";
-   regulator-name = "v3v3_sys";
-   regulator-always-on;
-   regulator-boot-on;
-   regulator-min-microvolt = <330>;
-   regulator-max-microvolt = <330>;
-   vin-supply = <&vcc5v0_sys>;
-   };
-};
-
-&gmac {
-   assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_ETHERNET_OUT>;
-   assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
-   assigned-clock-rates = <12500>, <0>, <2500>;
-   clock_in_out = "input";
-   phy-handle = <&phy>;
-   phy-mode = "rgmii";
-   phy-supply = <&vcc_3v3>;
-   pinctrl-names = "default";
-   pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 
&clk_out_ethernetm1_pins>;
-   tx_delay = <0x2a>;
-   rx_delay = <0x1a>;
-   status = "okay";
-};
-
-&mdio {
-   phy: ethernet-phy@0 {
-   compatible = "ethernet-phy-id001c.c916",
-"ethernet-phy-ieee802.3-c22";
-   reg = <0x0>;
-   pinctrl-names = "default";
-   pinctrl-0 = <ð_phy_rst>;
-   reset-assert-us = <2>;
-   reset-deas

Re: Raspberry Pi 3b Plus USB-Ethernet lan78xx_eth address not set

[Anand Moon]

Hi,

On Sun, 25 Feb 2024 at 12:25, Sourabh Hegde Ramu
 wrote:
>
> Hi Anand,
>
> Thanks for the update.
>
> Yes, I can set it manually. But this should be done by u-boot, right? Is 
> there any reason why this is not happening on Pi 3b plus?
> I have other Raspberry Pi (4 & 3b) and they are working fine.
>
> Also, is this MAC address for LAN75xx or LAN78xx? The error message shows 
> lan78xx_eth.
>

Most of the ethernet controllers get the MAC address via EPROM.
or they used some logic to set the MAC address.
check CONFIG_NET_RANDOM_ETHADDR this flag is needed for your device.

Thanks
-Anand
>
> On Sun, Feb 25, 2024, 06:50 Anand Moon  wrote:
>>
>> Hi,
>>
>> On Sat, 24 Feb 2024 at 01:56, Sourabh Hegde Ramu
>>  wrote:
>> >
>> > Hello,
>> >
>> > I have a Raspberry Pi 3B Plus which I want to integrate with U-boot
>> > (v2023.10) .
>> >
>> > I am using rpi_3_32b_defconfig to generate u-boot.bin. But while booting I
>> > am getting below error
>> >
>> > Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
>> > In:serial,usbkbd
>> > Out:   serial,vidconsole
>> > Err:   serial,vidconsole
>> > Net:   No ethernet found.
>> > starting USB...
>> > Bus usb@7e98: USB DWC2
>> > scanning bus usb@7e98 for devices...
>> > Error: lan78xx_eth address not set.
>> > 3 USB Device(s) found
>> >scanning usb for storage devices... 0 Storage Device(s) found
>> > Hit any key to stop autoboot:  0
>> >
>> > In the "bdinfo", "current eth" is not set
>> >
>> > U-Boot> bdinfo
>> > boot_params = 0x0100
>> > DRAM bank   = 0x
>> > -> start= 0x
>> > -> size = 0x3b40
>> > flashstart  = 0x
>> > flashsize   = 0x
>> > flashoffset = 0x
>> > baudrate= 115200 bps
>> > relocaddr   = 0x3b36
>> > reloc off   = 0x3b358000
>> > Build   = 32-bit
>> > current eth = unknown
>> > eth-1addr   = (not set)
>> > IP addr = 
>> >
>> > I also enabled LAN75xx in menuconfig and re-compiled u-boot. But still the
>> > same error.
>> >
>> > However on Raspberry Pi 3B, I don't see this error and "current eth" is set
>> > to "smsc95xx_eth" and "ethaddr" is also available.
>> >
>> > Can anyone please let me know the issue with Raspberry Pi 3b plus?
>> >
>> > Thanks in advance.
>>
>> Can you set the MAC address in boot environment?
>>
>> # setenv ethaddr 00:14:05:42:03:BB
>> # saveenv
>>
>> It should update the mac address for LAN75xx
>> printenv should display the mac address
>>
>> Thanks
>> -Anand

Re: Raspberry Pi 3b Plus USB-Ethernet lan78xx_eth address not set

[Anand Moon]

Hi,

On Sat, 24 Feb 2024 at 01:56, Sourabh Hegde Ramu
 wrote:
>
> Hello,
>
> I have a Raspberry Pi 3B Plus which I want to integrate with U-boot
> (v2023.10) .
>
> I am using rpi_3_32b_defconfig to generate u-boot.bin. But while booting I
> am getting below error
>
> Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
> In:serial,usbkbd
> Out:   serial,vidconsole
> Err:   serial,vidconsole
> Net:   No ethernet found.
> starting USB...
> Bus usb@7e98: USB DWC2
> scanning bus usb@7e98 for devices...
> Error: lan78xx_eth address not set.
> 3 USB Device(s) found
>scanning usb for storage devices... 0 Storage Device(s) found
> Hit any key to stop autoboot:  0
>
> In the "bdinfo", "current eth" is not set
>
> U-Boot> bdinfo
> boot_params = 0x0100
> DRAM bank   = 0x
> -> start= 0x
> -> size = 0x3b40
> flashstart  = 0x
> flashsize   = 0x
> flashoffset = 0x
> baudrate= 115200 bps
> relocaddr   = 0x3b36
> reloc off   = 0x3b358000
> Build   = 32-bit
> current eth = unknown
> eth-1addr   = (not set)
> IP addr = 
>
> I also enabled LAN75xx in menuconfig and re-compiled u-boot. But still the
> same error.
>
> However on Raspberry Pi 3B, I don't see this error and "current eth" is set
> to "smsc95xx_eth" and "ethaddr" is also available.
>
> Can anyone please let me know the issue with Raspberry Pi 3b plus?
>
> Thanks in advance.

Can you set the MAC address in boot environment?

# setenv ethaddr 00:14:05:42:03:BB
# saveenv

It should update the mac address for LAN75xx
printenv should display the mac address

Thanks
-Anand

Re: [PATCH] Revert "rockchip: Only call binman when TPL available"

[Anand Moon]

Hi Jagan,

On Fri, 27 Jan 2023 at 12:52, Jagan Teki  wrote:
>
> This reverts commit f5315dd6290a588434e4f79bfd2886bb7df9210d.
>
> [why]
> TPL is not mandatory for not all Rockchip SoCs, some SoCs like
> RK356x, and RK3588 still use mainline u-boot without TPL as
> their ddr init programs are accessed via binaries provided by
> Rockchip instead of ddr source code.
>
> Marking TPL build makes it not able to build u-boot.itb on
> RK356x targets so revert this so that it can build an SPL build
> that would support all across Rockchip platforms.
>
> Suggested-by: Quentin Schulz 
> Signed-off-by: Jagan Teki 
> ---

Please add my
Tested-by: Anand Moon   # CM3

Thanks

-Anand

Re: [PATCH v2 3/4] arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 IO

[Anand Moon]

Hi Jagan,

On Tue, 17 Jan 2023 at 14:53, Jagan Teki  wrote:
>
> Radxa Compute Module 3(CM3) IO board an application board from Radxa
> and is compatible with Raspberry Pi CM4 IO form factor.
>
> Specification:
> - 1x HDMI,
> - 2x MIPI DSI
> - 2x MIPI CSI2
> - 1x eDP
> - 1x PCIe card
> - 2x SATA
> - 2x USB 2.0 Host
> - 1x USB 3.0
> - 1x USB 2.0 OTG
> - Phone jack
> - microSD slot
> - 40-pin GPIO expansion header
> - 12V DC
>
> Radxa CM3 needs to mount on top of this IO board in order to create
> complete Radxa CM3 IO board platform.
>
> linux-next commit for the same,
> commit <096ebfb74b19> ("arm64: dts: rockchip: Add Radxa Compute Module 3
> IO board")
>
> Add support for Radxa CM3 IO Board.
>
> Co-developed-by: FUKAUMI Naoki 
> Signed-off-by: FUKAUMI Naoki 
> Co-developed-by: Manoj Sai 
> Signed-off-by: Manoj Sai 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v2:
> - add Linux-next commit

Please add my
Tested-by: Anand Moon   # CM3

Thanks

-Anand

Radax failed to boot - how to recover the board.

[Anand Moon]

Hi Kever / Jagan,

I have Radxa N10 RK3399pro model B 6 GB ram, (4 GB +2GB NPU).
When I tried to boot via micro sd card it booted with stock android u-boot,
but this u-boot was not enabled all 4BG memory in total.
So I tried to replace the image with the latest u-boot.

Now when I flash the u-boot to eMMC (onboard) with the latest u-boot
it failed to boot. see below.

Please help me recover the board, I cannot reset the board via the reset button
or nor is it entering the u-boot command prompt.

Please advise me on how to proceed.on recovery off the board?

Thanks
-Anand

As per the Radax wiki page the DRAM 6GB 64bit dual channel LPDDR3@1866Mb/s,
So I have modified the code as below.

$ git diff arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi
diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi
b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi
index 7c66e1145a..08266bb3ac 100644
--- a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi
+++ b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi
@@ -4,7 +4,7 @@
  */

 #include "rk3399pro-u-boot.dtsi"
-#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"

Boot failed ...not able to recover the.

U-Boot TPL 2021.10-rc4-00055-g8284d6f838-dirty (Sep 26 2021 - 20:29:22)
Channel 0: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256 stride
Trying to boot from&{{▒▒{kk
   Returning to boot ROM...

U,Boot SPL 2021.10-rc4-00055-g8284d6f838-dirty (Sep 26 2021 - 20:29:22 +0530)
Trying to boot from MMC1
Card did not respond to voltage select! : -110
spl: mmc init failed with error: -95
SPL: failed to boot from all boot deviceC
### ERROR ### Please RESET the board ###

[PATCHv4 3/3] pci: pcie_dw_rockchip: Replace msleep occurences by udelay

[Anand Moon]

Replace msleep occurences by udelay.

drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
 declaration of function 'msleep' [-Wimplicit-function-declaration]

Cc: Patrick Wildt 
Cc: Neil Armstrong 
Cc: Kever Yang 
Signed-off-by: Anand Moon 
---
Keep is simple...sorry !!!
---
 drivers/pci/pcie_dw_rockchip.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 4e448c0a3d..9322e735b9 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -61,7 +61,7 @@ struct rk_pcie {
 #define PCIE_CLIENT_DBF_EN 0x0003
 
 /* Parameters for the waiting for #perst signal */
-#define PERST_WAIT_MS  1000
+#define MACRO_US   1000
 
 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 {
@@ -249,7 +249,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
cap_speed)
 * some wired devices need much more, such as 600ms.
 * Add a enough delay to cover all cases.
 */
-   msleep(PERST_WAIT_MS);
+   udelay(MACRO_US * 1000);
dm_gpio_set_value(&priv->rst_gpio, 1);
}
 
@@ -271,12 +271,12 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
cap_speed)
dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
rk_pcie_debug_dump(priv);
-   msleep(1000);
+   udelay(MACRO_US * 1000);
}
 
dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
/* Link maybe in Gen switch recovery but we need to wait more 1s */
-   msleep(1000);
+   udelay(MACRO_US * 1000);
return -EIO;
 }
 
@@ -296,7 +296,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
}
}
 
-   msleep(1000);
+   udelay(MACRO_US * 1000);
 
ret = generic_phy_init(&priv->phy);
if (ret) {
-- 
2.31.1

[PATCHv4 2/3] pci: pcie_dw_rockchip: Drop the unused variable warning

[Anand Moon]

Drop the unused variable warning below.

drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable
'val' [-Wunused-variable]
  161 |  u32 val;
   |  ^~~
Cc: Patrick Wildt 
Cc: Neil Armstrong 
Cc: Kever Yang 
Reviewed-by: Neil Armstrong 
Reviewed-by: Patrick Wildt 
Signed-off-by: Anand Moon 
---
 drivers/pci/pcie_dw_rockchip.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 3ac2434b69..4e448c0a3d 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie 
*rk_pcie, u32 reg,
  */
 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
 {
-   u32 val;
-
dw_pcie_dbi_write_enable(&pci->dw, true);
 
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
-- 
2.31.1

[PATCHv4 1/3] pci: pcie_dw_rockchip: Fixed the below compilation error

[Anand Moon]

Use the generic error number instead of specific error number.
Changes fix the below error.

drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this function)
   70 |   return PCIBIOS_UNSUPPORTED;
  |  ^~~
drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write':
drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this function)
   90 |   return PCIBIOS_UNSUPPORTED;
  |  ^~~

Cc: Patrick Wildt 
Cc: Neil Armstrong 
Cc: Kever Yang 
Reviewed-by: Neil Armstrong 
Reviewed-by: Patrick Wildt 
Signed-off-by: Anand Moon 
---
 drivers/pci/pcie_dw_rockchip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index bc22af4230..3ac2434b69 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -67,7 +67,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 
*val)
 {
if ((uintptr_t)addr & (size - 1)) {
*val = 0;
-   return PCIBIOS_UNSUPPORTED;
+   return -EOPNOTSUPP;
}
 
if (size == 4) {
@@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 
*val)
 static int rk_pcie_write(void __iomem *addr, int size, u32 val)
 {
if ((uintptr_t)addr & (size - 1))
-   return PCIBIOS_UNSUPPORTED;
+   return -EOPNOTSUPP;
 
if (size == 4)
writel(val, addr);
-- 
2.31.1

Re: [PATCHv3 3/3] pci: pcie_dw_rockchip: Replace msleep occurences by udelay

[Anand Moon]

Hi Patrick.

On Fri, 4 Jun 2021 at 21:14, Patrick Wildt  wrote:
>
> Am Fri, Jun 04, 2021 at 04:56:07AM + schrieb Anand Moon:
> > Replace msleep occurences by udelay.
> >
> > drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
> >  declaration of function 'msleep' [-Wimplicit-function-declaration]
> >
> > Cc: Patrick Wildt 
> > Cc: Neil Armstrong 
> > Cc: Kever Yang 
> > Signed-off-by: Anand Moon 
> > ---
> > V2: drop the msleep macro.
> > ---
> >  drivers/pci/pcie_dw_rockchip.c | 9 +
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
> > index 4e448c0a3d..039266a357 100644
> > --- a/drivers/pci/pcie_dw_rockchip.c
> > +++ b/drivers/pci/pcie_dw_rockchip.c
> > @@ -62,6 +62,7 @@ struct rk_pcie {
> >
> >  /* Parameters for the waiting for #perst signal */
> >  #define PERST_WAIT_MS1000
> > +#define MACRO_US 1000
> >
> >  static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
> >  {
> > @@ -249,7 +250,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
> > cap_speed)
> >* some wired devices need much more, such as 600ms.
> >* Add a enough delay to cover all cases.
> >*/
> > - msleep(PERST_WAIT_MS);
> > + udelay(PERST_WAIT_MS);
>
> You're missing the * MACRO_US here.  I'm not sure though that really

Thanks, I forgot to update, it got skipped.

> needs a macro for MS to US, or did someone request that?

Neil suggested something in my review commend.

Please replace msleep occurences by udelay with either:
- udelay(MACRO_MS * 1000)
- udelay(MACRO_US) and replace MACRO_MS with MACRO_US with values *1000

Opps I miss read the request.

Thanks
-Anand

[PATCHv3 3/3] pci: pcie_dw_rockchip: Replace msleep occurences by udelay

[Anand Moon]

Replace msleep occurences by udelay.

drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
 declaration of function 'msleep' [-Wimplicit-function-declaration]

Cc: Patrick Wildt 
Cc: Neil Armstrong 
Cc: Kever Yang 
Signed-off-by: Anand Moon 
---
V2: drop the msleep macro.
---
 drivers/pci/pcie_dw_rockchip.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 4e448c0a3d..039266a357 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -62,6 +62,7 @@ struct rk_pcie {
 
 /* Parameters for the waiting for #perst signal */
 #define PERST_WAIT_MS  1000
+#define MACRO_US   1000
 
 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 {
@@ -249,7 +250,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
cap_speed)
 * some wired devices need much more, such as 600ms.
 * Add a enough delay to cover all cases.
 */
-   msleep(PERST_WAIT_MS);
+   udelay(PERST_WAIT_MS);
dm_gpio_set_value(&priv->rst_gpio, 1);
}
 
@@ -271,12 +272,12 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
cap_speed)
dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
rk_pcie_debug_dump(priv);
-   msleep(1000);
+   udelay(PERST_WAIT_MS * MACRO_US);
}
 
dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
/* Link maybe in Gen switch recovery but we need to wait more 1s */
-   msleep(1000);
+   udelay(PERST_WAIT_MS * MACRO_US);
return -EIO;
 }
 
@@ -296,7 +297,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
}
}
 
-   msleep(1000);
+   udelay(PERST_WAIT_MS * MACRO_US);
 
ret = generic_phy_init(&priv->phy);
if (ret) {
-- 
2.31.1

[PATCHv3 2/3] pci: pcie_dw_rockchip: Drop the unused variable warning

[Anand Moon]

Drop the unused variable warning below.

drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable
'val' [-Wunused-variable]
  161 |  u32 val;
   |  ^~~
Cc: Patrick Wildt 
Cc: Neil Armstrong 
Cc: Kever Yang 
Reviewed-by: Neil Armstrong 
Signed-off-by: Anand Moon 
---
V1
V2: Added Neil review tags.
---
 drivers/pci/pcie_dw_rockchip.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 3ac2434b69..4e448c0a3d 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie 
*rk_pcie, u32 reg,
  */
 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
 {
-   u32 val;
-
dw_pcie_dbi_write_enable(&pci->dw, true);
 
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
-- 
2.31.1

[PATCHv3 1/3] pci: pcie_dw_rockchip: Fixed the below compilation error

[Anand Moon]

Use the generic error number instead of specific error number.
Changes fix the below error.

drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this function)
   70 |   return PCIBIOS_UNSUPPORTED;
  |  ^~~
drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write':
drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this function)
   90 |   return PCIBIOS_UNSUPPORTED;
  |  ^~~

Cc: Patrick Wildt 
Cc: Neil Armstrong 
Cc: Kever Yang 
Reviewed-by: Neil Armstrong 
Signed-off-by: Anand Moon 
---
v1: Drop the PCI ERROR MACRO,
v2: added the Neil review tag.
---
---
 drivers/pci/pcie_dw_rockchip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index bc22af4230..3ac2434b69 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -67,7 +67,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 
*val)
 {
if ((uintptr_t)addr & (size - 1)) {
*val = 0;
-   return PCIBIOS_UNSUPPORTED;
+   return -EOPNOTSUPP;
}
 
if (size == 4) {
@@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 
*val)
 static int rk_pcie_write(void __iomem *addr, int size, u32 val)
 {
if ((uintptr_t)addr & (size - 1))
-   return PCIBIOS_UNSUPPORTED;
+   return -EOPNOTSUPP;
 
if (size == 4)
writel(val, addr);
-- 
2.31.1

[PATCHv2 3/3] pci: pcie_dw_rockchip: Use mleep macro to fix below error

[Anand Moon]

Define msleep macro to fix below error.

drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
declaration of function 'msleep' [-Wimplicit-function-declaration]

Cc: Patrick Wildt 
Cc: Neil Armstrong 
Cc: Kever Yang 
Signed-off-by: Anand Moon 
---
v1: drop the udelay changes.
---
 drivers/pci/pcie_dw_rockchip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 4e448c0a3d..bdc4d51007 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -60,6 +60,7 @@ struct rk_pcie {
 #define PCIE_CLIENT_DBG_TRANSITION_DATA0x
 #define PCIE_CLIENT_DBF_EN 0x0003
 
+#define msleep(a) udelay((a) * 1000)
 /* Parameters for the waiting for #perst signal */
 #define PERST_WAIT_MS  1000
 
-- 
2.31.1

[PATCHv2 2/3] pci: pcie_dw_rockchip: Drop the unused variable warning

[Anand Moon]

Drop the unused variable warning below.

drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable
'val' [-Wunused-variable]
  161 |  u32 val;
  |  ^~~

Cc: Patrick Wildt 
Cc: Neil Armstrong 
Cc: Kever Yang 
Signed-off-by: Anand Moon 
---
 drivers/pci/pcie_dw_rockchip.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 3ac2434b69..4e448c0a3d 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie 
*rk_pcie, u32 reg,
  */
 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
 {
-   u32 val;
-
dw_pcie_dbi_write_enable(&pci->dw, true);
 
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
-- 
2.31.1

[PATCHv2 1/3] pci: pcie_dw_rockchip: Fixed the below compilation error

[Anand Moon]

Use the generic error number instead of specific error number.
Changes fix the below error.

drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this function)
   70 |   return PCIBIOS_UNSUPPORTED;
  |  ^~~
drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write':
drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this function)
   90 |   return PCIBIOS_UNSUPPORTED;
  |  ^~~

Cc: Patrick Wildt 
Cc: Neil Armstrong 
Cc: Kever Yang 
Signed-off-by: Anand Moon 
---
v1: Drop the PCI ERROR MACRO,
---
 drivers/pci/pcie_dw_rockchip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index bc22af4230..3ac2434b69 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -67,7 +67,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 
*val)
 {
if ((uintptr_t)addr & (size - 1)) {
*val = 0;
-   return PCIBIOS_UNSUPPORTED;
+   return -EOPNOTSUPP;
}
 
if (size == 4) {
@@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 
*val)
 static int rk_pcie_write(void __iomem *addr, int size, u32 val)
 {
if ((uintptr_t)addr & (size - 1))
-   return PCIBIOS_UNSUPPORTED;
+   return -EOPNOTSUPP;
 
if (size == 4)
writel(val, addr);
-- 
2.31.1

Re: [PATCH 1/3] pci: pcie_dw_rockchip: Fixed the below compilation error

[Anand Moon]

H Kever,

On Fri, 21 May 2021 at 18:51, Kever Yang  wrote:
>
>
> On 2021/4/26 下午9:26, Anand Moon wrote:
> > Use the Error values that may be returned by PCI functions
> > Added the error macro from linux/include/linux/pci.h
> >
> > drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
> > drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
> >   undeclared (first use in this function)
> > 70 |   return PCIBIOS_UNSUPPORTED;
> >|  ^~~
> > drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write':
> > drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED'
> >   undeclared (first use in this function)
> > 90 |   return PCIBIOS_UNSUPPORTED;
> >|  ^~~
> >
> > Cc: Neil Armstrong 
> > Cc: Kever Yang 
> > Signed-off-by: Anand Moon 
>
>
> Reviewed-by: Kever Yang 
>

Oops, I forgot to send the revised version of these patches.

> Thanks,
>
> - Kever

Re: [PATCH 3/3] pci: pcie_dw_rockchip: Use udelay instead of msleep

[Anand Moon]

Hi Patrick,

On Wed, 28 Apr 2021 at 00:57, Patrick Wildt  wrote:
>
> Am Tue, Apr 27, 2021 at 11:11:19AM +0530 schrieb Anand Moon:
> > hi Patrick,
> >
> > On Tue, 27 Apr 2021 at 01:38, Patrick Wildt  wrote:
> > >
> > > Am Mon, Apr 26, 2021 at 01:26:32PM + schrieb Anand Moon:
> > > > Use udelay instead of msleep fix the below warning.
> > >
> > > You sure that's correct? the m in msleep means milli, while the u
> > > in udelay means micro.  That's a factor of 1000 of a difference.
> > >
> > Thanks for your review comments.
> >
> > Most of the u-boot driver prefers udelay and usleep_range internally
> > calls udelay.
> >
> > I don't have the HW to test and verify.
> >
> > -Anand
>
> Sure, I'm not complaining about that.  My point is that if you pass
> e. g. 8 milliseconds to a function that takes microseconds, you need
> to add the factor.
>
> Not good: msleep(1000) -> udelay(1000)
> Much better: msleep(1000) -> udelay(1000 * 1000)
>
> Which also means that you either have to rename PERST_WAIT_MS and change
> its value, or do udelay(PERST_WAIT_MS * 1000)

Thanks for this tip, can we use mdelay as sugged above.
.
static inline void mdelay(unsigned long msec)
{
udelay(1000 * msec);
}

Thanks
-Anand

Re: [PATCH 3/3] pci: pcie_dw_rockchip: Use udelay instead of msleep

[Anand Moon]

hi Patrick,

On Tue, 27 Apr 2021 at 01:38, Patrick Wildt  wrote:
>
> Am Mon, Apr 26, 2021 at 01:26:32PM + schrieb Anand Moon:
> > Use udelay instead of msleep fix the below warning.
>
> You sure that's correct? the m in msleep means milli, while the u
> in udelay means micro.  That's a factor of 1000 of a difference.
>
Thanks for your review comments.

Most of the u-boot driver prefers udelay and usleep_range internally
calls udelay.

I don't have the HW to test and verify.



-Anand

Re: [PATCH 1/3] pci: pcie_dw_rockchip: Fixed the below compilation error

[Anand Moon]

Hi Patrick,

On Tue, 27 Apr 2021 at 01:40, Patrick Wildt  wrote:
>
> Am Mon, Apr 26, 2021 at 01:26:30PM + schrieb Anand Moon:
> > Use the Error values that may be returned by PCI functions
> > Added the error macro from linux/include/linux/pci.h
> >
> > drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
> > drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
> >   undeclared (first use in this function)
> >70 |   return PCIBIOS_UNSUPPORTED;
> >   |  ^~~
> > drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write':
> > drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED'
> >   undeclared (first use in this function)
> >90 |   return PCIBIOS_UNSUPPORTED;
> >   |  ^~~
> >
> > Cc: Neil Armstrong 
> > Cc: Kever Yang 
> > Signed-off-by: Anand Moon 
> > ---
> >  drivers/pci/pcie_dw_common.h   | 9 +
> >  drivers/pci/pcie_dw_rockchip.c | 4 ++--
> >  2 files changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h
> > index 6b701645af..ba5feb5b51 100644
> > --- a/drivers/pci/pcie_dw_common.h
> > +++ b/drivers/pci/pcie_dw_common.h
> > @@ -90,6 +90,15 @@
> >  #define PCIE_MISC_CONTROL_1_OFF  0x8bc
> >  #define PCIE_DBI_RO_WR_ENBIT(0)
> >
> > +/* Error values that may be returned by PCI functions */
> > +#define PCIBIOS_SUCCESSFUL  0x00
> > +#define PCIBIOS_FUNC_NOT_SUPPORTED  0x81
> > +#define PCIBIOS_BAD_VENDOR_ID   0x83
> > +#define PCIBIOS_DEVICE_NOT_FOUND0x86
> > +#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
> > +#define PCIBIOS_SET_FAILED  0x88
> > +#define PCIBIOS_BUFFER_TOO_SMALL0x89
> > +
> >  /* Parameters for the waiting for iATU enabled routine */
> >  #define LINK_WAIT_MAX_IATU_RETRIES   5
> >  #define LINK_WAIT_IATU   1
> > diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
> > index bc22af4230..9702b40019 100644
> > --- a/drivers/pci/pcie_dw_rockchip.c
> > +++ b/drivers/pci/pcie_dw_rockchip.c
> > @@ -67,7 +67,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 
> > *val)
> >  {
> >   if ((uintptr_t)addr & (size - 1)) {
> >   *val = 0;
> > - return PCIBIOS_UNSUPPORTED;
> > + return PCIBIOS_BAD_REGISTER_NUMBER;
>
> Since this function seems to return normal error code, why not use
> -EINVAL?  Or even better -EOPNOTSUP?  The callers only check for != 0
> anyway.
>

Thanks for your review comments.
-EOPNOTSUPP It seems to be the correct return code over here.


-Anand

[PATCH 3/3] pci: pcie_dw_rockchip: Use udelay instead of msleep

[Anand Moon]

Use udelay instead of msleep fix the below warning.

drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
declaration of function 'msleep' [-Wimplicit-function-declaration]

Cc: Neil Armstrong 
Cc: Kever Yang 
Signed-off-by: Anand Moon 
---
 drivers/pci/pcie_dw_rockchip.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index e7f42604ab..6c87ee1ea0 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -249,7 +249,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
cap_speed)
 * some wired devices need much more, such as 600ms.
 * Add a enough delay to cover all cases.
 */
-   msleep(PERST_WAIT_MS);
+   udelay(PERST_WAIT_MS);
dm_gpio_set_value(&priv->rst_gpio, 1);
}
 
@@ -271,12 +271,12 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 
cap_speed)
dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
rk_pcie_debug_dump(priv);
-   msleep(1000);
+   udelay(1000);
}
 
dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
/* Link maybe in Gen switch recovery but we need to wait more 1s */
-   msleep(1000);
+   udelay(1000);
return -EIO;
 }
 
@@ -296,7 +296,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
}
}
 
-   msleep(1000);
+   udelay(1000);
 
ret = generic_phy_init(&priv->phy);
if (ret) {
-- 
2.31.1

[PATCH 2/3] pci: pcie_dw_rockchip: Drop the unused variable warning

[Anand Moon]

Drop the unused variable warning below.

drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable
'val' [-Wunused-variable]
  161 |  u32 val;
  |  ^~~

Cc: Neil Armstrong 
Cc: Kever Yang 
Signed-off-by: Anand Moon 
---
 drivers/pci/pcie_dw_rockchip.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 9702b40019..e7f42604ab 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie 
*rk_pcie, u32 reg,
  */
 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
 {
-   u32 val;
-
dw_pcie_dbi_write_enable(&pci->dw, true);
 
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
-- 
2.31.1

[PATCH 1/3] pci: pcie_dw_rockchip: Fixed the below compilation error

[Anand Moon]

Use the Error values that may be returned by PCI functions
Added the error macro from linux/include/linux/pci.h

drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this function)
   70 |   return PCIBIOS_UNSUPPORTED;
  |  ^~~
drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write':
drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this function)
   90 |   return PCIBIOS_UNSUPPORTED;
  |  ^~~

Cc: Neil Armstrong 
Cc: Kever Yang 
Signed-off-by: Anand Moon 
---
 drivers/pci/pcie_dw_common.h   | 9 +
 drivers/pci/pcie_dw_rockchip.c | 4 ++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h
index 6b701645af..ba5feb5b51 100644
--- a/drivers/pci/pcie_dw_common.h
+++ b/drivers/pci/pcie_dw_common.h
@@ -90,6 +90,15 @@
 #define PCIE_MISC_CONTROL_1_OFF0x8bc
 #define PCIE_DBI_RO_WR_EN  BIT(0)
 
+/* Error values that may be returned by PCI functions */
+#define PCIBIOS_SUCCESSFUL  0x00
+#define PCIBIOS_FUNC_NOT_SUPPORTED  0x81
+#define PCIBIOS_BAD_VENDOR_ID   0x83
+#define PCIBIOS_DEVICE_NOT_FOUND0x86
+#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
+#define PCIBIOS_SET_FAILED  0x88
+#define PCIBIOS_BUFFER_TOO_SMALL0x89
+
 /* Parameters for the waiting for iATU enabled routine */
 #define LINK_WAIT_MAX_IATU_RETRIES 5
 #define LINK_WAIT_IATU 1
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index bc22af4230..9702b40019 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -67,7 +67,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 
*val)
 {
if ((uintptr_t)addr & (size - 1)) {
*val = 0;
-   return PCIBIOS_UNSUPPORTED;
+   return PCIBIOS_BAD_REGISTER_NUMBER;
}
 
if (size == 4) {
@@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 
*val)
 static int rk_pcie_write(void __iomem *addr, int size, u32 val)
 {
if ((uintptr_t)addr & (size - 1))
-   return PCIBIOS_UNSUPPORTED;
+   return PCIBIOS_BAD_REGISTER_NUMBER;
 
if (size == 4)
writel(val, addr);
-- 
2.31.1

Re: [BUG]odroid-c2 does not hotplug usb-devices

[Anand Moon]

Hi Martin,

On Sun, 20 Dec 2020 at 20:04, Martin Blumenstingl
 wrote:
>
> Hi Anand,
>
> On Sun, Dec 20, 2020 at 2:46 PM Anand Moon  wrote:
> [...]
> > > On Sat, Dec 19, 2020 at 8:53 PM Anand Moon  wrote:
> > > [...]
> > > > I was also looking into this issue so I made some changes in the
> > > > phy driver to resolve the issue. Plz share your thoughts on the changes 
> > > > below.
> > > first I have some questions :-)
> > > 1. do you see the same problem that Otto sees? this means: a) USB
> > > hotplug works as long as at least one device is plugged in at boot b)
> > > (if I understand Otto correctly then) it breaks once all USB devices
> > > have been removed
> >
> > On C1/C2 issue is when single usb hdd is connected to board it will
> > not get detected.
> > unless you connect another usb keyboard or wireless dongle to the board.
> >
> > *USB hot plug only works if two ore more usb devices are connected.*
> I am not sure if that's really the same issue as described by Otto
>
OK.
> [...]
> > > > amoon@ThinkPad-T440s:~/mainline/linux-aml-5.y-devel$ git diff
> > > > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > > > b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > > > index 7c029f552a23..363dd2ac17e6 100644
> > > > --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > > > +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > > > @@ -20,6 +20,7 @@ usb0_phy: phy@c000 {
> > > > #phy-cells = <0>;
> > > > reg = <0x0 0xc000 0x0 0x20>;
> > > > resets = <&reset RESET_USB_OTG>;
> > > > +   reset-names = "phy-reset";
> > > > clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
> > > > clock-names = "usb_general", "usb";
> > > > status = "disabled";
> > > > @@ -30,6 +31,7 @@ usb1_phy: phy@c020 {
> > > > #phy-cells = <0>;
> > > > reg = <0x0 0xc020 0x0 0x20>;
> > > > resets = <&reset RESET_USB_OTG>;
> > > > +   reset-names = "phy-reset";
> > > > clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
> > > > clock-names = "usb_general", "usb";
> > > > status = "disabled";
> > > I don't see why the above two changes are needed
> > > see my comment about of_reset_control_get_shared below
> > >
> >
> > Yep I borrowed this logic from rockchip usb phy controller.
> > but I missed the action on reset.
> >
> > err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action,  rk_phy);
> > if (err)
> > return err;
> (assuming that your comment relates to the of_reset_control_get_shared
> call below)
> I checked rockchip_usb_phy_action and it's not calling reset_control_put 
> either
> this looks strange to me and I would say that there's a memory leak.
>
Ok, I will try to check this, my approach was just to get the reset code
to get trigger, but is seem that it is not getting triggered,

> [...]
> > > >  static const struct phy_ops phy_meson8b_usb2_ops = {
> > > > .power_on   = phy_meson8b_usb2_power_on,
> > > > .power_off  = phy_meson8b_usb2_power_off,
> > > > +   .reset  = phy_meson8b_usb2_reset,
> > > > .owner  = THIS_MODULE,
> > > >  };
> > > I tested this on my Odroid-C1: phy_meson8b_usb2_reset is never called
> > > after checking the dwc2 code this is expected: only in one very
> > > specific case the dwc2 driver calls phy_reset
> > > can you please find out how phy_meson8b_usb2_reset is called in your 
> > > kernel?
> > >
> >
> > Yep, Its not getting called on my board, l might be missing some thing.
> are you sure that your patch fixes USB hotplug for you?
>
> the new reset callback is a no-op because it's not called
> the code below (of_reset_control_get_shared) only fetches the same
> reset line that we are already using
> so I am not sure what changed behavior you are seeing - can you please
> explain this in more detail?

I am looking into the phy-meson-gxl-usb2.c and I will

Re: [BUG]odroid-c2 does not hotplug usb-devices

[Anand Moon]

Hi Martin,

Thanks for testing and sharing your view points.

On Sun, 20 Dec 2020 at 04:01, Martin Blumenstingl
 wrote:
>
> Hi Anand,
>
> On Sat, Dec 19, 2020 at 8:53 PM Anand Moon  wrote:
> [...]
> > I was also looking into this issue so I made some changes in the
> > phy driver to resolve the issue. Plz share your thoughts on the changes 
> > below.
> first I have some questions :-)
> 1. do you see the same problem that Otto sees? this means: a) USB
> hotplug works as long as at least one device is plugged in at boot b)
> (if I understand Otto correctly then) it breaks once all USB devices
> have been removed

On C1/C2 issue is when single usb hdd is connected to board it will
not get detected.
unless you connect another usb keyboard or wireless dongle to the board.

*USB hot plug only works if two ore more usb devices are connected.*

> 2. does the mainline u-boot patch mentioned by Otto fix the problem
> for you? according to him it fixes the problem and he did not have to
> modify the USB PHY driver
>

I have not check this out, I will verify this later.

> > amoon@ThinkPad-T440s:~/mainline/linux-aml-5.y-devel$ git diff
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > index 7c029f552a23..363dd2ac17e6 100644
> > --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> > @@ -20,6 +20,7 @@ usb0_phy: phy@c000 {
> > #phy-cells = <0>;
> > reg = <0x0 0xc000 0x0 0x20>;
> > resets = <&reset RESET_USB_OTG>;
> > +   reset-names = "phy-reset";
> > clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
> > clock-names = "usb_general", "usb";
> > status = "disabled";
> > @@ -30,6 +31,7 @@ usb1_phy: phy@c020 {
> > #phy-cells = <0>;
> > reg = <0x0 0xc020 0x0 0x20>;
> > resets = <&reset RESET_USB_OTG>;
> > +   reset-names = "phy-reset";
> > clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
> > clock-names = "usb_general", "usb";
> > status = "disabled";
> I don't see why the above two changes are needed
> see my comment about of_reset_control_get_shared below
>

Yep I borrowed this logic from rockchip usb phy controller.
but I missed the action on reset.

err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action,  rk_phy);
if (err)
return err;

> > diff --git a/drivers/phy/amlogic/phy-meson8b-usb2.c
> > b/drivers/phy/amlogic/phy-meson8b-usb2.c
> > index 03c061dd5f0d..31523becc878 100644
> > --- a/drivers/phy/amlogic/phy-meson8b-usb2.c
> > +++ b/drivers/phy/amlogic/phy-meson8b-usb2.c
> > @@ -143,14 +143,6 @@ static int phy_meson8b_usb2_power_on(struct phy *phy)
> > u32 reg;
> > int ret;
> >
> > -   if (!IS_ERR_OR_NULL(priv->reset)) {
> > -   ret = reset_control_reset(priv->reset);
> > -   if (ret) {
> > -   dev_err(&phy->dev, "Failed to trigger USB reset\n");
> > -   return ret;
> > -   }
> > -   }
> > -
> > ret = clk_prepare_enable(priv->clk_usb_general);
> > if (ret) {
> > dev_err(&phy->dev, "Failed to enable USB general clock\n");
> > @@ -222,9 +214,23 @@ static int phy_meson8b_usb2_power_off(struct phy *phy)
> > return 0;
> >  }
> >
> > +static int phy_meson8b_usb2_reset(struct phy *phy)
> > +{
> > +   struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy);
> > +
> > +   if (priv->reset) {
> > +   reset_control_assert(priv->reset);
> > +   udelay(10);
> > +   reset_control_deassert(priv->reset);
> > +   }
> > +
> > +   return 0;
> > +}
> > +
> >  static const struct phy_ops phy_meson8b_usb2_ops = {
> > .power_on   = phy_meson8b_usb2_power_on,
> > .power_off  = phy_meson8b_usb2_power_off,
> > +   .reset  = phy_meson8b_usb2_reset,
> > .owner  = THIS_MODULE,
> >  };
> I tested this on my Odroid-C1: phy_meson8b_usb2_reset is never called
> after check

Re: [BUG]odroid-c2 does not hotplug usb-devices

[Anand Moon]

Hi Martin,

On Sat, 19 Dec 2020 at 19:29, Martin Blumenstingl
 wrote:
>
> Hi Otto,
>
> On Mon, Dec 14, 2020 at 8:34 PM Otto Meier  wrote:
> >
> > Hi Martin,
> >
> > Am 13.12.20 um 19:46 schrieb Martin Blumenstingl:
> > > Hi Otto,
> > >
> > > On Mon, Dec 7, 2020 at 1:43 PM Otto Meier  wrote:
> > > [...]
> >  So with the latest u-boot and the kernel from 
> >  https://github.com/chewitt/linux/tree/amlogic-5.10.y
> >  commit 725fc8df7898102f9031ba2075f763884ffa3ee8 everything is working 
> >  again.
> >  USB does hotplugging as expected.
> > >>> So, this fixes USB under Linux ?? It's not clear
> > > if you have time it would be great if you could figure out which of
> > > the patches from Christian's tree fixes USB hotplugging for you.
> > > Or is it fixed in Linux 5.10-rcX even without any patches?
> > >
> > The new mainline kernel 5.10.0 from Linus, without any other patches
> > does detect USB hotpluging,
> > when using u-boot DMI: Hardkernel Co., Ltd. ODROID-C2/ODROID-C2, BIOS
> > 2021.01-rc3-00039-gec79f5ce22-dirty 12/08/2020
> > and the following u-boot patch:
> [...]
> > When i use the last unpatched emmc bootable u-boot 2020.04 the kernel
> > boots, but usb hotplugging
> > does not work.
> Thank you for testing this!
>
> > Hope this describes my findings. If i can help further, please give me a
> > note.
> to be honest: I am a bit lost here. I don't understand how the BOOT_*
> pins interfere with USB.
> I also don't have any Odroid-C2 board myself so I cannot do any
> experiments myself.
> Neil, please let me know if you have any idea here.
>
>
> Best regards,
> Martin
>

I was also looking into this issue so I made some changes in the
phy driver to resolve the issue. Plz share your thoughts on the changes below.

Best Regards
-Anand

amoon@ThinkPad-T440s:~/mainline/linux-aml-5.y-devel$ git diff
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 7c029f552a23..363dd2ac17e6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -20,6 +20,7 @@ usb0_phy: phy@c000 {
#phy-cells = <0>;
reg = <0x0 0xc000 0x0 0x20>;
resets = <&reset RESET_USB_OTG>;
+   reset-names = "phy-reset";
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
clock-names = "usb_general", "usb";
status = "disabled";
@@ -30,6 +31,7 @@ usb1_phy: phy@c020 {
#phy-cells = <0>;
reg = <0x0 0xc020 0x0 0x20>;
resets = <&reset RESET_USB_OTG>;
+   reset-names = "phy-reset";
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
clock-names = "usb_general", "usb";
status = "disabled";
diff --git a/drivers/phy/amlogic/phy-meson8b-usb2.c
b/drivers/phy/amlogic/phy-meson8b-usb2.c
index 03c061dd5f0d..31523becc878 100644
--- a/drivers/phy/amlogic/phy-meson8b-usb2.c
+++ b/drivers/phy/amlogic/phy-meson8b-usb2.c
@@ -143,14 +143,6 @@ static int phy_meson8b_usb2_power_on(struct phy *phy)
u32 reg;
int ret;

-   if (!IS_ERR_OR_NULL(priv->reset)) {
-   ret = reset_control_reset(priv->reset);
-   if (ret) {
-   dev_err(&phy->dev, "Failed to trigger USB reset\n");
-   return ret;
-   }
-   }
-
ret = clk_prepare_enable(priv->clk_usb_general);
if (ret) {
dev_err(&phy->dev, "Failed to enable USB general clock\n");
@@ -222,9 +214,23 @@ static int phy_meson8b_usb2_power_off(struct phy *phy)
return 0;
 }

+static int phy_meson8b_usb2_reset(struct phy *phy)
+{
+   struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy);
+
+   if (priv->reset) {
+   reset_control_assert(priv->reset);
+   udelay(10);
+   reset_control_deassert(priv->reset);
+   }
+
+   return 0;
+}
+
 static const struct phy_ops phy_meson8b_usb2_ops = {
.power_on   = phy_meson8b_usb2_power_on,
.power_off  = phy_meson8b_usb2_power_off,
+   .reset  = phy_meson8b_usb2_reset,
.owner  = THIS_MODULE,
 };

@@ -271,6 +277,10 @@ static int phy_meson8b_usb2_probe(struct
platform_device *pdev)
return -EINVAL;
}

+   priv->reset = of_reset_control_get_shared(pdev->dev.of_node,
"phy-reset");
+   if (IS_ERR(priv->reset))
+   priv->reset = NULL;
+
phy = devm_phy_create(&pdev->dev, NULL, &phy_meson8b_usb2_ops);
if (IS_ERR(phy)) {
dev_err(&pdev->dev, "failed to create PHY\n");

> ___
> linux-amlogic mailing list
> linux-amlo...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic

Re: [BUG] U-boot does not detect emmc card in odroid-c2 for newer U-boot as 2020.04

[Anand Moon]

Hi Otto,

On Thu, 19 Nov 2020 at 21:23, Otto Meier  wrote:
>
> Hi,
>
> I have extended the previous post.
>
>
>
> with these modifications i get:
>
> U-Boot 2021.01-rc2-00047-g9324c9a823-dirty (Nov 19 2020 - 15:33:00
> +0100) odroid-c2
>
> Model: Hardkernel ODROID-C2
> SoC:   Amlogic Meson GXBB (S905) Revision 1f:c (0:1)
> DRAM:  2 GiB
> MMC:   mmc@72000: 0, mmc@74000: 1
> In:serial
> Out:   serial
> Err:   serial
> Net:   Could not get PHY for ethernet@c941: addr -1
> No ethernet found.
>
> Hit any key to stop autoboot:  0
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = cdff
> MESON EMMC status = 01ff2800
> meson_dm_mmc_send_cmd[226]
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2800
> meson_dm_mmc_send_cmd[226]
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = cdff
> MESON EMMC status = 01ff2800
> meson_dm_mmc_send_cmd[226]
> Card did not respond to voltage select! : -110
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = cdff
> MESON EMMC status = 01ff2800
> meson_dm_mmc_send_cmd[226]
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2800
> meson_dm_mmc_send_cmd[226]
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 00ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2800
> meson_dm_mmc_send_cmd[226]
> Card did not respond to voltage select! : -110
> MMC Device 2 not found
> no mmc device at slot 2
> starting USB...
>
> Hope this shed more light on the issue.
>
> Following you find the output of 2020.04 with this mod.
>
> and working reading off mmc info of the emmc
>
> => mmc dev 1
> MESON EMMC status = c5ff
> MESON EMMC status = c5ff
> MESON EMMC status = c8ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = cdff
> MESON EMMC status = 01ff2800
> meson_dm_mmc_send_cmd[206]
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2800
> meson_dm_mmc_send_cmd[206]
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = d9fe
> MESON EMMC status = d9fe
> MESON EMMC status = d9fe
> MESON EMMC status = d9fe
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC status = 01ff2000
> MESON EMMC status = c5ff
> MESON EMMC stat

Re: [PATCH v2 2/3] mmc: meson-gx: change clock phase value on SM1 SoCs

[Anand Moon]

Hi Jaehoon,

On Wed, 11 Nov 2020 at 04:52, Jaehoon Chung  wrote:
>
> From: Neil Armstrong 
>
> Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's
> working fine over 50MHz on Amlogic SM1 SoCs.
> Since Other Amlogic SoCs doens't report an issue, phase value is using
> to 180' by default.
>
> To distinguish which value is used adds an u-boot only sm1 compatible.
>
> In future, it needs to find what value is a proper about each SoCs.
>
> Signed-off-by: Neil Armstrong 
> Signed-off-by: Jaehoon Chung 
> ---

Thanks for this patch series.
I have tested this on Odroid N2 and c4 eMMC module
so Please add my for this series,

Tested-by: Anand Moon 

>  drivers/mmc/meson_gx_mmc.c | 27 +++
>  drivers/mmc/meson_gx_mmc.h |  5 +
>  2 files changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index eedebb317b5f..a5e9ac5637b9 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -17,6 +17,14 @@
>  #include 
>  #include "meson_gx_mmc.h"
>
> +bool meson_gx_mmc_is_compatible(struct udevice *dev,
> +   enum meson_gx_mmc_compatible family)
> +{
> +   enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
> +
> +   return compat == family;
> +}
> +
>  static inline void *get_regbase(const struct mmc *mmc)
>  {
> struct meson_mmc_platdata *pdata = mmc->priv;
> @@ -42,6 +50,8 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> if (!mmc->clock)
> return;
>
> +   /* TOFIX This should use the proper clock taken from DT */
> +
> /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
> if (mmc->clock > 1600) {
> clk = SD_EMMC_CLKSRC_DIV2;
> @@ -52,8 +62,16 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> }
> clk_div = DIV_ROUND_UP(clk, mmc->clock);
>
> -   /* 180 phase core clock */
> -   meson_mmc_clk |= CLK_CO_PHASE_180;
> +   /*
> +* SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
> +* If CLK_CO_PHASE_270 is used, it's more stable than other.
> +* Other SoCs use CLK_CO_PHASE_180 by default.
> +* It needs to find what is a proper value about each SoCs.
> +*/
> +   if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
> +   meson_mmc_clk |= CLK_CO_PHASE_270;
> +   else
> +   meson_mmc_clk |= CLK_CO_PHASE_180;
>
> /* 180 phase tx clock */
> meson_mmc_clk |= CLK_TX_PHASE_000;
> @@ -308,8 +326,9 @@ int meson_mmc_bind(struct udevice *dev)
>  }
>
>  static const struct udevice_id meson_mmc_match[] = {
> -   { .compatible = "amlogic,meson-gx-mmc" },
> -   { .compatible = "amlogic,meson-axg-mmc" },
> +   { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
> +   { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
> +   { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
> { /* sentinel */ }
>  };
>
> diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h
> index b4544b55628f..92aec5329f6e 100644
> --- a/drivers/mmc/meson_gx_mmc.h
> +++ b/drivers/mmc/meson_gx_mmc.h
> @@ -9,6 +9,11 @@
>  #include 
>  #include 
>
> +enum meson_gx_mmc_compatible {
> +   MMC_COMPATIBLE_GX,
> +   MMC_COMPATIBLE_SM1,
> +};
> +
>  #define SDIO_PORT_A0
>  #define SDIO_PORT_B1
>  #define SDIO_PORT_C2
> --
> 2.29.0
>

Re: [PATCH] mmc: meson_gx_mmc: change a clock phase to stable value

[Anand Moon]

Hi Neil,

On Mon, 9 Nov 2020 at 19:56, Neil Armstrong  wrote:
>
> On 09/11/2020 15:10, Mark Kettenis wrote:
> >> From: Neil Armstrong 
> >> Date: Mon, 9 Nov 2020 14:37:09 +0100
> >>
> >> Hi,
> >>
> >> On 09/11/2020 04:12, Jaehoon Chung wrote:
> >>> Core clock phase value is changed from 180' to 270'.
> >>> It's more stable than before.
> >>> - Odroidn-N2/C4 : Working fine with 52MHz
> >>> - VIM3 : Working fine with 52MHz
> >>>
> >>> Before this patch, Odroid-C4 doesn't work fine with 52MHz.
> >>>
> >>> Signed-off-by: Jaehoon Chung 
> >>> ---
> >>>  drivers/mmc/meson_gx_mmc.c | 14 ++
> >>>  1 file changed, 10 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >>> index 719dd1e5e570..7c60e0566560 100644
> >>> --- a/drivers/mmc/meson_gx_mmc.c
> >>> +++ b/drivers/mmc/meson_gx_mmc.c
> >>> @@ -52,10 +52,16 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >>> }
> >>> clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >>>
> >>> -   /* 180 phase core clock */
> >>> -   meson_mmc_clk |= CLK_CO_PHASE_180;
> >>> -
> >>> -   /* 180 phase tx clock */
> >>> +   /*
> >>> +* Clock Phase needs to set a proper value.
> >>> +* It can be changed to other value.
> >>> +* Because CORE : 270' Phase and TX : 0' Phase are stable,
> >>> +* set to them by default.
> >>> +*/
> >>> +   /* Core Clock Phase */
> >>> +   meson_mmc_clk |= CLK_CO_PHASE_270;
> >>> +
> >>> +   /* TX Clock Phase */
> >>> meson_mmc_clk |= CLK_TX_PHASE_000;
> >>>
> >>> /* clock settings */
> >>>
> >>
> >> The previous values were aligned on the Linux driver, which is functional.
> >
> > Actually the Linux driver isn't really functional; the 52 MHz
> > high-speed mode doesn't work.  But since HS200 does work in Linux,
> > probably nobody noticed this.
> >
> > That said, I'm not confident a single clock phase setting will work
> > across all Amlogic SoCs and across different boards.  Maybe we need
> > something in the device tree such that we can control the values on a
> > per-board level.
> >
>
> So this is specific to SM1 SoCs then, because others families doesn't have 
> such issues
> at 52MHz.
>
> So the Linux must be fixes, including the bindings to introduce a new 
> compatible, then
> ported to U-Boot.
>
> So in the meantime, it's right to limit to 26MHz on SM1 in U-boot until we 
> have all this
> clarified.
>
> Neil

Earlier I had a similar approach for this FIX but somehow it did not get merged.

Please add my
Tested-by: Anand Moon 

Best Regards
-Anand