[U-Boot] [v3 09/30] arm: socfpga: add define for bootinfo bsel bit shift
From: Tien Fong CheeOn arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- .../arm/mach-socfpga/include/mach/system_manager.h |2 ++ arch/arm/mach-socfpga/misc.c |4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index e688c50..9ca889a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -203,8 +203,10 @@ struct socfpga_system_manager { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 0 #else #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 12 #endif #define SYSMGR_SDMMC_DRVSEL_SHIFT 0 diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index c1e5969..2645129 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { + const u32 bsel = (readl(_regs->bootinfo) >> + SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7; #if defined(CONFIG_TARGET_SOCFPGA_GEN5) - const u32 bsel = readl(_regs->bootinfo) & 0x7; puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); #else - const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7; puts("CPU: Altera SoCFPGA Arria 10\n"); #endif printf("BOOT: %s\n", bsel_str[bsel].name); -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 08/30] arm: socfpga: arria10: add config option build for arria10
From: Tien Fong CheeSigned-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/Kconfig |4 ++-- arch/arm/mach-socfpga/Kconfig | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0ed36cd..80c5992 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON config ARCH_SOCFPGA bool "Altera SOCFPGA family" select CPU_V7 - select SUPPORT_SPL + select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10 select OF_CONTROL - select SPL_OF_CONTROL + select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10 select DM select DM_SPI_FLASH select DM_SPI diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 6991af8..d9a5178 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 +config TARGET_SOCFPGA_ARRIA10 + bool + config TARGET_SOCFPGA_CYCLONE5 bool select TARGET_SOCFPGA_GEN5 @@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_ARRIA10_SOCDK + bool "Altera SOCFPGA SoCDK (Arria 10)" + select TARGET_SOCFPGA_ARRIA10 + config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -86,6 +93,7 @@ endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC @@ -98,6 +106,7 @@ config SYS_BOARD config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES @@ -111,6 +120,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig
From: Tien Fong CheeAdd a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- configs/socfpga_arria10_defconfig | 16 1 files changed, 16 insertions(+), 0 deletions(-) create mode 100644 configs/socfpga_arria10_defconfig diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig new file mode 100644 index 000..422261b --- /dev/null +++ b/configs/socfpga_arria10_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_TARGET_SOCFPGA_ARRIA10=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config
From: Tien Fong CheeAdd config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- include/configs/socfpga_arria10_socdk.h | 94 +++ 1 files changed, 94 insertions(+), 0 deletions(-) create mode 100644 include/configs/socfpga_arria10_socdk.h diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h new file mode 100644 index 000..577f60f --- /dev/null +++ b/include/configs/socfpga_arria10_socdk.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__ +#define __CONFIG_SOCFGPA_ARRIA10_H__ + +#include +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING + +/* + * Memory configurations + */ +#define PHYS_SDRAM_1_SIZE 0x200 + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE"zImage" +#define CONFIG_BOOTARGS"console=ttyS0," __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_LOADADDR0x0100 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + +#endif + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */ +#define CONFIG_ENV_OFFSET 512/* just after the MBR */ + +/* + * arguments passed to the bootz command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include +#endif /* __CONFIG_H */ -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 04/30] arm: socfpga: arria10: add system manager defines
From: Tien Fong CheeAdd system manager defines for Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- .../arm/mach-socfpga/include/mach/system_manager.h | 122 1 files changed, 122 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index c45edea..e688c50 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable); void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) struct socfpga_system_manager { /* System Manager Module */ u32 siliconid1; /* 0x00 */ @@ -115,6 +116,77 @@ struct socfpga_system_manager { u32 _pad_0x734; u32 spim0usefpga; /* 0x738 */ }; +#else /* Arria10 System Manager */ +struct socfpga_system_manager { + u32 siliconid1; + u32 siliconid2; + u32 wddbg; + u32 bootinfo; + u32 mpu_ctrl_l2_ecc; + u32 _pad_0x14_0x1f[3]; + u32 dma; + u32 dma_periph; + u32 sdmmcgrp_ctrl; + u32 sdmmc_l3master; + u32 nand_bootstrap; + u32 nand_l3master; + u32 usb0_l3master; + u32 usb1_l3master; + u32 emac_global; + u32 emac0; + u32 emac1; + u32 emac2; + u32 _pad_0x50_0x5f[4]; + u32 fpgaintf_en_global; + u32 fpgaintf_en_0; + u32 fpgaintf_en_1; + u32 fpgaintf_en_2; + u32 fpgaintf_en_3; + u32 _pad_0x74_0x7f[3]; + u32 noc_addr_remap_value; + u32 noc_addr_remap_set; + u32 noc_addr_remap_clear; + u32 _pad_0x8c_0x8f; + u32 ecc_intmask_value; + u32 ecc_intmask_set; + u32 ecc_intmask_clr; + u32 ecc_intstatus_serr; + u32 ecc_intstatus_derr; + u32 mpu_status_l2_ecc; + u32 mpu_clear_l2_ecc; + u32 mpu_status_l1_parity; + u32 mpu_clear_l1_parity; + u32 mpu_set_l1_parity; + u32 _pad_0xb8_0xbf[2]; + u32 noc_timeout; + u32 noc_idlereq_set; + u32 noc_idlereq_clr; + u32 noc_idlereq_value; + u32 noc_idleack; + u32 noc_idlestatus; + u32 fpga2soc_ctrl; + u32 _pad_0xdc_0xff[9]; + u32 tsmc_tsel_0; + u32 tsmc_tsel_1; + u32 tsmc_tsel_2; + u32 tsmc_tsel_3; + u32 _pad_0x110_0x200[60]; + u32 romhw_ctrl; + u32 romcode_ctrl; + u32 romcode_cpu1startaddr; + u32 romcode_initswstate; + u32 romcode_initswlastld; + u32 _pad_0x214_0x217; + u32 warmram_enable; + u32 warmram_datastart; + u32 warmram_length; + u32 warmram_execution; + u32 warmram_crc; + u32 _pad_0x22c_0x22f; + u32 isw_handoff[8]; + u32 romcode_bootromswstate[8]; +}; +#endif #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1) @@ -146,4 +218,54 @@ struct socfpga_system_manager { #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3 +/* For dedicated IO configuration */ +/* Voltage select enums */ +#define VOLTAGE_SEL_3V 0x0 +#define VOLTAGE_SEL_1P8V 0x1 +#define VOLTAGE_SEL_2P5V 0x2 + +/* Input buffer enable */ +#define INPUT_BUF_DISABLE 0 +#define INPUT_BUF_1P8V 1 +#define INPUT_BUF_2P5V3V 2 + +/* Weak pull up enable */ +#define WK_PU_DISABLE 0 +#define WK_PU_ENABLE 1 + +/* Pull up slew rate control */ +#define PU_SLW_RT_SLOW 0 +#define PU_SLW_RT_FAST 1 +#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW + +/* Pull down slew rate control */ +#define PD_SLW_RT_SLOW 0 +#define PD_SLW_RT_FAST 1 +#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW + +/* Drive strength control */ +#define PU_DRV_STRG_DEFAULT0x10 +#define PD_DRV_STRG_DEFAULT0x10 + +/* bit position */ +#define PD_DRV_STRG_LSB0 +#define PD_SLW_RT_LSB 5 +#define PU_DRV_STRG_LSB8 +#define PU_SLW_RT_LSB 13 +#define WK_PU_LSB 16 +#define INPUT_BUF_LSB 17 +#define BIAS_TRIM_LSB 19 +#define VOLTAGE_SEL_LSB0 + +#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001 +#define ALT_SYSMGR_NOC_LWH2F_SET_MSK 0x0010 +#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100 +#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK 0x0001 +#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK 0x0010 +#define
[U-Boot] [v3 05/30] arm: socfpga: arria10: add misc functions for Arria10
From: Tien Fong CheeAdd arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/misc.c | 51 ++ 1 files changed, 51 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index dd6b53b..c1e5969 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; static struct socfpga_reset_manager *reset_manager_base = (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; +#else +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; +#endif static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; @@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) const u32 bsel = readl(_regs->bootinfo) & 0x7; puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); +#else + const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7; + puts("CPU: Altera SoCFPGA Arria 10\n"); +#endif printf("BOOT: %s\n", bsel_str[bsel].name); return 0; } @@ -338,6 +351,7 @@ int arch_cpu_init(void) return 0; } +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* * Convert all NIC-301 AMBA slaves from secure to non-secure */ @@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#else +/* ++ * This function initializes security policies to be consistent across ++ * all logic units in the Arria 10. ++ * ++ * The idea is to set all security policies to be normal, nonsecure ++ * for all units. ++ */ +static void initialize_security_policies(void) +{ + /* Put OCRAM in non-secure */ + writel(0x003f, _fw_ocram_base->region0); + writel(0x1, _fw_ocram_base->enable); + + /* Put DDR in non-secure */ + writel(0x, _fw_ddr_l3_base->hpsregion0addr); + writel(0x1, _fw_ddr_l3_base->enable); +} + +int arch_early_init_r(void) +{ + initialize_security_policies(); + + /* Configure the L2 controller to make SDRAM start at 0 */ + writel(0x1, >pl310_addr_filter_start); + + /* assert reset to all except L4WD0 and L4TIMER0 */ + socfpga_per_reset_all(); + + /* configuring the clock based on handoff */ + /* TODO: Add call to cm_basic_init() */ + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + return 0; +} +#endif U_BOOT_CMD( bridge, 2, 1, do_bridge, -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK
From: Tien Fong CheeAdd minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- board/altera/arria10-socdk/Kconfig | 18 ++ board/altera/arria10-socdk/Makefile |7 +++ board/altera/arria10-socdk/socfpga.c | 24 3 files changed, 49 insertions(+), 0 deletions(-) create mode 100644 board/altera/arria10-socdk/Kconfig create mode 100644 board/altera/arria10-socdk/Makefile create mode 100644 board/altera/arria10-socdk/socfpga.c diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig new file mode 100644 index 000..b80cc6d --- /dev/null +++ b/board/altera/arria10-socdk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SOCFPGA_ARRIA10 + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "socfpga_arria10" + +config SYS_VENDOR + default "altera" + +config SYS_SOC + default "socfpga_arria10" + +config SYS_CONFIG_NAME + default "socfpga_arria10" + +endif diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile new file mode 100644 index 000..1d885ce --- /dev/null +++ b/board/altera/arria10-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Altera Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c new file mode 100644 index 000..abedc22 --- /dev/null +++ b/board/altera/arria10-socdk/socfpga.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) +{ +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + return 0; +} -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10
From: Tien Fong CheeAdd remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Reviewed-by: Stefan Roese Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index a7056d4..902c321 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -29,6 +29,9 @@ #define SOCFPGA_MPUL2_ADDRESS 0xf000 #define SOCFPGA_I2C0_ADDRESS 0xffc02200 #define SOCFPGA_I2C1_ADDRESS 0xffc02300 +#define SOCFPGA_I2C2_ADDRESS 0xffc02400 +#define SOCFPGA_I2C3_ADDRESS 0xffc02500 +#define SOCFPGA_I2C4_ADDRESS 0xffc02600 #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 02/30] arm: socfpga: arria10: add sdram defines for Arria10
From: Tien Fong CheeAdd the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 1 files changed, 380 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h b/arch/arm/mach-socfpga/include/mach/sdram_a10.h new file mode 100644 index 000..0403531 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef_SOCFPGA_SDRAM_A10_H_ +#define_SOCFPGA_SDRAM_A10_H_ + +#ifndef __ASSEMBLY__ + +struct socfpga_ecc_hmc { + u32 ip_rev_id; + u32 _pad_0x4_0x7; + u32 ddrioctrl; + u32 ddrcalstat; + u32 mpr_0beat1; + u32 mpr_1beat1; + u32 mpr_2beat1; + u32 mpr_3beat1; + u32 mpr_4beat1; + u32 mpr_5beat1; + u32 mpr_6beat1; + u32 mpr_7beat1; + u32 mpr_8beat1; + u32 mpr_0beat2; + u32 mpr_1beat2; + u32 mpr_2beat2; + u32 mpr_3beat2; + u32 mpr_4beat2; + u32 mpr_5beat2; + u32 mpr_6beat2; + u32 mpr_7beat2; + u32 mpr_8beat2; + u32 _pad_0x58_0x5f[2]; + u32 auto_precharge; + u32 _pad_0x64_0xff[39]; + u32 eccctrl; + u32 eccctrl2; + u32 _pad_0x108_0x10f[2]; + u32 errinten; + u32 errintens; + u32 errintenr; + u32 intmode; + u32 intstat; + u32 diaginttest; + u32 modstat; + u32 derraddra; + u32 serraddra; + u32 _pad_0x134_0x137; + u32 autowb_corraddr; + u32 serrcntreg; + u32 autowb_drop_cntreg; + u32 _pad_0x144_0x147; + u32 ecc_reg2wreccdatabus; + u32 ecc_rdeccdata2regbus; + u32 ecc_reg2rdeccdatabus; + u32 _pad_0x154_0x15f[3]; + u32 ecc_diagon; + u32 ecc_decstat; + u32 _pad_0x168_0x16f[2]; + u32 ecc_errgenaddr_0; + u32 ecc_errgenaddr_1; + u32 ecc_errgenaddr_2; + u32 ecc_errgenaddr_3; +}; + +struct socfpga_noc_ddr_scheduler { + u32 ddr_t_main_scheduler_id_coreid; + u32 ddr_t_main_scheduler_id_revisionid; + u32 ddr_t_main_scheduler_ddrconf; + u32 ddr_t_main_scheduler_ddrtiming; + u32 ddr_t_main_scheduler_ddrmode; + u32 ddr_t_main_scheduler_readlatency; + u32 _pad_0x20_0x34[8]; + u32 ddr_t_main_scheduler_activate; + u32 ddr_t_main_scheduler_devtodev; +}; + +/* + * OCRAM firewall + */ +struct socfpga_noc_fw_ocram { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 region0; + u32 region1; + u32 region2; + u32 region3; + u32 region4; + u32 region5; +}; + +/* for master such as MPU and FPGA */ +struct socfpga_noc_fw_ddr_mpu_fpga2sdram { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 _pad_0xc_0xf; + u32 mpuregion0addr; + u32 mpuregion1addr; + u32 mpuregion2addr; + u32 mpuregion3addr; + u32 fpga2sdram0region0addr; + u32 fpga2sdram0region1addr; + u32 fpga2sdram0region2addr; + u32 fpga2sdram0region3addr; + u32 fpga2sdram1region0addr; + u32 fpga2sdram1region1addr; + u32 fpga2sdram1region2addr; + u32 fpga2sdram1region3addr; + u32 fpga2sdram2region0addr; + u32 fpga2sdram2region1addr; + u32 fpga2sdram2region2addr; + u32 fpga2sdram2region3addr; +}; + +/* for L3 master */ +struct socfpga_noc_fw_ddr_l3 { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 hpsregion0addr; + u32 hpsregion1addr; + u32 hpsregion2addr; + u32 hpsregion3addr; + u32 hpsregion4addr; + u32 hpsregion5addr; + u32 hpsregion6addr; + u32 hpsregion7addr; +}; + +struct socfpga_io48_mmr { + u32 dbgcfg0; + u32 dbgcfg1; + u32 dbgcfg2; + u32 dbgcfg3; + u32 dbgcfg4; + u32 dbgcfg5; + u32 dbgcfg6; + u32 reserve0; + u32 reserve1; + u32 reserve2; + u32 ctrlcfg0; + u32 ctrlcfg1; + u32 ctrlcfg2; + u32 ctrlcfg3; + u32 ctrlcfg4; + u32 ctrlcfg5; + u32 ctrlcfg6; + u32 ctrlcfg7; + u32 ctrlcfg8; + u32 ctrlcfg9; + u32 dramtiming0; + u32 dramodt0; + u32 dramodt1; + u32 sbcfg0; + u32 sbcfg1; + u32 sbcfg2; + u32 sbcfg3; + u32 sbcfg4; + u32 sbcfg5; + u32 sbcfg6; + u32 sbcfg7; + u32 caltiming0; + u32 caltiming1; + u32 caltiming2; + u32 caltiming3; + u32
Re: [U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
On Jum, 2016-12-30 at 06:14 -0600, Dinh Nguyen wrote: > > On 12/28/2016 12:34 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > This patch adding the Arria10 critical hardware initialization > > before > > enabling console print out in spl. > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vasut <ma...@denx.de> > > Cc: Dinh Nguyen <dingu...@kernel.org> > > Cc: Chin Liang See <chin.liang@intel.com> > > Cc: Tien Fong <skywind...@gmail.com> > > --- > > Changes for V2 > > - Release UART from reset before enalbing console, and reverting > > license > > changes. > > --- > > arch/arm/mach-socfpga/spl.c | 84 > > +++-- > > 1 file changed, 82 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach- > > socfpga/spl.c > > index fec4c7a..9e27f82 100644 > > --- a/arch/arm/mach-socfpga/spl.c > > +++ b/arch/arm/mach-socfpga/spl.c > > @@ -1,5 +1,5 @@ > > /* > > - * Copyright (C) 2012 Altera Corporation > > + * Copyright (C) 2012-2016 Altera Corporation > > * > > * SPDX-License-Identifier:GPL-2.0+ > > */ > > @@ -19,22 +19,32 @@ > > #include > > #include > > #include > > +#include > > +#include > > +#include > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > +#include > > +#endif > > > > DECLARE_GLOBAL_DATA_PTR; > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > static struct pl310_regs *const pl310 = > > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > > static struct scu_registers *scu_regs = > > (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; > > static struct nic301_registers *nic301_regs = > > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; > > -static struct socfpga_system_manager *sysmgr_regs = > > +#endif > > + > > +static const struct socfpga_system_manager *sysmgr_regs = > > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > > > u32 spl_boot_device(void) > > { > > const u32 bsel = readl(_regs->bootinfo); > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > switch (bsel & 0x7) { > > case 0x1: /* FPGA (HPS2FPGA Bridge) */ > > return BOOT_DEVICE_RAM; > > @@ -55,6 +65,24 @@ u32 spl_boot_device(void) > > printf("Invalid boot device (bsel=%08x)!\n", > > bsel); > > hang(); > > } > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > + switch ((bsel>>12) & 0x7) { > Spaces around the '>>'. > > > > > + case 0x1: /* FPGA (HPS2FPGA Bridge) */ > > + return BOOT_DEVICE_RAM; > > + case 0x2: /* NAND Flash (1.8V) */ > > + case 0x3: /* NAND Flash (3.0V) */ > > + return BOOT_DEVICE_NAND; > > + case 0x4: /* SD/MMC External Transceiver (1.8V) */ > > + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ > > + return BOOT_DEVICE_MMC1; > > + case 0x6: /* QSPI Flash (1.8V) */ > > + case 0x7: /* QSPI Flash (3.0V) */ > > + return BOOT_DEVICE_SPI; > > + default: > > + printf("Invalid boot device (bsel=%08x)!\n", > > bsel); > > + hang(); > > + } > > +#endif > > } > You missed my comment from V1: > > You should just do a shift define here, so you don't have to add > all > this extra code here. Something like > > switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) > Okay, noted. > > Dinh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL
On Jum, 2016-12-30 at 20:04 +0100, Marek Vasut wrote: > On 12/29/2016 05:54 AM, Chee, Tien Fong wrote: > > > > On Kha, 2016-12-29 at 00:51 +0100, Marek Vasut wrote: > > > > > > On 12/28/2016 07:34 AM, Chee Tien Fong wrote: > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > Enhanced defconfig file for Arria10 to enable SPL build and > > > > supporting > > > > device tree build for SDMMC. > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Cc: Marek Vasut <ma...@denx.de> > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > Cc: Tien Fong <skywind...@gmail.com> > > > > --- > > > > Changes for V2 > > > > - Removed boot header info setup since it already fixed in > > > > mainline > > > > --- > > > > configs/socfpga_arria10_defconfig | 18 +- > > > > 1 file changed, 13 insertions(+), 5 deletions(-) > > > There's no arria10 defconfig in mainline ? > > > I only received patches 18/30 and on ? > > > > > patch1 to patch17 are 01-arria10 rebase on u-boot.git, i believe > > those > > patches not CC to you orginally. Could you get from U-Boot Digest, > > Vol > > 103, Issue 53, or you want me to edit those patches CC to you? > No, you cannot get them from the digest, it's a digest after all. > I can get them from the list, but please always CC maintainers on > relevant patches. > Yeah, i think so. I re-send patch1 to patch17 last week, i believe you received all of them already. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10
From: Dinh NguyenOn the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset function to support both GEN5 and Arria10 devices. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/system_manager.h | 4 +--- arch/arm/mach-socfpga/misc.c| 14 ++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 9ca889a..831ba4a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -133,9 +133,7 @@ struct socfpga_system_manager { u32 usb0_l3master; u32 usb1_l3master; u32 emac_global; - u32 emac0; - u32 emac1; - u32 emac2; + u32 emac[3]; u32 _pad_0x50_0x5f[4]; u32 fpgaintf_en_global; u32 fpgaintf_en_0; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index c97caea..510aa1d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -21,7 +21,11 @@ #include #include +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include +#else +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id, } else if (of_reset_id == EMAC1_RESET) { physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; reset = SOCFPGA_RESET(EMAC1); +#ifndef CONFIG_TARGET_SOCFPGA_GEN5 + } else if (of_reset_id == EMAC2_RESET) { + reset = SOCFPGA_RESET(EMAC2); +#endif } else { printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); return; } +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* configure to PHY interface select choosed */ clrsetbits_le32(_regs->emacgrp_ctrl, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, phymode << physhift); +#else + clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET], + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + phymode); +#endif /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 16/30] arm: socfpga: add reset manager defines for Arria10
From: Dinh NguyenAdd the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++ 1 file changed, 103 insertions(+) create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h new file mode 100644 index 000..7619ca2 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET32 +#define EMAC1_RESET33 +#define EMAC2_RESET34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +#define QSPI_RESET 38 +#define SDMMC_RESET39 +#define EMAC0_OCP_RESET40 +#define EMAC1_OCP_RESET41 +#define EMAC2_OCP_RESET42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +#define QSPI_OCP_RESET 46 +#define SDMMC_OCP_RESET47 +#define DMA_RESET 48 +#define SPIM0_RESET49 +#define SPIM1_RESET50 +#define SPIS0_RESET51 +#define SPIS1_RESET52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define L4WD0_RESET64 +#define L4WD1_RESET65 +#define L4SYSTIMER0_RESET 66 +#define L4SYSTIMER1_RESET 67 +#define SPTIMER0_RESET 68 +#define SPTIMER1_RESET 69 +/* 70-71 is reserved */ +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is reserved */ +#define UART0_RESET80 +#define UART1_RESET81 +/* 82-87 is reserved */ +#define GPIO0_RESET88 +#define GPIO1_RESET89 +#define GPIO2_RESET90 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 +#define F2SSDRAM0_RESET99 +#define F2SSDRAM1_RESET100 +#define F2SSDRAM2_RESET101 +#define DDRSCH_RESET 102 + +/* SYSMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET129 +/* 130 is reserved */ +#define FPGAMGR_RESET 131 +#define S2F_RESET 132 +#define SYSDBG_RESET 133 +#define OCRAM_OCP_RESET134 + +/* COLDMODRST */ +#define CLKMGRCOLD_RESET 160 +/* 161-162 is reserved */ +#define S2FCOLD_RESET 163 +#define TIMESTAMPCOLD_RESET164 +#define TAPCOLD_RESET 165 +#define HMCCOLD_RESET 166 +#define IOMGRCOLD_RESET167 + +/* NRSTMODRST */ +#define NRSTPINOE_RESET192 + +/* DBGMODRST */ +#define DBG_RESET 224 +#endif -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits
From: Dinh NguyenThere is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 2645129..c97caea 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id, return; } - /* Clearing emac0 PHY interface select to 0 */ - clrbits_le32(_regs->emacgrp_ctrl, -SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); - /* configure to PHY interface select choosed */ - setbits_le32(_regs->emacgrp_ctrl, -phymode << physhift); + clrsetbits_le32(_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, + phymode << physhift); /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 14/30] arm: socfpga: arria10: remove board_init and s_init
From: Dinh NguyenThese functions are already in arch/arm/mach-socfpga/board.c Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/socfpga.c | 17 - 1 file changed, 17 deletions(-) diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c index abedc22..8516633 100644 --- a/board/altera/arria10-socdk/socfpga.c +++ b/board/altera/arria10-socdk/socfpga.c @@ -5,20 +5,3 @@ */ #include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) -{ -} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - return 0; -} -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 13/30] arm: socfpga: arria10 fpga does not have bridges mapped
From: Dinh NguyenOn the Arria10 device, the bridges are not mapped through the interconnect. Signed-off-by: Dinh Nguyen --- drivers/fpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index f1b2f2c..bfefafd 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(1); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Unmap the bridges from NIC-301 */ writel(0x1, SOCFPGA_L3REGS_ADDRESS); +#endif /* Initialize the FPGA Manager */ status = fpgamgr_program_init(); -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10
From: Dinh NguyenThe Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig. Signed-off-by: Dinh Nguyen --- drivers/Kconfig | 2 ++ drivers/ddr/Kconfig | 1 + drivers/ddr/altera/Kconfig | 6 ++ include/configs/socfpga_common.h | 5 - 4 files changed, 9 insertions(+), 5 deletions(-) create mode 100644 drivers/ddr/Kconfig create mode 100644 drivers/ddr/altera/Kconfig diff --git a/drivers/Kconfig b/drivers/Kconfig index e8c9e0a..0178498 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig" source "drivers/crypto/Kconfig" +source "drivers/ddr/Kconfig" + source "drivers/demo/Kconfig" source "drivers/dfu/Kconfig" diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig new file mode 100644 index 000..b764add --- /dev/null +++ b/drivers/ddr/Kconfig @@ -0,0 +1 @@ +source "drivers/ddr/altera/Kconfig" diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig new file mode 100644 index 000..9554da7 --- /dev/null +++ b/drivers/ddr/altera/Kconfig @@ -0,0 +1,6 @@ +config ALTERA_SDRAM + bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices" + default y if TARGET_SOCFPGA_GEN5 + help + This is for building the SDRAM controller for the Arria5/Cyclone5 + devices. diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 58a6550..f6a2f8d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -77,11 +77,6 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* - * SDRAM controller - */ -#define CONFIG_ALTERA_SDRAM - -/* * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 09/30] arm: socfpga: add define for bootinfo bsel bit shift
From: Dinh NguyenOn arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++ arch/arm/mach-socfpga/misc.c| 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index e688c50..9ca889a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -203,8 +203,10 @@ struct socfpga_system_manager { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 0 #else #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 12 #endif #define SYSMGR_SDMMC_DRVSEL_SHIFT 0 diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index c1e5969..2645129 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { + const u32 bsel = (readl(_regs->bootinfo) >> + SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7; #if defined(CONFIG_TARGET_SOCFPGA_GEN5) - const u32 bsel = readl(_regs->bootinfo) & 0x7; puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); #else - const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7; puts("CPU: Altera SoCFPGA Arria 10\n"); #endif printf("BOOT: %s\n", bsel_str[bsel].name); -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 08/30] arm: socfpga: arria10: add config option build for arria10
From: Dinh NguyenSigned-off-by: Dinh Nguyen --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-socfpga/Kconfig | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d871a45..74b769f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -554,9 +554,9 @@ config ARCH_SNAPDRAGON config ARCH_SOCFPGA bool "Altera SOCFPGA family" select CPU_V7 - select SUPPORT_SPL + select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10 select OF_CONTROL - select SPL_OF_CONTROL + select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10 select DM select DM_SPI_FLASH select DM_SPI diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 6991af8..d9a5178 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 +config TARGET_SOCFPGA_ARRIA10 + bool + config TARGET_SOCFPGA_CYCLONE5 bool select TARGET_SOCFPGA_GEN5 @@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_ARRIA10_SOCDK + bool "Altera SOCFPGA SoCDK (Arria 10)" + select TARGET_SOCFPGA_ARRIA10 + config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -86,6 +93,7 @@ endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC @@ -98,6 +106,7 @@ config SYS_BOARD config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES @@ -111,6 +120,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 10/30] arm: socfpga: arria10: add reset manager for Arria10
From: Dinh NguyenAdd the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++ arch/arm/mach-socfpga/reset_manager.c | 24 +++- 2 files changed, 88 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 2f070f2..6225118 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) struct socfpga_reset_manager { u32 status; u32 ctrl; @@ -28,6 +29,42 @@ struct socfpga_reset_manager { u32 padding2[12]; u32 tstscratch; }; +#else +struct socfpga_reset_manager { + u32 stat; + u32 ramstat; + u32 miscstat; + u32 ctrl; + u32 hdsken; + u32 hdskreq; + u32 hdskack; + u32 counts; + u32 mpu_mod_reset; + u32 per_mod_reset; /* stated as per0_mod_reset in A10 datasheet */ + u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */ + u32 brg_mod_reset; + u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */ + u32 coldmodrst; + u32 nrstmodrst; + u32 dbgmodrst; + u32 mpuwarmmask; + u32 per0warmmask; + u32 per1warmmask; + u32 brgwarmmask; + u32 syswarmmask; + u32 nrstwarmmask; + u32 l3warmmask; + u32 tststa; + u32 tstscratch; + u32 hdsktimeout; + u32 hmcintr; + u32 hmcintren; + u32 hmcintrens; + u32 hmcintrenr; + u32 hmcgpout; + u32 hmcgpin; +}; +#endif #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 @@ -55,6 +92,7 @@ struct socfpga_reset_manager { #define RSTMGR_BANK(_reset)\ (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: * 0 ... mpumodrst @@ -75,6 +113,33 @@ struct socfpga_reset_manager { #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) +#else +/* + * SocFPGA Arria10 reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... per0modrst + * 2 ... per1modrst + * 3 ... brgmodrst + * 4 ... sysmodrst + */ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) +#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2) +#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3) +#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4) +#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) +#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) +#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) +#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6) +#endif /* Create a human-readable reference to SoCFPGA reset. */ #define SOCFPGA_RESET(_name) RSTMGR_##_name diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index b6beaa2..d0ff6c4 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base = static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -/* Assert or de-assert SoCFPGA reset manager reset. */ +/* + * Assert or de-assert SoCFPGA reset manager reset. + */ void socfpga_per_reset(u32 reset, int set) { const void *reg; @@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set) * Assert reset on every peripheral but L4WD0. * Watchdog must be kept intact to prevent glitches * and/or hangs. + * For the Arria10, we disable all the peripherals except L4 watchdog0, + * L4 Timer 0, and ECC. */ void socfpga_per_reset_all(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); writel(~l4wd0, _manager_base->per_mod_reset);
[U-Boot] [PATCH v2 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices
From: Dinh NguyenThe system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/system_manager.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 75a65f3..9e1c3fd 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs = * The value is not wrote to SYSMGR.FPGAINTF.MODULE but * CONFIG_SYSMGR_ISWGRP_HANDOFF. */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void populate_sysmgr_fpgaintf_module(void) { uint32_t handoff_val = 0; @@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable) clrbits_le32(_regs->romcodegrp_ctrl, SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */ -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 05/30] arm: socfpga: arria10: add misc functions for Arria10
From: Dinh NguyenAdd arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 51 1 file changed, 51 insertions(+) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index dd6b53b..c1e5969 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; static struct socfpga_reset_manager *reset_manager_base = (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; +#else +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; +#endif static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; @@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) const u32 bsel = readl(_regs->bootinfo) & 0x7; puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); +#else + const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7; + puts("CPU: Altera SoCFPGA Arria 10\n"); +#endif printf("BOOT: %s\n", bsel_str[bsel].name); return 0; } @@ -338,6 +351,7 @@ int arch_cpu_init(void) return 0; } +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* * Convert all NIC-301 AMBA slaves from secure to non-secure */ @@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#else +/* ++ * This function initializes security policies to be consistent across ++ * all logic units in the Arria 10. ++ * ++ * The idea is to set all security policies to be normal, nonsecure ++ * for all units. ++ */ +static void initialize_security_policies(void) +{ + /* Put OCRAM in non-secure */ + writel(0x003f, _fw_ocram_base->region0); + writel(0x1, _fw_ocram_base->enable); + + /* Put DDR in non-secure */ + writel(0x, _fw_ddr_l3_base->hpsregion0addr); + writel(0x1, _fw_ddr_l3_base->enable); +} + +int arch_early_init_r(void) +{ + initialize_security_policies(); + + /* Configure the L2 controller to make SDRAM start at 0 */ + writel(0x1, >pl310_addr_filter_start); + + /* assert reset to all except L4WD0 and L4TIMER0 */ + socfpga_per_reset_all(); + + /* configuring the clock based on handoff */ + /* TODO: Add call to cm_basic_init() */ + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + return 0; +} +#endif U_BOOT_CMD( bridge, 2, 1, do_bridge, -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig
From: Dinh NguyenAdd a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- configs/socfpga_arria10_defconfig | 16 1 file changed, 16 insertions(+) create mode 100644 configs/socfpga_arria10_defconfig diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig new file mode 100644 index 000..422261b --- /dev/null +++ b/configs/socfpga_arria10_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_TARGET_SOCFPGA_ARRIA10=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 04/30] arm: socfpga: arria10: add system manager defines
From: Tien Fong CheeAdd system manager defines for Arria10. Signed-off-by: Dinh Nguyen --- .../arm/mach-socfpga/include/mach/system_manager.h | 122 + 1 file changed, 122 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index c45edea..e688c50 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable); void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) struct socfpga_system_manager { /* System Manager Module */ u32 siliconid1; /* 0x00 */ @@ -115,6 +116,77 @@ struct socfpga_system_manager { u32 _pad_0x734; u32 spim0usefpga; /* 0x738 */ }; +#else /* Arria10 System Manager */ +struct socfpga_system_manager { + u32 siliconid1; + u32 siliconid2; + u32 wddbg; + u32 bootinfo; + u32 mpu_ctrl_l2_ecc; + u32 _pad_0x14_0x1f[3]; + u32 dma; + u32 dma_periph; + u32 sdmmcgrp_ctrl; + u32 sdmmc_l3master; + u32 nand_bootstrap; + u32 nand_l3master; + u32 usb0_l3master; + u32 usb1_l3master; + u32 emac_global; + u32 emac0; + u32 emac1; + u32 emac2; + u32 _pad_0x50_0x5f[4]; + u32 fpgaintf_en_global; + u32 fpgaintf_en_0; + u32 fpgaintf_en_1; + u32 fpgaintf_en_2; + u32 fpgaintf_en_3; + u32 _pad_0x74_0x7f[3]; + u32 noc_addr_remap_value; + u32 noc_addr_remap_set; + u32 noc_addr_remap_clear; + u32 _pad_0x8c_0x8f; + u32 ecc_intmask_value; + u32 ecc_intmask_set; + u32 ecc_intmask_clr; + u32 ecc_intstatus_serr; + u32 ecc_intstatus_derr; + u32 mpu_status_l2_ecc; + u32 mpu_clear_l2_ecc; + u32 mpu_status_l1_parity; + u32 mpu_clear_l1_parity; + u32 mpu_set_l1_parity; + u32 _pad_0xb8_0xbf[2]; + u32 noc_timeout; + u32 noc_idlereq_set; + u32 noc_idlereq_clr; + u32 noc_idlereq_value; + u32 noc_idleack; + u32 noc_idlestatus; + u32 fpga2soc_ctrl; + u32 _pad_0xdc_0xff[9]; + u32 tsmc_tsel_0; + u32 tsmc_tsel_1; + u32 tsmc_tsel_2; + u32 tsmc_tsel_3; + u32 _pad_0x110_0x200[60]; + u32 romhw_ctrl; + u32 romcode_ctrl; + u32 romcode_cpu1startaddr; + u32 romcode_initswstate; + u32 romcode_initswlastld; + u32 _pad_0x214_0x217; + u32 warmram_enable; + u32 warmram_datastart; + u32 warmram_length; + u32 warmram_execution; + u32 warmram_crc; + u32 _pad_0x22c_0x22f; + u32 isw_handoff[8]; + u32 romcode_bootromswstate[8]; +}; +#endif #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1) @@ -146,4 +218,54 @@ struct socfpga_system_manager { #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3 +/* For dedicated IO configuration */ +/* Voltage select enums */ +#define VOLTAGE_SEL_3V 0x0 +#define VOLTAGE_SEL_1P8V 0x1 +#define VOLTAGE_SEL_2P5V 0x2 + +/* Input buffer enable */ +#define INPUT_BUF_DISABLE 0 +#define INPUT_BUF_1P8V 1 +#define INPUT_BUF_2P5V3V 2 + +/* Weak pull up enable */ +#define WK_PU_DISABLE 0 +#define WK_PU_ENABLE 1 + +/* Pull up slew rate control */ +#define PU_SLW_RT_SLOW 0 +#define PU_SLW_RT_FAST 1 +#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW + +/* Pull down slew rate control */ +#define PD_SLW_RT_SLOW 0 +#define PD_SLW_RT_FAST 1 +#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW + +/* Drive strength control */ +#define PU_DRV_STRG_DEFAULT0x10 +#define PD_DRV_STRG_DEFAULT0x10 + +/* bit position */ +#define PD_DRV_STRG_LSB0 +#define PD_SLW_RT_LSB 5 +#define PU_DRV_STRG_LSB8 +#define PU_SLW_RT_LSB 13 +#define WK_PU_LSB 16 +#define INPUT_BUF_LSB 17 +#define BIAS_TRIM_LSB 19 +#define VOLTAGE_SEL_LSB0 + +#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001 +#define ALT_SYSMGR_NOC_LWH2F_SET_MSK 0x0010 +#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100 +#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK 0x0001 +#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK 0x0010 +#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK 0x0100 +#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK 0x0001 + +#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK 0x0002 +#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK 0x0002 + #endif /*
[U-Boot] [PATCH v2 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config
From: Dinh NguyenAdd config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- include/configs/socfpga_arria10_socdk.h | 94 + 1 file changed, 94 insertions(+) create mode 100644 include/configs/socfpga_arria10_socdk.h diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h new file mode 100644 index 000..577f60f --- /dev/null +++ b/include/configs/socfpga_arria10_socdk.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__ +#define __CONFIG_SOCFGPA_ARRIA10_H__ + +#include +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING + +/* + * Memory configurations + */ +#define PHYS_SDRAM_1_SIZE 0x200 + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE"zImage" +#define CONFIG_BOOTARGS"console=ttyS0," __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_LOADADDR0x0100 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + +#endif + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */ +#define CONFIG_ENV_OFFSET 512/* just after the MBR */ + +/* + * arguments passed to the bootz command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include +#endif /* __CONFIG_H */ -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK
From: Dinh NguyenAdd minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/Kconfig | 18 ++ board/altera/arria10-socdk/Makefile | 7 +++ board/altera/arria10-socdk/socfpga.c | 24 3 files changed, 49 insertions(+) create mode 100644 board/altera/arria10-socdk/Kconfig create mode 100644 board/altera/arria10-socdk/Makefile create mode 100644 board/altera/arria10-socdk/socfpga.c diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig new file mode 100644 index 000..b80cc6d --- /dev/null +++ b/board/altera/arria10-socdk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SOCFPGA_ARRIA10 + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "socfpga_arria10" + +config SYS_VENDOR + default "altera" + +config SYS_SOC + default "socfpga_arria10" + +config SYS_CONFIG_NAME + default "socfpga_arria10" + +endif diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile new file mode 100644 index 000..1d885ce --- /dev/null +++ b/board/altera/arria10-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Altera Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c new file mode 100644 index 000..abedc22 --- /dev/null +++ b/board/altera/arria10-socdk/socfpga.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) +{ +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + return 0; +} -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10
From: Dinh NguyenAdd remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen Reviewed-by: Stefan Roese --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index a7056d4..902c321 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -29,6 +29,9 @@ #define SOCFPGA_MPUL2_ADDRESS 0xf000 #define SOCFPGA_I2C0_ADDRESS 0xffc02200 #define SOCFPGA_I2C1_ADDRESS 0xffc02300 +#define SOCFPGA_I2C2_ADDRESS 0xffc02400 +#define SOCFPGA_I2C3_ADDRESS 0xffc02500 +#define SOCFPGA_I2C4_ADDRESS 0xffc02600 #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/30] arm: socfpga: arria10: add sdram defines for Arria10
From: Dinh NguyenAdd the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 + 1 file changed, 380 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h b/arch/arm/mach-socfpga/include/mach/sdram_a10.h new file mode 100644 index 000..0403531 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef_SOCFPGA_SDRAM_A10_H_ +#define_SOCFPGA_SDRAM_A10_H_ + +#ifndef __ASSEMBLY__ + +struct socfpga_ecc_hmc { + u32 ip_rev_id; + u32 _pad_0x4_0x7; + u32 ddrioctrl; + u32 ddrcalstat; + u32 mpr_0beat1; + u32 mpr_1beat1; + u32 mpr_2beat1; + u32 mpr_3beat1; + u32 mpr_4beat1; + u32 mpr_5beat1; + u32 mpr_6beat1; + u32 mpr_7beat1; + u32 mpr_8beat1; + u32 mpr_0beat2; + u32 mpr_1beat2; + u32 mpr_2beat2; + u32 mpr_3beat2; + u32 mpr_4beat2; + u32 mpr_5beat2; + u32 mpr_6beat2; + u32 mpr_7beat2; + u32 mpr_8beat2; + u32 _pad_0x58_0x5f[2]; + u32 auto_precharge; + u32 _pad_0x64_0xff[39]; + u32 eccctrl; + u32 eccctrl2; + u32 _pad_0x108_0x10f[2]; + u32 errinten; + u32 errintens; + u32 errintenr; + u32 intmode; + u32 intstat; + u32 diaginttest; + u32 modstat; + u32 derraddra; + u32 serraddra; + u32 _pad_0x134_0x137; + u32 autowb_corraddr; + u32 serrcntreg; + u32 autowb_drop_cntreg; + u32 _pad_0x144_0x147; + u32 ecc_reg2wreccdatabus; + u32 ecc_rdeccdata2regbus; + u32 ecc_reg2rdeccdatabus; + u32 _pad_0x154_0x15f[3]; + u32 ecc_diagon; + u32 ecc_decstat; + u32 _pad_0x168_0x16f[2]; + u32 ecc_errgenaddr_0; + u32 ecc_errgenaddr_1; + u32 ecc_errgenaddr_2; + u32 ecc_errgenaddr_3; +}; + +struct socfpga_noc_ddr_scheduler { + u32 ddr_t_main_scheduler_id_coreid; + u32 ddr_t_main_scheduler_id_revisionid; + u32 ddr_t_main_scheduler_ddrconf; + u32 ddr_t_main_scheduler_ddrtiming; + u32 ddr_t_main_scheduler_ddrmode; + u32 ddr_t_main_scheduler_readlatency; + u32 _pad_0x20_0x34[8]; + u32 ddr_t_main_scheduler_activate; + u32 ddr_t_main_scheduler_devtodev; +}; + +/* + * OCRAM firewall + */ +struct socfpga_noc_fw_ocram { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 region0; + u32 region1; + u32 region2; + u32 region3; + u32 region4; + u32 region5; +}; + +/* for master such as MPU and FPGA */ +struct socfpga_noc_fw_ddr_mpu_fpga2sdram { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 _pad_0xc_0xf; + u32 mpuregion0addr; + u32 mpuregion1addr; + u32 mpuregion2addr; + u32 mpuregion3addr; + u32 fpga2sdram0region0addr; + u32 fpga2sdram0region1addr; + u32 fpga2sdram0region2addr; + u32 fpga2sdram0region3addr; + u32 fpga2sdram1region0addr; + u32 fpga2sdram1region1addr; + u32 fpga2sdram1region2addr; + u32 fpga2sdram1region3addr; + u32 fpga2sdram2region0addr; + u32 fpga2sdram2region1addr; + u32 fpga2sdram2region2addr; + u32 fpga2sdram2region3addr; +}; + +/* for L3 master */ +struct socfpga_noc_fw_ddr_l3 { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 hpsregion0addr; + u32 hpsregion1addr; + u32 hpsregion2addr; + u32 hpsregion3addr; + u32 hpsregion4addr; + u32 hpsregion5addr; + u32 hpsregion6addr; + u32 hpsregion7addr; +}; + +struct socfpga_io48_mmr { + u32 dbgcfg0; + u32 dbgcfg1; + u32 dbgcfg2; + u32 dbgcfg3; + u32 dbgcfg4; + u32 dbgcfg5; + u32 dbgcfg6; + u32 reserve0; + u32 reserve1; + u32 reserve2; + u32 ctrlcfg0; + u32 ctrlcfg1; + u32 ctrlcfg2; + u32 ctrlcfg3; + u32 ctrlcfg4; + u32 ctrlcfg5; + u32 ctrlcfg6; + u32 ctrlcfg7; + u32 ctrlcfg8; + u32 ctrlcfg9; + u32 dramtiming0; + u32 dramodt0; + u32 dramodt1; + u32 sbcfg0; + u32 sbcfg1; + u32 sbcfg2; + u32 sbcfg3; + u32 sbcfg4; + u32 sbcfg5; + u32 sbcfg6; + u32 sbcfg7; + u32 caltiming0; + u32 caltiming1; + u32 caltiming2; + u32 caltiming3; + u32 caltiming4; + u32 caltiming5; + u32 caltiming6; + u32 caltiming7; + u32 caltiming8; + u32 caltiming9; + u32 caltiming10; + u32 dramaddrw; + u32 sideband0; + u32 sideband1; +
[U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
From: Tien Fong CheeThis patch adding the Arria10 critical hardware initialization before enabling console print out in spl. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Release UART from reset before enalbing console, and reverting license changes. --- arch/arm/mach-socfpga/spl.c | 84 +++-- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index fec4c7a..9e27f82 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2016 Altera Corporation * * SPDX-License-Identifier:GPL-2.0+ */ @@ -19,22 +19,32 @@ #include #include #include +#include +#include +#include +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include +#endif DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = +#endif + +static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; u32 spl_boot_device(void) { const u32 bsel = readl(_regs->bootinfo); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) switch (bsel & 0x7) { case 0x1: /* FPGA (HPS2FPGA Bridge) */ return BOOT_DEVICE_RAM; @@ -55,6 +65,24 @@ u32 spl_boot_device(void) printf("Invalid boot device (bsel=%08x)!\n", bsel); hang(); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + switch ((bsel>>12) & 0x7) { + case 0x1: /* FPGA (HPS2FPGA Bridge) */ + return BOOT_DEVICE_RAM; + case 0x2: /* NAND Flash (1.8V) */ + case 0x3: /* NAND Flash (3.0V) */ + return BOOT_DEVICE_NAND; + case 0x4: /* SD/MMC External Transceiver (1.8V) */ + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ + return BOOT_DEVICE_MMC1; + case 0x6: /* QSPI Flash (1.8V) */ + case 0x7: /* QSPI Flash (3.0V) */ + return BOOT_DEVICE_SPI; + default: + printf("Invalid boot device (bsel=%08x)!\n", bsel); + hang(); + } +#endif } #ifdef CONFIG_SPL_MMC_SUPPORT @@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void socfpga_nic301_slave_ns(void) { writel(0x1, _regs->lwhps2fpgaregs); @@ -182,3 +211,54 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +void board_init_f(ulong dummy) +{ + memset(__bss_start, 0, __bss_end - __bss_start); + /* +* Configure Clock Manager to use intosc clock instead external osc to +* ensure success watchdog operation. We do it as early as possible. +*/ + cm_use_intosc(); + + watchdog_disable(); + + arch_early_init_r(); + +#ifdef CONFIG_HW_WATCHDOG + /* release osc1 watchdog timer 0 from reset */ + reset_deassert_osc1wd0(); + + /* reconfigure and enable the watchdog */ + hw_watchdog_init(); + WATCHDOG_RESET(); +#endif /* CONFIG_HW_WATCHDOG */ + +#ifdef CONFIG_OF_CONTROL + /* We need to access to FDT as this stage */ + /* FDT is at end of image */ + gd->fdt_blob = (void *)(__bss_end); + /* Check whether we have a valid FDT or not. */ + if (fdtdec_prepare_fdt()) { + panic("** CONFIG_OF_CONTROL defined but no FDT - please see " + "doc/README.fdt-control"); + } +#endif /* CONFIG_OF_CONTROL */ + + /* Initialize the timer */ + timer_init(); + + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + WATCHDOG_RESET(); + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); + + /* Release UART from reset */ + reset_deassert_uart(); + + /* enable console uart printing */ + preloader_console_init(); +} +#endif -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 30/30] arm: socfpga: arria10: Enable fpga driver build for SPL.
From: Tien Fong CheeSigned-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - resolved build error of undefined some functions in fpga driver for SPL build --- drivers/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/Makefile b/drivers/Makefile index c19fa14..c15796b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)PINCTRL)+= pinctrl/ obj-$(CONFIG_$(SPL_)RAM) += ram/ ifdef CONFIG_SPL_BUILD - +obj-$(CONFIG_FPGA) += fpga/ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/ obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/ -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration
From: Tien Fong CheeSigned-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Removed extern declaration. --- arch/arm/mach-socfpga/include/mach/pinmux.h | 17 + arch/arm/mach-socfpga/pinmux.c | 104 2 files changed, 121 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h create mode 100644 arch/arm/mach-socfpga/pinmux.c diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h b/arch/arm/mach-socfpga/include/mach/pinmux.h new file mode 100644 index 000..ff54caa --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/pinmux.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef_PINMUX_H_ +#define_PINMUX_H_ + +#ifndef __ASSEMBLY__ +int config_dedicated_pins(const void *blob); +int config_pins(const void *blob, const char *pin_grp); +#endif + + + +#endif /* _PINMUX_H_ */ diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c new file mode 100644 index 000..d45722f --- /dev/null +++ b/arch/arm/mach-socfpga/pinmux.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016 Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include +#include +#include + +int config_dedicated_pins(const void *blob); +int config_pins(const void *blob, const char *pin_grp); +static int __do_pinctr_pins(const void *blob, int child, const char *node_name); +static int do_pinctrl_pins(const void *blob, int node, const char *child_name); + +static int __do_pinctr_pins(const void *blob, int child, const char *node_name) +{ + int len; + fdt_addr_t base_addr; + fdt_size_t size; + const u32 *cell; + u32 offset, value; + + base_addr = fdtdec_get_addr_size(blob, child, "reg", ); + if (base_addr != FDT_ADDR_T_NONE) { + cell = fdt_getprop(blob, child, "pinctrl-single,pins", + ); + if (cell != NULL) { + debug("%p %d\n", cell, len); + for (;len > 0; len -= (2*sizeof(u32))) { + offset = fdt32_to_cpu(*cell++); + value = fdt32_to_cpu(*cell++); + debug("<0x%x 0x%x>\n", offset, value); + writel(value, base_addr + offset); + } + return 0; + } + } + return 1; +} + +static int do_pinctrl_pins(const void *blob, int node, const char *child_name) +{ + int child, len; + const char *node_name; + + child = fdt_first_subnode(blob, node); + + if (child < 0) + return 2; + + node_name = fdt_get_name(blob, child, ); + + while (node_name) { + if (!strcmp(child_name, node_name)) { + __do_pinctr_pins(blob, child, node_name); + return(0); + } + child = fdt_next_subnode(blob, child); + + if (child < 0) + break; + + node_name = fdt_get_name(blob, child, ); + } + + return 1; +} + +int config_dedicated_pins(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return 1; + + if (do_pinctrl_pins(blob, node, "dedicated_cfg")) + return 2; + + if (do_pinctrl_pins(blob, node, "dedicated")) + return 3; + + return 0; +} + +int config_pins(const void *blob, const char *pin_grp) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return 1; + + if (do_pinctrl_pins(blob, node, pin_grp)) + return 2; + + return 0; +} -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 26/30] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10
From: Tien Fong CheeThe drivers is restructured such common functions, gen5 functions. and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ching Liang See Cc: Tien Fong --- Changes for V2 - Populating base address of UART based on handoff setting. --- arch/arm/mach-socfpga/Makefile| 6 +- arch/arm/mach-socfpga/include/mach/misc.h | 32 ++ arch/arm/mach-socfpga/misc.c | 427 +- arch/arm/mach-socfpga/misc_arria10.c | 255 +++ arch/arm/mach-socfpga/{misc.c => misc_gen5.c} | 232 ++ 5 files changed, 337 insertions(+), 615 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h create mode 100644 arch/arm/mach-socfpga/misc_arria10.c copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (66%) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index b8fcf6e..1ab68be 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,9 +9,11 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o board.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o \ + clock_manager_arria10.o pinmux.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ - reset_manager_gen5.o + reset_manager_gen5.o misc_gen5.o \ + clock_manager_gen5.o ifdef CONFIG_SPL_BUILD obj-y += spl.o diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h new file mode 100644 index 000..045268d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016, Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _MISC_H_ +#define_MISC_H_ + +extern void dwmac_deassert_reset(const unsigned int of_reset_id, +const u32 phymode); + +struct bsel{ + const char *mode; + const char *name; +}; + +extern struct bsel bsel_str[]; + +#ifdef CONFIG_FPGA +extern void socfpga_fpga_add(void); +#else +inline void socfpga_fpga_add(void) {} +#endif + +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +unsigned int dedicated_uart_com_port(const void *blob); +unsigned int shared_uart_com_port(const void *blob); +unsigned int uart_com_port(const void *blob); +#endif + +#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 510aa1d..7fd5c0e 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2016 Altera Corporation * * SPDX-License-Identifier:GPL-2.0+ */ @@ -7,45 +7,33 @@ #include #include #include -#include -#include #include #include #include #include +#include #include -#include #include #include #include #include #include -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#include -#else -#include -#endif - DECLARE_GLOBAL_DATA_PTR; -static struct pl310_regs *const pl310 = +static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_reset_manager *reset_manager_base = - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -static struct nic301_registers *nic301_regs = - (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -#else -static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = - (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; -static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = - (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; -#endif -static struct scu_registers *scu_regs = - (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; + +struct bselbsel_str[] = { + { "rsvd", "Reserved", }, + { "fpga", "FPGA (HPS2FPGA Bridge)", }, + { "nand", "NAND Flash (1.8V)", }, + { "nand", "NAND Flash (3.0V)", }, + { "sd", "SD/MMC External Transceiver (1.8V)", }, + { "sd", "SD/MMC Internal Transceiver (3.0V)", }, + { "qspi", "QSPI Flash (1.8V)", }, + { "qspi", "QSPI Flash (3.0V)", }, +}; int dram_init(void) { @@ -84,219 +72,6 @@ void v7_outer_cache_disable(void) clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN); } -/* - * DesignWare Ethernet initialization - */ -#ifdef CONFIG_ETH_DESIGNWARE -static void dwmac_deassert_reset(const unsigned
[U-Boot] [PATCH v2 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
From: Tien Fong CheeDrivers for reset manager is restructured such that common functions, gen5 drivers and Arria10 drivers are moved to reset_manager.c, reset_manager_gen5.c and reset_manager_arria10.c respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Reverted license changes, removing extern and volatile declaration --- arch/arm/mach-socfpga/Makefile | 16 +- arch/arm/mach-socfpga/include/mach/reset_manager.h | 155 ++-- arch/arm/mach-socfpga/reset_manager.c | 112 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 407 + .../{reset_manager.c => reset_manager_gen5.c} | 94 ++--- 5 files changed, 570 insertions(+), 214 deletions(-) create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 809cd47..b8fcf6e 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -2,21 +2,27 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, w...@denx.de. # -# Copyright (C) 2012 Altera Corporation +# Copyright (C) 2012-2016 Altera Corporation # # SPDX-License-Identifier: GPL-2.0+ # obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o board.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ + reset_manager_gen5.o -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \ + wrap_pinmux_config.o wrap_sdram_config.o +endif +ifdef CONFIG_TARGET_SOCFPGA_GEN5 # QTS-generated config file wrappers -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\ - wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR) +endif diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 6225118..13f9731 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2016 Altera Corporation * * SPDX-License-Identifier:GPL-2.0+ */ @@ -7,15 +7,27 @@ #ifndef_RESET_MANAGER_H_ #define_RESET_MANAGER_H_ +/* Common function prototypes */ void reset_cpu(ulong addr); -void reset_deassert_peripherals_handoff(void); - void socfpga_bridges_reset(int enable); - void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); #if defined(CONFIG_TARGET_SOCFPGA_GEN5) +void reset_deassert_peripherals_handoff(void); +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +void watchdog_disable(void); +void reset_deassert_noc_ddr_scheduler(void); +int is_wdt_in_reset(void); +void emac_manage_reset(ulong emacbase, uint state); +int reset_deassert_bridges_handoff(void); +void reset_assert_fpga_connected_peripherals(void); +void reset_deassert_osc1wd0(void); +void reset_assert_uart(void); +void reset_deassert_uart(void); +#endif + +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) struct socfpga_reset_manager { u32 status; u32 ctrl; @@ -29,40 +41,40 @@ struct socfpga_reset_manager { u32 padding2[12]; u32 tstscratch; }; -#else +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) struct socfpga_reset_manager { - u32 stat; - u32 ramstat; - u32 miscstat; - u32 ctrl; - u32 hdsken; - u32 hdskreq; - u32 hdskack; - u32 counts; - u32 mpu_mod_reset; - u32 per_mod_reset; /* stated as per0_mod_reset in A10 datasheet */ - u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */ - u32 brg_mod_reset; - u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */ - u32 coldmodrst; - u32 nrstmodrst; - u32 dbgmodrst; - u32 mpuwarmmask; - u32 per0warmmask; - u32 per1warmmask; - u32 brgwarmmask; - u32 syswarmmask; - u32 nrstwarmmask; - u32 l3warmmask; - u32 tststa; - u32
[U-Boot] [PATCH v2 27/30] arm: socfpga: arria10: Added drivers for Arria10 clock manager
From: Tien Fong CheeThe drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, clock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ching Liang See Cc: Tien Fong --- Changes for V2 - Reverted license changes, removing extern and volatile declaration. --- arch/arm/mach-socfpga/clock_manager.c | 752 +++- arch/arm/mach-socfpga/clock_manager_arria10.c | 954 + .../{clock_manager.c => clock_manager_gen5.c} | 240 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++-- 4 files changed, 1573 insertions(+), 729 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%) diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index aa71636..d209f7d 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013-2016 Altera Corporation * * SPDX-License-Identifier:GPL-2.0+ */ @@ -7,416 +7,287 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +/* Function prototypes */ +/* Common prototypes */ +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); +static void cm_print_clock_quick_summary(void); +int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +void cm_wait_for_lock(uint32_t mask); +void cm_wait_for_fsm(void); +unsigned int cm_get_main_vco_clk_hz(void); +unsigned int cm_get_per_vco_clk_hz(void); +unsigned long cm_get_mpu_clk_hz(void); + static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; -static void cm_wait_for_lock(uint32_t mask) +/* Common functions */ +int set_cpu_clk_info(void) { - register uint32_t inter_val; - uint32_t retry = 0; - do { - inter_val = readl(_manager_base->inter) & mask; - if (inter_val == mask) - retry++; - else - retry = 0; - if (retry >= 10) - break; - } while (1); -} + /* Calculate the clock frequencies required for drivers */ + cm_get_l4_sp_clk_hz(); + cm_get_mmc_controller_clk_hz(); -/* function to poll in the fsm busy bit */ -static void cm_wait_for_fsm(void) -{ - while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY) - ; -} + gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100; + gd->bd->bi_dsp_freq = 0; -/* - * function to write the bypass register which requires a poll of the - * busy bit - */ -static void cm_write_bypass(uint32_t val) -{ - writel(val, _manager_base->bypass); - cm_wait_for_fsm(); -} +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) + gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100; +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + gd->bd->bi_ddr_freq = 0; +#endif -/* function to write the ctrl register which requires a poll of the busy bit */ -static void cm_write_ctrl(uint32_t val) -{ - writel(val, _manager_base->ctrl); - cm_wait_for_fsm(); + return 0; } -/* function to write a clock register that has phase information */ -static void cm_write_with_phase(uint32_t value, - uint32_t reg_address, uint32_t mask) +unsigned int cm_get_spi_controller_clk_hz(void) { - /* poll until phase is zero */ - while (readl(reg_address) & mask) - ; + uint32_t clock = 0; - writel(value, reg_address); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) + uint32_t reg; + clock = cm_get_per_vco_clk_hz(); - while (readl(reg_address) & mask) - ; -} + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); +#endif -/* - * Setup clocks while making no assumptions about previous state of the clocks. - * - * Start by being paranoid and gate all sw managed clocks - * Put all plls in bypass - * Put all plls VCO registers back to reset value (bandgap power down). - * Put peripheral and main pll src to reset value to avoid glitch. - * Delay 5 us. - * Deassert bandgap power down and set numerator and denominator - * Start 7 us timer. - * set internal dividers - * Wait for 7 us timer. - * Enable
[U-Boot] [PATCH v2 22/30] arm: socfpga: arria10: Added clock manager and pin mux compat macro
From: Tien Fong CheeThese compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Added only compat strings with matching drivers in this series patches --- include/fdtdec.h | 8 lib/fdtdec.c | 8 2 files changed, 16 insertions(+) diff --git a/include/fdtdec.h b/include/fdtdec.h index d074478..73e3a46 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -155,6 +155,14 @@ enum fdt_compat_id { COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* pinctrl-single */ + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* Arria10 hps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 lwhps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* Arria10 fpga2hps bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* Arria10 fpga2SDRAM0 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* Arria10 fpga2SDRAM1 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* Arria10 fpga2SDRAM2 bridge */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 81f47ef..ebe4a9a 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), + COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"), + COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"), + COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"), + COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"), + COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"), + COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"), + COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"), + COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 24/30] arm: socfpga: arria10: Added support for Arria 10 socdk
From: Tien Fong CheeSigned-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Separate patch, reuse socfpga_common.h --- arch/arm/mach-socfpga/system_manager.c | 4 ++- drivers/fpga/socfpga.c | 7 +++-- include/configs/socfpga_arria10_socdk.h | 56 - include/configs/socfpga_common.h| 33 --- 4 files changed, 71 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 9e1c3fd..e1f0082 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013-2016 Altera Corporation * * SPDX-License-Identifier:GPL-2.0+ */ @@ -11,8 +11,10 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif /* * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index bfefafd..7fd922e 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2016 Altera Corporation * All rights reserved. * * SPDX-License-Identifier:BSD-3-Clause @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif /* Set CD ratio */ static void fpgamgr_set_cd_ratio(unsigned long ratio) @@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) } /* Prior programming the FPGA, all bridges need to be shut off */ - +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Disable all signals from hps peripheral controller to fpga */ writel(0, _regs->fpgaintfgrp_module); +#endif /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080 diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 577f60f..105c4c0 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Altera Corporation + * Copyright (C) 2015-2016 Altera Corporation * * SPDX-License-Identifier:GPL-2.0 */ @@ -8,31 +8,20 @@ #define __CONFIG_SOCFGPA_ARRIA10_H__ #include + /* U-Boot Commands */ -#define CONFIG_SYS_NO_FLASH #define CONFIG_DOS_PARTITION #define CONFIG_FAT_WRITE #define CONFIG_HW_WATCHDOG #define CONFIG_CMD_ASKENV #define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MMC #define CONFIG_CMD_PING -/* - * Memory configurations - */ -#define PHYS_SDRAM_1_SIZE 0x200 - /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE"zImage" #define CONFIG_BOOTARGS"console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" @@ -40,24 +29,30 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* - * Display CPU and Board Info + * U-Boot general configurations + */ +/* Cache options */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE + +/* + * U-Boot console configurations */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DOS_PARTITION + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x8000 /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9031 - #endif +/* + * U-Boot environment configurations + */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */ -#define CONFIG_ENV_OFFSET 512/* just after the MBR */ /* * arguments passed to the bootz command. The value of @@ -89,6 +84,23 @@ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ "bootm ${loadaddr} - ${fdt_addr}\0" +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * L4 OSC1 Timer 0 + */ +/* reload value when timer count to zero */
[U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL
From: Tien Fong CheeEnhanced defconfig file for Arria10 to enable SPL build and supporting device tree build for SDMMC. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Removed boot header info setup since it already fixed in mainline --- configs/socfpga_arria10_defconfig | 18 +- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 422261b..755bb66 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_TARGET_SOCFPGA_ARRIA10=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" +CONFIG_IDENT_STRING="socfpga_arria10" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_DWAPB_GPIO=y -CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_CMD_MMC=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL=y +CONFIG_SPL_DM=y +CONFIG_SPL_SIMPLE_BUS=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_OF_LIBFDT=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 20/30] arm: socfpga: arria10: Enable SPL for Arria 10
From: Tien Fong CheeThis patch enables SPL build and implementation for Arria 10. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Commit messages changed. --- arch/arm/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 74b769f..d871a45 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -554,9 +554,9 @@ config ARCH_SNAPDRAGON config ARCH_SOCFPGA bool "Altera SOCFPGA family" select CPU_V7 - select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10 + select SUPPORT_SPL select OF_CONTROL - select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10 + select SPL_OF_CONTROL select DM select DM_SPI_FLASH select DM_SPI -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10
From: Tien Fong CheeSigned-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- changes for v2 - Separate patch for adding some HW base address for Arria 10. --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index 902c321..2d66580 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Altera Corporation + * Copyright (C) 2014-2016 Altera Corporation * * SPDX-License-Identifier:GPL-2.0+ */ @@ -36,10 +36,13 @@ #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SDR_ADDRESS0xffcfb000 +#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000 +#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300 -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 19/30] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc
From: Tien Fong CheeThis is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - modified the handoff.dtsi to board specific, and moving some chosen config to handoff.dtsi because these config would be generated by tool --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/socfpga_arria10.dtsi | 859 + arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 30 + .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 479 4 files changed, 1370 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/socfpga_arria10.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3ee608b..024aa5f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -137,7 +137,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ - socfpga_cyclone5_vining_fpga.dtb + socfpga_cyclone5_vining_fpga.dtb\ + socfpga_arria10_socdk_sdmmc.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ dra72-evm-revc.dtb dra71-evm.dtb diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi new file mode 100644 index 000..f63c4b4 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -0,0 +1,859 @@ +/* + * Copyright (C) 2016 Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include "skeleton.dtsi" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = + ethernet1 = + ethernet2 = + serial0 = + serial1 = + timer0 = + timer1 = + timer2 = + timer3 = + spi0 = + spi1 = + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x4000>; /* 1GB */ + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <>; + }; + }; + + intc: intc@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <>; + ranges; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffda1000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda1000 0x1000>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, +<0 84 IRQ_TYPE_LEVEL_HIGH>, +<0 85 IRQ_TYPE_LEVEL_HIGH>, +<0 86 IRQ_TYPE_LEVEL_HIGH>, +<0 87 IRQ_TYPE_LEVEL_HIGH>, +<0 88 IRQ_TYPE_LEVEL_HIGH>, +<0 89 IRQ_TYPE_LEVEL_HIGH>, +<0 90 IRQ_TYPE_LEVEL_HIGH>, +<0 91 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <_main_clk>; + clock-names = "apb_pclk"; + }; + }; + +
[U-Boot] [PATCH v2 18/30] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address
From: Chin Liang SeeAdd base address header file for Stratix10 SoC Signed-off-by: Chin Liang See Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++ 1 file changed, 48 insertions(+) create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file mode 100755 index 000..411518d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016, Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ +#define _SOCFPGA_S10_BASE_HARDWARE_H_ + +#define SOCFPGA_SMMU_ADDRESS 0xfa00 +#define SOCFPGA_EMAC0_ADDRESS 0xff80 +#define SOCFPGA_EMAC1_ADDRESS 0xff802000 +#define SOCFPGA_EMAC2_ADDRESS 0xff804000 +#define SOCFPGA_SDMMC_ADDRESS 0xff808000 +#define SOCFPGA_USB0_ADDRESS 0xffb0 +#define SOCFPGA_USB1_ADDRESS 0xffb4 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb8 +#define SOCFPGA_NANDDATA_ADDRESS 0xffb9 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_I2C0_ADDRESS 0xffc02800 +#define SOCFPGA_I2C1_ADDRESS 0xffc02900 +#define SOCFPGA_I2C2_ADDRESS 0xffc02a00 +#define SOCFPGA_I2C3_ADDRESS 0xffc02b00 +#define SOCFPGA_I2C4_ADDRESS 0xffc02c00 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 +#define SOCFPGA_GPIO0_ADDRESS 0xffc03200 +#define SOCFPGA_GPIO1_ADDRESS 0xffc03300 +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd0 +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00100 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00300 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00400 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00500 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd1 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_SPIS0_ADDRESS 0xffda2000 +#define SOCFPGA_SPIS1_ADDRESS 0xffda3000 +#define SOCFPGA_SPIM0_ADDRESS 0xffda4000 +#define SOCFPGA_SPIM1_ADDRESS 0xffda5000 +#define SOCFPGA_OCRAM_ADDRESS 0xffe0 + +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */ -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10
From: Dinh NguyenOn the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset function to support both GEN5 and Arria10 devices. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/system_manager.h | 4 +--- arch/arm/mach-socfpga/misc.c| 14 ++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 9ca889a..831ba4a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -133,9 +133,7 @@ struct socfpga_system_manager { u32 usb0_l3master; u32 usb1_l3master; u32 emac_global; - u32 emac0; - u32 emac1; - u32 emac2; + u32 emac[3]; u32 _pad_0x50_0x5f[4]; u32 fpgaintf_en_global; u32 fpgaintf_en_0; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index c97caea..510aa1d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -21,7 +21,11 @@ #include #include +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include +#else +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id, } else if (of_reset_id == EMAC1_RESET) { physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; reset = SOCFPGA_RESET(EMAC1); +#ifndef CONFIG_TARGET_SOCFPGA_GEN5 + } else if (of_reset_id == EMAC2_RESET) { + reset = SOCFPGA_RESET(EMAC2); +#endif } else { printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); return; } +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* configure to PHY interface select choosed */ clrsetbits_le32(_regs->emacgrp_ctrl, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, phymode << physhift); +#else + clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET], + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + phymode); +#endif /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 16/30] arm: socfpga: add reset manager defines for Arria10
From: Dinh NguyenAdd the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++ 1 file changed, 103 insertions(+) create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h new file mode 100644 index 000..7619ca2 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET32 +#define EMAC1_RESET33 +#define EMAC2_RESET34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +#define QSPI_RESET 38 +#define SDMMC_RESET39 +#define EMAC0_OCP_RESET40 +#define EMAC1_OCP_RESET41 +#define EMAC2_OCP_RESET42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +#define QSPI_OCP_RESET 46 +#define SDMMC_OCP_RESET47 +#define DMA_RESET 48 +#define SPIM0_RESET49 +#define SPIM1_RESET50 +#define SPIS0_RESET51 +#define SPIS1_RESET52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define L4WD0_RESET64 +#define L4WD1_RESET65 +#define L4SYSTIMER0_RESET 66 +#define L4SYSTIMER1_RESET 67 +#define SPTIMER0_RESET 68 +#define SPTIMER1_RESET 69 +/* 70-71 is reserved */ +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is reserved */ +#define UART0_RESET80 +#define UART1_RESET81 +/* 82-87 is reserved */ +#define GPIO0_RESET88 +#define GPIO1_RESET89 +#define GPIO2_RESET90 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 +#define F2SSDRAM0_RESET99 +#define F2SSDRAM1_RESET100 +#define F2SSDRAM2_RESET101 +#define DDRSCH_RESET 102 + +/* SYSMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET129 +/* 130 is reserved */ +#define FPGAMGR_RESET 131 +#define S2F_RESET 132 +#define SYSDBG_RESET 133 +#define OCRAM_OCP_RESET134 + +/* COLDMODRST */ +#define CLKMGRCOLD_RESET 160 +/* 161-162 is reserved */ +#define S2FCOLD_RESET 163 +#define TIMESTAMPCOLD_RESET164 +#define TAPCOLD_RESET 165 +#define HMCCOLD_RESET 166 +#define IOMGRCOLD_RESET167 + +/* NRSTMODRST */ +#define NRSTPINOE_RESET192 + +/* DBGMODRST */ +#define DBG_RESET 224 +#endif -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits
From: Dinh NguyenThere is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 2645129..c97caea 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id, return; } - /* Clearing emac0 PHY interface select to 0 */ - clrbits_le32(_regs->emacgrp_ctrl, -SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); - /* configure to PHY interface select choosed */ - setbits_le32(_regs->emacgrp_ctrl, -phymode << physhift); + clrsetbits_le32(_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, + phymode << physhift); /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices
From: Dinh NguyenThe system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/system_manager.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 75a65f3..9e1c3fd 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs = * The value is not wrote to SYSMGR.FPGAINTF.MODULE but * CONFIG_SYSMGR_ISWGRP_HANDOFF. */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void populate_sysmgr_fpgaintf_module(void) { uint32_t handoff_val = 0; @@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable) clrbits_le32(_regs->romcodegrp_ctrl, SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */ -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 14/30] arm: socfpga: arria10: remove board_init and s_init
From: Dinh NguyenThese functions are already in arch/arm/mach-socfpga/board.c Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/socfpga.c | 17 - 1 file changed, 17 deletions(-) diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c index abedc22..8516633 100644 --- a/board/altera/arria10-socdk/socfpga.c +++ b/board/altera/arria10-socdk/socfpga.c @@ -5,20 +5,3 @@ */ #include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) -{ -} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - return 0; -} -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 13/30] arm: socfpga: arria10 fpga does not have bridges mapped
From: Dinh NguyenOn the Arria10 device, the bridges are not mapped through the interconnect. Signed-off-by: Dinh Nguyen --- drivers/fpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index f1b2f2c..bfefafd 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(1); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Unmap the bridges from NIC-301 */ writel(0x1, SOCFPGA_L3REGS_ADDRESS); +#endif /* Initialize the FPGA Manager */ status = fpgamgr_program_init(); -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10
From: Dinh NguyenThe Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig. Signed-off-by: Dinh Nguyen --- drivers/Kconfig | 2 ++ drivers/ddr/Kconfig | 1 + drivers/ddr/altera/Kconfig | 6 ++ include/configs/socfpga_common.h | 5 - 4 files changed, 9 insertions(+), 5 deletions(-) create mode 100644 drivers/ddr/Kconfig create mode 100644 drivers/ddr/altera/Kconfig diff --git a/drivers/Kconfig b/drivers/Kconfig index e8c9e0a..0178498 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig" source "drivers/crypto/Kconfig" +source "drivers/ddr/Kconfig" + source "drivers/demo/Kconfig" source "drivers/dfu/Kconfig" diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig new file mode 100644 index 000..b764add --- /dev/null +++ b/drivers/ddr/Kconfig @@ -0,0 +1 @@ +source "drivers/ddr/altera/Kconfig" diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig new file mode 100644 index 000..9554da7 --- /dev/null +++ b/drivers/ddr/altera/Kconfig @@ -0,0 +1,6 @@ +config ALTERA_SDRAM + bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices" + default y if TARGET_SOCFPGA_GEN5 + help + This is for building the SDRAM controller for the Arria5/Cyclone5 + devices. diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 58a6550..f6a2f8d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -77,11 +77,6 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* - * SDRAM controller - */ -#define CONFIG_ALTERA_SDRAM - -/* * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 10/30] arm: socfpga: arria10: add reset manager for Arria10
From: Dinh NguyenAdd the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++ arch/arm/mach-socfpga/reset_manager.c | 24 +++- 2 files changed, 88 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 2f070f2..6225118 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) struct socfpga_reset_manager { u32 status; u32 ctrl; @@ -28,6 +29,42 @@ struct socfpga_reset_manager { u32 padding2[12]; u32 tstscratch; }; +#else +struct socfpga_reset_manager { + u32 stat; + u32 ramstat; + u32 miscstat; + u32 ctrl; + u32 hdsken; + u32 hdskreq; + u32 hdskack; + u32 counts; + u32 mpu_mod_reset; + u32 per_mod_reset; /* stated as per0_mod_reset in A10 datasheet */ + u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */ + u32 brg_mod_reset; + u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */ + u32 coldmodrst; + u32 nrstmodrst; + u32 dbgmodrst; + u32 mpuwarmmask; + u32 per0warmmask; + u32 per1warmmask; + u32 brgwarmmask; + u32 syswarmmask; + u32 nrstwarmmask; + u32 l3warmmask; + u32 tststa; + u32 tstscratch; + u32 hdsktimeout; + u32 hmcintr; + u32 hmcintren; + u32 hmcintrens; + u32 hmcintrenr; + u32 hmcgpout; + u32 hmcgpin; +}; +#endif #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 @@ -55,6 +92,7 @@ struct socfpga_reset_manager { #define RSTMGR_BANK(_reset)\ (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: * 0 ... mpumodrst @@ -75,6 +113,33 @@ struct socfpga_reset_manager { #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) +#else +/* + * SocFPGA Arria10 reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... per0modrst + * 2 ... per1modrst + * 3 ... brgmodrst + * 4 ... sysmodrst + */ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) +#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2) +#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3) +#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4) +#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) +#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) +#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) +#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6) +#endif /* Create a human-readable reference to SoCFPGA reset. */ #define SOCFPGA_RESET(_name) RSTMGR_##_name diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index b6beaa2..d0ff6c4 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base = static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -/* Assert or de-assert SoCFPGA reset manager reset. */ +/* + * Assert or de-assert SoCFPGA reset manager reset. + */ void socfpga_per_reset(u32 reset, int set) { const void *reg; @@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set) * Assert reset on every peripheral but L4WD0. * Watchdog must be kept intact to prevent glitches * and/or hangs. + * For the Arria10, we disable all the peripherals except L4 watchdog0, + * L4 Timer 0, and ECC. */ void socfpga_per_reset_all(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); writel(~l4wd0, _manager_base->per_mod_reset);
[U-Boot] [PATCH v2 08/30] arm: socfpga: arria10: add config option build for arria10
From: Dinh NguyenSigned-off-by: Dinh Nguyen --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-socfpga/Kconfig | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d871a45..74b769f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -554,9 +554,9 @@ config ARCH_SNAPDRAGON config ARCH_SOCFPGA bool "Altera SOCFPGA family" select CPU_V7 - select SUPPORT_SPL + select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10 select OF_CONTROL - select SPL_OF_CONTROL + select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10 select DM select DM_SPI_FLASH select DM_SPI diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 6991af8..d9a5178 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 +config TARGET_SOCFPGA_ARRIA10 + bool + config TARGET_SOCFPGA_CYCLONE5 bool select TARGET_SOCFPGA_GEN5 @@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_ARRIA10_SOCDK + bool "Altera SOCFPGA SoCDK (Arria 10)" + select TARGET_SOCFPGA_ARRIA10 + config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -86,6 +93,7 @@ endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC @@ -98,6 +106,7 @@ config SYS_BOARD config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES @@ -111,6 +120,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 09/30] arm: socfpga: add define for bootinfo bsel bit shift
From: Dinh NguyenOn arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++ arch/arm/mach-socfpga/misc.c| 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index e688c50..9ca889a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -203,8 +203,10 @@ struct socfpga_system_manager { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 0 #else #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 12 #endif #define SYSMGR_SDMMC_DRVSEL_SHIFT 0 diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index c1e5969..2645129 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { + const u32 bsel = (readl(_regs->bootinfo) >> + SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7; #if defined(CONFIG_TARGET_SOCFPGA_GEN5) - const u32 bsel = readl(_regs->bootinfo) & 0x7; puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); #else - const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7; puts("CPU: Altera SoCFPGA Arria 10\n"); #endif printf("BOOT: %s\n", bsel_str[bsel].name); -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config
From: Dinh NguyenAdd config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- include/configs/socfpga_arria10_socdk.h | 94 + 1 file changed, 94 insertions(+) create mode 100644 include/configs/socfpga_arria10_socdk.h diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h new file mode 100644 index 000..577f60f --- /dev/null +++ b/include/configs/socfpga_arria10_socdk.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__ +#define __CONFIG_SOCFGPA_ARRIA10_H__ + +#include +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING + +/* + * Memory configurations + */ +#define PHYS_SDRAM_1_SIZE 0x200 + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE"zImage" +#define CONFIG_BOOTARGS"console=ttyS0," __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_LOADADDR0x0100 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + +#endif + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */ +#define CONFIG_ENV_OFFSET 512/* just after the MBR */ + +/* + * arguments passed to the bootz command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include +#endif /* __CONFIG_H */ -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig
From: Dinh NguyenAdd a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- configs/socfpga_arria10_defconfig | 16 1 file changed, 16 insertions(+) create mode 100644 configs/socfpga_arria10_defconfig diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig new file mode 100644 index 000..422261b --- /dev/null +++ b/configs/socfpga_arria10_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_TARGET_SOCFPGA_ARRIA10=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK
From: Dinh NguyenAdd minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/Kconfig | 18 ++ board/altera/arria10-socdk/Makefile | 7 +++ board/altera/arria10-socdk/socfpga.c | 24 3 files changed, 49 insertions(+) create mode 100644 board/altera/arria10-socdk/Kconfig create mode 100644 board/altera/arria10-socdk/Makefile create mode 100644 board/altera/arria10-socdk/socfpga.c diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig new file mode 100644 index 000..b80cc6d --- /dev/null +++ b/board/altera/arria10-socdk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SOCFPGA_ARRIA10 + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "socfpga_arria10" + +config SYS_VENDOR + default "altera" + +config SYS_SOC + default "socfpga_arria10" + +config SYS_CONFIG_NAME + default "socfpga_arria10" + +endif diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile new file mode 100644 index 000..1d885ce --- /dev/null +++ b/board/altera/arria10-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Altera Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c new file mode 100644 index 000..abedc22 --- /dev/null +++ b/board/altera/arria10-socdk/socfpga.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) +{ +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + return 0; +} -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 05/30] arm: socfpga: arria10: add misc functions for Arria10
From: Dinh NguyenAdd arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 51 1 file changed, 51 insertions(+) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index dd6b53b..c1e5969 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; static struct socfpga_reset_manager *reset_manager_base = (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; +#else +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; +#endif static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; @@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) const u32 bsel = readl(_regs->bootinfo) & 0x7; puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); +#else + const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7; + puts("CPU: Altera SoCFPGA Arria 10\n"); +#endif printf("BOOT: %s\n", bsel_str[bsel].name); return 0; } @@ -338,6 +351,7 @@ int arch_cpu_init(void) return 0; } +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* * Convert all NIC-301 AMBA slaves from secure to non-secure */ @@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#else +/* ++ * This function initializes security policies to be consistent across ++ * all logic units in the Arria 10. ++ * ++ * The idea is to set all security policies to be normal, nonsecure ++ * for all units. ++ */ +static void initialize_security_policies(void) +{ + /* Put OCRAM in non-secure */ + writel(0x003f, _fw_ocram_base->region0); + writel(0x1, _fw_ocram_base->enable); + + /* Put DDR in non-secure */ + writel(0x, _fw_ddr_l3_base->hpsregion0addr); + writel(0x1, _fw_ddr_l3_base->enable); +} + +int arch_early_init_r(void) +{ + initialize_security_policies(); + + /* Configure the L2 controller to make SDRAM start at 0 */ + writel(0x1, >pl310_addr_filter_start); + + /* assert reset to all except L4WD0 and L4TIMER0 */ + socfpga_per_reset_all(); + + /* configuring the clock based on handoff */ + /* TODO: Add call to cm_basic_init() */ + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + return 0; +} +#endif U_BOOT_CMD( bridge, 2, 1, do_bridge, -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 04/30] arm: socfpga: arria10: add system manager defines
From: Tien Fong CheeAdd system manager defines for Arria10. Signed-off-by: Dinh Nguyen --- .../arm/mach-socfpga/include/mach/system_manager.h | 122 + 1 file changed, 122 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index c45edea..e688c50 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable); void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) struct socfpga_system_manager { /* System Manager Module */ u32 siliconid1; /* 0x00 */ @@ -115,6 +116,77 @@ struct socfpga_system_manager { u32 _pad_0x734; u32 spim0usefpga; /* 0x738 */ }; +#else /* Arria10 System Manager */ +struct socfpga_system_manager { + u32 siliconid1; + u32 siliconid2; + u32 wddbg; + u32 bootinfo; + u32 mpu_ctrl_l2_ecc; + u32 _pad_0x14_0x1f[3]; + u32 dma; + u32 dma_periph; + u32 sdmmcgrp_ctrl; + u32 sdmmc_l3master; + u32 nand_bootstrap; + u32 nand_l3master; + u32 usb0_l3master; + u32 usb1_l3master; + u32 emac_global; + u32 emac0; + u32 emac1; + u32 emac2; + u32 _pad_0x50_0x5f[4]; + u32 fpgaintf_en_global; + u32 fpgaintf_en_0; + u32 fpgaintf_en_1; + u32 fpgaintf_en_2; + u32 fpgaintf_en_3; + u32 _pad_0x74_0x7f[3]; + u32 noc_addr_remap_value; + u32 noc_addr_remap_set; + u32 noc_addr_remap_clear; + u32 _pad_0x8c_0x8f; + u32 ecc_intmask_value; + u32 ecc_intmask_set; + u32 ecc_intmask_clr; + u32 ecc_intstatus_serr; + u32 ecc_intstatus_derr; + u32 mpu_status_l2_ecc; + u32 mpu_clear_l2_ecc; + u32 mpu_status_l1_parity; + u32 mpu_clear_l1_parity; + u32 mpu_set_l1_parity; + u32 _pad_0xb8_0xbf[2]; + u32 noc_timeout; + u32 noc_idlereq_set; + u32 noc_idlereq_clr; + u32 noc_idlereq_value; + u32 noc_idleack; + u32 noc_idlestatus; + u32 fpga2soc_ctrl; + u32 _pad_0xdc_0xff[9]; + u32 tsmc_tsel_0; + u32 tsmc_tsel_1; + u32 tsmc_tsel_2; + u32 tsmc_tsel_3; + u32 _pad_0x110_0x200[60]; + u32 romhw_ctrl; + u32 romcode_ctrl; + u32 romcode_cpu1startaddr; + u32 romcode_initswstate; + u32 romcode_initswlastld; + u32 _pad_0x214_0x217; + u32 warmram_enable; + u32 warmram_datastart; + u32 warmram_length; + u32 warmram_execution; + u32 warmram_crc; + u32 _pad_0x22c_0x22f; + u32 isw_handoff[8]; + u32 romcode_bootromswstate[8]; +}; +#endif #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1) @@ -146,4 +218,54 @@ struct socfpga_system_manager { #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3 +/* For dedicated IO configuration */ +/* Voltage select enums */ +#define VOLTAGE_SEL_3V 0x0 +#define VOLTAGE_SEL_1P8V 0x1 +#define VOLTAGE_SEL_2P5V 0x2 + +/* Input buffer enable */ +#define INPUT_BUF_DISABLE 0 +#define INPUT_BUF_1P8V 1 +#define INPUT_BUF_2P5V3V 2 + +/* Weak pull up enable */ +#define WK_PU_DISABLE 0 +#define WK_PU_ENABLE 1 + +/* Pull up slew rate control */ +#define PU_SLW_RT_SLOW 0 +#define PU_SLW_RT_FAST 1 +#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW + +/* Pull down slew rate control */ +#define PD_SLW_RT_SLOW 0 +#define PD_SLW_RT_FAST 1 +#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW + +/* Drive strength control */ +#define PU_DRV_STRG_DEFAULT0x10 +#define PD_DRV_STRG_DEFAULT0x10 + +/* bit position */ +#define PD_DRV_STRG_LSB0 +#define PD_SLW_RT_LSB 5 +#define PU_DRV_STRG_LSB8 +#define PU_SLW_RT_LSB 13 +#define WK_PU_LSB 16 +#define INPUT_BUF_LSB 17 +#define BIAS_TRIM_LSB 19 +#define VOLTAGE_SEL_LSB0 + +#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001 +#define ALT_SYSMGR_NOC_LWH2F_SET_MSK 0x0010 +#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100 +#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK 0x0001 +#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK 0x0010 +#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK 0x0100 +#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK 0x0001 + +#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK 0x0002 +#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK 0x0002 + #endif /*
[U-Boot] [PATCH v2 02/30] arm: socfpga: arria10: add sdram defines for Arria10
From: Dinh NguyenAdd the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 + 1 file changed, 380 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h b/arch/arm/mach-socfpga/include/mach/sdram_a10.h new file mode 100644 index 000..0403531 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef_SOCFPGA_SDRAM_A10_H_ +#define_SOCFPGA_SDRAM_A10_H_ + +#ifndef __ASSEMBLY__ + +struct socfpga_ecc_hmc { + u32 ip_rev_id; + u32 _pad_0x4_0x7; + u32 ddrioctrl; + u32 ddrcalstat; + u32 mpr_0beat1; + u32 mpr_1beat1; + u32 mpr_2beat1; + u32 mpr_3beat1; + u32 mpr_4beat1; + u32 mpr_5beat1; + u32 mpr_6beat1; + u32 mpr_7beat1; + u32 mpr_8beat1; + u32 mpr_0beat2; + u32 mpr_1beat2; + u32 mpr_2beat2; + u32 mpr_3beat2; + u32 mpr_4beat2; + u32 mpr_5beat2; + u32 mpr_6beat2; + u32 mpr_7beat2; + u32 mpr_8beat2; + u32 _pad_0x58_0x5f[2]; + u32 auto_precharge; + u32 _pad_0x64_0xff[39]; + u32 eccctrl; + u32 eccctrl2; + u32 _pad_0x108_0x10f[2]; + u32 errinten; + u32 errintens; + u32 errintenr; + u32 intmode; + u32 intstat; + u32 diaginttest; + u32 modstat; + u32 derraddra; + u32 serraddra; + u32 _pad_0x134_0x137; + u32 autowb_corraddr; + u32 serrcntreg; + u32 autowb_drop_cntreg; + u32 _pad_0x144_0x147; + u32 ecc_reg2wreccdatabus; + u32 ecc_rdeccdata2regbus; + u32 ecc_reg2rdeccdatabus; + u32 _pad_0x154_0x15f[3]; + u32 ecc_diagon; + u32 ecc_decstat; + u32 _pad_0x168_0x16f[2]; + u32 ecc_errgenaddr_0; + u32 ecc_errgenaddr_1; + u32 ecc_errgenaddr_2; + u32 ecc_errgenaddr_3; +}; + +struct socfpga_noc_ddr_scheduler { + u32 ddr_t_main_scheduler_id_coreid; + u32 ddr_t_main_scheduler_id_revisionid; + u32 ddr_t_main_scheduler_ddrconf; + u32 ddr_t_main_scheduler_ddrtiming; + u32 ddr_t_main_scheduler_ddrmode; + u32 ddr_t_main_scheduler_readlatency; + u32 _pad_0x20_0x34[8]; + u32 ddr_t_main_scheduler_activate; + u32 ddr_t_main_scheduler_devtodev; +}; + +/* + * OCRAM firewall + */ +struct socfpga_noc_fw_ocram { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 region0; + u32 region1; + u32 region2; + u32 region3; + u32 region4; + u32 region5; +}; + +/* for master such as MPU and FPGA */ +struct socfpga_noc_fw_ddr_mpu_fpga2sdram { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 _pad_0xc_0xf; + u32 mpuregion0addr; + u32 mpuregion1addr; + u32 mpuregion2addr; + u32 mpuregion3addr; + u32 fpga2sdram0region0addr; + u32 fpga2sdram0region1addr; + u32 fpga2sdram0region2addr; + u32 fpga2sdram0region3addr; + u32 fpga2sdram1region0addr; + u32 fpga2sdram1region1addr; + u32 fpga2sdram1region2addr; + u32 fpga2sdram1region3addr; + u32 fpga2sdram2region0addr; + u32 fpga2sdram2region1addr; + u32 fpga2sdram2region2addr; + u32 fpga2sdram2region3addr; +}; + +/* for L3 master */ +struct socfpga_noc_fw_ddr_l3 { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 hpsregion0addr; + u32 hpsregion1addr; + u32 hpsregion2addr; + u32 hpsregion3addr; + u32 hpsregion4addr; + u32 hpsregion5addr; + u32 hpsregion6addr; + u32 hpsregion7addr; +}; + +struct socfpga_io48_mmr { + u32 dbgcfg0; + u32 dbgcfg1; + u32 dbgcfg2; + u32 dbgcfg3; + u32 dbgcfg4; + u32 dbgcfg5; + u32 dbgcfg6; + u32 reserve0; + u32 reserve1; + u32 reserve2; + u32 ctrlcfg0; + u32 ctrlcfg1; + u32 ctrlcfg2; + u32 ctrlcfg3; + u32 ctrlcfg4; + u32 ctrlcfg5; + u32 ctrlcfg6; + u32 ctrlcfg7; + u32 ctrlcfg8; + u32 ctrlcfg9; + u32 dramtiming0; + u32 dramodt0; + u32 dramodt1; + u32 sbcfg0; + u32 sbcfg1; + u32 sbcfg2; + u32 sbcfg3; + u32 sbcfg4; + u32 sbcfg5; + u32 sbcfg6; + u32 sbcfg7; + u32 caltiming0; + u32 caltiming1; + u32 caltiming2; + u32 caltiming3; + u32 caltiming4; + u32 caltiming5; + u32 caltiming6; + u32 caltiming7; + u32 caltiming8; + u32 caltiming9; + u32 caltiming10; + u32 dramaddrw; + u32 sideband0; + u32 sideband1; +
[U-Boot] [PATCH v2 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10
From: Dinh NguyenAdd remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen Reviewed-by: Stefan Roese --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index a7056d4..902c321 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -29,6 +29,9 @@ #define SOCFPGA_MPUL2_ADDRESS 0xf000 #define SOCFPGA_I2C0_ADDRESS 0xffc02200 #define SOCFPGA_I2C1_ADDRESS 0xffc02300 +#define SOCFPGA_I2C2_ADDRESS 0xffc02400 +#define SOCFPGA_I2C3_ADDRESS 0xffc02500 +#define SOCFPGA_I2C4_ADDRESS 0xffc02600 #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/10] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
On Sel, 2016-12-20 at 09:17 -0600, Dinh Nguyen wrote: > > On 12/06/2016 02:11 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > This patch adding the Arria10 critical hardware initialization > > before > > enabling console print out in spl. > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vasut <ma...@denx.de> > > Cc: Dinh Nguyen <dingu...@kernel.org> > > Cc: Chin Liang See <chin.liang@intel.com> > > Cc: Tien Fong <skywind...@gmail.com> > > --- > > arch/arm/mach-socfpga/spl.c | 86 > > +- > > 1 files changed, 83 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach- > > socfpga/spl.c > > index fec4c7a..9375514 100644 > > --- a/arch/arm/mach-socfpga/spl.c > > +++ b/arch/arm/mach-socfpga/spl.c > > @@ -1,7 +1,7 @@ > > /* > > - * Copyright (C) 2012 Altera Corporation > > + * Copyright (C) 2012-2016 Altera Corporation > > * > > - * SPDX-License-Identifier:GPL-2.0+ > > + * SPDX-License-Identifier:GPL-2.0 > > */ > Shouldn't be changing the license. > Yeah, i will revert it. > > > > > > #include > > @@ -19,22 +19,32 @@ > > #include > > #include > > #include > > +#include > > +#include > > +#include > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > +#include > > +#endif > I don't know about all these includes, do you really need them? I > don't > see where you would need pinmux.h in this patch. > Yeah, we those header, otherwise compilation failed. we need pinmux.h also, because there is a function config_dedicated_pins(gd->fdt_blob); in void board_init_f(ulong dummy). This function would configure the dedicated IO such as UART IO before enable print console. > > > > > > DECLARE_GLOBAL_DATA_PTR; > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > static struct pl310_regs *const pl310 = > > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > > static struct scu_registers *scu_regs = > > (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; > > static struct nic301_registers *nic301_regs = > > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; > > -static struct socfpga_system_manager *sysmgr_regs = > > +#endif > > + > > +static const struct socfpga_system_manager *sysmgr_regs = > > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > > > u32 spl_boot_device(void) > > { > > const u32 bsel = readl(_regs->bootinfo); > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > switch (bsel & 0x7) { > > case 0x1: /* FPGA (HPS2FPGA Bridge) */ > > return BOOT_DEVICE_RAM; > > @@ -55,6 +65,24 @@ u32 spl_boot_device(void) > > printf("Invalid boot device (bsel=%08x)!\n", > > bsel); > > hang(); > > } > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > + switch ((bsel>>12) & 0x7) { > > + case 0x1: /* FPGA (HPS2FPGA Bridge) */ > > + return BOOT_DEVICE_RAM; > > + case 0x2: /* NAND Flash (1.8V) */ > > + case 0x3: /* NAND Flash (3.0V) */ > > + return BOOT_DEVICE_NAND; > > + case 0x4: /* SD/MMC External Transceiver (1.8V) */ > > + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ > > + return BOOT_DEVICE_MMC1; > > + case 0x6: /* QSPI Flash (1.8V) */ > > + case 0x7: /* QSPI Flash (3.0V) */ > > + return BOOT_DEVICE_SPI; > > + default: > > + printf("Invalid boot device (bsel=%08x)!\n", > > bsel); > > + hang(); > > + } > > +#endif > > } > You should just do a shift define here, so you don't have to add > all > this extra code here. Something like > > switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) > > > > > > > #ifdef CONFIG_SPL_MMC_SUPPORT > > @@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device) > > } > > #endif > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > static void socfpga_nic301_slave_ns(void) > > { > > writel(0x1, _regs->lwhps2fpgaregs); > > @@ -182,3 +211,54 @@ void board_init_f(ulong dummy) > > /* Configure simple malloc base pointer into RAM. */ > > gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); > > } &g
Re: [U-Boot] [PATCH 08/10] arm: socfpga: arria10: Added drivers for Arria10 clock manager
On Sel, 2016-12-06 at 16:10 +0800, Chee Tien Fong wrote: > From: Tien Fong Chee <tien.fong.c...@intel.com> > > The drivers is restructured such common functions, gen5 functions, > and arria10 functions are moved to clock_manager.c, cock_manager_gen5 > and clock_manager_arria10 respectively. > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > Cc: Marek Vasut <ma...@denx.de> > Cc: Dinh Nguyen <dingu...@kernel.org> > Cc: Chin Liang See <chin.liang@intel.com> > Cc: Tien Fong <skywind...@gmail.com> > --- > arch/arm/mach-socfpga/Makefile |6 +- > arch/arm/mach-socfpga/clock_manager.c | 754 +++--- > -- > arch/arm/mach-socfpga/clock_manager_arria10.c | 954 > > arch/arm/mach-socfpga/clock_manager_gen5.c | 342 +++ > arch/arm/mach-socfpga/include/mach/clock_manager.h | 360 ++-- > 5 files changed, 1910 insertions(+), 506 deletions(-) > create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c > create mode 100644 arch/arm/mach-socfpga/clock_manager_gen5.c > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach- > socfpga/Makefile > index f8b529e..71cf31c 100644 > --- a/arch/arm/mach-socfpga/Makefile > +++ b/arch/arm/mach-socfpga/Makefile > @@ -9,9 +9,11 @@ > Any comments on this patch before i start the version 2? > obj-y+= misc.o timer.o reset_manager.o system_manager.o > clock_manager.o \ > fpga_manager.o board.o > -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o > misc_arria10.o > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o > misc_arria10.o \ > + clock_manager_arria10.o > obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o > wrap_pll_config.o \ > - reset_manager_gen5.o misc_gen5.o > + reset_manager_gen5.o misc_gen5.o \ > + clock_manager_gen5.o > > ifdef CONFIG_SPL_BUILD > obj-y += spl.o > diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach- > socfpga/clock_manager.c > index aa71636..fe82c39 100644 > --- a/arch/arm/mach-socfpga/clock_manager.c > +++ b/arch/arm/mach-socfpga/clock_manager.c > @@ -1,422 +1,293 @@ > /* > - * Copyright (C) 2013 Altera Corporation > + * Copyright (C) 2013-2016 Intel Corporation > * > - * SPDX-License-Identifier: GPL-2.0+ > + * SPDX-License-Identifier: GPL-2.0 > */ > > #include > #include > #include > +#include > > DECLARE_GLOBAL_DATA_PTR; > > +/* Function prototypes */ > +/* Common prototypes */ > +unsigned int cm_get_l4_sp_clk_hz(void); > +unsigned int cm_get_qspi_controller_clk_hz(void); > +unsigned int cm_get_mmc_controller_clk_hz(void); > +unsigned int cm_get_spi_controller_clk_hz(void); > +static void cm_print_clock_quick_summary(void); > +int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const > argv[]); > +void cm_wait_for_lock(uint32_t mask); > +void cm_wait_for_fsm(void); > +unsigned int cm_get_main_vco_clk_hz(void); > +unsigned int cm_get_per_vco_clk_hz(void); > +unsigned long cm_get_mpu_clk_hz(void); > + > static const struct socfpga_clock_manager *clock_manager_base = > (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; > > -static void cm_wait_for_lock(uint32_t mask) > +/* Common functions */ > +int set_cpu_clk_info(void) > { > - register uint32_t inter_val; > - uint32_t retry = 0; > - do { > - inter_val = readl(_manager_base->inter) & > mask; > - if (inter_val == mask) > - retry++; > - else > - retry = 0; > - if (retry >= 10) > - break; > - } while (1); > -} > + /* Calculate the clock frequencies required for drivers */ > + cm_get_l4_sp_clk_hz(); > + cm_get_mmc_controller_clk_hz(); > > -/* function to poll in the fsm busy bit */ > -static void cm_wait_for_fsm(void) > -{ > - while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY) > - ; > -} > + gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100; > + gd->bd->bi_dsp_freq = 0; > > -/* > - * function to write the bypass register which requires a poll of > the > - * busy bit > - */ > -static void cm_write_bypass(uint32_t val) > -{ > - writel(val, _manager_base->bypass); > - cm_wait_for_fsm(); > -} > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > + gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100; > +#elif defined(CONFIG_TARGET_SOCFPGA_A
Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL
On Isn, 2016-12-19 at 09:44 +0100, Marek Vasut wrote: > On 12/19/2016 09:41 AM, Chee, Tien Fong wrote: > > > > On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote: > > > > > > On 12/19/2016 05:04 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > On 12/09/2016 10:46 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > > > > > > > > > > > > > These changes to ensure Arria10 SPL build success. > > > > > > > > > Please reword the commit message, mention you're > > > > > > > > > removing > > > > > > > > > the > > > > > > > > > Arria10 > > > > > > > > > bits. Still, this does not even apply on mainline, on > > > > > > > > > top > > > > > > > > > of > > > > > > > > > what > > > > > > > > > does > > > > > > > > > this apply ? > > > > > > > > > > > > > > > > > I disabled some features temporary, so SPL build can > > > > > > > > pass > > > > > > > > and > > > > > > > > print > > > > > > > > out > > > > > > > > working. I will enable these features back in upcoming > > > > > > > > patches. > > > > > > > > This is > > > > > > > > base on 01-arria10 branch. > > > > > > > But this patch seems to only enable stuff ... ? > > > > > > > > > > > > > Enable the spl. Disable SPI flash temporary, for preventing > > > > > > build > > > > > > failed, but this will be enabled back with upcoming patches > > > > > > for > > > > > > supporting SPI flash. > > > > > What's the problem with SPI flash ? I thought it's the same > > > > > block > > > > > as > > > > > in > > > > > C/A 5 ? > > > > > > > > > Some compilation error, but i haven't checked it out what > > > > errors > > > > causing the build failed. My plan is to have SPL and print out > > > > working, > > > > then following boot from SDMMC, FPGA configuration, DDR up. > > > > Once > > > > booting from SDMMC working, i will work to boot from QSPI and > > > > NAND > > > > too. > > > MW is now closed, so you can focus on fixing the CQSPI too, it > > > shouldn't > > > be too hard. > > > > > What is MW? > > > Merge Window just for comfirmation, are you means rebase to master of u-boot- socfpga.git or denx master? I think former,right? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro
On Isn, 2016-12-19 at 11:04 +0100, Marek Vasut wrote: > On 12/19/2016 09:54 AM, Chee, Tien Fong wrote: > > > > On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote: > > > > > > On 12/19/2016 09:40 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > On 12/19/2016 05:10 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > > > > > > > > > > > > > These compat macros would be used by clock manager > > > > > > > > > > and > > > > > > > > > > pin > > > > > > > > > > mux > > > > > > > > > > drivers > > > > > > > > > > to look the required HW info from DTS for hardware > > > > > > > > > > initialization. > > > > > > > > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel > > > > > > > > > > .com > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Cc: Marek Vasut <ma...@denx.de> > > > > > > > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > > > > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > > > > > > > Cc: Tien Fong <skywind...@gmail.com> > > > > > > > > > > --- > > > > > > > > > > include/fdtdec.h |8 > > > > > > > > > > lib/fdtdec.c |2 ++ > > > > > > > > > > 2 files changed, 10 insertions(+), 0 deletions(-) > > > > > > > > > > > > > > > > > > > > diff --git a/include/fdtdec.h b/include/fdtdec.h > > > > > > > > > > index 27887c8..68cb199 100644 > > > > > > > > > > --- a/include/fdtdec.h > > > > > > > > > > +++ b/include/fdtdec.h > > > > > > > > > > @@ -155,6 +155,14 @@ enum fdt_compat_id { > > > > > > > > > > COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* > > > > > > > > > > Intel > > > > > > > > > > FSP > > > > > > > > > > memory- > > > > > > > > > > down params */ > > > > > > > > > > COMPAT_INTEL_IVYBRIDGE_FSP, /* > > > > > > > > > > Intel > > > > > > > > > > Ivy > > > > > > > > > > Bridge > > > > > > > > > > FSP > > > > > > > > > > */ > > > > > > > > > > COMPAT_SUNXI_NAND, /* SUNXI > > > > > > > > > > NAND > > > > > > > > > > controller > > > > > > > > > > */ > > > > > > > > > > + COMPAT_ALTERA_SOCFPGA_CLK, /* > > > > > > > > > > SoCFPGA > > > > > > > > > > Clock > > > > > > > > > > ini
Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
On Isn, 2016-12-19 at 08:47 +0100, Marek Vasut wrote: > On 12/19/2016 07:53 AM, Chee, Tien Fong wrote: > > > > On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote: > > > > > > On 12/09/2016 11:04 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > On 12/07/2016 12:58 PM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 12/06/2016 09:08 AM, Chee Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > > > > > > > > > Drivers for reset manager is restructured such that > > > > > > > > common > > > > > > > > functions, > > > > > > > > gen5 drivers and Arria10 drivers are moved to > > > > > > > > reset_manager.c, > > > > > > > > reset_manager_gen5.c and reset_manager_arria10.c > > > > > > > > respectively. > > > > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com > > > > > > > > > > > > > > > > > Cc: Marek Vasut <ma...@denx.de> > > > > > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > > > > > Cc: Tien Fong <skywind...@gmail.com> > > > > > [...] > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > +void reset_deassert_dedicated_peripherals(void) > > > > > > > > +{ > > > > > > > > + int i; > > > > > > > > + u32 mask0 = 0; > > > > > > > > + u32 mask1 = 0; > > > > > > > > + u32 pinmux_addr = > > > > > > > > SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS; > > > > > > > > + u32 mask = 0; > > > > > > > > +#if defined(CONFIG_MMC) > > > > > > > > + mask |= > > > > > > > > ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK; > > > > > > > > +#elif defined(CONFIG_CADENCE_QSPI) > > > > > > > > + mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK; > > > > > > > > +#elif defined(CONFIG_NAND_DENALI) > > > > > > > > + mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK; > > > > > > > > +#else > > > > > > > Shouldn't this come from OF instead of being ifdef'd ? > > > > > > > > > > > > > What is OF? > > > > > Device Tree (Open Firmware). > > > > > > > > > > > > > > > > > > > > > > > > > > > > > what is your suggestion to make this function generic for > > > > > > all type of flash? > > > > > Pull it from OF ? > > > > > > > > > Why you prefer device tree implementation over #define in > > > > defconfig, > > > > because there is performance penalty. > > > Because we are moving away from excessive random #defines and > > > toward > > > having one single binary where you could exchange just the DT and > > > run > > > it on multiple boards, just like Linux, that is the ultimate > > > goal. > > > > > > Also, this is not performance critical code, is it. > > > > > This code just to release peripherals from reset, not performance > > critical codes. However, our defconfigs based on flash type > > booting, so > > this is why i din't use the DT, since we have flash type determined > > from defconfig. Since DT is ultimate goal, i can change to DT > > implementation. > You should really only unreset the peripherals which you need and, > ideally, only when you need them. So it should be the driver which > handles the peripheral reset, not the common code (unless there is > a reason for the common code to do it). > Yeah, i agree with you too. Did our cyclone5 implement this also? Does DM has framework to support user define reset mechanism? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro
On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote: > On 12/19/2016 09:40 AM, Chee, Tien Fong wrote: > > > > On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote: > > > > > > On 12/19/2016 05:10 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > > > > > > > > > These compat macros would be used by clock manager and > > > > > > > > pin > > > > > > > > mux > > > > > > > > drivers > > > > > > > > to look the required HW info from DTS for hardware > > > > > > > > initialization. > > > > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com > > > > > > > > > > > > > > > > > Cc: Marek Vasut <ma...@denx.de> > > > > > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > > > > > Cc: Tien Fong <skywind...@gmail.com> > > > > > > > > --- > > > > > > > > include/fdtdec.h |8 > > > > > > > > lib/fdtdec.c |2 ++ > > > > > > > > 2 files changed, 10 insertions(+), 0 deletions(-) > > > > > > > > > > > > > > > > diff --git a/include/fdtdec.h b/include/fdtdec.h > > > > > > > > index 27887c8..68cb199 100644 > > > > > > > > --- a/include/fdtdec.h > > > > > > > > +++ b/include/fdtdec.h > > > > > > > > @@ -155,6 +155,14 @@ enum fdt_compat_id { > > > > > > > > COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel > > > > > > > > FSP > > > > > > > > memory- > > > > > > > > down params */ > > > > > > > > COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel > > > > > > > > Ivy > > > > > > > > Bridge > > > > > > > > FSP > > > > > > > > */ > > > > > > > > COMPAT_SUNXI_NAND, /* SUNXI > > > > > > > > NAND > > > > > > > > controller > > > > > > > > */ > > > > > > > > + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA > > > > > > > > Clock > > > > > > > > initialization */ > > > > > > > > + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, / > > > > > > > > * > > > > > > > > pinctrl- > > > > > > > > single */ > > > > > > > > + COMPAT_ALTERA_SOCFPGA_H2F_BRG, > > > > > > > > /* > > > > > > > > Arria10 > > > > > > > > hps2fpga bridge */ > > > > > > > > + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* > > > > > > > > Arria10 > > > > > > > > lwhps2fpga bridge */ > > > > > > > > + COMPAT_ALTERA_SOCFPGA_F2H_BRG, > > > > > > > > /* > > > > > > > > Arria10 > > > > > > > > fpga2hps bridge */ > > > > > > > > + COMPAT_ALTERA_SOCFPGA_F2SDR0, / > > > > > > > > * > > > > > > > > Arria10 > > > > > > > > fpga2SDRAM0 bridge */ > > > > > > > > + COMPAT_ALTERA_SOCFPGA_F2SDR1, / > > > > > > > > * > > > > > > >
Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL
On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote: > On 12/19/2016 05:04 AM, Chee, Tien Fong wrote: > > > > On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote: > > > > > > On 12/09/2016 10:46 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > > > > > > > > > These changes to ensure Arria10 SPL build success. > > > > > > > Please reword the commit message, mention you're removing > > > > > > > the > > > > > > > Arria10 > > > > > > > bits. Still, this does not even apply on mainline, on top > > > > > > > of > > > > > > > what > > > > > > > does > > > > > > > this apply ? > > > > > > > > > > > > > I disabled some features temporary, so SPL build can pass > > > > > > and > > > > > > print > > > > > > out > > > > > > working. I will enable these features back in upcoming > > > > > > patches. > > > > > > This is > > > > > > base on 01-arria10 branch. > > > > > But this patch seems to only enable stuff ... ? > > > > > > > > > Enable the spl. Disable SPI flash temporary, for preventing > > > > build > > > > failed, but this will be enabled back with upcoming patches for > > > > supporting SPI flash. > > > What's the problem with SPI flash ? I thought it's the same block > > > as > > > in > > > C/A 5 ? > > > > > Some compilation error, but i haven't checked it out what errors > > causing the build failed. My plan is to have SPL and print out > > working, > > then following boot from SDMMC, FPGA configuration, DDR up. Once > > booting from SDMMC working, i will work to boot from QSPI and NAND > > too. > MW is now closed, so you can focus on fixing the CQSPI too, it > shouldn't > be too hard. > What is MW? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro
On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote: > On 12/19/2016 05:10 AM, Chee, Tien Fong wrote: > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > > > > > > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > > > > > These compat macros would be used by clock manager and pin > > > > > > mux > > > > > > drivers > > > > > > to look the required HW info from DTS for hardware > > > > > > initialization. > > > > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > Cc: Marek Vasut <ma...@denx.de> > > > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > > > Cc: Tien Fong <skywind...@gmail.com> > > > > > > --- > > > > > > include/fdtdec.h |8 > > > > > > lib/fdtdec.c |2 ++ > > > > > > 2 files changed, 10 insertions(+), 0 deletions(-) > > > > > > > > > > > > diff --git a/include/fdtdec.h b/include/fdtdec.h > > > > > > index 27887c8..68cb199 100644 > > > > > > --- a/include/fdtdec.h > > > > > > +++ b/include/fdtdec.h > > > > > > @@ -155,6 +155,14 @@ enum fdt_compat_id { > > > > > > COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP > > > > > > memory- > > > > > > down params */ > > > > > > COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy > > > > > > Bridge > > > > > > FSP > > > > > > */ > > > > > > COMPAT_SUNXI_NAND, /* SUNXI NAND > > > > > > controller > > > > > > */ > > > > > > + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock > > > > > > initialization */ > > > > > > + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* > > > > > > pinctrl- > > > > > > single */ > > > > > > + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* > > > > > > Arria10 > > > > > > hps2fpga bridge */ > > > > > > + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 > > > > > > lwhps2fpga bridge */ > > > > > > + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* > > > > > > Arria10 > > > > > > fpga2hps bridge */ > > > > > > + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* > > > > > > Arria10 > > > > > > fpga2SDRAM0 bridge */ > > > > > > + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* > > > > > > Arria10 > > > > > > fpga2SDRAM1 bridge */ > > > > > > + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* > > > > > > Arria10 > > > > > > fpga2SDRAM2 bridge */ > > > > > Is all of this needed ? You're only adding two entries in the > > > > > FDTDEC > > > > > below. > > > > > > > > > This is to avoid compilation error, we have some functions > > > > ported > > > > from > > > > our internal branch, which using above COMPAT macro. Soon, in > > > > upcoming > > > > patches, we will need those functions and more entries will be > > > > added > > > > into FDTDEC below. > > > You can add the compat strings when you really need them. Still, > > > with > > > DM, you shouldn't even need them AFAIK. > > > > > We have some drivers in these series of patches contain some COMPAT > > strings, without these compact strings, the compilation would fail > > due > > to error compact string is not defined. > All of them ? Mind you, with DM you should not need to add those at > all. > > > > > I think having compact string > > would giving us flexbility to put our nodes where we want without > > worrying to break our existing codes? > Which existing codes ? > let say we have version A, we found the node based on COMPAT STRING. One day, we move the node to somewhere else in version B, we still can find them based on COMPAT STRING without checking the node path. What do you think? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote: > On 12/09/2016 11:04 AM, Chee, Tien Fong wrote: > > > > On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote: > > > > > > On 12/07/2016 12:58 PM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > On 12/06/2016 09:08 AM, Chee Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > > > > > Drivers for reset manager is restructured such that common > > > > > > functions, > > > > > > gen5 drivers and Arria10 drivers are moved to > > > > > > reset_manager.c, > > > > > > reset_manager_gen5.c and reset_manager_arria10.c > > > > > > respectively. > > > > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > Cc: Marek Vasut <ma...@denx.de> > > > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > > > Cc: Tien Fong <skywind...@gmail.com> > > > [...] > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > +void reset_deassert_dedicated_peripherals(void) > > > > > > +{ > > > > > > + int i; > > > > > > + u32 mask0 = 0; > > > > > > + u32 mask1 = 0; > > > > > > + u32 pinmux_addr = > > > > > > SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS; > > > > > > + u32 mask = 0; > > > > > > +#if defined(CONFIG_MMC) > > > > > > + mask |= ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK; > > > > > > +#elif defined(CONFIG_CADENCE_QSPI) > > > > > > + mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK; > > > > > > +#elif defined(CONFIG_NAND_DENALI) > > > > > > + mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK; > > > > > > +#else > > > > > Shouldn't this come from OF instead of being ifdef'd ? > > > > > > > > > What is OF? > > > Device Tree (Open Firmware). > > > > > > > > > > > > > > > what is your suggestion to make this function generic for > > > > all type of flash? > > > Pull it from OF ? > > > > > Why you prefer device tree implementation over #define in > > defconfig, > > because there is performance penalty. > Because we are moving away from excessive random #defines and toward > having one single binary where you could exchange just the DT and run > it on multiple boards, just like Linux, that is the ultimate goal. > > Also, this is not performance critical code, is it. > This code just to release peripherals from reset, not performance critical codes. However, our defconfigs based on flash type booting, so this is why i din't use the DT, since we have flash type determined from defconfig. Since DT is ultimate goal, i can change to DT implementation. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/10] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
On Sel, 2016-12-06 at 16:11 +0800, Chee Tien Fong wrote: > From: Tien Fong Chee <tien.fong.c...@intel.com> > > This patch adding the Arria10 critical hardware initialization before > enabling console print out in spl. > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > Cc: Marek Vasut <ma...@denx.de> > Cc: Dinh Nguyen <dingu...@kernel.org> > Cc: Chin Liang See <chin.liang@intel.com> > Cc: Tien Fong <skywind...@gmail.com> > --- > arch/arm/mach-socfpga/spl.c | 86 > +- > 1 files changed, 83 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach- > socfpga/spl.c > index fec4c7a..9375514 100644 > --- a/arch/arm/mach-socfpga/spl.c > +++ b/arch/arm/mach-socfpga/spl.c Any comments on this patch before i start the version 2? > @@ -1,7 +1,7 @@ > /* > - * Copyright (C) 2012 Altera Corporation > + * Copyright (C) 2012-2016 Altera Corporation > * > - * SPDX-License-Identifier: GPL-2.0+ > + * SPDX-License-Identifier: GPL-2.0 > */ > > #include > @@ -19,22 +19,32 @@ > #include > #include > #include > +#include > +#include > +#include > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > +#include > +#endif > > DECLARE_GLOBAL_DATA_PTR; > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > static struct pl310_regs *const pl310 = > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > static struct scu_registers *scu_regs = > (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; > static struct nic301_registers *nic301_regs = > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; > -static struct socfpga_system_manager *sysmgr_regs = > +#endif > + > +static const struct socfpga_system_manager *sysmgr_regs = > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > u32 spl_boot_device(void) > { > const u32 bsel = readl(_regs->bootinfo); > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > switch (bsel & 0x7) { > case 0x1: /* FPGA (HPS2FPGA Bridge) */ > return BOOT_DEVICE_RAM; > @@ -55,6 +65,24 @@ u32 spl_boot_device(void) > printf("Invalid boot device (bsel=%08x)!\n", bsel); > hang(); > } > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > + switch ((bsel>>12) & 0x7) { > + case 0x1: /* FPGA (HPS2FPGA Bridge) */ > + return BOOT_DEVICE_RAM; > + case 0x2: /* NAND Flash (1.8V) */ > + case 0x3: /* NAND Flash (3.0V) */ > + return BOOT_DEVICE_NAND; > + case 0x4: /* SD/MMC External Transceiver (1.8V) */ > + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ > + return BOOT_DEVICE_MMC1; > + case 0x6: /* QSPI Flash (1.8V) */ > + case 0x7: /* QSPI Flash (3.0V) */ > + return BOOT_DEVICE_SPI; > + default: > + printf("Invalid boot device (bsel=%08x)!\n", bsel); > + hang(); > + } > +#endif > } > > #ifdef CONFIG_SPL_MMC_SUPPORT > @@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device) > } > #endif > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > static void socfpga_nic301_slave_ns(void) > { > writel(0x1, _regs->lwhps2fpgaregs); > @@ -182,3 +211,54 @@ void board_init_f(ulong dummy) > /* Configure simple malloc base pointer into RAM. */ > gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); > } > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > +void board_init_f(ulong dummy) > +{ > + memset(__bss_start, 0, __bss_end - __bss_start); > + /* > + * Configure Clock Manager to use intosc clock instead > external osc to > + * ensure success watchdog operation. We do it as early as > possible. > + */ > + cm_use_intosc(); > + > + watchdog_disable(); > + > + arch_early_init_r(); > + > +#ifdef CONFIG_HW_WATCHDOG > + /* release osc1 watchdog timer 0 from reset */ > + reset_deassert_osc1wd0(); > + > + /* reconfigure and enable the watchdog */ > + hw_watchdog_init(); > + WATCHDOG_RESET(); > +#endif /* CONFIG_HW_WATCHDOG */ > + > +#ifdef CONFIG_OF_CONTROL > + /* We need to access to FDT as this stage */ > + /* FDT is at end of image */ > + gd->fdt_blob = (void *)(__bss_end); > + /* Check whether we have a valid FDT or not. */ > + if (fdtdec_prepare_fdt()) { > + panic("** CONFIG_OF_CONTROL defined but no FDT - > please see " > + "doc/README.fd
Re: [U-Boot] [PATCH 09/10] arm: socfpga: arria10: Added drivers for Arria10 pin mux/pins configuration
On Sel, 2016-12-06 at 16:11 +0800, Chee Tien Fong wrote: > From: Tien Fong Chee <tien.fong.c...@intel.com> > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > Cc: Marek Vasut <ma...@denx.de> > Cc: Dinh Nguyen <dingu...@kernel.org> > Cc: Chin Liang See <chin.liang@intel.com> > Cc: Tien Fong <skywind...@gmail.com> > --- > arch/arm/mach-socfpga/Makefile |2 +- > arch/arm/mach-socfpga/include/mach/pinmux.h | 17 + > arch/arm/mach-socfpga/pinmux.c | 104 > +++ > 3 files changed, 122 insertions(+), 1 deletions(-) > create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h > create mode 100644 arch/arm/mach-socfpga/pinmux.c > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach- > socfpga/Makefile > index 71cf31c..1ab68be 100644 > --- a/arch/arm/mach-socfpga/Makefile > +++ b/arch/arm/mach-socfpga/Makefile Any comments on this patch before i start the version 2? > @@ -10,7 +10,7 @@ > obj-y+= misc.o timer.o reset_manager.o system_manager.o > clock_manager.o \ > fpga_manager.o board.o > obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o > misc_arria10.o \ > - clock_manager_arria10.o > + clock_manager_arria10.o pinmux.o > obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o > wrap_pll_config.o \ > reset_manager_gen5.o misc_gen5.o \ > clock_manager_gen5.o > diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h > b/arch/arm/mach-socfpga/include/mach/pinmux.h > new file mode 100644 > index 000..e7d831d > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/pinmux.h > @@ -0,0 +1,17 @@ > +/* > + * Copyright (C) 2016 Intel Corporation > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > + > +#ifndef _PINMUX_H_ > +#define _PINMUX_H_ > + > +#ifndef __ASSEMBLY__ > +extern int config_dedicated_pins(const void *blob); > +extern int config_pins(const void *blob, const char *pin_grp); > +#endif > + > + > + > +#endif /* _PINMUX_H_ */ > diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach- > socfpga/pinmux.c > new file mode 100644 > index 000..d45722f > --- /dev/null > +++ b/arch/arm/mach-socfpga/pinmux.c > @@ -0,0 +1,104 @@ > +/* > + * Copyright (C) 2016 Intel Corporation > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > + > +#include > +#include > +#include > +#include > + > +int config_dedicated_pins(const void *blob); > +int config_pins(const void *blob, const char *pin_grp); > +static int __do_pinctr_pins(const void *blob, int child, const char > *node_name); > +static int do_pinctrl_pins(const void *blob, int node, const char > *child_name); > + > +static int __do_pinctr_pins(const void *blob, int child, const char > *node_name) > +{ > + int len; > + fdt_addr_t base_addr; > + fdt_size_t size; > + const u32 *cell; > + u32 offset, value; > + > + base_addr = fdtdec_get_addr_size(blob, child, "reg", ); > + if (base_addr != FDT_ADDR_T_NONE) { > + cell = fdt_getprop(blob, child, "pinctrl- > single,pins", > + ); > + if (cell != NULL) { > + debug("%p %d\n", cell, len); > + for (;len > 0; len -= (2*sizeof(u32))) { > + offset = fdt32_to_cpu(*cell++); > + value = fdt32_to_cpu(*cell++); > + debug("<0x%x 0x%x>\n", offset, > value); > + writel(value, base_addr + offset); > + } > + return 0; > + } > + } > + return 1; > +} > + > +static int do_pinctrl_pins(const void *blob, int node, const char > *child_name) > +{ > + int child, len; > + const char *node_name; > + > + child = fdt_first_subnode(blob, node); > + > + if (child < 0) > + return 2; > + > + node_name = fdt_get_name(blob, child, ); > + > + while (node_name) { > + if (!strcmp(child_name, node_name)) { > + __do_pinctr_pins(blob, child, node_name); > + return(0); > + } > + child = fdt_next_subnode(blob, child); > + > + if (child < 0) > + break; > + > + node_name = fdt_get_name(blob, child, ); > + } > + > + return 1; > +} > + > +int config_dedicate
Re: [U-Boot] [PATCH 01/10] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc
On Rab, 2016-12-07 at 14:52 +0100, Marek Vasut wrote: > On 12/07/2016 11:30 AM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:44 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 08:50 AM, Chee Tien Fong wrote: > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > This is initial version of device tree for the Intel socfpga > > > > arria10 > > > > development kit with sdmmc. > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Cc: Marek Vasut <ma...@denx.de> > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > Cc: Tien Fong <skywind...@gmail.com> > > > > --- > > > > arch/arm/dts/Makefile |3 +- > > > > arch/arm/dts/socfpga_arria10.dtsi | 859 > > > > +++ > > > > arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi | 473 > > > > + > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts| 33 + > > > > 4 files changed, 1367 insertions(+), 1 deletions(-) > > > > create mode 100644 arch/arm/dts/socfpga_arria10.dtsi > > > > create mode 100644 > > > > arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi > > > Isn't the handoff file board-specific ? > > > > > board and flash specific. How bout this name > > "socfpga_arria10_socdk_sdmmc_handoff"? > Certainly better > > > > > > > > > > > > > > create mode 100644 > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts > > > Does this patchset somehow supersede the previous one [1] or what > > > is > > > the > > > plan here ? > > > > > Yeah, the series patches here based on 01-arria10. > Just rebase and repost the whole thing on top of u-boot/master > Okay,noted. > > > > > > > > [1] > > > http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs > > > /hea > > > ds/01-arria10 > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro
On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > These compat macros would be used by clock manager and pin mux > > > > drivers > > > > to look the required HW info from DTS for hardware > > > > initialization. > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Cc: Marek Vasut <ma...@denx.de> > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > Cc: Tien Fong <skywind...@gmail.com> > > > > --- > > > > include/fdtdec.h |8 > > > > lib/fdtdec.c |2 ++ > > > > 2 files changed, 10 insertions(+), 0 deletions(-) > > > > > > > > diff --git a/include/fdtdec.h b/include/fdtdec.h > > > > index 27887c8..68cb199 100644 > > > > --- a/include/fdtdec.h > > > > +++ b/include/fdtdec.h > > > > @@ -155,6 +155,14 @@ enum fdt_compat_id { > > > > COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP > > > > memory- > > > > down params */ > > > > COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge > > > > FSP > > > > */ > > > > COMPAT_SUNXI_NAND, /* SUNXI NAND > > > > controller > > > > */ > > > > + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock > > > > initialization */ > > > > + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* > > > > pinctrl- > > > > single */ > > > > + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* > > > > Arria10 > > > > hps2fpga bridge */ > > > > + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 > > > > lwhps2fpga bridge */ > > > > + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* > > > > Arria10 > > > > fpga2hps bridge */ > > > > + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* > > > > Arria10 > > > > fpga2SDRAM0 bridge */ > > > > + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* > > > > Arria10 > > > > fpga2SDRAM1 bridge */ > > > > + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* > > > > Arria10 > > > > fpga2SDRAM2 bridge */ > > > Is all of this needed ? You're only adding two entries in the > > > FDTDEC > > > below. > > > > > This is to avoid compilation error, we have some functions ported > > from > > our internal branch, which using above COMPAT macro. Soon, in > > upcoming > > patches, we will need those functions and more entries will be > > added > > into FDTDEC below. > You can add the compat strings when you really need them. Still, with > DM, you shouldn't even need them AFAIK. > We have some drivers in these series of patches contain some COMPAT strings, without these compact strings, the compilation would fail due to error compact string is not defined. I think having compact string would giving us flexbility to put our nodes where we want without worrying to break our existing codes? > > > > > > > > > > > > > > > > > > > > > COMPAT_COUNT, > > > > }; > > > > diff --git a/lib/fdtdec.c b/lib/fdtdec.c > > > > index 4defb90..09a1db4 100644 > > > > --- a/lib/fdtdec.c > > > > +++ b/lib/fdtdec.c > > > > @@ -66,6 +66,8 @@ static const char * const > > > > compat_names[COMPAT_COUNT] = { > > > > COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp- > > > > mdp"), > > > > COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), > > > > COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), > > > > + COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"), > > > > + COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl- > > > > single"), > > > > }; > > > > > > > > const char *fdtdec_get_compatible(enum fdt_compat_id id) > > > > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL
On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote: > On 12/09/2016 10:46 AM, Chee, Tien Fong wrote: > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > > > > > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote: > > > > > > > > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > > > > > These changes to ensure Arria10 SPL build success. > > > > > Please reword the commit message, mention you're removing the > > > > > Arria10 > > > > > bits. Still, this does not even apply on mainline, on top of > > > > > what > > > > > does > > > > > this apply ? > > > > > > > > > I disabled some features temporary, so SPL build can pass and > > > > print > > > > out > > > > working. I will enable these features back in upcoming patches. > > > > This is > > > > base on 01-arria10 branch. > > > But this patch seems to only enable stuff ... ? > > > > > Enable the spl. Disable SPI flash temporary, for preventing build > > failed, but this will be enabled back with upcoming patches for > > supporting SPI flash. > What's the problem with SPI flash ? I thought it's the same block as > in > C/A 5 ? > Some compilation error, but i haven't checked it out what errors causing the build failed. My plan is to have SPL and print out working, then following boot from SDMMC, FPGA configuration, DDR up. Once booting from SDMMC working, i will work to boot from QSPI and NAND too. > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote: > On 12/07/2016 12:58 PM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 09:08 AM, Chee Tien Fong wrote: > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > Drivers for reset manager is restructured such that common > > > > functions, > > > > gen5 drivers and Arria10 drivers are moved to reset_manager.c, > > > > reset_manager_gen5.c and reset_manager_arria10.c respectively. > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Cc: Marek Vasut <ma...@denx.de> > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > Cc: Tien Fong <skywind...@gmail.com> > [...] > > > > > > > > > > > > > > +void reset_deassert_dedicated_peripherals(void) > > > > +{ > > > > + int i; > > > > + u32 mask0 = 0; > > > > + u32 mask1 = 0; > > > > + u32 pinmux_addr = SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS; > > > > + u32 mask = 0; > > > > +#if defined(CONFIG_MMC) > > > > + mask |= ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK; > > > > +#elif defined(CONFIG_CADENCE_QSPI) > > > > + mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK; > > > > +#elif defined(CONFIG_NAND_DENALI) > > > > + mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK; > > > > +#else > > > Shouldn't this come from OF instead of being ifdef'd ? > > > > > What is OF? > Device Tree (Open Firmware). > > > > > what is your suggestion to make this function generic for > > all type of flash? > Pull it from OF ? > Why you prefer device tree implementation over #define in defconfig, because there is performance penalty. > > > > > > > > > > > > > +#error "unsupported dedicated peripherals" > > > > +#endif > > > > + mask |= ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK; > > > > + > > > > + /* enable ECC OCP first */ > > > > + clrbits_le32(_manager_base->per0modrst, mask); > > > [...] > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit
On Rab, 2016-12-07 at 14:57 +0100, Marek Vasut wrote: > On 12/07/2016 12:21 PM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:51 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 09:07 AM, Chee Tien Fong wrote: > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Cc: Marek Vasut <ma...@denx.de> > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > Cc: Tien Fong <skywind...@gmail.com> > > > > --- > > > > arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 11 +- > > > > arch/arm/mach-socfpga/system_manager.c |4 +- > > > > drivers/fpga/socfpga.c |7 +- > > > > include/configs/socfpga_arria10_socdk.h| 152 > > > > +-- > > > > 4 files changed, 151 insertions(+), 23 deletions(-) > > > > > > > > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h > > > > b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h > > > > index 902c321..487a5dc 100644 > > > > --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h > > > > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h > > > > @@ -1,7 +1,7 @@ > > > > /* > > > > - * Copyright (C) 2014 Altera Corporation > > > > + * Copyright (C) 2014-2016 Altera Corporation > > > > * > > > > - * SPDX-License-Identifier:GPL-2.0+ > > > > + * SPDX-License-Identifier:GPL-2.0 > > > Can you change license this way ? > > > > > Okay, i will revert this change. I discussed with Chin Liang today, > > and > > we decided to let owner to make the changes. How about the year > > change > > 2014-2016? > To change a license of a file, you need to get an ACK from every > single > contributor to that file. > > Year change I believe is fine. > > [...] > Okay, noted. > > > > > > > > > > > > > @@ -89,6 +120,95 @@ > > > > " root=${qspiroot} rw > > > > rootfstype=${qspirootfstype};"\ > > > > "bootm ${loadaddr} - ${fdt_addr}\0" > > > > > > > > -/* The rest of the configuration is shared */ > > > > -#include > > > > +/* > > > > + * External memory configurations > > > > + */ > > > Why is this being duplicated in board support code when it > > > previously > > > was in common code ? That's just wrong. > > > > > I found that many conflicts between the board support code and > > common > > code. It is safe for Arria10 having its own setting here. What do > > you > > think? > It looks like 95% of the stuff below is the same as the stuff in > socfpga-common.h , the rest can be pulled from DT or ifdef'd . > If socfpga-common.h is preferred, then i have to use ifdef method, are you ok with this? However, this would look a bit messy, because some #define setting in here, and other #define setting in socfpga-common.h under same category or peripheral configuration group. > > > > > > > > > > > > > +#define PHYS_SDRAM_1 0x0 > > > > +#define PHYS_SDRAM_1_SIZE 0x8000 > > > > +#define CONFIG_SYS_SDRAM_BASE 0 > > > > +#define CONFIG_NR_DRAM_BANKS 1 > > > > +#define CONFIG_SYS_MEMTEST_START 0 > > > > +#define CONFIG_SYS_MEMTEST_END 0x10 > > > > + > > > > +/* > > > > + * Serial / UART configurations > > > > + */ > > > > +#define CONFIG_SYS_NS16550_SERIAL > > > > +#define CONFIG_SYS_NS16550_MEM32 > > > > +#define CONFIG_SYS_NS16550_REG_SIZE-4 > > > > +#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART1_ADDRESS > > > > +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, > > > > 57600, 115200} > > > > +#define CONFIG_SYS_NS16550_CLK (5000) > > > > +#define CONFIG_CONS_INDEX 1 > > > > +#define CONFIG_BAUDRATE115200 > > > > + > > > > +/* > > > > + * L4 OSC1 Timer 0 > > > > + */ > > > > +/* This timer use eosc1 where the clock frequency is
Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL
On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > > > > > These changes to ensure Arria10 SPL build success. > > > Please reword the commit message, mention you're removing the > > > Arria10 > > > bits. Still, this does not even apply on mainline, on top of what > > > does > > > this apply ? > > > > > I disabled some features temporary, so SPL build can pass and print > > out > > working. I will enable these features back in upcoming patches. > > This is > > base on 01-arria10 branch. > But this patch seems to only enable stuff ... ? > Enable the spl. Disable SPI flash temporary, for preventing build failed, but this will be enabled back with upcoming patches for supporting SPI flash. > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Cc: Marek Vasut <ma...@denx.de> > > > > Cc: Dinh Nguyen <dingu...@kernel.org> > > > > Cc: Chin Liang See <chin.liang@intel.com> > > > > Cc: Tien Fong <skywind...@gmail.com> > > > > --- > > > > arch/arm/Kconfig |8 > > > > 1 files changed, 4 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > index 220bb19..05ce8b8 100644 > > > > --- a/arch/arm/Kconfig > > > > +++ b/arch/arm/Kconfig > > > > @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON > > > > config ARCH_SOCFPGA > > > > bool "Altera SOCFPGA family" > > > > select CPU_V7 > > > > - select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10 > > > > + select SUPPORT_SPL > > > > select OF_CONTROL > > > > - select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10 > > > > + select SPL_OF_CONTROL > > > > select DM > > > > - select DM_SPI_FLASH > > > > - select DM_SPI > > > > + select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10 > > > > + select DM_SPI if !TARGET_SOCFPGA_ARRIA10 > > > > > > > > config TARGET_CM_T43 > > > > bool "Support cm_t43" > > > > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/10] arm: socfpga: arria10: Added miscellaneous drivers for Arria10
On Sel, 2016-12-06 at 16:26 -0600, dinguyen wrote: > On Tue, 6 Dec 2016, Chee Tien Fong wrote: > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > The drivers is restructured such common functions, gen5 functions, > > and arria10 functions are moved to misc.c, misc_gen5 and > > misc_arria10 > > respectively. > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vasut <ma...@denx.de> > > Cc: Dinh Nguyen <dingu...@kernel.org> > > Cc: Chin Liang See <chin.liang@intel.com> > > Cc: Tien Fong <skywind...@gmail.com> > > --- > > arch/arm/mach-socfpga/Makefile|4 +- > > arch/arm/mach-socfpga/include/mach/misc.h | 25 ++ > > arch/arm/mach-socfpga/misc.c | 429 +-- > > - > > arch/arm/mach-socfpga/misc_arria10.c | 111 > > arch/arm/mach-socfpga/misc_gen5.c | 363 > > > > 5 files changed, 517 insertions(+), 415 deletions(-) > > create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h > > create mode 100644 arch/arm/mach-socfpga/misc_arria10.c > > create mode 100644 arch/arm/mach-socfpga/misc_gen5.c > > > The previous patches in this series applied to Marek's 01-arria10 > branch, > but this patch does not apply at all: > > error: patch failed: arch/arm/mach-socfpga/misc.c:361 > error: arch/arm/mach-socfpga/misc.c: patch does not apply > > Also, on the next revision, please add -C to git format-patch. > > Dinh Sorry to hear that. It is too weird the patch didn't applied, but i have no issue with this patch. Are you using git am command? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote: > On 12/06/2016 09:08 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Drivers for reset manager is restructured such that common > > functions, > > gen5 drivers and Arria10 drivers are moved to reset_manager.c, > > reset_manager_gen5.c and reset_manager_arria10.c respectively. > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vasut <ma...@denx.de> > > Cc: Dinh Nguyen <dingu...@kernel.org> > > Cc: Chin Liang See <chin.liang@intel.com> > > Cc: Tien Fong <skywind...@gmail.com> > > --- > > arch/arm/mach-socfpga/Makefile | 16 +- > > arch/arm/mach-socfpga/include/mach/reset_manager.h | 164 -- > > arch/arm/mach-socfpga/reset_manager.c | 114 +--- > > arch/arm/mach-socfpga/reset_manager_arria10.c | 766 > > > > arch/arm/mach-socfpga/reset_manager_gen5.c | 116 +++ > > 5 files changed, 1017 insertions(+), 159 deletions(-) > > create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c > > create mode 100644 arch/arm/mach-socfpga/reset_manager_gen5.c > > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach- > > socfpga/Makefile > > index 809cd47..b8fcf6e 100644 > > --- a/arch/arm/mach-socfpga/Makefile > > +++ b/arch/arm/mach-socfpga/Makefile > > @@ -2,21 +2,27 @@ > > # (C) Copyright 2000-2003 > > # Wolfgang Denk, DENX Software Engineering, w...@denx.de. > > # > > -# Copyright (C) 2012 Altera Corporation > > +# Copyright (C) 2012-2016 Altera Corporation > > # > > # SPDX-License-Identifier: GPL-2.0+ > > # > > > > obj-y += misc.o timer.o reset_manager.o system_manager.o > > clock_manager.o \ > > fpga_manager.o board.o > > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o > > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o > > wrap_pll_config.o \ > > + reset_manager_gen5.o > > > > -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o > > +ifdef CONFIG_SPL_BUILD > > +obj-y += spl.o > > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o > > wrap_iocsr_config.o \ > > + wrap_pinmux_config.o > > wrap_sdram_config.o > > +endif > > > > +ifdef CONFIG_TARGET_SOCFPGA_GEN5 > > # QTS-generated config file wrappers > > -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o > > wrap_pll_config.o > > -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o > > wrap_pinmux_config.o\ > > - wrap_sdram_config.o > > CFLAGS_wrap_iocsr_config.o += > > -I$(srctree)/board/$(BOARDDIR) > > CFLAGS_wrap_pinmux_config.o+= > > -I$(srctree)/board/$(BOARDDIR) > > CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR) > > CFLAGS_wrap_sdram_config.o += > > -I$(srctree)/board/$(BOARDDIR) > > +endif > > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h > > b/arch/arm/mach-socfpga/include/mach/reset_manager.h > > index 6225118..077391a 100644 > > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h > > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h > > @@ -1,19 +1,32 @@ > > /* > > - * Copyright (C) 2012 Altera Corporation > > + * Copyright (C) 2012-2016 Altera Corporation > > * > > - * SPDX-License-Identifier:GPL-2.0+ > > + * SPDX-License-Identifier:GPL-2.0 > License change ? > i will revert it. > > > > */ > > > > #ifndef_RESET_MANAGER_H_ > > #define_RESET_MANAGER_H_ > > > > -void reset_cpu(ulong addr); > > -void reset_deassert_peripherals_handoff(void); > > +/* Common function prototypes */ > > +extern void reset_cpu(ulong addr); > > +extern void socfpga_bridges_reset(int enable); > > +extern void socfpga_per_reset(u32 reset, int set); > > +extern void socfpga_per_reset_all(void); > Drop the extern ... > okay. > > > > -void socfpga_bridges_reset(int enable); > > - > > -void socfpga_per_reset(u32 reset, int set); > > -void socfpga_per_reset_all(void); > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > +extern void reset_deassert_peripherals_handoff(void); > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > +extern void watchdog_disable(void); > > +extern void reset_deassert_noc_ddr_scheduler(void); > > +extern int is_
Re: [U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit
On Sel, 2016-12-06 at 13:51 +0100, Marek Vasut wrote: > On 12/06/2016 09:07 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vasut <ma...@denx.de> > > Cc: Dinh Nguyen <dingu...@kernel.org> > > Cc: Chin Liang See <chin.liang@intel.com> > > Cc: Tien Fong <skywind...@gmail.com> > > --- > > arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 11 +- > > arch/arm/mach-socfpga/system_manager.c |4 +- > > drivers/fpga/socfpga.c |7 +- > > include/configs/socfpga_arria10_socdk.h| 152 > > +-- > > 4 files changed, 151 insertions(+), 23 deletions(-) > > > > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h > > b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h > > index 902c321..487a5dc 100644 > > --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h > > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h > > @@ -1,7 +1,7 @@ > > /* > > - * Copyright (C) 2014 Altera Corporation > > + * Copyright (C) 2014-2016 Altera Corporation > > * > > - * SPDX-License-Identifier:GPL-2.0+ > > + * SPDX-License-Identifier:GPL-2.0 > Can you change license this way ? > Okay, i will revert this change. I discussed with Chin Liang today, and we decided to let owner to make the changes. How about the year change 2014-2016? > > > > */ > > > > #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_ > > @@ -35,11 +35,14 @@ > > > > #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 > > #define SOCFPGA_UART0_ADDRESS 0xffc02000 > > -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 > > +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd0 > > +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 > > #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 > > #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 > This should be in a separate patch. > > > > > -#define SOCFPGA_SDR_ADDRESS0xffcfb000 > > +#define SOCFPGA_SDR_ADDRESS > > 0xffcfb000 > > +#define SOCFPGA_NOC_L4_PRIV_FLT_OFST0xffd11000 > > +#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13 > > 500 > > #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 > > #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 > > #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300 > > diff --git a/arch/arm/mach-socfpga/system_manager.c > > b/arch/arm/mach-socfpga/system_manager.c > > index 9e1c3fd..e1f0082 100644 > > --- a/arch/arm/mach-socfpga/system_manager.c > > +++ b/arch/arm/mach-socfpga/system_manager.c > This should also be in a separate patch, don't go hacking common code > in > board-support patch. > Okay, i will move these changes to separate patch. Those removed #define is no longer valid. > > > > @@ -1,5 +1,5 @@ > > /* > > - * Copyright (C) 2013 Altera Corporation > > + * Copyright (C) 2013-2016 Altera Corporation > > * > > * SPDX-License-Identifier:GPL-2.0+ > > */ > > @@ -11,8 +11,10 @@ > > > > DECLARE_GLOBAL_DATA_PTR; > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > static struct socfpga_system_manager *sysmgr_regs = > > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > +#endif > > > > /* > > * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux > > setting. > > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c > > index bfefafd..7fd922e 100644 > > --- a/drivers/fpga/socfpga.c > > +++ b/drivers/fpga/socfpga.c > > @@ -1,5 +1,5 @@ > > /* > > - * Copyright (C) 2012 Altera Corporation > > + * Copyright (C) 2012-2016 Altera Corporation > > * All rights reserved. > > * > > * SPDX-License-Identifier:BSD-3-Clause > > @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; > > > > static struct socfpga_fpga_manager *fpgamgr_regs = > > (struct socfpga_fpga_manager > > *)SOCFPGA_FPGAMGRREGS_ADDRESS; > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > static struct socfpga_system_manager *sysmgr_regs = > > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > +#endif > > > > /* Set CD ratio */ > > static void fpgamgr_set_cd_ratio(unsigned long ratio) > &g
Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL
On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote: > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > These changes to ensure Arria10 SPL build success. > Please reword the commit message, mention you're removing the Arria10 > bits. Still, this does not even apply on mainline, on top of what > does > this apply ? > I disabled some features temporary, so SPL build can pass and print out working. I will enable these features back in upcoming patches. This is base on 01-arria10 branch. > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vasut <ma...@denx.de> > > Cc: Dinh Nguyen <dingu...@kernel.org> > > Cc: Chin Liang See <chin.liang@intel.com> > > Cc: Tien Fong <skywind...@gmail.com> > > --- > > arch/arm/Kconfig |8 > > 1 files changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 220bb19..05ce8b8 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON > > config ARCH_SOCFPGA > > bool "Altera SOCFPGA family" > > select CPU_V7 > > - select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10 > > + select SUPPORT_SPL > > select OF_CONTROL > > - select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10 > > + select SPL_OF_CONTROL > > select DM > > - select DM_SPI_FLASH > > - select DM_SPI > > + select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10 > > + select DM_SPI if !TARGET_SOCFPGA_ARRIA10 > > > > config TARGET_CM_T43 > > bool "Support cm_t43" > > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro
On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote: > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > These compat macros would be used by clock manager and pin mux > > drivers > > to look the required HW info from DTS for hardware initialization. > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vasut <ma...@denx.de> > > Cc: Dinh Nguyen <dingu...@kernel.org> > > Cc: Chin Liang See <chin.liang@intel.com> > > Cc: Tien Fong <skywind...@gmail.com> > > --- > > include/fdtdec.h |8 > > lib/fdtdec.c |2 ++ > > 2 files changed, 10 insertions(+), 0 deletions(-) > > > > diff --git a/include/fdtdec.h b/include/fdtdec.h > > index 27887c8..68cb199 100644 > > --- a/include/fdtdec.h > > +++ b/include/fdtdec.h > > @@ -155,6 +155,14 @@ enum fdt_compat_id { > > COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory- > > down params */ > > COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP > > */ > > COMPAT_SUNXI_NAND, /* SUNXI NAND controller > > */ > > + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock > > initialization */ > > + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* pinctrl- > > single */ > > + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* Arria10 > > hps2fpga bridge */ > > + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 > > lwhps2fpga bridge */ > > + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* Arria10 > > fpga2hps bridge */ > > + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* Arria10 > > fpga2SDRAM0 bridge */ > > + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* Arria10 > > fpga2SDRAM1 bridge */ > > + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* Arria10 > > fpga2SDRAM2 bridge */ > Is all of this needed ? You're only adding two entries in the FDTDEC > below. > This is to avoid compilation error, we have some functions ported from our internal branch, which using above COMPAT macro. Soon, in upcoming patches, we will need those functions and more entries will be added into FDTDEC below. > > > > > > COMPAT_COUNT, > > }; > > diff --git a/lib/fdtdec.c b/lib/fdtdec.c > > index 4defb90..09a1db4 100644 > > --- a/lib/fdtdec.c > > +++ b/lib/fdtdec.c > > @@ -66,6 +66,8 @@ static const char * const > > compat_names[COMPAT_COUNT] = { > > COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), > > COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), > > COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), > > + COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"), > > + COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"), > > }; > > > > const char *fdtdec_get_compatible(enum fdt_compat_id id) > > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL
On Sel, 2016-12-06 at 13:48 +0100, Marek Vasut wrote: > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Enhanced defconfig file for Arria10 to enable SPL build and > > supporting > > device tree build for SDMMC. > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vasut <ma...@denx.de> > > Cc: Dinh Nguyen <dingu...@kernel.org> > > Cc: Chin Liang See <chin.liang@intel.com> > > Cc: Tien Fong <skywind...@gmail.com> > > --- > > arch/arm/mach-socfpga/include/mach/boot0.h | 17 > > + > > configs/socfpga_arria10_defconfig | 18 +--- > > -- > > 2 files changed, 30 insertions(+), 5 deletions(-) > > create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h > > > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h > > b/arch/arm/mach-socfpga/include/mach/boot0.h > > new file mode 100644 > > index 000..8052a0b > > --- /dev/null > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h > > @@ -0,0 +1,17 @@ > > +/* > > + * Copyright (C) 2016, Intel Corporation > > + * > > + * SPDX-License-Identifier:GPL-2.0 > > + */ > > + > > +#ifndef __BOOT0_H > > +#define __BOOT0_H > > + > > +#if (defined(CONFIG_ARCH_SOCFPGA) && defined(CONFIG_SPL_BUILD)) > > +/* BOOT0 header information */ > > +#define ARM_SOC_BOOT0_HOOK \ > > + .fill 12, 4, 0xdeadbeef > Seems unrelated and something that was fixed in mainline already. > Okay. We need the fixed sync from mainline, otherwise spl would not working. > > > > +#else > > +#define ARM_SOC_BOOT0_HOOK > > +#endif > > +#endif /* __BOOT0_H */ > > diff --git a/configs/socfpga_arria10_defconfig > > b/configs/socfpga_arria10_defconfig > > index 422261b..755bb66 100644 > > --- a/configs/socfpga_arria10_defconfig > > +++ b/configs/socfpga_arria10_defconfig > > @@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y > > CONFIG_TARGET_SOCFPGA_ARRIA10=y > > CONFIG_DM_GPIO=y > > CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y > > -CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk" > > +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" > > +CONFIG_IDENT_STRING="socfpga_arria10" > > # CONFIG_CMD_IMLS is not set > > # CONFIG_CMD_FLASH is not set > > CONFIG_CMD_GPIO=y > > CONFIG_DWAPB_GPIO=y > > -CONFIG_DM_ETH=y > > -CONFIG_ETH_DESIGNWARE=y > > CONFIG_SYS_NS16550=y > > -CONFIG_CADENCE_QSPI=y > > -CONFIG_DESIGNWARE_SPI=y > > CONFIG_DM_MMC=y > > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > > +CONFIG_CMD_MMC=y > > +CONFIG_USE_TINY_PRINTF=y > > +CONFIG_SPL=y > > +CONFIG_SPL_DM=y > > +CONFIG_SPL_SIMPLE_BUS=y > > +CONFIG_SPL_DM_SEQ_ALIAS=y > > +CONFIG_SPL_MMC_SUPPORT=y > > +CONFIG_SPL_SERIAL_SUPPORT=y > > +CONFIG_SPL_OF_LIBFDT=y > > +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y > > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/10] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc
On Sel, 2016-12-06 at 13:44 +0100, Marek Vasut wrote: > On 12/06/2016 08:50 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > This is initial version of device tree for the Intel socfpga > > arria10 > > development kit with sdmmc. > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vasut <ma...@denx.de> > > Cc: Dinh Nguyen <dingu...@kernel.org> > > Cc: Chin Liang See <chin.liang@intel.com> > > Cc: Tien Fong <skywind...@gmail.com> > > --- > > arch/arm/dts/Makefile |3 +- > > arch/arm/dts/socfpga_arria10.dtsi | 859 > > +++ > > arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi | 473 > > + > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts| 33 + > > 4 files changed, 1367 insertions(+), 1 deletions(-) > > create mode 100644 arch/arm/dts/socfpga_arria10.dtsi > > create mode 100644 arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi > Isn't the handoff file board-specific ? > board and flash specific. How bout this name "socfpga_arria10_socdk_sdmmc_handoff"? > > > > create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts > Does this patchset somehow supersede the previous one [1] or what is > the > plan here ? > Yeah, the series patches here based on 01-arria10. > [1] > http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/hea > ds/01-arria10 > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/10] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl
From: Tien Fong CheeThis patch adding the Arria10 critical hardware initialization before enabling console print out in spl. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/spl.c | 86 +- 1 files changed, 83 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index fec4c7a..9375514 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -1,7 +1,7 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2016 Altera Corporation * - * SPDX-License-Identifier:GPL-2.0+ + * SPDX-License-Identifier:GPL-2.0 */ #include @@ -19,22 +19,32 @@ #include #include #include +#include +#include +#include +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include +#endif DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = +#endif + +static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; u32 spl_boot_device(void) { const u32 bsel = readl(_regs->bootinfo); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) switch (bsel & 0x7) { case 0x1: /* FPGA (HPS2FPGA Bridge) */ return BOOT_DEVICE_RAM; @@ -55,6 +65,24 @@ u32 spl_boot_device(void) printf("Invalid boot device (bsel=%08x)!\n", bsel); hang(); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + switch ((bsel>>12) & 0x7) { + case 0x1: /* FPGA (HPS2FPGA Bridge) */ + return BOOT_DEVICE_RAM; + case 0x2: /* NAND Flash (1.8V) */ + case 0x3: /* NAND Flash (3.0V) */ + return BOOT_DEVICE_NAND; + case 0x4: /* SD/MMC External Transceiver (1.8V) */ + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ + return BOOT_DEVICE_MMC1; + case 0x6: /* QSPI Flash (1.8V) */ + case 0x7: /* QSPI Flash (3.0V) */ + return BOOT_DEVICE_SPI; + default: + printf("Invalid boot device (bsel=%08x)!\n", bsel); + hang(); + } +#endif } #ifdef CONFIG_SPL_MMC_SUPPORT @@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void socfpga_nic301_slave_ns(void) { writel(0x1, _regs->lwhps2fpgaregs); @@ -182,3 +211,54 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +void board_init_f(ulong dummy) +{ + memset(__bss_start, 0, __bss_end - __bss_start); + /* +* Configure Clock Manager to use intosc clock instead external osc to +* ensure success watchdog operation. We do it as early as possible. +*/ + cm_use_intosc(); + + watchdog_disable(); + + arch_early_init_r(); + +#ifdef CONFIG_HW_WATCHDOG + /* release osc1 watchdog timer 0 from reset */ + reset_deassert_osc1wd0(); + + /* reconfigure and enable the watchdog */ + hw_watchdog_init(); + WATCHDOG_RESET(); +#endif /* CONFIG_HW_WATCHDOG */ + +#ifdef CONFIG_OF_CONTROL + /* We need to access to FDT as this stage */ + /* FDT is at end of image */ + gd->fdt_blob = (void *)(__bss_end); + /* Check whether we have a valid FDT or not. */ + if (fdtdec_prepare_fdt()) { + panic("** CONFIG_OF_CONTROL defined but no FDT - please see " + "doc/README.fdt-control"); + } +#endif /* CONFIG_OF_CONTROL */ + + /* Initialize the timer */ + timer_init(); + + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + WATCHDOG_RESET(); + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); + + /* configure the Reset Manager */ + reset_deassert_dedicated_peripherals(); + + /* enable console uart printing */ + preloader_console_init(); +} +#endif -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/10] arm: socfpga: arria10: Added drivers for Arria10 pin mux/pins configuration
From: Tien Fong CheeSigned-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/Makefile |2 +- arch/arm/mach-socfpga/include/mach/pinmux.h | 17 + arch/arm/mach-socfpga/pinmux.c | 104 +++ 3 files changed, 122 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h create mode 100644 arch/arm/mach-socfpga/pinmux.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 71cf31c..1ab68be 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -10,7 +10,7 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o board.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o \ - clock_manager_arria10.o + clock_manager_arria10.o pinmux.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ reset_manager_gen5.o misc_gen5.o \ clock_manager_gen5.o diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h b/arch/arm/mach-socfpga/include/mach/pinmux.h new file mode 100644 index 000..e7d831d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/pinmux.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef_PINMUX_H_ +#define_PINMUX_H_ + +#ifndef __ASSEMBLY__ +extern int config_dedicated_pins(const void *blob); +extern int config_pins(const void *blob, const char *pin_grp); +#endif + + + +#endif /* _PINMUX_H_ */ diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c new file mode 100644 index 000..d45722f --- /dev/null +++ b/arch/arm/mach-socfpga/pinmux.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016 Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include +#include +#include + +int config_dedicated_pins(const void *blob); +int config_pins(const void *blob, const char *pin_grp); +static int __do_pinctr_pins(const void *blob, int child, const char *node_name); +static int do_pinctrl_pins(const void *blob, int node, const char *child_name); + +static int __do_pinctr_pins(const void *blob, int child, const char *node_name) +{ + int len; + fdt_addr_t base_addr; + fdt_size_t size; + const u32 *cell; + u32 offset, value; + + base_addr = fdtdec_get_addr_size(blob, child, "reg", ); + if (base_addr != FDT_ADDR_T_NONE) { + cell = fdt_getprop(blob, child, "pinctrl-single,pins", + ); + if (cell != NULL) { + debug("%p %d\n", cell, len); + for (;len > 0; len -= (2*sizeof(u32))) { + offset = fdt32_to_cpu(*cell++); + value = fdt32_to_cpu(*cell++); + debug("<0x%x 0x%x>\n", offset, value); + writel(value, base_addr + offset); + } + return 0; + } + } + return 1; +} + +static int do_pinctrl_pins(const void *blob, int node, const char *child_name) +{ + int child, len; + const char *node_name; + + child = fdt_first_subnode(blob, node); + + if (child < 0) + return 2; + + node_name = fdt_get_name(blob, child, ); + + while (node_name) { + if (!strcmp(child_name, node_name)) { + __do_pinctr_pins(blob, child, node_name); + return(0); + } + child = fdt_next_subnode(blob, child); + + if (child < 0) + break; + + node_name = fdt_get_name(blob, child, ); + } + + return 1; +} + +int config_dedicated_pins(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return 1; + + if (do_pinctrl_pins(blob, node, "dedicated_cfg")) + return 2; + + if (do_pinctrl_pins(blob, node, "dedicated")) + return 3; + + return 0; +} + +int config_pins(const void *blob, const char *pin_grp) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + + if (node < 0) + return 1; + + if (do_pinctrl_pins(blob, node, pin_grp)) + return 2; + + return 0; +} -- 1.7.7.4 ___ U-Boot mailing list
[U-Boot] [PATCH 08/10] arm: socfpga: arria10: Added drivers for Arria10 clock manager
From: Tien Fong CheeThe drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, cock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/Makefile |6 +- arch/arm/mach-socfpga/clock_manager.c | 754 +++- arch/arm/mach-socfpga/clock_manager_arria10.c | 954 arch/arm/mach-socfpga/clock_manager_gen5.c | 342 +++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 360 ++-- 5 files changed, 1910 insertions(+), 506 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c create mode 100644 arch/arm/mach-socfpga/clock_manager_gen5.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index f8b529e..71cf31c 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,9 +9,11 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o board.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o \ + clock_manager_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ - reset_manager_gen5.o misc_gen5.o + reset_manager_gen5.o misc_gen5.o \ + clock_manager_gen5.o ifdef CONFIG_SPL_BUILD obj-y += spl.o diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index aa71636..fe82c39 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -1,422 +1,293 @@ /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013-2016 Intel Corporation * - * SPDX-License-Identifier:GPL-2.0+ + * SPDX-License-Identifier:GPL-2.0 */ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +/* Function prototypes */ +/* Common prototypes */ +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); +static void cm_print_clock_quick_summary(void); +int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +void cm_wait_for_lock(uint32_t mask); +void cm_wait_for_fsm(void); +unsigned int cm_get_main_vco_clk_hz(void); +unsigned int cm_get_per_vco_clk_hz(void); +unsigned long cm_get_mpu_clk_hz(void); + static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; -static void cm_wait_for_lock(uint32_t mask) +/* Common functions */ +int set_cpu_clk_info(void) { - register uint32_t inter_val; - uint32_t retry = 0; - do { - inter_val = readl(_manager_base->inter) & mask; - if (inter_val == mask) - retry++; - else - retry = 0; - if (retry >= 10) - break; - } while (1); -} + /* Calculate the clock frequencies required for drivers */ + cm_get_l4_sp_clk_hz(); + cm_get_mmc_controller_clk_hz(); -/* function to poll in the fsm busy bit */ -static void cm_wait_for_fsm(void) -{ - while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY) - ; -} + gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100; + gd->bd->bi_dsp_freq = 0; -/* - * function to write the bypass register which requires a poll of the - * busy bit - */ -static void cm_write_bypass(uint32_t val) -{ - writel(val, _manager_base->bypass); - cm_wait_for_fsm(); -} +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) + gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100; +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + gd->bd->bi_ddr_freq = 0; +#endif -/* function to write the ctrl register which requires a poll of the busy bit */ -static void cm_write_ctrl(uint32_t val) -{ - writel(val, _manager_base->ctrl); - cm_wait_for_fsm(); + return 0; } -/* function to write a clock register that has phase information */ -static void cm_write_with_phase(uint32_t value, - uint32_t reg_address, uint32_t mask) +unsigned int cm_get_spi_controller_clk_hz(void) { - /* poll until phase is zero */ - while (readl(reg_address) & mask) - ; + uint32_t clock = 0; - writel(value, reg_address); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) + uint32_t reg; + clock = cm_get_per_vco_clk_hz(); -
[U-Boot] [PATCH 07/10] arm: socfpga: arria10: Added miscellaneous drivers for Arria10
From: Tien Fong CheeThe drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/Makefile|4 +- arch/arm/mach-socfpga/include/mach/misc.h | 25 ++ arch/arm/mach-socfpga/misc.c | 429 +--- arch/arm/mach-socfpga/misc_arria10.c | 111 arch/arm/mach-socfpga/misc_gen5.c | 363 5 files changed, 517 insertions(+), 415 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h create mode 100644 arch/arm/mach-socfpga/misc_arria10.c create mode 100644 arch/arm/mach-socfpga/misc_gen5.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index b8fcf6e..f8b529e 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,9 +9,9 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o board.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ - reset_manager_gen5.o + reset_manager_gen5.o misc_gen5.o ifdef CONFIG_SPL_BUILD obj-y += spl.o diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h new file mode 100644 index 000..1bf1783 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016, Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _MISC_H_ +#define_MISC_H_ + +extern void dwmac_deassert_reset(const unsigned int of_reset_id, +const u32 phymode); + +struct bsel{ + const char *mode; + const char *name; +}; + +extern struct bsel bsel_str[]; + +#ifdef CONFIG_FPGA +extern void socfpga_fpga_add(void); +#else +inline void socfpga_fpga_add(void) {} +#endif +#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 00e385f..f44233d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,51 +1,39 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2016 Altera Corporation * - * SPDX-License-Identifier:GPL-2.0+ + * SPDX-License-Identifier:GPL-2.0 */ #include #include #include -#include -#include #include #include #include #include +#include #include -#include #include #include #include #include #include -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#include -#else -#include -#endif - DECLARE_GLOBAL_DATA_PTR; -static struct pl310_regs *const pl310 = +static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_reset_manager *reset_manager_base = - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -static struct nic301_registers *nic301_regs = - (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -#else -static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = - (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; -static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = - (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; -#endif -static struct scu_registers *scu_regs = - (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; + +struct bselbsel_str[] = { + { "rsvd", "Reserved", }, + { "fpga", "FPGA (HPS2FPGA Bridge)", }, + { "nand", "NAND Flash (1.8V)", }, + { "nand", "NAND Flash (3.0V)", }, + { "sd", "SD/MMC External Transceiver (1.8V)", }, + { "sd", "SD/MMC Internal Transceiver (3.0V)", }, + { "qspi", "QSPI Flash (1.8V)", }, + { "qspi", "QSPI Flash (3.0V)", }, +}; int dram_init(void) { @@ -84,219 +72,6 @@ void v7_outer_cache_disable(void) clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN); } -/* - * DesignWare Ethernet initialization - */ -#ifdef CONFIG_ETH_DESIGNWARE -static void dwmac_deassert_reset(const unsigned int of_reset_id, -const u32 phymode) -{ - u32 physhift, reset; - - if (of_reset_id == EMAC0_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; - reset = SOCFPGA_RESET(EMAC0); - } else if (of_reset_id == EMAC1_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; - reset = SOCFPGA_RESET(EMAC1);
[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro
From: Tien Fong CheeThese compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- include/fdtdec.h |8 lib/fdtdec.c |2 ++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/include/fdtdec.h b/include/fdtdec.h index 27887c8..68cb199 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -155,6 +155,14 @@ enum fdt_compat_id { COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* pinctrl-single */ + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* Arria10 hps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 lwhps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* Arria10 fpga2hps bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* Arria10 fpga2SDRAM0 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* Arria10 fpga2SDRAM1 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* Arria10 fpga2SDRAM2 bridge */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 4defb90..09a1db4 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -66,6 +66,8 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), + COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"), + COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
From: Tien Fong CheeDrivers for reset manager is restructured such that common functions, gen5 drivers and Arria10 drivers are moved to reset_manager.c, reset_manager_gen5.c and reset_manager_arria10.c respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/Makefile | 16 +- arch/arm/mach-socfpga/include/mach/reset_manager.h | 164 -- arch/arm/mach-socfpga/reset_manager.c | 114 +--- arch/arm/mach-socfpga/reset_manager_arria10.c | 766 arch/arm/mach-socfpga/reset_manager_gen5.c | 116 +++ 5 files changed, 1017 insertions(+), 159 deletions(-) create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c create mode 100644 arch/arm/mach-socfpga/reset_manager_gen5.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 809cd47..b8fcf6e 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -2,21 +2,27 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, w...@denx.de. # -# Copyright (C) 2012 Altera Corporation +# Copyright (C) 2012-2016 Altera Corporation # # SPDX-License-Identifier: GPL-2.0+ # obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o board.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ + reset_manager_gen5.o -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \ + wrap_pinmux_config.o wrap_sdram_config.o +endif +ifdef CONFIG_TARGET_SOCFPGA_GEN5 # QTS-generated config file wrappers -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\ - wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR) +endif diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 6225118..077391a 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -1,19 +1,32 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2016 Altera Corporation * - * SPDX-License-Identifier:GPL-2.0+ + * SPDX-License-Identifier:GPL-2.0 */ #ifndef_RESET_MANAGER_H_ #define_RESET_MANAGER_H_ -void reset_cpu(ulong addr); -void reset_deassert_peripherals_handoff(void); +/* Common function prototypes */ +extern void reset_cpu(ulong addr); +extern void socfpga_bridges_reset(int enable); +extern void socfpga_per_reset(u32 reset, int set); +extern void socfpga_per_reset_all(void); -void socfpga_bridges_reset(int enable); - -void socfpga_per_reset(u32 reset, int set); -void socfpga_per_reset_all(void); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +extern void reset_deassert_peripherals_handoff(void); +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +extern void watchdog_disable(void); +extern void reset_deassert_noc_ddr_scheduler(void); +extern int is_wdt_in_reset(void); +extern void emac_manage_reset(ulong emacbase, uint state); +extern int reset_deassert_bridges_handoff(void); +extern void reset_deassert_dedicated_peripherals(void); +extern void reset_assert_fpga_connected_peripherals(void); +extern void reset_deassert_fpga_connected_peripherals(void); +extern void reset_deassert_shared_connected_peripherals(void); +extern void reset_deassert_osc1wd0(void); +#endif #if defined(CONFIG_TARGET_SOCFPGA_GEN5) struct socfpga_reset_manager { @@ -29,40 +42,40 @@ struct socfpga_reset_manager { u32 padding2[12]; u32 tstscratch; }; -#else +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) struct socfpga_reset_manager { - u32 stat; - u32 ramstat; - u32 miscstat; - u32 ctrl; - u32 hdsken; - u32 hdskreq; - u32 hdskack; - u32 counts; - u32 mpu_mod_reset; - u32 per_mod_reset; /* stated as per0_mod_reset in A10 datasheet */ - u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */ - u32 brg_mod_reset; - u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */ - u32 coldmodrst; - u32 nrstmodrst; - u32 dbgmodrst; - u32
[U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit
From: Tien Fong CheeSigned-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 11 +- arch/arm/mach-socfpga/system_manager.c |4 +- drivers/fpga/socfpga.c |7 +- include/configs/socfpga_arria10_socdk.h| 152 +-- 4 files changed, 151 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index 902c321..487a5dc 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -1,7 +1,7 @@ /* - * Copyright (C) 2014 Altera Corporation + * Copyright (C) 2014-2016 Altera Corporation * - * SPDX-License-Identifier:GPL-2.0+ + * SPDX-License-Identifier:GPL-2.0 */ #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_ @@ -35,11 +35,14 @@ #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd0 +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 -#define SOCFPGA_SDR_ADDRESS0xffcfb000 +#define SOCFPGA_SDR_ADDRESS0xffcfb000 +#define SOCFPGA_NOC_L4_PRIV_FLT_OFST0xffd11000 +#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300 diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 9e1c3fd..e1f0082 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013-2016 Altera Corporation * * SPDX-License-Identifier:GPL-2.0+ */ @@ -11,8 +11,10 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif /* * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index bfefafd..7fd922e 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2016 Altera Corporation * All rights reserved. * * SPDX-License-Identifier:BSD-3-Clause @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif /* Set CD ratio */ static void fpgamgr_set_cd_ratio(unsigned long ratio) @@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) } /* Prior programming the FPGA, all bridges need to be shut off */ - +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Disable all signals from hps peripheral controller to fpga */ writel(0, _regs->fpgaintfgrp_module); +#endif /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080 diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 577f60f..15c7a28 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Altera Corporation + * Copyright (C) 2015-2016 Altera Corporation * * SPDX-License-Identifier:GPL-2.0 */ @@ -16,36 +16,67 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MMC #define CONFIG_CMD_PING -/* - * Memory configurations - */ -#define PHYS_SDRAM_1_SIZE 0x200 - /* Booting Linux */ -#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE"zImage" #define CONFIG_BOOTARGS"console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#define CONFIG_LOADADDR0x0100 +#define CONFIG_LOADADDR0x8000 #define
[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL
From: Tien Fong CheeThese changes to ensure Arria10 SPL build success. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/Kconfig |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 220bb19..05ce8b8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON config ARCH_SOCFPGA bool "Altera SOCFPGA family" select CPU_V7 - select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10 + select SUPPORT_SPL select OF_CONTROL - select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10 + select SPL_OF_CONTROL select DM - select DM_SPI_FLASH - select DM_SPI + select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10 + select DM_SPI if !TARGET_SOCFPGA_ARRIA10 config TARGET_CM_T43 bool "Support cm_t43" -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL
From: Tien Fong CheeEnhanced defconfig file for Arria10 to enable SPL build and supporting device tree build for SDMMC. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/include/mach/boot0.h | 17 + configs/socfpga_arria10_defconfig | 18 +- 2 files changed, 30 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h new file mode 100644 index 000..8052a0b --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/boot0.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016, Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef __BOOT0_H +#define __BOOT0_H + +#if (defined(CONFIG_ARCH_SOCFPGA) && defined(CONFIG_SPL_BUILD)) +/* BOOT0 header information */ +#define ARM_SOC_BOOT0_HOOK \ + .fill 12, 4, 0xdeadbeef +#else +#define ARM_SOC_BOOT0_HOOK +#endif +#endif /* __BOOT0_H */ diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 422261b..755bb66 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_TARGET_SOCFPGA_ARRIA10=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" +CONFIG_IDENT_STRING="socfpga_arria10" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_DWAPB_GPIO=y -CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_CMD_MMC=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL=y +CONFIG_SPL_DM=y +CONFIG_SPL_SIMPLE_BUS=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_OF_LIBFDT=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y -- 1.7.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/10] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc
From: Tien Fong CheeThis is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/dts/Makefile |3 +- arch/arm/dts/socfpga_arria10.dtsi | 859 +++ arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi | 473 + arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts| 33 + 4 files changed, 1367 insertions(+), 1 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria10.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 032c5ae..72bbc67 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -131,7 +131,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ - socfpga_cyclone5_vining_fpga.dtb + socfpga_cyclone5_vining_fpga.dtb\ + socfpga_arria10_socdk_sdmmc.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi new file mode 100644 index 000..c54addb --- /dev/null +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -0,0 +1,859 @@ +/* + * Copyright (C) 2016 Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include "skeleton.dtsi" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = + ethernet1 = + ethernet2 = + serial0 = + serial1 = + timer0 = + timer1 = + timer2 = + timer3 = + spi0 = + spi1 = + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x4000>; /* 1GB */ + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <>; + }; + }; + + intc: intc@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <>; + ranges; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffda1000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda1000 0x1000>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, +<0 84 IRQ_TYPE_LEVEL_HIGH>, +<0 85 IRQ_TYPE_LEVEL_HIGH>, +<0 86 IRQ_TYPE_LEVEL_HIGH>, +<0 87 IRQ_TYPE_LEVEL_HIGH>, +<0 88 IRQ_TYPE_LEVEL_HIGH>, +<0 89 IRQ_TYPE_LEVEL_HIGH>, +<0 90 IRQ_TYPE_LEVEL_HIGH>, +<0 91 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + reg-names =
[U-Boot] [PATCH 01/10] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc
From: Tien Fong CheeThis is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/dts/Makefile |3 +- arch/arm/dts/socfpga_arria10.dtsi | 859 +++ arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi | 473 + arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts| 33 + 4 files changed, 1367 insertions(+), 1 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria10.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_handoff_sdmmc.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 032c5ae..72bbc67 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -131,7 +131,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ - socfpga_cyclone5_vining_fpga.dtb + socfpga_cyclone5_vining_fpga.dtb\ + socfpga_arria10_socdk_sdmmc.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi new file mode 100644 index 000..c54addb --- /dev/null +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -0,0 +1,859 @@ +/* + * Copyright (C) 2016 Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include "skeleton.dtsi" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = + ethernet1 = + ethernet2 = + serial0 = + serial1 = + timer0 = + timer1 = + timer2 = + timer3 = + spi0 = + spi1 = + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x4000>; /* 1GB */ + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <>; + }; + }; + + intc: intc@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <>; + ranges; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffda1000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda1000 0x1000>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, +<0 84 IRQ_TYPE_LEVEL_HIGH>, +<0 85 IRQ_TYPE_LEVEL_HIGH>, +<0 86 IRQ_TYPE_LEVEL_HIGH>, +<0 87 IRQ_TYPE_LEVEL_HIGH>, +<0 88 IRQ_TYPE_LEVEL_HIGH>, +<0 89 IRQ_TYPE_LEVEL_HIGH>, +<0 90 IRQ_TYPE_LEVEL_HIGH>, +<0 91 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + reg-names =