from:"Chin Liang See"

[U-Boot] [PATCH] arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

2018-02-27 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Enabling cache and TLB maintenance broadcast through ACTLR as required
by Linux.

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/misc_gen5.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/misc_gen5.c 
b/arch/arm/mach-socfpga/misc_gen5.c
index a7dcacc..7c7a708 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -239,7 +239,7 @@ static u32 iswgrp_handoff[8];
 
 int arch_early_init_r(void)
 {
-   int i;
+   int i, val;
 
/*
 * Write magic value into magic register to unlock support for
@@ -285,6 +285,15 @@ int arch_early_init_r(void)
socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 #endif
 
+   /* Enable cache and TLB maintainance broadcast as required by Linux */
+   /* Read auxiliary control register */
+   asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
+   val |= (1 << 0);
+   /* Write auxiliary control register */
+   asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
+   CP15DSB;
+   CP15ISB;
+
return 0;
 }
 
-- 
2.2.2

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[U-Boot] [PATCH v2] arm: socfpga: cyclone5: Enable Macronix flash support

2018-02-27 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Enable Macronix flash support for Cyclone5 SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
Changes for v2
- Undo change for is1, sr1500 and vining
---
 configs/socfpga_cyclone5_defconfig | 1 +
 configs/socfpga_sockit_defconfig   | 1 +
 configs/socfpga_socrates_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 522b6d2..5202f47 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -45,6 +45,7 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 8448913..f421740 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -45,6 +45,7 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_socrates_defconfig 
b/configs/socfpga_socrates_defconfig
index f49ee96..3873c2b 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -46,6 +46,7 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
-- 
2.2.2

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[U-Boot] [PATCH 2/2] arm: socfpga: cyclone5: Ensure spi-flash in the compatible string

2018-02-20 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Ensure "spi-flash" is added into compatible string when there is
NOR flash being instantiated in DTS. Discovered "sf probe" command
without argument would hit error if spi-flash compatible string
is missing.

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/dts/socfpga_cyclone5_is1.dts  | 2 +-
 arch/arm/dts/socfpga_cyclone5_socdk.dts| 2 +-
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts 
b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 2e2b71f..549024c 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -87,7 +87,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
-   compatible = "n25q00";
+   compatible = "n25q00","spi-flash";
reg = <0>;  /* chip select */
spi-max-frequency = <1>;
m25p,fast-read;
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts 
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 95a8e65..e30bf9a 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -98,7 +98,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
-   compatible = "n25q00";
+   compatible = "n25q00","spi-flash";
reg = <0>;  /* chip select */
spi-max-frequency = <1>;
m25p,fast-read;
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts 
b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index e3ae8a8..3e78038 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -68,7 +68,7 @@
flash0: n25q00@0 {
#address-cells = <1>;
#size-cells = <1>;
-   compatible = "n25q00";
+   compatible = "n25q00","spi-flash";
reg = <0>;  /* chip select */
spi-max-frequency = <5000>;
m25p,fast-read;
-- 
2.2.2

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[U-Boot] [PATCH 1/2] arm: socfpga: cyclone5: Enable Macronix flash support

2018-02-20 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Enable Macronix flash support for Cyclone5 SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 configs/socfpga_cyclone5_defconfig| 1 +
 configs/socfpga_is1_defconfig | 1 +
 configs/socfpga_sockit_defconfig  | 1 +
 configs/socfpga_socrates_defconfig| 1 +
 configs/socfpga_sr1500_defconfig  | 1 +
 configs/socfpga_vining_fpga_defconfig | 1 +
 6 files changed, 6 insertions(+)

diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 6ebd8a9..aa535c6 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -53,6 +53,7 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 08628ab..7be720a 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -48,6 +48,7 @@ CONFIG_SYS_I2C_DW=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 8ebe394..6edb47f 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -53,6 +53,7 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_socrates_defconfig 
b/configs/socfpga_socrates_defconfig
index 9f42481..7c2428a 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -54,6 +54,7 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index f9ed1a3..df1ee31 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -53,6 +53,7 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_DM_ETH=y
diff --git a/configs/socfpga_vining_fpga_defconfig 
b/configs/socfpga_vining_fpga_defconfig
index 6670b9f..512d701 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -69,6 +69,7 @@ CONFIG_LED_STATUS_CMD=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-- 
2.2.2

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[U-Boot] [PATCH v2 10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add SPL driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile|   4 +
 arch/arm/mach-socfpga/include/mach/firewall_s10.h |  84 +
 arch/arm/mach-socfpga/spl_s10.c   | 138 ++
 3 files changed, 226 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b669d43..35b124a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -40,6 +40,7 @@ obj-y += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y  += spl_gen5.o
@@ -51,6 +52,9 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y  += spl_a10.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += spl_s10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h 
b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
new file mode 100644
index 000..6894bb9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_FIREWALL_S10_
+#define_FIREWALL_S10_
+
+struct socfpga_firwall_l4_per {
+   u32 nand;   /* 0x00 */
+   u32 nand_data;
+   u32 _pad_0x8;
+   u32 usb0;
+   u32 usb1;   /* 0x10 */
+   u32 _pad_0x14;
+   u32 _pad_0x18;
+   u32 spim0;
+   u32 spim1;  /* 0x20 */
+   u32 spis0;
+   u32 spis1;
+   u32 emac0;
+   u32 emac1;  /* 0x30 */
+   u32 emac2;
+   u32 _pad_0x38;
+   u32 _pad_0x3c;
+   u32 sdmmc;  /* 0x40 */
+   u32 gpio0;
+   u32 gpio1;
+   u32 _pad_0x4c;
+   u32 i2c0;   /* 0x50 */
+   u32 i2c1;
+   u32 i2c2;
+   u32 i2c3;
+   u32 i2c4;   /* 0x60 */
+   u32 timer0;
+   u32 timer1;
+   u32 uart0;
+   u32 uart1;  /* 0x70 */
+};
+
+struct socfpga_firwall_l4_sys {
+   u32 _pad_0x00;  /* 0x00 */
+   u32 _pad_0x04;
+   u32 dma_ecc;
+   u32 emac0rx_ecc;
+   u32 emac0tx_ecc;/* 0x10 */
+   u32 emac1rx_ecc;
+   u32 emac1tx_ecc;
+   u32 emac2rx_ecc;
+   u32 emac2tx_ecc;/* 0x20 */
+   u32 _pad_0x24;
+   u32 _pad_0x28;
+   u32 nand_ecc;
+   u32 nand_read_ecc;  /* 0x30 */
+   u32 nand_write_ecc;
+   u32 ocram_ecc;
+   u32 _pad_0x3c;
+   u32 sdmmc_ecc;  /* 0x40 */
+   u32 usb0_ecc;
+   u32 usb1_ecc;
+   u32 clock_manager;
+   u32 _pad_0x50;  /* 0x50 */
+   u32 io_manager;
+   u32 reset_manager;
+   u32 system_manager;
+   u32 osc0_timer; /* 0x60 */
+   u32 osc1_timer;
+   u32 watchdog0;
+   u32 watchdog1;
+   u32 watchdog2;  /* 0x70 */
+   u32 watchdog3;
+};
+
+#define FIREWALL_L4_DISABLE_ALL(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_BRIDGE_DISABLE_ALL(~0)
+
+#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR 0xf7004688
+#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR  0xf7018628
+
+#define CCU_ADMASK_P_MASK  (BIT(0))
+#define CCU_ADMASK_NS_MASK (BIT(1))
+
+#endif /* _FIREWALL_S10_ */
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
new file mode 100644
index 000..12cafe6
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -0,0 +1,138 @@
+/*
+ *  Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
+   (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
+static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
+   (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
+
+u32 spl_boot_device(void)
+{
+   /* TODO: Get from SDM or handoff */
+/* #ifdef CONFIG_CADENCE_QSPI*/
+#if 0
+   return BOOT_DEVICE_SPI;
+#else
+   return BOOT_DEVICE_MMC1;
+#endif
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+   return MMCSD_MODE_FS;
+#else
+   return MM

[U-Boot] [PATCH v2 07/14] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add MMU support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile|  1 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++
 2 files changed, 72 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 43e18d2..098e5e9 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
 obj-y  += mailbox_s10.o
 obj-y  += misc_s10.o
+obj-y  += mmu-arm64_s10.o
 obj-y  += reset_manager_s10.o
 obj-y  += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c 
b/arch/arm/mach-socfpga/mmu-arm64_s10.c
new file mode 100644
index 000..91c7f2e
--- /dev/null
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+   {
+   /* MEM 2GB*/
+   .virt   = 0x0UL,
+   .phys   = 0x0UL,
+   .size   = 0x8000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* FPGA 1.5GB */
+   .virt   = 0x8000UL,
+   .phys   = 0x8000UL,
+   .size   = 0x6000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* DEVICE 142MB */
+   .virt   = 0xF700UL,
+   .phys   = 0xF700UL,
+   .size   = 0x08E0UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* OCRAM 1MB but available 256KB */
+   .virt   = 0xFFE0UL,
+   .phys   = 0xFFE0UL,
+   .size   = 0x0010UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* DEVICE 32KB */
+   .virt   = 0xFFFCUL,
+   .phys   = 0xFFFCUL,
+   .size   = 0x8000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* MEM 124GB */
+   .virt   = 0x01UL,
+   .phys   = 0x01UL,
+   .size   = 0x1FUL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* DEVICE 4GB */
+   .virt   = 0x20UL,
+   .phys   = 0x20UL,
+   .size   = 0x01UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* List terminator */
+   },
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;
-- 
2.2.2

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[U-Boot] [PATCH v2 11/14] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add timer support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/timer.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index 253cde3..23450b0 100644
--- a/arch/arm/mach-socfpga/timer.c
+++ b/arch/arm/mach-socfpga/timer.c
@@ -1,5 +1,6 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2016-2017 Intel Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -10,15 +11,29 @@
 
 #define TIMER_LOAD_VAL 0x
 
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+#endif
 
 /*
  * Timer initialization
  */
 int timer_init(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+   int enable = 0x3;   /* timer enable + output signal masked */
+   int loadval = ~0;
+
+   /* enable system counter */
+   writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
+   /* enable processor pysical counter */
+   asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
+   asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
+
+#else
writel(TIMER_LOAD_VAL, _base->load_val);
writel(TIMER_LOAD_VAL, _base->curr_val);
writel(readl(_base->ctrl) | 0x3, _base->ctrl);
+#endif
return 0;
 }
-- 
2.2.2

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[U-Boot] [PATCH v2 09/14] arm: socfpga: Restructure the SPL file

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Restructure the SPL so each devices such as CV, A10 and S10
will have their own dedicated SPL file. SPL file determine
the HW initialization flow which is device specific

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile  |   5 +-
 arch/arm/mach-socfpga/spl_a10.c | 105 
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c} |  46 
 3 files changed, 109 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/spl_a10.c
 rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (83%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 098e5e9..b669d43 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -41,13 +41,16 @@ obj-y   += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
-obj-y  += spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += spl_gen5.o
 obj-y  += freeze_controller.o
 obj-y  += wrap_iocsr_config.o
 obj-y  += wrap_pinmux_config.o
 obj-y  += wrap_sdram_config.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y  += spl_a10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
new file mode 100644
index 000..e6fc766
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -0,0 +1,105 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_system_manager *sysmgr_regs =
+   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+u32 spl_boot_device(void)
+{
+   const u32 bsel = readl(_regs->bootinfo);
+
+   switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+   case 0x1:   /* FPGA (HPS2FPGA Bridge) */
+   return BOOT_DEVICE_RAM;
+   case 0x2:   /* NAND Flash (1.8V) */
+   case 0x3:   /* NAND Flash (3.0V) */
+   socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+   return BOOT_DEVICE_NAND;
+   case 0x4:   /* SD/MMC External Transceiver (1.8V) */
+   case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+   socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+   socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+   return BOOT_DEVICE_MMC1;
+   case 0x6:   /* QSPI Flash (1.8V) */
+   case 0x7:   /* QSPI Flash (3.0V) */
+   socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+   return BOOT_DEVICE_SPI;
+   default:
+   printf("Invalid boot device (bsel=%08x)!\n", bsel);
+   hang();
+   }
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+   return MMCSD_MODE_FS;
+#else
+   return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void spl_board_init(void)
+{
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   socfpga_reset_uart(0);
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   socfpga_watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   socfpga_reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+}
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl_gen5.c
similarity index 83%
rename from arch/arm/mach-socfpga/spl.c
rename to arch/arm/mach-socfpga/spl_gen5.c
index 71bae82..9864082 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -22,21 +22,15 @@
 #include 
 #include 
 #include 
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#include 
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#endif
-
 static const struct socfpga_system_m

[U-Boot] [PATCH v2 14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add build support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/Kconfig  |   8 +-
 arch/arm/mach-socfpga/Kconfig |  13 ++
 configs/socfpga_stratix10_defconfig   |  39 ++
 include/configs/socfpga_stratix10_socdk.h | 216 ++
 4 files changed, 273 insertions(+), 3 deletions(-)
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d6d9558..4a6b9da 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -656,21 +656,23 @@ config ARCH_SNAPDRAGON
 
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
-   select CPU_V7
+   select CPU_V7 if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+   select ARM64 if TARGET_SOCFPGA_STRATIX10
select SUPPORT_SPL
select OF_CONTROL
select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
-   select ENABLE_ARM_SOC_BOOT0_HOOK
+   select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || 
TARGET_SOCFPGA_ARRIA10
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
-   select SYS_THUMB_BUILD
+   select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
imply CMD_MTDPARTS
imply CRC32_VERIFY
imply FAT_WRITE
+   select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
 
 config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 45e5379..03ab956 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -49,6 +49,12 @@ config TARGET_SOCFPGA_GEN5
bool
select ALTERA_SDRAM
 
+config TARGET_SOCFPGA_STRATIX10
+   bool
+   select ARMV8_MULTIENTRY
+   select ARMV8_SPIN_TABLE
+   select ARMV8_SET_SMPEN
+
 choice
prompt "Altera SOCFPGA board select"
optional
@@ -86,6 +92,10 @@ config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+   bool "Intel SOCFPGA SoCDK (Stratix 10)"
+   select TARGET_SOCFPGA_STRATIX10
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -116,12 +126,14 @@ config SYS_BOARD
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
+   default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+   default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
@@ -145,6 +157,7 @@ config SYS_CONFIG_NAME
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+   default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif
diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
new file mode 100644
index 000..e5a7a69
--- /dev/null
+++ b/configs/socfpga_stratix10_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_stratix10"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_MMC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DFU_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_CADENCE_QSPI=y
+CON

[U-Boot] [PATCH v2 13/14] board: altera: stratix10: Add socdk board support for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add socdk board support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 board/altera/stratix10-socdk/MAINTAINERS | 7 +++
 board/altera/stratix10-socdk/Makefile| 7 +++
 board/altera/stratix10-socdk/socfpga.c   | 7 +++
 3 files changed, 21 insertions(+)
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c

diff --git a/board/altera/stratix10-socdk/MAINTAINERS 
b/board/altera/stratix10-socdk/MAINTAINERS
new file mode 100644
index 000..6192bc9
--- /dev/null
+++ b/board/altera/stratix10-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M:     Chin-Liang See <chin.liang@intel.com>
+M: Dinh Nguyen <dinh.ngu...@intel.com>
+S: Maintained
+F: board/altera/stratix10-socdk/
+F: include/configs/socfpga_stratix10_socdk.h
+F: configs/socfpga_stratix10_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile 
b/board/altera/stratix10-socdk/Makefile
new file mode 100644
index 000..02a9cad
--- /dev/null
+++ b/board/altera/stratix10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016-2017 Intel Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c 
b/board/altera/stratix10-socdk/socfpga.c
new file mode 100644
index 000..3deb989
--- /dev/null
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
-- 
2.2.2

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[U-Boot] [PATCH v2 08/14] arm: dts: Add dts for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Device tree for Stratix10 SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/dts/Makefile|   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts | 180 +++
 2 files changed, 182 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7c062f0..f66b9c9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts 
b/arch/arm/dts/socfpga_stratix10_socdk.dts
new file mode 100644
index 000..26b407f
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
+   compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   aliases {
+   ethernet0 = 
+   spi0 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x8000>; /* 2GB */
+   };
+
+   regulator_3_3v: 3-3-v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x3>;
+   };
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   ranges;
+   u-boot,dm-pre-reloc;
+
+   rst: rstmgr@ffd11000 {
+   #reset-cells = <1>;
+   compatible = "altr,rst-mgr";
+   reg = <0xffd11000 0x100>;
+   altr,modrst-offset = <0x20>;
+   };
+
+   mdio {
+   phy0: ethernet-phy@0 {
+   txd0-skew-ps = <0>; /* -420ps */
+   txd1-skew-ps = <0>; /* -420ps */
+   txd2-skew-ps = <0>; /* -420ps */
+   txd3-skew-ps = <0>; /* -420ps */
+   rxd0-skew-ps = <420>; /* 0ps */
+   rxd1-skew-ps = <420>; /* 0ps */
+   rxd2-skew-ps = <420>; /* 0ps */
+   rxd3-skew-ps = <420>; /* 0ps */
+   txen-skew-ps = <0>; /* -420ps */
+   txc-skew-ps = <1860>; /* 960ps */
+   rxdv-skew-ps = <420>; /* 0ps */
+

[U-Boot] [PATCH v2 12/14] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add DDR support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 +
 drivers/ddr/altera/Makefile|   1 +
 drivers/ddr/altera/sdram_s10.c | 382 +
 3 files changed, 716 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 drivers/ddr/altera/sdram_s10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
new file mode 100644
index 000..d0fd958
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -0,0 +1,333 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SDRAM_S10_H_
+#define_SDRAM_S10_H_
+
+unsigned long sdram_calculate_size(void);
+int sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+#define DDR_TWR15
+#define DDR_READ_LATENCY_DELAY 40
+#define DDR_ACTIVATE_FAWBANK   0x1
+
+
+struct socfpga_ecc_hmc {
+   uint32_t ip_rev_id;
+   uint32_t _pad_0x4_0x7;
+   uint32_t ddrioctrl;
+   uint32_t ddrcalstat;
+   uint32_t mpr_0beat1;
+   uint32_t mpr_1beat1;
+   uint32_t mpr_2beat1;
+   uint32_t mpr_3beat1;
+   uint32_t mpr_4beat1;
+   uint32_t mpr_5beat1;
+   uint32_t mpr_6beat1;
+   uint32_t mpr_7beat1;
+   uint32_t mpr_8beat1;
+   uint32_t mpr_0beat2;
+   uint32_t mpr_1beat2;
+   uint32_t mpr_2beat2;
+   uint32_t mpr_3beat2;
+   uint32_t mpr_4beat2;
+   uint32_t mpr_5beat2;
+   uint32_t mpr_6beat2;
+   uint32_t mpr_7beat2;
+   uint32_t mpr_8beat2;
+   uint32_t _pad_0x58_0x5f[2];
+   uint32_t auto_precharge;
+   uint32_t _pad_0x64_0xdf[31];
+   uint32_t dramaddrwidth;
+   uint32_t _pad_0xe4_0xff[7];
+   uint32_t eccctrl;
+   uint32_t eccctrl2;
+   uint32_t _pad_0x108_0x10f[2];
+   uint32_t errinten;
+   uint32_t errintens;
+   uint32_t errintenr;
+   uint32_t intmode;
+   uint32_t intstat;
+   uint32_t diaginttest;
+   uint32_t modstat;
+   uint32_t derraddra;
+   uint32_t serraddra;
+   uint32_t _pad_0x134_0x137;
+   uint32_t autowb_corraddr;
+   uint32_t serrcntreg;
+   uint32_t autowb_drop_cntreg;
+   uint32_t ecc_reg2wreccdatabus;
+   uint32_t ecc_rdeccdata2regbus;
+   uint32_t ecc_reg2rdeccdatabus;
+   uint32_t ecc_diagon;
+   uint32_t ecc_decstat;
+   uint32_t _pad_0x158_0x15f[2];
+   uint32_t ecc_errgenaddr_0;
+   uint32_t ecc_errgenaddr_1;
+   uint32_t ecc_errgenaddr_2;
+   uint32_t ecc_errgenaddr_3;
+   uint32_t ecc_ref2rddatabus_beat0;
+   uint32_t ecc_ref2rddatabus_beat1;
+   uint32_t ecc_ref2rddatabus_beat2;
+   uint32_t ecc_ref2rddatabus_beat3;
+   uint32_t ecc_errgenhaddr_0;
+   uint32_t ecc_errgenhaddr_1;
+   uint32_t ecc_errgenhaddr_2;
+   uint32_t ecc_errgenhaddr_3;
+   uint32_t ecc_rdeccdata2regbus_beat0;
+   uint32_t ecc_rdeccdata2regbus_beat1;
+   uint32_t ecc_rdeccdata2regbus_beat2;
+   uint32_t ecc_rdeccdata2regbus_beat3;
+   uint32_t _pad_0x1a0_0x1af[4];
+   uint32_t derrhaddr;
+   uint32_t serrhaddr;
+   uint32_t _pad_0x1b8_0x1bb;
+   uint32_t autowb_corrhaddr;
+   uint32_t _pad_0x1c0_0x20f[20];
+   uint32_t hpsintfcsel;
+   uint32_t rsthandshakectrl;
+   uint32_t rsthandshakestat;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   uint32_t main_scheduler_id_coreid;
+   uint32_t main_scheduler_id_revisionid;
+   uint32_t main_scheduler_ddrconf;
+   uint32_t main_scheduler_ddrtiming;
+   uint32_t main_scheduler_ddrmode;
+   uint32_t main_scheduler_readlatency;
+   uint32_t _pad_0x18_0x37[8];
+   uint32_t main_scheduler_activate;
+   uint32_t main_scheduler_devtodev;
+   uint32_t main_scheduler_ddr4timing;
+};
+
+struct socfpga_io48_mmr {
+   uint32_t dbgcfg0;
+   uint32_t dbgcfg1;
+   uint32_t dbgcfg2;
+   uint32_t dbgcfg3;
+   uint32_t dbgcfg4;
+   uint32_t dbgcfg5;
+   uint32_t dbgcfg6;
+   uint32_t reserve0;
+   uint32_t reserve1;
+   uint32_t reserve2;
+   uint32_t ctrlcfg0;
+   uint32_t ctrlcfg1;
+   uint32_t ctrlcfg2;
+   uint32_t ctrlcfg3;
+   uint32_t ctrlcfg4;
+   uint32_t ctrlcfg5;
+   uint32_t ctrlcfg6;
+   uint32_t ctrlcfg7;
+   uint32_t ctrlcfg8;
+   uint32_t ctrlcfg9;
+   uint32_t dramtiming0;
+   uint32_t dramodt0;
+   uint32_t dramodt1;
+   uint32_t sbcfg0;
+   uint32_t sbcfg1;
+   uint32_t sbcfg2;
+   uint32_t sbcfg3;
+   uint32_t sbcfg4;
+   uint32_t sbcfg5;
+   uint32_t sbcfg6;
+   uint32_t sbcfg7;
+   uint32_

[U-Boot] [PATCH v2 04/14] arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add pinmux driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile |   2 +
 .../arm/mach-socfpga/include/mach/system_manager.h |   5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h | 169 +
 arch/arm/mach-socfpga/system_manager_s10.c |  91 +++
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c |  55 +++
 5 files changed, 321 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index f10b05c..910eb6f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -33,6 +33,8 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
 obj-y  += reset_manager_s10.o
+obj-y  += system_manager_s10.o
+obj-y  += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e6d4280..80c7d0b 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -7,6 +7,9 @@
 #ifndef _SYSTEM_MANAGER_H_
 #define _SYSTEM_MANAGER_H_
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include 
+#else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIOBIT(1)
 #define SYSMGR_ECC_OCRAM_ENBIT(0)
@@ -89,5 +92,5 @@
 
 #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
-
+#endif
 #endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
new file mode 100644
index 000..d992072
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SYSTEM_MANAGER_S10_
+#define_SYSTEM_MANAGER_S10_
+
+void sysmgr_pinmux_init(void);
+void populate_sysmgr_fpgaintf_module(void);
+void populate_sysmgr_pinmux(void);
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
+
+struct socfpga_system_manager {
+   /* System Manager Module */
+   u32 siliconid1; /* 0x00 */
+   u32 siliconid2;
+   u32 wddbg;
+   u32 _pad_0xc;
+   u32 mpu_status; /* 0x10 */
+   u32 mpu_ace;
+   u32 _pad_0x18_0x1c[2];
+   u32 dma;/* 0x20 */
+   u32 dma_periph;
+   /* SDMMC Controller Group */
+   u32 sdmmcgrp_ctrl;
+   u32 sdmmcgrp_l3master;
+   /* NAND Flash Controller Register Group */
+   u32 nandgrp_bootstrap;  /* 0x30 */
+   u32 nandgrp_l3master;
+   /* USB Controller Group */
+   u32 usb0_l3master;
+   u32 usb1_l3master;
+   /* EMAC Group */
+   u32 emac_gbl;   /* 0x40 */
+   u32 emac0;
+   u32 emac1;
+   u32 emac2;
+   u32 emac0_ace;  /* 0x50 */
+   u32 emac1_ace;
+   u32 emac2_ace;
+   u32 nand_axuser;
+   u32 _pad_0x60_0x64[2];  /* 0x60 */
+   /* FPGA interface Group */
+   u32 fpgaintf_en_1;
+   u32 fpgaintf_en_2;
+   u32 fpgaintf_en_3;  /* 0x70 */
+   u32 dma_l3master;
+   u32 etr_l3master;
+   u32 _pad_0x7c;
+   u32 sec_ctrl_slt;   /* 0x80 */
+   u32 osc_trim;
+   u32 _pad_0x88_0x8c[2];
+   /* ECC Group */
+   u32 ecc_intmask_value;  /* 0x90 */
+   u32 ecc_intmask_set;
+   u32 ecc_intmask_clr;
+   u32 ecc_intstatus_serr;
+   u32 ecc_intstatus_derr; /* 0xa0 */
+   u32 _pad_0xa4_0xac[3];
+   u32 noc_addr_remap; /* 0xb0 */
+   u32 hmc_clk;
+   u32 io_pa_ctrl;
+   u32 _pad_0xbc;
+   /* NOC Group */
+   u32 noc_timeout;/* 0xc0 */
+   u32 noc_idlereq_set;
+   u32 noc_idlereq_clr;
+   u32 noc_idlereq_value;
+   u32 noc_idleack;/* 0xd0 */
+   u32 noc_idlestatus;
+   u32 fpga

[U-Boot] [PATCH v2 03/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile |   1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../include/mach/reset_manager_arria10.h   |   8 +-
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 
 arch/arm/mach-socfpga/reset_manager.c  |  41 +++
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  67 +++-
 arch/arm/mach-socfpga/reset_manager_gen5.c |  33 --
 arch/arm/mach-socfpga/reset_manager_s10.c  | 118 +
 include/dt-bindings/reset/altr,rst-mgr-s10.h   |  97 +
 9 files changed, 395 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e5f9dd7..f10b05c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += reset_manager_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6591745..577fcce 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include 
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index b6d7f4f..e521839 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -28,10 +28,10 @@ struct socfpga_reset_manager {
u32 hdskreq;
u32 hdskack;
u32 counts;
-   u32 mpumodrst;
-   u32 per0modrst;
-   u32 per1modrst;
-   u32 brgmodrst;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;
+   u32 per2_mod_reset;
+   u32 brg_mod_reset;
u32 sysmodrst;
u32 coldmodrst;
u32 nrstmodrst;
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
new file mode 100644
index 000..07ada59
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_RESET_MANAGER_S10_
+#define_RESET_MANAGER_S10_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+   u32 status;
+   u32 mpu_rst_stat;
+   u32 misc_stat;
+   u32 padding1;
+   u32 hdsk_en;
+   u32 hdsk_req;
+   u32 hdsk_ack;
+   u32 hdsk_stall;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in S10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
+   u32 brg_mod_reset;
+   u32 padding2;
+   u32 cold_mod_reset;
+   u32 padding3;
+   u32 dbg_mod_reset;
+   u32 tap_mod_reset;
+   u32 padding4;
+   u32 padding5;
+   u32 brg_warm_mask;
+   u32 padding6[3];
+   u32 tst_stat;
+   u32 padding7;
+   u32 hdsk_timeout;
+   u32 mpul2flushtimeout;
+   u32 dbghdsktimeout;
+};
+
+#define RSTMGR_MPUMODRST_CORE0 0
+#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK   0X0040
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET 8
+#define RSTMGR_BANK_MASK   0x7
+#define RSTMGR_RESET_OFFSET0
+#define RSTMGR_RESET_MASK  0x1f
+#define RSTMGR_DEFINE(_bank, _offset)  \
+   ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset)   \
+   (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifi

[U-Boot] [PATCH v2 02/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add Clock Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
--
Changes in v2
- Declared defines for constant value used
- Fixed spacing and comments
---
 arch/arm/mach-socfpga/Makefile |   4 +
 arch/arm/mach-socfpga/clock_manager.c  |   4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c  | 355 +
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  | 210 
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c|  44 +++
 7 files changed, 646 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..e5f9dd7 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -30,6 +30,10 @@ obj-y+= pinmux_arria10.o
 obj-y  += reset_manager_arria10.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += clock_manager_s10.o
+obj-y  += wrap_pll_config_s10.o
+endif
 ifdef CONFIG_SPL_BUILD
 obj-y  += spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index cb6ae03..f9450a4 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)
do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
inter_val = readl(_manager_base->inter) & mask;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
inter_val = readl(_manager_base->stat) & mask;
 #endif
/* Wait for stable lock */
@@ -52,7 +52,7 @@ int set_cpu_clk_info(void)
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
gd->bd->bi_ddr_freq = 0;
 #endif
 
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c 
b/arch/arm/mach-socfpga/clock_manager_s10.c
new file mode 100644
index 000..cfb6708
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_clock_manager *clock_manager_base =
+   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void cm_write_bypass_mainpll(uint32_t val)
+{
+   writel(val, _manager_base->main_pll.bypass);
+   cm_wait_for_fsm();
+}
+
+static void cm_write_bypass_perpll(uint32_t val)
+{
+   writel(val, _manager_base->per_pll.bypass);
+   cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void cm_write_ctrl(uint32_t val)
+{
+   writel(val, _manager_base->ctrl);
+   cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+void cm_basic_init(const struct cm_config * const cfg)
+{
+   uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;
+
+   if (cfg == 0)
+   return;
+
+   /* Put all plls in bypass */
+   cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
+   cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
+
+   /* setup main PLL dividers where calculate the vcocalib value */
+   mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+   CLKMGR_FDBCK_MDIV_MASK;
+   refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+   mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+   hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+   CLKMGR_HSCNT_CONST;
+   vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+  CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+   writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+   ~CLKMGR_PLLGLOB_RST_MASK),
+   _manager_base->main_pll.pllglob);
+   writel(cfg->main_pll_fdbck, _manager_base->main_pll.fdbck);
+   writel(vcocalib, _manager_base->main_pll.vcocalib);
+   writel(cfg->main_pll_pllc0, _manager_base->main_pll.pllc0);
+   writel(cfg->main_pll_pllc1, _manager_base->main_pl

[U-Boot] [PATCH v2 05/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile|   1 +
 arch/arm/mach-socfpga/include/mach/misc.h |   1 +
 arch/arm/mach-socfpga/misc.c  |  76 
 arch/arm/mach-socfpga/misc_gen5.c |  75 ++-
 arch/arm/mach-socfpga/misc_s10.c  | 115 ++
 5 files changed, 197 insertions(+), 71 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 910eb6f..b253914 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += misc_s10.o
 obj-y  += reset_manager_s10.o
 obj-y  += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
index 0b65783..8466023 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -8,6 +8,7 @@
 #define _MISC_H_
 
 void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
+int socfpga_eth_reset(void);
 
 struct bsel {
const char  *mode;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 00eff90..cee3296 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -20,11 +20,14 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#endif
 
 struct bsel bsel_str[] = {
{ "rsvd", "Reserved", },
@@ -53,6 +56,7 @@ void enable_caches(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
/* Disable the L2 cache */
@@ -73,6 +77,7 @@ void v7_outer_cache_disable(void)
/* Disable the L2 cache */
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
+#endif
 
 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
@@ -136,3 +141,74 @@ int arch_cpu_init(void)
 
return 0;
 }
+
+#if !defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+   if (!phymode)
+   return -EINVAL;
+
+   if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+   return 0;
+   }
+
+   if (!strcmp(phymode, "rgmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+   return 0;
+   }
+
+   if (!strcmp(phymode, "rmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+   return 0;
+   }
+
+   return -EINVAL;
+}
+#endif
+
+#ifdef CONFIG_ETH_DESIGNWARE
+int socfpga_eth_reset(void)
+{
+   const void *fdt = gd->fdt_blob;
+   struct fdtdec_phandle_args args;
+   const char *phy_mode;
+   u32 phy_modereg;
+   int nodes[3];   /* Max. 3 GMACs */
+   int ret, count;
+   int i, node;
+
+   count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+  COMPAT_ALTERA_SOCFPGA_DWMAC,
+  nodes, ARRAY_SIZE(nodes));
+   for (i = 0; i < count; i++) {
+   node = nodes[i];
+   if (node <= 0)
+   continue;
+
+   ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+"#reset-cells", 1, 0,
+);
+   if (ret || (args.args_count != 1)) {
+   debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+   continue;
+   }
+
+   phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+   ret = dwmac_phymode_to_modereg(phy_mode, _modereg);
+   if (ret) {
+   debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+   continue;
+   }
+
+   dwmac_deassert_reset(args.args[0], phy_modereg);
+   }
+
+   return 0;
+}
+#else
+int socfpga_eth_reset(void)
+{
+   return 0;
+};
+#endif
diff --git a/arch/arm/mach-socfpga/misc_gen5.c 
b/arch/arm/mach-socfpga/misc_gen5.c
index 91ddb79..6149c8a 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -67,77 +67,6 @@ void dwmac_deassert_reset(const unsigned int of_reset_id,
/* Release the EMAC controller from reset */
s

[U-Boot] [PATCH v2 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add the base address map for Statix10 SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 56 ++
 1 file changed, 56 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100644
index 000..2fdc917
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS   0xf801
+#define SOCFPGA_SDR_ADDRESS0xf8011000
+#define SOCFPGA_SMMU_ADDRESS   0xfa00
+#define SOCFPGA_MAILBOX_ADDRESS0xffA3
+#define SOCFPGA_USB0_ADDRESS   0xffb0
+#define SOCFPGA_USB1_ADDRESS   0xffb4
+#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
+#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
+#define SOCFPGA_UART0_ADDRESS  0xffc02000
+#define SOCFPGA_UART1_ADDRESS  0xffc02100
+#define SOCFPGA_I2C0_ADDRESS   0xffc02800
+#define SOCFPGA_I2C1_ADDRESS   0xffc02900
+#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
+#define SOCFPGA_SYSTIMER1_ADDRESS  0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS  0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS  0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS  0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA  0xffd21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA0xffd21300
+#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
+#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS  0xffe0
+#define GICD_BASE  0xfffc1000
+#define GICC_BASE  0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
2.2.2

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[U-Boot] [PATCH v2 00/14] Enable Stratix10 SoC support

2017-10-05 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

This patch series are enabling support for Stratix 10 SoC

Changes for v2
- Removed defines for base addresses that can be extracted from DTS
- Added CPU node plus MDIO node for Ethernet at DTS
- Added defines for constant value for readability
- Consolidated common code for Clock Manager and misc code

Chin Liang See (14):
  arm: socfpga: stratix10: Add base address map for Statix10 SoC
  arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC
  arm: socfpga: stratix10: Add misc support for Stratix10 SoC
  arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC
  arm: socfpga: stratix10: Add MMU support for Stratix10 SoC
  arm: dts: Add dts for Stratix10 SoC
  arm: socfpga: Restructure the SPL file
  arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC
  arm: socfpga: stratix10: Add timer support for Stratix10 SoC
  ddr: altera: stratix10: Add DDR support for Stratix10 SoC
  board: altera: stratix10: Add socdk board support for Stratix10 SoC
  arm: socfpga: stratix10: Enable Stratix10 SoC build

 arch/arm/Kconfig   |   8 +-
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts   | 180 ++
 arch/arm/mach-socfpga/Kconfig  |  13 +
 arch/arm/mach-socfpga/Makefile |  19 +-
 arch/arm/mach-socfpga/clock_manager.c  |   4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c  | 355 +++
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |  56 +++
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  | 210 +++
 arch/arm/mach-socfpga/include/mach/firewall_s10.h  |  84 +
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h   | 108 ++
 arch/arm/mach-socfpga/include/mach/misc.h  |   1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../include/mach/reset_manager_arria10.h   |   8 +-
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 +++
 arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 ++
 .../arm/mach-socfpga/include/mach/system_manager.h |   5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h | 169 +
 arch/arm/mach-socfpga/mailbox_s10.c| 238 +
 arch/arm/mach-socfpga/misc.c   |  76 
 arch/arm/mach-socfpga/misc_gen5.c  |  75 +---
 arch/arm/mach-socfpga/misc_s10.c   | 115 +++
 arch/arm/mach-socfpga/mmu-arm64_s10.c  |  71 
 arch/arm/mach-socfpga/reset_manager.c  |  41 +++
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  67 +---
 arch/arm/mach-socfpga/reset_manager_gen5.c |  33 --
 arch/arm/mach-socfpga/reset_manager_s10.c  | 118 +++
 arch/arm/mach-socfpga/spl_a10.c| 105 ++
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c}|  46 ---
 arch/arm/mach-socfpga/spl_s10.c| 138 
 arch/arm/mach-socfpga/system_manager_s10.c |  91 +
 arch/arm/mach-socfpga/timer.c  |  17 +-
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c |  55 +++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c|  44 +++
 board/altera/stratix10-socdk/MAINTAINERS   |   7 +
 board/altera/stratix10-socdk/Makefile  |   7 +
 board/altera/stratix10-socdk/socfpga.c |   7 +
 configs/socfpga_stratix10_defconfig|  39 +++
 drivers/ddr/altera/Makefile|   1 +
 drivers/ddr/altera/sdram_s10.c | 382 +
 include/configs/socfpga_stratix10_socdk.h  | 216 
 include/dt-bindings/reset/altr,rst-mgr-s10.h   |  97 ++
 44 files changed, 3577 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c
 create mode 100644 arch

[U-Boot] [PATCH 11/14] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add timer support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/timer.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index 253cde3..23450b0 100644
--- a/arch/arm/mach-socfpga/timer.c
+++ b/arch/arm/mach-socfpga/timer.c
@@ -1,5 +1,6 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2016-2017 Intel Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -10,15 +11,29 @@
 
 #define TIMER_LOAD_VAL 0x
 
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+#endif
 
 /*
  * Timer initialization
  */
 int timer_init(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+   int enable = 0x3;   /* timer enable + output signal masked */
+   int loadval = ~0;
+
+   /* enable system counter */
+   writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
+   /* enable processor pysical counter */
+   asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
+   asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
+
+#else
writel(TIMER_LOAD_VAL, _base->load_val);
writel(TIMER_LOAD_VAL, _base->curr_val);
writel(readl(_base->ctrl) | 0x3, _base->ctrl);
+#endif
return 0;
 }
-- 
2.2.2

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[U-Boot] [PATCH 07/14] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add mailbox support for Stratix SoC

Signed-off-by: Ley Foon Tan <ley.foon@intel.com>
Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile   |   1 +
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 108 ++
 arch/arm/mach-socfpga/mailbox_s10.c  | 239 +++
 3 files changed, 348 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b253914..43e18d2 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += mailbox_s10.o
 obj-y  += misc_s10.o
 obj-y  += reset_manager_s10.o
 obj-y  += system_manager_s10.o
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h 
b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
new file mode 100644
index 000..b9bddf6
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+#ifndef _MAILBOX_S10_H_
+#define _MAILBOX_S10_H_
+
+/* user define Uboot ID */
+#define MBOX_CLIENT_ID_UBOOT   0xB
+#define MBOX_ID_UBOOT  0x1
+
+#define MBOX_MAX_CMD_INDEX 2047
+#define MBOX_CMD_BUFFER_SIZE   32
+#define MBOX_RESP_BUFFER_SIZE  16
+
+#define MBOX_HDR_CMD_LSB   0
+#define MBOX_HDR_CMD_MSK   (BIT(11) - 1)
+#define MBOX_HDR_I_LSB 11
+#define MBOX_HDR_I_MSK BIT(11)
+#define MBOX_HDR_LEN_LSB   12
+#define MBOX_HDR_LEN_MSK   0x007FF000
+#define MBOX_HDR_ID_LSB24
+#define MBOX_HDR_ID_MSK0x0F00
+#define MBOX_HDR_CLIENT_LSB28
+#define MBOX_HDR_CLIENT_MSK0xF000
+
+/* Interrupt flags */
+#define MBOX_FLAGS_INT_COE BIT(0)  /* COUT update interrupt enable */
+#define MBOX_FLAGS_INT_RIE BIT(1)  /* RIN update interrupt enable */
+#define MBOX_FLAGS_INT_UAE BIT(8)  /* Urgent ACK interrupt enable */
+#define MBOX_ALL_INTRS (MBOX_FLAGS_INT_COE | \
+MBOX_FLAGS_INT_RIE | \
+MBOX_FLAGS_INT_UAE)
+
+/* Status */
+#define MBOX_STATUS_UA_MSK BIT(8)
+
+#define MBOX_CMD_HEADER(client, id, len, cmd) \
+   (((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
+   (((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
+   (((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)| \
+   (((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)
+
+#define MBOX_RESP_ERR_GET(resp)\
+   (((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
+#define MBOX_RESP_LEN_GET(resp)\
+   (((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
+#define MBOX_RESP_ID_GET(resp) \
+   (((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
+#define MBOX_RESP_CLIENT_GET(resp) \
+   (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
+
+/* Response error list */
+typedef enum {
+   /* CMD completed succesfully, but check resp ARGS for any errors */
+   MBOX_RESP_STATOK = 0,
+   /* CMD is incorrectly formatted in some way */
+   MBOX_RESP_INVALID_COMMAND = 1,
+   /* BootROM Command code not undesrtood */
+   MBOX_RESP_UNKNOWN_BR = 2,
+   /* CMD code not recognized by firmware */
+   MBOX_RESP_UNKNOWN = 3,
+   /* Indicates that the device is not configured */
+   MBOX_RESP_NOT_CONFIGURED = 256,
+   /* Indicates that the device is busy */
+   MBOX_RESP_DEVICE_BUSY = 0x1FF,
+   /* Indicates that there is no valid response available */
+   MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
+   /* General Error */
+   MBOX_RESP_ERROR = 0x3FF,
+} ALT_SDM_MBOX_RESP_CODE;
+
+/* Mailbox command list */
+#define MBOX_RESTART   2
+#define MBOX_QSPI_OPEN 50
+#define MBOX_QSPI_CLOSE51
+#define MBOX_QSPI_DIRECT   59
+
+struct socfpga_mailbox {
+   u32 cin;/* command valid offset */
+   u32 rout;   /* response output offset */
+   u32 urg;/* urgent command */
+   u32 flags;  /* interrupt enables */
+   u32 pad_0x10_0x1f[4];   /* 0x10 - 0x1F reserved */
+   u32 cout;   /* command free offset */
+   u32 rin;/* respond valid offset */
+   u32 pad_0x28;   /* 0x28 reserved */
+   u32 status; /* mailbox status */
+   u32 pad_0x30_0x3f[4];   /* 0x30 - 0x3F reserved */
+   u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];  /* 0x40 - 0xBC circular command
+

[U-Boot] [PATCH 12/14] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add DDR support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 +
 drivers/ddr/altera/Makefile|   1 +
 drivers/ddr/altera/sdram_s10.c | 382 +
 3 files changed, 716 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 drivers/ddr/altera/sdram_s10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
new file mode 100644
index 000..d0fd958
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -0,0 +1,333 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SDRAM_S10_H_
+#define_SDRAM_S10_H_
+
+unsigned long sdram_calculate_size(void);
+int sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+#define DDR_TWR15
+#define DDR_READ_LATENCY_DELAY 40
+#define DDR_ACTIVATE_FAWBANK   0x1
+
+
+struct socfpga_ecc_hmc {
+   uint32_t ip_rev_id;
+   uint32_t _pad_0x4_0x7;
+   uint32_t ddrioctrl;
+   uint32_t ddrcalstat;
+   uint32_t mpr_0beat1;
+   uint32_t mpr_1beat1;
+   uint32_t mpr_2beat1;
+   uint32_t mpr_3beat1;
+   uint32_t mpr_4beat1;
+   uint32_t mpr_5beat1;
+   uint32_t mpr_6beat1;
+   uint32_t mpr_7beat1;
+   uint32_t mpr_8beat1;
+   uint32_t mpr_0beat2;
+   uint32_t mpr_1beat2;
+   uint32_t mpr_2beat2;
+   uint32_t mpr_3beat2;
+   uint32_t mpr_4beat2;
+   uint32_t mpr_5beat2;
+   uint32_t mpr_6beat2;
+   uint32_t mpr_7beat2;
+   uint32_t mpr_8beat2;
+   uint32_t _pad_0x58_0x5f[2];
+   uint32_t auto_precharge;
+   uint32_t _pad_0x64_0xdf[31];
+   uint32_t dramaddrwidth;
+   uint32_t _pad_0xe4_0xff[7];
+   uint32_t eccctrl;
+   uint32_t eccctrl2;
+   uint32_t _pad_0x108_0x10f[2];
+   uint32_t errinten;
+   uint32_t errintens;
+   uint32_t errintenr;
+   uint32_t intmode;
+   uint32_t intstat;
+   uint32_t diaginttest;
+   uint32_t modstat;
+   uint32_t derraddra;
+   uint32_t serraddra;
+   uint32_t _pad_0x134_0x137;
+   uint32_t autowb_corraddr;
+   uint32_t serrcntreg;
+   uint32_t autowb_drop_cntreg;
+   uint32_t ecc_reg2wreccdatabus;
+   uint32_t ecc_rdeccdata2regbus;
+   uint32_t ecc_reg2rdeccdatabus;
+   uint32_t ecc_diagon;
+   uint32_t ecc_decstat;
+   uint32_t _pad_0x158_0x15f[2];
+   uint32_t ecc_errgenaddr_0;
+   uint32_t ecc_errgenaddr_1;
+   uint32_t ecc_errgenaddr_2;
+   uint32_t ecc_errgenaddr_3;
+   uint32_t ecc_ref2rddatabus_beat0;
+   uint32_t ecc_ref2rddatabus_beat1;
+   uint32_t ecc_ref2rddatabus_beat2;
+   uint32_t ecc_ref2rddatabus_beat3;
+   uint32_t ecc_errgenhaddr_0;
+   uint32_t ecc_errgenhaddr_1;
+   uint32_t ecc_errgenhaddr_2;
+   uint32_t ecc_errgenhaddr_3;
+   uint32_t ecc_rdeccdata2regbus_beat0;
+   uint32_t ecc_rdeccdata2regbus_beat1;
+   uint32_t ecc_rdeccdata2regbus_beat2;
+   uint32_t ecc_rdeccdata2regbus_beat3;
+   uint32_t _pad_0x1a0_0x1af[4];
+   uint32_t derrhaddr;
+   uint32_t serrhaddr;
+   uint32_t _pad_0x1b8_0x1bb;
+   uint32_t autowb_corrhaddr;
+   uint32_t _pad_0x1c0_0x20f[20];
+   uint32_t hpsintfcsel;
+   uint32_t rsthandshakectrl;
+   uint32_t rsthandshakestat;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   uint32_t main_scheduler_id_coreid;
+   uint32_t main_scheduler_id_revisionid;
+   uint32_t main_scheduler_ddrconf;
+   uint32_t main_scheduler_ddrtiming;
+   uint32_t main_scheduler_ddrmode;
+   uint32_t main_scheduler_readlatency;
+   uint32_t _pad_0x18_0x37[8];
+   uint32_t main_scheduler_activate;
+   uint32_t main_scheduler_devtodev;
+   uint32_t main_scheduler_ddr4timing;
+};
+
+struct socfpga_io48_mmr {
+   uint32_t dbgcfg0;
+   uint32_t dbgcfg1;
+   uint32_t dbgcfg2;
+   uint32_t dbgcfg3;
+   uint32_t dbgcfg4;
+   uint32_t dbgcfg5;
+   uint32_t dbgcfg6;
+   uint32_t reserve0;
+   uint32_t reserve1;
+   uint32_t reserve2;
+   uint32_t ctrlcfg0;
+   uint32_t ctrlcfg1;
+   uint32_t ctrlcfg2;
+   uint32_t ctrlcfg3;
+   uint32_t ctrlcfg4;
+   uint32_t ctrlcfg5;
+   uint32_t ctrlcfg6;
+   uint32_t ctrlcfg7;
+   uint32_t ctrlcfg8;
+   uint32_t ctrlcfg9;
+   uint32_t dramtiming0;
+   uint32_t dramodt0;
+   uint32_t dramodt1;
+   uint32_t sbcfg0;
+   uint32_t sbcfg1;
+   uint32_t sbcfg2;
+   uint32_t sbcfg3;
+   uint32_t sbcfg4;
+   uint32_t sbcfg5;
+   uint32_t sbcfg6;
+   uint32_t sbcfg7;
+   uint32_

[U-Boot] [PATCH 09/14] arm: socfpga: Restructure the SPL file

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Restructure the SPL so each devices such as CV, A10 and S10
will have their own dedicated SPL file. SPL file determine
the HW initialization flow which is device specific

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile  |   5 +-
 arch/arm/mach-socfpga/spl_a10.c | 105 
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c} |  46 
 3 files changed, 109 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/spl_a10.c
 rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (83%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 098e5e9..b669d43 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -41,13 +41,16 @@ obj-y   += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
-obj-y  += spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y  += spl_gen5.o
 obj-y  += freeze_controller.o
 obj-y  += wrap_iocsr_config.o
 obj-y  += wrap_pinmux_config.o
 obj-y  += wrap_sdram_config.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y  += spl_a10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
new file mode 100644
index 000..e6fc766
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -0,0 +1,105 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_system_manager *sysmgr_regs =
+   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+u32 spl_boot_device(void)
+{
+   const u32 bsel = readl(_regs->bootinfo);
+
+   switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+   case 0x1:   /* FPGA (HPS2FPGA Bridge) */
+   return BOOT_DEVICE_RAM;
+   case 0x2:   /* NAND Flash (1.8V) */
+   case 0x3:   /* NAND Flash (3.0V) */
+   socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+   return BOOT_DEVICE_NAND;
+   case 0x4:   /* SD/MMC External Transceiver (1.8V) */
+   case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+   socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+   socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+   return BOOT_DEVICE_MMC1;
+   case 0x6:   /* QSPI Flash (1.8V) */
+   case 0x7:   /* QSPI Flash (3.0V) */
+   socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+   return BOOT_DEVICE_SPI;
+   default:
+   printf("Invalid boot device (bsel=%08x)!\n", bsel);
+   hang();
+   }
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+   return MMCSD_MODE_FS;
+#else
+   return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void spl_board_init(void)
+{
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   socfpga_reset_uart(0);
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   socfpga_watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   socfpga_reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+}
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl_gen5.c
similarity index 83%
rename from arch/arm/mach-socfpga/spl.c
rename to arch/arm/mach-socfpga/spl_gen5.c
index 71bae82..9864082 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -22,21 +22,15 @@
 #include 
 #include 
 #include 
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#include 
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#endif
-
 static const struct socfpga_system_m

[U-Boot] [PATCH 05/14] arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add pinmux driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile |   2 +
 .../arm/mach-socfpga/include/mach/system_manager.h |   5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h | 169 +
 arch/arm/mach-socfpga/system_manager_s10.c |  91 +++
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c |  55 +++
 5 files changed, 321 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index f10b05c..910eb6f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -33,6 +33,8 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
 obj-y  += reset_manager_s10.o
+obj-y  += system_manager_s10.o
+obj-y  += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e6d4280..80c7d0b 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -7,6 +7,9 @@
 #ifndef _SYSTEM_MANAGER_H_
 #define _SYSTEM_MANAGER_H_
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include 
+#else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIOBIT(1)
 #define SYSMGR_ECC_OCRAM_ENBIT(0)
@@ -89,5 +92,5 @@
 
 #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
-
+#endif
 #endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
new file mode 100644
index 000..d992072
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SYSTEM_MANAGER_S10_
+#define_SYSTEM_MANAGER_S10_
+
+void sysmgr_pinmux_init(void);
+void populate_sysmgr_fpgaintf_module(void);
+void populate_sysmgr_pinmux(void);
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
+
+struct socfpga_system_manager {
+   /* System Manager Module */
+   u32 siliconid1; /* 0x00 */
+   u32 siliconid2;
+   u32 wddbg;
+   u32 _pad_0xc;
+   u32 mpu_status; /* 0x10 */
+   u32 mpu_ace;
+   u32 _pad_0x18_0x1c[2];
+   u32 dma;/* 0x20 */
+   u32 dma_periph;
+   /* SDMMC Controller Group */
+   u32 sdmmcgrp_ctrl;
+   u32 sdmmcgrp_l3master;
+   /* NAND Flash Controller Register Group */
+   u32 nandgrp_bootstrap;  /* 0x30 */
+   u32 nandgrp_l3master;
+   /* USB Controller Group */
+   u32 usb0_l3master;
+   u32 usb1_l3master;
+   /* EMAC Group */
+   u32 emac_gbl;   /* 0x40 */
+   u32 emac0;
+   u32 emac1;
+   u32 emac2;
+   u32 emac0_ace;  /* 0x50 */
+   u32 emac1_ace;
+   u32 emac2_ace;
+   u32 nand_axuser;
+   u32 _pad_0x60_0x64[2];  /* 0x60 */
+   /* FPGA interface Group */
+   u32 fpgaintf_en_1;
+   u32 fpgaintf_en_2;
+   u32 fpgaintf_en_3;  /* 0x70 */
+   u32 dma_l3master;
+   u32 etr_l3master;
+   u32 _pad_0x7c;
+   u32 sec_ctrl_slt;   /* 0x80 */
+   u32 osc_trim;
+   u32 _pad_0x88_0x8c[2];
+   /* ECC Group */
+   u32 ecc_intmask_value;  /* 0x90 */
+   u32 ecc_intmask_set;
+   u32 ecc_intmask_clr;
+   u32 ecc_intstatus_serr;
+   u32 ecc_intstatus_derr; /* 0xa0 */
+   u32 _pad_0xa4_0xac[3];
+   u32 noc_addr_remap; /* 0xb0 */
+   u32 hmc_clk;
+   u32 io_pa_ctrl;
+   u32 _pad_0xbc;
+   /* NOC Group */
+   u32 noc_timeout;/* 0xc0 */
+   u32 noc_idlereq_set;
+   u32 noc_idlereq_clr;
+   u32 noc_idlereq_value;
+   u32 noc_idleack;/* 0xd0 */
+   u32 noc_idlestatus;
+   u32 fpga

[U-Boot] [PATCH 08/14] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add MMU support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile|  1 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++
 2 files changed, 72 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 43e18d2..098e5e9 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
 obj-y  += mailbox_s10.o
 obj-y  += misc_s10.o
+obj-y  += mmu-arm64_s10.o
 obj-y  += reset_manager_s10.o
 obj-y  += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c 
b/arch/arm/mach-socfpga/mmu-arm64_s10.c
new file mode 100644
index 000..91c7f2e
--- /dev/null
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+   {
+   /* MEM 2GB*/
+   .virt   = 0x0UL,
+   .phys   = 0x0UL,
+   .size   = 0x8000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* FPGA 1.5GB */
+   .virt   = 0x8000UL,
+   .phys   = 0x8000UL,
+   .size   = 0x6000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* DEVICE 142MB */
+   .virt   = 0xF700UL,
+   .phys   = 0xF700UL,
+   .size   = 0x08E0UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* OCRAM 1MB but available 256KB */
+   .virt   = 0xFFE0UL,
+   .phys   = 0xFFE0UL,
+   .size   = 0x0010UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* DEVICE 32KB */
+   .virt   = 0xFFFCUL,
+   .phys   = 0xFFFCUL,
+   .size   = 0x8000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* MEM 124GB */
+   .virt   = 0x01UL,
+   .phys   = 0x01UL,
+   .size   = 0x1FUL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* DEVICE 4GB */
+   .virt   = 0x20UL,
+   .phys   = 0x20UL,
+   .size   = 0x01UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* List terminator */
+   },
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;
-- 
2.2.2

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[U-Boot] [PATCH 13/14] board: altera: stratix10: Add socdk board support for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add socdk board support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 board/altera/stratix10-socdk/MAINTAINERS | 7 +++
 board/altera/stratix10-socdk/Makefile| 7 +++
 board/altera/stratix10-socdk/socfpga.c   | 7 +++
 3 files changed, 21 insertions(+)
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c

diff --git a/board/altera/stratix10-socdk/MAINTAINERS 
b/board/altera/stratix10-socdk/MAINTAINERS
new file mode 100644
index 000..6192bc9
--- /dev/null
+++ b/board/altera/stratix10-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M:     Chin-Liang See <chin.liang@intel.com>
+M: Dinh Nguyen <dinh.ngu...@intel.com>
+S: Maintained
+F: board/altera/stratix10-socdk/
+F: include/configs/socfpga_stratix10_socdk.h
+F: configs/socfpga_stratix10_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile 
b/board/altera/stratix10-socdk/Makefile
new file mode 100644
index 000..02a9cad
--- /dev/null
+++ b/board/altera/stratix10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016-2017 Intel Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c 
b/board/altera/stratix10-socdk/socfpga.c
new file mode 100644
index 000..3deb989
--- /dev/null
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
-- 
2.2.2

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[U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add Clock Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile |   4 +
 arch/arm/mach-socfpga/clock_manager.c  |   4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c  | 359 +
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  | 202 
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c|  46 +++
 7 files changed, 644 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..e5f9dd7 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -30,6 +30,10 @@ obj-y+= pinmux_arria10.o
 obj-y  += reset_manager_arria10.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += clock_manager_s10.o
+obj-y  += wrap_pll_config_s10.o
+endif
 ifdef CONFIG_SPL_BUILD
 obj-y  += spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index cb6ae03..f9450a4 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)
do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
inter_val = readl(_manager_base->inter) & mask;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
inter_val = readl(_manager_base->stat) & mask;
 #endif
/* Wait for stable lock */
@@ -52,7 +52,7 @@ int set_cpu_clk_info(void)
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
gd->bd->bi_ddr_freq = 0;
 #endif
 
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c 
b/arch/arm/mach-socfpga/clock_manager_s10.c
new file mode 100644
index 000..a9f9b07
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -0,0 +1,359 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_clock_manager *clock_manager_base =
+   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void cm_write_bypass_mainpll(uint32_t val)
+{
+   writel(val, _manager_base->main_pll.bypass);
+   cm_wait_for_fsm();
+}
+static void cm_write_bypass_perpll(uint32_t val)
+{
+   writel(val, _manager_base->per_pll.bypass);
+   cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void cm_write_ctrl(uint32_t val)
+{
+   writel(val, _manager_base->ctrl);
+   cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ */
+void cm_basic_init(const struct cm_config * const cfg)
+{
+   uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;
+
+   if (cfg == 0)
+   return;
+
+   /* Put all plls in bypass */
+   cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
+   cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
+
+   /* setup main PLL dividers */
+   /* calculate the vcocalib value */
+   mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+   CLKMGR_FDBCK_MDIV_MASK;
+   refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+   mscnt = 200 / (6 + mdiv) / refclkdiv;
+   hscnt = (mdiv + 6) * mscnt / refclkdiv - 9;
+   vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+  CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+   writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+   ~CLKMGR_PLLGLOB_RST_MASK),
+   _manager_base->main_pll.pllglob);
+   writel(cfg->main_pll_fdbck, _manager_base->main_pll.fdbck);
+   writel(vcocalib, _manager_base->main_pll.vcocalib);
+   writel(cfg->main_pll_pllc0, _manager_base->main_pll.pllc0);
+   writel(cfg->main_pll_pllc1, _manager_base->main_pll.pllc1);
+   writel(cfg->main_pll_nocdiv, _manager_base->main_pll.nocdiv);
+
+   /* setup peripheral PLL dividers */
+   /* calculat

[U-Boot] [PATCH 10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add SPL driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile |   4 +
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   4 +
 arch/arm/mach-socfpga/include/mach/firewall_s10.h  |  84 +
 arch/arm/mach-socfpga/spl_s10.c| 138 +
 4 files changed, 230 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b669d43..35b124a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -40,6 +40,7 @@ obj-y += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y  += spl_gen5.o
@@ -51,6 +52,9 @@ endif
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y  += spl_a10.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += spl_s10.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
index feb1881..d79b9cd 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -45,6 +45,10 @@
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA  0xffd21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA0xffd21300
 #define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
 #define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
 #define SOCFPGA_SPIS0_ADDRESS  0xffda2000
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h 
b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
new file mode 100644
index 000..6894bb9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_FIREWALL_S10_
+#define_FIREWALL_S10_
+
+struct socfpga_firwall_l4_per {
+   u32 nand;   /* 0x00 */
+   u32 nand_data;
+   u32 _pad_0x8;
+   u32 usb0;
+   u32 usb1;   /* 0x10 */
+   u32 _pad_0x14;
+   u32 _pad_0x18;
+   u32 spim0;
+   u32 spim1;  /* 0x20 */
+   u32 spis0;
+   u32 spis1;
+   u32 emac0;
+   u32 emac1;  /* 0x30 */
+   u32 emac2;
+   u32 _pad_0x38;
+   u32 _pad_0x3c;
+   u32 sdmmc;  /* 0x40 */
+   u32 gpio0;
+   u32 gpio1;
+   u32 _pad_0x4c;
+   u32 i2c0;   /* 0x50 */
+   u32 i2c1;
+   u32 i2c2;
+   u32 i2c3;
+   u32 i2c4;   /* 0x60 */
+   u32 timer0;
+   u32 timer1;
+   u32 uart0;
+   u32 uart1;  /* 0x70 */
+};
+
+struct socfpga_firwall_l4_sys {
+   u32 _pad_0x00;  /* 0x00 */
+   u32 _pad_0x04;
+   u32 dma_ecc;
+   u32 emac0rx_ecc;
+   u32 emac0tx_ecc;/* 0x10 */
+   u32 emac1rx_ecc;
+   u32 emac1tx_ecc;
+   u32 emac2rx_ecc;
+   u32 emac2tx_ecc;/* 0x20 */
+   u32 _pad_0x24;
+   u32 _pad_0x28;
+   u32 nand_ecc;
+   u32 nand_read_ecc;  /* 0x30 */
+   u32 nand_write_ecc;
+   u32 ocram_ecc;
+   u32 _pad_0x3c;
+   u32 sdmmc_ecc;  /* 0x40 */
+   u32 usb0_ecc;
+   u32 usb1_ecc;
+   u32 clock_manager;
+   u32 _pad_0x50;  /* 0x50 */
+   u32 io_manager;
+   u32 reset_manager;
+   u32 system_manager;
+   u32 osc0_timer; /* 0x60 */
+   u32 osc1_timer;
+   u32 watchdog0;
+   u32 watchdog1;
+   u32 watchdog2;  /* 0x70 */
+   u32 watchdog3;
+};
+
+#define FIREWALL_L4_DISABLE_ALL(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_BRIDGE_DISABLE_ALL(~0)
+
+#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR 0xf7004688
+#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR  0xf7018628
+
+#define CCU_ADMASK_P_MASK  (BIT(0))
+#define CCU_ADMASK_NS_MASK (BIT(1))
+
+#endif /* _FIREWALL_S10_ */
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
new file mode 100644
index 000..12cafe6
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@

[U-Boot] [PATCH 14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add build support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/Kconfig  |   8 +-
 arch/arm/mach-socfpga/Kconfig |  13 ++
 configs/socfpga_stratix10_defconfig   |  39 ++
 include/configs/socfpga_stratix10_socdk.h | 216 ++
 4 files changed, 273 insertions(+), 3 deletions(-)
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bb64b9c..13dd144 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -655,21 +655,23 @@ config ARCH_SNAPDRAGON
 
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
-   select CPU_V7
+   select CPU_V7 if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+   select ARM64 if TARGET_SOCFPGA_STRATIX10
select SUPPORT_SPL
select OF_CONTROL
select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
-   select ENABLE_ARM_SOC_BOOT0_HOOK
+   select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || 
TARGET_SOCFPGA_ARRIA10
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
-   select SYS_THUMB_BUILD
+   select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
imply CMD_MTDPARTS
imply CRC32_VERIFY
imply FAT_WRITE
+   select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
 
 config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 45e5379..03ab956 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -49,6 +49,12 @@ config TARGET_SOCFPGA_GEN5
bool
select ALTERA_SDRAM
 
+config TARGET_SOCFPGA_STRATIX10
+   bool
+   select ARMV8_MULTIENTRY
+   select ARMV8_SPIN_TABLE
+   select ARMV8_SET_SMPEN
+
 choice
prompt "Altera SOCFPGA board select"
optional
@@ -86,6 +92,10 @@ config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+   bool "Intel SOCFPGA SoCDK (Stratix 10)"
+   select TARGET_SOCFPGA_STRATIX10
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -116,12 +126,14 @@ config SYS_BOARD
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
+   default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+   default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
@@ -145,6 +157,7 @@ config SYS_CONFIG_NAME
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+   default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif
diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
new file mode 100644
index 000..e5a7a69
--- /dev/null
+++ b/configs/socfpga_stratix10_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_stratix10"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_MMC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DFU_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_CADENCE_QSPI=y
+CON

[U-Boot] [PATCH 06/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add misc support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile   |   1 +
 arch/arm/mach-socfpga/misc.c |   4 +
 arch/arm/mach-socfpga/misc_s10.c | 165 +++
 3 files changed, 170 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 910eb6f..b253914 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += misc_s10.o
 obj-y  += reset_manager_s10.o
 obj-y  += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 00eff90..2ea94bc 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -23,8 +23,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#endif
 
 struct bsel bsel_str[] = {
{ "rsvd", "Reserved", },
@@ -53,6 +55,7 @@ void enable_caches(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
/* Disable the L2 cache */
@@ -73,6 +76,7 @@ void v7_outer_cache_disable(void)
/* Disable the L2 cache */
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
+#endif
 
 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
new file mode 100644
index 000..b84f055
--- /dev/null
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE
+void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode)
+{
+   /* Put the emac we're using into reset.
+* This is required before configuring the PHY interface
+*/
+   socfpga_emac_manage_reset(of_reset_id, 1);
+
+   clrsetbits_le32(_regs->emac0 + (of_reset_id - EMAC0_RESET),
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+
+   socfpga_emac_manage_reset(of_reset_id, 0);
+}
+
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+   if (!phymode)
+   return -EINVAL;
+
+   if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+   return 0;
+   }
+
+   if (!strcmp(phymode, "rgmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+   return 0;
+   }
+
+   if (!strcmp(phymode, "rmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+   return 0;
+   }
+
+   return -EINVAL;
+}
+
+static int socfpga_eth_reset(void)
+{
+   const void *fdt = gd->fdt_blob;
+   struct fdtdec_phandle_args args;
+   const char *phy_mode;
+   u32 phy_modereg;
+   int nodes[2];   /* Max. 3 GMACs */
+   int ret, count;
+   int i, node;
+
+   count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+  COMPAT_ALTERA_SOCFPGA_DWMAC,
+  nodes, ARRAY_SIZE(nodes));
+   for (i = 0; i < count; i++) {
+   node = nodes[i];
+   if (node <= 0)
+   continue;
+
+   ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+"#reset-cells", 1, 0,
+);
+   if (ret || (args.args_count != 1)) {
+   debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+   continue;
+   }
+
+   phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+   ret = dwmac_phymode_to_modereg(phy_mode, _modereg);
+   if (ret) {
+   debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+   continue;
+   }
+
+   dwmac_deassert_reset(args.args[0], phy_modereg);
+   }
+
+   return 0;
+}
+#else
+static int socfpga_eth_rese

[U-Boot] [PATCH 04/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/Makefile |   1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 +
 arch/arm/mach-socfpga/reset_manager.c  |   5 +
 arch/arm/mach-socfpga/reset_manager_s10.c  | 140 +
 include/dt-bindings/reset/altr,rst-mgr-s10.h   |  97 ++
 6 files changed, 361 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e5f9dd7..f10b05c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += reset_manager_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6591745..577fcce 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include 
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
new file mode 100644
index 000..07ada59
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_RESET_MANAGER_S10_
+#define_RESET_MANAGER_S10_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+   u32 status;
+   u32 mpu_rst_stat;
+   u32 misc_stat;
+   u32 padding1;
+   u32 hdsk_en;
+   u32 hdsk_req;
+   u32 hdsk_ack;
+   u32 hdsk_stall;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in S10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
+   u32 brg_mod_reset;
+   u32 padding2;
+   u32 cold_mod_reset;
+   u32 padding3;
+   u32 dbg_mod_reset;
+   u32 tap_mod_reset;
+   u32 padding4;
+   u32 padding5;
+   u32 brg_warm_mask;
+   u32 padding6[3];
+   u32 tst_stat;
+   u32 padding7;
+   u32 hdsk_timeout;
+   u32 mpul2flushtimeout;
+   u32 dbghdsktimeout;
+};
+
+#define RSTMGR_MPUMODRST_CORE0 0
+#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK   0X0040
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET 8
+#define RSTMGR_BANK_MASK   0x7
+#define RSTMGR_RESET_OFFSET0
+#define RSTMGR_RESET_MASK  0x1f
+#define RSTMGR_DEFINE(_bank, _offset)  \
+   ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset)   \
+   (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset)\
+   (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_USB0RSTMGR_DEFINE(1, 3)
+#define RSTMGR_USB1RSTMGR_DEFINE(1, 4)
+#define RSTMGR_NANDRSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_EMAC0_OCP   RSTMGR_DEFINE(1, 8)
+#define RSTMGR_EMAC1_OCP   RSTMGR_DEFINE(1, 9)
+#define RSTMGR_EMAC2_OCP   RSTMGR_DEFINE(1, 10)
+#define RSTMGR_USB0_OCPRSTMGR_DEFINE(1, 11)
+#define RSTMGR_USB1_OCPRSTMGR_DEFINE(1, 12)
+#define RSTMGR_NAND_OCPRS

[U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Device tree for Stratix10 SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/dts/Makefile|   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts | 141 +++
 2 files changed, 143 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fee4680..4cf5fd0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts 
b/arch/arm/dts/socfpga_stratix10_socdk.dts
new file mode 100644
index 000..484c630
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
+   compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   aliases {
+   ethernet0 = 
+   spi0 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x8000>; /* 2GB */
+   };
+
+   regulator_3_3v: 3-3-v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   ranges;
+   u-boot,dm-pre-reloc;
+
+   rst: rstmgr@ffd11000 {
+   #reset-cells = <1>;
+   compatible = "altr,rst-mgr";
+   reg = <0xffd11000 0x100>;
+   altr,modrst-offset = <0x20>;
+   };
+
+   gmac0: ethernet@ff80 {
+   compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", 
"snps,dwmac";
+   reg = <0xff80 0x2000>;
+   interrupts = <0 90 4>;
+   interrupt-names = "macirq";
+   mac-address = [00 00 00 00 00 00];
+   resets = < EMAC0_RESET>;
+   reset-names = "stmmaceth";
+   phy-mode = "rgmii";
+   phy-addr = <0x>; /* probe for phy addr */
+   max-speed = <1000>;
+   txd0-skew-ps = <0>; /* -420ps */
+   txd1-skew-ps = <0>; /* -420ps */
+   txd2-skew-ps = <0>; /* -420ps */
+   txd3-skew-ps = <0>; /* -420ps */
+   rxd0-skew-ps = <420>; /* 0ps */
+   rxd1-skew-ps = <420>; /* 0ps */
+   rxd2-skew-ps = <420>; /* 0ps */
+   rxd3-skew-ps = <420>; /* 0ps */
+   txen-skew-ps = <0>; /* -420ps */
+   txc-skew-ps = <1860>; /* 960ps */
+   rxdv-skew-ps = <420>; /* 0ps */
+   rxc-skew-ps = <1680>; /* 780ps */
+   status = "okay";
+   };
+
+   mmc0: dwmmc0@0xff808000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "altr,socfpga-dw-mshc";
+   reg = <0xff808000 0x1000>;
+   interrupts = <0 96 4>;
+   num-slots = <1>;
+   broken-cd;
+   bus-width = <4>;
+   fifo-depth = <0x400>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+

[U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

Add the base address map for Statix10 SoC

Signed-off-by: Chin Liang See <chin.liang@intel.com>
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58 ++
 1 file changed, 58 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100644
index 000..feb1881
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS   0xf801
+#define SOCFPGA_SDR_ADDRESS0xf8011000
+#define SOCFPGA_SMMU_ADDRESS   0xfa00
+#define SOCFPGA_EMAC0_ADDRESS  0xff80
+#define SOCFPGA_EMAC1_ADDRESS  0xff802000
+#define SOCFPGA_EMAC2_ADDRESS  0xff804000
+#define SOCFPGA_SDMMC_ADDRESS  0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS   0xff8d2000
+#define SOCFPGA_QSPIDATA_ADDRESS   0xff90
+#define SOCFPGA_MAILBOX_ADDRESS0xffA3
+#define SOCFPGA_USB0_ADDRESS   0xffb0
+#define SOCFPGA_USB1_ADDRESS   0xffb4
+#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
+#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
+#define SOCFPGA_UART0_ADDRESS  0xffc02000
+#define SOCFPGA_UART1_ADDRESS  0xffc02100
+#define SOCFPGA_I2C0_ADDRESS   0xffc02800
+#define SOCFPGA_I2C1_ADDRESS   0xffc02900
+#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
+#define SOCFPGA_SYSTIMER1_ADDRESS  0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS  0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS  0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS  0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
+#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS  0xffe0
+#define GICD_BASE  0xfffc1000
+#define GICC_BASE  0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
2.2.2

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[U-Boot] [PATCH 00/14] Enable Stratix10 SoC support

2017-09-19 Thread chin . liang . see

From: Chin Liang See <chin.liang@intel.com>

This patch series are enabling support for Stratix 10 SoC

Chin Liang See (14):
  arm: socfpga: stratix10: Add base address map for Statix10 SoC
  arm: dts: Add dts for Stratix10 SoC
  arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC
  arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC
  arm: socfpga: stratix10: Add misc support for Stratix10 SoC
  arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC
  arm: socfpga: stratix10: Add MMU support for Stratix10 SoC
  arm: socfpga: Restructure the SPL file
  arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC
  arm: socfpga: stratix10: Add timer support for Stratix10 SoC
  ddr: altera: stratix10: Add DDR support for Stratix10 SoC
  board: altera: stratix10: Add socdk board support for Stratix10 SoC
  arm: socfpga: stratix10: Enable Stratix10 SoC build

 arch/arm/Kconfig   |   8 +-
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts   | 141 
 arch/arm/mach-socfpga/Kconfig  |  13 +
 arch/arm/mach-socfpga/Makefile |  19 +-
 arch/arm/mach-socfpga/clock_manager.c  |   4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c  | 359 +++
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |  62 
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  | 202 +++
 arch/arm/mach-socfpga/include/mach/firewall_s10.h  |  84 +
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h   | 108 ++
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 +++
 arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 ++
 .../arm/mach-socfpga/include/mach/system_manager.h |   5 +-
 .../mach-socfpga/include/mach/system_manager_s10.h | 169 +
 arch/arm/mach-socfpga/mailbox_s10.c| 239 +
 arch/arm/mach-socfpga/misc.c   |   4 +
 arch/arm/mach-socfpga/misc_s10.c   | 165 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c  |  71 
 arch/arm/mach-socfpga/reset_manager.c  |   5 +
 arch/arm/mach-socfpga/reset_manager_s10.c  | 140 
 arch/arm/mach-socfpga/spl_a10.c| 105 ++
 arch/arm/mach-socfpga/{spl.c => spl_gen5.c}|  46 ---
 arch/arm/mach-socfpga/spl_s10.c| 138 
 arch/arm/mach-socfpga/system_manager_s10.c |  91 +
 arch/arm/mach-socfpga/timer.c  |  17 +-
 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c |  55 +++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c|  46 +++
 board/altera/stratix10-socdk/MAINTAINERS   |   7 +
 board/altera/stratix10-socdk/Makefile  |   7 +
 board/altera/stratix10-socdk/socfpga.c |   7 +
 configs/socfpga_stratix10_defconfig|  39 +++
 drivers/ddr/altera/Makefile|   1 +
 drivers/ddr/altera/sdram_s10.c | 382 +
 include/configs/socfpga_stratix10_socdk.h  | 216 
 include/dt-bindings/reset/altr,rst-mgr-s10.h   |  97 ++
 39 files changed, 3482 insertions(+), 55 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c
 create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/spl_a10.c
 rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (83%)
 create mode 100644 arch/arm/mach-socfpga/spl_s10.c
 create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/str

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

2017-02-14 Thread Chin Liang See

On Sel, 2017-02-14 at 10:28 -0800, Dalon Westergreen wrote:
> When CSEL=0x0 the socfpga bootrom does not touch the clock
> configuration for the device.  This can lead to a boot failure
> on warm resets.  To address this, the bootrom is configured to
> run a bit of code in the last 4KB of onchip ram on a warm reset.
> This code puts the PLLs in bypass, disables the bootrom configuration
> to run the code snippet, and issues a warm reset to run the bootrom.
> 
> Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> 
> --
> Changes in V2:
>  - Fix checkpatch issues predominently due to whitespace issues
> ---
>  arch/arm/mach-socfpga/Makefile |  2 +-
>  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
>  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
>  arch/arm/mach-socfpga/misc.c   | 27 
>  arch/arm/mach-socfpga/reset_clock_manager.S| 71
> ++
>  6 files changed, 134 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
> 
> 

Acked-by: Chin Liang See <chin.liang@intel.com>

Thanks
Chin Liang
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Re: [U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2016-11-30 Thread Chin Liang See

On Sel, 2016-11-29 at 10:55 +0530, Vignesh R wrote:
> 
> On Monday 28 November 2016 07:45 PM, See, Chin Liang wrote:
> > 
> > On Jum, 2016-11-25 at 17:51 +0100, Marek Vasut wrote:
> > > 
> > > On 11/24/2016 06:35 AM, Vignesh R wrote:
> > > > 
> > > > 
> > > > According to Section 11.15.4.9.2 Indirect Write Controller of
> > > > K2G
> > > > SoC
> > > > TRM SPRUHY8D[1], the external master is only permitted to issue
> > > > 32-
> > > > bit
> > > > data interface writes until the last word of an indirect
> > > > transfer
> > > > otherwise indirect writes is known to fails sometimes. So, make
> > > > sure
> > > > that QSPI indirect writes are 32 bit sized except for the last
> > > > write. If
> > > > the txbuf is unaligned then use bounce buffer to avoid data
> > > > aborts.
> > > > 
> > > > So, now that the driver uses bounce_buffer, enable
> > > > CONFIG_BOUNCE_BUFFER
> > > > for all boards that use Cadence QSPI driver.
> > > > 
> > > > [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
> > > > 
> > > > Signed-off-by: Vignesh R 
> > > > ---
> > > Reviewed-by: Marek Vasut 
> > > 
> > > I'd like to have at least Dinh's/Chin's ack on this.
> > THanks Marek
> > 
> > Hmmm... From 11.15.4.1.1, the data slave port should able to accept
> > only byte, half-word and word access. This should not create any
> > data
> > abort but probably bad performance. But it should insignificant as
> > access time for the flash is longer than the data port access
> > itself.
> > 
> Data slave port does accept byte, half-word and word access, there
> are
> no data aborts. But indirect write controller seems to have
> limitation(as documented in section 11.15.4.9.2) couping with non 32-
> bit
> data writes on TI platform. For example with current driver if I try:
> 
> fatload mmc 0 0x8200 zImage
> sf erase 0x0 0x50
> sf write 0x8200 0x0 0x35
> sf read 0xA000 0x0 0x35
> 
> 
> md.b 0xA000
> a000: 00 00 a0 00 00 00 a0 00 00 00 a0 00 00 00 a0 00
> a010: 00 00 a0 00 00 00 a0 00 00 00 a0 00 00 00 a0 00
> a020: 03 00 00 00 18 28 6f 00 00 00 00 00 d8 5b 35 00
> a030: 01 02 03 00 00 00 00 00 00 00 00 00 00 00 00 00
> md.b 0x8200
> 8200: 00 00 a0 e1 00 00 a0 e1 00 00 a0 e1 00 00 a0 e1
> 8210: 00 00 a0 e1 00 00 a0 e1 00 00 a0 e1 00 00 a0 e1
> 8220: 03 00 00 ea 18 28 6f 01 00 00 00 00 d8 5b 35 00
> 8230: 01 02 03 04 00 90 0f e1 88 07 00 eb 01 70 a0 e1
> 
> 
> As you can see, every fourth byte turn out to be 0x00. Therefore this
> patch is required.

Thanks Vignesh

Interesting to know that the newer version of controller has this
constrain. Let me pull out my board to ensure this patch doesn't break
the SOCFPGA

Thanks
Chin Liang

> 
> 
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Re: [U-Boot] Macronix NOR_SPI and Quad I/O

2016-11-27 Thread Chin Liang See

On Sab, 2016-11-26 at 08:43 +0530, Jagan Teki wrote:
> On Fri, Nov 25, 2016 at 10:07 PM, Champ, Andy 
> wrote:
> > 
> > Hi all,
> > 
> > 
> > in the table in drivers/mtd/spi/spi_flash_ids.c there is a flag
> > WR_QPP set against Macronix devices (including the ones Dumitru is
> > just adding).
> > 
> > 
> > This is used when programming the devices on a 4-bit bus to select
> > the command to use for programming - either CMD_QUAD_PAGE_PROGRAM
> > (0x32) or CMD_PAGE_PROGRAM (0x2).
> > 
> > 
> > The Macronix devices that I have a spec for do not mention command
> > 0x32. Each of the devices that I have a spec for ( MX25L25635F
> > MX25U51245G MX25V8035F and MX25V1635F ) use command 0x38 instead.
> We need to fix this, till now no Macronix has been tested with QUAD I
> think, please send the suitable fix will review.
> 

Too bad that I don't have any Macronix part with me too.

Thanks
Chin Liang

> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com
> U-Boot, Linux | Upstream Maintainer
> Hyderabad, India.
> 
> 
> 
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Re: [U-Boot] [PATCH] ARM: socfpga: Add boot0 hook to prevent SPL corruption

2016-11-16 Thread Chin Liang See

On Rab, 2016-11-16 at 23:39 +0100, Marek Vasut wrote:
> On 11/16/2016 08:27 PM, Dinh Nguyen wrote:
> > 
> > 
> > 
> > On 11/16/2016 10:54 AM, Marek Vasut wrote:
> > > 
> > > Valid Altera SoCFPGA preloader image must contain special data at
> > > offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c
> > > or
> > > 0x50. These addresses are by default used by U-Boot's vector
> > > table
> > > and a piece of reset handler, thus a valid preloader corrupts
> > > those
> > > addresses slightly. While this works most of the time, this can
> > > and
> > > does prevent the board from rebooting sometimes and triggering
> > > this
> > > issue may even depend on compiler.
> > > 
> > > The problem is that when SoCFPGA performs warm reset, it checks
> > > the
> > > addresses 0x40..0x4b in SRAM for a valid preloader signature and
> > > header checksum. If those are found, it jumps to address 0x4c or
> > > 0x50 (this is unclear). These addresses are populated by the
> > > first
> > > few instructions of arch/arm/cpu/armv7/start.S:
> > > 
> > > 0040 :
> > > 0040:   ebfebl  0040 
> > > 
> > > 0044 :
> > > 0044:   ea12b   0094
> > > 
> > > 
> > > 0048 :
> > > 0048:   e10fmrs r0, CPSR
> > > 004c:   e200101fand r1, r0, #31
> > > 0050:   e331001ateq r1, #26
> > > 
> > > Without this patch, the CPU will enter the code at 0x004c or
> > > 0x0050 , at which point the value of r0 and r1 registers is
> > > undefined. Moreover, jumping directly to the preloader entry
> > > point
> > > at address 0x will also fail, because address 0xffff004.
> > > is invalid and contains the preloader magic.
> > > 
> > > Add BOOT0 hook which reserves the area at offset 0x40..0x5f and
> > > populates offset 0x50 with jump to the entry point. This way, the
> > > preloader signature is stored in reserved space and can not
> > > corrupt
> > > the SPL code.
> > > 
> > > Signed-off-by: Marek Vasut <ma...@denx.de>
> > > Cc: Chin Liang See <cl...@altera.com>
> > > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > > Cc: Stefan Roese <s...@denx.de>
> > > ---
> > >  arch/arm/Kconfig   |  1 +
> > >  arch/arm/mach-socfpga/include/mach/boot0.h | 28
> > > 
> > >  2 files changed, 29 insertions(+)
> > >  create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h
> > With this patch, I can properly do a soft reset on an Atlas DE0
> > Nano board.
> > 
> > So feel free to add:
> > 
> > Tested-by: Dinh Nguyen <dingu...@opensource.altera.com>
> That's great, thanks for checking ! You probably want to propagate
> this
> fix to your downstream U-Boot mutation and also that MPL loader.
> 

Great, this fix in time as we noticed this issue early of this week. We
were testing out the Arria10 SoC SPL. While for downstream, we already
cater that but not gracefully as we modified the start.s :)

THanks
Chin Liang

> --
> Best regards,
> Marek Vasut
> 
> 
> 
> Confidentiality Notice.
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Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

2016-10-18 Thread Chin Liang See

On Sel, 2016-10-18 at 06:00 +0200, Marek Vasut wrote:
> On 10/18/2016 05:22 AM, Chin Liang See wrote:
> > 
> > On Sen, 2016-10-17 at 18:14 +0200, Marek Vasut wrote:
> > > 
> > > On 10/17/2016 05:59 PM, Chin Liang See wrote:
> > > > 
> > > > 
> > > > On Sen, 2016-10-17 at 17:39 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 10/17/2016 05:28 PM, Chin Liang See wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 10/17/2016 05:07 PM, Chin Liang See wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On 10/17/2016 03:32 PM, See, Chin Liang wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > On Min, 2016-10-16 at 17:33 +0200, Marek Vasut
> > > > > > > > > > wrote:
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > Separate the Clock Manager to support both GEN5
> > > > > > > > > > > > SoC
> > > > > > > > > > > > and
> > > > > > > > > > > > Stratix 10 SoC.
> > > > > > > > > > > > 
> > > > > > > > > > > > Signed-off-by: Chin Liang See <cl...@altera.com
> > > > > > > > > > > > >
> > > > > > > > > > > > Cc: Marek Vasut <ma...@denx.de>
> > > > > > > > > > > > Cc: Dinh Nguyen <dingu...@opensource.altera.com
> > > > > > > > > > > > >
> > > > > > > > > > > > Cc: Ley Foon Tan <lf...@altera.com>
> > > > > > > > > > > > Cc: Tien Fong Chee <tfc...@altera.com>
> > > > > > > > > > > > ---
> > > > > > > > > > > >  arch/arm/mach-socfpga/clock_manager.c | 8
> > > > > > > > > > > > 
> > > > > > > > > > > >  1 file changed, 8 insertions(+)
> > > > > > > > > > > > 
> > > > > > > > > > > > diff --git a/arch/arm/mach-
> > > > > > > > > > > > socfpga/clock_manager.c
> > > > > > > > > > > > b/arch/arm/mach-
> > > > > > > > > > > > socfpga/clock_manager.c
> > > > > > > > > > > > index aa71636..0d67b3c 100644
> > > > > > > > > > > > --- a/arch/arm/mach-socfpga/clock_manager.c
> > > > > > > > > > > > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > > > > > > > > > > > @@ -10,6 +10,7 @@
> > > > > > > > > > > > 
> > > > > > > > > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > > > > > > > > 
> > > > > > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >

Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

2016-10-18 Thread Chin Liang See

On Sen, 2016-10-17 at 18:14 +0200, Marek Vasut wrote:
> On 10/17/2016 05:59 PM, Chin Liang See wrote:
> > 
> > On Sen, 2016-10-17 at 17:39 +0200, Marek Vasut wrote:
> > > 
> > > On 10/17/2016 05:28 PM, Chin Liang See wrote:
> > > > 
> > > > 
> > > > On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 10/17/2016 05:07 PM, Chin Liang See wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 10/17/2016 03:32 PM, See, Chin Liang wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Min, 2016-10-16 at 17:33 +0200, Marek Vasut wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > Separate the Clock Manager to support both GEN5 SoC
> > > > > > > > > > and
> > > > > > > > > > Stratix 10 SoC.
> > > > > > > > > > 
> > > > > > > > > > Signed-off-by: Chin Liang See <cl...@altera.com>
> > > > > > > > > > Cc: Marek Vasut <ma...@denx.de>
> > > > > > > > > > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > > > > > > > > > Cc: Ley Foon Tan <lf...@altera.com>
> > > > > > > > > > Cc: Tien Fong Chee <tfc...@altera.com>
> > > > > > > > > > ---
> > > > > > > > > >  arch/arm/mach-socfpga/clock_manager.c | 8 
> > > > > > > > > >  1 file changed, 8 insertions(+)
> > > > > > > > > > 
> > > > > > > > > > diff --git a/arch/arm/mach-socfpga/clock_manager.c
> > > > > > > > > > b/arch/arm/mach-
> > > > > > > > > > socfpga/clock_manager.c
> > > > > > > > > > index aa71636..0d67b3c 100644
> > > > > > > > > > --- a/arch/arm/mach-socfpga/clock_manager.c
> > > > > > > > > > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > > > > > > > > > @@ -10,6 +10,7 @@
> > > > > > > > > > 
> > > > > > > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > > > > > > 
> > > > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > > > > >  static const struct socfpga_clock_manager
> > > > > > > > > > *clock_manager_base
> > > > > > > > > > =
> > > > > > > > > >   (struct socfpga_clock_manager
> > > > > > > > > > *)SOCFPGA_CLKMGR_ADDRESS;
> > > > > > > > > > 
> > > > > > > > > > @@ -446,9 +447,11 @@ unsigned int
> > > > > > > > > > cm_get_l4_sp_clk_hz(void)
> > > > > > > > > > 
> > > > > > > > > >   return clock;
> > > > > > > > > >  }
> > > > > > > > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > > > > > > > > 
> > > > > > > > > >  unsigned int cm_get_mmc_controller_clk_hz(void)
> > > > > > > > > >  {
> > > > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > > > > >   uint32_t reg, clock = 0;
> > > > > > > > > > 
> > > > > > > > > >   /* identify the source of MMC clock */
> > > > > > > > > > @@ -475,8 +478,12 @@ unsi

Re: [U-Boot] [PATCH v3 05/12] arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10

2016-10-17 Thread Chin Liang See

On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> On 10/17/2016 03:35 PM, See, Chin Liang wrote:
> > 
> > On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote:
> > > 
> > > On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > > > 
> > > > 
> > > > Disable the FPGA Manager for Stratix 10 SoC as we are not
> > > > using this for SOCVP
> > > If it's not used on SoCVP, then shouldn't this be disabled only
> > > for
> > > SoCVP instead of S10 ?
> > > 
> > We will be enhancing this code to support the hardware / emulation
> > in
> > later phase. In another word, will switch the support from SOCVP to
> > hardware once its available.
> > 
> This is confusing, what would happen if someone tries to use old u-
> boot
> on real hardware ?

It won't work until added drivers for Clocks, Reset and DDR. Current
state would be good for SOCVP only where not all hardware is simulated.

Thanks
Chin Liang

> 
> --
> Best regards,
> Marek Vasut
> 
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Re: [U-Boot] [PATCH v3 09/12] arm: socfpga: stratix10: Add board directory for Stratix 10 socdk

2016-10-17 Thread Chin Liang See

On Min, 2016-10-16 at 17:39 +0200, Marek Vasut wrote:
> On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > 
> > Add board folder
> directory
> 

Will fix this.

> > 
> > for Stratix 10 SoC development kit
> > 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > Cc: Ley Foon Tan <lf...@altera.com>
> > Cc: Tien Fong Chee <tfc...@altera.com>
> > ---
> >  board/altera/stratix10-socdk/MAINTAINERS | 7 +++
> >  board/altera/stratix10-socdk/Makefile| 7 +++
> >  board/altera/stratix10-socdk/socfpga.c   | 7 +++
> >  3 files changed, 21 insertions(+)
> >  create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
> >  create mode 100644 board/altera/stratix10-socdk/Makefile
> >  create mode 100644 board/altera/stratix10-socdk/socfpga.c
> > 
> > diff --git a/board/altera/stratix10-socdk/MAINTAINERS
> > b/board/altera/stratix10-socdk/MAINTAINERS
> > new file mode 100644
> > index 000..596933c
> > --- /dev/null
> > +++ b/board/altera/stratix10-socdk/MAINTAINERS
> > @@ -0,0 +1,7 @@
> > +SOCFPGA BOARD
> > +M:   Chin-Liang See <cl...@altera.com>
> > +M:   Dinh Nguyen <dingu...@opensource.altera.com>
> > +S:   Maintained
> > +F:   board/altera/stratix10-socdk/
> > +F:   include/configs/socfpga_stratix10_socdk.h
> > +F:   configs/socfpga_stratix10_defconfig
> > diff --git a/board/altera/stratix10-socdk/Makefile
> > b/board/altera/stratix10-socdk/Makefile
> > new file mode 100644
> > index 000..a0c8024
> > --- /dev/null
> > +++ b/board/altera/stratix10-socdk/Makefile
> > @@ -0,0 +1,7 @@
> > +#
> > +# Copyright (C) 2016, Intel Corporation
> > +#
> > +# SPDX-License-Identifier:   GPL-2.0
> > +#
> > +
> > +obj-y:= socfpga.o
> > diff --git a/board/altera/stratix10-socdk/socfpga.c
> > b/board/altera/stratix10-socdk/socfpga.c
> > new file mode 100644
> > index 000..6778c04
> > --- /dev/null
> > +++ b/board/altera/stratix10-socdk/socfpga.c
> > @@ -0,0 +1,7 @@
> > +/*
> > + * Copyright (C) 2016, Intel Corporation
> > + *
> > + * SPDX-License-Identifier:  GPL-2.0
> > + */
> > +
> > +#include 
> > 
> Is this even needed or do we still need an empty file ?

As a place holder in case customization needed for socdk. Will document
this as avoiding customer change the common code.

Thanks
Chin Liang

> 
> --
> Best regards,
> Marek Vasut
> 
> 
> 
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Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

2016-10-17 Thread Chin Liang See

On Sen, 2016-10-17 at 17:39 +0200, Marek Vasut wrote:
> On 10/17/2016 05:28 PM, Chin Liang See wrote:
> > 
> > On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote:
> > > 
> > > On 10/17/2016 05:07 PM, Chin Liang See wrote:
> > > > 
> > > > 
> > > > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 10/17/2016 03:32 PM, See, Chin Liang wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Min, 2016-10-16 at 17:33 +0200, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > Separate the Clock Manager to support both GEN5 SoC and
> > > > > > > > Stratix 10 SoC.
> > > > > > > > 
> > > > > > > > Signed-off-by: Chin Liang See <cl...@altera.com>
> > > > > > > > Cc: Marek Vasut <ma...@denx.de>
> > > > > > > > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > > > > > > > Cc: Ley Foon Tan <lf...@altera.com>
> > > > > > > > Cc: Tien Fong Chee <tfc...@altera.com>
> > > > > > > > ---
> > > > > > > >  arch/arm/mach-socfpga/clock_manager.c | 8 
> > > > > > > >  1 file changed, 8 insertions(+)
> > > > > > > > 
> > > > > > > > diff --git a/arch/arm/mach-socfpga/clock_manager.c
> > > > > > > > b/arch/arm/mach-
> > > > > > > > socfpga/clock_manager.c
> > > > > > > > index aa71636..0d67b3c 100644
> > > > > > > > --- a/arch/arm/mach-socfpga/clock_manager.c
> > > > > > > > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > > > > > > > @@ -10,6 +10,7 @@
> > > > > > > > 
> > > > > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > > > > 
> > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > > >  static const struct socfpga_clock_manager
> > > > > > > > *clock_manager_base
> > > > > > > > =
> > > > > > > >   (struct socfpga_clock_manager
> > > > > > > > *)SOCFPGA_CLKMGR_ADDRESS;
> > > > > > > > 
> > > > > > > > @@ -446,9 +447,11 @@ unsigned int
> > > > > > > > cm_get_l4_sp_clk_hz(void)
> > > > > > > > 
> > > > > > > >   return clock;
> > > > > > > >  }
> > > > > > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > > > > > > 
> > > > > > > >  unsigned int cm_get_mmc_controller_clk_hz(void)
> > > > > > > >  {
> > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > > >   uint32_t reg, clock = 0;
> > > > > > > > 
> > > > > > > >   /* identify the source of MMC clock */
> > > > > > > > @@ -475,8 +478,12 @@ unsigned int
> > > > > > > > cm_get_mmc_controller_clk_hz(void)
> > > > > > > >   /* further divide by 4 as we have fixed divider
> > > > > > > > at
> > > > > > > > wrapper */
> > > > > > > >   clock /= 4;
> > > > > > > >   return clock;
> > > > > > > > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > > > > > > > + return 2500;
> > > > > > > Is this always gonna be the case or is this S10VP
> > > > > > > specific ?
> > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > > > > > >  }
> > > > > > > > 
> > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > > >  unsigned int cm_get_qspi_controller_clk_hz(void)
> > > > > > > >  {
> > > > > > > >   uint32_t reg, clock = 0;
> > > > > > > > @@ -556,3 +563,4 @@ U_BOOT_CMD(
> > > > > > > >   "display clocks",
> > > > > > > >   ""
> > > > > > > Why does the clock display not work on S10 ? Are some
> > > > > > > functions
> > > > > > > missing?
> > > > > > Not for SOCVP. But will be added in later stage when
> > > > > > testing
> > > > > > against
> > > > > > emulation
> > > > > How hard would it be to add this missing functionality now ?
> > > > > 
> > > > That will take weeks as that need to be validated as whole in
> > > > emulation
> > > > platform.
> > > You mean printing a few clock information based on some values
> > > from
> > > registers would take weeks ? Why ?
> > > 
> > Oh actually I am referring all the managers code such as full Clock
> > Manager, Reset Manager ... plus testing. Testing is the part take
> > some
> > significant time especially slow when come to emulation.
> Just use empty functions for the clock init code (since it's not
> needed
> on the socvp) and populate the clock reporting functions. That should
> be
> simple, right ?

Can be done but the value won't be meaningful as the register is
uninitialzied. Unless we hardcode to a hard value which might not sound
right. 

Thanks
Chin Liang

> 
> --
> Best regards,
> Marek Vasut
> 
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Re: [U-Boot] [PATCH v3 11/12] arm: socfpga: Add SPL support for Stratix 10 SoC

2016-10-17 Thread Chin Liang See

On Min, 2016-10-16 at 17:41 +0200, Marek Vasut wrote:
> On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > 
> > Add SPL support for Stratix 10 SoC development kit
> > 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > Cc: Ley Foon Tan <lf...@altera.com>
> > Cc: Tien Fong Chee <tfc...@altera.com>
> > ---
> >  arch/arm/mach-socfpga/Makefile | 13 -
> >  arch/arm/mach-socfpga/spl.c| 13 -
> >  2 files changed, 20 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index 5038919..2b00c8c 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -8,17 +8,20 @@
> >  #
> > 
> >  obj-y+= misc.o timer.o reset_manager.o clock_manager.o
> > board.o
> > -
> > -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > -
> >  obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += mmu-arm64.o
> > 
> > +ifdef CONFIG_SPL_BUILD
> > +obj-y += spl.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o
> > +endif
> > +
> > +ifdef CONFIG_TARGET_SOCFPGA_GEN5
> >  # QTS-generated config file wrappers
> > -obj-$(CONFIG_TARGET_SOCFPGA_GEN5)+= scan_manager.o
> > wrap_pll_config.o \
> > -fpga_manager.o
> > system_manager.o
> > +obj-y+= scan_manager.o wrap_pll_config.o fpga_manager.o
> > system_manager.o
> >  obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o
> > wrap_pinmux_config.o  \
> >  wrap_sdram_config.o
> >  CFLAGS_wrap_iocsr_config.o   += -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_pinmux_config.o  += -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_sdram_config.o   += -I$(srctree)/board/$(BOARDDIR)
> > +endif
> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > socfpga/spl.c
> > index fec4c7a..b514a01 100644
> > --- a/arch/arm/mach-socfpga/spl.c
> > +++ b/arch/arm/mach-socfpga/spl.c
> It seems like the only thing which happens in the spl.c for S10 is it
> calls spl_console_init(). In that case, just split the spl into gen5
> one
> and S10 one instead of polluting it with ifdefs.
> 

Ok can split this out as already seeing different flow for S10
hardware.

Thanks
Chin Liang
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Re: [U-Boot] [PATCH v3 05/12] arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10

2016-10-17 Thread Chin Liang See

On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote:
> On 10/17/2016 05:14 PM, Chin Liang See wrote:
> > 
> > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> > > 
> > > On 10/17/2016 03:35 PM, See, Chin Liang wrote:
> > > > 
> > > > 
> > > > On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > Disable the FPGA Manager for Stratix 10 SoC as we are not
> > > > > > using this for SOCVP
> > > > > If it's not used on SoCVP, then shouldn't this be disabled
> > > > > only
> > > > > for
> > > > > SoCVP instead of S10 ?
> > > > > 
> > > > We will be enhancing this code to support the hardware /
> > > > emulation
> > > > in
> > > > later phase. In another word, will switch the support from
> > > > SOCVP to
> > > > hardware once its available.
> > > > 
> > > This is confusing, what would happen if someone tries to use old
> > > u-
> > > boot
> > > on real hardware ?
> > It won't work until added drivers for Clocks, Reset and DDR.
> > Current
> > state would be good for SOCVP only where not all hardware is
> > simulated.
> In that case, mark it as SoCVP to prevent confusion please.
> 

In this case, I can update the config to indicate this is S10 SOCVP.

Thanks
Chin Liang

> 
> --
> Best regards,
> Marek Vasut
> 
> 
> 
> Confidentiality Notice.
> This message may contain information that is confidential or
> otherwise protected from disclosure. If you are not the intended
> recipient, you are hereby notified that any use, disclosure,
> dissemination, distribution, or copying of this message, or any
> attachments, is strictly prohibited. If you have received this
> message in error, please advise the sender by reply e-mail, and
> delete the message and any attachments. Thank you.
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Re: [U-Boot] [PATCH v3 01/12] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

2016-10-17 Thread Chin Liang See

On Sen, 2016-10-17 at 15:40 +0200, Marek Vasut wrote:
> On 10/17/2016 03:26 PM, See, Chin Liang wrote:
> > 
> > On Min, 2016-10-16 at 17:31 +0200, Marek Vasut wrote:
> > > 
> > > On 10/13/2016 10:32 AM, Chin Liang See wrote:
> > > > 
> > > > 
> > > > Add base address header file for Stratix10 SoC
> > > > 
> > > > Signed-off-by: Chin Liang See <cl...@altera.com>
> > > > Cc: Marek Vasut <ma...@denx.de>
> > > > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > > > Cc: Ley Foon Tan <lf...@altera.com>
> > > > Cc: Tien Fong Chee <tfc...@altera.com>
> > > > Acked-by: Marek Vasut <ma...@denx.de>
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48
> > > > ++
> > > >  1 file changed, 48 insertions(+)
> > > >  create mode 100644 arch/arm/mach-
> > > > socfpga/include/mach/base_addr_s10.h
> > > > 
> > > OK, V3 patch, but where's the changelog ? ;-)
> > > 
> > Oh I just added the changelog if particular patch is modified. For
> > this
> > patch 1/12, no change for v2 to v3 :)
> OK, got it.
> 
> [...]
> 
> > 
> > > 
> > > Confidentiality Notice.
> Oh yeah ?
> 

Strange as I didn't see this when using Intel email send to my gmail.
In this case, better use back my old altera.com while sorting with IT.

Thanks
Chin Liang

> > 
> > > 
> > > This message may contain information that is confidential or
> > > otherwise protected from disclosure. If you are not the intended
> > > recipient, you are hereby notified that any use, disclosure,
> > > dissemination, distribution, or copying of this message, or any
> > > attachments, is strictly prohibited. If you have received this
> > > message in error, please advise the sender by reply e-mail, and
> > > delete the message and any attachments. Thank you.
> 
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Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

2016-10-17 Thread Chin Liang See

On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote:
> On 10/17/2016 05:07 PM, Chin Liang See wrote:
> > 
> > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> > > 
> > > On 10/17/2016 03:32 PM, See, Chin Liang wrote:
> > > > 
> > > > 
> > > > On Min, 2016-10-16 at 17:33 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > Separate the Clock Manager to support both GEN5 SoC and
> > > > > > Stratix 10 SoC.
> > > > > > 
> > > > > > Signed-off-by: Chin Liang See <cl...@altera.com>
> > > > > > Cc: Marek Vasut <ma...@denx.de>
> > > > > > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > > > > > Cc: Ley Foon Tan <lf...@altera.com>
> > > > > > Cc: Tien Fong Chee <tfc...@altera.com>
> > > > > > ---
> > > > > >  arch/arm/mach-socfpga/clock_manager.c | 8 
> > > > > >  1 file changed, 8 insertions(+)
> > > > > > 
> > > > > > diff --git a/arch/arm/mach-socfpga/clock_manager.c
> > > > > > b/arch/arm/mach-
> > > > > > socfpga/clock_manager.c
> > > > > > index aa71636..0d67b3c 100644
> > > > > > --- a/arch/arm/mach-socfpga/clock_manager.c
> > > > > > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > > > > > @@ -10,6 +10,7 @@
> > > > > > 
> > > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > > 
> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > >  static const struct socfpga_clock_manager
> > > > > > *clock_manager_base
> > > > > > =
> > > > > >   (struct socfpga_clock_manager
> > > > > > *)SOCFPGA_CLKMGR_ADDRESS;
> > > > > > 
> > > > > > @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> > > > > > 
> > > > > >   return clock;
> > > > > >  }
> > > > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > > > > 
> > > > > >  unsigned int cm_get_mmc_controller_clk_hz(void)
> > > > > >  {
> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > >   uint32_t reg, clock = 0;
> > > > > > 
> > > > > >   /* identify the source of MMC clock */
> > > > > > @@ -475,8 +478,12 @@ unsigned int
> > > > > > cm_get_mmc_controller_clk_hz(void)
> > > > > >   /* further divide by 4 as we have fixed divider at
> > > > > > wrapper */
> > > > > >   clock /= 4;
> > > > > >   return clock;
> > > > > > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > > > > > + return 2500;
> > > > > Is this always gonna be the case or is this S10VP specific ?
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > > > >  }
> > > > > > 
> > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > >  unsigned int cm_get_qspi_controller_clk_hz(void)
> > > > > >  {
> > > > > >   uint32_t reg, clock = 0;
> > > > > > @@ -556,3 +563,4 @@ U_BOOT_CMD(
> > > > > >   "display clocks",
> > > > > >   ""
> > > > > Why does the clock display not work on S10 ? Are some
> > > > > functions
> > > > > missing?
> > > > Not for SOCVP. But will be added in later stage when testing
> > > > against
> > > > emulation
> > > How hard would it be to add this missing functionality now ?
> > > 
> > That will take weeks as that need to be validated as whole in
> > emulation
> > platform.
> You mean printing a few clock information based on some values from
> registers would take weeks ? Why ?
> 

Oh actually I am referring all the managers code such as full Clock
Manager, Reset Manager ... plus testing. Testing is the part take some
significant time especially slow when come to emulation.

Thanks
Chin Liang

[..]
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Re: [U-Boot] [PATCH v3 07/12] arm: socfpga: sysmgr: Disable System Manager for Stratix 10

2016-10-17 Thread Chin Liang See

On Min, 2016-10-16 at 17:38 +0200, Marek Vasut wrote:
> On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > 
> > Disable the System Manager for Stratix 10 SoC as we are not
> > using this for SOCVP
> So I wonder, shouldn't we introduce some bool Kconfig entry,
> something
> like CONFIG_SOCFPGA_HAS_SYSTEMMANAGER and then make each target (AV,
> CV,
> S10, S10SoCVP...) select whether it has it or not ? I think this
> might
> make things a bit cleaner.

This sound a good idea. Let's do this then.

Thanks
Chin Liang

[..]
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Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

2016-10-17 Thread Chin Liang See

On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> On 10/17/2016 03:32 PM, See, Chin Liang wrote:
> > 
> > On Min, 2016-10-16 at 17:33 +0200, Marek Vasut wrote:
> > > 
> > > On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > > > 
> > > > 
> > > > Separate the Clock Manager to support both GEN5 SoC and
> > > > Stratix 10 SoC.
> > > > 
> > > > Signed-off-by: Chin Liang See <cl...@altera.com>
> > > > Cc: Marek Vasut <ma...@denx.de>
> > > > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > > > Cc: Ley Foon Tan <lf...@altera.com>
> > > > Cc: Tien Fong Chee <tfc...@altera.com>
> > > > ---
> > > >  arch/arm/mach-socfpga/clock_manager.c | 8 
> > > >  1 file changed, 8 insertions(+)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/clock_manager.c
> > > > b/arch/arm/mach-
> > > > socfpga/clock_manager.c
> > > > index aa71636..0d67b3c 100644
> > > > --- a/arch/arm/mach-socfpga/clock_manager.c
> > > > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > > > @@ -10,6 +10,7 @@
> > > > 
> > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > 
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  static const struct socfpga_clock_manager *clock_manager_base
> > > > =
> > > >   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> > > > 
> > > > @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> > > > 
> > > >   return clock;
> > > >  }
> > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > > 
> > > >  unsigned int cm_get_mmc_controller_clk_hz(void)
> > > >  {
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >   uint32_t reg, clock = 0;
> > > > 
> > > >   /* identify the source of MMC clock */
> > > > @@ -475,8 +478,12 @@ unsigned int
> > > > cm_get_mmc_controller_clk_hz(void)
> > > >   /* further divide by 4 as we have fixed divider at
> > > > wrapper */
> > > >   clock /= 4;
> > > >   return clock;
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > > > + return 2500;
> > > Is this always gonna be the case or is this S10VP specific ?
> > > 
> > > > 
> > > > 
> > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > >  }
> > > > 
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  unsigned int cm_get_qspi_controller_clk_hz(void)
> > > >  {
> > > >   uint32_t reg, clock = 0;
> > > > @@ -556,3 +563,4 @@ U_BOOT_CMD(
> > > >   "display clocks",
> > > >   ""
> > > Why does the clock display not work on S10 ? Are some functions
> > > missing?
> > Not for SOCVP. But will be added in later stage when testing
> > against
> > emulation
> How hard would it be to add this missing functionality now ?
> 

That will take weeks as that need to be validated as whole in emulation
platform.

> > 
> > > 
> > > Maybe we should split the clock manager into common part and then
> > > gen5
> > > and gen10 specific parts ?
> > Ok, we can do that as initially we were worried too many files
> > created
> > within mach-socfpga.
> It's probably better than polluting the clock code with ifdefs.
> 

Ok, we have an consensus then

Thanks
Chin Liang


> [...]
> 
> 
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[U-Boot] [PATCH v3 09/12] arm: socfpga: stratix10: Add board directory for Stratix 10 socdk

2016-10-13 Thread Chin Liang See

Add board folder for Stratix 10 SoC development kit

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
 board/altera/stratix10-socdk/MAINTAINERS | 7 +++
 board/altera/stratix10-socdk/Makefile| 7 +++
 board/altera/stratix10-socdk/socfpga.c   | 7 +++
 3 files changed, 21 insertions(+)
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c

diff --git a/board/altera/stratix10-socdk/MAINTAINERS 
b/board/altera/stratix10-socdk/MAINTAINERS
new file mode 100644
index 000..596933c
--- /dev/null
+++ b/board/altera/stratix10-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chin-Liang See <cl...@altera.com>
+M: Dinh Nguyen <dingu...@opensource.altera.com>
+S: Maintained
+F: board/altera/stratix10-socdk/
+F: include/configs/socfpga_stratix10_socdk.h
+F: configs/socfpga_stratix10_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile 
b/board/altera/stratix10-socdk/Makefile
new file mode 100644
index 000..a0c8024
--- /dev/null
+++ b/board/altera/stratix10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016, Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c 
b/board/altera/stratix10-socdk/socfpga.c
new file mode 100644
index 000..6778c04
--- /dev/null
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
-- 
2.2.2

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[U-Boot] [PATCH v3 10/12] arm: dts: socfpga: Add dts for Stratix 10 socdk

2016-10-13 Thread Chin Liang See

Add device tree for Stratix 10 SoC development kit

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
Acked-by: Marek Vasut <ma...@denx.de>
---
Changes for v3
- Changed to correct file mode
- Removed trampoline code
- Fixed the DDR size to 2GB and SDMMC interrupt to 96
---
 arch/arm/dts/Makefile|  3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts | 71 
 2 files changed, 73 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8458f6b..1809660 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -131,7 +131,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts 
b/arch/arm/dts/socfpga_stratix10_socdk.dts
new file mode 100644
index 000..bb65f2b
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -0,0 +1,71 @@
+/*
+ *  Copyright (C) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+
+/ {
+   model = "Altera SOCFPGA Stratix 10 SoC Development Kit";
+   compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x8000>; /* 2GB */
+   };
+
+   regulator_3_3v: 3-3-v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   ranges;
+   u-boot,dm-pre-reloc;
+
+   mmc0: dwmmc0@0xff808000 {
+   compatible = "altr,socfpga-dw-mshc";
+   reg = <0xff808000 0x1000>;
+   interrupts = <0 96 4>;
+   num-slots = <1>;
+   broken-cd;
+   bus-width = <4>;
+   fifo-depth = <0x400>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   drvsel = <3>;
+   smplsel = <0>;
+   status = "okay";
+   u-boot,dm-pre-reloc;
+   vmmc-supply = <_3_3v>;
+   vqmmc-supply = <_3_3v>;
+   };
+
+   uart0: serial0@ffc02000 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0xffc02000 0x1000>;
+   interrupts = <0 108 4>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   status = "okay";
+   };
+   };
+};
-- 
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[U-Boot] [PATCH v3 12/12] arm: socfpga: Add support for Stratix 10 SoC dev kit

2016-10-13 Thread Chin Liang See

Add support for Stratix 10 SoC development kit

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
 arch/arm/Kconfig  |   4 +-
 arch/arm/mach-socfpga/Kconfig |  10 ++
 configs/socfpga_stratix10_defconfig   |  21 
 include/configs/socfpga_stratix10_socdk.h | 166 ++
 4 files changed, 200 insertions(+), 1 deletion(-)
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d3303b..f75010a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -544,13 +544,15 @@ config ARCH_SNAPDRAGON
 
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
-   select CPU_V7
+   select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
+   select ARM64 if TARGET_SOCFPGA_STRATIX10
select SUPPORT_SPL
select OF_CONTROL
select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
+   select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
 
 config TARGET_CM_T43
bool "Support cm_t43"
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index d91b8bb..12452a9 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -38,6 +38,9 @@ config TARGET_SOCFPGA_CYCLONE5
 config TARGET_SOCFPGA_GEN5
bool
 
+config TARGET_SOCFPGA_STRATIX10
+   bool
+
 choice
prompt "Altera SOCFPGA board select"
optional
@@ -70,6 +73,10 @@ config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Stratix 10)"
+   select TARGET_SOCFPGA_STRATIX10
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -89,11 +96,13 @@ config SYS_BOARD
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
+   default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+   default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
@@ -112,6 +121,7 @@ config SYS_CONFIG_NAME
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+   default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif
diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
new file mode 100644
index 000..b72aa8e
--- /dev/null
+++ b/configs/socfpga_stratix10_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_STRATIX10=y
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_IDENT_STRING="socfpga_stratix10"
+CONFIG_SYS_NS16550=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
new file mode 100644
index 000..ea70ec7
--- /dev/null
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
+#define __CONFIG_SOCFGPA_STRATIX10_H__
+
+#include 
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_TEXT_BASE   0x100
+#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
+#define CONFIG_LOADADDR0x8
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+#define CONFIG_REMAKE_ELF
+# define COUNTER_FREQUENCY 0x0180
+
+
+/*
+ * U-Boot console configurations
+ */
+#define C

[U-Boot] [PATCH v3 07/12] arm: socfpga: sysmgr: Disable System Manager for Stratix 10

2016-10-13 Thread Chin Liang See

Disable the System Manager for Stratix 10 SoC as we are not
using this for SOCVP

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
 arch/arm/mach-socfpga/Makefile | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index a8ea277..71c17ca 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -7,14 +7,13 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
-  board.o
+obj-y  += misc.o timer.o reset_manager.o clock_manager.o board.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  fpga_manager.o
+  fpga_manager.o system_manager.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
-- 
2.2.2

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[U-Boot] [PATCH v3 11/12] arm: socfpga: Add SPL support for Stratix 10 SoC

2016-10-13 Thread Chin Liang See

Add SPL support for Stratix 10 SoC development kit

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
 arch/arm/mach-socfpga/Makefile | 13 -
 arch/arm/mach-socfpga/spl.c| 13 -
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5038919..2b00c8c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,17 +8,20 @@
 #
 
 obj-y  += misc.o timer.o reset_manager.o clock_manager.o board.o
-
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
-
 obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += mmu-arm64.o
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
-  fpga_manager.o system_manager.o
+obj-y  += scan_manager.o wrap_pll_config.o fpga_manager.o system_manager.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..b514a01 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -22,6 +22,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
@@ -30,9 +31,11 @@ static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 u32 spl_boot_device(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 bsel = readl(_regs->bootinfo);
 
switch (bsel & 0x7) {
@@ -55,6 +58,9 @@ u32 spl_boot_device(void)
printf("Invalid boot device (bsel=%08x)!\n", bsel);
hang();
}
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+   return BOOT_DEVICE_MMC1;
+#endif
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -68,6 +74,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, _regs->lwhps2fpgaregs);
@@ -77,9 +84,11 @@ static void socfpga_nic301_slave_ns(void)
writel(0x1, _regs->ocram);
writel(0x1, _regs->sdrdata);
 }
+#endif
 
 void board_init_f(ulong dummy)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
const struct cm_config *cm_default_cfg = cm_get_default_config();
 #endif
@@ -152,10 +161,11 @@ void board_init_f(ulong dummy)
debug("Unfreezing/Thaw all I/O banks\n");
/* unfreeze / thaw all IO banks */
sys_mgr_frzctrl_thaw_req();
-
+#endif
/* enable console uart printing */
preloader_console_init();
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
if (sdram_mmr_init_full(0x) != 0) {
puts("SDRAM init failed.\n");
hang();
@@ -181,4 +191,5 @@ void board_init_f(ulong dummy)
 
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
+#endif
 }
-- 
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[U-Boot] [PATCH v3 06/12] arm: socfpga: misc: Separate the misc.c for Stratix 10

2016-10-13 Thread Chin Liang See

Separate the misc.c to support both GEN5 SoC and Stratix 10 SoC.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
 arch/arm/mach-socfpga/misc.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 5cbd8a4..295121f 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -24,6 +24,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct socfpga_system_manager *sysmgr_regs =
@@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+#endif
 
 int dram_init(void)
 {
@@ -41,6 +44,7 @@ int dram_init(void)
return 0;
 }
 
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
 void enable_caches(void)
 {
 #ifndef CONFIG_SYS_ICACHE_OFF
@@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool print_id)
   socfpga_fpga_model[i].name, version);
return i;
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
 
 /*
  * Print CPU information
@@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
printf("BOOT:  %s\n", bsel_str[bsel].name);
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+   puts("CPU:   Altera SoCFPGA Platform\n");
+   puts("FPGA:  Altera Stratix 10\n");
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
return 0;
 }
 #endif
 
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_ARCH_MISC_INIT
 int arch_misc_init(void)
 {
@@ -469,3 +480,4 @@ U_BOOT_CMD(
"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA 
bridges\n"
""
 );
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
2.2.2

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[U-Boot] [PATCH v3 03/12] arm: socfpga: rstmgr: Separate the Reset Manager for Stratix 10

2016-10-13 Thread Chin Liang See

Separate the Reset Manager to support both GEN5 SoC and
Stratix 10 SoC.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
Acked-by: Marek Vasut <ma...@denx.de>
---
 arch/arm/mach-socfpga/reset_manager.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-socfpga/reset_manager.c 
b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..0fa5f1a 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -15,8 +15,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
 
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
@@ -31,8 +33,10 @@ void socfpga_per_reset(u32 reset, int set)
reg = _manager_base->per2_mod_reset;
else if (RSTMGR_BANK(reset) == 3)
reg = _manager_base->brg_mod_reset;
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
else if (RSTMGR_BANK(reset) == 4)
reg = _manager_base->misc_mod_reset;
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
else/* Invalid reset register, do nothing */
return;
 
@@ -60,9 +64,15 @@ void socfpga_per_reset_all(void)
  */
 void reset_cpu(ulong addr)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* request a warm reset */
writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
_manager_base->ctrl);
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+   writel((1 << RSTMGR_MPUMODRST_CORE0),
+   _manager_base->mpu_mod_reset);
+#endif
+
/*
 * infinite loop here as watchdog will trigger and reset
 * the processor
@@ -92,6 +102,7 @@ void socfpga_bridges_reset(int enable)
 
 void socfpga_bridges_reset(int enable)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
L3REGS_REMAP_HPS2FPGA_MASK |
L3REGS_REMAP_OCRAM_MASK;
@@ -116,5 +127,6 @@ void socfpga_bridges_reset(int enable)
/* Remap the bridges into memory map */
writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
}
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
 }
 #endif
-- 
2.2.2

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[U-Boot] [PATCH v3 05/12] arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10

2016-10-13 Thread Chin Liang See

Disable the FPGA Manager for Stratix 10 SoC as we are not
using this for SOCVP

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
 arch/arm/mach-socfpga/Makefile | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..a8ea277 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,12 +8,13 @@
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
-  fpga_manager.o board.o
+  board.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
+  fpga_manager.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
-- 
2.2.2

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[U-Boot] [PATCH v3 08/12] arm: socfpga: mmu: Add memory map layout for Stratix 10 SoC

2016-10-13 Thread Chin Liang See

Add memory map layout for Stratix 10 SoC

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
 arch/arm/mach-socfpga/Makefile|  2 ++
 arch/arm/mach-socfpga/mmu-arm64.c | 71 +++
 2 files changed, 73 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 71c17ca..5038919 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -11,6 +11,8 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o 
board.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += mmu-arm64.o
+
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o \
   fpga_manager.o system_manager.o
diff --git a/arch/arm/mach-socfpga/mmu-arm64.c 
b/arch/arm/mach-socfpga/mmu-arm64.c
new file mode 100644
index 000..3b73143
--- /dev/null
+++ b/arch/arm/mach-socfpga/mmu-arm64.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+   {
+   /* MEM 2GB*/
+   .virt   = 0x0UL,
+   .phys   = 0x0UL,
+   .size   = 0x8000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* FPGA 1.5GB */
+   .virt   = 0x8000UL,
+   .phys   = 0x8000UL,
+   .size   = 0x6000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* DEVICE 142MB */
+   .virt   = 0xF700UL,
+   .phys   = 0xF700UL,
+   .size   = 0x08E0UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* OCRAM 1MB but available 256KB */
+   .virt   = 0xFFE0UL,
+   .phys   = 0xFFE0UL,
+   .size   = 0x0010UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* DEVICE 32KB */
+   .virt   = 0xFFFCUL,
+   .phys   = 0xFFFCUL,
+   .size   = 0x8000UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* MEM 124GB */
+   .virt   = 0x01UL,
+   .phys   = 0x01UL,
+   .size   = 0x1FUL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+   PTE_BLOCK_INNER_SHARE,
+   }, {
+   /* DEVICE 4GB */
+   .virt   = 0x20UL,
+   .phys   = 0x20UL,
+   .size   = 0x01UL,
+   .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+   PTE_BLOCK_NON_SHARE |
+   PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+   }, {
+   /* List terminator */
+   },
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;
-- 
2.2.2

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[U-Boot] [PATCH v3 00/12] Add support for Stratix 10 SoC

2016-10-13 Thread Chin Liang See

Add support for Stratix 10 SoC which is ARM64 based. This series
of patches are tested with Stratix 10 SOC Virtual Platform that
is available today.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
Chin Liang See (12):
  arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address
  arm: socfpga: rstmgr: Add Reset Manager for Stratix 10
  arm: socfpga: rstmgr: Separate the Reset Manager for Stratix 10
  arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10
  arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10
  arm: socfpga: misc: Separate the misc.c for Stratix 10
  arm: socfpga: sysmgr: Disable System Manager for Stratix 10
  arm: socfpga: mmu: Add memory map layout for Stratix 10 SoC
  arm: socfpga: stratix10: Add board directory for Stratix 10 socdk
  arm: dts: socfpga: Add dts for Stratix 10 socdk
  arm: socfpga: Add SPL support for Stratix 10 SoC
  arm: socfpga: Add support for Stratix 10 SoC dev kit

 arch/arm/Kconfig   |   4 +-
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts   |  71 +
 arch/arm/mach-socfpga/Kconfig  |  10 ++
 arch/arm/mach-socfpga/Makefile |  13 +-
 arch/arm/mach-socfpga/clock_manager.c  |   8 +
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |  48 ++
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  32 
 arch/arm/mach-socfpga/misc.c   |  12 ++
 arch/arm/mach-socfpga/mmu-arm64.c  |  71 +
 arch/arm/mach-socfpga/reset_manager.c  |  12 ++
 arch/arm/mach-socfpga/spl.c|  13 +-
 board/altera/stratix10-socdk/MAINTAINERS   |   7 +
 board/altera/stratix10-socdk/Makefile  |   7 +
 board/altera/stratix10-socdk/socfpga.c |   7 +
 configs/socfpga_stratix10_defconfig|  21 +++
 include/configs/socfpga_stratix10_socdk.h  | 166 +
 17 files changed, 498 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64.c
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 include/configs/socfpga_stratix10_socdk.h

--
2.2.2

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[U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

2016-10-13 Thread Chin Liang See

Separate the Clock Manager to support both GEN5 SoC and
Stratix 10 SoC.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
 arch/arm/mach-socfpga/clock_manager.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..0d67b3c 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,6 +10,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
@@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 
return clock;
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
 
 unsigned int cm_get_mmc_controller_clk_hz(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
uint32_t reg, clock = 0;
 
/* identify the source of MMC clock */
@@ -475,8 +478,12 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
/* further divide by 4 as we have fixed divider at wrapper */
clock /= 4;
return clock;
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+   return 2500;
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 unsigned int cm_get_qspi_controller_clk_hz(void)
 {
uint32_t reg, clock = 0;
@@ -556,3 +563,4 @@ U_BOOT_CMD(
"display clocks",
""
 );
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
2.2.2

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[U-Boot] [PATCH v3 01/12] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

2016-10-13 Thread Chin Liang See

Add base address header file for Stratix10 SoC

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
Acked-by: Marek Vasut <ma...@denx.de>
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++
 1 file changed, 48 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100644
index 000..cd29a59
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS   0xfa00
+#define SOCFPGA_EMAC0_ADDRESS  0xff80
+#define SOCFPGA_EMAC1_ADDRESS  0xff802000
+#define SOCFPGA_EMAC2_ADDRESS  0xff804000
+#define SOCFPGA_SDMMC_ADDRESS  0xff808000
+#define SOCFPGA_USB0_ADDRESS   0xffb0
+#define SOCFPGA_USB1_ADDRESS   0xffb4
+#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
+#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
+#define SOCFPGA_UART0_ADDRESS  0xffc02000
+#define SOCFPGA_UART1_ADDRESS  0xffc02100
+#define SOCFPGA_I2C0_ADDRESS   0xffc02800
+#define SOCFPGA_I2C1_ADDRESS   0xffc02900
+#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
+#define SOCFPGA_SYSTIMER1_ADDRESS  0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS  0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS  0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS  0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
+#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS  0xffe0
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
2.2.2

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[U-Boot] [PATCH v3 02/12] arm: socfpga: rstmgr: Add Reset Manager for Stratix 10

2016-10-13 Thread Chin Liang See

Add Reset Manager registers structure for Stratix 10 SoC

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
Acked-by: Marek Vasut <ma...@denx.de>
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 32 ++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..1f868da 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,11 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+struct socfpga_reset_manager {
+   u32 status;
+   u32 mpu_rst_stat;
+   u32 misc_stat;
+   u32 padding1;
+   u32 hdsk_en;
+   u32 hdsk_req;
+   u32 hdsk_ack;
+   u32 hdsk_stall;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in S10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
+   u32 brg_mod_reset;
+   u32 padding2;
+   u32 cold_mod_reset;
+   u32 padding3;
+   u32 dbg_mod_reset;
+   u32 tap_mod_reset;
+   u32 padding4;
+   u32 padding5;
+   u32 brg_warm_mask;
+   u32 padding6[3];
+   u32 tst_stat;
+   u32 padding7;
+   u32 hdsk_timeout;
+   u32 mpul2flushtimeout;
+   u32 dbghdsktimeout;
+};
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
 #else
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#define RSTMGR_MPUMODRST_CORE0 1
 #endif
 
 /*
-- 
2.2.2

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[U-Boot] [PATCH v3 00/12] Add support for Stratix 10 SoC

2016-10-13 Thread Chin Liang See

Add support for Stratix 10 SoC which is ARM64 based. This series
of patches are tested with Stratix 10 SOC Virtual Platform that
is available today.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
Cc: Ley Foon Tan <lf...@altera.com>
Cc: Tien Fong Chee <tfc...@altera.com>
---
Chin Liang See (12):
  arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address
  arm: socfpga: rstmgr: Add Reset Manager for Stratix 10
  arm: socfpga: rstmgr: Separate the Reset Manager for Stratix 10
  arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10
  arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10
  arm: socfpga: misc: Separate the misc.c for Stratix 10
  arm: socfpga: sysmgr: Disable System Manager for Stratix 10
  arm: socfpga: mmu: Add memory map layout for Stratix 10 SoC
  arm: socfpga: stratix10: Add board directory for Stratix 10 socdk
  arm: dts: socfpga: Add dts for Stratix 10 socdk
  arm: socfpga: Add SPL support for Stratix 10 SoC
  arm: socfpga: Add support for Stratix 10 SoC dev kit

 arch/arm/Kconfig   |   4 +-
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts   |  71 +
 arch/arm/mach-socfpga/Kconfig  |  10 ++
 arch/arm/mach-socfpga/Makefile |  13 +-
 arch/arm/mach-socfpga/clock_manager.c  |   8 +
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |  48 ++
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  32 
 arch/arm/mach-socfpga/misc.c   |  12 ++
 arch/arm/mach-socfpga/mmu-arm64.c  |  71 +
 arch/arm/mach-socfpga/reset_manager.c  |  12 ++
 arch/arm/mach-socfpga/spl.c|  13 +-
 board/altera/stratix10-socdk/MAINTAINERS   |   7 +
 board/altera/stratix10-socdk/Makefile  |   7 +
 board/altera/stratix10-socdk/socfpga.c |   7 +
 configs/socfpga_stratix10_defconfig|  21 +++
 include/configs/socfpga_stratix10_socdk.h  | 166 +
 17 files changed, 498 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64.c
 create mode 100644 board/altera/stratix10-socdk/MAINTAINERS
 create mode 100644 board/altera/stratix10-socdk/Makefile
 create mode 100644 board/altera/stratix10-socdk/socfpga.c
 create mode 100644 configs/socfpga_stratix10_defconfig
 create mode 100644 include/configs/socfpga_stratix10_socdk.h

--
2.2.2

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Re: [U-Boot] [RFC 4/4] arm: socfpga: scrub the SDRAM to properly enable ECC support

2016-10-12 Thread Chin Liang See

On Mon, 2016-10-10 at 10:52 -0500, Dinh Nguyen wrote:
> From: Dinh Nguyen 
> 
> In order for SDRAM ECC to work correctly, the SDRAM needs to get
> zero'd which
> enables the ECC bit. By using the PL330 DMA to fill the SDRAM with
> zeroes,
> the operation is completed in ~1.2 seconds, versus ~14 seconds with a
> memset.
> 
> Signed-off-by: Dinh Nguyen 
> ---
>  arch/arm/mach-socfpga/include/mach/reset_manager.h | 21
> 
>  arch/arm/mach-socfpga/include/mach/sdram.h |  2 ++
>  arch/arm/mach-socfpga/spl.c|  8 +++
>  arch/arm/mach-socfpga/wrap_sdram_config.c  | 28
> ++
>  configs/socfpga_cyclone5_defconfig |  2 ++
>  5 files changed, 61 insertions(+)
> 

[..]

> diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c
> b/arch/arm/mach-socfpga/wrap_sdram_config.c
> index 31cc7de..dfa6423 100644
> --- a/arch/arm/mach-socfpga/wrap_sdram_config.c
> +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
> @@ -5,8 +5,10 @@
>   */
>  
>  #include 
> +#include 
>  #include 
>  #include 
> +#include 
>  
>  /* Board-specific header. */
>  #include 
> @@ -310,3 +312,29 @@ const struct socfpga_sdram_misc_config
> *socfpga_get_sdram_misc_config(void)
>  {
>   return _config;
>  }
> +
> +#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN == 1)
> +/* init the whole SDRAM ECC bit */
> +void sdram_ecc_init(void)
> +{
> + struct pl330_transfer_struct pl330;
> + u8 pl330_buf[2000];

Would need size of 2500 if the SDRAM size is 2GB

Thanks
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Re: [U-Boot] [RFC 2/4] dma: Kconfig: Add CONFIG_PL330_DMA entry

2016-10-12 Thread Chin Liang See

On Mon, 2016-10-10 at 10:52 -0500, Dinh Nguyen wrote:
> From: Dinh Nguyen <dingu...@opensource.altera.com>
> 
> Add PL330_DMA entry.
> 
> Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
> ---
>  drivers/dma/Kconfig  | 4 
>  drivers/dma/Makefile | 1 +
>  2 files changed, 5 insertions(+)
> 

Reviewed-by: Chin Liang See <cl...@altera.com>

Thanks
Chin Liang
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Re: [U-Boot] [RFC 1/4] drivers: dma: Add the ARM PL330 DMA driver

2016-10-12 Thread Chin Liang See

On Mon, 2016-10-10 at 10:52 -0500, Dinh Nguyen wrote:
> From: Dinh Nguyen 
> 
> Adopted from the Linux kernel PL330 DMA driver.
> 
> Signed-off-by: Dinh Nguyen 
> ---
>  arch/arm/include/asm/pl330.h | 105 +
>  drivers/dma/pl330.c  | 942
> +++
>  2 files changed, 1047 insertions(+)
>  create mode 100644 arch/arm/include/asm/pl330.h
>  create mode 100644 drivers/dma/pl330.c
> 
> diff --git a/arch/arm/include/asm/pl330.h
> b/arch/arm/include/asm/pl330.h
> new file mode 100644
> index 000..dd19b4c
> --- /dev/null
> +++ b/arch/arm/include/asm/pl330.h
> @@ -0,0 +1,105 @@
> +/*
> + * Copyright (C) 2010 Samsung Electronics Co. Ltd.
> + *   Jaswinder Singh 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + *
> + * adapted from linux kernel pl330.h
> + */
> +
> +#ifndef  __PL330_H_
> +#define  __PL330_H_
> +
> +#define PL330_STATE_STOPPED  (1 << 0)
> +#define PL330_STATE_EXECUTING(1 << 1)
> +#define PL330_STATE_WFE  (1 << 2)
> +#define PL330_STATE_FAULTING (1 << 3)
> +#define PL330_STATE_COMPLETING   (1 << 4)
> +#define PL330_STATE_WFP  (1 << 5)
> +#define PL330_STATE_KILLING  (1 << 6)
> +#define PL330_STATE_FAULT_COMPLETING (1 << 7)
> +#define PL330_STATE_CACHEMISS(1 << 8)
> +#define PL330_STATE_UPDTPC   (1 << 9)
> +#define PL330_STATE_ATBARRIER(1 << 10)
> +#define PL330_STATE_QUEUEBUSY(1 << 11)
> +#define PL330_STATE_INVALID  (1 << 15)
> +
> +#define PL330_DMA_MAX_BURST_SIZE 3
> +

Not sure this is true for other platform. If not, this would need goto
include/configs header files.

[..]

> 
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
> new file mode 100644
> index 000..a97cd9f
> --- /dev/null
> +++ b/drivers/dma/pl330.c
> @@ -0,0 +1,942 @@
> +/*
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *   http://www.samsung.com
> + *
> + * Copyright (C) 2010 Samsung Electronics Co. Ltd.
> + *   Jaswinder Singh 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> 

[..]

> +
> +static inline u32 _state(struct pl330_transfer_struct *pl330)
> +{
> + void __iomem *regs = pl330->reg_base;
> + u32 val;
> +
> + val = readl(regs + CS(pl330->channel_num)) & 0xf;
> +
> + udelay(1);
> +
> + switch (val) {
> + case DS_ST_STOP:
> + return PL330_STATE_STOPPED;
> + case DS_ST_EXEC:
> + return PL330_STATE_EXECUTING;
> + case DS_ST_CMISS:
> + return PL330_STATE_CACHEMISS;
> + case DS_ST_UPDTPC:
> + return PL330_STATE_UPDTPC;
> + case DS_ST_WFE:
> + return PL330_STATE_WFE;
> + case DS_ST_FAULT:
> + return PL330_STATE_FAULTING;
> + case DS_ST_ATBRR:
> + return PL330_STATE_ATBARRIER;

This state and below would yield difference between channel and
manager.

[..]

> 
> +/*
> + * DMA transfer setup (DMA_SUPPORTS_MEM_TO_MEM,
> DMA_SUPPORTS_MEM_TO_DEV or
> + DMA_SUPPORTS_DEV_TO_MEM)
> + * For Peripheral transfer, the FIFO threshold value is expected at
> + * 2 ^ pl330->brst_size * pl330->brst_len.
> + * Return:   1 for error or not successful
> + *
> + * channel_num   -   channel number assigned, valid from 0
> to 7
> + * src_addr  -   address to transfer from / source
> + * dst_addr  -   address to transfer to / destination
> + * len   -   number of bytes to be transferred
> + * brst_size -   valid from 0 - 3
> + *   where 0 = 1 (2 ^ 0) bytes and 3 = 8 bytes
> (2 ^ 3)
> + * single_brst_size -single transfer size (from 0 - 3)
> + * brst_len  -   valid from 1 - 16 where each burst can
> trasfer 1 - 16
> + *   data chunk (each chunk size equivalent to
> brst_size)
> + * peripheral_id assigned peripheral_id, valid from 0 to 31
> + * transfer_type DMA_SUPPORTS_MEM_TO_MEM,
> DMA_SUPPORTS_MEM_TO_DEV or
> + *   DMA_SUPPORTS_DEV_TO_MEM
> + * buf_size  -   sizeof(buf)
> + * buf   -   buffer handler which will point to
> the memory
> + *   allocated for dma microcode
> + */
> +static int pl330_transfer_setup(struct pl330_transfer_struct *pl330)
> +{
> + /* Variable declaration */
> + int off = 0;/* buffer offset clear
> to 0 */
> + int ret = 0;
> + unsigned loopjmp0, loopjmp1;/* for DMALPEND */
> + unsigned lcnt0 = 0; /* loop count 0 */
> + unsigned lcnt1 = 0; /* loop count 1 */
> + unsigned burst_size = 0;
> + unsigned len = pl330->len;
> + u32 ccr = 0;/* Channel Control
> Register */
> + struct pl330_reqcfg

Re: [U-Boot] [PATCH] spi: Add support for MX66U51235F, MX66L1G45G and MT25QU02G

2016-10-12 Thread Chin Liang See

On Wed, 2016-10-12 at 09:15 -0500, dumitru.bac...@intel.com wrote:
> From: Radu Bacrau <dumitru.bac...@intel.com>
> 
> This commit adds support for the Macronix MX66U51235F, MX66L1G45G and
> Micron MT25QU02G flash parts.
> 
> Signed-off-by: Radu Bacrau <dumitru.bac...@intel.com>
> Cc: Chin Liang See <cl...@altera.com>
> Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> Cc: Jagan Teki <jt...@openedev.com>
> Cc: Radu Bacrau <radu.bac...@gmail.com>
> ---
>  drivers/mtd/spi/sf_params.c | 3 +++
>  1 file changed, 3 insertions(+)
> 

Reviewed-by: Chin Liang See <cl...@altera.com>

Thanks
Chin Liang
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Re: [U-Boot] [PATCH] doc: socfpga: Update README.socfpga for Preloader development flow

2016-09-22 Thread Chin Liang See

On Wed, 2016-09-21 at 11:59 +0200, Marek Vasut wrote:
> On 09/21/2016 04:35 AM, Chin Liang See wrote:
> > Update documentation to include the Cyclone V SoC Preloader
> > development flow. This include the update of Preloader handoff
> > through qts-filter.sh script. At same time, removed the SDMMC
> > documentation as its using DM now.
> 
> Good stuff . s/folder/directory/ , this is not windows.

haha sound like a habit using windows term :)

> 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > ---
> >  doc/README.socfpga | 69 +++---
> > 
> >  1 file changed, 29 insertions(+), 40 deletions(-)
> > 
> > diff --git a/doc/README.socfpga b/doc/README.socfpga
> > index cfcbbfe..04c5c0e 100644
> > --- a/doc/README.socfpga
> > +++ b/doc/README.socfpga
> > @@ -9,45 +9,34 @@ www.altera.com.
> 
> [...]
> 
> > +1. Please refer to SOCEDS documentation on generating handoff for
> > Preloader
> > +   Upon successful generation, there will be a folder
> > "software/preloader" at
>   ^^
> > +   the directory of your Qsys project.
> > +
> > +2. Then, you need to invoke qts-filter.sh at arch/arm/mach-socfpga
> > folder to
> > +   process the generated handoff files into Preloader source code.
> > +   $ sh arch/arm/mach-socfpga/qts-filter.sh   > directory> \
> > + /software/preloader>  > handoff files>
> > +
> > +   Example:
> > +
> > +   $ cd 
> > +   $ sh arch/arm/mach-socfpga/qts-filter.sh cyclone5 \
> > + /hardware/cv_soc_devkit_ghrd/ \
> > + /hardware/cv_soc_devkit_ghrd/software/preloader/ \
> > + board/altera/cyclone5-socdk/qts/
> 
> You should be explicit that these are two separate examples , one for
> CV
> and the other one for AV .

Sure, always to good to explain in detailed

> 
> > +   $ cd 
> > +   $ sh arch/arm/mach-socfpga/qts-filter.sh arria5 \
> > + /hardware/av_soc_devkit_ghrd/ \
> > + /hardware/av_soc_devkit_ghrd/software/preloader/
> > + board/altera/arria5-socdk/qts/
> > +
> > +3. Build the Preloader + U-Boot
> 
> It's called U-Boot SPL , not preloader .

Will fix

> 
> > +   $ export CROSS_COMPILE=arm-altera-eabi-
> > +   $ make mrproper
> > +   $ make socfpga_cyclone5_defconfig
> > +   $ make
> 
> It's worth mentioning the generated u-boot-with-spl.sfp and how to
> install it onto a card (mention partitioning layout) and into QSPI
> NOR (just write the binary at the beginning). Regarding QSPI NOR, it
> might be worth mentioning quartus_hps, see :
> https://rocketboards.org/foswiki/view/Documentation/GSRD131QspiProgra
> m
> 

Sure, I will add more as I just received email to explain these steps
:)

Thanks
Chin Liang

> 
> 
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[U-Boot] [PATCH] doc: socfpga: Update README.socfpga for Preloader development flow

2016-09-21 Thread Chin Liang See

Update documentation to include the Cyclone V SoC Preloader
development flow. This include the update of Preloader handoff
through qts-filter.sh script. At same time, removed the SDMMC
documentation as its using DM now.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
 doc/README.socfpga | 69 +++---
 1 file changed, 29 insertions(+), 40 deletions(-)

diff --git a/doc/README.socfpga b/doc/README.socfpga
index cfcbbfe..04c5c0e 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -9,45 +9,34 @@ www.altera.com.
 
 
 
-socfpga_dw_mmc
+Working with Cyclone V SoC Preloader
 
-Here are macro and detailed configuration required to enable DesignWare SDMMC
-controller support within SOCFPGA
 
-#define CONFIG_MMC
--> To enable the SD MMC framework support
-
-#define CONFIG_SDMMC_BASE  (SOCFPGA_SDMMC_ADDRESS)
--> The base address of CSR register for DesignWare SDMMC controller
-
-#define CONFIG_GENERIC_MMC
--> Enable the generic MMC driver
-
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT   256
--> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
-
-#define CONFIG_DWMMC
--> Enable the common DesignWare SDMMC controller framework
-
-#define CONFIG_SOCFPGA_DWMMC
--> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
-
-#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH1024
--> The FIFO depth for SOCFPGA DesignWare SDMMC controller
-
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL3
--> Phase-shifted clock of sdmmc_clk for controller to drive command and data to
-the card to meet hold time requirements. SD clock is running at 50MHz and
-drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time
-is 135 / 360 * 20ns = 7.5ns.
-
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL0
--> Phase-shifted clock of sdmmc_clk used to sample the command and data from
-the card
-
-#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4
--> Bus width of data line which either 1, 4 or 8 and based on board routing.
-
-#define CONFIG_SOCFPGA_DWMMC_BUS_HZ5000
--> The clock rate to controller. Do note the controller have a wrapper which
-divide the clock from PLL by 4.
+1. Please refer to SOCEDS documentation on generating handoff for Preloader
+   Upon successful generation, there will be a folder "software/preloader" at
+   the directory of your Qsys project.
+
+2. Then, you need to invoke qts-filter.sh at arch/arm/mach-socfpga folder to
+   process the generated handoff files into Preloader source code.
+   $ sh arch/arm/mach-socfpga/qts-filter.sh   \
+ /software/preloader> 
+
+   Example:
+
+   $ cd 
+   $ sh arch/arm/mach-socfpga/qts-filter.sh cyclone5 \
+ /hardware/cv_soc_devkit_ghrd/ \
+ /hardware/cv_soc_devkit_ghrd/software/preloader/ \
+ board/altera/cyclone5-socdk/qts/
+
+   $ cd 
+   $ sh arch/arm/mach-socfpga/qts-filter.sh arria5 \
+ /hardware/av_soc_devkit_ghrd/ \
+ /hardware/av_soc_devkit_ghrd/software/preloader/
+ board/altera/arria5-socdk/qts/
+
+3. Build the Preloader + U-Boot
+   $ export CROSS_COMPILE=arm-altera-eabi-
+   $ make mrproper
+   $ make socfpga_cyclone5_defconfig
+   $ make
-- 
2.2.2

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[U-Boot] [PATCH v3 8/9] arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-20 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v3
- Add macro for all boards to avoid ifdef
---
 board/terasic/de0-nano-soc/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h 
b/board/terasic/de0-nano-soc/qts/sdram_config.h
index 7084797..d96b28a 100644
--- a/board/terasic/de0-nano-soc/qts/sdram_config.h
+++ b/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -42,6 +42,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH   8
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK   3
 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA  0
-- 
2.2.2

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[U-Boot] [PATCH v3 9/9] arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-20 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v3
- Add macro for all boards to avoid ifdef
---
 board/terasic/sockit/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/terasic/sockit/qts/sdram_config.h 
b/board/terasic/sockit/qts/sdram_config.h
index 769aa77..9906436 100644
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
-- 
2.2.2

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[U-Boot] [PATCH v3 7/9] arm: socfpga: sr1500: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-20 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v3
- Add macro for all boards to avoid ifdef
---
 board/sr1500/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
index edbaf89..83b8a35 100644
--- a/board/sr1500/qts/sdram_config.h
+++ b/board/sr1500/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP5
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
-- 
2.2.2

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[U-Boot] [PATCH v3 6/9] arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-20 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v3
- Add macro for all boards to avoid ifdef
---
 board/samtec/vining_fpga/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/samtec/vining_fpga/qts/sdram_config.h 
b/board/samtec/vining_fpga/qts/sdram_config.h
index 74cb405..372e8bc 100644
--- a/board/samtec/vining_fpga/qts/sdram_config.h
+++ b/board/samtec/vining_fpga/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT200
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-- 
2.2.2

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[U-Boot] [PATCH v3 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-20 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v3
- Add macro for all boards to avoid ifdef
---
 board/altera/arria5-socdk/qts/sdram_config.h   | 3 +++
 board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/board/altera/arria5-socdk/qts/sdram_config.h 
b/board/altera/arria5-socdk/qts/sdram_config.h
index e9fe60f..2589f3f 100644
--- a/board/altera/arria5-socdk/qts/sdram_config.h
+++ b/board/altera/arria5-socdk/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h 
b/board/altera/cyclone5-socdk/qts/sdram_config.h
index 37c1476..8f3ddce 100644
--- a/board/altera/cyclone5-socdk/qts/sdram_config.h
+++ b/board/altera/cyclone5-socdk/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-- 
2.2.2

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[U-Boot] [PATCH v3 4/9] arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-20 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v3
- Add macro for all boards to avoid ifdef
---
 board/ebv/socrates/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/ebv/socrates/qts/sdram_config.h 
b/board/ebv/socrates/qts/sdram_config.h
index cf9d1d3..b4872c2 100644
--- a/board/ebv/socrates/qts/sdram_config.h
+++ b/board/ebv/socrates/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-- 
2.2.2

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[U-Boot] [PATCH v3 5/9] arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-20 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v3
- Add macro for all boards to avoid ifdef
---
 board/is1/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
index 67ea1ec..8ce3c70 100644
--- a/board/is1/qts/sdram_config.h
+++ b/board/is1/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
-- 
2.2.2

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[U-Boot] [PATCH v3 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-20 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v3
- Add macro for all boards to avoid ifdef
---
 board/denx/mcvevk/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/denx/mcvevk/qts/sdram_config.h 
b/board/denx/mcvevk/qts/sdram_config.h
index 30c4d7d..ff64f55 100644
--- a/board/denx/mcvevk/qts/sdram_config.h
+++ b/board/denx/mcvevk/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP5
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-- 
2.2.2

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[U-Boot] [PATCH v3 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-20 Thread Chin Liang See

To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v3
- Removed ifdef by setting macro to zeroes for all boards
Changes for v2
- Removed v1 patches #2 to #9 as no boards are using LPDDR2
---
 arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
 arch/arm/mach-socfpga/qts-filter.sh| 2 +-
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 7 +++
 drivers/ddr/altera/sdram.c | 3 +++
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index f12bb84..b11228f 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
u32 dram_timing4;   /* 0x10 */
u32 lowpwr_timing;
u32 dram_odt;
-   u32 __padding0[4];
+   u32 extratime1;
+   u32 __padding0[3];
u32 dram_addrw; /* 0x2c */
u32 dram_if_width;  /* 0x30 */
u32 dram_dev_width;
@@ -88,6 +89,7 @@ struct socfpga_sdram_config {
u32 dram_timing4;
u32 lowpwr_timing;
u32 dram_odt;
+   u32 extratime1;
u32 dram_addrw;
u32 dram_if_width;
u32 dram_dev_width;
@@ -427,6 +429,10 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK 
\
 /* Field instance: sdr::ctrlgrp::dramsts   */
 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x0008
 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x0004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28

 /* SDRAM width macro for configuration with ECC */
 #define SDRAM_WIDTH_32BIT_WITH_ECC 40
diff --git a/arch/arm/mach-socfpga/qts-filter.sh 
b/arch/arm/mach-socfpga/qts-filter.sh
index 050d6ba..1148a71 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -119,7 +119,7 @@ EOF
 # Filter out only the macros which are actually used by the code
 #
 grep_sdram_config() {
-   egrep "#define 
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CO!

NFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP!
 |CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_POR
TCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEI

Re: [U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-20 Thread Chin Liang See

On Wed, 2016-09-21 at 03:20 +0200, Marek Vasut wrote:
> On 09/20/2016 08:05 AM, Chin Liang See wrote:
> > To enable configuration of sdr.ctrlcfg.extratime1 register which
> > enable
> > extra clocks for read to write command timing. This is critical to
> > ensure successful LPDDR2 interface
> > 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > ---
> > Changes for v2
> > - Removed v1 patches #2 to #9 as no boards are using LPDDR2
> > ---
> >  arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
> >  arch/arm/mach-socfpga/qts-filter.sh| 2 +-
> >  arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +
> >  drivers/ddr/altera/sdram.c | 3 +++
> >  4 files changed, 20 insertions(+), 2 deletions(-)
> > [...]
> 
> I'd really like to avoid the ifdef, can we do that (fix all boards to
> set the register to zero) ? Otherwise I'm fine with the patch.
> 

Ok I know where you come from. ifdef will cause some test challenge in
term of coverage. In this case, let me fix all boards to zeroes.

Thanks
Chin Liang

> 
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Re: [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-20 Thread Chin Liang See

On Tue, 2016-09-20 at 09:52 +0200, Marek Vasut wrote:
> On 09/20/2016 07:37 AM, Chin Liang See wrote:
> > On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote:
> > > On 09/19/2016 12:12 PM, Chin Liang See wrote:
> > > > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> > > > > On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > > > > > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > > > > > required for stabil LPDDR2 operation
> > > > > 
> > > > > ... stable ...
> > > > > 
> > > > > Isn't SoCDK using DDR3 DRAM ?
> > > > 
> > > > Yah, you are right where we won't need this patch and others
> > > > except
> > > > #1
> > > > one. Should I send v2 which only have first patch?
> > > 
> > > Then should this register be set to zero on SoCDK ?
> > 
> > Not required as the default value is zero.
> 
> OK, if we can avoid the ifdef(s)
> 

Removing the ifdef would requiring the patch against all socfpga
boards. As commented by you earlier, all our boards are using DDR3 and
this patch for LPDDR2 would not applicable then.

Thanks
Chin Liang
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[U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-20 Thread Chin Liang See

To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
Changes for v2
- Removed v1 patches #2 to #9 as no boards are using LPDDR2
---
 arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
 arch/arm/mach-socfpga/qts-filter.sh| 2 +-
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +
 drivers/ddr/altera/sdram.c | 3 +++
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index f12bb84..b11228f 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
u32 dram_timing4;   /* 0x10 */
u32 lowpwr_timing;
u32 dram_odt;
-   u32 __padding0[4];
+   u32 extratime1;
+   u32 __padding0[3];
u32 dram_addrw; /* 0x2c */
u32 dram_if_width;  /* 0x30 */
u32 dram_dev_width;
@@ -88,6 +89,7 @@ struct socfpga_sdram_config {
u32 dram_timing4;
u32 lowpwr_timing;
u32 dram_odt;
+   u32 extratime1;
u32 dram_addrw;
u32 dram_if_width;
u32 dram_dev_width;
@@ -427,6 +429,10 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK 
\
 /* Field instance: sdr::ctrlgrp::dramsts   */
 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x0008
 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x0004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28

 /* SDRAM width macro for configuration with ECC */
 #define SDRAM_WIDTH_32BIT_WITH_ECC 40
diff --git a/arch/arm/mach-socfpga/qts-filter.sh 
b/arch/arm/mach-socfpga/qts-filter.sh
index 050d6ba..1148a71 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -119,7 +119,7 @@ EOF
 # Filter out only the macros which are actually used by the code
 #
 grep_sdram_config() {
-   egrep "#define 
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CO!

NFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP!
 |CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_POR
TCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CT

Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Chin Liang See

On Mon, 2016-09-19 at 20:54 +0200, Marek Vasut wrote:
> On 09/19/2016 12:11 PM, Chin Liang See wrote:
> > On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote:
> > > On 09/15/2016 09:26 AM, Chin Liang See wrote:
> > > > To enable configuration of sdr.ctrlcfg.extratime1 register
> > > > which
> > > > enable
> > > > extra clocks for read to write command timing. This is critical
> > > > to
> > > > ensure successful LPDDR2 interface
> > > > 
> > > > Signed-off-by: Chin Liang See <cl...@altera.com>
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
> > > >  arch/arm/mach-socfpga/qts-filter.sh| 2 +-
> > > >  arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +
> > > >  drivers/ddr/altera/sdram.c | 3 +++
> > > >  4 files changed, 20 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > index f12bb84..b11228f 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > @@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
> > > > u32 dram_timing4;   /* 0x10 */
> > > > u32 lowpwr_timing;
> > > > u32 dram_odt;
> > > > -   u32 __padding0[4];
> > > > +   u32 extratime1;
> > > > +   u32 __padding0[3];
> > > > u32 dram_addrw; /* 0x2c */
> > > > u32 dram_if_width;  /* 0x30 */
> > > > u32 dram_dev_width;
> > > > @@ -88,6 +89,7 @@ struct socfpga_sdram_config {
> > > > u32 dram_timing4;
> > > > u32 lowpwr_timing;
> > > > u32 dram_odt;
> > > > +   u32 extratime1;
> > > > u32 dram_addrw;
> > > > u32 dram_if_width;
> > > > u32 dram_dev_width;
> > > 
> > > This seems to be changing the DRAM register layout, is this
> > > really
> > > correct and was this really tested on AV SoCDK ?
> > 
> > Previously its treated unused register as default value is good
> > enough.
> > But this not true anymore for LPDDR2 and we are exposing extratime1
> > register.
> 
> I mean the later one , which adds an entry and moves the other
> registers
> by 4 bytes.

Oh you referring to socfpga_sdram_config. That structure is used to
store the handoff value. The address of register is actually pointed by
structure socfpga_sdr_ctrl.

> 
> > While for testing, I tested both CV and AV SoCDK few times as I
> > also
> > worried even they are using DDR3 instead LPDDR2.
> 
> Yes, they do, it's in the documentation ;-)

Oh actually I meant that this patch should not impact existing boards
which are using DDR3.

Thanks
Chin Liang

> 
> > > 
> > > [...]
> > > 
> > > > diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c
> > > > b/arch/arm/mach-socfpga/wrap_sdram_config.c
> > > > index 31cc7de..d72f5e1 100644
> > > > --- a/arch/arm/mach-socfpga/wrap_sdram_config.c
> > > > +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
> > > > @@ -81,6 +81,15 @@ static const struct socfpga_sdram_config
> > > > sdram_config = {
> > > > SDR_CTRLGRP_DRAMODT_READ_LSB)   
> > > > |
> > > > (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
> > > > SDR_CTRLGRP_DRAMODT_WRITE_LSB),
> > > > +#ifdef
> > > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR
> > > 
> > > How come this is not always defined for all boards ?
> > 
> > This is to ensure it still works if users are using older SOCEDS
> > instead of SOCEDS 16.1. Besides that, this is only applicable for
> > LPDDR2. With that, patches #2 to #9 are not needed.
> > 
> > Thanks
> > Chin Liang
> > 
> > > 
> > > > +   .extratime1 =
> > > > +   (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_R
> > > > D_TO
> > > > _WR <<
> > > > +   SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)
> > > > |
> > > > +   (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_R
> > >

Re: [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote:
> On 09/19/2016 12:12 PM, Chin Liang See wrote:
> > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> > > On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > > > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > > > required for stabil LPDDR2 operation
> > > 
> > > ... stable ...
> > > 
> > > Isn't SoCDK using DDR3 DRAM ?
> > 
> > Yah, you are right where we won't need this patch and others except
> > #1
> > one. Should I send v2 which only have first patch?
> 
> Then should this register be set to zero on SoCDK ?

Not required as the default value is zero.

Thanks
Chin Liang

> 
> 
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Re: [U-Boot] [PATCH 4/9] arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > required for stabil LPDDR2 operation
> 
> Same comment as 2/9 applies to the rest


Yup, we just need 1/9.

Thanks
Chin Liang


> 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > ---
> >  board/ebv/socrates/qts/sdram_config.h | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/board/ebv/socrates/qts/sdram_config.h
> > b/board/ebv/socrates/qts/sdram_config.h
> > index cf9d1d3..a0cad51 100644
> > --- a/board/ebv/socrates/qts/sdram_config.h
> > +++ b/board/ebv/socrates/qts/sdram_config.h
> > @@ -49,6 +49,9 @@
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
> > 4
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 
> > 3
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
> > 512
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C
> > HIP 2
> >  #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 
> > 0
> >  #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
> > 0
> >  #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 
> > 0x0
> > 
> 
> 
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Re: [U-Boot] [PATCH 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > required for stabil LPDDR2 operation
> 
> Same comment as 2/9

Yup, this patch is not required.

Thanks
Chin Liang

> 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > ---
> >  board/denx/mcvevk/qts/sdram_config.h | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/board/denx/mcvevk/qts/sdram_config.h
> > b/board/denx/mcvevk/qts/sdram_config.h
> > index 30c4d7d..0328850 100644
> > --- a/board/denx/mcvevk/qts/sdram_config.h
> > +++ b/board/denx/mcvevk/qts/sdram_config.h
> > @@ -49,6 +49,9 @@
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
> > 5
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 
> > 3
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
> > 512
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C
> > HIP 2
> >  #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 
> > 0
> >  #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
> > 0
> >  #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 
> > 0x0
> > 
> 
> 
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Re: [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > required for stabil LPDDR2 operation
> 
> ... stable ...
> 
> Isn't SoCDK using DDR3 DRAM ?

Yah, you are right where we won't need this patch and others except #1
one. Should I send v2 which only have first patch?

Thanks
Chin Liang

> 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > ---
> >  board/altera/arria5-socdk/qts/sdram_config.h   | 3 +++
> >  board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++
> >  2 files changed, 6 insertions(+)
> > 
> > diff --git a/board/altera/arria5-socdk/qts/sdram_config.h
> > b/board/altera/arria5-socdk/qts/sdram_config.h
> > index e9fe60f..8964637 100644
> > --- a/board/altera/arria5-socdk/qts/sdram_config.h
> > +++ b/board/altera/arria5-socdk/qts/sdram_config.h
> > @@ -49,6 +49,9 @@
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
> > 4
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 
> > 3
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
> > 512
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C
> > HIP 2
> >  #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 
> > 0
> >  #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
> > 0
> >  #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 
> > 0
> > diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h
> > b/board/altera/cyclone5-socdk/qts/sdram_config.h
> > index 37c1476..1bc6f6f 100644
> > --- a/board/altera/cyclone5-socdk/qts/sdram_config.h
> > +++ b/board/altera/cyclone5-socdk/qts/sdram_config.h
> > @@ -49,6 +49,9 @@
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
> > 3
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 
> > 3
> >  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
> > 512
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
> > +#define
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C
> > HIP 2
> >  #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 
> > 0
> >  #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
> > 0
> >  #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 
> > 0
> > 
> 
> 
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Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Chin Liang See

On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote:
> On 09/15/2016 09:26 AM, Chin Liang See wrote:
> > To enable configuration of sdr.ctrlcfg.extratime1 register which
> > enable
> > extra clocks for read to write command timing. This is critical to
> > ensure successful LPDDR2 interface
> > 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > ---
> >  arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
> >  arch/arm/mach-socfpga/qts-filter.sh| 2 +-
> >  arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +
> >  drivers/ddr/altera/sdram.c | 3 +++
> >  4 files changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > index f12bb84..b11228f 100644
> > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > @@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
> > u32 dram_timing4;   /* 0x10 */
> > u32 lowpwr_timing;
> > u32 dram_odt;
> > -   u32 __padding0[4];
> > +   u32 extratime1;
> > +   u32 __padding0[3];
> > u32 dram_addrw; /* 0x2c */
> > u32 dram_if_width;  /* 0x30 */
> > u32 dram_dev_width;
> > @@ -88,6 +89,7 @@ struct socfpga_sdram_config {
> > u32 dram_timing4;
> > u32 lowpwr_timing;
> > u32 dram_odt;
> > +   u32 extratime1;
> > u32 dram_addrw;
> > u32 dram_if_width;
> > u32 dram_dev_width;
> 
> This seems to be changing the DRAM register layout, is this really
> correct and was this really tested on AV SoCDK ?

Previously its treated unused register as default value is good enough.
But this not true anymore for LPDDR2 and we are exposing extratime1
register.

While for testing, I tested both CV and AV SoCDK few times as I also
worried even they are using DDR3 instead LPDDR2.

> 
> [...]
> 
> > diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c
> > b/arch/arm/mach-socfpga/wrap_sdram_config.c
> > index 31cc7de..d72f5e1 100644
> > --- a/arch/arm/mach-socfpga/wrap_sdram_config.c
> > +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
> > @@ -81,6 +81,15 @@ static const struct socfpga_sdram_config
> > sdram_config = {
> > SDR_CTRLGRP_DRAMODT_READ_LSB)   
> > |
> > (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
> > SDR_CTRLGRP_DRAMODT_WRITE_LSB),
> > +#ifdef
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR
> 
> How come this is not always defined for all boards ?

This is to ensure it still works if users are using older SOCEDS
instead of SOCEDS 16.1. Besides that, this is only applicable for
LPDDR2. With that, patches #2 to #9 are not needed.

Thanks
Chin Liang

> 
> > +   .extratime1 =
> > +   (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO
> > _WR <<
> > +   SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)
> > |
> > +   (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO
> > _WR_BC <<
> > +   SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) 
> > |
> > +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF
> > _CHIP <<
> > +   SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
> > +#endif
> > .dram_addrw =
> > (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
> > SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)  
> > |
> > diff --git a/drivers/ddr/altera/sdram.c
> > b/drivers/ddr/altera/sdram.c
> > index 7e4606d..e74c5b0 100644
> > --- a/drivers/ddr/altera/sdram.c
> > +++ b/drivers/ddr/altera/sdram.c
> > @@ -418,6 +418,9 @@ static void sdr_load_regs(const struct
> > socfpga_sdram_config *cfg)
> >  
> > debug("Configuring DRAMODT\n");
> > writel(cfg->dram_odt, _ctrl->dram_odt);
> > +
> > +   debug("Configuring EXTRATIME1\n");
> > +   writel(cfg->extratime1, _ctrl->extratime1);
> >  }
> >  
> >  /**
> > 
> 
> 
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[U-Boot] [PATCH 7/9] arm: socfpga: sr1500: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <cl...@altera.com>
---
 board/sr1500/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
index edbaf89..4bb5aec 100644
--- a/board/sr1500/qts/sdram_config.h
+++ b/board/sr1500/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP5
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 
2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
-- 
2.2.2

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[U-Boot] [PATCH 9/9] arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <cl...@altera.com>
---
 board/terasic/sockit/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/terasic/sockit/qts/sdram_config.h 
b/board/terasic/sockit/qts/sdram_config.h
index 769aa77..5fa202f 100644
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 
2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
-- 
2.2.2

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[U-Boot] [PATCH 8/9] arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <cl...@altera.com>
---
 board/terasic/de0-nano-soc/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h 
b/board/terasic/de0-nano-soc/qts/sdram_config.h
index 7084797..75aecda 100644
--- a/board/terasic/de0-nano-soc/qts/sdram_config.h
+++ b/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -33,6 +33,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 
2
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES   0
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS   10
-- 
2.2.2

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[U-Boot] [PATCH 6/9] arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <cl...@altera.com>
---
 board/samtec/vining_fpga/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/samtec/vining_fpga/qts/sdram_config.h 
b/board/samtec/vining_fpga/qts/sdram_config.h
index 74cb405..4230066 100644
--- a/board/samtec/vining_fpga/qts/sdram_config.h
+++ b/board/samtec/vining_fpga/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT200
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 
2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-- 
2.2.2

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[U-Boot] [PATCH 5/9] arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <cl...@altera.com>
---
 board/is1/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
index 67ea1ec..aad7dce 100644
--- a/board/is1/qts/sdram_config.h
+++ b/board/is1/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 
2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
-- 
2.2.2

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[U-Boot] [PATCH 4/9] arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <cl...@altera.com>
---
 board/ebv/socrates/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/ebv/socrates/qts/sdram_config.h 
b/board/ebv/socrates/qts/sdram_config.h
index cf9d1d3..a0cad51 100644
--- a/board/ebv/socrates/qts/sdram_config.h
+++ b/board/ebv/socrates/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 
2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-- 
2.2.2

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[U-Boot] [PATCH 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <cl...@altera.com>
---
 board/denx/mcvevk/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/denx/mcvevk/qts/sdram_config.h 
b/board/denx/mcvevk/qts/sdram_config.h
index 30c4d7d..0328850 100644
--- a/board/denx/mcvevk/qts/sdram_config.h
+++ b/board/denx/mcvevk/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP5
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 
2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-- 
2.2.2

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[U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

2016-09-19 Thread Chin Liang See

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <cl...@altera.com>
---
 board/altera/arria5-socdk/qts/sdram_config.h   | 3 +++
 board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/board/altera/arria5-socdk/qts/sdram_config.h 
b/board/altera/arria5-socdk/qts/sdram_config.h
index e9fe60f..8964637 100644
--- a/board/altera/arria5-socdk/qts/sdram_config.h
+++ b/board/altera/arria5-socdk/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 
2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h 
b/board/altera/cyclone5-socdk/qts/sdram_config.h
index 37c1476..1bc6f6f 100644
--- a/board/altera/cyclone5-socdk/qts/sdram_config.h
+++ b/board/altera/cyclone5-socdk/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 
2
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-- 
2.2.2

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[U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Chin Liang See

To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See <cl...@altera.com>
---
 arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
 arch/arm/mach-socfpga/qts-filter.sh| 2 +-
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 9 +
 drivers/ddr/altera/sdram.c | 3 +++
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index f12bb84..b11228f 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
u32 dram_timing4;   /* 0x10 */
u32 lowpwr_timing;
u32 dram_odt;
-   u32 __padding0[4];
+   u32 extratime1;
+   u32 __padding0[3];
u32 dram_addrw; /* 0x2c */
u32 dram_if_width;  /* 0x30 */
u32 dram_dev_width;
@@ -88,6 +89,7 @@ struct socfpga_sdram_config {
u32 dram_timing4;
u32 lowpwr_timing;
u32 dram_odt;
+   u32 extratime1;
u32 dram_addrw;
u32 dram_if_width;
u32 dram_dev_width;
@@ -427,6 +429,10 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK 
\
 /* Field instance: sdr::ctrlgrp::dramsts   */
 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x0008
 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x0004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
 
 /* SDRAM width macro for configuration with ECC */
 #define SDRAM_WIDTH_32BIT_WITH_ECC 40
diff --git a/arch/arm/mach-socfpga/qts-filter.sh 
b/arch/arm/mach-socfpga/qts-filter.sh
index 050d6ba..1148a71 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -119,7 +119,7 @@ EOF
 # Filter out only the macros which are actually used by the code
 #
 grep_sdram_config() {
-   egrep "#define 
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CO!
 
NFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP!
 |CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_POR
TCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRE

Re: [U-Boot] [PATCH v2 01/11] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

2016-09-07 Thread Chin Liang See

On Tue, 2016-09-06 at 09:29 -0500, Dinh Nguyen wrote:
> 
> On 09/06/2016 05:03 AM, Chin Liang See wrote:
> > Add base address header file for Stratix10 SoC
> > 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > Cc: Ley Foon Tan <lf...@altera.com>
> > Acked-by: Marek Vasut <ma...@denx.de>
> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48
> > ++
> >  1 file changed, 48 insertions(+)
> >  create mode 100755 arch/arm/mach
> > -socfpga/include/mach/base_addr_s10.h
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > new file mode 100755
> 
> Shouldn't this be 644?

Good catch as seems my editor is using this mode when creating new
files. Will chmod and fix it

Thanks
Chin Liang

> 
> Dinh
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Re: [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit

2016-09-07 Thread Chin Liang See

On Tue, 2016-09-06 at 14:15 +0200, Marek Vasut wrote:
> On 09/06/2016 11:18 AM, Chin Liang See wrote:
> > On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:
> > > On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > > > Add support for Stratix 10 SoC development kit
> > > >
> > > > Signed-off-by: Chin Liang See <cl...@altera.com>
> > > > Cc: Marek Vasut <ma...@denx.de>
> > > > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > > > Cc: Ley Foon Tan <lf...@altera.com>
> > > > ---
> > > >  arch/arm/Kconfig  |   7 +-
> > > >  arch/arm/mach-socfpga/Kconfig |  10 +++
> > > >  configs/socfpga_stratix10_defconfig   |  14 
> > > >  include/configs/socfpga_stratix10_socdk.h | 135
> > > > ++
> > > >  4 files changed, 163 insertions(+), 3 deletions(-)
> > > >  create mode 100755 configs/socfpga_stratix10_defconfig
> > > >  create mode 100644 include/configs/socfpga_stratix10_socdk.h
> > > >
> > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > > index aef901c..c8e8767 100644
> > > > --- a/arch/arm/Kconfig
> > > > +++ b/arch/arm/Kconfig
> > > > @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
> > > >
> > > >  config ARCH_SOCFPGA
> > > > bool "Altera SOCFPGA family"
> > > > -   select CPU_V7
> > > > -   select SUPPORT_SPL
> > > > +   select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
> > > > +   select ARM64 if TARGET_SOCFPGA_STRATIX10
> > > > +   select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10
> > > > select OF_CONTROL
> > > > -   select SPL_OF_CONTROL
> > > > +   select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
> > >
> > > Why is the SPL disabled ?
> >
> > We will be having SPL for Stratix 10. It will added in later days
> > as
> > SPL main function is for DDR setup. This is not needed for SOC
> > Virtual
> > Platform now.
>
> Please do things right from the start, add the SPL and skip the DRAM
> init if it's not needed.

That is my next to do list as I am enabling the Stratix 10 by phases.
In this case, I shall repost this series once getting SPL available.

Thanks
Chin Liang

>
> > > > select DM
> > > > select DM_SPI_FLASH
> > > > select DM_SPI
> > > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach
> > > > -socfpga/Kconfig
> > > > index 1a43c7b..4e3b238 100644
> > > > --- a/arch/arm/mach-socfpga/Kconfig
> > > > +++ b/arch/arm/mach-socfpga/Kconfig
> > > > @@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5
> > > >  config TARGET_SOCFPGA_GEN5
> > > > bool
> > > >
> > > > +config TARGET_SOCFPGA_STRATIX10
> > > > +   bool
> > > > +
> > > >  choice
> > > > prompt "Altera SOCFPGA board select"
> > > > optional
> > > > @@ -51,6 +54,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
> > > > bool "Terasic SoCkit (Cyclone V)"
> > > > select TARGET_SOCFPGA_CYCLONE5
> > > >
> > > > +config TARGET_SOCFPGA_STRATIX10_SOCDK
> > > > +   bool "Altera SOCFPGA SoCDK (Stratix 10)"
> > > > +   select TARGET_SOCFPGA_STRATIX10
> > > > +
> > > >  endchoice
> > > >
> > > >  config SYS_BOARD
> > > > @@ -63,6 +70,7 @@ config SYS_BOARD
> > > > default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
> > > > default "sr1500" if TARGET_SOCFPGA_SR1500
> > > > default "vining_fpga" if
> > > > TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> > > > +   default "stratix10-socdk" if
> > > > TARGET_SOCFPGA_STRATIX10_SOCDK
> > >
> > > Keep all the lists sorted .
> >
> > Noted, will fix this.
> >
> > >
> > > >  config SYS_VENDOR
> > > > default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
> > > > @@ -72,6 +80,7 @@ config SYS_VENDOR
> > > > default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> > > > default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
> > > > default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
> > > > +   default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
> > > >
> > > >  config SYS_SOC
> > > > default "socfpga"
> > > > @@ -86,5 +95,6 @@ config SYS_CONFIG_NAME
> > > > default "socfpga_socrates" if
> > > > TARGET_SOCFPGA_EBV_SOCRATES
> > > > default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
> > > > default "socfpga_vining_fpga" if
> > > > TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> > > > +   default "socfpga_stratix10_socdk" if
> > > > TARGET_SOCFPGA_STRATIX10_SOCDK
> > > >
> > > >  endif
> > >
> > > [...]
> > >
> > > btw. what about Arria 10 ? Will it ever land ?
> > > And will I ever get a kit ? :)
> >
> > Since S10 is good, I will help out the A10 upstreaming once S10 is
> > intergrated. While for dev kit, let me work that out as we have A10
> > dev
> > kit with production silicon :)
>
> The production silicon a10 is still not available ?
>
> > Thanks
> > Chin Liang
> >
> > >
>
>
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Re: [U-Boot] [PATCH v2 09/11] arm: socfpga: stratix10: Add board directory for Stratix 10 socdk

2016-09-07 Thread Chin Liang See

On Tue, 2016-09-06 at 09:30 -0500, Dinh Nguyen wrote:
> 
> On 09/06/2016 05:03 AM, Chin Liang See wrote:
> > Add board folder for Stratix 10 SoC development kit
> > 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > Cc: Ley Foon Tan <lf...@altera.com>
> > ---
> >  board/altera/stratix10-socdk/MAINTAINERS | 7 +++
> >  board/altera/stratix10-socdk/Makefile| 7 +++
> >  board/altera/stratix10-socdk/socfpga.c   | 7 +++
> >  3 files changed, 21 insertions(+)
> >  create mode 100755 board/altera/stratix10-socdk/MAINTAINERS
> >  create mode 100755 board/altera/stratix10-socdk/Makefile
> >  create mode 100755 board/altera/stratix10-socdk/socfpga.c
> > 
> > diff --git a/board/altera/stratix10-socdk/MAINTAINERS
> > b/board/altera/stratix10-socdk/MAINTAINERS
> > new file mode 100755
> 
> 644?

Will chmod 

> 
> > index 000..596933c
> > --- /dev/null
> > +++ b/board/altera/stratix10-socdk/MAINTAINERS
> > @@ -0,0 +1,7 @@
> > +SOCFPGA BOARD
> > +M: Chin-Liang See <cl...@altera.com>
> > +M: Dinh Nguyen <dingu...@opensource.altera.com>
> > +S: Maintained
> > +F: board/altera/stratix10-socdk/
> > +F: include/configs/socfpga_stratix10_socdk.h
> > +F: configs/socfpga_stratix10_defconfig
> > diff --git a/board/altera/stratix10-socdk/Makefile
> > b/board/altera/stratix10-socdk/Makefile
> > new file mode 100755
> 
> 644?
> 

Will chmod too

Thanks
Chin Liang

> Dinh
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Re: [U-Boot] [PATCH v2 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit

2016-09-07 Thread Chin Liang See

On Tue, 2016-09-06 at 09:32 -0500, Dinh Nguyen wrote:
> 
> On 09/06/2016 05:03 AM, Chin Liang See wrote:
> > Add support for Stratix 10 SoC development kit
> > 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > Cc: Ley Foon Tan <lf...@altera.com>
> > ---
> > Changes for v2
> > - Sorting the config alphabetically
> > ---
> 
> Please re-check all of your new file attributes for this series.
> 

Yup, definitely :)

Thanks
Chin Liang

> Dinh
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Re: [U-Boot] [PATCH v2 10/11] arm: dts: socfpga: Add dts for Stratix 10 socdk

2016-09-07 Thread Chin Liang See

On Tue, 2016-09-06 at 09:14 -0500, Dinh Nguyen wrote:
> 
> On 09/06/2016 05:03 AM, Chin Liang See wrote:
> > Add device tree for Stratix 10 SoC development kit
> > 
> > Signed-off-by: Chin Liang See <cl...@altera.com>
> > Cc: Marek Vasut <ma...@denx.de>
> > Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> > Cc: Ley Foon Tan <lf...@altera.com>
> > Acked-by: Marek Vasut <ma...@denx.de>
> > ---
> >  arch/arm/dts/Makefile|  3 +-
> >  arch/arm/dts/socfpga_stratix10_socdk.dts | 63
> > 
> >  2 files changed, 65 insertions(+), 1 deletion(-)
> >  create mode 100755 arch/arm/dts/socfpga_stratix10_socdk.dts
> > 
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 223124e..c5e2d3c 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -127,7 +127,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
> > \
> > socfpga_cyclone5_sockit.dtb \
> > socfpga_cyclone5_socrates.dtb   \
> > socfpga_cyclone5_sr1500.dtb \
> > -   socfpga_cyclone5_vining_fpga.dtb
> > +   socfpga_cyclone5_vining_fpga.dtb\
> > +   socfpga_stratix10_socdk.dtb
> >  
> >  dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
> >  dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
> > diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
> > b/arch/arm/dts/socfpga_stratix10_socdk.dts
> > new file mode 100755
> > index 000..7465358
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> > @@ -0,0 +1,63 @@
> > +/*
> > + *  Copyright (C) 2016 Intel Corporation
> > + *
> > + * SPDX-License-Identifier:GPL-2.0
> > + */
> > +
> > +/dts-v1/;
> > +/* First 4KB has trampoline code for secondary cores. */
> > +/memreserve/ 0x 0x0001000;
> 
> ARM64 should be using PSCI for SMP. I don't think the trampoline code
> is
> needed.
> 

You are right and will remove this

> > +#include "skeleton.dtsi"
> > +
> > +/ {
> > +   model = "Altera SOCFPGA Stratix 10 SoC Development Kit";
> > +   compatible = "altr,socfpga-stratix10", "altr,socfpga";
> > +
> > +   #address-cells = <1>;
> > +   #size-cells = <1>;
> > +
> > +   chosen {
> > +   bootargs = "console=ttyS0,115200";
> > +   };
> > +
> > +   memory {
> > +   name = "memory";
> > +   device_type = "memory";
> > +   reg = <0x0 0x4000>; /* 1GB */
> > +   };
> 
> are you sure we still have only 1GB?
> 

Good catch as SOCVP has 2GB. But we should have more than 2GB per spec
and will investigate more.

> > +
> > +   regulator_3_3v: 3-3-v-regulator {
> > +   compatible = "regulator-fixed";
> > +   regulator-name = "3.3V";
> > +   regulator-min-microvolt = <330>;
> > +   regulator-max-microvolt = <330>;
> > +   };
> > +
> > +   soc {
> > +   #address-cells = <1>;
> > +   #size-cells = <1>;
> > +   compatible = "simple-bus";
> > +   device_type = "soc";
> > +   ranges;
> > +
> > +   mmc0: dwmmc0@0xff808000 {
> > +   compatible = "altr,socfpga-dw-mshc";
> > +   reg = <0xff808000 0x1000>;
> > +   interrupts = <0 139 4>;
> 
> This interrupt number is not correct. Copy/paste error from Cyclone5?
> For S10, I think it's 96.
> 

Yup, my bad as overlook this when enabling the SDMMC. Will fix this.

Thanks
Chin Liang

> > +   num-slots = <1>;
> > +   broken-cd;
> > +   bus-width = <4>;
> > +   fifo-depth = <0x400>;
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   cap-mmc-highspeed;
> > +   cap-sd-highspeed;
> > +   drvsel = <3>;
> > +   smplsel = <0>;
> > +   status = "okay";
> > +   u-boot,dm-pre-reloc;
> > +   vmmc-supply = <_3_3v>;
> > +   vqmmc-supply = <_3_3v>;
> > +   };
> > +   };
> > +};
> > 
> 
> Dinh
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