[U-Boot] [PATCH v3] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
To add the Cadence SPI driver support for Altera SOCFPGA. It
required information such as clocks and timing from platform's
configuration header file within include/configs folder
Signed-off-by: Chin Liang See
Cc: Jagan Teki
Cc: Gerhard Sittig
---
Changes for v3
- Moved the documentation from doc folder to driver
- Documented down macro specific to driver only
Changes for v2
- Combine driver into single C file instead of 2
- Added documentation on the macro used
- Using structure for registers instead of macro
---
drivers/spi/Makefile |1 +
drivers/spi/cadence_qspi.c | 1018
drivers/spi/cadence_qspi.h | 196 +
3 files changed, 1215 insertions(+)
create mode 100644 drivers/spi/cadence_qspi.c
create mode 100644 drivers/spi/cadence_qspi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ed4ecd7..b8d56ea 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
new file mode 100644
index 000..4712b45
--- /dev/null
+++ b/drivers/spi/cadence_qspi.c
@@ -0,0 +1,1018 @@
+/*
+ * (C) Copyright 2014 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "cadence_qspi.h"
+
+static int qspi_is_init;
+static unsigned int qspi_calibrated_hz;
+static unsigned int qspi_calibrated_cs;
+
+static const struct cadence_qspi *cadence_qspi_base = (void *)QSPI_BASE;
+
+#define to_cadence_qspi_slave(s) \
+ container_of(s, struct cadence_qspi_slave, slave)
+
+#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
+ tdelay_ns) - (tsclk_ns)) / (tref_ns)))
+
+#define CQSPI_GET_WR_SRAM_LEVEL() \
+ ((readl(&cadence_qspi_base->sramfill) >>\
+ CQSPI_REG_SRAMLEVEL_WR_LSB) & CQSPI_REG_SRAMLEVEL_WR_MASK)
+
+static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
+ unsigned int addr_width)
+{
+ unsigned int addr;
+
+ addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
+
+ if (addr_width == 4)
+ addr = (addr << 8) | addr_buf[3];
+
+ return addr;
+}
+
+static void cadence_qspi_apb_read_fifo_data(void *dest,
+ const void *src_ahb_addr, unsigned int bytes)
+{
+ unsigned int temp;
+ int remaining = bytes;
+ unsigned int *dest_ptr = (unsigned int *)dest;
+ unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
+
+ while (remaining > 0) {
+ if (remaining >= CQSPI_FIFO_WIDTH) {
+ *dest_ptr = readl(src_ptr);
+ remaining -= CQSPI_FIFO_WIDTH;
+ } else {
+ /* dangling bytes */
+ temp = readl(src_ptr);
+ memcpy(dest_ptr, &temp, remaining);
+ break;
+ }
+ dest_ptr++;
+ }
+
+ return;
+}
+
+static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
+ const void *src, unsigned int bytes)
+{
+ unsigned int temp;
+ int remaining = bytes;
+ unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
+ unsigned int *src_ptr = (unsigned int *)src;
+
+ while (remaining > 0) {
+ if (remaining >= CQSPI_FIFO_WIDTH) {
+ writel(*src_ptr, dest_ptr);
+ remaining -= sizeof(unsigned int);
+ } else {
+ /* dangling bytes */
+ memcpy(&temp, src_ptr, remaining);
+ writel(temp, dest_ptr);
+ break;
+ }
+ src_ptr++;
+ }
+
+ return;
+}
+
+/* Read from SRAM FIFO with polling SRAM fill level. */
+static int qspi_read_sram_fifo_poll(void *dest_addr,
+ const void *src_addr, unsigned int num_bytes)
+{
+ unsigned int remaining = num_bytes;
+ unsigned int retry;
+ unsigned int sram_level = 0;
+ unsigned char *dest = (unsigned char *)dest_addr;
+
+ while (remaining > 0) {
+ retry = CQSPI_REG_RETRY;
+ while (retry--) {
+ sram_level = (readl(&cadence_qspi_base->sramfill) >>
+ CQSPI_REG_SRAMLEVEL_RD_LSB) &
+ CQSPI_REG_SRAMLEVEL_RD_MASK;
+ if (sram_level)
+
Re: [U-Boot] [OT] CC:s in commits (was: [PATCH 1/2] socfpga: Adding Scan Manager driver)
Dear Albert, On Mon, 2014-01-13 at 09:34 +0100, ZY - albert.u.boot wrote: > On Wed, 13 Nov 2013 11:34:10 -0600, Chin Liang See > wrote: > > > Scan Manager driver will be called to configure the IOCSR > > scan chain. This configuration will setup the IO buffer settings > > > > Signed-off-by: Chin Liang See > > Cc: Dinh Nguyen > > Cc: Wolfgang Denk > > CC: Pavel Machek > > Cc: Tom Rini > > Cc: Albert Aribaud > > --- > > Not sure what the point is of these CC:s in the commit message. Do I > miss some use of these? Can I, should I, should I not remove them > from the commit when applying to my tree? > Actually these Cc will be helpful when using git send-email. It will auto cc to these mailing list when the patch is send out for review (instead entering the names manually every time). Thanks Chin Liang > Amicalement, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [OT] CC:s in commits (was: [PATCH 1/2] socfpga: Adding Scan Manager driver)
Hi Albert, On Mon, 2014-01-13 at 17:39 +0100, ZY - albert.u.boot wrote: > Hi Chin, > > On Mon, 13 Jan 2014 08:34:36 -0600, Chin Liang See > wrote: > > > Dear Albert, > > > > On Mon, 2014-01-13 at 09:34 +0100, ZY - albert.u.boot wrote: > > > On Wed, 13 Nov 2013 11:34:10 -0600, Chin Liang See > > > wrote: > > > > > > > Scan Manager driver will be called to configure the IOCSR > > > > scan chain. This configuration will setup the IO buffer settings > > > > > > > > Signed-off-by: Chin Liang See > > > > Cc: Dinh Nguyen > > > > Cc: Wolfgang Denk > > > > CC: Pavel Machek > > > > Cc: Tom Rini > > > > Cc: Albert Aribaud > > > > --- > > > > > > Not sure what the point is of these CC:s in the commit message. Do I > > > miss some use of these? Can I, should I, should I not remove them > > > from the commit when applying to my tree? > > > > > > > Actually these Cc will be helpful when using git send-email. It will > > auto cc to these mailing list when the patch is send out for review > > (instead entering the names manually every time). Thanks > > That is useful to the sender, but useless to anyone else. > > Aren't patman's Series-CC tags fulfilling the same function without > cluttering the commit message on the receiving/applying end? The patman script looks cool. Let me learn up this and using this when submitting future patches. At same time, sorry for the hassle as I am not aware the git send-email method not helpful for maintainer. For this patch, wonder is it ok for you to manually remove the Ccs? Thanks and appreciate again for your helps. Chin Liang > > > Chin Liang > > Amicalement, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [OT] CC:s in commits (was: [PATCH 1/2] socfpga: Adding Scan Manager driver)
Dear Wolfgang, On Mon, 2014-01-13 at 22:09 +0100, ZY - wd wrote: > Dear Chin Liang See, > > In message <1389634896.9425.4.ca...@clsee-virtualbox.altera.com> you wrote: > > > > The patman script looks cool. Let me learn up this and using this when > > submitting future patches. At same time, sorry for the hassle as I am > > not aware the git send-email method not helpful for maintainer. For this > > patch, wonder is it ok for you to manually remove the Ccs? Thanks and > > appreciate again for your helps. > > Patman and the Cc: in the commit message may overlap, but they may > also include different lists of addresses. For documentation > purposes, the Cc in the commit message are useful and should be kept. > Just my $ 0.02 ... > Thanks for the explanation. It definitely worth more than 2 cents. :) Chin Liang > Best regards, > > Wolfgang Denk > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [OT] CC:s in commits (was: [PATCH 1/2] socfpga: Adding Scan Manager driver)
Dear Albert, On Mon, 2014-01-13 at 23:07 +0100, ZY - albert.u.boot wrote: > Hi Wolfgang, > > On Mon, 13 Jan 2014 22:08:15 +0100, Wolfgang Denk wrote: > > > Dear Albert, > > > > In message <20140113173924.684ce548@lilith> you wrote: > > > > > > > Actually these Cc will be helpful when using git send-email. It will > > > > auto cc to these mailing list when the patch is send out for review > > > > (instead entering the names manually every time). Thanks > > > > > > That is useful to the sender, but useless to anyone else. > > > > This is not correct. It is also an indicatioin who was explicitly > > addressed when the patch was submitted, so you can later still see > > from the commit message who was invited to commend and refrained from > > doing so. This may help a lot in discussions like "but I never had a > > chance to see this patch". > > > > Please keep these. The are really useful. > > Thanks Wolfgang. I hadn't considered this 'traceability' aspect -- I > haven't been involved in enough such discussions, obviously. > > Chin Liang See: apologies for the noise. No worries. We learned something today :) Chin Liang > > > Best regards, > > > > Wolfgang Denk > > Amicalement, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] designware_i2c: Enhance DesignWare I2C driver address support
Enhance the DesignWare I2C driver to support address length more
than 1 byte. This enhancement is required as some I2C slave
device such as EEPROM chip might have 16 bit address byte.
Signed-off-by: Chin Liang See
Cc: Alexey Brodkin
Cc: Tom Rini
cc: Armando Visconti
Cc: Stefan Roese
Cc: Albert ARIBAUD
Cc: Heiko Schocher
Cc: Vipin KUMAR
Cc: Tom Rix
Cc: Mischa Jonker
---
drivers/i2c/designware_i2c.c | 24 +---
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index cb2ac04..c0ac5f7 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -205,27 +205,21 @@ static int check_params(uint addr, int alen, uchar
*buffer, int len)
return 1;
}
- if (alen > 1) {
- printf("addr len %d not supported\n", alen);
- return 1;
- }
-
- if (addr + len > 256) {
- printf("address out of range\n");
- return 1;
- }
-
return 0;
}
-static int i2c_xfer_init(uchar chip, uint addr)
+static int i2c_xfer_init(uchar chip, uint addr, int alen)
{
if (i2c_wait_for_bb())
return 1;
i2c_setaddress(chip);
- writel(addr, &i2c_regs_p->ic_cmd_data);
-
+ while (alen) {
+ alen--;
+ /* high byte address going out first */
+ writel((addr >> (alen * 8)) & 0xff,
+ &i2c_regs_p->ic_cmd_data);
+ }
return 0;
}
@@ -269,7 +263,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar
*buffer, int len)
if (check_params(addr, alen, buffer, len))
return 1;
- if (i2c_xfer_init(chip, addr))
+ if (i2c_xfer_init(chip, addr, alen))
return 1;
start_time_rx = get_timer(0);
@@ -310,7 +304,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
if (check_params(addr, alen, buffer, len))
return 1;
- if (i2c_xfer_init(chip, addr))
+ if (i2c_xfer_init(chip, addr, alen))
return 1;
start_time_tx = get_timer(0);
--
1.7.9.5
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Re: [U-Boot] [PATCH] designware_i2c: Enhance DesignWare I2C driver address support
Hi Alexey,
On Wed, 2014-01-15 at 15:30 +, Alexey Brodkin wrote:
> On Wed, 2014-01-15 at 08:58 -0600, Chin Liang See wrote:
> > Enhance the DesignWare I2C driver to support address length more
> > than 1 byte. This enhancement is required as some I2C slave
> > device such as EEPROM chip might have 16 bit address byte.
> > diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
> > index cb2ac04..c0ac5f7 100644
> > --- a/drivers/i2c/designware_i2c.c
> > +++ b/drivers/i2c/designware_i2c.c
> > @@ -205,27 +205,21 @@ static int check_params(uint addr, int alen, uchar
> > *buffer, int len)
> > return 1;
> > }
> >
> > - if (alen > 1) {
> > - printf("addr len %d not supported\n", alen);
> > - return 1;
> > - }
> > -
> > - if (addr + len > 256) {
> > - printf("address out of range\n");
> > - return 1;
> > - }
> > -
> > return 0;
> > }
>
> Hi Chin,
>
> if you strip down functionality of "check_params()" to one single check
> I would recommend you to remove "check_params()" at all and do in-place
> check for "buffer" existence.
>
> Moreover you may just use "assert" for this check because this buffer is
> passed by u-boot (no need to check every parameter passed to any
> function in run-time) so in production/release build it won't exist at
> all.
Good suggestion. I agreed that we can strip off the check_params. Let me
send the v2 patch. Thanks and have a nice day!
Chin Liang
>
> Regards,
> Alexey
>
>
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[U-Boot] [PATCH v2] designware_i2c: Enhance DesignWare I2C driver address support
Enhance the DesignWare I2C driver to support address length more
than 1 byte. This enhancement is required as some I2C slave
device such as EEPROM chip might have 16 bit address byte.
Signed-off-by: Chin Liang See
Cc: Alexey Brodkin
Cc: Tom Rini
cc: Armando Visconti
Cc: Stefan Roese
Cc: Albert ARIBAUD
Cc: Heiko Schocher
Cc: Vipin KUMAR
Cc: Mischa Jonker
---
Changes for v2
- Removed the function check_params()
---
drivers/i2c/designware_i2c.c | 41 +
1 file changed, 9 insertions(+), 32 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index cb2ac04..5b8482a 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -197,35 +197,18 @@ static int i2c_wait_for_bb(void)
return 0;
}
-/* check parameters for i2c_read and i2c_write */
-static int check_params(uint addr, int alen, uchar *buffer, int len)
-{
- if (buffer == NULL) {
- printf("Buffer is invalid\n");
- return 1;
- }
-
- if (alen > 1) {
- printf("addr len %d not supported\n", alen);
- return 1;
- }
-
- if (addr + len > 256) {
- printf("address out of range\n");
- return 1;
- }
-
- return 0;
-}
-
-static int i2c_xfer_init(uchar chip, uint addr)
+static int i2c_xfer_init(uchar chip, uint addr, int alen)
{
if (i2c_wait_for_bb())
return 1;
i2c_setaddress(chip);
- writel(addr, &i2c_regs_p->ic_cmd_data);
-
+ while (alen) {
+ alen--;
+ /* high byte address going out first */
+ writel((addr >> (alen * 8)) & 0xff,
+ &i2c_regs_p->ic_cmd_data);
+ }
return 0;
}
@@ -266,10 +249,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar
*buffer, int len)
{
unsigned long start_time_rx;
- if (check_params(addr, alen, buffer, len))
- return 1;
-
- if (i2c_xfer_init(chip, addr))
+ if (i2c_xfer_init(chip, addr, alen))
return 1;
start_time_rx = get_timer(0);
@@ -307,10 +287,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
int nb = len;
unsigned long start_time_tx;
- if (check_params(addr, alen, buffer, len))
- return 1;
-
- if (i2c_xfer_init(chip, addr))
+ if (i2c_xfer_init(chip, addr, alen))
return 1;
start_time_tx = get_timer(0);
--
1.7.9.5
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Re: [U-Boot] [PATCH v2] designware_i2c: Enhance DesignWare I2C driver address support
Thanks Alexey. Hi Heiko, I believe this patch should be good for apply. Would need your help then. :) Thanks Chin Liang On Wed, 2014-01-15 at 15:51 +, Alexey Brodkin wrote: > On Wed, 2014-01-15 at 09:45 -0600, Chin Liang See wrote: > > Changes for v2 > > - Removed the function check_params() > > Ok, so you decided to not add "assert" check instead. > I think it's ok - it's not a requirement. Others don't do it as well so > let's leave it as it is. > > Acked-by: Alexey Brodkin > > Regards, > Alexey > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] designware_i2c: Enhance DesignWare I2C driver address support
Hi Heiko, On Thu, 2014-01-30 at 06:20 +0100, Heiko Schocher wrote: > Hello Chin, > > Am 22.01.2014 16:37, schrieb Chin Liang See: > > Thanks Alexey. > > > > Hi Heiko, > > > > I believe this patch should be good for apply. Would need your help > > then. :) Thanks > > > > Chin Liang > > > > > > On Wed, 2014-01-15 at 15:51 +0000, Alexey Brodkin wrote: > >> On Wed, 2014-01-15 at 09:45 -0600, Chin Liang See wrote: > >>> Changes for v2 > >>> - Removed the function check_params() > >> > >> Ok, so you decided to not add "assert" check instead. > >> I think it's ok - it's not a requirement. Others don't do it as well so > >> let's leave it as it is. > >> > >> Acked-by: Alexey Brodkin > >> > >> Regards, > >> Alexey > > Your patch apply not clean to current head > f889cc81c1572f4af0be950fd49bb6b67bc580fb > also checkpatch drops one warning: > Yup, it caused by a later patch. Let me re-base my patch. > CHECK: Alignment should match open parenthesis > #82: FILE: drivers/i2c/designware_i2c.c:210: > + writel((addr >> (alen * 8)) & 0xff, > + &i2c_regs_p->ic_cmd_data); > > total: 0 errors, 0 warnings, 1 checks, 64 lines checked I overlooked this as I saw no errors. Let me fix that too. Thanks again for your helps. Chin Liang > > Could you please fix this, thanks! > > bye, > Heiko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] designware_i2c: Enhance DesignWare I2C driver address support
Enhance the DesignWare I2C driver to support address length more
than 1 byte. This enhancement is required as some I2C slave
device such as EEPROM chip might have 16 bit address byte.
Signed-off-by: Chin Liang See
Acked-by: Alexey Brodkin
Cc: Tom Rini
cc: Armando Visconti
Cc: Stefan Roese
Cc: Albert ARIBAUD
Cc: Heiko Schocher
---
Changes for v3
- Re-based the patch to latest head
Changes for v2
- Removed the function check_params()
---
drivers/i2c/designware_i2c.c | 41 +
1 file changed, 9 insertions(+), 32 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 9ed9295..deea4f8 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -197,35 +197,18 @@ static int i2c_wait_for_bb(void)
return 0;
}
-/* check parameters for i2c_read and i2c_write */
-static int check_params(uint addr, int alen, uchar *buffer, int len)
-{
- if (buffer == NULL) {
- printf("Buffer is invalid\n");
- return 1;
- }
-
- if (alen > 1) {
- printf("addr len %d not supported\n", alen);
- return 1;
- }
-
- if (addr + len > 256) {
- printf("address out of range\n");
- return 1;
- }
-
- return 0;
-}
-
-static int i2c_xfer_init(uchar chip, uint addr)
+static int i2c_xfer_init(uchar chip, uint addr, int alen)
{
if (i2c_wait_for_bb())
return 1;
i2c_setaddress(chip);
- writel(addr, &i2c_regs_p->ic_cmd_data);
-
+ while (alen) {
+ alen--;
+ /* high byte address going out first */
+ writel((addr >> (alen * 8)) & 0xff,
+ &i2c_regs_p->ic_cmd_data);
+ }
return 0;
}
@@ -285,10 +268,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar
*buffer, int len)
addr);
#endif
- if (check_params(addr, alen, buffer, len))
- return 1;
-
- if (i2c_xfer_init(chip, addr))
+ if (i2c_xfer_init(chip, addr, alen))
return 1;
start_time_rx = get_timer(0);
@@ -345,10 +325,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
addr);
#endif
- if (check_params(addr, alen, buffer, len))
- return 1;
-
- if (i2c_xfer_init(chip, addr))
+ if (i2c_xfer_init(chip, addr, alen))
return 1;
start_time_tx = get_timer(0);
--
1.7.9.5
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Re: [U-Boot] [PATCH] watchdog/denali: Adding DesignWare watchdog driver support
Hi Albert,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
On Wed, 2013-12-18 at 16:23 -0600, Chin Liang See wrote:
> To add the DesignWare watchdog driver support. It required
> information such as register base address and clock info from
> configuration header file within include/configs folder.
>
> Signed-off-by: Chin Liang See
> Cc: Anatolij Gustschin
> Cc: Albert Aribaud
> Cc: Heiko Schocher
> Cc: Tom Rini
> ---
> drivers/watchdog/Makefile |1 +
> drivers/watchdog/designware_wdt.c | 75
> +
> 2 files changed, 76 insertions(+)
> create mode 100644 drivers/watchdog/designware_wdt.c
>
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index 06ced10..0276a10 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
> obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
> obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
> obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
> +obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
> diff --git a/drivers/watchdog/designware_wdt.c
> b/drivers/watchdog/designware_wdt.c
> new file mode 100644
> index 000..c3b14f5
> --- /dev/null
> +++ b/drivers/watchdog/designware_wdt.c
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright (C) 2013 Altera Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#define DW_WDT_CR0x00
> +#define DW_WDT_TORR 0x04
> +#define DW_WDT_CRR 0x0C
> +
> +#define DW_WDT_CR_EN_OFFSET 0x00
> +#define DW_WDT_CR_RMOD_OFFSET0x01
> +#define DW_WDT_CR_RMOD_VAL 0x00
> +#define DW_WDT_CRR_RESTART_VAL 0x76
> +
> +/*
> + * Set the watchdog time interval.
> + * Counter is 32 bit.
> + */
> +int designware_wdt_settimeout(unsigned int timeout)
> +{
> + signed int i;
> + /* calculate the timeout range value */
> + i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ))\
> + - 16;
> + if (i > 15)
> + i = 15;
> + if (i < 0)
> + i = 0;
> +
> + writel((i | (i<<4)),
> + (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
> + return 0;
> +}
> +
> +void designware_wdt_enable(void)
> +{
> + writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | \
> + (0x1 << DW_WDT_CR_EN_OFFSET)),
> + (CONFIG_DW_WDT_BASE + DW_WDT_CR));
> +}
> +
> +unsigned int designware_wdt_is_enabled(void)
> +{
> + unsigned long val;
> + val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
> + return val & 0x1;
> +}
> +
> +#if defined(CONFIG_HW_WATCHDOG)
> +void hw_watchdog_reset(void)
> +{
> + if (designware_wdt_is_enabled())
> + /* restart the watchdog counter */
> + writel(DW_WDT_CRR_RESTART_VAL,
> + (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
> +}
> +
> +void hw_watchdog_init(void)
> +{
> + /* reset to disable the watchdog */
> + hw_watchdog_reset();
> + /* set timer in miliseconds */
> + designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
> + /* enable the watchdog */
> + designware_wdt_enable();
> + /* reset the watchdog */
> + hw_watchdog_reset();
> +}
> +#endif
___
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U-Boot@lists.denx.de
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[U-Boot] [RESEND PATCH 1/2 v2] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
Signed-off-by: Chin Liang See
---
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 231
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 97
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
include/configs/socfpga_cyclone5.h |1 +
6 files changed, 335 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..4edc5d4 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..30cbb8b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(&scan_manager_base->stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
+ || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+
+ max_iter--;
+
+ if (max_iter > 0)
+ scanmgr_status = readl(&scan_manager_base->stat);
+ else
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
+ }
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
+}
+
+
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /* De-assert reinit if the IO scan chain is intended for HIO */
+ if (3 == io_scan_chain_id)
+ clrbits_le32(&freeze_controller_base->hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
+ != scan_mgr_io_scan_chain_engine_is_idle(
+ MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
+ return 1;
+ }
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits >>
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+ tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD <<
+ TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+ /* Program IO scan chain in 128-bit iteration */
+ for (i = 0; i < io_program_iter; i++) {
+
+ /* write TDI_TDO packet header to scan manager */
+ writel(tdi_tdo_header, &scan_manager_base->fifodoublebyte);
+
+ /* calculate array index */
+ index = i * 4;
+
+
[U-Boot] [RESEND PATCH 2/2 v2] socfpga: Adding Scan Manager IOCSR handoff files
The IOCSR handoff files will be consumed by Scan Manager driver.
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
Signed-off-by: Chin Liang See
---
Changes for v2
- rebase with latest v2014.01-rc1
---
board/altera/socfpga/iocsr_config.c | 653 +++
board/altera/socfpga/iocsr_config.h | 12 +
2 files changed, 665 insertions(+)
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/board/altera/socfpga/iocsr_config.c
b/board/altera/socfpga/iocsr_config.c
new file mode 100644
index 000..7e66ff8
--- /dev/null
+++ b/board/altera/socfpga/iocsr_config.c
@@ -0,0 +1,653 @@
+
+/* This file is generated by Preloader Generator */
+
+#include
+
+const unsigned long iocsr_scan_chain0_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+ 0x,
+ 0x,
+ 0x0FF0,
+ 0xC000,
+ 0x003F,
+ 0x8000,
+ 0x00020080,
+ 0x0802,
+ 0x0800,
+ 0x00018020,
+ 0x,
+ 0x4000,
+ 0x00010040,
+ 0x0401,
+ 0x0400,
+ 0x0010,
+ 0x4010,
+ 0x2000,
+ 0x0002,
+ 0x02008000,
+ 0x0200,
+ 0x0008,
+ 0x2008,
+ 0x1000,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+ 0x000C0300,
+ 0x1004,
+ 0x10C0,
+ 0x0040,
+ 0x00010040,
+ 0x8000,
+ 0x0008,
+ 0x1806,
+ 0x1800,
+ 0x0060,
+ 0x00018060,
+ 0x4000,
+ 0x00010040,
+ 0x1000,
+ 0x0400,
+ 0x0010,
+ 0x4010,
+ 0x2000,
+ 0x06008020,
+ 0x02008000,
+ 0x01FE,
+ 0xF800,
+ 0x0007,
+ 0x1000,
+ 0x4010,
+ 0x01004000,
+ 0x0100,
+ 0x3004,
+ 0x1004,
+ 0x0800,
+ 0x,
+ 0x,
+ 0x0080,
+ 0x0002,
+ 0x2000,
+ 0x0400,
+ 0x,
+ 0x00401000,
+ 0x0003,
+ 0x,
+ 0x,
+ 0x0200,
+ 0x00600802,
+ 0x,
+ 0x8020,
+ 0x8600,
+ 0x0200,
+ 0x0100,
+ 0x00300401,
+ 0xC0100400,
+ 0x4010,
+ 0x4300,
+ 0x000C0100,
+ 0x0080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+ 0x80040100,
+ 0x,
+ 0x0FF0,
+ 0x,
+ 0x0C010040,
+ 0x8000,
+ 0x18020080,
+ 0x,
+ 0x0800,
+ 0x00040020,
+ 0x06018060,
+ 0x4000,
+ 0x0C010040,
+ 0x0401,
+ 0x0030,
+ 0x,
+ 0x03004010,
+ 0x2000,
+ 0x06008020,
+ 0x02008000,
+ 0x0218,
+ 0x6008,
+ 0x01802008,
+ 0x1000,
+ 0x03004010,
+ 0x01004000,
+ 0x010C,
+ 0x3004,
+ 0x00C01004,
+ 0x0800,
+};
+
+const unsigned long iocsr_scan_chain3_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+ 0x2C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x0790,
+ 0x0802,
+ 0x0010,
+ 0x0A80,
+ 0x0790,
+ 0x0802,
+ 0x0010,
+ 0xC880,
+ 0x3001,
+ 0x00C00722,
+ 0x,
+ 0x0021,
+ 0x8204,
+ 0x0540,
+ 0x03C8,
+ 0x0401,
+ 0x0008,
+ 0x0540,
+ 0x03C8,
+ 0x0540,
+ 0x03C8,
+ 0xE440,
+ 0x1800,
+ 0x00600391,
+ 0x800E4400,
+ 0x0001,
+ 0x4002,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x7220,
+ 0x8C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C88,
+ 0x2300,
+ 0x0004,
+ 0x5067,
+ 0x0070,
+ 0x2459,
+ 0x1000,
+ 0xA034,
+ 0x0D01,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D,
+ 0x24906808,
+ 0x00A28340,
+ 0xD01A,
+ 0x06808A20,
+ 0x1004,
+ 0x0020,
+ 0x1004,
+ 0x0020,
+ 0x1500,
+ 0x0F20,
+ 0x1500,
+ 0x0F20,
+ 0x01FE,
+ 0x,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x,
+ 0x0A81,
+ 0x0790
Re: [U-Boot] [PATCH 1/2] socfpga: Adding Clock Manager driver
Hi Albert,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
On Wed, 2013-12-18 at 17:54 -0600, Chin Liang See wrote:
> Clock Manager driver will be called to reconfigure all the
> clocks setting based on user input. The input are passed to
> Preloader through handoff files
>
> Signed-off-by: Chin Liang See
> Cc: Albert Aribaud
> Cc: Tom Rini
> Cc: Wolfgang Denk
> CC: Pavel Machek
> Cc: Dinh Nguyen
> ---
> arch/arm/cpu/armv7/socfpga/Makefile|2 +-
> arch/arm/cpu/armv7/socfpga/clock_manager.c | 378
>
> arch/arm/cpu/armv7/socfpga/spl.c | 90 +
> arch/arm/include/asm/arch-socfpga/clock_manager.h | 205 +++
> .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
> include/configs/socfpga_cyclone5.h |1 +
> 6 files changed, 676 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/cpu/armv7/socfpga/clock_manager.c
> create mode 100644 arch/arm/include/asm/arch-socfpga/clock_manager.h
>
> diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
> b/arch/arm/cpu/armv7/socfpga/Makefile
> index 4edc5d4..eb33f2c 100644
> --- a/arch/arm/cpu/armv7/socfpga/Makefile
> +++ b/arch/arm/cpu/armv7/socfpga/Makefile
> @@ -8,5 +8,5 @@
> #
>
> obj-y:= lowlevel_init.o
> -obj-y+= misc.o timer.o reset_manager.o system_manager.o
> +obj-y+= misc.o timer.o reset_manager.o system_manager.o
> clock_manager.o
> obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
> diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
> b/arch/arm/cpu/armv7/socfpga/clock_manager.c
> new file mode 100644
> index 000..7caa76f
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
> @@ -0,0 +1,378 @@
> +/*
> + * Copyright (C) 2013 Altera Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +
> +static const struct socfpga_clock_manager *clock_manager_base =
> + (void *)SOCFPGA_CLKMGR_ADDRESS;
> +
> +#define CLKMGR_BYPASS_ENUM_ENABLE1
> +#define CLKMGR_BYPASS_ENUM_DISABLE 0
> +#define CLKMGR_STAT_BUSY_ENUM_IDLE 0x0
> +#define CLKMGR_STAT_BUSY_ENUM_BUSY 0x1
> +#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_EOSC10x0
> +#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_INPUT_MUX0x1
> +#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_EOSC10x0
> +#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_INPUT_MUX0x1
> +
> +#define CLEAR_BGP_EN_PWRDN \
> + (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
> + CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
> + CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
> +
> +#define VCO_EN_BASE \
> + (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
> + CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
> + CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
> +
> +static inline void cm_wait_for_lock(uint32_t mask)
> +{
> + register uint32_t inter_val;
> + do {
> + inter_val = readl(&clock_manager_base->inter) & mask;
> + } while (inter_val != mask);
> +}
> +
> +/* function to poll in the fsm busy bit */
> +static inline void cm_wait4fsm(void)
> +{
> + register uint32_t inter_val;
> + do {
> + inter_val = readl(&clock_manager_base->stat) &
> CLKMGR_STAT_BUSY_ENUM_BUSY;
> + } while (inter_val);
> +}
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +static inline void cm_write_bypass(uint32_t val)
> +{
> + writel(val, &clock_manager_base->bypass);
> + cm_wait4fsm();
> +}
> +
> +/* function to write the ctrl register which requires a poll of the busy bit
> */
> +static inline void cm_write_ctrl(uint32_t val)
> +{
> + writel(val, &clock_manager_base->ctrl);
> + cm_wait4fsm();
> +}
> +
> +/* function to write a clock register that has phase information */
> +static inline void cm_write_with_phase(uint32_t value,
> + uint32_t reg_address, uint32_t mask)
> +{
> + /* poll until phase is zero */
> + do {} while (readl(reg_address) & mask);
> +
> + writel(value, reg_address);
> +
> + do {} while (readl(reg_address) & mask);
> +}
> +
> +/*
> + * Setup clocks while making no assumptions of the
> + * previous state of the clocks.
> + *
> + * Start by being paranoid and gate all sw managed clocks
> + *
> + * Put all plls in bypass
> + *
> + * Put all plls VCO registers back to reset value (bgpwr dwn).
> + *
> + * Put peripheral and main pll src to reset value to avoid glit
Re: [U-Boot] [PATCH] nand/denali: Adding Denali NAND driver support
Hi Scott,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
On Wed, 2013-12-18 at 15:18 -0600, Chin Liang See wrote:
> To add the Denali NAND driver support into U-Boot. It required
> information such as register base address from configuration
> header file within include/configs folder.
>
> Signed-off-by: Chin Liang See
> Cc: Artem Bityutskiy
> Cc: David Woodhouse
> Cc: Brian Norris
> Cc: Scott Wood
> ---
> drivers/mtd/nand/Makefile |1 +
> drivers/mtd/nand/denali_nand.c | 1166
>
> drivers/mtd/nand/denali_nand.h | 501 +
> 3 files changed, 1668 insertions(+)
> create mode 100644 drivers/mtd/nand/denali_nand.c
> create mode 100644 drivers/mtd/nand/denali_nand.h
>
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 02b149c..24e8218 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -39,6 +39,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
> obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
> obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
> obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
> +obj-$(CONFIG_NAND_DENALI) += denali_nand.o
> obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
> obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
> obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
> diff --git a/drivers/mtd/nand/denali_nand.c b/drivers/mtd/nand/denali_nand.c
> new file mode 100644
> index 000..55246c9
> --- /dev/null
> +++ b/drivers/mtd/nand/denali_nand.c
> @@ -0,0 +1,1166 @@
> +/*
> + * Copyright (C) 2013 Altera Corporation
> + * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "denali_nand.h"
> +
> +/* We define a module parameter that allows the user to override
> + * the hardware and decide what timing mode should be used.
> + */
> +#define NAND_DEFAULT_TIMINGS -1
> +
> +static struct denali_nand_info denali;
> +static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
> +
> +/* We define a macro here that combines all interrupts this driver uses into
> + * a single constant value, for convenience. */
> +#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
> + INTR_STATUS__ECC_TRANSACTION_DONE | \
> + INTR_STATUS__ECC_ERR | \
> + INTR_STATUS__PROGRAM_FAIL | \
> + INTR_STATUS__LOAD_COMP | \
> + INTR_STATUS__PROGRAM_COMP | \
> + INTR_STATUS__TIME_OUT | \
> + INTR_STATUS__ERASE_FAIL | \
> + INTR_STATUS__RST_COMP | \
> + INTR_STATUS__ERASE_COMP | \
> + INTR_STATUS__ECC_UNCOR_ERR | \
> + INTR_STATUS__INT_ACT | \
> + INTR_STATUS__LOCKED_BLK)
> +
> +/* indicates whether or not the internal value for the flash bank is
> + * valid or not */
> +#define CHIP_SELECT_INVALID -1
> +
> +#define SUPPORT_8BITECC 1
> +
> +/* This macro divides two integers and rounds fractional values up
> + * to the nearest integer value. */
> +#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
> +
> +/* These constants are defined by the driver to enable common driver
> + * configuration options. */
> +#define SPARE_ACCESS 0x41
> +#define MAIN_ACCESS 0x42
> +#define MAIN_SPARE_ACCESS0x43
> +
> +#define DENALI_UNLOCK_START 0x10
> +#define DENALI_UNLOCK_END0x11
> +#define DENALI_LOCK 0x21
> +#define DENALI_LOCK_TIGHT0x31
> +#define DENALI_BUFFER_LOAD 0x60
> +#define DENALI_BUFFER_WRITE 0x62
> +
> +#define DENALI_READ 0
> +#define DENALI_WRITE 0x100
> +
> +/* types of device accesses. We can issue commands and get status */
> +#define COMMAND_CYCLE0
> +#define ADDR_CYCLE 1
> +#define STATUS_CYCLE 2
> +
> +/* this is a helper macro that allows us to
> + * format the bank into the proper bits for the controller */
> +#define BANK(x) ((x) << 24)
> +
> +/* Interrupts are cleared by writing a 1 to the appropriate status bit */
> +static inline void clear_interrupt(uint32_t irq_mask)
> +{
> + uint32_t intr_status_reg = 0;
> + intr_status_reg = INTR_STATUS(denali.flash_bank);
> + __raw_writel(irq_mask, denali.flash_reg + intr_status_reg);
> +}
> +
> +static uint32_t read_interrupt_status(void)
> +{
> + uint32_t intr_status_reg = 0;
> + intr_status_reg = INTR_STATUS(denali.flash_bank);
&g
Re: [U-Boot] [PATCH 2/2] socfpga: Adding Clock Manager handoff file
Hi Albert, As there are no further comments, would need your help to apply this patch. Thanks and appreciate for your support. Chin Liang On Wed, 2013-12-18 at 17:54 -0600, Chin Liang See wrote: > The pll_config.h will be consumed by Clock Manager driver > > Signed-off-by: Chin Liang See > Cc: Albert Aribaud > Cc: Tom Rini > Cc: Wolfgang Denk > CC: Pavel Machek > Cc: Dinh Nguyen > --- > board/altera/socfpga/pll_config.h | 115 > + > 1 file changed, 115 insertions(+) > create mode 100755 board/altera/socfpga/pll_config.h > > diff --git a/board/altera/socfpga/pll_config.h > b/board/altera/socfpga/pll_config.h > new file mode 100755 > index 000..32aa4ad > --- /dev/null > +++ b/board/altera/socfpga/pll_config.h > @@ -0,0 +1,115 @@ > + > +/* This file is generated by Preloader Generator */ > + > +#ifndef _PRELOADER_PLL_CONFIG_H_ > +#define _PRELOADER_PLL_CONFIG_H_ > + > +/* PLL configuration data */ > +/* Main PLL */ > +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) > +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) > +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) > +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT(0) > +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) > +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT(3) > +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) > +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12) > +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK(1) > +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK(1) > +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK(1) > +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK(1) > +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK(0) > +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) > +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) > +/* > + * To tell where is the clock source: > + * 0 = MAINPLL > + * 1 = PERIPHPLL > + */ > +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) > +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) > + > +/* Peripheral PLL */ > +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) > +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) > +/* > + * To tell where is the VCOs source: > + * 0 = EOSC1 > + * 1 = EOSC2 > + * 2 = F2S > + */ > +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC(0) > +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT(3) > +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT(3) > +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) > +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) > +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) > +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) > +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) > +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) > +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) > +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) > +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) > +/* > + * To tell where is the clock source: > + * 0 = F2S_PERIPH_REF_CLK > + * 1 = MAIN_CLK > + * 2 = PERIPH_CLK > + */ > +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) > +#define CONFIG_HPS_PERPLLGRP_SRC_NAND(2) > +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI(1) > + > +/* SDRAM PLL */ > +#ifdef CONFIG_SOCFPGA_ARRIA5 > +/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz > + * This if..else... is not required if generated by tools */ > +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) > +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127) > +#else > +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) > +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) > +#endif /* CONFIG_SOCFPGA_ARRIA5 */ > + > +/* > + * To tell where is the VCOs source: > + * 0 = EOSC1 > + * 1 = EOSC2 > + * 2 = F2S > + */ > +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC(0) > +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) > +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) > +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) > +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) > +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT(1) > +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) > +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) > +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE
Re: [U-Boot] [PATCH v3] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
Hi Jagan,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
On Fri, 2014-01-10 at 11:39 -0600, Chin Liang See wrote:
> To add the Cadence SPI driver support for Altera SOCFPGA. It
> required information such as clocks and timing from platform's
> configuration header file within include/configs folder
>
> Signed-off-by: Chin Liang See
> Cc: Jagan Teki
> Cc: Gerhard Sittig
> ---
> Changes for v3
> - Moved the documentation from doc folder to driver
> - Documented down macro specific to driver only
> Changes for v2
> - Combine driver into single C file instead of 2
> - Added documentation on the macro used
> - Using structure for registers instead of macro
> ---
> drivers/spi/Makefile |1 +
> drivers/spi/cadence_qspi.c | 1018
>
> drivers/spi/cadence_qspi.h | 196 +
> 3 files changed, 1215 insertions(+)
> create mode 100644 drivers/spi/cadence_qspi.c
> create mode 100644 drivers/spi/cadence_qspi.h
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index ed4ecd7..b8d56ea 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
> obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
> obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
> obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
> +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o
> obj-$(CONFIG_CF_SPI) += cf_spi.o
> obj-$(CONFIG_CF_QSPI) += cf_qspi.o
> obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> new file mode 100644
> index 000..4712b45
> --- /dev/null
> +++ b/drivers/spi/cadence_qspi.c
> @@ -0,0 +1,1018 @@
> +/*
> + * (C) Copyright 2014 Altera Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "cadence_qspi.h"
> +
> +static int qspi_is_init;
> +static unsigned int qspi_calibrated_hz;
> +static unsigned int qspi_calibrated_cs;
> +
> +static const struct cadence_qspi *cadence_qspi_base = (void *)QSPI_BASE;
> +
> +#define to_cadence_qspi_slave(s) \
> + container_of(s, struct cadence_qspi_slave, slave)
> +
> +#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)\
> + tdelay_ns) - (tsclk_ns)) / (tref_ns)))
> +
> +#define CQSPI_GET_WR_SRAM_LEVEL()\
> + ((readl(&cadence_qspi_base->sramfill) >>\
> + CQSPI_REG_SRAMLEVEL_WR_LSB) & CQSPI_REG_SRAMLEVEL_WR_MASK)
> +
> +static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
> + unsigned int addr_width)
> +{
> + unsigned int addr;
> +
> + addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
> +
> + if (addr_width == 4)
> + addr = (addr << 8) | addr_buf[3];
> +
> + return addr;
> +}
> +
> +static void cadence_qspi_apb_read_fifo_data(void *dest,
> + const void *src_ahb_addr, unsigned int bytes)
> +{
> + unsigned int temp;
> + int remaining = bytes;
> + unsigned int *dest_ptr = (unsigned int *)dest;
> + unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
> +
> + while (remaining > 0) {
> + if (remaining >= CQSPI_FIFO_WIDTH) {
> + *dest_ptr = readl(src_ptr);
> + remaining -= CQSPI_FIFO_WIDTH;
> + } else {
> + /* dangling bytes */
> + temp = readl(src_ptr);
> + memcpy(dest_ptr, &temp, remaining);
> + break;
> + }
> + dest_ptr++;
> + }
> +
> + return;
> +}
> +
> +static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
> + const void *src, unsigned int bytes)
> +{
> + unsigned int temp;
> + int remaining = bytes;
> + unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
> + unsigned int *src_ptr = (unsigned int *)src;
> +
> + while (remaining > 0) {
> + if (remaining >= CQSPI_FIFO_WIDTH) {
> + writel(*src_ptr, dest_ptr);
> + remaining -= sizeof(unsigned int);
> + } else {
> + /* dangling bytes */
> + memcpy(&temp, src_ptr, remaining);
> + writel(temp, dest_ptr);
> + break;
> + }
> + src_ptr++;
> + }
> +
> + return;
> +}
>
Re: [U-Boot] [RESEND PATCH 1/2 v2] socfpga: Adding Scan Manager driver -- ROLLED BACK.
Dear Albert, On Thu, 2014-02-13 at 10:45 +0100, ZY - albert.u.boot wrote: > > > > Applied to u-boot-arm/master, thanks! > > > > Note that arch/arm/cpu/armv7/socfpga/scan_manager.c had spurious empty > > lines at the end; I fixed that. > > > > Tom: as V1 and V2 were assigned to me, I reassigned this RESEND from > > you to me and fixed V1 and V2 status in patchwork to superseded. > > > > Amicalement, > > Correction -- while both patches together do work, the first one does > not, for the reason that it relies on a file which is only created by > the second patch. > > Please re-send as a single patch, or in reversed order, so that build > works at each patch. > > Amicalement, Yup, I was combining them initially but split them out later due to comments. But I can combine them again as its easy to do :) Thanks again for your support. Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
---
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 228 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 1006 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..4edc5d4 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..c9b988a
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(&scan_manager_base->stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
+ || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+
+ max_iter--;
+
+ if (max_iter > 0)
+ scanmgr_status = readl(&scan_manager_base->stat);
+ else
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
+ }
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
+}
+
+
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /* De-assert reinit if the IO scan chain is intended for HIO */
+ if (3 == io_scan_chain_id)
+ clrbits_le32(&freeze_controller_base->hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
+ != scan_mgr_io_scan_chain_engine_is_idle(
+ MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
+ return 1;
+ }
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits >>
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+ tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD <<
+ TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+ /* Program IO scan chain in 128-bit iteration */
+ for (i = 0
[U-Boot] [PATCH v2] socfpga: Adding Clock Manager driver
Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files
Signed-off-by: Chin Liang See
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Dinh Nguyen
---
Changes for v2
- merge the handoff file and driver into single patch
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/clock_manager.c | 378
arch/arm/cpu/armv7/socfpga/spl.c | 90 +
arch/arm/include/asm/arch-socfpga/clock_manager.h | 205 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/pll_config.h | 118 ++
include/configs/socfpga_cyclone5.h |1 +
7 files changed, 794 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/clock_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/clock_manager.h
create mode 100755 board/altera/socfpga/pll_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 4edc5d4..eb33f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -8,5 +8,5 @@
#
obj-y := lowlevel_init.o
-obj-y += misc.o timer.o reset_manager.o system_manager.o
+obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
new file mode 100644
index 000..7caa76f
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+static const struct socfpga_clock_manager *clock_manager_base =
+ (void *)SOCFPGA_CLKMGR_ADDRESS;
+
+#define CLKMGR_BYPASS_ENUM_ENABLE 1
+#define CLKMGR_BYPASS_ENUM_DISABLE 0
+#define CLKMGR_STAT_BUSY_ENUM_IDLE 0x0
+#define CLKMGR_STAT_BUSY_ENUM_BUSY 0x1
+#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_EOSC1 0x0
+#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_INPUT_MUX 0x1
+#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_EOSC1 0x0
+#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_INPUT_MUX 0x1
+
+#define CLEAR_BGP_EN_PWRDN \
+ (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+ CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
+ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+#define VCO_EN_BASE \
+ (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+ CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
+ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+static inline void cm_wait_for_lock(uint32_t mask)
+{
+ register uint32_t inter_val;
+ do {
+ inter_val = readl(&clock_manager_base->inter) & mask;
+ } while (inter_val != mask);
+}
+
+/* function to poll in the fsm busy bit */
+static inline void cm_wait4fsm(void)
+{
+ register uint32_t inter_val;
+ do {
+ inter_val = readl(&clock_manager_base->stat) &
CLKMGR_STAT_BUSY_ENUM_BUSY;
+ } while (inter_val);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static inline void cm_write_bypass(uint32_t val)
+{
+ writel(val, &clock_manager_base->bypass);
+ cm_wait4fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static inline void cm_write_ctrl(uint32_t val)
+{
+ writel(val, &clock_manager_base->ctrl);
+ cm_wait4fsm();
+}
+
+/* function to write a clock register that has phase information */
+static inline void cm_write_with_phase(uint32_t value,
+ uint32_t reg_address, uint32_t mask)
+{
+ /* poll until phase is zero */
+ do {} while (readl(reg_address) & mask);
+
+ writel(value, reg_address);
+
+ do {} while (readl(reg_address) & mask);
+}
+
+/*
+ * Setup clocks while making no assumptions of the
+ * previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ *
+ * Put all plls in bypass
+ *
+ * Put all plls VCO registers back to reset value (bgpwr dwn).
+ *
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ *
+ * Delay 5 us.
+ *
+ * Deassert bg pwr dn and set numerator and denominator
+ *
+ * Start 7 us timer.
+ *
+ * set internal dividers
+ *
+ * Wait for 7 us timer.
+ *
+ * Enable plls
+ *
+ * Set external dividers while plls are locking
+ *
+ * Wait for pll lock
+ *
+ * Assert/deassert outreset all.
+ *
+ * Take all pll's out of bypass
+ *
+ * Clear safe mode
+ *
+ * set source main and peripheral clocks
+ *
+ * Ungate clocks
+ */
+
+void cm_basic_init(const cm_config_t *cfg)
+{
+ uint32_t start, timeout;
+
+ /* Start by being paranoid and gate all sw managed clocks */
+
+ /*
+* We need to disable
Re: [U-Boot] [PATCH 1/2] socfpga: Adding Clock Manager driver
Hi Albert, On Thu, 2014-02-13 at 10:53 +0100, ZY - albert.u.boot wrote: > Hi Chin, > > On Wed, 18 Dec 2013 17:54:33 -0600, Chin Liang See > wrote: > > > Clock Manager driver will be called to reconfigure all the > > clocks setting based on user input. The input are passed to > > Preloader through handoff files > > Like the scan manager series, patch 1/2 will fail because it needs a > new file which is introduced by patch 2/2. Please post v2 as a single > patch. > > Amicalement, Sure, I can combine them. Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] socfpga: Adding Scan Manager driver
Hi Pavel,
Nice to hear from you again :)
On Fri, 2014-02-21 at 16:07 +0100, ZY - pavel wrote:
> Hi!
>
> > + /*
> > +* Check if the scan chain engine is inactive and the
> > +* WFIFO is empty before enabling the IO scan chain
> > +*/
> > + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
> > + != scan_mgr_io_scan_chain_engine_is_idle(
> > + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
> > + return 1;
> > + }
>
> Hmm.. function named "_is_idle" maybe should just return 0 or 1?
Yup we can simplify that. Probably just remain for readability. Hope its
ok for you.
>
> > + /*
> > +* Check if the scan chain engine has completed the
> > +* IO scan chain data shifting
> > +*/
> > + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
> > + != scan_mgr_io_scan_chain_engine_is_idle(
> > + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
> > + /* Disable IO Scan chain when error detected */
> > + clrbits_le32(&scan_manager_base->en,
> > + 1 << io_scan_chain_id);
> > + return 1;
> > + }
> > + }
>
> "goto error" would help avoid code duplication.
Good suggestion here. Will change that.
>
> > +struct socfpga_scan_manager {
> > + u32 stat;
> > + u32 en;
> > + u32 padding[2];
> > + u32 fifosinglebyte;
> > + u32 fifodoublebyte;
> > + u32 fifoquadbyte;
> > +};
>
> some underscores should be added here.
Sure, for better readability.
Thanks!
Chin Liang
>
> Thanks,
> Pavel
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[U-Boot] [PATCH v4] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
---
Changes for v4
- avoid code duplication by add goto error
- include underscore to variables name
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 225 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 1003 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..4edc5d4 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..3ec6c7e
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(&scan_manager_base->stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
+ || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+
+ max_iter--;
+
+ if (max_iter > 0)
+ scanmgr_status = readl(&scan_manager_base->stat);
+ else
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
+ }
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
+}
+
+
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /* De-assert reinit if the IO scan chain is intended for HIO */
+ if (3 == io_scan_chain_id)
+ clrbits_le32(&freeze_controller_base->hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
+ != scan_mgr_io_scan_chain_engine_is_idle(
+ MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
+ return 1;
+ }
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits >>
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+ tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD <<
+ TDI_TDO_HEADER_S
Re: [U-Boot] [PATCH] watchdog/denali: Adding DesignWare watchdog driver support
Hi Albert, On Thu, 2014-02-13 at 10:35 +0100, ZY - albert.u.boot wrote: > Hi Chin, > > On Wed, 18 Dec 2013 16:23:35 -0600, Chin Liang See > wrote: > > > To add the DesignWare watchdog driver support. It required > > information such as register base address and clock info from > > configuration header file within include/configs folder. > > > > Signed-off-by: Chin Liang See > > Cc: Anatolij Gustschin > > Cc: Albert Aribaud > > Cc: Heiko Schocher > > Cc: Tom Rini > > --- > > drivers/watchdog/Makefile |1 + > > drivers/watchdog/designware_wdt.c | 75 > > + > > 2 files changed, 76 insertions(+) > > create mode 100644 drivers/watchdog/designware_wdt.c > > As such, this code is dead code in that no board uses this watchdog -- > same as the NAND driver series assigned to scott Wood (cc:). > > If there is a board which uses these drivers, please resubmit the > drivers and board patches in a single series where some board config > is made to use them. > > Amicalement, Sorry my bad as I would thought they would need 2 different patches. Let me fix this watchdog and nand patch. Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] watchdog/denali: Adding DesignWare watchdog driver support
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See
Cc: Anatolij Gustschin
Cc: Albert Aribaud
Cc: Heiko Schocher
Cc: Tom Rini
---
Changes for v2
- Enable this driver at socfpga_cyclone5 board
---
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
drivers/watchdog/Makefile |1 +
drivers/watchdog/designware_wdt.c | 73
include/configs/socfpga_cyclone5.h | 13
4 files changed, 88 insertions(+)
create mode 100644 drivers/watchdog/designware_wdt.c
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index 20f12e0..5f73824 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -11,6 +11,7 @@
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 06ced10..0276a10 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
+obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
new file mode 100644
index 000..cb88844
--- /dev/null
+++ b/drivers/watchdog/designware_wdt.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#define DW_WDT_CR 0x00
+#define DW_WDT_TORR0x04
+#define DW_WDT_CRR 0x0C
+
+#define DW_WDT_CR_EN_OFFSET0x00
+#define DW_WDT_CR_RMOD_OFFSET 0x01
+#define DW_WDT_CR_RMOD_VAL 0x00
+#define DW_WDT_CRR_RESTART_VAL 0x76
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+int designware_wdt_settimeout(unsigned int timeout)
+{
+ signed int i;
+ /* calculate the timeout range value */
+ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
+ if (i > 15)
+ i = 15;
+ if (i < 0)
+ i = 0;
+
+ writel((i | (i<<4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
+ return 0;
+}
+
+void designware_wdt_enable(void)
+{
+ writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | \
+ (0x1 << DW_WDT_CR_EN_OFFSET)),
+ (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+}
+
+unsigned int designware_wdt_is_enabled(void)
+{
+ unsigned long val;
+ val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ return val & 0x1;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ if (designware_wdt_is_enabled())
+ /* restart the watchdog counter */
+ writel(DW_WDT_CRR_RESTART_VAL,
+ (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+}
+
+void hw_watchdog_init(void)
+{
+ /* reset to disable the watchdog */
+ hw_watchdog_reset();
+ /* set timer in miliseconds */
+ designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
+ /* enable the watchdog */
+ designware_wdt_enable();
+ /* reset the watchdog */
+ hw_watchdog_reset();
+}
+#endif
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index fc921ee..1b78ccb 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -207,6 +207,16 @@
#define CONFIG_ENV_IS_NOWHERE
/*
+ * L4 Watchdog
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
+/* Clocks source frequency to watchdog timer */
+#define CONFIG_DW_WDT_CLOCK_KHZ25000
+
+/*
* SPL "Second Program Loader" aka Initial Software
*/
@@ -238,4 +248,7 @@
/* Support for lib/libgeneric.o in SPL binary */
#define CONFIG_SPL_LIBGENERIC_SUPPORT
+/* Support for watchdog */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
#endif /* __CONFIG_H */
--
1.7.9.5
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Re: [U-Boot] [PATCH] nand/denali: Adding Denali NAND driver support
Hi Masahiro, On Fri, 2014-02-21 at 19:57 +0900, Masahiro Yamada wrote: > Hi Chin, > (adding Albert to Cc:) > > > Hi Scott, > > > > As there are no further comments, would need your help to apply this > > patch. Thanks and appreciate for your support. > > > > Chin Liang > > > Panasonic SoCs are using Denali NAND controller. > I guess I can test your patch. > Please wait a week. > > > As Albert mentioned, the problem is > there must be a board which uses your driver code. > Thanks for the help. Actually this driver is used in socfpga_cyclone5 board. Just that I misunderstood they would need separate patches. I will fix this in next commit. > I'll review and test your code (it looks like most parts are ported from > Linux) and if it works fine, then I will post Panasonic SoCs (based on > ARM coretexA9) and boards series with CONFIG_NAND_DENALI enabled. > Yup, the code base are from Linux. But I need to modify it to certain extend to get it working at dev kit. Anyway, it would be excited to figure whether it work for other platform too. > As for the initial run test on my board, it is not working so far. > So I am diving into the code... If you want to run under SPL, there are some patches for that. Let me know if you need that. While for U-Boot, they are working fine. Probably it might due to parameter setting. I will attach my configuration in my new patches. Maybe worth to note, this driver was tested against 3 different devices but they all are ONFI parts. Thanks and appreciate for your offers to help Chin Liang > > > Best Regards > Masahiro Yamada > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] watchdog/denali: Adding DesignWare watchdog driver support
Hi Albert, On Fri, 2014-02-21 at 17:58 +0100, ZY - albert.u.boot wrote: > Hi Chin, > > On Fri, 21 Feb 2014 10:00:08 -0600, Chin Liang See > wrote: > > > Hi Albert, > > > > On Thu, 2014-02-13 at 10:35 +0100, ZY - albert.u.boot wrote: > > > Hi Chin, > > > > > > On Wed, 18 Dec 2013 16:23:35 -0600, Chin Liang See > > > wrote: > > > > > > > To add the DesignWare watchdog driver support. It required > > > > information such as register base address and clock info from > > > > configuration header file within include/configs folder. > > > > > > > > Signed-off-by: Chin Liang See > > > > Cc: Anatolij Gustschin > > > > Cc: Albert Aribaud > > > > Cc: Heiko Schocher > > > > Cc: Tom Rini > > > > --- > > > > drivers/watchdog/Makefile |1 + > > > > drivers/watchdog/designware_wdt.c | 75 > > > > + > > > > 2 files changed, 76 insertions(+) > > > > create mode 100644 drivers/watchdog/designware_wdt.c > > > > > > As such, this code is dead code in that no board uses this watchdog -- > > > same as the NAND driver series assigned to scott Wood (cc:). > > > > > > If there is a board which uses these drivers, please resubmit the > > > drivers and board patches in a single series where some board config > > > is made to use them. > > > > > > Amicalement, > > > > Sorry my bad as I would thought they would need 2 different patches. > > Actually it could have been two different patches, but in a single > series (i.e., patch 1/2 provides the driver, patch 2/2 provides the > configurations which use the driver). > Sure I can do that too. Thanks! Chin Liang > > Chin Liang > > Amicalement, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] nand/denali: Adding Denali NAND driver support
To add the Denali NAND driver support into U-Boot. It required
information such as register base address from configuration
header file within include/configs folder.
Signed-off-by: Chin Liang See
Cc: Artem Bityutskiy
Cc: David Woodhouse
Cc: Brian Norris
Cc: Scott Wood
---
Changes for v2
- Enable this driver support for SOCFPGA
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/denali_nand.c | 1166
drivers/mtd/nand/denali_nand.h | 501 +
3 files changed, 1668 insertions(+)
create mode 100644 drivers/mtd/nand/denali_nand.c
create mode 100644 drivers/mtd/nand/denali_nand.h
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 02b149c..24e8218 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
+obj-$(CONFIG_NAND_DENALI) += denali_nand.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
diff --git a/drivers/mtd/nand/denali_nand.c b/drivers/mtd/nand/denali_nand.c
new file mode 100644
index 000..55246c9
--- /dev/null
+++ b/drivers/mtd/nand/denali_nand.c
@@ -0,0 +1,1166 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#include "denali_nand.h"
+
+/* We define a module parameter that allows the user to override
+ * the hardware and decide what timing mode should be used.
+ */
+#define NAND_DEFAULT_TIMINGS -1
+
+static struct denali_nand_info denali;
+static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
+
+/* We define a macro here that combines all interrupts this driver uses into
+ * a single constant value, for convenience. */
+#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
+ INTR_STATUS__ECC_TRANSACTION_DONE | \
+ INTR_STATUS__ECC_ERR | \
+ INTR_STATUS__PROGRAM_FAIL | \
+ INTR_STATUS__LOAD_COMP | \
+ INTR_STATUS__PROGRAM_COMP | \
+ INTR_STATUS__TIME_OUT | \
+ INTR_STATUS__ERASE_FAIL | \
+ INTR_STATUS__RST_COMP | \
+ INTR_STATUS__ERASE_COMP | \
+ INTR_STATUS__ECC_UNCOR_ERR | \
+ INTR_STATUS__INT_ACT | \
+ INTR_STATUS__LOCKED_BLK)
+
+/* indicates whether or not the internal value for the flash bank is
+ * valid or not */
+#define CHIP_SELECT_INVALID-1
+
+#define SUPPORT_8BITECC1
+
+/* This macro divides two integers and rounds fractional values up
+ * to the nearest integer value. */
+#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
+
+/* These constants are defined by the driver to enable common driver
+ * configuration options. */
+#define SPARE_ACCESS 0x41
+#define MAIN_ACCESS0x42
+#define MAIN_SPARE_ACCESS 0x43
+
+#define DENALI_UNLOCK_START0x10
+#define DENALI_UNLOCK_END 0x11
+#define DENALI_LOCK0x21
+#define DENALI_LOCK_TIGHT 0x31
+#define DENALI_BUFFER_LOAD 0x60
+#define DENALI_BUFFER_WRITE0x62
+
+#define DENALI_READ0
+#define DENALI_WRITE 0x100
+
+/* types of device accesses. We can issue commands and get status */
+#define COMMAND_CYCLE 0
+#define ADDR_CYCLE 1
+#define STATUS_CYCLE 2
+
+/* this is a helper macro that allows us to
+ * format the bank into the proper bits for the controller */
+#define BANK(x) ((x) << 24)
+
+/* Interrupts are cleared by writing a 1 to the appropriate status bit */
+static inline void clear_interrupt(uint32_t irq_mask)
+{
+ uint32_t intr_status_reg = 0;
+ intr_status_reg = INTR_STATUS(denali.flash_bank);
+ __raw_writel(irq_mask, denali.flash_reg + intr_status_reg);
+}
+
+static uint32_t read_interrupt_status(void)
+{
+ uint32_t intr_status_reg = 0;
+ intr_status_reg = INTR_STATUS(denali.flash_bank);
+ return __raw_readl(denali.flash_reg + intr_status_reg);
+}
+
+static void clear_interrupts(void)
+{
+ uint32_t status = 0x0;
+ status = read_interrupt_status();
+ clear_interrupt(status);
+ denali.irq_status = 0x0;
+}
+
+static void denali_irq_enable(uint32_t int_mask)
+{
+ int i;
+ for (i = 0; i < denali.max_banks; ++i)
+ __raw_writel(int_mask, denali.flash_reg + INTR_EN(i));
+}
+
+static uint32_t wait_for_irq(uint32_t irq_mask)
+{
+ unsigned long comp_res = 1000;
+ uint32_t intr_status = 0;
+
+ do {
+ intr_status = read_interrupt_status() & DENALI_IRQ_ALL;
+ if
[U-Boot] [PATCH v2 2/2] socfpga: Adding Denali NAND driver support
To add the Denali NAND driver support into SOCFPGA. But it would not enabled by default as Altera Cyclone V dev kit doesn't have a NAND device on it. Signed-off-by: Chin Liang See Cc: Artem Bityutskiy Cc: David Woodhouse Cc: Brian Norris Cc: Scott Wood --- Changes for v2 - Enable this driver support for SOCFPGA --- .../include/asm/arch-socfpga/socfpga_base_addrs.h |2 ++ include/configs/socfpga_cyclone5.h | 16 2 files changed, 18 insertions(+) diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 5f73824..dd3988b 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -8,6 +8,8 @@ #define _SOCFPGA_BASE_ADDRS_H_ #define SOCFPGA_L3REGS_ADDRESS 0xff80 +#define SOCFPGA_NAND_DATA_ADDRESS 0xff90 +#define SOCFPGA_NAND_REGS_ADDRESS 0xffb8 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 1b78ccb..7f26c14 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -216,6 +216,22 @@ /* Clocks source frequency to watchdog timer */ #define CONFIG_DW_WDT_CLOCK_KHZ25000 +/* NAND */ +#undef CONFIG_NAND_DENALI +#ifdef CONFIG_NAND_DENALI +#define CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NAND_REGS_ADDRESS +#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NAND_DATA_ADDRESS +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_REGS_BASE +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* How many bytes need to be skipped at the start of spare area */ +#define CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES (2) +/* The ECC size which either 512 or 1024 */ +#define CONFIG_NAND_DENALI_ECC_SIZE(512) +#endif /* CONFIG_NAND_DENALI */ + /* * SPL "Second Program Loader" aka Initial Software */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/2] watchdog/denali: Adding DesignWare watchdog driver support
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See
Cc: Anatolij Gustschin
Cc: Albert Aribaud
Cc: Heiko Schocher
Cc: Tom Rini
---
Changes for v3
- Split to 2 series patch
Changes for v2
- Enable this driver at socfpga_cyclone5 board
---
drivers/watchdog/Makefile |1 +
drivers/watchdog/designware_wdt.c | 73 +
2 files changed, 74 insertions(+)
create mode 100644 drivers/watchdog/designware_wdt.c
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 06ced10..0276a10 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
+obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
new file mode 100644
index 000..cb88844
--- /dev/null
+++ b/drivers/watchdog/designware_wdt.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#define DW_WDT_CR 0x00
+#define DW_WDT_TORR0x04
+#define DW_WDT_CRR 0x0C
+
+#define DW_WDT_CR_EN_OFFSET0x00
+#define DW_WDT_CR_RMOD_OFFSET 0x01
+#define DW_WDT_CR_RMOD_VAL 0x00
+#define DW_WDT_CRR_RESTART_VAL 0x76
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+int designware_wdt_settimeout(unsigned int timeout)
+{
+ signed int i;
+ /* calculate the timeout range value */
+ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
+ if (i > 15)
+ i = 15;
+ if (i < 0)
+ i = 0;
+
+ writel((i | (i<<4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
+ return 0;
+}
+
+void designware_wdt_enable(void)
+{
+ writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | \
+ (0x1 << DW_WDT_CR_EN_OFFSET)),
+ (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+}
+
+unsigned int designware_wdt_is_enabled(void)
+{
+ unsigned long val;
+ val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ return val & 0x1;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ if (designware_wdt_is_enabled())
+ /* restart the watchdog counter */
+ writel(DW_WDT_CRR_RESTART_VAL,
+ (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+}
+
+void hw_watchdog_init(void)
+{
+ /* reset to disable the watchdog */
+ hw_watchdog_reset();
+ /* set timer in miliseconds */
+ designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
+ /* enable the watchdog */
+ designware_wdt_enable();
+ /* reset the watchdog */
+ hw_watchdog_reset();
+}
+#endif
--
1.7.9.5
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/2] socfpga: Adding DesignWare watchdog support
To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: Chin Liang See Cc: Anatolij Gustschin Cc: Albert Aribaud Cc: Heiko Schocher Cc: Tom Rini --- Changes for v3 - Split to 2 series patch Changes for v2 - Enable this driver at socfpga_cyclone5 board --- .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + include/configs/socfpga_cyclone5.h | 13 + 2 files changed, 14 insertions(+) diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 20f12e0..5f73824 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -11,6 +11,7 @@ #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index fc921ee..1b78ccb 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -207,6 +207,16 @@ #define CONFIG_ENV_IS_NOWHERE /* + * L4 Watchdog + */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 +#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +/* Clocks source frequency to watchdog timer */ +#define CONFIG_DW_WDT_CLOCK_KHZ25000 + +/* * SPL "Second Program Loader" aka Initial Software */ @@ -238,4 +248,7 @@ /* Support for lib/libgeneric.o in SPL binary */ #define CONFIG_SPL_LIBGENERIC_SUPPORT +/* Support for watchdog */ +#define CONFIG_SPL_WATCHDOG_SUPPORT + #endif /* __CONFIG_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] socfpga: Adding Scan Manager driver
Hi Michal,
On Fri, 2014-02-21 at 17:01 +0100, Michal Simek wrote:
> Hi,
>
> On 02/21/2014 04:26 PM, Chin Liang See wrote:
> > Scan Manager driver will be called to configure the IOCSR
> > scan chain. This configuration will setup the IO buffer settings
> >
> > Signed-off-by: Chin Liang See
> > Cc: Dinh Nguyen
> > Cc: Wolfgang Denk
> > CC: Pavel Machek
> > Cc: Tom Rini
> > Cc: Albert Aribaud
> > ---
> > Changes for v4
> > - avoid code duplication by add goto error
> > - include underscore to variables name
> > Changes for v3
> > - merge the handoff file and driver into single patch
> > Changes for v2
> > - rebase with latest v2014.01-rc1
> > ---
> > arch/arm/cpu/armv7/socfpga/Makefile|2 +-
> > arch/arm/cpu/armv7/socfpga/scan_manager.c | 225 +++
> > arch/arm/cpu/armv7/socfpga/spl.c |4 +
> > arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++
> > .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
> > board/altera/socfpga/iocsr_config.c| 657
> >
> > board/altera/socfpga/iocsr_config.h| 17 +
> > include/configs/socfpga_cyclone5.h |1 +
> > 8 files changed, 1003 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
> > create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
> > create mode 100644 board/altera/socfpga/iocsr_config.c
> > create mode 100644 board/altera/socfpga/iocsr_config.h
> >
> > diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
> > b/arch/arm/cpu/armv7/socfpga/Makefile
> > index 3e84a0c..4edc5d4 100644
> > --- a/arch/arm/cpu/armv7/socfpga/Makefile
> > +++ b/arch/arm/cpu/armv7/socfpga/Makefile
> > @@ -9,4 +9,4 @@
> >
> > obj-y := lowlevel_init.o
> > obj-y += misc.o timer.o reset_manager.o system_manager.o
> > -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
> > diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
> > b/arch/arm/cpu/armv7/socfpga/scan_manager.c
> > new file mode 100644
> > index 000..3ec6c7e
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
> > @@ -0,0 +1,225 @@
> > +/*
> > + * Copyright (C) 2013 Altera Corporation
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +
>
> probably we can use just empty line here.
Removed
>
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static const struct socfpga_scan_manager *scan_manager_base =
> > + (void *)(SOCFPGA_SCANMGR_ADDRESS);
> > +static const struct socfpga_freeze_controller *freeze_controller_base =
> > + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
> > +
> > +/*
> > + * Function to check IO scan chain engine status and wait if the engine is
> > + * is active. Poll the IO scan chain engine till maximum iteration reached.
> > + */
> > +static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t
> > max_iter)
> > +{
> > + uint32_t scanmgr_status;
> > +
> > + scanmgr_status = readl(&scan_manager_base->stat);
> > +
> > + /* Poll the engine until the scan engine is inactive */
> > + while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
> > + || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
> > +
> > + max_iter--;
> > +
> > + if (max_iter > 0)
> > + scanmgr_status = readl(&scan_manager_base->stat);
> > + else
> > + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
> > + }
> > + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
> > +}
> > +
> > +
> > +
>
> ditto.
Removed
>
> > +/* Program HPS IO Scan Chain */
> > +uint32_t scan_mgr_io_scan_chain_prg(
> > + uint32_t io_scan_chain_id,
> > + uint32_t io_scan_chain_len_in_bits,
> > + const uint32_t *iocsr_scan_chain)
> > +{
> > +
>
> why blanks line here.
Removed
>
> > + uint16_t tdi_tdo_header;
> > + uint32_t io_program_iter;
> > + uint32_t io_scan_chain_data_residual;
> > + uint32_t residual;
> > + uint32_t i;
> > + uint32_t index = 0;
> > +
> > + /* De-assert reinit if the IO scan chain is intended
[U-Boot] [PATCH v5] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
---
Changes for v5
- Removal of additional blank line
- Added comment for magic number
Changes for v4
- avoid code duplication by add goto error
- include underscore to variables name
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 214 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 96 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 991 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..4edc5d4 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..6e6f372
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(&scan_manager_base->stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
+ || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+ max_iter--;
+ if (max_iter > 0)
+ scanmgr_status = readl(&scan_manager_base->stat);
+ else
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
+ }
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /*
+* De-assert reinit if the IO scan chain is intended for HIO. In
+* this, its the chain 3.
+*/
+ if (3 == io_scan_chain_id)
+ clrbits_le32(&freeze_controller_base->hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
+ != scan_mgr_io_scan_chain_engine_is_idle(
+ MAX_WAITING_DELAY_IO_SCAN_ENGINE))
+ return 1;
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits >>
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit
Re: [U-Boot] [PATCH v5] socfpga: Adding Scan Manager driver
Dear Wolfgang,
On Sat, 2014-02-22 at 09:42 +0100, ZY - wd wrote:
> Dear Chin Liang See,
>
> In message <1393022790-9296-1-git-send-email-cl...@altera.com> you wrote:
> > Scan Manager driver will be called to configure the IOCSR
> > scan chain. This configuration will setup the IO buffer settings
> >
> > Signed-off-by: Chin Liang See
> > Cc: Dinh Nguyen
> > Cc: Wolfgang Denk
> > CC: Pavel Machek
> > Cc: Tom Rini
> > Cc: Albert Aribaud
> > ---
> > Changes for v5
> > - Removal of additional blank line
> > - Added comment for magic number
> > Changes for v4
> > - avoid code duplication by add goto error
> > - include underscore to variables name
> > Changes for v3
> > - merge the handoff file and driver into single patch
> > Changes for v2
> > - rebase with latest v2014.01-rc1
> > ---
> > arch/arm/cpu/armv7/socfpga/Makefile|2 +-
> > arch/arm/cpu/armv7/socfpga/scan_manager.c | 214 +++
> > arch/arm/cpu/armv7/socfpga/spl.c |4 +
> > arch/arm/include/asm/arch-socfpga/scan_manager.h | 96 +++
> > .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
> > board/altera/socfpga/iocsr_config.c| 657
> >
> > board/altera/socfpga/iocsr_config.h| 17 +
> > include/configs/socfpga_cyclone5.h |1 +
> > 8 files changed, 991 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
> > create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
> > create mode 100644 board/altera/socfpga/iocsr_config.c
> > create mode 100644 board/altera/socfpga/iocsr_config.h
> >
> > diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
> > b/arch/arm/cpu/armv7/socfpga/Makefile
> > index 3e84a0c..4edc5d4 100644
> > --- a/arch/arm/cpu/armv7/socfpga/Makefile
> > +++ b/arch/arm/cpu/armv7/socfpga/Makefile
> > @@ -9,4 +9,4 @@
> >
> > obj-y := lowlevel_init.o
> > obj-y += misc.o timer.o reset_manager.o system_manager.o
> > -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
> > diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
> > b/arch/arm/cpu/armv7/socfpga/scan_manager.c
> > new file mode 100644
> > index 000..6e6f372
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
> > @@ -0,0 +1,214 @@
> > +/*
> > + * Copyright (C) 2013 Altera Corporation
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static const struct socfpga_scan_manager *scan_manager_base =
> > + (void *)(SOCFPGA_SCANMGR_ADDRESS);
> > +static const struct socfpga_freeze_controller *freeze_controller_base =
> > + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
> > +
> > +/*
> > + * Function to check IO scan chain engine status and wait if the engine is
> > + * is active. Poll the IO scan chain engine till maximum iteration reached.
> > + */
> > +static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t
> > max_iter)
> > +{
> > + uint32_t scanmgr_status;
> > +
> > + scanmgr_status = readl(&scan_manager_base->stat);
> > +
> > + /* Poll the engine until the scan engine is inactive */
> > + while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
> > + || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
> > + max_iter--;
>
> This is difficult to read due to unlucky indentation. I suggest to
> rewrite like this:
>
>
> while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
> (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
>
> or even
>
> while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
> (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)
> ) {
>
Fixed
> > + scanmgr_status = readl(&scan_manager_base->stat);
> > + else
> > + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
> > + }
> > + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
> > +}
>
> You decrement the parameter "max_iter" in the loop - I guess this was
> intended to make sure this is not an endless loop. But there is no
> test anywhere for it becoming 0 or so - which makes the p
[U-Boot] [PATCH v6] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
---
Changes for v6
- Fixed various coding style issue
Changes for v5
- Removal of additional blank line
- Added comment for magic number
Changes for v4
- avoid code duplication by add goto error
- include underscore to variables name
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 211 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 96 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 988 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..4edc5d4 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..a79b57b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(&scan_manager_base->stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
+ (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+ max_iter--;
+ if (max_iter > 0)
+ scanmgr_status = readl(&scan_manager_base->stat);
+ else
+ return SCAN_MGR_STATUS_ACTIVE;
+ }
+ return SCAN_MGR_STATUS_IDLE;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /*
+* De-assert reinit if the IO scan chain is intended for HIO. In
+* this, its the chain 3.
+*/
+ if (io_scan_chain_id == 3)
+ clrbits_le32(&freeze_controller_base->hioctrl,
+SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (scan_chain_engine_is_idle(SCAN_MAX_DELAY) != SCAN_MGR_STATUS_IDLE)
+ return 1;
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits >>
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+ tdi_tdo_header = TDI_TDO_HEADER
Re: [U-Boot] [PATCH v2 1/2] nand/denali: Adding Denali NAND driver support
Hi Michal, On Mon, 2014-02-24 at 08:48 +0100, Michal Simek wrote: > On 02/21/2014 09:51 PM, Chin Liang See wrote: > > To add the Denali NAND driver support into U-Boot. It required > > information such as register base address from configuration > > header file within include/configs folder. > > > > Signed-off-by: Chin Liang See > > Cc: Artem Bityutskiy > > Cc: David Woodhouse > > Cc: Brian Norris > > Cc: Scott Wood > > --- > > Changes for v2 > > - Enable this driver support for SOCFPGA > > --- > > drivers/mtd/nand/Makefile |1 + > > drivers/mtd/nand/denali_nand.c | 1166 > > > > drivers/mtd/nand/denali_nand.h | 501 + > > 3 files changed, 1668 insertions(+) > > create mode 100644 drivers/mtd/nand/denali_nand.c > > create mode 100644 drivers/mtd/nand/denali_nand.h > > > > diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile > > index 02b149c..24e8218 100644 > > --- a/drivers/mtd/nand/Makefile > > +++ b/drivers/mtd/nand/Makefile > > @@ -39,6 +39,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o > > obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o > > obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o > > obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o > > +obj-$(CONFIG_NAND_DENALI) += denali_nand.o > > obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o > > obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o > > obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o > > diff --git a/drivers/mtd/nand/denali_nand.c b/drivers/mtd/nand/denali_nand.c > > new file mode 100644 > > index 000..55246c9 > > --- /dev/null > > +++ b/drivers/mtd/nand/denali_nand.c > > @@ -0,0 +1,1166 @@ > > +/* > > + * Copyright (C) 2013 Altera Corporation > > What about 2014? Good catch. The first revision was sent on 2013. Fixed > > > > + * Copyright (C) 2009-2010, Intel Corporation and its suppliers. > > + * > > + * SPDX-License-Identifier:GPL-2.0+ > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +#include "denali_nand.h" > > + > > +/* We define a module parameter that allows the user to override > > + * the hardware and decide what timing mode should be used. > > + */ > > +#define NAND_DEFAULT_TIMINGS -1 > > + > > +static struct denali_nand_info denali; > > +static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; > > + > > +/* We define a macro here that combines all interrupts this driver uses > > into > > + * a single constant value, for convenience. */ > > +#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ > > + INTR_STATUS__ECC_TRANSACTION_DONE | \ > > + INTR_STATUS__ECC_ERR | \ > > + INTR_STATUS__PROGRAM_FAIL | \ > > + INTR_STATUS__LOAD_COMP | \ > > + INTR_STATUS__PROGRAM_COMP | \ > > + INTR_STATUS__TIME_OUT | \ > > + INTR_STATUS__ERASE_FAIL | \ > > + INTR_STATUS__RST_COMP | \ > > + INTR_STATUS__ERASE_COMP | \ > > + INTR_STATUS__ECC_UNCOR_ERR | \ > > + INTR_STATUS__INT_ACT | \ > > + INTR_STATUS__LOCKED_BLK) > > + > > +/* indicates whether or not the internal value for the flash bank is > > + * valid or not */ > > +#define CHIP_SELECT_INVALID-1 > > + > > +#define SUPPORT_8BITECC1 > > + > > +/* This macro divides two integers and rounds fractional values up > > + * to the nearest integer value. */ > > +#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) > > + > > +/* These constants are defined by the driver to enable common driver > > + * configuration options. */ > > +#define SPARE_ACCESS 0x41 > > +#define MAIN_ACCESS0x42 > > +#define MAIN_SPARE_ACCESS 0x43 > > + > > +#define DENALI_UNLOCK_START0x10 > > +#define DENALI_UNLOCK_END 0x11 > > +#define DENALI_LOCK0x21 > > +#define DENALI_LOCK_TIGHT 0x31 > > +#define DENALI_BUFFER_LOAD 0x60 > > +#define DENALI_BUFFER_WRITE0x62 > > + > > +#define DENALI_READ0 > > +#define DENALI_WRITE 0x100 > > + > > +/* types of device accesses. We can issue commands and get status */ > > +#define COMMAND_CYCLE 0 > > +#define ADDR_CYCLE 1 > > +#define STATUS_CYCLE 2 > > + > > +
[U-Boot] [PATCH v3] nand/denali: Adding Denali NAND driver support
To add the Denali NAND driver support into U-Boot. It required
information such as register base address from configuration
header file within include/configs folder.
Signed-off-by: Chin Liang See
Cc: Artem Bityutskiy
Cc: David Woodhouse
Cc: Brian Norris
Cc: Scott Wood
---
Changes for v3
- Fixed coding style
Changes for v2
- Enable this driver support for SOCFPGA
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/denali_nand.c | 1201
drivers/mtd/nand/denali_nand.h | 501 +
3 files changed, 1703 insertions(+)
create mode 100644 drivers/mtd/nand/denali_nand.c
create mode 100644 drivers/mtd/nand/denali_nand.h
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 02b149c..24e8218 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
+obj-$(CONFIG_NAND_DENALI) += denali_nand.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
diff --git a/drivers/mtd/nand/denali_nand.c b/drivers/mtd/nand/denali_nand.c
new file mode 100644
index 000..e9db390
--- /dev/null
+++ b/drivers/mtd/nand/denali_nand.c
@@ -0,0 +1,1201 @@
+/*
+ * Copyright (C) 2013-2014 Altera Corporation
+ * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#include "denali_nand.h"
+
+/*
+ * We define a module parameter that allows the user to override
+ * the hardware and decide what timing mode should be used.
+ */
+#define NAND_DEFAULT_TIMINGS -1
+
+static struct denali_nand_info denali;
+static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
+
+/*
+ * We define a macro here that combines all interrupts this driver uses into
+ * a single constant value, for convenience.
+ */
+#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
+ INTR_STATUS__ECC_TRANSACTION_DONE | \
+ INTR_STATUS__ECC_ERR | \
+ INTR_STATUS__PROGRAM_FAIL | \
+ INTR_STATUS__LOAD_COMP | \
+ INTR_STATUS__PROGRAM_COMP | \
+ INTR_STATUS__TIME_OUT | \
+ INTR_STATUS__ERASE_FAIL | \
+ INTR_STATUS__RST_COMP | \
+ INTR_STATUS__ERASE_COMP | \
+ INTR_STATUS__ECC_UNCOR_ERR | \
+ INTR_STATUS__INT_ACT | \
+ INTR_STATUS__LOCKED_BLK)
+
+/*
+ * indicates whether or not the internal value for the flash bank is
+ * valid or not
+ */
+#define CHIP_SELECT_INVALID-1
+
+#define SUPPORT_8BITECC1
+
+/*
+ * This macro divides two integers and rounds fractional values up
+ * to the nearest integer value.
+ */
+#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
+
+/*
+ * These constants are defined by the driver to enable common driver
+ * configuration options.
+ */
+#define SPARE_ACCESS 0x41
+#define MAIN_ACCESS0x42
+#define MAIN_SPARE_ACCESS 0x43
+
+#define DENALI_UNLOCK_START0x10
+#define DENALI_UNLOCK_END 0x11
+#define DENALI_LOCK0x21
+#define DENALI_LOCK_TIGHT 0x31
+#define DENALI_BUFFER_LOAD 0x60
+#define DENALI_BUFFER_WRITE0x62
+
+#define DENALI_READ0
+#define DENALI_WRITE 0x100
+
+/* types of device accesses. We can issue commands and get status */
+#define COMMAND_CYCLE 0
+#define ADDR_CYCLE 1
+#define STATUS_CYCLE 2
+
+/*
+ * this is a helper macro that allows us to
+ * format the bank into the proper bits for the controller
+ */
+#define BANK(x) ((x) << 24)
+
+/* Interrupts are cleared by writing a 1 to the appropriate status bit */
+static inline void clear_interrupt(uint32_t irq_mask)
+{
+ uint32_t intr_status_reg = 0;
+ intr_status_reg = INTR_STATUS(denali.flash_bank);
+ __raw_writel(irq_mask, denali.flash_reg + intr_status_reg);
+}
+
+static uint32_t read_interrupt_status(void)
+{
+ uint32_t intr_status_reg = 0;
+ intr_status_reg = INTR_STATUS(denali.flash_bank);
+ return __raw_readl(denali.flash_reg + intr_status_reg);
+}
+
+static void clear_interrupts(void)
+{
+ uint32_t status = 0;
+ status = read_interrupt_status();
+ clear_interrupt(status);
+ denali.irq_status = 0;
+}
+
+static void denali_irq_enable(uint32_t int_mask)
+{
+ int i;
+ for (i = 0; i < denali.max_banks; ++i)
+ __raw_writel(int_mask, denali.flash_reg + INTR_EN(i));
+}
+
+static uint32_t wait_for_irq(uint32_t irq_mask)
+{
+ unsigned long comp_res = 1000;
+ uint32_t intr_status;
+
+ do {
+ intr_status = read_interrupt_status
Re: [U-Boot] [PATCH v3 1/2] watchdog/denali: Adding DesignWare watchdog driver support
Hi Michal,
On Mon, 2014-02-24 at 08:51 +0100, Michal Simek wrote:
> On 02/21/2014 09:57 PM, Chin Liang See wrote:
> > To add the DesignWare watchdog driver support. It required
> > information such as register base address and clock info from
> > configuration header file within include/configs folder.
> >
> > Signed-off-by: Chin Liang See
> > Cc: Anatolij Gustschin
> > Cc: Albert Aribaud
> > Cc: Heiko Schocher
> > Cc: Tom Rini
> > ---
> > Changes for v3
> > - Split to 2 series patch
> > Changes for v2
> > - Enable this driver at socfpga_cyclone5 board
> > ---
> > drivers/watchdog/Makefile |1 +
> > drivers/watchdog/designware_wdt.c | 73
> > +
> > 2 files changed, 74 insertions(+)
> > create mode 100644 drivers/watchdog/designware_wdt.c
> >
>
> Checkpatch.
> total: 0 errors, 1 warnings, 1 checks, 77 lines checked
Fixed
>
>
> > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> > index 06ced10..0276a10 100644
> > --- a/drivers/watchdog/Makefile
> > +++ b/drivers/watchdog/Makefile
> > @@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
> > obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
> > obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
> > obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
> > +obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
> > diff --git a/drivers/watchdog/designware_wdt.c
> > b/drivers/watchdog/designware_wdt.c
> > new file mode 100644
> > index 000..cb88844
> > --- /dev/null
> > +++ b/drivers/watchdog/designware_wdt.c
> > @@ -0,0 +1,73 @@
> > +/*
> > + * Copyright (C) 2013 Altera Corporation
>
> 2014?
Oops, good catch. Fixed
>
>
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#define DW_WDT_CR 0x00
> > +#define DW_WDT_TORR0x04
> > +#define DW_WDT_CRR 0x0C
> > +
> > +#define DW_WDT_CR_EN_OFFSET0x00
> > +#define DW_WDT_CR_RMOD_OFFSET 0x01
> > +#define DW_WDT_CR_RMOD_VAL 0x00
> > +#define DW_WDT_CRR_RESTART_VAL 0x76
> > +
> > +/*
> > + * Set the watchdog time interval.
> > + * Counter is 32 bit.
> > + */
> > +int designware_wdt_settimeout(unsigned int timeout)
> > +{
> > + signed int i;
>
> you should separate variables from code.
Actually I am trying to avoid to create a new header as its just few
simple defines.
Thanks
Chin Liang
>
> Thanks,
> Michal
>
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[U-Boot] [PATCH v4 1/2] watchdog/denali: Adding DesignWare watchdog driver support
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See
Cc: Anatolij Gustschin
Cc: Albert Aribaud
Cc: Heiko Schocher
Cc: Tom Rini
---
Changes for v4
- Add 2014 to license header
Changes for v3
- Split to 2 series patch
Changes for v2
- Enable this driver at socfpga_cyclone5 board
---
drivers/watchdog/Makefile |1 +
drivers/watchdog/designware_wdt.c | 73 +
2 files changed, 74 insertions(+)
create mode 100644 drivers/watchdog/designware_wdt.c
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 06ced10..0276a10 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
+obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
new file mode 100644
index 000..6abee81
--- /dev/null
+++ b/drivers/watchdog/designware_wdt.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2013-2014 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#define DW_WDT_CR 0x00
+#define DW_WDT_TORR0x04
+#define DW_WDT_CRR 0x0C
+
+#define DW_WDT_CR_EN_OFFSET0x00
+#define DW_WDT_CR_RMOD_OFFSET 0x01
+#define DW_WDT_CR_RMOD_VAL 0x00
+#define DW_WDT_CRR_RESTART_VAL 0x76
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+int designware_wdt_settimeout(unsigned int timeout)
+{
+ signed int i;
+ /* calculate the timeout range value */
+ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
+ if (i > 15)
+ i = 15;
+ if (i < 0)
+ i = 0;
+
+ writel((i | (i<<4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
+ return 0;
+}
+
+void designware_wdt_enable(void)
+{
+ writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
+ (0x1 << DW_WDT_CR_EN_OFFSET)),
+ (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+}
+
+unsigned int designware_wdt_is_enabled(void)
+{
+ unsigned long val;
+ val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ return val & 0x1;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ if (designware_wdt_is_enabled())
+ /* restart the watchdog counter */
+ writel(DW_WDT_CRR_RESTART_VAL,
+ (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+}
+
+void hw_watchdog_init(void)
+{
+ /* reset to disable the watchdog */
+ hw_watchdog_reset();
+ /* set timer in miliseconds */
+ designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
+ /* enable the watchdog */
+ designware_wdt_enable();
+ /* reset the watchdog */
+ hw_watchdog_reset();
+}
+#endif
--
1.7.9.5
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Re: [U-Boot] [PATCH v3 2/2] socfpga: Adding DesignWare watchdog support
Hi Michal, On Mon, 2014-02-24 at 08:52 +0100, Michal Simek wrote: > On 02/21/2014 09:57 PM, Chin Liang See wrote: > > To enable the DesignWare watchdog support at SOCFPGA Cyclone V > > dev kit. > > > > Signed-off-by: Chin Liang See > > Cc: Anatolij Gustschin > > Cc: Albert Aribaud > > Cc: Heiko Schocher > > Cc: Tom Rini > > --- > > Changes for v3 > > - Split to 2 series patch > > Changes for v2 > > - Enable this driver at socfpga_cyclone5 board > > --- > > .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + > > include/configs/socfpga_cyclone5.h | 13 + > > 2 files changed, 14 insertions(+) > > > > diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > > b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > > index 20f12e0..5f73824 100644 > > --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > > +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > > @@ -11,6 +11,7 @@ > > #define SOCFPGA_UART0_ADDRESS 0xffc02000 > > #define SOCFPGA_UART1_ADDRESS 0xffc03000 > > #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 > > +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 > > #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 > > #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 > > #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 > > diff --git a/include/configs/socfpga_cyclone5.h > > b/include/configs/socfpga_cyclone5.h > > index fc921ee..1b78ccb 100644 > > --- a/include/configs/socfpga_cyclone5.h > > +++ b/include/configs/socfpga_cyclone5.h > > @@ -207,6 +207,16 @@ > > #define CONFIG_ENV_IS_NOWHERE > > > > /* > > + * L4 Watchdog > > + */ > > Why multiline comment here? Oh its just for easy reading. > > > +#define CONFIG_HW_WATCHDOG > > +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 > > +#define CONFIG_DESIGNWARE_WATCHDOG > > +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS > > Why not just use SOCFPGA_L4WD0_ADDRESS directly? Nope, cause this driver might be used by other platform. Thanks Chin Liang > > Thanks, > Michal > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Separate EBV Socrates board from Altera Cyclone 5 board
Hi Pavel, On Mon, 2013-11-11 at 20:26 +0100, ZY - pavel wrote: > Altera Cyclone 5 board is very different board (big, rectangular, > expensive) than EBV Socrates (small, circular, cheap) board. Different > parts are used there, too, but same configuration of u-boot works on > both. Nevertheless, printing wrong name confuses users. > > Therefore this splits the configuration so that u-boot knows they are > different. So far it is only used for correcting the puts, but there > may be other uses in future. > > Signed-off-by: Pavel Machek > Looks good to me. Reviewed-by: Chin Liang See In fact, we already make this change at our git at http://rocketboards.org/gitweb/?p=u-boot-socfpga.git;a=shortlog;h=refs/heads/socfpga_v2013.01.01. Hopefully I can continue to upstream few new patches in coming days. Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Separate EBV Socrates board from Altera Cyclone 5 board
Hi all, On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote: > On 11/12/2013 10:56 AM, Detlev Zundel wrote: > > Hi Michal, > > > >> On 11/11/2013 09:33 PM, Tom Rini wrote: > >>> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: > >>> > Altera Cyclone 5 board is very different board (big, rectangular, > expensive) than EBV Socrates (small, circular, cheap) board. Different > parts are used there, too, but same configuration of u-boot works on > both. Nevertheless, printing wrong name confuses users. > > Therefore this splits the configuration so that u-boot knows they are > different. So far it is only used for correcting the puts, but there > may be other uses in future. > > Signed-off-by: Pavel Machek > >>> > >>> Is there any way at run time to tell which board we are on? > >> > >> Why do you care about board name in general? > > > > We care for board names for a very long time in U-Boot and I'd like to > > keep this. I actually expect a sensible board name on any platform that > > I touch. The board name is an important extra information additional to > > the SoC name. So the question is the other way round - since when do we > > _not_ care about board names? > > There could be i2c memory on board where you can find out this information > but that's > problematic if it is empty or you want to use this i2c for something else. > For all microblaze boards I use XILINX_BOARD_NAME which reflects hw design > (if user is smart enough board name is the part of hw design name). > For zynq/socfpga sensible solution is probably to load this name for DTS. > Currently, the SOCFPGA SPL is customized through a set of handoff files which located at board folders. These handoff files are generated by tools based on board and user design in FPGA. With that, not much decision being made during run time based on the board. With this handoff and tools approach, it will shield off the complexity of hardware configuration and errors (if user change it manually without tools help). Thanks Chin Liang > Thanks, > Michal > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Separate EBV Socrates board from Altera Cyclone 5 board
On Tue, 2013-11-12 at 16:17 +0100, Michal Simek wrote: > On 11/12/2013 03:46 PM, Chin Liang See wrote: > > Hi all, > > > > On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote: > >> On 11/12/2013 10:56 AM, Detlev Zundel wrote: > >>> Hi Michal, > >>> > >>>> On 11/11/2013 09:33 PM, Tom Rini wrote: > >>>>> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: > >>>>> > >>>>>> Altera Cyclone 5 board is very different board (big, rectangular, > >>>>>> expensive) than EBV Socrates (small, circular, cheap) board. Different > >>>>>> parts are used there, too, but same configuration of u-boot works on > >>>>>> both. Nevertheless, printing wrong name confuses users. > >>>>>> > >>>>>> Therefore this splits the configuration so that u-boot knows they are > >>>>>> different. So far it is only used for correcting the puts, but there > >>>>>> may be other uses in future. > >>>>>> > >>>>>> Signed-off-by: Pavel Machek > >>>>> > >>>>> Is there any way at run time to tell which board we are on? > >>>> > >>>> Why do you care about board name in general? > >>> > >>> We care for board names for a very long time in U-Boot and I'd like to > >>> keep this. I actually expect a sensible board name on any platform that > >>> I touch. The board name is an important extra information additional to > >>> the SoC name. So the question is the other way round - since when do we > >>> _not_ care about board names? > >> > >> There could be i2c memory on board where you can find out this information > >> but that's > >> problematic if it is empty or you want to use this i2c for something else. > >> For all microblaze boards I use XILINX_BOARD_NAME which reflects hw design > >> (if user is smart enough board name is the part of hw design name). > >> For zynq/socfpga sensible solution is probably to load this name for DTS. > >> > > > > Currently, the SOCFPGA SPL is customized through a set of handoff files > > which located at board folders. These handoff files are generated by > > tools based on board and user design in FPGA. With that, not much > > decision being made during run time based on the board. With this > > handoff and tools approach, it will shield off the complexity of > > hardware configuration and errors (if user change it manually without > > tools help). Thanks > > Which nice copy of our approach. :-) Hmmm... is it true? This approach being used since few years back at NIOS soft processor. Besides that, we are utilizing the SPL framework for our second stage boot loader. I believe you guys are not using SPL right? It seems you guys would need tools to generate and even build you guys own version of boot loader. It creates high dependency for user to your tools. For our solution, customer can just grab the code from git and build it using the normal U-Boot way (if they don't want to use the tools). With the SPL also, we are taking advantage of open source community power to make our second stage boot loader more powerful and user friendly to user. Our user can grab any drivers or leverage the supports from the open community too. I believe that is the power of open source :) Chin Liang > But anyway I believe that you are also generating one macro which define > name of this configuration based on hw design/board you are using. > And then you can use this macro for showing board/design name in u-boot. > > Thanks, > Michal > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] socfpga: Adding Scan Manager
Adding Scan Manager driver and handoff files. Scan Manager driver will be called to configure the IO buffer setting. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Wolfgang Denk CC: Pavel Machek Cc: Tom Rini Cc: Albert Aribaud Chin Liang See (2): socfpga: Adding Scan Manager driver socfpga: Adding Scan Manager IOCSR handoff files arch/arm/cpu/armv7/socfpga/Makefile|2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 +++ arch/arm/cpu/armv7/socfpga/spl.c |4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + board/altera/socfpga/iocsr_config.c| 653 board/altera/socfpga/iocsr_config.h| 12 + include/configs/socfpga_cyclone5.h |1 + 8 files changed, 1000 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h create mode 100644 board/altera/socfpga/iocsr_config.c create mode 100644 board/altera/socfpga/iocsr_config.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 231
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 97
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
include/configs/socfpga_cyclone5.h |1 +
6 files changed, 335 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..4edc5d4 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..30cbb8b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(&scan_manager_base->stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
+ || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+
+ max_iter--;
+
+ if (max_iter > 0)
+ scanmgr_status = readl(&scan_manager_base->stat);
+ else
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
+ }
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
+}
+
+
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /* De-assert reinit if the IO scan chain is intended for HIO */
+ if (3 == io_scan_chain_id)
+ clrbits_le32(&freeze_controller_base->hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
+ != scan_mgr_io_scan_chain_engine_is_idle(
+ MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
+ return 1;
+ }
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits >>
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+ tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD <<
+ TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+ /* Program IO scan chain in 128-bit iteration */
+ for (i = 0; i < io_program_iter; i++) {
+
+ /* write TDI_TDO packet header to scan manager */
+ writel(tdi_tdo_header, &scan_manager_base->fifodoublebyte);
+
+ /* calculate array index */
+ index = i * 4;
+
+ /* write 4 successive 32-bit IO scan chai
[U-Boot] [PATCH 2/2] socfpga: Adding Scan Manager IOCSR handoff files
The IOCSR handoff files will be consumed by Scan Manager driver.
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
---
board/altera/socfpga/iocsr_config.c | 653 +++
board/altera/socfpga/iocsr_config.h | 12 +
2 files changed, 665 insertions(+)
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/board/altera/socfpga/iocsr_config.c
b/board/altera/socfpga/iocsr_config.c
new file mode 100644
index 000..7e66ff8
--- /dev/null
+++ b/board/altera/socfpga/iocsr_config.c
@@ -0,0 +1,653 @@
+
+/* This file is generated by Preloader Generator */
+
+#include
+
+const unsigned long iocsr_scan_chain0_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+ 0x,
+ 0x,
+ 0x0FF0,
+ 0xC000,
+ 0x003F,
+ 0x8000,
+ 0x00020080,
+ 0x0802,
+ 0x0800,
+ 0x00018020,
+ 0x,
+ 0x4000,
+ 0x00010040,
+ 0x0401,
+ 0x0400,
+ 0x0010,
+ 0x4010,
+ 0x2000,
+ 0x0002,
+ 0x02008000,
+ 0x0200,
+ 0x0008,
+ 0x2008,
+ 0x1000,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+ 0x000C0300,
+ 0x1004,
+ 0x10C0,
+ 0x0040,
+ 0x00010040,
+ 0x8000,
+ 0x0008,
+ 0x1806,
+ 0x1800,
+ 0x0060,
+ 0x00018060,
+ 0x4000,
+ 0x00010040,
+ 0x1000,
+ 0x0400,
+ 0x0010,
+ 0x4010,
+ 0x2000,
+ 0x06008020,
+ 0x02008000,
+ 0x01FE,
+ 0xF800,
+ 0x0007,
+ 0x1000,
+ 0x4010,
+ 0x01004000,
+ 0x0100,
+ 0x3004,
+ 0x1004,
+ 0x0800,
+ 0x,
+ 0x,
+ 0x0080,
+ 0x0002,
+ 0x2000,
+ 0x0400,
+ 0x,
+ 0x00401000,
+ 0x0003,
+ 0x,
+ 0x,
+ 0x0200,
+ 0x00600802,
+ 0x,
+ 0x8020,
+ 0x8600,
+ 0x0200,
+ 0x0100,
+ 0x00300401,
+ 0xC0100400,
+ 0x4010,
+ 0x4300,
+ 0x000C0100,
+ 0x0080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+ 0x80040100,
+ 0x,
+ 0x0FF0,
+ 0x,
+ 0x0C010040,
+ 0x8000,
+ 0x18020080,
+ 0x,
+ 0x0800,
+ 0x00040020,
+ 0x06018060,
+ 0x4000,
+ 0x0C010040,
+ 0x0401,
+ 0x0030,
+ 0x,
+ 0x03004010,
+ 0x2000,
+ 0x06008020,
+ 0x02008000,
+ 0x0218,
+ 0x6008,
+ 0x01802008,
+ 0x1000,
+ 0x03004010,
+ 0x01004000,
+ 0x010C,
+ 0x3004,
+ 0x00C01004,
+ 0x0800,
+};
+
+const unsigned long iocsr_scan_chain3_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+ 0x2C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x0790,
+ 0x0802,
+ 0x0010,
+ 0x0A80,
+ 0x0790,
+ 0x0802,
+ 0x0010,
+ 0xC880,
+ 0x3001,
+ 0x00C00722,
+ 0x,
+ 0x0021,
+ 0x8204,
+ 0x0540,
+ 0x03C8,
+ 0x0401,
+ 0x0008,
+ 0x0540,
+ 0x03C8,
+ 0x0540,
+ 0x03C8,
+ 0xE440,
+ 0x1800,
+ 0x00600391,
+ 0x800E4400,
+ 0x0001,
+ 0x4002,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x7220,
+ 0x8C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C88,
+ 0x2300,
+ 0x0004,
+ 0x5067,
+ 0x0070,
+ 0x2459,
+ 0x1000,
+ 0xA034,
+ 0x0D01,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D,
+ 0x24906808,
+ 0x00A28340,
+ 0xD01A,
+ 0x06808A20,
+ 0x1004,
+ 0x0020,
+ 0x1004,
+ 0x0020,
+ 0x1500,
+ 0x0F20,
+ 0x1500,
+ 0x0F20,
+ 0x01FE,
+ 0x,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x,
+ 0x0A81,
+ 0x0790,
+ 0x0A80,
+ 0x0790,
+ 0x0A80,
+ 0x0790
[U-Boot] [RESEND PATCH v4 1/1] socfpga: Adding Freeze Controller driver
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Dinh Nguyen
Cc: Tom Rini
Cc: Albert Aribaud
---
Changes for v4
- Removed additional lines
- Single function call to freeze and thaw all channels
Changes for v3
- Removed unused macro in freeze_controller.h
Changes for v2
- Removed FREEZE_CONTROLLER_FSM_HW
- Removed the get_timer_count_masked and convert to use delay in us
- Used shorter local variables
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/freeze_controller.c | 216
arch/arm/cpu/armv7/socfpga/spl.c |9 +
.../include/asm/arch-socfpga/freeze_controller.h | 50 +
4 files changed, 276 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/freeze_controller.c
create mode 100644 arch/arm/include/asm/arch-socfpga/freeze_controller.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index dac2bbd..3e84a0c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c
b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
new file mode 100644
index 000..330b4aa
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Default state from cold reset is FREEZE_ALL; the global
+ * flag is set to TRUE to indicate the IO banks are frozen
+ */
+static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
+ = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
+ FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
+
+/* Freeze HPS IOs */
+void sys_mgr_frzctrl_freeze_req(void)
+{
+ u32 ioctrl_reg_offset;
+ u32 reg_value;
+ u32 reg_cfg_mask;
+ u32 channel_id;
+
+ /* select software FSM */
+ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
+
+ /* Freeze channel 0 to 2 */
+ for (channel_id = 0; channel_id <= 2; channel_id++) {
+ ioctrl_reg_offset = (u32)(
+ &freeze_controller_base->vioctrl +
+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+ /*
+* Assert active low enrnsl, plniotri
+* and niotri signals
+*/
+ reg_cfg_mask =
+ SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
+ | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+ | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+ clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
+
+ /*
+* Note: Delay for 20ns at min
+* Assert active low bhniotri signal and de-assert
+* active high csrdone
+*/
+ reg_cfg_mask
+ = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+ | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+ clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
+
+ /* Set global flag to indicate channel is frozen */
+ frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+ }
+
+ /* Freeze channel 3 */
+ /*
+* Assert active low enrnsl, plniotri and
+* niotri signals
+*/
+ reg_cfg_mask
+ = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+ clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+ /*
+* assert active low bhniotri & nfrzdrv signals,
+* de-assert active high csrdone and assert
+* active high frzreg and nfrzdrv signals
+*/
+ reg_value = readl(&freeze_controller_base->hioctrl);
+ reg_cfg_mask
+ = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
+ reg_value
+ = (reg_value & ~reg_cfg_mask)
+ | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+ writel(reg_value, &freeze_controller_base->hioctrl);
+
+ /*
+* assert active hig
Re: [U-Boot] [PATCH] Separate EBV Socrates board from Altera Cyclone 5 board
Hi, > > >>> > >>> Currently, the SOCFPGA SPL is customized through a set of handoff files > >>> which located at board folders. These handoff files are generated by > >>> tools based on board and user design in FPGA. With that, not much > >>> decision being made during run time based on the board. With this > >>> handoff and tools approach, it will shield off the complexity of > >>> hardware configuration and errors (if user change it manually without > >>> tools help). Thanks > >> > >> Which nice copy of our approach. :-) > > > > Hmmm... is it true? This approach being used since few years back at > > NIOS soft processor. Besides that, we are utilizing the SPL framework > > for our second stage boot loader. I believe you guys are not using SPL > > right? It seems you guys would need tools to generate and even build you > > guys own version of boot loader. It creates high dependency for user to > > your tools. > > Interesting discussion. :-) > I believe we will use SPL at some point in future for Microblaze > just because of easier maintenance . But will see. Yup, utilizing SPL will gain you the power of open source :) > > I don't understand your point regarding to tool dependency. For DTSes > I believe you are also generating this structure from design tools > or you can write it by hand. > We are also generating U-boot configuration but if someone wants to write > it by hand they can. I believe we have misalignment on the term used. For us, second stage bootloader is referring to the bootloader loaded by BootROM. I believe you guys are referring that as FSBL. > > For our solution, customer can just grab the code from git and build it > > using the normal U-Boot way (if they don't want to use the tools). With > > the SPL also, we are taking advantage of open source community power to > > make our second stage boot loader more powerful and user friendly to > > user. Our user can grab any drivers or leverage the supports from the > > open community too. I believe that is the power of open source :) > > We have the same for Microblaze and Zynq. Same as above, I believe both of us are using U-Boot. But for bootloader before U-Boot, we are using SPL while you guys using FSBL which is not SPL framework, right? With that, I believe you guys would need a proprietary tools to compile and build the FSBL. We would not have this dependency when building the SPL code. Thanks Chin Liang > > Cheers, > Michal > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] socfpga: Adding Freeze Controller driver
Hi Albert On Mon, 2013-12-02 at 18:15 +0100, ZY - albert.u.boot wrote: > Hi Chin Liang, > > On Tue, 1 Oct 2013 13:42:20 -0500, Chin Liang See > wrote: > > > Hi guys, > > > > Any further comments on this? Thanks > > None from me, and I would happily apply it except it does not apply > cleanly any more on ARM. Can you rebase and re-send? Sure I already re-based it and will send it out after this email. Thanks again for your helps. Chin Liang > > > Chin Liang > > Amicalement, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5] socfpga: Adding Freeze Controller driver
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Dinh Nguyen
Cc: Tom Rini
Cc: Albert Aribaud
---
Changes for v5
- Rebase with latest v2014.01-rc1
Changes for v4
- Removed additional lines
- Single function call to freeze and thaw all channels
Changes for v3
- Removed unused macro in freeze_controller.h
Changes for v2
- Removed FREEZE_CONTROLLER_FSM_HW
- Removed the get_timer_count_masked and convert to use delay in us
- Used shorter local variables
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/freeze_controller.c | 216
arch/arm/cpu/armv7/socfpga/spl.c |9 +
.../include/asm/arch-socfpga/freeze_controller.h | 50 +
4 files changed, 276 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/freeze_controller.c
create mode 100644 arch/arm/include/asm/arch-socfpga/freeze_controller.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index dac2bbd..3e84a0c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c
b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
new file mode 100644
index 000..330b4aa
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Default state from cold reset is FREEZE_ALL; the global
+ * flag is set to TRUE to indicate the IO banks are frozen
+ */
+static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
+ = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
+ FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
+
+/* Freeze HPS IOs */
+void sys_mgr_frzctrl_freeze_req(void)
+{
+ u32 ioctrl_reg_offset;
+ u32 reg_value;
+ u32 reg_cfg_mask;
+ u32 channel_id;
+
+ /* select software FSM */
+ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
+
+ /* Freeze channel 0 to 2 */
+ for (channel_id = 0; channel_id <= 2; channel_id++) {
+ ioctrl_reg_offset = (u32)(
+ &freeze_controller_base->vioctrl +
+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+ /*
+* Assert active low enrnsl, plniotri
+* and niotri signals
+*/
+ reg_cfg_mask =
+ SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
+ | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+ | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+ clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
+
+ /*
+* Note: Delay for 20ns at min
+* Assert active low bhniotri signal and de-assert
+* active high csrdone
+*/
+ reg_cfg_mask
+ = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+ | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+ clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
+
+ /* Set global flag to indicate channel is frozen */
+ frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+ }
+
+ /* Freeze channel 3 */
+ /*
+* Assert active low enrnsl, plniotri and
+* niotri signals
+*/
+ reg_cfg_mask
+ = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+ clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+ /*
+* assert active low bhniotri & nfrzdrv signals,
+* de-assert active high csrdone and assert
+* active high frzreg and nfrzdrv signals
+*/
+ reg_value = readl(&freeze_controller_base->hioctrl);
+ reg_cfg_mask
+ = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
+ reg_value
+ = (reg_value & ~reg_cfg_mask)
+ | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
+ | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+ writel(reg_value, &freeze_controller_base->hioctrl
[U-Boot] [PATCH 0/2 v2] socfpga: Adding Scan Manager
Adding Scan Manager driver and handoff files. Scan Manager driver will be called to configure the IO buffer setting. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Wolfgang Denk CC: Pavel Machek Cc: Tom Rini Cc: Albert Aribaud --- Changes for v2 - Rebase with latest v2014.01-rc1 Chin Liang See (2): socfpga: Adding Scan Manager driver socfpga: Adding Scan Manager IOCSR handoff files arch/arm/cpu/armv7/socfpga/Makefile|2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 +++ arch/arm/cpu/armv7/socfpga/spl.c |4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + board/altera/socfpga/iocsr_config.c| 653 board/altera/socfpga/iocsr_config.h| 12 + include/configs/socfpga_cyclone5.h |1 + 8 files changed, 1000 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h create mode 100644 board/altera/socfpga/iocsr_config.c create mode 100644 board/altera/socfpga/iocsr_config.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] socfpga: Adding Scan Manager IOCSR handoff files
The IOCSR handoff files will be consumed by Scan Manager driver.
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
Signed-off-by: Chin Liang See
---
Changes for v2
- rebase with latest v2014.01-rc1
---
board/altera/socfpga/iocsr_config.c | 653 +++
board/altera/socfpga/iocsr_config.h | 12 +
2 files changed, 665 insertions(+)
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/board/altera/socfpga/iocsr_config.c
b/board/altera/socfpga/iocsr_config.c
new file mode 100644
index 000..7e66ff8
--- /dev/null
+++ b/board/altera/socfpga/iocsr_config.c
@@ -0,0 +1,653 @@
+
+/* This file is generated by Preloader Generator */
+
+#include
+
+const unsigned long iocsr_scan_chain0_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+ 0x,
+ 0x,
+ 0x0FF0,
+ 0xC000,
+ 0x003F,
+ 0x8000,
+ 0x00020080,
+ 0x0802,
+ 0x0800,
+ 0x00018020,
+ 0x,
+ 0x4000,
+ 0x00010040,
+ 0x0401,
+ 0x0400,
+ 0x0010,
+ 0x4010,
+ 0x2000,
+ 0x0002,
+ 0x02008000,
+ 0x0200,
+ 0x0008,
+ 0x2008,
+ 0x1000,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+ 0x000C0300,
+ 0x1004,
+ 0x10C0,
+ 0x0040,
+ 0x00010040,
+ 0x8000,
+ 0x0008,
+ 0x1806,
+ 0x1800,
+ 0x0060,
+ 0x00018060,
+ 0x4000,
+ 0x00010040,
+ 0x1000,
+ 0x0400,
+ 0x0010,
+ 0x4010,
+ 0x2000,
+ 0x06008020,
+ 0x02008000,
+ 0x01FE,
+ 0xF800,
+ 0x0007,
+ 0x1000,
+ 0x4010,
+ 0x01004000,
+ 0x0100,
+ 0x3004,
+ 0x1004,
+ 0x0800,
+ 0x,
+ 0x,
+ 0x0080,
+ 0x0002,
+ 0x2000,
+ 0x0400,
+ 0x,
+ 0x00401000,
+ 0x0003,
+ 0x,
+ 0x,
+ 0x0200,
+ 0x00600802,
+ 0x,
+ 0x8020,
+ 0x8600,
+ 0x0200,
+ 0x0100,
+ 0x00300401,
+ 0xC0100400,
+ 0x4010,
+ 0x4300,
+ 0x000C0100,
+ 0x0080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+ 0x80040100,
+ 0x,
+ 0x0FF0,
+ 0x,
+ 0x0C010040,
+ 0x8000,
+ 0x18020080,
+ 0x,
+ 0x0800,
+ 0x00040020,
+ 0x06018060,
+ 0x4000,
+ 0x0C010040,
+ 0x0401,
+ 0x0030,
+ 0x,
+ 0x03004010,
+ 0x2000,
+ 0x06008020,
+ 0x02008000,
+ 0x0218,
+ 0x6008,
+ 0x01802008,
+ 0x1000,
+ 0x03004010,
+ 0x01004000,
+ 0x010C,
+ 0x3004,
+ 0x00C01004,
+ 0x0800,
+};
+
+const unsigned long iocsr_scan_chain3_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+ 0x2C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x0790,
+ 0x0802,
+ 0x0010,
+ 0x0A80,
+ 0x0790,
+ 0x0802,
+ 0x0010,
+ 0xC880,
+ 0x3001,
+ 0x00C00722,
+ 0x,
+ 0x0021,
+ 0x8204,
+ 0x0540,
+ 0x03C8,
+ 0x0401,
+ 0x0008,
+ 0x0540,
+ 0x03C8,
+ 0x0540,
+ 0x03C8,
+ 0xE440,
+ 0x1800,
+ 0x00600391,
+ 0x800E4400,
+ 0x0001,
+ 0x4002,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x02A0,
+ 0x01E4,
+ 0x7220,
+ 0x8C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C88,
+ 0x2300,
+ 0x0004,
+ 0x5067,
+ 0x0070,
+ 0x2459,
+ 0x1000,
+ 0xA034,
+ 0x0D01,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D,
+ 0x24906808,
+ 0x00A28340,
+ 0xD01A,
+ 0x06808A20,
+ 0x1004,
+ 0x0020,
+ 0x1004,
+ 0x0020,
+ 0x1500,
+ 0x0F20,
+ 0x1500,
+ 0x0F20,
+ 0x01FE,
+ 0x,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x,
+ 0x0A81,
+ 0x0790
[U-Boot] [PATCH v2 1/2] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
Signed-off-by: Chin Liang See
---
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 231
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 97
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
include/configs/socfpga_cyclone5.h |1 +
6 files changed, 335 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3e84a0c..4edc5d4 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..30cbb8b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(&scan_manager_base->stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
+ || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+
+ max_iter--;
+
+ if (max_iter > 0)
+ scanmgr_status = readl(&scan_manager_base->stat);
+ else
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE;
+ }
+ return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE;
+}
+
+
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /* De-assert reinit if the IO scan chain is intended for HIO */
+ if (3 == io_scan_chain_id)
+ clrbits_le32(&freeze_controller_base->hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
+ != scan_mgr_io_scan_chain_engine_is_idle(
+ MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
+ return 1;
+ }
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits >>
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+ tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD <<
+ TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+ /* Program IO scan chain in 128-bit iteration */
+ for (i = 0; i < io_program_iter; i++) {
+
+ /* write TDI_TDO packet header to scan manager */
+ writel(tdi_tdo_header, &scan_manager_base->fifodoublebyte);
+
+ /* calculate array index */
+ index = i * 4;
+
+
Re: [U-Boot] [PATCH 0/2 v2] socfpga: Adding Scan Manager
Hi Albert, Can you help to apply this patches as I believe there are not further comments on this? Thanks and have a nice day! Chin Liang On Mon, 2013-12-02 at 14:31 -0600, Chin Liang See wrote: > Adding Scan Manager driver and handoff files. Scan Manager driver > will be called to configure the IO buffer setting. > > Signed-off-by: Chin Liang See > Cc: Dinh Nguyen > Cc: Wolfgang Denk > CC: Pavel Machek > Cc: Tom Rini > Cc: Albert Aribaud > --- > Changes for v2 > - Rebase with latest v2014.01-rc1 > > Chin Liang See (2): > socfpga: Adding Scan Manager driver > socfpga: Adding Scan Manager IOCSR handoff files > > arch/arm/cpu/armv7/socfpga/Makefile|2 +- > arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 +++ > arch/arm/cpu/armv7/socfpga/spl.c |4 + > arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++ > .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + > board/altera/socfpga/iocsr_config.c| 653 > > board/altera/socfpga/iocsr_config.h| 12 + > include/configs/socfpga_cyclone5.h |1 + > 8 files changed, 1000 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c > create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h > create mode 100644 board/altera/socfpga/iocsr_config.c > create mode 100644 board/altera/socfpga/iocsr_config.h > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mmc/dwmmc: Using calloc instead malloc
To enhance the SDMMC DesignWare driver to use calloc instead of
malloc. This will avoid the incident that uninitialized members
of mmc structure are later used for NULL comparison.
Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Mischa Jonker
Cc: Alexey Brodkin
Cc: Andy Fleming
---
drivers/mmc/dw_mmc.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
mode change 100644 => 100755 drivers/mmc/dw_mmc.c
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
old mode 100644
new mode 100755
index 19d9b0b..82abe19
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -336,9 +336,9 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32
min_clk)
struct mmc *mmc;
int err = 0;
- mmc = malloc(sizeof(struct mmc));
+ mmc = calloc(sizeof(struct mmc), 1);
if (!mmc) {
- printf("mmc malloc fail!\n");
+ printf("mmc calloc fail!\n");
return -1;
}
--
1.7.9.5
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[U-Boot] [PATCH] socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA
To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)
Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Andy Fleming
---
arch/arm/include/asm/arch-socfpga/dwmmc.h | 12 +
drivers/mmc/Makefile |1 +
drivers/mmc/socfpga_dw_mmc.c | 72 +
3 files changed, 85 insertions(+)
create mode 100755 arch/arm/include/asm/arch-socfpga/dwmmc.h
create mode 100755 drivers/mmc/socfpga_dw_mmc.c
diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h
b/arch/arm/include/asm/arch-socfpga/dwmmc.h
new file mode 100755
index 000..945eb64
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/dwmmc.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef_SOCFPGA_DWMMC_H_
+#define_SOCFPGA_DWMMC_H_
+
+extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index);
+
+#endif /* _SOCFPGA_SDMMC_H_ */
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1ed26ca..e793ed9 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
obj-$(CONFIG_DWMMC) += dw_mmc.o
obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
+obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
else
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
new file mode 100755
index 000..554f51b
--- /dev/null
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#define CLKMGR_PERPLLGRP_EN_REG(SOCFPGA_CLKMGR_ADDRESS + 0xA0)
+#define CLKMGR_SDMMC_CLK_ENABLE(1 << 8)
+#define SYSMGR_SDMMCGRP_CTRL_REG (SOCFPGA_SYSMGR_ADDRESS + 0x108)
+#define SYSMGR_SDMMC_CTRL_GET_DRVSEL(x)(((x) >> 0) & 0x7)
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+ drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+
+static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
+
+static void socfpga_dwmci_clksel(struct dwmci_host *host)
+{
+ unsigned int en;
+ unsigned int drvsel;
+ unsigned int smplsel;
+
+ /* Disable SDMMC clock. */
+ en = readl(CLKMGR_PERPLLGRP_EN_REG);
+ en &= ~CLKMGR_SDMMC_CLK_ENABLE;
+ writel(en, CLKMGR_PERPLLGRP_EN_REG);
+
+ /* Configures drv_sel and smpl_sel */
+ drvsel = 3;
+ smplsel = 0;
+
+ debug("%s: drvsel %d smplsel %d\n", __FUNCTION__, drvsel, smplsel);
+ writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
+ SYSMGR_SDMMCGRP_CTRL_REG);
+
+ debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __FUNCTION__,
+ readl(SYSMGR_SDMMCGRP_CTRL_REG));
+ /* Enable SDMMC clock */
+ en = readl(CLKMGR_PERPLLGRP_EN_REG);
+ en |= CLKMGR_SDMMC_CLK_ENABLE;
+ writel(en, CLKMGR_PERPLLGRP_EN_REG);
+}
+
+int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
+{
+ struct dwmci_host *host = NULL;
+ host = calloc(sizeof(struct dwmci_host), 1);
+ if (!host) {
+ printf("dwmci_host calloc fail!\n");
+ return 1;
+ }
+
+ host->name = SOCFPGA_NAME;
+ host->ioaddr = (void *)regbase;
+ host->buswidth = bus_width;
+ host->clksel = socfpga_dwmci_clksel;
+ host->dev_index = index;
+ /* fixed clock divide by 4 which due to the SDMMC wrapper */
+ host->bus_hz = CONFIG_DWMMC_BUS_HZ;
+ host->fifoth_val = MSIZE(0x2) |
+ RX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2 - 1) |
+ TX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2);
+
+ add_dwmci(host, host->bus_hz, 40);
+
+ return 0;
+}
+
--
1.7.9.5
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[U-Boot] [PATCH v2] socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA
To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)
Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Andy Fleming
Cc: Pantelis Antoniou
---
Changes for v2
- Adding u-boot-mmc maintainer
---
arch/arm/include/asm/arch-socfpga/dwmmc.h | 12 +
drivers/mmc/Makefile |1 +
drivers/mmc/socfpga_dw_mmc.c | 72 +
3 files changed, 85 insertions(+)
create mode 100755 arch/arm/include/asm/arch-socfpga/dwmmc.h
create mode 100755 drivers/mmc/socfpga_dw_mmc.c
diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h
b/arch/arm/include/asm/arch-socfpga/dwmmc.h
new file mode 100755
index 000..945eb64
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/dwmmc.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef_SOCFPGA_DWMMC_H_
+#define_SOCFPGA_DWMMC_H_
+
+extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index);
+
+#endif /* _SOCFPGA_SDMMC_H_ */
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1ed26ca..e793ed9 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
obj-$(CONFIG_DWMMC) += dw_mmc.o
obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
+obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
else
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
new file mode 100755
index 000..554f51b
--- /dev/null
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#define CLKMGR_PERPLLGRP_EN_REG(SOCFPGA_CLKMGR_ADDRESS + 0xA0)
+#define CLKMGR_SDMMC_CLK_ENABLE(1 << 8)
+#define SYSMGR_SDMMCGRP_CTRL_REG (SOCFPGA_SYSMGR_ADDRESS + 0x108)
+#define SYSMGR_SDMMC_CTRL_GET_DRVSEL(x)(((x) >> 0) & 0x7)
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+ drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+
+static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
+
+static void socfpga_dwmci_clksel(struct dwmci_host *host)
+{
+ unsigned int en;
+ unsigned int drvsel;
+ unsigned int smplsel;
+
+ /* Disable SDMMC clock. */
+ en = readl(CLKMGR_PERPLLGRP_EN_REG);
+ en &= ~CLKMGR_SDMMC_CLK_ENABLE;
+ writel(en, CLKMGR_PERPLLGRP_EN_REG);
+
+ /* Configures drv_sel and smpl_sel */
+ drvsel = 3;
+ smplsel = 0;
+
+ debug("%s: drvsel %d smplsel %d\n", __FUNCTION__, drvsel, smplsel);
+ writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
+ SYSMGR_SDMMCGRP_CTRL_REG);
+
+ debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __FUNCTION__,
+ readl(SYSMGR_SDMMCGRP_CTRL_REG));
+ /* Enable SDMMC clock */
+ en = readl(CLKMGR_PERPLLGRP_EN_REG);
+ en |= CLKMGR_SDMMC_CLK_ENABLE;
+ writel(en, CLKMGR_PERPLLGRP_EN_REG);
+}
+
+int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
+{
+ struct dwmci_host *host = NULL;
+ host = calloc(sizeof(struct dwmci_host), 1);
+ if (!host) {
+ printf("dwmci_host calloc fail!\n");
+ return 1;
+ }
+
+ host->name = SOCFPGA_NAME;
+ host->ioaddr = (void *)regbase;
+ host->buswidth = bus_width;
+ host->clksel = socfpga_dwmci_clksel;
+ host->dev_index = index;
+ /* fixed clock divide by 4 which due to the SDMMC wrapper */
+ host->bus_hz = CONFIG_DWMMC_BUS_HZ;
+ host->fifoth_val = MSIZE(0x2) |
+ RX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2 - 1) |
+ TX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2);
+
+ add_dwmci(host, host->bus_hz, 40);
+
+ return 0;
+}
+
--
1.7.9.5
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[U-Boot] [PATCH v2] mmc/dwmmc: Using calloc instead malloc
To enhance the SDMMC DesignWare driver to use calloc instead of
malloc. This will avoid the incident that uninitialized members
of mmc structure are later used for NULL comparison.
Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Mischa Jonker
Cc: Alexey Brodkin
Cc: Andy Fleming
Cc: Pantelis Antoniou
---
Changes for v2
- Adding u-boot-mmc maintainer
---
drivers/mmc/dw_mmc.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
mode change 100644 => 100755 drivers/mmc/dw_mmc.c
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
old mode 100644
new mode 100755
index 19d9b0b..82abe19
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -336,9 +336,9 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32
min_clk)
struct mmc *mmc;
int err = 0;
- mmc = malloc(sizeof(struct mmc));
+ mmc = calloc(sizeof(struct mmc), 1);
if (!mmc) {
- printf("mmc malloc fail!\n");
+ printf("mmc calloc fail!\n");
return -1;
}
--
1.7.9.5
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[U-Boot] [PATCH] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
To add the Cadence SPI driver support for Altera SOCFPGA. It
required information such as clocks and timing from platform's
configuration header file within include/configs folder
Signed-off-by: Chin Liang See
Cc: Jagannadha Sutradharudu Teki
---
drivers/spi/Makefile |1 +
drivers/spi/cadence_qspi.c | 337
drivers/spi/cadence_qspi.h | 56 +++
drivers/spi/cadence_qspi_apb.c | 873
4 files changed, 1267 insertions(+)
create mode 100644 drivers/spi/cadence_qspi.c
create mode 100644 drivers/spi/cadence_qspi.h
create mode 100644 drivers/spi/cadence_qspi_apb.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ed4ecd7..838e6ca 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
new file mode 100644
index 000..e2bf39f
--- /dev/null
+++ b/drivers/spi/cadence_qspi.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright (C) Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include "cadence_qspi.h"
+
+#define CQSPI_STIG_READ0
+#define CQSPI_STIG_WRITE 1
+#define CQSPI_INDIRECT_READ2
+#define CQSPI_INDIRECT_WRITE 3
+
+static int qspi_is_init;
+static unsigned int qspi_calibrated_hz;
+static unsigned int qspi_calibrated_cs;
+
+struct cadence_qspi_slave {
+ struct spi_slave slave;
+ unsigned intmode;
+ unsigned intmax_hz;
+ void*regbase;
+ void*ahbbase;
+ size_t cmd_len;
+ u8 cmd_buf[32];
+ size_t data_len;
+};
+
+#define to_cadence_qspi_slave(s) \
+ container_of(s, struct cadence_qspi_slave, slave)
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave);
+ void *base = cadence_qspi->regbase;
+
+ cadence_qspi_apb_config_baudrate_div(base, CONFIG_CQSPI_REF_CLK, hz);
+
+ /* Reconfigure delay timing if speed is changed. */
+ cadence_qspi_apb_delay(base, CONFIG_CQSPI_REF_CLK, hz,
+ CONFIG_CQSPI_TSHSL_NS, CONFIG_CQSPI_TSD2D_NS,
+ CONFIG_CQSPI_TCHSH_NS, CONFIG_CQSPI_TSLCH_NS);
+ return;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct cadence_qspi_slave *cadence_qspi;
+
+ debug("%s: bus %d cs %d max_hz %dMHz mode %d\n", __func__,
+ bus, cs, max_hz/100, mode);
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ cadence_qspi = malloc(sizeof(struct cadence_qspi_slave));
+ if (!cadence_qspi) {
+ printf("QSPI: Can't allocate struct cadence_qspi_slave. "
+ "Bus %d cs %d\n", bus, cs);
+ return NULL;
+ }
+
+ cadence_qspi->slave.bus = bus;
+ cadence_qspi->slave.cs = cs;
+ cadence_qspi->mode = mode;
+ cadence_qspi->max_hz = max_hz;
+ cadence_qspi->regbase = (void *)QSPI_BASE;
+ cadence_qspi->ahbbase = (void *)QSPI_AHB_BASE;
+
+ if (!qspi_is_init)
+ spi_init();
+
+ return &cadence_qspi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave);
+ free(cadence_qspi);
+ return;
+}
+
+void spi_init(void)
+{
+ cadence_qspi_apb_controller_init((void *)QSPI_BASE);
+ qspi_is_init = 1;
+ return;
+}
+
+/* calibration sequence to determine the read data capture delay register */
+int spi_calibration(struct spi_slave *slave)
+{
+ struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave);
+ void *base = cadence_qspi->regbase;
+ u8 opcode_rdid = 0x9F;
+ unsigned int idcode = 0, temp = 0;
+ int err = 0, i, range_lo = -1, range_hi = -1;
+
+ /* start with slowest clock (1 MHz) */
+ spi_set_speed(slave, 100);
+
+ /* configure the read data capture delay register to 0 */
+ cadence_qspi_apb_readdata_capture(base, 1, 0);
+
+ /* Enable QSPI */
+ cadence_qspi_apb_controller_enable(base);
+
+ /* read the ID which will be our golden value */
+ err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
+ 3, (u8 *)&idcode);
+ if (e
[U-Boot] [PATCH] nand/denali: Adding Denali NAND driver support
To add the Denali NAND driver support into U-Boot. It required
information such as register base address from configuration
header file within include/configs folder.
Signed-off-by: Chin Liang See
Cc: Artem Bityutskiy
Cc: David Woodhouse
Cc: Brian Norris
Cc: Scott Wood
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/denali_nand.c | 1166
drivers/mtd/nand/denali_nand.h | 501 +
3 files changed, 1668 insertions(+)
create mode 100644 drivers/mtd/nand/denali_nand.c
create mode 100644 drivers/mtd/nand/denali_nand.h
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 02b149c..24e8218 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
+obj-$(CONFIG_NAND_DENALI) += denali_nand.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
diff --git a/drivers/mtd/nand/denali_nand.c b/drivers/mtd/nand/denali_nand.c
new file mode 100644
index 000..55246c9
--- /dev/null
+++ b/drivers/mtd/nand/denali_nand.c
@@ -0,0 +1,1166 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#include "denali_nand.h"
+
+/* We define a module parameter that allows the user to override
+ * the hardware and decide what timing mode should be used.
+ */
+#define NAND_DEFAULT_TIMINGS -1
+
+static struct denali_nand_info denali;
+static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
+
+/* We define a macro here that combines all interrupts this driver uses into
+ * a single constant value, for convenience. */
+#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
+ INTR_STATUS__ECC_TRANSACTION_DONE | \
+ INTR_STATUS__ECC_ERR | \
+ INTR_STATUS__PROGRAM_FAIL | \
+ INTR_STATUS__LOAD_COMP | \
+ INTR_STATUS__PROGRAM_COMP | \
+ INTR_STATUS__TIME_OUT | \
+ INTR_STATUS__ERASE_FAIL | \
+ INTR_STATUS__RST_COMP | \
+ INTR_STATUS__ERASE_COMP | \
+ INTR_STATUS__ECC_UNCOR_ERR | \
+ INTR_STATUS__INT_ACT | \
+ INTR_STATUS__LOCKED_BLK)
+
+/* indicates whether or not the internal value for the flash bank is
+ * valid or not */
+#define CHIP_SELECT_INVALID-1
+
+#define SUPPORT_8BITECC1
+
+/* This macro divides two integers and rounds fractional values up
+ * to the nearest integer value. */
+#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
+
+/* These constants are defined by the driver to enable common driver
+ * configuration options. */
+#define SPARE_ACCESS 0x41
+#define MAIN_ACCESS0x42
+#define MAIN_SPARE_ACCESS 0x43
+
+#define DENALI_UNLOCK_START0x10
+#define DENALI_UNLOCK_END 0x11
+#define DENALI_LOCK0x21
+#define DENALI_LOCK_TIGHT 0x31
+#define DENALI_BUFFER_LOAD 0x60
+#define DENALI_BUFFER_WRITE0x62
+
+#define DENALI_READ0
+#define DENALI_WRITE 0x100
+
+/* types of device accesses. We can issue commands and get status */
+#define COMMAND_CYCLE 0
+#define ADDR_CYCLE 1
+#define STATUS_CYCLE 2
+
+/* this is a helper macro that allows us to
+ * format the bank into the proper bits for the controller */
+#define BANK(x) ((x) << 24)
+
+/* Interrupts are cleared by writing a 1 to the appropriate status bit */
+static inline void clear_interrupt(uint32_t irq_mask)
+{
+ uint32_t intr_status_reg = 0;
+ intr_status_reg = INTR_STATUS(denali.flash_bank);
+ __raw_writel(irq_mask, denali.flash_reg + intr_status_reg);
+}
+
+static uint32_t read_interrupt_status(void)
+{
+ uint32_t intr_status_reg = 0;
+ intr_status_reg = INTR_STATUS(denali.flash_bank);
+ return __raw_readl(denali.flash_reg + intr_status_reg);
+}
+
+static void clear_interrupts(void)
+{
+ uint32_t status = 0x0;
+ status = read_interrupt_status();
+ clear_interrupt(status);
+ denali.irq_status = 0x0;
+}
+
+static void denali_irq_enable(uint32_t int_mask)
+{
+ int i;
+ for (i = 0; i < denali.max_banks; ++i)
+ __raw_writel(int_mask, denali.flash_reg + INTR_EN(i));
+}
+
+static uint32_t wait_for_irq(uint32_t irq_mask)
+{
+ unsigned long comp_res = 1000;
+ uint32_t intr_status = 0;
+
+ do {
+ intr_status = read_interrupt_status() & DENALI_IRQ_ALL;
+ if (intr_status & irq_mask) {
+ denali.irq_status &= ~irq_mask;
[U-Boot] [PATCH] watchdog/denali: Adding DesignWare watchdog driver support
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See
Cc: Anatolij Gustschin
Cc: Albert Aribaud
Cc: Heiko Schocher
Cc: Tom Rini
---
drivers/watchdog/Makefile |1 +
drivers/watchdog/designware_wdt.c | 75 +
2 files changed, 76 insertions(+)
create mode 100644 drivers/watchdog/designware_wdt.c
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 06ced10..0276a10 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
+obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
new file mode 100644
index 000..c3b14f5
--- /dev/null
+++ b/drivers/watchdog/designware_wdt.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#define DW_WDT_CR 0x00
+#define DW_WDT_TORR0x04
+#define DW_WDT_CRR 0x0C
+
+#define DW_WDT_CR_EN_OFFSET0x00
+#define DW_WDT_CR_RMOD_OFFSET 0x01
+#define DW_WDT_CR_RMOD_VAL 0x00
+#define DW_WDT_CRR_RESTART_VAL 0x76
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+int designware_wdt_settimeout(unsigned int timeout)
+{
+ signed int i;
+ /* calculate the timeout range value */
+ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ))\
+ - 16;
+ if (i > 15)
+ i = 15;
+ if (i < 0)
+ i = 0;
+
+ writel((i | (i<<4)),
+ (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
+ return 0;
+}
+
+void designware_wdt_enable(void)
+{
+ writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | \
+ (0x1 << DW_WDT_CR_EN_OFFSET)),
+ (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+}
+
+unsigned int designware_wdt_is_enabled(void)
+{
+ unsigned long val;
+ val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ return val & 0x1;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ if (designware_wdt_is_enabled())
+ /* restart the watchdog counter */
+ writel(DW_WDT_CRR_RESTART_VAL,
+ (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+}
+
+void hw_watchdog_init(void)
+{
+ /* reset to disable the watchdog */
+ hw_watchdog_reset();
+ /* set timer in miliseconds */
+ designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
+ /* enable the watchdog */
+ designware_wdt_enable();
+ /* reset the watchdog */
+ hw_watchdog_reset();
+}
+#endif
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] socfpga: Adding Clock Manager
Adding Clock Manager driver and handoff files. Clock Manager driver will be called to configure the all the clocks setting. Chin Liang See (2): socfpga: Adding Clock Manager driver socfpga: Adding Clock Manager handoff file arch/arm/cpu/armv7/socfpga/Makefile|2 +- arch/arm/cpu/armv7/socfpga/clock_manager.c | 378 arch/arm/cpu/armv7/socfpga/spl.c | 90 + arch/arm/include/asm/arch-socfpga/clock_manager.h | 205 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + board/altera/socfpga/pll_config.h | 115 ++ include/configs/socfpga_cyclone5.h |1 + 7 files changed, 791 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/clock_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/clock_manager.h create mode 100755 board/altera/socfpga/pll_config.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] socfpga: Adding Clock Manager handoff file
The pll_config.h will be consumed by Clock Manager driver Signed-off-by: Chin Liang See Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk CC: Pavel Machek Cc: Dinh Nguyen --- board/altera/socfpga/pll_config.h | 115 + 1 file changed, 115 insertions(+) create mode 100755 board/altera/socfpga/pll_config.h diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h new file mode 100755 index 000..32aa4ad --- /dev/null +++ b/board/altera/socfpga/pll_config.h @@ -0,0 +1,115 @@ + +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_PLL_CONFIG_H_ +#define _PRELOADER_PLL_CONFIG_H_ + +/* PLL configuration data */ +/* Main PLL */ +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM(0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER(63) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK(1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK(0) +/* + * To tell where is the clock source: + * 0 = MAINPLL + * 1 = PERIPHPLL + */ +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) + +/* Peripheral PLL */ +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) +/* + * To tell where is the VCOs source: + * 0 = EOSC1 + * 1 = EOSC2 + * 2 = F2S + */ +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT(1) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT(4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK(0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +/* + * To tell where is the clock source: + * 0 = F2S_PERIPH_REF_CLK + * 1 = MAIN_CLK + * 2 = PERIPH_CLK + */ +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +/* SDRAM PLL */ +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz + * This if..else... is not required if generated by tools */ +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127) +#else +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) +#endif /* CONFIG_SOCFPGA_ARRIA5 */ + +/* + * To tell where is the VCOs source: + * 0 = EOSC1 + * 1 = EOSC2 + * 2 = F2S + */ +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE(4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +/* Info for driver */ +#define CONFIG_HPS_CLK_OSC1_HZ (2500) +#define CONFIG_HPS_CLK_MAINVCO_HZ (16) +#define CONFIG_HPS_CLK_PERVCO_HZ (10) +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define CONFIG_HPS_CLK_SDRVCO_HZ (106600) +#else +#define CONFIG_HPS_CLK_SDRVCO_HZ (8) +#endif +#define CONFIG_HPS_CLK_EMAC0_HZ(25000) +#define CONFIG_HPS_CLK_EMAC1_HZ(25000) +#define CONFIG_HPS_CLK_USBCLK_HZ (2) +#define CONFIG_HPS_CLK_NAND_HZ (5000) +#define CONFIG_HPS_CLK_SDMMC_HZ(2) +#define CONFIG_HPS_CLK_QSPI_HZ
[U-Boot] [PATCH 1/2] socfpga: Adding Clock Manager driver
Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files
Signed-off-by: Chin Liang See
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Dinh Nguyen
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/clock_manager.c | 378
arch/arm/cpu/armv7/socfpga/spl.c | 90 +
arch/arm/include/asm/arch-socfpga/clock_manager.h | 205 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
include/configs/socfpga_cyclone5.h |1 +
6 files changed, 676 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/clock_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/clock_manager.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 4edc5d4..eb33f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -8,5 +8,5 @@
#
obj-y := lowlevel_init.o
-obj-y += misc.o timer.o reset_manager.o system_manager.o
+obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
new file mode 100644
index 000..7caa76f
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+static const struct socfpga_clock_manager *clock_manager_base =
+ (void *)SOCFPGA_CLKMGR_ADDRESS;
+
+#define CLKMGR_BYPASS_ENUM_ENABLE 1
+#define CLKMGR_BYPASS_ENUM_DISABLE 0
+#define CLKMGR_STAT_BUSY_ENUM_IDLE 0x0
+#define CLKMGR_STAT_BUSY_ENUM_BUSY 0x1
+#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_EOSC1 0x0
+#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_INPUT_MUX 0x1
+#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_EOSC1 0x0
+#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_INPUT_MUX 0x1
+
+#define CLEAR_BGP_EN_PWRDN \
+ (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+ CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
+ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+#define VCO_EN_BASE \
+ (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+ CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
+ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+static inline void cm_wait_for_lock(uint32_t mask)
+{
+ register uint32_t inter_val;
+ do {
+ inter_val = readl(&clock_manager_base->inter) & mask;
+ } while (inter_val != mask);
+}
+
+/* function to poll in the fsm busy bit */
+static inline void cm_wait4fsm(void)
+{
+ register uint32_t inter_val;
+ do {
+ inter_val = readl(&clock_manager_base->stat) &
CLKMGR_STAT_BUSY_ENUM_BUSY;
+ } while (inter_val);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static inline void cm_write_bypass(uint32_t val)
+{
+ writel(val, &clock_manager_base->bypass);
+ cm_wait4fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static inline void cm_write_ctrl(uint32_t val)
+{
+ writel(val, &clock_manager_base->ctrl);
+ cm_wait4fsm();
+}
+
+/* function to write a clock register that has phase information */
+static inline void cm_write_with_phase(uint32_t value,
+ uint32_t reg_address, uint32_t mask)
+{
+ /* poll until phase is zero */
+ do {} while (readl(reg_address) & mask);
+
+ writel(value, reg_address);
+
+ do {} while (readl(reg_address) & mask);
+}
+
+/*
+ * Setup clocks while making no assumptions of the
+ * previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ *
+ * Put all plls in bypass
+ *
+ * Put all plls VCO registers back to reset value (bgpwr dwn).
+ *
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ *
+ * Delay 5 us.
+ *
+ * Deassert bg pwr dn and set numerator and denominator
+ *
+ * Start 7 us timer.
+ *
+ * set internal dividers
+ *
+ * Wait for 7 us timer.
+ *
+ * Enable plls
+ *
+ * Set external dividers while plls are locking
+ *
+ * Wait for pll lock
+ *
+ * Assert/deassert outreset all.
+ *
+ * Take all pll's out of bypass
+ *
+ * Clear safe mode
+ *
+ * set source main and peripheral clocks
+ *
+ * Ungate clocks
+ */
+
+void cm_basic_init(const cm_config_t *cfg)
+{
+ uint32_t start, timeout;
+
+ /* Start by being paranoid and gate all sw managed clocks */
+
+ /*
+* We need to disable nandclk
+* and then do another apb access before disabling
+* gatting off the rest of the periperal clocks.
+*/
+ writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
Re: [U-Boot] [PATCH] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
Hi Gerhard, On Thu, 2013-12-19 at 14:50 +0100, Gerhard Sittig wrote: > On Wed, Dec 18, 2013 at 14:05 -0600, Chin Liang See wrote: > > > > To add the Cadence SPI driver support for Altera SOCFPGA. It > > required information such as clocks and timing from platform's > > configuration header file within include/configs folder > > > > Signed-off-by: Chin Liang See > > Cc: Jagannadha Sutradharudu Teki > > --- > > drivers/spi/Makefile |1 + > > drivers/spi/cadence_qspi.c | 337 > > drivers/spi/cadence_qspi.h | 56 +++ > > drivers/spi/cadence_qspi_apb.c | 873 > > > > 4 files changed, 1267 insertions(+) > > create mode 100644 drivers/spi/cadence_qspi.c > > create mode 100644 drivers/spi/cadence_qspi.h > > create mode 100644 drivers/spi/cadence_qspi_apb.c > > Can you please add the information which header file is required? > And do I get it right that this header file does not come with > the source but is provided "externally" to the U-Boot project? > Oh actually its part of the header file within include/configs. For our case, it would be include/configs/socfpga_cyclone5.h. Its not external or generated file. But it would need macro in order to get some customization to the driver. Wonder would it be good we need to document the required macros? Or just the standard way where people normally just grep macro used in others platform header file (which I normally did). Thanks and have a nice day! Chin Liang > Does this mean that compilation breaks if one enables the Cadence > QSPI controller in the config and does not provide the header > file which is not documented as a dependency? It would be nice > to have a more visible warning about this, or better > documentation of the requirements. If the content of the file or > required settings are not documented, users should at least be > able to learn which external tool can generate/provide the file > and how to make it available to the U-Boot project source. > > It's probably best to provide a specific example file for an eval > board. So interested persons can see the file name, its > location, its content, and can either use it or adjust it to > their needs depending on whether they use the eval board or some > similar design of their own. > > > virtually yours > Gerhard Sittig ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
Hi Jagan,
On Thu, 2013-12-19 at 21:39 +0530, Jagan Teki wrote:
> Thanks for your patch.
>
> Please see the typical driver code suggestions on below thread.
> http://u-boot.10912.n7.nabble.com/Suggestions-for-SPI-driver-pusher-td161008.html
>
> Try to avoid the header files make sure to code everything in single .c file.
> Also add some documents as well as test log on doc/ folder if possible.
Thanks for pointing the info. I agree that it would much readable if all
drivers are following same standard. I will reformat the code and
re-submit again. Thanks
Chin Liang
>
> On Thu, Dec 19, 2013 at 1:35 AM, Chin Liang See wrote:
> > To add the Cadence SPI driver support for Altera SOCFPGA. It
> > required information such as clocks and timing from platform's
> > configuration header file within include/configs folder
> >
> > Signed-off-by: Chin Liang See
> > Cc: Jagannadha Sutradharudu Teki
> > ---
> > drivers/spi/Makefile |1 +
> > drivers/spi/cadence_qspi.c | 337
> > drivers/spi/cadence_qspi.h | 56 +++
> > drivers/spi/cadence_qspi_apb.c | 873
> >
> > 4 files changed, 1267 insertions(+)
> > create mode 100644 drivers/spi/cadence_qspi.c
> > create mode 100644 drivers/spi/cadence_qspi.h
> > create mode 100644 drivers/spi/cadence_qspi_apb.c
> >
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> > index ed4ecd7..838e6ca 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
> > obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
> > obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
> > obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
> > +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
> > obj-$(CONFIG_CF_SPI) += cf_spi.o
> > obj-$(CONFIG_CF_QSPI) += cf_qspi.o
> > obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
> > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> > new file mode 100644
> > index 000..e2bf39f
> > --- /dev/null
> > +++ b/drivers/spi/cadence_qspi.c
> > @@ -0,0 +1,337 @@
> > +/*
> > + * Copyright (C) Altera Corporation
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include "cadence_qspi.h"
> > +
> > +#define CQSPI_STIG_READ0
> > +#define CQSPI_STIG_WRITE 1
> > +#define CQSPI_INDIRECT_READ2
> > +#define CQSPI_INDIRECT_WRITE 3
> > +
> > +static int qspi_is_init;
> > +static unsigned int qspi_calibrated_hz;
> > +static unsigned int qspi_calibrated_cs;
> > +
> > +struct cadence_qspi_slave {
> > + struct spi_slave slave;
> > + unsigned intmode;
> > + unsigned intmax_hz;
> > + void*regbase;
> > + void*ahbbase;
> > + size_t cmd_len;
> > + u8 cmd_buf[32];
> > + size_t data_len;
> > +};
> > +
> > +#define to_cadence_qspi_slave(s) \
> > + container_of(s, struct cadence_qspi_slave, slave)
> > +
> > +void spi_set_speed(struct spi_slave *slave, uint hz)
> > +{
> > + struct cadence_qspi_slave *cadence_qspi =
> > to_cadence_qspi_slave(slave);
> > + void *base = cadence_qspi->regbase;
> > +
> > + cadence_qspi_apb_config_baudrate_div(base, CONFIG_CQSPI_REF_CLK,
> > hz);
> > +
> > + /* Reconfigure delay timing if speed is changed. */
> > + cadence_qspi_apb_delay(base, CONFIG_CQSPI_REF_CLK, hz,
> > + CONFIG_CQSPI_TSHSL_NS, CONFIG_CQSPI_TSD2D_NS,
> > + CONFIG_CQSPI_TCHSH_NS, CONFIG_CQSPI_TSLCH_NS);
> > + return;
> > +}
> > +
> > +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > + unsigned int max_hz, unsigned int mode)
> > +{
> > + struct cadence_qspi_slave *cadence_qspi;
> > +
> > + debug("%s: bus %d cs %d max_hz %dMHz mode %d\n", __func__,
> > + bus, cs, max_hz/100, mode);
> > +
> > + if (!spi_cs_is_valid(bus, cs))
> > + return NULL;
> > +
> > + cadence_qspi = malloc(sizeof(struct cadence_qspi_slave));
> > + if (!cadence_qspi) {
> > + printf("QSPI: Can't allocate struct cadence_qspi_slave. "
> > +
Re: [U-Boot] [PATCH] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
Hi Gerhard, On Thu, 2013-12-19 at 21:03 +0100, Gerhard Sittig wrote: > On Thu, Dec 19, 2013 at 08:46 -0600, Chin Liang See wrote: > > > > Hi Gerhard, > > > > On Thu, 2013-12-19 at 14:50 +0100, Gerhard Sittig wrote: > > > On Wed, Dec 18, 2013 at 14:05 -0600, Chin Liang See wrote: > > > > > > > > To add the Cadence SPI driver support for Altera SOCFPGA. It > > > > required information such as clocks and timing from platform's > > > > configuration header file within include/configs folder > > > > > > > > [ ... ] > > > > > > Can you please add the information which header file is required? > > > And do I get it right that this header file does not come with > > > the source but is provided "externally" to the U-Boot project? > > > > > > > Oh actually its part of the header file within include/configs. For our > > case, it would be include/configs/socfpga_cyclone5.h. Its not external > > or generated file. > > Ah, thank you for the explanation. So the board's configuration > file is referenced as usual. That's OK. > > > But it would need macro in order to get some customization to the > > driver. Wonder would it be good we need to document the required macros? > > Or just the standard way where people normally just grep macro used in > > others platform header file (which I normally did). > > Well, grepping sources may not always be as obvious as code > authors may think. :) Some textual description with the complete > set of possible options, their type and units would be nice. > It's hard to guess for e.g. clocks whether a number is cycles or > nanoseconds or a frequency or bit times or any other arbitrary > thing that may need to get written to hardware with or without > any further conversion. Yup, I totally agree with you on this as I went through the pain before. To solve this, I will create a short documentation at doc/spi folder. I will resubmit my v2 patch with this documentation. > > In current master's socfpga_cyclone5.h I can't see any SPI > related defines, and your patch set does not update this file. > So I'm still afraid that simply enabling the controller in the > config won't result in successful build output. And waiting for > compile errors is the only way to learn when settings are > missing. And still you won't notice when settings are wrong > (like booleans). This would be unsatisfying an experience. > Users should not have to read and reverse engineer code just to > find out how to enable and use it. > > To cut it short, please provide example entries in the cyclone5 > board configuration, and a either a text document or a comment in > the driver source listing all options and their meaning. Actually its not inside cyclone5 board configuration as there are few patches for the platform specific yet to be pushed. I am planning to submit once we cleared the pending patches. With that said, the documentation is a good suggestion as we can put more info there. Thanks again for your helps and feedback Chin Liang > > > virtually yours > Gerhard Sittig ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA
Dear Jaehoon,
On Thu, 2013-12-26 at 14:05 +0900, Jaehoon Chung wrote:
> Hi, Chin.
>
> On 12/19/2013 02:16 AM, Chin Liang See wrote:
> >
> > +
> > +#define CLKMGR_PERPLLGRP_EN_REG(SOCFPGA_CLKMGR_ADDRESS + 0xA0)
> > +#define CLKMGR_SDMMC_CLK_ENABLE(1 << 8)
> > +#define SYSMGR_SDMMCGRP_CTRL_REG (SOCFPGA_SYSMGR_ADDRESS + 0x108)
> Where is SOCFPGA_CLKMGR_ADDRESS defined?
This is located at platform specific declaration file.
>
> > +#define SYSMGR_SDMMC_CTRL_GET_DRVSEL(x)(((x) >> 0) & 0x7)
> ((x) & 0x7) is more readable?
> > +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> > + drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
> > +
> > +static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
> > +
> > +static void socfpga_dwmci_clksel(struct dwmci_host *host)
> > +{
> > + unsigned int en;
> > + unsigned int drvsel;
> > + unsigned int smplsel;
> > +
> > + /* Disable SDMMC clock. */
> > + en = readl(CLKMGR_PERPLLGRP_EN_REG);
> > + en &= ~CLKMGR_SDMMC_CLK_ENABLE;
> > + writel(en, CLKMGR_PERPLLGRP_EN_REG);
> > +
> > + /* Configures drv_sel and smpl_sel */
> > + drvsel = 3;
> > + smplsel = 0;
> Is this value static? then why is value assigned drvsel and smpsel at here?
> I didn't know that SOCFPGA is only used with drvsel = 3, smplsel = 0.
> But if you need to change this value for other SoC version in future, I think
> that hard coding is not good.
Good suggestion as I put them as macro now for v3
>
> > +
> > + debug("%s: drvsel %d smplsel %d\n", __FUNCTION__, drvsel, smplsel);
> > + writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
> > + SYSMGR_SDMMCGRP_CTRL_REG);
> > +
> > + debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __FUNCTION__,
> > + readl(SYSMGR_SDMMCGRP_CTRL_REG));
> > + /* Enable SDMMC clock */
> > + en = readl(CLKMGR_PERPLLGRP_EN_REG);
> > + en |= CLKMGR_SDMMC_CLK_ENABLE;
> > + writel(en, CLKMGR_PERPLLGRP_EN_REG);
> > +}
> > +
> > +int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
> > +{
> > + struct dwmci_host *host = NULL;
> > + host = calloc(sizeof(struct dwmci_host), 1);
> > + if (!host) {
> > + printf("dwmci_host calloc fail!\n");
> > + return 1;
> > + }
> > +
> > + host->name = SOCFPGA_NAME;
> > + host->ioaddr = (void *)regbase;
> > + host->buswidth = bus_width;
> > + host->clksel = socfpga_dwmci_clksel;
> > + host->dev_index = index;
> > + /* fixed clock divide by 4 which due to the SDMMC wrapper */
> > + host->bus_hz = CONFIG_DWMMC_BUS_HZ;
> I didn't want to use the CONFIG_DWMMC_BUS_HZ.
Yup, this is SOCFPGA specific and I am using CONFIG_SOCFPGA_DWMMC_BUS_HZ
for v3
Thanks
Chin Liang
>
> > + host->fifoth_val = MSIZE(0x2) |
> > + RX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2 - 1) |
> > + TX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2);
> > +
> > + add_dwmci(host, host->bus_hz, 40);
> add_dwmci() has the return value.
>
> Best Regards,
> Jaehoon Chung
> > +
> > + return 0;
> > +}
> > +
> >
>
>
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA
To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)
Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Pantelis Antoniou
Cc: Wolfgang Denk
---
Changes for v3
- Used structure instead macro for the register access
- Made drvsel and smpsel configurable
- Used better macro names
- Added a documentation on macro used to enable the driver
Changes for v2
- Adding u-boot-mmc maintainer
---
arch/arm/include/asm/arch-socfpga/dwmmc.h | 12
arch/arm/include/asm/arch-socfpga/system_manager.h | 65 +++
doc/README.socfpga | 53 +++
drivers/mmc/Makefile |1 +
drivers/mmc/socfpga_dw_mmc.c | 68
5 files changed, 199 insertions(+)
create mode 100644 arch/arm/include/asm/arch-socfpga/dwmmc.h
create mode 100644 doc/README.socfpga
create mode 100644 drivers/mmc/socfpga_dw_mmc.c
diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h
b/arch/arm/include/asm/arch-socfpga/dwmmc.h
new file mode 100644
index 000..945eb64
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/dwmmc.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef_SOCFPGA_DWMMC_H_
+#define_SOCFPGA_DWMMC_H_
+
+extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index);
+
+#endif /* _SOCFPGA_SDMMC_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
index d965d25..838d210 100644
--- a/arch/arm/include/asm/arch-socfpga/system_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -19,4 +19,69 @@ extern unsigned long
sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+ drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+
+struct socfpga_system_manager {
+ u32 siliconid1;
+ u32 siliconid2;
+ u32 _pad_0x8_0xf[2];
+ u32 wddbg;
+ u32 bootinfo;
+ u32 hpsinfo;
+ u32 parityinj;
+ u32 fpgaintfgrp_gbl;
+ u32 fpgaintfgrp_indiv;
+ u32 fpgaintfgrp_module;
+ u32 _pad_0x2c_0x2f;
+ u32 scanmgrgrp_ctrl;
+ u32 _pad_0x34_0x3f[3];
+ u32 frzctrl_vioctrl;
+ u32 _pad_0x44_0x4f[3];
+ u32 frzctrl_hioctrl;
+ u32 frzctrl_src;
+ u32 frzctrl_hwctrl;
+ u32 _pad_0x5c_0x5f;
+ u32 emacgrp_ctrl;
+ u32 emacgrp_l3master;
+ u32 _pad_0x68_0x6f[2];
+ u32 dmagrp_ctrl;
+ u32 dmagrp_persecurity;
+ u32 _pad_0x78_0x7f[2];
+ u32 iswgrp_handoff[8];
+ u32 _pad_0xa0_0xbf[8];
+ u32 romcodegrp_ctrl;
+ u32 romcodegrp_cpu1startaddr;
+ u32 romcodegrp_initswstate;
+ u32 romcodegrp_initswlastld;
+ u32 romcodegrp_bootromswstate;
+ u32 __pad_0xd4_0xdf[3];
+ u32 romcodegrp_warmramgrp_enable;
+ u32 romcodegrp_warmramgrp_datastart;
+ u32 romcodegrp_warmramgrp_length;
+ u32 romcodegrp_warmramgrp_execution;
+ u32 romcodegrp_warmramgrp_crc;
+ u32 __pad_0xf4_0xff[3];
+ u32 romhwgrp_ctrl;
+ u32 _pad_0x104_0x107;
+ u32 sdmmcgrp_ctrl;
+ u32 sdmmcgrp_l3master;
+ u32 nandgrp_bootstrap;
+ u32 nandgrp_l3master;
+ u32 usbgrp_l3master;
+ u32 _pad_0x11c_0x13f[9];
+ u32 eccgrp_l2;
+ u32 eccgrp_ocram;
+ u32 eccgrp_usb0;
+ u32 eccgrp_usb1;
+ u32 eccgrp_emac0;
+ u32 eccgrp_emac1;
+ u32 eccgrp_dma;
+ u32 eccgrp_can0;
+ u32 eccgrp_can1;
+ u32 eccgrp_nand;
+ u32 eccgrp_qspi;
+ u32 eccgrp_sdmmc;
+};
+
#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/doc/README.socfpga b/doc/README.socfpga
new file mode 100644
index 000..cfcbbfe
--- /dev/null
+++ b/doc/README.socfpga
@@ -0,0 +1,53 @@
+
+
+SOCFPGA Documentation for U-Boot and SPL
+
+
+This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
+based SOCFPGA. To know more about the hardware itself, please refer to
+www.altera.com.
+
+
+
+socfpga_dw_mmc
+
+Here are macro and detailed configuration required to enable DesignWare SDMMC
+controller support within SOCFPGA
+
+#define CONFIG_MMC
+-> To enable the SD MMC framework support
+
+#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS)
+-> The b
Re: [U-Boot] [PATCH v2] socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA
Dear Wolfgang, On Thu, 2013-12-26 at 09:38 +0100, ZY - wd wrote: > Dear Chin Liang See, > > PLease fix your address list. There is no such address as > "a...@denx.de". Oh... I presume you are referring to Andy Fleming. I am getting delivery failure to aflem...@freescale.com and removing it from CC list. > > In message <1387386987-3581-1-git-send-email-cl...@altera.com> you wrote: > > To add the DesignWare MMC driver support for Altera SOCFPGA. It > > required information such as clocks and bus width from platform > > specific files (SOCFPGA handoff files) > ... > > +#define CLKMGR_PERPLLGRP_EN_REG(SOCFPGA_CLKMGR_ADDRESS + 0xA0) > ... > > +#define SYSMGR_SDMMCGRP_CTRL_REG (SOCFPGA_SYSMGR_ADDRESS + 0x108) > > This looks as if you were trying to access device rtegisters through a > base address plus offset notation? > > We do not allow this in U-Boot, as the compiler then has no chance to > check if you are using the correct data types, i. e. it cannot warn > you for example when you access a 32 bit register for a 16 bit data > type. > Noted and I believe I miss out this. I will be using structure for v3 > Please use C structs and proper I/O accessors instead. > > > + /* Disable SDMMC clock. */ > > + en = readl(CLKMGR_PERPLLGRP_EN_REG); > > + en &= ~CLKMGR_SDMMC_CLK_ENABLE; > > + writel(en, CLKMGR_PERPLLGRP_EN_REG); > > Please fix such code. Use proper I/O accessors. This could (and > should) be written as: > > clrbits_le32(clkmgr->perpllgrp_en, CLKMGR_SDMMC_CLK_ENABLE); > > [or similar struct member name]. > > > + /* Enable SDMMC clock */ > > + en = readl(CLKMGR_PERPLLGRP_EN_REG); > > + en |= CLKMGR_SDMMC_CLK_ENABLE; > > + writel(en, CLKMGR_PERPLLGRP_EN_REG); > > Ditto here, etc. Noted. Thanks Chin Liang > > Please check all your device accesses. > > Best regards, > > Wolfgang Denk > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
To add the Cadence SPI driver support for Altera SOCFPGA. It
required information such as clocks and timing from platform's
configuration header file within include/configs folder
Signed-off-by: Chin Liang See
Cc: Jagan Teki
Cc: Gerhard Sittig
---
Changes for v2
- Combine driver into single C file instead of 2
- Added documentation on the macro used
- Using structure for registers instead of macro
---
doc/README.socfpga | 47 ++
drivers/spi/Makefile |1 +
drivers/spi/cadence_qspi.c | 1018
drivers/spi/cadence_qspi.h | 170
4 files changed, 1236 insertions(+)
create mode 100644 drivers/spi/cadence_qspi.c
create mode 100644 drivers/spi/cadence_qspi.h
diff --git a/doc/README.socfpga b/doc/README.socfpga
index cfcbbfe..242af97 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -51,3 +51,50 @@ the card
#define CONFIG_SOCFPGA_DWMMC_BUS_HZ5000
-> The clock rate to controller. Do note the controller have a wrapper which
divide the clock from PLL by 4.
+
+
+cadence_qspi
+
+Here are macro and detailed configuration required to enable Cadence QSPI
+controller support within SOCFPGA
+
+#define CONFIG_SPI_FLASH
+-> To enable the SPI flash framework support
+
+#define CONFIG_CMD_SF
+-> To enable the console support for SPI flash
+
+#define CONFIG_SF_DEFAULT_SPEED(5000)
+-> To set the target SPI clock frequency in Hz
+
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+-> To set the SPI mode (CPOL & CPHA). Normally use mode 3 for serial NOR flash
+
+#define CONFIG_SPI_FLASH_QUAD (1)
+-> To enable the Quad IO mode for performance boost
+
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
+-> To enable the SPI flash support for vendor Micron and Spansion
+
+#define CONFIG_CQSPI_BASE (SOCFPGA_QSPIREGS_ADDRESS)
+#define CONFIG_CQSPI_AHB_BASE (SOCFPGA_QSPIDATA_ADDRESS)
+-> To specify the base address for controller CSR base and AHB data base addr
+
+#define CONFIG_CQSPI_REF_CLK (4)
+-> The clock frequency supplied from PLL to the QSPI controller
+
+#define CONFIG_CQSPI_PAGE_SIZE (256)
+-> To define the page size of serial flash in bytes
+
+#define CONFIG_CQSPI_BLOCK_SIZE(16)
+-> To define the block size of serial flash in pages
+
+#define CONFIG_CQSPI_DECODER (0)
+-> To enable the 4-to-16 decoder which enable up to 16 serial flash devices
+
+#define CONFIG_CQSPI_TSHSL_NS (200)
+#define CONFIG_CQSPI_TSD2D_NS (255)
+#define CONFIG_CQSPI_TCHSH_NS (20)
+#define CONFIG_CQSPI_TSLCH_NS (20)
+-> Configure the controller based on serial flash device timing characteristic
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ed4ecd7..b8d56ea 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
new file mode 100644
index 000..4712b45
--- /dev/null
+++ b/drivers/spi/cadence_qspi.c
@@ -0,0 +1,1018 @@
+/*
+ * (C) Copyright 2014 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "cadence_qspi.h"
+
+static int qspi_is_init;
+static unsigned int qspi_calibrated_hz;
+static unsigned int qspi_calibrated_cs;
+
+static const struct cadence_qspi *cadence_qspi_base = (void *)QSPI_BASE;
+
+#define to_cadence_qspi_slave(s) \
+ container_of(s, struct cadence_qspi_slave, slave)
+
+#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
+ tdelay_ns) - (tsclk_ns)) / (tref_ns)))
+
+#define CQSPI_GET_WR_SRAM_LEVEL() \
+ ((readl(&cadence_qspi_base->sramfill) >>\
+ CQSPI_REG_SRAMLEVEL_WR_LSB) & CQSPI_REG_SRAMLEVEL_WR_MASK)
+
+static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
+ unsigned int addr_width)
+{
+ unsigned int addr;
+
+ addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
+
+ if (addr_width == 4)
+ addr = (addr << 8) | addr_buf[3];
+
+ return addr;
+}
+
+static void cadence_qspi_apb_read_fifo_data(void *dest,
+ const void *src_ahb_addr, unsigned int bytes)
+{
+ unsigned int temp;
+ int remaining = bytes;
+ unsigned int *dest_ptr = (unsigned int *)dest;
+ unsigned int *src_ptr = (unsigned int *)src_
Re: [U-Boot] [PATCH v2] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
Hi Jagan, On Wed, 2014-01-08 at 17:43 +0530, Jagan Teki wrote: > Hi Chin Liang See, > > On Thu, Jan 2, 2014 at 8:13 AM, Chin Liang See wrote: > > To add the Cadence SPI driver support for Altera SOCFPGA. It > > required information such as clocks and timing from platform's > > configuration header file within include/configs folder > > > > Signed-off-by: Chin Liang See > > Cc: Jagan Teki > > Cc: Gerhard Sittig > > --- > > Changes for v2 > > - Combine driver into single C file instead of 2 > > - Added documentation on the macro used > > - Using structure for registers instead of macro > > --- > > doc/README.socfpga | 47 ++ > > drivers/spi/Makefile |1 + > > drivers/spi/cadence_qspi.c | 1018 > > > > drivers/spi/cadence_qspi.h | 170 > > 4 files changed, 1236 insertions(+) > > create mode 100644 drivers/spi/cadence_qspi.c > > create mode 100644 drivers/spi/cadence_qspi.h > > > > diff --git a/doc/README.socfpga b/doc/README.socfpga > > index cfcbbfe..242af97 100644 > > --- a/doc/README.socfpga > > +++ b/doc/README.socfpga > > @@ -51,3 +51,50 @@ the card > > #define CONFIG_SOCFPGA_DWMMC_BUS_HZ5000 > > -> The clock rate to controller. Do note the controller have a wrapper > > which > > divide the clock from PLL by 4. > > + > > + > > +cadence_qspi > > + > > +Here are macro and detailed configuration required to enable Cadence QSPI > > +controller support within SOCFPGA > > + > > +#define CONFIG_SPI_FLASH > > +-> To enable the SPI flash framework support > > + > > +#define CONFIG_CMD_SF > > +-> To enable the console support for SPI flash > > + > > +#define CONFIG_SF_DEFAULT_SPEED(5000) > > +-> To set the target SPI clock frequency in Hz > > + > > +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 > > +-> To set the SPI mode (CPOL & CPHA). Normally use mode 3 for serial NOR > > flash > > + > > +#define CONFIG_SPI_FLASH_QUAD (1) > > +-> To enable the Quad IO mode for performance boost > > + > > +#define CONFIG_SPI_FLASH_STMICRO > > +#define CONFIG_SPI_FLASH_SPANSION > > +-> To enable the SPI flash support for vendor Micron and Spansion > > + > > +#define CONFIG_CQSPI_BASE (SOCFPGA_QSPIREGS_ADDRESS) > > +#define CONFIG_CQSPI_AHB_BASE (SOCFPGA_QSPIDATA_ADDRESS) > > +-> To specify the base address for controller CSR base and AHB data base > > addr > > + > > +#define CONFIG_CQSPI_REF_CLK (4) > > +-> The clock frequency supplied from PLL to the QSPI controller > > + > > +#define CONFIG_CQSPI_PAGE_SIZE (256) > > +-> To define the page size of serial flash in bytes > > + > > +#define CONFIG_CQSPI_BLOCK_SIZE(16) > > +-> To define the block size of serial flash in pages > > + > > +#define CONFIG_CQSPI_DECODER (0) > > +-> To enable the 4-to-16 decoder which enable up to 16 serial flash devices > > + > > +#define CONFIG_CQSPI_TSHSL_NS (200) > > +#define CONFIG_CQSPI_TSD2D_NS (255) > > +#define CONFIG_CQSPI_TCHSH_NS (20) > > +#define CONFIG_CQSPI_TSLCH_NS (20) > > +-> Configure the controller based on serial flash device timing > > characteristic > Do we really require this, because most of the known macros definitions. > Better to not write too many duplicates - Yes there are few macro's > which are specific to cadence > but I don't think those were required. Oh actually this is to address Gerhard's comment. This document will guide user the required macro (and its details) in order to use this Cadence QSPI controller. > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > > index ed4ecd7..b8d56ea 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o > > obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o > > obj-$(CONFIG_BFIN_SPI) += bfin_spi.o > > obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o > > +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o > > obj-$(CONFIG_CF_SPI) += cf_spi.o > > obj-$(CONFIG_CF_QSPI) += cf_qspi.o > > obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o > > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c > > new file mode 100644 >
Re: [U-Boot] [PATCH] watchdog/denali: Adding DesignWare watchdog driver support
Hi guys,
Wonder any comments for this patch?
Thanks
Chin Liang
On Wed, 2013-12-18 at 16:23 -0600, Chin Liang See wrote:
> To add the DesignWare watchdog driver support. It required
> information such as register base address and clock info from
> configuration header file within include/configs folder.
>
> Signed-off-by: Chin Liang See
> Cc: Anatolij Gustschin
> Cc: Albert Aribaud
> Cc: Heiko Schocher
> Cc: Tom Rini
> ---
> drivers/watchdog/Makefile |1 +
> drivers/watchdog/designware_wdt.c | 75
> +
> 2 files changed, 76 insertions(+)
> create mode 100644 drivers/watchdog/designware_wdt.c
>
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index 06ced10..0276a10 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
> obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
> obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
> obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
> +obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
> diff --git a/drivers/watchdog/designware_wdt.c
> b/drivers/watchdog/designware_wdt.c
> new file mode 100644
> index 000..c3b14f5
> --- /dev/null
> +++ b/drivers/watchdog/designware_wdt.c
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright (C) 2013 Altera Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#define DW_WDT_CR0x00
> +#define DW_WDT_TORR 0x04
> +#define DW_WDT_CRR 0x0C
> +
> +#define DW_WDT_CR_EN_OFFSET 0x00
> +#define DW_WDT_CR_RMOD_OFFSET0x01
> +#define DW_WDT_CR_RMOD_VAL 0x00
> +#define DW_WDT_CRR_RESTART_VAL 0x76
> +
> +/*
> + * Set the watchdog time interval.
> + * Counter is 32 bit.
> + */
> +int designware_wdt_settimeout(unsigned int timeout)
> +{
> + signed int i;
> + /* calculate the timeout range value */
> + i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ))\
> + - 16;
> + if (i > 15)
> + i = 15;
> + if (i < 0)
> + i = 0;
> +
> + writel((i | (i<<4)),
> + (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
> + return 0;
> +}
> +
> +void designware_wdt_enable(void)
> +{
> + writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | \
> + (0x1 << DW_WDT_CR_EN_OFFSET)),
> + (CONFIG_DW_WDT_BASE + DW_WDT_CR));
> +}
> +
> +unsigned int designware_wdt_is_enabled(void)
> +{
> + unsigned long val;
> + val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
> + return val & 0x1;
> +}
> +
> +#if defined(CONFIG_HW_WATCHDOG)
> +void hw_watchdog_reset(void)
> +{
> + if (designware_wdt_is_enabled())
> + /* restart the watchdog counter */
> + writel(DW_WDT_CRR_RESTART_VAL,
> + (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
> +}
> +
> +void hw_watchdog_init(void)
> +{
> + /* reset to disable the watchdog */
> + hw_watchdog_reset();
> + /* set timer in miliseconds */
> + designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
> + /* enable the watchdog */
> + designware_wdt_enable();
> + /* reset the watchdog */
> + hw_watchdog_reset();
> +}
> +#endif
___
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Re: [U-Boot] [PATCH 1/2] socfpga: Adding Clock Manager driver
Hi guys,
Wonder any comments for this patch?
Thanks
Chin Liang
On Wed, 2013-12-18 at 17:54 -0600, Chin Liang See wrote:
> Clock Manager driver will be called to reconfigure all the
> clocks setting based on user input. The input are passed to
> Preloader through handoff files
>
> Signed-off-by: Chin Liang See
> Cc: Albert Aribaud
> Cc: Tom Rini
> Cc: Wolfgang Denk
> CC: Pavel Machek
> Cc: Dinh Nguyen
> ---
> arch/arm/cpu/armv7/socfpga/Makefile|2 +-
> arch/arm/cpu/armv7/socfpga/clock_manager.c | 378
>
> arch/arm/cpu/armv7/socfpga/spl.c | 90 +
> arch/arm/include/asm/arch-socfpga/clock_manager.h | 205 +++
> .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
> include/configs/socfpga_cyclone5.h |1 +
> 6 files changed, 676 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/cpu/armv7/socfpga/clock_manager.c
> create mode 100644 arch/arm/include/asm/arch-socfpga/clock_manager.h
>
> diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
> b/arch/arm/cpu/armv7/socfpga/Makefile
> index 4edc5d4..eb33f2c 100644
> --- a/arch/arm/cpu/armv7/socfpga/Makefile
> +++ b/arch/arm/cpu/armv7/socfpga/Makefile
> @@ -8,5 +8,5 @@
> #
>
> obj-y:= lowlevel_init.o
> -obj-y+= misc.o timer.o reset_manager.o system_manager.o
> +obj-y+= misc.o timer.o reset_manager.o system_manager.o
> clock_manager.o
> obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
> diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
> b/arch/arm/cpu/armv7/socfpga/clock_manager.c
> new file mode 100644
> index 000..7caa76f
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
> @@ -0,0 +1,378 @@
> +/*
> + * Copyright (C) 2013 Altera Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +
> +static const struct socfpga_clock_manager *clock_manager_base =
> + (void *)SOCFPGA_CLKMGR_ADDRESS;
> +
> +#define CLKMGR_BYPASS_ENUM_ENABLE1
> +#define CLKMGR_BYPASS_ENUM_DISABLE 0
> +#define CLKMGR_STAT_BUSY_ENUM_IDLE 0x0
> +#define CLKMGR_STAT_BUSY_ENUM_BUSY 0x1
> +#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_EOSC10x0
> +#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_INPUT_MUX0x1
> +#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_EOSC10x0
> +#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_INPUT_MUX0x1
> +
> +#define CLEAR_BGP_EN_PWRDN \
> + (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
> + CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
> + CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
> +
> +#define VCO_EN_BASE \
> + (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
> + CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
> + CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
> +
> +static inline void cm_wait_for_lock(uint32_t mask)
> +{
> + register uint32_t inter_val;
> + do {
> + inter_val = readl(&clock_manager_base->inter) & mask;
> + } while (inter_val != mask);
> +}
> +
> +/* function to poll in the fsm busy bit */
> +static inline void cm_wait4fsm(void)
> +{
> + register uint32_t inter_val;
> + do {
> + inter_val = readl(&clock_manager_base->stat) &
> CLKMGR_STAT_BUSY_ENUM_BUSY;
> + } while (inter_val);
> +}
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +static inline void cm_write_bypass(uint32_t val)
> +{
> + writel(val, &clock_manager_base->bypass);
> + cm_wait4fsm();
> +}
> +
> +/* function to write the ctrl register which requires a poll of the busy bit
> */
> +static inline void cm_write_ctrl(uint32_t val)
> +{
> + writel(val, &clock_manager_base->ctrl);
> + cm_wait4fsm();
> +}
> +
> +/* function to write a clock register that has phase information */
> +static inline void cm_write_with_phase(uint32_t value,
> + uint32_t reg_address, uint32_t mask)
> +{
> + /* poll until phase is zero */
> + do {} while (readl(reg_address) & mask);
> +
> + writel(value, reg_address);
> +
> + do {} while (readl(reg_address) & mask);
> +}
> +
> +/*
> + * Setup clocks while making no assumptions of the
> + * previous state of the clocks.
> + *
> + * Start by being paranoid and gate all sw managed clocks
> + *
> + * Put all plls in bypass
> + *
> + * Put all plls VCO registers back to reset value (bgpwr dwn).
> + *
> + * Put peripheral and main pll src to reset value to avoid glitch.
> + *
> + * Delay 5 us.
> + *
> + * Deassert bg
Re: [U-Boot] [PATCH] nand/denali: Adding Denali NAND driver support
Hi guys,
Wonder any comments for this patch?
Thanks
Chin Liang
On Wed, 2013-12-18 at 15:18 -0600, Chin Liang See wrote:
> To add the Denali NAND driver support into U-Boot. It required
> information such as register base address from configuration
> header file within include/configs folder.
>
> Signed-off-by: Chin Liang See
> Cc: Artem Bityutskiy
> Cc: David Woodhouse
> Cc: Brian Norris
> Cc: Scott Wood
> ---
> drivers/mtd/nand/Makefile |1 +
> drivers/mtd/nand/denali_nand.c | 1166
>
> drivers/mtd/nand/denali_nand.h | 501 +
> 3 files changed, 1668 insertions(+)
> create mode 100644 drivers/mtd/nand/denali_nand.c
> create mode 100644 drivers/mtd/nand/denali_nand.h
>
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 02b149c..24e8218 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -39,6 +39,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
> obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
> obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
> obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
> +obj-$(CONFIG_NAND_DENALI) += denali_nand.o
> obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
> obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
> obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
> diff --git a/drivers/mtd/nand/denali_nand.c b/drivers/mtd/nand/denali_nand.c
> new file mode 100644
> index 000..55246c9
> --- /dev/null
> +++ b/drivers/mtd/nand/denali_nand.c
> @@ -0,0 +1,1166 @@
> +/*
> + * Copyright (C) 2013 Altera Corporation
> + * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "denali_nand.h"
> +
> +/* We define a module parameter that allows the user to override
> + * the hardware and decide what timing mode should be used.
> + */
> +#define NAND_DEFAULT_TIMINGS -1
> +
> +static struct denali_nand_info denali;
> +static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
> +
> +/* We define a macro here that combines all interrupts this driver uses into
> + * a single constant value, for convenience. */
> +#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
> + INTR_STATUS__ECC_TRANSACTION_DONE | \
> + INTR_STATUS__ECC_ERR | \
> + INTR_STATUS__PROGRAM_FAIL | \
> + INTR_STATUS__LOAD_COMP | \
> + INTR_STATUS__PROGRAM_COMP | \
> + INTR_STATUS__TIME_OUT | \
> + INTR_STATUS__ERASE_FAIL | \
> + INTR_STATUS__RST_COMP | \
> + INTR_STATUS__ERASE_COMP | \
> + INTR_STATUS__ECC_UNCOR_ERR | \
> + INTR_STATUS__INT_ACT | \
> + INTR_STATUS__LOCKED_BLK)
> +
> +/* indicates whether or not the internal value for the flash bank is
> + * valid or not */
> +#define CHIP_SELECT_INVALID -1
> +
> +#define SUPPORT_8BITECC 1
> +
> +/* This macro divides two integers and rounds fractional values up
> + * to the nearest integer value. */
> +#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
> +
> +/* These constants are defined by the driver to enable common driver
> + * configuration options. */
> +#define SPARE_ACCESS 0x41
> +#define MAIN_ACCESS 0x42
> +#define MAIN_SPARE_ACCESS0x43
> +
> +#define DENALI_UNLOCK_START 0x10
> +#define DENALI_UNLOCK_END0x11
> +#define DENALI_LOCK 0x21
> +#define DENALI_LOCK_TIGHT0x31
> +#define DENALI_BUFFER_LOAD 0x60
> +#define DENALI_BUFFER_WRITE 0x62
> +
> +#define DENALI_READ 0
> +#define DENALI_WRITE 0x100
> +
> +/* types of device accesses. We can issue commands and get status */
> +#define COMMAND_CYCLE0
> +#define ADDR_CYCLE 1
> +#define STATUS_CYCLE 2
> +
> +/* this is a helper macro that allows us to
> + * format the bank into the proper bits for the controller */
> +#define BANK(x) ((x) << 24)
> +
> +/* Interrupts are cleared by writing a 1 to the appropriate status bit */
> +static inline void clear_interrupt(uint32_t irq_mask)
> +{
> + uint32_t intr_status_reg = 0;
> + intr_status_reg = INTR_STATUS(denali.flash_bank);
> + __raw_writel(irq_mask, denali.flash_reg + intr_status_reg);
> +}
> +
> +static uint32_t read_interrupt_status(void)
> +{
> + uint32_t intr_status_reg = 0;
> + intr_status_reg = INTR_STATUS(denali.flash_bank);
> + return __raw_readl(denali.flash_reg + intr_status_reg);
> +}
> +
> +stati
Re: [U-Boot] [PATCH 0/2 v2] socfpga: Adding Scan Manager
Hi guys, Wonder any comments for this patch? Thanks Chin Liang On Mon, 2013-12-02 at 14:31 -0600, Chin Liang See wrote: > Adding Scan Manager driver and handoff files. Scan Manager driver > will be called to configure the IO buffer setting. > > Signed-off-by: Chin Liang See > Cc: Dinh Nguyen > Cc: Wolfgang Denk > CC: Pavel Machek > Cc: Tom Rini > Cc: Albert Aribaud > --- > Changes for v2 > - Rebase with latest v2014.01-rc1 > > Chin Liang See (2): > socfpga: Adding Scan Manager driver > socfpga: Adding Scan Manager IOCSR handoff files > > arch/arm/cpu/armv7/socfpga/Makefile|2 +- > arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 +++ > arch/arm/cpu/armv7/socfpga/spl.c |4 + > arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++ > .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + > board/altera/socfpga/iocsr_config.c| 653 > > board/altera/socfpga/iocsr_config.h| 12 + > include/configs/socfpga_cyclone5.h |1 + > 8 files changed, 1000 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c > create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h > create mode 100644 board/altera/socfpga/iocsr_config.c > create mode 100644 board/altera/socfpga/iocsr_config.h > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
Hi Jagan, On Thu, 2014-01-09 at 20:56 +0530, Jagan Teki wrote: > HI Chin Liang, > > On Thu, Jan 9, 2014 at 8:06 PM, Chin Liang See wrote: > > Hi Jagan, > > > > On Wed, 2014-01-08 at 17:43 +0530, Jagan Teki wrote: > >> Hi Chin Liang See, > >> > >> On Thu, Jan 2, 2014 at 8:13 AM, Chin Liang See wrote: > >> > To add the Cadence SPI driver support for Altera SOCFPGA. It > >> > required information such as clocks and timing from platform's > >> > configuration header file within include/configs folder > >> > > >> > Signed-off-by: Chin Liang See > >> > Cc: Jagan Teki > >> > Cc: Gerhard Sittig > >> > --- > >> > Changes for v2 > >> > - Combine driver into single C file instead of 2 > >> > - Added documentation on the macro used > >> > - Using structure for registers instead of macro > >> > --- > >> > doc/README.socfpga | 47 ++ > >> > drivers/spi/Makefile |1 + > >> > drivers/spi/cadence_qspi.c | 1018 > >> > > >> > drivers/spi/cadence_qspi.h | 170 > >> > 4 files changed, 1236 insertions(+) > >> > create mode 100644 drivers/spi/cadence_qspi.c > >> > create mode 100644 drivers/spi/cadence_qspi.h > >> > > >> > diff --git a/doc/README.socfpga b/doc/README.socfpga > >> > index cfcbbfe..242af97 100644 > >> > --- a/doc/README.socfpga > >> > +++ b/doc/README.socfpga > >> > @@ -51,3 +51,50 @@ the card > >> > #define CONFIG_SOCFPGA_DWMMC_BUS_HZ5000 > >> > -> The clock rate to controller. Do note the controller have a wrapper > >> > which > >> > divide the clock from PLL by 4. > >> > + > >> > + > >> > +cadence_qspi > >> > + > >> > +Here are macro and detailed configuration required to enable Cadence > >> > QSPI > >> > +controller support within SOCFPGA > >> > + > >> > +#define CONFIG_SPI_FLASH > >> > +-> To enable the SPI flash framework support > >> > + > >> > +#define CONFIG_CMD_SF > >> > +-> To enable the console support for SPI flash > >> > + > >> > +#define CONFIG_SF_DEFAULT_SPEED(5000) > >> > +-> To set the target SPI clock frequency in Hz > >> > + > >> > +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 > >> > +-> To set the SPI mode (CPOL & CPHA). Normally use mode 3 for serial > >> > NOR flash > >> > + > >> > +#define CONFIG_SPI_FLASH_QUAD (1) > >> > +-> To enable the Quad IO mode for performance boost > >> > + > >> > +#define CONFIG_SPI_FLASH_STMICRO > >> > +#define CONFIG_SPI_FLASH_SPANSION > >> > +-> To enable the SPI flash support for vendor Micron and Spansion > >> > + > >> > +#define CONFIG_CQSPI_BASE (SOCFPGA_QSPIREGS_ADDRESS) > >> > +#define CONFIG_CQSPI_AHB_BASE (SOCFPGA_QSPIDATA_ADDRESS) > >> > +-> To specify the base address for controller CSR base and AHB data > >> > base addr > >> > + > >> > +#define CONFIG_CQSPI_REF_CLK (4) > >> > +-> The clock frequency supplied from PLL to the QSPI controller > >> > + > >> > +#define CONFIG_CQSPI_PAGE_SIZE (256) > >> > +-> To define the page size of serial flash in bytes > >> > + > >> > +#define CONFIG_CQSPI_BLOCK_SIZE(16) > >> > +-> To define the block size of serial flash in pages > >> > + > >> > +#define CONFIG_CQSPI_DECODER (0) > >> > +-> To enable the 4-to-16 decoder which enable up to 16 serial flash > >> > devices > >> > + > >> > +#define CONFIG_CQSPI_TSHSL_NS (200) > >> > +#define CONFIG_CQSPI_TSD2D_NS (255) > >> > +#define CONFIG_CQSPI_TCHSH_NS (20) > >> > +#define CONFIG_CQSPI_TSLCH_NS (20) > >> > +-> Configure the controller based on serial flash device timing > >> > characteristic > >> Do we really require this, because most of the known macros definitions. > >> Better to not write too many duplicates - Yes there are few macro
Re: [U-Boot] Mainline u-boot on socfpga (SocKit) board
Hi Pavel, On Wed, 2014-05-07 at 17:48 +0200, ZY - pavel wrote: > Hi! > > I know that mainline U-Boot SPL is quite far from working on > socfpga... but would like to ask, what is the status of U-Boot > proper. That should work on socfpga, right? Or are there some pieces > missing? > > I tried > > commit 173d294b94cfec10063a5be40934d6d8fb7981ce > Merge: 33b0f7b 870e0bd > Author: Tom Rini > Date: Tue May 6 14:55:45 2014 -0400 > > Merge branch 'serial' of git://www.denx.de/git/u-boot-microblaze > > and it just dies with no output. > > I'd really like to get something close to mainline working, so that I > can generate patches etc. > The missing piece here is the SDRAM driver. This is a big piece as U-boot require the SDRAM to run. As of now, I am enhancing the existing SDRAM drivers to ensure its compliance with the coding standard. But nevertheless, it poses another challenge when come to license. The driver is currently licensed under BSD-3 clause. Wonder can we upstream BSD-3 clause code? Any advise would be appreciated. Thanks Chin Liang > Thanks, > Pavel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Mainline u-boot SPL for socfpga
Hi Charles, On Tue, 2014-05-06 at 12:22 +1200, Charles Manning wrote: > Hello > > > I am trying to understand the state of the socfpga preloader in > mainline u-boot. > > > From what I see, this is broken and perhaps has never worked. > > > When I build the code in u-boot-socfpga I get a healthy working > u-boot-spl.bin of approx 45kbytes. > > > When I build the mainline u-boot code I get a broken u-boot-spl.bin of > approx 3kbytes. > > > It seems the mainline u-boot is missing stuff, including the > all-critical sdram initialisation without which the SPL is useless. > > As of now, we have most of the drivers already upstreamed to main line. The missing piece here are the SDRAM driver. The SDRAM driver poses a big challenge as its now licensed under BSD-3 clause. I am still working with legal team to look into potential to make it GPL license. > So, I have a few related questions: > > > 1. The SDRAM init code, like other SocFPGA "hand-off" files is > generated by the Altera tools. Since it is not hand written, and is > not compliant with u-boot coding style. Is it more important to > preserve coding style and have a broken SPL than it is to have a > working SPL and broken code? > The SDRAM handoff files generated by tools is not compliance as the original code developer doesn't familiar with open source world. But if you look into the SDRAM handoff files within rocketboard.org git, the existing code already updated. I enhanced the code to ensure it meet with basic coding standard. But further enhancement is needed and on-going now. > > 2. Is there a practical "half-way" compromise whereby the generated > code is run through lindent and we just accept that this is as good as > it gets? > > The on-going plan now is to use the enhanced SDRAM handoff file at rocketboard.org. From there, we want to streamline the driver by removing unused code. Once its ready, we will upstream this file. > 3. Can we get some sort of coding style waiver, considering that this > code is off in a board file and does not impact on anyone working on > anything other than socfpga (indeed nobody even working on socfpga > even reads it). > > > Clearly significant hand editing generated code makes for a very > broken workflow, but running it through an automated step like lindent > is Ok from a workflow point of view. > > > Unless this can be resolved we end up with a situation where people > working on SocFPGA are forced to fork for practical reasons. I believe it would be tough to get the waiver. Nevertheless, we are further enhancing the handoff files to a state which is good for upstreaming. At same time, I am also working with tools team to ensure all these enhancement is putting back to original code. Thanks Chin Liang > > > Regards > > > Charles > > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Mainline u-boot SPL for socfpga
Hi, On Thu, 2014-05-15 at 07:01 +1200, Charles Manning wrote: > On Thursday 15 May 2014 04:42:58 Pavel Machek wrote: > > Hi! > > > > > I am trying to understand the state of the socfpga preloader in mainline > > > u-boot. > > > > > > >From what I see, this is broken and perhaps has never worked. > > > > That's correct AFAICT. Yup, Preloader without the SDRAM would not work correctly. > > > > > When I build the code in u-boot-socfpga I get a healthy working > > > u-boot-spl.bin of approx 45kbytes. > > > > > > When I build the mainline u-boot code I get a broken u-boot-spl.bin of > > > approx 3kbytes. > > > > > > It seems the mainline u-boot is missing stuff, including the all-critical > > > sdram initialisation without which the SPL is useless. > > > > Are you able to build working u-boot proper from recent sources? > > > > I know u-boot SPL misses critical parts, but I was told that u-boot > > proper should have everything. Only... I was not able to get it to > > work. [I'm attempting to load recent u-boot from patched/old u-boot; I > > know this is not exactly recommended, but due to spl/proper split, it > > should work AFAIK... and does for old versions.] > > I have not tried booting u-boot proper from mainline. It just seemed > pointless > to me to be working from 2 source trees to make a single product. > > I will give it a go though. Actually the U-Boot is working. You just need to #undef CONFIG_SOCFPGA_VIRTUAL_TARGET and build it. I loaded it using a working Preloader and I can reach the U-Boot console. U-Boot SPL 2013.01.01 (May 16 2014 - 10:42:39) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 25000 KHz CLOCK: EOSC2 clock 25000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 925 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 10 KHz CLOCK: MMC clock 5 KHz CLOCK: QSPI clock 37 KHz INFO : Watchdog enabled SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 1024 MiB SDRAM: ECC Enabled ALTERA DWMMC: 0 reading u-boot.img reading u-boot.img U-Boot 2014.07-rc1-00079-g2072e72-dirty (May 16 2014 - 15:54:55) CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone5 Board DRAM: 1 GiB WARNING: Caches not enabled Using default environment In:serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Wrong Image Format for bootm command ERROR: can't get kernel image! SOCFPGA_CYCLONE5 # help ? - alias for 'help' base- print or set address offset bdinfo - print Board Info structure boot- boot default, i.e., run 'bootcmd' bootd - boot default, i.e., run 'bootcmd' bootm - boot application image from memory bootp - boot image via network using BOOTP/TFTP protocol cmp - memory compare coninfo - print console devices and information cp - memory copy crc32 - checksum calculation echo- echo args to console editenv - edit environment variable env - environment handling commands exit- exit script false - do nothing, unsuccessfully fatinfo - print information about filesystem fatload - load binary file from a dos filesystem fatls - list files in a directory (default /) fdt - flattened device tree utility commands go - start application at address 'addr' help- print command description/usage iminfo - print header information for application image imxtract- extract a part of a multi-image itest - return true/false on integer compare loadb - load binary file over serial line (kermit mode) loads - load S-Record file over serial line loadx - load binary file over serial line (xmodem mode) loady - load binary file over serial line (ymodem mode) loop- infinite loop on address range md - memory display mm - memory modify (auto-incrementing address) mw - memory write (fill) nfs - boot image via network using NFS protocol nm - memory modify (constant address) printenv- print environment variables reset - Perform RESET of the CPU run - run commands in an environment variable setenv - set environment variables showvar - print local hushshell variables sleep - delay execution for some time source - run script from memory test- minimal test like /bin/sh tftpboot- boot image via network using TFTP protocol true- do nothing, successfully version - print monitor, compiler and linker version SOCFPGA_CYCLONE5 # > > As Chin Liang See has said, there are two issues thwarting this: legal AND > source conformance. The code we can fix, the legal can only be fixed by > bending Altera - I am going to do that too. We are making some progress on this. Once we have final green light, we will start the upstreaming of SDRAM code. :) Thanks Chin Liang > > Regards > > Charles ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] nand/denali: Adding Denali NAND driver support
Hi Masahiro, On Mon, 2014-05-26 at 13:58 +0900, Masahiro Yamada wrote: > Hi Chin, > > Could you tell me the status of Denali NAND driver? > > Please apply my feedback and post v8. > I really need this driver. > Sorry as I was busy on some issues recently. Let me work out the v8 patch and send out within this few days. Thanks for reminding. Chin Liang > Thanks, > > Best Regards > Masahiro Yamada > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nand/denali: Adding Denali NAND driver support
Hi Rik, This patch is for U-Boot only. You might wanna find the kernel patch at http://rocketboards.org/gitweb/?p=linux-socfpga.git;a=commit;h=23b95d8c25d34afadc82325313f25e72d76c5cef While for your issue, its quite strange. Currently, we are using 512 byte sector protected with 8 bit ECC. With this configuration, we will need around 58 bytes at OOB. This is to accommodate 2 bytes bad block market + 42 bytes data + 14 bytes ECC. Wonder you are using different configuration? Thanks and have a nice day! Chin Liang On Fri, 2014-05-30 at 11:06 +, Rik Smith wrote: > Chin, > >I was wondering which kernel this patch went into or is going into? > > I am having problems with accessing a hynix NAND from an altera > cyclone V > using kernel 3.11. It is coming up with a kernel driver error on boot > of: > "Your NAND chip OOB is not large enough to contain 8bit ECC correction > codes" > > Looking for help on this issue. > > Cheers > Rik > > kernel bootlog extract: > > at24 0-0051: 4096 byte 24c32 EEPROM, writable, 32 bytes/write > denali-nand-dt ff90.flash: Dump timing register values:acc_clks: > 0, > re_2_we: 50, re_2_re: 50 > we_2_re: 5170, addr_2_data: 5170, rdwr_en_lo_cnt: 18 > rdwr_en_hi_cnt: 12, cs_setup_cnt: 3 > NAND device: Manufacturer ID: 0xad, Chip ID: 0xd5 (Hynix NAND 2GiB > 3,3V > 8-bit), 2048MiB, page size: 4096, OOB size: 64 > Your NAND chip OOB is not large enough > to > contain 8bit ECC correction codes > cadence-qspi ff705000.flash: DMA NOT enabled > cadence-qspi ff705000.flash: master is unqueued, this is deprecated > m25p80 spi2.0: found n25q00, expected n25q512a > > > > __ > Rik Smith | Senior Software Engineer > > > > > > Optos Plc > Queensferry House > Carnegie Campus > Enterprise Way, Dunfermline > Scotland, UK > > KY11 8GR > > > > Tel: +44 (0)1383 843300 > > Dir: +44 (0)1383 843427 > > Fax:+44 (0)1383 84 > > Email: rsm...@optos.com > > Web: www.optos.com > > > > > > > Transmission of this email and any files that may be attached is > confidential and may contain proprietary information, and is intended > solely for the use of the individual(s) or entity to who it is > addressed. If you are not the intended recipient, any use including, > but not limited to, dissemination, printing or copying of the email > and its attachments is strictly prohibited.If you have received the > email in error you are requested to contact the sender by telephone > and permanently delete the material from your system.Any views or > opinions expressed herein are solely those of the individual sender > and do not necessarily represent those of Optos plc or its subsidiary > companies. Precautions have been taken to minimize the risk of > transmitting software viruses. Optos plc requests virus checks on any > attachments to this message are carried out by the recipient(s), as no > responsibility or liability can be assumed for any loss or damage to > the recipient's computer software or hardware. OPTOS PLC. SC139953. > REGISTERED OFFICE. QUEENSFERRY HOUSE, CARNEGIE CAMPUS, ENTERPRISE WAY, > DUNFERMLINE, SCOTLAND, KY11 8GR, UNITED KINGDOM; OPTOS INC. 67 FOREST > STREET, MARLBOROUGH, MA 01752, USA; OPTOS GmbH. PRINZENALLEE 7, > D-40549, DÜSSELDORF, GERMANY. GESCHÄFTSFÜHRER: ROY DAVIS, ROBERT > KENNEDY. AMTSGERICHT MANNHEIM HRB 700 960 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] generic board for socfpga
Hi Pavel, On Tue, 2014-05-27 at 14:50 +0200, ZY - pavel wrote: > Socfpga u-boot works fine with CONFIG_SYS_GENERIC_BOARD, so enable > that option as documentation suggests. > Yup, it works well for me without modification. Acked-by: Chin Liang See Thanks Chin Liang > Signed-off-by: Pavel Machek > > diff --git a/include/configs/socfpga_cyclone5.h > b/include/configs/socfpga_cyclone5.h > index 2fc16ef..72d77f4 100644 > --- a/include/configs/socfpga_cyclone5.h > +++ b/include/configs/socfpga_cyclone5.h > @@ -16,6 +16,8 @@ > /* Virtual target or real hardware */ > #define CONFIG_SOCFPGA_VIRTUAL_TARGET > > +#define CONFIG_SYS_GENERIC_BOARD > + > #define CONFIG_ARMV7 > #define CONFIG_SYS_DCACHE_OFF > #undef CONFIG_USE_IRQ > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Mainline u-boot SPL for socfpga
Hi Pavel, On Tue, 2014-05-27 at 14:40 +0200, ZY - pavel wrote: > Hi! > > (Sorry for the delay) > > > > > I know u-boot SPL misses critical parts, but I was told that u-boot > > > > proper should have everything. Only... I was not able to get it to > > > > work. [I'm attempting to load recent u-boot from patched/old u-boot; I > > > > know this is not exactly recommended, but due to spl/proper split, it > > > > should work AFAIK... and does for old versions.] > > > > > > I have not tried booting u-boot proper from mainline. It just seemed > > > pointless > > > to me to be working from 2 source trees to make a single product. > > > > > > I will give it a go though. > > > > > > Actually the U-Boot is working. You just need to #undef > > CONFIG_SOCFPGA_VIRTUAL_TARGET and build it. I loaded it using a working > > Preloader and I can reach the U-Boot console. > > Aha, you are right, I forgot about VIRTUAL_TARGET define. > > > U-Boot 2014.07-rc1-00079-g2072e72-dirty (May 16 2014 - 15:54:55) > > > > CPU : Altera SOCFPGA Platform > > BOARD : Altera SOCFPGA Cyclone5 Board > > DRAM: 1 GiB > > WARNING: Caches not enabled > > Using default environment > > > > In:serial > > Out: serial > > Err: serial > > Net: No ethernet found. > > Do you have any hints how to get ethernet to work? > I yet to upstream the ethernet part yet. I plan to do that once I upstreamed all the minimum SPL code to run on dev kit. > Plus, for me it says: > > tertiary u-boot 13.760972 Warning: Your board does not use generic > board. Please read > tertiary u-boot 13.770775 doc/README.generic-board and take > action. Boards not > tertiary u-boot 13.779813 upgraded by the late 2014 may break or be > removed. > I believe your patch already resolved this :) > > > > As Chin Liang See has said, there are two issues thwarting this: legal > > > AND > > > source conformance. The code we can fix, the legal can only be fixed by > > > bending Altera - I am going to do that too. > > > > > > We are making some progress on this. Once we have final green light, we > > will start the upstreaming of SDRAM code. :) > > Looking forward :-). Yup, work in progress. It slightly time consuming especially removing some unused code :) Thanks Chin Liang > > Thanks, > Pavel > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] Separate EBV Socrates board from Altera Cyclone 5 board and from Virtual Target
Hi guys, On Fri, 2014-05-30 at 11:41 +0200, Detlev Zundel wrote: > Hi Pavel, > > > On Wed 2014-05-28 16:29:50, Wolfgang Denk wrote: > >> In message <20140528124910.ga24...@amd.pavel.ucw.cz> you wrote: > >> > > >> > There are no differences between EBV socrates and socfpga boards, > >> > currently. > >> > >> Well, for one thing, the board vendor and the board name differ... > > > > I meant from current code in u-boot point of view... > > But as we all agree, this may change quickly and for multiple boards. Yup, some other board vendors are using different HW configuration. Some of the difference are Altera dev kit have EEPROM and using Micrel PHY for EMAC. I presume Socrates board should have their own board path such as board/socrates/socfpga. > > >> > > > AFAICT, one solution would be to put "-" in that column, and > >> > > > do "git > >> > > > mv board/altera/ board/socfpga/". > >> > > > >> > > Putting "-" in the vendor column just doesn't feel right. > >> > > >> > That's what mx6 did, AFAICT. > >> > >> I think Detlev is right here. We do have specific board vendors > >> directories, and there are a number of reasons to keep this used > >> (just to give one example: say a vendor wants to use a similar look > >> and feel for the default environment settings etc. for all boards). > > > >> If there is code which is identical for several (or all?) boards we > >> should ask ourself if it really belongs into the board/ directory at > >> all? > > > > That might be the case. It seems that current code in board/altera is > > SoC-specific, as it works on both Altera and EBV boards. > > Then we are in agreement that it does not belong below board/ ;) Within board/altera, there are 2 types of files as below: 1. HW configuration handoff files (such as pinmux_config, pll_config). Pinmux might be different as certain board might have different routing (normally to optimize the board layout and shorter PCB trace length). 2. Board specific code (socfpga_cyclone5.c) These functions include board_init, board_early_init, checkboard. I believe that the function print_cpuinfo and overwrite _console should goto arch/arm/cpu/armv7/socfpga/misc.c. I will create the patch to change this later (as I already did this at rocketboard.org). > > >> > Actually.. there's nothing Altera specific in board/altera (it works > >> > on ebv just fine), so board/socfpga sounds like a better name. But I > >> > don't think such rename should be done lightly, so I still believe the > >> > patch as submitted is the best way to go. > >> > >> I think board/altera as such makes sense, with Altera being the vendor > >> of that specific board. However, if there is common code there, this > >> code should be moved out of board/ . > > > > It seems there's currently 99.99% of SoC-specific code there. > > > > What would be the right place for that code? > > Depends on what exactly it implements. Apart from that we can also take > a look at where the code is in a Linux tree and take that as an > example. After all, we want people developing the Linux kernel to also > feel at home in the U-Boot sources. > > > arch/arm/cpu/armv7/socfpga/ ? But it is not really armv7-specific. > > drivers/misc ? Do we need to make a soc/ directory? > > We have arch/arm/imx-common for example, but I'm not so sure if this is > a good approach. Maybe there is not a _single_ correct place, but we > have to distribute the files to multiple directories? > > > And then... who does the move? It is not going to make merging between > > rocketboards.org and mainline even trickier than it already is :-(. > > This is a good question and we should certainly not answer it lightly. > Usually we care only to a certain degree for non-mainline code, though. > Blocking ourselves because of non-mainline code would allow "external" > control which I think is not really helpful for the project. > As above, I can move some common function to arch/arm/cpu/armv7/socfpga/misc.c. Thanks Chin Liang > Cheers > Detlev > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] Separate EBV Socrates board from Altera Cyclone 5 board and from Virtual Target
Hi Pavel,
On Tue, 2014-05-27 at 15:12 +0200, ZY - pavel wrote:
> Altera Cyclone 5 board is very different board (big, rectangular,
> expensive) than EBV Socrates (small, circular, cheap) board. Different
> parts are used there, too, but same configuration of u-boot works on
> both. Nevertheless, printing wrong name confuses users. Virtual target
> is completely different, and board configured for it will not boot on
> physical targets.
>
> Therefore this splits the configuration so that u-boot knows they are
> different. So far it is only used for correcting the puts, but there
> may be other uses in future.
>
> Signed-off-by: Pavel Machek
>
> ---
>
> Diff from v1: separate virtual target, too, and make it apply to
> recent u-boot.
>
> diff --git a/board/altera/socfpga/socfpga_cyclone5.c
> b/board/altera/socfpga/socfpga_cyclone5.c
> index a960eb6..33946b6 100644
> --- a/board/altera/socfpga/socfpga_cyclone5.c
> +++ b/board/altera/socfpga/socfpga_cyclone5.c
> @@ -28,7 +28,7 @@ int print_cpuinfo(void)
> */
> int checkboard(void)
> {
> - puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
> + puts("BOARD : " ALTERA_BOARD_NAME "\n");
> return 0;
> }
>
> diff --git a/boards.cfg b/boards.cfg
> index 221b7f8..6eebbf5 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -379,6 +379,8 @@ Active arm armv7 rmobile renesas
> lager
> Active arm armv7 s5pc1xx samsung goni
> s5p_goni -
>
> Przemyslaw Marczak
> Active arm armv7 s5pc1xx samsung smdkc100
> smdkc100 -
>
> Minkyu Kang
> Active arm armv7 socfpga altera socfpga
> socfpga_cyclone5 -
>
> -
> +Active arm armv7 socfpga altera socfpga
> socfpga_virtual -
>
> -
> +Active arm armv7 socfpga altera socfpga
> socfpga_socrates -
>
> -
> Active arm armv7 u8500 st-ericsson snowball
> snowball -
>
> Mathieu Poirier
> Active arm armv7 u8500 st-ericsson u8500
> u8500_href-
>
> -
> Active arm armv7 vf610 freescale vf610twr
> vf610twr
> vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg
> Alison Wang
>
> diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_common.h
> new file mode 100644
> index 000..4d90952
> --- /dev/null
> +++ b/include/configs/socfpga_common.h
> @@ -0,0 +1,240 @@
> +/*
> + * Copyright (C) 2012 Altera Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef __CONFIG_COMMON_H
> +#define __CONFIG_COMMON_H
> +
> +#include
> +#include "../../board/altera/socfpga/pinmux_config.h"
> +#include "../../board/altera/socfpga/pll_config.h"
> +
I believe these should go to board specific header file such as
socfpga_cyclone5 and socfpga_socrates. These are HW configuration
handoff files and different from board to board.
> +/*
> + * Hardware drivers
> + */
> +
> +/*
> + * SDRAM Memory Map
> + */
> +/* We have 1 bank of DRAM */
> +#define CONFIG_NR_DRAM_BANKS 1
> +/* SDRAM Bank #1 */
> +#define CONFIG_SYS_SDRAM_BASE0x
> +/* SDRAM memory size */
> +#define PHYS_SDRAM_1_SIZE0x4000
> +
Just a quick comments. In newer version SPL at rocketboard.org, we won't
need to specify the size. It will be calculated based on HW registers.
We will change this together with SPL SDRAM patch.
> diff --git a/include/configs/socfpga_cyclone5.h
> b/include/configs/socfpga_cyclone5.h
> index 517070c..d5d59d2 100644
> --- a/include/configs/socfpga_cyclone5.h
> +++ b/include/configs/socfpga_cyclone5.h
> @@ -1,242 +1,1
[U-Boot] [PATCH v8] nand/denali: Adding Denali NAND driver support
To add the Denali NAND driver support into U-Boot. It required
information such as register base address from configuration
header file within include/configs folder.
Signed-off-by: Chin Liang See
Cc: Artem Bityutskiy
Cc: David Woodhouse
Cc: Brian Norris
Cc: Scott Wood
Cc: Masahiro Yamada
---
Changes for v8
- Applied Masahiro's patch as below
- Replaced "denali->foo" with "denali.foo"
- Fixed denali_write_oob() handler
- Made denali_read_oob() 10x faster
Changes for v7
- Adding Masahiro's code to support 64bit version controller
- Removed unused stub functions
- Enhanced the ECC calculation
Changes for v6
- Remove chip_delay as its unused
- Remove ECC bit assignment in nand_para functions
Changes for v5
- Rename denali_nand to denali only
- Rename the macro for ctrl and data address
Changes for v4
- Added cache flush to handle dcache enabled
- Used standard return where 0 for pass
- Removed unnecessary casting
- Used standard readl and writel
Changes for v3
- Fixed coding style
Changes for v2
- Enable this driver support for SOCFPGA
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/denali.c | 1214 +
drivers/mtd/nand/denali.h | 490 ++
3 files changed, 1705 insertions(+)
create mode 100644 drivers/mtd/nand/denali.c
create mode 100644 drivers/mtd/nand/denali.h
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 02b149c..76ae105 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
+obj-$(CONFIG_NAND_DENALI) += denali.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
new file mode 100644
index 000..7e16bf3
--- /dev/null
+++ b/drivers/mtd/nand/denali.c
@@ -0,0 +1,1214 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2013-2014, Altera Corporation
+ * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "denali.h"
+
+#define NAND_DEFAULT_TIMINGS -1
+
+static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
+
+/* We define a macro here that combines all interrupts this driver uses into
+ * a single constant value, for convenience. */
+#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
+ INTR_STATUS__ECC_TRANSACTION_DONE | \
+ INTR_STATUS__ECC_ERR | \
+ INTR_STATUS__PROGRAM_FAIL | \
+ INTR_STATUS__LOAD_COMP | \
+ INTR_STATUS__PROGRAM_COMP | \
+ INTR_STATUS__TIME_OUT | \
+ INTR_STATUS__ERASE_FAIL | \
+ INTR_STATUS__RST_COMP | \
+ INTR_STATUS__ERASE_COMP | \
+ INTR_STATUS__ECC_UNCOR_ERR | \
+ INTR_STATUS__INT_ACT | \
+ INTR_STATUS__LOCKED_BLK)
+
+/* indicates whether or not the internal value for the flash bank is
+ * valid or not */
+#define CHIP_SELECT_INVALID-1
+
+#define SUPPORT_8BITECC1
+
+/*
+ * this macro allows us to convert from an MTD structure to our own
+ * device context (denali) structure.
+ */
+#define mtd_to_denali(m) (((struct nand_chip *)mtd->priv)->priv)
+
+/* These constants are defined by the driver to enable common driver
+ * configuration options. */
+#define SPARE_ACCESS 0x41
+#define MAIN_ACCESS0x42
+#define MAIN_SPARE_ACCESS 0x43
+
+#define DENALI_UNLOCK_START0x10
+#define DENALI_UNLOCK_END 0x11
+#define DENALI_LOCK0x21
+#define DENALI_LOCK_TIGHT 0x31
+#define DENALI_BUFFER_LOAD 0x60
+#define DENALI_BUFFER_WRITE0x62
+
+#define DENALI_READ0
+#define DENALI_WRITE 0x100
+
+/* types of device accesses. We can issue commands and get status */
+#define COMMAND_CYCLE 0
+#define ADDR_CYCLE 1
+#define STATUS_CYCLE 2
+
+/* this is a helper macro that allows us to
+ * format the bank into the proper bits for the controller */
+#define BANK(x) ((x) << 24)
+
+/* Interrupts are cleared by writing a 1 to the appropriate status bit */
+static inline void clear_interrupt(struct denali_nand_info *denali,
+ uint32_t irq_mask)
+{
+ uint32_t intr_status_reg;
+
+ intr_status_reg = INTR_STATUS(denali->flash_bank);
+
+ writel(irq_mask, denali->flash_reg + intr_status_reg);
+}
+
+static uint32_t read_interrupt_status(struct denali_nand_info *denali)
+{
+ uint32_t intr_status_reg;
+
+ intr_status_reg = I
[U-Boot] [PATCH v5 1/2] watchdog/denali: Adding DesignWare watchdog driver support
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See
Cc: Anatolij Gustschin
Cc: Albert Aribaud
Cc: Heiko Schocher
Cc: Tom Rini
---
Changes for v5
- Updated to latest code branch
Changes for v4
- Added static for local function
Changes for v3
- Split to 2 series patch
Changes for v2
- Enable this driver at socfpga_cyclone5 board
---
drivers/watchdog/Makefile |1 +
drivers/watchdog/designware_wdt.c | 74 +
2 files changed, 75 insertions(+)
create mode 100644 drivers/watchdog/designware_wdt.c
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 06ced10..0276a10 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
+obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
new file mode 100644
index 000..e788e1b
--- /dev/null
+++ b/drivers/watchdog/designware_wdt.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#define DW_WDT_CR 0x00
+#define DW_WDT_TORR0x04
+#define DW_WDT_CRR 0x0C
+
+#define DW_WDT_CR_EN_OFFSET0x00
+#define DW_WDT_CR_RMOD_OFFSET 0x01
+#define DW_WDT_CR_RMOD_VAL 0x00
+#define DW_WDT_CRR_RESTART_VAL 0x76
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+static int designware_wdt_settimeout(unsigned int timeout)
+{
+ signed int i;
+
+ /* calculate the timeout range value */
+ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
+ if (i > 15)
+ i = 15;
+ if (i < 0)
+ i = 0;
+
+ writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
+ return 0;
+}
+
+static void designware_wdt_enable(void)
+{
+ writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
+ (0x1 << DW_WDT_CR_EN_OFFSET)),
+ (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+}
+
+static unsigned int designware_wdt_is_enabled(void)
+{
+ unsigned long val;
+ val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ return val & 0x1;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ if (designware_wdt_is_enabled())
+ /* restart the watchdog counter */
+ writel(DW_WDT_CRR_RESTART_VAL,
+ (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+}
+
+void hw_watchdog_init(void)
+{
+ /* reset to disable the watchdog */
+ hw_watchdog_reset();
+ /* set timer in miliseconds */
+ designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
+ /* enable the watchdog */
+ designware_wdt_enable();
+ /* reset the watchdog */
+ hw_watchdog_reset();
+}
+#endif
--
1.7.9.5
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[U-Boot] [PATCH v5 2/2] socfpga: Adding DesignWare watchdog support
To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: Chin Liang See Cc: Anatolij Gustschin Cc: Albert Aribaud Cc: Heiko Schocher Cc: Tom Rini --- Changes for v5 - Updated to latest code branch Changes for v4 - Updated to latest code branch Changes for v3 - Split to 2 series patch Changes for v2 - Enable this driver at socfpga_cyclone5 board --- .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + include/configs/socfpga_cyclone5.h | 14 ++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index f564046..f2ecbbd 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -11,6 +11,7 @@ #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 0254249..34291c7 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -206,6 +206,17 @@ #define CONFIG_ENV_IS_NOWHERE /* + * L4 Watchdog + */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 +#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +/* Clocks source frequency to watchdog timer */ +#define CONFIG_DW_WDT_CLOCK_KHZ25000 + + +/* * SPL "Second Program Loader" aka Initial Software */ @@ -237,4 +248,7 @@ /* Support for lib/libgeneric.o in SPL binary */ #define CONFIG_SPL_LIBGENERIC_SUPPORT +/* Support for watchdog */ +#define CONFIG_SPL_WATCHDOG_SUPPORT + #endif /* __CONFIG_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8] socfpga: Adding Scan Manager driver
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud
---
Changes for v8
- Updated to latest code branch
Changes for v7
- Enhance the function scan_chain_engine_is_idle
Changes for v6
- Fixed various coding style issue
Changes for v5
- Removal of additional blank line
- Added comment for magic number
Changes for v4
- avoid code duplication by add goto error
- include underscore to variables name
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 209 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 980 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index cbe1d40..eb33f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..a820b1b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(&scan_manager_base->stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
+ (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+ max_iter--;
+ if (max_iter > 0)
+ scanmgr_status = readl(&scan_manager_base->stat);
+ else
+ return 0;
+ }
+ return 1;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /*
+* De-assert reinit if the IO scan chain is intended for HIO. In
+* this, its the chain 3.
+*/
+ if (io_scan_chain_id == 3)
+ clrbits_le32(&freeze_controller_base->hioctrl,
+SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+ return 1;
+
+ /*
+* Enable IO Scan chain based on scan chain id
+* Note: only one chain can be enabled at a time
+*/
+ setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+ /*
+* Calculate number of iteration needed for full 128-bit (4 x32-bits)
+* bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+*/
+ io_program_iter = io_scan_chain_len_in_bits >>
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
[U-Boot] [PATCH] mmc/dw_mmc: Fix clock divider calculation error for bypass mode
To fix the clock divider calculation error when the controller clock same as the operating frequency. This is known as bypass mode. In this mode, the divider should be 0. Signed-off-by: Chin Liang See Cc: Pantelis Antoniou Cc: Rajeshwari Shinde Cc: Jaehoon Chung Cc: Mischa Jonker --- drivers/mmc/dw_mmc.c |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 5bf36a0..0df30bc 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -245,7 +245,10 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) return -EINVAL; } - div = DIV_ROUND_UP(sclk, 2 * freq); + if (sclk == freq) + div = 0;/* bypass mode */ + else + div = DIV_ROUND_UP(sclk, 2 * freq); dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] socfpga: Relocate arch common functions away from board
To move the arch common function away from board folder to
arch/arm/cpu/armv7/socfpga folder.
Signed-off-by: Chin Liang See
Cc: Wolfgang Denk
Cc: Detlev Zundel
Cc: Pavel Machek
Cc: Dinh Nguyen
---
arch/arm/cpu/armv7/socfpga/misc.c | 24
board/altera/socfpga/socfpga_cyclone5.c | 23 ---
2 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 2f1c716..5268f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -14,3 +14,27 @@ int dram_init(void)
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+ puts("CPU : Altera SOCFPGA Platform\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
+defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+ return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/board/altera/socfpga/socfpga_cyclone5.c
b/board/altera/socfpga/socfpga_cyclone5.c
index a960eb6..f366565 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -12,17 +12,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_DISPLAY_CPUINFO)
-/*
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
- puts("CPU : Altera SOCFPGA Platform\n");
- return 0;
-}
-#endif
-
/*
* Print Board information
*/
@@ -49,18 +38,6 @@ int board_init(void)
return 0;
}
-int misc_init_r(void)
-{
- return 0;
-}
-
-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) &&
defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-int overwrite_console(void)
-{
- return 0;
-}
-#endif
-
/*
* DesignWare Ethernet initialization
*/
--
1.7.9.5
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Re: [U-Boot] [PATCH] socfpga: Relocate arch common functions away from board
Hi Albert,
On Tue, 2014-06-10 at 09:07 +0200, ZY - albert.u.boot wrote:
> Hi Chin,
>
> On Tue, 10 Jun 2014 01:41:06 -0500, Chin Liang See
> wrote:
>
> > To move the arch common function away from board folder to
> > arch/arm/cpu/armv7/socfpga folder.
> >
> > Signed-off-by: Chin Liang See
> > Cc: Wolfgang Denk
> > Cc: Detlev Zundel
> > Cc: Pavel Machek
> > Cc: Dinh Nguyen
> > ---
> > arch/arm/cpu/armv7/socfpga/misc.c | 24
> > board/altera/socfpga/socfpga_cyclone5.c | 23 ---
> > 2 files changed, 24 insertions(+), 23 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
> > b/arch/arm/cpu/armv7/socfpga/misc.c
> > index 2f1c716..5268f2c 100644
> > --- a/arch/arm/cpu/armv7/socfpga/misc.c
> > +++ b/arch/arm/cpu/armv7/socfpga/misc.c
> > @@ -14,3 +14,27 @@ int dram_init(void)
> > gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
> > return 0;
> > }
> > +
> > +#if defined(CONFIG_DISPLAY_CPUINFO)
> > +/*
> > + * Print CPU information
> > + */
> > +int print_cpuinfo(void)
> > +{
> > + puts("CPU : Altera SOCFPGA Platform\n");
> > + return 0;
> > +}
> > +#endif
> > +
> > +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
> > +defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
> > +int overwrite_console(void)
> > +{
> > + return 0;
> > +}
> > +#endif
> > +
> > +int misc_init_r(void)
> > +{
> > + return 0;
> > +}
> > diff --git a/board/altera/socfpga/socfpga_cyclone5.c
> > b/board/altera/socfpga/socfpga_cyclone5.c
> > index a960eb6..f366565 100644
> > --- a/board/altera/socfpga/socfpga_cyclone5.c
> > +++ b/board/altera/socfpga/socfpga_cyclone5.c
> > @@ -12,17 +12,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -#if defined(CONFIG_DISPLAY_CPUINFO)
> > -/*
> > - * Print CPU information
> > - */
> > -int print_cpuinfo(void)
> > -{
> > - puts("CPU : Altera SOCFPGA Platform\n");
> > - return 0;
> > -}
> > -#endif
> > -
> > /*
> > * Print Board information
> > */
> > @@ -49,18 +38,6 @@ int board_init(void)
> > return 0;
> > }
> >
> > -int misc_init_r(void)
> > -{
> > - return 0;
> > -}
> > -
> > -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) &&
> > defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
> > -int overwrite_console(void)
> > -{
> > - return 0;
> > -}
> > -#endif
> > -
> > /*
> > * DesignWare Ethernet initialization
> > */
>
> Can you clarify in the commit message why this change is needed or
> useful?
>
Sure, let me send out the v2.
Its to avoid code duplication for other non Altera board which use
socfpga.
Thanks
Chin Liang
> Amicalement,
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[U-Boot] [PATCH v2] socfpga: Relocate arch common functions away from board
To move the arch common function away from board folder to
arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication
for other non Altera dev kit which is using socfpga device.
Signed-off-by: Chin Liang See
Cc: Wolfgang Denk
Cc: Detlev Zundel
Cc: Pavel Machek
Cc: Dinh Nguyen
---
Changes for v2
- Added the purpose of the patch to commit message
---
arch/arm/cpu/armv7/socfpga/misc.c | 24
board/altera/socfpga/socfpga_cyclone5.c | 23 ---
2 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 2f1c716..5268f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -14,3 +14,27 @@ int dram_init(void)
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+ puts("CPU : Altera SOCFPGA Platform\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
+defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+ return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/board/altera/socfpga/socfpga_cyclone5.c
b/board/altera/socfpga/socfpga_cyclone5.c
index a960eb6..f366565 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -12,17 +12,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_DISPLAY_CPUINFO)
-/*
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
- puts("CPU : Altera SOCFPGA Platform\n");
- return 0;
-}
-#endif
-
/*
* Print Board information
*/
@@ -49,18 +38,6 @@ int board_init(void)
return 0;
}
-int misc_init_r(void)
-{
- return 0;
-}
-
-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) &&
defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-int overwrite_console(void)
-{
- return 0;
-}
-#endif
-
/*
* DesignWare Ethernet initialization
*/
--
1.7.9.5
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Re: [U-Boot] [PATCH v2] socfpga: Relocate arch common functions away from board
On Thu, 2014-06-12 at 11:02 +0200, Detlev Zundel wrote: > Hi Chin, > > > To move the arch common function away from board folder to > > arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication > > for other non Altera dev kit which is using socfpga device. > > This looks like a good first step. I'm sure that followup patches are > neccessary to clean up the division between generic and board specific > patches, but we'll see this once other boards (like socrates) are added. > > Pavel, can you rebase your intended change on this? Thanks! > > Acked-by: Detlev Zundel > Thanks Detlev. Hi Albert, Can you help to apply this patch? Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v8] nand/denali: Adding Denali NAND driver support
On Tue, 2014-06-10 at 21:45 +0900, Masahiro Yamada wrote: > Hi Chin, > > > On Tue, 10 Jun 2014 00:42:19 -0500 > Chin Liang See wrote: > > > To add the Denali NAND driver support into U-Boot. It required > > information such as register base address from configuration > > header file within include/configs folder. > > > > Signed-off-by: Chin Liang See > > Cc: Artem Bityutskiy > > Cc: David Woodhouse > > Cc: Brian Norris > > Cc: Scott Wood > > Cc: Masahiro Yamada > > > Thanks for posting v8 when you are busy! > > Signed-off-by: Masahiro Yamada > Reviewed-by: Masahiro Yamada > Tested-by: Masahiro Yamada > > > > Scott, > Could you apply this patch please? > > Thanks Masahiro Hi Scott / Tom, Can you help to apply this patch? Thanks Chin Liang > > Best Regards > Masahiro Yamada > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit
socfpga: Separating the configuration file for Virtual Target and
real hardware Cyclone V development kit
Signed-off-by: Chin Liang See
---
include/configs/socfpga_cyclone5.h | 28 +---
1 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 5633d2a..86563b7 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -22,6 +22,8 @@
/*
* High level configuration
*/
+/* Running on virtual target or real hardware */ #define
+CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
#define CONFIG_L2_OFF
@@ -32,11 +34,12 @@
#define CONFIG_SINGLE_BOOTLOADER
#define CONFIG_SOCFPGA
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE0x0840
-#define V_NS16550_CLK100
-#define CONFIG_BAUDRATE57600
-#define CONFIG_SYS_HZ1000
-#define CONFIG_TIMER_CLOCK_KHZ2400
+#else
+#define CONFIG_SYS_TEXT_BASE0x0140
+#endif
#define CONFIG_SYS_LOAD_ADDR0x7fc0
/* Console I/O Buffer Size */
@@ -165,7 +168,7 @@
/* SDRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE0x
/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE0x8000
+#define PHYS_SDRAM_1_SIZE0x4000
#define PHYS_SDRAM_1CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START0x
@@ -181,8 +184,13 @@
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1UART0_BASE
-
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK100
+#else
+#define V_NS16550_CLK1
+#endif
+#define CONFIG_BAUDRATE115200
/*
* FLASH
@@ -195,9 +203,15 @@
/* This timer use eosc1 where the clock frequency is fixed
* throughout any condition */
#define CONFIG_SYS_TIMERBASESOCFPGA_OSC1TIMER0_ADDRESS
-
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL0x
+/* Timer info */
+#define CONFIG_SYS_HZ1000
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_TIMER_CLOCK_KHZ2400
+#else
+#define CONFIG_TIMER_CLOCK_KHZ25000
+#endif
#define CONFIG_ENV_IS_NOWHERE
--
1.7.7.4
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[U-Boot] [PATCH 1/1] socfpga: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V
socfpga: Adding System Manager driver which will configure the pin mux
for real hardware Cyclone V development kit (not Virtual Platform)
Signed-off-by: Chin Liang See
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/spl.c |6 +
arch/arm/cpu/armv7/socfpga/system_manager.c| 40
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
arch/arm/include/asm/arch-socfpga/system_manager.h | 32 +++
board/altera/socfpga_cyclone5/Makefile |4 +-
board/altera/socfpga_cyclone5/pinmux_config.c | 213
board/altera/socfpga_cyclone5/pinmux_config.h | 53 +
include/configs/socfpga_cyclone5.h |1 +
9 files changed, 350 insertions(+), 2 deletions(-) create mode
100644 arch/arm/cpu/armv7/socfpga/system_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/system_manager.h
create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.c
create mode 100644 board/altera/socfpga_cyclone5/pinmux_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 518e67a..cf2829a 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS-y:= misc.o timer.o reset_manager.o
+COBJS-y:= misc.o timer.o reset_manager.o system_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 84216eb..28d8c99 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -36,6 +37,11 @@ u32 spl_boot_device(void)
*/
void spl_board_init(void)
{
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ /* configure the pin muxing through system manager */
+ sysmgr_pinmux_init();
+#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
+
/* de-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
new file mode 100644
index 000..f2707d8b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or
+modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but
+WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin mux
+ */
+void sysmgr_pinmux_init(void)
+{
+ unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+
+ const unsigned long *pval = sys_mgr_init_table;
+ unsigned long i;
+
+ for (i = 0;
+ i < ((sizeof(sys_mgr_init_table)) / sizeof(unsigned long));
+ i++, offset += sizeof(unsigned long)) {
+ writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+ }
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index f353eb2..819c280 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -23,5 +23,6 @@
#define SOCFPGA_UART1_ADDRESS 0xffc03000 #define
SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 #define SOCFPGA_RSTMGR_ADDRESS
0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
new file mode 100644
index 000..aec9be7
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or
+modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but
+WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+License
+ * for more details.
+ *
+ * You should have received
[U-Boot] [PATCH 1/1] socfpga: Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit
socfpga: Consolidating reset code into reset_manager.c. Also separating
reset configuration for virtual target and real hardware Cyclone V
development kit
Signed-off-by: Chin Liang See
---
arch/arm/cpu/armv7/socfpga/Makefile |2 +-
arch/arm/cpu/armv7/socfpga/misc.c | 27 ---
arch/arm/cpu/armv7/socfpga/reset_manager.c| 50 +
arch/arm/include/asm/arch-socfpga/reset_manager.h | 17 +++
4 files changed, 68 insertions(+), 28 deletions(-) create mode
100644 arch/arm/cpu/armv7/socfpga/reset_manager.c
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 376a4bd..518e67a 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS:= lowlevel_init.o
-COBJS-y:= misc.o timer.o
+COBJS-y:= misc.o timer.o reset_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS:= $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index fa16424..59f5b94 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -17,36 +17,9 @@
#include
#include
-#include
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
-(void *)SOCFPGA_RSTMGR_ADDRESS;
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
-/* request a warm reset */
-writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
-/*
- * infinite loop here as watchdog will trigger and reset
- * the processor
- */
-while (1)
-;
-}
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
-writel(0, &reset_manager_base->per_mod_reset);
-}
-
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE); diff --git
a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
new file mode 100644
index 000..b0cc399
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright Altera Corporation (C) <2013>. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or
+modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but
+WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset */ void
+reset_cpu(ulong addr) {
+/* request a warm reset */
+writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+&reset_manager_base->ctrl);
+/*
+ * infinite loop here as watchdog will trigger and reset
+ * the processor
+ */
+while (1)
+;
+}
+
+/*
+ * Release peripherals from reset based on handoff */ void
+reset_deassert_peripherals_handoff(void)
+{
+writel(0, &reset_manager_base->per_mod_reset);
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index d9d2c1c..58d85e3 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -21,6 +21,7 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
struct socfpga_reset_manager {
u32padding1;
u32ctrl;
@@ -31,7 +32,23 @@ struct socfpga_reset_manager {
u32per2_mod_reset;
u32brg_mod_reset;
};
+#else
+struct socfpga_reset_manager {
+u32status;
+u32ctrl;
+u32counts;
+u32padding1;
+u32mpu_mod_reset;
+u32per_mod_reset;
+u32per2_mod_reset;
+u32brg_mod_reset;
+};
+#endif
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
+#else
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#endif
#endif /* _RESET_MANAGER_H_ */
--
1.7.7.4
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strictly prohibited. If you have received t
