Re: [U-Boot] [PATCH v2 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
Hi Lukasz,
在 2019/1/19 上午7:34, Lukasz Majewski 写道:
Hi David,
Hi Heiko,
在 2019/1/6 上午1:17, Heiko Stuebner 写道:
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c index
3c6c3d3c09..a5e4d39cb7 100644 ---
a/arch/arm/mach-rockchip/rk3188-board-spl.c +++
b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -120,7 +120,7 @@
void board_debug_uart_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
#define EARLY_UART
@@ -134,10 +134,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
Did you test this change?
I remember rk3188 having issues (aka hanging) when trying to print
strings through the debug uart and only printch working at all.
(Timer issue or so?) ... Not sure if this got fixed in the meantime?
But you are using the debug uart for "production". Please use the
proper driver.
You may either properly setup normal uart or buffer the console output
until the uart is configured by device model (DM).
Here, we just use it for debug print, and the sram size is limited to
use more complex driver at spl stage.
I don't know there was a issue, but i test it on the Radxa board
today, it looks okay.
U-Boot SPL board init
U-Boot SPL 2019.01-rc1-9-gdd7b9156fe (Jan 14 2019 - 19:53:50
+0800) Returning to boot ROM...
U-Boot 2019.01-rc1-9-gdd7b9156fe (Jan 14 2019 - 19:53:50 +0800)
Model: Radxa Rock
DRAM: 2 GiB
MMC: dwmmc@10214000: 0
Loading Environment from MMC... Card did not respond to voltage
select! *** Warning - No block device, using default environment
In:serial@20064000
Out: serial@20064000
Err: serial@20064000
Model: Radxa Rock
rockchip_dnl_key_pressed: adc_channel_single_shot fail!
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
=>
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Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [U-Boot] [PATCH v2 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
Hi Heiko,
在 2019/1/6 上午1:17, Heiko Stuebner 写道:
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 3c6c3d3c09..a5e4d39cb7 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -120,7 +120,7 @@ void board_debug_uart_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
#define EARLY_UART
@@ -134,10 +134,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
Did you test this change?
I remember rk3188 having issues (aka hanging) when trying to print
strings through the debug uart and only printch working at all.
(Timer issue or so?) ... Not sure if this got fixed in the meantime?
I don't know there was a issue, but i test it on the Radxa board today,
it looks okay.
U-Boot SPL board init
U-Boot SPL 2019.01-rc1-9-gdd7b9156fe (Jan 14 2019 - 19:53:50 +0800)
Returning to boot ROM...
U-Boot 2019.01-rc1-9-gdd7b9156fe (Jan 14 2019 - 19:53:50 +0800)
Model: Radxa Rock
DRAM: 2 GiB
MMC: dwmmc@10214000: 0
Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment
In:serial@20064000
Out: serial@20064000
Err: serial@20064000
Model: Radxa Rock
rockchip_dnl_key_pressed: adc_channel_single_shot fail!
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
=>
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[U-Boot] [PATCH v2 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.
Signed-off-by: David Wu
---
Changes in v2: None
arch/arm/dts/rk322x.dtsi | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index be026b0e07..4a8be5dabb 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -206,7 +206,7 @@
clocks = < SCLK_UART2>, < PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
- pinctrl-0 = <_xfer>;
+ pinctrl-0 = <_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -748,7 +748,7 @@
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <1 RK_PC2 RK_FUNC_2
_pull_none>,
+ rockchip,pins = <1 RK_PC2 RK_FUNC_2
_pull_up>,
<1 RK_PC3 RK_FUNC_2
_pull_none>;
};
@@ -760,6 +760,13 @@
rockchip,pins = <0 RK_PD0 RK_FUNC_1
_pull_none>;
};
};
+
+ uart2-1 {
+ uart21_xfer: uart21-xfer {
+ rockchip,pins = <1 10 RK_FUNC_2 _pull_up>,
+ <1 9 RK_FUNC_2 _pull_none>;
+ };
+ };
};
dmc: dmc@1120 {
--
2.19.1
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[U-Boot] [PATCH v2 7/9] rockchip: defconfig: Clean the unused pinctrl config
If we used the pinctrl-rockchip driver, these config is not needed, so remove them. Signed-off-by: David Wu --- Changes in v2: None configs/chromebit_mickey_defconfig | 2 -- configs/chromebook_jerry_defconfig | 2 -- configs/chromebook_minnie_defconfig | 2 -- configs/evb-px5_defconfig | 1 - configs/evb-rk3128_defconfig| 1 - configs/evb-rk3229_defconfig| 1 - configs/evb-rk3288_defconfig| 2 -- configs/evb-rk3399_defconfig| 1 - configs/evb-rv1108_defconfig| 1 - configs/fennec-rk3288_defconfig | 2 -- configs/firefly-rk3288_defconfig| 2 -- configs/firefly-rk3399_defconfig| 1 - configs/geekbox_defconfig | 1 - configs/kylin-rk3036_defconfig | 1 - configs/lion-rk3368_defconfig | 1 - configs/miqi-rk3288_defconfig | 2 -- configs/phycore-rk3288_defconfig| 2 -- configs/popmetal-rk3288_defconfig | 2 -- configs/puma-rk3399_defconfig | 1 - configs/rock2_defconfig | 2 -- configs/rock_defconfig | 1 - configs/sandbox_defconfig | 2 -- configs/sandbox_flattree_defconfig | 2 -- configs/sandbox_noblk_defconfig | 2 -- configs/sheep-rk3368_defconfig | 1 - configs/tinker-rk3288_defconfig | 2 -- configs/vyasa-rk3288_defconfig | 2 -- 27 files changed, 42 deletions(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 5fbb5a4ebc..2b3e7b409a 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -61,8 +61,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index f6f0697050..d8db223e90 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -63,8 +63,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 705a3cd0e5..ee92a22e18 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -62,8 +62,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index c3bda3bf3b..1d428e7ac8 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -22,7 +22,6 @@ CONFIG_CLK=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3368=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index 044e60735a..17ad6ae58d 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -31,7 +31,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3128=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 0cc92a3314..14ff54af20 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -44,7 +44,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=150 diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 1485844aa6..4bf548790c 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -57,8 +57,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 27cf8304be..9746755f1e 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -49,7 +49,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3399=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 2ef041f2c5..7836a772e2 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -37,7 +37,6 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RV1108=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=150
[U-Boot] [PATCH v2 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Signed-off-by: David Wu --- Changes in v2: - Remove px30, rk2928, rk3066*. - Split it to multiple files for the relevant per-SoC data structures. drivers/pinctrl/Kconfig | 91 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/rockchip/Kconfig | 17 + drivers/pinctrl/rockchip/Makefile | 19 +- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 65 ++ drivers/pinctrl/rockchip/pinctrl-rk3128.c | 155 drivers/pinctrl/rockchip/pinctrl-rk3188.c | 82 ++ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 215 + drivers/pinctrl/rockchip/pinctrl-rk3288.c | 157 drivers/pinctrl/rockchip/pinctrl-rk3328.c | 227 + drivers/pinctrl/rockchip/pinctrl-rk3368.c | 116 +++ drivers/pinctrl/rockchip/pinctrl-rk3399.c | 193 + .../pinctrl/rockchip/pinctrl-rockchip-core.c | 788 ++ drivers/pinctrl/rockchip/pinctrl-rockchip.h | 302 +++ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 203 + 15 files changed, 2532 insertions(+), 100 deletions(-) create mode 100644 drivers/pinctrl/rockchip/Kconfig create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3128.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3188.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk322x.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3288.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3328.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3368.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3399.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip-core.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip.h create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1108.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7e6fad305a..d2168f7b72 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -158,96 +158,6 @@ config PINCTRL_QCA953X the GPIO definitions and pin control functions for each available multiplex function. -config PINCTRL_ROCKCHIP_RK3036 - bool "Rockchip rk3036 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3036 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3128 - bool "Rockchip rk3128 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3128 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3188 - bool "Rockchip rk3188 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3188 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK322X - bool "Rockchip rk322x pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk322x SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3288 - bool "Rockchip rk3288 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3288 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3328 - bool "Rockchip rk3328 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3328 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3368 - bool "Rockchip RK3368 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3368 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3399 - bool "Rockchip rk3399 pin control dr
[U-Boot] [PATCH v2 5/9] rk3288: chrome: defconfig: Enable FDT for new pinctrl driver
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA and enable SPL_OF_LIBFDT to make FDT be built in. Signed-off-by: David Wu --- Changes in v2: None configs/chromebit_mickey_defconfig | 2 -- configs/chromebook_jerry_defconfig | 2 -- configs/chromebook_minnie_defconfig | 2 -- 3 files changed, 6 deletions(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 79ab6acaec..5fbb5a4ebc 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -38,7 +38,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -93,4 +92,3 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index d892d65bf0..f6f0697050 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -40,7 +40,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -95,4 +94,3 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index b042874073..705a3cd0e5 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -39,7 +39,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -95,4 +94,3 @@ CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu
Reviewed-by: Philipp Tomsich
---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board-spl.c | 79 ---
1 file changed, 79 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index abd62e520f..9463b255e1 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -77,45 +77,6 @@ fallback:
return BOOT_DEVICE_MMC1;
}
-#ifdef CONFIG_SPL_MMC_SUPPORT
-static int configure_emmc(struct udevice *pinctrl)
-{
-#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
-
- struct gpio_desc desc;
- int ret;
-
- pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
-
- /*
-* TODO(s...@chromium.org): Pick this up from device tree or perhaps
-* use the EMMC_PWREN setting.
-*/
- ret = dm_gpio_lookup_name("D9", );
- if (ret) {
- debug("gpio ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_request(, "emmc_pwren");
- if (ret) {
- debug("gpio_request ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_dir_flags(, GPIOD_IS_OUT);
- if (ret) {
- debug("gpio dir ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_value(, 1);
- if (ret) {
- debug("gpio value ret=%d\n", ret);
- return ret;
- }
-#endif
- return 0;
-}
-#endif
-
#if !defined(CONFIG_SPL_OF_PLATDATA)
static int phycore_init(void)
{
@@ -144,7 +105,6 @@ static int phycore_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl;
struct udevice *dev;
int ret;
@@ -183,12 +143,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
#if !defined(CONFIG_SPL_OF_PLATDATA)
if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
ret = phycore_init();
@@ -239,52 +193,19 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
-
if (ret) {
debug("LED ret=%d\n", ret);
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
- ret = configure_emmc(pinctrl);
- if (ret) {
- debug("%s: Failed to set up eMMC\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
#ifdef CONFIG_SPL_OS_BOOT
--
2.19.1
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[U-Boot] [PATCH v2 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
It seems that pinctrl is not requested for rk3188 SPL, remove it so that can save more space for SPL image size. Signed-off-by: David Wu Reviewed-by: Philipp Tomsich --- Changes in v2: None arch/arm/mach-rockchip/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6dc8e3a017..15c6ed2340 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -29,7 +29,6 @@ config ROCKCHIP_RK3188 select SUPPORT_SPL select SPL select SPL_CLK - select SPL_PINCTRL select SPL_REGMAP select SPL_SYSCON select SPL_RAM -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/9] rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA to make FDT be built in. Signed-off-by: David Wu --- Changes in v2: None configs/evb-rk3399_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index f173c10a6b..27cf8304be 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.
Signed-off-by: David Wu
---
Changes in v2: None
arch/arm/mach-rockchip/rk3188-board-spl.c | 41 ++-
1 file changed, 2 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 3c6c3d3c09..a5e4d39cb7 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -120,7 +120,7 @@ void board_debug_uart_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
#define EARLY_UART
@@ -134,10 +134,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
#endif
#ifdef CONFIG_ROCKCHIP_USB_UART
@@ -171,12 +168,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
ret = uclass_get_device(UCLASS_RAM, 0, );
if (ret) {
debug("DRAM init failed: %d\n", ret);
@@ -214,7 +205,6 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
@@ -223,36 +213,9 @@ void spl_board_init(void)
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
--
2.19.1
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[U-Boot] [PATCH v2 0/9] Add common pinctrl driver support for rockchip
The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config. If use it, the default pinctrl setup from DTS could be configured at device probe. Changes in v2: - Remove px30, rk2928, rk3066*. - Split it to multiple files for the relevant per-SoC data structures. David Wu (9): rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 ARM: rockchip: Remove the pinctrl request at rk3288-board-spl rk3288: chrome: defconfig: Enable FDT for new pinctrl driver pinctrl: rockchip: Add common rockchip pinctrl driver rockchip: defconfig: Clean the unused pinctrl config pinctrl: rockchip: Clean the unused rockchip pinctrl drivers ARM: dts: rk322x: Correct the uart2 default pin configuration arch/arm/dts/rk322x.dtsi | 11 +- arch/arm/mach-rockchip/Kconfig| 1 - arch/arm/mach-rockchip/rk3188-board-spl.c | 41 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 79 -- configs/chromebit_mickey_defconfig| 4 - configs/chromebook_jerry_defconfig| 4 - configs/chromebook_minnie_defconfig | 4 - configs/evb-px5_defconfig | 1 - configs/evb-rk3128_defconfig | 1 - configs/evb-rk3229_defconfig | 1 - configs/evb-rk3288_defconfig | 2 - configs/evb-rk3399_defconfig | 2 - configs/evb-rv1108_defconfig | 1 - configs/fennec-rk3288_defconfig | 2 - configs/firefly-rk3288_defconfig | 2 - configs/firefly-rk3399_defconfig | 1 - configs/geekbox_defconfig | 1 - configs/kylin-rk3036_defconfig| 1 - configs/lion-rk3368_defconfig | 1 - configs/miqi-rk3288_defconfig | 2 - configs/phycore-rk3288_defconfig | 2 - configs/popmetal-rk3288_defconfig | 2 - configs/puma-rk3399_defconfig | 1 - configs/rock2_defconfig | 2 - configs/rock_defconfig| 1 - configs/sandbox_defconfig | 2 - configs/sandbox_flattree_defconfig| 2 - configs/sandbox_noblk_defconfig | 2 - configs/sheep-rk3368_defconfig| 1 - configs/tinker-rk3288_defconfig | 2 - configs/vyasa-rk3288_defconfig| 2 - drivers/pinctrl/Kconfig | 91 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/rockchip/Kconfig | 17 + drivers/pinctrl/rockchip/Makefile | 19 +- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 65 ++ drivers/pinctrl/rockchip/pinctrl-rk3128.c | 155 +++ drivers/pinctrl/rockchip/pinctrl-rk3188.c | 82 ++ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 215 drivers/pinctrl/rockchip/pinctrl-rk3288.c | 157 +++ drivers/pinctrl/rockchip/pinctrl-rk3328.c | 227 drivers/pinctrl/rockchip/pinctrl-rk3368.c | 116 ++ drivers/pinctrl/rockchip/pinctrl-rk3399.c | 193 .../pinctrl/rockchip/pinctrl-rockchip-core.c | 788 ++ drivers/pinctrl/rockchip/pinctrl-rockchip.h | 302 ++ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 203 drivers/pinctrl/rockchip/pinctrl_rk3036.c | 671 drivers/pinctrl/rockchip/pinctrl_rk3128.c | 186 drivers/pinctrl/rockchip/pinctrl_rk3188.c | 989 -- drivers/pinctrl/rockchip/pinctrl_rk322x.c | 894 drivers/pinctrl/rockchip/pinctrl_rk3288.c | 869 --- drivers/pinctrl/rockchip/pinctrl_rk3328.c | 705 - drivers/pinctrl/rockchip/pinctrl_rk3368.c | 739 - drivers/pinctrl/rockchip/pinctrl_rk3399.c | 503 - drivers/pinctrl/rockchip/pinctrl_rv1108.c | 580 -- 55 files changed, 2543 insertions(+), 6406 deletions(-) create mode 100644 drivers/pinctrl/rockchip/Kconfig create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3128.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3188.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk322x.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3288.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3328.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3368.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3399.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip-core.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip.h create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1108.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c delete mode 100644 drivers/pinctrl
Re: [U-Boot] [PATCH v3 5/8] rockchip: rk3399: Add improved pinctrl driver.
Hi Philipp, 在 2018/12/27 下午10:31, Philipp Tomsich 写道: David, On 27.12.2018, at 13:49, David Wu wrote: Hi Christoph, I once submitted a series of patches that they can support all Socs' Pinctrl and how do you feel about using them. http://patchwork.ozlabs.org/patch/868849/ Which reminds me that I am still waiting for a newer revision that addresses the various comments (e.g. breaking up into a driver and mini-drivers/driver-data, not including support for yet-unsupported SoCs, etc.)... Are you planning to do an updatted and rebased version in the near future? Yes, i will pick them up, and update. Thanks, Philipp. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 5/8] rockchip: rk3399: Add improved pinctrl driver.
Hi Christoph,
This patch seems is less of code about drive strength, for some modules,
like LCD, Ethernet is still needed.
在 2018/12/27 下午9:13, Christoph Müllner 写道:
Hi David,
On 12/27/18 1:49 PM, David Wu wrote:
Hi Christoph,
I once submitted a series of patches that they can support all Socs'
Pinctrl and how do you feel about using them.
Thank's for pointing to that.
Your driver looks good, but I don't like the huge amount
of duplication in it (you have a function rk_calc_pull_reg_and_bit()
for each SoC variant, which more or less do all the same).
Also I prefer to have a generic core driver and SoC specific parts
in their own C files (to have a slim driver for each SoC, but a maximum
of code reuse). Also Kconfig entries like PINCTRL_ROCKCHIP_RK3188 don't
seem to do anything in your driver.
Since this is from Feb 2018:
May I ask, why you did not continue to bring that mainline?
It seems i have lost them in my mailbox. I'm going to update a new
version in the near future.
My plan is to get the driver in for RK3399 asap and enable it only for
the RK3399-Q7 board for now (to not mess with other boards).
During the next merge window I want to move the generic parts into their
own C files. Other SoC-specific drivers can follow then with their own
mini-drivers (no code just configuration).
Thanks,
Christoph
http://patchwork.ozlabs.org/patch/868849/
在 2018/12/27 上午9:11, Kever Yang 写道:
Add David to review the pinctrl driver.
Thanks,
- Kever
On 12/17/2018 09:30 PM, Christoph Muellner wrote:
The current pinctrl driver for the RK3399 has a range of qulity issues.
E.g. it only implements the .set_state_simple() callback, it
does not parse the available pinctrl information from the DTS
(instead uses hardcoded values), is not flexible enough to cover
devices without 'interrupt' field in the DTS (e.g. PWM),
is not written generic enough to make code reusable among other
rockchip SoCs...
This patch addresses these issues by reimplementing the whole driver
from scratch using the .set_state() callback.
The new implementation covers all featurese of the old code
(i.e. it supports pinmuxing and pullup/pulldown configuration).
This patch has been tested on a RK3399-Q7 SoM (Puma).
Signed-off-by: Christoph Muellner
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 226
++
1 file changed, 226 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index bc92dd7c06..ed9828989f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) 2018 Theobroma Systems Design und Consulting GmbH
*/
#include
@@ -14,11 +15,234 @@
#include
#include
+static const u32 RK_GRF_P_PULLUP = 1;
+static const u32 RK_GRF_P_PULLDOWN = 2;
+
struct rk3399_pinctrl_priv {
struct rk3399_grf_regs *grf;
struct rk3399_pmugrf_regs *pmugrf;
+ struct rockchip_pin_bank *banks;
+};
+
+/**
+ * Location of pinctrl/pinconf registers.
+ */
+enum rk_grf_location {
+ RK_GRF,
+ RK_PMUGRF,
+};
+
+/**
+ * @nr_pins: number of pins in this bank
+ * @bank_num: number of the bank, to account for holes
+ * @iomux: array describing the 4 iomux sources of the bank
+ */
+struct rockchip_pin_bank {
+ u8 nr_pins;
+ enum rk_grf_location grf_location;
+ size_t iomux_offset;
+ size_t pupd_offset;
};
+#define PIN_BANK(pins, grf, iomux, pupd) \
+ { \
+ .nr_pins = pins, \
+ .grf_location = grf, \
+ .iomux_offset = iomux, \
+ .pupd_offset = pupd, \
+ }
+
+static struct rockchip_pin_bank rk3399_pin_banks[] = {
+ PIN_BANK(16, RK_PMUGRF,
+ offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
+ offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
+ PIN_BANK(32, RK_PMUGRF,
+ offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
+ offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
+ PIN_BANK(32, RK_GRF,
+ offsetof(struct rk3399_grf_regs, gpio2a_iomux),
+ offsetof(struct rk3399_grf_regs, gpio2_p)),
+ PIN_BANK(32, RK_GRF,
+ offsetof(struct rk3399_grf_regs, gpio3a_iomux),
+ offsetof(struct rk3399_grf_regs, gpio3_p)),
+ PIN_BANK(32, RK_GRF,
+ offsetof(struct rk3399_grf_regs, gpio4a_iomux),
+ offsetof(struct rk3399_grf_regs, gpio4_p)),
+};
+
+static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t
*addr,
+ u32 *shift, u32 *mask)
+{
+ /*
+ * In general we four subsequent 32-bit configuration registers
+ * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
+ * The configuration for each pin has two bits.
+ *
+ * @base...contains the address to the first register
Re: [U-Boot] [PATCH v3 5/8] rockchip: rk3399: Add improved pinctrl driver.
Hi Christoph,
I once submitted a series of patches that they can support all Socs'
Pinctrl and how do you feel about using them.
http://patchwork.ozlabs.org/patch/868849/
在 2018/12/27 上午9:11, Kever Yang 写道:
Add David to review the pinctrl driver.
Thanks,
- Kever
On 12/17/2018 09:30 PM, Christoph Muellner wrote:
The current pinctrl driver for the RK3399 has a range of qulity issues.
E.g. it only implements the .set_state_simple() callback, it
does not parse the available pinctrl information from the DTS
(instead uses hardcoded values), is not flexible enough to cover
devices without 'interrupt' field in the DTS (e.g. PWM),
is not written generic enough to make code reusable among other
rockchip SoCs...
This patch addresses these issues by reimplementing the whole driver
from scratch using the .set_state() callback.
The new implementation covers all featurese of the old code
(i.e. it supports pinmuxing and pullup/pulldown configuration).
This patch has been tested on a RK3399-Q7 SoM (Puma).
Signed-off-by: Christoph Muellner
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 226 ++
1 file changed, 226 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index bc92dd7c06..ed9828989f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) 2018 Theobroma Systems Design und Consulting GmbH
*/
#include
@@ -14,11 +15,234 @@
#include
#include
+static const u32 RK_GRF_P_PULLUP = 1;
+static const u32 RK_GRF_P_PULLDOWN = 2;
+
struct rk3399_pinctrl_priv {
struct rk3399_grf_regs *grf;
struct rk3399_pmugrf_regs *pmugrf;
+ struct rockchip_pin_bank *banks;
+};
+
+/**
+ * Location of pinctrl/pinconf registers.
+ */
+enum rk_grf_location {
+ RK_GRF,
+ RK_PMUGRF,
+};
+
+/**
+ * @nr_pins: number of pins in this bank
+ * @bank_num: number of the bank, to account for holes
+ * @iomux: array describing the 4 iomux sources of the bank
+ */
+struct rockchip_pin_bank {
+ u8 nr_pins;
+ enum rk_grf_location grf_location;
+ size_t iomux_offset;
+ size_t pupd_offset;
};
+#define PIN_BANK(pins, grf, iomux, pupd) \
+ { \
+ .nr_pins = pins,\
+ .grf_location = grf,\
+ .iomux_offset = iomux, \
+ .pupd_offset = pupd,\
+ }
+
+static struct rockchip_pin_bank rk3399_pin_banks[] = {
+ PIN_BANK(16, RK_PMUGRF,
+offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
+offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
+ PIN_BANK(32, RK_PMUGRF,
+offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
+offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
+ PIN_BANK(32, RK_GRF,
+offsetof(struct rk3399_grf_regs, gpio2a_iomux),
+offsetof(struct rk3399_grf_regs, gpio2_p)),
+ PIN_BANK(32, RK_GRF,
+offsetof(struct rk3399_grf_regs, gpio3a_iomux),
+offsetof(struct rk3399_grf_regs, gpio3_p)),
+ PIN_BANK(32, RK_GRF,
+offsetof(struct rk3399_grf_regs, gpio4a_iomux),
+offsetof(struct rk3399_grf_regs, gpio4_p)),
+};
+
+static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr,
+ u32 *shift, u32 *mask)
+{
+ /*
+* In general we four subsequent 32-bit configuration registers
+* per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
+* The configuration for each pin has two bits.
+*
+* @base...contains the address to the first register.
+* @index...defines the pin within the bank (0..31).
+* @addr...will be the address of the actual register to use
+*/
+
+ const u32 pins_per_register = 8;
+ const u32 config_bits_per_pin = 2;
+
+ /* Get the address of the configuration register. */
+ *addr = base + (index / pins_per_register) * sizeof(u32);
+
+ /* Get the bit offset within the configruation register. */
+ *shift = (index & (pins_per_register - 1)) * config_bits_per_pin;
+
+ /* Get the (unshifted) mask for the configuration pins. */
+ *mask = ((1 << config_bits_per_pin) - 1);
+
+ pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n",
+__func__, *addr, *mask, *shift);
+}
+
+static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr,
+struct rockchip_pin_bank *bank,
+u32 index, u32 muxval)
+{
+ uintptr_t iomux_base, addr;
+ u32 shift, mask;
+
+
Re: [U-Boot] [U-Boot, 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
Hi Philipp, Okay, each SOC should have its own file, which include private data structure, and probe(). Can reduce driver size. 在 2018年02月19日 03:20, Philipp Tomsich 写道: On Sat, 3 Feb 2018, David Wu wrote: Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Please split this into multiple comments (and possibly multiple files) for the relevant per-SoC data structures. I'd like this to be multiple commits to add the individual data structures for each of the SOCs. We had the fundamental discussion of how to deal with drivers that require additional config-structures and code for some SOCs in the HDMI/VOP context and we should follow the same here. Signed-off-by: David Wu <david...@rock-chips.com> Reviewed-by: Kever Yang <kever.y...@rock-chips.com> Tested-by: Kever Yang <kever.y...@rock-chips.com> Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> --- drivers/pinctrl/Kconfig | 98 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/pinctrl-rockchip.c | 2440 3 files changed, 2454 insertions(+), 86 deletions(-) create mode 100644 drivers/pinctrl/pinctrl-rockchip.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7e8e4b0..6177e7c 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -158,95 +158,23 @@ config PINCTRL_QCA953X the GPIO definitions and pin control functions for each available multiplex function. -config PINCTRL_ROCKCHIP_RK3036 - bool "Rockchip rk3036 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3036 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3128 - bool "Rockchip rk3128 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3128 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3188 - bool "Rockchip rk3188 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3188 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK322X - bool "Rockchip rk322x pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk322x SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3288 - bool "Rockchip rk3288 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3288 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3328 - bool "Rockchip rk3328 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3328 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3368 - bool "Rockchip RK3368 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3368 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3399 - bool "Rockchip rk3399 pin control driver" - depends on DM +config PINCTRL_ROCKCHIP + bool "Rockchip pin control driver" + depends on PINCTRL_FULL + default y help - Support pin multiplexing control on Rockchip rk3399 SoCs. + Support pin multiplexing control on Rockchip SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. + The driver is controlled by a device tree node which contains pin + control functions for each available multiplex function. -config PINCTRL_ROCKCHIP_RV1108 - bool "Rockchip rv1108 pin control driver" - depends on DM +config SPL_PINCTRL_ROCKCHIP + bool "Support Rockchip pin controllers in SPL" + depends on SPL_PINCTRL_FULL + default y
Re: [U-Boot] [U-Boot, 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
Hi Philipp,
在 2018年02月19日 03:00, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug
message.
If the MMC always set up correctly for all configurations (e.g. bus-width)
or should some of the setup be duplicated there to ensure that we catch
all corner cases?
For this, I will do a check if we need to setup duplicated.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
arch/arm/mach-rockchip/rk3188-board-spl.c | 42
+++
1 file changed, 3 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 8e3b8ae..8371a31 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -100,10 +100,11 @@ static int setup_arm_clock(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
/* Example code showing how to enable the debug UART on RK3188 */
+#define EARLY_UART
#ifdef EARLY_UART
#include
/* Enable early UART on the RK3188 */
@@ -124,10 +125,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
#endif
ret = spl_early_init();
@@ -144,12 +142,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
ret = uclass_get_device(UCLASS_RAM, 0, );
if (ret) {
debug("DRAM init failed: %d\n", ret);
@@ -187,7 +179,6 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
@@ -196,36 +187,9 @@ void spl_board_init(void)
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
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Re: [U-Boot] [U-Boot, 10/14] ARM: dts: rockchip: Enable integrated phy support for rk3229-evb
Hi Philipp,
在 2018年02月19日 03:38, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
In fact, the evb-rk3229 is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
arch/arm/dts/rk3229-evb.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index ae0b0a4..547c7a2 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -63,7 +63,29 @@
snps,reset-delays-us = <0 1 100>;
tx_delay = <0x30>;
rx_delay = <0x10>;
+ status = "disabled";
+};
+
+ {
+ assigned-clocks = < SCLK_MAC_SRC>;
+ assigned-clock-rates = <5000>;
+ clock_in_out = "output";
+ phy-supply = <_phy>;
+ phy-mode = "rmii";
+ phy-handle = <>;
status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@0 {
+ compatible = "ethernet-phy-id1234.d400",
"ethernet-phy-ieee802.3-c22";
Where is "ethernet-phy-id1234.d400" defined/used? I don't see anything
in Linux or U-Boot.
Yes, The "ethernet-phy-id1234.d400" is not defined at linux/U-Boot.
It does use the "ethernet-phy-ieee802.3-c22". The
"ethernet-phy-id1234.d400" is a decorated aliases, the 0x1234d0 is the
phy-id.
+ reg = <0>;
+ phy-is-integrated;
Documentation in the documentation for DTS bindings?
Shouldn't this be rockchip,phy-is-integrated?
What is the status of this on the Linux side?
I think it's consistent with kernel, especially if we might use kernel
DTB file.
+ };
+ };
};
{
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Re: [U-Boot] [U-Boot, 01/14] net: rockchip: Separate rmii and rgmii speed setup
Hi Philipp,
在 2018年02月19日 03:36, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
Some Socs both have rgmii and rmii interface, so we need to
separate their speed setting.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
drivers/net/gmac_rockchip.c | 62
+++--
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 683e820..4396ca1 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -40,7 +40,10 @@ struct gmac_rockchip_platdata {
};
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv);
+ int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv);
Why can't this be a single fix_mac_speed function that does the right
thing both for RMII and RGMII depending on the platdata?
I think this part is similar to the kernel code, and it's better to
maintain.
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -70,7 +73,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct
udevice *dev)
return designware_eth_ofdata_to_platdata(dev);
}
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk322x_grf *grf;
int clk;
@@ -103,7 +107,8 @@ static int rk3228_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk3288_grf *grf;
int clk;
@@ -129,7 +134,8 @@ static int rk3288_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk3328_grf_regs *grf;
int clk;
@@ -162,7 +168,8 @@ static int rk3328_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk3368_grf *grf;
int clk;
@@ -194,7 +201,8 @@ static int rk3368_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk3399_grf_regs *grf;
int clk;
@@ -220,7 +228,8 @@ static int rk3399_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rv1108_grf *grf;
int clk, speed;
@@ -489,7 +498,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
break;
default:
- debug("NO interface defined!\n");
+ debug("%s: NO interface defined!\n", __func__);
return -ENXIO;
}
@@ -498,18 +507,33 @@ static int gmac_rockchip_probe(struct udevice *dev)
static int gmac_rockchip_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = dev_get_platdata(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
+ struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
int ret;
- ret = designware_eth_init(priv, pdata->enetaddr);
- if (ret)
- return ret;
- ret = ops->fix_mac_speed(priv);
+ ret = designware_eth_init(priv, eth_pdata->enetaddr);
if (ret)
return ret;
+
+ switch (eth_pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ret = ops->fix_rgmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ ret = ops->fix_rmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
Looking at this, the fix_mac_speed()-function could look into pdata to
determine what needs to be done... no need to complicate the common code
path with this.
+ default:
+ debug("%s: NO interface defined!\n", __func__);
+ return -ENXIO;
+ }
+
ret = designware_eth_enable(priv);
if (ret)
[U-Boot] [PATCH 13/14] ARM: dts: rockchip: Enable gmac2phy feature for rk3328-evb
In fact, the rk3328-evb is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3328-evb.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 336c2d5..1e09f7d 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -101,6 +101,16 @@
pinctrl-0 = <_pins>;
tx_delay = <0x26>;
rx_delay = <0x11>;
+ status = "disabled";
+};
+
+ {
+ phy-supply = <_phy>;
+ clock_in_out = "output";
+ assigned-clocks = < SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <5000>;
+ assigned-clocks = < SCLK_MAC2PHY>;
+ assigned-clock-parents = < SCLK_MAC2PHY_SRC>;
status = "okay";
};
--
2.7.4
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[U-Boot] [PATCH 14/14] rockchip: defconfig: Enable CONFIG_RESET_ROCKCHIP for rk3329-evb and rk3328-evb
The integtated phy inside the rk3229 and rk3328 need the reset request for power up. Signed-off-by: David Wu <david...@rock-chips.com> --- configs/evb-rk3229_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 39469b4..311019d 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -40,6 +40,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_BASE=0x1103 CONFIG_DEBUG_UART_CLOCK=2400 diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 3d8c04d..12497fa 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -38,6 +38,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_BASE=0xFF13 CONFIG_DEBUG_UART_CLOCK=2400 -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 11/14] clk: rk3328: Implement the gmac2phy clock assignment
Implement the setting parent and rate for gmac2phy clock, and
add internal pll div set for gmac2phy clk.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3328.c | 86 +++
1 file changed, 86 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index 3f8cdc0..c576262 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -95,6 +95,14 @@ enum {
PCLK_DBG_DIV_SHIFT = 0,
PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
+ /* CLKSEL_CON26 */
+ GMAC2PHY_PLL_SEL_SHIFT = 7,
+ GMAC2PHY_PLL_SEL_MASK = 1 << GMAC2PHY_PLL_SEL_SHIFT,
+ GMAC2PHY_PLL_SEL_CPLL = 0,
+ GMAC2PHY_PLL_SEL_GPLL = 1,
+ GMAC2PHY_CLK_DIV_MASK = 0x1f,
+ GMAC2PHY_CLK_DIV_SHIFT = 0,
+
/* CLKSEL_CON27 */
GMAC2IO_PLL_SEL_SHIFT = 7,
GMAC2IO_PLL_SEL_MASK= 1 << GMAC2IO_PLL_SEL_SHIFT,
@@ -440,6 +448,39 @@ static ulong rk3328_gmac2io_set_clk(struct rk3328_cru
*cru, ulong rate)
return ret;
}
+static ulong rk3328_gmac2phy_src_set_clk(struct rk3328_cru *cru, ulong rate)
+{
+ u32 con = readl(>clksel_con[26]);
+ ulong pll_rate;
+ u8 div;
+
+ if ((con >> GMAC2PHY_PLL_SEL_SHIFT) & GMAC2PHY_PLL_SEL_GPLL)
+ pll_rate = GPLL_HZ;
+ else
+ pll_rate = CPLL_HZ;
+
+ div = DIV_ROUND_UP(pll_rate, rate) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(>clksel_con[26], GMAC2PHY_CLK_DIV_MASK,
+div << GMAC2PHY_CLK_DIV_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+}
+
+static ulong rk3328_gmac2phy_set_clk(struct rk3328_cru *cru, ulong rate)
+{
+ struct rk3328_grf_regs *grf;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (readl(>mac_con[2]) & BIT(10))
+ /* An external clock will always generate the right rate... */
+ return rate;
+ else
+ return rk3328_gmac2phy_src_set_clk(cru, rate);
+}
+
static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
{
u32 div, con, con_id;
@@ -608,6 +649,12 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong
rate)
case SCLK_MAC2IO:
ret = rk3328_gmac2io_set_clk(priv->cru, rate);
break;
+ case SCLK_MAC2PHY:
+ ret = rk3328_gmac2phy_set_clk(priv->cru, rate);
+ break;
+ case SCLK_MAC2PHY_SRC:
+ ret = rk3328_gmac2phy_src_set_clk(priv->cru, rate);
+ break;
case SCLK_PWM:
ret = rk3328_pwm_set_clk(priv->cru, rate);
break;
@@ -728,6 +775,43 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk,
struct clk *parent)
return -EINVAL;
}
+static int rk3328_gmac2phy_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3328_grf_regs *grf;
+ const char *clock_output_name;
+ int ret;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+* If the requested parent is in the same clock-controller and the id
+* is SCLK_MAC2PHY_SRC ("clk_mac2phy_src"), switch to the internal
clock.
+*/
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2PHY_SRC)) {
+ debug("%s: switching MAC CLK to SCLK_MAC2IO_PHY\n", __func__);
+ rk_clrreg(>mac_con[2], BIT(10));
+ return 0;
+ }
+
+ /*
+* Otherwise, we need to check the clock-output-names of the
+* requested parent to see if the requested id is "phy_50m_out".
+*/
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, _output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "phy_50m_out", switch to the external clock input */
+ if (!strcmp(clock_output_name, "phy_50m_out")) {
+ debug("%s: switching MAC CLK to PHY_50M_OUT\n", __func__);
+ rk_setreg(>mac_con[2], BIT(10));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
{
switch (clk->id) {
@@ -735,6 +819,8 @@ static int rk3328_clk_set_parent(struct clk *clk, struct
clk *parent)
return rk3328_gmac2io_set_parent(clk, parent);
case SCLK_MAC2IO_EXT:
return rk3328_gmac2io_ext_set_parent(clk, parent);
+ case SCLK_MAC2PHY:
+ return rk3328_gmac2phy_set_parent(clk, paren
[U-Boot] [PATCH 10/14] ARM: dts: rockchip: Enable integrated phy support for rk3229-evb
In fact, the evb-rk3229 is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3229-evb.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index ae0b0a4..547c7a2 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -63,7 +63,29 @@
snps,reset-delays-us = <0 1 100>;
tx_delay = <0x30>;
rx_delay = <0x10>;
+ status = "disabled";
+};
+
+ {
+ assigned-clocks = < SCLK_MAC_SRC>;
+ assigned-clock-rates = <5000>;
+ clock_in_out = "output";
+ phy-supply = <_phy>;
+ phy-mode = "rmii";
+ phy-handle = <>;
status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@0 {
+ compatible = "ethernet-phy-id1234.d400",
"ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ phy-is-integrated;
+ };
+ };
};
{
--
2.7.4
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[U-Boot] [PATCH 12/14] ARM: dts: rockchip: Add gmac2phy dts node for rk3328
The gmac2phy is connected with integrated with phy, we can
fix the phy node at dtsi level.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3328.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 5de1059..7026601 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -475,6 +475,41 @@
status = "disabled";
};
+ gmac2phy: ethernet@ff55 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff55 0x0 0x1>;
+ rockchip,grf = <>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ clocks = < SCLK_MAC2PHY_SRC>, < SCLK_MAC2PHY_RXTX>,
+< SCLK_MAC2PHY_RXTX>, < SCLK_MAC2PHY_REF>,
+< ACLK_MAC2PHY>, < PCLK_MAC2PHY>,
+< SCLK_MAC2PHY_OUT>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "aclk_mac", "pclk_mac",
+ "clk_macphy";
+ resets = < SRST_GMAC2PHY_A>, < SRST_MACPHY>;
+ reset-names = "stmmaceth", "mac-phy";
+ phy-mode = "rmii";
+ phy-handle = <>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_rxm1 _linkm1>;
+ status = "disabled";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@0 {
+ compatible = "ethernet-phy-id1234.d400",
"ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ phy-is-integrated;
+ };
+ };
+ };
+
usb_host0_ehci: usb@ff5c {
compatible = "generic-ehci";
reg = <0x0 0xff5c 0x0 0x1>;
--
2.7.4
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[U-Boot] [PATCH 09/14] ARM: dts: rockchip: Add integrated phy reset and clock for rk322x
To support the integrated phy for rk322x, add their reset and clock property at dtsi level. Signed-off-by: David Wu <david...@rock-chips.com> --- arch/arm/dts/rk322x.dtsi | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 22324f9..b0254a3 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -449,13 +449,13 @@ clocks = < SCLK_MAC>, < SCLK_MAC_RX>, < SCLK_MAC_TX>, < SCLK_MAC_REF>, < SCLK_MAC_REFOUT>, < ACLK_GMAC>, - < PCLK_GMAC>; + < PCLK_GMAC>, < SCLK_MAC_PHY>; clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = < SRST_GMAC>; - reset-names = "stmmaceth"; + "pclk_mac", "clk_macphy"; + resets = < SRST_GMAC>, < SRST_MACPHY>; + reset-names = "stmmaceth", "mac-phy"; rockchip,grf = <>; status = "disabled"; }; -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 07/14] clk: rockchip: Init CPLL 600M for rk322x
The gmac for integrated phy need 50M clock, it seems that only
come from CPLL 600M, the GPLL is not suitable.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 +
drivers/clk/rockchip/clk_rk322x.c | 11 +++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
index a7999ca..801363d 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
@@ -13,6 +13,7 @@
#define APLL_HZ(600 * MHz)
#define GPLL_HZ(594 * MHz)
+#define CPLL_HZ(600 * MHz)
#define CORE_PERI_HZ 15000
#define CORE_ACLK_HZ 3
diff --git a/drivers/clk/rockchip/clk_rk322x.c
b/drivers/clk/rockchip/clk_rk322x.c
index 72c8757..4022065 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -40,6 +40,7 @@ enum {
/* use integer mode*/
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
@@ -89,11 +90,13 @@ static void rkclk_init(struct rk322x_cru *cru)
rk_clrsetreg(>cru_mode_con,
GPLL_MODE_MASK | APLL_MODE_MASK,
GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
-APLL_MODE_SLOW << APLL_MODE_SHIFT);
+APLL_MODE_SLOW << APLL_MODE_SHIFT |
+CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
/* init pll */
rkclk_set_pll(cru, CLK_ARM, _init_cfg);
rkclk_set_pll(cru, CLK_GENERAL, _init_cfg);
+ rkclk_set_pll(cru, CLK_CODEC, _init_cfg);
/*
* select apll as cpu/core clock pll source and
@@ -166,7 +169,8 @@ static void rkclk_init(struct rk322x_cru *cru)
rk_clrsetreg(>cru_mode_con,
GPLL_MODE_MASK | APLL_MODE_MASK,
GPLL_MODE_NORM << GPLL_MODE_SHIFT |
-APLL_MODE_NORM << APLL_MODE_SHIFT);
+APLL_MODE_NORM << APLL_MODE_SHIFT |
+CPLL_MODE_NORM << CPLL_MODE_SHIFT);
}
/* Get pll rate by id */
@@ -258,8 +262,7 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru,
uint freq)
if (con & MAC_PLL_SEL_MASK)
pll_rate = GPLL_HZ;
else
- /* CPLL is not set */
- return -EPERM;
+ pll_rate = CPLL_HZ;
div = DIV_ROUND_UP(pll_rate, freq) - 1;
if (div <= 0x1f)
--
2.7.4
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[U-Boot] [PATCH 08/14] clk: rockchip: Add SCLK_MAC_SRC clock rate setup
The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested by the integrated phy usuage. Signed-off-by: David Wu <david...@rock-chips.com> --- drivers/clk/rockchip/clk_rk322x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4022065..7276c4a 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -390,6 +390,7 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) case CLK_DDR: new_rate = rk322x_ddr_set_clk(priv->cru, rate); break; + case SCLK_MAC_SRC: case SCLK_MAC: new_rate = rk322x_mac_set_clk(priv->cru, rate); break; -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/14] clk: rockchip: fix the gmac selection of pll source for rk322x
There is a wrong selection for gmac pll source, fix it. Signed-off-by: David Wu <david...@rock-chips.com> --- drivers/clk/rockchip/clk_rk322x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4bbcaf8..72c8757 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -255,7 +255,7 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) ulong pll_rate; u8 div; - if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK) + if (con & MAC_PLL_SEL_MASK) pll_rate = GPLL_HZ; else /* CPLL is not set */ -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/14] cllk: rockchip: Change the defined name for CONFIG_RESET_ROCKCHIP
It seems that the "CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)" always
should not been active.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3036.c | 2 +-
drivers/clk/rockchip/clk_rk322x.c | 4 ++--
drivers/clk/rockchip/clk_rk3288.c | 2 +-
drivers/clk/rockchip/clk_rk3328.c | 4 ++--
drivers/clk/rockchip/clk_rk3368.c | 2 +-
drivers/clk/rockchip/clk_rk3399.c | 2 +-
drivers/clk/rockchip/clk_rv1108.c | 2 +-
7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3036.c
b/drivers/clk/rockchip/clk_rk3036.c
index 510a00a..3c74189 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -347,7 +347,7 @@ static int rk3036_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 9);
if (ret)
diff --git a/drivers/clk/rockchip/clk_rk322x.c
b/drivers/clk/rockchip/clk_rk322x.c
index 4e6d2f0..4bbcaf8 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -509,9 +509,9 @@ static int rk322x_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
- ret = rockchip_reset_bind(dev, ret, 9);
+ ret = rockchip_reset_bind(dev, ret, 63);
if (ret)
debug("Warning: software reset driver bind faile\n");
#endif
diff --git a/drivers/clk/rockchip/clk_rk3288.c
b/drivers/clk/rockchip/clk_rk3288.c
index 552a71a..0c6b14b 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -968,7 +968,7 @@ static int rk3288_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 12);
if (ret)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index 2ccc798..3f8cdc0 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -792,9 +792,9 @@ static int rk3328_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
ret = offsetof(struct rk3328_cru, softrst_con[0]);
- ret = rockchip_reset_bind(dev, ret, 12);
+ ret = rockchip_reset_bind(dev, ret, 100);
if (ret)
debug("Warning: software reset driver bind faile\n");
#endif
diff --git a/drivers/clk/rockchip/clk_rk3368.c
b/drivers/clk/rockchip/clk_rk3368.c
index 3ac9add..bde3635 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -622,7 +622,7 @@ static int rk3368_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
ret = offsetof(struct rk3368_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 15);
if (ret)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index 42926ba..a0fc329 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1320,7 +1320,7 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct
udevice *dev)
static int rk3399_pmuclk_bind(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
int ret;
ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
diff --git a/drivers/clk/rockchip/clk_rv1108.c
b/drivers/clk/rockchip/clk_rv1108.c
index 224c813..a2a1223 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -240,7 +240,7 @@ static int rv1108_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
ret = offsetof(struct rk3368_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 13);
if (ret)
--
2.7.4
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[U-Boot] [PATCH 04/14] net: rockchip: Add integrated phy for rk3228 and rk3328
The rk3228 and rk3328 Socs both support integrated phy, implement
their power up function to support it.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 122
1 file changed, 122 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index bca0a2a..ec47933 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -583,6 +583,126 @@ static void rv1108_gmac_set_to_rmii(struct
gmac_rockchip_platdata *pdata)
RV1108_GMAC_PHY_INTF_SEL_RMII);
}
+static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata
*pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15),
+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15),
+ };
+ enum {
+ RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14),
+ RK3228_MACPHY_CFG_CLK_50M = BIT(14),
+
+ RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6),
+ RK3228_MACPHY_RMII_MODE = BIT(6),
+
+ RK3228_MACPHY_ENABLE_MASK = BIT(0),
+ RK3228_MACPHY_DISENABLE = 0,
+ RK3228_MACPHY_ENABLE = BIT(0),
+ };
+ enum {
+ RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0),
+ RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234,
+ };
+ enum {
+ RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0),
+ RK3228_RK_GRF_CON3_MACPHY_ID = 0x35,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>con_iomux,
+RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK,
+RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
+
+ rk_clrsetreg(>macphy_con[2],
+RK3228_RK_GRF_CON2_MACPHY_ID_MASK,
+RK3228_RK_GRF_CON2_MACPHY_ID);
+
+ rk_clrsetreg(>macphy_con[3],
+RK3228_RK_GRF_CON3_MACPHY_ID_MASK,
+RK3228_RK_GRF_CON3_MACPHY_ID);
+
+ /* disabled before trying to reset it &*/
+ rk_clrsetreg(>macphy_con[0],
+RK3228_MACPHY_CFG_CLK_50M_MASK |
+RK3228_MACPHY_RMII_MODE_MASK |
+RK3228_MACPHY_ENABLE_MASK,
+RK3228_MACPHY_CFG_CLK_50M |
+RK3228_MACPHY_RMII_MODE |
+RK3228_MACPHY_DISENABLE);
+
+ reset_assert(>phy_reset);
+ udelay(10);
+ reset_deassert(>phy_reset);
+ udelay(10);
+
+ rk_clrsetreg(>macphy_con[0],
+RK3228_MACPHY_ENABLE_MASK,
+RK3228_MACPHY_ENABLE);
+ udelay(30 * 1000);
+}
+
+static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata
*pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_GRF_CON_RMII_MODE_MASK = BIT(9),
+ RK3328_GRF_CON_RMII_MODE = BIT(9),
+ };
+ enum {
+ RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14),
+ RK3328_MACPHY_CFG_CLK_50M = BIT(14),
+
+ RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6),
+ RK3328_MACPHY_RMII_MODE = BIT(6),
+
+ RK3328_MACPHY_ENABLE_MASK = BIT(0),
+ RK3328_MACPHY_DISENABLE = 0,
+ RK3328_MACPHY_ENABLE = BIT(0),
+ };
+ enum {
+ RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0),
+ RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234,
+ };
+ enum {
+ RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0),
+ RK3328_RK_GRF_CON3_MACPHY_ID = 0x35,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>macphy_con[1],
+RK3328_GRF_CON_RMII_MODE_MASK,
+RK3328_GRF_CON_RMII_MODE);
+
+ rk_clrsetreg(>macphy_con[2],
+RK3328_RK_GRF_CON2_MACPHY_ID_MASK,
+RK3328_RK_GRF_CON2_MACPHY_ID);
+
+ rk_clrsetreg(>macphy_con[3],
+RK3328_RK_GRF_CON3_MACPHY_ID_MASK,
+RK3328_RK_GRF_CON3_MACPHY_ID);
+
+ /* disabled before trying to reset it &*/
+ rk_clrsetreg(>macphy_con[0],
+RK3328_MACPHY_CFG_CLK_50M_MASK |
+RK3328_MACPHY_RMII_MODE_MASK |
+RK3328_MACPHY_ENABLE_MASK,
+RK3328_MACPHY_CFG_CLK_50M |
+RK3328_MACPHY_RMII_MODE |
+RK3328_MACPHY_DISENABLE);
+
+ reset_assert(>phy_reset);
+ udelay(10);
+ reset_deassert(>phy_reset);
+ udelay(10);
+
+ rk_clrsetreg(>macphy_con[0],
+RK3328_MACPHY_ENABLE_MASK,
+RK3328_MACPHY_ENABLE);
+ udelay(30 * 1000);
+}
+
static int gmac_rockchip_probe(struct udevice *dev)
{
struct gmac_roc
[U-Boot] [PATCH 03/14] net: rockchip: Add integrated phy ops
Some rockchio Socs have integrated phy inside, to support it,
add the integrated phy ops.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 5afc415..bca0a2a 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -22,6 +23,7 @@
#include
#include
#include
+#include
#include
#include "designware.h"
@@ -35,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR;
struct gmac_rockchip_platdata {
struct dw_eth_pdata dw_eth_pdata;
bool clock_input;
+ bool integrated_phy;
+ struct reset_ctl phy_reset;
int tx_delay;
int rx_delay;
};
@@ -46,13 +50,16 @@ struct rk_gmac_ops {
struct dw_eth_dev *priv);
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
+ void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata);
};
static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ struct ofnode_phandle_args args;
const char *string;
+ int ret;
string = dev_read_string(dev, "clock_in_out");
if (!strcmp(string, "input"))
@@ -60,6 +67,25 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
else
pdata->clock_input = false;
+ /* If phy-handle property is passed from DT, use it as the PHY */
+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, );
+ if (ret) {
+ debug("Cannot get phy phandle: ret=%d\n", ret);
+ pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated");
+ } else {
+ debug("Found phy-handle subnode\n");
+ pdata->integrated_phy = ofnode_read_bool(args.node,
+"phy-is-integrated");
+ }
+
+ if (pdata->integrated_phy) {
+ ret = reset_get_by_name(dev, "mac-phy", >phy_reset);
+ if (ret) {
+ debug("No PHY reset control found: ret=%d\n", ret);
+ return ret;
+ }
+ }
+
/* Check the new naming-style first... */
pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
@@ -572,6 +598,9 @@ static int gmac_rockchip_probe(struct udevice *dev)
if (ret)
return ret;
+ if (pdata->integrated_phy && ops->integrated_phy_powerup)
+ ops->integrated_phy_powerup(pdata);
+
switch (eth_pdata->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
/*
--
2.7.4
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[U-Boot] [PATCH 02/14] net: rockchip: Add rmii interface and rmii speed setup for rk3228 and rk3328
The rk3228 and rk3328 Socs both have rmii interface, that might be used,
so add them for usage.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 115
1 file changed, 115 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 4396ca1..5afc415 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -73,6 +73,41 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
+{
+ struct rk322x_grf *grf;
+ int clk;
+ enum {
+ RK3228_GMAC_RMII_CLK_MASK = BIT(7),
+ RK3228_GMAC_RMII_CLK_2_5M = 0,
+ RK3228_GMAC_RMII_CLK_25M= BIT(7),
+
+ RK3228_GMAC_RMII_SPEED_MASK = BIT(2),
+ RK3228_GMAC_RMII_SPEED_10 = 0,
+ RK3228_GMAC_RMII_SPEED_100 = BIT(2),
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10;
+ break;
+ case 100:
+ clk = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>mac_con[1],
+RK3228_GMAC_RMII_CLK_MASK | RK3228_GMAC_RMII_SPEED_MASK,
+clk);
+
+ return 0;
+}
+
static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv)
{
@@ -134,6 +169,41 @@ static int rk3288_gmac_fix_rgmii_speed(struct
gmac_rockchip_platdata *pdata,
return 0;
}
+static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
+{
+ struct rk3328_grf_regs *grf;
+ int clk;
+ enum {
+ RK3328_GMAC_RMII_CLK_MASK = BIT(7),
+ RK3328_GMAC_RMII_CLK_2_5M = 0,
+ RK3328_GMAC_RMII_CLK_25M= BIT(7),
+
+ RK3328_GMAC_RMII_SPEED_MASK = BIT(2),
+ RK3328_GMAC_RMII_SPEED_10 = 0,
+ RK3328_GMAC_RMII_SPEED_100 = BIT(2),
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10;
+ break;
+ case 100:
+ clk = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(pdata->integrated_phy ? >mac_con[2] :
>mac_con[1],
+RK3328_GMAC_RMII_CLK_MASK | RK3328_GMAC_RMII_SPEED_MASK,
+clk);
+
+ return 0;
+}
+
static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv)
{
@@ -264,6 +334,28 @@ static int rv1108_gmac_fix_rmii_speed(struct
gmac_rockchip_platdata *pdata,
return 0;
}
+static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_GRF_CON_RMII_MODE_MASK = BIT(11),
+ RK3228_GRF_CON_RMII_MODE_SEL = BIT(11),
+ RK3228_RMII_MODE_MASK = BIT(10),
+ RK3228_RMII_MODE_SEL = BIT(10),
+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>mac_con[1],
+RK3228_GRF_CON_RMII_MODE_MASK |
+RK3228_RMII_MODE_MASK |
+RK3228_GMAC_PHY_INTF_SEL_MASK,
+RK3228_GRF_CON_RMII_MODE_SEL |
+RK3228_RMII_MODE_SEL |
+RK3228_GMAC_PHY_INTF_SEL_RMII);
+}
+
static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk322x_grf *grf;
@@ -328,6 +420,25 @@ static void rk3288_gmac_set_to_rgmii(struct
gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_RMII_MODE_MASK = BIT(9),
+ RK3328_RMII_MODE = BIT(9),
+
+ RK3328_GMAC_PHY_INTF_SEL_MA
[U-Boot] [PATCH 01/14] net: rockchip: Separate rmii and rgmii speed setup
Some Socs both have rgmii and rmii interface, so we need to
separate their speed setting.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 62 +++--
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 683e820..4396ca1 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -40,7 +40,10 @@ struct gmac_rockchip_platdata {
};
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv);
+ int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv);
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -70,7 +73,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
{
struct rk322x_grf *grf;
int clk;
@@ -103,7 +107,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
{
struct rk3288_grf *grf;
int clk;
@@ -129,7 +134,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
{
struct rk3328_grf_regs *grf;
int clk;
@@ -162,7 +168,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
{
struct rk3368_grf *grf;
int clk;
@@ -194,7 +201,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
{
struct rk3399_grf_regs *grf;
int clk;
@@ -220,7 +228,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
{
struct rv1108_grf *grf;
int clk, speed;
@@ -489,7 +498,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
break;
default:
- debug("NO interface defined!\n");
+ debug("%s: NO interface defined!\n", __func__);
return -ENXIO;
}
@@ -498,18 +507,33 @@ static int gmac_rockchip_probe(struct udevice *dev)
static int gmac_rockchip_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = dev_get_platdata(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
+ struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
int ret;
- ret = designware_eth_init(priv, pdata->enetaddr);
- if (ret)
- return ret;
- ret = ops->fix_mac_speed(priv);
+ ret = designware_eth_init(priv, eth_pdata->enetaddr);
if (ret)
return ret;
+
+ switch (eth_pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ret = ops->fix_rgmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ ret = ops->fix_rmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
+ default:
+ debug("%s: NO interface defined!\n", __func__);
+ return -ENXIO;
+ }
+
ret = designware_eth_enable(priv);
if (ret)
return ret;
@@ -527,32 +551,32 @@ const struct eth_ops gmac_rockchip_eth_ops = {
};
const struct
[U-Boot] [PATCH 00/14] Add integrated phy support for rk322x and rk3328
To support the integrated phy, it is necessary that the gmac need to get 50M clock rate from internal PLL, the integrated phy can't generate 50M clock itself. David Wu (14): net: rockchip: Separate rmii and rgmii speed setup net: rockchip: Add rmii interface and rmii speed setup for rk3228 and rk3328 net: rockchip: Add integrated phy ops net: rockchip: Add integrated phy for rk3228 and rk3328 cllk: rockchip: Change the defined name for CONFIG_RESET_ROCKCHIP clk: rockchip: fix the gmac selection of pll source for rk322x clk: rockchip: Init CPLL 600M for rk322x clk: rockchip: Add SCLK_MAC_SRC clock rate setup ARM: dts: rockchip: Add integrated phy reset and clock for rk322x ARM: dts: rockchip: Enable integrated phy support for rk3229-evb clk: rk3328: Implement the gmac2phy clock assignment ARM: dts: rockchip: Add gmac2phy dts node for rk3328 ARM: dts: rockchip: Enable gmac2phy feature for rk3328-evb rockchip: defconfig: Enable CONFIG_RESET_ROCKCHIP for rk3329-evb and rk3328-evb arch/arm/dts/rk3229-evb.dts | 22 ++ arch/arm/dts/rk322x.dtsi| 8 +- arch/arm/dts/rk3328-evb.dts | 10 + arch/arm/dts/rk3328.dtsi| 35 +++ arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 + configs/evb-rk3229_defconfig| 1 + configs/evb-rk3328_defconfig| 1 + drivers/clk/rockchip/clk_rk3036.c | 2 +- drivers/clk/rockchip/clk_rk322x.c | 18 +- drivers/clk/rockchip/clk_rk3288.c | 2 +- drivers/clk/rockchip/clk_rk3328.c | 90 ++- drivers/clk/rockchip/clk_rk3368.c | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- drivers/clk/rockchip/clk_rv1108.c | 2 +- drivers/net/gmac_rockchip.c | 328 ++-- 15 files changed, 487 insertions(+), 37 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk322x.dtsi | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 22324f9..023ced6 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -207,7 +207,7 @@
clocks = < SCLK_UART2>, < PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
- pinctrl-0 = <_xfer>;
+ pinctrl-0 = <_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -749,7 +749,7 @@
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <1 RK_PC2 RK_FUNC_2
_pull_none>,
+ rockchip,pins = <1 RK_PC2 RK_FUNC_2
_pull_up>,
<1 RK_PC3 RK_FUNC_2
_pull_none>;
};
@@ -761,6 +761,13 @@
rockchip,pins = <0 RK_PD0 RK_FUNC_1
_pull_none>;
};
};
+
+ uart2-1 {
+ uart21_xfer: uart21-xfer {
+ rockchip,pins = <1 10 RK_FUNC_2 _pull_up>,
+ <1 9 RK_FUNC_2 _pull_none>;
+ };
+ };
};
dmc: dmc@1120 {
--
2.7.4
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[U-Boot] [PATCH 7/9] rockchip: defconfig: Clean the unused pinctrl config
If we used the pinctrl-rockchip driver, these config is not needed, so remove them. Signed-off-by: David Wu <david...@rock-chips.com> --- configs/chromebit_mickey_defconfig | 2 -- configs/chromebook_jerry_defconfig | 2 -- configs/chromebook_minnie_defconfig | 2 -- configs/evb-px5_defconfig | 1 - configs/evb-rk3128_defconfig| 1 - configs/evb-rk3229_defconfig| 1 - configs/evb-rk3288_defconfig| 2 -- configs/evb-rk3399_defconfig| 1 - configs/evb-rv1108_defconfig| 1 - configs/fennec-rk3288_defconfig | 2 -- configs/firefly-rk3288_defconfig| 2 -- configs/firefly-rk3399_defconfig| 1 - configs/geekbox_defconfig | 1 - configs/kylin-rk3036_defconfig | 1 - configs/lion-rk3368_defconfig | 1 - configs/miqi-rk3288_defconfig | 2 -- configs/phycore-rk3288_defconfig| 2 -- configs/popmetal-rk3288_defconfig | 2 -- configs/puma-rk3399_defconfig | 1 - configs/rock2_defconfig | 2 -- configs/rock_defconfig | 1 - configs/sandbox_defconfig | 2 -- configs/sandbox_flattree_defconfig | 2 -- configs/sandbox_noblk_defconfig | 2 -- configs/sheep-rk3368_defconfig | 1 - configs/tinker-rk3288_defconfig | 2 -- configs/vyasa-rk3288_defconfig | 2 -- 27 files changed, 42 deletions(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 93c5c4e..7d51348 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -54,8 +54,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 57d35e9..76022fa 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -56,8 +56,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 529444a..c2d2422 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -55,8 +55,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 0e8594c..663d9fc 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -16,7 +16,6 @@ CONFIG_CLK=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3368=y CONFIG_RAM=y CONFIG_DEBUG_UART_BASE=0xFF1c CONFIG_DEBUG_UART_CLOCK=2400 diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index d49cea0..a767154 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -24,7 +24,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3128=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 39469b4..c203d6f 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -37,7 +37,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=150 diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 09a8844..34498fa 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -51,8 +51,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 54eb703..d026d0a 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -40,7 +40,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3399=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index a59d89e..5b80988 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -31,7 +31,6 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RV1108=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=150 # CONFIG_SPL_SERIAL_PRESENT is n
[U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Signed-off-by: David Wu <david...@rock-chips.com> --- drivers/pinctrl/Kconfig| 98 +- drivers/pinctrl/Makefile |2 +- drivers/pinctrl/pinctrl-rockchip.c | 2440 3 files changed, 2454 insertions(+), 86 deletions(-) create mode 100644 drivers/pinctrl/pinctrl-rockchip.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7e8e4b0..6177e7c 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -158,95 +158,23 @@ config PINCTRL_QCA953X the GPIO definitions and pin control functions for each available multiplex function. -config PINCTRL_ROCKCHIP_RK3036 - bool "Rockchip rk3036 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3036 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3128 - bool "Rockchip rk3128 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3128 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3188 - bool "Rockchip rk3188 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3188 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK322X - bool "Rockchip rk322x pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk322x SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3288 - bool "Rockchip rk3288 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3288 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3328 - bool "Rockchip rk3328 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3328 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3368 - bool "Rockchip RK3368 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3368 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3399 - bool "Rockchip rk3399 pin control driver" - depends on DM +config PINCTRL_ROCKCHIP + bool "Rockchip pin control driver" + depends on PINCTRL_FULL + default y help - Support pin multiplexing control on Rockchip rk3399 SoCs. + Support pin multiplexing control on Rockchip SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. + The driver is controlled by a device tree node which contains pin + control functions for each available multiplex function. -config PINCTRL_ROCKCHIP_RV1108 - bool "Rockchip rv1108 pin control driver" - depends on DM +config SPL_PINCTRL_ROCKCHIP + bool "Support Rockchip pin controllers in SPL" + depends on SPL_PINCTRL_FULL + default y help - Support pin multiplexing control on Rockchip rv1108 SoC. - - The driver is controlled by a device tree node which contains - both the GPIO definitions and pin control functions for each - available multiplex function. + This option is an SPL-variant of the PINCTRL_ROCKCHIP option. + See the help of PINCTRL_ROCKCHIP for details. config PINCTRL_SANDBOX bool "Sandbox pinctrl driver" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8c04028..2429eb9 100644 --- a/drivers/pinctrl/Makefile +++ b
[U-Boot] [PATCH 5/9] rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver
The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA to make fdedesc be built in. Signed-off-by: David Wu <david...@rock-chips.com> --- configs/chromebit_mickey_defconfig | 2 -- configs/chromebook_jerry_defconfig | 2 -- configs/chromebook_minnie_defconfig | 2 -- 3 files changed, 6 deletions(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index b350811..93c5c4e 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -88,7 +87,6 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_GADGET_VBUS_DRAW=0 CONFIG_G_DNL_MANUFACTURER="Rockchip" diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index f80faae..57d35e9 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -90,7 +89,6 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_GADGET_VBUS_DRAW=0 CONFIG_G_DNL_MANUFACTURER="Rockchip" diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index ff94a4d..529444a 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -90,7 +89,6 @@ CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_GADGET_VBUS_DRAW=0 CONFIG_G_DNL_MANUFACTURER="Rockchip" -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3288-board-spl.c | 79 ---
1 file changed, 79 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index f64a548..0e68382 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -83,45 +83,6 @@ u32 spl_boot_mode(const u32 boot_device)
return MMCSD_MODE_RAW;
}
-#ifdef CONFIG_SPL_MMC_SUPPORT
-static int configure_emmc(struct udevice *pinctrl)
-{
-#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
-
- struct gpio_desc desc;
- int ret;
-
- pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
-
- /*
-* TODO(s...@chromium.org): Pick this up from device tree or perhaps
-* use the EMMC_PWREN setting.
-*/
- ret = dm_gpio_lookup_name("D9", );
- if (ret) {
- debug("gpio ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_request(, "emmc_pwren");
- if (ret) {
- debug("gpio_request ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_dir_flags(, GPIOD_IS_OUT);
- if (ret) {
- debug("gpio dir ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_value(, 1);
- if (ret) {
- debug("gpio value ret=%d\n", ret);
- return ret;
- }
-#endif
- return 0;
-}
-#endif
-
#if !defined(CONFIG_SPL_OF_PLATDATA)
static int phycore_init(void)
{
@@ -150,7 +111,6 @@ static int phycore_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl;
struct udevice *dev;
int ret;
@@ -189,12 +149,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
#if !defined(CONFIG_SPL_OF_PLATDATA)
if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
ret = phycore_init();
@@ -245,52 +199,19 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
-
if (ret) {
debug("LED ret=%d\n", ret);
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
- ret = configure_emmc(pinctrl);
- if (ret) {
- debug("%s: Failed to set up eMMC\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
#ifdef CONFIG_SPL_OS_BOOT
--
2.7.4
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[U-Boot] [PATCH 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3188-board-spl.c | 42 +++
1 file changed, 3 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 8e3b8ae..8371a31 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -100,10 +100,11 @@ static int setup_arm_clock(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
/* Example code showing how to enable the debug UART on RK3188 */
+#define EARLY_UART
#ifdef EARLY_UART
#include
/* Enable early UART on the RK3188 */
@@ -124,10 +125,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
#endif
ret = spl_early_init();
@@ -144,12 +142,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
ret = uclass_get_device(UCLASS_RAM, 0, );
if (ret) {
debug("DRAM init failed: %d\n", ret);
@@ -187,7 +179,6 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
@@ -196,36 +187,9 @@ void spl_board_init(void)
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, );
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
--
2.7.4
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[U-Boot] [PATCH 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
It seems that pinctrl is not requested for rk3188 SPL, remove it so that can save more space for SPL image size. Signed-off-by: David Wu <david...@rock-chips.com> --- arch/arm/mach-rockchip/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 1e5a7bb..8a0fb83 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -29,7 +29,6 @@ config ROCKCHIP_RK3188 select SUPPORT_SPL select SPL select SPL_CLK - select SPL_PINCTRL select SPL_REGMAP select SPL_SYSCON select SPL_RAM -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver
The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA to make fdedesc be built in. Signed-off-by: David Wu <david...@rock-chips.com> --- configs/evb-rk3399_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index e8e52c3..54eb703 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -22,7 +22,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip
The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config. If use it, the default pinctrl setup from DTS could be configured at device probe. David Wu (9): rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 ARM: rockchip: Remove the pinctrl request at rk3288-board-spl rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver pinctrl: rockchip: Add common rockchip pinctrl driver rockchip: defconfig: Clean the unused pinctrl config pinctrl: rockchip: Clean the unused rockchip pinctrl drivers ARM: dts: rk322x: Correct the uart2 default pin configuration arch/arm/dts/rk322x.dtsi | 11 +- arch/arm/mach-rockchip/Kconfig|1 - arch/arm/mach-rockchip/rk3188-board-spl.c | 42 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 79 - configs/chromebit_mickey_defconfig|4 - configs/chromebook_jerry_defconfig|4 - configs/chromebook_minnie_defconfig |4 - configs/evb-px5_defconfig |1 - configs/evb-rk3128_defconfig |1 - configs/evb-rk3229_defconfig |1 - configs/evb-rk3288_defconfig |2 - configs/evb-rk3399_defconfig |2 - configs/evb-rv1108_defconfig |1 - configs/fennec-rk3288_defconfig |2 - configs/firefly-rk3288_defconfig |2 - configs/firefly-rk3399_defconfig |1 - configs/geekbox_defconfig |1 - configs/kylin-rk3036_defconfig|1 - configs/lion-rk3368_defconfig |1 - configs/miqi-rk3288_defconfig |2 - configs/phycore-rk3288_defconfig |2 - configs/popmetal-rk3288_defconfig |2 - configs/puma-rk3399_defconfig |1 - configs/rock2_defconfig |2 - configs/rock_defconfig|1 - configs/sandbox_defconfig |2 - configs/sandbox_flattree_defconfig|2 - configs/sandbox_noblk_defconfig |2 - configs/sheep-rk3368_defconfig|1 - configs/tinker-rk3288_defconfig |2 - configs/vyasa-rk3288_defconfig|2 - drivers/pinctrl/Kconfig | 98 +- drivers/pinctrl/Makefile |2 +- drivers/pinctrl/pinctrl-rockchip.c| 2440 + drivers/pinctrl/rockchip/Makefile | 15 - drivers/pinctrl/rockchip/pinctrl_rk3036.c | 264 drivers/pinctrl/rockchip/pinctrl_rk3128.c | 187 --- drivers/pinctrl/rockchip/pinctrl_rk3188.c | 610 drivers/pinctrl/rockchip/pinctrl_rk322x.c | 895 --- drivers/pinctrl/rockchip/pinctrl_rk3288.c | 870 -- drivers/pinctrl/rockchip/pinctrl_rk3328.c | 708 - drivers/pinctrl/rockchip/pinctrl_rk3368.c | 742 - drivers/pinctrl/rockchip/pinctrl_rk3399.c | 457 -- drivers/pinctrl/rockchip/pinctrl_rv1108.c | 582 --- 44 files changed, 2466 insertions(+), 5586 deletions(-) create mode 100644 drivers/pinctrl/pinctrl-rockchip.c delete mode 100644 drivers/pinctrl/rockchip/Makefile delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3399.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rv1108.c -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 17/20] config: evb-rk3229: Enable rk gmac configs
Add gmac config support for rk3229 evb. Signed-off-by: David Wu <david...@rock-chips.com> --- Changes in v3: - None Changes in v2: - New patch configs/evb-rk3229_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index b226f66..39469b4 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -31,6 +32,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 20/20] clk: rockchip: clk_rk3368: Implement "assign-clock-parent"
Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 7 ++
drivers/clk/rockchip/clk_rk3368.c | 91 +++--
2 files changed, 91 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 5f6a5fb..6a6fe47 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -95,6 +95,13 @@ enum {
CLK_SARADC_DIV_CON_WIDTH= 8,
/* CLKSEL43_CON */
+ GMAC_DIV_CON_SHIFT = 0x0,
+ GMAC_DIV_CON_MASK = GENMASK(4, 0),
+ GMAC_PLL_SHIFT = 6,
+ GMAC_PLL_MASK = GENMASK(7, 6),
+ GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT),
+ GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT),
+ GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT),
GMAC_MUX_SEL_EXTCLK = BIT(8),
/* CLKSEL51_CON */
diff --git a/drivers/clk/rockchip/clk_rk3368.c
b/drivers/clk/rockchip/clk_rk3368.c
index a831991..3364e6a 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -311,15 +311,43 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru,
ulong set_rate)
#endif
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
-ulong clk_id, ulong set_rate)
+static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
{
+ ulong ret;
+
/*
-* This models the 'assigned-clock-parents = <_gmac>' from
-* the DTS and switches to the 'ext_gmac' clock parent.
+* The gmac clock can be derived either from an external clock
+* or can be generated from internally by a divider from SCLK_MAC.
*/
- rk_setreg(>clksel_con[43], GMAC_MUX_SEL_EXTCLK);
- return set_rate;
+ if (readl(>clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
+ /* An external clock will always generate the right rate... */
+ ret = set_rate;
+ } else {
+ u32 con = readl(>clksel_con[43]);
+ ulong pll_rate;
+ u8 div;
+
+ if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+ GMAC_PLL_SELECT_GENERAL)
+ pll_rate = GPLL_HZ;
+ else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+GMAC_PLL_SELECT_CODEC)
+ pll_rate = CPLL_HZ;
+ else
+ /* CPLL is not set */
+ return -EPERM;
+
+ div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(>clksel_con[43], GMAC_DIV_CON_MASK,
+div << GMAC_DIV_CON_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
}
#endif
@@ -479,7 +507,7 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong
rate)
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
case SCLK_MAC:
/* select the external clock */
- ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);
+ ret = rk3368_gmac_set_clk(priv->cru, rate);
break;
#endif
case SCLK_SARADC:
@@ -492,9 +520,58 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong
rate)
return ret;
}
+static int rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3368_cru *cru = priv->cru;
+ const char *clock_output_name;
+ int ret;
+
+ /*
+* If the requested parent is in the same clock-controller and
+* the id is SCLK_MAC ("sclk_mac"), switch to the internal
+* clock.
+*/
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
+ debug("%s: switching GAMC to SCLK_MAC\n", __func__);
+ rk_clrreg(>clksel_con[43], GMAC_MUX_SEL_EXTCLK);
+ return 0;
+ }
+
+ /*
+* Otherwise, we need to check the clock-output-names of the
+* requested parent to see if the requested id is "ext_gmac".
+*/
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, _output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "e
[U-Boot] [PATCH v3 18/20] ARM: dts: rk3288: Remove unused LCDC clock assigned
The LCDC assigned rate is 0, it will make boot error,
error log:"pll_para_config: the frequency can not be
0 Hz". Remove them, and the lcdc driver will do the
correct clock rate setting.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in v2: None
arch/arm/dts/rk3288.dtsi | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index da51878..2c8a616 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -604,19 +604,16 @@
u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks = < DCLK_VOP0>, < DCLK_VOP1>,
- < PLL_GPLL>, < PLL_CPLL>,
+ assigned-clocks = < PLL_GPLL>, < PLL_CPLL>,
< PLL_NPLL>, < ACLK_CPU>,
< HCLK_CPU>, < PCLK_CPU>,
< ACLK_PERI>, < HCLK_PERI>,
< PCLK_PERI>;
- assigned-clock-rates = <0>, <0>,
- <59400>, <4>,
+ assigned-clock-rates = <59400>, <4>,
<5>, <3>,
<15000>, <7500>,
<3>, <15000>,
<7500>;
- assigned-clock-parents = < PLL_NPLL>, < PLL_GPLL>;
};
grf: syscon@ff77 {
--
2.7.4
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[U-Boot] [PATCH v3 12/20] rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb
Add rk3328-evb gmac support.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/dts/rk3328-evb.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 3dd9d81..336c2d5 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -15,6 +15,13 @@
stdout-path =
};
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -40,6 +47,13 @@
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
};
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
{
@@ -74,6 +88,22 @@
status = "okay";
};
+ {
+ phy-supply = <_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = < RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ assigned-clocks = < SCLK_MAC2IO>, < SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <_clkin>, <_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
_host0_ehci {
status = "okay";
};
--
2.7.4
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[U-Boot] [PATCH v3 16/20] net: gmac_rockchip: Add support for the RK3228 GMAC
The GMAC in the RK3228 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
drivers/net/gmac_rockchip.c | 85 +
1 file changed, 85 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 551c230..683e820 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -69,6 +70,39 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk322x_grf *grf;
+ int clk;
+ enum {
+ RK3228_GMAC_CLK_SEL_SHIFT = 8,
+ RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
+ RK3228_GMAC_CLK_SEL_125M = 0 << 8,
+ RK3228_GMAC_CLK_SEL_25M = 3 << 8,
+ RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3228_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3228_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3228_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct rk3288_grf *grf;
@@ -221,6 +255,50 @@ static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
return 0;
}
+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_RMII_MODE_SHIFT = 10,
+ RK3228_RMII_MODE_MASK = BIT(10),
+
+ RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>mac_con[1],
+RK3228_RMII_MODE_MASK |
+RK3228_GMAC_PHY_INTF_SEL_MASK |
+RK3228_RXCLK_DLY_ENA_GMAC_MASK |
+RK3228_TXCLK_DLY_ENA_GMAC_MASK,
+RK3228_GMAC_PHY_INTF_SEL_RGMII |
+RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
+RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+ rk_clrsetreg(>mac_con[0],
+RK3228_CLK_RX_DL_CFG_GMAC_MASK |
+RK3228_CLK_TX_DL_CFG_GMAC_MASK,
+pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
+pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3288_grf *grf;
@@ -448,6 +526,11 @@ const struct eth_ops gmac_rockchip_eth_ops = {
.write_hwaddr = designware_eth_write_hwaddr,
};
+const struct rk_gmac_ops rk3228_gmac_ops = {
+ .fix_mac_speed = rk3228_gmac_fix_mac_speed,
+ .set_to_rgmii = rk3228_gmac_set_to_rgmii,
+};
+
const struct rk_gmac_ops rk3288_gmac_ops = {
.fix_mac_speed = rk3288_gmac_fix_mac_speed,
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
@@ -474,6 +557,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
};
static const struct udevice_id rockchip_gmac_ids[] = {
+ { .compatible = "rockchip,rk3228-gmac",
+ .data = (ulong)_gmac_ops },
{ .compatible = "rockchip,rk3288-gmac",
.data = (ulong)_gmac_ops },
{ .compatible = "rockchip,rk3328-gmac",
--
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[U-Boot] [PATCH v3 19/20] clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-rate"
The RK3288 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3288 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
implement the gmac clock set parent, but simply ignore the
others' set_rate() operation and return 0 to signal success.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in v2: None
drivers/clk/rockchip/clk_rk3288.c | 106 ++---
include/dt-bindings/clock/rk3288-cru.h | 1 +
2 files changed, 99 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3288.c
b/drivers/clk/rockchip/clk_rk3288.c
index b64c107..baa8122 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -295,15 +295,42 @@ static int pll_para_config(ulong freq_hz, struct pll_div
*div, uint *ext_div)
return 0;
}
-static int rockchip_mac_set_clk(struct rk3288_cru *cru,
- int periph, uint freq)
+static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
{
- /* Assuming mac_clk is fed by an external clock */
- rk_clrsetreg(>cru_clksel_con[21],
-RMII_EXTCLK_MASK,
-RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+ ulong ret;
-return 0;
+ /*
+* The gmac clock can be derived either from an external clock
+* or can be generated from internally by a divider from SCLK_MAC.
+*/
+ if (readl(>cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
+ /* An external clock will always generate the right rate... */
+ ret = freq;
+ } else {
+ u32 con = readl(>cru_clksel_con[21]);
+ ulong pll_rate;
+ u8 div;
+
+ if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
+ EMAC_PLL_SELECT_GENERAL)
+ pll_rate = GPLL_HZ;
+ else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
+EMAC_PLL_SELECT_CODEC)
+ pll_rate = CPLL_HZ;
+ else
+ pll_rate = NPLL_HZ;
+
+ div = DIV_ROUND_UP(pll_rate, freq) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(>cru_clksel_con[21], MAC_DIV_CON_MASK,
+div << MAC_DIV_CON_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
}
static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
@@ -744,7 +771,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong
rate)
break;
#ifndef CONFIG_SPL_BUILD
case SCLK_MAC:
- new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
+ new_rate = rockchip_mac_set_clk(priv->cru, rate);
break;
case DCLK_VOP0:
case DCLK_VOP1:
@@ -797,6 +824,17 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong
rate)
case SCLK_SARADC:
new_rate = rockchip_saradc_set_clk(priv->cru, rate);
break;
+ case PLL_GPLL:
+ case PLL_CPLL:
+ case PLL_NPLL:
+ case ACLK_CPU:
+ case HCLK_CPU:
+ case PCLK_CPU:
+ case ACLK_PERI:
+ case HCLK_PERI:
+ case PCLK_PERI:
+ case SCLK_UART0:
+ return 0;
default:
return -ENOENT;
}
@@ -804,9 +842,61 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong
rate)
return new_rate;
}
+static int rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3288_cru *cru = priv->cru;
+ const char *clock_output_name;
+ int ret;
+
+ /*
+* If the requested parent is in the same clock-controller and
+* the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
+* clock.
+*/
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
+ debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
+ rk_clrsetreg(>cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
+ return 0;
+ }
+
+ /*
+* Otherwise, we need to check the clock-output-names of the
+* requested parent to see if the requested id is "ext_gmac".
+*/
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, _output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "ext_gmac", switch to the external clock input */
+ if (!strcmp(clock_outpu
[U-Boot] [PATCH v3 14/20] rockchip: pinctrl: Add rk322x gmac pinctrl support
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- adhere to the established way of writing this to avoid future confusion
- use defined symbolic constants for drive-strength
Changes in v2:
- New patch
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 148 ++
1 file changed, 148 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c
b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
index 28d9996..354fea2 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
@@ -470,6 +470,56 @@ enum {
CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
};
+/* GRF_GPIO2B_E */
+enum {
+ GRF_GPIO2B0_E_SHIFT = 0,
+ GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT,
+ GRF_GPIO2B1_E_SHIFT = 2,
+ GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT,
+ GRF_GPIO2B3_E_SHIFT = 6,
+ GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT,
+ GRF_GPIO2B4_E_SHIFT = 8,
+ GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT,
+ GRF_GPIO2B5_E_SHIFT = 10,
+ GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT,
+ GRF_GPIO2B6_E_SHIFT = 12,
+ GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT,
+};
+
+/* GRF_GPIO2C_E */
+enum {
+ GRF_GPIO2C0_E_SHIFT = 0,
+ GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT,
+ GRF_GPIO2C1_E_SHIFT = 2,
+ GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT,
+ GRF_GPIO2C2_E_SHIFT = 4,
+ GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT,
+ GRF_GPIO2C3_E_SHIFT = 6,
+ GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT,
+ GRF_GPIO2C4_E_SHIFT = 8,
+ GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT,
+ GRF_GPIO2C5_E_SHIFT = 10,
+ GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT,
+ GRF_GPIO2C6_E_SHIFT = 12,
+ GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT,
+ GRF_GPIO2C7_E_SHIFT = 14,
+ GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT,
+};
+
+/* GRF_GPIO2D_E */
+enum {
+ GRF_GPIO2D1_E_SHIFT = 2,
+ GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT,
+};
+
+/* GPIO Bias drive strength settings */
+enum GPIO_BIAS {
+ GPIO_BIAS_2MA = 0,
+ GPIO_BIAS_4MA,
+ GPIO_BIAS_8MA,
+ GPIO_BIAS_12MA,
+};
+
struct rk322x_pinctrl_priv {
struct rk322x_grf *grf;
};
@@ -633,6 +683,95 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf
*grf, int mmc_id)
}
}
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
+{
+ switch (gmac_id) {
+ case PERIPH_ID_GMAC:
+ /* set rgmii pins mux */
+ rk_clrsetreg(>gpio2b_iomux,
+GPIO2B0_MASK |
+GPIO2B1_MASK |
+GPIO2B3_MASK |
+GPIO2B4_MASK |
+GPIO2B5_MASK |
+GPIO2B6_MASK,
+GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
+GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
+GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
+GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
+GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
+GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
+
+ rk_clrsetreg(>gpio2c_iomux,
+GPIO2C0_MASK |
+GPIO2C1_MASK |
+GPIO2C2_MASK |
+GPIO2C3_MASK |
+GPIO2C4_MASK |
+GPIO2C5_MASK |
+GPIO2C6_MASK |
+GPIO2C7_MASK,
+GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
+GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
+GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
+GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
+GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
+GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
+GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
+GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
+
+ rk_clrsetreg(>gpio2d_iomux,
+GPIO2D1_MASK,
+GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
+
+ /*
+* set rgmii tx pins to 12ma drive-strength,
+* clean others with 2ma.
+*/
+ rk_clrsetreg(>gpio2_e[1],
+GRF_GPIO2B0_E_MASK |
+GRF_GPIO2B1_E_
[U-Boot] [PATCH v3 11/20] rockchip: dts: rk3328: Add gmac2io support
Add basic dts configuration for rk3328 gmac2io.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/dts/rk3328.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 0bab1e3..5de1059 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -456,6 +456,25 @@
status = "disabled";
};
+ gmac2io: ethernet@ff54 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff54 0x0 0x1>;
+ rockchip,grf = <>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ clocks = < SCLK_MAC2IO>, < SCLK_MAC2IO_RX>,
+< SCLK_MAC2IO_TX>, < SCLK_MAC2IO_REF>,
+< SCLK_MAC2IO_REFOUT>, < ACLK_MAC2IO>,
+< PCLK_MAC2IO>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = < SRST_GMAC2IO_A>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@ff5c {
compatible = "generic-ehci";
reg = <0x0 0xff5c 0x0 0x1>;
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 15/20] clk: rockchip: Add rk322x gamc clock support
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add "set parent" for gmac
- Add internal mac clk div_sel for gmac
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk322x.c | 107 ++
1 file changed, 107 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk322x.c
b/drivers/clk/rockchip/clk_rk322x.c
index c8a2413..4e6d2f0 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -239,6 +239,41 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru,
uint clk_general_rate,
return DIV_TO_RATE(src_rate, div) / 2;
}
+static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
+{
+ ulong ret;
+
+ /*
+* The gmac clock can be derived either from an external clock
+* or can be generated from internally by a divider from SCLK_MAC.
+*/
+ if (readl(>cru_clksel_con[5]) & BIT(5)) {
+ /* An external clock will always generate the right rate... */
+ ret = freq;
+ } else {
+ u32 con = readl(>cru_clksel_con[5]);
+ ulong pll_rate;
+ u8 div;
+
+ if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
+ pll_rate = GPLL_HZ;
+ else
+ /* CPLL is not set */
+ return -EPERM;
+
+ div = DIV_ROUND_UP(pll_rate, freq) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(>cru_clksel_con[5], CLK_MAC_DIV_MASK,
+div << CLK_MAC_DIV_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
+}
+
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint
clk_general_rate,
int periph, uint freq)
{
@@ -352,6 +387,11 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong
rate)
case CLK_DDR:
new_rate = rk322x_ddr_set_clk(priv->cru, rate);
break;
+ case SCLK_MAC:
+ new_rate = rk322x_mac_set_clk(priv->cru, rate);
+ break;
+ case PLL_GPLL:
+ return 0;
default:
return -ENOENT;
}
@@ -359,9 +399,76 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong
rate)
return new_rate;
}
+static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk322x_cru *cru = priv->cru;
+
+ /*
+* If the requested parent is in the same clock-controller and the id
+* is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
+*/
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
+ debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
+ rk_clrsetreg(>cru_clksel_con[5], BIT(5), 0);
+ return 0;
+ }
+
+ /*
+* If the requested parent is in the same clock-controller and the id
+* is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
+*/
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
+ debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
+ rk_clrsetreg(>cru_clksel_con[5], BIT(5), BIT(5));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ const char *clock_output_name;
+ struct rk322x_cru *cru = priv->cru;
+ int ret;
+
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, _output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ if (!strcmp(clock_output_name, "ext_gmac")) {
+ debug("%s: switching gmac extclk to ext_gmac\n", __func__);
+ rk_clrsetreg(>cru_clksel_con[29], BIT(10), 0);
+ return 0;
+ } else if (!strcmp(clock_output_name, "phy_50m_out")) {
+ debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
+ rk_clrsetreg(>cru_clksel_con[29], BIT(10), BIT(10));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case SCLK_MAC:
+ return rk322x_gmac_set_parent(clk, par
[U-Boot] [PATCH v3 13/20] rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver
Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Fix the wrong define for uart2 iomux
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455
arch/arm/mach-rockchip/rk322x-board-spl.c | 22 +-
arch/arm/mach-rockchip/rk322x-board.c | 18 +
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 453 +++
4 files changed, 492 insertions(+), 456 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
index c0c0d84..52e5a0a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
@@ -88,461 +88,6 @@ struct rk322x_sgrf {
unsigned int busdmac_con[4];
};
-/* GRF_GPIO0A_IOMUX */
-enum {
- GPIO0A7_SHIFT = 14,
- GPIO0A7_MASK= 3 << GPIO0A7_SHIFT,
- GPIO0A7_GPIO= 0,
- GPIO0A7_I2C3_SDA,
- GPIO0A7_HDMI_DDCSDA,
-
- GPIO0A6_SHIFT = 12,
- GPIO0A6_MASK= 3 << GPIO0A6_SHIFT,
- GPIO0A6_GPIO= 0,
- GPIO0A6_I2C3_SCL,
- GPIO0A6_HDMI_DDCSCL,
-
- GPIO0A3_SHIFT = 6,
- GPIO0A3_MASK= 3 << GPIO0A3_SHIFT,
- GPIO0A3_GPIO= 0,
- GPIO0A3_I2C1_SDA,
- GPIO0A3_SDIO_CMD,
-
- GPIO0A2_SHIFT = 4,
- GPIO0A2_MASK= 3 << GPIO0A2_SHIFT,
- GPIO0A2_GPIO= 0,
- GPIO0A2_I2C1_SCL,
-
- GPIO0A1_SHIFT = 2,
- GPIO0A1_MASK= 3 << GPIO0A1_SHIFT,
- GPIO0A1_GPIO= 0,
- GPIO0A1_I2C0_SDA,
-
- GPIO0A0_SHIFT = 0,
- GPIO0A0_MASK= 3 << GPIO0A0_SHIFT,
- GPIO0A0_GPIO= 0,
- GPIO0A0_I2C0_SCL,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
- GPIO0B7_SHIFT = 14,
- GPIO0B7_MASK= 3 << GPIO0B7_SHIFT,
- GPIO0B7_GPIO= 0,
- GPIO0B7_HDMI_HDP,
-
- GPIO0B6_SHIFT = 12,
- GPIO0B6_MASK= 3 << GPIO0B6_SHIFT,
- GPIO0B6_GPIO= 0,
- GPIO0B6_I2S_SDI,
- GPIO0B6_SPI_CSN0,
-
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK= 3 << GPIO0B5_SHIFT,
- GPIO0B5_GPIO= 0,
- GPIO0B5_I2S_SDO,
- GPIO0B5_SPI_RXD,
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK= 3 << GPIO0B3_SHIFT,
- GPIO0B3_GPIO= 0,
- GPIO0B3_I2S1_LRCKRX,
- GPIO0B3_SPI_TXD,
-
- GPIO0B1_SHIFT = 2,
- GPIO0B1_MASK= 3 << GPIO0B1_SHIFT,
- GPIO0B1_GPIO= 0,
- GPIO0B1_I2S_SCLK,
- GPIO0B1_SPI_CLK,
-
- GPIO0B0_SHIFT = 0,
- GPIO0B0_MASK= 3,
- GPIO0B0_GPIO= 0,
- GPIO0B0_I2S_MCLK,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK= 3 << GPIO0C4_SHIFT,
- GPIO0C4_GPIO= 0,
- GPIO0C4_HDMI_CECSDA,
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK= 3 << GPIO0C1_SHIFT,
- GPIO0C1_GPIO= 0,
- GPIO0C1_UART0_RSTN,
- GPIO0C1_CLK_OUT1,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK= 3 << GPIO0D6_SHIFT,
- GPIO0D6_GPIO= 0,
- GPIO0D6_SDIO_PWREN,
- GPIO0D6_PWM11,
-
-
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK= 3 << GPIO0D4_SHIFT,
- GPIO0D4_GPIO= 0,
- GPIO0D4_PWM2,
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK= 3 << GPIO0D3_SHIFT,
- GPIO0D3_GPIO= 0,
- GPIO0D3_PWM1,
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK= 3 << GPIO0D2_SHIFT,
- GPIO0D2_GPIO= 0,
- GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
- GPIO1A7_SHIFT = 14,
- GPIO1A7_MASK= 1,
- GPIO1A7_GPIO= 0,
- GPIO1A7_SDMMC_WRPRT,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK= 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO= 0,
- GPIO1B7_SDMMC_CMD,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK= 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO= 0,
- GPIO1B6_SDMMC_PWREN,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK= 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO= 0,
- GPIO1B4_SPI_CSN1,
- GPIO1B4_PWM12,
-
[U-Boot] [PATCH v3 10/20] rockchip: configs: Enable GMAC configs for evb-rk3328
Enable GMAC configs for evb-rk3328 Signed-off-by: David Wu <david...@rock-chips.com> --- Changes in v3: - None Changes in v2: - New patch configs/evb-rk3328_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 3b8b104..3d8c04d 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y @@ -24,6 +25,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3328=y CONFIG_DM_PMIC=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 09/20] net: gmac_rockchip: Add rk3328 gmac support
The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3328-specific logic necessary to reuse this driver.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
drivers/net/gmac_rockchip.c | 85 +
1 file changed, 85 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index cfffe29..551c230 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -94,6 +95,39 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
+static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk3328_grf_regs *grf;
+ int clk;
+ enum {
+ RK3328_GMAC_CLK_SEL_SHIFT = 11,
+ RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
+ RK3328_GMAC_CLK_SEL_125M = 0 << 11,
+ RK3328_GMAC_CLK_SEL_25M = 3 << 11,
+ RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3328_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3328_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3328_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct rk3368_grf *grf;
@@ -207,6 +241,50 @@ static void rk3288_gmac_set_to_rgmii(struct
gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_RMII_MODE_SHIFT = 9,
+ RK3328_RMII_MODE_MASK = BIT(9),
+
+ RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>mac_con[1],
+RK3328_RMII_MODE_MASK |
+RK3328_GMAC_PHY_INTF_SEL_MASK |
+RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+RK3328_TXCLK_DLY_ENA_GMAC_MASK,
+RK3328_GMAC_PHY_INTF_SEL_RGMII |
+RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+ rk_clrsetreg(>mac_con[0],
+RK3328_CLK_RX_DL_CFG_GMAC_MASK |
+RK3328_CLK_TX_DL_CFG_GMAC_MASK,
+pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
+pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3368_grf *grf;
@@ -375,6 +453,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
};
+const struct rk_gmac_ops rk3328_gmac_ops = {
+ .fix_mac_speed = rk3328_gmac_fix_mac_speed,
+ .set_to_rgmii = rk3328_gmac_set_to_rgmii,
+};
+
const struct rk_gmac_ops rk3368_gmac_ops = {
.fix_mac_speed = rk3368_gmac_fix_mac_speed,
.set_to_rgmii = rk3368_gmac_set_to_rgmii,
@@ -393,6 +476,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
static const struct udevice_id rockchip_gmac_ids[] = {
{ .compatible = "rockchip,rk3288-gmac",
.data = (ulong)_gmac_ops },
+ { .compatible = "rockchip,rk3328-gmac",
+ .data = (ulong)_gmac_ops },
{ .compatible = "rockchip,rk3368-gmac",
.data = (ulong)_gmac_ops },
{ .compatible = "rockchip,rk3399-gmac",
[U-Boot] [PATCH v3 08/20] clk: rockchip: Add rk3328 gamc clock support
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add "set parent" for gmac2io
- Add internal mac clk div_sel for gmac2io
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk3328.c | 178 +
include/dt-bindings/clock/rk3328-cru.h | 6 +-
2 files changed, 181 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index fa0c777..2ccc798 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -94,6 +95,14 @@ enum {
PCLK_DBG_DIV_SHIFT = 0,
PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
+ /* CLKSEL_CON27 */
+ GMAC2IO_PLL_SEL_SHIFT = 7,
+ GMAC2IO_PLL_SEL_MASK= 1 << GMAC2IO_PLL_SEL_SHIFT,
+ GMAC2IO_PLL_SEL_CPLL= 0,
+ GMAC2IO_PLL_SEL_GPLL= 1,
+ GMAC2IO_CLK_DIV_MASK= 0x1f,
+ GMAC2IO_CLK_DIV_SHIFT = 0,
+
/* CLKSEL_CON28 */
ACLK_PERIHP_PLL_SEL_CPLL= 0,
ACLK_PERIHP_PLL_SEL_GPLL,
@@ -393,6 +402,44 @@ static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru,
ulong clk_id, uint hz)
return DIV_TO_RATE(GPLL_HZ, src_clk_div);
}
+static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
+{
+ struct rk3328_grf_regs *grf;
+ ulong ret;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+* The RGMII CLK can be derived either from an external "clkin"
+* or can be generated from internally by a divider from SCLK_MAC.
+*/
+ if (readl(>mac_con[1]) & BIT(10) &&
+ readl(>soc_con[4]) & BIT(14)) {
+ /* An external clock will always generate the right rate... */
+ ret = rate;
+ } else {
+ u32 con = readl(>clksel_con[27]);
+ ulong pll_rate;
+ u8 div;
+
+ if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
+ pll_rate = GPLL_HZ;
+ else
+ pll_rate = CPLL_HZ;
+
+ div = DIV_ROUND_UP(pll_rate, rate) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(>clksel_con[27], GMAC2IO_CLK_DIV_MASK,
+div << GMAC2IO_CLK_DIV_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
+}
+
static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
{
u32 div, con, con_id;
@@ -558,12 +605,48 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong
rate)
case SCLK_I2C3:
ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
break;
+ case SCLK_MAC2IO:
+ ret = rk3328_gmac2io_set_clk(priv->cru, rate);
+ break;
case SCLK_PWM:
ret = rk3328_pwm_set_clk(priv->cru, rate);
break;
case SCLK_SARADC:
ret = rk3328_saradc_set_clk(priv->cru, rate);
break;
+ case DCLK_LCDC:
+ case SCLK_PDM:
+ case SCLK_RTC32K:
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_SDIO:
+ case SCLK_TSP:
+ case SCLK_WIFI:
+ case ACLK_BUS_PRE:
+ case HCLK_BUS_PRE:
+ case PCLK_BUS_PRE:
+ case ACLK_PERI_PRE:
+ case HCLK_PERI:
+ case PCLK_PERI:
+ case ACLK_VIO_PRE:
+ case HCLK_VIO_PRE:
+ case ACLK_RGA_PRE:
+ case SCLK_RGA:
+ case ACLK_VOP_PRE:
+ case ACLK_RKVDEC_PRE:
+ case ACLK_RKVENC:
+ case ACLK_VPU_PRE:
+ case SCLK_VDEC_CABAC:
+ case SCLK_VDEC_CORE:
+ case SCLK_VENC_CORE:
+ case SCLK_VENC_DSP:
+ case SCLK_EFUSE:
+ case PCLK_DDR:
+ case ACLK_GMAC:
+ case PCLK_GMAC:
+ case SCLK_USB3OTG_SUSPEND:
+ return 0;
default:
return -ENOENT;
}
@@ -571,9 +654,104 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong
rate)
return ret;
}
+static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3328_grf_regs *grf;
+ const char *clock_output_name;
+ int ret;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+* If the requested parent is in the same clock-controller and the id
+* is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
+*
[U-Boot] [PATCH v3 06/20] rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver
Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 113
2 files changed, 113 insertions(+), 113 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index f0a0781..0c37f2a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -131,118 +131,5 @@ struct rk3328_sgrf_regs {
};
check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
-enum {
- /* GPIO0A_IOMUX */
- GPIO0A5_SEL_SHIFT = 10,
- GPIO0A5_SEL_MASK= 3 << GPIO0A5_SEL_SHIFT,
- GPIO0A5_I2C3_SCL= 2,
-
- GPIO0A6_SEL_SHIFT = 12,
- GPIO0A6_SEL_MASK= 3 << GPIO0A6_SEL_SHIFT,
- GPIO0A6_I2C3_SDA= 2,
-
- GPIO0A7_SEL_SHIFT = 14,
- GPIO0A7_SEL_MASK= 3 << GPIO0A7_SEL_SHIFT,
- GPIO0A7_EMMC_DATA0 = 2,
-
- /* GPIO0D_IOMUX*/
- GPIO0D6_SEL_SHIFT = 12,
- GPIO0D6_SEL_MASK= 3 << GPIO0D6_SEL_SHIFT,
- GPIO0D6_GPIO= 0,
- GPIO0D6_SDMMC0_PWRENM1 = 3,
-
- /* GPIO1A_IOMUX */
- GPIO1A0_SEL_SHIFT = 0,
- GPIO1A0_SEL_MASK= 0x3fff << GPIO1A0_SEL_SHIFT,
- GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
-
- /* GPIO2A_IOMUX */
- GPIO2A0_SEL_SHIFT = 0,
- GPIO2A0_SEL_MASK= 3 << GPIO2A0_SEL_SHIFT,
- GPIO2A0_UART2_TX_M1 = 1,
-
- GPIO2A1_SEL_SHIFT = 2,
- GPIO2A1_SEL_MASK= 3 << GPIO2A1_SEL_SHIFT,
- GPIO2A1_UART2_RX_M1 = 1,
-
- GPIO2A2_SEL_SHIFT = 4,
- GPIO2A2_SEL_MASK= 3 << GPIO2A2_SEL_SHIFT,
- GPIO2A2_PWM_IR = 1,
-
- GPIO2A4_SEL_SHIFT = 8,
- GPIO2A4_SEL_MASK= 3 << GPIO2A4_SEL_SHIFT,
- GPIO2A4_PWM_0 = 1,
- GPIO2A4_I2C1_SDA,
-
- GPIO2A5_SEL_SHIFT = 10,
- GPIO2A5_SEL_MASK= 3 << GPIO2A5_SEL_SHIFT,
- GPIO2A5_PWM_1 = 1,
- GPIO2A5_I2C1_SCL,
-
- GPIO2A6_SEL_SHIFT = 12,
- GPIO2A6_SEL_MASK= 3 << GPIO2A6_SEL_SHIFT,
- GPIO2A6_PWM_2 = 1,
-
- GPIO2A7_SEL_SHIFT = 14,
- GPIO2A7_SEL_MASK= 3 << GPIO2A7_SEL_SHIFT,
- GPIO2A7_GPIO= 0,
- GPIO2A7_SDMMC0_PWRENM0,
-
- /* GPIO2BL_IOMUX */
- GPIO2BL0_SEL_SHIFT = 0,
- GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
- GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
-
- GPIO2BL3_SEL_SHIFT = 6,
- GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
- GPIO2BL3_SPI_CSN0_M0= 1,
-
- GPIO2BL4_SEL_SHIFT = 8,
- GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
- GPIO2BL4_SPI_CSN1_M0= 1,
-
- GPIO2BL5_SEL_SHIFT = 10,
- GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
- GPIO2BL5_I2C2_SDA = 1,
-
- GPIO2BL6_SEL_SHIFT = 12,
- GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
- GPIO2BL6_I2C2_SCL = 1,
-
- /* GPIO2D_IOMUX */
- GPIO2D0_SEL_SHIFT = 0,
- GPIO2D0_SEL_MASK= 3 << GPIO2D0_SEL_SHIFT,
- GPIO2D0_I2C0_SCL= 1,
-
- GPIO2D1_SEL_SHIFT = 2,
- GPIO2D1_SEL_MASK= 3 << GPIO2D1_SEL_SHIFT,
- GPIO2D1_I2C0_SDA= 1,
-
- GPIO2D4_SEL_SHIFT = 8,
- GPIO2D4_SEL_MASK= 0xff << GPIO2D4_SEL_SHIFT,
- GPIO2D4_EMMC_DATA1234 = 0xaa,
-
- /* GPIO3C_IOMUX */
- GPIO3C0_SEL_SHIFT = 0,
- GPIO3C0_SEL_MASK= 0x3fff << GPIO3C0_SEL_SHIFT,
- GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
-
- /* COM_IOMUX */
- IOMUX_SEL_UART2_SHIFT = 0,
- IOMUX_SEL_UART2_MASK= 3 << IOMUX_SEL_UART2_SHIFT,
- IOMUX_SEL_UART2_M0 = 0,
- IOMUX_SEL_UART2_M1,
-
- IOMUX_SEL_SPI_SHIFT = 4,
- IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
- IOMUX_SEL_SPI_M0= 0,
- IOMUX_SEL_SPI_M1,
- IOMUX_SEL_SPI_M2,
-
- IOMUX_SEL_SDMMC_SHIFT = 7,
- IOMUX_SEL_SDMMC_MASK= 1 << IOMUX_SEL_SDMMC_SHIFT,
- IOMUX_SEL_SDMMC_M0 = 0,
- IOMUX_SEL_SDMMC_M1,
-};
#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index c74163e..3c2253f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328
[U-Boot] [PATCH v3 07/20] rockchip: pinctrl: Add rk3328 gmac pinctrl support
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
and bit10 at com iomux register. After that, set rgmii m1 tx
pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- adhere to the established way of writing this to avoid future confusion
- use defined symbolic constants for drive-strength
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 1 -
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 275
2 files changed, 275 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index 0c37f2a..2776cef 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -131,5 +131,4 @@ struct rk3328_sgrf_regs {
};
check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
-
#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index 3c2253f..fa2356a 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -31,6 +31,37 @@ enum {
GPIO0A7_SEL_MASK= 3 << GPIO0A7_SEL_SHIFT,
GPIO0A7_EMMC_DATA0 = 2,
+ /* GPIO0B_IOMUX*/
+ GPIO0B0_SEL_SHIFT = 0,
+ GPIO0B0_SEL_MASK= 3 << GPIO0B0_SEL_SHIFT,
+ GPIO0B0_GAMC_CLKTXM0= 1,
+
+ GPIO0B4_SEL_SHIFT = 8,
+ GPIO0B4_SEL_MASK= 3 << GPIO0B4_SEL_SHIFT,
+ GPIO0B4_GAMC_TXENM0 = 1,
+
+ /* GPIO0C_IOMUX*/
+ GPIO0C0_SEL_SHIFT = 0,
+ GPIO0C0_SEL_MASK= 3 << GPIO0C0_SEL_SHIFT,
+ GPIO0C0_GAMC_TXD1M0 = 1,
+
+ GPIO0C1_SEL_SHIFT = 2,
+ GPIO0C1_SEL_MASK= 3 << GPIO0C1_SEL_SHIFT,
+ GPIO0C1_GAMC_TXD0M0 = 1,
+
+ GPIO0C6_SEL_SHIFT = 12,
+ GPIO0C6_SEL_MASK= 3 << GPIO0C6_SEL_SHIFT,
+ GPIO0C6_GAMC_TXD2M0 = 1,
+
+ GPIO0C7_SEL_SHIFT = 14,
+ GPIO0C7_SEL_MASK= 3 << GPIO0C7_SEL_SHIFT,
+ GPIO0C7_GAMC_TXD3M0 = 1,
+
+ /* GPIO0D_IOMUX*/
+ GPIO0D0_SEL_SHIFT = 0,
+ GPIO0D0_SEL_MASK= 3 << GPIO0D0_SEL_SHIFT,
+ GPIO0D0_GMAC_CLKM0 = 1,
+
GPIO0D6_SEL_SHIFT = 12,
GPIO0D6_SEL_MASK= 3 << GPIO0D6_SEL_SHIFT,
GPIO0D6_GPIO= 0,
@@ -41,6 +72,69 @@ enum {
GPIO1A0_SEL_MASK= 0x3fff << GPIO1A0_SEL_SHIFT,
GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
+ /* GPIO1B_IOMUX */
+ GPIO1B0_SEL_SHIFT = 0,
+ GPIO1B0_SEL_MASK= 3 << GPIO1B0_SEL_SHIFT,
+ GPIO1B0_GMAC_TXD1M1 = 2,
+
+ GPIO1B1_SEL_SHIFT = 2,
+ GPIO1B1_SEL_MASK= 3 << GPIO1B1_SEL_SHIFT,
+ GPIO1B1_GMAC_TXD0M1 = 2,
+
+ GPIO1B2_SEL_SHIFT = 4,
+ GPIO1B2_SEL_MASK= 3 << GPIO1B2_SEL_SHIFT,
+ GPIO1B2_GMAC_RXD1M1 = 2,
+
+ GPIO1B3_SEL_SHIFT = 6,
+ GPIO1B3_SEL_MASK= 3 << GPIO1B3_SEL_SHIFT,
+ GPIO1B3_GMAC_RXD0M1 = 2,
+
+ GPIO1B4_SEL_SHIFT = 8,
+ GPIO1B4_SEL_MASK= 3 << GPIO1B4_SEL_SHIFT,
+ GPIO1B4_GMAC_TXCLKM1= 2,
+
+ GPIO1B5_SEL_SHIFT = 10,
+ GPIO1B5_SEL_MASK= 3 << GPIO1B5_SEL_SHIFT,
+ GPIO1B5_GMAC_RXCLKM1= 2,
+
+ GPIO1B6_SEL_SHIFT = 12,
+ GPIO1B6_SEL_MASK= 3 << GPIO1B6_SEL_SHIFT,
+ GPIO1B6_GMAC_RXD3M1 = 2,
+
+ GPIO1B7_SEL_SHIFT = 14,
+ GPIO1B7_SEL_MASK= 3 << GPIO1B7_SEL_SHIFT,
+ GPIO1B7_GMAC_RXD2M1 = 2,
+
+ /* GPIO1C_IOMUX */
+ GPIO1C0_SEL_SHIFT = 0,
+ GPIO1C0_SEL_MASK= 3 << GPIO1C0_SEL_SHIFT,
+ GPIO1C0_GMAC_TXD3M1 = 2,
+
+ GPIO1C1_SEL_SHIFT = 2,
+ GPIO1C1_SEL_MASK= 3 << GPIO1C1_SEL_SHIFT,
+ GPIO1C1_GMAC_TXD2M1 = 2,
+
+ GPIO1C3_SEL_SHIFT = 6,
+ GPIO1C3_SEL_MASK= 3 << GPIO1C3_SEL_SHIFT,
+ GPIO1C3_GMAC_MDIOM1 = 2,
+
+ GPIO1C5_SEL_SHIFT = 10,
+ GPIO1C5_SEL_MASK= 3 << GPIO1C5_SEL_SHIFT,
+ GPIO1C5_GMAC_CLKM1 = 2,
+
+ GPIO1C6_SEL_SHIFT = 12,
+ GPIO1C6_SEL_MASK= 3 << GPIO1C6_SEL_SHIFT,
+ GPIO1C6_GMAC_RXDVM1 = 2,
+
+ GPIO1C7_SEL_SHIFT = 14,
+ GPIO1C7_SEL_MASK= 3 << GPIO1C7_SEL_SHIFT,
+ GPIO1C7_GMAC_MDCM1 = 2,
+
+ /* GPIO1D_IOMUX */
+ GPIO1D1_SEL_SHIFT = 2,
+ GPIO1D1_SEL_MASK= 3 << GPIO1D1_SEL_SHIFT,
+ GPIO1D1_GMAC_TXENM1 = 2,
+
/* GPIO2A_IOMUX */
GPIO2A0_SEL_SHIFT = 0,
GPIO2A0_SEL_MASK
[U-Boot] [PATCH v3 05/20] net: gmac_rockchip: Add support for the RV1108 GMAC
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- return error if there was no set_to_rgmii ops at rgmii case
- return error if there was no set_to_rmii ops at rmii case
- set and check clock rate when gmac clock is internal pll.
Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Clean the grf offset at gmac_rockchip.c
- Use current phy interface to set mac clock rate
drivers/net/gmac_rockchip.c | 115 +---
1 file changed, 109 insertions(+), 6 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 586ccbf..cfffe29 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include "designware.h"
@@ -31,12 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
*/
struct gmac_rockchip_platdata {
struct dw_eth_pdata dw_eth_pdata;
+ bool clock_input;
int tx_delay;
int rx_delay;
};
struct rk_gmac_ops {
int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -44,6 +47,13 @@ struct rk_gmac_ops {
static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ const char *string;
+
+ string = dev_read_string(dev, "clock_in_out");
+ if (!strcmp(string, "input"))
+ pdata->clock_input = true;
+ else
+ pdata->clock_input = false;
/* Check the new naming-style first... */
pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
@@ -142,6 +152,41 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
+static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+{
+ struct rv1108_grf *grf;
+ int clk, speed;
+ enum {
+ RV1108_GMAC_SPEED_MASK = BIT(2),
+ RV1108_GMAC_SPEED_10M = 0 << 2,
+ RV1108_GMAC_SPEED_100M = 1 << 2,
+ RV1108_GMAC_CLK_SEL_MASK= BIT(7),
+ RV1108_GMAC_CLK_SEL_2_5M= 0 << 7,
+ RV1108_GMAC_CLK_SEL_25M = 1 << 7,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RV1108_GMAC_CLK_SEL_2_5M;
+ speed = RV1108_GMAC_SPEED_10M;
+ break;
+ case 100:
+ clk = RV1108_GMAC_CLK_SEL_25M;
+ speed = RV1108_GMAC_SPEED_100M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>gmac_con0,
+RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
+clk | speed);
+
+ return 0;
+}
+
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3288_grf *grf;
@@ -221,25 +266,76 @@ static void rk3399_gmac_set_to_rgmii(struct
gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rv1108_grf *grf;
+
+ enum {
+ RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>gmac_con0,
+RV1108_GMAC_PHY_INTF_SEL_MASK,
+RV1108_GMAC_PHY_INTF_SEL_RMII);
+}
+
static int gmac_rockchip_probe(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = _pdata->eth_pdata;
struct clk clk;
+ ulong rate;
int ret;
ret = clk_get_by_index(dev, 0, );
if (ret)
return ret;
- /* Since mac_clk is fed by an external clock we can use 0 here */
- ret = clk_set_rate(, 0);
- if (ret)
- return ret;
+ switch (eth_pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ /*
+* If the gmac clock is from internal pll, need
[U-Boot] [PATCH v3 02/20] rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb
If the Ethernet address is not set, the network can't work, enable the random address config for default use. Signed-off-by: David Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> --- Changes in v3: - None Changes in v2: - None configs/evb-rk3288_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index e944f97..6c67509 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 04/20] rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver
If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
and move them into pinctrl-driver.
Signed-off-by: David Wu <david...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v3:
- Fix the wrong define for uart2M0
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 399
board/rockchip/evb_rv1108/evb_rv1108.c | 17 +
drivers/pinctrl/rockchip/pinctrl_rv1108.c | 399
3 files changed, 416 insertions(+), 399 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index 428cf6a..76e742b 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -111,403 +111,4 @@ struct rv1108_grf {
};
check_member(rv1108_grf, chip_id, 0x0c00);
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK= 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO= 0,
- GPIO1B7_LCDC_D12,
- GPIO1B7_I2S_SDIO2_M0,
- GPIO1B7_GMAC_RXDV,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK= 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO= 0,
- GPIO1B6_LCDC_D13,
- GPIO1B6_I2S_LRCLKTX_M0,
- GPIO1B6_GMAC_RXD1,
-
- GPIO1B5_SHIFT = 10,
- GPIO1B5_MASK= 3 << GPIO1B5_SHIFT,
- GPIO1B5_GPIO= 0,
- GPIO1B5_LCDC_D14,
- GPIO1B5_I2S_SDIO1_M0,
- GPIO1B5_GMAC_RXD0,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK= 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO= 0,
- GPIO1B4_LCDC_D15,
- GPIO1B4_I2S_MCLK_M0,
- GPIO1B4_GMAC_TXEN,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK= 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO= 0,
- GPIO1B3_LCDC_D16,
- GPIO1B3_I2S_SCLK_M0,
- GPIO1B3_GMAC_TXD1,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK= 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO= 0,
- GPIO1B2_LCDC_D17,
- GPIO1B2_I2S_SDIO_M0,
- GPIO1B2_GMAC_TXD0,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK= 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO= 0,
- GPIO1B1_LCDC_D9,
- GPIO1B1_PWM7,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK= 3,
- GPIO1B0_GPIO= 0,
- GPIO1B0_LCDC_D8,
- GPIO1B0_PWM6,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK= 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO= 0,
- GPIO1C7_CIF_D5,
- GPIO1C7_I2S_SDIO2_M1,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK= 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO= 0,
- GPIO1C6_CIF_D4,
- GPIO1C6_I2S_LRCLKTX_M1,
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK= 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO= 0,
- GPIO1C5_LCDC_CLK,
- GPIO1C5_GMAC_CLK,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK= 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO= 0,
- GPIO1C4_LCDC_HSYNC,
- GPIO1C4_GMAC_MDC,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK= 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO= 0,
- GPIO1C3_LCDC_VSYNC,
- GPIO1C3_GMAC_MDIO,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK= 3 << GPIO1C2_SHIFT,
- GPIO1C2_GPIO= 0,
- GPIO1C2_LCDC_EN,
- GPIO1C2_I2S_SDIO3_M0,
- GPIO1C2_GMAC_RXER,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK= 3 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO= 0,
- GPIO1C1_LCDC_D10,
- GPIO1C1_I2S_SDI_M0,
- GPIO1C1_PWM4,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK= 3,
- GPIO1C0_GPIO= 0,
- GPIO1C0_LCDC_D11,
- GPIO1C0_I2S_LRCLKRX_M0,
-};
-
-/* GRF_GPIO1D_OIMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK= 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO= 0,
- GPIO1D7_HDMI_CEC,
- GPIO1D7_DSP_RTCK,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK= 1 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO= 0,
- GPIO1D6_HDMI_HPD_M0,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK= 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO= 0,
- GPIO1D5_UART2_RTSN,
- GPIO1D5_HDMI_SDA_M0,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK= 3 << GPIO1D4_SHIFT,
- GPI
[U-Boot] [PATCH v3 01/20] rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality
Give the mac controller the correct tx-delay and rx-delay value for the rgmii mode transmission. If they are not matched, there would be Ethernet packets lost, the net feature may not work. Signed-off-by: David Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> --- Changes in v3: - None Changes in v2: - None arch/arm/dts/rk3399-evb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index f0567c9..ed0e00e 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -279,7 +279,7 @@ assigned-clock-parents = <_gmac>; pinctrl-names = "default"; pinctrl-0 = <_pins>; - tx_delay = <0x10>; - rx_delay = <0x10>; + tx_delay = <0x28>; + rx_delay = <0x11>; status = "okay"; }; -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 03/20] rockchip: grf_rv1108.h: Fix the grf offsets
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.
Signed-off-by: David Wu <david...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index c816a5b..428cf6a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -100,13 +100,17 @@ struct rv1108_grf {
u32 reserved14[2];
u32 dma_con0;
u32 dma_con1;
- u32 reserved15[539];
+ u32 reserved15[59];
u32 uoc_status;
+ u32 reserved16[2];
u32 host_status;
+ u32 reserved17[59];
u32 gmac_con0;
+ u32 reserved18[191];
u32 chip_id;
};
-check_member(rv1108_grf, chip_id, 0xf90);
+
+check_member(rv1108_grf, chip_id, 0x0c00);
/* GRF_GPIO1B_IOMUX */
enum {
--
2.7.4
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[U-Boot] [PATCH v3 00/20] Add gmac support for rk3399-evb rv1108-evb rk3328-evb and rk3229-evb
This serie of patches add rmii interface support, and support more socs's gmac function, such as rv1108, rk3328 and rk3229. Implement the "assign-clock-parent" and "assign-clock-rate" for rk3328, rk3228, rk3288 and rk3368. This series of patches is based on Philipp's branch: https://github.com/ptomsich/u-boot-rockchip/tree/assigned-clocks-wip Changes in v3: - Add "set parent" for gmac - Add "set parent" for gmac2io - Add internal mac clk div_sel for gmac - Add internal mac clk div_sel for gmac2io - Fix the wrong define for uart2 iomux - Fix the wrong define for uart2M0 - New patch - None - adhere to the established way of writing this to avoid future confusion - return error if there was no set_to_rgmii ops at rgmii case - return error if there was no set_to_rmii ops at rmii case - set and check clock rate when gmac clock is internal pll. - use defined symbolic constants for drive-strength Changes in v2: - Add check whether the set rgmii/rmii function is a valid function pointer - Clean the grf offset at gmac_rockchip.c - New patch - None - Use current phy interface to set mac clock rate David Wu (20): rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb rockchip: grf_rv1108.h: Fix the grf offsets rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver net: gmac_rockchip: Add support for the RV1108 GMAC rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver rockchip: pinctrl: Add rk3328 gmac pinctrl support clk: rockchip: Add rk3328 gamc clock support net: gmac_rockchip: Add rk3328 gmac support rockchip: configs: Enable GMAC configs for evb-rk3328 rockchip: dts: rk3328: Add gmac2io support rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver rockchip: pinctrl: Add rk322x gmac pinctrl support clk: rockchip: Add rk322x gamc clock support net: gmac_rockchip: Add support for the RK3228 GMAC config: evb-rk3229: Enable rk gmac configs ARM: dts: rk3288: Remove unused LCDC clock assigned clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-rate" clk: rockchip: clk_rk3368: Implement "assign-clock-parent" arch/arm/dts/rk3288.dtsi| 7 +- arch/arm/dts/rk3328-evb.dts | 30 ++ arch/arm/dts/rk3328.dtsi| 19 + arch/arm/dts/rk3399-evb.dts | 4 +- arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 7 + arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 -- arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 114 - arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 405 +--- arch/arm/mach-rockchip/rk322x-board-spl.c | 22 +- arch/arm/mach-rockchip/rk322x-board.c | 18 + board/rockchip/evb_rv1108/evb_rv1108.c | 17 + configs/evb-rk3229_defconfig| 5 + configs/evb-rk3288_defconfig| 1 + configs/evb-rk3328_defconfig| 5 + drivers/clk/rockchip/clk_rk322x.c | 107 + drivers/clk/rockchip/clk_rk3288.c | 106 - drivers/clk/rockchip/clk_rk3328.c | 178 +++ drivers/clk/rockchip/clk_rk3368.c | 91 +++- drivers/net/gmac_rockchip.c | 285 ++- drivers/pinctrl/rockchip/pinctrl_rk322x.c | 601 drivers/pinctrl/rockchip/pinctrl_rk3328.c | 388 +++ drivers/pinctrl/rockchip/pinctrl_rv1108.c | 399 include/dt-bindings/clock/rk3288-cru.h | 1 + include/dt-bindings/clock/rk3328-cru.h | 6 +- 24 files changed, 2270 insertions(+), 1001 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 16/18] clk: rockchip: Add rk322x gamc clock support
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk322x.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk322x.c
b/drivers/clk/rockchip/clk_rk322x.c
index e87267d..5fd27cd 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -239,6 +239,16 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru,
uint clk_general_rate,
return DIV_TO_RATE(src_rate, div) / 2;
}
+static int rk322x_mac_set_clk(struct rk322x_cru *cru,
+ int periph, uint freq)
+{
+ /* Assuming mac_clk is fed by an external clock */
+ rk_clrsetreg(>cru_clksel_con[5], BIT(5),
+BIT(5));
+
+ return 0;
+}
+
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint
clk_general_rate,
int periph, uint freq)
{
@@ -352,6 +362,9 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong
rate)
case CLK_DDR:
new_rate = rk322x_ddr_set_clk(priv->cru, rate);
break;
+ case SCLK_MAC:
+ new_rate = rk322x_mac_set_clk(priv->cru, clk->id, rate);
+ break;
default:
return -ENOENT;
}
--
2.7.4
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[U-Boot] [PATCH v2 15/18] rockchip: pinctrl: Add rk322x gmac pinctrl support
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 138 ++
1 file changed, 138 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c
b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
index 28d9996..956e02f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
@@ -470,6 +470,48 @@ enum {
CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
};
+/* GRF_GPIO2B_E */
+enum {
+ GRF_GPIO2B0_E_SHIFT = 0,
+ GRF_GPIO2B0_E_MASK = GENMASK(1, 0),
+ GRF_GPIO2B1_E_SHIFT = 2,
+ GRF_GPIO2B1_E_MASK = GENMASK(3, 2),
+ GRF_GPIO2B3_E_SHIFT = 6,
+ GRF_GPIO2B3_E_MASK = GENMASK(7, 6),
+ GRF_GPIO2B4_E_SHIFT = 8,
+ GRF_GPIO2B4_E_MASK = GENMASK(9, 8),
+ GRF_GPIO2B5_E_SHIFT = 10,
+ GRF_GPIO2B5_E_MASK = GENMASK(11, 10),
+ GRF_GPIO2B6_E_SHIFT = 12,
+ GRF_GPIO2B6_E_MASK = GENMASK(13, 12),
+};
+
+/* GRF_GPIO2C_E */
+enum {
+ GRF_GPIO2C0_E_SHIFT = 0,
+ GRF_GPIO2C0_E_MASK = GENMASK(1, 0),
+ GRF_GPIO2C1_E_SHIFT = 2,
+ GRF_GPIO2C1_E_MASK = GENMASK(3, 2),
+ GRF_GPIO2C2_E_SHIFT = 4,
+ GRF_GPIO2C2_E_MASK = GENMASK(5, 4),
+ GRF_GPIO2C3_E_SHIFT = 6,
+ GRF_GPIO2C3_E_MASK = GENMASK(7, 6),
+ GRF_GPIO2C4_E_SHIFT = 8,
+ GRF_GPIO2C4_E_MASK = GENMASK(9, 8),
+ GRF_GPIO2C5_E_SHIFT = 10,
+ GRF_GPIO2C5_E_MASK = GENMASK(11, 10),
+ GRF_GPIO2C6_E_SHIFT = 12,
+ GRF_GPIO2C6_E_MASK = GENMASK(13, 12),
+ GRF_GPIO2C7_E_SHIFT = 14,
+ GRF_GPIO2C7_E_MASK = GENMASK(15, 14),
+};
+
+/* GRF_GPIO2D_E */
+enum {
+ GRF_GPIO2D1_E_SHIFT = 2,
+ GRF_GPIO2D1_E_MASK = GENMASK(3, 2),
+};
+
struct rk322x_pinctrl_priv {
struct rk322x_grf *grf;
};
@@ -633,6 +675,95 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf
*grf, int mmc_id)
}
}
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
+{
+ switch (gmac_id) {
+ case PERIPH_ID_GMAC:
+ /* set rgmii pins mux */
+ rk_clrsetreg(>gpio2b_iomux,
+GPIO2B0_MASK |
+GPIO2B1_MASK |
+GPIO2B3_MASK |
+GPIO2B4_MASK |
+GPIO2B5_MASK |
+GPIO2B6_MASK,
+GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
+GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
+GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
+GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
+GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
+GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
+
+ rk_clrsetreg(>gpio2c_iomux,
+GPIO2C0_MASK |
+GPIO2C1_MASK |
+GPIO2C2_MASK |
+GPIO2C3_MASK |
+GPIO2C4_MASK |
+GPIO2C5_MASK |
+GPIO2C6_MASK |
+GPIO2C7_MASK,
+GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
+GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
+GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
+GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
+GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
+GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
+GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
+GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
+
+ rk_clrsetreg(>gpio2d_iomux,
+GPIO2D1_MASK,
+GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
+
+ /*
+* set rgmii tx pins to 12ma drive-strength,
+* clean others with 2ma.
+*/
+ rk_clrsetreg(>gpio2_e[1],
+GRF_GPIO2B0_E_MASK |
+GRF_GPIO2B1_E_MASK |
+GRF_GPIO2B3_E_MASK |
+GRF_GPIO2B4_E_MASK |
+GRF_GPIO2B5_E_MASK |
+GRF_GPIO2B6_E_MASK,
+0x0 << GRF_GPIO2B0_E_SHIFT |
+0x3 << GRF_GPIO2B1_E_SHIFT |
+0x0 << GRF_GPIO2B3_E_SHIFT |
+0x0 << GRF_GPIO2B4_E_SHIFT |
+0x3 << GRF_GPIO2B5_E_SHIFT |
+
[U-Boot] [PATCH v2 14/18] rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver
Spam detection software, running on the system "lists.denx.de",
has identified this incoming email as possible spam. The original
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Content preview: Clean the iomux definitions at grf_rk322x.h, and move them
into pinctrl-driver for resolving the compiling error of redefinition. After
that, define the uart2 iomux at rk322x-board file. Signed-off-by: David Wu
<david...@rock-chips.com> --- [...]
Content analysis details: (6.5 points, 5.0 required)
pts rule name description
-- --
0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL
[211.157.147.133 listed in psbl.surriel.com]
2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5)
[211.157.147.133 listed in bl.mailspike.net]
0.8 UPPERCASE_50_75message body is 50-75% uppercase
0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted
--- Begin Message ---
Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455
arch/arm/mach-rockchip/rk322x-board-spl.c | 20 +-
arch/arm/mach-rockchip/rk322x-board.c | 16 +
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 453 +++
4 files changed, 488 insertions(+), 456 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
index c0c0d84..52e5a0a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
@@ -88,461 +88,6 @@ struct rk322x_sgrf {
unsigned int busdmac_con[4];
};
-/* GRF_GPIO0A_IOMUX */
-enum {
- GPIO0A7_SHIFT = 14,
- GPIO0A7_MASK= 3 << GPIO0A7_SHIFT,
- GPIO0A7_GPIO= 0,
- GPIO0A7_I2C3_SDA,
- GPIO0A7_HDMI_DDCSDA,
-
- GPIO0A6_SHIFT = 12,
- GPIO0A6_MASK= 3 << GPIO0A6_SHIFT,
- GPIO0A6_GPIO= 0,
- GPIO0A6_I2C3_SCL,
- GPIO0A6_HDMI_DDCSCL,
-
- GPIO0A3_SHIFT = 6,
- GPIO0A3_MASK= 3 << GPIO0A3_SHIFT,
- GPIO0A3_GPIO= 0,
- GPIO0A3_I2C1_SDA,
- GPIO0A3_SDIO_CMD,
-
- GPIO0A2_SHIFT = 4,
- GPIO0A2_MASK= 3 << GPIO0A2_SHIFT,
- GPIO0A2_GPIO= 0,
- GPIO0A2_I2C1_SCL,
-
- GPIO0A1_SHIFT = 2,
- GPIO0A1_MASK= 3 << GPIO0A1_SHIFT,
- GPIO0A1_GPIO= 0,
- GPIO0A1_I2C0_SDA,
-
- GPIO0A0_SHIFT = 0,
- GPIO0A0_MASK= 3 << GPIO0A0_SHIFT,
- GPIO0A0_GPIO= 0,
- GPIO0A0_I2C0_SCL,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
- GPIO0B7_SHIFT = 14,
- GPIO0B7_MASK= 3 << GPIO0B7_SHIFT,
- GPIO0B7_GPIO= 0,
- GPIO0B7_HDMI_HDP,
-
- GPIO0B6_SHIFT = 12,
- GPIO0B6_MASK= 3 << GPIO0B6_SHIFT,
- GPIO0B6_GPIO= 0,
- GPIO0B6_I2S_SDI,
- GPIO0B6_SPI_CSN0,
-
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK= 3 << GPIO0B5_SHIFT,
- GPIO0B5_GPIO= 0,
- GPIO0B5_I2S_SDO,
- GPIO0B5_SPI_RXD,
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK= 3 << GPIO0B3_SHIFT,
- GPIO0B3_GPIO= 0,
- GPIO0B3_I2S1_LRCKRX,
- GPIO0B3_SPI_TXD,
-
- GPIO0B1_SHIFT = 2,
- GPIO0B1_MASK= 3 << GPIO0B1_SHIFT,
- GPIO0B1_GPIO= 0,
- GPIO0B1_I2S_SCLK,
- GPIO0B1_SPI_CLK,
-
- GPIO0B0_SHIFT = 0,
- GPIO0B0_MASK= 3,
- GPIO0B0_GPIO= 0,
- GPIO0B0_I2S_MCLK,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK= 3 << GPIO0C4_SHIFT,
- GPIO0C4_GPIO= 0,
- GPIO0C4_HDMI_CECSDA,
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK= 3 << GPIO0C1_SHIFT,
- GPIO0C1_GPIO= 0,
- GPIO0C1_UART0_RSTN,
- GPIO0C1_CLK_OUT1,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK= 3 << GPIO0D6_SHIFT,
- GPIO0D6_GPIO= 0,
- GPIO0D6_SDIO_
[U-Boot] [PATCH v2 13/18] rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb
Add rk3328-evb gmac support.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/dts/rk3328-evb.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 3dd9d81..336c2d5 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -15,6 +15,13 @@
stdout-path =
};
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -40,6 +47,13 @@
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
};
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
{
@@ -74,6 +88,22 @@
status = "okay";
};
+ {
+ phy-supply = <_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = < RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ assigned-clocks = < SCLK_MAC2IO>, < SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <_clkin>, <_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
_host0_ehci {
status = "okay";
};
--
2.7.4
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[U-Boot] [PATCH v2 12/18] rockchip: dts: rk3328: Add gmac2io support
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Content preview: Add basic dts configuration for rk3328 gmac2io. Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v2: - New patch [...]
Content analysis details: (5.7 points, 5.0 required)
pts rule name description
-- --
2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL
[211.157.147.130 listed in psbl.surriel.com]
0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5)
[211.157.147.130 listed in bl.mailspike.net]
0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted
--- Begin Message ---
Add basic dts configuration for rk3328 gmac2io.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/dts/rk3328.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 0bab1e3..5de1059 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -456,6 +456,25 @@
status = "disabled";
};
+ gmac2io: ethernet@ff54 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff54 0x0 0x1>;
+ rockchip,grf = <>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ clocks = < SCLK_MAC2IO>, < SCLK_MAC2IO_RX>,
+< SCLK_MAC2IO_TX>, < SCLK_MAC2IO_REF>,
+< SCLK_MAC2IO_REFOUT>, < ACLK_MAC2IO>,
+< PCLK_MAC2IO>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = < SRST_GMAC2IO_A>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@ff5c {
compatible = "generic-ehci";
reg = <0x0 0xff5c 0x0 0x1>;
--
2.7.4
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[U-Boot] [PATCH v2 11/18] rockchip: configs: Enable GMAC configs for evb-rk3328
Enable GMAC configs for evb-rk3328 Signed-off-by: David Wu <david...@rock-chips.com> --- Changes in v2: - New patch configs/evb-rk3328_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 3b8b104..3d8c04d 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y @@ -24,6 +25,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3328=y CONFIG_DM_PMIC=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 10/18] net: gmac_rockchip: Add rk3328 gmac support
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Content preview: The GMAC2IO in the RK3328 once again is identical to the
incarnation
in the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF. This adds the RK3328-specific
logic necessary to reuse this driver. [...]
Content analysis details: (5.7 points, 5.0 required)
pts rule name description
-- --
2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL
[211.157.147.134 listed in psbl.surriel.com]
0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5)
[211.157.147.134 listed in bl.mailspike.net]
0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted
--- Begin Message ---
The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3328-specific logic necessary to reuse this driver.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/net/gmac_rockchip.c | 85 +
1 file changed, 85 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 22e3941..f24c347 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -86,6 +87,39 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
+static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk3328_grf_regs *grf;
+ int clk;
+ enum {
+ RK3328_GMAC_CLK_SEL_SHIFT = 11,
+ RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
+ RK3328_GMAC_CLK_SEL_125M = 0 << 11,
+ RK3328_GMAC_CLK_SEL_25M = 3 << 11,
+ RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3328_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3328_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3328_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct rk3368_grf *grf;
@@ -199,6 +233,50 @@ static void rk3288_gmac_set_to_rgmii(struct
gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_RMII_MODE_SHIFT = 9,
+ RK3328_RMII_MODE_MASK = BIT(9),
+
+ RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>mac_con[1],
+RK3328_RMII_MODE_MASK |
+RK3328_GMAC_PHY_INTF_SEL_MASK |
+RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+RK3328_TXCLK_DLY_ENA_GMAC_MASK,
+RK3328_GMAC_PHY_INTF_SEL_RGMII |
+RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+ rk_clrsetreg(>mac_con[0],
+RK3328_CLK_RX_DL_CFG_GMAC_MASK |
+
[U-Boot] [PATCH v2 09/18] clk: rockchip: Add rk3328 gamc clock support
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk3328.c | 20
include/dt-bindings/clock/rk3328-cru.h | 6 +++---
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index 540d910..0940474 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -393,6 +394,22 @@ static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru,
ulong clk_id, uint hz)
return DIV_TO_RATE(GPLL_HZ, src_clk_div);
}
+static int rockchip_mac_set_clk(struct rk3328_cru *cru,
+ int periph, uint freq)
+{
+ struct rk3328_grf_regs *grf;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ /* Assuming mac_clk is fed by an external clock */
+ rk_clrsetreg(>soc_con[4], BIT(14),
+BIT(14));
+
+ rk_clrsetreg(>mac_con[1], BIT(10),
+BIT(10));
+
+ return 0;
+}
+
static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
{
u32 div, con, con_id;
@@ -558,6 +575,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong
rate)
case SCLK_I2C3:
ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
break;
+ case SCLK_MAC2IO:
+ ret = rockchip_mac_set_clk(priv->cru, clk->id, rate);
+ break;
case SCLK_PWM:
ret = rk3328_pwm_set_clk(priv->cru, rate);
break;
diff --git a/include/dt-bindings/clock/rk3328-cru.h
b/include/dt-bindings/clock/rk3328-cru.h
index 6d8bf13..cdc0b33 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -86,6 +86,9 @@
#define SCLK_USB3OTG_SUSPEND 97
#define SCLK_REF_USB3OTG_SRC 98
#define SCLK_MAC2IO_SRC99
+#define SCLK_MAC2IO100
+#define SCLK_MAC2PHY 101
+#define SCLK_MAC2IO_EXT102
/* dclk gates */
#define DCLK_LCDC 180
@@ -199,9 +202,6 @@
#define CLK_NR_CLKS(HCLK_HDCP + 1)
-#define SCLK_MAC2IO0
-#define SCLK_MAC2PHY 1
-
#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
/* soft-reset indices */
--
2.7.4
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[U-Boot] [PATCH v2 08/18] rockchip: pinctrl: Add rk3328 gmac pinctrl support
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
and bit10 at com iomux register. After that, set rgmii m1 tx
pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 236 ++
1 file changed, 236 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index 0042025..c155027 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -72,6 +72,69 @@ enum {
GPIO1A0_SEL_MASK= 0x3fff << GPIO1A0_SEL_SHIFT,
GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
+ /* GPIO1B_IOMUX */
+ GPIO1B0_SEL_SHIFT = 0,
+ GPIO1B0_SEL_MASK= GENMASK(1, 0),
+ GPIO1B0_GMAC_TXD1M1 = 2,
+
+ GPIO1B1_SEL_SHIFT = 2,
+ GPIO1B1_SEL_MASK= GENMASK(3, 2),
+ GPIO1B1_GMAC_TXD0M1 = 2,
+
+ GPIO1B2_SEL_SHIFT = 4,
+ GPIO1B2_SEL_MASK= GENMASK(5, 4),
+ GPIO1B2_GMAC_RXD1M1 = 2,
+
+ GPIO1B3_SEL_SHIFT = 6,
+ GPIO1B3_SEL_MASK= GENMASK(7, 6),
+ GPIO1B3_GMAC_RXD0M1 = 2,
+
+ GPIO1B4_SEL_SHIFT = 8,
+ GPIO1B4_SEL_MASK= GENMASK(9, 8),
+ GPIO1B4_GMAC_TXCLKM1= 2,
+
+ GPIO1B5_SEL_SHIFT = 10,
+ GPIO1B5_SEL_MASK= GENMASK(11, 10),
+ GPIO1B5_GMAC_RXCLKM1= 2,
+
+ GPIO1B6_SEL_SHIFT = 12,
+ GPIO1B6_SEL_MASK= GENMASK(13, 12),
+ GPIO1B6_GMAC_RXD3M1 = 2,
+
+ GPIO1B7_SEL_SHIFT = 14,
+ GPIO1B7_SEL_MASK= GENMASK(15, 14),
+ GPIO1B7_GMAC_RXD2M1 = 2,
+
+ /* GPIO1C_IOMUX */
+ GPIO1C0_SEL_SHIFT = 0,
+ GPIO1C0_SEL_MASK= GENMASK(1, 0),
+ GPIO1C0_GMAC_TXD3M1 = 2,
+
+ GPIO1C1_SEL_SHIFT = 2,
+ GPIO1C1_SEL_MASK= GENMASK(3, 2),
+ GPIO1C1_GMAC_TXD2M1 = 2,
+
+ GPIO1C3_SEL_SHIFT = 6,
+ GPIO1C3_SEL_MASK= GENMASK(7, 6),
+ GPIO1C3_GMAC_MDIOM1 = 2,
+
+ GPIO1C5_SEL_SHIFT = 10,
+ GPIO1C5_SEL_MASK= GENMASK(11, 10),
+ GPIO1C5_GMAC_CLKM1 = 2,
+
+ GPIO1C6_SEL_SHIFT = 12,
+ GPIO1C6_SEL_MASK= GENMASK(13, 12),
+ GPIO1C6_GMAC_RXDVM1 = 2,
+
+ GPIO1C7_SEL_SHIFT = 14,
+ GPIO1C7_SEL_MASK= GENMASK(15, 14),
+ GPIO1C7_GMAC_MDCM1 = 2,
+
+ /* GPIO1D_IOMUX */
+ GPIO1D1_SEL_SHIFT = 2,
+ GPIO1D1_SEL_MASK= GENMASK(3, 2),
+ GPIO1D1_GMAC_TXENM1 = 2,
+
/* GPIO2A_IOMUX */
GPIO2A0_SEL_SHIFT = 0,
GPIO2A0_SEL_MASK= 3 << GPIO2A0_SEL_SHIFT,
@@ -149,6 +212,11 @@ enum {
IOMUX_SEL_UART2_M0 = 0,
IOMUX_SEL_UART2_M1,
+ IOMUX_SEL_GMAC_SHIFT= 2,
+ IOMUX_SEL_GMAC_MASK = BIT(2),
+ IOMUX_SEL_GMAC_M0 = 0,
+ IOMUX_SEL_GMAC_M1,
+
IOMUX_SEL_SPI_SHIFT = 4,
IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
IOMUX_SEL_SPI_M0= 0,
@@ -159,6 +227,47 @@ enum {
IOMUX_SEL_SDMMC_MASK= 1 << IOMUX_SEL_SDMMC_SHIFT,
IOMUX_SEL_SDMMC_M0 = 0,
IOMUX_SEL_SDMMC_M1,
+
+ IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = BIT(10),
+ IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE= 0,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER,
+
+ /* GRF_GPIO1B_E */
+ GRF_GPIO1B0_E_SHIFT = 0,
+ GRF_GPIO1B0_E_MASK = GENMASK(1, 0),
+ GRF_GPIO1B1_E_SHIFT = 2,
+ GRF_GPIO1B1_E_MASK = GENMASK(3, 2),
+ GRF_GPIO1B2_E_SHIFT = 4,
+ GRF_GPIO1B2_E_MASK = GENMASK(5, 4),
+ GRF_GPIO1B3_E_SHIFT = 6,
+ GRF_GPIO1B3_E_MASK = GENMASK(7, 6),
+ GRF_GPIO1B4_E_SHIFT = 8,
+ GRF_GPIO1B4_E_MASK = GENMASK(9, 8),
+ GRF_GPIO1B5_E_SHIFT = 10,
+ GRF_GPIO1B5_E_MASK = GENMASK(11, 10),
+ GRF_GPIO1B6_E_SHIFT = 12,
+ GRF_GPIO1B6_E_MASK = GENMASK(13, 12),
+ GRF_GPIO1B7_E_SHIFT = 14,
+ GRF_GPIO1B7_E_MASK = GENMASK(15, 14),
+
+ /* GRF_GPIO1C_E */
+ GRF_GPIO1C0_E_SHIFT = 0,
+ GRF_GPIO1C0_E_MASK = GENMASK(1, 0),
+ GRF_GPIO1C1_E_SHIFT = 2,
+ GRF_GPIO1C1_E_MASK = GENMASK(3, 2),
+ GRF_GPIO1C3_E_SHIFT = 6,
+ GRF_GPIO1C3_E_MASK = GENMASK(7, 6),
+ GRF_GPIO1C5_E_SHIFT = 10,
+ GRF_GPIO1C5_E_MASK = GENMASK(11, 10),
+ GRF_GPIO1C6_E_SHIFT = 12,
+ GRF_GPIO1C6_E_MASK = GENMASK(13, 12),
+ GRF_GPIO1C7_E_SHIFT = 14,
+ GRF_GPIO1C7_E_MASK = GENMASK(15, 14),
+
+ /* GRF_GPIO1D_E */
+ GRF_GPIO1D1_E_SHIFT = 2,
+ GRF_GPIO1D1_E_MASK = GENMASK(3, 2),
};
struct rk3328_pinctrl_priv {
@@ -344,6 +453,124 @@ static void pinctrl_rk3328_sdmmc_confi
[U-Boot] [PATCH v2 07/18] rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver
Spam detection software, running on the system "lists.denx.de",
has identified this incoming email as possible spam. The original
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@@CONTACT_ADDRESS@@ for details.
Content preview: Clean the iomux definitions at grf_rk3328.h, and move them
into pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v2: - New patch [...]
Content analysis details: (6.5 points, 5.0 required)
pts rule name description
-- --
0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL
[211.157.147.134 listed in psbl.surriel.com]
2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5)
[211.157.147.134 listed in bl.mailspike.net]
0.8 UPPERCASE_50_75message body is 50-75% uppercase
0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted
--- Begin Message ---
Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113 ---
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 144
2 files changed, 144 insertions(+), 113 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index f0a0781..0c37f2a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -131,118 +131,5 @@ struct rk3328_sgrf_regs {
};
check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
-enum {
- /* GPIO0A_IOMUX */
- GPIO0A5_SEL_SHIFT = 10,
- GPIO0A5_SEL_MASK= 3 << GPIO0A5_SEL_SHIFT,
- GPIO0A5_I2C3_SCL= 2,
-
- GPIO0A6_SEL_SHIFT = 12,
- GPIO0A6_SEL_MASK= 3 << GPIO0A6_SEL_SHIFT,
- GPIO0A6_I2C3_SDA= 2,
-
- GPIO0A7_SEL_SHIFT = 14,
- GPIO0A7_SEL_MASK= 3 << GPIO0A7_SEL_SHIFT,
- GPIO0A7_EMMC_DATA0 = 2,
-
- /* GPIO0D_IOMUX*/
- GPIO0D6_SEL_SHIFT = 12,
- GPIO0D6_SEL_MASK= 3 << GPIO0D6_SEL_SHIFT,
- GPIO0D6_GPIO= 0,
- GPIO0D6_SDMMC0_PWRENM1 = 3,
-
- /* GPIO1A_IOMUX */
- GPIO1A0_SEL_SHIFT = 0,
- GPIO1A0_SEL_MASK= 0x3fff << GPIO1A0_SEL_SHIFT,
- GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
-
- /* GPIO2A_IOMUX */
- GPIO2A0_SEL_SHIFT = 0,
- GPIO2A0_SEL_MASK= 3 << GPIO2A0_SEL_SHIFT,
- GPIO2A0_UART2_TX_M1 = 1,
-
- GPIO2A1_SEL_SHIFT = 2,
- GPIO2A1_SEL_MASK= 3 << GPIO2A1_SEL_SHIFT,
- GPIO2A1_UART2_RX_M1 = 1,
-
- GPIO2A2_SEL_SHIFT = 4,
- GPIO2A2_SEL_MASK= 3 << GPIO2A2_SEL_SHIFT,
- GPIO2A2_PWM_IR = 1,
-
- GPIO2A4_SEL_SHIFT = 8,
- GPIO2A4_SEL_MASK= 3 << GPIO2A4_SEL_SHIFT,
- GPIO2A4_PWM_0 = 1,
- GPIO2A4_I2C1_SDA,
-
- GPIO2A5_SEL_SHIFT = 10,
- GPIO2A5_SEL_MASK= 3 << GPIO2A5_SEL_SHIFT,
- GPIO2A5_PWM_1 = 1,
- GPIO2A5_I2C1_SCL,
-
- GPIO2A6_SEL_SHIFT = 12,
- GPIO2A6_SEL_MASK= 3 << GPIO2A6_SEL_SHIFT,
- GPIO2A6_PWM_2 = 1,
-
- GPIO2A7_SEL_SHIFT = 14,
- GPIO2A7_SEL_MASK= 3 << GPIO2A7_SEL_SHIFT,
- GPIO2A7_GPIO= 0,
- GPIO2A7_SDMMC0_PWRENM0,
-
- /* GPIO2BL_IOMUX */
- GPIO2BL0_SEL_SHIFT = 0,
- GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
- GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
-
- GPIO2BL3_SEL_SHIFT = 6,
- GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
- GPIO2BL3_SPI_CSN0_M0= 1,
-
- GPIO2BL4_SEL_SHIFT = 8,
- GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
- GPIO2BL4_SPI_CSN1_M0= 1,
-
- GPIO2BL5_SEL_SHIFT = 10,
- GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
- GPIO2BL5_I2C2_SDA = 1,
-
- GPIO2BL6_SEL_SHIFT = 12,
- GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
- GPIO2BL6_I2C2_SCL = 1,
-
- /* GPIO2D_IOMUX */
- GPIO2D0_SEL_SHIFT = 0,
- GPIO2D0_SEL_MASK= 3 << GPIO2D0_SEL_SHIFT,
- GPIO2D0_I2C0_SCL= 1,
-
- GPIO2D1_SEL_SHIFT = 2,
- GPIO2D1_SEL_MASK= 3 <&l
[U-Boot] [PATCH v2 06/18] net: gmac_rockchip: Add support for the RV1108 GMAC
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Use current phy interface to set mac clock rate
- Clean the grf offset at gmac_rockchip.c
drivers/net/gmac_rockchip.c | 89 +
1 file changed, 82 insertions(+), 7 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 586ccbf..22e3941 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include "designware.h"
@@ -37,6 +38,7 @@ struct gmac_rockchip_platdata {
struct rk_gmac_ops {
int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -142,6 +144,41 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
+static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+{
+ struct rv1108_grf *grf;
+ int clk, speed;
+ enum {
+ RV1108_GMAC_SPEED_MASK = BIT(2),
+ RV1108_GMAC_SPEED_10M = 0 << 2,
+ RV1108_GMAC_SPEED_100M = 1 << 2,
+ RV1108_GMAC_CLK_SEL_MASK= BIT(7),
+ RV1108_GMAC_CLK_SEL_2_5M= 0 << 7,
+ RV1108_GMAC_CLK_SEL_25M = 1 << 7,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RV1108_GMAC_CLK_SEL_2_5M;
+ speed = RV1108_GMAC_SPEED_10M;
+ break;
+ case 100:
+ clk = RV1108_GMAC_CLK_SEL_25M;
+ speed = RV1108_GMAC_SPEED_100M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>gmac_con0,
+RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
+clk | speed);
+
+ return 0;
+}
+
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3288_grf *grf;
@@ -221,11 +258,28 @@ static void rk3399_gmac_set_to_rgmii(struct
gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rv1108_grf *grf;
+
+ enum {
+ RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(>gmac_con0,
+RV1108_GMAC_PHY_INTF_SEL_MASK,
+RV1108_GMAC_PHY_INTF_SEL_RMII);
+}
+
static int gmac_rockchip_probe(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = _pdata->eth_pdata;
struct clk clk;
int ret;
@@ -233,13 +287,27 @@ static int gmac_rockchip_probe(struct udevice *dev)
if (ret)
return ret;
- /* Since mac_clk is fed by an external clock we can use 0 here */
- ret = clk_set_rate(, 0);
- if (ret)
- return ret;
-
- /* Set to RGMII mode */
- ops->set_to_rgmii(pdata);
+ switch (eth_pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ret = clk_set_rate(, 12500);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ /* Set to RGMII mode */
+ if (ops->set_to_rgmii)
+ ops->set_to_rgmii(pdata);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ ret = clk_set_rate(, 5000);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ /* Set to RMII mode */
+ if (ops->set_to_rmii)
+ ops->set_to_rmii(pdata);
+ break;
+ default:
+ debug("NO interface defined!\n");
+ return -ENXIO;
+ }
return designware_eth_probe(dev);
}
@@ -289,6 +357,11 @@ const struct rk_gmac_ops rk3399_gmac_ops = {
.set_to_rgmii = rk3399_gmac_set_to_rgmii,
};
+const struct rk_gmac_ops
[U-Boot] [PATCH v2 05/18] rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver
Spam detection software, running on the system "lists.denx.de",
has identified this incoming email as possible spam. The original
message has been attached to this so you can view it or label
similar future email. If you have any questions, see
@@CONTACT_ADDRESS@@ for details.
Content preview: If we include both the rk3288_grf.h and rv1108_grf.h, it will
cause the conflicts of redefinition. Clean the iomux definitions at
grf_rv1108.h,
and move them into pinctrl-driver. Signed-off-by: David Wu
<david...@rock-chips.com>
--- [...]
Content analysis details: (6.5 points, 5.0 required)
pts rule name description
-- --
2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL
[211.157.147.130 listed in psbl.surriel.com]
0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5)
[211.157.147.130 listed in bl.mailspike.net]
0.8 UPPERCASE_50_75message body is 50-75% uppercase
0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted
--- Begin Message ---
If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
and move them into pinctrl-driver.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 399
board/rockchip/evb_rv1108/evb_rv1108.c | 15 +
drivers/pinctrl/rockchip/pinctrl_rv1108.c | 399
3 files changed, 414 insertions(+), 399 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index 428cf6a..76e742b 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -111,403 +111,4 @@ struct rv1108_grf {
};
check_member(rv1108_grf, chip_id, 0x0c00);
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK= 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO= 0,
- GPIO1B7_LCDC_D12,
- GPIO1B7_I2S_SDIO2_M0,
- GPIO1B7_GMAC_RXDV,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK= 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO= 0,
- GPIO1B6_LCDC_D13,
- GPIO1B6_I2S_LRCLKTX_M0,
- GPIO1B6_GMAC_RXD1,
-
- GPIO1B5_SHIFT = 10,
- GPIO1B5_MASK= 3 << GPIO1B5_SHIFT,
- GPIO1B5_GPIO= 0,
- GPIO1B5_LCDC_D14,
- GPIO1B5_I2S_SDIO1_M0,
- GPIO1B5_GMAC_RXD0,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK= 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO= 0,
- GPIO1B4_LCDC_D15,
- GPIO1B4_I2S_MCLK_M0,
- GPIO1B4_GMAC_TXEN,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK= 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO= 0,
- GPIO1B3_LCDC_D16,
- GPIO1B3_I2S_SCLK_M0,
- GPIO1B3_GMAC_TXD1,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK= 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO= 0,
- GPIO1B2_LCDC_D17,
- GPIO1B2_I2S_SDIO_M0,
- GPIO1B2_GMAC_TXD0,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK= 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO= 0,
- GPIO1B1_LCDC_D9,
- GPIO1B1_PWM7,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK= 3,
- GPIO1B0_GPIO= 0,
- GPIO1B0_LCDC_D8,
- GPIO1B0_PWM6,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK= 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO= 0,
- GPIO1C7_CIF_D5,
- GPIO1C7_I2S_SDIO2_M1,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK= 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO= 0,
- GPIO1C6_CIF_D4,
- GPIO1C6_I2S_LRCLKTX_M1,
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK= 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO= 0,
- GPIO1C5_LCDC_CLK,
- GPIO1C5_GMAC_CLK,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK= 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO= 0,
- GPIO1C4_LCDC_HSYNC,
- GPIO1C4_GMAC_MDC,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK= 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO= 0,
- GPIO1C3_LCDC_VSYNC,
- GPIO1C3_GMAC_MDIO,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK= 3 << GPIO1C2_SHIFT,
- GPIO1C2_GPIO= 0,
-
[U-Boot] [PATCH v2 04/18] rockchip: grf_rv1108.h: Fix the grf offsets
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index c816a5b..428cf6a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -100,13 +100,17 @@ struct rv1108_grf {
u32 reserved14[2];
u32 dma_con0;
u32 dma_con1;
- u32 reserved15[539];
+ u32 reserved15[59];
u32 uoc_status;
+ u32 reserved16[2];
u32 host_status;
+ u32 reserved17[59];
u32 gmac_con0;
+ u32 reserved18[191];
u32 chip_id;
};
-check_member(rv1108_grf, chip_id, 0xf90);
+
+check_member(rv1108_grf, chip_id, 0x0c00);
/* GRF_GPIO1B_IOMUX */
enum {
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 03/18] rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb
If the Ethernet address is not set, the network can't work, enable the random address config for default use. Signed-off-by: David Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> --- Changes in v2: None configs/evb-rk3288_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index e944f97..6c67509 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 02/18] rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality
Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Give the mac controller the correct tx-delay and rx-delay value for the rgmii mode transmission. If they are not matched, there would be Ethernet packets lost, the net feature may not work. Signed-off-by: David Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> --- [...] Content analysis details: (5.7 points, 5.0 required) pts rule name description -- -- 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.130 listed in psbl.surriel.com] 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.130 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted --- Begin Message --- Give the mac controller the correct tx-delay and rx-delay value for the rgmii mode transmission. If they are not matched, there would be Ethernet packets lost, the net feature may not work. Signed-off-by: David Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> --- Changes in v2: None arch/arm/dts/rk3399-evb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 0e5d8d7..ed5ef88 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -276,7 +276,7 @@ assigned-clock-parents = <_gmac>; pinctrl-names = "default"; pinctrl-0 = <_pins>; - tx_delay = <0x10>; - rx_delay = <0x10>; + tx_delay = <0x28>; + rx_delay = <0x11>; status = "okay"; }; -- 2.7.4 --- End Message --- ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 01/18] rockchip: clk: Add mac clock set for rk3399
Spam detection software, running on the system "lists.denx.de",
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Content preview: Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface. Signed-off-by:
David Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich
<philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> ---
[...]
Content analysis details: (5.7 points, 5.0 required)
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-- --
0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
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[211.157.147.130 listed in psbl.surriel.com]
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--- Begin Message ---
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v2: None
drivers/clk/rockchip/clk_rk3399.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index 6f85a38..93aa4ff 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -143,6 +143,14 @@ enum {
ACLK_PERIHP_DIV_CON_SHIFT = 0,
ACLK_PERIHP_DIV_CON_MASK= 0x1f,
+ /* CLKSEL_CON19 */
+ MAC_DIV_CON_SHIFT = 8,
+ MAC_DIV_CON_MASK= GENMASK(10, 8),
+ RMII_EXTCLK_SHIFT = 4,
+ RMII_EXTCLK_MASK= BIT(4),
+ RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+ RMII_EXTCLK_SELECT_EXT_CLK = BIT(4),
+
/* CLKSEL_CON21 */
ACLK_EMMC_PLL_SEL_SHIFT = 7,
ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
@@ -785,6 +793,16 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
return set_rate;
}
+static int rockchip_mac_set_clk(struct rk3399_cru *cru,
+ int periph, uint freq)
+{
+ /* Assuming mac_clk is fed by an external clock */
+ rk_clrsetreg(>clksel_con[19], RMII_EXTCLK_MASK,
+RMII_EXTCLK_SELECT_EXT_CLK);
+
+ return 0;
+}
+
static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
{
u32 div, val;
@@ -869,8 +887,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong
rate)
ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_MAC:
- /* nothing to do, as this is an external clock */
- ret = rate;
+ ret = rockchip_mac_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_I2C1:
case SCLK_I2C2:
--
2.7.4
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[U-Boot] [PATCH v2 00/18] Add gmac support for rk3399-evb rv1108-evb rk3328-evb and rk3229-evb
This serie of patches add rmii interface support, and support more socs's gmac function, such as rv1108, rk3328 and rk3229. Changes in v2: - New patch - New patch - Add check whether the set rgmii/rmii function is a valid function pointer - Use current phy interface to set mac clock rate - Clean the grf offset at gmac_rockchip.c - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch David Wu (18): rockchip: clk: Add mac clock set for rk3399 rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb rockchip: grf_rv1108.h: Fix the grf offsets rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver net: gmac_rockchip: Add support for the RV1108 GMAC rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver rockchip: pinctrl: Add rk3328 gmac pinctrl support clk: rockchip: Add rk3328 gamc clock support net: gmac_rockchip: Add rk3328 gmac support rockchip: configs: Enable GMAC configs for evb-rk3328 rockchip: dts: rk3328: Add gmac2io support rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver rockchip: pinctrl: Add rk322x gmac pinctrl support clk: rockchip: Add rk322x gamc clock support net: gmac_rockchip: Add support for the RK3228 GMAC config: evb-rk3229: Enable rk gmac configs arch/arm/dts/rk3328-evb.dts | 30 ++ arch/arm/dts/rk3328.dtsi| 19 + arch/arm/dts/rk3399-evb.dts | 4 +- arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 -- arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113 - arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 405 +--- arch/arm/mach-rockchip/rk322x-board-spl.c | 20 +- arch/arm/mach-rockchip/rk322x-board.c | 16 + board/rockchip/evb_rv1108/evb_rv1108.c | 15 + configs/evb-rk3229_defconfig| 5 + configs/evb-rk3288_defconfig| 1 + configs/evb-rk3328_defconfig| 5 + drivers/clk/rockchip/clk_rk322x.c | 13 + drivers/clk/rockchip/clk_rk3328.c | 20 + drivers/clk/rockchip/clk_rk3399.c | 21 +- drivers/net/gmac_rockchip.c | 259 ++- drivers/pinctrl/rockchip/pinctrl_rk322x.c | 591 drivers/pinctrl/rockchip/pinctrl_rk3328.c | 380 +++ drivers/pinctrl/rockchip/pinctrl_rv1108.c | 399 include/dt-bindings/clock/rk3328-cru.h | 6 +- 20 files changed, 1794 insertions(+), 983 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 6/6] rockchip: gmac_rockchip: Add gmac support for rv1108
The rv1108 mac only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 67 +++--
1 file changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 26f7a96..16b8c2b 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -37,6 +37,7 @@ struct gmac_rockchip_platdata {
struct rk_gmac_ops {
int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv);
+ void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -177,6 +178,40 @@ static int rk3399_gmac_fix_mac_speed(struct
gmac_rockchip_platdata *pdata,
return 0;
}
+static int rv1108_set_rmii_speed(struct gmac_rockchip_platdata *pdata,
+struct dw_eth_dev *priv)
+{
+ int clk, speed;
+ enum {
+ RV1108_GMAC_SPEED_MASK = BIT(2),
+ RV1108_GMAC_SPEED_10M = 0 << 2,
+ RV1108_GMAC_SPEED_100M = 1 << 2,
+ RV1108_GMAC_CLK_SEL_MASK= BIT(7),
+ RV1108_GMAC_CLK_SEL_2_5M= 0 << 7,
+ RV1108_GMAC_CLK_SEL_25M = 1 << 7,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RV1108_GMAC_CLK_SEL_2_5M;
+ speed = RV1108_GMAC_SPEED_10M;
+ break;
+ case 100:
+ clk = RV1108_GMAC_CLK_SEL_25M;
+ speed = RV1108_GMAC_SPEED_100M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ rk_clrsetreg(pdata->grf,
+RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
+clk | speed);
+
+ return 0;
+}
+
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;
@@ -292,6 +327,18 @@ static void rk3399_gmac_set_to_rgmii(struct
gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ enum {
+ RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
+ };
+
+ rk_clrsetreg(pdata->grf,
+RV1108_GMAC_PHY_INTF_SEL_MASK,
+RV1108_GMAC_PHY_INTF_SEL_RMII);
+}
+
static int gmac_rockchip_probe(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
@@ -325,8 +372,12 @@ static int gmac_rockchip_probe(struct udevice *dev)
pdata->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF) +
data->grf_offset;
- /* Set to RGMII mode */
- ops->set_to_rgmii(pdata);
+ if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII)
+ ops->set_to_rgmii(pdata);
+ else if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ ops->set_to_rmii(pdata);
+ else
+ debug("NO interface defined!\n");
return designware_eth_probe(dev);
}
@@ -392,6 +443,16 @@ const struct gmac_rockchip_driver_data rk3399_gmac_data = {
.grf_offset = 0xc214,
};
+const struct rk_gmac_ops rv1108_gmac_ops = {
+ .fix_mac_speed = rv1108_set_rmii_speed,
+ .set_to_rmii = rv1108_gmac_set_to_rmii,
+};
+
+const struct gmac_rockchip_driver_data rv1108_gmac_data = {
+ .ops= _gmac_ops,
+ .grf_offset = 0x900,
+};
+
static const struct udevice_id rockchip_gmac_ids[] = {
{ .compatible = "rockchip,rk3288-gmac",
.data = (ulong)_gmac_data },
@@ -399,6 +460,8 @@ static const struct udevice_id rockchip_gmac_ids[] = {
.data = (ulong)_gmac_data },
{ .compatible = "rockchip,rk3399-gmac",
.data = (ulong)_gmac_data },
+ { .compatible = "rockchip,rv1108-gmac",
+ .data = (ulong)_gmac_data },
{ }
};
--
2.7.4
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[U-Boot] [PATCH 5/6] net: gmac_rockchip: Use the proerty of "clock_in_out" to set mac clock
If the mac clock if from the external IO, set clock rate with 0;
If the mac clock if from the internal divider pll, set 50M for
rmii mode and set 125M for rgmii.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 5f8f0cd..26f7a96 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct gmac_rockchip_platdata {
struct dw_eth_pdata dw_eth_pdata;
void *grf;
+ int clk_in;
int tx_delay;
int rx_delay;
};
@@ -64,6 +65,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ pdata->clk_in = dev_read_u32_default(dev, "clock_in_out", 1);
+
/* Check the new naming-style first... */
pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
@@ -294,6 +297,8 @@ static int gmac_rockchip_probe(struct udevice *dev)
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
struct gmac_rockchip_driver_data *data =
(struct gmac_rockchip_driver_data *)dev_get_driver_data(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = _pdata->eth_pdata;
const struct rk_gmac_ops *ops = data->ops;
struct clk clk;
int ret;
@@ -302,10 +307,20 @@ static int gmac_rockchip_probe(struct udevice *dev)
if (ret)
return ret;
- /* Since mac_clk is fed by an external clock we can use 0 here */
- ret = clk_set_rate(, 0);
- if (ret)
- return ret;
+ if (pdata->clk_in) {
+ /*
+* Since mac_clk is fed by an external clock
+* we can use 0 here.
+*/
+ ret = clk_set_rate(, 0);
+ if (ret)
+ return ret;
+ } else {
+ if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII)
+ clk_set_rate(, 12500);
+ else
+ clk_set_rate(, 5000);
+ }
pdata->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF) +
data->grf_offset;
--
2.7.4
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[U-Boot] [PATCH 2/6] rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality
Give the mac controller the correct tx-delay and rx-delay value for the rgmii mode transmission. If they are not matched, there would be Ethernet packets lost, the net feature may not work. Signed-off-by: David Wu <david...@rock-chips.com> --- arch/arm/dts/rk3399-evb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index be0c6d9..13958b8 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -272,7 +272,7 @@ assigned-clock-parents = <_gmac>; pinctrl-names = "default"; pinctrl-0 = <_pins>; - tx_delay = <0x10>; - rx_delay = <0x10>; + tx_delay = <0x28>; + rx_delay = <0x11>; status = "okay"; }; -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/6] rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb
If the Ethernet address is not set, the network can't work, enable the random address config for default use. Signed-off-by: David Wu <david...@rock-chips.com> --- configs/evb-rk3288_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index f09b769..461bd3e 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/6] net: gmac_rockchip: Define the gmac grf register struct at gmac_rockchip.c
If we include both the rk3288_grf.h and rv1108_grf.h, there is a
number of compiling error for redefinition. So we define the reg
structs of mac_grf at gmac_rockchip.c. Remove the rk**_grf.h files,
give them own grf offset for their use.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 144 +++-
1 file changed, 116 insertions(+), 28 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 586ccbf..5f8f0cd 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -15,9 +15,6 @@
#include
#include
#include
-#include
-#include
-#include
#include
#include
#include "designware.h"
@@ -31,15 +28,37 @@ DECLARE_GLOBAL_DATA_PTR;
*/
struct gmac_rockchip_platdata {
struct dw_eth_pdata dw_eth_pdata;
+ void *grf;
int tx_delay;
int rx_delay;
};
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata,
+struct dw_eth_dev *priv);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
+struct gmac_rockchip_driver_data {
+ const struct rk_gmac_ops *ops;
+ unsigned int grf_offset;
+};
+
+struct rk3288_mac_grf {
+ u32 soc_con1;
+ u32 reserved;
+ u32 soc_con3;
+};
+
+struct rk3368_mac_grf {
+ u32 soc_con15;
+ u32 soc_con16;
+};
+
+struct rk3399_mac_grf {
+ u32 soc_con5;
+ u32 soc_con6;
+};
static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
{
@@ -58,10 +77,18 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
+struct dw_eth_dev *priv)
{
- struct rk3288_grf *grf;
+ struct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;
int clk;
+ enum {
+ RK3288_GMAC_CLK_SEL_SHIFT = 12,
+ RK3288_GMAC_CLK_SEL_MASK = GENMASK(13, 12),
+ RK3288_GMAC_CLK_SEL_125M = 0 << 12,
+ RK3288_GMAC_CLK_SEL_25M = 3 << 12,
+ RK3288_GMAC_CLK_SEL_2_5M = 2 << 12,
+ };
switch (priv->phydev->speed) {
case 10:
@@ -78,15 +105,15 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return -EINVAL;
}
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrsetreg(>soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
return 0;
}
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
+struct dw_eth_dev *priv)
{
- struct rk3368_grf *grf;
+ struct rk3368_mac_grf *grf = (struct rk3368_mac_grf *)pdata->grf;
int clk;
enum {
RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
@@ -110,16 +137,22 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return -EINVAL;
}
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrsetreg(>soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
return 0;
}
-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,
+struct dw_eth_dev *priv)
{
- struct rk3399_grf_regs *grf;
+ struct rk3399_mac_grf *grf = (struct rk3399_mac_grf *)pdata->grf;
int clk;
+ enum {
+ RK3399_GMAC_CLK_SEL_MASK = GENMASK(6, 4),
+ RK3399_GMAC_CLK_SEL_125M = 0 << 4,
+ RK3399_GMAC_CLK_SEL_25M = 3 << 4,
+ RK3399_GMAC_CLK_SEL_2_5M = 2 << 4,
+ };
switch (priv->phydev->speed) {
case 10:
@@ -136,7 +169,6 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return -EINVAL;
}
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrsetreg(>soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
return 0;
@@ -144,9 +176,31 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
- struct rk3288_grf *grf;
+ struct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;
+ enum {
+ RK3288_RMII_MODE_SHIFT = 14,
+ RK3288_RMII_MODE_MASK = BIT(14),
+
+ RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
+ RK3288_GMAC_PHY_INTF_SEL_MASK = GENMASK(8, 6),
+ RK3288_GMAC_PHY_INTF_SEL_RGMII = BIT(6),
+ };
+ enum {
+ RK32
[U-Boot] [PATCH 1/6] rockchip: clk: Add mac clock set for rk3399
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3399.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index 105c499..03d7518 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -143,6 +143,14 @@ enum {
ACLK_PERIHP_DIV_CON_SHIFT = 0,
ACLK_PERIHP_DIV_CON_MASK= 0x1f,
+ /* CLKSEL_CON19 */
+ MAC_DIV_CON_SHIFT = 8,
+ MAC_DIV_CON_MASK= GENMASK(10, 8),
+ RMII_EXTCLK_SHIFT = 4,
+ RMII_EXTCLK_MASK= BIT(4),
+ RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+ RMII_EXTCLK_SELECT_EXT_CLK = BIT(4),
+
/* CLKSEL_CON21 */
ACLK_EMMC_PLL_SEL_SHIFT = 7,
ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
@@ -863,6 +871,16 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
return set_rate;
}
+static int rockchip_mac_set_clk(struct rk3399_cru *cru,
+ int periph, uint freq)
+{
+ /* Assuming mac_clk is fed by an external clock */
+ rk_clrsetreg(>clksel_con[19], RMII_EXTCLK_MASK,
+RMII_EXTCLK_SELECT_EXT_CLK);
+
+ return 0;
+}
+
static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
{
u32 div, val;
@@ -947,8 +965,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong
rate)
ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_MAC:
- /* nothing to do, as this is an external clock */
- ret = rate;
+ ret = rockchip_mac_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_I2C1:
case SCLK_I2C2:
--
2.7.4
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[U-Boot] [PATCH 0/6] Add gmac support for rk3399-evb and rv1108-evb
This serie of patches integrates the setup mac clock is internal or external, as well as the way for setting rmii or rgmii interface. David Wu (6): rockchip: clk: Add mac clock set for rk3399 rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb net: gmac_rockchip: Define the gmac grf register struct at gmac_rockchip.c net: gmac_rockchip: Use the proerty of "clock_in_out" to set mac clock rockchip: gmac_rockchip: Add gmac support for rv1108 arch/arm/dts/rk3399-evb.dts | 4 +- configs/evb-rk3288_defconfig | 1 + drivers/clk/rockchip/clk_rk3399.c | 21 +++- drivers/net/gmac_rockchip.c | 234 -- 4 files changed, 222 insertions(+), 38 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 14/14] rockchip: dts: Enable SARADC for rk3399-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rk3399-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index be0c6d9..0e5d8d7 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -149,6 +149,10 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
bus-width = <4>;
status = "okay";
--
2.7.4
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[U-Boot] [PATCH v3 13/14] rockchip: dts: Enable SARADC for rk3368-sheep
Spam detection software, running on the system "lists.denx.de",
has identified this incoming email as possible spam. The original
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@@CONTACT_ADDRESS@@ for details.
Content preview: Enable the SARADC for download key pressed detect.
Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v3: - Add commit message
[...]
Content analysis details: (5.6 points, 5.0 required)
pts rule name description
-- --
0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
2.6 RCVD_IN_SBLRBL: Received via a relay in Spamhaus SBL
[211.157.147.132 listed in zen.spamhaus.org]
2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5)
[211.157.147.132 listed in bl.mailspike.net]
0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted
--- Begin Message ---
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rk3368-sheep.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3368-sheep.dts b/arch/arm/dts/rk3368-sheep.dts
index 7c190f7..27befad 100644
--- a/arch/arm/dts/rk3368-sheep.dts
+++ b/arch/arm/dts/rk3368-sheep.dts
@@ -260,6 +260,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
rockchip,hw-tshut-mode = <0>; /* CRU */
--
2.7.4
--- End Message ---
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[U-Boot] [PATCH v3 12/14] rockchip: dts: Enable SARADC for rk3368-px5-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rk3368-px5-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3368-px5-evb.dts b/arch/arm/dts/rk3368-px5-evb.dts
index c7478f7..e9c5eba 100644
--- a/arch/arm/dts/rk3368-px5-evb.dts
+++ b/arch/arm/dts/rk3368-px5-evb.dts
@@ -296,6 +296,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
rockchip,hw-tshut-mode = <0>; /* CRU */
--
2.7.4
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[U-Boot] [PATCH v3 10/14] rockchip: dts: Enable SARADC for rk3288-popmetal
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has identified this incoming email as possible spam. The original
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@@CONTACT_ADDRESS@@ for details.
Content preview: Enable the SARADC for download key pressed detect.
Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v3: - Add commit message
[...]
Content analysis details: (5.6 points, 5.0 required)
pts rule name description
-- --
0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server
[58.22.7.114 listed in dnsbl.sorbs.net]
2.6 RCVD_IN_SBLRBL: Received via a relay in Spamhaus SBL
[211.157.147.132 listed in zen.spamhaus.org]
2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5)
[211.157.147.132 listed in bl.mailspike.net]
0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted
--- Begin Message ---
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rk3288-popmetal.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3288-popmetal.dtsi
b/arch/arm/dts/rk3288-popmetal.dtsi
index dd6ce8b..63785eb 100644
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -491,6 +491,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
--
2.7.4
--- End Message ---
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[U-Boot] [PATCH v3 09/14] rockchip: dts: Enable SARADC for rv1108-evb
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rv1108-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts
index 0128dd8..e21b57f 100644
--- a/arch/arm/dts/rv1108-evb.dts
+++ b/arch/arm/dts/rv1108-evb.dts
@@ -30,6 +30,10 @@
snps,reset-gpio = < RK_PC1 GPIO_ACTIVE_LOW>;
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
flash@0 {
--
2.7.4
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[U-Boot] [PATCH v3 07/14] rockchip: clk: Add rk3399 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v3: None
Changes in v2:
- Use GENMASK
drivers/clk/rockchip/clk_rk3399.c | 36 +++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index 3edafea..105c499 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -181,7 +182,8 @@ enum {
/* CLKSEL_CON26 */
CLK_SARADC_DIV_CON_SHIFT= 8,
- CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT,
+ CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
+ CLK_SARADC_DIV_CON_WIDTH= 8,
/* CLKSEL_CON27 */
CLK_TSADC_SEL_X24M = 0x0,
@@ -860,6 +862,32 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
return set_rate;
}
+
+static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
+{
+ u32 div, val;
+
+ val = readl(>clksel_con[26]);
+ div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+ CLK_SARADC_DIV_CON_WIDTH);
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+ assert(src_clk_div < 128);
+
+ rk_clrsetreg(>clksel_con[26],
+CLK_SARADC_DIV_CON_MASK,
+src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+ return rk3399_saradc_get_clk(cru);
+}
+
static ulong rk3399_clk_get_rate(struct clk *clk)
{
struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
@@ -895,6 +923,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
break;
case PCLK_EFUSE1024NS:
break;
+ case SCLK_SARADC:
+ rate = rk3399_saradc_get_clk(priv->cru);
+ break;
default:
return -ENOENT;
}
@@ -943,6 +974,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong
rate)
break;
case PCLK_EFUSE1024NS:
break;
+ case SCLK_SARADC:
+ ret = rk3399_saradc_set_clk(priv->cru, rate);
+ break;
default:
return -ENOENT;
}
--
2.7.4
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[U-Boot] [PATCH v3 06/14] rockchip: clk: Add rk3368 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v3: None
Changes in v2:
- Use GENMASK
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5
drivers/clk/rockchip/clk_rk3368.c | 32 +
2 files changed, 37 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 2b1197f..5f6a5fb 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -89,6 +89,11 @@ enum {
MCU_CLK_DIV_SHIFT = 0,
MCU_CLK_DIV_MASK= GENMASK(4, 0),
+ /* CLKSEL_CON25 */
+ CLK_SARADC_DIV_CON_SHIFT= 8,
+ CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
+ CLK_SARADC_DIV_CON_WIDTH= 8,
+
/* CLKSEL43_CON */
GMAC_MUX_SEL_EXTCLK = BIT(8),
diff --git a/drivers/clk/rockchip/clk_rk3368.c
b/drivers/clk/rockchip/clk_rk3368.c
index 2be1f57..2eedf77 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -397,6 +398,31 @@ static ulong rk3368_spi_set_clk(struct rk3368_cru *cru,
ulong clk_id, uint hz)
return rk3368_spi_get_clk(cru, clk_id);
}
+static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)
+{
+ u32 div, val;
+
+ val = readl(>clksel_con[25]);
+ div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+ CLK_SARADC_DIV_CON_WIDTH);
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+ assert(src_clk_div < 128);
+
+ rk_clrsetreg(>clksel_con[25],
+CLK_SARADC_DIV_CON_MASK,
+src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+ return rk3368_saradc_get_clk(cru);
+}
+
static ulong rk3368_clk_get_rate(struct clk *clk)
{
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -419,6 +445,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
rate = rk3368_mmc_get_clk(priv->cru, clk->id);
break;
#endif
+ case SCLK_SARADC:
+ rate = rk3368_saradc_get_clk(priv->cru);
+ break;
default:
return -ENOENT;
}
@@ -453,6 +482,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong
rate)
ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);
break;
#endif
+ case SCLK_SARADC:
+ ret = rk3368_saradc_set_clk(priv->cru, rate);
+ break;
default:
return -ENOENT;
}
--
2.7.4
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[U-Boot] [PATCH v3 05/14] rockchip: clk: Add rk3328 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v3: None
Changes in v2:
- Use bitfield_extract
- Use GENMASK
drivers/clk/rockchip/clk_rk3328.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index c3a6650..540d910 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -114,7 +115,8 @@ enum {
/* CLKSEL_CON23 */
CLK_SARADC_DIV_CON_SHIFT= 0,
- CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT,
+ CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
+ CLK_SARADC_DIV_CON_WIDTH= 10,
/* CLKSEL_CON24 */
CLK_PWM_PLL_SEL_CPLL= 0,
@@ -478,6 +480,31 @@ static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru,
uint hz)
return DIV_TO_RATE(GPLL_HZ, div);
}
+static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
+{
+ u32 div, val;
+
+ val = readl(>clksel_con[23]);
+ div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+ CLK_SARADC_DIV_CON_WIDTH);
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+ assert(src_clk_div < 128);
+
+ rk_clrsetreg(>clksel_con[23],
+CLK_SARADC_DIV_CON_MASK,
+src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+ return rk3328_saradc_get_clk(cru);
+}
+
static ulong rk3328_clk_get_rate(struct clk *clk)
{
struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
@@ -501,6 +528,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
case SCLK_PWM:
rate = rk3328_pwm_get_clk(priv->cru);
break;
+ case SCLK_SARADC:
+ rate = rk3328_saradc_get_clk(priv->cru);
+ break;
default:
return -ENOENT;
}
@@ -531,6 +561,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong
rate)
case SCLK_PWM:
ret = rk3328_pwm_set_clk(priv->cru, rate);
break;
+ case SCLK_SARADC:
+ ret = rk3328_saradc_set_clk(priv->cru, rate);
+ break;
default:
return -ENOENT;
}
--
2.7.4
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[U-Boot] [PATCH v3 04/14] rockchip: clk: Add SARADC clock support for rk3288
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v3: None
Changes in v2:
- Use bitfield_extract
- Use GENMASK
drivers/clk/rockchip/clk_rk3288.c | 41 +++
1 file changed, 41 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3288.c
b/drivers/clk/rockchip/clk_rk3288.c
index 478195b..a133810 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -111,6 +112,15 @@ enum {
PERI_ACLK_DIV_SHIFT = 0,
PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
+ /*
+* CLKSEL24
+* saradc_div_con:
+* clk_saradc=24MHz/(saradc_div_con+1)
+*/
+ CLK_SARADC_DIV_CON_SHIFT= 8,
+ CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
+ CLK_SARADC_DIV_CON_WIDTH= 8,
+
SOCSTS_DPLL_LOCK= 1 << 5,
SOCSTS_APLL_LOCK= 1 << 6,
SOCSTS_CPLL_LOCK= 1 << 7,
@@ -634,6 +644,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru,
uint gclk_rate,
return rockchip_spi_get_clk(cru, gclk_rate, periph);
}
+static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
+{
+ u32 div, val;
+
+ val = readl(>cru_clksel_con[24]);
+ div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+ CLK_SARADC_DIV_CON_WIDTH);
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+ assert(src_clk_div < 128);
+
+ rk_clrsetreg(>cru_clksel_con[24],
+CLK_SARADC_DIV_CON_MASK,
+src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+ return rockchip_saradc_get_clk(cru);
+}
+
static ulong rk3288_clk_get_rate(struct clk *clk)
{
struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
@@ -666,6 +701,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
return gclk_rate;
case PCLK_PWM:
return PD_BUS_PCLK_HZ;
+ case SCLK_SARADC:
+ new_rate = rockchip_saradc_get_clk(priv->cru);
+ break;
default:
return -ENOENT;
}
@@ -756,6 +794,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong
rate)
new_rate = rate;
break;
#endif
+ case SCLK_SARADC:
+ new_rate = rockchip_saradc_set_clk(priv->cru, rate);
+ break;
default:
return -ENOENT;
}
--
2.7.4
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[U-Boot] [PATCH v3 02/14] rockchip: configs: Enable the ROCKCHIP_SARADC config
Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Except for 3036 and 3228 Socs, which don't support SARADC, enable the ROCKCHIP_SARADC config at the other Socs' defconfig. Signed-off-by: David Wu <david...@rock-chips.com> --- [...] Content analysis details: (5.6 points, 5.0 required) pts rule name description -- -- 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.6 RCVD_IN_SBLRBL: Received via a relay in Spamhaus SBL [211.157.147.132 listed in zen.spamhaus.org] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.132 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted --- Begin Message --- Except for 3036 and 3228 Socs, which don't support SARADC, enable the ROCKCHIP_SARADC config at the other Socs' defconfig. Signed-off-by: David Wu <david...@rock-chips.com> --- Changes in v3: None Changes in v2: - Add the ROCKCHIP_SARADC config at other rockchip defconfigs like evb-px5... configs/chromebit_mickey_defconfig | 2 ++ configs/chromebook_jerry_defconfig | 2 ++ configs/chromebook_minnie_defconfig | 2 ++ configs/evb-px5_defconfig | 2 ++ configs/evb-rk3288_defconfig| 2 ++ configs/evb-rk3328_defconfig| 2 ++ configs/evb-rk3399_defconfig| 2 ++ configs/evb-rv1108_defconfig| 2 ++ configs/fennec-rk3288_defconfig | 2 ++ configs/firefly-rk3288_defconfig| 2 ++ configs/firefly-rk3399_defconfig| 2 ++ configs/geekbox_defconfig | 2 ++ configs/lion-rk3368_defconfig | 2 ++ configs/miqi-rk3288_defconfig | 2 ++ configs/phycore-rk3288_defconfig| 2 ++ configs/popmetal-rk3288_defconfig | 2 ++ configs/puma-rk3399_defconfig | 2 ++ configs/rock2_defconfig | 2 ++ configs/rock_defconfig | 2 ++ configs/sheep-rk3368_defconfig | 2 ++ configs/tinker-rk3288_defconfig | 2 ++ 21 files changed, 42 insertions(+) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index f40c0b9..e84706d 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -40,6 +40,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index cdeabaa..f612d31 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -42,6 +42,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index c1e36fa..38a4b42 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -41,6 +41,8 @@ CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 4323b77..cbf467f 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -13,6 +13,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 5294ba9..f09b769 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -37,6 +37,8 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 7bec001..b44b029 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_TIME=y CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_SARADC_ROCKCHIP=y CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_MMC_DW=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7a0bd4a..6d0d1a0 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -30,6 +30,8 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_
[U-Boot] [PATCH v3 03/14] rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v3: None
Changes in v2:
- Use bitfield_extract
- Use GENMASK
arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5
drivers/clk/rockchip/clk_rv1108.c | 33 -
include/dt-bindings/clock/rv1108-cru.h | 2 ++
3 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
index 2a1ae69..ad2dc96 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
@@ -90,6 +90,11 @@ enum {
CORE_CLK_DIV_SHIFT = 0,
CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT,
+ /* CLKSEL_CON22 */
+ CLK_SARADC_DIV_CON_SHIFT= 0,
+ CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
+ CLK_SARADC_DIV_CON_WIDTH= 10,
+
/* CLKSEL24_CON */
MAC_PLL_SEL_SHIFT = 12,
MAC_PLL_SEL_MASK= 1 << MAC_PLL_SEL_SHIFT,
diff --git a/drivers/clk/rockchip/clk_rv1108.c
b/drivers/clk/rockchip/clk_rv1108.c
index cf966bb..86e73e4 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -36,7 +37,7 @@ enum {
#hz "Hz cannot be hit with PLL "\
"divisors on line " __stringify(__LINE__));
-/* use interge mode*/
+/* use integer mode */
static inline int rv1108_pll_id(enum rk_clk_id clk_id)
{
int id = 0;
@@ -130,6 +131,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint
rate)
return DIV_TO_RATE(pll_rate, div);
}
+static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
+{
+ u32 div, val;
+
+ val = readl(>clksel_con[22]);
+ div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+ CLK_SARADC_DIV_CON_WIDTH);
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+ assert(src_clk_div < 128);
+
+ rk_clrsetreg(>clksel_con[22],
+CLK_SARADC_DIV_CON_MASK,
+src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+ return rv1108_saradc_get_clk(cru);
+}
+
static ulong rv1108_clk_get_rate(struct clk *clk)
{
struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
@@ -137,6 +163,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk)
switch (clk->id) {
case 0 ... 63:
return rkclk_pll_get_rate(priv->cru, clk->id);
+ case SCLK_SARADC:
+ return rv1108_saradc_get_clk(priv->cru);
default:
return -ENOENT;
}
@@ -154,6 +182,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong
rate)
case SCLK_SFC:
new_rate = rv1108_sfc_set_clk(priv->cru, rate);
break;
+ case SCLK_SARADC:
+ new_rate = rv1108_saradc_set_clk(priv->cru, rate);
+ break;
default:
return -ENOENT;
}
diff --git a/include/dt-bindings/clock/rv1108-cru.h
b/include/dt-bindings/clock/rv1108-cru.h
index d2ad3bb..7defc6b 100644
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -39,6 +39,7 @@
#define SCLK_MAC_TX88
#define SCLK_MACREF89
#define SCLK_MACREF_OUT90
+#define SCLK_SARADC91
/* aclk gates */
@@ -67,6 +68,7 @@
#define PCLK_TIMER 270
#define PCLK_PERI 271
#define PCLK_GMAC 272
+#define PCLK_SARADC273
/* hclk gates */
#define HCLK_I2S0_8CH 320
--
2.7.4
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[U-Boot] [PATCH v3 00/14] Add rockchip SARADC support
The SARADC is used for adc keys and charging detect at uboot loader. Except for the rk3036 and rk3228 Socs, the others support the SARADC IP. Changes in v3: - Add commit message - Add commit message - Add commit message - Add commit message - Add commit message - Add commit message Changes in v2: - Order the the include file - Use structures for I/O access - Use dev_read_add - Add the ROCKCHIP_SARADC config at other rockchip defconfigs like evb-px5... - Use bitfield_extract - Use GENMASK - Use bitfield_extract - Use GENMASK - Use bitfield_extract - Use GENMASK - Use GENMASK - Use GENMASK David Wu (14): dm: adc: Add driver for Rockchip SARADC rockchip: configs: Enable the ROCKCHIP_SARADC config rockchip: clk: Add rv1108 SARADC clock support rockchip: clk: Add SARADC clock support for rk3288 rockchip: clk: Add rk3328 SARADC clock support rockchip: clk: Add rk3368 SARADC clock support rockchip: clk: Add rk3399 SARADC clock support rockchip: dts: rv1108: Add SARADC node at dtsi level rockchip: dts: Enable SARADC for rv1108-evb rockchip: dts: Enable SARADC for rk3288-popmetal rockchip: dts: Enable SARADC for rk3328-evb rockchip: dts: Enable SARADC for rk3368-px5-evb rockchip: dts: Enable SARADC for rk3368-sheep rockchip: dts: Enable SARADC for rk3399-evb arch/arm/dts/rk3288-popmetal.dtsi | 4 + arch/arm/dts/rk3328-evb.dts | 4 + arch/arm/dts/rk3368-px5-evb.dts | 4 + arch/arm/dts/rk3368-sheep.dts | 4 + arch/arm/dts/rk3399-evb.dts | 4 + arch/arm/dts/rv1108-evb.dts | 4 + arch/arm/dts/rv1108.dtsi| 11 ++ arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 + arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5 + configs/chromebit_mickey_defconfig | 2 + configs/chromebook_jerry_defconfig | 2 + configs/chromebook_minnie_defconfig | 2 + configs/evb-px5_defconfig | 2 + configs/evb-rk3288_defconfig| 2 + configs/evb-rk3328_defconfig| 2 + configs/evb-rk3399_defconfig| 2 + configs/evb-rv1108_defconfig| 2 + configs/fennec-rk3288_defconfig | 2 + configs/firefly-rk3288_defconfig| 2 + configs/firefly-rk3399_defconfig| 2 + configs/geekbox_defconfig | 2 + configs/lion-rk3368_defconfig | 2 + configs/miqi-rk3288_defconfig | 2 + configs/phycore-rk3288_defconfig| 2 + configs/popmetal-rk3288_defconfig | 2 + configs/puma-rk3399_defconfig | 2 + configs/rock2_defconfig | 2 + configs/rock_defconfig | 2 + configs/sheep-rk3368_defconfig | 2 + configs/tinker-rk3288_defconfig | 2 + drivers/adc/Kconfig | 9 ++ drivers/adc/Makefile| 1 + drivers/adc/rockchip-saradc.c | 183 drivers/clk/rockchip/clk_rk3288.c | 41 ++ drivers/clk/rockchip/clk_rk3328.c | 35 - drivers/clk/rockchip/clk_rk3368.c | 32 + drivers/clk/rockchip/clk_rk3399.c | 36 - drivers/clk/rockchip/clk_rv1108.c | 33 - include/dt-bindings/clock/rv1108-cru.h | 2 + 39 files changed, 456 insertions(+), 3 deletions(-) create mode 100644 drivers/adc/rockchip-saradc.c -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [U-Boot,v2,11/14] arm: dts: Enable SARADC for rk3328-evb
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3328-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 8a14c65..df44ccb 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -42,6 +42,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
};
--
2.7.4
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