Re: Ficus EE not working / supported ?

[Ezequiel Garcia]

Hi Mani,

Have you had any chance to look at this?

Thanks!
Ezequiel

On Tue, 16 Mar 2021 at 09:44, Ezequiel Garcia
 wrote:
>
> Hi Mani, Kever,
>
> I tried to bringup (again) my Ficus board, but I've been unable to
> boot a kernel.
>
> Seems my old u-boot branch doesn't want to boot, and the only U-Boot I managed
> to boot is some recent one (which I guess is better than having an ancient 
> one).
>
> Now, doc/board/rockchip/rockchip.rst mentions TPL but Ficus defconfig
> isn't updated
> to use that. So I'm using rock960-rk3399_defconfig, with ethernet enabled,
> the issue is I can't boot any kernel with that. Seems it hangs up very early,
> and doesn't even want to output anything on earlyconsole.
>
> I was wondering if maybe this rings a bell? Maybe DDR setup?
>
> U-Boot TPL 2021.01-dirty (Mar 15 2021 - 17:46:11)
> Channel 0: DDR3, 800MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> Channel 1: DDR3, 800MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> 256B stride
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> U-Boot SPL 2021.01-dirty (Mar 15 2021 - 17:46:11 -0300)
> Trying to boot from MMC1
> cannot find image node 'atf_1': -1
>
>
> U-Boot 2021.01-dirty (Mar 15 2021 - 17:46:11 -0300)
>
> SoC: Rockchip rk3399
> Reset cause: POR
> Model: 96boards RK3399 Ficus
> DRAM:  2 GiB
> PMIC:  RK808
> MMC:   mmc@fe31: 2, mmc@fe32: 1, sdhci@fe33: 0
> Loading Environment from MMC... *** Warning - bad CRC, using default 
> environment
>
> In:serial
> Out:   serial
> Err:   serial
> Model: 96boards RK3399 Ficus
> Net:
> Warning: ethernet@fe30 (eth0) using random MAC address - f2:a3:4d:58:42:dd
> eth0: ethernet@fe30
> starting USB...
> 
> 
> rock960 => setenv ipaddr 192.168.0.20
> rock960 => setenv ipaddr 192.168.0.200
> rock960 => setenv bootcmd "tftpboot 0x0200 rk3399-ficus/Image;
> tftpboot 0x01f0 rk3399-ficus/rk3399-ficus.dtb; booti 0x0200 -
> 0x01f0"
> rock960 => boot
> Speed: 1000, full duplex
> Using ethernet@fe30 device
> TFTP from server 192.168.0.20; our IP address is 192.168.0.200
> Filename 'rk3399-ficus/Image'.
> Load address: 0x200
> Loading: #
> #
> #
> #
> #
> #
> #
> #
> #
> #
> ##
> 5.1 MiB/s
> done
> Bytes transferred = 9736704 (949200 hex)
> Speed: 1000, full duplex
> Using ethernet@fe30 device
> TFTP from server 192.168.0.20; our IP address is 192.168.0.200
> Filename 'rk3399-ficus/rk3399-ficus.dtb'.
> Load address: 0x1f0
> Loading: 
> 3.7 MiB/s
> done
> Bytes transferred = 50911 (c6df hex)
> Moving Image from 0x200 to 0x208, end=2a1f000
> ## Flattened Device Tree blob at 01f0
>Booting using the fdt blob at 0x1f0
> Host not halted after 16000 microseconds.
>Loading Device Tree to 79f16000, end 79f256de ... OK
>
> Starting kernel ...
>
> Thanks,
> Ezequiel

Ficus EE not working / supported ?

[Ezequiel Garcia]

Hi Mani, Kever,

I tried to bringup (again) my Ficus board, but I've been unable to
boot a kernel.

Seems my old u-boot branch doesn't want to boot, and the only U-Boot I managed
to boot is some recent one (which I guess is better than having an ancient one).

Now, doc/board/rockchip/rockchip.rst mentions TPL but Ficus defconfig
isn't updated
to use that. So I'm using rock960-rk3399_defconfig, with ethernet enabled,
the issue is I can't boot any kernel with that. Seems it hangs up very early,
and doesn't even want to output anything on earlyconsole.

I was wondering if maybe this rings a bell? Maybe DDR setup?

U-Boot TPL 2021.01-dirty (Mar 15 2021 - 17:46:11)
Channel 0: DDR3, 800MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
Channel 1: DDR3, 800MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
256B stride
Trying to boot from BOOTROM
Returning to boot ROM...

U-Boot SPL 2021.01-dirty (Mar 15 2021 - 17:46:11 -0300)
Trying to boot from MMC1
cannot find image node 'atf_1': -1


U-Boot 2021.01-dirty (Mar 15 2021 - 17:46:11 -0300)

SoC: Rockchip rk3399
Reset cause: POR
Model: 96boards RK3399 Ficus
DRAM:  2 GiB
PMIC:  RK808
MMC:   mmc@fe31: 2, mmc@fe32: 1, sdhci@fe33: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Model: 96boards RK3399 Ficus
Net:
Warning: ethernet@fe30 (eth0) using random MAC address - f2:a3:4d:58:42:dd
eth0: ethernet@fe30
starting USB...


rock960 => setenv ipaddr 192.168.0.20
rock960 => setenv ipaddr 192.168.0.200
rock960 => setenv bootcmd "tftpboot 0x0200 rk3399-ficus/Image;
tftpboot 0x01f0 rk3399-ficus/rk3399-ficus.dtb; booti 0x0200 -
0x01f0"
rock960 => boot
Speed: 1000, full duplex
Using ethernet@fe30 device
TFTP from server 192.168.0.20; our IP address is 192.168.0.200
Filename 'rk3399-ficus/Image'.
Load address: 0x200
Loading: #
#
#
#
#
#
#
#
#
#
##
5.1 MiB/s
done
Bytes transferred = 9736704 (949200 hex)
Speed: 1000, full duplex
Using ethernet@fe30 device
TFTP from server 192.168.0.20; our IP address is 192.168.0.200
Filename 'rk3399-ficus/rk3399-ficus.dtb'.
Load address: 0x1f0
Loading: 
3.7 MiB/s
done
Bytes transferred = 50911 (c6df hex)
Moving Image from 0x200 to 0x208, end=2a1f000
## Flattened Device Tree blob at 01f0
   Booting using the fdt blob at 0x1f0
Host not halted after 16000 microseconds.
   Loading Device Tree to 79f16000, end 79f256de ... OK

Starting kernel ...

Thanks,
Ezequiel

Re: [PATCH RFC 10/20] mmc/jz_mmc: Add a JZ4740 compatible string

[Ezequiel Garcia]

Hi Lubomir,

On Tue, 2020-11-17 at 22:00 +0100, Lubomir Rintel wrote:
> The driver doesn't use the jz4780's extra DMA channels and handles jz4740
> just fine.
> 
> Signed-off-by: Lubomir Rintel 
> ---
>  drivers/mmc/jz_mmc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
> index b33f0850738..d4b9d15ef2e 100644
> --- a/drivers/mmc/jz_mmc.c
> +++ b/drivers/mmc/jz_mmc.c
> @@ -490,6 +490,7 @@ static int jz_mmc_probe(struct udevice *dev)
>  }
>  
>  static const struct udevice_id jz_mmc_ids[] = {
> + { .compatible = "ingenic,jz4740-mmc" },

Normally, you don't need to add another compatible
if there's nothing in the implementation to distinguish
them.

However, I'm guessing here you want to add the compatible
so you can support kernel compatibles such as ingenic,jz4740-mmc?

Regards,
Ezequiel

>   { .compatible = "ingenic,jz4780-mmc" },
>   { }
>  };

Re: [PATCH 3/3] doc: rockchip: Remove list of supported boards

[Ezequiel Garcia]

On Fri, 22 May 2020 at 11:16, Walter Lozano  wrote:
>
> As documentation is being moved to doc/boards/rockchip create a warning
> message and remove the redundant list of supported boards.
>
> Signed-off-by: Walter Lozano 
> ---
>  doc/README.rockchip | 72 +++--
>  1 file changed, 4 insertions(+), 68 deletions(-)
>

How about we simply remove this file and move all its content
to doc/boards/rockchip?

I'd say it can be all done in one go.

Thanks,
Eze

> diff --git a/doc/README.rockchip b/doc/README.rockchip
> index 70c8798ed2..154166ec78 100644
> --- a/doc/README.rockchip
> +++ b/doc/README.rockchip
> @@ -8,6 +8,10 @@ U-Boot on Rockchip
>
>  A wide range of Rockchip SoCs are supported in mainline U-Boot
>
> +Warning
> +===
> +This document is being moved to doc/board/rockchip, so information on it
> +might be incomplete or outdated.
>
>  Prerequisites
>  =
> @@ -24,77 +28,9 @@ You will need:
> - Suitable ARM cross compiler, e.g.:
>  sudo apt-get install gcc-4.7-arm-linux-gnueabi
>
> -
>  Building
>  
>
> -At present 11 RK3288 boards are supported:
> -
> -   - EVB RK3288 - use evb-rk3288 configuration
> -   - Firefly RK3288 - use firefly-rk3288 configuration
> -   - Hisense Chromebook - use chromebook_jerry configuration
> -   - Asus C100P Chromebook - use chromebook_minnie configuration
> -   - Asus Chromebit - use chromebook_mickey configuration
> -   - MiQi RK3288 - use miqi-rk3288 configuration
> -   - phyCORE-RK3288 RDK - use phycore-rk3288 configuration
> -   - PopMetal RK3288 - use popmetal-rk3288 configuration
> -   - Radxa Rock 2 - use rock2 configuration
> -   - Tinker RK3288 - use tinker-rk3288 configuration
> -   - Vyasa RK3288 - use vyasa-rk3288 configuration
> -
> -Two RK3036 boards are supported:
> -
> -   - EVB RK3036 - use evb-rk3036 configuration
> -   - Kylin - use kylin_rk3036 configuration
> -
> -Two RK3308 boards are supported:
> -
> -   - EVB RK3308 - use evb-rk3308 configuration
> -   - ROC-CC-RK3308 - use roc-cc-rk3308 configuration
> -
> -Three RK3328 boards are supported:
> -
> -   - EVB RK3328 - use evb-rk3328_defconfig
> -   - Pine64 Rock64 board - use rock64-rk3328_defconfig
> -   - Firefly / Libre Computer Project ROC-RK3328-CC board -
> - use roc-cc-rk3328_defconfig
> -
> -Size RK3399 boards are supported (aarch64):
> -
> -   - EBV RK3399 - use evb_rk3399 configuration
> -   - Firefly RK3399 - use the firefly_rk3399 configuration
> -   - Puma - use puma_rk3399 configuration
> -   - Ficus - use ficus-rk3399 configuration
> -   - Rock960 (Vamrs) - use rock960-rk3399 configuration
> -   - Bob - use chromebook_bob configuration
> -
> -Four RK3368 boards are supported:
> -
> -   - Sheep - use sheep-rk3368 configuration
> -   - Lion - use lion-rk3368 configuration
> -   - Geekbox - use geekbox configuration
> -   - EVB PX5 - use evb-px5  configuration
> -
> -One RK3128 board is supported:
> -
> -   - EVB RK3128 - use evb-rk3128 configuration
> -
> -One RK3229 board is supported:
> -
> -   - EVB RK3229 - use evb-rk3229 configuration
> -
> -Two RV1108 boards are supported:
> -
> -   - EVB RV1108 - use evb-rv1108 configuration
> -   - Elgin R1 - use elgin-rv1108 configuration
> -
> -One RV3188 baord is supported:
> -
> -   - Raxda Rock - use rock configuration
> -
> -
> -For example:
> -
>  1. To build RK3288 board:
>
> CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig 
> all
> --
> 2.20.1
>

Re: [U-Boot] Issues when saving environment in RK399 RockPI 4

[Ezequiel Garcia]

Hi Matthias, Fabio:

Thanks for the reply.

On Fri, 8 Nov 2019 at 13:45, Matthias Brugger  wrote:
>
> Hi Ezequiel,
>
> On 07/11/2019 20:27, Fabio Estevam wrote:
> > Hi Ezequiel,
> >
> > On Thu, Nov 7, 2019 at 3:45 PM Ezequiel Garcia
> >  wrote:
> >>
> >> I decided to test latest U-Boot, following instructions in
> >> doc/README.rockchip. The instructions seemed
> >> clear and I could build this easily.
> >>
> >> However, there seems to be an issue when I save the environment. Any ideas?
> >>
> >> => saveenv
> >> Saving Environment to MMC... Writing to MMC(0)... OK
> >> => reset
> >> resetting ...
> >> U-Boot TPL 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44)
> >> Trying to boot from BOOTROM
> >> Returning to boot ROM...
> >>
> >> U-Boot SPL 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44 
> >> -0300)
> >> Trying to boot from MMC2
> >>
> >>
> >> U-Boot 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44 -0300)
> >>
> >> Model: Radxa ROCK Pi 4
> >> DRAM:  2 GiB
> >> Cannot find regulator pwm init_voltage
> >> MMC:   dwmmc@fe32: 1, sdhci@fe33: 0
> >> Loading Environment from MMC... OK
> >> In:serial@ff1a
> >> Out:   serial@ff1a
> >> Err:   serial@ff1a
> >> Model: Radxa ROCK Pi 4
> >> ## Error: Can't overwrite "serial#"
> >> ## Error inserting "serial#" variable, errno=1
> >> initcall sequence 7ffc10b8 failed at call 00202a20 (err=-1)
> >> ### ERROR ### Please RESET the board ###
> >
> > I have observed issues like this with i.MX when U-Boot size grew and
> > overlapped the environment variable region.
> >
> > Here is one commit that fixed the issue for mx53loco board:
> > https://gitlab.denx.de/u-boot/u-boot/commit/033f6ea5fa5fce63d52c8c2b63d8284144415b88
> >
> > Try to investigate if this could be cause of the issue you are seeing.
> >
>
> You could also try the first two patches from this series:
> https://patchwork.ozlabs.org/user/todo/uboot/?series=132338
>
> Maybe you are hit by the over-writing discontiguous files bug in the FAT code.
>

It's probably something along those lines. OTOH, it seems RK3399 is under going
some more work, judging by some patches recently sent. I decided to go back
to some vendor bootloader until upstream settles a bit on the stable side.

Will be getting back to this sooner or later.

Thanks again,
Ezequiel
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[U-Boot] Issues when saving environment in RK399 RockPI 4

[Ezequiel Garcia]

I decided to test latest U-Boot, following instructions in
doc/README.rockchip. The instructions seemed
clear and I could build this easily.

However, there seems to be an issue when I save the environment. Any ideas?

=> saveenv
Saving Environment to MMC... Writing to MMC(0)... OK
=> reset
resetting ...
U-Boot TPL 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44)
Trying to boot from BOOTROM
Returning to boot ROM...

U-Boot SPL 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44 -0300)
Trying to boot from MMC2


U-Boot 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44 -0300)

Model: Radxa ROCK Pi 4
DRAM:  2 GiB
Cannot find regulator pwm init_voltage
MMC:   dwmmc@fe32: 1, sdhci@fe33: 0
Loading Environment from MMC... OK
In:serial@ff1a
Out:   serial@ff1a
Err:   serial@ff1a
Model: Radxa ROCK Pi 4
## Error: Can't overwrite "serial#"
## Error inserting "serial#" variable, errno=1
initcall sequence 7ffc10b8 failed at call 00202a20 (err=-1)
### ERROR ### Please RESET the board ###
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Re: [U-Boot] [RFC PATCH] dm: core: Remove libfdt dependency when unnecessary

[Ezequiel Garcia]

On Tue, 5 Nov 2019 at 15:12, Walter Lozano  wrote:
>
> Hi Ezequiel,
>
> On 5/11/19 13:56, Ezequiel Garcia wrote:
> > Hello Walter,
> >
> > Thanks for the patch.
> >
> > On Tue, 5 Nov 2019 at 12:27, Walter Lozano  
> > wrote:
> >> The support of libfdt should only be needed when OF_CONTROL
> >> is enabled and OF_PLATDATA is not, as in other cases there is no
> >> DT file to query.
> >>
> >> This patch fixes this dependency allowing to save some space.
> >>
> > Can you add some more information about the space saving?
>
>
> Sure, I will add some additional information about the static footprint.
> However according to my understanding the impact depends on how well
> different drivers supports features like OF_PLATDATA. For instance, in
> my current configuration it saves 2 KB.
>

Not sure I follow you. This patch adds a condition which adds/removes code
based on some conditions. So, it should depend on the arch, but otherwise
the reduction is an invariant as it just depend on the size of the
code that is being
added/removed. Or am I missing something?

>
> > The ./scripts/bloat-o-meter will help you get some info
> > on static footprint.
>
>
> Thanks for your suggestion. I think you are pointing to a script found
> in the Linux kernel, right?

Ah, yes. I have this script imported on my U-Boot repo, so I assumed
it was here as well.

> I also think it could be useful to have a
> deep understanding on how the static footprint of some .o files changes,
> but it won't give us much information about the end result of the binary
> image, which is affected by the dependencies and compiler/linker
> optimizations. Is this correct?
>

Normally, bloat-o-meter gives you a rough idea and allows you to
weigh code complexity vs. size reduction.

>
> >> Signed-off-by: Walter Lozano 
> >> ---
> >>   drivers/core/ofnode.c | 132 +--
> >>   include/dm/read.h | 141 ++
> >>   2 files changed, 267 insertions(+), 6 deletions(-)
> >>
> > You should try to avoid adding #ifdefery to the code. Normally,
> > the way to ifdef code is by having this in a header:
> >
> > #ifdef CONFIG_FOO
> > int foo_feature_optional(struct foo *priv);
> > #else
> > static inline int foo_feature_optional(struct foo *priv)
> > {
> >  return 0;
> > }
> > #endif
> >
> > The user of foo_feature_optional shouldn't be bothered with
> > FOO being enabled or not. Pushing ifdefs away from .c to .h
> > is a common pattern, well described in a classic old article:
> >
> > http://www.literateprogramming.com/ifdefs.pdf
> >
> > Do you think you can try to rework the patch to reduce its impact
> > as much as possible?
>
>
> Thanks for your review and your suggestions, I will be happy to rework
> this to improve it.
>
>
> The intention of this RFC is to get some feedback about if this is
> something worth to be added and if this is the right approach. The use
> of OF_PLATDATA is quite limited as it needs drivers to support it, which
> will probably be a long process. Enabling it but having some drivers to
> query DT properties has no sense and requires additional dependencies,
> like libfdt.
>
> Also I think it should be possible to remove some extra components but
> it will require extra work to avoid break some configurations.
>

It's always good to shave off bytes, specially in SPL -- not so much
in proper U-Boot, right?

BTW, what is the motivation of this patch: which platform are you
working on, and
how is it size constrained?

Thanks,
Ezequiel
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Re: [U-Boot] [RFC PATCH] dm: core: Remove libfdt dependency when unnecessary

[Ezequiel Garcia]

Hello Walter,

Thanks for the patch.

On Tue, 5 Nov 2019 at 12:27, Walter Lozano  wrote:
>
> The support of libfdt should only be needed when OF_CONTROL
> is enabled and OF_PLATDATA is not, as in other cases there is no
> DT file to query.
>
> This patch fixes this dependency allowing to save some space.
>

Can you add some more information about the space saving?
The ./scripts/bloat-o-meter will help you get some info
on static footprint.

> Signed-off-by: Walter Lozano 
> ---
>  drivers/core/ofnode.c | 132 +--
>  include/dm/read.h | 141 ++
>  2 files changed, 267 insertions(+), 6 deletions(-)
>

You should try to avoid adding #ifdefery to the code. Normally,
the way to ifdef code is by having this in a header:

#ifdef CONFIG_FOO
int foo_feature_optional(struct foo *priv);
#else
static inline int foo_feature_optional(struct foo *priv)
{
return 0;
}
#endif

The user of foo_feature_optional shouldn't be bothered with
FOO being enabled or not. Pushing ifdefs away from .c to .h
is a common pattern, well described in a classic old article:

http://www.literateprogramming.com/ifdefs.pdf

Do you think you can try to rework the patch to reduce its impact
as much as possible?

Thanks,
Ezequiel
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Re: [U-Boot] [PATCH v3 3/3] board: puma: Use rockchip_* helpers to setup cpuid and macaddr【请注意，邮件由u-boot-boun...@lists.denx.de代发】 setup cpuid and macaddr

[Ezequiel Garcia]

Hi Kever, Rohan,

On Wed, 2019-07-24 at 20:26 +0800, Kever Yang wrote:
> Hi Rohan,
> 
> On 2019/7/24 下午7:09, Rohan Garg wrote:
> > We should use the shared helpers to setup the necessary parts
> > 
> > Signed-off-by: Rohan Garg 
> > ---
> > 
> >   .../puma_rk3399/puma-rk3399.c | 108 +++---
> >   1 file changed, 18 insertions(+), 90 deletions(-)
> > 
> > diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c 
> > b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
> > index 251cd2d566..fb6c7c1f0a 100644
> > --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
> > +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
> > @@ -17,6 +17,7 @@
> >   #include 
> >   #include 
> >   #include 
> > +#include 
> >   #include 
> >   #include 
> >   #include 
> > @@ -36,94 +37,6 @@ int board_init(void)
> > return 0;
> >   }
> >   
> > -static void setup_macaddr(void)
> > -{
> > -#if CONFIG_IS_ENABLED(CMD_NET)
> > -   int ret;
> > -   const char *cpuid = env_get("cpuid#");
> > -   u8 hash[SHA256_SUM_LEN];
> > -   int size = sizeof(hash);
> > -   u8 mac_addr[6];
> > -
> > -   /* Only generate a MAC address, if none is set in the environment */
> > -   if (env_get("ethaddr"))
> > -   return;
> > -
> > -   if (!cpuid) {
> > -   debug("%s: could not retrieve 'cpuid#'\n", __func__);
> > -   return;
> > -   }
> > -
> > -   ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, );
> > -   if (ret) {
> > -   debug("%s: failed to calculate SHA256\n", __func__);
> > -   return;
> > -   }
> > -
> > -   /* Copy 6 bytes of the hash to base the MAC address on */
> > -   memcpy(mac_addr, hash, 6);
> > -
> > -   /* Make this a valid MAC address and set it */
> > -   mac_addr[0] &= 0xfe;  /* clear multicast bit */
> > -   mac_addr[0] |= 0x02;  /* set local assignment bit (IEEE802) */
> > -   eth_env_set_enetaddr("ethaddr", mac_addr);
> > -#endif
> > -}
> > -
> > -static void setup_serial(void)
> > -{
> > -#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
> > -   const u32 cpuid_offset = 0x7;
> > -   const u32 cpuid_length = 0x10;
> > -
> > -   struct udevice *dev;
> > -   int ret, i;
> > -   u8 cpuid[cpuid_length];
> > -   u8 low[cpuid_length/2], high[cpuid_length/2];
> > -   char cpuid_str[cpuid_length * 2 + 1];
> > -   u64 serialno;
> > -   char serialno_str[17];
> > -
> > -   /* retrieve the device */
> > -   ret = uclass_get_device_by_driver(UCLASS_MISC,
> > - DM_GET_DRIVER(rockchip_efuse), );
> > -   if (ret) {
> > -   debug("%s: could not find efuse device\n", __func__);
> > -   return;
> > -   }
> > -
> > -   /* read the cpu_id range from the efuses */
> > -   ret = misc_read(dev, cpuid_offset, , sizeof(cpuid));
> > -   if (ret) {
> > -   debug("%s: reading cpuid from the efuses failed\n",
> > - __func__);
> > -   return;
> > -   }
> > -
> > -   memset(cpuid_str, 0, sizeof(cpuid_str));
> > -   for (i = 0; i < 16; i++)
> > -   sprintf(_str[i * 2], "%02x", cpuid[i]);
> > -
> > -   debug("cpuid: %s\n", cpuid_str);
> > -
> > -   /*
> > -* Mix the cpuid bytes using the same rules as in
> > -*   ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
> > -*/
> > -   for (i = 0; i < 8; i++) {
> > -   low[i] = cpuid[1 + (i << 1)];
> > -   high[i] = cpuid[i << 1];
> > -   }
> > -
> > -   serialno = crc32_no_comp(0, low, 8);
> > -   serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
> > -   snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
> > -
> > -   env_set("cpuid#", cpuid_str);
> > -   env_set("serial#", serialno_str);
> > -#endif
> > -}
> > -
> >   static void setup_iodomain(void)
> >   {
> > const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3;
> > @@ -213,8 +126,23 @@ static int setup_boottargets(void)
> >   
> >   int misc_init_r(void)
> 
> After misc_init_r has add into rk3399_board, then this misc_init_r() 
> here will be multi-defined?
> 
> In this case, maybe we need to remove the misc_init_r() from 
> rk3399_board.c first? :(
> 
> 

Good catch. Indeed, with the first patch applied the build would fail.

Does this mean we should let each board introduce
its own misc_init_r, or instead provide a common weak misc_init_r?

Thanks,
Ezequiel

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Re: [U-Boot] [PATCH v2 00/99] ram: rk3399: Add LPDDR4 support

[Ezequiel Garcia]

Hi Jagan,

Thanks for your hard work. I'm sure everyone in the Rockchip community
is excited about finally having this support in U-Boot.

On Tue, 25 Jun 2019 at 12:46, Jagan Teki  wrote:
[..]
> >
> > Was it absolutely necessary to split these changes into 99 commits? I
> > believe at least some of them can be squashed. Reviewing 99 patches
> > isn't feasible.
>
> Squashed, I'm not sure because the patches were created to satisfy the
> bisectability and travis-ci, if you find any please feel to comment.
> About the commit count, I have mentioned in v1, the idea of having
> many commits in one series to have all lpddr4(-related) changes in one
> place and also all the commit has incremental approach of supporting
> rank detection and lpddr4. If require I'm open to sent next versions
> as multiple series, no problem on that.
>

I strongly agree with Vasily, and I don't think multiple series makes it any
better.

What's the reason for having two commits for:

"ram: rk3399: Set lpddr4 MR3" and "ram: rk3399: Set lpddr4 MR12" ?

Or splitting all the "ram: rk3399: Add ... macro" ?

What do you loose if you merge the patches into one?

I must confess I am very surprised, and don't really understand what do you
gain with this excessive split. Normally, when we are adding a new feature,
we normally don't need many patches, so it's the other way around, really.

Bisectability is about not breaking existing support, but because the feature
is new, normally this is easy.

Thanks again!
Eze
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Re: [U-Boot] [PATCH 2/2] mmc: Register only the first MMC device on MMC_TINY

[Ezequiel Garcia]

On Sat, 25 May 2019 at 19:26, Ezequiel Garcia  wrote:
>
> When MMC_TINY is enabled, support for only one MMC device
> is provided. Boards that register more than one device,
> will just write over mmc_static keeping only the last one
> registered.
>
> This commit prevents this, keeping only the first MMC
> device created. A debug warning message is added, if nothing
> else, as a hint/documentation for developers.
>
> Signed-off-by: Ezequiel Garcia 

Not sure if it's too early for an gently ping here.

I just want to make sure these two will get some eyes.

Thanks,
Eze

> ---
>  drivers/mmc/mmc_legacy.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
> index 66a7cda440cd..b0f5cf58a2b3 100644
> --- a/drivers/mmc/mmc_legacy.c
> +++ b/drivers/mmc/mmc_legacy.c
> @@ -150,6 +150,15 @@ struct mmc *mmc_create(const struct mmc_config *cfg, 
> void *priv)
>  {
> struct mmc *mmc = _static;
>
> +   /* First MMC device registered, fail to register a new one.
> +* Given users are not expecting this to fail, instead
> +* of failing let's just return the only MMC device
> +*/
> +   if (mmc->cfg) {
> +   debug("Warning: MMC_TINY doesn't support multiple MMC 
> devices\n");
> +   return mmc;
> +   }
> +
> mmc->cfg = cfg;
> mmc->priv = priv;
>
> --
> 2.20.1
>
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Re: [U-Boot] [PATCH] configs: Remove CONFIG_SPL_FS_EXT4 for all MX6 platforms

[Ezequiel Garcia]

On Fri, 2019-05-31 at 12:39 +0200, Stefano Babic wrote:
> Hi Ezequiel,
> 
> On 26/05/19 00:57, Marek Vasut wrote:
> > On 5/26/19 12:45 AM, Ezequiel Garcia wrote:
> > > On Sun, 2019-05-26 at 00:24 +0200, Marek Vasut wrote:
> > > > On 5/25/19 11:47 PM, Ezequiel Garcia wrote:
> > > > > On Sat, 2019-05-25 at 22:15 +0200, Marek Vasut wrote:
> > > > > > On 5/25/19 6:49 PM, Ezequiel Garcia wrote:
> > > > > > > i.MX6 platforms boot U-Boot second-stage from unformatted space,
> > > > > > > and should not need Ext filesystem support on SPL.
> > > > > > > 
> > > > > > > The commit was generated with:
> > > > > > > 
> > > > > > > git grep -l MX6 -- configs/ | xargs grep -l SPL_FS_EXT4 | xargs 
> > > > > > > sed -i -e '/CONFIG_SPL_FS_EXT4=y/d'
> > > > > > > 
> > > > > > > This change has a dramatic impact on SPL size:
> > > > > > > 
> > > > > > > ./scripts/bloat-o-meter old new
> > > > > > > add/remove: 0/59 grow/shrink: 0/3 up/down: 0/-8674 (-8674)
> > > > > > > [..]
> > > > > > > Total: Before=38320, After=29646, chg -22.64%
> > > > > > > 
> > > > > > > Cc: Otavio Salvador 
> > > > > > > Cc: Fabio Estevam 
> > > > > > > Cc: Peng Fan 
> > > > > > > Cc: Marek Vasut 
> > > > > > > Cc: Stefano Babic 
> > > > > > > Cc: Stefan Roese 
> > > > > > > Cc: "Eric Bénard" 
> > > > > > > Cc: Breno Lima 
> > > > > > > Cc: Francesco Montefoschi 
> > > > > > > Signed-off-by: Ezequiel Garcia 
> > > > > > > ---
> > > > > > > Tested on Wandboard only. Maintainers, please ACK or NAK!
> > > > > > > 
> > > > > > >  configs/cgtqmx6eval_defconfig   | 1 -
> > > > > > >  configs/mx6cuboxi_defconfig | 1 -
> > > > > > >  configs/mx6sabreauto_defconfig  | 1 -
> > > > > > >  configs/mx6sabresd_defconfig| 1 -
> > > > > > >  configs/mx6slevk_spl_defconfig  | 1 -
> > > > > > >  configs/mx6sxsabresd_spl_defconfig  | 1 -
> > > > > > >  configs/mx6ul_14x14_evk_defconfig   | 1 -
> > > > > > >  configs/mx6ul_9x9_evk_defconfig | 1 -
> > > > > > >  configs/novena_defconfig| 1 -
> > > > > > 
> > > > > > NAK, I boot my Novena from ext4 and this just broke it.
> > > > > > 
> > > > > > And also, NAK, this removes functionality from SPL which worked 
> > > > > > fine before.
> > > > > > 
> > > > > 
> > > > > I'll drop from Novena, but I think the patch still makes some sense,
> > > > > why do you want Ext4 on SPL?
> > > > 
> > > > What other filesystem is available in SPL and doesn't have patent 
> > > > problems ?
> > > > 
> > > 
> > > Sorry for not being clear. I am asking why turn on a feature that is so 
> > > heavy,
> > > on a system that won't need it (such as Sabre* boards, Wandboard and 
> > > similar)?
> > 
> > Two reasons:
> > 1) It was enabled, disabling it means removing functionality for no good
> >reason (oops, bloat, is not a good reason), and that is not desired.
> > 2) Booting from block device implies booting from a filesystem,
> >otherwise you might overwrite various things on the block device when
> >updating the file (u-boot image).
> > 
> 
> They *could* be good reasons, but it depends on the use case. In case of
> Novena as Marek stated, it boots from filesystem and dropping this
> feature breaks definetly the board.
> 
> My position is that each board maintainer can take the decision what is
> necessary for the board he maintained. I think this should be done per
> each board, so just send single patches (not a compund as this one) just
> for the boards you want to drop ext4 (I guess just sabre and Wandboard).
> If the board maintainers agree (Fabio and Otavio), patches can be merged.
> 

I am dropping these changes. If board maintainers want to pursue this path,
it's up to them, as this clearly has heavier implications than I
originally thought.

Thanks,
Ezequiel

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Re: [U-Boot] [PATCH] configs: Remove CONFIG_SPL_FS_EXT4 for all MX6 platforms

[Ezequiel Garcia]

On Sun, 26 May 2019 at 14:30, Marek Vasut  wrote:
>
> On 5/26/19 6:18 PM, Ezequiel Garcia wrote:
> > On Sun, 26 May 2019 at 12:05, Lukasz Majewski  wrote:
> >>
> >> Hi Tom,
> >>
> >>> On Sun, May 26, 2019 at 01:46:53PM +0200, Lukasz Majewski wrote:
> >>>> Hi Tom,
> >>>>
> >>>>> On Sun, May 26, 2019 at 10:22:00AM +0200, Lukasz Majewski wrote:
> >>>>>> Dear Marek, Tom,
> >>>>>>
> >>>>>>> On 5/26/19 1:23 AM, Tom Rini wrote:
> >>>>>>>> On Sun, May 26, 2019 at 01:20:34AM +0200, Marek Vasut
> >>>>>>>> wrote:
> >>>>>>>>> On 5/26/19 1:08 AM, Tom Rini wrote:
> >>>>>>>>>> On Sun, May 26, 2019 at 12:57:08AM +0200, Marek Vasut
> >>>>>>>>>> wrote:
> >>>>>>>>>>> On 5/26/19 12:45 AM, Ezequiel Garcia wrote:
> >>>>>>>>>>>> On Sun, 2019-05-26 at 00:24 +0200, Marek Vasut
> >>>>>>>>>>>> wrote:
> >>>>>>>>>>>>> On 5/25/19 11:47 PM, Ezequiel Garcia wrote:
> >>>>>>>>>>>>>> On Sat, 2019-05-25 at 22:15 +0200, Marek Vasut
> >>>>>>>>>>>>>> wrote:
> >>>>>>>>>>>>>>> On 5/25/19 6:49 PM, Ezequiel Garcia wrote:
> >>>>>>>>>>>>>>>> i.MX6 platforms boot U-Boot second-stage from
> >>>>>>>>>>>>>>>> unformatted space, and should not need Ext
> >>>>>>>>>>>>>>>> filesystem support on SPL.
> >>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>> The commit was generated with:
> >>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>> git grep -l MX6 -- configs/ | xargs grep -l
> >>>>>>>>>>>>>>>> SPL_FS_EXT4 | xargs sed -i -e
> >>>>>>>>>>>>>>>> '/CONFIG_SPL_FS_EXT4=y/d'
> >>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>> This change has a dramatic impact on SPL size:
> >>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>> ./scripts/bloat-o-meter old new
> >>>>>>>>>>>>>>>> add/remove: 0/59 grow/shrink: 0/3 up/down: 0/-8674
> >>>>>>>>>>>>>>>> (-8674) [..]
> >>>>>>>>>>>>>>>> Total: Before=38320, After=29646, chg -22.64%
> >>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>> Cc: Otavio Salvador 
> >>>>>>>>>>>>>>>> Cc: Fabio Estevam 
> >>>>>>>>>>>>>>>> Cc: Peng Fan 
> >>>>>>>>>>>>>>>> Cc: Marek Vasut 
> >>>>>>>>>>>>>>>> Cc: Stefano Babic 
> >>>>>>>>>>>>>>>> Cc: Stefan Roese 
> >>>>>>>>>>>>>>>> Cc: "Eric Bénard" 
> >>>>>>>>>>>>>>>> Cc: Breno Lima 
> >>>>>>>>>>>>>>>> Cc: Francesco Montefoschi
> >>>>>>>>>>>>>>>>  Signed-off-by:
> >>>>>>>>>>>>>>>> Ezequiel Garcia  ---
> >>>>>>>>>>>>>>>> Tested on Wandboard only. Maintainers, please ACK or
> >>>>>>>>>>>>>>>> NAK!
> >>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>>  configs/cgtqmx6eval_defconfig   | 1 -
> >>>>>>>>>>>>>>>>  configs/mx6cuboxi_defconfig | 1 -
> >>>>>>>>>>>>>>>>  configs/mx6sabreauto_defconfig  | 1 -
> >>>>>>>>>>>>>>>>  configs/mx6sabresd_defconfig| 1 -
> >>>>>>>>&g

Re: [U-Boot] [PATCH] configs: Remove CONFIG_SPL_FS_EXT4 for all MX6 platforms

[Ezequiel Garcia]

On Sun, 26 May 2019 at 12:05, Lukasz Majewski  wrote:
>
> Hi Tom,
>
> > On Sun, May 26, 2019 at 01:46:53PM +0200, Lukasz Majewski wrote:
> > > Hi Tom,
> > >
> > > > On Sun, May 26, 2019 at 10:22:00AM +0200, Lukasz Majewski wrote:
> > > > > Dear Marek, Tom,
> > > > >
> > > > > > On 5/26/19 1:23 AM, Tom Rini wrote:
> > > > > > > On Sun, May 26, 2019 at 01:20:34AM +0200, Marek Vasut
> > > > > > > wrote:
> > > > > > >> On 5/26/19 1:08 AM, Tom Rini wrote:
> > > > > > >>> On Sun, May 26, 2019 at 12:57:08AM +0200, Marek Vasut
> > > > > > >>> wrote:
> > > > > > >>>> On 5/26/19 12:45 AM, Ezequiel Garcia wrote:
> > > > > > >>>>> On Sun, 2019-05-26 at 00:24 +0200, Marek Vasut
> > > > > > >>>>> wrote:
> > > > > > >>>>>> On 5/25/19 11:47 PM, Ezequiel Garcia wrote:
> > > > > > >>>>>>> On Sat, 2019-05-25 at 22:15 +0200, Marek Vasut
> > > > > > >>>>>>> wrote:
> > > > > > >>>>>>>> On 5/25/19 6:49 PM, Ezequiel Garcia wrote:
> > > > > > >>>>>>>>> i.MX6 platforms boot U-Boot second-stage from
> > > > > > >>>>>>>>> unformatted space, and should not need Ext
> > > > > > >>>>>>>>> filesystem support on SPL.
> > > > > > >>>>>>>>>
> > > > > > >>>>>>>>> The commit was generated with:
> > > > > > >>>>>>>>>
> > > > > > >>>>>>>>> git grep -l MX6 -- configs/ | xargs grep -l
> > > > > > >>>>>>>>> SPL_FS_EXT4 | xargs sed -i -e
> > > > > > >>>>>>>>> '/CONFIG_SPL_FS_EXT4=y/d'
> > > > > > >>>>>>>>>
> > > > > > >>>>>>>>> This change has a dramatic impact on SPL size:
> > > > > > >>>>>>>>>
> > > > > > >>>>>>>>> ./scripts/bloat-o-meter old new
> > > > > > >>>>>>>>> add/remove: 0/59 grow/shrink: 0/3 up/down: 0/-8674
> > > > > > >>>>>>>>> (-8674) [..]
> > > > > > >>>>>>>>> Total: Before=38320, After=29646, chg -22.64%
> > > > > > >>>>>>>>>
> > > > > > >>>>>>>>> Cc: Otavio Salvador 
> > > > > > >>>>>>>>> Cc: Fabio Estevam 
> > > > > > >>>>>>>>> Cc: Peng Fan 
> > > > > > >>>>>>>>> Cc: Marek Vasut 
> > > > > > >>>>>>>>> Cc: Stefano Babic 
> > > > > > >>>>>>>>> Cc: Stefan Roese 
> > > > > > >>>>>>>>> Cc: "Eric Bénard" 
> > > > > > >>>>>>>>> Cc: Breno Lima 
> > > > > > >>>>>>>>> Cc: Francesco Montefoschi
> > > > > > >>>>>>>>>  Signed-off-by:
> > > > > > >>>>>>>>> Ezequiel Garcia  ---
> > > > > > >>>>>>>>> Tested on Wandboard only. Maintainers, please ACK or
> > > > > > >>>>>>>>> NAK!
> > > > > > >>>>>>>>>
> > > > > > >>>>>>>>>  configs/cgtqmx6eval_defconfig   | 1 -
> > > > > > >>>>>>>>>  configs/mx6cuboxi_defconfig | 1 -
> > > > > > >>>>>>>>>  configs/mx6sabreauto_defconfig  | 1 -
> > > > > > >>>>>>>>>  configs/mx6sabresd_defconfig| 1 -
> > > > > > >>>>>>>>>  configs/mx6slevk_spl_defconfig  | 1 -
> > > > > > >>>>>>>>>  configs/mx6sxsabresd_spl_defconfig  | 1 -
> > > > > > >>>>>>>>>  configs/mx6ul_14x14_evk_defconfig   | 1 -
> > > > > > >>>>

Re: [U-Boot] [PATCH] configs: Remove CONFIG_SPL_FS_EXT4 for all MX6 platforms

[Ezequiel Garcia]

On Sun, 2019-05-26 at 00:24 +0200, Marek Vasut wrote:
> On 5/25/19 11:47 PM, Ezequiel Garcia wrote:
> > On Sat, 2019-05-25 at 22:15 +0200, Marek Vasut wrote:
> > > On 5/25/19 6:49 PM, Ezequiel Garcia wrote:
> > > > i.MX6 platforms boot U-Boot second-stage from unformatted space,
> > > > and should not need Ext filesystem support on SPL.
> > > > 
> > > > The commit was generated with:
> > > > 
> > > > git grep -l MX6 -- configs/ | xargs grep -l SPL_FS_EXT4 | xargs sed -i 
> > > > -e '/CONFIG_SPL_FS_EXT4=y/d'
> > > > 
> > > > This change has a dramatic impact on SPL size:
> > > > 
> > > > ./scripts/bloat-o-meter old new
> > > > add/remove: 0/59 grow/shrink: 0/3 up/down: 0/-8674 (-8674)
> > > > [..]
> > > > Total: Before=38320, After=29646, chg -22.64%
> > > > 
> > > > Cc: Otavio Salvador 
> > > > Cc: Fabio Estevam 
> > > > Cc: Peng Fan 
> > > > Cc: Marek Vasut 
> > > > Cc: Stefano Babic 
> > > > Cc: Stefan Roese 
> > > > Cc: "Eric Bénard" 
> > > > Cc: Breno Lima 
> > > > Cc: Francesco Montefoschi 
> > > > Signed-off-by: Ezequiel Garcia 
> > > > ---
> > > > Tested on Wandboard only. Maintainers, please ACK or NAK!
> > > > 
> > > >  configs/cgtqmx6eval_defconfig   | 1 -
> > > >  configs/mx6cuboxi_defconfig | 1 -
> > > >  configs/mx6sabreauto_defconfig  | 1 -
> > > >  configs/mx6sabresd_defconfig| 1 -
> > > >  configs/mx6slevk_spl_defconfig  | 1 -
> > > >  configs/mx6sxsabresd_spl_defconfig  | 1 -
> > > >  configs/mx6ul_14x14_evk_defconfig   | 1 -
> > > >  configs/mx6ul_9x9_evk_defconfig | 1 -
> > > >  configs/novena_defconfig| 1 -
> > > 
> > > NAK, I boot my Novena from ext4 and this just broke it.
> > > 
> > > And also, NAK, this removes functionality from SPL which worked fine 
> > > before.
> > > 
> > 
> > I'll drop from Novena, but I think the patch still makes some sense,
> > why do you want Ext4 on SPL?
> 
> What other filesystem is available in SPL and doesn't have patent problems ?
> 

Sorry for not being clear. I am asking why turn on a feature that is so heavy,
on a system that won't need it (such as Sabre* boards, Wandboard and similar)?

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[U-Boot] [PATCH 1/2] spl: Move SPL_MMC_TINY option to appear under SPL menu

[Ezequiel Garcia]

The SPL_MMC_TINY implements feature-reduced MMC support
on SPL, and as such, it's more consistent and convenient
to find it as part of the SPL configuration.

Signed-off-by: Ezequiel Garcia 
---
 common/spl/Kconfig  | 17 +
 drivers/mmc/Kconfig | 15 ---
 2 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c7cd34449a52..1408575dd511 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -515,6 +515,23 @@ config SPL_MMC_SUPPORT
  this option to build the drivers in drivers/mmc as part of an SPL
  build.
 
+config SPL_MMC_TINY
+   bool "Tiny MMC framework in SPL"
+   depends on SPL_MMC_SUPPORT
+   default n
+   help
+ Enable MMC framework tinification support. This option is useful if
+ if your SPL is extremely size constrained. Heed the warning, enable
+ this option if and only if you know exactly what you are doing, if
+ you are reading this help text, you most likely have no idea :-)
+
+ The MMC framework is reduced to bare minimum to be useful. No malloc
+ support is needed for the MMC framework operation with this option
+ enabled. The framework supports exactly one MMC device and exactly
+ one MMC driver. The MMC driver can be adjusted to avoid any malloc
+ operations too, which can remove the need for malloc support in SPL
+ and thus further reduce footprint.
+
 config SPL_MMC_WRITE
bool "MMC/SD/SDIO card support for write operations in SPL"
depends on SPL_MMC_SUPPORT
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c23299ea962b..76d8bff2eb83 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -158,21 +158,6 @@ config MMC_TRACE
 
  If you need to see the MMC core message, say Y.
 
-config SPL_MMC_TINY
-   bool "Tiny MMC framework in SPL"
-   help
- Enable MMC framework tinification support. This option is useful if
- if your SPL is extremely size constrained. Heed the warning, enable
- this option if and only if you know exactly what you are doing, if
- you are reading this help text, you most likely have no idea :-)
-
- The MMC framework is reduced to bare minimum to be useful. No malloc
- support is needed for the MMC framework operation with this option
- enabled. The framework supports exactly one MMC device and exactly
- one MMC driver. The MMC driver can be adjusted to avoid any malloc
- operations too, which can remove the need for malloc support in SPL
- and thus further reduce footprint.
-
 config MMC_DAVINCI
bool "TI DAVINCI Multimedia Card Interface support"
depends on ARCH_DAVINCI
-- 
2.20.1

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[U-Boot] [PATCH 2/2] mmc: Register only the first MMC device on MMC_TINY

[Ezequiel Garcia]

When MMC_TINY is enabled, support for only one MMC device
is provided. Boards that register more than one device,
will just write over mmc_static keeping only the last one
registered.

This commit prevents this, keeping only the first MMC
device created. A debug warning message is added, if nothing
else, as a hint/documentation for developers.

Signed-off-by: Ezequiel Garcia 
---
 drivers/mmc/mmc_legacy.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
index 66a7cda440cd..b0f5cf58a2b3 100644
--- a/drivers/mmc/mmc_legacy.c
+++ b/drivers/mmc/mmc_legacy.c
@@ -150,6 +150,15 @@ struct mmc *mmc_create(const struct mmc_config *cfg, void 
*priv)
 {
struct mmc *mmc = _static;
 
+   /* First MMC device registered, fail to register a new one.
+* Given users are not expecting this to fail, instead
+* of failing let's just return the only MMC device
+*/
+   if (mmc->cfg) {
+   debug("Warning: MMC_TINY doesn't support multiple MMC 
devices\n");
+   return mmc;
+   }
+
mmc->cfg = cfg;
mmc->priv = priv;
 
-- 
2.20.1

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[U-Boot] [PATCH] wandboard: Rework Makefile to prevent spl.o from being built

[Ezequiel Garcia]

The spl.c source was entirely conditioned by CONFIG_SPL_BUILD.
Change this moving CONFIG_SPL_BUILD to be used in the Makefile,
which is slightly cleaner and more readable.

Signed-off-by: Ezequiel Garcia 
---
 board/wandboard/Makefile | 3 ++-
 board/wandboard/spl.c| 3 ---
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile
index 6e886f729a85..c3d80536b3a3 100644
--- a/board/wandboard/Makefile
+++ b/board/wandboard/Makefile
@@ -2,4 +2,5 @@
 #
 # (C) Copyright 2013 Freescale Semiconductor, Inc.
 
-obj-y  := wandboard.o spl.o
+obj-y  := wandboard.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 000cb109fc15..7b0f15a5c4d1 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -20,7 +20,6 @@
 #include 
 #include 
 
-#if defined(CONFIG_SPL_BUILD)
 #include 
 /*
  * Driving strength:
@@ -513,5 +512,3 @@ int board_mmc_init(bd_t *bis)
 
return 0;
 }
-
-#endif
-- 
2.20.1

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Re: [U-Boot] [PATCH] configs: Remove CONFIG_SPL_FS_EXT4 for all MX6 platforms

[Ezequiel Garcia]

On Sat, 2019-05-25 at 22:15 +0200, Marek Vasut wrote:
> On 5/25/19 6:49 PM, Ezequiel Garcia wrote:
> > i.MX6 platforms boot U-Boot second-stage from unformatted space,
> > and should not need Ext filesystem support on SPL.
> > 
> > The commit was generated with:
> > 
> > git grep -l MX6 -- configs/ | xargs grep -l SPL_FS_EXT4 | xargs sed -i -e 
> > '/CONFIG_SPL_FS_EXT4=y/d'
> > 
> > This change has a dramatic impact on SPL size:
> > 
> > ./scripts/bloat-o-meter old new
> > add/remove: 0/59 grow/shrink: 0/3 up/down: 0/-8674 (-8674)
> > [..]
> > Total: Before=38320, After=29646, chg -22.64%
> > 
> > Cc: Otavio Salvador 
> > Cc: Fabio Estevam 
> > Cc: Peng Fan 
> > Cc: Marek Vasut 
> > Cc: Stefano Babic 
> > Cc: Stefan Roese 
> > Cc: "Eric Bénard" 
> > Cc: Breno Lima 
> > Cc: Francesco Montefoschi 
> > Signed-off-by: Ezequiel Garcia 
> > ---
> > Tested on Wandboard only. Maintainers, please ACK or NAK!
> > 
> >  configs/cgtqmx6eval_defconfig   | 1 -
> >  configs/mx6cuboxi_defconfig | 1 -
> >  configs/mx6sabreauto_defconfig  | 1 -
> >  configs/mx6sabresd_defconfig| 1 -
> >  configs/mx6slevk_spl_defconfig  | 1 -
> >  configs/mx6sxsabresd_spl_defconfig  | 1 -
> >  configs/mx6ul_14x14_evk_defconfig   | 1 -
> >  configs/mx6ul_9x9_evk_defconfig | 1 -
> >  configs/novena_defconfig| 1 -
> 
> NAK, I boot my Novena from ext4 and this just broke it.
> 
> And also, NAK, this removes functionality from SPL which worked fine before.
> 

I'll drop from Novena, but I think the patch still makes some sense,
why do you want Ext4 on SPL?

Thanks for the review,
Eze


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[U-Boot] [PATCH] configs: Remove CONFIG_SPL_FS_EXT4 for all MX6 platforms

[Ezequiel Garcia]

i.MX6 platforms boot U-Boot second-stage from unformatted space,
and should not need Ext filesystem support on SPL.

The commit was generated with:

git grep -l MX6 -- configs/ | xargs grep -l SPL_FS_EXT4 | xargs sed -i -e 
'/CONFIG_SPL_FS_EXT4=y/d'

This change has a dramatic impact on SPL size:

./scripts/bloat-o-meter old new
add/remove: 0/59 grow/shrink: 0/3 up/down: 0/-8674 (-8674)
[..]
Total: Before=38320, After=29646, chg -22.64%

Cc: Otavio Salvador 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Marek Vasut 
Cc: Stefano Babic 
Cc: Stefan Roese 
Cc: "Eric Bénard" 
Cc: Breno Lima 
Cc: Francesco Montefoschi 
Signed-off-by: Ezequiel Garcia 
---
Tested on Wandboard only. Maintainers, please ACK or NAK!

 configs/cgtqmx6eval_defconfig   | 1 -
 configs/mx6cuboxi_defconfig | 1 -
 configs/mx6sabreauto_defconfig  | 1 -
 configs/mx6sabresd_defconfig| 1 -
 configs/mx6slevk_spl_defconfig  | 1 -
 configs/mx6sxsabresd_spl_defconfig  | 1 -
 configs/mx6ul_14x14_evk_defconfig   | 1 -
 configs/mx6ul_9x9_evk_defconfig | 1 -
 configs/novena_defconfig| 1 -
 configs/pcm058_defconfig| 1 -
 configs/pfla02_defconfig| 1 -
 configs/platinum_picon_defconfig| 1 -
 configs/platinum_titanium_defconfig | 1 -
 configs/riotboard_spl_defconfig | 1 -
 configs/sksimx6_defconfig   | 1 -
 configs/udoo_defconfig  | 1 -
 configs/udoo_neo_defconfig  | 1 -
 configs/wandboard_defconfig | 1 -
 configs/xpress_spl_defconfig| 1 -
 configs/zc5202_defconfig| 1 -
 configs/zc5601_defconfig| 1 -
 21 files changed, 21 deletions(-)

diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 0a6ff20a4d42..cf8502b370f4 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -22,7 +22,6 @@ CONFIG_MISC_INIT_R=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index f13e6885071b..31427e24ad14 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -18,7 +18,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run 
distro_bootcmd"
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index d0f302e9d09b..303636511326 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -24,7 +24,6 @@ CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
-CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 0fda6fc3946e..c060d6f692d7 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -23,7 +23,6 @@ CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
-CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_USB_HOST_SUPPORT=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 4841dc62bf5c..fbf0e3e774c7 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6sxsabresd_spl_defconfig 
b/configs/mx6sxsabresd_spl_defconfig
index 159f07931a3b..51eb0726d658 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -18,7 +18,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6ul_14x14_evk_defconfig 
b/configs/mx6ul_14x14_evk_defconfig
index 2fc7119042a1..8735401bb71a 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -17,7 +17,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 8816f6a4fdec..c204b49e2bc9 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -17,7 +17,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_

Re: [U-Boot] [PATCH v2 1/3] mx6sabresd: Remove CONFIG_SPL_DM to decrease the SPL size

[Ezequiel Garcia]

On Fri, 2019-05-24 at 18:41 -0300, Fabio Estevam wrote:
> Hi Ezequiel,
> 
> On Fri, May 24, 2019 at 6:31 PM Ezequiel Garcia  
> wrote:
> 
> > Since we care about the SPL size, is there any reason why we have 
> > CONFIG_SPL_FS_EXT4?
> > 
> > AFAICS, u-boot.img is not on a filesystem, so why do we need ext2/3/4?
> 
> Yes, I will remove CONFIG_SPL_FS_EXT4 and CONFIG_SPL_I2C_SUPPORT=y in
> my next round of patches to reduce SPL size on mx6sabresd.
> 

Perhaps instead of per-board, we can check the MX6 lot.

PS: Not needed on Wandboard either, and I found a way to move to TINY_MMC.
Interestingly, and as we would expect, turning off EXT had more impact.


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Re: [U-Boot] [PATCH v2 1/3] mx6sabresd: Remove CONFIG_SPL_DM to decrease the SPL size

[Ezequiel Garcia]

On Tue, 2019-05-21 at 10:37 -0300, Fabio Estevam wrote:
> Currently the mx6qsabresd board does not boot:
> 
> U-Boot SPL 2019.07-rc2 (May 16 2019 - 14:28:55 -0300)
> Trying to boot from MMC1
> spl: could not find mmc device 0. error: -19
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
> 
> The reason for the boot failure is that that the SPL
> size got greater than the 68KB limit (4KB header + 64KB max
> size) as explained in include/configs/imx6_spl.h.
> 
> Remove the CONFIG_SPL_DM option, so that the SPL binary could
> fit into the allowed size and the board can boot again.
> 
> Signed-off-by: Fabio Estevam 
> ---
> Changes since v1:
> - Improve the commit log by explaining that the boot failure
> is caused by SPL size overflow
> 
>  configs/mx6sabresd_defconfig | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
> index d3ed3c4543..5c2d055561 100644
> --- a/configs/mx6sabresd_defconfig
> +++ b/configs/mx6sabresd_defconfig
> @@ -65,7 +65,6 @@ CONFIG_SPL_MULTI_DTB_FIT=y
>  CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
>  CONFIG_ENV_IS_IN_MMC=y
>  CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> -CONFIG_SPL_DM=y
>  CONFIG_USB_FUNCTION_FASTBOOT=y
>  CONFIG_FASTBOOT_BUF_ADDR=0x1200
>  CONFIG_FASTBOOT_BUF_SIZE=0x1000

Since we care about the SPL size, is there any reason why we have 
CONFIG_SPL_FS_EXT4?

AFAICS, u-boot.img is not on a filesystem, so why do we need ext2/3/4?

Thanks,
Eze

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Re: [U-Boot] Cannot boot mx6qsabred with 2019.07-rc2

[Ezequiel Garcia]

On Wed, 2019-05-22 at 11:15 -0400, Tom Rini wrote:
> On Wed, May 22, 2019 at 11:23:11AM -0300, Fabio Estevam wrote:
> > On Tue, May 21, 2019 at 11:34 PM Tom Rini  wrote:
> > 
> > > As came up in another thread, CONFIG_MMC_TINY may be more widely useable
> > > and should help with space.
> > 
> > How it can be used exactly?
> > 
> > I tried it like this:
> > 
> > --- a/configs/mx6sabresd_defconfig
> > +++ b/configs/mx6sabresd_defconfig
> > @@ -6,7 +6,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
> >  CONFIG_SPL_LIBGENERIC_SUPPORT=y
> >  CONFIG_SYS_MALLOC_F_LEN=0x4000
> >  CONFIG_TARGET_MX6SABRESD=y
> > -CONFIG_SPL_MMC_SUPPORT=y
> >  CONFIG_SPL_SERIAL_SUPPORT=y
> >  CONFIG_NR_DRAM_BANKS=1
> >  CONFIG_SPL=y
> > @@ -100,3 +99,4 @@ CONFIG_USB_HOST_ETHER=y
> >  CONFIG_USB_ETHER_ASIX=y
> >  CONFIG_DM_VIDEO=y
> >  CONFIG_VIDEO_IPUV3=y
> > +CONFIG_SPL_MMC_TINY=y
> > 
> > , but the board does not boot:
> > 
> > U-Boot SPL 2019.07-rc2-00164-ge1a2ed7180-dirty (May 22 2019 - 11:19:41 
> > -0300)
> > SPL: Unsupported Boot Device!
> > SPL: failed to boot from all boot devices
> > ### ERROR ### Please RESET the board ###
> 
> Yes, I was hoping to get Marek or Ezequiel to speak up a bit more on how
> to configure / use it, in the other thread.
> 

I was planning to look at this, and planned to start with a Wandboard I just 
happen
to have on my desk.

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Re: [U-Boot] [PATCH 0/2] MIPS: cleanup/optimise linker scripts

[Ezequiel Garcia]

On Sun, 2019-01-06 at 20:42 +0100, Daniel Schwierzeck wrote:
> Cleanup and optimise MIPS linker scripts and align them more with
> Linux.
> 
> Switch the CI20 board from the custom SPL linker script to the
> generic MIPS SPL linker script.
> 
> 

For both patches:

Tested-by: Ezequiel Garcia 

Thanks a lot!

> Daniel Schwierzeck (2):
>   MIPS: optimize and fix ELF sections
>   MIPS: jz47xx: remove custom u-boot-spl.lds
> 
>  arch/mips/cpu/u-boot-spl.lds| 100 ---
>  arch/mips/cpu/u-boot.lds| 104 +---
>  arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds |  50 --
>  configs/ci20_mmc_defconfig  |   1 -
>  4 files changed, 136 insertions(+), 119 deletions(-)
>  delete mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
> 


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[U-Boot] [PATCH 2/2] mmc: jz_mmc: Compile-out write support if disabled

[Ezequiel Garcia]

Do not build write support, unless it's enabled.

In the SPL case, this change will typically remove
precious bytes (as write support is most often
not needed in SPL).

This is important on this platform, where the maximum
SPL size is 14 KiB.

With gcc v7.3, this change saves 144 bytes producing:

size spl/u-boot-spl
   textdata bss dec hex filename
   9240 752 712   1070429d0 spl/u-boot-spl

To make the code easier to compile-out and more
readable, a pair of read_data/write_data helpers are created.

Signed-off-by: Ezequiel Garcia 
---
 drivers/mmc/jz_mmc.c | 105 +--
 1 file changed, 61 insertions(+), 44 deletions(-)

diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
index 3132c3e191ac..cb2a7c3eb5e1 100644
--- a/drivers/mmc/jz_mmc.c
+++ b/drivers/mmc/jz_mmc.c
@@ -134,6 +134,60 @@ static int jz_mmc_clock_rate(void)
return 2400;
 }
 
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data 
*data)
+{
+   int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
+   const void *buf = data->src;
+
+   while (sz--) {
+   u32 val = get_unaligned_le32(buf);
+
+   wait_for_bit_le32(priv->regs + MSC_IREG,
+ MSC_IREG_TXFIFO_WR_REQ,
+ true, 1, false);
+   writel(val, priv->regs + MSC_TXFIFO);
+   buf += 4;
+   }
+}
+#else
+static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
+{}
+#endif
+
+static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data 
*data)
+{
+   int sz = data->blocks * data->blocksize;
+   void *buf = data->dest;
+   u32 stat, val;
+
+   do {
+   stat = readl(priv->regs + MSC_STAT);
+
+   if (stat & MSC_STAT_TIME_OUT_READ)
+   return -ETIMEDOUT;
+   if (stat & MSC_STAT_CRC_READ_ERROR)
+   return -EINVAL;
+   if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
+   udelay(10);
+   continue;
+   }
+   do {
+   val = readl(priv->regs + MSC_RXFIFO);
+   if (sz == 1)
+   *(u8 *)buf = (u8)val;
+   else if (sz == 2)
+   put_unaligned_le16(val, buf);
+   else if (sz >= 4)
+   put_unaligned_le32(val, buf);
+   buf += 4;
+   sz -= 4;
+   stat = readl(priv->regs + MSC_STAT);
+   } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
+   } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
+   return 0;
+}
+
 static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
   struct mmc_cmd *cmd, struct mmc_data *data)
 {
@@ -249,51 +303,14 @@ static int jz_mmc_send_cmd(struct mmc *mmc, struct 
jz_mmc_priv *priv,
cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
}
}
-
-   if (data && (data->flags & MMC_DATA_WRITE)) {
-   /* write the data */
-   int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
-   const void *buf = data->src;
-
-   while (sz--) {
-   u32 val = get_unaligned_le32(buf);
-
-   wait_for_bit_le32(priv->regs + MSC_IREG,
- MSC_IREG_TXFIFO_WR_REQ,
- true, 1, false);
-   writel(val, priv->regs + MSC_TXFIFO);
-   buf += 4;
+   if (data) {
+   if (data->flags & MMC_DATA_WRITE)
+   jz_mmc_write_data(priv, data);
+   else if (data->flags & MMC_DATA_READ) {
+   ret = jz_mmc_read_data(priv, data);
+   if (ret)
+   return ret;
}
-   } else if (data && (data->flags & MMC_DATA_READ)) {
-   /* read the data */
-   int sz = data->blocks * data->blocksize;
-   void *buf = data->dest;
-
-   do {
-   stat = readl(priv->regs + MSC_STAT);
-
-   if (stat & MSC_STAT_TIME_OUT_READ)
-   return -ETIMEDOUT;
-   if (stat & MSC_STAT_CRC_READ_ERROR)
-   return -EINVAL;
-   if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
-   udelay(10);
-   continue;
-   }
-   do {
-   

[U-Boot] [PATCH 1/2] mmc: Use proper IS_ENABLED macro to check block support

[Ezequiel Garcia]

Use CONFIG_IS_ENABLED(BLK) instead of CONFIG_BLK,
in order to fix the following build issues when
CONFIG_SPL_MMC_WRITE is selected:

drivers/mmc/mmc_write.c:69:7: error: conflicting types for 'mmc_berase'
 ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
   ^~
In file included from drivers/mmc/mmc_write.c:15:0:
drivers/mmc/mmc_private.h:39:7: note: previous declaration of 'mmc_berase' was 
here
 ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt);
   ^~
drivers/mmc/mmc_write.c:187:7: error: conflicting types for 'mmc_bwrite'
 ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
   ^~
In file included from drivers/mmc/mmc_write.c:15:0:
drivers/mmc/mmc_private.h:37:7: note: previous declaration of 'mmc_bwrite' was 
here
 ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
   ^~

Signed-off-by: Ezequiel Garcia 
---
 drivers/mmc/mmc_write.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index b8acc33c76d0..c8c83c9188ec 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -65,13 +65,13 @@ err_out:
return err;
 }
 
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
 ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
 #else
 ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
 #endif
 {
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 #endif
int dev_num = block_dev->devnum;
@@ -183,7 +183,7 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t 
start,
return blkcnt;
 }
 
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
 ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
 const void *src)
 #else
@@ -191,7 +191,7 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t 
start, lbaint_t blkcnt,
 const void *src)
 #endif
 {
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 #endif
int dev_num = block_dev->devnum;
-- 
2.20.1

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Re: [U-Boot] [PATCH v3 0/5] Add support for MIPS Creator CI20

[Ezequiel Garcia]

On Tue, 2018-12-18 at 01:05 +0100, Daniel Schwierzeck wrote:
> 
> Am 16.12.18 um 23:25 schrieb Ezequiel Garcia:
> > A new round, addressing feedback from Daniel.
> > 
> > Daniel: do you think this is acceptable as a first submission?
> > 
> > v3:
> >  * Cleanup SoC reset logic.
> >  * Move gpio driver to SoC specific code, to be used by SPL.
> >A proper dm gpio driver will be added later.
> >  * Cleaned up SPDX.
> >  * Added myself as JZ4780 maintainer.
> >  * Added TODO file.
> > 
> > v2:
> > 
> >  * Replaced infinite while loop with wait_for_bit.
> >  * Added a MAINTAINERS file. If anyone wants to co-maintain this,
> >please let me know.
> > 
> > This is based on master and has been tested by SD-card booting
> > both U-Boot and Linux. Booting Linux via TFTP was also tested.
> > 
> > I've pushed a branch to 
> > https://github.com/ezequielgarcia/u-boot/tree/ci20-v3
> > and started travis.
> > 
> > Note that Paul's contributions are recorded using his imgtec.com
> > mail although it's no longer valid, and that we will rely on mailmap
> > to map it to mips.com.
> > 
> > It would be terrific to fit this on the next release.
> > 
> > Thanks!
> > 
> > Paul Burton (5):
> >   misc: Add JZ47xx efuse driver
> >   mmc: Add JZ47xx SD/MMC controller driver
> >   mips: Add SPL header
> >   mips: jz47xx: Add JZ4780 SoC support
> >   mips: jz47xx: Add Creator CI20 platform
> 
> applied to u-boot-mips, thanks.
> 
> I fixed some additional SPDX license identifiers because not all files
> got updated ;) I also fixed some minor checkpatch.pl issues.
> 
> I renamed the defconfig to ci20_mmc to clearly indicate the MMC boot
> mode in case someone wants to add boot from NAND or USB later. The
> latter could be useful for developing. I hope you don't mind ;)
> 

Great. I had the intention to rename the defconfig, but then
I forgot about it, so thanks.

> I also moved CONFIG_MISC_INIT_R from ci20.h to defconfig as this option
> has been converted to Kconfig some time ago. Finally I enabled cmd_dm to
> quickly test current DM integration.
> 

Cool.

> The updated series still booted on my rev1 board.
> 
> Maybe one of the next improvements should be to enable
> CONFIG_DISTRO_DEFAULTS and CONFIG_MIPS_BOOT_FDT.
> 

OK. Let me take a look at that.

Thanks,
Ezequiel

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[U-Boot] [PATCH v3 5/5] mips: jz47xx: Add Creator CI20 platform

[Ezequiel Garcia]

From: Paul Burton 

Add support for the Creator CI20 platform based on the JZ4780 SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 120 +++
 arch/mips/mach-jz47xx/Kconfig |  11 ++
 board/imgtec/ci20/Kconfig |  15 ++
 board/imgtec/ci20/MAINTAINERS |   6 +
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 +
 board/imgtec/ci20/ci20.c  | 362 ++
 configs/ci20_defconfig|  46 +
 include/configs/ci20.h|  73 +++
 10 files changed, 649 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/MAINTAINERS
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 include/configs/ci20.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b447141f8717..647d2bf0d53b 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts
new file mode 100644
index ..934d9e96d24d
--- /dev/null
+++ b/arch/mips/dts/ci20.dts
@@ -0,0 +1,120 @@
+/dts-v1/;
+
+#include "jz4780.dtsi"
+
+/ {
+   compatible = "img,ci20", "ingenic,jz4780";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   chosen {
+   stdout-path = "serial4:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x0 0x1000
+  0x3000 0x3000>;
+   };
+};
+
+ {
+   clock-frequency = <4800>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+
+   nandc: nand-controller@1 {
+   compatible = "ingenic,jz4780-nand";
+   reg = <1 0 0x100>;
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ingenic,bch-controller = <>;
+
+   ingenic,nemc-tAS = <10>;
+   ingenic,nemc-tAH = <5>;
+   ingenic,nemc-tBP = <10>;
+   ingenic,nemc-tAW = <15>;
+   ingenic,nemc-tSTRV = <100>;
+
+   nand@1 {
+   reg = <1>;
+
+   nand-ecc-step-size = <1024>;
+   nand-ecc-strength = <24>;
+   nand-ecc-mode = "hw";
+   nand-on-flash-bbt;
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   partition@0 {
+   label = "u-boot-spl";
+   reg = <0x0 0x0 0x0 0x80>;
+   };
+
+   partition@0x80 {
+   label = "u-boot";
+   reg = <0x0 0x80 0x0 0x20>;
+   };
+
+   partition@0xa0 {
+   label = "u-boot-env";
+   reg = <0x0 0xa0 0x0 0x20>;
+   };
+
+   partition@0xc0 {
+   label = "boot";
+   reg = <0x0 0xc0 0x0 0x400>;
+   };
+
+   partition@0x8c0 {
+   label = "system";
+   reg = <0x0 0x4c0 0x1 0xfb40>;
+   };
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   bus-width = <4>;
+   max-frequency = <5000>;
+   status = "okay";
+};
+
+ {
+ 

[U-Boot] [PATCH v3 4/5] mips: jz47xx: Add JZ4780 SoC support

[Ezequiel Garcia]

From: Paul Burton 

Add initial support for the Ingenic JZ47xx MIPS SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 MAINTAINERS   |   6 +
 arch/mips/Kconfig |   7 +
 arch/mips/Makefile|   1 +
 arch/mips/dts/jz4780.dtsi | 162 ++
 arch/mips/mach-jz47xx/Kconfig |  15 +
 arch/mips/mach-jz47xx/Makefile|   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h   | 103 
 .../mach-jz47xx/include/mach/jz4780_dram.h| 456 +++
 .../mach-jz47xx/include/mach/jz4780_gpio.h|  12 +
 arch/mips/mach-jz47xx/jz4780/Makefile |   5 +
 arch/mips/mach-jz47xx/jz4780/TODO |   4 +
 arch/mips/mach-jz47xx/jz4780/gpio.c   |  39 ++
 arch/mips/mach-jz47xx/jz4780/jz4780.c |  82 +++
 arch/mips/mach-jz47xx/jz4780/pll.c| 527 ++
 arch/mips/mach-jz47xx/jz4780/reset.c  |  53 ++
 arch/mips/mach-jz47xx/jz4780/sdram.c  | 270 +
 arch/mips/mach-jz47xx/jz4780/timer.c  | 237 
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds   |  52 ++
 arch/mips/mach-jz47xx/start.S |  99 
 include/dt-bindings/clock/jz4780-cgu.h|  88 +++
 20 files changed, 2225 insertions(+)
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_gpio.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/TODO
 create mode 100644 arch/mips/mach-jz47xx/jz4780/gpio.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/reset.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 0cec39c542db..3809a12f9ee7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -512,6 +512,12 @@ S: Maintained
 T: git git://git.denx.de/u-boot-mips.git
 F: arch/mips/
 
+MIPS JZ4780
+M: Ezequiel Garcia 
+S: Maintained
+T: git git://git.denx.de/u-boot-mips.git
+F: arch/mips/mach-jz47xx/
+
 MMC
 M: Jaehoon Chung 
 S: Maintained
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b1b1d7d0031..44b25460b8cc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -88,6 +88,12 @@ config ARCH_MT7620
select SUPPORTS_LITTLE_ENDIAN
select SYSRESET
 
+config ARCH_JZ47XX
+   bool "Support Ingenic JZ47xx"
+   select SUPPORT_SPL
+   select OF_CONTROL
+   select DM
+
 config MACH_PIC32
bool "Support Microchip PIC32"
select DM
@@ -139,6 +145,7 @@ source "board/micronas/vct/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
 source "arch/mips/mach-bmips/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 source "arch/mips/mach-mt7620/Kconfig"
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 802244a06e5d..a294e9b1e8b9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -13,6 +13,7 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_ARCH_BMIPS) += bmips
+machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
 machine-$(CONFIG_ARCH_MT7620) += mt7620
 
diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
new file mode 100644
index ..e34f8d359036
--- /dev/null
+++ b/arch/mips/dts/jz4780.dtsi
@@ -0,0 +1,162 @@
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "ingenic,jz4780";
+
+   cpuintc: interrupt-controller {
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "mti,cpu-interrupt-controller";
+   };
+
+   intc: interrupt-controller@10001000 {
+   compatible = "ingenic,jz4780-intc";
+   reg = <0x10001000 0x50>;
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interrupt-parent = <>;
+   interrupts = <2>;
+   };
+
+   ext: ext {
+   compatible = "fixed-clock";
+ 

[U-Boot] [PATCH v3 2/5] mmc: Add JZ47xx SD/MMC controller driver

[Ezequiel Garcia]

From: Paul Burton 

Add driver for the JZ47xx MSC controller.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   1 +
 drivers/mmc/jz_mmc.  |   0
 drivers/mmc/jz_mmc.c | 489 +++
 4 files changed, 496 insertions(+)
 create mode 100644 drivers/mmc/jz_mmc.
 create mode 100644 drivers/mmc/jz_mmc.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index fbd13964a084..496b2cba6405 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -332,6 +332,12 @@ config MMC_BCM2835
 
  If unsure, say N.
 
+config JZ47XX_MMC
+   bool "Ingenic JZ47xx SD/MMC Host Controller support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the SD Card Controller on Ingenic JZ47xx 
SoCs.
+
 config MMC_SANDBOX
bool "Sandbox MMC support"
depends on SANDBOX
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 801a26d82192..7892c468f05c 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
 obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
+obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
diff --git a/drivers/mmc/jz_mmc. b/drivers/mmc/jz_mmc.
new file mode 100644
index ..e69de29bb2d1
diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
new file mode 100644
index ..2e92fa16e6c8
--- /dev/null
+++ b/drivers/mmc/jz_mmc.c
@@ -0,0 +1,489 @@
+/*
+ * Ingenic JZ MMC driver
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Registers */
+#define MSC_STRPCL 0x000
+#define MSC_STAT   0x004
+#define MSC_CLKRT  0x008
+#define MSC_CMDAT  0x00c
+#define MSC_RESTO  0x010
+#define MSC_RDTO   0x014
+#define MSC_BLKLEN 0x018
+#define MSC_NOB0x01c
+#define MSC_SNOB   0x020
+#define MSC_IMASK  0x024
+#define MSC_IREG   0x028
+#define MSC_CMD0x02c
+#define MSC_ARG0x030
+#define MSC_RES0x034
+#define MSC_RXFIFO 0x038
+#define MSC_TXFIFO 0x03c
+#define MSC_LPM0x040
+#define MSC_DMAC   0x044
+#define MSC_DMANDA 0x048
+#define MSC_DMADA  0x04c
+#define MSC_DMALEN 0x050
+#define MSC_DMACMD 0x054
+#define MSC_CTRL2  0x058
+#define MSC_RTCNT  0x05c
+#define MSC_DBG0x0fc
+
+/* MSC Clock and Control Register (MSC_STRPCL) */
+#define MSC_STRPCL_EXIT_MULTIPLE   BIT(7)
+#define MSC_STRPCL_EXIT_TRANSFER   BIT(6)
+#define MSC_STRPCL_START_READWAIT  BIT(5)
+#define MSC_STRPCL_STOP_READWAIT   BIT(4)
+#define MSC_STRPCL_RESET   BIT(3)
+#define MSC_STRPCL_START_OPBIT(2)
+#define MSC_STRPCL_CLOCK_CONTROL_STOP  BIT(0)
+#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
+
+/* MSC Status Register (MSC_STAT) */
+#define MSC_STAT_AUTO_CMD_DONE BIT(31)
+#define MSC_STAT_IS_RESETTING  BIT(15)
+#define MSC_STAT_SDIO_INT_ACTIVE   BIT(14)
+#define MSC_STAT_PRG_DONE  BIT(13)
+#define MSC_STAT_DATA_TRAN_DONEBIT(12)
+#define MSC_STAT_END_CMD_RES   BIT(11)
+#define MSC_STAT_DATA_FIFO_AFULL   BIT(10)
+#define MSC_STAT_IS_READWAIT   BIT(9)
+#define MSC_STAT_CLK_ENBIT(8)
+#define MSC_STAT_DATA_FIFO_FULLBIT(7)
+#define MSC_STAT_DATA_FIFO_EMPTY   BIT(6)
+#define MSC_STAT_CRC_RES_ERR   BIT(5)
+#define MSC_STAT_CRC_READ_ERRORBIT(4)
+#define MSC_STAT_CRC_WRITE_ERROR   BIT(2)
+#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
+#define MSC_STAT_TIME_OUT_RES  BIT(1)
+#define MSC_STAT_TIME_OUT_READ BIT(0)
+
+/* MSC Bus Clock Control Register (MSC_CLKRT) */
+#define MSC_CLKRT_CLK_RATE_MASK0x7
+
+/* MSC Command Sequence Control Register (MSC_CMDAT) */
+#define MSC_CMDAT_IO_ABORT BIT(11)
+#define MSC_CMDAT_BUS_WIDTH_1BIT   (0x0 << 9)
+#define MSC_CMDAT_BUS_WIDTH_4BIT   (0x2 << 9)
+#define MSC_CMDAT_DMA_EN   BIT(8)
+#define MSC_CMDAT_INIT BIT(7)
+#define MSC_CMDAT_BUSY BIT(6)
+#define MSC_CMDAT_STREAM_BLOCK

[U-Boot] [PATCH v3 1/5] misc: Add JZ47xx efuse driver

[Ezequiel Garcia]

From: Paul Burton 

Add driver for the efuse block in the JZ47xx SOC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 drivers/misc/Kconfig|   6 +++
 drivers/misc/Makefile   |   1 +
 drivers/misc/jz4780_efuse.c | 104 
 3 files changed, 111 insertions(+)
 create mode 100644 drivers/misc/jz4780_efuse.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 48febc47d263..704c8dd1955f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -120,6 +120,12 @@ config FSL_SEC_MON
  Security Monitor can be transitioned on any security failures,
  like software violations or hardware security violations.
 
+config JZ4780_EFUSE
+   bool "Ingenic JZ4780 eFUSE support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the eFUSE on Ingenic JZ4780 SoCs.
+
 config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 302d44159274..6bdf5054f475 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -62,3 +62,4 @@ obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
 obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c
new file mode 100644
index ..7b327f54b15c
--- /dev/null
+++ b/drivers/misc/jz4780_efuse.c
@@ -0,0 +1,104 @@
+/*
+ * JZ4780 EFUSE driver
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ * Author: Alex Smith 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define EFUSE_EFUCTRL  0xd0
+#define EFUSE_EFUCFG   0xd4
+#define EFUSE_EFUSTATE 0xd8
+#define EFUSE_EFUDATA(n)   (0xdc + ((n) * 4))
+
+#define EFUSE_EFUCTRL_RD_ENBIT(0)
+#define EFUSE_EFUCTRL_LEN_BIT  16
+#define EFUSE_EFUCTRL_LEN_MASK 0x1f
+#define EFUSE_EFUCTRL_ADDR_BIT 21
+#define EFUSE_EFUCTRL_ADDR_MASK0x1ff
+#define EFUSE_EFUCTRL_CS   BIT(30)
+
+#define EFUSE_EFUCFG_RD_STROBE_BIT 16
+#define EFUSE_EFUCFG_RD_STROBE_MASK0xf
+#define EFUSE_EFUCFG_RD_ADJ_BIT20
+#define EFUSE_EFUCFG_RD_ADJ_MASK   0xf
+
+#define EFUSE_EFUSTATE_RD_DONE BIT(0)
+
+static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   size_t i;
+   u32 val;
+   int ret;
+
+   val = EFUSE_EFUCTRL_RD_EN |
+ ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
+ (addr << EFUSE_EFUCTRL_ADDR_BIT) |
+ ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
+   writel(val, regs + EFUSE_EFUCTRL);
+
+   ret = wait_for_bit_le32(regs + EFUSE_EFUSTATE,
+   EFUSE_EFUSTATE_RD_DONE, true, 1, false);
+   if (ret)
+   return;
+
+   if ((count % 4) == 0) {
+   for (i = 0; i < count / 4; i++) {
+   val = readl(regs + EFUSE_EFUDATA(i));
+   put_unaligned(val, (u32 *)(buf + (i * 4)));
+   }
+   } else {
+   val = readl(regs + EFUSE_EFUDATA(0));
+   if (count > 2)
+   buf[2] = (val >> 16) & 0xff;
+   if (count > 1)
+   buf[1] = (val >> 8) & 0xff;
+   buf[0] = val & 0xff;
+   }
+}
+
+static inline int jz4780_efuse_chunk_size(size_t count)
+{
+   if (count >= 32)
+   return 32;
+   else if ((count / 4) > 0)
+   return (count / 4) * 4;
+   else
+   return count % 4;
+}
+
+void jz4780_efuse_read(size_t addr, size_t count, u8 *buf)
+{
+   size_t chunk;
+
+   while (count > 0) {
+   chunk = jz4780_efuse_chunk_size(count);
+   jz4780_efuse_read_chunk(addr, chunk, buf);
+   addr += chunk;
+   buf += chunk;
+   count -= chunk;
+   }
+}
+
+void jz4780_efuse_init(u32 ahb2_rate)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   u32 rd_adj, rd_strobe, tmp;
+
+   rd_adj = (((6500 * (ahb2_rate / 100)) / 100) + 0xf) / 2;
+   tmp = (((35000 * (ahb2_rate / 100)) / 100) - 4) - rd_adj;
+   rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2;
+
+   tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) |
+ (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT);
+   writel(tmp, regs + EFUSE_EFUCFG);
+}
-- 
2.20.0

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[U-Boot] [PATCH v3 3/5] mips: Add SPL header

[Ezequiel Garcia]

From: Paul Burton 

Add header with SPL boot mode and type definitions.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
---
 arch/mips/include/asm/spl.h | 35 +++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/mips/include/asm/spl.h

diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h
new file mode 100644
index ..01baab606606
--- /dev/null
+++ b/arch/mips/include/asm/spl.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef_ASM_SPL_H_
+#define_ASM_SPL_H_
+
+enum {
+   BOOT_DEVICE_RAM,
+   BOOT_DEVICE_MMC1,
+   BOOT_DEVICE_MMC2,
+   BOOT_DEVICE_MMC2_2,
+   BOOT_DEVICE_NAND,
+   BOOT_DEVICE_ONENAND,
+   BOOT_DEVICE_NOR,
+   BOOT_DEVICE_UART,
+   BOOT_DEVICE_SPI,
+   BOOT_DEVICE_USB,
+   BOOT_DEVICE_SATA,
+   BOOT_DEVICE_I2C,
+   BOOT_DEVICE_BOARD,
+   BOOT_DEVICE_NONE
+};
+
+/* Linker symbols. */
+extern char __bss_start[];
+extern ulong __bss_end;
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif
-- 
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[U-Boot] [PATCH v3 0/5] Add support for MIPS Creator CI20

[Ezequiel Garcia]

A new round, addressing feedback from Daniel.

Daniel: do you think this is acceptable as a first submission?

v3:
 * Cleanup SoC reset logic.
 * Move gpio driver to SoC specific code, to be used by SPL.
   A proper dm gpio driver will be added later.
 * Cleaned up SPDX.
 * Added myself as JZ4780 maintainer.
 * Added TODO file.

v2:

 * Replaced infinite while loop with wait_for_bit.
 * Added a MAINTAINERS file. If anyone wants to co-maintain this,
   please let me know.

This is based on master and has been tested by SD-card booting
both U-Boot and Linux. Booting Linux via TFTP was also tested.

I've pushed a branch to https://github.com/ezequielgarcia/u-boot/tree/ci20-v3
and started travis.

Note that Paul's contributions are recorded using his imgtec.com
mail although it's no longer valid, and that we will rely on mailmap
to map it to mips.com.

It would be terrific to fit this on the next release.

Thanks!

Paul Burton (5):
  misc: Add JZ47xx efuse driver
  mmc: Add JZ47xx SD/MMC controller driver
  mips: Add SPL header
  mips: jz47xx: Add JZ4780 SoC support
  mips: jz47xx: Add Creator CI20 platform

 MAINTAINERS   |   6 +
 arch/mips/Kconfig |   7 +
 arch/mips/Makefile|   1 +
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 120 
 arch/mips/dts/jz4780.dtsi | 162 ++
 arch/mips/include/asm/spl.h   |  35 ++
 arch/mips/mach-jz47xx/Kconfig |  26 +
 arch/mips/mach-jz47xx/Makefile|   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h   | 103 
 .../mach-jz47xx/include/mach/jz4780_dram.h| 456 +++
 .../mach-jz47xx/include/mach/jz4780_gpio.h|  12 +
 arch/mips/mach-jz47xx/jz4780/Makefile |   5 +
 arch/mips/mach-jz47xx/jz4780/TODO |   4 +
 arch/mips/mach-jz47xx/jz4780/gpio.c   |  39 ++
 arch/mips/mach-jz47xx/jz4780/jz4780.c |  82 +++
 arch/mips/mach-jz47xx/jz4780/pll.c| 527 ++
 arch/mips/mach-jz47xx/jz4780/reset.c  |  53 ++
 arch/mips/mach-jz47xx/jz4780/sdram.c  | 270 +
 arch/mips/mach-jz47xx/jz4780/timer.c  | 237 
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds   |  52 ++
 arch/mips/mach-jz47xx/start.S |  99 
 board/imgtec/ci20/Kconfig |  15 +
 board/imgtec/ci20/MAINTAINERS |   6 +
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 +
 board/imgtec/ci20/ci20.c  | 362 
 configs/ci20_defconfig|  46 ++
 drivers/misc/Kconfig  |   6 +
 drivers/misc/Makefile |   1 +
 drivers/misc/jz4780_efuse.c   | 104 
 drivers/mmc/Kconfig   |   6 +
 drivers/mmc/Makefile  |   1 +
 drivers/mmc/jz_mmc.   |   0
 drivers/mmc/jz_mmc.c  | 489 
 include/configs/ci20.h|  73 +++
 include/dt-bindings/clock/jz4780-cgu.h|  88 +++
 37 files changed, 3516 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/include/asm/spl.h
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_gpio.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/TODO
 create mode 100644 arch/mips/mach-jz47xx/jz4780/gpio.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/reset.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/MAINTAINERS
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 drivers/misc/jz4780_efuse.c
 create mode 100644 drivers/mmc/jz_mmc.
 create mode 100644 drivers/mmc/jz_mmc.c
 create mode 100644 include/configs/ci20.h
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

-- 
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Re: [U-Boot] [PATCH v2 0/6] Add support for MIPS Creator CI20

[Ezequiel Garcia]

Hi Daniel,

On Wed, 2018-12-12 at 18:27 +0100, Daniel Schwierzeck wrote:
> Hi Ezequiel,
> 
> Am 12.12.18 um 14:58 schrieb Ezequiel Garcia:
> > A new round.
> > 
> > For this new round:
> > 
> >  * Replaced infinite while loop with wait_for_bit.
> >  * Added a MAINTAINERS file. If anyone wants to co-maintain this,
> >please let me know.
> > 
> > This is based on top of yesterday's master (ee168783ae8) and has
> > been tested by SD-card booting both U-Boot and Linux. Booting
> > Linux via TFTP was also tested.
> > 
> > Toolchain used to test:
> > 
> > $ mips-linux-gcc -v
> > Using built-in specs.
> > COLLECT_GCC=mips-linux-gcc
> > COLLECT_LTO_WRAPPER=/home/zeta/.buildman-toolchains/gcc-7.3.0-nolibc/mips-linux/bin/../libexec/gcc/mips-linux/7.3.0/lto-wrapper
> > Target: mips-linux
> > Configured with: /home/arnd/git/gcc/configure --target=mips-linux 
> > --enable-targets=all --prefix=/opt/crosstool/gcc-7.3.0-nolibc/mips-linux --
> > enable-languages=c --without-headers --disable-bootstrap --disable-nls 
> > --disable-threads --disable-shared --disable-libmudflap --disable-libssp --
> > disable-libgomp --disable-decimal-float --disable-libquadmath 
> > --disable-libatomic --disable-libcc1 --disable-libmpx 
> > --enable-checking=release
> > Thread model: single
> > gcc version 7.3.0 (GCC) 
> > 
> > SPL size:
> > 
> > $ size spl/u-boot-spl
> >textdata bss dec hex filename
> >9252 752 736   1074029f4 spl/u-boot-spl
> > 
> > I've pushed a branch to 
> > https://github.com/ezequielgarcia/u-boot/tree/ci20-v2
> > and made sure travis passed.
> > 
> 
> Thanks for working on this but the problem with the original patch
> series was that it was not fully driver model compatible and that stuff
> like watchdog, reset and pin-muxing was open-coded instead of using the
> proper frameworks. As the ship is sailing towards having only driver
> model and device tree in U-Boot proper, it doesn't make sense to accept
> new SoC/boards with legacy code especially if there is no active
> maintainer who would do the conversion work. And with the upcoming dead
> lines for DM conversions, boards with legacy code will be removed when
> not converted. This is also one of the reasons why the Ingenic SoC
> support we already had in mainline was removed. And readding parts of
> the removed code doesn't make sense either because the patch series is
> based on that old Ingenic SoC code.
> 

I have to say I disagree with all of this.

The open coded drivers are used in SPL, which most likely can't affort
any DM. Or **if** it can't afford it, it's a separate question that
needs research.

The BootROM for this SoC can only load 14 KiB of code, and we are already
at roughly 11 KiB.

This series, on the other side, is quite clean, quite small, has quite
simple drivers (with even a DM MMC driver for the second stage)...
... and most importantly it works.

Given how much history this particular series has, if we delay it now
with yet more requirements, we risk not ever having it.

We want to put this board on kernelCI labs, and having upstream U-Boot
would be really nice for that, so we don't rely on ancient vendor forks.

As for a maintainer doing the work, I'm here and not going anywhere.
I can do any follow-up work that's considered needed, including any DM
conversions.

But, it would be really important to have a working starting point.

> I wanted to work on Marek's patch series to fix those issues because
> it's quite some work which I couldn't expect from Marek ;)
> But I got stuck with EJTAG because halting the CPU didn't work. Then I
> hadn't time anymore.
> 
> I'm little busy right now so I can't do a detailed review. But the
> issues which should be addressed at first are:
> 
> - fix all SPDX license identifiers
> - convert GPIO driver to DM
> - add a DM watchdog driver
> - implement machine reset with the generic watchdog reset (see BMIPS for
> an example)
> - don't use SoC specific start.S and u-boot-spl.lds, the generic code is
> now configurable enough and non-generic things could be done in a
> lowlevel_init.S
> - reduce the hundreds of definitions of register addresses to the ones
> really needed in assembly or SPL. This stuff should come from device tree
> - define the remaining register base addresses as physical addresses and
> establish a mapping with ioremap_nocache()
> 
> 

This really sounds that work that can be done as follow-up patches.
And, we don't know if any of this will bloat the SPL beyond the current
limit :-)

I must admit, I have a hard time understanding this blocker policy,
for a series that gives support to a new board, and affects no other platforms.

Thanks,
Ezequiel

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[U-Boot] [PATCH v2 5/6] mips: jz47xx: Add JZ4780 SoC support

[Ezequiel Garcia]

From: Paul Burton 

Add initial support for the Ingenic JZ47xx MIPS SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
Reviewed-by: Marek Vasut 
---
 arch/mips/Kconfig |   7 +
 arch/mips/Makefile|   1 +
 arch/mips/dts/jz4780.dtsi | 162 ++
 arch/mips/mach-jz47xx/Kconfig |  15 +
 arch/mips/mach-jz47xx/Makefile|   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h   | 104 
 .../mach-jz47xx/include/mach/jz4780_dram.h| 457 +++
 arch/mips/mach-jz47xx/jz4780/Makefile |   5 +
 arch/mips/mach-jz47xx/jz4780/jz4780.c | 142 +
 arch/mips/mach-jz47xx/jz4780/pll.c| 528 ++
 arch/mips/mach-jz47xx/jz4780/sdram.c  | 271 +
 arch/mips/mach-jz47xx/jz4780/timer.c  | 238 
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds   |  52 ++
 arch/mips/mach-jz47xx/start.S |  99 
 include/dt-bindings/clock/jz4780-cgu.h|  88 +++
 15 files changed, 2176 insertions(+)
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b1b1d7d0031..44b25460b8cc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -88,6 +88,12 @@ config ARCH_MT7620
select SUPPORTS_LITTLE_ENDIAN
select SYSRESET
 
+config ARCH_JZ47XX
+   bool "Support Ingenic JZ47xx"
+   select SUPPORT_SPL
+   select OF_CONTROL
+   select DM
+
 config MACH_PIC32
bool "Support Microchip PIC32"
select DM
@@ -139,6 +145,7 @@ source "board/micronas/vct/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
 source "arch/mips/mach-bmips/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 source "arch/mips/mach-mt7620/Kconfig"
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 802244a06e5d..a294e9b1e8b9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -13,6 +13,7 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_ARCH_BMIPS) += bmips
+machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
 machine-$(CONFIG_ARCH_MT7620) += mt7620
 
diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
new file mode 100644
index ..e34f8d359036
--- /dev/null
+++ b/arch/mips/dts/jz4780.dtsi
@@ -0,0 +1,162 @@
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "ingenic,jz4780";
+
+   cpuintc: interrupt-controller {
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "mti,cpu-interrupt-controller";
+   };
+
+   intc: interrupt-controller@10001000 {
+   compatible = "ingenic,jz4780-intc";
+   reg = <0x10001000 0x50>;
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interrupt-parent = <>;
+   interrupts = <2>;
+   };
+
+   ext: ext {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   };
+
+   rtc: rtc {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+
+   cgu: jz4780-cgu@1000 {
+   compatible = "ingenic,jz4780-cgu";
+   reg = <0x1000 0x100>;
+
+   clocks = <>, <>;
+   clock-names = "ext", "rtc";
+
+   #clock-cells = <1>;
+   };
+
+   mmc0: mmc@1345 {
+   compatible = "ingenic,jz4780-mmc";
+   reg = <0x1345 0x1000>;
+
+   status = "disabled";
+
+   clocks = < JZ4780_CLK_MSC0>;
+   clock-names = "mmc";
+   };
+
+   mmc1: mmc@1346 {
+   compatible = &qu

[U-Boot] [PATCH v2 3/6] mmc: Add JZ47xx SD/MMC controller driver

[Ezequiel Garcia]

From: Paul Burton 

Add driver for the JZ47xx MSC controller.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
Reviewed-by: Marek Vasut 
---
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   1 +
 drivers/mmc/jz_mmc.  |   0
 drivers/mmc/jz_mmc.c | 489 +++
 4 files changed, 496 insertions(+)
 create mode 100644 drivers/mmc/jz_mmc.
 create mode 100644 drivers/mmc/jz_mmc.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index fbd13964a084..496b2cba6405 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -332,6 +332,12 @@ config MMC_BCM2835
 
  If unsure, say N.
 
+config JZ47XX_MMC
+   bool "Ingenic JZ47xx SD/MMC Host Controller support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the SD Card Controller on Ingenic JZ47xx 
SoCs.
+
 config MMC_SANDBOX
bool "Sandbox MMC support"
depends on SANDBOX
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 801a26d82192..7892c468f05c 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
 obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
+obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
diff --git a/drivers/mmc/jz_mmc. b/drivers/mmc/jz_mmc.
new file mode 100644
index ..e69de29bb2d1
diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
new file mode 100644
index ..2e92fa16e6c8
--- /dev/null
+++ b/drivers/mmc/jz_mmc.c
@@ -0,0 +1,489 @@
+/*
+ * Ingenic JZ MMC driver
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Registers */
+#define MSC_STRPCL 0x000
+#define MSC_STAT   0x004
+#define MSC_CLKRT  0x008
+#define MSC_CMDAT  0x00c
+#define MSC_RESTO  0x010
+#define MSC_RDTO   0x014
+#define MSC_BLKLEN 0x018
+#define MSC_NOB0x01c
+#define MSC_SNOB   0x020
+#define MSC_IMASK  0x024
+#define MSC_IREG   0x028
+#define MSC_CMD0x02c
+#define MSC_ARG0x030
+#define MSC_RES0x034
+#define MSC_RXFIFO 0x038
+#define MSC_TXFIFO 0x03c
+#define MSC_LPM0x040
+#define MSC_DMAC   0x044
+#define MSC_DMANDA 0x048
+#define MSC_DMADA  0x04c
+#define MSC_DMALEN 0x050
+#define MSC_DMACMD 0x054
+#define MSC_CTRL2  0x058
+#define MSC_RTCNT  0x05c
+#define MSC_DBG0x0fc
+
+/* MSC Clock and Control Register (MSC_STRPCL) */
+#define MSC_STRPCL_EXIT_MULTIPLE   BIT(7)
+#define MSC_STRPCL_EXIT_TRANSFER   BIT(6)
+#define MSC_STRPCL_START_READWAIT  BIT(5)
+#define MSC_STRPCL_STOP_READWAIT   BIT(4)
+#define MSC_STRPCL_RESET   BIT(3)
+#define MSC_STRPCL_START_OPBIT(2)
+#define MSC_STRPCL_CLOCK_CONTROL_STOP  BIT(0)
+#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
+
+/* MSC Status Register (MSC_STAT) */
+#define MSC_STAT_AUTO_CMD_DONE BIT(31)
+#define MSC_STAT_IS_RESETTING  BIT(15)
+#define MSC_STAT_SDIO_INT_ACTIVE   BIT(14)
+#define MSC_STAT_PRG_DONE  BIT(13)
+#define MSC_STAT_DATA_TRAN_DONEBIT(12)
+#define MSC_STAT_END_CMD_RES   BIT(11)
+#define MSC_STAT_DATA_FIFO_AFULL   BIT(10)
+#define MSC_STAT_IS_READWAIT   BIT(9)
+#define MSC_STAT_CLK_ENBIT(8)
+#define MSC_STAT_DATA_FIFO_FULLBIT(7)
+#define MSC_STAT_DATA_FIFO_EMPTY   BIT(6)
+#define MSC_STAT_CRC_RES_ERR   BIT(5)
+#define MSC_STAT_CRC_READ_ERRORBIT(4)
+#define MSC_STAT_CRC_WRITE_ERROR   BIT(2)
+#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
+#define MSC_STAT_TIME_OUT_RES  BIT(1)
+#define MSC_STAT_TIME_OUT_READ BIT(0)
+
+/* MSC Bus Clock Control Register (MSC_CLKRT) */
+#define MSC_CLKRT_CLK_RATE_MASK0x7
+
+/* MSC Command Sequence Control Register (MSC_CMDAT) */
+#define MSC_CMDAT_IO_ABORT BIT(11)
+#define MSC_CMDAT_BUS_WIDTH_1BIT   (0x0 << 9)
+#define MSC_CMDAT_BUS_WIDTH_4BIT   (0x2 << 9)
+#define MSC_CMDAT_DMA_EN   BIT(8)
+#define MSC_CMDAT_INIT BIT(7)
+#define MSC_CMDAT_BUSY BIT(6)
+#define MSC_

[U-Boot] [PATCH v2 4/6] mips: Add SPL header

[Ezequiel Garcia]

From: Paul Burton 

Add header with SPL boot mode and type definitions.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Reviewed-by: Marek Vasut 
---
 arch/mips/include/asm/spl.h | 35 +++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/mips/include/asm/spl.h

diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h
new file mode 100644
index ..01baab606606
--- /dev/null
+++ b/arch/mips/include/asm/spl.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef_ASM_SPL_H_
+#define_ASM_SPL_H_
+
+enum {
+   BOOT_DEVICE_RAM,
+   BOOT_DEVICE_MMC1,
+   BOOT_DEVICE_MMC2,
+   BOOT_DEVICE_MMC2_2,
+   BOOT_DEVICE_NAND,
+   BOOT_DEVICE_ONENAND,
+   BOOT_DEVICE_NOR,
+   BOOT_DEVICE_UART,
+   BOOT_DEVICE_SPI,
+   BOOT_DEVICE_USB,
+   BOOT_DEVICE_SATA,
+   BOOT_DEVICE_I2C,
+   BOOT_DEVICE_BOARD,
+   BOOT_DEVICE_NONE
+};
+
+/* Linker symbols. */
+extern char __bss_start[];
+extern ulong __bss_end;
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif
-- 
2.20.0.rc2

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[U-Boot] [PATCH v2 6/6] mips: jz47xx: Add Creator CI20 platform

[Ezequiel Garcia]

From: Paul Burton 

Add support for the Creator CI20 platform based on the JZ4780 SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
Reviewed-by: Marek Vasut 
---
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 120 +++
 arch/mips/mach-jz47xx/Kconfig |  11 +
 board/imgtec/ci20/Kconfig |  15 ++
 board/imgtec/ci20/MAINTAINERS |   6 +
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 +
 board/imgtec/ci20/ci20.c  | 365 ++
 configs/ci20_defconfig|  47 +
 include/configs/ci20.h|  74 +++
 10 files changed, 654 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/MAINTAINERS
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 include/configs/ci20.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b447141f8717..647d2bf0d53b 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts
new file mode 100644
index ..934d9e96d24d
--- /dev/null
+++ b/arch/mips/dts/ci20.dts
@@ -0,0 +1,120 @@
+/dts-v1/;
+
+#include "jz4780.dtsi"
+
+/ {
+   compatible = "img,ci20", "ingenic,jz4780";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   chosen {
+   stdout-path = "serial4:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x0 0x1000
+  0x3000 0x3000>;
+   };
+};
+
+ {
+   clock-frequency = <4800>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+
+   nandc: nand-controller@1 {
+   compatible = "ingenic,jz4780-nand";
+   reg = <1 0 0x100>;
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ingenic,bch-controller = <>;
+
+   ingenic,nemc-tAS = <10>;
+   ingenic,nemc-tAH = <5>;
+   ingenic,nemc-tBP = <10>;
+   ingenic,nemc-tAW = <15>;
+   ingenic,nemc-tSTRV = <100>;
+
+   nand@1 {
+   reg = <1>;
+
+   nand-ecc-step-size = <1024>;
+   nand-ecc-strength = <24>;
+   nand-ecc-mode = "hw";
+   nand-on-flash-bbt;
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   partition@0 {
+   label = "u-boot-spl";
+   reg = <0x0 0x0 0x0 0x80>;
+   };
+
+   partition@0x80 {
+   label = "u-boot";
+   reg = <0x0 0x80 0x0 0x20>;
+   };
+
+   partition@0xa0 {
+   label = "u-boot-env";
+   reg = <0x0 0xa0 0x0 0x20>;
+   };
+
+   partition@0xc0 {
+   label = "boot";
+   reg = <0x0 0xc0 0x0 0x400>;
+   };
+
+   partition@0x8c0 {
+   label = "system";
+   reg = <0x0 0x4c0 0x1 0xfb40>;
+   };
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   bus-width = <4>;
+   max-frequency = <5000>;
+   status = "okay"

[U-Boot] [PATCH v2 2/6] gpio: Add JZ47xx GPIO driver

[Ezequiel Garcia]

From: Paul Burton 

Add primitive GPIO controller driver for the JZ47xx SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Reviewed-by: Marek Vasut 
---
 drivers/gpio/Kconfig   |  7 
 drivers/gpio/Makefile  |  1 +
 drivers/gpio/gpio-jz47xx.c | 78 ++
 3 files changed, 86 insertions(+)
 create mode 100644 drivers/gpio/gpio-jz47xx.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 35344e57c6c6..46c161c99ce9 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -322,4 +322,11 @@ config MT7621_GPIO
help
  Say yes here to support MediaTek MT7621 compatible GPIOs.
 
+config JZ47XX_GPIO
+   bool "Ingenic JZ47xx GPIO driver"
+   depends on ARCH_JZ47XX
+   default y
+   help
+ Supports GPIO access on Ingenic JZ47xx SoCs.
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7ed9a4ec4221..92310e9ba934 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,3 +59,4 @@ obj-$(CONFIG_MSM_GPIO)+= msm_gpio.o
 obj-$(CONFIG_$(SPL_)PCF8575_GPIO)  += pcf8575_gpio.o
 obj-$(CONFIG_PM8916_GPIO)  += pm8916_gpio.o
 obj-$(CONFIG_MT7621_GPIO)  += mt7621_gpio.o
+obj-$(CONFIG_JZ47XX_GPIO)  += gpio-jz47xx.o
diff --git a/drivers/gpio/gpio-jz47xx.c b/drivers/gpio/gpio-jz47xx.c
new file mode 100644
index ..565108192306
--- /dev/null
+++ b/drivers/gpio/gpio-jz47xx.c
@@ -0,0 +1,78 @@
+/*
+ * Ingenic JZ47xx GPIO
+ *
+ * Copyright (C) 2018 Marek Vasut 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int gpio_get_value(unsigned gpio)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   if (value)
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT0S(port));
+   else
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT0C(port));
+
+   return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port));
+
+   return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port));
+
+   gpio_set_value(gpio, value);
+
+   return 0;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+   int port = gpio / 32;
+
+   if (port >= 6)
+   return -EINVAL;
+
+   return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+   return 0;
+}
-- 
2.20.0.rc2

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[U-Boot] [PATCH v2 1/6] misc: Add JZ47xx efuse driver

[Ezequiel Garcia]

From: Paul Burton 

Add driver for the efuse block in the JZ47xx SOC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
Reviewed-by: Marek Vasut 
---
 drivers/misc/Kconfig|   6 +++
 drivers/misc/Makefile   |   1 +
 drivers/misc/jz4780_efuse.c | 104 
 3 files changed, 111 insertions(+)
 create mode 100644 drivers/misc/jz4780_efuse.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 48febc47d263..704c8dd1955f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -120,6 +120,12 @@ config FSL_SEC_MON
  Security Monitor can be transitioned on any security failures,
  like software violations or hardware security violations.
 
+config JZ4780_EFUSE
+   bool "Ingenic JZ4780 eFUSE support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the eFUSE on Ingenic JZ4780 SoCs.
+
 config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 302d44159274..6bdf5054f475 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -62,3 +62,4 @@ obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
 obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c
new file mode 100644
index ..7b327f54b15c
--- /dev/null
+++ b/drivers/misc/jz4780_efuse.c
@@ -0,0 +1,104 @@
+/*
+ * JZ4780 EFUSE driver
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ * Author: Alex Smith 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define EFUSE_EFUCTRL  0xd0
+#define EFUSE_EFUCFG   0xd4
+#define EFUSE_EFUSTATE 0xd8
+#define EFUSE_EFUDATA(n)   (0xdc + ((n) * 4))
+
+#define EFUSE_EFUCTRL_RD_ENBIT(0)
+#define EFUSE_EFUCTRL_LEN_BIT  16
+#define EFUSE_EFUCTRL_LEN_MASK 0x1f
+#define EFUSE_EFUCTRL_ADDR_BIT 21
+#define EFUSE_EFUCTRL_ADDR_MASK0x1ff
+#define EFUSE_EFUCTRL_CS   BIT(30)
+
+#define EFUSE_EFUCFG_RD_STROBE_BIT 16
+#define EFUSE_EFUCFG_RD_STROBE_MASK0xf
+#define EFUSE_EFUCFG_RD_ADJ_BIT20
+#define EFUSE_EFUCFG_RD_ADJ_MASK   0xf
+
+#define EFUSE_EFUSTATE_RD_DONE BIT(0)
+
+static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   size_t i;
+   u32 val;
+   int ret;
+
+   val = EFUSE_EFUCTRL_RD_EN |
+ ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
+ (addr << EFUSE_EFUCTRL_ADDR_BIT) |
+ ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
+   writel(val, regs + EFUSE_EFUCTRL);
+
+   ret = wait_for_bit_le32(regs + EFUSE_EFUSTATE,
+   EFUSE_EFUSTATE_RD_DONE, true, 1, false);
+   if (ret)
+   return;
+
+   if ((count % 4) == 0) {
+   for (i = 0; i < count / 4; i++) {
+   val = readl(regs + EFUSE_EFUDATA(i));
+   put_unaligned(val, (u32 *)(buf + (i * 4)));
+   }
+   } else {
+   val = readl(regs + EFUSE_EFUDATA(0));
+   if (count > 2)
+   buf[2] = (val >> 16) & 0xff;
+   if (count > 1)
+   buf[1] = (val >> 8) & 0xff;
+   buf[0] = val & 0xff;
+   }
+}
+
+static inline int jz4780_efuse_chunk_size(size_t count)
+{
+   if (count >= 32)
+   return 32;
+   else if ((count / 4) > 0)
+   return (count / 4) * 4;
+   else
+   return count % 4;
+}
+
+void jz4780_efuse_read(size_t addr, size_t count, u8 *buf)
+{
+   size_t chunk;
+
+   while (count > 0) {
+   chunk = jz4780_efuse_chunk_size(count);
+   jz4780_efuse_read_chunk(addr, chunk, buf);
+   addr += chunk;
+   buf += chunk;
+   count -= chunk;
+   }
+}
+
+void jz4780_efuse_init(u32 ahb2_rate)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   u32 rd_adj, rd_strobe, tmp;
+
+   rd_adj = (((6500 * (ahb2_rate / 100)) / 100) + 0xf) / 2;
+   tmp = (((35000 * (ahb2_rate / 100)) / 100) - 4) - rd_adj;
+   rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2;
+
+   tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) |
+ (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT);
+   writel(tmp, regs + EFUSE_EFUCFG);
+}
-- 
2.20.0.rc2

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[U-Boot] [PATCH v2 0/6] Add support for MIPS Creator CI20

[Ezequiel Garcia]

A new round.

For this new round:

 * Replaced infinite while loop with wait_for_bit.
 * Added a MAINTAINERS file. If anyone wants to co-maintain this,
   please let me know.

This is based on top of yesterday's master (ee168783ae8) and has
been tested by SD-card booting both U-Boot and Linux. Booting
Linux via TFTP was also tested.

Toolchain used to test:

$ mips-linux-gcc -v
Using built-in specs.
COLLECT_GCC=mips-linux-gcc
COLLECT_LTO_WRAPPER=/home/zeta/.buildman-toolchains/gcc-7.3.0-nolibc/mips-linux/bin/../libexec/gcc/mips-linux/7.3.0/lto-wrapper
Target: mips-linux
Configured with: /home/arnd/git/gcc/configure --target=mips-linux 
--enable-targets=all --prefix=/opt/crosstool/gcc-7.3.0-nolibc/mips-linux 
--enable-languages=c --without-headers --disable-bootstrap --disable-nls 
--disable-threads --disable-shared --disable-libmudflap --disable-libssp 
--disable-libgomp --disable-decimal-float --disable-libquadmath 
--disable-libatomic --disable-libcc1 --disable-libmpx --enable-checking=release
Thread model: single
gcc version 7.3.0 (GCC) 

SPL size:

$ size spl/u-boot-spl
   textdata bss dec hex filename
   9252 752 736   1074029f4 spl/u-boot-spl

I've pushed a branch to https://github.com/ezequielgarcia/u-boot/tree/ci20-v2
and made sure travis passed.

Note that Paul's contributions are recorded using his imgtec.com
mail although it's no longer valid, and that we will rely on mailmap
to map it to mips.com.

It would be terrific to fit this on the next release.

Thanks!

Paul Burton (6):
  misc: Add JZ47xx efuse driver
  gpio: Add JZ47xx GPIO driver
  mmc: Add JZ47xx SD/MMC controller driver
  mips: Add SPL header
  mips: jz47xx: Add JZ4780 SoC support
  mips: jz47xx: Add Creator CI20 platform

 arch/mips/Kconfig |   7 +
 arch/mips/Makefile|   1 +
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 120 
 arch/mips/dts/jz4780.dtsi | 162 ++
 arch/mips/include/asm/spl.h   |  35 ++
 arch/mips/mach-jz47xx/Kconfig |  26 +
 arch/mips/mach-jz47xx/Makefile|   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h   | 104 
 .../mach-jz47xx/include/mach/jz4780_dram.h| 457 +++
 arch/mips/mach-jz47xx/jz4780/Makefile |   5 +
 arch/mips/mach-jz47xx/jz4780/jz4780.c | 142 +
 arch/mips/mach-jz47xx/jz4780/pll.c| 528 ++
 arch/mips/mach-jz47xx/jz4780/sdram.c  | 271 +
 arch/mips/mach-jz47xx/jz4780/timer.c  | 238 
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds   |  52 ++
 arch/mips/mach-jz47xx/start.S |  99 
 board/imgtec/ci20/Kconfig |  15 +
 board/imgtec/ci20/MAINTAINERS |   6 +
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 +
 board/imgtec/ci20/ci20.c  | 365 
 configs/ci20_defconfig|  47 ++
 drivers/gpio/Kconfig  |   7 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/gpio-jz47xx.c|  78 +++
 drivers/misc/Kconfig  |   6 +
 drivers/misc/Makefile |   1 +
 drivers/misc/jz4780_efuse.c   | 104 
 drivers/mmc/Kconfig   |   6 +
 drivers/mmc/Makefile  |   1 +
 drivers/mmc/jz_mmc.   |   0
 drivers/mmc/jz_mmc.c  | 489 
 include/configs/ci20.h|  74 +++
 include/dt-bindings/clock/jz4780-cgu.h|  88 +++
 35 files changed, 3558 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/include/asm/spl.h
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/MAINTAINERS
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 drivers/gpio/gpio-jz47xx.c
 create mode 100644 drivers/misc/jz4780_efuse.c
 create mode 100644 drivers/mmc/jz_mmc.
 

Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

[Ezequiel Garcia]

On Mon, 2018-12-10 at 19:48 -0500, Tom Rini wrote:
> On Mon, Dec 10, 2018 at 05:35:56PM -0300, Ezequiel Garcia wrote:
> 
> > As the subject says, this series adds support for CI20.
> > 
> > Most of the work was done by Paul Burton, and then by Marek Vasut.
> > I've just rescued the work from the dark wastelands of Mordor,
> > did some cleaning here and there and submitted.
> > 
> > Patches 1, 2, and 4 are completely untouched. I've picked them
> > from Marek's tree.
> > 
> > For the MMC driver (patch 3) there is some cleanup, and some
> > fixes for proper DM migration.
> > 
> > Finally, patches 5 and 6 have been changed a bit: I've cleaned
> > up the devicetree, the board support files and the defconfig.
> > 
> > This is based on top of today's master (7ff485c68b7e) and has
> > been tested by SD-card booting both U-Boot and Linux. Booting
> > Linux via TFTP was also tested.
> > 
> > Please note that I've added Paul's SOB to all the patches
> > he authored, to make the authorship chain more clear.
> > 
> > Reviews and tests are welcome. Bikesheds not so much! ;-)
> 
> There's some stuff that's been noted that needs fixing and a v5 (I
> think, really) posted with those addressed.  But if there's nothing
> else, it would be good to finally get this platform in and I would be
> open to seeing it come in still at this point in the merge window.
> Thanks all!
> 

I think that if we are worried about those infinite loops in the drivers,
and stuff along that severity level, it won't hurt to fix them as
follow-up patches.

Thanks,
Eze

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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

[Ezequiel Garcia]

On Mon, 2018-12-10 at 18:41 -0500, Tom Rini wrote:
> On Mon, Dec 10, 2018 at 06:31:29PM -0300, Ezequiel Garcia wrote:
> > On Mon, 2018-12-10 at 22:00 +0100, Andreas Färber wrote:
> [snip]
> > > Further, it would be very helpful - given the history of this patchset -
> > > to indicate which toolchain and version you used for building this.
> > > 
> > 
> > I've used gcc version 5.3.0 (Sourcery CodeBench Lite 2016.05-8),
> > installed via Buildroot. Wasn't really paying attention to the toolchain.
> > 
> > I'll test with a recent gcc and post the results.
> 
> Just to chime in on this part for now, to be clear, it needs to work
> with the default toolchain buildman uses, which is currently the gcc-7.3
> kernel.org ones and buildman will fetch one for you.
> 

Done!

$ strings u-boot | grep GCC
mips-linux-gcc (GCC) 7.3.0
GCC: (GNU) 7.3.0
$ strings spl/u-boot-spl | grep GCC
GCC: (GNU) 7.3.0

U-Boot 2019.01-rc1-00226-g208679cb9307 (Dec 10 2018 - 21:19:57 -0300)

CPU:   Ingenic JZ4780
Board: Creator CI20 (rev.1)
DRAM:  1 GiB
MMC:   MSC: 0, MSC: 1
Loading Environment from MMC... OK
In:serial@10034000
Out:   serial@10034000
Err:   serial@10034000
Net:   dm9000
Hit any key to stop autoboot:  0 
=>

Regards,
Eze

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Re: [U-Boot] [PATCH 1/6] misc: Add JZ47xx efuse driver

[Ezequiel Garcia]

On Mon, 2018-12-10 at 21:56 +0100, Marek Vasut wrote:
> On 12/10/2018 09:35 PM, Ezequiel Garcia wrote:
> > From: Paul Burton 
> > 
> > Add driver for the efuse block in the JZ47xx SOC.
> > 
> > Cc: Daniel Schwierzeck 
> > Signed-off-by: Paul Burton 
> > Signed-off-by: Marek Vasut 
> 
> [...]
> 
> > +static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
> > +{
> > +   void __iomem *regs = (void __iomem *)NEMC_BASE;
> > +   size_t i;
> > +   u32 val;
> > +
> > +   val = EFUSE_EFUCTRL_RD_EN |
> > + ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
> > + (addr << EFUSE_EFUCTRL_ADDR_BIT) |
> > + ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
> > +   writel(val, regs + EFUSE_EFUCTRL);
> > +   /* FIXME -- wait_bit() */
> > +   while (!(readl(regs + EFUSE_EFUSTATE) & EFUSE_EFUSTATE_RD_DONE))
> > +   ;
> 
> Does wait_for_bit_le32() fit into the SPL if you use it here ?
> 

I literally haven't looked at these (working) drivers. Let's see..

...hm, to be honest, I'm more worried about these infinite loops
than about fancy API uses. An infinite loop in the MMC driver caused
a freeze during driver-model porting, so these are more serious threats.

Will try to address the unbounded loop and take a stab at using
wait_for_bit_le32.

Thanks for the review!
Eze

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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

[Ezequiel Garcia]

On Mon, 2018-12-10 at 22:00 +0100, Andreas Färber wrote:
> Hi Ezequiel,
> 
> Am 10.12.18 um 21:35 schrieb Ezequiel Garcia:
> > Please note that I've added Paul's SOB to all the patches
> > he authored, to make the authorship chain more clear.
> 
> That's only permitted if Paul agreed to that beforehand - did he?
> Never add other people's Signed-off-by if their patches didn't have it!
> 

Fair enough. Let's hope Paul is OK with this. I wasn't really comfortable
not having Paul's SOB, given he authored all the patches.

Paul, do we have green light?

> https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin
> 
> As far as the authorship chain goes, you re-did all my forward-porting,
> that I'm not being credited with Signed-off-by in MMC/SoC/defconfig
> patches or verbally anywhere?
> 

Oh, sorry, but I haven't used anything from your work. This series
is entirely based on https://github.com/marex/u-boot-mips/tree/ci20-v2018.xx.

Basically, I've cherry-picked the commits that weren't already available
in upstream, adding my SOB to those patches that I've modified.

Like I mentioned in the cover letter, most of the work has been done
by Paul Burton and Marek, so they deserve all the credit.

I'm just cleaning and submitting.

> Also this is surely not a v1 patch! Marek had posted CI20 before, so
> this should be v2 (doesn't look like I posted mine as v2, it didn't
> fully build yet) and thus your next iteration should be v3 please.
> 

Well, I couldn't find Marek's cover letter, and I've decided to start from 
scratch.

Two years have passed, we have a new try at getting this merged so I think
it deserves it's own set of integers.

> Further, it would be very helpful - given the history of this patchset -
> to indicate which toolchain and version you used for building this.
> 

I've used gcc version 5.3.0 (Sourcery CodeBench Lite 2016.05-8),
installed via Buildroot. Wasn't really paying attention to the toolchain.

I'll test with a recent gcc and post the results.

Thanks,
Eze

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[U-Boot] [PATCH 4/6] mips: Add SPL header

[Ezequiel Garcia]

From: Paul Burton 

Add header with SPL boot mode and type definitions.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
---
 arch/mips/include/asm/spl.h | 35 +++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/mips/include/asm/spl.h

diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h
new file mode 100644
index ..01baab606606
--- /dev/null
+++ b/arch/mips/include/asm/spl.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef_ASM_SPL_H_
+#define_ASM_SPL_H_
+
+enum {
+   BOOT_DEVICE_RAM,
+   BOOT_DEVICE_MMC1,
+   BOOT_DEVICE_MMC2,
+   BOOT_DEVICE_MMC2_2,
+   BOOT_DEVICE_NAND,
+   BOOT_DEVICE_ONENAND,
+   BOOT_DEVICE_NOR,
+   BOOT_DEVICE_UART,
+   BOOT_DEVICE_SPI,
+   BOOT_DEVICE_USB,
+   BOOT_DEVICE_SATA,
+   BOOT_DEVICE_I2C,
+   BOOT_DEVICE_BOARD,
+   BOOT_DEVICE_NONE
+};
+
+/* Linker symbols. */
+extern char __bss_start[];
+extern ulong __bss_end;
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif
-- 
2.20.0.rc2

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[U-Boot] [PATCH 6/6] mips: jz47xx: Add Creator CI20 platform

[Ezequiel Garcia]

From: Paul Burton 

Add support for the Creator CI20 platform based on the JZ4780 SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 120 +++
 arch/mips/mach-jz47xx/Kconfig |  11 +
 board/imgtec/ci20/Kconfig |  15 ++
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 +
 board/imgtec/ci20/ci20.c  | 365 ++
 configs/ci20_defconfig|  47 +
 include/configs/ci20.h|  74 +++
 9 files changed, 648 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 include/configs/ci20.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b447141f8717..647d2bf0d53b 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts
new file mode 100644
index ..934d9e96d24d
--- /dev/null
+++ b/arch/mips/dts/ci20.dts
@@ -0,0 +1,120 @@
+/dts-v1/;
+
+#include "jz4780.dtsi"
+
+/ {
+   compatible = "img,ci20", "ingenic,jz4780";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   chosen {
+   stdout-path = "serial4:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x0 0x1000
+  0x3000 0x3000>;
+   };
+};
+
+ {
+   clock-frequency = <4800>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+
+   nandc: nand-controller@1 {
+   compatible = "ingenic,jz4780-nand";
+   reg = <1 0 0x100>;
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ingenic,bch-controller = <>;
+
+   ingenic,nemc-tAS = <10>;
+   ingenic,nemc-tAH = <5>;
+   ingenic,nemc-tBP = <10>;
+   ingenic,nemc-tAW = <15>;
+   ingenic,nemc-tSTRV = <100>;
+
+   nand@1 {
+   reg = <1>;
+
+   nand-ecc-step-size = <1024>;
+   nand-ecc-strength = <24>;
+   nand-ecc-mode = "hw";
+   nand-on-flash-bbt;
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   partition@0 {
+   label = "u-boot-spl";
+   reg = <0x0 0x0 0x0 0x80>;
+   };
+
+   partition@0x80 {
+   label = "u-boot";
+   reg = <0x0 0x80 0x0 0x20>;
+   };
+
+   partition@0xa0 {
+   label = "u-boot-env";
+   reg = <0x0 0xa0 0x0 0x20>;
+   };
+
+   partition@0xc0 {
+   label = "boot";
+   reg = <0x0 0xc0 0x0 0x400>;
+   };
+
+   partition@0x8c0 {
+   label = "system";
+   reg = <0x0 0x4c0 0x1 0xfb40>;
+   };
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   bus-width = <4>;
+   max-frequency = <5000>;
+   status = "okay";
+};
+
+ {
+   bus-width = <4>;
+   max-frequency = <5000>;
+   status 

[U-Boot] [PATCH 5/6] mips: jz47xx: Add JZ4780 SoC support

[Ezequiel Garcia]

From: Paul Burton 

Add initial support for the Ingenic JZ47xx MIPS SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 arch/mips/Kconfig |   7 +
 arch/mips/Makefile|   1 +
 arch/mips/dts/jz4780.dtsi | 162 ++
 arch/mips/mach-jz47xx/Kconfig |  15 +
 arch/mips/mach-jz47xx/Makefile|   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h   | 104 
 .../mach-jz47xx/include/mach/jz4780_dram.h| 457 +++
 arch/mips/mach-jz47xx/jz4780/Makefile |   5 +
 arch/mips/mach-jz47xx/jz4780/jz4780.c | 142 +
 arch/mips/mach-jz47xx/jz4780/pll.c| 528 ++
 arch/mips/mach-jz47xx/jz4780/sdram.c  | 271 +
 arch/mips/mach-jz47xx/jz4780/timer.c  | 238 
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds   |  52 ++
 arch/mips/mach-jz47xx/start.S |  99 
 include/dt-bindings/clock/jz4780-cgu.h|  88 +++
 15 files changed, 2176 insertions(+)
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b1b1d7d0031..44b25460b8cc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -88,6 +88,12 @@ config ARCH_MT7620
select SUPPORTS_LITTLE_ENDIAN
select SYSRESET
 
+config ARCH_JZ47XX
+   bool "Support Ingenic JZ47xx"
+   select SUPPORT_SPL
+   select OF_CONTROL
+   select DM
+
 config MACH_PIC32
bool "Support Microchip PIC32"
select DM
@@ -139,6 +145,7 @@ source "board/micronas/vct/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
 source "arch/mips/mach-bmips/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 source "arch/mips/mach-mt7620/Kconfig"
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 802244a06e5d..a294e9b1e8b9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -13,6 +13,7 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_ARCH_BMIPS) += bmips
+machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
 machine-$(CONFIG_ARCH_MT7620) += mt7620
 
diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
new file mode 100644
index ..e34f8d359036
--- /dev/null
+++ b/arch/mips/dts/jz4780.dtsi
@@ -0,0 +1,162 @@
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "ingenic,jz4780";
+
+   cpuintc: interrupt-controller {
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "mti,cpu-interrupt-controller";
+   };
+
+   intc: interrupt-controller@10001000 {
+   compatible = "ingenic,jz4780-intc";
+   reg = <0x10001000 0x50>;
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interrupt-parent = <>;
+   interrupts = <2>;
+   };
+
+   ext: ext {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   };
+
+   rtc: rtc {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+
+   cgu: jz4780-cgu@1000 {
+   compatible = "ingenic,jz4780-cgu";
+   reg = <0x1000 0x100>;
+
+   clocks = <>, <>;
+   clock-names = "ext", "rtc";
+
+   #clock-cells = <1>;
+   };
+
+   mmc0: mmc@1345 {
+   compatible = "ingenic,jz4780-mmc";
+   reg = <0x1345 0x1000>;
+
+   status = "disabled";
+
+   clocks = < JZ4780_CLK_MSC0>;
+   clock-names = "mmc";
+   };
+
+   mmc1: mmc@1346 {
+   compatible = "ingenic,jz4780-mm

[U-Boot] [PATCH 3/6] mmc: Add JZ47xx SD/MMC controller driver

[Ezequiel Garcia]

From: Paul Burton 

Add driver for the JZ47xx MSC controller.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   1 +
 drivers/mmc/jz_mmc.  |   0
 drivers/mmc/jz_mmc.c | 491 +++
 4 files changed, 498 insertions(+)
 create mode 100644 drivers/mmc/jz_mmc.
 create mode 100644 drivers/mmc/jz_mmc.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index fbd13964a084..496b2cba6405 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -332,6 +332,12 @@ config MMC_BCM2835
 
  If unsure, say N.
 
+config JZ47XX_MMC
+   bool "Ingenic JZ47xx SD/MMC Host Controller support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the SD Card Controller on Ingenic JZ47xx 
SoCs.
+
 config MMC_SANDBOX
bool "Sandbox MMC support"
depends on SANDBOX
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 801a26d82192..7892c468f05c 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
 obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
+obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
diff --git a/drivers/mmc/jz_mmc. b/drivers/mmc/jz_mmc.
new file mode 100644
index ..e69de29bb2d1
diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
new file mode 100644
index ..18c1810ff42c
--- /dev/null
+++ b/drivers/mmc/jz_mmc.c
@@ -0,0 +1,491 @@
+/*
+ * Ingenic JZ MMC driver
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Registers */
+#define MSC_STRPCL 0x000
+#define MSC_STAT   0x004
+#define MSC_CLKRT  0x008
+#define MSC_CMDAT  0x00c
+#define MSC_RESTO  0x010
+#define MSC_RDTO   0x014
+#define MSC_BLKLEN 0x018
+#define MSC_NOB0x01c
+#define MSC_SNOB   0x020
+#define MSC_IMASK  0x024
+#define MSC_IREG   0x028
+#define MSC_CMD0x02c
+#define MSC_ARG0x030
+#define MSC_RES0x034
+#define MSC_RXFIFO 0x038
+#define MSC_TXFIFO 0x03c
+#define MSC_LPM0x040
+#define MSC_DMAC   0x044
+#define MSC_DMANDA 0x048
+#define MSC_DMADA  0x04c
+#define MSC_DMALEN 0x050
+#define MSC_DMACMD 0x054
+#define MSC_CTRL2  0x058
+#define MSC_RTCNT  0x05c
+#define MSC_DBG0x0fc
+
+/* MSC Clock and Control Register (MSC_STRPCL) */
+#define MSC_STRPCL_EXIT_MULTIPLE   BIT(7)
+#define MSC_STRPCL_EXIT_TRANSFER   BIT(6)
+#define MSC_STRPCL_START_READWAIT  BIT(5)
+#define MSC_STRPCL_STOP_READWAIT   BIT(4)
+#define MSC_STRPCL_RESET   BIT(3)
+#define MSC_STRPCL_START_OPBIT(2)
+#define MSC_STRPCL_CLOCK_CONTROL_STOP  BIT(0)
+#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
+
+/* MSC Status Register (MSC_STAT) */
+#define MSC_STAT_AUTO_CMD_DONE BIT(31)
+#define MSC_STAT_IS_RESETTING  BIT(15)
+#define MSC_STAT_SDIO_INT_ACTIVE   BIT(14)
+#define MSC_STAT_PRG_DONE  BIT(13)
+#define MSC_STAT_DATA_TRAN_DONEBIT(12)
+#define MSC_STAT_END_CMD_RES   BIT(11)
+#define MSC_STAT_DATA_FIFO_AFULL   BIT(10)
+#define MSC_STAT_IS_READWAIT   BIT(9)
+#define MSC_STAT_CLK_ENBIT(8)
+#define MSC_STAT_DATA_FIFO_FULLBIT(7)
+#define MSC_STAT_DATA_FIFO_EMPTY   BIT(6)
+#define MSC_STAT_CRC_RES_ERR   BIT(5)
+#define MSC_STAT_CRC_READ_ERRORBIT(4)
+#define MSC_STAT_CRC_WRITE_ERROR   BIT(2)
+#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
+#define MSC_STAT_TIME_OUT_RES  BIT(1)
+#define MSC_STAT_TIME_OUT_READ BIT(0)
+
+/* MSC Bus Clock Control Register (MSC_CLKRT) */
+#define MSC_CLKRT_CLK_RATE_MASK0x7
+
+/* MSC Command Sequence Control Register (MSC_CMDAT) */
+#define MSC_CMDAT_IO_ABORT BIT(11)
+#define MSC_CMDAT_BUS_WIDTH_1BIT   (0x0 << 9)
+#define MSC_CMDAT_BUS_WIDTH_4BIT   (0x2 << 9)
+#define MSC_CMDAT_DMA_EN   BIT(8)
+#define MSC_CMDAT_INIT BIT(7)
+#define MSC_CMDAT_BUSY BIT(6)
+#define MSC_CMDAT_STREAM_BLOCK

[U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

[Ezequiel Garcia]

As the subject says, this series adds support for CI20.

Most of the work was done by Paul Burton, and then by Marek Vasut.
I've just rescued the work from the dark wastelands of Mordor,
did some cleaning here and there and submitted.

Patches 1, 2, and 4 are completely untouched. I've picked them
from Marek's tree.

For the MMC driver (patch 3) there is some cleanup, and some
fixes for proper DM migration.

Finally, patches 5 and 6 have been changed a bit: I've cleaned
up the devicetree, the board support files and the defconfig.

This is based on top of today's master (7ff485c68b7e) and has
been tested by SD-card booting both U-Boot and Linux. Booting
Linux via TFTP was also tested.

Please note that I've added Paul's SOB to all the patches
he authored, to make the authorship chain more clear.

Reviews and tests are welcome. Bikesheds not so much! ;-)

Thanks!

Paul Burton (6):
  misc: Add JZ47xx efuse driver
  gpio: Add JZ47xx GPIO driver
  mmc: Add JZ47xx SD/MMC controller driver
  mips: Add SPL header
  mips: jz47xx: Add JZ4780 SoC support
  mips: jz47xx: Add Creator CI20 platform

 arch/mips/Kconfig |   7 +
 arch/mips/Makefile|   1 +
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 120 
 arch/mips/dts/jz4780.dtsi | 162 ++
 arch/mips/include/asm/spl.h   |  35 ++
 arch/mips/mach-jz47xx/Kconfig |  26 +
 arch/mips/mach-jz47xx/Makefile|   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h   | 104 
 .../mach-jz47xx/include/mach/jz4780_dram.h| 457 +++
 arch/mips/mach-jz47xx/jz4780/Makefile |   5 +
 arch/mips/mach-jz47xx/jz4780/jz4780.c | 142 +
 arch/mips/mach-jz47xx/jz4780/pll.c| 528 ++
 arch/mips/mach-jz47xx/jz4780/sdram.c  | 271 +
 arch/mips/mach-jz47xx/jz4780/timer.c  | 238 
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds   |  52 ++
 arch/mips/mach-jz47xx/start.S |  99 
 board/imgtec/ci20/Kconfig |  15 +
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 +
 board/imgtec/ci20/ci20.c  | 365 
 configs/ci20_defconfig|  47 ++
 drivers/gpio/Kconfig  |   7 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/gpio-jz47xx.c|  78 +++
 drivers/misc/Kconfig  |   6 +
 drivers/misc/Makefile |   1 +
 drivers/misc/jz4780_efuse.c   | 100 
 drivers/mmc/Kconfig   |   6 +
 drivers/mmc/Makefile  |   1 +
 drivers/mmc/jz_mmc.   |   0
 drivers/mmc/jz_mmc.c  | 491 
 include/configs/ci20.h|  74 +++
 include/dt-bindings/clock/jz4780-cgu.h|  88 +++
 34 files changed, 3550 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/include/asm/spl.h
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 drivers/gpio/gpio-jz47xx.c
 create mode 100644 drivers/misc/jz4780_efuse.c
 create mode 100644 drivers/mmc/jz_mmc.
 create mode 100644 drivers/mmc/jz_mmc.c
 create mode 100644 include/configs/ci20.h
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

-- 
2.20.0.rc2

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[U-Boot] [PATCH 2/6] gpio: Add JZ47xx GPIO driver

[Ezequiel Garcia]

From: Paul Burton 

Add primitive GPIO controller driver for the JZ47xx SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
---
 drivers/gpio/Kconfig   |  7 
 drivers/gpio/Makefile  |  1 +
 drivers/gpio/gpio-jz47xx.c | 78 ++
 3 files changed, 86 insertions(+)
 create mode 100644 drivers/gpio/gpio-jz47xx.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 35344e57c6c6..46c161c99ce9 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -322,4 +322,11 @@ config MT7621_GPIO
help
  Say yes here to support MediaTek MT7621 compatible GPIOs.
 
+config JZ47XX_GPIO
+   bool "Ingenic JZ47xx GPIO driver"
+   depends on ARCH_JZ47XX
+   default y
+   help
+ Supports GPIO access on Ingenic JZ47xx SoCs.
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7ed9a4ec4221..92310e9ba934 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,3 +59,4 @@ obj-$(CONFIG_MSM_GPIO)+= msm_gpio.o
 obj-$(CONFIG_$(SPL_)PCF8575_GPIO)  += pcf8575_gpio.o
 obj-$(CONFIG_PM8916_GPIO)  += pm8916_gpio.o
 obj-$(CONFIG_MT7621_GPIO)  += mt7621_gpio.o
+obj-$(CONFIG_JZ47XX_GPIO)  += gpio-jz47xx.o
diff --git a/drivers/gpio/gpio-jz47xx.c b/drivers/gpio/gpio-jz47xx.c
new file mode 100644
index ..565108192306
--- /dev/null
+++ b/drivers/gpio/gpio-jz47xx.c
@@ -0,0 +1,78 @@
+/*
+ * Ingenic JZ47xx GPIO
+ *
+ * Copyright (C) 2018 Marek Vasut 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int gpio_get_value(unsigned gpio)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   if (value)
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT0S(port));
+   else
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT0C(port));
+
+   return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port));
+
+   return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port));
+
+   gpio_set_value(gpio, value);
+
+   return 0;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+   int port = gpio / 32;
+
+   if (port >= 6)
+   return -EINVAL;
+
+   return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+   return 0;
+}
-- 
2.20.0.rc2

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[U-Boot] [PATCH 1/6] misc: Add JZ47xx efuse driver

[Ezequiel Garcia]

From: Paul Burton 

Add driver for the efuse block in the JZ47xx SOC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
---
 drivers/misc/Kconfig|   6 +++
 drivers/misc/Makefile   |   1 +
 drivers/misc/jz4780_efuse.c | 100 
 3 files changed, 107 insertions(+)
 create mode 100644 drivers/misc/jz4780_efuse.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 48febc47d263..704c8dd1955f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -120,6 +120,12 @@ config FSL_SEC_MON
  Security Monitor can be transitioned on any security failures,
  like software violations or hardware security violations.
 
+config JZ4780_EFUSE
+   bool "Ingenic JZ4780 eFUSE support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the eFUSE on Ingenic JZ4780 SoCs.
+
 config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 302d44159274..6bdf5054f475 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -62,3 +62,4 @@ obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
 obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c
new file mode 100644
index ..78383f343dce
--- /dev/null
+++ b/drivers/misc/jz4780_efuse.c
@@ -0,0 +1,100 @@
+/*
+ * JZ4780 EFUSE driver
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ * Author: Alex Smith 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define EFUSE_EFUCTRL  0xd0
+#define EFUSE_EFUCFG   0xd4
+#define EFUSE_EFUSTATE 0xd8
+#define EFUSE_EFUDATA(n)   (0xdc + ((n) * 4))
+
+#define EFUSE_EFUCTRL_RD_ENBIT(0)
+#define EFUSE_EFUCTRL_LEN_BIT  16
+#define EFUSE_EFUCTRL_LEN_MASK 0x1f
+#define EFUSE_EFUCTRL_ADDR_BIT 21
+#define EFUSE_EFUCTRL_ADDR_MASK0x1ff
+#define EFUSE_EFUCTRL_CS   BIT(30)
+
+#define EFUSE_EFUCFG_RD_STROBE_BIT 16
+#define EFUSE_EFUCFG_RD_STROBE_MASK0xf
+#define EFUSE_EFUCFG_RD_ADJ_BIT20
+#define EFUSE_EFUCFG_RD_ADJ_MASK   0xf
+
+#define EFUSE_EFUSTATE_RD_DONE BIT(0)
+
+static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   size_t i;
+   u32 val;
+
+   val = EFUSE_EFUCTRL_RD_EN |
+ ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
+ (addr << EFUSE_EFUCTRL_ADDR_BIT) |
+ ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
+   writel(val, regs + EFUSE_EFUCTRL);
+   /* FIXME -- wait_bit() */
+   while (!(readl(regs + EFUSE_EFUSTATE) & EFUSE_EFUSTATE_RD_DONE))
+   ;
+
+   if ((count % 4) == 0) {
+   for (i = 0; i < count / 4; i++) {
+   val = readl(regs + EFUSE_EFUDATA(i));
+   put_unaligned(val, (u32 *)(buf + (i * 4)));
+   }
+   } else {
+   val = readl(regs + EFUSE_EFUDATA(0));
+   if (count > 2)
+   buf[2] = (val >> 16) & 0xff;
+   if (count > 1)
+   buf[1] = (val >> 8) & 0xff;
+   buf[0] = val & 0xff;
+   }
+}
+
+static inline int jz4780_efuse_chunk_size(size_t count)
+{
+   if (count >= 32)
+   return 32;
+   else if ((count / 4) > 0)
+   return (count / 4) * 4;
+   else
+   return count % 4;
+}
+
+void jz4780_efuse_read(size_t addr, size_t count, u8 *buf)
+{
+   size_t chunk;
+
+   while (count > 0) {
+   chunk = jz4780_efuse_chunk_size(count);
+   jz4780_efuse_read_chunk(addr, chunk, buf);
+   addr += chunk;
+   buf += chunk;
+   count -= chunk;
+   }
+}
+
+void jz4780_efuse_init(u32 ahb2_rate)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   u32 rd_adj, rd_strobe, tmp;
+
+   rd_adj = (((6500 * (ahb2_rate / 100)) / 100) + 0xf) / 2;
+   tmp = (((35000 * (ahb2_rate / 100)) / 100) - 4) - rd_adj;
+   rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2;
+
+   tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) |
+ (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT);
+   writel(tmp, regs + EFUSE_EFUCFG);
+}
-- 
2.20.0.rc2

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Re: [U-Boot] [U-Boot, v3, 4/4] rockchip: rk3399: Add Ficus EE board support

[Ezequiel Garcia]

On Tue, 2018-12-04 at 22:21 +0100, Philipp Tomsich wrote:
> Peter (Robinson) already asked: I had lost this series one during a rebase 
> screw-up
> and will send out the PR as soon as it’s through Travis-CI.
> 

Thanks for the quick reply.

Should you need anything from me or Mani, please let us know.

Thanks!
Eze

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Re: [U-Boot] [U-Boot, v3, 4/4] rockchip: rk3399: Add Ficus EE board support

[Ezequiel Garcia]

On Wed, 2018-10-03 at 21:35 +0200, Philipp Tomsich wrote:
> > Add board support for Ficus EE board from Vamrs. This board utilizes
> > common Rock960 family support.
> > 
> > Following peripherals are tested and known to work:
> > * Gigabit Ethernet
> > * USB 2.0
> > * MMC
> > 
> > Signed-off-by: Ezequiel Garcia 
> > [Reworked based on common Rock960 family support]
> > Signed-off-by: Manivannan Sadhasivam 
> > Reviewed-by: Simon Glass 
> > ---
> > 
> > Changes in v3: Modified the DRAM config header from LPDDR3 to DDR3
> > 
> > Changes in v2: None
> > 
> >  arch/arm/dts/Makefile  |  1 +
> >  arch/arm/dts/rk3399-ficus.dts  | 78 ++
> >  configs/ficus-rk3399_defconfig | 71 +++
> >  3 files changed, 150 insertions(+)
> >  create mode 100644 arch/arm/dts/rk3399-ficus.dts
> >  create mode 100644 configs/ficus-rk3399_defconfig
> > 
> 
> Reviewed-by: Philipp Tomsich 

Two months have passed... guys, what's the problem with this series?

Regards,
Ezequiel


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Re: [U-Boot] [U-Boot, v3, 3/4] rockchip: rk3399: Add Rock960 CE board support

[Ezequiel Garcia]

On Wed, 2018-10-03 at 21:35 +0200, Philipp Tomsich wrote:
> > Add board support for Rock960 CE board from Vamrs. This board utilizes
> > common Rock960 family support.
> > 
> > Following peripherals are tested and known to work:
> > * USB 2.0
> > * MMC
> > 
> > This commit also adds DDR configuration for LPDDR3-2GiB-1600MHz which
> > is being used on the board.
> > 
> > Signed-off-by: Manivannan Sadhasivam 
> > Reviewed-by: Simon Glass 
> > Tested-by: Peter Robinson 
> > ---
> > 
> > Changes in v3:
> > 
> > * Add config options for USB to Ethernet and USB2 PHY
> > 
> > Changes in v2:
> > 
> > * Added missing config options for USB/uSD
> > * Fixed the commit description for DDR speed
> > 
> >  arch/arm/dts/Makefile |1 +
> >  arch/arm/dts/rk3399-rock960.dts   |   45 +
> >  .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 1536 +
> >  configs/rock960-rk3399_defconfig  |   69 +
> >  4 files changed, 1651 insertions(+)
> >  create mode 100644 arch/arm/dts/rk3399-rock960.dts
> >  create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
> >  create mode 100644 configs/rock960-rk3399_defconfig
> > 
> 
> Reviewed-by: Philipp Tomsich 
> 

What's the status of this series?

Thanks,
Eze


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Re: [U-Boot] [PATCH v3 2/4] rockchip: rk3399: Add common Rock960 family from Vamrs

[Ezequiel Garcia]

On Wed, 2018-10-03 at 21:34 +0200, Philipp Tomsich wrote:
> > On 02.10.2018, at 16:01, Manivannan Sadhasivam 
> >  wrote:
> > 
> > Hi Simon,
> > 
> > On Tue, Oct 02, 2018 at 04:21:38AM -0700, Simon Glass wrote:
> > > On 27 September 2018 at 12:02, Manivannan Sadhasivam
> > >  wrote:
> > > > Rock960 is a family of boards based on Rockchip RK3399 SoC from Vamrs.
> > > > It consists of Rock960 (Consumer Edition) and Ficus (Enterprise Edition)
> > > > 96Boards.
> > > > 
> > > > Below are some of the key differences between both Rock960 and Ficus
> > > > boards:
> > > > 
> > > > 1. Different host enable GPIO for USB
> > > > 2. Different power and reset GPIO for PCI-E
> > > > 3. No Ethernet port on Rock960
> > > > 
> > > > The common board support will be utilized by both boards. The device
> > > > tree has been organized in such a way that only the properties which
> > > > differ between both boards are placed in the board specific dts and
> > > > the reset of the nodes are placed in common dtsi file.
> > > > 
> > > > Signed-off-by: Manivannan Sadhasivam 
> > > > [Added instructions for SD card boot]
> > > > Signed-off-by: Ezequiel Garcia 
> > > > ---
> > > > 
> > > > Changes in v3: Added instruction for copying prebuilt bl31.elf for SPL
> > > > 
> > > > Changes in v2: None
> > > > 
> > > > arch/arm/dts/rk3399-rock960.dtsi| 506 
> > > > arch/arm/mach-rockchip/rk3399/Kconfig   |  26 +
> > > > board/vamrs/rock960_rk3399/Kconfig  |  15 +
> > > > board/vamrs/rock960_rk3399/MAINTAINERS  |   6 +
> > > > board/vamrs/rock960_rk3399/Makefile |   6 +
> > > > board/vamrs/rock960_rk3399/README   | 152 ++
> > > > board/vamrs/rock960_rk3399/rock960-rk3399.c |  50 ++
> > > > include/configs/rock960_rk3399.h|  15 +
> > > > 8 files changed, 776 insertions(+)
> > > > create mode 100644 arch/arm/dts/rk3399-rock960.dtsi
> > > > create mode 100644 board/vamrs/rock960_rk3399/Kconfig
> > > > create mode 100644 board/vamrs/rock960_rk3399/MAINTAINERS
> > > > create mode 100644 board/vamrs/rock960_rk3399/Makefile
> > > > create mode 100644 board/vamrs/rock960_rk3399/README
> > > > create mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c
> > > > create mode 100644 include/configs/rock960_rk3399.h
> > > 
> > > Reviewed-by: Simon Glass 
> > > 
> > > Could you also add a note to README.rockchip? Some of your docs seem
> > > to duplicate what is there.
> > 
> > Thanks for your review!
> > 
> > You mean, I should skip the duplicate instructions and add a pointer to
> > relevant sections in Rockchip README?
> 
> I also had had a similar comment on an earlier series: we should avoid just 
> copying these
> instructions verbatim into every new board: if these are indeed identical to 
> Rockchip’s EVB
> (i.e. if the board-vendor completely relies on the chip-vendor's tools), they 
> should reference
> back to the EVB’s README instead of duplicating the content.
> 

Yes, I agree here. The instructions are almost 100% SoC-specific, not board 
specific.
Having a doc per SoC is the way to go, IMO.

Philipp: do you think it's acceptable that this is done as follow-up patches?

Thanks!
Eze
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Re: [U-Boot] [PATCH 0/2] Add Rock960 board support

[Ezequiel Garcia]

On 31 August 2018 at 09:24, Manivannan Sadhasivam
 wrote:
> On Fri, Aug 31, 2018 at 09:08:08AM -0300, Ezequiel Garcia wrote:
>> On 31 August 2018 at 07:56, Peter Robinson  wrote:
>> >> On Thu, Aug 30, 2018 at 12:44:00AM -0300, Ezequiel Garcia wrote:
>> >> > On 30 August 2018 at 00:00, Manivannan Sadhasivam
>> >> >  wrote:
>> >> > > Hi Ezequiel,
>> >> > >
>> >> > > On Wed, Aug 29, 2018 at 03:11:17AM -0300, Ezequiel Garcia wrote:
>> >> > >> Hi Manivannan,
>> >> > >>
>> >> > >> On 21 August 2018 at 14:09, Manivannan Sadhasivam
>> >> > >>  wrote:
>> >> > >> > This patchset adds board support for Vamrs Limited Rock960,
>> >> > >> > which is one of the 96Boards Consumer Edition platform based
>> >> > >> > on Rockchip RK3399 SoC.
>> >> > >> >
>> >> > >>
>> >> > >> What are the differences between this consumer edition board,
>> >> > >> and the enterprise edition (aka Ficus) Vamrs board?
>> >> > >>
>> >> > >
>> >> > > I asked Vamrs about this and they said the difference is very minimal.
>> >> > >
>> >> >
>> >> > In that case, you should try to leverage the Linux ficus.dts:
>> >> >
>> >> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
>> >> >
>> >> > If no differences, using the ficus dts should do. If there are 
>> >> > differences,
>> >> > we can create a common rock960.dtsi and then enterprise and consumer
>> >> > edition dts.
>> >> >
>> >>
>> >> Okay. Here are the differences between Ficus and Rock960 CE:
>> >>
>> >> 1. Different host enable GPIO for USB (vcc5v0_host)
>> >> 2. Different power and reset for PCI-E (vcc3v3_pcie, pcie0)
>> >> 3. No Ethernet port on Rock960 (gmac)
>> >>
>> >> So, I would suggest keeping USB, PCI-E and GMAC related nodes on the board
>> >> specific devicetree and rest on the rk3399-rock960.dtsi. What do you 
>> >> think?
>> >>
>> >> Same applies to Linux also!
>> >
>>
>> Sounds good. If you have some cycles to work on the dts/dtsi split,
>> that would be great.
>>
>
> Sure, will do it for Linux now. Once your u-boot patches gets in,
> will tackle it also.
>

Well, I think we can tackle u-boot from scratch. No need to
merge my patches if we think they are already wrong :-)

>> > Yes, I think a rk3399-rock960.dtsi with the differences in two .dts
>> > would be great, and even better a single U-Boot which can detect the
>> > board and load the right DT, but I do think it should be a separate
>> > config to evb as Mani mentioned.
>> >
>
> Thanks Peter for your thoughts!
>
>>
>> Sounds good too. That'd make board-specific hooks easier.
>>
>> On the other side, the documentation should be
>> merged somewhere.
>>
>> Seems nonsense to have a README per board,
>> with more or less the same instructions each time.
>>
>
> This has other side as well. If we continue to merge board specific
> instructions onto evb-rk3399, it will become messy. So, IMO it's better
> to have it separate. If you have other ideas, please let me know.
>

Bootloader wise, there is no such thing as board specific instructions, is it?
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Re: [U-Boot] [PATCH 0/2] Add Rock960 board support

[Ezequiel Garcia]

On 31 August 2018 at 07:56, Peter Robinson  wrote:
>> On Thu, Aug 30, 2018 at 12:44:00AM -0300, Ezequiel Garcia wrote:
>> > On 30 August 2018 at 00:00, Manivannan Sadhasivam
>> >  wrote:
>> > > Hi Ezequiel,
>> > >
>> > > On Wed, Aug 29, 2018 at 03:11:17AM -0300, Ezequiel Garcia wrote:
>> > >> Hi Manivannan,
>> > >>
>> > >> On 21 August 2018 at 14:09, Manivannan Sadhasivam
>> > >>  wrote:
>> > >> > This patchset adds board support for Vamrs Limited Rock960,
>> > >> > which is one of the 96Boards Consumer Edition platform based
>> > >> > on Rockchip RK3399 SoC.
>> > >> >
>> > >>
>> > >> What are the differences between this consumer edition board,
>> > >> and the enterprise edition (aka Ficus) Vamrs board?
>> > >>
>> > >
>> > > I asked Vamrs about this and they said the difference is very minimal.
>> > >
>> >
>> > In that case, you should try to leverage the Linux ficus.dts:
>> >
>> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
>> >
>> > If no differences, using the ficus dts should do. If there are differences,
>> > we can create a common rock960.dtsi and then enterprise and consumer
>> > edition dts.
>> >
>>
>> Okay. Here are the differences between Ficus and Rock960 CE:
>>
>> 1. Different host enable GPIO for USB (vcc5v0_host)
>> 2. Different power and reset for PCI-E (vcc3v3_pcie, pcie0)
>> 3. No Ethernet port on Rock960 (gmac)
>>
>> So, I would suggest keeping USB, PCI-E and GMAC related nodes on the board
>> specific devicetree and rest on the rk3399-rock960.dtsi. What do you think?
>>
>> Same applies to Linux also!
>

Sounds good. If you have some cycles to work on the dts/dtsi split,
that would be great.

> Yes, I think a rk3399-rock960.dtsi with the differences in two .dts
> would be great, and even better a single U-Boot which can detect the
> board and load the right DT, but I do think it should be a separate
> config to evb as Mani mentioned.
>

Sounds good too. That'd make board-specific hooks easier.

On the other side, the documentation should be
merged somewhere.

Seems nonsense to have a README per board,
with more or less the same instructions each time.

Thanks!
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Re: [U-Boot] [PATCH 0/2] Add Rock960 board support

[Ezequiel Garcia]

On 30 August 2018 at 00:00, Manivannan Sadhasivam
 wrote:
> Hi Ezequiel,
>
> On Wed, Aug 29, 2018 at 03:11:17AM -0300, Ezequiel Garcia wrote:
>> Hi Manivannan,
>>
>> On 21 August 2018 at 14:09, Manivannan Sadhasivam
>>  wrote:
>> > This patchset adds board support for Vamrs Limited Rock960,
>> > which is one of the 96Boards Consumer Edition platform based
>> > on Rockchip RK3399 SoC.
>> >
>>
>> What are the differences between this consumer edition board,
>> and the enterprise edition (aka Ficus) Vamrs board?
>>
>
> I asked Vamrs about this and they said the difference is very minimal.
>

In that case, you should try to leverage the Linux ficus.dts:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts

If no differences, using the ficus dts should do. If there are differences,
we can create a common rock960.dtsi and then enterprise and consumer
edition dts.

>> Perhaps the devicetree and the board support can be
>> shared with ficus support?
>>
>
> I'm fine with it but you seem to have added Ficus board under
> evb_rk3399 which I think not the good place. Since the board
> manufacturer is different, I would suggest you to place it under
> boards/vamrs as I have done here. Also with more boards coming from
> Vamrs, this makes much more sense.
>
> Please let me know your thoughts!
>

Well, I've reused the evb support, because there was no reason
to have board-specific code. If we have now a reason, then of course
having a board dir makes sense.

When possible, we should try to avoid code duplication and scattering.
For instance, the instructions in the README look RK3399 generic
and not board specific. We should consolidate that.
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Re: [U-Boot] [PATCH 0/2] Add Rock960 board support

[Ezequiel Garcia]

Hi Manivannan,

On 21 August 2018 at 14:09, Manivannan Sadhasivam
 wrote:
> This patchset adds board support for Vamrs Limited Rock960,
> which is one of the 96Boards Consumer Edition platform based
> on Rockchip RK3399 SoC.
>

What are the differences between this consumer edition board,
and the enterprise edition (aka Ficus) Vamrs board?

Perhaps the devicetree and the board support can be
shared with ficus support?

I submitted v2 moments ago:

https://patchwork.ozlabs.org/patch/963241/
https://patchwork.ozlabs.org/patch/963242/

Regards,
Ezequiel


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Re: [U-Boot] [PATCH 2/2] board: Add Vamrs Limited Rock960 board support

[Ezequiel Garcia]

On 21 August 2018 at 14:09, Manivannan Sadhasivam
 wrote:
> Add board support for Vamrs Limited Rock960 board, which is
> one of the 96Boards Consumer Edition platform.
>
> Rock960 features:
> * CPU: ARMv8 64bit Big-Little architecture,
> * Big: dual-core Cortex-A72
> * Little: quad-core Cortex-A53
> * IRAM: 200KB
> * DRAM: 2GB/4GB LPDDR3 @ 1866MHz
> * eMMC: 16/32GB eMMC 5.1
> * PMU: RK808
> * SD/MMC
> * USB:
> * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only) and
>   1x USB 3.0 type C OTG
> * Display:
> * 1x HDMI 2.0(Type A - full) up to 4Kx2K@60Hz,
>   1x 4L - MIPI DSI up to 1080p@60Hz,
>   1x DP 1.2(Type C) up to 4Kx2K@60
> * Camera: 2x 4-lane MIPI CSI
> * PCI-E: 4- lane M.2 PCI-E 2.1
> * Low Speed Expansion Connector
> * High Speed Expansion Connector
>
> Signed-off-by: Manivannan Sadhasivam 
> ---
>  arch/arm/mach-rockchip/rk3399/Kconfig   | 16 +
>  board/vamrs/rock960_rk3399/Kconfig  | 15 
>  board/vamrs/rock960_rk3399/MAINTAINERS  |  6 ++
>  board/vamrs/rock960_rk3399/Makefile |  6 ++
>  board/vamrs/rock960_rk3399/README   | 79 +
>  board/vamrs/rock960_rk3399/rock960-rk3399.c | 50 +
>  configs/rock960-rk3399_defconfig| 62 
>  include/configs/rock960_rk3399.h| 15 
>  8 files changed, 249 insertions(+)
>  create mode 100644 board/vamrs/rock960_rk3399/Kconfig
>  create mode 100644 board/vamrs/rock960_rk3399/MAINTAINERS
>  create mode 100644 board/vamrs/rock960_rk3399/Makefile
>  create mode 100644 board/vamrs/rock960_rk3399/README
>  create mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c
>  create mode 100644 configs/rock960-rk3399_defconfig
>  create mode 100644 include/configs/rock960_rk3399.h
>
> diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig 
> b/arch/arm/mach-rockchip/rk3399/Kconfig
> index 415466a49bb..ce4605187e3 100644
> --- a/arch/arm/mach-rockchip/rk3399/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3399/Kconfig
> @@ -28,6 +28,21 @@ config TARGET_PUMA_RK3399
>* HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI
>* SPI, I2C, I2S, UART, GPIO, ...
>
> +config TARGET_ROCK960_RK3399
> +   bool "Vamrs Limited Rock960 board"
> +   help
> + Support for Rock960 board. This board complies with
> + 96Board Consumer Edition Specification.
> +
> + Features:
> +  * Rockchip RK3399 SoC (2xCortex A72, 4xCortex A53, ARM Mali 
> T860MP4)
> +  * 2GiB/4GiB RAM
> +  * 16/32GB eMMC, uSD slot
> +  * WiFi, Bluetooth
> +  * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only), 1x USB 
> 3.0 type C OTG
> +  * HDMI
> +  * 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 
> buttons
> +
>  endchoice
>
>  config SYS_SOC
> @@ -38,5 +53,6 @@ config SYS_MALLOC_F_LEN
>
>  source "board/rockchip/evb_rk3399/Kconfig"
>  source "board/theobroma-systems/puma_rk3399/Kconfig"
> +source "board/vamrs/rock960_rk3399/Kconfig"
>
>  endif
> diff --git a/board/vamrs/rock960_rk3399/Kconfig 
> b/board/vamrs/rock960_rk3399/Kconfig
> new file mode 100644
> index 000..cacc53f3780
> --- /dev/null
> +++ b/board/vamrs/rock960_rk3399/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_ROCK960_RK3399
> +
> +config SYS_BOARD
> +   default "rock960_rk3399"
> +
> +config SYS_VENDOR
> +   default "vamrs"
> +
> +config SYS_CONFIG_NAME
> +   default "rock960_rk3399"
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +   def_bool y
> +
> +endif
> diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS 
> b/board/vamrs/rock960_rk3399/MAINTAINERS
> new file mode 100644
> index 000..9f3fe75f4fb
> --- /dev/null
> +++ b/board/vamrs/rock960_rk3399/MAINTAINERS
> @@ -0,0 +1,6 @@
> +ROCK960-RK3399
> +M:  Manivannan Sadhasivam manivannan.sadhasi...@linaro.org
> +S:  Maintained
> +F:  board/rockchip/rock960_rk3399
> +F:  include/configs/rock960_rk3399.h
> +F:  configs/rock960-rk3399_defconfig
> diff --git a/board/vamrs/rock960_rk3399/Makefile 
> b/board/vamrs/rock960_rk3399/Makefile
> new file mode 100644
> index 000..6c3e475b3a8
> --- /dev/null
> +++ b/board/vamrs/rock960_rk3399/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2018 Manivannan Sadhasivam 
> +#
> +
> +obj-y  += rock960-rk3399.o
> diff --git a/board/vamrs/rock960_rk3399/README 
> b/board/vamrs/rock960_rk3399/README
> new file mode 100644
> index 000..be6b5cd1d34
> --- /dev/null
> +++ b/board/vamrs/rock960_rk3399/README
> @@ -0,0 +1,79 @@
> +Introduction
> +
> +
> +Rock960 is a 96Boards Consumer Edition platform featuring the Rockchip
> +RK3399 SoC.
> +
> +Rock960 features:
> +   * CPU: ARMv8 64bit Big-Little architecture,
> +   * 

[U-Boot] [PATCH v2 3/3] rockchip: rk3399: Add more instructions to the README

[Ezequiel Garcia]

This commit adds a content section and also instructions
on how to create a bootable SD/MMC device for RK3399 boards.

Acked-by: Philipp Tomsich 
Reviewed-by: Simon Glass 
Signed-off-by: Ezequiel Garcia 
---
 board/rockchip/evb_rk3399/README | 55 ++--
 1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README
index d08e2ea13147..4d283dc31d48 100644
--- a/board/rockchip/evb_rk3399/README
+++ b/board/rockchip/evb_rk3399/README
@@ -1,3 +1,21 @@
+Contents
+
+
+1. Introduction
+2. Get the Source and prebuild binary
+3. Compile the ATF
+4. Compile the U-Boot
+5. Compile the rkdeveloptool
+6. Package the image
+   6.1. Package the image for U-Boot SPL(option 1)
+   6.2. Package the image for Rockchip miniloader(option 2)
+7. Bootloader storage options
+8. Flash the image to eMMC
+   8.1. Flash the image with U-Boot SPL(option 1)
+   8.2. Flash the image with Rockchip miniloader(option 2)
+9. Create a bootable SD/MMC
+10. And that is it
+
 Introduction
 
 
@@ -97,6 +115,12 @@ Package the image for Rockchip miniloader(option 2)
 
   Get trust.img and uboot.img in this step.
 
+Bootloader storage options
+==
+
+There are a few different storage options for the bootloader.
+This document explores two of these: eMMC and removable SD/MMC.
+
 Flash the image to eMMC
 ===
 
@@ -117,6 +141,33 @@ Power on(or reset with RESET KEY) with MASKROM KEY 
preesed, and then:
   > rkdeveloptool wl 0x6000 u-boot/trust.img
   > rkdeveloptool rd
 
+Create a bootable SD/MMC
+
+
+The idbspl.img contains the first stage, and the u-boot.img the second stage.
+As explained in the Rockchip partition table reference [2], the first stage
+(aka loader1) start sector is 64, and the second stage start sector is 16384.
+
+Each sector is 512 bytes, which means the first stage offset is 32 KiB,
+and the second stage offset is 8 MiB.
+
+Note: the second stage location is actually not as per the spec,
+but defined by the SPL. Mainline SPL defines an 8 MiB offset for the second
+stage.
+
+Assuming the SD card is exposed by device /dev/mmcblk0, the commands
+to write the two stages are:
+
+  > dd if=idbspl.img of=/dev/mmcblk0 bs=1k seek=32
+  > dd if=u-boot.itb of=/dev/mmcblk0 bs=1k seek=8192
+
+Setting up the kernel and rootfs is beyond the scope of this document.
+
+And that is it
+==
+
 You should be able to get U-Boot log in console/UART2(baurdrate 150)
-For more detail, please reference to:
-http://opensource.rock-chips.com/wiki_Boot_option
+For more detail, please reference [2].
+
+[1] http://opensource.rock-chips.com/wiki_Partitions
+[2] http://opensource.rock-chips.com/wiki_Boot_option
-- 
2.18.0

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[U-Boot] [PATCH v2 2/3] rockchip: rk3399: add Ficus board

[Ezequiel Garcia]

This commit adds support for RK3399 Ficus board,
aka ROCK960 Enterprise Edition.

Following peripherals are tested and known to work:
* Gigabit Ethernet
* USB 2.0
* MMC

Acked-by: Philipp Tomsich 
Signed-off-by: Ezequiel Garcia 
---
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/rk3399-ficus.dts| 564 +++
 board/rockchip/evb_rk3399/README |   2 +
 configs/ficus-rk3399_defconfig   |  70 
 4 files changed, 637 insertions(+)
 create mode 100644 arch/arm/dts/rk3399-ficus.dts
 create mode 100644 configs/ficus-rk3399_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ebfa2272627b..9aaee42c1521 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
rk3399-evb.dtb \
+   rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts
new file mode 100644
index ..db015a26
--- /dev/null
+++ b/arch/arm/dts/rk3399-ficus.dts
@@ -0,0 +1,564 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
+ */
+
+/dts-v1/;
+#include 
+#include "rk3399.dtsi"
+#include "rk3399-sdram-ddr3-1600.dtsi"
+
+/ {
+   model = "96boards RK3399 Ficus";
+   compatible = "vamrs,ficus", "rockchip,rk3399";
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   clkin_gmac: external-gmac-clock {
+   compatible = "fixed-clock";
+   clock-frequency = <12500>;
+   clock-output-names = "clkin_gmac";
+   #clock-cells = <0>;
+   };
+
+   vcc1v8_s0: vcc1v8-s0 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc1v8_s0";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   };
+
+   vcc_sys: vcc-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_sys";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
+
+   vcc3v3_sys: vcc3v3-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   vin-supply = <_sys>;
+   };
+
+   vcc3v3_pcie: vcc3v3-pcie-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 24 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_drv>;
+   regulator-boot-on;
+   regulator-name = "vcc3v3_pcie";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <_sys>;
+   };
+
+   vcc5v0_host: vcc5v0-host-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 27 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_vbus_drv>;
+   regulator-name = "vcc5v0_host";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   vin-supply = <_sys>;
+   };
+
+   vdd_log: vdd-log {
+   compatible = "pwm-regulator";
+   pwms = < 0 25000 0>;
+   regulator-name = "vdd_log";
+   regulator-min-microvolt = <80>;
+   regulator-max-microvolt = <140>;
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <_sys>;
+   };
+};
+
+_l0 {
+   cpu-supply = <_cpu_l>;
+};
+
+_l1 {
+   cpu-supply = <_cpu_l>;
+};
+
+_l2 {
+   cpu-supply = <_cpu_l>;
+};
+
+_l3 {
+   cpu-supply = <_cpu_l>;
+};
+
+_b0 {
+   cpu-supply = <_cpu_b>;
+};
+
+_b1 {
+   cpu-supply = <_cpu_b>;
+};
+
+_phy {
+   status = "okay";
+};
+
+ {
+   assigned-clocks = < SCLK_RMII_SRC>;
+   assigned-clock-parents = <_gmac>;
+ 

[U-Boot] [PATCH v2 0/3] RK3399: Add support for Ficus board

[Ezequiel Garcia]

Add support for a new RK3399-based board. The RK3399 Ficus
board is an Enterprise Edition board manufactured by Vamrs Ltd.,
based on the Rockchip RK3399 SoC.

While here, we extend the evb_rk3399/README document
with instructions for SD/MMC boot.

The devicetree file for this board has been already merged
in Linux maintainer's tree:

https://kernel.googlesource.com/pub/scm/linux/kernel/git/mmind/linux-rockchip/+/v4.19-armsoc/dts64/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts

Changes from v1:
  * Drop CONFIG_ROCKCHIP_USB2_PHY which wasn't
appropriate for this board, and also it was breaking
the build.
  * Tested on travis-ci.org.

Ezequiel Garcia (2):
  rockchip: rk3399: add Ficus board
  rockchip: rk3399: Add more instructions to the README

Randy Li (1):
  arm: dts: rockchip: add some common pin-settings to rk3399

 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/rk3399-ficus.dts| 564 +++
 arch/arm/dts/rk3399.dtsi |  55 ++-
 board/rockchip/evb_rk3399/README |  57 +++-
 configs/ficus-rk3399_defconfig   |  70 
 5 files changed, 739 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/dts/rk3399-ficus.dts
 create mode 100644 configs/ficus-rk3399_defconfig

-- 
2.18.0

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[U-Boot] [PATCH v2 1/3] arm: dts: rockchip: add some common pin-settings to rk3399

[Ezequiel Garcia]

From: Randy Li 

Those pins would be used by many boards.

Commit grabbed from Linux:

commit b41023282d07b61a53e2c9b9508912b1e7ce7b4f
Author: Randy Li 
Date:   Thu Jun 21 21:32:10 2018 +0800

arm64: dts: rockchip: add some common pin-settings to rk3399

Those pins would be used by many boards.

Signed-off-by: Randy Li 
Signed-off-by: Heiko Stuebner 

Acked-by: Philipp Tomsich 
Signed-off-by: Randy Li 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Ezequiel Garcia 
---
 arch/arm/dts/rk3399.dtsi | 55 +++-
 1 file changed, 49 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 83c257b1228b..8349451b03dc 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1602,19 +1602,49 @@
drive-strength = <12>;
};
 
+   pcfg_pull_none_13ma: pcfg-pull-none-13ma {
+   bias-disable;
+   drive-strength = <13>;
+   };
+
+   pcfg_pull_none_18ma: pcfg-pull-none-18ma {
+   bias-disable;
+   drive-strength = <18>;
+   };
+
+   pcfg_pull_none_20ma: pcfg-pull-none-20ma {
+   bias-disable;
+   drive-strength = <20>;
+   };
+
+   pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+   bias-pull-up;
+   drive-strength = <2>;
+   };
+
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
bias-pull-up;
drive-strength = <8>;
};
 
+   pcfg_pull_up_18ma: pcfg-pull-up-18ma {
+   bias-pull-up;
+   drive-strength = <18>;
+   };
+
+   pcfg_pull_up_20ma: pcfg-pull-up-20ma {
+   bias-pull-up;
+   drive-strength = <20>;
+   };
+
pcfg_pull_down_4ma: pcfg-pull-down-4ma {
bias-pull-down;
drive-strength = <4>;
};
 
-   pcfg_pull_up_2ma: pcfg-pull-up-2ma {
-   bias-pull-up;
-   drive-strength = <2>;
+   pcfg_pull_down_8ma: pcfg-pull-down-8ma {
+   bias-pull-down;
+   drive-strength = <8>;
};
 
pcfg_pull_down_12ma: pcfg-pull-down-12ma {
@@ -1622,9 +1652,22 @@
drive-strength = <12>;
};
 
-   pcfg_pull_none_13ma: pcfg-pull-none-13ma {
-   bias-disable;
-   drive-strength = <13>;
+   pcfg_pull_down_18ma: pcfg-pull-down-18ma {
+   bias-pull-down;
+   drive-strength = <18>;
+   };
+
+   pcfg_pull_down_20ma: pcfg-pull-down-20ma {
+   bias-pull-down;
+   drive-strength = <20>;
+   };
+
+   pcfg_output_high: pcfg-output-high {
+   output-high;
+   };
+
+   pcfg_output_low: pcfg-output-low {
+   output-low;
};
 
clock {
-- 
2.18.0

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Re: [U-Boot] [U-Boot,2/3] ARM: add RK3399 Ficus board

[Ezequiel Garcia]

On 25 July 2018 at 18:20, Dr. Philipp Tomsich
 wrote:
> Ezequiel,
>
>> On 25 Jul 2018, at 22:31, Ezequiel Garcia  wrote:
>>
>> On Sat, 2018-07-21 at 16:23 +0200, Dr. Philipp Tomsich wrote:
>>> Ezequiel,
>>>
>>> This series breaks the build (see 
>>> https://travis-ci.org/ptomsich/u-boot-rockchip/builds/406351695).
>>> Did you test with Travis prior to submitting?
>>>
>>
>> No, I haven't. It's quite odd, as the README patch just adds some 
>> documentation.
>
> I responded to this mail, as there’s no cover letter.
> It’s the series breaking the build, not the README change.
>
>> I am having a hard time figuring out how could it break the build,
>> and I do not see any logs in the travis-ci link either.
>
> Does the direct link to the line with the error work for you:
> https://travis-ci.org/ptomsich/u-boot-rockchip/jobs/406351815#L1330
>
> If not, I’ll have to copy this into a mail manually...
>

Right, I see it now. Thanks!


+drivers/usb/phy/rockchip_usb2_phy.c: In function 'property_enable':
+arch/arm/include/asm/io.h:49:29: error: cast to pointer from integer
of different size [-Werror=int-to-pointer-cast]
+ #define __arch_putl(v,a)  (*(volatile unsigned int *)(a) = (v))
+ ^
+arch/arm/include/asm/io.h:117:48: note: in expansion of macro '__arch_putl'
+ #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
+^~~
+drivers/usb/phy/rockchip_usb2_phy.c:61:2: note: in expansion of macro 'writel'
+  writel(val, pdata->regs_phy + reg->offset);
+  ^~

So, it seems that since the defconfig is enabling this USB PHY driver,
it's causing
the failure.

I'll see if I can fix this issue and send a patch, but it seems
totally orthogonal to the Ficus
patchset.

>>
>> Any ideas?
>>
>>> When you revise, I’d also prefer a ‘rockchip:’ and a ‘board:’ tag over the 
>>> ARM tag …
>>>
>>
>> OK, I will.
>>
>>> Thanks,
>>> Philipp.
>>>
>>>
>>>> On 20 Jul 2018, at 19:30, Philipp Tomsich 
>>>>  wrote:
>>>>
>>>>> This commit adds support for RK3399 Ficus board,
>>>>> aka ROCK960 Enterprise Edition.
>>>>>
>>>>> Following peripherals are tested and known to work:
>>>>> * Gigabit Ethernet
>>>>> * USB 2.0
>>>>> * MMC
>>>>>
>>>>> Signed-off-by: Ezequiel Garcia 
>>>>> Reviewed-by: Simon Glass 
>>>>> Reviewed-by: Philipp Tomsich 
>>>>> ---
>>>>> arch/arm/dts/Makefile|   1 +
>>>>> arch/arm/dts/rk3399-ficus.dts| 564 +++
>>>>> board/rockchip/evb_rk3399/README |   2 +
>>>>> configs/ficus-rk3399_defconfig   |  71 
>>>>> 4 files changed, 638 insertions(+)
>>>>> create mode 100644 arch/arm/dts/rk3399-ficus.dts
>>>>> create mode 100644 configs/ficus-rk3399_defconfig
>>>>>
>>>>
>>>> Acked-by: Philipp Tomsich 
>>>> ___
>>>> U-Boot mailing list
>>>> U-Boot@lists.denx.de
>>>> https://lists.denx.de/listinfo/u-boot
>>>
>>>
>>
>
> ___
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-- 
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www.vanguardiasur.com.ar
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Re: [U-Boot] [U-Boot,2/3] ARM: add RK3399 Ficus board

[Ezequiel Garcia]

On Sat, 2018-07-21 at 16:23 +0200, Dr. Philipp Tomsich wrote:
> Ezequiel,
> 
> This series breaks the build (see 
> https://travis-ci.org/ptomsich/u-boot-rockchip/builds/406351695).
> Did you test with Travis prior to submitting?
> 

No, I haven't. It's quite odd, as the README patch just adds some documentation.
I am having a hard time figuring out how could it break the build,
and I do not see any logs in the travis-ci link either.

Any ideas?

> When you revise, I’d also prefer a ‘rockchip:’ and a ‘board:’ tag over the 
> ARM tag …
> 

OK, I will.

> Thanks,
> Philipp.
> 
> 
> > On 20 Jul 2018, at 19:30, Philipp Tomsich 
> >  wrote:
> > 
> > > This commit adds support for RK3399 Ficus board,
> > > aka ROCK960 Enterprise Edition.
> > > 
> > > Following peripherals are tested and known to work:
> > > * Gigabit Ethernet
> > > * USB 2.0
> > > * MMC
> > > 
> > > Signed-off-by: Ezequiel Garcia 
> > > Reviewed-by: Simon Glass 
> > > Reviewed-by: Philipp Tomsich 
> > > ---
> > > arch/arm/dts/Makefile|   1 +
> > > arch/arm/dts/rk3399-ficus.dts| 564 +++
> > > board/rockchip/evb_rk3399/README |   2 +
> > > configs/ficus-rk3399_defconfig   |  71 
> > > 4 files changed, 638 insertions(+)
> > > create mode 100644 arch/arm/dts/rk3399-ficus.dts
> > > create mode 100644 configs/ficus-rk3399_defconfig
> > > 
> > 
> > Acked-by: Philipp Tomsich 
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
> 
> 

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Re: [U-Boot] [U-Boot, 1/3] arm: dts: rockchip: add some common pin-settings to rk3399

[Ezequiel Garcia]

On Fri, 2018-07-20 at 18:26 +0200, Philipp Tomsich wrote:
> 
> On Mon, 16 Jul 2018, Ezequiel Garcia wrote:
> 
> > From: Randy Li 
> > 
> > Those pins would be used by many boards.
> 
> The Rockchip pinctrl driver in U-Boot does not (yet) read the DTS for pin 
> configuration information.
> 
> Is this a sync of the Linux DTS (which seems unlikely, as I'd expect more 
> changes) or why are we doing this as part of this series?
> 

As a matter of fact, it is a sync. It is literally this commit:

https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.19-armsoc/dts64=b41023282d07b61a53e2c9b9508912b1e7ce7b4f

It's just needed so that at least the ficus.dts file compiles.

Thanks,
Eze
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Re: [U-Boot] [U-Boot, 3/3] rockchip: rk3399: Add more instructions to the README

[Ezequiel Garcia]

On Fri, 2018-07-20 at 18:28 +0200, Philipp Tomsich wrote:
> 
> On Mon, 16 Jul 2018, Ezequiel Garcia wrote:
> 
> > This commit adds a content section and also instructions
> > on how to create a bootable SD/MMC device for RK3399 boards.
> 
> Are any of these instructions Ficus-specific?  We have our own README for 
> our own boards, as these have different instructions from the EVB boards.
> 

Nope, it applies to any rk3399 board. And the rest of the file as well,
as long as the board has eMMC.

> Just wondering, as I'd have expected this to come in as part of the ficus 
> board-directory...
> 

Yeah, but all the instructions on this file applied to the Ficus
(and to many others) so I decided to just extend it for now.

If it needs moving to some generic doc, I think we can do that as a follow up 
patch.

> > Signed-off-by: Ezequiel Garcia 
> > Reviewed-by: Simon Glass 
> 
> Reviewed-by: Philipp Tomsich 
> 

Thanks for the review!
Eze
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Re: [U-Boot] [PATCH 3/3] rockchip: rk3399: Add more instructions to the README

[Ezequiel Garcia]

On Wed, 2018-07-18 at 19:32 -0600, Simon Glass wrote:
> On 16 July 2018 at 13:41, Ezequiel Garcia  wrote:
> > This commit adds a content section and also instructions
> > on how to create a bootable SD/MMC device for RK3399 boards.
> > 
> > Signed-off-by: Ezequiel Garcia 
> > ---
> >  board/rockchip/evb_rk3399/README | 55 ++--
> >  1 file changed, 53 insertions(+), 2 deletions(-)
> 
> Reviewed-by: Simon Glass 
> 
> Hmm, we should convert all of rockchip to use binman I think.
> 

Yeah, that would be sweet.
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[U-Boot] [PATCH 3/3] rockchip: rk3399: Add more instructions to the README

[Ezequiel Garcia]

This commit adds a content section and also instructions
on how to create a bootable SD/MMC device for RK3399 boards.

Signed-off-by: Ezequiel Garcia 
---
 board/rockchip/evb_rk3399/README | 55 ++--
 1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README
index 0b4c6d19ad39..3775d3ff447f 100644
--- a/board/rockchip/evb_rk3399/README
+++ b/board/rockchip/evb_rk3399/README
@@ -1,3 +1,21 @@
+Contents
+
+
+1. Introduction
+2. Get the Source and prebuild binary
+3. Compile the ATF
+4. Compile the U-Boot
+5. Compile the rkdeveloptool
+6. Package the image
+   6.1. Package the image for U-Boot SPL(option 1)
+   6.2. Package the image for Rockchip miniloader(option 2)
+7. Bootloader storage options
+8. Flash the image to eMMC
+   8.1. Flash the image with U-Boot SPL(option 1)
+   8.2. Flash the image with Rockchip miniloader(option 2)
+9. Create a bootable SD/MMC
+10. And that is it
+
 Introduction
 
 
@@ -97,6 +115,12 @@ Package the image for Rockchip miniloader(option 2)
 
   Get trust.img and uboot.img in this step.
 
+Bootloader storage options
+==
+
+There are a few different storage options for the bootloader.
+This document explores two of these: eMMC and removable SD/MMC.
+
 Flash the image to eMMC
 ===
 
@@ -117,6 +141,33 @@ Power on(or reset with RESET KEY) with MASKROM KEY 
preesed, and then:
   > rkdeveloptool wl 0x6000 u-boot/trust.img
   > rkdeveloptool rd
 
+Create a bootable SD/MMC
+
+
+The idbspl.img contains the first stage, and the u-boot.img the second stage.
+As explained in the Rockchip partition table reference [2], the first stage
+(aka loader1) start sector is 64, and the second stage start sector is 16384.
+
+Each sector is 512 bytes, which means the first stage offset is 32 KiB,
+and the second stage offset is 8 MiB.
+
+Note: the second stage location is actually not as per the spec,
+but defined by the SPL. Mainline SPL defines an 8 MiB offset for the second
+stage.
+
+Assuming the SD card is exposed by device /dev/mmcblk0, the commands
+to write the two stages are:
+
+  > dd if=idbspl.img of=/dev/mmcblk0 bs=1k seek=32
+  > dd if=u-boot.itb of=/dev/mmcblk0 bs=1k seek=8192
+
+Setting up the kernel and rootfs is beyond the scope of this document.
+
+And that is it
+==
+
 You should be able to get U-Boot log in console/UART2(baurdrate 150)
-For more detail, please reference to:
-http://opensource.rock-chips.com/wiki_Boot_option
+For more detail, please reference [2].
+
+[1] http://opensource.rock-chips.com/wiki_Partitions
+[2] http://opensource.rock-chips.com/wiki_Boot_option
-- 
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[U-Boot] [PATCH 2/3] ARM: add RK3399 Ficus board

[Ezequiel Garcia]

This commit adds support for RK3399 Ficus board,
aka ROCK960 Enterprise Edition.

Following peripherals are tested and known to work:
* Gigabit Ethernet
* USB 2.0
* MMC

Signed-off-by: Ezequiel Garcia 
---
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/rk3399-ficus.dts| 564 +++
 board/rockchip/evb_rk3399/README |   2 +
 configs/ficus-rk3399_defconfig   |  71 
 4 files changed, 638 insertions(+)
 create mode 100644 arch/arm/dts/rk3399-ficus.dts
 create mode 100644 configs/ficus-rk3399_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 946023093df6..fbce68d9a2eb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
rk3399-evb.dtb \
+   rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts
new file mode 100644
index ..db015a26
--- /dev/null
+++ b/arch/arm/dts/rk3399-ficus.dts
@@ -0,0 +1,564 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
+ */
+
+/dts-v1/;
+#include 
+#include "rk3399.dtsi"
+#include "rk3399-sdram-ddr3-1600.dtsi"
+
+/ {
+   model = "96boards RK3399 Ficus";
+   compatible = "vamrs,ficus", "rockchip,rk3399";
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   clkin_gmac: external-gmac-clock {
+   compatible = "fixed-clock";
+   clock-frequency = <12500>;
+   clock-output-names = "clkin_gmac";
+   #clock-cells = <0>;
+   };
+
+   vcc1v8_s0: vcc1v8-s0 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc1v8_s0";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-always-on;
+   };
+
+   vcc_sys: vcc-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_sys";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
+
+   vcc3v3_sys: vcc3v3-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   vin-supply = <_sys>;
+   };
+
+   vcc3v3_pcie: vcc3v3-pcie-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 24 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_drv>;
+   regulator-boot-on;
+   regulator-name = "vcc3v3_pcie";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <_sys>;
+   };
+
+   vcc5v0_host: vcc5v0-host-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 27 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_vbus_drv>;
+   regulator-name = "vcc5v0_host";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   vin-supply = <_sys>;
+   };
+
+   vdd_log: vdd-log {
+   compatible = "pwm-regulator";
+   pwms = < 0 25000 0>;
+   regulator-name = "vdd_log";
+   regulator-min-microvolt = <80>;
+   regulator-max-microvolt = <140>;
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <_sys>;
+   };
+};
+
+_l0 {
+   cpu-supply = <_cpu_l>;
+};
+
+_l1 {
+   cpu-supply = <_cpu_l>;
+};
+
+_l2 {
+   cpu-supply = <_cpu_l>;
+};
+
+_l3 {
+   cpu-supply = <_cpu_l>;
+};
+
+_b0 {
+   cpu-supply = <_cpu_b>;
+};
+
+_b1 {
+   cpu-supply = <_cpu_b>;
+};
+
+_phy {
+   status = "okay";
+};
+
+ {
+   assigned-clocks = < SCLK_RMII_SRC>;
+   assigned-clock-parents = <_gmac>;
+   clock_in_out = &qu

[U-Boot] [PATCH 1/3] arm: dts: rockchip: add some common pin-settings to rk3399

[Ezequiel Garcia]

From: Randy Li 

Those pins would be used by many boards.

Signed-off-by: Randy Li 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Ezequiel Garcia 
---
 arch/arm/dts/rk3399.dtsi | 55 +++-
 1 file changed, 49 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 83c257b1228b..8349451b03dc 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1602,19 +1602,49 @@
drive-strength = <12>;
};
 
+   pcfg_pull_none_13ma: pcfg-pull-none-13ma {
+   bias-disable;
+   drive-strength = <13>;
+   };
+
+   pcfg_pull_none_18ma: pcfg-pull-none-18ma {
+   bias-disable;
+   drive-strength = <18>;
+   };
+
+   pcfg_pull_none_20ma: pcfg-pull-none-20ma {
+   bias-disable;
+   drive-strength = <20>;
+   };
+
+   pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+   bias-pull-up;
+   drive-strength = <2>;
+   };
+
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
bias-pull-up;
drive-strength = <8>;
};
 
+   pcfg_pull_up_18ma: pcfg-pull-up-18ma {
+   bias-pull-up;
+   drive-strength = <18>;
+   };
+
+   pcfg_pull_up_20ma: pcfg-pull-up-20ma {
+   bias-pull-up;
+   drive-strength = <20>;
+   };
+
pcfg_pull_down_4ma: pcfg-pull-down-4ma {
bias-pull-down;
drive-strength = <4>;
};
 
-   pcfg_pull_up_2ma: pcfg-pull-up-2ma {
-   bias-pull-up;
-   drive-strength = <2>;
+   pcfg_pull_down_8ma: pcfg-pull-down-8ma {
+   bias-pull-down;
+   drive-strength = <8>;
};
 
pcfg_pull_down_12ma: pcfg-pull-down-12ma {
@@ -1622,9 +1652,22 @@
drive-strength = <12>;
};
 
-   pcfg_pull_none_13ma: pcfg-pull-none-13ma {
-   bias-disable;
-   drive-strength = <13>;
+   pcfg_pull_down_18ma: pcfg-pull-down-18ma {
+   bias-pull-down;
+   drive-strength = <18>;
+   };
+
+   pcfg_pull_down_20ma: pcfg-pull-down-20ma {
+   bias-pull-down;
+   drive-strength = <20>;
+   };
+
+   pcfg_output_high: pcfg-output-high {
+   output-high;
+   };
+
+   pcfg_output_low: pcfg-output-low {
+   output-low;
};
 
clock {
-- 
2.18.0

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[U-Boot] [PATCH 0/3] RK3399: Add support for Ficus board

[Ezequiel Garcia]

Add support for a new RK3399-based board. The RK3399 Ficus
board is an Enterprise Edition board manufactured by Vamrs Ltd.,
based on the Rockchip RK3399 SoC.

While here, we extend the evb_rk3399/README document
with instructions for SD/MMC boot.

The devicetree file for this board has been already merged
in Linux maintainer's tree:

https://kernel.googlesource.com/pub/scm/linux/kernel/git/mmind/linux-rockchip/+/v4.19-armsoc/dts64/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts

Ezequiel Garcia (2):
  ARM: add RK3399 Ficus board
  rockchip: rk3399: Add more instructions to the README

Randy Li (1):
  arm: dts: rockchip: add some common pin-settings to rk3399

 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/rk3399-ficus.dts| 564 +++
 arch/arm/dts/rk3399.dtsi |  55 ++-
 board/rockchip/evb_rk3399/README |  57 +++-
 configs/ficus-rk3399_defconfig   |  71 
 5 files changed, 740 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/dts/rk3399-ficus.dts
 create mode 100644 configs/ficus-rk3399_defconfig

-- 
2.18.0

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Re: [U-Boot] [PATCH 1/1] rockchip: rk3399: spl: add missing \n to output

[Ezequiel Garcia]

On 3 June 2018 at 19:28, Dr. Philipp Tomsich
 wrote:
>
>> On 3 Jun 2018, at 21:10, Heinrich Schuchardt  wrote:
>>
>> Without the patch SPL (in case of an error) creates an output like:
>>
>>   U-Boot SPL board initMissing DTB
>>
>> The patch adds the missing line feed. So now we get:
>>
>>   U-Boot SPL board init
>>   Missing DTB
>>
>> Signed-off-by: Heinrich Schuchardt 
>
> Reviewed-by: Philipp Tomsich 
> Acked-by: Philipp Tomsich 
>

Guys,

Any chance we pick this one?

Thanks,
-- 
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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Re: [U-Boot] [PATCH 1/2] nand: zynq: Fix driver initialization

[Ezequiel Garcia]

Hi Michal,

On 19 April 2018 at 08:10, Michal Simek <michal.si...@xilinx.com> wrote:
> From: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
>
> This driver is currently broken, refusing to initialize properly.
>
> The reason is that get_nand_dev_by_index() was being called before
> nand_register(), thus returning a pointer into uninitialized memory.
> In other words, the struct mtd_info used by the driver is total junk.
>
> Fix it by getting the correct struct mtd_info, via nand_to_mtd()
> on the driver's struct nand_chip.
>
> Tested on a custom board, where the CPU is halted without this patch.
>
> Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
> Reviewed-by: Michal Simek <michal.si...@xilinx.com>
> Signed-off-by: Michal Simek <michal.si...@xilinx.com>

Thanks for collecting these and submitting them!

BTW, I thought there was no need for a reviewed-by on top
of a signed-off-by. It's kind of assumed that if you are signing
something, you have reviewed it in the first place.

Or at least that's how I've been doing it.
-- 
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www.vanguardiasur.com.ar
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Re: [U-Boot] [PATCH 3/5] zynq: Support CPU info display

[Ezequiel Garcia]

On 1 February 2018 at 05:26, Michal Simek <michal.si...@xilinx.com> wrote:
> On 31.1.2018 22:25, Ezequiel Garcia wrote:
>> On 26 January 2018 at 09:33, Michal Simek <michal.si...@xilinx.com> wrote:
>>> Hi,
>>>
>>>
>>> On 17.1.2018 14:56, Ezequiel Garcia wrote:
>>>> This commit adds CPU and silicon version information
>>>> consuming the SLCR IDCODE and DEVCFG MCTRL registers,
>>>> respectively.
>>>>
>>>> Signed-off-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar>
>>>> Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
>>>> ---
>>>>  arch/arm/mach-zynq/cpu.c | 46 
>>>> ++
>>>>  1 file changed, 46 insertions(+)
>>>>
>>>> diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
>>>> index 53a07b0059c2..602f483c162b 100644
>>>> --- a/arch/arm/mach-zynq/cpu.c
>>>> +++ b/arch/arm/mach-zynq/cpu.c
>>>> @@ -35,6 +35,25 @@ static const struct {
>>>>  };
>>>>  #endif
>>>>
>>>> +#ifdef CONFIG_DISPLAY_CPUINFO
>>>> +static const struct {
>>>> + u8 idcode;
>>>> + const char *cpuinfo;
>>>> +} zynq_cpu_info[] = {
>>>> + { .idcode = XILINX_ZYNQ_7007S,  .cpuinfo = XILINX_XC7Z007S_NAME },
>>>> + { .idcode = XILINX_ZYNQ_7010,   .cpuinfo = XILINX_XC7Z010_NAME },
>>>> + { .idcode = XILINX_ZYNQ_7012S,  .cpuinfo = XILINX_XC7Z012S_NAME },
>>>> + { .idcode = XILINX_ZYNQ_7014S,  .cpuinfo = XILINX_XC7Z014S_NAME },
>>>> + { .idcode = XILINX_ZYNQ_7015,   .cpuinfo = XILINX_XC7Z015_NAME },
>>>> + { .idcode = XILINX_ZYNQ_7020,   .cpuinfo = XILINX_XC7Z020_NAME },
>>>> + { .idcode = XILINX_ZYNQ_7030,   .cpuinfo = XILINX_XC7Z030_NAME },
>>>> + { .idcode = XILINX_ZYNQ_7035,   .cpuinfo = XILINX_XC7Z035_NAME },
>>>> + { .idcode = XILINX_ZYNQ_7045,   .cpuinfo = XILINX_XC7Z045_NAME },
>>>> + { .idcode = XILINX_ZYNQ_7100,   .cpuinfo = XILINX_XC7Z100_NAME },
>>>> + { /* Sentinel */ },
>>>
>>> This table pretty much reflect what it is in 2/5.
>>>
>>> static const struct {
>>> u8 idcode;
>>> const char *cpuinfo; /* or better name devicename */
>>> u32 fpga_size;
>>> } zynq_cpu_info[] = {
>>>
>>> From xilinx_desc I think size is unused but we can keep in filled and
>>> cookie is also not used and can be 0. The rest of data for xilinx_desc
>>> is static anyway.
>>>
>>> It means doing this properly will be the best to fill that xilinx_desc
>>> and also it doesn't make sense to call zynq_slcr_get_idcode() twice.
>>> It should be enough to detect chip once and fill pointer to actual
>>> configuration. And then when fpga should be add then use them. The same
>>> for cpuinfo. Link is already setup and you can just use it.
>>>
>>
>> So you propose to have just one table instead of two
>> zynq_cpu_info and zynq_fpga_descs ?
>
> I was playing with it last Friday and I have sent that 2 patches as RFC.
>

I see.

>> I guess that'll work and might result in simpler code.
>> On the other side, the reason I kept them separate
>> is because each of them are compiled-in via different
>> compile-time options.
>>
>> Having a single table will mean playing nasty ifdef
>> games, which usually mean trouble.
>>
>> Regarding calling zynq_slcr_get_idcode twice,
>> is it really that bad?
>
> It is not that bad. It is probably better than having global variable.
>
> Take a look at that RFC. Buildman is also showing pretty nice size
> reduction but there are still some pieces which can be done better.
> It is based on your code that's why fell free to rework it.
>

Indeed, it doesn't look bad at all. Let me try those patches,
see how they work.
-- 
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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Re: [U-Boot] [PATCH 3/5] zynq: Support CPU info display

[Ezequiel Garcia]

On 26 January 2018 at 09:33, Michal Simek <michal.si...@xilinx.com> wrote:
> Hi,
>
>
> On 17.1.2018 14:56, Ezequiel Garcia wrote:
>> This commit adds CPU and silicon version information
>> consuming the SLCR IDCODE and DEVCFG MCTRL registers,
>> respectively.
>>
>> Signed-off-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar>
>> Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
>> ---
>>  arch/arm/mach-zynq/cpu.c | 46 ++
>>  1 file changed, 46 insertions(+)
>>
>> diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
>> index 53a07b0059c2..602f483c162b 100644
>> --- a/arch/arm/mach-zynq/cpu.c
>> +++ b/arch/arm/mach-zynq/cpu.c
>> @@ -35,6 +35,25 @@ static const struct {
>>  };
>>  #endif
>>
>> +#ifdef CONFIG_DISPLAY_CPUINFO
>> +static const struct {
>> + u8 idcode;
>> + const char *cpuinfo;
>> +} zynq_cpu_info[] = {
>> + { .idcode = XILINX_ZYNQ_7007S,  .cpuinfo = XILINX_XC7Z007S_NAME },
>> + { .idcode = XILINX_ZYNQ_7010,   .cpuinfo = XILINX_XC7Z010_NAME },
>> + { .idcode = XILINX_ZYNQ_7012S,  .cpuinfo = XILINX_XC7Z012S_NAME },
>> + { .idcode = XILINX_ZYNQ_7014S,  .cpuinfo = XILINX_XC7Z014S_NAME },
>> + { .idcode = XILINX_ZYNQ_7015,   .cpuinfo = XILINX_XC7Z015_NAME },
>> + { .idcode = XILINX_ZYNQ_7020,   .cpuinfo = XILINX_XC7Z020_NAME },
>> + { .idcode = XILINX_ZYNQ_7030,   .cpuinfo = XILINX_XC7Z030_NAME },
>> + { .idcode = XILINX_ZYNQ_7035,   .cpuinfo = XILINX_XC7Z035_NAME },
>> + { .idcode = XILINX_ZYNQ_7045,   .cpuinfo = XILINX_XC7Z045_NAME },
>> + { .idcode = XILINX_ZYNQ_7100,   .cpuinfo = XILINX_XC7Z100_NAME },
>> + { /* Sentinel */ },
>
> This table pretty much reflect what it is in 2/5.
>
> static const struct {
> u8 idcode;
> const char *cpuinfo; /* or better name devicename */
> u32 fpga_size;
> } zynq_cpu_info[] = {
>
> From xilinx_desc I think size is unused but we can keep in filled and
> cookie is also not used and can be 0. The rest of data for xilinx_desc
> is static anyway.
>
> It means doing this properly will be the best to fill that xilinx_desc
> and also it doesn't make sense to call zynq_slcr_get_idcode() twice.
> It should be enough to detect chip once and fill pointer to actual
> configuration. And then when fpga should be add then use them. The same
> for cpuinfo. Link is already setup and you can just use it.
>

So you propose to have just one table instead of two
zynq_cpu_info and zynq_fpga_descs ?

I guess that'll work and might result in simpler code.
On the other side, the reason I kept them separate
is because each of them are compiled-in via different
compile-time options.

Having a single table will mean playing nasty ifdef
games, which usually mean trouble.

Regarding calling zynq_slcr_get_idcode twice,
is it really that bad?
-- 
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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[U-Boot] [PATCH 4/5] zynq: board: Remove checkboard

[Ezequiel Garcia]

Now that showing silicon version is part of the CPU
info display, let's remove checkboard().

Note that the generic show_board_info() will still
show the DT 'model' property. For instance:

  U-Boot 2018.01-00172-g5e296ab7317a (Jan 17 2018 - 09:57:36 -0300)

  CPU:   Zynq 7z010
  Silicon: v3.1
  Model: Bitmain Antminer S9 Board

Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 board/xilinx/zynq/board.c | 17 -
 1 file changed, 17 deletions(-)

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index f9e7bca4ee40..2374da68328f 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -11,7 +11,6 @@
 #include 
 #include 
 #include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,22 +51,6 @@ int board_late_init(void)
return 0;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-   u32 version = zynq_get_silicon_version();
-
-   version <<= 1;
-   if (version > (PCW_SILICON_VERSION_3 << 1))
-   version += 1;
-
-   puts("Board: Xilinx Zynq\n");
-   printf("Silicon: v%d.%d\n", version >> 1, version & 1);
-
-   return 0;
-}
-#endif
-
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 {
 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
-- 
2.15.1

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[U-Boot] [PATCH 3/5] zynq: Support CPU info display

[Ezequiel Garcia]

This commit adds CPU and silicon version information
consuming the SLCR IDCODE and DEVCFG MCTRL registers,
respectively.

Signed-off-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar>
Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 arch/arm/mach-zynq/cpu.c | 46 ++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index 53a07b0059c2..602f483c162b 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -35,6 +35,25 @@ static const struct {
 };
 #endif
 
+#ifdef CONFIG_DISPLAY_CPUINFO
+static const struct {
+   u8 idcode;
+   const char *cpuinfo;
+} zynq_cpu_info[] = {
+   { .idcode = XILINX_ZYNQ_7007S,  .cpuinfo = XILINX_XC7Z007S_NAME },
+   { .idcode = XILINX_ZYNQ_7010,   .cpuinfo = XILINX_XC7Z010_NAME },
+   { .idcode = XILINX_ZYNQ_7012S,  .cpuinfo = XILINX_XC7Z012S_NAME },
+   { .idcode = XILINX_ZYNQ_7014S,  .cpuinfo = XILINX_XC7Z014S_NAME },
+   { .idcode = XILINX_ZYNQ_7015,   .cpuinfo = XILINX_XC7Z015_NAME },
+   { .idcode = XILINX_ZYNQ_7020,   .cpuinfo = XILINX_XC7Z020_NAME },
+   { .idcode = XILINX_ZYNQ_7030,   .cpuinfo = XILINX_XC7Z030_NAME },
+   { .idcode = XILINX_ZYNQ_7035,   .cpuinfo = XILINX_XC7Z035_NAME },
+   { .idcode = XILINX_ZYNQ_7045,   .cpuinfo = XILINX_XC7Z045_NAME },
+   { .idcode = XILINX_ZYNQ_7100,   .cpuinfo = XILINX_XC7Z100_NAME },
+   { /* Sentinel */ },
+};
+#endif
+
 int arch_cpu_init(void)
 {
zynq_slcr_unlock();
@@ -99,3 +118,30 @@ const xilinx_desc *zynq_fpga_desc(void)
return NULL;
 }
 #endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+   u32 idcode, version;
+   bool found;
+   u8 i;
+
+   idcode = zynq_slcr_get_idcode();
+   found = false;
+   for (i = 0; zynq_cpu_info[i].idcode; i++) {
+   if (zynq_cpu_info[i].idcode == idcode) {
+   found = true;
+   break;
+   }
+   }
+
+   version = zynq_get_silicon_version() << 1;
+   if (version > (PCW_SILICON_VERSION_3 << 1))
+   version += 1;
+   if (found) {
+   printf("CPU:   Zynq %s\n", zynq_cpu_info[i].cpuinfo);
+   printf("Silicon: v%d.%d\n", version >> 1, version & 1);
+   }
+   return 0;
+}
+#endif
-- 
2.15.1

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[U-Boot] [PATCH 5/5] configs: zynq: Enable DISPLAY_CPUINFO

[Ezequiel Garcia]

Now that silicon version has been moved from checkboard()
to print_cpuinfo(), we need to enable DISPLAY_CPUINFO option.

Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 configs/syzygy_hub_defconfig   | 1 -
 configs/topic_miami_defconfig  | 1 -
 configs/topic_miamilite_defconfig  | 1 -
 configs/topic_miamiplus_defconfig  | 1 -
 configs/zynq_cc108_defconfig   | 1 -
 configs/zynq_cse_qspi_defconfig| 1 -
 configs/zynq_microzed_defconfig| 1 -
 configs/zynq_picozed_defconfig | 1 -
 configs/zynq_z_turn_defconfig  | 1 -
 configs/zynq_zc702_defconfig   | 1 -
 configs/zynq_zc706_defconfig   | 1 -
 configs/zynq_zc770_xm010_defconfig | 1 -
 configs/zynq_zc770_xm011_defconfig | 1 -
 configs/zynq_zc770_xm012_defconfig | 1 -
 configs/zynq_zc770_xm013_defconfig | 1 -
 configs/zynq_zed_defconfig | 1 -
 configs/zynq_zybo_defconfig| 1 -
 17 files changed, 17 deletions(-)

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 8bdc4be67d70..b4a41b484885 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index aabd705da0fb..866c91276d95 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -8,7 +8,6 @@ 
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
 CONFIG_DEBUG_UART=y
 CONFIG_BOOTDELAY=0
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/topic_miamilite_defconfig 
b/configs/topic_miamilite_defconfig
index 7228283b3c6b..1cae54c2da5e 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -8,7 +8,6 @@ 
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
 CONFIG_DEBUG_UART=y
 CONFIG_BOOTDELAY=0
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/topic_miamiplus_defconfig 
b/configs/topic_miamiplus_defconfig
index d511a942838b..13f69eb4b1ca 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -8,7 +8,6 @@ 
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
 CONFIG_DEBUG_UART=y
 CONFIG_BOOTDELAY=0
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index bdba0d1cc9ba..31d5dda12b06 100644
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -7,7 +7,6 @@ CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 9659faefbf33..f5201a72d6be 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
 CONFIG_DEBUG_UART=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_BOOTDELAY=-1
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index fc21eb8f67a3..fbce9631f893 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index f36e7bd849f4..e58b90b710ca 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x400
 CONFIG_SPL_STACK_R_ADDR=0x20
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index c727b2acbf28..d4934c8d1673 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -7,7 +7,6 @@ CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 0d0efc223dd4..df0a1adf793d 100

[U-Boot] [PATCH 2/5] zynq: Rework FPGA initialization

[Ezequiel Garcia]

This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.

Also, the implementation is reworked to be cleaner
and a bit smaller.

add/remove: 2/11 grow/shrink: 0/1 up/down: 420/-608 (-188)
function old new   delta
zynq_fpga_descs- 352+352
zynq_fpga_desc -  68 +68
fpga100   28   - -28
fpga045   28   - -28
fpga035   28   - -28
fpga030   28   - -28
fpga020   28   - -28
fpga015   28   - -28
fpga014s  28   - -28
fpga012s  28   - -28
fpga010   28   - -28
fpga007s  28   - -28
fpga  28   - -28
board_init   332  32-300
Total: Before=574182, After=573994, chg -0.03%

Signed-off-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar>
Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 arch/arm/mach-zynq/cpu.c| 41 +++-
 arch/arm/mach-zynq/include/mach/sys_proto.h |  3 ++
 board/xilinx/zynq/board.c   | 59 +
 3 files changed, 44 insertions(+), 59 deletions(-)

diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index ee1c1a943b66..53a07b0059c2 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -5,14 +5,36 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 #include 
+#include 
 #include 
 #include 
-#include 
 #include 
+#include 
+#include 
 
 #define ZYNQ_SILICON_VER_MASK  0xF000
 #define ZYNQ_SILICON_VER_SHIFT 28
 
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static const struct {
+   u8 idcode;
+   xilinx_desc desc;
+} zynq_fpga_descs[] = {
+   { .idcode = XILINX_ZYNQ_7007S,  .desc = XILINX_XC7Z007S_DESC(0x07) },
+   { .idcode = XILINX_ZYNQ_7010,   .desc = XILINX_XC7Z010_DESC(0x10)  },
+   { .idcode = XILINX_ZYNQ_7012S,  .desc = XILINX_XC7Z012S_DESC(0x12) },
+   { .idcode = XILINX_ZYNQ_7014S,  .desc = XILINX_XC7Z014S_DESC(0x14) },
+   { .idcode = XILINX_ZYNQ_7015,   .desc = XILINX_XC7Z015_DESC(0x15)  },
+   { .idcode = XILINX_ZYNQ_7020,   .desc = XILINX_XC7Z020_DESC(0x20)  },
+   { .idcode = XILINX_ZYNQ_7030,   .desc = XILINX_XC7Z030_DESC(0x30)  },
+   { .idcode = XILINX_ZYNQ_7035,   .desc = XILINX_XC7Z035_DESC(0x35)  },
+   { .idcode = XILINX_ZYNQ_7045,   .desc = XILINX_XC7Z045_DESC(0x45)  },
+   { .idcode = XILINX_ZYNQ_7100,   .desc = XILINX_XC7Z100_DESC(0x100) },
+   { /* Sentinel */ },
+};
+#endif
+
 int arch_cpu_init(void)
 {
zynq_slcr_unlock();
@@ -60,3 +82,20 @@ void enable_caches(void)
dcache_enable();
 }
 #endif
+
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+const xilinx_desc *zynq_fpga_desc(void)
+{
+   u32 idcode;
+   u8 i;
+
+   idcode = zynq_slcr_get_idcode();
+   for (i = 0; zynq_fpga_descs[i].idcode; i++) {
+   if (zynq_fpga_descs[i].idcode == idcode) {
+   return _fpga_descs[i].desc;
+   }
+   }
+   return NULL;
+}
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h 
b/arch/arm/mach-zynq/include/mach/sys_proto.h
index af61352dd110..fd5744c4e85e 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -7,6 +7,8 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
+#include 
+
 extern void zynq_slcr_lock(void);
 extern void zynq_slcr_unlock(void);
 extern void zynq_slcr_cpu_reset(void);
@@ -16,6 +18,7 @@ extern u32 zynq_slcr_get_boot_mode(void);
 extern u32 zynq_slcr_get_idcode(void);
 extern int zynq_slcr_get_mio_pin_status(const char *periph);
 extern void zynq_ddrc_init(void);
+extern const xilinx_desc *zynq_fpga_desc(void);
 extern unsigned int zynq_get_silicon_version(void);
 
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index e59038106aa6..f9e7bca4ee40 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -15,69 +15,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static xilinx_desc fpga;
-
-/* It can be done differently */
-static xilinx_desc fpga0

[U-Boot] [PATCH 1/5] zynq: Define macros for the device names

[Ezequiel Garcia]

This will allow to reuse the macros when showing
the CPU info.

Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 include/zynqpl.h | 32 ++--
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/include/zynqpl.h b/include/zynqpl.h
index 5a34a17daefe..e10a266643bd 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -42,45 +42,57 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_XC7Z045_SIZE106571232/8
 #define XILINX_XC7Z100_SIZE139330784/8
 
+/* Device Names */
+#define XILINX_XC7Z007S_NAME   "7z007s"
+#define XILINX_XC7Z010_NAME"7z010"
+#define XILINX_XC7Z012S_NAME   "7z012s"
+#define XILINX_XC7Z014S_NAME   "7z014s"
+#define XILINX_XC7Z015_NAME"7z015"
+#define XILINX_XC7Z020_NAME"7z020"
+#define XILINX_XC7Z030_NAME"7z030"
+#define XILINX_XC7Z035_NAME"7z035"
+#define XILINX_XC7Z045_NAME"7z045"
+#define XILINX_XC7Z100_NAME"7z100"
+
 /* Descriptor Macros */
 #define XILINX_XC7Z007S_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z007s" }
+   XILINX_XC7Z007S_NAME }
 
 #define XILINX_XC7Z010_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z010" }
+   XILINX_XC7Z010_NAME }
 
 #define XILINX_XC7Z012S_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z012s" }
+   XILINX_XC7Z012S_NAME }
 
 #define XILINX_XC7Z014S_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z014s" }
+   XILINX_XC7Z014S_NAME }
 
 #define XILINX_XC7Z015_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z015" }
+   XILINX_XC7Z015_NAME }
 
 #define XILINX_XC7Z020_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z020" }
+   XILINX_XC7Z020_NAME }
 
 #define XILINX_XC7Z030_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z030" }
+   XILINX_XC7Z030_NAME }
 
 #define XILINX_XC7Z035_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z035" }
+   XILINX_XC7Z035_NAME }
 
 #define XILINX_XC7Z045_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z045" }
+   XILINX_XC7Z045_NAME }
 
 #define XILINX_XC7Z100_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-   "7z100" }
+   XILINX_XC7Z100_NAME }
 
 #endif /* _ZYNQPL_H_ */
-- 
2.15.1

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[U-Boot] [PATCH 0/5] zynq: Fun with board and CPU info display

[Ezequiel Garcia]

This series aims at adding support for CPU information display.
While here, following suggestions from Michal, the FPGA
initialization is cleaned up.

Ezequiel Garcia (5):
  zynq: Define macros for the device names
  zynq: Rework FPGA initialization
  zynq: Support CPU info display
  zynq: board: Remove checkboard
  configs: zynq: Enable DISPLAY_CPUINFO

 arch/arm/mach-zynq/cpu.c| 87 -
 arch/arm/mach-zynq/include/mach/sys_proto.h |  3 +
 board/xilinx/zynq/board.c   | 76 +
 configs/syzygy_hub_defconfig|  1 -
 configs/topic_miami_defconfig   |  1 -
 configs/topic_miamilite_defconfig   |  1 -
 configs/topic_miamiplus_defconfig   |  1 -
 configs/zynq_cc108_defconfig|  1 -
 configs/zynq_cse_qspi_defconfig |  1 -
 configs/zynq_microzed_defconfig |  1 -
 configs/zynq_picozed_defconfig  |  1 -
 configs/zynq_z_turn_defconfig   |  1 -
 configs/zynq_zc702_defconfig|  1 -
 configs/zynq_zc706_defconfig|  1 -
 configs/zynq_zc770_xm010_defconfig  |  1 -
 configs/zynq_zc770_xm011_defconfig  |  1 -
 configs/zynq_zc770_xm012_defconfig  |  1 -
 configs/zynq_zc770_xm013_defconfig  |  1 -
 configs/zynq_zed_defconfig  |  1 -
 configs/zynq_zybo_defconfig |  1 -
 include/zynqpl.h| 32 +++
 21 files changed, 112 insertions(+), 103 deletions(-)

-- 
2.15.1

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Re: [U-Boot] [PATCH 2/2] zynq: Support CPU info display

[Ezequiel Garcia]

On 16 January 2018 at 09:08, Michal Simek <michal.si...@xilinx.com> wrote:
> On 15.1.2018 16:46, Ezequiel Garcia wrote:
>> This commit adds CPU and silicon version information
>> consuming the SLCR IDCODE and DEVCFG MCTRL registers,
>> respectively.
>>
>> Signed-off-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar>
>> Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
>> ---
>>  arch/arm/mach-zynq/Makefile   |  1 +
>>  arch/arm/mach-zynq/cpu_info.c | 49 
>> +++
>>  2 files changed, 50 insertions(+)
>>  create mode 100644 arch/arm/mach-zynq/cpu_info.c
>>
>> diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
>> index e3f0117da563..31f1e0d5a8ad 100644
>> --- a/arch/arm/mach-zynq/Makefile
>> +++ b/arch/arm/mach-zynq/Makefile
>> @@ -14,5 +14,6 @@ obj-y   += ddrc.o
>>  obj-y+= slcr.o
>>  obj-y+= clk.o
>>  obj-y+= lowlevel_init.o
>> +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
>>  AFLAGS_lowlevel_init.o := -mfpu=neon
>>  obj-$(CONFIG_SPL_BUILD)  += spl.o ps7_spl_init.o
>> diff --git a/arch/arm/mach-zynq/cpu_info.c b/arch/arm/mach-zynq/cpu_info.c
>> new file mode 100644
>> index ..730b73da
>> --- /dev/null
>> +++ b/arch/arm/mach-zynq/cpu_info.c
>> @@ -0,0 +1,49 @@
>> +/*
>> + * Copyright (C) 2018 VanguardiaSur - www.vanguardiasur.com.ar
>
> The part of code below is copied from board.c which is interestingly
> copyrighted just by me. But there should be also Xilinx. :-)
>

Oh, sorry about!

/*
 * (C) Copyright 2012 Michal Simek <mon...@monstr.eu>
 * (C) Copyright 2018 VanguardiaSur - www.vanguardiasur.com.ar
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

This OK ? How should the Xilinx copyright look like?

>> + *
>> + * SPDX-License-Identifier:  GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>
> Already the part of common.h
>

Got it.

>> +#include 
>
> This is not needed but both these patches are pointing to one more thing
> which could be the part of this series which is filling FPGA structure
> which should be removed from board.c too.
>

OK.

>> +#include 
>> +#include 
>
> This header is probably not needed.
>

Seems needed because of PCW_SILICON_VERSION_3.

>> +
>> +static const struct {
>> + u8 idcode;
>> + const char *cpuinfo;
>> +} zynq_cpu_info[] = {
>> + { .idcode = XILINX_ZYNQ_7007S,  .cpuinfo = "7007S" },
>> + { .idcode = XILINX_ZYNQ_7010,   .cpuinfo = "7010" },
>> + { .idcode = XILINX_ZYNQ_7012S,  .cpuinfo = "7012S" },
>> + { .idcode = XILINX_ZYNQ_7014S,  .cpuinfo = "7014S" },
>> + { .idcode = XILINX_ZYNQ_7015,   .cpuinfo = "7015" },
>> + { .idcode = XILINX_ZYNQ_7020,   .cpuinfo = "7020" },
>> + { .idcode = XILINX_ZYNQ_7030,   .cpuinfo = "7030" },
>> + { .idcode = XILINX_ZYNQ_7035,   .cpuinfo = "7035" },
>> + { .idcode = XILINX_ZYNQ_7045,   .cpuinfo = "7045" },
>> + { .idcode = XILINX_ZYNQ_7100,   .cpuinfo = "7100"},
>
> If you look at include/zynqpl.h then 7z007s name is used instead.

Oh, missed those strings. We should be able to reuse them.

> Normally this was available via fpga info command but not a problem to
> show it as the part of boot log.
>
>> + { /* Sentinel */ },
>> +};
>> +
>> +int print_cpuinfo(void)
>> +{
>> + u32 idcode, version;
>> + u8 i;
>> +
>> + idcode = zynq_slcr_get_idcode();
>> +
>> + for (i = 0; zynq_cpu_info[i].idcode; i++) {
>> + if (zynq_cpu_info[i].idcode == idcode) {
>> + printf("CPU:   Zynq %s\n", zynq_cpu_info[i].cpuinfo);
>> + break;
>> + }
>> + }
>> +
>> + version = zynq_get_silicon_version() << 1;
>> + if (version > (PCW_SILICON_VERSION_3 << 1))
>> + version += 1;
>> + printf("Silicon: v%d.%d\n", version >> 1, version & 1);
>
>
> When this is running on QEMU only silicon version is shown and nothing else.
>
> U-Boot 2018.01-00101-g2cb1e21ccc8e (Jan 16 2018 - 12:08:57 +0100) Xilinx
> Zynq ZC702
>
> Silicon: v0.0
> Model: Zynq ZC702 Development Board
> I2C:   ready
> DRAM:  ECC disabled 1 GiB
>
> I think if you print cpu information you should also print silicon
> version. If you don't print it, then just don't print silicon version too.
>

OK, makes sense.

> Anyway just a summary. You pointed to this code that's why I think to do
> it properly we should also remove fpga initialization from board.c and
> move it to mach-zynq and detect idcode just once and then reuse it.
>

Right. Perhaps we can put both fpga init and print_cpuinfo in slcr.c.

> Also this patch is not enabling CONFIG_DISPLAY_CPUINFO which is required
> to see the same information before and after this patch for existing
> boards and this should be added too.
>

OK.

> Thanks,
> Michal
>



-- 
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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[U-Boot] [PATCH] nand: arasan: Select CONFIG_SYS_NAND_SELF_INIT

[Ezequiel Garcia]

The Arasan NFC driver requires the self-init mode,
so it should select it.

Instead of having the config header define the macro,
it's cleaner to select the option at the Kconfig level.

Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 drivers/mtd/nand/Kconfig| 1 +
 include/configs/xilinx_zynqmp.h | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 78a39abf7542..97ec6cf5f9c3 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -123,6 +123,7 @@ endif
 
 config NAND_ARASAN
bool "Configure Arasan Nand"
+   select SYS_NAND_SELF_INIT
imply CMD_NAND
help
  This enables Nand driver support for Arasan nand flash
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 9997fd095982..d883897c6cc2 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -76,7 +76,6 @@
 
 #ifdef CONFIG_NAND_ARASAN
 # define CONFIG_SYS_MAX_NAND_DEVICE1
-# define CONFIG_SYS_NAND_SELF_INIT
 # define CONFIG_SYS_NAND_ONFI_DETECTION
 # define CONFIG_MTD_DEVICE
 #endif
-- 
2.15.1

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[U-Boot] [PATCH 2/2] zynq: Support CPU info display

[Ezequiel Garcia]

This commit adds CPU and silicon version information
consuming the SLCR IDCODE and DEVCFG MCTRL registers,
respectively.

Signed-off-by: Ariel D'Alessandro <ar...@vanguardiasur.com.ar>
Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 arch/arm/mach-zynq/Makefile   |  1 +
 arch/arm/mach-zynq/cpu_info.c | 49 +++
 2 files changed, 50 insertions(+)
 create mode 100644 arch/arm/mach-zynq/cpu_info.c

diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index e3f0117da563..31f1e0d5a8ad 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -14,5 +14,6 @@ obj-y += ddrc.o
 obj-y  += slcr.o
 obj-y  += clk.o
 obj-y  += lowlevel_init.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
 AFLAGS_lowlevel_init.o := -mfpu=neon
 obj-$(CONFIG_SPL_BUILD)+= spl.o ps7_spl_init.o
diff --git a/arch/arm/mach-zynq/cpu_info.c b/arch/arm/mach-zynq/cpu_info.c
new file mode 100644
index ..730b73da
--- /dev/null
+++ b/arch/arm/mach-zynq/cpu_info.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2018 VanguardiaSur - www.vanguardiasur.com.ar
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct {
+   u8 idcode;
+   const char *cpuinfo;
+} zynq_cpu_info[] = {
+   { .idcode = XILINX_ZYNQ_7007S,  .cpuinfo = "7007S" },
+   { .idcode = XILINX_ZYNQ_7010,   .cpuinfo = "7010" },
+   { .idcode = XILINX_ZYNQ_7012S,  .cpuinfo = "7012S" },
+   { .idcode = XILINX_ZYNQ_7014S,  .cpuinfo = "7014S" },
+   { .idcode = XILINX_ZYNQ_7015,   .cpuinfo = "7015" },
+   { .idcode = XILINX_ZYNQ_7020,   .cpuinfo = "7020" },
+   { .idcode = XILINX_ZYNQ_7030,   .cpuinfo = "7030" },
+   { .idcode = XILINX_ZYNQ_7035,   .cpuinfo = "7035" },
+   { .idcode = XILINX_ZYNQ_7045,   .cpuinfo = "7045" },
+   { .idcode = XILINX_ZYNQ_7100,   .cpuinfo = "7100"},
+   { /* Sentinel */ },
+};
+
+int print_cpuinfo(void)
+{
+   u32 idcode, version;
+   u8 i;
+
+   idcode = zynq_slcr_get_idcode();
+
+   for (i = 0; zynq_cpu_info[i].idcode; i++) {
+   if (zynq_cpu_info[i].idcode == idcode) {
+   printf("CPU:   Zynq %s\n", zynq_cpu_info[i].cpuinfo);
+   break;
+   }
+   }
+
+   version = zynq_get_silicon_version() << 1;
+   if (version > (PCW_SILICON_VERSION_3 << 1))
+   version += 1;
+   printf("Silicon: v%d.%d\n", version >> 1, version & 1);
+   return 0;
+}
-- 
2.15.1

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[U-Boot] [PATCH 1/2] zynq: board: Remove checkboard()

[Ezequiel Garcia]

Currently we are showing silicon version as board info,
which should be part of the CPU info display.

This commit removes the current checkboard implementation,
and lets the generic show_board_info() show the DT 'model'
property.

CPU and silicon information will be added in a follow-up patch.

Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 board/xilinx/zynq/board.c | 16 
 1 file changed, 16 deletions(-)

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index e59038106aa6..5785ad369fa0 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -109,22 +109,6 @@ int board_late_init(void)
return 0;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-   u32 version = zynq_get_silicon_version();
-
-   version <<= 1;
-   if (version > (PCW_SILICON_VERSION_3 << 1))
-   version += 1;
-
-   puts("Board: Xilinx Zynq\n");
-   printf("Silicon: v%d.%d\n", version >> 1, version & 1);
-
-   return 0;
-}
-#endif
-
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 {
 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
-- 
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[U-Boot] [PATCH] doc: Update the zynq u-boot status

[Ezequiel Garcia]

NAND and QSPI devices are now supported, so mark
them as such.

Cc: Michal Simek <michal.si...@xilinx.com>
Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 doc/README.zynq | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/doc/README.zynq b/doc/README.zynq
index b89c39edac18..451743f39eaa 100644
--- a/doc/README.zynq
+++ b/doc/README.zynq
@@ -62,9 +62,10 @@ bootmode strings at runtime.
   serial - drivers/serial/serial_zynq.c
   net - drivers/net/zynq_gem.c
   mmc - drivers/mmc/zynq_sdhci.c
-  mmc - drivers/mmc/zynq_sdhci.c
-  spi-  drivers/spi/zynq_spi.c
+  spi - drivers/spi/zynq_spi.c
+  qspi - drivers/spi/zynq_qspi.c
   i2c - drivers/i2c/zynq_i2c.c
+  nand - drivers/mtd/nand/zynq_nand.c
 - Done proper cleanups on board configurations
 - Added basic FDT support for zynq boards
 - d-cache support for zynq_gem.c
@@ -72,8 +73,6 @@ bootmode strings at runtime.
 6. TODO
 
 - Add zynq boards support - zc770_xm011
-- Add zynq qspi controller driver
-- Add zynq nand controller driver
 - Add FDT support on individual drivers
 
 [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
-- 
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Re: [U-Boot] [PATCH] mtd: zynq: nand: Move board_nand_init() function to board.c

[Ezequiel Garcia]

Hi Wilson,

On 8 November 2017 at 06:24, Wilson Lee  wrote:
> Hi Michal,
>
> On Wed, 2017-11-08 at 08:54 +0100, Michal Simek wrote:
>> On 8.11.2017 03:44, Wilson Lee wrote:
>> >
>> > Putting board_nand_init() function inside NAND driver was not
>> > appropriate
>> > due to it doesn't allow board vendor to customise their NAND
>> > initialization code such as adding NAND lock/unlock code.
>> >
>> > This commit was to move the board_nand_init() function from NAND
>> > driver
>> > to board.c file. This allow customization of board_nand_init()
>> > function.
>> >
>> > Signed-off-by: Wilson Lee 
>> > Cc: Joe Hershberger 
>> > Cc: Keng Soon Cheah 
>> > Cc: Chen Yee Chew 
>> > Cc: Albert Aribaud 
>> > Cc: Michal Simek 
>> > Cc: Siva Durga Prasad Paladugu 
>> > Cc: Scott Wood 
>> > ---
>> >  arch/arm/mach-zynq/include/mach/nand.h |  9 +
>> >  board/xilinx/zynq/board.c  | 10 ++
>> >  drivers/mtd/nand/zynq_nand.c   | 12 +---
>> >  3 files changed, 20 insertions(+), 11 deletions(-)
>> >  create mode 100644 arch/arm/mach-zynq/include/mach/nand.h
>> >
>> > diff --git a/arch/arm/mach-zynq/include/mach/nand.h
>> > b/arch/arm/mach-zynq/include/mach/nand.h
>> > new file mode 100644
>> > index 000..61ef45f
>> > --- /dev/null
>> > +++ b/arch/arm/mach-zynq/include/mach/nand.h
>> > @@ -0,0 +1,9 @@
>> > +/*
>> > + * Copyright (C) 2017 National Instruments Corp.
>> > + *
>> > + * SPDX-License-Identifier:GPL-2.0+
>> > + */
>> > +
>> > +#include 
>> > +
>> > +void zynq_nand_init(void);
>> > diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
>> > index 90ef542..8bcb830 100644
>> > --- a/board/xilinx/zynq/board.c
>> > +++ b/board/xilinx/zynq/board.c
>> > @@ -9,6 +9,7 @@
>> >  #include 
>> >  #include 
>> >  #include 
>> > +#include 
>> >  #include 
>> >  #include 
>> >
>> > @@ -156,3 +157,12 @@ int dram_init(void)
>> > return 0;
>> >  }
>> >  #endif
>> > +
>> > +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
>> > +void board_nand_init(void)
>> > +{
>> > +   struct nand_chip *nand = _chip[0];
>> > +
>> > +   if (zynq_nand_init(nand, 0))
>> > +   puts("ZYNQ NAND init failed\n");
>> > +}
>> This is probably not enough for platforms which don't enable NAND.
>>
>> >
>> > diff --git a/drivers/mtd/nand/zynq_nand.c
>> > b/drivers/mtd/nand/zynq_nand.c
>> > index dec2c41..9be6856 100644
>> > --- a/drivers/mtd/nand/zynq_nand.c
>> > +++ b/drivers/mtd/nand/zynq_nand.c
>> > @@ -1006,7 +1006,7 @@ static int zynq_nand_device_ready(struct
>> > mtd_info *mtd)
>> > return 0;
>> >  }
>> >
>> > -static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
>> > +int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
>> >  {
>> > struct zynq_nand_info *xnand;
>> > struct mtd_info *mtd;
>> > @@ -1191,13 +1191,3 @@ fail:
>> > free(xnand);
>> > return err;
>> >  }
>> > -
>> > -static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
>> > -
>> > -void board_nand_init(void)
>> > -{
>> > -   struct nand_chip *nand = _chip[0];
>> > -
>> > -   if (zynq_nand_init(nand, 0))
>> > -   puts("ZYNQ NAND init failed\n");
>> > -}
>> >
>> What's the sequence which you want to add?
>
> Actually we wish to perform a NAND unlock right after the NAND was
> begin initialized. So that, we can do some write operation (ubifs table
> R/W) when we mount it as ubifs.
>

Why do you need to export board_nand_init
in order to add do a NAND unlock after NAND initialization?

Perhaps you could point me at your U-Boot repo to see
what you need exactly.

I'm seeing at least two ways of doing this:

1) Using a script that calls nand unlock command
and then does the UBIFS stuff.

2) Using board_late_init like this:

static void unlock_nand(void)
{
int dev = nand_curr_device;
struct mtd_info *mtd;

mtd = get_nand_dev_by_index(dev);
nand_unlock(mtd, 0, mtd->size, 0);
}

int board_late_init(void)
{
/* some other stuff  */

unlock_nand();
}

To be honest, I dislike this patch quite a bit,
because it's code meant for out-of-tree ports.

We tend to avoid keeping infra for out-of-tree code,
because it makes the code hard to improve or cleanup
without breaking the out-of-tree port doing so.

>> Isn't it better just to include this there or create a hook here?
>
> I was thinking for adding a hook here before. But, it will be more make
> sense to me if we correct the NAND driver by moving board_nand to
> board.c file.
>
>>
>> Definitely some platforms moved this to board file and not a problem
>> with moving it because it shouldn't be in nand driver.
>>
>> Thanks,
>> Michal
>>
>
> Thanks, Michal.
>
> Best Regards,
> Wilson Lee
> ___
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> 

Re: [U-Boot] [PATCH v2] mtd: zynq: nand: Move board_nand_init() function to board.c

[Ezequiel Garcia]

On 15 November 2017 at 06:14, Wilson Lee  wrote:
> Putting board_nand_init() function inside NAND driver was not appropriate
> due to it doesn't allow board vendor to customise their NAND
> initialization code such as adding NAND lock/unlock code.
>
> This commit was to move the board_nand_init() function from NAND driver
> to board.c file. This allow customization of board_nand_init() function.
>
> Signed-off-by: Wilson Lee 
> Cc: Joe Hershberger 
> Cc: Keng Soon Cheah 
> Cc: Chen Yee Chew 
> Cc: Albert Aribaud 
> Cc: Michal Simek 
> Cc: Siva Durga Prasad Paladugu 
> Cc: Scott Wood 
> ---
>  arch/arm/mach-zynq/include/mach/nand.h | 9 +
>  drivers/mtd/nand/zynq_nand.c   | 6 --
>  2 files changed, 13 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/mach-zynq/include/mach/nand.h
>
> diff --git a/arch/arm/mach-zynq/include/mach/nand.h 
> b/arch/arm/mach-zynq/include/mach/nand.h
> new file mode 100644
> index 000..61ef45f
> --- /dev/null
> +++ b/arch/arm/mach-zynq/include/mach/nand.h
> @@ -0,0 +1,9 @@
> +/*
> + * Copyright (C) 2017 National Instruments Corp.
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include 
> +
> +void zynq_nand_init(void);
> diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c
> index dec2c41..076b878 100644
> --- a/drivers/mtd/nand/zynq_nand.c
> +++ b/drivers/mtd/nand/zynq_nand.c
> @@ -1006,7 +1006,7 @@ static int zynq_nand_device_ready(struct mtd_info *mtd)
> return 0;
>  }
>
> -static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
> +int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
>  {
> struct zynq_nand_info *xnand;
> struct mtd_info *mtd;
> @@ -1192,12 +1192,14 @@ fail:
> return err;
>  }
>
> +#ifdef CONFIG_SYS_NAND_SELF_INIT

Just found this patch while debugging a NAND problem
using current U-Boot upstream, on a custom board. In fact,
I wrote a patch which is an exact revert of this one,
until I noticed the board_nand_init is exported on purpose.

A few observations:

1) The driver selects CONFIG_SYS_NAND_SELF_INIT,
which makes this ifdef a no-op. I'm guessing vendors are using
the driver without the self-init mode. Is that the case?

2) This driver looks broken in upstream, refusing to initalize properly.
The reason is that get_nand_dev_by_index() was being called before
nand_register(), thus returning a pointer into uninitialized memory.
In other words, the struct mtd_info used by the driver is total junk.

The fix is simple, I cooked a patch for it:

diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c
index 6494196049f1..9f6ff3d045c2 100644
--- a/drivers/mtd/nand/zynq_nand.c
+++ b/drivers/mtd/nand/zynq_nand.c
@@ -1025,7 +1025,7 @@ int zynq_nand_init(struct nand_chip *nand_chip,
int devnum)
}

xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
-   mtd = get_nand_dev_by_index(0);
+   mtd = nand_to_mtd(nand_chip);

However, I am not sure about sending this patch upstream, because
it assumes the driver is used on self-init mode only.

Any hints on how this should be fixed properly? Perhaps we should
find a cleaner path into a lock/unlock hook in upstream.

>  static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
>
> -void board_nand_init(void)
> +void __weak board_nand_init(void)
>  {
> struct nand_chip *nand = _chip[0];
>
> if (zynq_nand_init(nand, 0))
> puts("ZYNQ NAND init failed\n");
>  }
> +#endif
> --
> 2.7.4
>
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[U-Boot] [PATCH] arm: zynq: Enable SPL_CLK only if SPL is enabled

[Ezequiel Garcia]

Setup proper dependency in Kconfig for SPL_CLK.
If SPL is not enabled, SPL_CLK shouldn't be selected.

Cc: Michal Simek <michal.si...@xilinx.com>
Signed-off-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
---
 arch/arm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index de323bf4b96e..4ff369c32524 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -760,7 +760,7 @@ config ARCH_ZYNQ
select DM_USB if USB
select BLK
select CLK
-   select SPL_CLK
+   select SPL_CLK if SPL
select CLK_ZYNQ
imply CMD_CLK
imply FAT_WRITE
-- 
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Re: [U-Boot] [RFC PATCH v1 1/6] mtd: nand: pxa3xx_nand: Increase initial buffer size

[Ezequiel Garcia]

On 20 October 2016 at 17:14, Chris Packham <judge.pack...@gmail.com> wrote:
> On Fri, Oct 21, 2016 at 1:58 AM, Ezequiel Garcia
> <ezequ...@vanguardiasur.com.ar> wrote:
>> On 20 October 2016 at 01:31, Chris Packham <judge.pack...@gmail.com> wrote:
>>> The initial buffer is used for the initial commands used to detect
>>> a flash device (STATUS, READID and PARAM).
>>>
>>> ONFI param page is 256 bytes, and there are three redundant copies
>>> to be read. JEDEC param page is 512 bytes, and there are also three
>>> redundant copies to be read. Hence this buffer should be at least
>>> 512 x 3. This commits rounds the buffer size to 2048.
>>>
>>
>> Hey Chris,
>>
>> So you are basically picking the commit and commit log from Linux:
>>
>> http://lists.infradead.org/pipermail/linux-mtd/2015-August/060721.html
>>
>> Shouldn't you mention that somewhere?
>
> Indeed. I mentioned it here
> http://lists.denx.de/pipermail/u-boot/2016-October/270605.html and
> that was the intent of the Cc line below.
>

Oh, I see. IMO, that won't do it. See, the mail is going to get lost
in the internet sea, but the commit log is going to be set on git stone
and pass to generations to come.

I'm not really about taking credit, but rather about creating a persistent
reference between code you've copy-pasted. This will be useful, e.g.
in case it turns out it's wrong, which is perfectly possible. If someone
notices it's wrong in U-Boot code, it might git-blame-it and so from
there realise the change is needed in Linux too.

Just a silly example, but I'm trying to make a point on why it's useful
to link copy-pasted implementations.

Mentioning in the cover letter is probably great, but don't forget
the actual patch serves a different purpose.

> I should probably set the From: line to the original author and call
> out the Linux commit sha1. I wasn't sure of the usual u-boot practice,
> I could equally squash these all together and say "sync with linux".
>

I'm not sure that matters, as long as you state where is the code
coming from.

>>
>>> Cc: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
>>> Signed-off-by: Chris Packham <judge.pack...@gmail.com>
>>> ---
>>>
>>>  drivers/mtd/nand/pxa3xx_nand.c | 16 ++--
>>>  1 file changed, 10 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
>>> index dfe8966b56b6..ea0a6f3778bd 100644
>>> --- a/drivers/mtd/nand/pxa3xx_nand.c
>>> +++ b/drivers/mtd/nand/pxa3xx_nand.c
>>> @@ -26,10 +26,13 @@
>>>
>>>  /*
>>>   * Define a buffer size for the initial command that detects the flash 
>>> device:
>>> - * STATUS, READID and PARAM. The largest of these is the PARAM command,
>>> - * needing 256 bytes.
>>> + * STATUS, READID and PARAM.
>>> + * ONFI param page is 256 bytes, and there are three redundant copies
>>> + * to be read. JEDEC param page is 512 bytes, and there are also three
>>> + * redundant copies to be read.
>>> + * Hence this buffer should be at least 512 x 3. Let's pick 2048.
>>>   */
>>> -#define INIT_BUFFER_SIZE   256
>>> +#define INIT_BUFFER_SIZE   2048
>>>
>>>  /* registers and bit definitions */
>>>  #define NDCR   (0x00) /* Control register */
>>> @@ -838,14 +841,14 @@ static int prepare_set_command(struct 
>>> pxa3xx_nand_info *info, int command,
>>> break;
>>>
>>> case NAND_CMD_PARAM:
>>> -   info->buf_count = 256;
>>> +   info->buf_count = INIT_BUFFER_SIZE;
>>> info->ndcb0 |= NDCB0_CMD_TYPE(0)
>>> | NDCB0_ADDR_CYC(1)
>>> | NDCB0_LEN_OVRD
>>> | command;
>>> info->ndcb1 = (column & 0xFF);
>>> -   info->ndcb3 = 256;
>>> -   info->data_size = 256;
>>> +   info->ndcb3 = INIT_BUFFER_SIZE;
>>> +   info->data_size = INIT_BUFFER_SIZE;
>>> break;
>>>
>>> case NAND_CMD_READID:
>>> @@ -1468,6 +1471,7 @@ KEEP_CONFIG:
>>> host->row_addr_cycles = 3;
>>> else
>>> host->row_addr_cycles = 2;
>>> +
>>
>> Spurious change. I suggest to drop it.
>>
>
> Will do.
>
>>> return nand_scan_tail(mtd);
>>>  }
>>>
>>> --
>>> 2.10.0.479.g7c56b16
>>>
>>
>>
>>
>> --
>> Ezequiel García, VanguardiaSur
>> www.vanguardiasur.com.ar



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Re: [U-Boot] [RFC PATCH v1 1/6] mtd: nand: pxa3xx_nand: Increase initial buffer size

[Ezequiel Garcia]

On 20 October 2016 at 01:31, Chris Packham <judge.pack...@gmail.com> wrote:
> The initial buffer is used for the initial commands used to detect
> a flash device (STATUS, READID and PARAM).
>
> ONFI param page is 256 bytes, and there are three redundant copies
> to be read. JEDEC param page is 512 bytes, and there are also three
> redundant copies to be read. Hence this buffer should be at least
> 512 x 3. This commits rounds the buffer size to 2048.
>

Hey Chris,

So you are basically picking the commit and commit log from Linux:

http://lists.infradead.org/pipermail/linux-mtd/2015-August/060721.html

Shouldn't you mention that somewhere?

> Cc: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>
> Signed-off-by: Chris Packham <judge.pack...@gmail.com>
> ---
>
>  drivers/mtd/nand/pxa3xx_nand.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index dfe8966b56b6..ea0a6f3778bd 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -26,10 +26,13 @@
>
>  /*
>   * Define a buffer size for the initial command that detects the flash 
> device:
> - * STATUS, READID and PARAM. The largest of these is the PARAM command,
> - * needing 256 bytes.
> + * STATUS, READID and PARAM.
> + * ONFI param page is 256 bytes, and there are three redundant copies
> + * to be read. JEDEC param page is 512 bytes, and there are also three
> + * redundant copies to be read.
> + * Hence this buffer should be at least 512 x 3. Let's pick 2048.
>   */
> -#define INIT_BUFFER_SIZE   256
> +#define INIT_BUFFER_SIZE   2048
>
>  /* registers and bit definitions */
>  #define NDCR   (0x00) /* Control register */
> @@ -838,14 +841,14 @@ static int prepare_set_command(struct pxa3xx_nand_info 
> *info, int command,
> break;
>
> case NAND_CMD_PARAM:
> -   info->buf_count = 256;
> +   info->buf_count = INIT_BUFFER_SIZE;
> info->ndcb0 |= NDCB0_CMD_TYPE(0)
> | NDCB0_ADDR_CYC(1)
> | NDCB0_LEN_OVRD
> | command;
> info->ndcb1 = (column & 0xFF);
> -   info->ndcb3 = 256;
> -   info->data_size = 256;
> +   info->ndcb3 = INIT_BUFFER_SIZE;
> +   info->data_size = INIT_BUFFER_SIZE;
> break;
>
> case NAND_CMD_READID:
> @@ -1468,6 +1471,7 @@ KEEP_CONFIG:
> host->row_addr_cycles = 3;
> else
> host->row_addr_cycles = 2;
> +

Spurious change. I suggest to drop it.

> return nand_scan_tail(mtd);
>  }
>
> --
> 2.10.0.479.g7c56b16
>



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Re: [U-Boot] [PATCH] rockchip: Turn on CONFIG_DEBUG_LL for firefly

[Ezequiel Garcia]

On 12 November 2015 at 18:42, Ariel D'Alessandro
 wrote:
> CONFIG_DEBUG_UART is enabled in defconfig, but there's no Low-level
> debugging functions implemented, so build fails because of undefined
> references to `printch' in common/console.c.
> In order to fix this, enable CONFIG_DEBUG_LL.
>

I think you are fixing this the wrong way. This patch
solves the problem as well, and I think it's the right way:

[patch format is probably wasted]
@@ -34,6 +34,7 @@ CONFIG_REGULATOR_ACT8846=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_NS16550=y
 CONFIG_DEBUG_UART_BASE=0xff69
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2

Without this fix, Altera JTAG UART is selected instead of NS16550.
I expect other defconfigs (e.g. chromebook_jerry_defconfig) to suffer
from this as well.

That said, I still haven't looked at the differences between
DEBUG_LL and DEBUG_UART.
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Re: [U-Boot] Porting UBI fixes (specially fastmap's) to U-Boot

[Ezequiel Garcia]

On 19 October 2015 at 02:17, Heiko Schocher <h...@denx.de> wrote:
> Hello Ezequiel,
>
> Am 17.10.2015 um 20:07 schrieb Ezequiel Garcia:
>>
>> Hi Heiko,
>>
>> On 9 October 2015 at 09:30, Heiko Schocher <h...@denx.de> wrote:
>> [..]
>>>
>>>
>>>
>>> I just updated the "ubi_sync_with_linux" branch on u-boot-ubi.
>>>
>>> It seems UBI/UBIFS now work with the NAND on the aristainetos2
>>> board, but my stomach says, there are some subtile issues ...
>>>
>>> Still needs more testing, also not tested yet UBI on the SPI NOR on
>>> this board.
>>>
>>> If I "nand erase" the mtd device, and try "ubi part ..." it fails
>>>
>>> :-(
>>>
>>> But If I flash_eraseall under linux the device, and then make
>>> "ubi part..." in U-Boot, commmand succeeds ...
>>>
>>
>> Tested it on my custom AM335x board. Haven't used mainline U-Boot
>> but cherry-picked the following commits:
>>
>>linux, compat: add missing definitions for ubi
>>ubi/ubifs: some bugfixes
>>ubi,ubifs: sync with linux v4.2
>>ubi: reset mtd_devs when ubi part fail
>>
>> Commits apply cleanly except for "linux, compat: add missing
>> definitions for ubi"
>> which was trivial to backport anyway.
>>
>> U-Boot built fine, but there was a warning:
>>
>> drivers/mtd/ubi/fastmap.c: In function 'ubi_attach_fastmap':
>> drivers/mtd/ubi/fastmap.c:816:2: warning: pointer targets in passing
>> argument 3 of 'scan_pool' differ in signedness [-Wpointer-sign]
>>ret = scan_pool(ubi, ai, fmpl->pebs, pool_size, _sqnum, );
>>
>> Just sent this patch which should fix it:
>> http://patchwork.ozlabs.org/patch/531842/
>
>
> Thanks for fixing. With it, I see no compiler warning anymore.
> Applied to u-boot-ubi.git ubi_sync_with_linux
>
> Tried this branch on the aristainetos2 board with ubi/ubifs on nand and
> spi nor flash, worked fine, see log:
>
> http://xeidos.ddns.net/buildbot/builders/ari_ubi/builds/7
> http://xeidos.ddns.net/buildbot/builders/ari_ubi/builds/7/steps/shell/logs/tbotlog
>
>> The board seems to work fine, and I can even to "nand erase" and "ubi
>> part" without
>> any problem.
>
>
> Did you tried "ubi part" more than once in a row?
>

Yup, I can do "ubi part $mypart" several times. And can also do "nand
erase.part foo"
and then "ubi part foo" several times.

The patches seem to work fine here, so:

Tested-by: Ezequiel Garcia <ezequ...@vanguardiasur.com.ar>

>> However, I'm still seeing the same warning I had before, when my partition
>> is attached:
>>
>> ubi0: default fastmap pool size: 200
>> ubi0: default fastmap WL pool size: 100
>> ubi0: attaching mtd1
>> WARNING in drivers/mtd/ubi/fastmap.c line 846
>> ubi0: scanning is finished
>> ubi0: attached mtd1 (name "mtd=7", size 509 MiB)
>> ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 129024 bytes
>> ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 512
>> ubi0: VID header offset: 512 (aligned 512), data offset: 2048
>> ubi0: good PEBs: 4072, bad PEBs: 4, corrupted PEBs: 0
>> ubi0: user volume: 4, internal volumes: 1, max. volumes count: 128
>> ubi0: max/mean erase counter: 5/3, WL threshold: 4096, image sequence
>> number: 2068197800
>> ubi0: available PEBs: 3504, total reserved PEBs: 568, PEBs reserved
>> for bad PEB handling: 76
>>
>> @Richard, any ideas? Do you know which of the fixes should fix that?
>

After some further investigation, printing the counters as Richard suggested
I found it was a bug on my side :-( The Linux partition and the U-Boot partition
had different size (i.e. PEB count) and so Fastmap complained :-(

We trimmed the Linux partition size, and forgot to change U-Boot's
(or thought it wouldn't matter).

Sorry for the noise guys!

>
> Does this warning raise also in linux? I do not see it on the aristainetos2
> board.
>
> U-Boot code:
>
>/*
>  * If fastmap is leaking PEBs (must not happen), raise a
>  * fat warning and fall back to scanning mode.
>  * We do this here because in ubi_wl_init() it's too late
>  * and we cannot fall back to scanning.
>  */
> #ifndef __UBOOT__
> if (WARN_ON(count_fastmap_pebs(ai) != ubi->peb_count -
> ai->bad_peb_count - fm->used_blocks))
> goto fail_bad;
> #else
> if (count_fastmap_pebs(ai) != ubi->peb_count -
> 

Re: [U-Boot] Porting UBI fixes (specially fastmap's) to U-Boot

[Ezequiel Garcia]

On 19 October 2015 at 17:22, Richard Weinberger <rich...@nod.at> wrote:
> Am 19.10.2015 um 15:47 schrieb Ezequiel Garcia:
>> After some further investigation, printing the counters as Richard suggested
>> I found it was a bug on my side :-( The Linux partition and the U-Boot 
>> partition
>> had different size (i.e. PEB count) and so Fastmap complained :-(
>>
>> We trimmed the Linux partition size, and forgot to change U-Boot's
>> (or thought it wouldn't matter).
>>
>> Sorry for the noise guys!
>
> Good to know. :)
>
> Let me find a way to detect and report this kind of user error
> better.
> The WARN_ON() is only meant for bad internal errors.
>

Sure. In case it's not clear, let me clarify what the issue was: the
MTD partition
has one size in Linux (4072 EB) and another size in U-Boot (4076 EB).

When the map was built by Linux's Fastmap, it contained a number of PEBs that
conflicted with the number of PEBs U-Boot's Fastmap code was expecting
(becase Linux EB != U-Boot EB).

Not sure how you would detect such a mismatch, but it was a very good
idea to print a noisy warning :-)

We were effectively running without fastmap so far, becasue neither U-Boot
nor Linux could find a proper fastmap and attach the UBI partition using it.

Hope it's clear.
-- 
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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Re: [U-Boot] Porting UBI fixes (specially fastmap's) to U-Boot

[Ezequiel Garcia]

Hi Heiko,

On 9 October 2015 at 09:30, Heiko Schocher  wrote:
[..]
>
>
> I just updated the "ubi_sync_with_linux" branch on u-boot-ubi.
>
> It seems UBI/UBIFS now work with the NAND on the aristainetos2
> board, but my stomach says, there are some subtile issues ...
>
> Still needs more testing, also not tested yet UBI on the SPI NOR on
> this board.
>
> If I "nand erase" the mtd device, and try "ubi part ..." it fails
>
> :-(
>
> But If I flash_eraseall under linux the device, and then make
> "ubi part..." in U-Boot, commmand succeeds ...
>

Tested it on my custom AM335x board. Haven't used mainline U-Boot
but cherry-picked the following commits:

  linux, compat: add missing definitions for ubi
  ubi/ubifs: some bugfixes
  ubi,ubifs: sync with linux v4.2
  ubi: reset mtd_devs when ubi part fail

Commits apply cleanly except for "linux, compat: add missing
definitions for ubi"
which was trivial to backport anyway.

U-Boot built fine, but there was a warning:

drivers/mtd/ubi/fastmap.c: In function 'ubi_attach_fastmap':
drivers/mtd/ubi/fastmap.c:816:2: warning: pointer targets in passing
argument 3 of 'scan_pool' differ in signedness [-Wpointer-sign]
  ret = scan_pool(ubi, ai, fmpl->pebs, pool_size, _sqnum, );

Just sent this patch which should fix it:
http://patchwork.ozlabs.org/patch/531842/

The board seems to work fine, and I can even to "nand erase" and "ubi
part" without
any problem.

However, I'm still seeing the same warning I had before, when my partition
is attached:

ubi0: default fastmap pool size: 200
ubi0: default fastmap WL pool size: 100
ubi0: attaching mtd1
WARNING in drivers/mtd/ubi/fastmap.c line 846
ubi0: scanning is finished
ubi0: attached mtd1 (name "mtd=7", size 509 MiB)
ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 129024 bytes
ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 512
ubi0: VID header offset: 512 (aligned 512), data offset: 2048
ubi0: good PEBs: 4072, bad PEBs: 4, corrupted PEBs: 0
ubi0: user volume: 4, internal volumes: 1, max. volumes count: 128
ubi0: max/mean erase counter: 5/3, WL threshold: 4096, image sequence
number: 2068197800
ubi0: available PEBs: 3504, total reserved PEBs: 568, PEBs reserved
for bad PEB handling: 76

@Richard, any ideas? Do you know which of the fixes should fix that?
-- 
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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Re: [U-Boot] Porting UBI fixes (specially fastmap's) to U-Boot

[Ezequiel Garcia]

On 16 October 2015 at 04:56, Heiko Schocher <h...@denx.de> wrote:
> Hello Ezequiel,
>
>
> Am 09.10.2015 um 14:30 schrieb Heiko Schocher:
>>
>> Hello Ezequiel,
>>
>> Am 09.10.2015 um 06:01 schrieb Heiko Schocher:
>>>
>>> Hello Ezequiel,
>>>
>>> Am 08.10.2015 um 17:54 schrieb Ezequiel Garcia:
>>>>
>>>> Heiko,
>>>>
>>>> On 8 October 2015 at 11:54, Heiko Schocher <h...@denx.de> wrote:
>>>> [..]
>>>>>
>>>>>
>>>>> Currently I have a (with warnings) compiled U-Boot with ubi/ubifs
>>>>> with linux 4.2 base ... now testing (or tomorrow)
>>>>>
>>>>
>>>> If you share a branch, I can help with some tests here.
>>>
>>>
>>> I pushed my current develop state to:
>>>
>>>
>>> http://git.denx.de/?p=u-boot/u-boot-ubi.git;a=shortlog;h=refs/heads/ubi_sync_with_linux
>>>
>>> ! Only for Testing !
>>>
>>> I tested it on the aristainetos2 board, with fastmap enabled. I was
>>> enable to attach the ubi partition on nand flash with the "ubi part .."
>>> command. If I have attached a partition and again call "ubi part ..."
>>> u-boot hangs currently ... more testing debugging hopefully I can do
>>> today. so there is some work for debugging. It would be nice, if you
>>> can look into this issue (and of course try ubi on your hw), thanks!
>>>
>>> And maybe you find time to get rid of the compilerwarnings ;-)
>>>
>>>> Thanks a lot for the quick work!
>>>
>>>
>>> You are welcome
>>
>>
>> I just updated the "ubi_sync_with_linux" branch on u-boot-ubi.
>>
>> It seems UBI/UBIFS now work with the NAND on the aristainetos2
>> board, but my stomach says, there are some subtile issues ...
>>
>> Still needs more testing, also not tested yet UBI on the SPI NOR on
>> this board.
>>
>> If I "nand erase" the mtd device, and try "ubi part ..." it fails
>>
>> :-(
>>
>> But If I flash_eraseall under linux the device, and then make
>> "ubi part..." in U-Boot, commmand succeeds ...
>
>
> ping?
>

Just got back from a trip...

> Did you had time for some tests?
>

...so it will take me some time to get to this. Still it's
on the top of my list, so I'll try to work on this as soon
as possible.
-- 
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www.vanguardiasur.com.ar
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Re: [U-Boot] Porting UBI fixes (specially fastmap's) to U-Boot

[Ezequiel Garcia]

Heiko,

On 8 October 2015 at 11:54, Heiko Schocher  wrote:
[..]
>
> Currently I have a (with warnings) compiled U-Boot with ubi/ubifs
> with linux 4.2 base ... now testing (or tomorrow)
>

If you share a branch, I can help with some tests here.

Thanks a lot for the quick work!
-- 
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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