Re: [U-Boot] x86: ACPI support suggestion
Hi Bin, On 06/23/2015 04:30 AM, Bin Meng wrote: Hi Gabriel, On Sat, Feb 7, 2015 at 11:07 PM, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Simon, On 02/06/2015 03:14 PM, Simon Glass wrote: Hi, On 6 February 2015 at 16:11, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Simon, On 02/06/2015 03:04 PM, Simon Glass wrote: Hi Gabriel, On 6 February 2015 at 16:01, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Bin, Actually I was able to try with a quickdirty code the integration of the ACPI tables (aml files) and it doesn't seem to be possible. The boot to Linux is working fine, all the ACPI tables are loaded correctly, but the system is unstable and it seems to have some issue with the interrupts handler. As debugging this kind of issues could be really tricky and involve also a lot of modification, I think we are stuck to port the ACPI support from coreboot to u-boot. I will try to work on a first draft and see how things look like. One thing to note is that U-Boot may not currently set up the PCI interrupts fully. Or perhaps the problem is that ACPI needs to match. What platform are you using? [snip] MinnowBoard Max (BayTrail). Actually, you may be right, I didn't check this part. Actually that uses an FSP so might already be correct, but it is certainly worth checking. I just checked the dmesg again and I didn't see that the first time: [0.723098] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15) *0, disabled. [0.732328] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 11 12 14 15) *0, disabled. [0.741551] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15) *0, disabled. [0.750782] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 11 12 14 15) *0, disabled. [0.760006] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15) *0, disabled. So I believe the PIRQ routing is missing in u-boot. I checked in the source of Coreboot, and actually everything is done in the southcluster initialization. Also, I saw that the GPIO iomap wasn't done and it appeared that the USB2 port wasn't powered up (the white one), enabling the port allow us to use of both port in the EHCI mode. I'll give a try to initialize the PIRQ and see how things is going. Did you manage to get PIRQ work on MinnowMax? If not, I think you may try to implement PIRQ routing support first to see how things go. You can look at Intel Crown Bay device tree to add the PIRQ routing for MinnowMax. As for ACPI support, we have already started the work as part of GSoC 2015. Regards, Bin No, actually I will try to run some tests this week end, I'll keep you posted. This is good news for the ACPI support, I just saw the projects for the minnowboard, I'm really excited to see the first patches. Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Hi Andy,
On 05/26/2015 01:01 AM, Andy Pont wrote:
Hi Gabriel,
soc_gpio_s5_0@0 {
gpio-offset = 0x80 0;
pad-offset = 0x1d0;
mode-gpio;
output-value = 0;
direction = PIN_OUTPUT;
};
soc_gpio_s5_1@0 {
gpio-offset = 0x80 1;
pad-offset = 0x210;
mode-gpio;
output-value = 0;
direction = PIN_OUTPUT;
};
soc_gpio_s5_2@0 {
gpio-offset = 0x80 2;
pad-offset = 0x1e0;
mode-gpio;
output-value = 0;
direction = PIN_OUTPUT;
};
And after, you can use the GPIO commands:
= gpio set E0
gpio: pin E0 (gpio 128) value is 1
= gpio clear E0
gpio: pin E0 (gpio 128) value is 0
= gpio set E2
gpio: pin E2 (gpio 130) value is 1
= gpio clear E2
gpio: pin E2 (gpio 130) value is 0
E0 E1 and E2 correspond to the GPIO0 1 and 2.
Is there, or can someone add, some documentation somewhere as to how to
convert between the device tree definition and the value used for pin in
the gpio commands as it doesn't seem intuitive or obvious to me that what
you have defined translates to E0, E1 and E2.
I agree, but I think the documentation should be part of another patch,
especially as this is the case for all the x86 platform.
The naming is not specific to the minnowboard max (baytrail).
Thanks,
Andy.
Regards,
Gabriel
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[U-Boot] [PATCH v4 3/4] x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes in v4:
- Rebase modification on latest update
- Fix typo to read the io-base
- Fix direction_output function to set the value
Changes in v3:
- Fix the dt-binding copyright header
- Remove define for IOBASE and use a property
- Fix issues with signed/unsigned variable type
- Fix coding style
- Add a compatible string for the driver
Changes in v2:
- Clean commit message
- Rename compatible string 'ich6' to 'x86'
- Fix coding style
- Create a dt-bindinds documentation
- Move x86-gpio defines to a specific header
- Reorder the functions to avoid the need for forward declarations
- Rename double underscore functions to only one
- Create a specific function to configure one pin
- Use a define to prevent build/support issues with other x86 CPU that
doesn't have a IOBASE.
arch/x86/dts/minnowmax.dts | 23 ++
arch/x86/include/asm/gpio.h| 1 +
.../gpio/intel,x86-pinctrl.txt | 31 +++
drivers/gpio/intel_ich6_gpio.c | 257 ++---
include/dt-bindings/gpio/x86-gpio.h| 31 +++
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
7 files changed, 317 insertions(+), 28 deletions(-)
create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
create mode 100644 include/dt-bindings/gpio/x86-gpio.h
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 7103bc5..bd21bfb 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/x86-gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -22,6 +24,27 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,x86-pinctrl;
+ io-base = 0x4c;
+
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to
configured.
+- gpio-offset - (required) offset in the GPIOBASE for the pin to
configured and
+ also the bit shift in this register.
+- mode-gpio- (optional) standalone property to force the
pin into GPIO mode.
+- mode-func- (optional) function number to assign to the
pin. if 'mode-gpio'
+ is set, this property will be ignored.
+in case of 'mode-gpio' property set:
+- output-value - (optional) this set the default output value of the
GPIO.
+- direction - (optional) this set the direction of the gpio.
+- pull-str - (optional) this set the pull strength of the pin.
+- pull-assign - (optional) this set the pull assignement (up/down) of
the pin.
+
+Example:
+
+pin_usb_host_en0@0 {
+gpio-offset = 0x80 8;
+pad-offset = 0x260;
+mode-gpio;
+output-value = 1;
+direction = PIN_OUTPUT;
+};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..8a108f3 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers
Re: [U-Boot] [PATCH v3 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Hi Simon,
I just submitted a new version of the patch, actually, when I tried to
use the GPIO on the header I saw a typo in the code.
To test it, you have to define these nodes in the device tree (should be
there by default or not?):
soc_gpio_s5_0@0 {
gpio-offset = 0x80 0;
pad-offset = 0x1d0;
mode-gpio;
output-value = 0;
direction = PIN_OUTPUT;
};
soc_gpio_s5_1@0 {
gpio-offset = 0x80 1;
pad-offset = 0x210;
mode-gpio;
output-value = 0;
direction = PIN_OUTPUT;
};
soc_gpio_s5_2@0 {
gpio-offset = 0x80 2;
pad-offset = 0x1e0;
mode-gpio;
output-value = 0;
direction = PIN_OUTPUT;
};
And after, you can use the GPIO commands:
= gpio set E0
gpio: pin E0 (gpio 128) value is 1
= gpio clear E0
gpio: pin E0 (gpio 128) value is 0
= gpio set E2
gpio: pin E2 (gpio 130) value is 1
= gpio clear E2
gpio: pin E2 (gpio 130) value is 0
E0 E1 and E2 correspond to the GPIO0 1 and 2.
Regards,
Gabriel
On 05/20/2015 07:21 AM, Simon Glass wrote:
Hi Gabriel,
I have two patches in patchwork:
http://patchwork.ozlabs.org/patch/471146/
http://patchwork.ozlabs.org/patch/471147/
Are they the correct ones? Also do you know how to use the gpio
command to toggle a bin on the Minnowboard MAX header? I'd like to try
that.
Regards,
Simon
On 12 May 2015 at 00:20, gabriel huau cont...@huau-gabriel.fr wrote:
Please ignore this email/patch, I put the wrong message id ...
On 05/11/2015 11:12 PM, Gabriel Huau wrote:
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Rebase to the origin/master
Changes in v2:
- Fix ordering of include header
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 1f5549a..383cae0 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include asm/gpio.h
#include asm/ibmpc.h
#include asm/pnp_def.h
#include netdev.h
@@ -12,6 +13,14 @@
#define SERIAL_DEV PNP_DEV(0x2e, 4)
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index eb35a50..547765d 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
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[U-Boot] [PATCH v3 3/4] x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes in v3:
- Fix the dt-binding copyright header
- Remove define for IOBASE and use a property
- Fix issues with signed/unsigned variable type
- Fix coding style
- Add a compatible string for the driver
Changes in v2:
- Clean commit message
- Rename compatible string 'ich6' to 'x86'
- Fix coding style
- Create a dt-bindinds documentation
- Move x86-gpio defines to a specific header
- Reorder the functions to avoid the need for forward declarations
- Rename double underscore functions to only one
- Create a specific function to configure one pin
- Use a define to prevent build/support issues with other x86 CPU that
doesn't have a IOBASE.
arch/x86/dts/minnowmax.dts | 23 ++
arch/x86/include/asm/gpio.h| 1 +
.../gpio/intel,x86-pinctrl.txt | 31 +++
drivers/gpio/intel_ich6_gpio.c | 254 ++---
include/dt-bindings/gpio/x86-gpio.h| 31 +++
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
7 files changed, 312 insertions(+), 30 deletions(-)
create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
create mode 100644 include/dt-bindings/gpio/x86-gpio.h
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 7103bc5..bd21bfb 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/x86-gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -22,6 +24,27 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,x86-pinctrl;
+ io-base = 0x4c;
+
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to
configured.
+- gpio-offset - (required) offset in the GPIOBASE for the pin to
configured and
+ also the bit shift in this register.
+- mode-gpio- (optional) standalone property to force the
pin into GPIO mode.
+- mode-func- (optional) function number to assign to the
pin. if 'mode-gpio'
+ is set, this property will be ignored.
+in case of 'mode-gpio' property set:
+- output-value - (optional) this set the default output value of the
GPIO.
+- direction - (optional) this set the direction of the gpio.
+- pull-str - (optional) this set the pull strength of the pin.
+- pull-assign - (optional) this set the pull assignement (up/down) of
the pin.
+
+Example:
+
+pin_usb_host_en0@0 {
+gpio-offset = 0x80 8;
+pad-offset = 0x260;
+mode-gpio;
+output-value = 1;
+direction = PIN_OUTPUT;
+};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..35e8197 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,28 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define
[U-Boot] [PATCH v3 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Rebase to the origin/master
Changes in v2:
- Fix ordering of include header
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 1f5549a..383cae0 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include asm/gpio.h
#include asm/ibmpc.h
#include asm/pnp_def.h
#include netdev.h
@@ -12,6 +13,14 @@
#define SERIAL_DEV PNP_DEV(0x2e, 4)
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index eb35a50..547765d 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
--
2.1.4
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[U-Boot] [PATCH v3 3/4] x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes in v3:
- Fix the dt-binding copyright header
- Remove define for IOBASE and use a property
- Fix issues with signed/unsigned variable type
- Fix coding style
- Add a compatible string for the driver
Changes in v2:
- Clean commit message
- Rename compatible string 'ich6' to 'x86'
- Fix coding style
- Create a dt-bindinds documentation
- Move x86-gpio defines to a specific header
- Reorder the functions to avoid the need for forward declarations
- Rename double underscore functions to only one
- Create a specific function to configure one pin
- Use a define to prevent build/support issues with other x86 CPU that
doesn't have a IOBASE.
arch/x86/dts/minnowmax.dts | 23 ++
arch/x86/include/asm/gpio.h| 1 +
.../gpio/intel,x86-pinctrl.txt | 31 +++
drivers/gpio/intel_ich6_gpio.c | 254 ++---
include/dt-bindings/gpio/x86-gpio.h| 31 +++
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
7 files changed, 312 insertions(+), 30 deletions(-)
create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
create mode 100644 include/dt-bindings/gpio/x86-gpio.h
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 7103bc5..bd21bfb 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/x86-gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -22,6 +24,27 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,x86-pinctrl;
+ io-base = 0x4c;
+
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to
configured.
+- gpio-offset - (required) offset in the GPIOBASE for the pin to
configured and
+ also the bit shift in this register.
+- mode-gpio- (optional) standalone property to force the
pin into GPIO mode.
+- mode-func- (optional) function number to assign to the
pin. if 'mode-gpio'
+ is set, this property will be ignored.
+in case of 'mode-gpio' property set:
+- output-value - (optional) this set the default output value of the
GPIO.
+- direction - (optional) this set the direction of the gpio.
+- pull-str - (optional) this set the pull strength of the pin.
+- pull-assign - (optional) this set the pull assignement (up/down) of
the pin.
+
+Example:
+
+pin_usb_host_en0@0 {
+gpio-offset = 0x80 8;
+pad-offset = 0x260;
+mode-gpio;
+output-value = 1;
+direction = PIN_OUTPUT;
+};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..35e8197 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,28 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define
[U-Boot] [PATCH v3 3/4] x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes in v3:
- Fix the dt-binding copyright header
- Remove define for IOBASE and use a property
- Fix issues with signed/unsigned variable type
- Fix coding style
- Add a compatible string for the driver
Changes in v2:
- Clean commit message
- Rename compatible string 'ich6' to 'x86'
- Fix coding style
- Create a dt-bindinds documentation
- Move x86-gpio defines to a specific header
- Reorder the functions to avoid the need for forward declarations
- Rename double underscore functions to only one
- Create a specific function to configure one pin
- Use a define to prevent build/support issues with other x86 CPU that
doesn't have a IOBASE.
arch/x86/dts/minnowmax.dts | 23 ++
arch/x86/include/asm/gpio.h| 1 +
.../gpio/intel,x86-pinctrl.txt | 31 +++
drivers/gpio/intel_ich6_gpio.c | 254 ++---
include/dt-bindings/gpio/x86-gpio.h| 31 +++
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
7 files changed, 312 insertions(+), 30 deletions(-)
create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
create mode 100644 include/dt-bindings/gpio/x86-gpio.h
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 7103bc5..bd21bfb 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/x86-gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -22,6 +24,27 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,x86-pinctrl;
+ io-base = 0x4c;
+
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to
configured.
+- gpio-offset - (required) offset in the GPIOBASE for the pin to
configured and
+ also the bit shift in this register.
+- mode-gpio- (optional) standalone property to force the
pin into GPIO mode.
+- mode-func- (optional) function number to assign to the
pin. if 'mode-gpio'
+ is set, this property will be ignored.
+in case of 'mode-gpio' property set:
+- output-value - (optional) this set the default output value of the
GPIO.
+- direction - (optional) this set the direction of the gpio.
+- pull-str - (optional) this set the pull strength of the pin.
+- pull-assign - (optional) this set the pull assignement (up/down) of
the pin.
+
+Example:
+
+pin_usb_host_en0@0 {
+gpio-offset = 0x80 8;
+pad-offset = 0x260;
+mode-gpio;
+output-value = 1;
+direction = PIN_OUTPUT;
+};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..35e8197 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,28 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define
[U-Boot] [PATCH v3 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Rebase to the origin/master
Changes in v2:
- Fix ordering of include header
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 1f5549a..383cae0 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include asm/gpio.h
#include asm/ibmpc.h
#include asm/pnp_def.h
#include netdev.h
@@ -12,6 +13,14 @@
#define SERIAL_DEV PNP_DEV(0x2e, 4)
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index eb35a50..547765d 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Please ignore this email/patch, I put the wrong message id ...
On 05/11/2015 11:12 PM, Gabriel Huau wrote:
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Rebase to the origin/master
Changes in v2:
- Fix ordering of include header
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 1f5549a..383cae0 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include asm/gpio.h
#include asm/ibmpc.h
#include asm/pnp_def.h
#include netdev.h
@@ -12,6 +13,14 @@
#define SERIAL_DEV PNP_DEV(0x2e, 4)
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index eb35a50..547765d 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/4] x86: gpio: add pinctrl support from the device tree
Please ignore this email/patch, I put the wrong message id ...
On 05/11/2015 11:10 PM, Gabriel Huau wrote:
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes in v3:
- Fix the dt-binding copyright header
- Remove define for IOBASE and use a property
- Fix issues with signed/unsigned variable type
- Fix coding style
- Add a compatible string for the driver
Changes in v2:
- Clean commit message
- Rename compatible string 'ich6' to 'x86'
- Fix coding style
- Create a dt-bindinds documentation
- Move x86-gpio defines to a specific header
- Reorder the functions to avoid the need for forward declarations
- Rename double underscore functions to only one
- Create a specific function to configure one pin
- Use a define to prevent build/support issues with other x86 CPU that
doesn't have a IOBASE.
arch/x86/dts/minnowmax.dts | 23 ++
arch/x86/include/asm/gpio.h| 1 +
.../gpio/intel,x86-pinctrl.txt | 31 +++
drivers/gpio/intel_ich6_gpio.c | 254 ++---
include/dt-bindings/gpio/x86-gpio.h| 31 +++
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
7 files changed, 312 insertions(+), 30 deletions(-)
create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
create mode 100644 include/dt-bindings/gpio/x86-gpio.h
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 7103bc5..bd21bfb 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/x86-gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -22,6 +24,27 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,x86-pinctrl;
+ io-base = 0x4c;
+
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to
configured.
+- gpio-offset - (required) offset in the GPIOBASE for the pin to
configured and
+ also the bit shift in this register.
+- mode-gpio- (optional) standalone property to force the
pin into GPIO mode.
+- mode-func- (optional) function number to assign to the
pin. if 'mode-gpio'
+ is set, this property will be ignored.
+in case of 'mode-gpio' property set:
+- output-value - (optional) this set the default output value of the
GPIO.
+- direction - (optional) this set the direction of the gpio.
+- pull-str - (optional) this set the pull strength of the pin.
+- pull-assign - (optional) this set the pull assignement (up/down) of
the pin.
+
+Example:
+
+pin_usb_host_en0@0 {
+gpio-offset = 0x80 8;
+pad-offset = 0x260;
+mode-gpio;
+output-value = 1;
+direction = PIN_OUTPUT;
+};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..35e8197 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers
Re: [U-Boot] [PATCH v3 3/4] x86: gpio: add pinctrl support from the device tree
Please ignore this email/patch, I put the wrong message id ...
On 05/11/2015 11:15 PM, Gabriel Huau wrote:
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes in v3:
- Fix the dt-binding copyright header
- Remove define for IOBASE and use a property
- Fix issues with signed/unsigned variable type
- Fix coding style
- Add a compatible string for the driver
Changes in v2:
- Clean commit message
- Rename compatible string 'ich6' to 'x86'
- Fix coding style
- Create a dt-bindinds documentation
- Move x86-gpio defines to a specific header
- Reorder the functions to avoid the need for forward declarations
- Rename double underscore functions to only one
- Create a specific function to configure one pin
- Use a define to prevent build/support issues with other x86 CPU that
doesn't have a IOBASE.
arch/x86/dts/minnowmax.dts | 23 ++
arch/x86/include/asm/gpio.h| 1 +
.../gpio/intel,x86-pinctrl.txt | 31 +++
drivers/gpio/intel_ich6_gpio.c | 254 ++---
include/dt-bindings/gpio/x86-gpio.h| 31 +++
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
7 files changed, 312 insertions(+), 30 deletions(-)
create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
create mode 100644 include/dt-bindings/gpio/x86-gpio.h
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 7103bc5..bd21bfb 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/x86-gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -22,6 +24,27 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,x86-pinctrl;
+ io-base = 0x4c;
+
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to
configured.
+- gpio-offset - (required) offset in the GPIOBASE for the pin to
configured and
+ also the bit shift in this register.
+- mode-gpio- (optional) standalone property to force the
pin into GPIO mode.
+- mode-func- (optional) function number to assign to the
pin. if 'mode-gpio'
+ is set, this property will be ignored.
+in case of 'mode-gpio' property set:
+- output-value - (optional) this set the default output value of the
GPIO.
+- direction - (optional) this set the direction of the gpio.
+- pull-str - (optional) this set the pull strength of the pin.
+- pull-assign - (optional) this set the pull assignement (up/down) of
the pin.
+
+Example:
+
+pin_usb_host_en0@0 {
+gpio-offset = 0x80 8;
+pad-offset = 0x260;
+mode-gpio;
+output-value = 1;
+direction = PIN_OUTPUT;
+};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..35e8197 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers
Re: [U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree
Hi Simon,
Sorry for the delay, I'm gonna provide a new version in the next few
days but here is some answers to your question:
On 04/28/2015 06:53 AM, Simon Glass wrote:
Hi Gabriel,
On 25 April 2015 at 14:17, Gabriel Huau cont...@huau-gabriel.fr wrote:
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Clean commit message
- Rename compatible string 'ich6' to 'x86'
- Fix coding style
- Create a dt-bindinds documentation
- Move x86-gpio defines to a specific header
- Reorder the functions to avoid the need for forward declarations
- Rename double underscore functions to only one
- Create a specific function to configure one pin
- Use a define to prevent build/support issues with other x86 CPU that
doesn't have a IOBASE.
I have a few minor comments below. Do you know how to access the GPIO
pings on the top connector of the Minnowboard MAX? I'd like to figure
out the pin names for those in U-Boot and that would allow me to test
a few things.
You should be able to access SOC_GPIO_S5_0, SOC_GPIO_S5_1, SOC_GPIO_S5_2
GPIO_BASE should be 0x80 (respecting bit 0 1 and 2).
IO_BASE should be 0x1D0, 0x210, 0x1E0 (respect GPIO0, 1 and 2).
arch/x86/dts/minnowmax.dts | 21 ++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h| 1 +
.../gpio/intel,x86-pinctrl.txt | 31 +++
drivers/gpio/intel_ich6_gpio.c | 234 ++---
include/dt-bindings/gpio/x86-gpio.h| 36
6 files changed, 295 insertions(+), 29 deletions(-)
create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
create mode 100644 include/dt-bindings/gpio/x86-gpio.h
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..ea10963 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/x86-gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,x86-pinctrl;
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
Can we put this in the device tree as a property of the pch_pinctrl
node? If you like we could do it later.
Yes, I will do the modification, I thought as a first version it would
be easier to use a define but actually, a property is cleaner and also
easy to implement.
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to
configured.
+- gpio-offset - (required) offset in the GPIOBASE for the pin to
configured and
+ also the bit
Re: [U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree
Hi Stephen, Thanks for the feedback, I completely miss it, I will do the modification for the v3. On 04/28/2015 08:22 AM, Stephen Warren wrote: On 04/28/2015 07:53 AM, Simon Glass wrote: Hi Gabriel, On 25 April 2015 at 14:17, Gabriel Huau cont...@huau-gabriel.fr wrote: Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. diff --git a/include/dt-bindings/gpio/x86-gpio.h b/include/dt-bindings/gpio/x86-gpio.h +/* + * This header provides constants for binding nvidia,tegra*-gpio. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. I think this comment needs updating. Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Clean commit message
- Rename compatible string 'ich6' to 'x86'
- Fix coding style
- Create a dt-bindinds documentation
- Move x86-gpio defines to a specific header
- Reorder the functions to avoid the need for forward declarations
- Rename double underscore functions to only one
- Create a specific function to configure one pin
- Use a define to prevent build/support issues with other x86 CPU that
doesn't have a IOBASE.
arch/x86/dts/minnowmax.dts | 21 ++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h| 1 +
.../gpio/intel,x86-pinctrl.txt | 31 +++
drivers/gpio/intel_ich6_gpio.c | 234 ++---
include/dt-bindings/gpio/x86-gpio.h| 36
6 files changed, 295 insertions(+), 29 deletions(-)
create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
create mode 100644 include/dt-bindings/gpio/x86-gpio.h
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..ea10963 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/x86-gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,x86-pinctrl;
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
new file mode 100644
index 000..45ab1af
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -0,0 +1,31 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on x86 can be described with a node for the PINCTRL master
+node and a set of child nodes for each pin on the SoC.
+
+The PINCTRL master node requires the following properties:
+- compatible : intel,x86-pinctrl
+
+Pin nodes must be children of the pinctrl master node and can
+contain the following properties:
+- pad-offset- (required) offset in the IOBASE for the pin to
configured.
+- gpio-offset - (required) offset in the GPIOBASE for the pin to
configured and
+ also the bit shift in this register.
+- mode-gpio- (optional) standalone property to force the
pin into GPIO mode.
+- mode-func- (optional) function number to assign to the
pin. if 'mode-gpio'
+ is set, this property will be ignored.
+in case of 'mode-gpio' property set:
+- output-value - (optional) this set the default output value of the
GPIO.
+- direction - (optional) this set the direction of the gpio.
+- pull-str - (optional) this set the pull strength of the pin.
+- pull-assign - (optional) this set the pull assignement (up/down) of
the pin.
+
+Example:
+
+pin_usb_host_en0@0 {
+gpio-offset = 0x80 8;
+pad-offset = 0x260;
+mode-gpio;
+output-value = 1;
+direction = PIN_OUTPUT;
+};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..c18c60f 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio
[U-Boot] [PATCH 4/4 v2] x86: minnowmax: initialize the pin-muxing from device tree
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Fix ordering of include header
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 6e82b16..0244d35 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include asm/gpio.h
#include asm/ibmpc.h
#include asm/pnp_def.h
#include netdev.h
@@ -14,6 +15,14 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 823e051..3c7b266 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_NR_DRAM_BANKS 1
--
2.1.4
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[U-Boot] [PATCH 2/4 v2] x86: minnowmax: add GPIO banks in the device tree
There are 6 banks:
4 banks for CORE: available in S0 mode
2 banks for SUS (Suspend): available in S0-S5 mode
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Fix typo in the commit message
arch/x86/dts/minnowmax.dts | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 8f34369..c73e421 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -21,6 +21,48 @@
silent_console = 0;
};
+ gpioa {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0 0x20;
+ bank-name = A;
+ };
+
+ gpiob {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x20 0x20;
+ bank-name = B;
+ };
+
+ gpioc {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x40 0x20;
+ bank-name = C;
+ };
+
+ gpiod {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x60 0x20;
+ bank-name = D;
+ };
+
+ gpioe {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x80 0x20;
+ bank-name = E;
+ };
+
+ gpiof {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0xA0 0x20;
+ bank-name = F;
+ };
+
chosen {
stdout-path = /serial;
};
--
2.1.4
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[U-Boot] [PATCH 1/4 v3] x86: baytrail: fix the GPIOBASE address
The correct GPIOBASE address on the baytrail is 0x48 Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Add a commit message Changes for v3: - Fix patch number arch/x86/include/asm/arch-baytrail/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..4e8987c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5 v2] x86: baytrail: fix the GPIOBASE address
The correct GPIOBASE address on the baytrail is 0x48 Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Add a commit message arch/x86/include/asm/arch-baytrail/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..4e8987c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Update the dts to put the correct flash name
arch/x86/dts/minnowmax.dts | 2 +-
include/configs/minnowmax.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 3936e21..dd20b2c 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -94,7 +94,7 @@
compatible = intel,ich;
spi-flash@0 {
reg = 0;
- compatible = sst,25vf016b, spi-flash;
+ compatible = stmicro,n25q064a, spi-flash;
memory-map = 0xff80 0x0080;
};
};
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
--
2.1.4
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[U-Boot] [PATCH v2] x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Update the dts to put the correct flash name
arch/x86/dts/minnowmax.dts | 2 +-
include/configs/minnowmax.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 3936e21..dd20b2c 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -94,7 +94,7 @@
compatible = intel,ich;
spi-flash@0 {
reg = 0;
- compatible = sst,25vf016b, spi-flash;
+ compatible = stmicro,n25q064a, spi-flash;
memory-map = 0xff80 0x0080;
};
};
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
--
2.1.4
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Re: [U-Boot] [PATCH v2] x86: minnowmax: use the correct NOR in the configuration
Hi,
Wrong command ... I sent a duplicate patch v2, you can ignore this one,
sorry.
Regards,
Gabriel
On 04/25/2015 08:19 AM, Gabriel Huau wrote:
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Update the dts to put the correct flash name
arch/x86/dts/minnowmax.dts | 2 +-
include/configs/minnowmax.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 3936e21..dd20b2c 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -94,7 +94,7 @@
compatible = intel,ich;
spi-flash@0 {
reg = 0;
- compatible = sst,25vf016b, spi-flash;
+ compatible = stmicro,n25q064a, spi-flash;
memory-map = 0xff80 0x0080;
};
};
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
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Re: [U-Boot] [PATCH] x86: minnowmax: use the correct NOR in the configuration
Hi Bin,
On 04/23/2015 08:20 PM, Bin Meng wrote:
Hi Gabriel,
On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
include/configs/minnowmax.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
--
I think you need also update minnowmax.dts file to change the compatible string.
Regards,
Bin
Well ... I didn't see that as the NOR was still working on the board, I
didn't find any reference except in the device tree for this compatible
string, do you know if this is really used or not?
I'll do the modification anyway, it's always better to put the correct
information.
Regards,
Gabriel
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Re: [U-Boot] [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
Hi Simon,
On 04/23/2015 08:35 PM, Simon Glass wrote:
Hi,
On 23 April 2015 at 10:16, Gabriel Huau cont...@huau-gabriel.fr wrote:
A set of properties has been defined for the device tree to select for
each pin the pull/func/default output configuration.
The offset for the PAD needs to be provided and if a GPIO needs to be
configured, his offset needs to be provided as well.
Here is an example:
pin_usb_host_en0@0 {
gpio-offset = 0x80 8;
pad-offset = 0x260;
mode-gpio;
output-value = 1;
direction = PIN_OUTPUT;
};
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts| 21 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h | 1 +
drivers/gpio/intel_ich6_gpio.c| 222 ++
include/dt-bindings/gpio/gpio.h | 20 +++
5 files changed, 239 insertions(+), 26 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..3936e21 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,ich6-pinctrl;
Make sure you use tabs for indenting here.
You should create a binding file to describe your binding - in
doc/device-tree-bindings.
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..a110d5b 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,32 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define GPIO_IOSEL_OFFSET(x) (x + 4)
+#define GPIO_LVL_OFFSET(x) (x + 8)
Comments on the above
+
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_MASK 0x3
+#define IOPAD_PULL_ASSIGN_SHIFT7
Can you make the mask value an actual valid mask, like:
+#define IOPAD_PULL_ASSIGN_MASK (0x3 IOPAD_PULL_ASSIGN_SHIFT)
+#define IOPAD_PULL_STRENGTH_MASK 0x3
+#define IOPAD_PULL_STRENGTH_SHIFT 9
+
+static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
Can you reorder the functions to avoid the need for these forward
declarations? Also only one underscore prefix please.
+static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir);
+static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int func);
+
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd-arch.gpio_map = map;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_get_base(unsigned long base)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u16 gpiobase;
- int offset;
/* Where should it be? */
pci_dev = PCI_BDF(0, 0x1f, 0);
@@ -123,9 +134,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
- tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
Can the base come
Re: [U-Boot] [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
On 04/23/2015 08:14 PM, Bin Meng wrote:
Hi Gabriel,
On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
A set of properties has been defined for the device tree to select for
each pin the pull/func/default output configuration.
The offset for the PAD needs to be provided and if a GPIO needs to be
configured, his offset needs to be provided as well.
Here is an example:
pin_usb_host_en0@0 {
gpio-offset = 0x80 8;
pad-offset = 0x260;
mode-gpio;
output-value = 1;
direction = PIN_OUTPUT;
};
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts| 21 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h | 1 +
drivers/gpio/intel_ich6_gpio.c| 222 ++
include/dt-bindings/gpio/gpio.h | 20 +++
5 files changed, 239 insertions(+), 26 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..3936e21 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,ich6-pinctrl;
I guess the prefix 'ich6' is debatable.
I hesitated with 'x86' but I'm open to any suggestion.
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..a110d5b 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,32 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define GPIO_IOSEL_OFFSET(x) (x + 4)
+#define GPIO_LVL_OFFSET(x) (x + 8)
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_MASK 0x3
+#define IOPAD_PULL_ASSIGN_SHIFT7
+#define IOPAD_PULL_STRENGTH_MASK 0x3
+#define IOPAD_PULL_STRENGTH_SHIFT 9
+
+static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
+static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir);
+static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int func);
+
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd-arch.gpio_map = map;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_get_base(unsigned long base)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u16 gpiobase;
- int offset;
/* Where should it be? */
pci_dev = PCI_BDF(0, 0x1f, 0);
@@ -123,9 +134,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
- tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
+ tmplong = x86_pci_read_config32(pci_dev, base);
if (tmplong == 0x || tmplong == 0x) {
- debug(%s: unexpected GPIOBASE value\n, __func__);
+ debug(%s: unexpected BASE value\n, __func__);
return -ENODEV;
}
@@ -135,7 +146,138 @@ static int
Re: [U-Boot] [PATCH 0/4] x86: support of pin-muxing from device tree
Hi Bin, On 04/23/2015 08:23 PM, Bin Meng wrote: Hi Gabriel, On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: This serie of patches adds the support of pin-muxing from the device tree through different properties. I have put two example to enable the USB Host on the minnowboard max. The support of the call to 'setup_pch_gpios' is still supported and only the minnowboard has been tested with the device tree implementation. Because the GPIO and IO base register ares different, I have also defined some proxy function to set the function/value and direction of the GPIO as the GPIO register can override some registers in the IO. Gabriel Huau (4): x86: baytrail: fix the GPIOBASE address x86: minnowmax: add GPIO banks in the device tree x86: gpio: add pinctrl support from the device tree x86: minnowmax: initialize the pin-muxing from device tree arch/x86/dts/minnowmax.dts| 63 + arch/x86/include/asm/arch-baytrail/gpio.h | 3 +- arch/x86/include/asm/gpio.h | 1 + board/intel/minnowmax/minnowmax.c | 9 ++ drivers/gpio/intel_ich6_gpio.c| 222 ++ include/configs/minnowmax.h | 1 + include/dt-bindings/gpio/gpio.h | 20 +++ 7 files changed, 292 insertions(+), 27 deletions(-) -- Thanks for these patches! Just a general comment, you don't need send emails to u-boot-patc...@bugs.denx.de, and always include a simple sentence in the commit message :) Regards, Bin That's why I received plenty of emails to tell me that my patches were not assigned :). I'll do the modification for the next version, thank you for the feedback, I appreciate this. Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] x86: baytrail: fix the GPIOBASE address
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/include/asm/arch-baytrail/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..4e8987c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] x86: support of pin-muxing from device tree
This serie of patches adds the support of pin-muxing from the device tree through different properties. I have put two example to enable the USB Host on the minnowboard max. The support of the call to 'setup_pch_gpios' is still supported and only the minnowboard has been tested with the device tree implementation. Because the GPIO and IO base register ares different, I have also defined some proxy function to set the function/value and direction of the GPIO as the GPIO register can override some registers in the IO. Gabriel Huau (4): x86: baytrail: fix the GPIOBASE address x86: minnowmax: add GPIO banks in the device tree x86: gpio: add pinctrl support from the device tree x86: minnowmax: initialize the pin-muxing from device tree arch/x86/dts/minnowmax.dts| 63 + arch/x86/include/asm/arch-baytrail/gpio.h | 3 +- arch/x86/include/asm/gpio.h | 1 + board/intel/minnowmax/minnowmax.c | 9 ++ drivers/gpio/intel_ich6_gpio.c| 222 ++ include/configs/minnowmax.h | 1 + include/dt-bindings/gpio/gpio.h | 20 +++ 7 files changed, 292 insertions(+), 27 deletions(-) -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] x86: minnowmax: add GPIO banks in the device tree
There is 6 banks:
4 banks for CORE: available in S0 mode
2 banks for SUS (Suspend): available in S0-S5 mode
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 8f34369..c73e421 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -21,6 +21,48 @@
silent_console = 0;
};
+ gpioa {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0 0x20;
+ bank-name = A;
+ };
+
+ gpiob {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x20 0x20;
+ bank-name = B;
+ };
+
+ gpioc {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x40 0x20;
+ bank-name = C;
+ };
+
+ gpiod {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x60 0x20;
+ bank-name = D;
+ };
+
+ gpioe {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x80 0x20;
+ bank-name = E;
+ };
+
+ gpiof {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0xA0 0x20;
+ bank-name = F;
+ };
+
chosen {
stdout-path = /serial;
};
--
2.1.4
___
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[U-Boot] [PATCH] x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
include/configs/minnowmax.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
--
2.1.4
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[U-Boot] [PATCH 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 6e82b16..60dd2bb 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -7,6 +7,7 @@
#include common.h
#include asm/ibmpc.h
#include asm/pnp_def.h
+#include asm/gpio.h
#include netdev.h
#include smsc_lpc47m.h
@@ -14,6 +15,14 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 823e051..3c7b266 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_NR_DRAM_BANKS 1
--
2.1.4
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[U-Boot] [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
A set of properties has been defined for the device tree to select for
each pin the pull/func/default output configuration.
The offset for the PAD needs to be provided and if a GPIO needs to be
configured, his offset needs to be provided as well.
Here is an example:
pin_usb_host_en0@0 {
gpio-offset = 0x80 8;
pad-offset = 0x260;
mode-gpio;
output-value = 1;
direction = PIN_OUTPUT;
};
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts| 21 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h | 1 +
drivers/gpio/intel_ich6_gpio.c| 222 ++
include/dt-bindings/gpio/gpio.h | 20 +++
5 files changed, 239 insertions(+), 26 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..3936e21 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,ich6-pinctrl;
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..a110d5b 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,32 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define GPIO_IOSEL_OFFSET(x) (x + 4)
+#define GPIO_LVL_OFFSET(x) (x + 8)
+
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_MASK 0x3
+#define IOPAD_PULL_ASSIGN_SHIFT7
+#define IOPAD_PULL_STRENGTH_MASK 0x3
+#define IOPAD_PULL_STRENGTH_SHIFT 9
+
+static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
+static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir);
+static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int func);
+
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd-arch.gpio_map = map;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_get_base(unsigned long base)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u16 gpiobase;
- int offset;
/* Where should it be? */
pci_dev = PCI_BDF(0, 0x1f, 0);
@@ -123,9 +134,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
- tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
+ tmplong = x86_pci_read_config32(pci_dev, base);
if (tmplong == 0x || tmplong == 0x) {
- debug(%s: unexpected GPIOBASE value\n, __func__);
+ debug(%s: unexpected BASE value\n, __func__);
return -ENODEV;
}
@@ -135,7 +146,138 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice
*dev)
* at the offset that we just read. Bit 0 indicates that it's
* an I/O address, not a memory address, so mask that off.
*/
- gpiobase = tmplong 0xfffe;
+ return tmplong 0xfffc;
+}
+
+int
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon, On 04/07/2015 07:03 PM, Simon Glass wrote: Hi Gabriel, On 6 April 2015 at 00:10, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Simon, On 04/05/2015 11:31 AM, Simon Glass wrote: Hi Gabriel, On 1 April 2015 at 05:20, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Simon, On 03/31/2015 07:32 PM, Simon Glass wrote: Hi Gabriel, On 27 February 2015 at 01:52, Bin Meng bmeng...@gmail.com wrote: Hi Gabriel, On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau cont...@huau-gabriel.fr wrote: Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. Yep, the offset should be 0x48 for BayTrail. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. I checked the gpio driver codes, and it currently has: /* * Okay, I guess we're looking at the right device. The actual * GPIO registers are in the PCI device's I/O space, starting * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ gpiobase = tmplong 0xfffe; This should be changed to gpiobase = tmplong 0xfffc; as bit1 is the enable bit on BayTrail (Intel changes this GPIO base register again for BayTrail, sigh...) Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. #endif /* __CONFIG_H */ -- What is the next step
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon, On 04/05/2015 11:31 AM, Simon Glass wrote: Hi Gabriel, On 1 April 2015 at 05:20, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Simon, On 03/31/2015 07:32 PM, Simon Glass wrote: Hi Gabriel, On 27 February 2015 at 01:52, Bin Meng bmeng...@gmail.com wrote: Hi Gabriel, On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau cont...@huau-gabriel.fr wrote: Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. Yep, the offset should be 0x48 for BayTrail. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. I checked the gpio driver codes, and it currently has: /* * Okay, I guess we're looking at the right device. The actual * GPIO registers are in the PCI device's I/O space, starting * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ gpiobase = tmplong 0xfffe; This should be changed to gpiobase = tmplong 0xfffc; as bit1 is the enable bit on BayTrail (Intel changes this GPIO base register again for BayTrail, sigh...) Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. #endif /* __CONFIG_H */ -- What is the next step with this patch please? It would be good to apply it to with the changes discussed. Sorry, actually I was super busy and wasn't able to work on the minnowboard max
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon, On 03/31/2015 07:32 PM, Simon Glass wrote: Hi Gabriel, On 27 February 2015 at 01:52, Bin Meng bmeng...@gmail.com wrote: Hi Gabriel, On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau cont...@huau-gabriel.fr wrote: Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. Yep, the offset should be 0x48 for BayTrail. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. I checked the gpio driver codes, and it currently has: /* * Okay, I guess we're looking at the right device. The actual * GPIO registers are in the PCI device's I/O space, starting * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ gpiobase = tmplong 0xfffe; This should be changed to gpiobase = tmplong 0xfffc; as bit1 is the enable bit on BayTrail (Intel changes this GPIO base register again for BayTrail, sigh...) Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. #endif /* __CONFIG_H */ -- What is the next step with this patch please? It would be good to apply it to with the changes discussed. Sorry, actually I was super busy and wasn't able to work on the minnowboard max ... I should have some time this week end. But you can go ahead and drop this patch, I will submit a new one because most of the modification are actually not needed, we
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. #endif /* __CONFIG_H */ -- Regards, Bin Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon,
With a little bit of delay here are the responses ... :)
On 02/17/2015 08:04 PM, Simon Glass wrote:
Hi Gabriel,
On 15 February 2015 at 14:55, Gabriel Huau cont...@huau-gabriel.fr wrote:
Configure the pinctrl as it required to make some IO controllers
working (USB/UART/I2C/...).
The idea would be in the next version to modify the pch GPIO driver and
configure these pins through the device tree.
These modifications are ported from the coreboot project.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
Thanks for the patch!
I have mostly nits except for one comment about register access which
is different in U-Boot...
I read all the comments and I agree on almost all of them but I have
some questions.
+
+ /* Add correct func to GPIO pad config */
+ pad_conf0 = config-pad_conf0;
+ if (config-is_gpio) {
+ if (gpio = bank-gpio_f1_range_start
+ gpio = bank-gpio_f1_range_end)
+ pad_conf0 |= PAD_FUNC1;
+ else
+ pad_conf0 |= PAD_FUNC0;
+ }
+
+ writel(reg + PAD_CONF0_REG, pad_conf0);
+ writel(reg + PAD_CONF1_REG, config-pad_conf1);
+ writel(reg + PAD_VAL_REG, config-pad_val);
+ }
+
+ if (bank-legacy_base != GP_LEGACY_BASE_NONE)
+ for (set = 0; set = (bank-gpio_count - 1) / 32; ++set) {
+ reg = bank-legacy_base + 0x20 * set;
+
+ outl(use_sel[set], reg + LEGACY_USE_SEL_REG);
+ outl(io_sel[set], reg + LEGACY_IO_SEL_REG);
+ outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG);
+ outl(tpe[set], reg + LEGACY_TPE_REG);
+ outl(tne[set], reg + LEGACY_TNE_REG);
+
+ /* TS registers are WOC */
If you know what this comment means, please spell it out without abbreviations.
Actually, I don't know the meaning of WOC and I couldn't find a
definition in the datasheet.
+ outl(0, reg + LEGACY_TS_REG);
+
+ if (bank-has_wake_en)
+ outl(wake_en[set], reg + LEGACY_WAKE_EN_REG);
+ }
+}
+
+static void setup_gpio_route(const struct byt_gpio_map *sus,
+ const struct byt_gpio_map *core)
+{
+ uint32_t route_reg = 0;
+ int i;
+
+ for (i = 0; i 8; i++) {
+ /* SMI takes precedence and wake_en implies SCI. */
+ if (sus[i].smi)
+ route_reg |= ROUTE_SMI (2 * i);
+ else if (sus[i].sci)
+ route_reg |= ROUTE_SCI (2 * i);
+
+ if (core[i].smi)
+ route_reg |= ROUTE_SMI (2 * (i + 8));
+ else if (core[i].sci)
+ route_reg |= ROUTE_SCI (2 * (i + 8));
+ }
What happens to route_reg after this? I don't see it get returned.
I will remove the code, actually it was used when the SMI was enabled.
+
+#define GPIO_LEVEL_LOW 0
+#define GPIO_LEVEL_HIGH1
+
+#define GPIO_PEDGE_DISABLE 0
+#define GPIO_PEDGE_ENABLE 1
+
+#define GPIO_NEDGE_DISABLE 0
+#define GPIO_NEDGE_ENABLE 1
+
+/* config0[29] - Disable second mask */
+#define PAD_MASK2_DISABLE (1 29)
+
+/* config0[27] - Direct Irq En */
+#define PAD_IRQ_EN (1 27)
+
+/* config0[26] - gd_tne */
+#define PAD_TNE_IRQ(1 26)
+
+/* config0[25] - gd_tpe */
+#define PAD_TPE_IRQ(1 25)
+
+/* config0[24] - Gd Level */
+#define PAD_LEVEL_IRQ (1 24)
+#define PAD_EDGE_IRQ (0 24)
+
+/* config0[17] - Slow clkgate / glitch filter */
+#define PAD_SLOWGF_ENABLE (1 17)
+
+/* config0[16] - Fast clkgate / glitch filter */
+#define PAD_FASTGF_ENABLE (1 16)
+
+/* config0[15] - Hysteresis enable (inverted) */
+#define PAD_HYST_DISABLE (1 15)
+#define PAD_HYST_ENABLE(0 15)
+
+/* config0[14:13] - Hysteresis control */
+#define PAD_HYST_CTRL_DEFAULT (2 13)
+
+/* config0[11] - Bypass Flop */
+#define PAD_FLOP_BYPASS(1 11)
+#define PAD_FLOP_ENABLE(0 11)
+
+/* config0[10:9] - Pull str */
+#define PAD_PU_2K (0 9)
+#define PAD_PU_10K (1 9)
+#define PAD_PU_20K (2 9)
+#define PAD_PU_40K (3 9)
+
+/* config0[8:7] - Pull assign */
+#define PAD_PULL_DISABLE (0 7)
+#define PAD_PULL_UP(1 7)
+#define PAD_PULL_DOWN (2 7)
+
+/* config0[2:0] - Func. pin mux */
+#define PAD_FUNC0 0x0
+#define PAD_FUNC1 0x1
+#define PAD_FUNC2 0x2
+#define PAD_FUNC3 0x3
+#define PAD_FUNC4 0x4
+#define PAD_FUNC5 0x5
+#define PAD_FUNC6 0x6
These could be an anonymous enum (optional)
For me, only the PAD_FUNCX could be part
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! #endif /* __CONFIG_H */ -- Regards, Bin Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Configure the pinctrl as it required to make some IO controllers
working (USB/UART/I2C/...).
The idea would be in the next version to modify the pch GPIO driver and
configure these pins through the device tree.
These modifications are ported from the coreboot project.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/cpu/baytrail/Makefile| 1 +
arch/x86/cpu/baytrail/gpio.c | 206 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++
arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++
arch/x86/include/asm/arch-baytrail/irq.h | 119 +
arch/x86/include/asm/arch-baytrail/irqroute.h | 67 +
arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++
arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++
board/intel/minnowmax/minnowmax.c | 212 +++
include/configs/minnowmax.h | 11 +
10 files changed, 1450 insertions(+)
create mode 100644 arch/x86/cpu/baytrail/gpio.c
create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h
create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h
create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h
create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h
create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
index 8914e8b..c20a616 100644
--- a/arch/x86/cpu/baytrail/Makefile
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -8,3 +8,4 @@ obj-y += early_uart.o
obj-y += fsp_configs.o
obj-y += pci.o
obj-y += valleyview.o
+obj-y += gpio.o
diff --git a/arch/x86/cpu/baytrail/gpio.c b/arch/x86/cpu/baytrail/gpio.c
new file mode 100644
index 000..0ad41cc
--- /dev/null
+++ b/arch/x86/cpu/baytrail/gpio.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include pci.h
+#include asm/arch/gpio.h
+#include asm/arch/irqroute.h
+#include asm/arch/pmc.h
+#include asm/gpio.h
+#include asm/io.h
+#include asm/pci.h
+
+/* GPIO-to-Pad LUTs */
+static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = {
+ 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
+ 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
+ 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
+ 2, 5, 9 /* [24:26] */
+};
+
+static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = {
+ 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
+ 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
+ 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
+ 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
+ 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
+ 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
+ 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
+ 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
+ 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
+ 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
+ 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
+ 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
+ 106, 87, 91, 104, 97, 100 /* [96:101] */
+};
+
+static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = {
+ 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
+ 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
+ 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
+ 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
+ 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
+ 52, 53, 59, 40 /* [40:43] */
+};
+
+/* GPIO bank descriptions */
+static const struct gpio_bank gpncore_bank = {
+ .gpio_count = GPNCORE_COUNT,
+ .gpio_to_pad = gpncore_gpio_to_pad,
+ .legacy_base = GP_LEGACY_BASE_NONE,
+ .pad_base = GPNCORE_PAD_BASE,
+ .has_wake_en = 0,
+ .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START,
+ .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END,
+};
+
+static const struct gpio_bank gpscore_bank = {
+ .gpio_count = GPSCORE_COUNT,
+ .gpio_to_pad = gpscore_gpio_to_pad,
+ .legacy_base = GPSCORE_LEGACY_BASE,
+ .pad_base = GPSCORE_PAD_BASE,
+ .has_wake_en = 0,
+ .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START,
+ .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END,
+};
+
+static const struct gpio_bank gpssus_bank = {
+ .gpio_count = GPSSUS_COUNT,
+ .gpio_to_pad = gpssus_gpio_to_pad,
+ .legacy_base = GPSSUS_LEGACY_BASE,
+ .pad_base = GPSSUS_PAD_BASE,
+ .has_wake_en = 1,
+ .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START,
+ .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END,
+};
+
+static void setup_gpios(const struct byt_gpio_map *gpios,
+ const struct gpio_bank *bank)
+{
+ const struct byt_gpio_map *config
Re: [U-Boot] x86: ACPI support suggestion
Hi Simon, On 02/06/2015 03:14 PM, Simon Glass wrote: Hi, On 6 February 2015 at 16:11, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Simon, On 02/06/2015 03:04 PM, Simon Glass wrote: Hi Gabriel, On 6 February 2015 at 16:01, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Bin, Actually I was able to try with a quickdirty code the integration of the ACPI tables (aml files) and it doesn't seem to be possible. The boot to Linux is working fine, all the ACPI tables are loaded correctly, but the system is unstable and it seems to have some issue with the interrupts handler. As debugging this kind of issues could be really tricky and involve also a lot of modification, I think we are stuck to port the ACPI support from coreboot to u-boot. I will try to work on a first draft and see how things look like. One thing to note is that U-Boot may not currently set up the PCI interrupts fully. Or perhaps the problem is that ACPI needs to match. What platform are you using? [snip] MinnowBoard Max (BayTrail). Actually, you may be right, I didn't check this part. Actually that uses an FSP so might already be correct, but it is certainly worth checking. I just checked the dmesg again and I didn't see that the first time: [0.723098] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15) *0, disabled. [0.732328] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 11 12 14 15) *0, disabled. [0.741551] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15) *0, disabled. [0.750782] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 11 12 14 15) *0, disabled. [0.760006] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15) *0, disabled. So I believe the PIRQ routing is missing in u-boot. I checked in the source of Coreboot, and actually everything is done in the southcluster initialization. Also, I saw that the GPIO iomap wasn't done and it appeared that the USB2 port wasn't powered up (the white one), enabling the port allow us to use of both port in the EHCI mode. I'll give a try to initialize the PIRQ and see how things is going. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] x86: ACPI support suggestion
Hi Bin, Actually I was able to try with a quickdirty code the integration of the ACPI tables (aml files) and it doesn't seem to be possible. The boot to Linux is working fine, all the ACPI tables are loaded correctly, but the system is unstable and it seems to have some issue with the interrupts handler. As debugging this kind of issues could be really tricky and involve also a lot of modification, I think we are stuck to port the ACPI support from coreboot to u-boot. I will try to work on a first draft and see how things look like. Regards, Gabriel On 02/06/2015 07:41 AM, Bin Meng wrote: Hi Gabriel, Thank you for taking the initiative for the U-Boot ACPI support. On Thu, Feb 5, 2015 at 3:52 AM, Simon Glass s...@chromium.org wrote: +Bin Hi Gabriel, On 4 February 2015 at 12:22, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi All, I'm currently thinking on how to integrate the ACPI support in u-boot x86. I've investigated the coreboot implementation. My first thought was to port all the source code over but looking at the source code in more details it doesn't look like an easy option. For example, it involves reading a lot of values over PCI to dynamically fill the tables, and integration a lot of SoC specific headers (IRQ definition, GPIO, ...). That doesn't sound nice. If we choose to implement generating ACPI tables by U-Boot, we have to do that unfortunately. We may port coreboot stuff and fix anything that is not good. Therefore, as a first implementation I was thinking about the following: - booting a board with the Intel UEFI + Linux - extracting all the ACPI tables (/sys/firmware/acpi/ or acpixtract) - disassembling the binaries tables via iasl to allow people to modify them - integrating these files into u-boot in board specific folder (for example: board/intel/minnowmax/acpi/*) - generating one blob per table using iasl during build time which requires iasl tool to be installed if we have the CONFIG_ACPI - writing at the RSDP location all the ACPI tables previously exported With this flow, the integration would be quite simple. Also this allows the tables to be modified easily when there is a new release or to add some new devices to the DSDT. What are your thoughts about that? Feel free to provide some feedback on this implementation. It seems reasonable to me. Bin may have some comments so I copied him. We have been using the device tree to statically define the hardware, so there is some duplication here. I would like to avoid actually using ACPI in U-Boot (device tree seems to do everything we need in a boot loader), but generating it make sense, and so long as it is source code, we can change it, as you say. This sounds a fast way to enable ACPI support. For the first implementation, I think it's enough. Let's see how it looks like. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] x86: ACPI support suggestion
Hi Simon, On 02/06/2015 03:04 PM, Simon Glass wrote: Hi Gabriel, On 6 February 2015 at 16:01, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Bin, Actually I was able to try with a quickdirty code the integration of the ACPI tables (aml files) and it doesn't seem to be possible. The boot to Linux is working fine, all the ACPI tables are loaded correctly, but the system is unstable and it seems to have some issue with the interrupts handler. As debugging this kind of issues could be really tricky and involve also a lot of modification, I think we are stuck to port the ACPI support from coreboot to u-boot. I will try to work on a first draft and see how things look like. One thing to note is that U-Boot may not currently set up the PCI interrupts fully. Or perhaps the problem is that ACPI needs to match. What platform are you using? [snip] MinnowBoard Max (BayTrail). Actually, you may be right, I didn't check this part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] x86: ACPI support suggestion
Hi All, I'm currently thinking on how to integrate the ACPI support in u-boot x86. I've investigated the coreboot implementation. My first thought was to port all the source code over but looking at the source code in more details it doesn't look like an easy option. For example, it involves reading a lot of values over PCI to dynamically fill the tables, and integration a lot of SoC specific headers (IRQ definition, GPIO, ...). Therefore, as a first implementation I was thinking about the following: - booting a board with the Intel UEFI + Linux - extracting all the ACPI tables (/sys/firmware/acpi/ or acpixtract) - disassembling the binaries tables via iasl to allow people to modify them - integrating these files into u-boot in board specific folder (for example: board/intel/minnowmax/acpi/*) - generating one blob per table using iasl during build time which requires iasl tool to be installed if we have the CONFIG_ACPI - writing at the RSDP location all the ACPI tables previously exported With this flow, the integration would be quite simple. Also this allows the tables to be modified easily when there is a new release or to add some new devices to the DSDT. What are your thoughts about that? Feel free to provide some feedback on this implementation. Thanks, Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] mx6: add support of multi-processor command
On 09/03/2014 11:36 AM, York Sun wrote: On 09/03/2014 11:26 AM, Gabriel Huau wrote: Hi York, On 09/03/2014 11:00 AM, York Sun wrote: On 07/28/2014 08:15 AM, Stefano Babic wrote: Hi Gabriel, On 26/07/2014 20:35, Gabriel Huau wrote: This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Add a commit log message to explain the purpose of this patch Changes for v3: - Remove unnecessary check for unsigned values when they are negative Changes for v4: - Add CONFIG_MP to the common mx6 configuration - Get the number of CPUs dynamically instead of using a macro Changes for v5: - Rebase on the last update of the tree (conflicts solved) Changes for v6: - Remove useless switch case - Update board_f to not depend on mp.h unnecessary - Fix build warnings - Update commit message snip --- a/common/board_f.c +++ b/common/board_f.c @@ -34,6 +34,9 @@ #ifdef CONFIG_MPC5xxx #include mpc5xxx.h #endif +#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#include asm/mp.h +#endif #include os.h #include post.h @@ -43,9 +46,6 @@ #include watchdog.h #include asm/errno.h #include asm/io.h -#ifdef CONFIG_MP -#include asm/mp.h -#endif #include asm/sections.h #ifdef CONFIG_X86 #include asm/init_helpers.h @@ -381,7 +381,7 @@ static int setup_dest_addr(void) gd-ram_top = board_get_usable_ram_top(gd-mon_len); gd-relocaddr = gd-ram_top; debug(Ram top: %08lX\n, (ulong)gd-ram_top); -#if defined(CONFIG_MP) (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) I didn't notice this patch until it got merged. Why dropping CONFIG_MP here? This change breaks these boards MPC8536DS MPC8536DS_36BIT MPC8536DS_SDCARD MPC8536DS_SPIFLASH qemu-ppce500 York Sorry, I didn't see the break for these boards. 'asm/mp.h' is used only for the powerpc board and using CONFIG_MP force the other architecture (or board) to create an empty header. As this header was here to use only specific features (not generic), I removed it and put the include guards only for the boards needed. Can't we add these boards to the board_f.c? I don't mind to change the guard for asm/mp.h. But you shouldn't remove the guard for the function call. Not all powerpc SoCs support SMP. You could use +#if defined(CONFIG_MP) (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#include asm/mp.h +#endif York Oh! I see what you mean, my bad, sorry. I'll propose the fix as soon as possible to revert the modification on the include guard and modify the one for the asm/mp.h Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] mx6: add support of multi-processor command
Hi York, On 09/03/2014 11:00 AM, York Sun wrote: On 07/28/2014 08:15 AM, Stefano Babic wrote: Hi Gabriel, On 26/07/2014 20:35, Gabriel Huau wrote: This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Add a commit log message to explain the purpose of this patch Changes for v3: - Remove unnecessary check for unsigned values when they are negative Changes for v4: - Add CONFIG_MP to the common mx6 configuration - Get the number of CPUs dynamically instead of using a macro Changes for v5: - Rebase on the last update of the tree (conflicts solved) Changes for v6: - Remove useless switch case - Update board_f to not depend on mp.h unnecessary - Fix build warnings - Update commit message snip --- a/common/board_f.c +++ b/common/board_f.c @@ -34,6 +34,9 @@ #ifdef CONFIG_MPC5xxx #include mpc5xxx.h #endif +#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#include asm/mp.h +#endif #include os.h #include post.h @@ -43,9 +46,6 @@ #include watchdog.h #include asm/errno.h #include asm/io.h -#ifdef CONFIG_MP -#include asm/mp.h -#endif #include asm/sections.h #ifdef CONFIG_X86 #include asm/init_helpers.h @@ -381,7 +381,7 @@ static int setup_dest_addr(void) gd-ram_top = board_get_usable_ram_top(gd-mon_len); gd-relocaddr = gd-ram_top; debug(Ram top: %08lX\n, (ulong)gd-ram_top); -#if defined(CONFIG_MP) (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) I didn't notice this patch until it got merged. Why dropping CONFIG_MP here? This change breaks these boards MPC8536DS MPC8536DS_36BIT MPC8536DS_SDCARD MPC8536DS_SPIFLASH qemu-ppce500 York Sorry, I didn't see the break for these boards. 'asm/mp.h' is used only for the powerpc board and using CONFIG_MP force the other architecture (or board) to create an empty header. As this header was here to use only specific features (not generic), I removed it and put the include guards only for the boards needed. Can't we add these boards to the board_f.c? Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] common: fix include guards for CONFIG_MP
This was breaking the build for some boards: MPC8536DS MPC8536DS_36BIT MPC8536DS_SDCARD MPC8536DS_SPIFLASH qemu-ppce500 Include only these features for some PPC boards if the configuration for MultiProcessor is enabled. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr Cc: Tom Rini tr...@ti.com Cc: York Sun york...@freescale.com --- common/board_f.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index 4ece2b6..deea9ca 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -34,7 +34,7 @@ #ifdef CONFIG_MPC5xxx #include mpc5xxx.h #endif -#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#if defined(CONFIG_MP) (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) #include asm/mp.h #endif @@ -392,7 +392,7 @@ static int setup_dest_addr(void) gd-ram_top = board_get_usable_ram_top(gd-mon_len); gd-relocaddr = gd-ram_top; debug(Ram top: %08lX\n, (ulong)gd-ram_top); -#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#if defined(CONFIG_MP) (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) /* * We need to make sure the location we intend to put secondary core * boot code is reserved and not used by any part of u-boot -- 2.0.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6] mx6: add support of multi-processor command
This allows u-boot to load different OS or Bare Metal application on
different cores of the i.MX6 SoC.
For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Add a commit log message to explain the purpose of this patch
Changes for v3:
- Remove unnecessary check for unsigned values when they are negative
Changes for v4:
- Add CONFIG_MP to the common mx6 configuration
- Get the number of CPUs dynamically instead of using a macro
Changes for v5:
- Rebase on the last update of the tree (conflicts solved)
Changes for v6:
- Remove useless switch case
- Update board_f to not depend on mp.h unnecessary
- Fix build warnings
- Update commit message
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/mp.c | 87 +++
arch/arm/cpu/armv7/mx6/soc.c | 6 +++
arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +
arch/arm/include/asm/arch-mx6/sys_proto.h | 1 +
common/board_f.c | 8 +--
include/configs/mx6_common.h | 2 +
7 files changed, 114 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/mx6/mp.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index 6dc9f8e..bf6effc 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -10,3 +10,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
+obj-$(CONFIG_MP) += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
new file mode 100644
index 000..9f034d6
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/mp.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/sys_proto.h
+#include asm/arch/imx-regs.h
+
+#define MAX_CPUS 4
+static struct src *src = (struct src *)SRC_BASE_ADDR;
+
+static uint32_t cpu_reset_mask[MAX_CPUS] = {
+ 0, /* We don't really want to modify the cpu0 */
+ SRC_SCR_CORE_1_RESET_MASK,
+ SRC_SCR_CORE_2_RESET_MASK,
+ SRC_SCR_CORE_3_RESET_MASK
+};
+
+static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
+ 0, /* We don't really want to modify the cpu0 */
+ SRC_SCR_CORE_1_ENABLE_MASK,
+ SRC_SCR_CORE_2_ENABLE_MASK,
+ SRC_SCR_CORE_3_ENABLE_MASK
+};
+
+int cpu_reset(int nr)
+{
+ /* Software reset of the CPU N */
+ src-scr |= cpu_reset_mask[nr];
+ return 0;
+}
+
+int cpu_status(int nr)
+{
+ printf(core %d = %d\n, nr, !!(src-scr cpu_ctrl_mask[nr]));
+ return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+ uint32_t boot_addr;
+
+ boot_addr = simple_strtoul(argv[0], NULL, 16);
+
+ switch (nr) {
+ case 1:
+ src-gpr3 = boot_addr;
+ break;
+ case 2:
+ src-gpr5 = boot_addr;
+ break;
+ case 3:
+ src-gpr7 = boot_addr;
+ break;
+ default:
+ return 1;
+ }
+
+ /* CPU N is ready to start */
+ src-scr |= cpu_ctrl_mask[nr];
+
+ return 0;
+}
+
+int is_core_valid(unsigned int core)
+{
+ uint32_t nr_cores = get_nr_cpus();
+
+ if (core nr_cores)
+ return 0;
+
+ return 1;
+}
+
+int cpu_disable(int nr)
+{
+ /* Disable the CPU N */
+ src-scr = ~cpu_ctrl_mask[nr];
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index f20bdeb..19429b2 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -35,6 +35,12 @@ struct scu_regs {
u32 fpga_rev;
};
+u32 get_nr_cpus(void)
+{
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ return readl(scu-config) 3;
+}
+
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index a69a753..a90cbe9 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -227,6 +227,19 @@
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+#define SRC_SCR_CORE_1_RESET_OFFSET 14
+#define SRC_SCR_CORE_1_RESET_MASK (1SRC_SCR_CORE_1_RESET_OFFSET)
+#define SRC_SCR_CORE_2_RESET_OFFSET 15
+#define SRC_SCR_CORE_2_RESET_MASK (1SRC_SCR_CORE_2_RESET_OFFSET)
+#define SRC_SCR_CORE_3_RESET_OFFSET 16
+#define SRC_SCR_CORE_3_RESET_MASK (1SRC_SCR_CORE_3_RESET_OFFSET)
+#define SRC_SCR_CORE_1_ENABLE_OFFSET22
+#define SRC_SCR_CORE_1_ENABLE_MASK (1SRC_SCR_CORE_1_ENABLE_OFFSET)
+#define
Re: [U-Boot] [PATCH v5] mx6: add support of multi-processor command
On 07/15/2014 12:49 AM, Stefano Babic wrote: Hi Gabriel, On 13/07/2014 00:31, Gabriel Huau wrote: This allows u-boot to load different OS or Bare Metal application on the different cores of the i.MX6DQ. For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Add a commit log message to explain the purpose of this patch Changes for v3: - Remove unnecessary check for unsigned values when they are negative Changes for v4: - Add CONFIG_MP to the common mx6 configuration - Get the number of CPUs dynamically instead of using a macro Changes for v5: - Rebase on the last update of the tree (conflicts solved) However, I get several warnings applying your patch: arch/arm/include/asm/arch/sys_proto.h:17:0: warning: is_soc_rev redefined [enabled by default] arch/arm/include/asm/arch/sys_proto.h:15:0: note: this is the location of the previous definition and: arch/arm/cpu/armv7/mx6/mp.c:101:2: warning: implicit declaration of function 'get_nr_cpus' [-Wimplicit-function-declaration] In file included from arch/arm/imx-common/cpu.c:15:0: You muxt fix them. My bad during the merge conflict, I'll fix that for the next version of the patch. - Add a dummy header to solve build issue regarding the common/board_f.c I do not think this is the best solution. An empty file is a file that is not needed. arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/mp.c | 134 ++ arch/arm/cpu/armv7/mx6/soc.c | 6 ++ arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++ arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + arch/arm/include/asm/mp.h | 11 +++ include/configs/mx6_common.h | 2 + 7 files changed, 168 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx6/mp.c create mode 100644 arch/arm/include/asm/mp.h I have just investigate a bit. The file is included by common/board_f.c but it is, frankly, quite not used. There are several prototype inside it: void setup_mp(void); void cpu_mp_lmb_reserve(struct lmb *lmb); int is_core_disabled(int nr); They are not used at all. u32 determine_mp_bootpg(unsigned int *pagesize); This is the only one that is used. Then it makes more sense to drop mp.h from board_f.c and add a prototype for determine_mp_bootpg(). This function is already protected by: #if defined(CONFIG_MP) (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) I agree adding an empty is not necessary the best solution, but I'd rather not to add any cpu/board specific defines in the common/ folder. That's why I think we should keep CONFIG_PM as this is a generic define. If necessary, I can propose another patch to fix it. Best regards, Stefano Babic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] mx6: add support of multi-processor command
Agreed, I misunderstood sorry. I'll do the modification for the next version of the patch. Thanks! Regards, Gabriel On 07/15/2014 12:35 PM, Stefano Babic wrote: Hi Gabriel, On 15/07/2014 16:13, gabriel huau wrote: I have just investigate a bit. The file is included by common/board_f.c but it is, frankly, quite not used. There are several prototype inside it: void setup_mp(void); void cpu_mp_lmb_reserve(struct lmb *lmb); int is_core_disabled(int nr); They are not used at all. u32 determine_mp_bootpg(unsigned int *pagesize); This is the only one that is used. Then it makes more sense to drop mp.h from board_f.c and add a prototype for determine_mp_bootpg(). This function is already protected by: #if defined(CONFIG_MP) (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) I agree adding an empty is not necessary the best solution, but I'd rather not to add any cpu/board specific defines in the common/ folder. That's why I think we should keep CONFIG_PM as this is a generic define. If necessary, I can propose another patch to fix it. I think we are saying the same thing. I agree letting CONFIG_MP, this is not the point. But prototype for determine_mp_bootg() can be moved in a powerpc include file and board_f does not need to include any mp.h Best regards, Stefano Babic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] mx6: add support of multi-processor command
Hi Wolfgang,
On 07/13/2014 02:58 AM, Wolfgang Denk wrote:
Dear Gabriel Huau,
In message 1405204264-10922-1-git-send-email-cont...@huau-gabriel.fr you
wrote:
This allows u-boot to load different OS or Bare Metal application on the
different cores of the i.MX6DQ.
For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
Has this patch really to be specific for the quad core version? Can
we not also support the dual core version in the same way?
...
Nope, but it makes sense for only Dual and Quad version. I'll update the
commit message to be more specific.
+int cpu_reset(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg |= SRC_SCR_CORE_1_RESET_MASK;
+ break;
+
+ case 2:
+ reg |= SRC_SCR_CORE_2_RESET_MASK;
+ break;
+
+ case 3:
+ reg |= SRC_SCR_CORE_3_RESET_MASK;
+ break;
+ }
I feel this should not be hardwired for 4 cores, and I also think we
should avoid using such a switch statement here. All you need is an
index into an array.
Agreed.
+int cpu_status(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ printf(core 1: %d\n, !!(reg SRC_SCR_CORE_1_ENABLE_MASK));
+ break;
+
+ case 2:
+ printf(core 2: %d\n, !!(reg SRC_SCR_CORE_2_ENABLE_MASK));
+ break;
+
+ case 3:
+ printf(core 3: %d\n, !!(reg SRC_SCR_CORE_3_ENABLE_MASK));
+ break;
+ }
Ditto. Such code duplication does not scale. Please rework to avoid
the switch.
+ switch (nr) {
+ case 1:
+ __raw_writel(boot_addr, src-gpr3);
+ reg |= SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ __raw_writel(boot_addr, src-gpr5);
+ reg |= SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ __raw_writel(boot_addr, src-gpr7);
+ reg |= SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* CPU N is ready to start */
+ __raw_writel(reg, src-scr);
Ditto here.
And can you please explain why you are using __raw_writel() here?
No particular reason, I'll update with the generic macro.
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg = ~SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ reg = ~SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ reg = ~SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* Disable the CPU N */
+ __raw_writel(reg, src-scr);
Again, please avoid the switch.
We have read-modify-write macros which you could use, unless you
really have to use the __raw_*() accessors. Why is this needed?
Best regards,
Wolfgang Denk
I'll send a version 6 with your correction.
Regards,
Gabriel
___
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[U-Boot] [PATCH v5] mx6: add support of multi-processor command
This allows u-boot to load different OS or Bare Metal application on the
different cores of the i.MX6DQ.
For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Add a commit log message to explain the purpose of this patch
Changes for v3:
- Remove unnecessary check for unsigned values when they are negative
Changes for v4:
- Add CONFIG_MP to the common mx6 configuration
- Get the number of CPUs dynamically instead of using a macro
Changes for v5:
- Rebase on the last update of the tree (conflicts solved)
- Add a dummy header to solve build issue regarding the common/board_f.c
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/mp.c | 134 ++
arch/arm/cpu/armv7/mx6/soc.c | 6 ++
arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++
arch/arm/include/asm/arch-mx6/sys_proto.h | 1 +
arch/arm/include/asm/mp.h | 11 +++
include/configs/mx6_common.h | 2 +
7 files changed, 168 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/mp.c
create mode 100644 arch/arm/include/asm/mp.h
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index 6dc9f8e..bf6effc 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -10,3 +10,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
+obj-$(CONFIG_MP) += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
new file mode 100644
index 000..85003d3
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/mp.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/sys_proto.h
+#include asm/arch/imx-regs.h
+
+int cpu_reset(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg |= SRC_SCR_CORE_1_RESET_MASK;
+ break;
+
+ case 2:
+ reg |= SRC_SCR_CORE_2_RESET_MASK;
+ break;
+
+ case 3:
+ reg |= SRC_SCR_CORE_3_RESET_MASK;
+ break;
+ }
+
+ /* Software reset of the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int cpu_status(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ printf(core 1: %d\n, !!(reg SRC_SCR_CORE_1_ENABLE_MASK));
+ break;
+
+ case 2:
+ printf(core 2: %d\n, !!(reg SRC_SCR_CORE_2_ENABLE_MASK));
+ break;
+
+ case 3:
+ printf(core 3: %d\n, !!(reg SRC_SCR_CORE_3_ENABLE_MASK));
+ break;
+ }
+
+ return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+ uint32_t boot_addr;
+
+ boot_addr = simple_strtoul(argv[0], NULL, 16);
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ __raw_writel(boot_addr, src-gpr3);
+ reg |= SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ __raw_writel(boot_addr, src-gpr5);
+ reg |= SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ __raw_writel(boot_addr, src-gpr7);
+ reg |= SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* CPU N is ready to start */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int is_core_valid(unsigned int core)
+{
+ uint32_t nr_cores = get_nr_cpus();
+
+ if (core nr_cores)
+ return 0;
+
+ return 1;
+}
+
+int cpu_disable(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg = ~SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ reg = ~SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ reg = ~SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* Disable the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index f20bdeb..19429b2 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -35,6 +35,12 @@ struct scu_regs {
u32 fpga_rev;
};
+u32 get_nr_cpus(void)
+{
+ struct
Re: [U-Boot] [PATCH v3] mx6: add support of multi-processor command
Hi Stefano,
On 06/24/2014 05:50 AM, Stefano Babic wrote:
Hi Gabriel,
On 22/06/2014 18:56, Gabriel Huau wrote:
This allows u-boot to load different OS or Bare Metal application on the
different cores of the i.MX6DQ.
For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Add a commit log message to explain the purpose of this patch
Changes for v3:
- Remove unnecessary check for unsigned values when they are negative
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/mp.c | 131 +++
arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++
3 files changed, 145 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/mp.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..ec08526 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -9,3 +9,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
+obj-$(CONFIG_MP) += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
Do you have a user of this code ? I do not see it at the mopment.
I didn't enable the configuration in the board file so it won't be
available by default, should I do it? or should we leave the user to add
this command in their board file?
new file mode 100644
index 000..8105fcc
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/mp.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/imx-regs.h
+
+int cpu_reset(int nr)
+{
As cpu__ are quite too generic and could conflict, I suggest to use more
specific names indicating that you are enabling/disabling a core on the
cpu. Something like imx_core_reset() or whatever you choose.
The name 'cpu_reset' is not really my choice, when you enable the
command MP you have to defines these functions (common/cmd_mp.c), I'm
open to any suggestion but anyway we will have to define these function
(except if I missed
something).
To avoid any conflict, I've defined them in the SoC code (they did the
same for PowerPC), so another SoC can define these functions without any
conflict.
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg |= SRC_SCR_CORE_1_RESET_MASK;
+ break;
+
+ case 2:
+ reg |= SRC_SCR_CORE_2_RESET_MASK;
+ break;
+
+ case 3:
+ reg |= SRC_SCR_CORE_3_RESET_MASK;
+ break;
+ }
+
+ /* Software reset of the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int cpu_status(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ printf(core 1: %d\n, !!(reg SRC_SCR_CORE_1_ENABLE_MASK));
+ break;
+
+ case 2:
+ printf(core 2: %d\n, !!(reg SRC_SCR_CORE_2_ENABLE_MASK));
+ break;
+
+ case 3:
+ printf(core 3: %d\n, !!(reg SRC_SCR_CORE_3_ENABLE_MASK));
+ break;
+ }
+
+ return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+ uint32_t boot_addr;
+
+ boot_addr = simple_strtoul(argv[0], NULL, 16);
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ __raw_writel(boot_addr, src-gpr3);
+ reg |= SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ __raw_writel(boot_addr, src-gpr5);
+ reg |= SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ __raw_writel(boot_addr, src-gpr7);
+ reg |= SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* CPU N is ready to start */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int is_core_valid(unsigned int nr)
+{
+ if (nr = CONFIG_NUM_CPUS)
And where is defined CONFIG_NUM_CPUS ?
Why do we have to configure it ? The number is related to the running
SOC and cannot be changed.
By default, I didn't enable the common MP for the mx6, but the
CONFIG_NUM_CPUS should be defined in the config file of the SoC (Quad =
4, Dual = 2, Solo = 1).
I think a better way will be to read directly the SCU registers to get
the current CPU configuration of the board, I'll update the patch.
+ return 0;
+
+ return 1;
+}
+
+int cpu_disable(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src
[U-Boot] [PATCH v4] mx6: add support of multi-processor command
This allows u-boot to load different OS or Bare Metal application on the
different cores of the i.MX6DQ.
For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Add a commit log message to explain the purpose of this patch
Changes for v3:
- Remove unnecessary check for unsigned values when they are negative
Changes for v4:
- Add CONFIG_MP to the common mx6 configuration
- Get the number of CPUs dynamically instead of using a macro
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/mp.c | 134 ++
arch/arm/cpu/armv7/mx6/soc.c | 6 ++
arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++
arch/arm/include/asm/arch-mx6/sys_proto.h | 2 +
include/configs/mx6_common.h | 2 +
6 files changed, 158 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/mp.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..ec08526 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -9,3 +9,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
+obj-$(CONFIG_MP) += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
new file mode 100644
index 000..85003d3
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/mp.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/sys_proto.h
+#include asm/arch/imx-regs.h
+
+int cpu_reset(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg |= SRC_SCR_CORE_1_RESET_MASK;
+ break;
+
+ case 2:
+ reg |= SRC_SCR_CORE_2_RESET_MASK;
+ break;
+
+ case 3:
+ reg |= SRC_SCR_CORE_3_RESET_MASK;
+ break;
+ }
+
+ /* Software reset of the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int cpu_status(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ printf(core 1: %d\n, !!(reg SRC_SCR_CORE_1_ENABLE_MASK));
+ break;
+
+ case 2:
+ printf(core 2: %d\n, !!(reg SRC_SCR_CORE_2_ENABLE_MASK));
+ break;
+
+ case 3:
+ printf(core 3: %d\n, !!(reg SRC_SCR_CORE_3_ENABLE_MASK));
+ break;
+ }
+
+ return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+ uint32_t boot_addr;
+
+ boot_addr = simple_strtoul(argv[0], NULL, 16);
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ __raw_writel(boot_addr, src-gpr3);
+ reg |= SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ __raw_writel(boot_addr, src-gpr5);
+ reg |= SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ __raw_writel(boot_addr, src-gpr7);
+ reg |= SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* CPU N is ready to start */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int is_core_valid(unsigned int core)
+{
+ uint32_t nr_cores = get_nr_cpus();
+
+ if (core nr_cores)
+ return 0;
+
+ return 1;
+}
+
+int cpu_disable(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg = ~SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ reg = ~SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ reg = ~SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* Disable the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 1725279..9a01b7e 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -35,6 +35,12 @@ struct scu_regs {
u32 fpga_rev;
};
+u32 get_nr_cpus(void)
+{
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ return readl(scu-config) 3;
+}
+
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 1f19727..3f8c2ee
Re: [U-Boot] [PATCH v2] mx6: add support of multi-processor command
Hi Nikolay, I agree that you have to modify those OS to support 'multi-OS' on different core but this customization is not part of u-boot in my sense. For the second point, I have to disagree, the imx6 is totally appropriate for AMP/multi-OS, in my case, I wasn't thinking about virtualization which is something different but really about multi-OS/Bare Metal application. The interrupt controller (GIC) can be configured to distribute any interrupt on any core, for example, you can have UART1 interrupt on core0 and UART2 interrupt on core1. The only problem is the resource partitioning but as I said this is another subject which is not really part of u-boot and I already did some test by running Android on core0 and QNX on core1 without any problem as a proof of concept. A good example may be the support on this kind of application on the Zynq: http://www.wiki.xilinx.com/Multi-OS+Support+%28AMP+%26+Hypervisor%29 This is also a Cortex A9 without the support of virtualization extensions. Regards, Gabriel On 06/22/2014 07:09 AM, Nikolay Dimitrov wrote: Hi Gabriel, This allows u-boot to load different OS or Bare Metal application on the different cores of the i.MX6DQ. For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. I think this explanation is a little misleading - if you run unmodified versions of Android some RTOS, they will fight for the imx6 interrupt controller, power management and clocks. As far as I know, imx6 is not appropriate for AMP (asymmetric multi-processing) because it doesn't support virtualization extensions. Kind regards, Nikolay ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mx6: add support of multi-processor command
Agreed, I'll submit a patch to fix that.
Regards,
Gabriel
On 06/22/2014 02:14 AM, Jeroen Hofstee wrote:
Hello Gabriel,
On 22-06-14 01:55, Gabriel Huau wrote:
This allows u-boot to load different OS or Bare Metal application on the
different cores of the i.MX6DQ.
For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS
on cpu1.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
funny..
+int is_core_valid(unsigned int nr)
+{
+if (nr 0 || nr = CONFIG_NUM_CPUS)
+return 0;
+
+return 1;
+}
+
I am not sure if u-boot has rules for it, but personally I would prefer
not to test values which are obvious unsigned for negativity, since it
causes unnecessary noise when compiling u-boot with W=1, W=2.
Regards,
Jeroen
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[U-Boot] [PATCH v3] mx6: add support of multi-processor command
This allows u-boot to load different OS or Bare Metal application on the
different cores of the i.MX6DQ.
For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Add a commit log message to explain the purpose of this patch
Changes for v3:
- Remove unnecessary check for unsigned values when they are negative
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/mp.c | 131 +++
arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++
3 files changed, 145 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/mp.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..ec08526 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -9,3 +9,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
+obj-$(CONFIG_MP) += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
new file mode 100644
index 000..8105fcc
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/mp.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/imx-regs.h
+
+int cpu_reset(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg |= SRC_SCR_CORE_1_RESET_MASK;
+ break;
+
+ case 2:
+ reg |= SRC_SCR_CORE_2_RESET_MASK;
+ break;
+
+ case 3:
+ reg |= SRC_SCR_CORE_3_RESET_MASK;
+ break;
+ }
+
+ /* Software reset of the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int cpu_status(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ printf(core 1: %d\n, !!(reg SRC_SCR_CORE_1_ENABLE_MASK));
+ break;
+
+ case 2:
+ printf(core 2: %d\n, !!(reg SRC_SCR_CORE_2_ENABLE_MASK));
+ break;
+
+ case 3:
+ printf(core 3: %d\n, !!(reg SRC_SCR_CORE_3_ENABLE_MASK));
+ break;
+ }
+
+ return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+ uint32_t boot_addr;
+
+ boot_addr = simple_strtoul(argv[0], NULL, 16);
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ __raw_writel(boot_addr, src-gpr3);
+ reg |= SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ __raw_writel(boot_addr, src-gpr5);
+ reg |= SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ __raw_writel(boot_addr, src-gpr7);
+ reg |= SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* CPU N is ready to start */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int is_core_valid(unsigned int nr)
+{
+ if (nr = CONFIG_NUM_CPUS)
+ return 0;
+
+ return 1;
+}
+
+int cpu_disable(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg = ~SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ reg = ~SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ reg = ~SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* Disable the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 1f19727..3f8c2ee 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -225,6 +225,19 @@
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+#define SRC_SCR_CORE_1_RESET_OFFSET 14
+#define SRC_SCR_CORE_1_RESET_MASK (1SRC_SCR_CORE_1_RESET_OFFSET)
+#define SRC_SCR_CORE_2_RESET_OFFSET 15
+#define SRC_SCR_CORE_2_RESET_MASK (1SRC_SCR_CORE_2_RESET_OFFSET)
+#define SRC_SCR_CORE_3_RESET_OFFSET 16
+#define SRC_SCR_CORE_3_RESET_MASK (1SRC_SCR_CORE_3_RESET_OFFSET)
+#define SRC_SCR_CORE_1_ENABLE_OFFSET22
+#define SRC_SCR_CORE_1_ENABLE_MASK (1SRC_SCR_CORE_1_ENABLE_OFFSET)
+#define SRC_SCR_CORE_2_ENABLE_OFFSET23
+#define SRC_SCR_CORE_2_ENABLE_MASK (1SRC_SCR_CORE_2_ENABLE_OFFSET)
+#define SRC_SCR_CORE_3_ENABLE_OFFSET24
+#define
[U-Boot] [PATCH] mx6: add support of multi-processor command
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/mp.c | 131 +++
arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++
3 files changed, 145 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/mp.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..ec08526 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -9,3 +9,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
+obj-$(CONFIG_MP) += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
new file mode 100644
index 000..a805be8
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/mp.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/imx-regs.h
+
+int cpu_reset(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg |= SRC_SCR_CORE_1_RESET_MASK;
+ break;
+
+ case 2:
+ reg |= SRC_SCR_CORE_2_RESET_MASK;
+ break;
+
+ case 3:
+ reg |= SRC_SCR_CORE_3_RESET_MASK;
+ break;
+ }
+
+ /* Software reset of the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int cpu_status(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ printf(core 1: %d\n, !!(reg SRC_SCR_CORE_1_ENABLE_MASK));
+ break;
+
+ case 2:
+ printf(core 2: %d\n, !!(reg SRC_SCR_CORE_2_ENABLE_MASK));
+ break;
+
+ case 3:
+ printf(core 3: %d\n, !!(reg SRC_SCR_CORE_3_ENABLE_MASK));
+ break;
+ }
+
+ return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+ uint32_t boot_addr;
+
+ boot_addr = simple_strtoul(argv[0], NULL, 16);
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ __raw_writel(boot_addr, src-gpr3);
+ reg |= SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ __raw_writel(boot_addr, src-gpr5);
+ reg |= SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ __raw_writel(boot_addr, src-gpr7);
+ reg |= SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* CPU N is ready to start */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int is_core_valid(unsigned int nr)
+{
+ if (nr 0 || nr = CONFIG_NUM_CPUS)
+ return 0;
+
+ return 1;
+}
+
+int cpu_disable(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg = ~SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ reg = ~SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ reg = ~SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* Disable the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 1f19727..3f8c2ee 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -225,6 +225,19 @@
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+#define SRC_SCR_CORE_1_RESET_OFFSET 14
+#define SRC_SCR_CORE_1_RESET_MASK (1SRC_SCR_CORE_1_RESET_OFFSET)
+#define SRC_SCR_CORE_2_RESET_OFFSET 15
+#define SRC_SCR_CORE_2_RESET_MASK (1SRC_SCR_CORE_2_RESET_OFFSET)
+#define SRC_SCR_CORE_3_RESET_OFFSET 16
+#define SRC_SCR_CORE_3_RESET_MASK (1SRC_SCR_CORE_3_RESET_OFFSET)
+#define SRC_SCR_CORE_1_ENABLE_OFFSET22
+#define SRC_SCR_CORE_1_ENABLE_MASK (1SRC_SCR_CORE_1_ENABLE_OFFSET)
+#define SRC_SCR_CORE_2_ENABLE_OFFSET23
+#define SRC_SCR_CORE_2_ENABLE_MASK (1SRC_SCR_CORE_2_ENABLE_OFFSET)
+#define SRC_SCR_CORE_3_ENABLE_OFFSET24
+#define SRC_SCR_CORE_3_ENABLE_MASK (1SRC_SCR_CORE_3_ENABLE_OFFSET)
+
/* System Reset Controller (SRC) */
struct src {
u32 scr;
--
2.0.0.rc2
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[U-Boot] [PATCH v2] mx6: add support of multi-processor command
This allows u-boot to load different OS or Bare Metal application on the
different cores of the i.MX6DQ.
For example: we can run Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/mp.c | 131 +++
arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++
3 files changed, 145 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/mp.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..ec08526 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -9,3 +9,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
+obj-$(CONFIG_MP) += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
new file mode 100644
index 000..a805be8
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/mp.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/imx-regs.h
+
+int cpu_reset(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg |= SRC_SCR_CORE_1_RESET_MASK;
+ break;
+
+ case 2:
+ reg |= SRC_SCR_CORE_2_RESET_MASK;
+ break;
+
+ case 3:
+ reg |= SRC_SCR_CORE_3_RESET_MASK;
+ break;
+ }
+
+ /* Software reset of the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int cpu_status(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ printf(core 1: %d\n, !!(reg SRC_SCR_CORE_1_ENABLE_MASK));
+ break;
+
+ case 2:
+ printf(core 2: %d\n, !!(reg SRC_SCR_CORE_2_ENABLE_MASK));
+ break;
+
+ case 3:
+ printf(core 3: %d\n, !!(reg SRC_SCR_CORE_3_ENABLE_MASK));
+ break;
+ }
+
+ return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+ uint32_t boot_addr;
+
+ boot_addr = simple_strtoul(argv[0], NULL, 16);
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ __raw_writel(boot_addr, src-gpr3);
+ reg |= SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ __raw_writel(boot_addr, src-gpr5);
+ reg |= SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ __raw_writel(boot_addr, src-gpr7);
+ reg |= SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* CPU N is ready to start */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
+
+int is_core_valid(unsigned int nr)
+{
+ if (nr 0 || nr = CONFIG_NUM_CPUS)
+ return 0;
+
+ return 1;
+}
+
+int cpu_disable(int nr)
+{
+ uint32_t reg;
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ reg = __raw_readl(src-scr);
+
+ switch (nr) {
+ case 1:
+ reg = ~SRC_SCR_CORE_1_ENABLE_MASK;
+ break;
+
+ case 2:
+ reg = ~SRC_SCR_CORE_2_ENABLE_MASK;
+ break;
+
+ case 3:
+ reg = ~SRC_SCR_CORE_3_ENABLE_MASK;
+ break;
+ }
+
+ /* Disable the CPU N */
+ __raw_writel(reg, src-scr);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 1f19727..3f8c2ee 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -225,6 +225,19 @@
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+#define SRC_SCR_CORE_1_RESET_OFFSET 14
+#define SRC_SCR_CORE_1_RESET_MASK (1SRC_SCR_CORE_1_RESET_OFFSET)
+#define SRC_SCR_CORE_2_RESET_OFFSET 15
+#define SRC_SCR_CORE_2_RESET_MASK (1SRC_SCR_CORE_2_RESET_OFFSET)
+#define SRC_SCR_CORE_3_RESET_OFFSET 16
+#define SRC_SCR_CORE_3_RESET_MASK (1SRC_SCR_CORE_3_RESET_OFFSET)
+#define SRC_SCR_CORE_1_ENABLE_OFFSET22
+#define SRC_SCR_CORE_1_ENABLE_MASK (1SRC_SCR_CORE_1_ENABLE_OFFSET)
+#define SRC_SCR_CORE_2_ENABLE_OFFSET23
+#define SRC_SCR_CORE_2_ENABLE_MASK (1SRC_SCR_CORE_2_ENABLE_OFFSET)
+#define SRC_SCR_CORE_3_ENABLE_OFFSET24
+#define SRC_SCR_CORE_3_ENABLE_MASK (1SRC_SCR_CORE_3_ENABLE_OFFSET)
+
/* System Reset Controller (SRC) */
struct src {
u32 scr;
--
2.0.0
[U-Boot] ARM : Removing unwind dummy functions
Hi, I would like to know if it's really necessary to keep the dummy functions in arch/arm/lib/eabi_compat.c. These function should not be happen in our case (that why the body is empty). They have been introduced due to problems with some toolchains that was referencing these functions. But we can avoid this hack by adding the option '-fno-unwind-tables' at the compilation time no ? (correct me if I'm wrong). Best regards, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
Hi, I sent patches v5 and v10 and I have no more review since a few weeks, so I think it's ok now, no ? About the comment/definitions, it has been fixed in last patches :). Best regards, On Mon, May 21, 2012 at 11:55:10PM +0200, Wolfgang Denk wrote: Dear Gabriel Huau, In message 20120521203733.GC9379@debian you wrote: Is it ok ? Can we apply theses patches ? What do you mean - unfixed? On Sun, Apr 29, 2012 at 11:27:23PM +0200, Gabriel Huau wrote: From the last time, I removed the patch about the PLL initialization because it's board specific. I added a new patch for s3c440 gpio driver. Now in the board file we have no more magic bloat. +/* + * When booting from NAND, it is impossible to access the lowest addresses + * due to the SteppingStone being in the way. Luckily the NOR doesn't really + * care about the highest 16 bits of address, so we set the controlers + * registers to go and poke over there, instead. + */ +#define PHYS_FLASH_1 0x0 +#define CONFIG_SYS_FLASH_BASE0x0 Urghh... this sounds very much like a serious design issue? About this point, I ported it from the old version uboot as well. It may need some investigation, but I remember it was a big problem with this board. In the case of a NAND boot, we don't have access to NOR because the SteppingStone (SRAM) is mapped at the same range. The comment and/or definitions are apparently broken, so they should be fixed / removed. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I will not say that women have no character; rather, they have a new one every day. -- Heine ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
Is it ok ? Can we apply theses patches ? On Sun, Apr 29, 2012 at 11:27:23PM +0200, Gabriel Huau wrote: From the last time, I removed the patch about the PLL initialization because it's board specific. I added a new patch for s3c440 gpio driver. Now in the board file we have no more magic bloat. +/* + * When booting from NAND, it is impossible to access the lowest addresses + * due to the SteppingStone being in the way. Luckily the NOR doesn't really + * care about the highest 16 bits of address, so we set the controlers + * registers to go and poke over there, instead. + */ +#define PHYS_FLASH_1 0x0 +#define CONFIG_SYS_FLASH_BASE0x0 Urghh... this sounds very much like a serious design issue? About this point, I ported it from the old version uboot as well. It may need some investigation, but I remember it was a big problem with this board. In the case of a NAND boot, we don't have access to NOR because the SteppingStone (SRAM) is mapped at the same range. Gabriel Huau (2): Add GPIO Driver and IOMUX definition for S3C2440 Add support for MINI2440 (s3c2440). MAINTAINERS |4 + arch/arm/include/asm/arch-s3c24x0/gpio.h | 183 + arch/arm/include/asm/arch-s3c24x0/iomux.h | 197 +++ board/friendlyarm/mini2440/Makefile | 44 ++ board/friendlyarm/mini2440/mini2440.c | 135 +++ board/friendlyarm/mini2440/mini2440.h | 144 boards.cfg|1 + doc/README.mini2440 | 28 drivers/gpio/Makefile |1 + drivers/gpio/s3c2440_gpio.c | 74 ++ include/configs/mini2440.h| 209 + 11 files changed, 1020 insertions(+) create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 drivers/gpio/s3c2440_gpio.c create mode 100644 include/configs/mini2440.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
On Wed, May 02, 2012 at 01:40:35PM -0500, Scott Wood wrote:
On 05/02/2012 01:16 AM, Minkyu Kang wrote:
Dear Marek,
On 2 May 2012 11:44, Marek Vasut ma...@denx.de wrote:
+int gpio_set_value(unsigned gpio, int value)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+ unsigned port = GPIO_FULLPORT(gpio);
+
+ /*
+* All GPIO Port have a configuration on
+* 2 bits excepted the first GPIO (A) which
+* have only 1 bit of configuration.
+*/
+ if (value)
+ if (!GPIO_PORT(gpio))
+ l |= (0x1 GPIO_BIT(gpio));
+ else
+ l |= (0x3 GPIO_BIT(gpio));
+ else
+ if (!GPIO_PORT(gpio))
+ l = ~(0x1 GPIO_BIT(gpio));
+ else
+ l = ~(0x3 GPIO_BIT(gpio));
Need brace at this if..else statement.
I wanted to ask why, but ... C isn't python, good point ;-)
As I know, it's a rule of u-boot.. maybe. :)
It is a U-Boot rule (multi-line if/loop body), and also it's good to
avoid the ambiguous if/if/else construct, but wouldn't this be better as:
if (GPIO_PORT(gpio))
bit = 1 GPIO_BIT(gpio);
else
bit = 3 GPIO_BIT(gpio);
if (value)
l |= bit;
else
l = ~bit;
?
For multi-line, we should maybe patch the checkpatch.pl to check this
statement. But, indeed, I will do the modification of Scott.
-Scott
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[U-Boot] [PATCH 2/2 v10] ARM : Add support for MINI2440 (s3c2440).
Support of the MINI2440 board from FriendlyARM from an old version of u-boot : http://repo.or.cz/r/u-boot-openmoko/mini2440.git Currently, supporting only boot from NOR. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some magic bloat with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright Changes for v4: - Move dram init to dram_init() instead low_levelinit - Remove u -boot env from configuration file and change the address of initial SP - Remove PLL init, now it's SoC specific Changes for v5: - Clean up configuration file - Add a MAINTAINERS entry - Add a README.mini2440 file - Use gpio/iomux interface in case of magic numbers - Use get_ram_size() Changes for v6: - Coding style cleanup - Remove some unused define in the board config Changes for v7: - Cleanup coding style - Changement of the commit message Changes for v8: - Replace define[tab] by define[space] Changes for v9: - Add a nice commit message Changes for v10: - Sort the MAINTAINERS file MAINTAINERS |4 + board/friendlyarm/mini2440/Makefile | 44 board/friendlyarm/mini2440/mini2440.c | 134 board/friendlyarm/mini2440/mini2440.h | 144 + boards.cfg|1 + doc/README.mini2440 | 28 + include/configs/mini2440.h| 186 + 7 files changed, 541 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 include/configs/mini2440.h diff --git a/MAINTAINERS b/MAINTAINERS index 708ded7..c31ae6f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -677,6 +677,10 @@ Vaibhav Hiremath hvaib...@ti.com am3517_evm ARM ARMV7 (AM35x SoC) +Gabriel Huau cont...@huau-gabriel.fr + + mini2440s3c2440 + Grazvydas Ignotas nota...@gmail.com omap3_pandora ARM ARMV7 (OMAP3xx SoC) diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 000..b88e569 --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := mini2440.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 000..e97d981 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Marius Groeger mgroe...@sysgo.de + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * + * (C) Copyright 2009 + * Michel Pollet buser...@gmail.com + * + * (C) Copyright 2012 + * Gabriel Huau cont...@huau-gabriel.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute
[U-Boot] [PATCH 1/2 v2] Add GPIO Driver and IOMUX definition for S3C2440
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Modification of the coding style
- Add my email address to copyright
- Remove a typedef
- Move some defines to driver file
---
arch/arm/include/asm/arch-s3c24x0/gpio.h | 171
arch/arm/include/asm/arch-s3c24x0/iomux.h | 200 +
drivers/gpio/Makefile |1 +
drivers/gpio/s3c2440_gpio.c | 94 ++
4 files changed, 466 insertions(+)
create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
create mode 100644 drivers/gpio/s3c2440_gpio.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h
b/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 000..baac14c
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+typedef enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+} s3c2240_gpio;
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h
b/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 000..cc4d6b3
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307
Re: [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440
On Mon, Apr 30, 2012 at 01:29:37AM +0200, Marek Vasut wrote: Dear Gabriel Huau, Commit message got lost ? :p It's strange, I have the commit message in my log, but when I format-patch, The commit message is set only in the subject, not in the body. Any idea ? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
Hi, Just a little question about the ChangeLog. I added the --- and my changements after it, but I see this part in git log, is it normal ? Will this part be deleted in the merge ? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2 v6] Add support for MINI2440 (s3c2440).
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some magic bloat with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright Changes for v4: - Move dram init to dram_init() instead low_levelinit - Remove u-boot env from configuration file and change the address of initial SP - Remove PLL init, now it's SoC specific Changes for v5: - Clean up configuration file - Add a MAINTAINERS entry - Add a README.mini2440 file - Use gpio/iomux interface in case of magic numbers - Use get_ram_size() Changes for v6: - Coding style cleanup - Remove some unused define in the board config --- MAINTAINERS |4 + board/friendlyarm/mini2440/Makefile | 44 board/friendlyarm/mini2440/mini2440.c | 132 +++ board/friendlyarm/mini2440/mini2440.h | 144 + boards.cfg|1 + doc/README.mini2440 | 28 + include/configs/mini2440.h| 186 + 7 files changed, 539 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 include/configs/mini2440.h diff --git a/MAINTAINERS b/MAINTAINERS index 708ded7..2611fb5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,10 @@ Unknown / orphaned boards: # Board CPU # # +Gabriel HUAU cont...@huau-gabriel.fr + + mini2440s3c2440 + Albert ARIBAUD albert.u.b...@aribaud.net edminiv2ARM926EJS (Orion5x SoC) diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 000..b88e569 --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := mini2440.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 000..bd726e7 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Marius Groeger mgroe...@sysgo.de + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * + * (C) Copyright 2009 + * Michel Pollet buser...@gmail.com + * + * (C) Copyright 2012 + * Gabriel Huau cont...@huau-gabriel.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty
Re: [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
On Mon, Apr 30, 2012 at 01:35:01PM +0200, Wolfgang Denk wrote: Dear Gabriel Huau, In message 20120430110724.GB4656@debian you wrote: Just a little question about the ChangeLog. I added the --- and my changements after it, but I see this part in git log, is it normal ? Will this part be deleted in the merge ? You should never see this in a git log. The --- separator line gets automatically inserted by git format-patch; you add your comments manually after creating the patch by inserting them below this line. git am will then ignore this line and everything below it. So if you can see this as part of the commit message, something went wrong. Ok thanks, I misunderstood, I will modify this error after the next review. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Modification of the coding style
- Add my email address to copyright
- Remove a typedef
- Move some defines to driver file
Changes for v3:
- Cleanup coding style
- Changement of the commit message
arch/arm/include/asm/arch-s3c24x0/gpio.h | 171
arch/arm/include/asm/arch-s3c24x0/iomux.h | 200 +
drivers/gpio/Makefile |1 +
drivers/gpio/s3c2440_gpio.c | 94 ++
4 files changed, 466 insertions(+)
create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
create mode 100644 drivers/gpio/s3c2440_gpio.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h
b/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 000..76bc52c
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h
b/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 000..cc22de7
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
[U-Boot] [PATCH 2/2 v7] Add support for MINI2440 (s3c2440).
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some magic bloat with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright Changes for v4: - Move dram init to dram_init() instead low_levelinit - Remove u -boot env from configuration file and change the address of initial SP - Remove PLL init, now it's SoC specific Changes for v5: - Clean up configuration file - Add a MAINTAINERS entry - Add a README.mini2440 file - Use gpio/iomux interface in case of magic numbers - Use get_ram_size() Changes for v6: - Coding style cleanup - Remove some unused define in the board config Changes for v7: - Cleanup coding style - Changement of the commit message MAINTAINERS |4 + board/friendlyarm/mini2440/Makefile | 44 board/friendlyarm/mini2440/mini2440.c | 134 board/friendlyarm/mini2440/mini2440.h | 144 + boards.cfg|1 + doc/README.mini2440 | 28 + include/configs/mini2440.h| 186 + 7 files changed, 541 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 include/configs/mini2440.h diff --git a/MAINTAINERS b/MAINTAINERS index 708ded7..2611fb5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,10 @@ Unknown / orphaned boards: # Board CPU # # +Gabriel HUAU cont...@huau-gabriel.fr + + mini2440s3c2440 + Albert ARIBAUD albert.u.b...@aribaud.net edminiv2ARM926EJS (Orion5x SoC) diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 000..b88e569 --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := mini2440.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 000..e97d981 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Marius Groeger mgroe...@sysgo.de + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * + * (C) Copyright 2009 + * Michel Pollet buser...@gmail.com + * + * (C) Copyright 2012 + * Gabriel Huau cont...@huau-gabriel.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope
Re: [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440
On Mon, Apr 30, 2012 at 02:25:20PM +0200, Marek Vasut wrote: Dear Gabriel Huau, On Mon, Apr 30, 2012 at 01:29:37AM +0200, Marek Vasut wrote: Dear Gabriel Huau, Commit message got lost ? :p It's strange, I have the commit message in my log, but when I format-patch, The commit message is set only in the subject, not in the body. Are you sure you sent the correct patch ? ;-) Yeap, I just did some tests, it seems that the commit message in the body text is only from line 2. The line 1 is in the subject :) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440
On Mon, Apr 30, 2012 at 03:20:42PM +0200, Marek Vasut wrote: Dear Gabriel Huau, Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Modification of the coding style - Add my email address to copyright - Remove a typedef - Move some defines to driver file Changes for v3: - Cleanup coding style - Changement of the commit message There is no commit message here ;-) As I explained in another mail, Only the second line of the commit message in the text body :) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2 v7] Add support for MINI2440 (s3c2440).
On Mon, Apr 30, 2012 at 03:21:49PM +0200, Marek Vasut wrote: Dear Gabriel Huau, + +/* + * Miscellaneous configurable options + */ +#defineCONFIG_LONGHELP +#defineCONFIG_SYS_PROMPT MINI2440 = +#defineCONFIG_SYS_CBSIZE 256 +#defineCONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#defineCONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE #define[tab] mixed with #define[space] ... also, please Cc Albert Aribaud for the next round, he'll likely pick this up. You gonna to kill me ... :P. checkpatch.pl didn't see this obfuscation ;). ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2 v8] Add support for MINI2440 (s3c2440).
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some magic bloat with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright Changes for v4: - Move dram init to dram_init() instead low_levelinit - Remove u -boot env from configuration file and change the address of initial SP - Remove PLL init, now it's SoC specific Changes for v5: - Clean up configuration file - Add a MAINTAINERS entry - Add a README.mini2440 file - Use gpio/iomux interface in case of magic numbers - Use get_ram_size() Changes for v6: - Coding style cleanup - Remove some unused define in the board config Changes for v7: - Cleanup coding style - Changement of the commit message Changes for v8: - Replace define[tab] by define[space] MAINTAINERS |4 + board/friendlyarm/mini2440/Makefile | 44 board/friendlyarm/mini2440/mini2440.c | 134 board/friendlyarm/mini2440/mini2440.h | 144 + boards.cfg|1 + doc/README.mini2440 | 28 + include/configs/mini2440.h| 186 + 7 files changed, 541 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 include/configs/mini2440.h diff --git a/MAINTAINERS b/MAINTAINERS index 708ded7..2611fb5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,10 @@ Unknown / orphaned boards: # Board CPU # # +Gabriel HUAU cont...@huau-gabriel.fr + + mini2440s3c2440 + Albert ARIBAUD albert.u.b...@aribaud.net edminiv2ARM926EJS (Orion5x SoC) diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 000..b88e569 --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := mini2440.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 000..e97d981 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Marius Groeger mgroe...@sysgo.de + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * + * (C) Copyright 2009 + * Michel Pollet buser...@gmail.com + * + * (C) Copyright 2012 + * Gabriel Huau cont...@huau-gabriel.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later
[U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
It's now possible to use the gpio driver interface
for s3c2440. This patch add iomux definitions too.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Modification of the coding style
- Add my email address to copyright
- Remove a typedef
- Move some defines to driver file
Changes for v3:
- Cleanup coding style
- Changement of the commit message
Changes for v4:
- Add a nice commit message
arch/arm/include/asm/arch-s3c24x0/gpio.h | 171
arch/arm/include/asm/arch-s3c24x0/iomux.h | 200 +
drivers/gpio/Makefile |1 +
drivers/gpio/s3c2440_gpio.c | 94 ++
4 files changed, 466 insertions(+)
create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
create mode 100644 drivers/gpio/s3c2440_gpio.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h
b/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 000..76bc52c
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h
b/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 000..cc22de7
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more
[U-Boot] [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440).
Support of the MINI2440 board from FriendlyARM from an old version of u-boot : http://repo.or.cz/r/u-boot-openmoko/mini2440.git Currently, supporting only boot from NOR. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some magic bloat with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright Changes for v4: - Move dram init to dram_init() instead low_levelinit - Remove u -boot env from configuration file and change the address of initial SP - Remove PLL init, now it's SoC specific Changes for v5: - Clean up configuration file - Add a MAINTAINERS entry - Add a README.mini2440 file - Use gpio/iomux interface in case of magic numbers - Use get_ram_size() Changes for v6: - Coding style cleanup - Remove some unused define in the board config Changes for v7: - Cleanup coding style - Changement of the commit message Changes for v8: - Replace define[tab] by define[space] Changes for v9: - Add a nice commit message MAINTAINERS |4 + board/friendlyarm/mini2440/Makefile | 44 board/friendlyarm/mini2440/mini2440.c | 134 board/friendlyarm/mini2440/mini2440.h | 144 + boards.cfg|1 + doc/README.mini2440 | 28 + include/configs/mini2440.h| 186 + 7 files changed, 541 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 include/configs/mini2440.h diff --git a/MAINTAINERS b/MAINTAINERS index 708ded7..2611fb5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,10 @@ Unknown / orphaned boards: # Board CPU # # +Gabriel HUAU cont...@huau-gabriel.fr + + mini2440s3c2440 + Albert ARIBAUD albert.u.b...@aribaud.net edminiv2ARM926EJS (Orion5x SoC) diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 000..b88e569 --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := mini2440.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 000..e97d981 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Marius Groeger mgroe...@sysgo.de + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * + * (C) Copyright 2009 + * Michel Pollet buser...@gmail.com + * + * (C) Copyright 2012 + * Gabriel Huau cont...@huau-gabriel.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free
Re: [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
Hi Minkyu Kang, Can you review/apply theses patches please ? (Marex have already tortured me ...) : - [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440 - [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440). Thanks, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
From the last time, I removed the patch about the PLL initialization because it's board specific. I added a new patch for s3c440 gpio driver. Now in the board file we have no more magic bloat. +/* + * When booting from NAND, it is impossible to access the lowest addresses + * due to the SteppingStone being in the way. Luckily the NOR doesn't really + * care about the highest 16 bits of address, so we set the controlers + * registers to go and poke over there, instead. + */ +#define PHYS_FLASH_1 0x0 +#define CONFIG_SYS_FLASH_BASE0x0 Urghh... this sounds very much like a serious design issue? About this point, I ported it from the old version uboot as well. It may need some investigation, but I remember it was a big problem with this board. In the case of a NAND boot, we don't have access to NOR because the SteppingStone (SRAM) is mapped at the same range. Gabriel Huau (2): Add GPIO Driver and IOMUX definition for S3C2440 Add support for MINI2440 (s3c2440). MAINTAINERS |4 + arch/arm/include/asm/arch-s3c24x0/gpio.h | 183 + arch/arm/include/asm/arch-s3c24x0/iomux.h | 197 +++ board/friendlyarm/mini2440/Makefile | 44 ++ board/friendlyarm/mini2440/mini2440.c | 135 +++ board/friendlyarm/mini2440/mini2440.h | 144 boards.cfg|1 + doc/README.mini2440 | 28 drivers/gpio/Makefile |1 + drivers/gpio/s3c2440_gpio.c | 74 ++ include/configs/mini2440.h| 209 + 11 files changed, 1020 insertions(+) create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 drivers/gpio/s3c2440_gpio.c create mode 100644 include/configs/mini2440.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/arm/include/asm/arch-s3c24x0/gpio.h | 183 +++
arch/arm/include/asm/arch-s3c24x0/iomux.h | 197 +
drivers/gpio/Makefile |1 +
drivers/gpio/s3c2440_gpio.c | 74 +++
4 files changed, 455 insertions(+)
create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
create mode 100644 drivers/gpio/s3c2440_gpio.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h
b/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 000..e7fbefe
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2012, Gabriel Huau. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+
+/* 0x4 means that we can DAT and not CON register */
+#define GPIO_PORT(x) x) 5) 0x3) + 0x4)
+#define GPIO_BIT(x)((x) 0x3f)
+
+/*
+ * It's how we calculate the full port address
+ * We have to get the number of the port + 1 (Port A is at 0x5601 ...)
+ * We move it at the second digit, and finally we add 0x4 because we want
+ * to modify GPIO DAT and not CON
+ */
+#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) 1))
+
+typedef enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+} s3c2240_gpio;
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h
b/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 000..2201cd3
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2012, Gabriel Huau. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty
[U-Boot] [PATCH 2/2 v5] Add support for MINI2440 (s3c2440).
--- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some magic bloat with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright Changes for v4: - Move dram init to dram_init() instead low_levelinit - Remove u-boot env from configuration file and change the address of initial SP - Remove PLL init, now it's SoC specific Changes fr v5: - Clean up configuration file - Add a MAINTAINERS entry - Add a README.mini2440 file - Use gpio/iomux interface in case of magic numbers - Use get_ram_size() Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- MAINTAINERS |4 + board/friendlyarm/mini2440/Makefile | 44 +++ board/friendlyarm/mini2440/mini2440.c | 135 + board/friendlyarm/mini2440/mini2440.h | 144 +++ boards.cfg|1 + doc/README.mini2440 | 28 + include/configs/mini2440.h| 209 + 7 files changed, 565 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 include/configs/mini2440.h diff --git a/MAINTAINERS b/MAINTAINERS index 72f8b64..f1bc316 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,10 @@ Unknown / orphaned boards: # Board CPU # # +Gabriel HUAU cont...@huau-gabriel.fr + + mini2440s3c2440 + Albert ARIBAUD albert.u.b...@aribaud.net edminiv2ARM926EJS (Orion5x SoC) diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 000..b88e569 --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := mini2440.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 000..49e66a5 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Marius Groeger mgroe...@sysgo.de + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * + * (C) Copyright 2009 + * Michel Pollet buser...@gmail.com + * + * (C) Copyright 2012 + * Gabriel Huau cont...@huau-gabriel.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details
Re: [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
On Sun, Apr 29, 2012 at 11:32:27PM +0200, Wolfgang Denk wrote: Dear Gabriel Huau, In message 1335734845-27396-1-git-send-email-cont...@huau-gabriel.fr you wrote: +/* + * When booting from NAND, it is impossible to access the lowest addresses + * due to the SteppingStone being in the way. Luckily the NOR doesn't really + * care about the highest 16 bits of address, so we set the controlers + * registers to go and poke over there, instead. + */ +#define PHYS_FLASH_1 0x0 +#define CONFIG_SYS_FLASH_BASE0x0 Urghh... this sounds very much like a serious design issue? About this point, I ported it from the old version uboot as well. It may need some investigation, but I remember it was a big problem with this board. In the case of a NAND boot, we don't have access to NOR because the SteppingStone (SRAM) is mapped at the same range. Should this not only affect the SPL part of the code, while you could use normal mappings for the real U-Boot. Umm... but I don't even see any reference to SPL files here. Is this current code supposed to support NAND booting? and if so, why doesn;t it use SPL? Nope, laters. Currently, the code is only supporting boot from NOR. Should I remove these defines ? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Genitiv ins Wasser, weil's Dativ ist! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] Add support for MINI2440
These patches add the support for the mini2440 (s3c2440 arm). Currently, I'm supporting only boot from NOR. The first patch move the PLL initialization to SoC specific directory. I also changed boards which depend on this SoC. Gabriel Huau (2): S3C2440 : PLL Initialization should be SoC specific Add support for MINI2440 (s3c2440). arch/arm/cpu/arm920t/s3c24x0/timer.c | 36 ++ board/friendlyarm/mini2440/Makefile | 44 +++ board/friendlyarm/mini2440/mini2440.c | 121 +++ board/mpl/vcma9/lowlevel_init.S | 22 board/samsung/smdk2410/smdk2410.c | 19 --- boards.cfg|1 + include/configs/mini2440.h| 212 + 7 files changed, 414 insertions(+), 41 deletions(-) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 include/configs/mini2440.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] S3C2440 : PLL Initialization should be SoC specific
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/arm/cpu/arm920t/s3c24x0/timer.c | 36 ++
board/mpl/vcma9/lowlevel_init.S | 22 -
board/samsung/smdk2410/smdk2410.c| 19 --
3 files changed, 36 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c
b/arch/arm/cpu/arm920t/s3c24x0/timer.c
index d8668be..7ff687c 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -37,8 +37,27 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_S3C2440
+/*
+ * PLL/Clock configuration
+ */
+/* FCLK = 405 MHz, HCLK = 101 MHz, PCLK = 50 MHz, UCLK = 48 MHz */
+#define CLKDIVN_VAL7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+#endif
+
int timer_init(void)
{
+#ifdef CONFIG_S3C2440
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+#endif
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
ulong tmr;
@@ -65,6 +84,23 @@ int timer_init(void)
gd-lastinc = 0;
gd-tbl = 0;
+#ifdef CONFIG_S3C2440
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power-locktime = 0xFF;
+ clk_power-clkdivn = CLKDIVN_VAL;
+
+ /* configure UPLL */
+ clk_power-upllcon = ((U_M_MDIV 12) + (U_M_PDIV 4) + U_M_SDIV);
+ /* some delay between MPLL and UPLL */
+ __udelay(10);
+
+ /* configure MPLL */
+ clk_power-mpllcon = ((M_MDIV 12) + (M_PDIV 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ __udelay(8000);
+#endif
+
return 0;
}
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
index dadaac7..4deb451 100644
--- a/board/mpl/vcma9/lowlevel_init.S
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -262,28 +262,6 @@ lowlevel_init:
cmp r3, r4
bne 0b
- /* setup MPLL registers */
- ldr r1, =CLKBASE
- ldr r4, =0xFF
- add r3, r2, #4 /* r3 points to PLL values */
- str r4, [r1, #LOCKTIME]
- ldmia r3, {r4,r5}
- str r5, [r1, #UPLLCON] /* writing PLL register */
- /* !! order seems to be important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subsr3, r3, #1
- bne 0b
-
- str r4, [r1, #MPLLCON] /* writing PLL register */
- /* !! order seems to be important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subsr3, r3, #1
- bne 0b
-
/* everything is fine now */
mov pc, lr
diff --git a/board/samsung/smdk2410/smdk2410.c
b/board/samsung/smdk2410/smdk2410.c
index e9ba922..3beb587 100644
--- a/board/samsung/smdk2410/smdk2410.c
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -69,27 +69,8 @@ static inline void pll_delay(unsigned long loops)
int board_early_init_f(void)
{
- struct s3c24x0_clock_power * const clk_power =
- s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- /* to reduce PLL lock time, adjust the LOCKTIME register */
- writel(0xFF, clk_power-locktime);
-
- /* configure MPLL */
- writel((M_MDIV 12) + (M_PDIV 4) + M_SDIV,
- clk_power-mpllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(4000);
-
- /* configure UPLL */
- writel((U_M_MDIV 12) + (U_M_PDIV 4) + U_M_SDIV,
- clk_power-upllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(8000);
-
/* set up the I/O ports */
writel(0x007F, gpio-gpacon);
writel(0x00044555, gpio-gpbcon);
--
1.7.9.5
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[U-Boot] [PATCH 2/2 v4] Add support for MINI2440 (s3c2440).
---
Changes for v2:
- Coding style cleanup
- Remove unnecessary files modification
- Remove unnecessary board configuration set
Changes for v3:
- Coding style cleanup
- Move some macro definition from lowlevel_init.S
to a new header
- Remove some magic bloat with I/O board initialization
- Add a pll_delay and replace loop by it
- Somme cleanup in the configuration file
- Cancel modifications on an SoC specific header
- Add my name to copyright
Changes for v4:
- Move dram init to dram_init() instead low_levelinit
- Remove u-boot env from configuration file and change
the address of initial SP
- Remove PLL init, now it's SoC specific
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
board/friendlyarm/mini2440/Makefile | 44 +++
board/friendlyarm/mini2440/mini2440.c | 121 +++
boards.cfg|1 +
include/configs/mini2440.h| 212 +
4 files changed, 378 insertions(+)
create mode 100644 board/friendlyarm/mini2440/Makefile
create mode 100644 board/friendlyarm/mini2440/mini2440.c
create mode 100644 include/configs/mini2440.h
diff --git a/board/friendlyarm/mini2440/Makefile
b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 000..b88e569
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2012
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := mini2440.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/friendlyarm/mini2440/mini2440.c
b/board/friendlyarm/mini2440/mini2440.c
new file mode 100644
index 000..ab81939
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Marius Groeger mgroe...@sysgo.de
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.muel...@elsoft.ch
+ *
+ * (C) Copyright 2009
+ * Michel Pollet buser...@gmail.com
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau cont...@huau-gabriel.fr
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/arch/s3c2440.h
+#include asm/io.h
+#include video_fb.h
+
+#ifdef CONFIG_DRIVER_DM9000
+#include netdev.h
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* set up the I/O ports */
+ writel(0x007F, gpio-gpacon);
+ writel(0x00044555, gpio-gpbcon);
+ writel(0x07FF, gpio-gpbup);
+ writel(0x, gpio-gpccon);
+ writel(0x, gpio-gpcup);
+ writel(0x, gpio-gpdcon);
+ writel(0x, gpio-gpdup);
+ writel(0x, gpio-gpecon);
+ writel(0x, gpio-gpeup
Re: [U-Boot] [PATCH 1/2] S3C2440 : PLL Initialization should be SoC specific
On Sun, Apr 22, 2012 at 10:30:52PM +0200, Marek Vasut wrote:
Dear Gabriel Huau,
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/arm/cpu/arm920t/s3c24x0/timer.c | 36
++ board/mpl/vcma9/lowlevel_init.S |
22 - board/samsung/smdk2410/smdk2410.c| 19
--
3 files changed, 36 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c
b/arch/arm/cpu/arm920t/s3c24x0/timer.c index d8668be..7ff687c 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -37,8 +37,27 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_S3C2440
+/*
+ * PLL/Clock configuration
+ */
+/* FCLK = 405 MHz, HCLK = 101 MHz, PCLK = 50 MHz, UCLK = 48 MHz */
+#define CLKDIVN_VAL7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+#endif
So after applying your patch, timer driver won't build for 2410 ?
Yes it will build, This patch is only for s3c2440. I just moved PLL
initialization of s3c2440 board to this file. I don't know if theses
values are correct for s3c2410 too.
+
+ /* configure MPLL */
+ clk_power-mpllcon = ((M_MDIV 12) + (M_PDIV 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ __udelay(8000);
+#endif
+
return 0;
}
diff --git a/board/mpl/vcma9/lowlevel_init.S
b/board/mpl/vcma9/lowlevel_init.S index dadaac7..4deb451 100644
--- a/board/mpl/vcma9/lowlevel_init.S
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -262,28 +262,6 @@ lowlevel_init:
cmp r3, r4
bne 0b
- /* setup MPLL registers */
- ldr r1, =CLKBASE
- ldr r4, =0xFF
- add r3, r2, #4 /* r3 points to PLL values */
- str r4, [r1, #LOCKTIME]
- ldmia r3, {r4,r5}
- str r5, [r1, #UPLLCON] /* writing PLL register */
- /* !! order seems to be important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subsr3, r3, #1
- bne 0b
-
- str r4, [r1, #MPLLCON] /* writing PLL register */
- /* !! order seems to be important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subsr3, r3, #1
- bne 0b
-
/* everything is fine now */
mov pc, lr
diff --git a/board/samsung/smdk2410/smdk2410.c
b/board/samsung/smdk2410/smdk2410.c index e9ba922..3beb587 100644
--- a/board/samsung/smdk2410/smdk2410.c
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -69,27 +69,8 @@ static inline void pll_delay(unsigned long loops)
int board_early_init_f(void)
{
- struct s3c24x0_clock_power * const clk_power =
- s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- /* to reduce PLL lock time, adjust the LOCKTIME register */
- writel(0xFF, clk_power-locktime);
-
- /* configure MPLL */
- writel((M_MDIV 12) + (M_PDIV 4) + M_SDIV,
- clk_power-mpllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(4000);
-
- /* configure UPLL */
- writel((U_M_MDIV 12) + (U_M_PDIV 4) + U_M_SDIV,
- clk_power-upllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(8000);
-
/* set up the I/O ports */
writel(0x007F, gpio-gpacon);
writel(0x00044555, gpio-gpbcon);
Magic?
I don't maintain theses boards, I just removed PLL initialization
because I moved it. So for magic values in I/O port, we have to contact
the maintainers :).
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/2] S3C2440 : PLL Initialization should be SoC specific
This patch can be cancel/ignore ... PLL initialization is BOARD-specific
and not SoC So, now, no more problem about magic number in
others boards and management of s3c2410/s3c2440 :).
On Sun, Apr 22, 2012 at 11:32:18PM +0200, Marek Vasut wrote:
Dear Gabriel Huau,
On Sun, Apr 22, 2012 at 10:30:52PM +0200, Marek Vasut wrote:
Dear Gabriel Huau,
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/arm/cpu/arm920t/s3c24x0/timer.c | 36
++ board/mpl/vcma9/lowlevel_init.S
|
22 - board/samsung/smdk2410/smdk2410.c| 19
--
3 files changed, 36 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c
b/arch/arm/cpu/arm920t/s3c24x0/timer.c index d8668be..7ff687c 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -37,8 +37,27 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_S3C2440
+/*
+ * PLL/Clock configuration
+ */
+/* FCLK = 405 MHz, HCLK = 101 MHz, PCLK = 50 MHz, UCLK = 48 MHz */
+#define CLKDIVN_VAL7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+#endif
So after applying your patch, timer driver won't build for 2410 ?
Yes it will build, This patch is only for s3c2440. I just moved PLL
initialization of s3c2440 board to this file. I don't know if theses
values are correct for s3c2410 too.
I think these should be unified ... all these #ifdef blocks are stupid
+
+ /* configure MPLL */
+ clk_power-mpllcon = ((M_MDIV 12) + (M_PDIV 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ __udelay(8000);
+#endif
+
return 0;
}
diff --git a/board/mpl/vcma9/lowlevel_init.S
b/board/mpl/vcma9/lowlevel_init.S index dadaac7..4deb451 100644
--- a/board/mpl/vcma9/lowlevel_init.S
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -262,28 +262,6 @@ lowlevel_init:
cmp r3, r4
bne 0b
- /* setup MPLL registers */
- ldr r1, =CLKBASE
- ldr r4, =0xFF
- add r3, r2, #4 /* r3 points to PLL values */
- str r4, [r1, #LOCKTIME]
- ldmia r3, {r4,r5}
- str r5, [r1, #UPLLCON] /* writing PLL register */
- /* !! order seems to be
important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subsr3, r3, #1
- bne 0b
-
- str r4, [r1, #MPLLCON] /* writing PLL register */
- /* !! order seems to be
important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subsr3, r3, #1
- bne 0b
-
/* everything is fine now */
mov pc, lr
diff --git a/board/samsung/smdk2410/smdk2410.c
b/board/samsung/smdk2410/smdk2410.c index e9ba922..3beb587 100644
--- a/board/samsung/smdk2410/smdk2410.c
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -69,27 +69,8 @@ static inline void pll_delay(unsigned long loops)
int board_early_init_f(void)
{
- struct s3c24x0_clock_power * const clk_power =
- s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- /* to reduce PLL lock time, adjust the LOCKTIME register */
- writel(0xFF, clk_power-locktime);
-
- /* configure MPLL */
- writel((M_MDIV 12) + (M_PDIV 4) + M_SDIV,
- clk_power-mpllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(4000);
-
- /* configure UPLL */
- writel((U_M_MDIV 12) + (U_M_PDIV 4) + U_M_SDIV,
- clk_power-upllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(8000);
-
/* set up the I/O ports */
writel(0x007F, gpio-gpacon);
writel(0x00044555, gpio-gpbcon);
Magic?
I don't maintain theses boards, I just removed PLL initialization
because I moved it. So for magic values in I/O port, we have to contact
the maintainers :).
Good idea, please do :-)
Best regards,
Marek Vasut
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3] Add support for MINI2440 (s3c2440)
On Sat, Apr 21, 2012 at 02:51:46AM +0400, Ilya Averyanov wrote: 2012/4/21 Marek Vasut ma...@denx.de Dear Vasily Khoruzhick, 2012/4/20 Marek Vasut ma...@denx.de: Which doesn't matter, either way you need stack ... and you can have the stack in cache ;-) s3c24xx has 4kb of SRAM (steppingstone), you can use it for stack Oh, I didn't know that ... so there's no longer any problem. No have problem. Available only if you boot from NOR flash. If you boot from the NAND 4kb of SRAM (steppingstone) not available. SteppingStone is available ONLY in NAND boot :) and not available in NOR boot. Btw, using cache for stack looks like awful hack to me. It's fairy normal. I agree with Vasily Khoruzhick, it looks like a hack Regards Vasily Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] Add support for MINI2440 (s3c2440). Documentation about the product can be found on: http://www.friendlyarm.net/products/mini2440
--- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some magic bloat with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright --- board/friendlyarm/mini2440/Makefile| 45 ++ board/friendlyarm/mini2440/lowlevel_init.S | 76 ++ board/friendlyarm/mini2440/mini2440.c | 139 ++ board/friendlyarm/mini2440/mini2440.h | 104 ++ boards.cfg |1 + include/configs/mini2440.h | 215 6 files changed, 580 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/lowlevel_init.S create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 include/configs/mini2440.h diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 000..e8d68cb --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := mini2440.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/friendlyarm/mini2440/lowlevel_init.S b/board/friendlyarm/mini2440/lowlevel_init.S new file mode 100644 index 000..f69a08c --- /dev/null +++ b/board/friendlyarm/mini2440/lowlevel_init.S @@ -0,0 +1,76 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (j.a.k.m...@its.tudelft.nl) and + * Jan-Derk Bakker (j.d.bak...@its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * + * (C) Copyright 2012 + * Gabriel Huau cont...@huau-gabriel.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include config.h +#include version.h +#include mini2440.h + +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now
Re: [U-Boot] [PATCH v3] Add support for MINI2440 (s3c2440). Documentation about the product can be found on: http://www.friendlyarm.net/products/mini2440
On Thu, Apr 19, 2012 at 10:08:47PM +0200, Marek Vasut wrote: Dear Gabriel Huau, --- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some magic bloat with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright --- board/friendlyarm/mini2440/Makefile| 45 ++ board/friendlyarm/mini2440/lowlevel_init.S | 76 ++ board/friendlyarm/mini2440/mini2440.c | 139 ++ board/friendlyarm/mini2440/mini2440.h | 104 ++ boards.cfg |1 + include/configs/mini2440.h | 215 6 files changed, 580 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/lowlevel_init.S create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 include/configs/mini2440.h diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 000..e8d68cb --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := mini2440.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/friendlyarm/mini2440/lowlevel_init.S b/board/friendlyarm/mini2440/lowlevel_init.S new file mode 100644 index 000..f69a08c --- /dev/null +++ b/board/friendlyarm/mini2440/lowlevel_init.S @@ -0,0 +1,76 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (j.a.k.m...@its.tudelft.nl) and + * Jan-Derk Bakker (j.d.bak...@its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * + * (C) Copyright 2012 + * Gabriel Huau cont...@huau-gabriel.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include config.h +#include version.h +#include mini2440.h + +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA
Re: [U-Boot] [PATCH v3] Add support for MINI2440 (s3c2440). Documentation about the product can be found on: http://www.friendlyarm.net/products/mini2440
On Thu, Apr 19, 2012 at 10:45:21PM +0200, Marek Vasut wrote: Dear Gabriel Huau, On Thu, Apr 19, 2012 at 10:08:47PM +0200, Marek Vasut wrote: Dear Gabriel Huau, --- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some magic bloat with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright --- board/friendlyarm/mini2440/Makefile| 45 ++ board/friendlyarm/mini2440/lowlevel_init.S | 76 ++ board/friendlyarm/mini2440/mini2440.c | 139 ++ board/friendlyarm/mini2440/mini2440.h | 104 ++ boards.cfg |1 + include/configs/mini2440.h | 215 6 files changed, 580 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/lowlevel_init.S create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 include/configs/mini2440.h diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 000..e8d68cb --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := mini2440.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +## ### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +## ### diff --git a/board/friendlyarm/mini2440/lowlevel_init.S b/board/friendlyarm/mini2440/lowlevel_init.S new file mode 100644 index 000..f69a08c --- /dev/null +++ b/board/friendlyarm/mini2440/lowlevel_init.S @@ -0,0 +1,76 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (j.a.k.m...@its.tudelft.nl) and + * Jan-Derk Bakker (j.d.bak...@its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.muel...@elsoft.ch + * + * (C) Copyright 2012 + * Gabriel Huau cont...@huau-gabriel.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111
[U-Boot] [PATCH V2] Add support for Mini2440
A little review of my first patch. As you can see, I removed some
unnecessary modifications that I did in arm920t directory ... (I don't
really remember why I did it), and some modifications on drivers (nand
and i2c) that was unnecessary because I am not currently supporting
theses features.
I forget to say in my first mail that is a porting from an old version
of u-boot patched by BusError (Michel Pollet).
From 9cefb0a55332b094256447f32d1b27c4f3f7808a Mon Sep 17 00:00:00 2001
From: Gabriel Huau cont...@huau-gabriel.fr
Date: Sun, 15 Apr 2012 00:10:22 +0200
Subject: [PATCH v2] Add support for MINI2440 (s3c2440). Documentation about
the product can be found on:
http://www.friendlyarm.net/products/mini2440
---
Changes for v2:
- Coding style cleanup
- Remove unnecessary files modification
- Remove unnecessary board configuration set
---
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 51 +-
board/friendlyarm/mini2440/Makefile | 45 +
board/friendlyarm/mini2440/lowlevel_init.S | 177 +
board/friendlyarm/mini2440/mini2440.c | 283 +++
boards.cfg |1 +
include/configs/mini2440.h | 203 +++
6 files changed, 710 insertions(+), 50 deletions(-)
create mode 100644 board/friendlyarm/mini2440/Makefile
create mode 100644 board/friendlyarm/mini2440/lowlevel_init.S
create mode 100644 board/friendlyarm/mini2440/mini2440.c
create mode 100644 include/configs/mini2440.h
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index ca978c9..96e623b 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -416,7 +416,7 @@ struct s3c24x0_gpio {
u32 misccr;
u32 extint;
#endif
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 gpacon;
u32 gpadat;
u32 res1[2];
@@ -467,55 +467,6 @@ struct s3c24x0_gpio {
u32 gstatus4;
#endif
#if defined(CONFIG_S3C2440)
- u32 gpacon;
- u32 gpadat;
- u32 res1[2];
- u32 gpbcon;
- u32 gpbdat;
- u32 gpbup;
- u32 res2;
- u32 gpccon;
- u32 gpcdat;
- u32 gpcup;
- u32 res3;
- u32 gpdcon;
- u32 gpddat;
- u32 gpdup;
- u32 res4;
- u32 gpecon;
- u32 gpedat;
- u32 gpeup;
- u32 res5;
- u32 gpfcon;
- u32 gpfdat;
- u32 gpfup;
- u32 res6;
- u32 gpgcon;
- u32 gpgdat;
- u32 gpgup;
- u32 res7;
- u32 gphcon;
- u32 gphdat;
- u32 gphup;
- u32 res8;
-
- u32 misccr;
- u32 dclkcon;
- u32 extint0;
- u32 extint1;
- u32 extint2;
- u32 eintflt0;
- u32 eintflt1;
- u32 eintflt2;
- u32 eintflt3;
- u32 eintmask;
- u32 eintpend;
- u32 gstatus0;
- u32 gstatus1;
- u32 gstatus2;
- u32 gstatus3;
- u32 gstatus4;
-
u32 res9;
u32 dsc0;
u32 dsc1;
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 000..065f1db
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mini2440.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/friendlyarm/mini2440/lowlevel_init.S b/board/friendlyarm/mini2440/lowlevel_init.S
new file mode 100644
index 000..2a057ea
--- /dev/null
+++ b/board/friendlyarm/mini2440/lowlevel_init.S
@@ -0,0 +1,177 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (j.a.k.m...@its.tudelft.nl) and
+ * Jan-Derk Bakker (j.d.bak...@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.muel...@elsoft.ch
+ *
+ * See file CREDITS for list of people
[U-Boot] Add support for Mini2440
Hi all,
This is a first patch to introduce the support of the Mini2440. It's a
board based on the S3C2440, arm920t. I based the support on the code of
BusError (old version of u-boot).
I have a few work to do again, like some clean up in the configuration
file. Currently, with this patch, we can boot from NOR and the network
is available (tftp, dhcp, ...). Boot from NAND will be the next step
(and laters MMC).
Best regards,
From 5f373acac7447aaf3072f0d1ba88d364a8b2ebfe Mon Sep 17 00:00:00 2001
From: Gabriel Huau cont...@huau-gabriel.fr
Date: Sun, 15 Apr 2012 00:10:22 +0200
Subject: [PATCH] Add support for MINI2440 (s3c2440). Documentation about the
product can be found on:
http://www.friendlyarm.net/products/mini2440
---
arch/arm/cpu/arm920t/cpu.c | 34 +++
arch/arm/cpu/arm920t/start.S|4 +
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 51 +
board/friendlyarm/mini2440/Makefile | 45
board/friendlyarm/mini2440/lowlevel_init.S | 197
board/friendlyarm/mini2440/mini2440.c | 279 +++
boards.cfg |1 +
drivers/i2c/s3c24x0_i2c.c | 11 +-
drivers/mtd/nand/s3c2410_nand.c | 82 +++
include/configs/mini2440.h | 323 +++
10 files changed, 973 insertions(+), 54 deletions(-)
create mode 100644 board/friendlyarm/mini2440/Makefile
create mode 100644 board/friendlyarm/mini2440/lowlevel_init.S
create mode 100644 board/friendlyarm/mini2440/mini2440.c
create mode 100644 include/configs/mini2440.h
diff --git a/arch/arm/cpu/arm920t/cpu.c b/arch/arm/cpu/arm920t/cpu.c
index 34adb11..baf3d01 100644
--- a/arch/arm/cpu/arm920t/cpu.c
+++ b/arch/arm/cpu/arm920t/cpu.c
@@ -32,9 +32,43 @@
#include common.h
#include command.h
#include asm/system.h
+#include asm/arch/s3c2440.h
+
+/* FCLK = 405 MHz, HCLK = 101 MHz, PCLK = 50 MHz, UCLK = 48 MHz */
+#define CLKDIVN_VAL 7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
static void cache_flush(void);
+int arch_cpu_init (void)
+{
+ struct s3c24x0_clock_power * const clk_power = s3c24x0_get_base_clock_power();
+ int i;
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power-locktime = 0xFF;
+ clk_power-clkdivn = CLKDIVN_VAL;
+
+ /* configure UPLL */
+ clk_power-upllcon = ((U_M_MDIV 12) + (U_M_PDIV 4) + U_M_SDIV);
+ /* some delay between MPLL and UPLL */
+ for(i = 0; i 10; i++);
+
+ /* configure MPLL */
+ clk_power-mpllcon = ((M_MDIV 12) + (M_PDIV 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ for(i = 0; i 50; i++);
+
+ return 0;
+}
+
int cleanup_before_linux (void)
{
/*
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 8c5612c..1d75fb5 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -165,6 +165,10 @@ copyex:
ldr r1, =0x3ff
ldr r0, =INTSUBMSK
str r1, [r0]
+# else
+ ldr r1, =0x
+ ldr r0, =INTSUBMSK
+ str r1, [r0]
# endif
/* FCLK:HCLK:PCLK = 1:2:4 */
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index ca978c9..96e623b 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -416,7 +416,7 @@ struct s3c24x0_gpio {
u32 misccr;
u32 extint;
#endif
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 gpacon;
u32 gpadat;
u32 res1[2];
@@ -467,55 +467,6 @@ struct s3c24x0_gpio {
u32 gstatus4;
#endif
#if defined(CONFIG_S3C2440)
- u32 gpacon;
- u32 gpadat;
- u32 res1[2];
- u32 gpbcon;
- u32 gpbdat;
- u32 gpbup;
- u32 res2;
- u32 gpccon;
- u32 gpcdat;
- u32 gpcup;
- u32 res3;
- u32 gpdcon;
- u32 gpddat;
- u32 gpdup;
- u32 res4;
- u32 gpecon;
- u32 gpedat;
- u32 gpeup;
- u32 res5;
- u32 gpfcon;
- u32 gpfdat;
- u32 gpfup;
- u32 res6;
- u32 gpgcon;
- u32 gpgdat;
- u32 gpgup;
- u32 res7;
- u32 gphcon;
- u32 gphdat;
- u32 gphup;
- u32 res8;
-
- u32 misccr;
- u32 dclkcon;
- u32 extint0;
- u32 extint1;
- u32 extint2;
- u32 eintflt0;
- u32 eintflt1;
- u32 eintflt2;
- u32 eintflt3;
- u32 eintmask;
- u32 eintpend;
- u32 gstatus0;
- u32 gstatus1;
- u32 gstatus2;
- u32 gstatus3;
- u32 gstatus4;
-
u32 res9;
u32 dsc0;
u32 dsc1;
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 000..065f1db
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your
