Re: [RFC 4/7] pinctrl: mscc: Fix multiple definition error
The 05/03/2021 16:48, Tom Rini wrote: > > With gcc-11 we get a multiple errors here as the declarations for > mscc_pinctrl_ops and mscc_gpio_ops are missing an extern. Reviewed-by: Horatiu Vultur > > CC: Gregory CLEMENT > Cc: Lars Povlsen > Cc: Horatiu Vultur > Signed-off-by: Tom Rini > --- > drivers/pinctrl/mscc/mscc-common.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/mscc/mscc-common.h > b/drivers/pinctrl/mscc/mscc-common.h > index 3c5c1faf840f..49c84a9f410b 100644 > --- a/drivers/pinctrl/mscc/mscc-common.h > +++ b/drivers/pinctrl/mscc/mscc-common.h > @@ -61,6 +61,6 @@ int mscc_pinctrl_probe(struct udevice *dev, int num_func, >const struct mscc_pin_data *mscc_pins, int num_pins, >char * const *function_names, >const unsigned long *mscc_gpios); > -const struct pinctrl_ops mscc_pinctrl_ops; > +extern const struct pinctrl_ops mscc_pinctrl_ops; > > -const struct dm_gpio_ops mscc_gpio_ops; > +extern const struct dm_gpio_ops mscc_gpio_ops; > -- > 2.17.1 > -- /Horatiu
Re: [PATCH 0/2] net: jr2: Fix for jr2 switch
Hi, A gentle ping. Thanks. The 03/10/2021 09:31, Horatiu Vultur wrote: > This patch series contains two patches. The first patch resets the > switch at probe time while the second one fixes an issue with the > serdes6g configuration which is used on jr2_pcb111 board > > Horatiu Vultur (2): > net: jr2: Reset switch > net: jr2: Fix Serdes6G configuration > > arch/mips/dts/mscc,jr2.dtsi | 6 ++-- > drivers/net/mscc_eswitch/jr2_switch.c | 43 +++ > 2 files changed, 42 insertions(+), 7 deletions(-) > > -- > 2.30.1 > -- /Horatiu
Re: [PATCH] dm: core: Add address translation in fdt_get_resource
The 04/06/2021 09:38, Patrick Delaunay wrote:
Hi Patrick,
I have applied your patches and I have done a basic test on jr2_switch.
It seems to work fine. I got some warnings from the function
'__of_translate_address' which I need to figure out.
But one more important thing is that also luton_switch should be
updated.
>
> Today of_address_to_resource() is called only in
> ofnode_read_resource() for livetree support and
> fdt_get_resource() is called when livetree is not supported.
>
> The fdt_get_resource() doesn't do the address translation
> so when it is required, but the address translation is done
> by ofnode_read_resource() caller, for example in
> drivers/firmware/scmi/smt.c::scmi_dt_get_smt_buffer() {
> ...
> ret = ofnode_read_resource(args.node, 0, );
> if (ret)
> return ret;
>
> faddr = cpu_to_fdt32(resource.start);
> paddr = ofnode_translate_address(args.node, );
> ...
>
> The both behavior should be aligned and the address translation
> must be called in fdt_get_resource() and removed for each caller.
>
> Fixes: a44810123f9e ("dm: core: Add dev_read_resource() to read device
> resources")
> Signed-off-by: Patrick Delaunay
> ---
>
> This patch allows to remove the workaround in smci/smt.c
> introduced by [1].
>
> But it impact with all user of
> - ofnode_read_resource
> - ofnode_read_resource_byname
> - dev_read_resource
> - dev_read_resource_byname
>
> After my first check, the only impacts are in drivers/net/mscc_eswitch
> => I remove the unnecessary translate after code review,
>this patch need to be verify on real hardware
>
> I proposed to merge the workaround [1] as soon as possible to avoid issue
> on stm32mp1 platform and this patch can be merged when it will be acked
> by mscc_eswitch maintainers and other API users.
>
> [1] "scmi: translate the resource only when livetree is not activated"
> http://patchwork.ozlabs.org/project/uboot/list/?series=236526=*
>
>
> drivers/firmware/scmi/smt.c | 12 +---
> drivers/net/mscc_eswitch/jr2_switch.c | 4 +---
> drivers/net/mscc_eswitch/ocelot_switch.c | 4 +---
> drivers/net/mscc_eswitch/serval_switch.c | 4 +---
> drivers/net/mscc_eswitch/servalt_switch.c | 4 +---
> lib/fdtdec.c | 6 +-
> 6 files changed, 10 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
> index f1915c0074..e60c2aebc8 100644
> --- a/drivers/firmware/scmi/smt.c
> +++ b/drivers/firmware/scmi/smt.c
> @@ -30,8 +30,6 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct
> scmi_smt *smt)
> int ret;
> struct ofnode_phandle_args args;
> struct resource resource;
> - fdt32_t faddr;
> - phys_addr_t paddr;
>
> ret = dev_read_phandle_with_args(dev, "shmem", NULL, 0, 0, );
> if (ret)
> @@ -41,21 +39,13 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct
> scmi_smt *smt)
> if (ret)
> return ret;
>
> - /* TEMP workaround for ofnode_read_resource translation issue */
> - if (of_live_active()) {
> - paddr = resource.start;
> - } else {
> - faddr = cpu_to_fdt32(resource.start);
> - paddr = ofnode_translate_address(args.node, );
> - }
> -
> smt->size = resource_size();
> if (smt->size < sizeof(struct scmi_smt_header)) {
> dev_err(dev, "Shared memory buffer too small\n");
> return -EINVAL;
> }
>
> - smt->buf = devm_ioremap(dev, paddr, smt->size);
> + smt->buf = devm_ioremap(dev, resource.start, smt->size);
> if (!smt->buf)
> return -ENOMEM;
>
> diff --git a/drivers/net/mscc_eswitch/jr2_switch.c
> b/drivers/net/mscc_eswitch/jr2_switch.c
> index 128d7f21ce..bf3e9b56ec 100644
> --- a/drivers/net/mscc_eswitch/jr2_switch.c
> +++ b/drivers/net/mscc_eswitch/jr2_switch.c
> @@ -842,7 +842,6 @@ static int jr2_probe(struct udevice *dev)
> int i;
> int ret;
> struct resource res;
> - fdt32_t faddr;
> phys_addr_t addr_base;
> unsigned long addr_size;
> ofnode eth_node, node, mdio_node;
> @@ -893,9 +892,8 @@ static int jr2_probe(struct udevice *dev)
>
> if (ofnode_read_resource(mdio_node, 0, ))
> return -ENOMEM;
> - faddr = cpu_to_fdt32(res.start);
>
> - addr_base = ofnode_translate_address(mdio_node, );
> + addr_base = res.start;
> addr_size = res.end - res.start;
>
> /* If the bus is new then create a new bus */
> diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
> b/drivers/net/mscc_eswitch/ocelot_switch.c
> index 19e725c6f9..d1d0a489ab 100644
> --- a/drivers/net/mscc_eswitch/ocelot_switch.c
> +++ b/drivers/net/mscc_eswitch/ocelot_switch.c
> @@ -530,7 +530,6 @@ static int ocelot_probe(struct
[PATCH 2/2] net: jr2: Fix Serdes6G configuration
Sometimes no traffic was getting out on the ports, the root cause was
a wrong configuration of the Serdes6G, which is used on jr2 pcb111.
This patch fixes this issue by applying the correct configuration.
Fixes: 5e1d417bec92ac ("net: Add MSCC Jaguar2 network driver.")
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/jr2_switch.c | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c
b/drivers/net/mscc_eswitch/jr2_switch.c
index 9ba6ccc1bb..570d5a5109 100644
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -369,7 +369,6 @@ static void serdes6g_setup(void __iomem *base, uint32_t
addr,
{
u32 ib_if_mode = 0;
u32 ib_qrate = 0;
- u32 ib_cal_ena = 0;
u32 ib1_tsdet = 0;
u32 ob_lev = 0;
u32 ob_ena_cas = 0;
@@ -381,7 +380,6 @@ static void serdes6g_setup(void __iomem *base, uint32_t
addr,
case PHY_INTERFACE_MODE_SGMII:
ib_if_mode = 1;
ib_qrate = 1;
- ib_cal_ena = 1;
ib1_tsdet = 3;
ob_lev = 48;
ob_ena_cas = 2;
@@ -404,6 +402,12 @@ static void serdes6g_setup(void __iomem *base, uint32_t
addr,
if (interface == PHY_INTERFACE_MODE_QSGMII)
writel(0xfff, base + HSIO_HW_CFGSTAT_HW_CFG);
+ writel(HSIO_ANA_SERDES6G_OB_CFG_RESISTOR_CTRL(1) |
+ HSIO_ANA_SERDES6G_OB_CFG_SR(7) |
+ HSIO_ANA_SERDES6G_OB_CFG_SR_H |
+ HSIO_ANA_SERDES6G_OB_CFG_ENA1V_MODE(ob_ena1v_mode) |
+ HSIO_ANA_SERDES6G_OB_CFG_POL, base + HSIO_ANA_SERDES6G_OB_CFG);
+
writel(HSIO_ANA_SERDES6G_COMMON_CFG_IF_MODE(3),
base + HSIO_ANA_SERDES6G_COMMON_CFG);
writel(HSIO_ANA_SERDES6G_PLL_CFG_FSM_CTRL_DATA(120) |
@@ -433,6 +437,21 @@ static void serdes6g_setup(void __iomem *base, uint32_t
addr,
HSIO_ANA_SERDES6G_IB_CFG1_TSDET(3) |
HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(8),
base + HSIO_ANA_SERDES6G_IB_CFG1);
+
+ writel(HSIO_ANA_SERDES6G_IB_CFG2_UREG(4) |
+ HSIO_ANA_SERDES6G_IB_CFG2_UMAX(2) |
+ HSIO_ANA_SERDES6G_IB_CFG2_TCALV(12) |
+ HSIO_ANA_SERDES6G_IB_CFG2_OCALS(32) |
+ HSIO_ANA_SERDES6G_IB_CFG2_OINFS(7) |
+ HSIO_ANA_SERDES6G_IB_CFG2_OINFI(0x1f) |
+ HSIO_ANA_SERDES6G_IB_CFG2_TINFV(3),
+ base + HSIO_ANA_SERDES6G_IB_CFG2);
+
+ writel(HSIO_ANA_SERDES6G_IB_CFG3_INI_OFFSET(0x1f) |
+ HSIO_ANA_SERDES6G_IB_CFG3_INI_LP(1) |
+ HSIO_ANA_SERDES6G_IB_CFG3_INI_MID(0x1f),
+ base + HSIO_ANA_SERDES6G_IB_CFG3);
+
writel(HSIO_DIG_SERDES6G_MISC_CFG_LANE_RST,
base + HSIO_DIG_SERDES6G_MISC_CFG);
@@ -507,7 +526,7 @@ static void serdes6g_setup(void __iomem *base, uint32_t
addr,
writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
- HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(ib_cal_ena) |
+ HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(1) |
HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
@@ -532,7 +551,7 @@ static void serdes6g_setup(void __iomem *base, uint32_t
addr,
writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
- HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(ib_cal_ena) |
+ HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(1) |
HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
--
2.30.1
[PATCH 0/2] net: jr2: Fix for jr2 switch
This patch series contains two patches. The first patch resets the switch at probe time while the second one fixes an issue with the serdes6g configuration which is used on jr2_pcb111 board Horatiu Vultur (2): net: jr2: Reset switch net: jr2: Fix Serdes6G configuration arch/mips/dts/mscc,jr2.dtsi | 6 ++-- drivers/net/mscc_eswitch/jr2_switch.c | 43 +++ 2 files changed, 42 insertions(+), 7 deletions(-) -- 2.30.1
[PATCH 1/2] net: jr2: Reset switch
Make sure to reset the switch core at probe time.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/mscc,jr2.dtsi | 6 --
drivers/net/mscc_eswitch/jr2_switch.c | 16 +++-
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi
index c44e9a2b3a..87db7cae9c 100644
--- a/arch/mips/dts/mscc,jr2.dtsi
+++ b/arch/mips/dts/mscc,jr2.dtsi
@@ -243,7 +243,9 @@
<0x017d 0x1>, // QFWD
<0x0102 0x2>, // QS
<0x017e 0x1>, // QSYS
- <0x01b0 0x8>; // REW
+ <0x01b0 0x8>, // REW
+ <0x0101 0x100>,// GCB
+ <0x 0x100>;// ICPU
reg-names = "port0", "port1", "port2", "port3", "port4",
"port5", "port6", "port7", "port8", "port9",
"port10", "port11", "port12", "port13",
@@ -257,7 +259,7 @@
"port42", "port43", "port44", "port45",
"port46", "port47", "ana_ac", "ana_cl",
"ana_l2", "asm", "hsio", "lrn", "qfwd",
- "qs", "qsys", "rew";
+ "qs", "qsys", "rew", "gcb", "icpu";
status = "okay";
ethernet-ports {
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c
b/drivers/net/mscc_eswitch/jr2_switch.c
index 128d7f21ce..9ba6ccc1bb 100644
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -235,7 +235,7 @@ static const char * const regs_names[] = {
"port36", "port37", "port38", "port39", "port40", "port41", "port42",
"port43", "port44", "port45", "port46", "port47",
"ana_ac", "ana_cl", "ana_l2", "asm", "hsio", "lrn",
- "qfwd", "qs", "qsys", "rew",
+ "qfwd", "qs", "qsys", "rew", "gcb", "icpu",
};
#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
@@ -252,6 +252,8 @@ enum jr2_ctrl_regs {
QS,
QSYS,
REW,
+ GCB,
+ ICPU,
};
#define JR2_MIIM_BUS_COUNT 3
@@ -850,6 +852,7 @@ static int jr2_probe(struct udevice *dev)
struct mii_dev *bus;
struct ofnode_phandle_args phandle;
struct phy_device *phy;
+ u32 val;
if (!priv)
return -EINVAL;
@@ -865,6 +868,17 @@ static int jr2_probe(struct udevice *dev)
}
}
+ val = readl(priv->regs[ICPU] + ICPU_RESET);
+ val |= ICPU_RESET_CORE_RST_PROTECT;
+ writel(val, priv->regs[ICPU] + ICPU_RESET);
+
+ val = readl(priv->regs[GCB] + PERF_SOFT_RST);
+ val |= PERF_SOFT_RST_SOFT_SWC_RST;
+ writel(val, priv->regs[GCB] + PERF_SOFT_RST);
+
+ while (readl(priv->regs[GCB] + PERF_SOFT_RST) &
PERF_SOFT_RST_SOFT_SWC_RST)
+ ;
+
/* Initialize miim buses */
memset(, 0x0, sizeof(struct mscc_miim_dev) * JR2_MIIM_BUS_COUNT);
--
2.30.1
Re: [U-Boot] [PATCH] net: mscc: serval: Remove delay when serdes is configured
Hi, I just wanted to give you a gentle ping. Thanks. The 06/01/2019 20:10, Daniel Schwierzeck wrote: > External E-Mail > > > > Am 23.05.19 um 21:45 schrieb Horatiu Vultur: > > When serdes configuration was written in hardware there was a delay > > of 100ms to be sure that configuration was written. But the delay is not > > needed because already the function serdes_write it is checking that the > > operation finished. > > > > Therefore remove the mdelay. This improves the speed of configuring the > > network driver. > > > > Signed-off-by: Horatiu Vultur > > --- > > drivers/net/mscc_eswitch/serval_switch.c | 2 -- > > 1 file changed, 2 deletions(-) > > > > Reviewed-by: Daniel Schwierzeck > > -- > - Daniel -- /Horatiu ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RESEND Patch] net: mscc: refactor mscc_miim
Because all MSCC SoC use the same MDIO bus, put the implementation in
one common file(mscc_miim) and make all the other MSCC network drivers to
use these functions.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/Makefile | 10 +--
drivers/net/mscc_eswitch/jr2_switch.c | 119 ++
drivers/net/mscc_eswitch/luton_switch.c | 101 +
drivers/net/mscc_eswitch/mscc_miim.c | 28 +++
drivers/net/mscc_eswitch/mscc_miim.h | 14 +++-
drivers/net/mscc_eswitch/ocelot_switch.c | 104 +-
drivers/net/mscc_eswitch/serval_switch.c | 101 +
drivers/net/mscc_eswitch/servalt_switch.c | 102 +
8 files changed, 63 insertions(+), 516 deletions(-)
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
index 02f39a7..d583fe9 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,6 +1,6 @@
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o
mscc_mac_table.o
-obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o
-obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o
-obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o
-obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o
mscc_mac_table.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o
mscc_mac_table.o mscc_miim.o
+obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o
mscc_miim.o
+obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o mscc_miim.o
+obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o mscc_miim.o
+obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o
mscc_mac_table.o mscc_miim.o
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c
b/drivers/net/mscc_eswitch/jr2_switch.c
index 60d408f..6655177 100644
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -17,20 +17,7 @@
#include
#include "mscc_xfer.h"
-
-#define GCB_MIIM_MII_STATUS0x0
-#defineGCB_MIIM_STAT_BUSY BIT(3)
-#define GCB_MIIM_MII_CMD 0x8
-#defineGCB_MIIM_MII_CMD_SCAN BIT(0)
-#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
-#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2)
-#defineGCB_MIIM_MII_CMD_SINGLE_SCANBIT(3)
-#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
-#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
-#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
-#defineGCB_MIIM_MII_CMD_VLDBIT(31)
-#define GCB_MIIM_DATA 0xC
-#defineGCB_MIIM_DATA_ERROR (0x3 << 16)
+#include "mscc_miim.h"
#define ANA_AC_RAM_CTRL_RAM_INIT 0x94358
#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x94370
@@ -279,13 +266,6 @@ struct jr2_private {
struct jr2_phy_port_t ports[MAX_PORT];
};
-struct jr2_miim_dev {
- void __iomem *regs;
- phys_addr_t miim_base;
- unsigned long miim_size;
- struct mii_dev *bus;
-};
-
static const unsigned long jr2_regs_qs[] = {
[MSCC_QS_XTR_RD] = 0x8,
[MSCC_QS_XTR_FLUSH] = 0x18,
@@ -294,99 +274,9 @@ static const unsigned long jr2_regs_qs[] = {
[MSCC_QS_INJ_CTRL] = 0x34,
};
-static struct jr2_miim_dev miim[JR2_MIIM_BUS_COUNT];
+static struct mscc_miim_dev miim[JR2_MIIM_BUS_COUNT];
static int miim_count = -1;
-static int mscc_miim_wait_ready(struct jr2_miim_dev *miim)
-{
- unsigned long deadline;
- u32 val;
-
- deadline = timer_get_us() + 25;
-
- do {
- val = readl(miim->regs + GCB_MIIM_MII_STATUS);
- } while (timer_get_us() <= deadline && (val & GCB_MIIM_STAT_BUSY));
-
- if (val & GCB_MIIM_STAT_BUSY)
- return -ETIMEDOUT;
-
- return 0;
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct jr2_miim_dev *miim = (struct jr2_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
- miim->regs + GCB_MIIM_MII_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + GCB_MIIM_DATA);
- if (val & GCB_MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0x;
- out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
-
[U-Boot] [PATCH] net: mscc: serval: Remove delay when serdes is configured
When serdes configuration was written in hardware there was a delay
of 100ms to be sure that configuration was written. But the delay is not
needed because already the function serdes_write it is checking that the
operation finished.
Therefore remove the mdelay. This improves the speed of configuring the
network driver.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/serval_switch.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/mscc_eswitch/serval_switch.c
b/drivers/net/mscc_eswitch/serval_switch.c
index 2559f5d..2c30941 100644
--- a/drivers/net/mscc_eswitch/serval_switch.c
+++ b/drivers/net/mscc_eswitch/serval_switch.c
@@ -356,8 +356,6 @@ static void serdes_write(void __iomem *base, u32 addr)
do {
data = readl(base + HSIO_MCB_SERDES1G_CFG);
} while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
-
- mdelay(100);
}
static void serdes1g_setup(void __iomem *base, uint32_t addr,
--
2.7.4
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[U-Boot] [PATCH] net: mscc: refactor mscc_miim
Because all MSCC SoC use the same MDIO bus, put the implementation in
one common file(mscc_miim) and make all the other MSCC network drivers to
use these functions.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/Makefile | 10 +--
drivers/net/mscc_eswitch/jr2_switch.c | 119 ++
drivers/net/mscc_eswitch/luton_switch.c | 101 +
drivers/net/mscc_eswitch/mscc_miim.c | 28 +++
drivers/net/mscc_eswitch/mscc_miim.h | 14 +++-
drivers/net/mscc_eswitch/ocelot_switch.c | 104 +-
drivers/net/mscc_eswitch/serval_switch.c | 101 +
drivers/net/mscc_eswitch/servalt_switch.c | 102 +
8 files changed, 63 insertions(+), 516 deletions(-)
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
index 02f39a7..d583fe9 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,6 +1,6 @@
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o
mscc_mac_table.o
-obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o
-obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o
-obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o
-obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o
mscc_mac_table.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o
mscc_mac_table.o mscc_miim.o
+obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o
mscc_miim.o
+obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o mscc_miim.o
+obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o mscc_miim.o
+obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o
mscc_mac_table.o mscc_miim.o
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c
b/drivers/net/mscc_eswitch/jr2_switch.c
index 60d408f..6655177 100644
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -17,20 +17,7 @@
#include
#include "mscc_xfer.h"
-
-#define GCB_MIIM_MII_STATUS0x0
-#defineGCB_MIIM_STAT_BUSY BIT(3)
-#define GCB_MIIM_MII_CMD 0x8
-#defineGCB_MIIM_MII_CMD_SCAN BIT(0)
-#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
-#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2)
-#defineGCB_MIIM_MII_CMD_SINGLE_SCANBIT(3)
-#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
-#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
-#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
-#defineGCB_MIIM_MII_CMD_VLDBIT(31)
-#define GCB_MIIM_DATA 0xC
-#defineGCB_MIIM_DATA_ERROR (0x3 << 16)
+#include "mscc_miim.h"
#define ANA_AC_RAM_CTRL_RAM_INIT 0x94358
#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x94370
@@ -279,13 +266,6 @@ struct jr2_private {
struct jr2_phy_port_t ports[MAX_PORT];
};
-struct jr2_miim_dev {
- void __iomem *regs;
- phys_addr_t miim_base;
- unsigned long miim_size;
- struct mii_dev *bus;
-};
-
static const unsigned long jr2_regs_qs[] = {
[MSCC_QS_XTR_RD] = 0x8,
[MSCC_QS_XTR_FLUSH] = 0x18,
@@ -294,99 +274,9 @@ static const unsigned long jr2_regs_qs[] = {
[MSCC_QS_INJ_CTRL] = 0x34,
};
-static struct jr2_miim_dev miim[JR2_MIIM_BUS_COUNT];
+static struct mscc_miim_dev miim[JR2_MIIM_BUS_COUNT];
static int miim_count = -1;
-static int mscc_miim_wait_ready(struct jr2_miim_dev *miim)
-{
- unsigned long deadline;
- u32 val;
-
- deadline = timer_get_us() + 25;
-
- do {
- val = readl(miim->regs + GCB_MIIM_MII_STATUS);
- } while (timer_get_us() <= deadline && (val & GCB_MIIM_STAT_BUSY));
-
- if (val & GCB_MIIM_STAT_BUSY)
- return -ETIMEDOUT;
-
- return 0;
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct jr2_miim_dev *miim = (struct jr2_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
- miim->regs + GCB_MIIM_MII_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + GCB_MIIM_DATA);
- if (val & GCB_MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0x;
- out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
-
Re: [U-Boot] [PATCH 1/3] net: mscc: luton: Update network driver for pcb90
Hi Joe,
The 05/09/2019 21:03, Joe Hershberger wrote:
> External E-Mail
>
>
> On Wed, May 1, 2019 at 6:18 AM Horatiu Vultur
> wrote:
> >
> > Update Luton network driver to have support also for pcb90. The pcb90
> > has 24 ports from which 12 ports are connected to SerDes6G.
>
> Can you separate this into a restructuring patch and the patch that
> adds support for this device? This is a bit hard to read.
Well the patch was already applied on the master. So I am not
sure what I can do.
>
> Thanks,
> -Joe
>
> >
> > Signed-off-by: Horatiu Vultur
> > ---
> > drivers/net/mscc_eswitch/Makefile | 2 +-
> > drivers/net/mscc_eswitch/luton_switch.c | 415
> >
> > 2 files changed, 258 insertions(+), 159 deletions(-)
> >
> > diff --git a/drivers/net/mscc_eswitch/Makefile
> > b/drivers/net/mscc_eswitch/Makefile
> > index 9c208d1..02f39a7 100644
> > --- a/drivers/net/mscc_eswitch/Makefile
> > +++ b/drivers/net/mscc_eswitch/Makefile
> > @@ -1,6 +1,6 @@
> >
> > obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o
> > mscc_mac_table.o
> > -obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o
> > mscc_mac_table.o
> > +obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o
> > mscc_mac_table.o
> > obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o
> > obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o
> > obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o
> > mscc_mac_table.o
> > diff --git a/drivers/net/mscc_eswitch/luton_switch.c
> > b/drivers/net/mscc_eswitch/luton_switch.c
> > index 6667614..94852b0 100644
> > --- a/drivers/net/mscc_eswitch/luton_switch.c
> > +++ b/drivers/net/mscc_eswitch/luton_switch.c
> > @@ -15,10 +15,21 @@
> > #include
> > #include
> >
> > -#include "mscc_miim.h"
> > #include "mscc_xfer.h"
> > #include "mscc_mac_table.h"
> >
> > +#define GCB_MIIM_MII_STATUS0x0
> > +#defineGCB_MIIM_STAT_BUSY BIT(3)
> > +#define GCB_MIIM_MII_CMD 0x8
> > +#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
> > +#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2)
> > +#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
> > +#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
> > +#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
> > +#defineGCB_MIIM_MII_CMD_VLDBIT(31)
> > +#define GCB_MIIM_DATA 0xC
> > +#defineGCB_MIIM_DATA_ERROR (0x2 << 16)
> > +
> > #define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x))
> > #defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
> > #defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18)
> > @@ -136,61 +147,53 @@
> > #define PGID_UNICAST 29
> > #define PGID_SRC 80
> >
> > -enum luton_target {
> > - PORT0,
> > - PORT1,
> > - PORT2,
> > - PORT3,
> > - PORT4,
> > - PORT5,
> > - PORT6,
> > - PORT7,
> > - PORT8,
> > - PORT9,
> > - PORT10,
> > - PORT11,
> > - PORT12,
> > - PORT13,
> > - PORT14,
> > - PORT15,
> > - PORT16,
> > - PORT17,
> > - PORT18,
> > - PORT19,
> > - PORT20,
> > - PORT21,
> > - PORT22,
> > - PORT23,
> > - SYS,
> > +static const char * const regs_names[] = {
> > + "port0", "port1", "port2", "port3", "port4", "port5", "port6",
> > "port7",
> > + "port8", "port9", "port10", "port11", "port12", "port13", "port14",
> > + "port15", "port16", "port17", "port18", "port19", "port20",
> > "port21",
> > + "port22", "port23",
> > + "sys", "ana", "rew", "gcb", "qs", "hsio",
> > +};
> > +
> > +#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
> > +#define MAX_PORT 24
>
[U-Boot] [PATCH 3/3] net: mscc: ocelot: Update DTS for Luton pcb90
Update device tree for luton to add support for luton pcb90.
This pcb has 24 ports from which 12 ports are connected to
SerDes6G.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/luton_pcb090.dts| 228 +++---
arch/mips/dts/luton_pcb091.dts| 132 +---
arch/mips/dts/mscc,luton.dtsi | 126 +++
include/dt-bindings/mscc/luton_data.h | 17 +++
4 files changed, 307 insertions(+), 196 deletions(-)
create mode 100644 include/dt-bindings/mscc/luton_data.h
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index fe457ba..ea3e3b7 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "mscc,luton.dtsi"
+#include
/ {
model = "Luton26 PCB090 Reference Board";
@@ -57,52 +58,195 @@
{
status = "okay";
-};
-
- {
- phy-handle = <>;
-};
-
- {
- phy-handle = <>;
-};
-
- {
- phy-handle = <>;
-};
-
- {
- phy-handle = <>;
-};
-
- {
- phy-handle = <>;
-};
-
- {
- phy-handle = <>;
-};
-
- {
- phy-handle = <>;
-};
-
- {
- phy-handle = <>;
-};
- {
- phy-handle = <>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
};
- {
- phy-handle = <>;
-};
+ {
+ status = "okay";
- {
- phy-handle = <>;
+ phy12: ethernet-phy@12 {
+ reg = <0>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <1>;
+ };
+ phy14: ethernet-phy@14 {
+ reg = <2>;
+ };
+ phy15: ethernet-phy@15 {
+ reg = <3>;
+ };
+ phy16: ethernet-phy@16 {
+ reg = <4>;
+ };
+ phy17: ethernet-phy@17 {
+ reg = <5>;
+ };
+ phy18: ethernet-phy@18 {
+ reg = <6>;
+ };
+ phy19: ethernet-phy@19 {
+ reg = <7>;
+ };
+ phy20: ethernet-phy@20 {
+ reg = <8>;
+ };
+ phy21: ethernet-phy@21 {
+ reg = <9>;
+ };
+ phy22: ethernet-phy@22 {
+ reg = <10>;
+ };
+ phy23: ethernet-phy@23 {
+ reg = <11>;
+ };
};
- {
- phy-handle = <>;
+ {
+ ethernet-ports {
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ phy-handle = <>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ phy-handle = <>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ phy-handle = <>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ phy-handle = <>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ phy-handle = <>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ phy-handle = <>;
+ };
+ port8: port@8 {
+ reg = <8>;
+ phy-handle = <>;
+ };
+ port9: port@9 {
+ reg = <9>;
+ phy-handle = <>;
+ };
+ port10: port@10 {
+ reg = <10>;
+ phy-handle = <>;
+ };
+ port11: port@11 {
+ reg = <11>;
+ phy-handle = &l
[U-Boot] [PATCH 2/3] board: mscc: luton: Update MSCC Luton board
Implement method board_phy_config to configure the external phys
on the pcb90.
Signed-off-by: Horatiu Vultur
---
board/mscc/luton/luton.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
index 807c717..114f7fd 100644
--- a/board/mscc/luton/luton.c
+++ b/board/mscc/luton/luton.c
@@ -6,8 +6,7 @@
#include
#include
#include
-
-DECLARE_GLOBAL_DATA_PTR;
+#include
enum {
BOARD_TYPE_PCB090 = 0xAABBCD00,
@@ -36,6 +35,16 @@ int board_early_init_r(void)
return 0;
}
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80A0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 31, 0);
+ return 0;
+}
+
static void do_board_detect(void)
{
u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0x;
--
2.7.4
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[U-Boot] [PATCH 0/3] Update Luton network driver
Update Luton network driver to add support for all the ports on pcb90. The existing support is only for first 12 ports, with this patch adds support for another 12 ports. This patch series is based on u-boot-mips/master. Horatiu Vultur (3): net: mscc: luton: Update network driver for pcb90 board: mscc: luton: Update MSCC Luton board net: mscc: ocelot: Update DTS for Luton pcb90 arch/mips/dts/luton_pcb090.dts | 228 ++ arch/mips/dts/luton_pcb091.dts | 132 ++ arch/mips/dts/mscc,luton.dtsi | 126 ++ board/mscc/luton/luton.c| 13 +- drivers/net/mscc_eswitch/Makefile | 2 +- drivers/net/mscc_eswitch/luton_switch.c | 415 include/dt-bindings/mscc/luton_data.h | 17 ++ 7 files changed, 576 insertions(+), 357 deletions(-) create mode 100644 include/dt-bindings/mscc/luton_data.h -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/3] net: mscc: luton: Update network driver for pcb90
Update Luton network driver to have support also for pcb90. The pcb90
has 24 ports from which 12 ports are connected to SerDes6G.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/Makefile | 2 +-
drivers/net/mscc_eswitch/luton_switch.c | 415
2 files changed, 258 insertions(+), 159 deletions(-)
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
index 9c208d1..02f39a7 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,6 +1,6 @@
obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o
mscc_mac_table.o
-obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o
mscc_mac_table.o
+obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o
obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o
obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o
obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o
mscc_mac_table.o
diff --git a/drivers/net/mscc_eswitch/luton_switch.c
b/drivers/net/mscc_eswitch/luton_switch.c
index 6667614..94852b0 100644
--- a/drivers/net/mscc_eswitch/luton_switch.c
+++ b/drivers/net/mscc_eswitch/luton_switch.c
@@ -15,10 +15,21 @@
#include
#include
-#include "mscc_miim.h"
#include "mscc_xfer.h"
#include "mscc_mac_table.h"
+#define GCB_MIIM_MII_STATUS0x0
+#defineGCB_MIIM_STAT_BUSY BIT(3)
+#define GCB_MIIM_MII_CMD 0x8
+#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
+#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2)
+#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
+#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
+#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
+#defineGCB_MIIM_MII_CMD_VLDBIT(31)
+#define GCB_MIIM_DATA 0xC
+#defineGCB_MIIM_DATA_ERROR (0x2 << 16)
+
#define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x))
#defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
#defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18)
@@ -136,61 +147,53 @@
#define PGID_UNICAST 29
#define PGID_SRC 80
-enum luton_target {
- PORT0,
- PORT1,
- PORT2,
- PORT3,
- PORT4,
- PORT5,
- PORT6,
- PORT7,
- PORT8,
- PORT9,
- PORT10,
- PORT11,
- PORT12,
- PORT13,
- PORT14,
- PORT15,
- PORT16,
- PORT17,
- PORT18,
- PORT19,
- PORT20,
- PORT21,
- PORT22,
- PORT23,
- SYS,
+static const char * const regs_names[] = {
+ "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10", "port11", "port12", "port13", "port14",
+ "port15", "port16", "port17", "port18", "port19", "port20", "port21",
+ "port22", "port23",
+ "sys", "ana", "rew", "gcb", "qs", "hsio",
+};
+
+#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
+#define MAX_PORT 24
+
+enum luton_ctrl_regs {
+ SYS = MAX_PORT,
ANA,
REW,
GCB,
QS,
- HSIO,
- TARGET_MAX,
+ HSIO
};
-#define MAX_PORT (PORT23 - PORT0 + 1)
+#define MIN_INT_PORT 0
+#define PORT10 10
+#define PORT11 11
+#define MAX_INT_PORT 12
+#define MIN_EXT_PORT MAX_INT_PORT
+#define MAX_EXT_PORT MAX_PORT
-#define MIN_INT_PORT PORT0
-#define MAX_INT_PORT (PORT11 - PORT0 + 1)
-#define MIN_EXT_PORT PORT12
-#define MAX_EXT_PORT MAX_PORT
+#define LUTON_MIIM_BUS_COUNT 2
-enum luton_mdio_target {
- MIIM,
- TARGET_MDIO_MAX,
+struct luton_phy_port_t {
+ size_t phy_addr;
+ struct mii_dev *bus;
+ u8 serdes_index;
+ u8 phy_mode;
};
-enum luton_phy_id {
- INTERNAL,
- EXTERNAL,
- NUM_PHY,
+struct luton_private {
+ void __iomem *regs[REGS_NAMES_COUNT];
+ struct mii_dev *bus[LUTON_MIIM_BUS_COUNT];
+ struct luton_phy_port_t ports[MAX_PORT];
};
-struct luton_private {
- void __iomem *regs[TARGET_MAX];
- struct mii_dev *bus[NUM_PHY];
+struct mscc_miim_dev {
+ void __iomem *regs;
+ phys_addr_t miim_base;
+ unsigned long miim_size;
+ struct mii_dev *bus;
};
static const unsigned long luton_regs_qs[] = {
@@ -207,53 +210,85 @@ static const unsigned long luton_regs_ana_table[] = {
[MSCC_ANA_TABLES
[U-Boot] [PATCH] arch: mips: Update initrd_start and initrd_end
Microsemi SoC defines CONFIG_SYS_SDRAM_BASE to be 0x8000, which
represents the start of kseg0 and represents a virtual address. Meaning
that the initrd_start and initrd_end point somewhere kseg0.
When these parameters are passed to linux kernel through DT
they are pointing somewhere in kseg0 which is a virtual address but linux
kernel expects the addresses to be physical addresses(in kuseg) because
it is converting the physical address to a virtual one.
Therefore update the uboot to pass the physical address of initrd_start
and initrd_end by converting them using the function virt_to_phys before
setting up the DT.
Signed-off-by: Horatiu Vultur
---
arch/mips/lib/bootm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 35152cb..6a462f3 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -247,6 +247,8 @@ int arch_fixup_fdt(void *blob)
static int boot_setup_fdt(bootm_headers_t *images)
{
+ images->initrd_start = virt_to_phys((void *)images->initrd_start);
+ images->initrd_end = virt_to_phys((void *)images->initrd_end);
return image_setup_libfdt(images, images->ft_addr, images->ft_len,
>lmb);
}
--
2.7.4
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[U-Boot] [PATCH 1/3] net: mscc: ocelot: Update network driver for pcb120
Update Ocelot network driver to have support also for pcb120. Signed-off-by: Horatiu Vultur --- .../include/mach/ocelot/ocelot_devcpu_gcb.h| 1 + drivers/net/mscc_eswitch/Makefile | 2 +- drivers/net/mscc_eswitch/ocelot_switch.c | 434 - 3 files changed, 338 insertions(+), 99 deletions(-) diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h index d3a7641..b2a4203 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h @@ -20,4 +20,5 @@ #define GPIO_ALT(x)(0x54 + 4 * (x)) +#define PERF_PHY_CFG 0xf0 #endif diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index 6aa59ef..9c208d1 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -1,5 +1,5 @@ -obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o +obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c index 815c2da..5c7e696 100644 --- a/drivers/net/mscc_eswitch/ocelot_switch.c +++ b/drivers/net/mscc_eswitch/ocelot_switch.c @@ -15,7 +15,6 @@ #include #include -#include "mscc_miim.h" #include "mscc_xfer.h" #include "mscc_mac_table.h" @@ -26,6 +25,20 @@ #define PHY_STAT 0x4 #define PHY_STAT_SUPERVISOR_COMPLETE BIT(0) +#define GCB_MIIM_MII_STATUS0x0 +#defineGCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#defineGCB_MIIM_MII_CMD_SCAN BIT(0) +#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2) +#defineGCB_MIIM_MII_CMD_SINGLE_SCANBIT(3) +#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#defineGCB_MIIM_MII_CMD_VLDBIT(31) +#define GCB_MIIM_DATA 0xC +#defineGCB_MIIM_DATA_ERROR (0x3 << 16) + #define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x)) #defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) #defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18) @@ -33,6 +46,41 @@ #defineANA_PORT_PORT_CFG_RECV_ENA BIT(6) #define ANA_PGID(x)(0x8c00 + 4 * (x)) +#define HSIO_ANA_SERDES1G_DES_CFG 0x4c +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << 1) +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#defineHSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES1G_IB_CFG 0x50 +#defineHSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) +#defineHSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24) +#define HSIO_ANA_SERDES1G_OB_CFG 0x54 +#defineHSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << 4) +#defineHSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10) +#defineHSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << 13) +#defineHSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17) +#define HSIO_ANA_SERDES1G_SER_CFG 0x58 +#define HSIO_ANA_SERDES1G_COMMON_CFG 0x5c +#defineHSIO_ANA_SERDES1G_COMMON_CFG_IF_MODEBIT(0) +#defineHSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) +#defineHSIO_ANA_SERDES1G_COMMON_CFG_SYS_RSTBIT(31) +#define HSIO_ANA_SERDES1G_PLL_CFG 0x60 +#defineHSIO_ANA_SERDES1G_PLL_CFG_F
[U-Boot] [PATCH 3/3] net: mscc: ocelot: Update DTS for Ocelot pcb120.
Update device tree for ocelot to add support for ocelot pcb120.
Signed-off-by: Horatiu Vultur
---
MAINTAINERS| 1 +
arch/mips/dts/mscc,ocelot.dtsi | 109 +
arch/mips/dts/ocelot_pcb120.dts| 75 +++
arch/mips/dts/ocelot_pcb123.dts| 44 +
include/dt-bindings/mscc/ocelot_data.h | 19 ++
5 files changed, 167 insertions(+), 81 deletions(-)
create mode 100644 include/dt-bindings/mscc/ocelot_data.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c77abba..a6e40be 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -568,6 +568,7 @@ F: configs/mscc*
F: drivers/gpio/mscc_sgpio.c
F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
+F: include/dt-bindings/mscc/
F: drivers/pinctrl/mscc/
F: drivers/net/mscc_eswitch/
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 4f3fe35..9a187b6 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -112,32 +112,33 @@
status = "disabled";
};
- switch@101 {
+ switch: switch@101 {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
compatible = "mscc,vsc7514-switch";
- reg = <0x101 0x1>, /* VTSS_TO_SYS */
- <0x103 0x1>, /* VTSS_TO_REW */
- <0x108 0x100>, /* VTSS_TO_DEVCPU_QS */
- <0x10d 0x1>, /* VTSS_TO_HSIO */
- <0x11e 0x100>, /* VTSS_TO_DEV_0 */
- <0x11f 0x100>, /* VTSS_TO_DEV_1 */
- <0x120 0x100>, /* VTSS_TO_DEV_2 */
- <0x121 0x100>, /* VTSS_TO_DEV_3 */
- <0x122 0x100>, /* VTSS_TO_DEV_4 */
- <0x123 0x100>, /* VTSS_TO_DEV_5 */
- <0x124 0x100>, /* VTSS_TO_DEV_6 */
- <0x125 0x100>, /* VTSS_TO_DEV_7 */
- <0x126 0x100>, /* VTSS_TO_DEV_8 */
- <0x127 0x100>, /* NA */
- <0x128 0x100>, /* NA */
- <0x180 0x8>, /* VTSS_TO_QSYS */
- <0x188 0x1>; /* VTSS_TO_ANA */
- reg-names = "sys", "rew", "qs", "hsio", "port0",
- "port1", "port2", "port3", "port4", "port5",
- "port6", "port7", "port8", "port9",
- "port10", "qsys", "ana";
+
+ reg = <0x11e 0x100>, // VTSS_TO_DEV_0
+ <0x11f 0x100>, // VTSS_TO_DEV_1
+ <0x120 0x100>, // VTSS_TO_DEV_2
+ <0x121 0x100>, // VTSS_TO_DEV_3
+ <0x122 0x100>, // VTSS_TO_DEV_4
+ <0x123 0x100>, // VTSS_TO_DEV_5
+ <0x124 0x100>, // VTSS_TO_DEV_6
+ <0x125 0x100>, // VTSS_TO_DEV_7
+ <0x126 0x100>, // VTSS_TO_DEV_8
+ <0x127 0x100>, // VTSS_TO_DEV_9
+ <0x128 0x100>, // VTSS_TO_DEV_10
+ <0x101 0x1>, // VTSS_TO_SYS
+ <0x103 0x1>, // VTSS_TO_REW
+ <0x108 0x100>, // VTSS_TO_DEVCPU_QS
+ <0x10d 0x1>, // VTSS_TO_HSIO
+ <0x180 0x8>,// VTSS_TO_QSYS
+ <0x188 0x1>;// VTSS_TO_ANA
+ reg-names = "port0", "port1", "port2", "port3", "port4",
+ "port5", "port6", "port7", "port8", "port9",
+ "port10",
+ "sys", "rew", "qs", "hsio", "qsys", "ana";
interrupts = <21 22>;
interrupt-names = "xtr", "inj";
status = "okay";
[U-Boot] [PATCH 0/3] Update Ocelot network driver.
Update Ocelot network driver to add support for pcb120. This patch series is based on u-boot-mips/master. Horatiu Vultur (3): net: mscc: ocelot: Update network driver for pcb120 board: mscc: ocelot: Update MSCC Ocelot board. net: mscc: ocelot: Update DTS for Ocelot pcb120. MAINTAINERS| 1 + arch/mips/dts/mscc,ocelot.dtsi | 109 ++ arch/mips/dts/ocelot_pcb120.dts| 75 arch/mips/dts/ocelot_pcb123.dts| 44 ++- .../include/mach/ocelot/ocelot_devcpu_gcb.h| 1 + board/mscc/ocelot/ocelot.c | 15 + drivers/net/mscc_eswitch/Makefile | 2 +- drivers/net/mscc_eswitch/ocelot_switch.c | 434 - include/dt-bindings/mscc/ocelot_data.h | 19 + 9 files changed, 520 insertions(+), 180 deletions(-) create mode 100644 include/dt-bindings/mscc/ocelot_data.h -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/3] board: mscc: ocelot: Update MSCC Ocelot board.
Implement method board_phy_config to configure the phy for pcb120.
Signed-off-by: Horatiu Vultur
---
board/mscc/ocelot/ocelot.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 532d06f..bcae8fa 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,20 @@ void mscc_switch_reset(bool enter)
mscc_gpio_set_alternate(19, 0);
}
+int board_phy_config(struct phy_device *phydev)
+{
+ if (gd->board_type == BOARD_TYPE_PCB123)
+ return 0;
+
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80F0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 31, 0);
+
+ return 0;
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
--
2.7.4
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[U-Boot] [PATCH v2 2/2] board: mscc: serval: Fix board detect
When detecting the board, it was reading a register in the GPIO page of
the phy and based on that value it was making a decision. The bug was that
after the GPIO page for the first phy was set it was not reseted back.
Signed-off-by: Horatiu Vultur
---
board/mscc/serval/serval.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c
index 24ee5e5..ade041e 100644
--- a/board/mscc/serval/serval.c
+++ b/board/mscc/serval/serval.c
@@ -42,10 +42,10 @@ static void do_board_detect(void)
gd->board_type = BOARD_TYPE_PCB106;
else
gd->board_type = BOARD_TYPE_PCB105;
- mscc_phy_wr(1, 16, 15, 0);
} else {
gd->board_type = BOARD_TYPE_PCB105;
}
+ mscc_phy_wr(1, 16, 31, 0x0);
}
#if defined(CONFIG_MULTI_DTB_FIT)
--
2.7.4
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[U-Boot] [PATCH v2 1/2] mips: mscc: serval: Fix reset
In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.
Signed-off-by: Horatiu Vultur
---
arch/mips/mach-mscc/include/mach/ddr.h | 55 ++
arch/mips/mach-mscc/reset.c| 2 +-
2 files changed, 31 insertions(+), 26 deletions(-)
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h
b/arch/mips/mach-mscc/include/mach/ddr.h
index 84ecfbd..d1f4287 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -401,23 +401,7 @@ static inline void sleep_100ns(u32 val)
;
}
-#if defined(CONFIG_SOC_OCELOT)
-static inline void hal_vcoreiii_ddr_reset_assert(void)
-{
- /* DDR has reset pin on GPIO 19 toggle Low-High to release */
- setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
- writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
- sleep_100ns(1);
-}
-
-static inline void hal_vcoreiii_ddr_reset_release(void)
-{
- /* DDR has reset pin on GPIO 19 toggle Low-High to release */
- setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
- writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
- sleep_100ns(1);
-}
-
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
/*
* DDR memory sanity checking failed, tally and do hard reset
*
@@ -427,9 +411,11 @@ static inline void hal_vcoreiii_ddr_failed(void)
{
register u32 reset;
+#if defined(CONFIG_SOC_OCELOT)
writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6));
clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+#endif
/* We have to execute the reset function from cache. Indeed,
* the reboot workaround in _machine_restart() will change the
@@ -452,6 +438,33 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n");
}
+#else /* JR2 || ServalT */
+static inline void hal_vcoreiii_ddr_failed(void)
+{
+ writel(0, BASE_CFG + ICPU_RESET);
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
+
+ panic("DDR init failed\n");
+}
+#endif
+
+#if defined(CONFIG_SOC_OCELOT)
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+ /* DDR has reset pin on GPIO 19 toggle Low-High to release */
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
+ sleep_100ns(1);
+}
+
+static inline void hal_vcoreiii_ddr_reset_release(void)
+{
+ /* DDR has reset pin on GPIO 19 toggle Low-High to release */
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+ sleep_100ns(1);
+}
+
#else /* JR2 || ServalT || Serval */
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
@@ -463,14 +476,6 @@ static inline void hal_vcoreiii_ddr_reset_assert(void)
writel(readl(BASE_CFG + ICPU_RESET) |
ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET);
}
-
-static inline void hal_vcoreiii_ddr_failed(void)
-{
- writel(0, BASE_CFG + ICPU_RESET);
- writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
-
- panic("DDR init failed\n");
-}
#endif /* JR2 || ServalT || Serval */
/*
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
index a555fc9..a121457 100644
--- a/arch/mips/mach-mscc/reset.c
+++ b/arch/mips/mach-mscc/reset.c
@@ -36,7 +36,7 @@ void _machine_restart(void)
/* Do global reset */
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
- for (i = 0; i < 1000; i++)
+ for (i = 0; i < 2000; i++)
;
/* Power down DDR for clean DDR re-training */
--
2.7.4
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[U-Boot] [PATCH v2 0/2] Fix minor issues with Serval SoC.
This patch series fix different issues with Serval. - first patch fix resets when DDR training fails. - second patch fix the detection of the board. This patch series is based on u-boot-mips/next. v2-changes: - Update reset based on Daniel's comments Horatiu Vultur (2): mips: mscc: serval: Fix reset board: mscc: serval: Fix board detect arch/mips/mach-mscc/include/mach/ddr.h | 55 ++ arch/mips/mach-mscc/reset.c| 2 +- board/mscc/serval/serval.c | 2 +- 3 files changed, 32 insertions(+), 27 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/4] net: mscc: serval: Add ethernet nodes for Serval
Add ethernet nodes for Serval SoCs family. There are 2 pcb in this
family: pcb105 and pcb106.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/mscc,serval.dtsi | 58 ++
arch/mips/dts/serval_pcb105.dts| 44 ++
arch/mips/dts/serval_pcb106.dts| 44 ++
include/dt-bindings/mscc/serval_data.h | 19 +++
4 files changed, 165 insertions(+)
create mode 100644 include/dt-bindings/mscc/serval_data.h
diff --git a/arch/mips/dts/mscc,serval.dtsi b/arch/mips/dts/mscc,serval.dtsi
index bd60051..90eeebd 100644
--- a/arch/mips/dts/mscc,serval.dtsi
+++ b/arch/mips/dts/mscc,serval.dtsi
@@ -145,5 +145,63 @@
#gpio-cells = <2>;
gpio-ranges = < 0 0 64>;
};
+
+ switch: switch@011e {
+ compatible = "mscc,vsc7418-switch";
+ reg = <0x011e 0x0100>, // VTSS_TO_DEV0
+ <0x011f 0x0100>, // VTSS_TO_DEV1
+ <0x0120 0x0100>, // VTSS_TO_DEV2
+ <0x0121 0x0100>, // VTSS_TO_DEV3
+ <0x0122 0x0100>, // VTSS_TO_DEV4
+ <0x0123 0x0100>, // VTSS_TO_DEV5
+ <0x0124 0x0100>, // VTSS_TO_DEV6
+ <0x0125 0x0100>, // VTSS_TO_DEV7
+ <0x0126 0x0100>, // VTSS_TO_DEV8
+ <0x0127 0x0100>, // VTSS_TO_DEV9
+ <0x0128 0x0100>, // VTSS_TO_DEV10
+ <0x0190 0x10>, // ANA
+ <0x0108 0x2>, // QS
+ <0x0180 0x10>, // QSYS
+ <0x0103 0x1>, // REW
+ <0x0101 0x2>, // SYS
+ <0x010a 0x1>; // HSIO
+ reg-names = "port0", "port1", "port2", "port3",
+ "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10",
+ "ana", "qs", "qsys", "rew", "sys",
+ "hsio";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio0: mdio@0107005c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,serval-miim";
+ reg = <0x0107005c 0x24>;
+ status = "disabled";
+ };
+
+ mdio1: mdio@01070080 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,serval-miim";
+ reg = <0x01070080 0x24>;
+ status = "disabled";
+ };
+
+ hsio: syscon@10d {
+ compatible = "mscc,serval-hsio", "syscon", "simple-mfd";
+ reg = <0x10a 0x1>;
+
+ serdes_hsio: serdes_hsio {
+ compatible = "mscc,vsc7418-serdes";
+ #phy-cells = <3>;
+ };
+ };
};
};
diff --git a/arch/mips/dts/serval_pcb105.dts b/arch/mips/dts/serval_pcb105.dts
index d0d6fac..b58ec5e 100644
--- a/arch/mips/dts/serval_pcb105.dts
+++ b/arch/mips/dts/serval_pcb105.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "mscc,serval.dtsi"
+#include
/ {
model = "Serval PCB105 Reference Board";
@@ -54,3 +55,46 @@
status = "okay";
sgpio-ports = <0x00FF>;
};
+
+ {
+ status = "okay";
+
+ phy16: ethernet-phy@16 {
+ reg = <16>;
+ };
+ phy17: ethernet-phy@17 {
+ reg = <17>;
+ };
+ phy18: ethernet-phy@18 {
+ reg = <18>;
+ };
+ phy19: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+ {
+ ethernet-ports {
+
+ port0: port@0 {
+ reg = <7>;
+ phy-ha
[U-Boot] [PATCH 4/4] configs: mscc_serval: Add network support
Update default config to use network driver for Serval SoCs. Signed-off-by: Horatiu Vultur --- configs/mscc_serval_defconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig index f2c9563..444fefd 100644 --- a/configs/mscc_serval_defconfig +++ b/configs/mscc_serval_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NFS is not set CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)" @@ -62,3 +61,8 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_LZMA=y +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_MSCC_SERVAL_SWITCH=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/4] net: Add MSCC Serval network driver.
Add network driver for Microsemi Ethernet switch. It is present on Serval SoCs. Signed-off-by: Horatiu Vultur --- drivers/net/mscc_eswitch/Kconfig | 7 + drivers/net/mscc_eswitch/Makefile| 1 + drivers/net/mscc_eswitch/serval_switch.c | 703 +++ 3 files changed, 711 insertions(+) create mode 100644 drivers/net/mscc_eswitch/serval_switch.c diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 6359d0b..80dd22f 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -29,3 +29,10 @@ config MSCC_SERVALT_SWITCH select PHYLIB help This driver supports the Servalt network switch device. + +config MSCC_SERVAL_SWITCH + bool "Serval switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Serval network switch device. diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index bffd8ec..6aa59ef 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o +obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o mscc_mac_table.o diff --git a/drivers/net/mscc_eswitch/serval_switch.c b/drivers/net/mscc_eswitch/serval_switch.c new file mode 100644 index 000..2559f5d --- /dev/null +++ b/drivers/net/mscc_eswitch/serval_switch.c @@ -0,0 +1,703 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mscc_xfer.h" +#include "mscc_mac_table.h" + +#define GCB_MIIM_MII_STATUS0x0 +#defineGCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2) +#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#defineGCB_MIIM_MII_CMD_VLDBIT(31) +#define GCB_MIIM_DATA 0xC +#defineGCB_MIIM_DATA_ERROR (0x2 << 16) + +#define ANA_PORT_VLAN_CFG(x) (0xc000 + 0x100 * (x)) +#defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) +#defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18) +#define ANA_PORT_PORT_CFG(x) (0xc070 + 0x100 * (x)) +#defineANA_PORT_PORT_CFG_RECV_ENA BIT(6) +#define ANA_PGID(x)(0x9c00 + 4 * (x)) + +#define HSIO_ANA_SERDES1G_DES_CFG 0x3c +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << 1) +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#defineHSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES1G_IB_CFG 0x40 +#defineHSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) +#defineHSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19) +#defineHSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24) +#define HSIO_ANA_SERDES1G_OB_CFG 0x44 +#defineHSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << 4) +#defineHSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10) +#defineHSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << 13) +#defineHSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17) +#define HSIO_ANA_SERDES1G_SER_CFG 0x48 +#define HSIO_ANA_SERDES1G_COMMON_CFG 0x4c +#defineHSIO_ANA_
[U-Boot] [PATCH 2/4] board: mscc: serval: Update MSCC Serval boards
In Serval SoC family there are 2 different pcb, both of them have the same
phy, but with different version. Therefore implement board_phy_config
and set all the phys in the same way.
Signed-off-by: Horatiu Vultur
---
board/mscc/serval/serval.c | 12
1 file changed, 12 insertions(+)
diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c
index ade041e..da7f556 100644
--- a/board/mscc/serval/serval.c
+++ b/board/mscc/serval/serval.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
enum {
BOARD_TYPE_PCB106 = 0xAABBCD00,
@@ -27,6 +28,17 @@ int board_early_init_r(void)
return 0;
}
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80F0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 14, 0x800);
+ phy_write(phydev, 0, 31, 0);
+ return 0;
+}
+
static void do_board_detect(void)
{
u16 gpio_in_reg;
--
2.7.4
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[U-Boot] [PATCH 0/4] Add network support for Serval SoCs.
This patch series add network support for Serval SoCs family. There are the following pcb: Serval-nid(pcb106), Serval-ref (pcb105). Horatiu Vultur (4): net: Add MSCC Serval network driver. board: mscc: serval: Update MSCC Serval boards net: mscc: serval: Add ethernet nodes for Serval configs: mscc_serval: Add network support arch/mips/dts/mscc,serval.dtsi | 58 +++ arch/mips/dts/serval_pcb105.dts | 44 ++ arch/mips/dts/serval_pcb106.dts | 44 ++ board/mscc/serval/serval.c | 12 + configs/mscc_serval_defconfig| 6 +- drivers/net/mscc_eswitch/Kconfig | 7 + drivers/net/mscc_eswitch/Makefile| 1 + drivers/net/mscc_eswitch/serval_switch.c | 703 +++ include/dt-bindings/mscc/serval_data.h | 19 + 9 files changed, 893 insertions(+), 1 deletion(-) create mode 100644 drivers/net/mscc_eswitch/serval_switch.c create mode 100644 include/dt-bindings/mscc/serval_data.h -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] mips: mscc: serval: Fix reset
In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.
Signed-off-by: Horatiu Vultur
---
arch/mips/mach-mscc/include/mach/ddr.h | 14 ++
arch/mips/mach-mscc/reset.c| 5 +
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h
b/arch/mips/mach-mscc/include/mach/ddr.h
index 84ecfbd..97dac3e 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -464,6 +464,19 @@ static inline void hal_vcoreiii_ddr_reset_assert(void)
ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET);
}
+#if defined(CONFIG_SOC_SERVAL)
+static inline void hal_vcoreiii_ddr_failed(void)
+{
+ register u32 reset;
+
+ pr_err("DDR training failed\n");
+
+ /* Jump to reset - does not return */
+ reset = KSEG0ADDR(_machine_restart);
+ icache_lock((void *)reset, 128); // Reset while running from cache
+ asm volatile ("jr %0" : : "r" (reset));
+}
+#else // JR2 || ServalT
static inline void hal_vcoreiii_ddr_failed(void)
{
writel(0, BASE_CFG + ICPU_RESET);
@@ -471,6 +484,7 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n");
}
+#endif /* Serval */
#endif /* JR2 || ServalT || Serval */
/*
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
index a555fc9..95fe0d8 100644
--- a/arch/mips/mach-mscc/reset.c
+++ b/arch/mips/mach-mscc/reset.c
@@ -28,16 +28,13 @@ void _machine_restart(void)
ICPU_RESET_CORE_RST_FORCE,
BASE_CFG + ICPU_RESET);
#elif defined(CONFIG_SOC_SERVAL)
- register unsigned long i;
-
/* Prevent VCore-III from being reset with a global reset */
writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
/* Do global reset */
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
- for (i = 0; i < 1000; i++)
- ;
+ mdelay(100);
/* Power down DDR for clean DDR re-training */
writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) |
--
2.7.4
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[U-Boot] [PATCH 2/2] board: mscc: serval: Fix board detect
When detecting the board, it was reading a register in the GPIO page of
the phy and based on that value it was making a decision. The bug was that
after the GPIO page for the first phy was set it was not reseted back.
Signed-off-by: Horatiu Vultur
---
board/mscc/serval/serval.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c
index 52faac9..50444e4 100644
--- a/board/mscc/serval/serval.c
+++ b/board/mscc/serval/serval.c
@@ -49,10 +49,10 @@ static void do_board_detect(void)
gd->board_type = BOARD_TYPE_PCB106;
else
gd->board_type = BOARD_TYPE_PCB105;
- mscc_phy_wr(1, 16, 15, 0);
} else {
gd->board_type = BOARD_TYPE_PCB105;
}
+ mscc_phy_wr(1, 16, 31, 0x0);
}
#if defined(CONFIG_MULTI_DTB_FIT)
--
2.7.4
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[U-Boot] [PATCH 0/2] Fix minor issues with Serval SoC.
This patch series fix different issues with Serval. - first patch fix resets when DDR training fails. - second patch fix the detection of the board. This patch series is based on u-boot-mips/next. Horatiu Vultur (2): mips: mscc: serval: Fix reset board: mscc: serval: Fix board detect arch/mips/mach-mscc/include/mach/ddr.h | 14 ++ arch/mips/mach-mscc/reset.c| 5 + board/mscc/serval/serval.c | 2 +- 3 files changed, 16 insertions(+), 5 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] configs: vcoreiii: Change CONFIG_ENV_SIZE
Shrink the environment size for 3 reasons: - reading the environment it is slow, therefore having a smaller env improves the speed. - usually in the environment there are only few variables, therefore the enviromnent is almost empty. - because the same image can run on different boards which may have different flashes with different page sizes, the CONFIG_ENV_SECT_SIZE can't be change, it is set to least common multiple of the page sizes. Adding this change improves the boot time. Before update for reading the entire environment it took ~850 msec, after the change it takes ~40 msecs. Signed-off-by: Horatiu Vultur --- include/configs/vcoreiii.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index aeef58d..8c68372 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -27,7 +27,7 @@ #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) #define CONFIG_ENV_OFFSET (1024 * 1024) -#define CONFIG_ENV_SIZE(256 * 1024) +#define CONFIG_ENV_SIZE(8 * 1024) #define CONFIG_ENV_SECT_SIZE (256 * 1024) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/3] Add network support for ServalT SoCs
This patch series adds network support for ServalT SoCs family. There is only one pcb in this family: ServalT(pcb116). This patch series is based on: u-boot-mips/next. Horatiu Vultur (3): net: Add MSCC ServalT network driver. net: mscc: servalt: Add ethernet nodes for ServalT configs: mscc_servalt: Add network support arch/mips/dts/mscc,servalt.dtsi| 40 ++ arch/mips/dts/servalt_pcb116.dts | 25 + .../include/mach/servalt/servalt_devcpu_gcb.h | 2 + configs/mscc_servalt_defconfig | 6 +- drivers/net/mscc_eswitch/Kconfig | 7 + drivers/net/mscc_eswitch/Makefile | 1 + drivers/net/mscc_eswitch/servalt_switch.c | 622 + 7 files changed, 702 insertions(+), 1 deletion(-) create mode 100644 drivers/net/mscc_eswitch/servalt_switch.c -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/3] net: mscc: servalt: Add ethernet nodes for ServalT
Add ethernet nodes for ServalT SoCs family. Currently there is only one
pcb(pcb116) in this family.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/mscc,servalt.dtsi | 40
arch/mips/dts/servalt_pcb116.dts | 25 +
2 files changed, 65 insertions(+)
diff --git a/arch/mips/dts/mscc,servalt.dtsi b/arch/mips/dts/mscc,servalt.dtsi
index 4beb7a3..45ae2de 100644
--- a/arch/mips/dts/mscc,servalt.dtsi
+++ b/arch/mips/dts/mscc,servalt.dtsi
@@ -145,5 +145,45 @@
#gpio-cells = <2>;
gpio-ranges = < 0 0 128>;
};
+
+ switch: switch@101 {
+ compatible = "mscc,vsc7437-switch";
+ reg = <0x0103 0x0100>, // VTSS_TO_DEV_0
+ <0x0104 0x0100>, // VTSS_TO_DEV_1
+ <0x01f0 0x10>, // ANA_AC
+ <0x01d0 0x10>, // ANA_CL
+ <0x01e0 0x10>, // ANA_L2
+ <0x0112 0x1>, // ASM
+ <0x0113 0x0>, // LRN
+ <0x017d 0x1>, // QFWD
+ <0x0102 0x2>, // QS
+ <0x017e 0x1>, // QSYS
+ <0x01b0 0x8>; // REW
+ reg-names = "port0", "port1",
+ "ana_ac", "ana_cl", "ana_l2", "asm", "lrn",
+ "qfwd", "qs", "qsys", "rew";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio0: mdio@010100c4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,jr2-miim";
+ reg = <0x010100c4 0x24>;
+ status = "disabled";
+ };
+
+ mdio1: mdio@010100e8 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,jr2-miim";
+ reg = <0x010100e8 0x24>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/dts/servalt_pcb116.dts b/arch/mips/dts/servalt_pcb116.dts
index fb33312..9d49215 100644
--- a/arch/mips/dts/servalt_pcb116.dts
+++ b/arch/mips/dts/servalt_pcb116.dts
@@ -54,3 +54,28 @@
status = "okay";
sgpio-ports = <0xfe7f>;
};
+
+ {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ {
+ ethernet-ports {
+
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <>;
+ };
+ };
+};
--
2.7.4
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[U-Boot] [PATCH 3/3] configs: mscc_servalt: Add network support
Update default config to use network driver for ServalT SoCs. Signed-off-by: Horatiu Vultur --- configs/mscc_servalt_defconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig index 027aaa4..33d43de 100644 --- a/configs/mscc_servalt_defconfig +++ b/configs/mscc_servalt_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)" @@ -59,3 +58,8 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_LZMA=y +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_MSCC_SERVALT_SWITCH=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/3] net: Add MSCC ServalT network driver.
Add network driver for Microsemi Ethernet switch. It is present on ServalT SoCs. Signed-off-by: Horatiu Vultur --- .../include/mach/servalt/servalt_devcpu_gcb.h | 2 + drivers/net/mscc_eswitch/Kconfig | 7 + drivers/net/mscc_eswitch/Makefile | 1 + drivers/net/mscc_eswitch/servalt_switch.c | 622 + 4 files changed, 632 insertions(+) create mode 100644 drivers/net/mscc_eswitch/servalt_switch.c diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h index f6e7245..493eaad 100644 --- a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h @@ -17,4 +17,6 @@ #define GPIO_GPIO_ALT(x) (0x74 + 4 * (x)) #define GPIO_GPIO_ALT1(x) (0x7c + 4 * (x)) +#define GCB_PHY_CFG 0x118 + #endif diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 3f9d14b..6359d0b 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -22,3 +22,10 @@ config MSCC_JR2_SWITCH select PHYLIB help This driver supports the Jaguar2 network switch device. + +config MSCC_SERVALT_SWITCH + bool "Servalt switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Servalt network switch device. diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index 0a1b863..bffd8ec 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o +obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o diff --git a/drivers/net/mscc_eswitch/servalt_switch.c b/drivers/net/mscc_eswitch/servalt_switch.c new file mode 100644 index 000..995c623 --- /dev/null +++ b/drivers/net/mscc_eswitch/servalt_switch.c @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mscc_xfer.h" + +#define GCB_MIIM_MII_STATUS0x0 +#defineGCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2) +#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#defineGCB_MIIM_MII_CMD_VLDBIT(31) +#define GCB_MIIM_DATA 0xC +#defineGCB_MIIM_DATA_ERROR (0x3 << 16) + +#define PHY_CFG0x0 +#define PHY_CFG_ENA0x3 +#define PHY_CFG_COMMON_RST BIT(2) +#define PHY_CFG_RST(0x3 << 3) +#define PHY_STAT 0x4 +#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0) + +#define ANA_AC_RAM_CTRL_RAM_INIT 0x14fdc +#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x15474 + +#define ANA_CL_PORT_VLAN_CFG(x)(0xa018 + 0xc8 * (x)) +#defineANA_CL_PORT_VLAN_CFG_AWARE_ENA BIT(19) +#defineANA_CL_PORT_VLAN_CFG_POP_CNT(x) ((x) << 17) + +#define ANA_L2_COMMON_FWD_CFG 0x18498 +#defineANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) + +#define ASM_CFG_STAT_CFG 0xb08 +#define ASM_CFG_PORT(x)(0xb74 + 0x4 * (x)) +#defineASM_CFG_PORT_NO_PREAMBLE_ENABIT(8) +#defineASM_CFG_PORT_INJ_FORMAT_CFG(x) ((x) << 1) +#define ASM_RAM_CTRL_RAM_INIT 0xbfc + +#define DEV_DEV_CFG_DEV_RST_CTRL 0x0 +#defineDEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(x) ((x) << 20) +#define DEV_MAC_CFG_MAC_ENA0x24 +#defineDEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4) +#defineDEV_MAC_CFG_MAC_ENA_TX_ENA BIT(0) +#define DEV_MAC_CFG_MAC_IFG0x3c +#defineDEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8) +#defineDEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4) +#defineDEV_MAC_CFG_MAC_I
[U-Boot] [PATCH v4 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
In Jaguar2 SoC family there are 3 different pcb. Each of this needs
to configure the phys in different ways. Therefore implement the
function board_phy_config and based on pcb configure them accordingly.
Signed-off-by: Horatiu Vultur
---
board/mscc/jr2/jr2.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
index 58a4a04..6e5ef4c 100644
--- a/board/mscc/jr2/jr2.c
+++ b/board/mscc/jr2/jr2.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
enum {
BOARD_TYPE_PCB110 = 0xAABBCE00,
@@ -64,6 +65,28 @@ static void vcoreiii_gpio_set_alternate(int gpio, int mode)
}
}
+int board_phy_config(struct phy_device *phydev)
+{
+ if (gd->board_type == BOARD_TYPE_PCB110 ||
+ gd->board_type == BOARD_TYPE_PCB112) {
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80F0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 31, 0);
+ }
+ if (gd->board_type == BOARD_TYPE_PCB111) {
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80A0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 14, 0x800);
+ phy_write(phydev, 0, 31, 0);
+ }
+
+ return 0;
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
--
2.7.4
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[U-Boot] [PATCH v4 4/4] configs: mscc_jr2: Add network support
Update default confing to use network driver for Jaguar2 SoCs. Signed-off-by: Horatiu Vultur --- configs/mscc_jr2_defconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 95562b7..92c22b8 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -28,7 +28,10 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)" @@ -66,3 +69,4 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_LZMA=y +CONFIG_MSCC_JR2_SWITCH=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 3/4] net: mscc: jaguar2: Add ethenet nodes for Jaguar2.
Add ethernet nodes for Jaguar2 SoCs family. There are 3 pcb in this
family: pcb110, pcb111 and pcb112.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/jr2_pcb110.dts| 76 +++
arch/mips/dts/jr2_pcb111.dts| 400
arch/mips/dts/mscc,jr2.dtsi | 116 +++
arch/mips/dts/serval2_pcb112.dts| 44
include/dt-bindings/mscc/jr2_data.h | 19 ++
5 files changed, 655 insertions(+)
create mode 100644 include/dt-bindings/mscc/jr2_data.h
diff --git a/arch/mips/dts/jr2_pcb110.dts b/arch/mips/dts/jr2_pcb110.dts
index ddc30ff..4a5a584 100644
--- a/arch/mips/dts/jr2_pcb110.dts
+++ b/arch/mips/dts/jr2_pcb110.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "mscc,jr2.dtsi"
+#include
/ {
model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
@@ -72,3 +73,78 @@
sgpio-ports = <0x3f00>;
gpio-ranges = < 0 0 96>;
};
+
+ {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+};
+
+ {
+ ethernet-ports {
+
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <>;
+ phys = <_hsio 0 SERDES1G(1) PHY_MODE_SGMII>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <>;
+ phys = <_hsio 1 SERDES1G(2) PHY_MODE_SGMII>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ phy-handle = <>;
+ phys = <_hsio 2 SERDES1G(3) PHY_MODE_SGMII>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ phy-handle = <>;
+ phys = <_hsio 3 SERDES1G(4) PHY_MODE_SGMII>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ phy-handle = <>;
+ phys = <_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ phy-handle = <>;
+ phys = <_hsio 5 SERDES1G(6) PHY_MODE_SGMII>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ phy-handle = <>;
+ phys = <_hsio 6 SERDES1G(7) PHY_MODE_SGMII>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ phy-handle = <>;
+ phys = <_hsio 7 SERDES1G(8) PHY_MODE_SGMII>;
+ };
+ };
+};
diff --git a/arch/mips/dts/jr2_pcb111.dts b/arch/mips/dts/jr2_pcb111.dts
index 4d411b6..f37ebc7 100644
--- a/arch/mips/dts/jr2_pcb111.dts
+++ b/arch/mips/dts/jr2_pcb111.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "mscc,jr2.dtsi"
+#include
/ {
model = "Jaguar2 Cu48 PCB111 Reference Board";
@@ -72,3 +73,402 @@
sgpio-ports = <0xff00>;
gpio-ranges = < 0 0 96>;
};
+
+ {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
+ phy12: ethernet-phy@12 {
+ reg = <12>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <13>;
+ };
+ phy14: ethernet-phy@14 {
+ reg = <14>;
+ };
+ phy15: ethernet-
[U-Boot] [PATCH v4 1/4] net: Add MSCC Jaguar2 network driver.
Add network driver for Microsemi Ethernet switch. It is present on Jaguar2 SoCs. Reviewed-by: Daniel Schwierzeck Signed-off-by: Horatiu Vultur --- drivers/net/mscc_eswitch/Kconfig |7 + drivers/net/mscc_eswitch/Makefile |1 + drivers/net/mscc_eswitch/jr2_switch.c | 1075 + include/configs/vcoreiii.h|2 +- 4 files changed, 1084 insertions(+), 1 deletion(-) create mode 100644 drivers/net/mscc_eswitch/jr2_switch.c diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 88e5a97..3f9d14b 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -15,3 +15,10 @@ config MSCC_LUTON_SWITCH select PHYLIB help This driver supports the Luton network switch device. + +config MSCC_JR2_SWITCH + bool "Jaguar2 switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Jaguar2 network switch device. diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index 751a839..0a1b863 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o +obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c new file mode 100644 index 000..60d408f --- /dev/null +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -0,0 +1,1075 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "mscc_xfer.h" + +#define GCB_MIIM_MII_STATUS0x0 +#defineGCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#defineGCB_MIIM_MII_CMD_SCAN BIT(0) +#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2) +#defineGCB_MIIM_MII_CMD_SINGLE_SCANBIT(3) +#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#defineGCB_MIIM_MII_CMD_VLDBIT(31) +#define GCB_MIIM_DATA 0xC +#defineGCB_MIIM_DATA_ERROR (0x3 << 16) + +#define ANA_AC_RAM_CTRL_RAM_INIT 0x94358 +#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x94370 + +#define ANA_CL_PORT_VLAN_CFG(x)(0x24018 + 0xc8 * (x)) +#defineANA_CL_PORT_VLAN_CFG_AWARE_ENA BIT(19) +#defineANA_CL_PORT_VLAN_CFG_POP_CNT(x) ((x) << 17) + +#define ANA_L2_COMMON_FWD_CFG 0x8a2a8 +#defineANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) + +#define ASM_CFG_STAT_CFG 0x3508 +#define ASM_CFG_PORT(x)(0x36c4 + 0x4 * (x)) +#defineASM_CFG_PORT_NO_PREAMBLE_ENABIT(8) +#defineASM_CFG_PORT_INJ_FORMAT_CFG(x) ((x) << 1) +#define ASM_RAM_CTRL_RAM_INIT 0x39b8 + +#define DEV_DEV_CFG_DEV_RST_CTRL 0x0 +#defineDEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(x) ((x) << 20) +#define DEV_MAC_CFG_MAC_ENA0x1c +#defineDEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4) +#defineDEV_MAC_CFG_MAC_ENA_TX_ENA BIT(0) +#defineDEV_MAC_CFG_MAC_IFG 0x34 +#defineDEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8) +#defineDEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4) +#defineDEV_MAC_CFG_MAC_IFG_RX_IFG1(x) (x) +#defineDEV_PCS1G_CFG_PCS1G_CFG 0x40 +#defineDEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA BIT(0) +#defineDEV_PCS1G_CFG_PCS1G_MODE0x44 +#defineDEV_PCS1G_CFG_PCS1G_SD 0x48 +#defineDEV_PCS1G_CFG_PCS1G_ANEG0x4c +#defineDEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(x) ((x) << 16) + +#define DSM_RAM_CTRL_RAM_INIT 0x8 + +#define HSIO_ANA_SERDES1G_DES_CFG 0xac +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << 1) +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#define
[U-Boot] [PATCH v4 0/4] Add network support for Jaguar2 SoCs
v4-changes: - address Daniel comments. v3-changes: - move serdes setup in network driver and read serdes configuration from DT. v2-changes: - create serdes6g_setup and serdes1g_setup functions to be easier to extand for future boards. Horatiu Vultur (4): net: Add MSCC Jaguar2 network driver. board: mscc: jr2: Update MSCC Jaguar2 boards net: mscc: jaguar2: Add ethenet nodes for Jaguar2. configs: mscc_jr2: Add network support arch/mips/dts/jr2_pcb110.dts | 76 +++ arch/mips/dts/jr2_pcb111.dts | 400 arch/mips/dts/mscc,jr2.dtsi | 116 arch/mips/dts/serval2_pcb112.dts | 44 ++ board/mscc/jr2/jr2.c | 23 + configs/mscc_jr2_defconfig|6 +- drivers/net/mscc_eswitch/Kconfig |7 + drivers/net/mscc_eswitch/Makefile |1 + drivers/net/mscc_eswitch/jr2_switch.c | 1075 + include/configs/vcoreiii.h|2 +- include/dt-bindings/mscc/jr2_data.h | 19 + 11 files changed, 1767 insertions(+), 2 deletions(-) create mode 100644 drivers/net/mscc_eswitch/jr2_switch.c create mode 100644 include/dt-bindings/mscc/jr2_data.h -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/4] net: Add MSCC Jaguar2 network driver.
Hi Daniel, The 04/03/2019 12:18, Daniel Schwierzeck wrote: > External E-Mail > > > > Am 30.03.19 um 11:17 schrieb Horatiu Vultur: > > Add network driver for Microsemi Ethernet switch. > > It is present on Jaguar2 SoCs. > > > > Signed-off-by: Horatiu Vultur > > --- > > drivers/net/mscc_eswitch/Kconfig |7 + > > drivers/net/mscc_eswitch/Makefile |1 + > > drivers/net/mscc_eswitch/jr2_switch.c | 1075 > > + > > include/configs/vcoreiii.h|2 +- > > 4 files changed, 1084 insertions(+), 1 deletion(-) > > create mode 100644 drivers/net/mscc_eswitch/jr2_switch.c > > Reviewed-by: Daniel Schwierzeck > > nits below > > > > > diff --git a/drivers/net/mscc_eswitch/Kconfig > > b/drivers/net/mscc_eswitch/Kconfig > > index 88e5a97..3f9d14b 100644 > > --- a/drivers/net/mscc_eswitch/Kconfig > > +++ b/drivers/net/mscc_eswitch/Kconfig > > @@ -15,3 +15,10 @@ config MSCC_LUTON_SWITCH > > select PHYLIB > > help > > This driver supports the Luton network switch device. > > + > > +config MSCC_JR2_SWITCH > > + bool "Jaguar2 switch driver" > > + depends on DM_ETH && ARCH_MSCC > > + select PHYLIB > > + help > > + This driver supports the Jaguar2 network switch device. > > diff --git a/drivers/net/mscc_eswitch/Makefile > > b/drivers/net/mscc_eswitch/Makefile > > index 751a839..0a1b863 100644 > > --- a/drivers/net/mscc_eswitch/Makefile > > +++ b/drivers/net/mscc_eswitch/Makefile > > @@ -1,3 +1,4 @@ > > > > obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o > > mscc_xfer.o mscc_mac_table.o > > obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o > > mscc_mac_table.o > > +obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o > > diff --git a/drivers/net/mscc_eswitch/jr2_switch.c > > b/drivers/net/mscc_eswitch/jr2_switch.c > > new file mode 100644 > > index 000..d4a2498 > > --- /dev/null > > +++ b/drivers/net/mscc_eswitch/jr2_switch.c > > @@ -0,0 +1,1075 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Copyright (c) 2018 Microsemi Corporation > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > +#include "mscc_xfer.h" > > + > > +#define GCB_MIIM_MII_STATUS0x0 > > +#defineGCB_MIIM_STAT_BUSY BIT(3) > > +#define GCB_MIIM_MII_CMD 0x8 > > +#defineGCB_MIIM_MII_CMD_SCAN BIT(0) > > +#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1) > > +#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2) > > +#defineGCB_MIIM_MII_CMD_SINGLE_SCANBIT(3) > > +#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) > > +#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) > > +#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) > > +#defineGCB_MIIM_MII_CMD_VLDBIT(31) > > +#define GCB_MIIM_DATA 0xC > > +#defineGCB_MIIM_DATA_ERROR (0x3 << 16) > > + > > +#define ANA_AC_RAM_CTRL_RAM_INIT 0x94358 > > +#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x94370 > > + > > +#define ANA_CL_PORT_VLAN_CFG(x)(0x24018 + 0xc8 * (x)) > > +#defineANA_CL_PORT_VLAN_CFG_AWARE_ENA BIT(19) > > +#defineANA_CL_PORT_VLAN_CFG_POP_CNT(x) ((x) << > > 17) > > + > > +#define ANA_L2_COMMON_FWD_CFG 0x8a2a8 > > +#defineANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) > > + > > +#define ASM_CFG_STAT_CFG 0x3508 > > +#define ASM_CFG_PORT(x)(0x36c4 + 0x4 * (x)) > > +#defineASM_CFG_PORT_NO_PREAMBLE_ENABIT(8) > > +#defineASM_CFG_PORT_INJ_FORMAT_CFG(x) ((x) << 1) > > +#define ASM_RAM_CTRL_RAM_INIT 0x39b8 > > + > > +#define DEV_DEV_CFG_DEV_RST_CTRL 0x0 > > +#defineDEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(x) ((x) << 20) > > +#define DEV_MAC_CFG_MAC_ENA0x1c > > +#defineDEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4) &
[U-Boot] [PATCH v3 4/4] configs: mscc_jr2: Add network support
Update default confing to use network driver for Jaguar2 SoCs. Signed-off-by: Horatiu Vultur --- configs/mscc_jr2_defconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 95562b7..92c22b8 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -28,7 +28,10 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)" @@ -66,3 +69,4 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_LZMA=y +CONFIG_MSCC_JR2_SWITCH=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/4] net: Add MSCC Jaguar2 network driver.
Add network driver for Microsemi Ethernet switch. It is present on Jaguar2 SoCs. Signed-off-by: Horatiu Vultur --- drivers/net/mscc_eswitch/Kconfig |7 + drivers/net/mscc_eswitch/Makefile |1 + drivers/net/mscc_eswitch/jr2_switch.c | 1075 + include/configs/vcoreiii.h|2 +- 4 files changed, 1084 insertions(+), 1 deletion(-) create mode 100644 drivers/net/mscc_eswitch/jr2_switch.c diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 88e5a97..3f9d14b 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -15,3 +15,10 @@ config MSCC_LUTON_SWITCH select PHYLIB help This driver supports the Luton network switch device. + +config MSCC_JR2_SWITCH + bool "Jaguar2 switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Jaguar2 network switch device. diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index 751a839..0a1b863 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o +obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c new file mode 100644 index 000..d4a2498 --- /dev/null +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -0,0 +1,1075 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "mscc_xfer.h" + +#define GCB_MIIM_MII_STATUS0x0 +#defineGCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#defineGCB_MIIM_MII_CMD_SCAN BIT(0) +#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2) +#defineGCB_MIIM_MII_CMD_SINGLE_SCANBIT(3) +#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#defineGCB_MIIM_MII_CMD_VLDBIT(31) +#define GCB_MIIM_DATA 0xC +#defineGCB_MIIM_DATA_ERROR (0x3 << 16) + +#define ANA_AC_RAM_CTRL_RAM_INIT 0x94358 +#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x94370 + +#define ANA_CL_PORT_VLAN_CFG(x)(0x24018 + 0xc8 * (x)) +#defineANA_CL_PORT_VLAN_CFG_AWARE_ENA BIT(19) +#defineANA_CL_PORT_VLAN_CFG_POP_CNT(x) ((x) << 17) + +#define ANA_L2_COMMON_FWD_CFG 0x8a2a8 +#defineANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) + +#define ASM_CFG_STAT_CFG 0x3508 +#define ASM_CFG_PORT(x)(0x36c4 + 0x4 * (x)) +#defineASM_CFG_PORT_NO_PREAMBLE_ENABIT(8) +#defineASM_CFG_PORT_INJ_FORMAT_CFG(x) ((x) << 1) +#define ASM_RAM_CTRL_RAM_INIT 0x39b8 + +#define DEV_DEV_CFG_DEV_RST_CTRL 0x0 +#defineDEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(x) ((x) << 20) +#define DEV_MAC_CFG_MAC_ENA0x1c +#defineDEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4) +#defineDEV_MAC_CFG_MAC_ENA_TX_ENA BIT(0) +#defineDEV_MAC_CFG_MAC_IFG 0x34 +#defineDEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8) +#defineDEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4) +#defineDEV_MAC_CFG_MAC_IFG_RX_IFG1(x) (x) +#defineDEV_PCS1G_CFG_PCS1G_CFG 0x40 +#defineDEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA BIT(0) +#defineDEV_PCS1G_CFG_PCS1G_MODE0x44 +#defineDEV_PCS1G_CFG_PCS1G_SD 0x48 +#defineDEV_PCS1G_CFG_PCS1G_ANEG0x4c +#defineDEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(x) ((x) << 16) + +#define DSM_RAM_CTRL_RAM_INIT 0x8 + +#define HSIO_ANA_SERDES1G_DES_CFG 0xac +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << 1) +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#defineHSIO_ANA_SERDES1
[U-Boot] [PATCH v3 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
In Jaguar2 SoC family there are 3 different pcb. Each of this needs
to configure the phys in different ways. Therefore implement the
function board_phy_config and based on pcb configure them accordingly.
Signed-off-by: Horatiu Vultur
---
board/mscc/jr2/jr2.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
index 58a4a04..6e5ef4c 100644
--- a/board/mscc/jr2/jr2.c
+++ b/board/mscc/jr2/jr2.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
enum {
BOARD_TYPE_PCB110 = 0xAABBCE00,
@@ -64,6 +65,28 @@ static void vcoreiii_gpio_set_alternate(int gpio, int mode)
}
}
+int board_phy_config(struct phy_device *phydev)
+{
+ if (gd->board_type == BOARD_TYPE_PCB110 ||
+ gd->board_type == BOARD_TYPE_PCB112) {
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80F0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 31, 0);
+ }
+ if (gd->board_type == BOARD_TYPE_PCB111) {
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80A0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 14, 0x800);
+ phy_write(phydev, 0, 31, 0);
+ }
+
+ return 0;
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
--
2.7.4
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[U-Boot] [PATCH v3 3/4] net: mscc: jaguar2: Add ethenet nodes for Jaguar2.
Add ethernet nodes for Jaguar2 SoCs family. There are 3 pcb in this
family: pcb110, pcb111 and pcb112.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/jr2_pcb110.dts| 76 +++
arch/mips/dts/jr2_pcb111.dts| 400
arch/mips/dts/mscc,jr2.dtsi | 116 +++
arch/mips/dts/serval2_pcb112.dts| 44
include/dt-bindings/mscc/jr2_data.h | 19 ++
5 files changed, 655 insertions(+)
create mode 100644 include/dt-bindings/mscc/jr2_data.h
diff --git a/arch/mips/dts/jr2_pcb110.dts b/arch/mips/dts/jr2_pcb110.dts
index ddc30ff..4a5a584 100644
--- a/arch/mips/dts/jr2_pcb110.dts
+++ b/arch/mips/dts/jr2_pcb110.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "mscc,jr2.dtsi"
+#include
/ {
model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
@@ -72,3 +73,78 @@
sgpio-ports = <0x3f00>;
gpio-ranges = < 0 0 96>;
};
+
+ {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+};
+
+ {
+ ethernet-ports {
+
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <>;
+ phys = <_hsio 0 SERDES1G(1) PHY_MODE_SGMII>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <>;
+ phys = <_hsio 1 SERDES1G(2) PHY_MODE_SGMII>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ phy-handle = <>;
+ phys = <_hsio 2 SERDES1G(3) PHY_MODE_SGMII>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ phy-handle = <>;
+ phys = <_hsio 3 SERDES1G(4) PHY_MODE_SGMII>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ phy-handle = <>;
+ phys = <_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ phy-handle = <>;
+ phys = <_hsio 5 SERDES1G(6) PHY_MODE_SGMII>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ phy-handle = <>;
+ phys = <_hsio 6 SERDES1G(7) PHY_MODE_SGMII>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ phy-handle = <>;
+ phys = <_hsio 7 SERDES1G(8) PHY_MODE_SGMII>;
+ };
+ };
+};
diff --git a/arch/mips/dts/jr2_pcb111.dts b/arch/mips/dts/jr2_pcb111.dts
index 4d411b6..f37ebc7 100644
--- a/arch/mips/dts/jr2_pcb111.dts
+++ b/arch/mips/dts/jr2_pcb111.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "mscc,jr2.dtsi"
+#include
/ {
model = "Jaguar2 Cu48 PCB111 Reference Board";
@@ -72,3 +73,402 @@
sgpio-ports = <0xff00>;
gpio-ranges = < 0 0 96>;
};
+
+ {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
+ phy12: ethernet-phy@12 {
+ reg = <12>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <13>;
+ };
+ phy14: ethernet-phy@14 {
+ reg = <14>;
+ };
+ phy15: ethernet-
[U-Boot] [PATCH v3 0/4] Add network support for Jaguar2 SoCs
v3-changes: - move serdes setup in network driver and read serdes configuration from DT. v2-changes: - create serdes6g_setup and serdes1g_setup functions to be easier to extand for future boards. Horatiu Vultur (4): net: Add MSCC Jaguar2 network driver. board: mscc: jr2: Update MSCC Jaguar2 boards net: mscc: jaguar2: Add ethenet nodes for Jaguar2. configs: mscc_jr2: Add network support arch/mips/dts/jr2_pcb110.dts | 76 +++ arch/mips/dts/jr2_pcb111.dts | 400 arch/mips/dts/mscc,jr2.dtsi | 116 arch/mips/dts/serval2_pcb112.dts | 44 ++ board/mscc/jr2/jr2.c | 23 + configs/mscc_jr2_defconfig|6 +- drivers/net/mscc_eswitch/Kconfig |7 + drivers/net/mscc_eswitch/Makefile |1 + drivers/net/mscc_eswitch/jr2_switch.c | 1075 + include/configs/vcoreiii.h|2 +- include/dt-bindings/mscc/jr2_data.h | 19 + 11 files changed, 1767 insertions(+), 2 deletions(-) create mode 100644 drivers/net/mscc_eswitch/jr2_switch.c create mode 100644 include/dt-bindings/mscc/jr2_data.h -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [Resend Patch] net: mscc: ocelot: Fix reset of the phys
The function mscc_miim_reset resets all the phys, but it is called for
each phy separetely. One consequence of this is that the boot time
is increased by 2 seconds.
The fix consists for calling the mscc_miim_reset function only once for
all phys.
Signed-off-by: Horatiu Vultur
Reviewed-by: Daniel Schwierzeck
---
drivers/net/mscc_eswitch/ocelot_switch.c | 27 ++-
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
index bf08c35..815c2da 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -142,18 +142,16 @@ static const unsigned long ocelot_regs_ana_table[] = {
static struct mscc_miim_dev miim[NUM_PHY];
-static int mscc_miim_reset(struct mii_dev *bus)
+static void mscc_phy_reset(void)
{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
-
- if (miim->phy_regs) {
- writel(0, miim->phy_regs + PHY_CFG);
- writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
- | PHY_CFG_ENA, miim->phy_regs + PHY_CFG);
- mdelay(500);
+ writel(0, miim[INTERNAL].phy_regs + PHY_CFG);
+ writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
+ | PHY_CFG_ENA, miim[INTERNAL].phy_regs + PHY_CFG);
+ if (wait_for_bit_le32(miim[INTERNAL].phy_regs + PHY_STAT,
+ PHY_STAT_SUPERVISOR_COMPLETE,
+ true, 2000, false)) {
+ pr_err("Timeout in phy reset\n");
}
-
- return 0;
}
/* For now only setup the internal mdio bus */
@@ -194,7 +192,6 @@ static struct mii_dev *ocelot_mdiobus_init(struct udevice
*dev)
miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);
miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);
bus->priv = [INTERNAL];
- bus->reset = mscc_miim_reset;
bus->read = mscc_miim_read;
bus->write = mscc_miim_write;
@@ -210,13 +207,8 @@ __weak void mscc_switch_reset(void)
static void ocelot_stop(struct udevice *dev)
{
- struct ocelot_private *priv = dev_get_priv(dev);
- int i;
-
mscc_switch_reset();
- for (i = 0; i < NUM_PHY; i++)
- if (priv->bus[i])
- mscc_miim_reset(priv->bus[i]);
+ mscc_phy_reset();
}
static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
@@ -473,6 +465,7 @@ static int ocelot_probe(struct udevice *dev)
}
priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);
+ mscc_phy_reset();
for (i = 0; i < 4; i++) {
phy_connect(priv->bus[INTERNAL], i, dev,
--
2.7.4
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Re: [U-Boot] [PATCH] Revert "env: add spi_flash_read_env function"
Hi Heiko, Sorry, for late reply. I have seen that this patch was accepted, so I have only few things bellow. The 03/15/2019 05:34, Heiko Schocher wrote: > External E-Mail > > > Hello Horatiu, > > Am 14.03.2019 um 13:53 schrieb Horatiu Vultur: > > Hi Heiko, > > > > I managed to reproduce the issue that you described. > > Fine, thanks for testing! > > > Don't you think it is a little bit too harsh to remove the commit > > completely? > > I am unsure here ... > > > I am not sure but how many cases are where UBoot doesn't store anything > > in flash? And then lets the linux to update the flash. > > I think that can happen very often. In my case for example we boot > SPL/U-Boot with usb loader, than an initsystem with kernel/dtb/ramdisk > and start swupdate for installing all sources (including setup > the Environment with fw_setenv)... > > > Or is wouldn't better to update fw_setenv to set the entire flash to > > 0x0 when it detects that the CRC error? The same way how the saveenv it > > is doing in UBoot? > > Indeed, just reproduced this on my board. Saving the Environment > with saveenv fills with 0x0 and saving with fw_setenv fills with > 0xff. > > This is no problem, until your optimization, and I think, we cannot > change this here without breaking a lot of boards, running fine. > > I am here also on Stefanos side always to read the hole Environment > space, because we cannot be sure, with what the empty space is filled > up. > > Back to your intention for this patch, stated in the commit message: > """ > This is an optimization for large environments that contain few bytes > environment variables. In this case it doesn't need to read the entire > environment and only few pages. > """ > > Hmm... why you use a big Environment, if you only have "few bytes" of > variables ? We choose a big Environment because different boards can have different flashes which can have different page size. Therefore we chose for the environmnet size to be the least common multiple. > > Simply set CONFIG_ENV_SIZE to a smaller value than your CONFIG_ENV_SECT_SIZE > > Is this not possible for you ? Thanks for the suggestion. I have done few tests with this option and improves the speed setting the CONFIG_ENV_SIZE to something smaller than CONFIG_ENV_SECT_SIZE. > > bye, > Heiko > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de -- /Horatiu ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
Hi Daniel, The 03/15/2019 13:02, Daniel Schwierzeck wrote: > External E-Mail > > > Hi Horatio, > > Am 06.03.19 um 23:11 schrieb Horatiu Vultur: > > Hi Daniel, > > > > The 03/06/2019 14:19, Daniel Schwierzeck wrote: > >> > >> > >> Am 05.03.19 um 12:57 schrieb Horatiu Vultur: > >>> In Jaguar2 SoC family there are 3 different pcb. Each of this needs > >>> to configure the SerDes and the phys in different ways. > >>> Therefore implement the function board_phy_config and serdes_cfg > >>> and based on pcb configure them accordingly. > >> > >> what are the differences between all boards? Can't you model the > >> different register values somehow as custom DT properties? This method > >> looks like a lot of code duplication and doesn't scale well when adding > >> new boards. > > > > So there are following boards: > > - pcb110: it has viper phys that are connected to serdes1g using the > >interface sgmii > > - pcb111: it has atom phys that are connected to serdes6g using the > >interface qsgmii > > - pcb112: it has viper phys that are connected to serdes6g using the > >interface sgmii. > > > > Do you have an example where I can look, how to add this custom > > properties? > > > > Yes, it looks like a lot code duplication, but there are only few > > differences between them. I was thinking maybe I can create 2 functions > > that configure the serdes1g and serdes6g which will get as a paramenter > > the interface mode. In this way I think it would scale better, because > > then each new board it would just call these new functions. > > > > /Horatiu > > but this code belongs to the ethernet driver. Board specific differences > like PHY interface or Serdes type could be configured via appropiate > device-tree bindings (PHY interface already exists as generic binding). > How do you plan to do it in Linux? I understand now. Currently there is no Jaguar2 support on the upstream kernel, maybe at a later point in time will come this. > > I've found Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt > which looks very similar to what you want to achieve here. Maybe the > Bootlin guys can give you some more hints ;) I managed to talk with Alexandre and he proposed to have a look over the comphy inside the u-boot. Therefore I will have a look over this and I will send a new patch series. Thank you. > > > > > >> > >>> > >>> Signed-off-by: Horatiu Vultur > >>> --- > >>> board/mscc/jr2/jr2.c | 542 > >>> +++ > >>> 1 file changed, 542 insertions(+) > >>> > >>> diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c > >>> index 58a4a04..94e0c5d 100644 > >>> --- a/board/mscc/jr2/jr2.c > >>> +++ b/board/mscc/jr2/jr2.c > >>> @@ -6,6 +6,140 @@ > >>> #include > >>> #include > >>> #include > >>> +#include > >>> + > >>> +#define HSIO_ANA_SERDES1G_DES_CFG0xac > >>> +#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << > >>> 1) > >>> +#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << > >>> 5) > >>> +#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << > >>> 8) > >>> +#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << > >>> 13) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0 > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << > >>> 6) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << > >>> 19) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << > >>> 24) > >>> +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4 > >>> +#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) > >>> +#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << > >>> 4) > >>> +#
Re: [U-Boot] [PATCH] Revert "env: add spi_flash_read_env function"
Hi Heiko,
I managed to reproduce the issue that you described.
Don't you think it is a little bit too harsh to remove the commit
completely?
I am not sure but how many cases are where UBoot doesn't store anything
in flash? And then lets the linux to update the flash.
Or is wouldn't better to update fw_setenv to set the entire flash to
0x0 when it detects that the CRC error? The same way how the saveenv it
is doing in UBoot?
/Horatiu
The 03/13/2019 12:15, Heiko Schocher wrote:
> This reverts commit 9a9d66f5eff0f443de4c2c6ca3e27771ed14b1b4.
>
> because it breaks fw_setenv and U-Boot interworking, if
> U-Boot environment is stored in a SPI-NOR.
>
> Reproduce it with:
> boot linux with empty Environment and store a variable
> with fw_setenv into it, the Environment is now filled
> with 0xff:
>
> root@ckey5e:10:8e:~# hexdump -C /dev/mtd4
> e9 e8 07 fa 01 62 6f 6f 74 63 6d 64 3d 72 75 6e |.bootcmd=run|
> [...]
> 0f30 7d 00 75 62 69 62 6f 6f 74 76 6f 6c 3d 32 00 00 |}.ubibootvol=2..|
> 0f40 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ||
>
> Boot now U-Boot prints:
>
> Loading Environment from SPI Flash... SF: Detected s25fl128l with page size
> 256 Bytes, erase size 4 KiB, total 16 MiB
> *** Warning - bad CRC, using default environment
>
> Reason is the above commit, as it only reads until \0\0
> is found, and assumes the rest of the Environment
> space is filled with 0x00, which is not the case when
> saving an Environment under linux with fw_setenv.
>
> Signed-off-by: Heiko Schocher
> ---
> I already posted a fix:
> https://lists.denx.de/pipermail/u-boot/2019-January/355148.html
> which I withdrawed:
> https://lists.denx.de/pipermail/u-boot/2019-January/355529.html
>
> because I did not recognised the correlation between fw_setenv
> in linux context and saveenv in U-Boot context.
>
> I think now, best is to revert this commit.
>
> Comments?
>
> This patch drops checkpatch warnings:
> env/sf.c:120: check: Alignment should match open parenthesis
> env/sf.c:224: check: Alignment should match open parenthesis
> env/sf.c:281: check: Alignment should match open parenthesis
>
> but as it is a revert I did not correct them.
>
> env/sf.c | 56 +++-
> 1 file changed, 11 insertions(+), 45 deletions(-)
>
> diff --git a/env/sf.c b/env/sf.c
> index b3dec82c35..23cbad5d88 100644
> --- a/env/sf.c
> +++ b/env/sf.c
> @@ -81,40 +81,6 @@ static int setup_flash_device(void)
> return 0;
> }
>
> -static int is_end(const char *addr, size_t size)
> -{
> - /* The end of env variables is marked by '\0\0' */
> - int i = 0;
> -
> - for (i = 0; i < size - 1; ++i)
> - if (addr[i] == 0x0 && addr[i + 1] == 0x0)
> - return 1;
> - return 0;
> -}
> -
> -static int spi_flash_read_env(struct spi_flash *flash, u32 offset, size_t
> len,
> - void *buf)
> -{
> - u32 addr = 0;
> - u32 page_size = flash->page_size;
> -
> - memset(buf, 0x0, len);
> - for (int i = 0; i < len / page_size; ++i) {
> - int ret = spi_flash_read(flash, offset, page_size,
> - &((char *)buf)[addr]);
> -
> - if (ret < 0)
> - return ret;
> -
> - if (is_end(&((char *)buf)[addr], page_size))
> - return 0;
> -
> - addr += page_size;
> - offset += page_size;
> - }
> - return 0;
> -}
> -
> #if defined(CONFIG_ENV_OFFSET_REDUND)
> #ifdef CMD_SAVEENV
> static int env_sf_save(void)
> @@ -150,8 +116,8 @@ static int env_sf_save(void)
> ret = -ENOMEM;
> goto done;
> }
> - ret = spi_flash_read_env(env_flash, saved_offset,
> - saved_size, saved_buffer);
> + ret = spi_flash_read(env_flash, saved_offset,
> + saved_size, saved_buffer);
> if (ret)
> goto done;
> }
> @@ -217,10 +183,10 @@ static int env_sf_load(void)
> if (ret)
> goto out;
>
> - read1_fail = spi_flash_read_env(env_flash, CONFIG_ENV_OFFSET,
> - CONFIG_ENV_SIZE, tmp_env1);
> - read2_fail = spi_flash_read_env(env_flash, CONFIG_ENV_OFFSET_REDUND,
> - CONFIG_ENV_SIZE, tmp_env2);
> + read1_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET,
> + CONFIG_ENV_SIZE, tmp_env1);
> + read2_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET_REDUND,
> + CONFIG_ENV_SIZE, tmp_env2);
>
> ret = env_import_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2,
> read2_fail);
> @@ -254,8 +220,8 @@ static int env_sf_save(void)
> if (!saved_buffer)
> goto
[U-Boot] [PATCH] net: mscc: ocelot: Fix reset of the phys
The function mscc_miim_reset resets all the phys, but it is called for
each phy separetely. One consequence of this is that the boot time
is increased by 2 seconds.
The fix consists for calling the mscc_miim_reset function only once for
all phys.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/ocelot_switch.c | 27 ++-
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
index bf08c35..815c2da 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -142,18 +142,16 @@ static const unsigned long ocelot_regs_ana_table[] = {
static struct mscc_miim_dev miim[NUM_PHY];
-static int mscc_miim_reset(struct mii_dev *bus)
+static void mscc_phy_reset(void)
{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
-
- if (miim->phy_regs) {
- writel(0, miim->phy_regs + PHY_CFG);
- writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
- | PHY_CFG_ENA, miim->phy_regs + PHY_CFG);
- mdelay(500);
+ writel(0, miim[INTERNAL].phy_regs + PHY_CFG);
+ writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
+ | PHY_CFG_ENA, miim[INTERNAL].phy_regs + PHY_CFG);
+ if (wait_for_bit_le32(miim[INTERNAL].phy_regs + PHY_STAT,
+ PHY_STAT_SUPERVISOR_COMPLETE,
+ true, 2000, false)) {
+ pr_err("Timeout in phy reset\n");
}
-
- return 0;
}
/* For now only setup the internal mdio bus */
@@ -194,7 +192,6 @@ static struct mii_dev *ocelot_mdiobus_init(struct udevice
*dev)
miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);
miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);
bus->priv = [INTERNAL];
- bus->reset = mscc_miim_reset;
bus->read = mscc_miim_read;
bus->write = mscc_miim_write;
@@ -210,13 +207,8 @@ __weak void mscc_switch_reset(void)
static void ocelot_stop(struct udevice *dev)
{
- struct ocelot_private *priv = dev_get_priv(dev);
- int i;
-
mscc_switch_reset();
- for (i = 0; i < NUM_PHY; i++)
- if (priv->bus[i])
- mscc_miim_reset(priv->bus[i]);
+ mscc_phy_reset();
}
static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
@@ -473,6 +465,7 @@ static int ocelot_probe(struct udevice *dev)
}
priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);
+ mscc_phy_reset();
for (i = 0; i < 4; i++) {
phy_connect(priv->bus[INTERNAL], i, dev,
--
2.7.4
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Re: [U-Boot] [PATCH] bootm: mips: Remove boot_reloc_ramdisk
Hi Daniel,
The 03/07/2019 18:33, Daniel Schwierzeck wrote:
> Am Do., 7. März 2019 um 16:49 Uhr schrieb Horatiu Vultur
> :
> >
> > Remove the function boot_reloc_ramdisk in the file arch/mips/lib/bootm
> > because it is relocating again the ramdisk. The function do_bootm_states()
> > already relocates the ramdisk even if it is a legacy uImage or a FIT image.
> >
> > The relocation in the function do_bootm_states() was introduce in the
> > commit c2e7e72bb9f0cb47d024997b381cb64786eb5402 ("bootm: relocate ramdisk
> > if CONFIG_SYS_BOOT_RAMDISK_HIGH set")
> >
> > Signed-off-by: Horatiu Vultur
> > ---
> > arch/mips/lib/bootm.c | 19 ---
> > 1 file changed, 19 deletions(-)
> >
> > diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
> > index deca518..35152cb 100644
> > --- a/arch/mips/lib/bootm.c
> > +++ b/arch/mips/lib/bootm.c
> > @@ -215,23 +215,6 @@ static void linux_env_legacy(bootm_headers_t *images)
> > }
> > }
> >
> > -static int boot_reloc_ramdisk(bootm_headers_t *images)
> > -{
> > - ulong rd_len = images->rd_end - images->rd_start;
> > -
> > - /*
> > -* In case of legacy uImage's, relocation of ramdisk is already done
> > -* by do_bootm_states() and should not repeated in 'bootm prep'.
> > -*/
> > - if (images->state & BOOTM_STATE_RAMDISK) {
> > - debug("## Ramdisk already relocated\n");
> > - return 0;
> > - }
> > -
> > - return boot_ramdisk_high(>lmb, images->rd_start,
> > - rd_len, >initrd_start, >initrd_end);
> > -}
> > -
> > static int boot_reloc_fdt(bootm_headers_t *images)
> > {
> > /*
> > @@ -270,8 +253,6 @@ static int boot_setup_fdt(bootm_headers_t *images)
> >
> > static void boot_prep_linux(bootm_headers_t *images)
> > {
> > - boot_reloc_ramdisk(images);
> > -
> > if (CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && images->ft_len) {
> > boot_reloc_fdt(images);
> > boot_setup_fdt(images);
> > --
> > 2.7.4
> >
>
> Combined with c2e7e72bb9f0cb47d024997b381cb64786eb5402 it looks right.
> But could you please verify that following scenarios still work?
>
> - bootm uImage_legacy_addr initrd_addr
> - bootm start uImage_legacy_addr initrd_addr + bootm loados ramdisk
> fdt prep go (single step)
> - bootm uImage_fit_addr
> - bootm start uImage_fit_addr (single step) + bootm loados ramdisk fdt
> prep go (single step)
I tried all the above cases and all seems to work fine. I managed to
start the linux kernel and it found the ramdisk. One observation
in my case I used also a DT, but I don't see how this can influence the
tests.
>
> --
> - Daniel
--
/Horatiu
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[U-Boot] [PATCH] bootm: mips: Remove boot_reloc_ramdisk
Remove the function boot_reloc_ramdisk in the file arch/mips/lib/bootm
because it is relocating again the ramdisk. The function do_bootm_states()
already relocates the ramdisk even if it is a legacy uImage or a FIT image.
The relocation in the function do_bootm_states() was introduce in the
commit c2e7e72bb9f0cb47d024997b381cb64786eb5402 ("bootm: relocate ramdisk
if CONFIG_SYS_BOOT_RAMDISK_HIGH set")
Signed-off-by: Horatiu Vultur
---
arch/mips/lib/bootm.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index deca518..35152cb 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -215,23 +215,6 @@ static void linux_env_legacy(bootm_headers_t *images)
}
}
-static int boot_reloc_ramdisk(bootm_headers_t *images)
-{
- ulong rd_len = images->rd_end - images->rd_start;
-
- /*
-* In case of legacy uImage's, relocation of ramdisk is already done
-* by do_bootm_states() and should not repeated in 'bootm prep'.
-*/
- if (images->state & BOOTM_STATE_RAMDISK) {
- debug("## Ramdisk already relocated\n");
- return 0;
- }
-
- return boot_ramdisk_high(>lmb, images->rd_start,
- rd_len, >initrd_start, >initrd_end);
-}
-
static int boot_reloc_fdt(bootm_headers_t *images)
{
/*
@@ -270,8 +253,6 @@ static int boot_setup_fdt(bootm_headers_t *images)
static void boot_prep_linux(bootm_headers_t *images)
{
- boot_reloc_ramdisk(images);
-
if (CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && images->ft_len) {
boot_reloc_fdt(images);
boot_setup_fdt(images);
--
2.7.4
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[U-Boot] [PATCH v2 3/4] net: mscc: jaguar2: Add ethenet nodes for Jaguar2.
Add ethernet nodes for Jaguar2 SoCs family. There are 3 pcb in this
family: pcb110, pcb111 and pcb112.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/jr2_pcb110.dts | 67
arch/mips/dts/jr2_pcb111.dts | 352 +++
arch/mips/dts/mscc,jr2.dtsi | 106
arch/mips/dts/serval2_pcb112.dts | 39 +
4 files changed, 564 insertions(+)
diff --git a/arch/mips/dts/jr2_pcb110.dts b/arch/mips/dts/jr2_pcb110.dts
index ddc30ff..bd89f7c 100644
--- a/arch/mips/dts/jr2_pcb110.dts
+++ b/arch/mips/dts/jr2_pcb110.dts
@@ -72,3 +72,70 @@
sgpio-ports = <0x3f00>;
gpio-ranges = < 0 0 96>;
};
+
+ {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+};
+
+ {
+ ethernet-ports {
+
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ phy-handle = <>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ phy-handle = <>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ phy-handle = <>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ phy-handle = <>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ phy-handle = <>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ phy-handle = <>;
+ };
+ };
+};
diff --git a/arch/mips/dts/jr2_pcb111.dts b/arch/mips/dts/jr2_pcb111.dts
index 4d411b6..8b616c8 100644
--- a/arch/mips/dts/jr2_pcb111.dts
+++ b/arch/mips/dts/jr2_pcb111.dts
@@ -72,3 +72,355 @@
sgpio-ports = <0xff00>;
gpio-ranges = < 0 0 96>;
};
+
+ {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
+ phy12: ethernet-phy@12 {
+ reg = <12>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <13>;
+ };
+ phy14: ethernet-phy@14 {
+ reg = <14>;
+ };
+ phy15: ethernet-phy@15 {
+ reg = <15>;
+ };
+ phy16: ethernet-phy@16 {
+ reg = <16>;
+ };
+ phy17: ethernet-phy@17 {
+ reg = <17>;
+ };
+ phy18: ethernet-phy@18 {
+ reg = <18>;
+ };
+ phy19: ethernet-phy@19 {
+ reg = <19>;
+ };
+ phy20: ethernet-phy@20 {
+ reg = <20>;
+ };
+ phy21: ethernet-phy@21 {
+ reg = <21>;
+ };
+ phy22: ethernet-phy@22 {
+ reg = <22>;
+ };
+ phy23: ethernet-phy@23 {
+ reg = <23>;
+ };
+};
+
+ {
+ status = "okay";
+
+ phy24: ethernet-phy@24 {
+ reg = <0>;
+ };
+ phy25: ethernet-phy@25 {
+ reg = <1>;
+ };
+ phy26: ethernet-phy@26 {
+ reg = <2>;
+ };
+ phy27: ethernet-phy@27 {
+ reg
[U-Boot] [PATCH v2 4/4] configs: mscc_jr2: Add network support
Update default confing to use network driver for Jaguar2 SoCs. Signed-off-by: Horatiu Vultur --- configs/mscc_jr2_defconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 9276df2..d6e4bd4 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -28,7 +28,10 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)" @@ -62,3 +65,4 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_LZMA=y +CONFIG_MSCC_JR2_SWITCH=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
In Jaguar2 SoC family there are 3 different pcb. Each of this needs to configure the SerDes and the phys in different ways. Therefore implement the function board_phy_config and serdes_cfg and based on pcb configure them accordingly. Signed-off-by: Horatiu Vultur --- board/mscc/jr2/jr2.c | 443 +++ 1 file changed, 443 insertions(+) diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index 58a4a04..2c04efb 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -6,6 +6,140 @@ #include #include #include +#include + +#define HSIO_ANA_SERDES1G_DES_CFG 0xac +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << 1) +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#defineHSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0 +#defineHSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) +#defineHSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19) +#defineHSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24) +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4 +#defineHSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << 4) +#defineHSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10) +#defineHSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << 13) +#defineHSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17) +#define HSIO_ANA_SERDES1G_SER_CFG 0xb8 +#define HSIO_ANA_SERDES1G_COMMON_CFG 0xbc +#defineHSIO_ANA_SERDES1G_COMMON_CFG_IF_MODEBIT(0) +#defineHSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) +#defineHSIO_ANA_SERDES1G_COMMON_CFG_SYS_RSTBIT(31) +#define HSIO_ANA_SERDES1G_PLL_CFG 0xc0 +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8) +#defineHSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) +#define HSIO_DIG_SERDES1G_DFT_CFG0 0xc8 +#define HSIO_DIG_SERDES1G_TP_CFG 0xd4 +#define HSIO_DIG_SERDES1G_MISC_CFG 0xdc +#defineHSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) +#define HSIO_MCB_SERDES1G_CFG 0xe8 +#defineHSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) +#defineHSIO_MCB_SERDES1G_CFG_ADDR(x) (x) + +#define HSIO_ANA_SERDES6G_DES_CFG 0x11c +#defineHSIO_ANA_SERDES6G_DES_CFG_SWAP_ANA BIT(0) +#defineHSIO_ANA_SERDES6G_DES_CFG_BW_ANA(x) ((x) << 1) +#defineHSIO_ANA_SERDES6G_DES_CFG_SWAP_HYST BIT(4) +#defineHSIO_ANA_SERDES6G_DES_CFG_BW_HYST(x)((x) << 5) +#defineHSIO_ANA_SERDES6G_DES_CFG_CPMD_SEL(x) ((x) << 8) +#defineHSIO_ANA_SERDES6G_DES_CFG_MBTR_CTRL(x) ((x) << 10) +#defineHSIO_ANA_SERDES6G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES6G_IB_CFG 0x120 +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_ENABIT(0) +#defineHSIO_ANA_SERDES6G_IB_CFG_EQZ_ENABIT(1) +#defineHSIO_ANA_SERDES6G_IB_CFG_SAM_ENABIT(2) +#defineHSIO_ANA_SERDES6G_IB_CFG_CAL_ENA(x) ((x) << 3) +#defineHSIO_ANA_SERDES6G_IB_CFG_CONCUR BIT(4) +#defineHSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENABIT(5) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(x) ((x) << 7) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(x) ((x) << 9) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(x) ((x) << 11) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(x) ((x) << 13) +#defineHSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(x) ((x) << 15) +#defineHSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(x) ((x) << 18) +#define
[U-Boot] [PATCH v2 1/4] net: Add MSCC Jaguar2 network driver.
Add network driver for Microsemi Ethernet switch. It is present on Jaguar2 SoCs. Signed-off-by: Horatiu Vultur --- drivers/net/mscc_eswitch/Kconfig | 7 + drivers/net/mscc_eswitch/Makefile | 1 + drivers/net/mscc_eswitch/jr2_switch.c | 735 ++ include/configs/vcoreiii.h| 2 +- 4 files changed, 744 insertions(+), 1 deletion(-) create mode 100644 drivers/net/mscc_eswitch/jr2_switch.c diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 88e5a97..3f9d14b 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -15,3 +15,10 @@ config MSCC_LUTON_SWITCH select PHYLIB help This driver supports the Luton network switch device. + +config MSCC_JR2_SWITCH + bool "Jaguar2 switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Jaguar2 network switch device. diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index 751a839..0a1b863 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o +obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c new file mode 100644 index 000..27b72ee --- /dev/null +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -0,0 +1,735 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mscc_xfer.h" + +#define GCB_MIIM_MII_STATUS0x0 +#defineGCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#defineGCB_MIIM_MII_CMD_SCAN BIT(0) +#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2) +#defineGCB_MIIM_MII_CMD_SINGLE_SCANBIT(3) +#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#defineGCB_MIIM_MII_CMD_VLDBIT(31) +#define GCB_MIIM_DATA 0xC +#defineGCB_MIIM_DATA_ERROR (0x3 << 16) + +#define ANA_AC_RAM_CTRL_RAM_INIT 0x94358 +#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x94370 + +#define ANA_CL_PORT_VLAN_CFG(x)(0x24018 + 0xc8 * (x)) +#defineANA_CL_PORT_VLAN_CFG_AWARE_ENA BIT(19) +#defineANA_CL_PORT_VLAN_CFG_POP_CNT(x) ((x) << 17) + +#define ANA_L2_COMMON_FWD_CFG 0x8a2a8 +#defineANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) + +#define ASM_CFG_STAT_CFG 0x3508 +#define ASM_CFG_PORT(x)(0x36c4 + 0x4 * (x)) +#defineASM_CFG_PORT_NO_PREAMBLE_ENABIT(8) +#defineASM_CFG_PORT_INJ_FORMAT_CFG(x) ((x) << 1) +#define ASM_RAM_CTRL_RAM_INIT 0x39b8 + +#define DEV_DEV_CFG_DEV_RST_CTRL 0x0 +#defineDEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(x) ((x) << 20) +#define DEV_MAC_CFG_MAC_ENA0x1c +#defineDEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4) +#defineDEV_MAC_CFG_MAC_ENA_TX_ENA BIT(0) +#defineDEV_MAC_CFG_MAC_IFG 0x34 +#defineDEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8) +#defineDEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4) +#defineDEV_MAC_CFG_MAC_IFG_RX_IFG1(x) (x) +#defineDEV_PCS1G_CFG_PCS1G_CFG 0x40 +#defineDEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA BIT(0) +#defineDEV_PCS1G_CFG_PCS1G_MODE0x44 +#defineDEV_PCS1G_CFG_PCS1G_SD 0x48 +#defineDEV_PCS1G_CFG_PCS1G_ANEG0x4c +#defineDEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(x) ((x) << 16) + +#define DSM_RAM_CTRL_RAM_INIT 0x8 + +#define HSIO_ANA_SERDES1G_DES_CFG 0xac +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << 1) +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#defineHSIO_ANA_SERDES1
[U-Boot] [PATCH v2 0/4] Add network support for Jaguar2 SoCs
This patch series add network support for Jaguar2 SoCs family. There are following pcb: Jaguar2-24(110), Jaguar2-48(pcb111) and Serval2(pcb112). v2-changes: - create serdes6g_setup and serdes1g_setup functions to be easier to extand for future boards. Horatiu Vultur (4): net: Add MSCC Jaguar2 network driver. board: mscc: jr2: Update MSCC Jaguar2 boards net: mscc: jaguar2: Add ethenet nodes for Jaguar2. configs: mscc_jr2: Add network support arch/mips/dts/jr2_pcb110.dts | 67 arch/mips/dts/jr2_pcb111.dts | 352 arch/mips/dts/mscc,jr2.dtsi | 106 + arch/mips/dts/serval2_pcb112.dts | 39 ++ board/mscc/jr2/jr2.c | 443 configs/mscc_jr2_defconfig| 6 +- drivers/net/mscc_eswitch/Kconfig | 7 + drivers/net/mscc_eswitch/Makefile | 1 + drivers/net/mscc_eswitch/jr2_switch.c | 735 ++ include/configs/vcoreiii.h| 2 +- 10 files changed, 1756 insertions(+), 2 deletions(-) create mode 100644 drivers/net/mscc_eswitch/jr2_switch.c -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
Hi Daniel, The 03/06/2019 14:19, Daniel Schwierzeck wrote: > > > Am 05.03.19 um 12:57 schrieb Horatiu Vultur: > > In Jaguar2 SoC family there are 3 different pcb. Each of this needs > > to configure the SerDes and the phys in different ways. > > Therefore implement the function board_phy_config and serdes_cfg > > and based on pcb configure them accordingly. > > what are the differences between all boards? Can't you model the > different register values somehow as custom DT properties? This method > looks like a lot of code duplication and doesn't scale well when adding > new boards. So there are following boards: - pcb110: it has viper phys that are connected to serdes1g using the interface sgmii - pcb111: it has atom phys that are connected to serdes6g using the interface qsgmii - pcb112: it has viper phys that are connected to serdes6g using the interface sgmii. Do you have an example where I can look, how to add this custom properties? Yes, it looks like a lot code duplication, but there are only few differences between them. I was thinking maybe I can create 2 functions that configure the serdes1g and serdes6g which will get as a paramenter the interface mode. In this way I think it would scale better, because then each new board it would just call these new functions. /Horatiu > > > > > Signed-off-by: Horatiu Vultur > > --- > > board/mscc/jr2/jr2.c | 542 > > +++ > > 1 file changed, 542 insertions(+) > > > > diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c > > index 58a4a04..94e0c5d 100644 > > --- a/board/mscc/jr2/jr2.c > > +++ b/board/mscc/jr2/jr2.c > > @@ -6,6 +6,140 @@ > > #include > > #include > > #include > > +#include > > + > > +#define HSIO_ANA_SERDES1G_DES_CFG 0xac > > +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << > > 1) > > +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << > > 5) > > +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << > > 8) > > +#defineHSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << > > 13) > > +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0 > > +#defineHSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << > > 6) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << > > 19) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << > > 24) > > +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4 > > +#defineHSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) > > +#defineHSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << > > 4) > > +#defineHSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << > > 10) > > +#defineHSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << > > 13) > > +#defineHSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << > > 17) > > +#define HSIO_ANA_SERDES1G_SER_CFG 0xb8 > > +#define HSIO_ANA_SERDES1G_COMMON_CFG 0xbc > > +#defineHSIO_ANA_SERDES1G_COMMON_CFG_IF_MODEBIT(0) > > +#defineHSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) > > +#defineHSIO_ANA_SERDES1G_COMMON_CFG_SYS_RSTBIT(31) > > +#define HSIO_ANA_SERDES1G_PLL_CFG 0xc0 > > +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) > > +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << > > 8) > > +#defineHSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) > > +#define HSIO_DIG_SERDES1G_DFT_CFG0 0xc8 > > +#define HSIO_DIG_SERDES1G_TP_CFG 0xd4 > > +#define HSIO_DIG_SERDES1G_MISC_CFG 0xdc > > +#defineHSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) > > +#define HSIO_MCB_SERDES1G_CFG 0xe8 > > +#defineHSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) > > +#defineHSIO_MCB_SERDES1G_CFG_ADDR(x) (x) > > + > > +#define HSIO_ANA_SERDES6G_DES_CFG 0x11c >
[U-Boot] [PATCH 1/4] net: Add MSCC Jaguar2 network driver.
Add network driver for Microsemi Ethernet switch. It is present on Jaguar2 SoCs. Signed-off-by: Horatiu Vultur --- drivers/net/mscc_eswitch/Kconfig | 7 + drivers/net/mscc_eswitch/Makefile | 1 + drivers/net/mscc_eswitch/jr2_switch.c | 735 ++ include/configs/vcoreiii.h| 2 +- 4 files changed, 744 insertions(+), 1 deletion(-) create mode 100644 drivers/net/mscc_eswitch/jr2_switch.c diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 88e5a97..3f9d14b 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -15,3 +15,10 @@ config MSCC_LUTON_SWITCH select PHYLIB help This driver supports the Luton network switch device. + +config MSCC_JR2_SWITCH + bool "Jaguar2 switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Jaguar2 network switch device. diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index 751a839..0a1b863 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o +obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c new file mode 100644 index 000..27b72ee --- /dev/null +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -0,0 +1,735 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mscc_xfer.h" + +#define GCB_MIIM_MII_STATUS0x0 +#defineGCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#defineGCB_MIIM_MII_CMD_SCAN BIT(0) +#defineGCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#defineGCB_MIIM_MII_CMD_OPR_READ BIT(2) +#defineGCB_MIIM_MII_CMD_SINGLE_SCANBIT(3) +#defineGCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#defineGCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#defineGCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#defineGCB_MIIM_MII_CMD_VLDBIT(31) +#define GCB_MIIM_DATA 0xC +#defineGCB_MIIM_DATA_ERROR (0x3 << 16) + +#define ANA_AC_RAM_CTRL_RAM_INIT 0x94358 +#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x94370 + +#define ANA_CL_PORT_VLAN_CFG(x)(0x24018 + 0xc8 * (x)) +#defineANA_CL_PORT_VLAN_CFG_AWARE_ENA BIT(19) +#defineANA_CL_PORT_VLAN_CFG_POP_CNT(x) ((x) << 17) + +#define ANA_L2_COMMON_FWD_CFG 0x8a2a8 +#defineANA_L2_COMMON_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) + +#define ASM_CFG_STAT_CFG 0x3508 +#define ASM_CFG_PORT(x)(0x36c4 + 0x4 * (x)) +#defineASM_CFG_PORT_NO_PREAMBLE_ENABIT(8) +#defineASM_CFG_PORT_INJ_FORMAT_CFG(x) ((x) << 1) +#define ASM_RAM_CTRL_RAM_INIT 0x39b8 + +#define DEV_DEV_CFG_DEV_RST_CTRL 0x0 +#defineDEV_DEV_CFG_DEV_RST_CTRL_SPEED_SEL(x) ((x) << 20) +#define DEV_MAC_CFG_MAC_ENA0x1c +#defineDEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4) +#defineDEV_MAC_CFG_MAC_ENA_TX_ENA BIT(0) +#defineDEV_MAC_CFG_MAC_IFG 0x34 +#defineDEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8) +#defineDEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4) +#defineDEV_MAC_CFG_MAC_IFG_RX_IFG1(x) (x) +#defineDEV_PCS1G_CFG_PCS1G_CFG 0x40 +#defineDEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA BIT(0) +#defineDEV_PCS1G_CFG_PCS1G_MODE0x44 +#defineDEV_PCS1G_CFG_PCS1G_SD 0x48 +#defineDEV_PCS1G_CFG_PCS1G_ANEG0x4c +#defineDEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(x) ((x) << 16) + +#define DSM_RAM_CTRL_RAM_INIT 0x8 + +#define HSIO_ANA_SERDES1G_DES_CFG 0xac +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << 1) +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#defineHSIO_ANA_SERDES1
[U-Boot] [PATCH 4/4] configs: mscc_jr2: Add network support
Update default confing to use network driver for Jaguar2 SoCs. Signed-off-by: Horatiu Vultur --- configs/mscc_jr2_defconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 9276df2..d6e4bd4 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -28,7 +28,10 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)" @@ -62,3 +65,4 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_LZMA=y +CONFIG_MSCC_JR2_SWITCH=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/4] net: mscc: jaguar2: Add ethenet nodes for Jaguar2.
Add ethernet nodes for Jaguar2 SoCs family. There are 3 pcb in this
family: pcb110, pcb111 and pcb112.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/jr2_pcb110.dts | 67
arch/mips/dts/jr2_pcb111.dts | 352 +++
arch/mips/dts/mscc,jr2.dtsi | 106
arch/mips/dts/serval2_pcb112.dts | 39 +
4 files changed, 564 insertions(+)
diff --git a/arch/mips/dts/jr2_pcb110.dts b/arch/mips/dts/jr2_pcb110.dts
index ddc30ff..bd89f7c 100644
--- a/arch/mips/dts/jr2_pcb110.dts
+++ b/arch/mips/dts/jr2_pcb110.dts
@@ -72,3 +72,70 @@
sgpio-ports = <0x3f00>;
gpio-ranges = < 0 0 96>;
};
+
+ {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+};
+
+ {
+ ethernet-ports {
+
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ phy-handle = <>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ phy-handle = <>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ phy-handle = <>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ phy-handle = <>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ phy-handle = <>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ phy-handle = <>;
+ };
+ };
+};
diff --git a/arch/mips/dts/jr2_pcb111.dts b/arch/mips/dts/jr2_pcb111.dts
index 4d411b6..8b616c8 100644
--- a/arch/mips/dts/jr2_pcb111.dts
+++ b/arch/mips/dts/jr2_pcb111.dts
@@ -72,3 +72,355 @@
sgpio-ports = <0xff00>;
gpio-ranges = < 0 0 96>;
};
+
+ {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
+ phy12: ethernet-phy@12 {
+ reg = <12>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <13>;
+ };
+ phy14: ethernet-phy@14 {
+ reg = <14>;
+ };
+ phy15: ethernet-phy@15 {
+ reg = <15>;
+ };
+ phy16: ethernet-phy@16 {
+ reg = <16>;
+ };
+ phy17: ethernet-phy@17 {
+ reg = <17>;
+ };
+ phy18: ethernet-phy@18 {
+ reg = <18>;
+ };
+ phy19: ethernet-phy@19 {
+ reg = <19>;
+ };
+ phy20: ethernet-phy@20 {
+ reg = <20>;
+ };
+ phy21: ethernet-phy@21 {
+ reg = <21>;
+ };
+ phy22: ethernet-phy@22 {
+ reg = <22>;
+ };
+ phy23: ethernet-phy@23 {
+ reg = <23>;
+ };
+};
+
+ {
+ status = "okay";
+
+ phy24: ethernet-phy@24 {
+ reg = <0>;
+ };
+ phy25: ethernet-phy@25 {
+ reg = <1>;
+ };
+ phy26: ethernet-phy@26 {
+ reg = <2>;
+ };
+ phy27: ethernet-phy@27 {
+ reg
[U-Boot] [PATCH 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
In Jaguar2 SoC family there are 3 different pcb. Each of this needs to configure the SerDes and the phys in different ways. Therefore implement the function board_phy_config and serdes_cfg and based on pcb configure them accordingly. Signed-off-by: Horatiu Vultur --- board/mscc/jr2/jr2.c | 542 +++ 1 file changed, 542 insertions(+) diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index 58a4a04..94e0c5d 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -6,6 +6,140 @@ #include #include #include +#include + +#define HSIO_ANA_SERDES1G_DES_CFG 0xac +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << 1) +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#defineHSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0 +#defineHSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) +#defineHSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19) +#defineHSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24) +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4 +#defineHSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << 4) +#defineHSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10) +#defineHSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << 13) +#defineHSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17) +#define HSIO_ANA_SERDES1G_SER_CFG 0xb8 +#define HSIO_ANA_SERDES1G_COMMON_CFG 0xbc +#defineHSIO_ANA_SERDES1G_COMMON_CFG_IF_MODEBIT(0) +#defineHSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) +#defineHSIO_ANA_SERDES1G_COMMON_CFG_SYS_RSTBIT(31) +#define HSIO_ANA_SERDES1G_PLL_CFG 0xc0 +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8) +#defineHSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) +#define HSIO_DIG_SERDES1G_DFT_CFG0 0xc8 +#define HSIO_DIG_SERDES1G_TP_CFG 0xd4 +#define HSIO_DIG_SERDES1G_MISC_CFG 0xdc +#defineHSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) +#define HSIO_MCB_SERDES1G_CFG 0xe8 +#defineHSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) +#defineHSIO_MCB_SERDES1G_CFG_ADDR(x) (x) + +#define HSIO_ANA_SERDES6G_DES_CFG 0x11c +#defineHSIO_ANA_SERDES6G_DES_CFG_SWAP_ANA BIT(0) +#defineHSIO_ANA_SERDES6G_DES_CFG_BW_ANA(x) ((x) << 1) +#defineHSIO_ANA_SERDES6G_DES_CFG_SWAP_HYST BIT(4) +#defineHSIO_ANA_SERDES6G_DES_CFG_BW_HYST(x)((x) << 5) +#defineHSIO_ANA_SERDES6G_DES_CFG_CPMD_SEL(x) ((x) << 8) +#defineHSIO_ANA_SERDES6G_DES_CFG_MBTR_CTRL(x) ((x) << 10) +#defineHSIO_ANA_SERDES6G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES6G_IB_CFG 0x120 +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_ENABIT(0) +#defineHSIO_ANA_SERDES6G_IB_CFG_EQZ_ENABIT(1) +#defineHSIO_ANA_SERDES6G_IB_CFG_SAM_ENABIT(2) +#defineHSIO_ANA_SERDES6G_IB_CFG_CAL_ENABIT(3) +#defineHSIO_ANA_SERDES6G_IB_CFG_CONCUR BIT(4) +#defineHSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENABIT(5) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(x) ((x) << 7) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(x) ((x) << 9) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(x) ((x) << 11) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(x) ((x) << 13) +#defineHSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(x) ((x) << 15) +#defineHSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(x) ((x) << 18) +#define
[U-Boot] [PATCH 0/4] Add network support for Jaguar2 SoCs
This patch series add network support for Jaguar2 SoCs family. There are following pcb: Jaguar2-24(110), Jaguar2-48(pcb111) and Serval2(pcb112). Horatiu Vultur (4): net: Add MSCC Jaguar2 network driver. board: mscc: jr2: Update MSCC Jaguar2 boards net: mscc: jaguar2: Add ethenet nodes for Jaguar2. configs: mscc_jr2: Add network support arch/mips/dts/jr2_pcb110.dts | 67 arch/mips/dts/jr2_pcb111.dts | 352 arch/mips/dts/mscc,jr2.dtsi | 106 + arch/mips/dts/serval2_pcb112.dts | 39 ++ board/mscc/jr2/jr2.c | 542 + configs/mscc_jr2_defconfig| 6 +- drivers/net/mscc_eswitch/Kconfig | 7 + drivers/net/mscc_eswitch/Makefile | 1 + drivers/net/mscc_eswitch/jr2_switch.c | 735 ++ include/configs/vcoreiii.h| 2 +- 10 files changed, 1855 insertions(+), 2 deletions(-) create mode 100644 drivers/net/mscc_eswitch/jr2_switch.c -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 8/8] configs: mscc_luton: Add network support.
Update default config to use network driver for Luton SoCs. Signed-off-by: Horatiu Vultur --- configs/mscc_luton_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index 7154e97..0fdd9b8 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y +CONFIG_MSCC_LUTON_SWITCH=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_SERIAL=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 7/8] net: Add MSCC Luton networkd driver.
Add network driver for Microsemi Ethernet switch, it is present on Luton SoCs. Signed-off-by: Horatiu Vultur --- drivers/net/mscc_eswitch/Kconfig| 7 + drivers/net/mscc_eswitch/Makefile | 1 + drivers/net/mscc_eswitch/luton_switch.c | 736 3 files changed, 744 insertions(+) create mode 100644 drivers/net/mscc_eswitch/luton_switch.c diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 2f3c8cc..88e5a97 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -8,3 +8,10 @@ config MSCC_OCELOT_SWITCH select PHYLIB help This driver supports the Ocelot network switch device. + +config MSCC_LUTON_SWITCH + bool "Luton switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Luton network switch device. diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index 704f854..751a839 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o +obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c new file mode 100644 index 000..6667614 --- /dev/null +++ b/drivers/net/mscc_eswitch/luton_switch.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mscc_miim.h" +#include "mscc_xfer.h" +#include "mscc_mac_table.h" + +#define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x)) +#defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) +#defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18) +#define ANA_PORT_CPU_FWD_CFG(x)(0x50 + 0x80 * (x)) +#defineANA_PORT_CPU_FWD_CFG_SRC_COPY_ENA BIT(1) +#define ANA_PORT_PORT_CFG(x) (0x60 + 0x80 * (x)) +#defineANA_PORT_PORT_CFG_RECV_ENA BIT(5) +#define ANA_PGID(x)(0x1000 + 4 * (x)) + +#define SYS_FRM_AGING 0x8300 + +#define SYS_SYSTEM_RST_CFG 0x81b0 +#defineSYS_SYSTEM_RST_MEM_INIT BIT(0) +#defineSYS_SYSTEM_RST_MEM_ENA BIT(1) +#defineSYS_SYSTEM_RST_CORE_ENA BIT(2) +#define SYS_PORT_MODE(x) (0x81bc + 0x4 * (x)) +#defineSYS_PORT_MODE_INCL_INJ_HDR BIT(0) +#define SYS_SWITCH_PORT_MODE(x)(0x8294 + 0x4 * (x)) +#defineSYS_SWITCH_PORT_MODE_PORT_ENA BIT(3) +#define SYS_EGR_NO_SHARING 0x8378 +#define SYS_SCH_CPU0x85a0 + +#define REW_PORT_CFG(x)(0x8 + 0x80 * (x)) +#defineREW_PORT_CFG_IFH_INSERT_ENA BIT(7) + +#define GCB_DEVCPU_RST_SOFT_CHIP_RST 0x90 +#defineGCB_DEVCPU_RST_SOFT_CHIP_RST_SOFT_PHY BIT(1) +#define GCB_MISC_STAT 0x11c +#defineGCB_MISC_STAT_PHY_READY BIT(3) + +#defineQS_XTR_MAP(x) (0x10 + 4 * (x)) +#defineQS_XTR_MAP_GRP BIT(4) +#defineQS_XTR_MAP_ENA BIT(0) + +#define HSIO_PLL5G_CFG_PLL5G_CFG2 0x8 + +#define HSIO_RCOMP_CFG_CFG00x20 +#defineHSIO_RCOMP_CFG_CFG0_MODE_SEL(x) ((x) << 8) +#defineHSIO_RCOMP_CFG_CFG0_RUN_CAL BIT(12) +#define HSIO_RCOMP_STATUS 0x24 +#defineHSIO_RCOMP_STATUS_BUSY BIT(12) +#defineHSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0) +#define HSIO_SERDES6G_ANA_CFG_DES_CFG 0x64 +#defineHSIO_SERDES6G_ANA_CFG_DES_CFG_BW_ANA(x) ((x) << 1) +#defineHSIO_SERDES6G_ANA_CFG_DES_CFG_BW_HYST(x)((x) << 5) +#defineHSIO_SERDES6G_ANA_CFG_DES_CFG_MBTR_CTRL(x) ((x) << 10) +#defineHSIO_SERDES6G_ANA_CFG_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_SERDES6G_ANA_CFG_IB_CFG 0x68 +#defineHSIO_SERDES6G_ANA_CFG_IB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_SERDES6G_ANA_CFG_IB_CFG_VBCOM(x) ((x) << 4) +#defineHSIO_SERDES6G_ANA_CFG_IB_CFG_VBAC(x)((x) << 7) +#defineHSIO_SERDES6G_ANA_CFG_IB_CFG_RT(x) ((x) << 9) +#defineHSIO_SERDES6G_ANA_CFG_IB_CFG_RF(x) ((x) << 14) +#define HSIO_SERDES6G_A
[U-Boot] [PATCH v3 6/8] mips: mscc: luton: Add ethernet nodes for Luton.
Add nodes for pcb090 and pcb091. There is currently no support
in Linux for this SoC.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/luton_pcb090.dts | 51 +
arch/mips/dts/luton_pcb091.dts | 51 +
arch/mips/dts/mscc,luton.dtsi | 165 +
3 files changed, 267 insertions(+)
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index 951d8da..315172b 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -55,3 +55,54 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index bf638b2..9b4d628 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -61,3 +61,54 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index d11ec48..de354fe 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -92,5 +92,170 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ switch: switch@101 {
+ compatible = "mscc,vsc7527-switch";
+ reg = <0x1e 0x0100>, // VTSS_TO_DEV_0
+ <0x1f 0x0100>, // VTSS_TO_DEV_1
+ <0x20 0x0100>, // VTSS_TO_DEV_2
+ <0x21 0x0100>, // VTSS_TO_DEV_3
+ <0x22 0x0100>, // VTSS_TO_DEV_4
+ <0x23 0x0100>, // VTSS_TO_DEV_5
+ <0x24 0x0100>, // VTSS_TO_DEV_6
+ <0x25 0x0100>, // VTSS_TO_DEV_7
+ <0x26 0x0100>, // VTSS_TO_DEV_8
+ <0x27 0x0100>, // VTSS_TO_DEV_9
+ <0x28 0x0100>, // VTSS_TO_DEV_10
+ <0x29 0x0100>, // VTSS_TO_DEV_11
+ <0x2a 0x0100>, // VTSS_TO_DEV_12
+ <0x2b 0x0100>, // VTSS_TO_DEV_13
+ <0x2c 0x0100>, // VTSS_TO_DEV_14
+ <0x2d 0x0100>, // VTSS_TO_DEV_15
+ <0x2e 0x0100>, // VTSS_TO_DEV_16
+ <0x2f 0x0100>, // VTSS_TO_DEV_17
+ <0x30 0x0100>, // VTSS_TO_DEV_18
+ <0x31 0x0100>, // VTSS_TO_DEV_19
+ <0x32 0x0100>, // VTSS_TO_DEV_20
+ <0x33 0x0100>, // VTSS_TO_DEV_21
+ <0x34 0x0100>, // VTSS_TO_DEV_22
+ <0x35 0x0100>, // VTSS_TO_DEV_23
+ <0x01 0x1000>, // VTSS_TO_SYS
+ <0x02 0x1000>, // VTSS_TO_ANA
+ <0x03 0x1000>, // VTSS_TO_REW
+ <0x07 0x1000>, // VTSS_TO_DEVCPU_GCB
+ <0x08 0x0100>, // VTSS_TO_DEVCPU_QS
+ <0x0a 0x0100>; // VTSS_TO_HSIO
+ reg-names = "port0", "port1", "port2", "port3",
+ "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10", "port11",
+ "port12", "port13", "port14", "port15",
+ "port16", "port17"
[U-Boot] [PATCH v3 4/8] net: mscc: Move mac_table_add function into different file.
Move the function mac_table_add into a different file,
so it can be reused.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/Makefile | 2 +-
drivers/net/mscc_eswitch/mscc_mac_table.c | 74 +
drivers/net/mscc_eswitch/mscc_mac_table.h | 19 +++
drivers/net/mscc_eswitch/ocelot_switch.c | 90 +--
4 files changed, 107 insertions(+), 78 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/mscc_mac_table.c
create mode 100644 drivers/net/mscc_eswitch/mscc_mac_table.h
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
index 20e8e4c..704f854 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,2 +1,2 @@
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o
mscc_mac_table.o
diff --git a/drivers/net/mscc_eswitch/mscc_mac_table.c
b/drivers/net/mscc_eswitch/mscc_mac_table.c
new file mode 100644
index 000..833e233
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_mac_table.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include "mscc_mac_table.h"
+
+#define ANA_TABLES_MACACCESS_VALID BIT(11)
+#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9)
+#define ANA_TABLES_MACACCESS_DEST_IDX(x) ((x) << 3)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
+#define MACACCESS_CMD_IDLE 0
+#define MACACCESS_CMD_LEARN1
+
+/* MAC table entry types.
+ * ENTRYTYPE_NORMAL is subject to aging.
+ * ENTRYTYPE_LOCKED is not subject to aging.
+ */
+enum macaccess_entry_type {
+ ENTRYTYPE_NORMAL = 0,
+ ENTRYTYPE_LOCKED,
+};
+
+static int vlan_wait_for_completion(void __iomem *regs,
+ const unsigned long *mscc_mac_table_offset)
+{
+ unsigned int val, timeout = 10;
+
+ /* Wait for the issued mac table command to be completed, or timeout.
+* When the command read from ANA_TABLES_MACACCESS is
+* MACACCESS_CMD_IDLE, the issued command completed successfully.
+*/
+ do {
+ val = readl(regs +
+ mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
+ val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
+ } while (val != MACACCESS_CMD_IDLE && timeout--);
+
+ if (!timeout)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+int mscc_mac_table_add(void __iomem *regs,
+ const unsigned long *mscc_mac_table_offset,
+ const unsigned char mac[ETH_LEN], int pgid)
+{
+ u32 macl = 0, mach = 0;
+
+ /* Set the MAC address to handle and the vlan associated in a format
+* understood by the hardware.
+*/
+ mach |= MAC_VID << 16;
+ mach |= ((u32)mac[0]) << 8;
+ mach |= ((u32)mac[1]) << 0;
+ macl |= ((u32)mac[2]) << 24;
+ macl |= ((u32)mac[3]) << 16;
+ macl |= ((u32)mac[4]) << 8;
+ macl |= ((u32)mac[5]) << 0;
+
+ writel(macl, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACLDATA]);
+ writel(mach, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACHDATA]);
+
+ writel(ANA_TABLES_MACACCESS_VALID |
+ ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
+ ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
+ ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
+ regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
+
+ return vlan_wait_for_completion(regs, mscc_mac_table_offset);
+}
diff --git a/drivers/net/mscc_eswitch/mscc_mac_table.h
b/drivers/net/mscc_eswitch/mscc_mac_table.h
new file mode 100644
index 000..17fed2e
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_mac_table.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+
+#define ETH_LEN 6
+#define MAC_VID 1
+
+enum mscc_regs_ana_table {
+ MSCC_ANA_TABLES_MACHDATA,
+ MSCC_ANA_TABLES_MACLDATA,
+ MSCC_ANA_TABLES_MACACCESS,
+};
+
+int mscc_mac_table_add(void __iomem *regs,
+ const unsigned long *mscc_mac_table_offset,
+ const unsigned char mac[ETH_LEN], int pgid);
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
index c33ecd4..40152e6 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -17,6 +17,7 @@
#include "mscc_miim.h"
#include "mscc_xfer.h"
+#include "mscc_mac_table.h"
#define PHY_CFG0x0
#define PHY_CFG_ENA
[U-Boot] [PATCH v3 5/8] net: mscc: Remove unused variables
Remove unused variables in the struct ocelot_private and make
miim variable static.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/ocelot_switch.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
index 40152e6..bf08c35 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -123,19 +123,7 @@ enum ocelot_phy_id {
struct ocelot_private {
void __iomem *regs[TARGET_MAX];
-
struct mii_dev *bus[NUM_PHY];
- struct phy_device *phydev;
- int phy_mode;
- int max_speed;
-
- int rx_pos;
- int rx_siz;
- int rx_off;
- int tx_num;
-
- u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
- void *tx_adj_buf;
};
static const unsigned long ocelot_regs_qs[] = {
@@ -152,7 +140,7 @@ static const unsigned long ocelot_regs_ana_table[] = {
[MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
};
-struct mscc_miim_dev miim[NUM_PHY];
+static struct mscc_miim_dev miim[NUM_PHY];
static int mscc_miim_reset(struct mii_dev *bus)
{
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/8] net: mscc: Move ocelot_send and ocelot_recv in a different file.
This functions can be reused by other MSCC SoCs therefore,
make them more generic and move them in separate files.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/Makefile| 2 +-
drivers/net/mscc_eswitch/mscc_xfer.c | 139 +++
drivers/net/mscc_eswitch/mscc_xfer.h | 20 +
drivers/net/mscc_eswitch/ocelot_switch.c | 130 -
4 files changed, 175 insertions(+), 116 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/mscc_xfer.c
create mode 100644 drivers/net/mscc_eswitch/mscc_xfer.h
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
index 1ceb92a..20e8e4c 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,2 +1,2 @@
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o
diff --git a/drivers/net/mscc_eswitch/mscc_xfer.c
b/drivers/net/mscc_eswitch/mscc_xfer.c
new file mode 100644
index 000..f412901
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_xfer.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include "mscc_xfer.h"
+
+#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
+#define QS_INJ_CTRL_GAP_SIZE(x)((x) << 21)
+#define QS_INJ_CTRL_EOFBIT(19)
+#define QS_INJ_CTRL_SOFBIT(18)
+#define QS_INJ_CTRL_VLD_BYTES(x) ((x) << 16)
+
+#define XTR_EOF_0 ntohl(0x8000u)
+#define XTR_EOF_1 ntohl(0x8001u)
+#define XTR_EOF_2 ntohl(0x8002u)
+#define XTR_EOF_3 ntohl(0x8003u)
+#define XTR_PRUNEDntohl(0x8004u)
+#define XTR_ABORT ntohl(0x8005u)
+#define XTR_ESCAPEntohl(0x8006u)
+#define XTR_NOT_READY ntohl(0x8007u)
+
+#define BUF_CELL_SZ60
+#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
+
+int mscc_send(void __iomem *regs, const unsigned long *mscc_qs_offset,
+ u32 *ifh, size_t ifh_len, u32 *buff, size_t buff_len)
+{
+ int i, count = (buff_len + 3) / 4, last = buff_len % 4;
+
+ writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
+ regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
+
+ for (i = 0; i < ifh_len; i++)
+ writel(ifh[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+ for (i = 0; i < count; i++)
+ writel(buff[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+ /* Add padding */
+ while (i < (BUF_CELL_SZ / 4)) {
+ writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+ i++;
+ }
+
+ /* Indicate EOF and valid bytes in last word */
+ writel(QS_INJ_CTRL_GAP_SIZE(1) |
+ QS_INJ_CTRL_VLD_BYTES(buff_len < BUF_CELL_SZ ? 0 : last) |
+ QS_INJ_CTRL_EOF, regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
+
+ /* Add dummy CRC */
+ writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+ return 0;
+}
+
+int mscc_recv(void __iomem *regs, const unsigned long *mscc_qs_offset,
+ u32 *rxbuf, size_t ifh_len, bool byte_swap)
+{
+ u8 grp = 0; /* Recv everything on CPU group 0 */
+ int i, byte_cnt = 0;
+ bool eof_flag = false, pruned_flag = false, abort_flag = false;
+
+ if (!(readl(regs + mscc_qs_offset[MSCC_QS_XTR_DATA_PRESENT]) &
+ BIT(grp)))
+ return -EAGAIN;
+
+ /* skip IFH */
+ for (i = 0; i < ifh_len; i++)
+ readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+
+ while (!eof_flag) {
+ u32 val = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ u32 cmp = val;
+
+ if (byte_swap)
+ cmp = ntohl(val);
+
+ switch (cmp) {
+ case XTR_NOT_READY:
+ debug("%d NOT_READY...?\n", byte_cnt);
+ break;
+ case XTR_ABORT:
+ *rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ abort_flag = true;
+ eof_flag = true;
+ debug("XTR_ABORT\n");
+ break;
+ case XTR_EOF_0:
+ case XTR_EOF_1:
+ case XTR_EOF_2:
+ case XTR_EOF_3:
+ byte_cnt += XTR_VALID_BYTES(val);
+ *rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ eof_flag = true;
+ debug("EOF\n");
+ break;
+ case XTR_PRUNED:
+ /* But get the last 4 bytes as well */
+ eof_flag = true;
+ pruned_flag = true;
+ debug("PRUNED\n");
+ /* fallthrough */
+
[U-Boot] [PATCH v3 1/8] net: mscc: Move ocelot_switch to mscc_eswitch folder
Move file ocelot_switch to mscc_eswitch to prepare to add
new net drivers for other MSCC SoCs.
Signed-off-by: Horatiu Vultur
---
MAINTAINERS| 2 +-
drivers/net/Kconfig| 7 +--
drivers/net/Makefile | 2 +-
drivers/net/mscc_eswitch/Kconfig | 10 ++
drivers/net/mscc_eswitch/Makefile | 2 ++
drivers/net/{ => mscc_eswitch}/ocelot_switch.c | 0
6 files changed, 15 insertions(+), 8 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/Kconfig
create mode 100644 drivers/net/mscc_eswitch/Makefile
rename drivers/net/{ => mscc_eswitch}/ocelot_switch.c (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cb092e..edbb4ad 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -539,7 +539,7 @@ F: drivers/gpio/mscc_sgpio.c
F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
F: drivers/pinctrl/mscc/
-F: drivers/net/ocelot_switch.c
+F: drivers/net/mscc_eswitch/
MIPS JZ4780
M: Ezequiel Garcia
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 39ce4e8..6a57028 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -432,12 +432,7 @@ config SNI_AVE
This driver implements support for the Socionext AVE Ethernet
controller, as found on the Socionext UniPhier family.
-config MSCC_OCELOT_SWITCH
- bool "Ocelot switch driver"
- depends on DM_ETH && ARCH_MSCC
- select PHYLIB
- help
- This driver supports the Ocelot network switch device.
+source "drivers/net/mscc_eswitch/Kconfig"
config ETHER_ON_FEC1
bool "FEC1"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index e38c164..51be72b 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -75,4 +75,4 @@ obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
+obj-y += mscc_eswitch/
diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig
new file mode 100644
index 000..2f3c8cc
--- /dev/null
+++ b/drivers/net/mscc_eswitch/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Microsemi Corporation
+
+config MSCC_OCELOT_SWITCH
+ bool "Ocelot switch driver"
+ depends on DM_ETH && ARCH_MSCC
+ select PHYLIB
+ help
+ This driver supports the Ocelot network switch device.
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
new file mode 100644
index 000..32f411d
--- /dev/null
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -0,0 +1,2 @@
+
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
diff --git a/drivers/net/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
similarity index 100%
rename from drivers/net/ocelot_switch.c
rename to drivers/net/mscc_eswitch/ocelot_switch.c
--
2.7.4
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[U-Boot] [PATCH v3 2/8] net: mscc: Move miim commands into separate file.
Move miim functions that can be shared in a different file inside
mscc_eswitch.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/Makefile| 2 +-
drivers/net/mscc_eswitch/mscc_miim.c | 74
drivers/net/mscc_eswitch/mscc_miim.h | 12 ++
drivers/net/mscc_eswitch/ocelot_switch.c | 71 +-
4 files changed, 88 insertions(+), 71 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/mscc_miim.c
create mode 100644 drivers/net/mscc_eswitch/mscc_miim.h
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
index 32f411d..1ceb92a 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,2 +1,2 @@
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o
diff --git a/drivers/net/mscc_eswitch/mscc_miim.c
b/drivers/net/mscc_eswitch/mscc_miim.c
new file mode 100644
index 000..419dcc1
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_miim.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include "mscc_miim.h"
+
+#define MIIM_STATUS0x0
+#defineMIIM_STAT_BUSY BIT(3)
+#define MIIM_CMD 0x8
+#defineMIIM_CMD_SCAN BIT(0)
+#defineMIIM_CMD_OPR_WRITE BIT(1)
+#defineMIIM_CMD_OPR_READ BIT(2)
+#defineMIIM_CMD_SINGLE_SCANBIT(3)
+#defineMIIM_CMD_WRDATA(x) ((x) << 4)
+#defineMIIM_CMD_REGAD(x) ((x) << 20)
+#defineMIIM_CMD_PHYAD(x) ((x) << 25)
+#defineMIIM_CMD_VLDBIT(31)
+#define MIIM_DATA 0xC
+#defineMIIM_DATA_ERROR (0x2 << 16)
+
+static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+{
+ return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
+false, 250, false);
+}
+
+int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ u32 val;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
+ miim->regs + MIIM_CMD);
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ val = readl(miim->regs + MIIM_DATA);
+ if (val & MIIM_DATA_ERROR) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = val & 0x;
+ out:
+ return ret;
+}
+
+int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret < 0)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
+ MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
+ out:
+ return ret;
+}
diff --git a/drivers/net/mscc_eswitch/mscc_miim.h
b/drivers/net/mscc_eswitch/mscc_miim.h
new file mode 100644
index 000..0e5d5e3
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_miim.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+struct mscc_miim_dev {
+ void __iomem *regs;
+ void __iomem *phy_regs;
+};
+
+int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg);
+int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg, u16
val);
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
index 9fed26c..a4361e8 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -15,19 +15,7 @@
#include
#include
-#define MIIM_STATUS0x0
-#defineMIIM_STAT_BUSY BIT(3)
-#define MIIM_CMD 0x8
-#defineMIIM_CMD_SCAN BIT(0)
-#defineMIIM_CMD_OPR_WRITE BIT(1)
-#defineMIIM_CMD_OPR_READ BIT(2)
-#defineMIIM_CMD_SINGLE_SCANBIT(3)
-#defineMIIM_CMD_WRDATA(x) ((x) << 4)
-#defineMIIM_CMD_REGAD(x) ((x) << 20)
-#defineMIIM_CMD_PHYAD(x) ((x) << 25)
-#defineMIIM_CMD_VLDBIT(31)
-#define MIIM_DATA 0xC
-#defineMIIM_DATA_ERROR (0x2 << 16)
+#include &
[U-Boot] [PATCH v3 0/8] Add network support for Luton SoCs
This series adds network support for Luton SoCs. Currently
there is not support for Luton SoCs in Linux.
v3-changes:
- reorder the changes of the commits and add Kconfig
in mscc_eswitch folder
v2-changes:
- reuse functions from ocelot for luton network driver
Horatiu Vultur (8):
net: mscc: Move ocelot_switch to mscc_eswitch folder
net: mscc: Move miim commands into separate file.
net: mscc: Move ocelot_send and ocelot_recv in a different file.
net: mscc: Move mac_table_add function into different file.
net: mscc: Remove unused variables
mips: mscc: luton: Add ethernet nodes for Luton.
net: Add MSCC Luton networkd driver.
configs: mscc_luton: Add network support.
MAINTAINERS| 2 +-
arch/mips/dts/luton_pcb090.dts | 51 ++
arch/mips/dts/luton_pcb091.dts | 51 ++
arch/mips/dts/mscc,luton.dtsi | 165 ++
configs/mscc_luton_defconfig | 1 +
drivers/net/Kconfig| 7 +-
drivers/net/Makefile | 2 +-
drivers/net/mscc_eswitch/Kconfig | 17 +
drivers/net/mscc_eswitch/Makefile | 3 +
drivers/net/mscc_eswitch/luton_switch.c| 736 +
drivers/net/mscc_eswitch/mscc_mac_table.c | 74 +++
drivers/net/mscc_eswitch/mscc_mac_table.h | 19 +
drivers/net/mscc_eswitch/mscc_miim.c | 74 +++
drivers/net/mscc_eswitch/mscc_miim.h | 12 +
drivers/net/mscc_eswitch/mscc_xfer.c | 139 +
drivers/net/mscc_eswitch/mscc_xfer.h | 20 +
drivers/net/{ => mscc_eswitch}/ocelot_switch.c | 299 +-
17 files changed, 1392 insertions(+), 280 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/Kconfig
create mode 100644 drivers/net/mscc_eswitch/Makefile
create mode 100644 drivers/net/mscc_eswitch/luton_switch.c
create mode 100644 drivers/net/mscc_eswitch/mscc_mac_table.c
create mode 100644 drivers/net/mscc_eswitch/mscc_mac_table.h
create mode 100644 drivers/net/mscc_eswitch/mscc_miim.c
create mode 100644 drivers/net/mscc_eswitch/mscc_miim.h
create mode 100644 drivers/net/mscc_eswitch/mscc_xfer.c
create mode 100644 drivers/net/mscc_eswitch/mscc_xfer.h
rename drivers/net/{ => mscc_eswitch}/ocelot_switch.c (62%)
--
2.7.4
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[U-Boot] [PATCH v2 2/8] net: mscc: Move miim commands into separate file.
Move miim functions that can be shared in a different file inside
mscc_eswitch.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/Makefile| 2 +-
drivers/net/mscc_eswitch/mscc_miim.c | 74
drivers/net/mscc_eswitch/mscc_miim.h | 12 ++
drivers/net/mscc_eswitch/ocelot_switch.c | 71 +-
4 files changed, 88 insertions(+), 71 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/mscc_miim.c
create mode 100644 drivers/net/mscc_eswitch/mscc_miim.h
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
index 32f411d..1ceb92a 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,2 +1,2 @@
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o
diff --git a/drivers/net/mscc_eswitch/mscc_miim.c
b/drivers/net/mscc_eswitch/mscc_miim.c
new file mode 100644
index 000..419dcc1
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_miim.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include "mscc_miim.h"
+
+#define MIIM_STATUS0x0
+#defineMIIM_STAT_BUSY BIT(3)
+#define MIIM_CMD 0x8
+#defineMIIM_CMD_SCAN BIT(0)
+#defineMIIM_CMD_OPR_WRITE BIT(1)
+#defineMIIM_CMD_OPR_READ BIT(2)
+#defineMIIM_CMD_SINGLE_SCANBIT(3)
+#defineMIIM_CMD_WRDATA(x) ((x) << 4)
+#defineMIIM_CMD_REGAD(x) ((x) << 20)
+#defineMIIM_CMD_PHYAD(x) ((x) << 25)
+#defineMIIM_CMD_VLDBIT(31)
+#define MIIM_DATA 0xC
+#defineMIIM_DATA_ERROR (0x2 << 16)
+
+static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+{
+ return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
+false, 250, false);
+}
+
+int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ u32 val;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
+ miim->regs + MIIM_CMD);
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ val = readl(miim->regs + MIIM_DATA);
+ if (val & MIIM_DATA_ERROR) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = val & 0x;
+ out:
+ return ret;
+}
+
+int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret < 0)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
+ MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
+ out:
+ return ret;
+}
diff --git a/drivers/net/mscc_eswitch/mscc_miim.h
b/drivers/net/mscc_eswitch/mscc_miim.h
new file mode 100644
index 000..0e5d5e3
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_miim.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+struct mscc_miim_dev {
+ void __iomem *regs;
+ void __iomem *phy_regs;
+};
+
+int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg);
+int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg, u16
val);
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
index 9fed26c..a4361e8 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -15,19 +15,7 @@
#include
#include
-#define MIIM_STATUS0x0
-#defineMIIM_STAT_BUSY BIT(3)
-#define MIIM_CMD 0x8
-#defineMIIM_CMD_SCAN BIT(0)
-#defineMIIM_CMD_OPR_WRITE BIT(1)
-#defineMIIM_CMD_OPR_READ BIT(2)
-#defineMIIM_CMD_SINGLE_SCANBIT(3)
-#defineMIIM_CMD_WRDATA(x) ((x) << 4)
-#defineMIIM_CMD_REGAD(x) ((x) << 20)
-#defineMIIM_CMD_PHYAD(x) ((x) << 25)
-#defineMIIM_CMD_VLDBIT(31)
-#define MIIM_DATA 0xC
-#defineMIIM_DATA_ERROR (0x2 << 16)
+#include &
[U-Boot] [PATCH v2 7/8] net: Add MSCC Luton networkd driver.
Add network driver for Microsemi Ethernet switch, it is present on Luton SoCs. Signed-off-by: Horatiu Vultur --- drivers/net/Kconfig | 7 + drivers/net/Makefile| 2 +- drivers/net/mscc_eswitch/Makefile | 1 + drivers/net/mscc_eswitch/luton_switch.c | 736 4 files changed, 745 insertions(+), 1 deletion(-) create mode 100644 drivers/net/mscc_eswitch/luton_switch.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 39ce4e8..d82037d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -439,6 +439,13 @@ config MSCC_OCELOT_SWITCH help This driver supports the Ocelot network switch device. +config MSCC_LUTON_SWITCH + bool "Luton switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Luton network switch device. + config ETHER_ON_FEC1 bool "FEC1" depends on MPC8XX_FEC diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 3ab7f26..51be72b 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -75,4 +75,4 @@ obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_SNI_AVE) += sni_ave.o obj-y += ti/ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o -obj-$(CONFIG_MSCC_OCELOT_SWITCH) += mscc_eswitch/ +obj-y += mscc_eswitch/ diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index 704f854..751a839 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o +obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c new file mode 100644 index 000..dee6f15 --- /dev/null +++ b/drivers/net/mscc_eswitch/luton_switch.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mscc_miim.h" +#include "mscc_xfer.h" +#include "mscc_mac_table.h" + +#define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x)) +#defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) +#defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18) +#define ANA_PORT_CPU_FWD_CFG(x)(0x50 + 0x80 * (x)) +#defineANA_PORT_CPU_FWD_CFG_SRC_COPY_ENA BIT(1) +#define ANA_PORT_PORT_CFG(x) (0x60 + 0x80 * (x)) +#defineANA_PORT_PORT_CFG_RECV_ENA BIT(5) +#define ANA_PGID(x)(0x1000 + 4 * (x)) + +#define SYS_FRM_AGING 0x8300 + +#define SYS_SYSTEM_RST_CFG 0x81b0 +#defineSYS_SYSTEM_RST_MEM_INIT BIT(0) +#defineSYS_SYSTEM_RST_MEM_ENA BIT(1) +#defineSYS_SYSTEM_RST_CORE_ENA BIT(2) +#define SYS_PORT_MODE(x) (0x81bc + 0x4 * (x)) +#defineSYS_PORT_MODE_INCL_INJ_HDR BIT(0) +#define SYS_SWITCH_PORT_MODE(x)(0x8294 + 0x4 * (x)) +#defineSYS_SWITCH_PORT_MODE_PORT_ENA BIT(3) +#define SYS_EGR_NO_SHARING 0x8378 +#define SYS_SCH_CPU0x85a0 + +#define REW_PORT_CFG(x)(0x8 + 0x80 * (x)) +#defineREW_PORT_CFG_IFH_INSERT_ENA BIT(7) + +#define GCB_DEVCPU_RST_SOFT_CHIP_RST 0x90 +#defineGCB_DEVCPU_RST_SOFT_CHIP_RST_SOFT_PHY BIT(1) +#define GCB_MISC_STAT 0x11c +#defineGCB_MISC_STAT_PHY_READY BIT(3) + +#defineQS_XTR_MAP(x) (0x10 + 4 * (x)) +#defineQS_XTR_MAP_GRP BIT(4) +#defineQS_XTR_MAP_ENA BIT(0) + +#define HSIO_PLL5G_CFG_PLL5G_CFG2 0x8 + +#define HSIO_RCOMP_CFG_CFG00x20 +#defineHSIO_RCOMP_CFG_CFG0_MODE_SEL(x) ((x) << 8) +#defineHSIO_RCOMP_CFG_CFG0_RUN_CAL BIT(12) +#define HSIO_RCOMP_STATUS 0x24 +#defineHSIO_RCOMP_STATUS_BUSY BIT(12) +#defineHSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0) +#define HSIO_SERDES6G_ANA_CFG_DES_CFG 0x64 +#defineHSIO_SERDES6G_ANA_CFG_DES_CFG_BW_ANA(x) ((x) << 1) +#defineHSIO_SERDES6G_ANA_CFG_DES_CFG_BW_HYST(x)((x) << 5) +#defineHSIO_SERDES6G_ANA_CFG_DES_CFG_MBTR_CTRL(x) ((x) << 10) +#defineHSIO_SERDES6G_ANA_CFG_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_SERDES6G_ANA_CFG_IB_C
[U-Boot] [PATCH v2 8/8] configs: mscc_luton: Add network support.
Update default config to use network driver for Luton SoCs. Signed-off-by: Horatiu Vultur --- configs/mscc_luton_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index 7154e97..0fdd9b8 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y +CONFIG_MSCC_LUTON_SWITCH=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_SERIAL=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 6/8] mips: mscc: luton: Add ethernet nodes for Luton.
Add nodes for pcb090 and pcb091. There is currently no support
in Linux for this SoC.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/luton_pcb090.dts | 51 +
arch/mips/dts/luton_pcb091.dts | 51 +
arch/mips/dts/mscc,luton.dtsi | 165 +
3 files changed, 267 insertions(+)
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index 951d8da..315172b 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -55,3 +55,54 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index bf638b2..9b4d628 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -61,3 +61,54 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index d11ec48..de354fe 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -92,5 +92,170 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ switch: switch@101 {
+ compatible = "mscc,vsc7527-switch";
+ reg = <0x1e 0x0100>, // VTSS_TO_DEV_0
+ <0x1f 0x0100>, // VTSS_TO_DEV_1
+ <0x20 0x0100>, // VTSS_TO_DEV_2
+ <0x21 0x0100>, // VTSS_TO_DEV_3
+ <0x22 0x0100>, // VTSS_TO_DEV_4
+ <0x23 0x0100>, // VTSS_TO_DEV_5
+ <0x24 0x0100>, // VTSS_TO_DEV_6
+ <0x25 0x0100>, // VTSS_TO_DEV_7
+ <0x26 0x0100>, // VTSS_TO_DEV_8
+ <0x27 0x0100>, // VTSS_TO_DEV_9
+ <0x28 0x0100>, // VTSS_TO_DEV_10
+ <0x29 0x0100>, // VTSS_TO_DEV_11
+ <0x2a 0x0100>, // VTSS_TO_DEV_12
+ <0x2b 0x0100>, // VTSS_TO_DEV_13
+ <0x2c 0x0100>, // VTSS_TO_DEV_14
+ <0x2d 0x0100>, // VTSS_TO_DEV_15
+ <0x2e 0x0100>, // VTSS_TO_DEV_16
+ <0x2f 0x0100>, // VTSS_TO_DEV_17
+ <0x30 0x0100>, // VTSS_TO_DEV_18
+ <0x31 0x0100>, // VTSS_TO_DEV_19
+ <0x32 0x0100>, // VTSS_TO_DEV_20
+ <0x33 0x0100>, // VTSS_TO_DEV_21
+ <0x34 0x0100>, // VTSS_TO_DEV_22
+ <0x35 0x0100>, // VTSS_TO_DEV_23
+ <0x01 0x1000>, // VTSS_TO_SYS
+ <0x02 0x1000>, // VTSS_TO_ANA
+ <0x03 0x1000>, // VTSS_TO_REW
+ <0x07 0x1000>, // VTSS_TO_DEVCPU_GCB
+ <0x08 0x0100>, // VTSS_TO_DEVCPU_QS
+ <0x0a 0x0100>; // VTSS_TO_HSIO
+ reg-names = "port0", "port1", "port2", "port3",
+ "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10", "port11",
+ "port12", "port13", "port14", "port15",
+ "port16", "port17"
[U-Boot] [PATCH v2 5/8] net: mscc: Remove unused variables
Remove unused variables in the struct ocelot_private.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/ocelot_switch.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
index 40152e6..6546b4f 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -123,19 +123,7 @@ enum ocelot_phy_id {
struct ocelot_private {
void __iomem *regs[TARGET_MAX];
-
struct mii_dev *bus[NUM_PHY];
- struct phy_device *phydev;
- int phy_mode;
- int max_speed;
-
- int rx_pos;
- int rx_siz;
- int rx_off;
- int tx_num;
-
- u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
- void *tx_adj_buf;
};
static const unsigned long ocelot_regs_qs[] = {
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/8] net: mscc: Move mac_table_add function into different file.
Move the function mac_table_add into a different file,
so it can be reused.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/Makefile | 2 +-
drivers/net/mscc_eswitch/mscc_mac_table.c | 74 +
drivers/net/mscc_eswitch/mscc_mac_table.h | 19 +++
drivers/net/mscc_eswitch/ocelot_switch.c | 90 +--
4 files changed, 107 insertions(+), 78 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/mscc_mac_table.c
create mode 100644 drivers/net/mscc_eswitch/mscc_mac_table.h
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
index 20e8e4c..704f854 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,2 +1,2 @@
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o
mscc_mac_table.o
diff --git a/drivers/net/mscc_eswitch/mscc_mac_table.c
b/drivers/net/mscc_eswitch/mscc_mac_table.c
new file mode 100644
index 000..833e233
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_mac_table.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include "mscc_mac_table.h"
+
+#define ANA_TABLES_MACACCESS_VALID BIT(11)
+#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9)
+#define ANA_TABLES_MACACCESS_DEST_IDX(x) ((x) << 3)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
+#define MACACCESS_CMD_IDLE 0
+#define MACACCESS_CMD_LEARN1
+
+/* MAC table entry types.
+ * ENTRYTYPE_NORMAL is subject to aging.
+ * ENTRYTYPE_LOCKED is not subject to aging.
+ */
+enum macaccess_entry_type {
+ ENTRYTYPE_NORMAL = 0,
+ ENTRYTYPE_LOCKED,
+};
+
+static int vlan_wait_for_completion(void __iomem *regs,
+ const unsigned long *mscc_mac_table_offset)
+{
+ unsigned int val, timeout = 10;
+
+ /* Wait for the issued mac table command to be completed, or timeout.
+* When the command read from ANA_TABLES_MACACCESS is
+* MACACCESS_CMD_IDLE, the issued command completed successfully.
+*/
+ do {
+ val = readl(regs +
+ mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
+ val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
+ } while (val != MACACCESS_CMD_IDLE && timeout--);
+
+ if (!timeout)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+int mscc_mac_table_add(void __iomem *regs,
+ const unsigned long *mscc_mac_table_offset,
+ const unsigned char mac[ETH_LEN], int pgid)
+{
+ u32 macl = 0, mach = 0;
+
+ /* Set the MAC address to handle and the vlan associated in a format
+* understood by the hardware.
+*/
+ mach |= MAC_VID << 16;
+ mach |= ((u32)mac[0]) << 8;
+ mach |= ((u32)mac[1]) << 0;
+ macl |= ((u32)mac[2]) << 24;
+ macl |= ((u32)mac[3]) << 16;
+ macl |= ((u32)mac[4]) << 8;
+ macl |= ((u32)mac[5]) << 0;
+
+ writel(macl, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACLDATA]);
+ writel(mach, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACHDATA]);
+
+ writel(ANA_TABLES_MACACCESS_VALID |
+ ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
+ ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
+ ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
+ regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
+
+ return vlan_wait_for_completion(regs, mscc_mac_table_offset);
+}
diff --git a/drivers/net/mscc_eswitch/mscc_mac_table.h
b/drivers/net/mscc_eswitch/mscc_mac_table.h
new file mode 100644
index 000..17fed2e
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_mac_table.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+
+#define ETH_LEN 6
+#define MAC_VID 1
+
+enum mscc_regs_ana_table {
+ MSCC_ANA_TABLES_MACHDATA,
+ MSCC_ANA_TABLES_MACLDATA,
+ MSCC_ANA_TABLES_MACACCESS,
+};
+
+int mscc_mac_table_add(void __iomem *regs,
+ const unsigned long *mscc_mac_table_offset,
+ const unsigned char mac[ETH_LEN], int pgid);
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
index c33ecd4..40152e6 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -17,6 +17,7 @@
#include "mscc_miim.h"
#include "mscc_xfer.h"
+#include "mscc_mac_table.h"
#define PHY_CFG0x0
#define PHY_CFG_ENA
[U-Boot] [PATCH v2 3/8] net: mscc: Move ocelot_send and ocelot_recv in a different file.
This functions can be reused by other MSCC SoCs therefore,
make them more generic and move them in separate files.
Signed-off-by: Horatiu Vultur
---
drivers/net/mscc_eswitch/Makefile| 2 +-
drivers/net/mscc_eswitch/mscc_xfer.c | 139 +++
drivers/net/mscc_eswitch/mscc_xfer.h | 20 +
drivers/net/mscc_eswitch/ocelot_switch.c | 130 -
4 files changed, 175 insertions(+), 116 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/mscc_xfer.c
create mode 100644 drivers/net/mscc_eswitch/mscc_xfer.h
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
index 1ceb92a..20e8e4c 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,2 +1,2 @@
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o
diff --git a/drivers/net/mscc_eswitch/mscc_xfer.c
b/drivers/net/mscc_eswitch/mscc_xfer.c
new file mode 100644
index 000..f412901
--- /dev/null
+++ b/drivers/net/mscc_eswitch/mscc_xfer.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include "mscc_xfer.h"
+
+#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
+#define QS_INJ_CTRL_GAP_SIZE(x)((x) << 21)
+#define QS_INJ_CTRL_EOFBIT(19)
+#define QS_INJ_CTRL_SOFBIT(18)
+#define QS_INJ_CTRL_VLD_BYTES(x) ((x) << 16)
+
+#define XTR_EOF_0 ntohl(0x8000u)
+#define XTR_EOF_1 ntohl(0x8001u)
+#define XTR_EOF_2 ntohl(0x8002u)
+#define XTR_EOF_3 ntohl(0x8003u)
+#define XTR_PRUNEDntohl(0x8004u)
+#define XTR_ABORT ntohl(0x8005u)
+#define XTR_ESCAPEntohl(0x8006u)
+#define XTR_NOT_READY ntohl(0x8007u)
+
+#define BUF_CELL_SZ60
+#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
+
+int mscc_send(void __iomem *regs, const unsigned long *mscc_qs_offset,
+ u32 *ifh, size_t ifh_len, u32 *buff, size_t buff_len)
+{
+ int i, count = (buff_len + 3) / 4, last = buff_len % 4;
+
+ writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
+ regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
+
+ for (i = 0; i < ifh_len; i++)
+ writel(ifh[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+ for (i = 0; i < count; i++)
+ writel(buff[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+ /* Add padding */
+ while (i < (BUF_CELL_SZ / 4)) {
+ writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+ i++;
+ }
+
+ /* Indicate EOF and valid bytes in last word */
+ writel(QS_INJ_CTRL_GAP_SIZE(1) |
+ QS_INJ_CTRL_VLD_BYTES(buff_len < BUF_CELL_SZ ? 0 : last) |
+ QS_INJ_CTRL_EOF, regs + mscc_qs_offset[MSCC_QS_INJ_CTRL]);
+
+ /* Add dummy CRC */
+ writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]);
+
+ return 0;
+}
+
+int mscc_recv(void __iomem *regs, const unsigned long *mscc_qs_offset,
+ u32 *rxbuf, size_t ifh_len, bool byte_swap)
+{
+ u8 grp = 0; /* Recv everything on CPU group 0 */
+ int i, byte_cnt = 0;
+ bool eof_flag = false, pruned_flag = false, abort_flag = false;
+
+ if (!(readl(regs + mscc_qs_offset[MSCC_QS_XTR_DATA_PRESENT]) &
+ BIT(grp)))
+ return -EAGAIN;
+
+ /* skip IFH */
+ for (i = 0; i < ifh_len; i++)
+ readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+
+ while (!eof_flag) {
+ u32 val = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ u32 cmp = val;
+
+ if (byte_swap)
+ cmp = ntohl(val);
+
+ switch (cmp) {
+ case XTR_NOT_READY:
+ debug("%d NOT_READY...?\n", byte_cnt);
+ break;
+ case XTR_ABORT:
+ *rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ abort_flag = true;
+ eof_flag = true;
+ debug("XTR_ABORT\n");
+ break;
+ case XTR_EOF_0:
+ case XTR_EOF_1:
+ case XTR_EOF_2:
+ case XTR_EOF_3:
+ byte_cnt += XTR_VALID_BYTES(val);
+ *rxbuf = readl(regs + mscc_qs_offset[MSCC_QS_XTR_RD]);
+ eof_flag = true;
+ debug("EOF\n");
+ break;
+ case XTR_PRUNED:
+ /* But get the last 4 bytes as well */
+ eof_flag = true;
+ pruned_flag = true;
+ debug("PRUNED\n");
+ /* fallthrough */
+
[U-Boot] [PATCH v2 0/8] Add network support for Luton SoCs
This series adds network support for Luton SoCs. Currently
there is not support for Luton SoCs in Linux.
v2-changes:
- reuse functions from ocelot for luton network driver
Horatiu Vultur (8):
net: mscc: Move ocelot_switch to mscc_switch folder.
net: mscc: Move miim commands into separate file.
net: mscc: Move ocelot_send and ocelot_recv in a different file.
net: mscc: Move mac_table_add function into different file.
net: mscc: Remove unused variables
mips: mscc: luton: Add ethernet nodes for Luton.
net: Add MSCC Luton networkd driver.
configs: mscc_luton: Add network support.
MAINTAINERS| 2 +-
arch/mips/dts/luton_pcb090.dts | 51 ++
arch/mips/dts/luton_pcb091.dts | 51 ++
arch/mips/dts/mscc,luton.dtsi | 165 ++
configs/mscc_luton_defconfig | 1 +
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 2 +-
drivers/net/mscc_eswitch/Makefile | 3 +
drivers/net/mscc_eswitch/luton_switch.c| 736 +
drivers/net/mscc_eswitch/mscc_mac_table.c | 74 +++
drivers/net/mscc_eswitch/mscc_mac_table.h | 19 +
drivers/net/mscc_eswitch/mscc_miim.c | 74 +++
drivers/net/mscc_eswitch/mscc_miim.h | 12 +
drivers/net/mscc_eswitch/mscc_xfer.c | 139 +
drivers/net/mscc_eswitch/mscc_xfer.h | 20 +
drivers/net/{ => mscc_eswitch}/ocelot_switch.c | 297 +-
16 files changed, 1380 insertions(+), 273 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/Makefile
create mode 100644 drivers/net/mscc_eswitch/luton_switch.c
create mode 100644 drivers/net/mscc_eswitch/mscc_mac_table.c
create mode 100644 drivers/net/mscc_eswitch/mscc_mac_table.h
create mode 100644 drivers/net/mscc_eswitch/mscc_miim.c
create mode 100644 drivers/net/mscc_eswitch/mscc_miim.h
create mode 100644 drivers/net/mscc_eswitch/mscc_xfer.c
create mode 100644 drivers/net/mscc_eswitch/mscc_xfer.h
rename drivers/net/{ => mscc_eswitch}/ocelot_switch.c (62%)
--
2.7.4
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[U-Boot] [PATCH v2 1/8] net: mscc: Move ocelot_switch to mscc_switch folder.
Move file ocelot_switch to mscc_switch to prepare to add
new net drivers for other MSCC SoCs.
Signed-off-by: Horatiu Vultur
---
MAINTAINERS| 2 +-
drivers/net/Makefile | 2 +-
drivers/net/mscc_eswitch/Makefile | 2 ++
drivers/net/{ => mscc_eswitch}/ocelot_switch.c | 0
4 files changed, 4 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/mscc_eswitch/Makefile
rename drivers/net/{ => mscc_eswitch}/ocelot_switch.c (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cb092e..edbb4ad 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -539,7 +539,7 @@ F: drivers/gpio/mscc_sgpio.c
F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
F: drivers/pinctrl/mscc/
-F: drivers/net/ocelot_switch.c
+F: drivers/net/mscc_eswitch/
MIPS JZ4780
M: Ezequiel Garcia
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index e38c164..3ab7f26 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -75,4 +75,4 @@ obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += mscc_eswitch/
diff --git a/drivers/net/mscc_eswitch/Makefile
b/drivers/net/mscc_eswitch/Makefile
new file mode 100644
index 000..32f411d
--- /dev/null
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -0,0 +1,2 @@
+
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
diff --git a/drivers/net/ocelot_switch.c
b/drivers/net/mscc_eswitch/ocelot_switch.c
similarity index 100%
rename from drivers/net/ocelot_switch.c
rename to drivers/net/mscc_eswitch/ocelot_switch.c
--
2.7.4
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[U-Boot] [PATCH] MSCC: Fix Jaguar2 board detection.
When power cycle the Jaguar2 boards, it couldn't read the
phys, therefore it always deduce that the board type is
pcb111.
Add a small delay after setting the gpio pins, fix the
issue.
Signed-off-by: Horatiu Vultur
---
board/mscc/jr2/jr2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
index 226181f..58a4a04 100644
--- a/board/mscc/jr2/jr2.c
+++ b/board/mscc/jr2/jr2.c
@@ -80,6 +80,9 @@ static void do_board_detect(void)
for (i = 56; i < 60; i++)
vcoreiii_gpio_set_alternate(i, 1);
+ /* small delay for settling the pins */
+ mdelay(30);
+
if (mscc_phy_rd(0, 0x10, 0x3, ) == 0 &&
((pval >> 4) & 0x3F) == 0x3c) {
gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
--
2.7.4
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[U-Boot] [PATCH] MSCC: Jaguar2 enable debug uart
Enable debug uart for Jaguar2 SoC family.
Signed-off-by: Horatiu Vultur
---
board/mscc/jr2/jr2.c | 7 +++
configs/mscc_jr2_defconfig | 6 ++
2 files changed, 13 insertions(+)
diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
index eac4dca..226181f 100644
--- a/board/mscc/jr2/jr2.c
+++ b/board/mscc/jr2/jr2.c
@@ -64,6 +64,13 @@ static void vcoreiii_gpio_set_alternate(int gpio, int mode)
}
}
+void board_debug_uart_init(void)
+{
+ /* too early for the pinctrl driver, so configure the UART pins here */
+ vcoreiii_gpio_set_alternate(10, 1);
+ vcoreiii_gpio_set_alternate(11, 1);
+}
+
static void do_board_detect(void)
{
int i;
diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig
index 040e1e1..d80ca41 100644
--- a/configs/mscc_jr2_defconfig
+++ b/configs/mscc_jr2_defconfig
@@ -56,3 +56,9 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_LZMA=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x7010
+CONFIG_DEBUG_UART_CLOCK=25000
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
--
2.7.4
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[U-Boot] [PATCH 3/3] configs: mscc_luton: add network support.
Update default config to use network driver for Luton SoC. Signed-off-by: Horatiu Vultur --- configs/mscc_luton_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index 7154e97..0fdd9b8 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y +CONFIG_MSCC_LUTON_SWITCH=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_SERIAL=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/3] net: add MSCC Luton switch support
Add network driver for Microsemi Ethernet switch is present on Luton SoCs. Signed-off-by: Horatiu Vultur --- MAINTAINERS| 1 + drivers/net/Kconfig| 7 + drivers/net/Makefile | 1 + drivers/net/luton_switch.c | 972 + 4 files changed, 981 insertions(+) create mode 100644 drivers/net/luton_switch.c diff --git a/MAINTAINERS b/MAINTAINERS index 1cb092e..253274b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -540,6 +540,7 @@ F: drivers/spi/mscc_bb_spi.c F: include/configs/vcoreiii.h F: drivers/pinctrl/mscc/ F: drivers/net/ocelot_switch.c +F: drivers/net/luton_switch.c MIPS JZ4780 M: Ezequiel Garcia diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 39ce4e8..d82037d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -439,6 +439,13 @@ config MSCC_OCELOT_SWITCH help This driver supports the Ocelot network switch device. +config MSCC_LUTON_SWITCH + bool "Luton switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Luton network switch device. + config ETHER_ON_FEC1 bool "FEC1" depends on MPC8XX_FEC diff --git a/drivers/net/Makefile b/drivers/net/Makefile index e38c164..470660d 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -76,3 +76,4 @@ obj-$(CONFIG_SNI_AVE) += sni_ave.o obj-y += ti/ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o +obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o diff --git a/drivers/net/luton_switch.c b/drivers/net/luton_switch.c new file mode 100644 index 000..816b5fe --- /dev/null +++ b/drivers/net/luton_switch.c @@ -0,0 +1,972 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MIIM_STATUS0x0 +#defineMIIM_STATUS_BUSYBIT(3) +#define MIIM_CMD 0x8 +#defineMIIM_CMD_SCAN BIT(0) +#defineMIIM_CMD_OPR_WRITE BIT(1) +#defineMIIM_CMD_OPR_READ BIT(2) +#defineMIIM_CMD_SINGLE_SCANBIT(3) +#defineMIIM_CMD_WRDATA(x) ((x) << 4) +#defineMIIM_CMD_REGAD(x) ((x) << 20) +#defineMIIM_CMD_PHYAD(x) ((x) << 25) +#defineMIIM_CMD_VLDBIT(31) +#define MIIM_DATA 0xC +#defineMIIM_DATA_ERROR (0x3 << 16) + +#define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x)) +#defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) +#defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18) +#define ANA_PORT_CPU_FWD_CFG(x)(0x50 + 0x80 * (x)) +#defineANA_PORT_CPU_FWD_CFG_SRC_COPY_ENA BIT(1) +#define ANA_PORT_PORT_CFG(x) (0x60 + 0x80 * (x)) +#defineANA_PORT_PORT_CFG_RECV_ENA BIT(5) +#define ANA_TABLES_MACHDATA0x11b0 +#define ANA_TABLES_MACLDATA0x11b4 +#define ANA_TABLES_MACACCESS 0x11b8 +#defineANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15) +#defineANA_TABLES_MACACCESS_VALID BIT(11) +#defineANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9) +#defineANA_TABLES_MACACCESS_DEST_IDX(x)((x) << 3) +#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x) +#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD_MGENMASK(2, 0) +#defineMACACCESS_CMD_IDLE 0 +#defineMACACCESS_CMD_LEARN 1 +#define ANA_PGID(x)(0x1000 + 4 * (x)) + +#define SYS_FRM_AGING 0x8300 + +#define SYS_SYSTEM_RST_CFG 0x81b0 +#defineSYS_SYSTEM_RST_MEM_INIT BIT(0) +#defineSYS_SYSTEM_RST_MEM_ENA BIT(1) +#defineSYS_SYSTEM_RST_CORE_ENA BIT(2) +#define SYS_PORT_MODE(x) (0x81bc + 0x4 * (x)) +#defineSYS_PORT_MODE_INCL_INJ_HDR BIT(0) +#define SYS_SWITCH_PORT_MODE(x)(0x8294 + 0x4 * (x)) +#defineSYS_SWITCH_PORT_MODE_PORT_ENA BIT(3) +#define SYS_EGR_NO_SHARING 0x8378 +#define SYS_SCH_CPU0x85a0 + +#define REW_PORT_CFG(x)(0x8 + 0x80 * (x)) +#defineREW_PORT_CFG_IFH_INSERT_ENA BIT(7) + +#define GCB_DEVCPU_RST_SOFT_CHIP_RST 0x90 +#defineGCB_DEVCPU_RST_SOFT_CHIP_RST_SOFT_PHY BIT(1) +#define GCB_MISC_STAT 0x11c +#defineGCB_MIS
[U-Boot] [PATCH 1/3] MIPS: mscc: luton: Add ethernet nodes for Luton.
Add nodes for pcb090 and pcb091. There is currently no support
in Linux for this SoC.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/luton_pcb090.dts | 51 +
arch/mips/dts/luton_pcb091.dts | 51 +
arch/mips/dts/mscc,luton.dtsi | 165 +
3 files changed, 267 insertions(+)
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index 951d8da..315172b 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -55,3 +55,54 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index bf638b2..9b4d628 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -61,3 +61,54 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
+
+ {
+ phy-handle = <>;
+};
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index d11ec48..de354fe 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -92,5 +92,170 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ switch: switch@101 {
+ compatible = "mscc,vsc7527-switch";
+ reg = <0x1e 0x0100>, // VTSS_TO_DEV_0
+ <0x1f 0x0100>, // VTSS_TO_DEV_1
+ <0x20 0x0100>, // VTSS_TO_DEV_2
+ <0x21 0x0100>, // VTSS_TO_DEV_3
+ <0x22 0x0100>, // VTSS_TO_DEV_4
+ <0x23 0x0100>, // VTSS_TO_DEV_5
+ <0x24 0x0100>, // VTSS_TO_DEV_6
+ <0x25 0x0100>, // VTSS_TO_DEV_7
+ <0x26 0x0100>, // VTSS_TO_DEV_8
+ <0x27 0x0100>, // VTSS_TO_DEV_9
+ <0x28 0x0100>, // VTSS_TO_DEV_10
+ <0x29 0x0100>, // VTSS_TO_DEV_11
+ <0x2a 0x0100>, // VTSS_TO_DEV_12
+ <0x2b 0x0100>, // VTSS_TO_DEV_13
+ <0x2c 0x0100>, // VTSS_TO_DEV_14
+ <0x2d 0x0100>, // VTSS_TO_DEV_15
+ <0x2e 0x0100>, // VTSS_TO_DEV_16
+ <0x2f 0x0100>, // VTSS_TO_DEV_17
+ <0x30 0x0100>, // VTSS_TO_DEV_18
+ <0x31 0x0100>, // VTSS_TO_DEV_19
+ <0x32 0x0100>, // VTSS_TO_DEV_20
+ <0x33 0x0100>, // VTSS_TO_DEV_21
+ <0x34 0x0100>, // VTSS_TO_DEV_22
+ <0x35 0x0100>, // VTSS_TO_DEV_23
+ <0x01 0x1000>, // VTSS_TO_SYS
+ <0x02 0x1000>, // VTSS_TO_ANA
+ <0x03 0x1000>, // VTSS_TO_REW
+ <0x07 0x1000>, // VTSS_TO_DEVCPU_GCB
+ <0x08 0x0100>, // VTSS_TO_DEVCPU_QS
+ <0x0a 0x0100>; // VTSS_TO_HSIO
+ reg-names = "port0", "port1", "port2", "port3",
+ "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10", "port11",
+ "port12", "port13", "port14", "port15",
+ "port16", "port17"
[U-Boot] [PATCH 0/3] Add network support for Luton SoCs
This series adds network support for Luton SoCs. Currently there is not support for Luton SoCs in Linux. Horatiu Vultur (3): MIPS: mscc: luton: Add ethernet nodes for Luton. net: add MSCC Luton switch support configs: mscc_luton: add network support. MAINTAINERS| 1 + arch/mips/dts/luton_pcb090.dts | 51 +++ arch/mips/dts/luton_pcb091.dts | 51 +++ arch/mips/dts/mscc,luton.dtsi | 165 +++ configs/mscc_luton_defconfig | 1 + drivers/net/Kconfig| 7 + drivers/net/Makefile | 1 + drivers/net/luton_switch.c | 972 + 8 files changed, 1249 insertions(+) create mode 100644 drivers/net/luton_switch.c -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family.
Hi Daniel, The 01/23/2019 17:38, Daniel Schwierzeck wrote: > > > Am 23.01.19 um 16:39 schrieb Horatiu Vultur: > > This patch series adds support for MSCC Serval SoC family. In this > > family there are the following boards: pcb105 and pcb106. > > > > This is based off the patch series[1]. > > > > [1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html > > > > Horatiu Vultur (5): > > pinctrl: mscc: Add gpio and pinctrl for Serval SoC family. > > MSCC: Add support for Serval SoC family. > > MSCC: add device tree for Serval pcb105 board > > MSCC: Add device tree for Serval pcb106 board > > MSCC: Add board support for Serval SoC family. > > > > is this a resend or an extension of your v2 series? > > Normally a resend is not necessary and should be annotated accordingly. > If this is an update, then you should have sent it as a v3 with a proper > changelog. Well, it is none, it is a new patch series. The one in [1] is for ServalT while this patch series is for Serval. There are 2 different SoC families. [1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html > > -- > - Daniel -- /Horatiu ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/5] MSCC: Add board support for Serval SoC family.
Add board support and configuration for Jaguar2 SoC family.
The detection of the board type is based on the phy ids.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/Makefile| 1 +
arch/mips/mach-mscc/Makefile | 1 +
board/mscc/serval/Kconfig | 14
board/mscc/serval/Makefile| 3 ++
board/mscc/serval/serval.c| 74 +++
configs/mscc_serval_defconfig | 62
6 files changed, 155 insertions(+)
create mode 100644 board/mscc/serval/Kconfig
create mode 100644 board/mscc/serval/Makefile
create mode 100644 board/mscc/serval/serval.c
create mode 100644 configs/mscc_serval_defconfig
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index af264ff..b94b582 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -21,6 +21,7 @@ dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb
+dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb
targets += $(dtb-y)
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index f5b6968..6d60020 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -5,3 +5,4 @@ CFLAGS_cpu.o += -finline-limit=64000
obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o gpio.o
obj-$(CONFIG_SOC_OCELOT) += gpio.o
+obj-$(CONFIG_SOC_SERVAL) += gpio.o
diff --git a/board/mscc/serval/Kconfig b/board/mscc/serval/Kconfig
new file mode 100644
index 000..64f1c68
--- /dev/null
+++ b/board/mscc/serval/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+ default "mscc"
+
+if SOC_SERVAL
+
+config SYS_BOARD
+ default "serval"
+
+config SYS_CONFIG_NAME
+ default "serval"
+
+endif
diff --git a/board/mscc/serval/Makefile b/board/mscc/serval/Makefile
new file mode 100644
index 000..c7ba56e
--- /dev/null
+++ b/board/mscc/serval/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_SERVAL) := serval.o
diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c
new file mode 100644
index 000..24ee5e5
--- /dev/null
+++ b/board/mscc/serval/serval.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+
+enum {
+ BOARD_TYPE_PCB106 = 0xAABBCD00,
+ BOARD_TYPE_PCB105,
+};
+
+int board_early_init_r(void)
+{
+ /* Prepare SPI controller to be used in master mode */
+ writel(0, BASE_CFG + ICPU_SW_MODE);
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+ /* LED setup */
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
+static void do_board_detect(void)
+{
+ u16 gpio_in_reg;
+
+ /* Set MDIO and MDC */
+ mscc_gpio_set_alternate(9, 2);
+ mscc_gpio_set_alternate(10, 2);
+
+ /* Set GPIO page */
+ mscc_phy_wr(1, 16, 31, 0x10);
+ if (!mscc_phy_rd(1, 16, 15, _in_reg)) {
+ if (gpio_in_reg & 0x200)
+ gd->board_type = BOARD_TYPE_PCB106;
+ else
+ gd->board_type = BOARD_TYPE_PCB105;
+ mscc_phy_wr(1, 16, 15, 0);
+ } else {
+ gd->board_type = BOARD_TYPE_PCB105;
+ }
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB106 &&
+ strcmp(name, "serval_pcb106") == 0)
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_PCB105 &&
+ strcmp(name, "serval_pcb105") == 0)
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig
new file mode 100644
index 000..263e37d
--- /dev/null
+++ b/configs/mscc_serval_defconfig
@@ -0,0 +1,62 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_MSCC=y
+CONFIG_SOC_SERVAL=y
+CONFIG_DDRTYPE_H5TQ1G63BFA=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="serval # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CO
[U-Boot] [PATCH 4/5] MSCC: Add device tree for Serval pcb106 board
Add device tree based on evaluation board pcb106.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/serval_pcb106.dts | 56 +
1 file changed, 56 insertions(+)
create mode 100644 arch/mips/dts/serval_pcb106.dts
diff --git a/arch/mips/dts/serval_pcb106.dts b/arch/mips/dts/serval_pcb106.dts
new file mode 100644
index 000..1198249
--- /dev/null
+++ b/arch/mips/dts/serval_pcb106.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,serval.dtsi"
+
+/ {
+ model = "Serval PCB106 Reference Board";
+ compatible = "mscc,serval-pcb106", "mscc,serval";
+
+ aliases {
+ spi0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb106:green:status";
+ gpios = < 43 1>; /* p11.1 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb106:red:status";
+ gpios = < 11 1>; /* p11.0 */
+ default-state = "off";
+ };
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <1800>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
+ {
+ status = "okay";
+ sgpio-ports = <0x00FF>;
+};
--
2.7.4
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[U-Boot] [PATCH 3/5] MSCC: add device tree for Serval pcb105 board
Add device tree based on evaluation board pcb105.
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/mscc,serval.dtsi | 149
arch/mips/dts/serval_pcb105.dts | 56 +++
2 files changed, 205 insertions(+)
create mode 100644 arch/mips/dts/mscc,serval.dtsi
create mode 100644 arch/mips/dts/serval_pcb105.dts
diff --git a/arch/mips/dts/mscc,serval.dtsi b/arch/mips/dts/mscc,serval.dtsi
new file mode 100644
index 000..bd60051
--- /dev/null
+++ b/arch/mips/dts/mscc,serval.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,serval";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 =
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <41666>;
+ };
+
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20833>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20833>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x7000 0x200>;
+
+ interrupt-parent = <>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,serval-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,serval-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@10 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x10 0x20>;
+ interrupts = <6>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ reset@1070008 {
+ compatible = "mscc,serval-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
+ gpio: pinctrl@1070034 {
+ compatible = "mscc,serval-pinctrl";
+ reg = <0x1070034 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 22>;
+
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
+ function = "sio";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_26", "GPIO_27";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+
[U-Boot] [PATCH 2/5] MSCC: Add support for Serval SoC family.
As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
found in Microsemi Switches solution.
Signed-off-by: Horatiu Vultur
---
arch/mips/mach-mscc/Kconfig| 9 +
arch/mips/mach-mscc/cpu.c | 2 +-
arch/mips/mach-mscc/dram.c | 2 +-
arch/mips/mach-mscc/include/mach/common.h | 5 +
arch/mips/mach-mscc/include/mach/ddr.h | 20 +-
arch/mips/mach-mscc/include/mach/serval/serval.h | 24 ++
.../include/mach/serval/serval_devcpu_gcb.h| 21 ++
.../mach/serval/serval_devcpu_gcb_miim_regs.h | 25 ++
.../include/mach/serval/serval_icpu_cfg.h | 314 +
arch/mips/mach-mscc/reset.c| 25 +-
include/configs/vcoreiii.h | 5 +-
11 files changed, 438 insertions(+), 14 deletions(-)
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval.h
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h
create mode 100644
arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h
create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 80e4b44..34584a1 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -47,6 +47,13 @@ config SOC_SERVALT
help
This supports MSCC Servalt family of SOCs.
+config SOC_SERVAL
+ bool "Serval SOC Family"
+ select SOC_VCOREIII
+ select MSCC_BB_SPI
+ help
+ This supports MSCC Serval family of SOCs.
+
endchoice
config SYS_CONFIG_NAME
@@ -82,4 +89,6 @@ source "board/mscc/luton/Kconfig"
source "board/mscc/jr2/Kconfig"
source "board/mscc/servalt/Kconfig"
+
+source "board/mscc/serval/Kconfig"
endmenu
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index 1bfd636..ac75d51 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -87,7 +87,7 @@ int mach_cpu_init(void)
ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#else
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#endif
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index 2073821..c43f7a5 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -20,7 +20,7 @@ static inline int vcoreiii_train_bytelane(void)
ret = hal_vcoreiii_train_bytelane(0);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index 97b3f82..8f9a9c2 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -26,6 +26,11 @@
#include
#include
#include
+#elif defined(CONFIG_SOC_SERVAL)
+#include
+#include
+#include
+#include
#else
#error Unsupported platform
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h
b/arch/mips/mach-mscc/include/mach/ddr.h
index ff32f22..84ecfbd 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -25,7 +25,7 @@
#define VC3_MPAR_CL 6
#define VC3_MPAR_tWTR 4
#define VC3_MPAR_tRC 16
-#define VC3_MPR_tFAW 16
+#define VC3_MPAR_tFAW 16
#define VC3_MPAR_tRP 5
#define VC3_MPAR_tRRD 4
#define VC3_MPAR_tRCD 5
@@ -162,7 +162,7 @@
#endif
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
#define MIPS_VCOREIII_MEMORY_16BIT 1
#endif
@@ -241,7 +241,7 @@
ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
#define MSCC_MEMPARM_PERIOD\
ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
@@ -381,7 +381,7 @@ static inline void memphy_soft_reset(void)
}
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
- defined(CONFIG_SOC_SERVALT)
+ defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
static inline void sleep_100ns(u32 val)
@@ -452,7 +4
[U-Boot] [PATCH 1/5] pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.
Signed-off-by: Horatiu Vultur
---
drivers/pinctrl/mscc/Kconfig | 10 ++
drivers/pinctrl/mscc/Makefile | 1 +
drivers/pinctrl/mscc/pinctrl-serval.c | 233 ++
3 files changed, 244 insertions(+)
create mode 100644 drivers/pinctrl/mscc/pinctrl-serval.c
diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
index 0269565..aab67fa 100644
--- a/drivers/pinctrl/mscc/Kconfig
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -38,3 +38,13 @@ config PINCTRL_MSCC_SERVALT
help
Support pin multiplexing and pin configuration control on
Microsemi servalt SoCs.
+
+config PINCTRL_MSCC_SERVAL
+ depends on SOC_SERVAL && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi serval family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi serval SoCs.
+
diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
index c6b0373..fd7eba2 100644
--- a/drivers/pinctrl/mscc/Makefile
+++ b/drivers/pinctrl/mscc/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
obj-$(CONFIG_PINCTRL_MSCC_SERVALT) += pinctrl-servalt.o
+obj-$(CONFIG_PINCTRL_MSCC_SERVAL) += pinctrl-serval.o
diff --git a/drivers/pinctrl/mscc/pinctrl-serval.c
b/drivers/pinctrl/mscc/pinctrl-serval.c
new file mode 100644
index 000..d59f08d
--- /dev/null
+++ b/drivers/pinctrl/mscc/pinctrl-serval.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author:
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_IRQ0,
+ FUNC_IRQ1,
+ FUNC_MIIM1,
+ FUNC_PCI_WAKE,
+ FUNC_PTP0,
+ FUNC_PTP1,
+ FUNC_PTP2,
+ FUNC_PTP3,
+ FUNC_PWM,
+ FUNC_RECO_CLK0,
+ FUNC_RECO_CLK1,
+ FUNC_SFP0,
+ FUNC_SFP1,
+ FUNC_SFP2,
+ FUNC_SFP3,
+ FUNC_SFP4,
+ FUNC_SFP5,
+ FUNC_SFP6,
+ FUNC_SFP7,
+ FUNC_SFP8,
+ FUNC_SFP9,
+ FUNC_SFP10,
+ FUNC_SIO,
+ FUNC_SI,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_TWI_SCL_M,
+ FUNC_UART,
+ FUNC_UART2,
+ FUNC_MD,
+ FUNC_PTP1588,
+ FUNC_MAX
+};
+
+static char * const serval_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0] = "irq0",
+ [FUNC_IRQ1] = "irq1",
+ [FUNC_MIIM1]= "miim1",
+ [FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_PTP0] = "ptp0",
+ [FUNC_PTP1] = "ptp1",
+ [FUNC_PTP2] = "ptp2",
+ [FUNC_PTP3] = "ptp3",
+ [FUNC_PWM] = "pwm",
+ [FUNC_RECO_CLK0]= "reco_clk0",
+ [FUNC_RECO_CLK1]= "reco_clk1",
+ [FUNC_SFP0] = "sfp0",
+ [FUNC_SFP1] = "sfp1",
+ [FUNC_SFP2] = "sfp2",
+ [FUNC_SFP3] = "sfp3",
+ [FUNC_SFP4] = "sfp4",
+ [FUNC_SFP5] = "sfp5",
+ [FUNC_SFP6] = "sfp6",
+ [FUNC_SFP7] = "sfp7",
+ [FUNC_SFP8] = "sfp8",
+ [FUNC_SFP9] = "sfp9",
+ [FUNC_SFP10]= "sfp10",
+ [FUNC_SIO] = "sio",
+ [FUNC_SI] = "si",
+ [FUNC_TACHO]= "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_TWI_SCL_M]= "twi_scl_m",
+ [FUNC_UART] = "uart",
+ [FUNC_UART2]= "uart2",
+ [FUNC_MD] = "md",
+ [FUNC_PTP1588] = "1588",
+};
+
+MSCC_P(0, SIO, NONE, NONE);
+MSCC_P(1, SIO, NONE, NONE);
+MSCC_P(2, SIO, NONE, NONE);
+MSCC_P(3, SIO, NONE, NONE);
+MSCC_P(4, TACHO, NONE, NONE);
+MSCC_P(5, PWM, NONE, NONE);
+MSCC_P(6, TWI, NONE, NONE);
+MSCC_P(7, TWI, NONE, NONE);
+MSCC_P(8, SI,NONE, NONE);
+MSCC_P(9, SI,MD,NONE);
+MSCC_P(10, SI,MD,NONE);
+MSCC_P(1
[U-Boot] [PATCH 0/5] MSCC: Add Serval SoC family.
This patch series adds support for MSCC Serval SoC family. In this family there are the following boards: pcb105 and pcb106. This is based off the patch series[1]. [1] https://lists.denx.de/pipermail/u-boot/2019-January/355031.html Horatiu Vultur (5): pinctrl: mscc: Add gpio and pinctrl for Serval SoC family. MSCC: Add support for Serval SoC family. MSCC: add device tree for Serval pcb105 board MSCC: Add device tree for Serval pcb106 board MSCC: Add board support for Serval SoC family. arch/mips/dts/Makefile | 1 + arch/mips/dts/mscc,serval.dtsi | 149 ++ arch/mips/dts/serval_pcb105.dts| 56 arch/mips/dts/serval_pcb106.dts| 56 arch/mips/mach-mscc/Kconfig| 9 + arch/mips/mach-mscc/Makefile | 1 + arch/mips/mach-mscc/cpu.c | 2 +- arch/mips/mach-mscc/dram.c | 2 +- arch/mips/mach-mscc/include/mach/common.h | 5 + arch/mips/mach-mscc/include/mach/ddr.h | 20 +- arch/mips/mach-mscc/include/mach/serval/serval.h | 24 ++ .../include/mach/serval/serval_devcpu_gcb.h| 21 ++ .../mach/serval/serval_devcpu_gcb_miim_regs.h | 25 ++ .../include/mach/serval/serval_icpu_cfg.h | 314 + arch/mips/mach-mscc/reset.c| 25 +- board/mscc/serval/Kconfig | 14 + board/mscc/serval/Makefile | 3 + board/mscc/serval/serval.c | 74 + configs/mscc_serval_defconfig | 62 drivers/pinctrl/mscc/Kconfig | 10 + drivers/pinctrl/mscc/Makefile | 1 + drivers/pinctrl/mscc/pinctrl-serval.c | 233 +++ include/configs/vcoreiii.h | 5 +- 23 files changed, 1098 insertions(+), 14 deletions(-) create mode 100644 arch/mips/dts/mscc,serval.dtsi create mode 100644 arch/mips/dts/serval_pcb105.dts create mode 100644 arch/mips/dts/serval_pcb106.dts create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval.h create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h create mode 100644 board/mscc/serval/Kconfig create mode 100644 board/mscc/serval/Makefile create mode 100644 board/mscc/serval/serval.c create mode 100644 configs/mscc_serval_defconfig create mode 100644 drivers/pinctrl/mscc/pinctrl-serval.c -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/11] SF: Migrate to Linux SPI NOR framework
Hi Vignesh, I have done few small tests on Ocelot and Luton boards which have SPI NOR: mx25l25635f and m25p128. I have not seen any issues. So if you want, you can add: Tested-by: Horatiu Vultur The 12/21/2018 12:08, Vignesh R wrote: > U-Boot SPI NOR support (sf layer) is quite outdated as it does not > support 4 byte addressing opcodes, SFDP table parsing and different types of > quad mode enable sequences. Many newer flashes no longer support BANK > registers used by sf layer to a access >16MB space. > Also, many SPI controllers have special MMIO interfaces which provide > accelerated read/write access but require knowledge of flash parameters > to make use of it. Recent spi-mem layer provides a way to support such > flashes but sf layer isn't using that. > This patch series syncs SPI NOR framework from Linux v4.19. It also adds > spi-mem support on top. > So, we gain 4byte addressing support and SFDP support. This makes > migrating to U-Boot MTD framework easier. > > Tested with few Spansion, micron and macronix flashes with TI's dra7xx, > k2g, am43xx EVMs. I dont have access to flashes from other vendors. So, > I would greatly appreciate testing on other platforms. Complete series > with dependencies here[1] > > For clean build on some platforms, depends on CONFIG_SPI_FLASH migration > to defconfigs [2] > > [1] https://github.com/r-vignesh/u-boot.git branch: spi-nor-mig-patch-v2 > [2] https://patchwork.ozlabs.org/patch/1007485/ > > Simon, Stefan, Thanks for testing previous versions. > I haven't carried Tested-by's here as I have added back SPI_FLASH_BAR > support (but isn't enabled by default). Would be great if you could > retest this series. > I am hoping there won't be any major rework/changes after this round. > > Change log: > Since v1: > Remove #ifindef __UBOOT__ > Add back BAR support, but dont enable as default for all platform (see > 10/11 for more details) > Enable SPI_FLASH_TINY on boards where there is SPL size constraint as > seen on travis ci builds. > Drop sf_mtd changes for now as it seems to cause issues. > v1: https://patchwork.ozlabs.org/cover/1012146/ > > Since RFC v2: > Fix issues reported by Simon Goldschmidt wrt 4 use of byte addressing opcode > Fix issues in compiling SFDP code > Re organize file names and Makefile to simply spi-nor-tiny inclusion > Remove SPI_FLASH_BAR and SF_DUAL_FLASH as these are no longer used > RFC v2: https://patchwork.ozlabs.org/cover/1007589/ > > Since RFC v1: > Add lightweight SPI flash stack for boards with SPL size constraints > Provide non DM version of spi-mem > Fix build issues on different platforms as reported by travis-ci on v1 > > RFC v1: https://patchwork.ozlabs.org/cover/1004689/ > > Vignesh R (11): > spi-mem: Claim SPI bus before spi mem access > spi: Add non DM version of SPI_MEM > sh: bitops: add hweight*() macros > mtd: spi: Port SPI NOR framework from Linux > mtd: spi: Switch to new SPI NOR framework > mtd: spi: Remove unused files > mtd: spi: Add lightweight SPI flash stack for SPL > configs: Enable SPI_FLASH_TINY for resource constrained boards > configs: Remove SF_DUAL_FLASH > configs: Don't use SPI_FLASH_BAR as default > MAINTAINERS: Add an entry for SPI NOR > > MAINTAINERS |9 + > arch/arm/mach-omap2/am33xx/Kconfig|1 - > arch/sh/include/asm/bitops.h |4 + > common/spl/Kconfig| 21 +- > configs/alt_defconfig |1 - > configs/am57xx_evm_defconfig |1 - > configs/am57xx_hs_evm_defconfig |1 - > configs/ap121_defconfig |1 - > configs/ap143_defconfig |1 - > configs/avnet_ultra96_rev1_defconfig |1 - > configs/axm_defconfig |1 + > configs/axs101_defconfig |1 - > configs/axs103_defconfig |1 - > configs/bg0900_defconfig |1 - > configs/blanche_defconfig |1 - > configs/cl-som-am57x_defconfig|1 - > configs/clearfog_defconfig|1 - > configs/cm_t43_defconfig |1 - > configs/da850_am18xxevm_defconfig |1 + > configs/da850evm_nand_defconfig |2 +- > configs/db-88f6820-amc_defconfig |1 - > configs/db-88f6820-gp_defconfig |1 + > configs/display5_defconfig|1 - > configs/display5_factory_defconfig|1 - > configs/dra7xx_evm_defconfig |1 - > configs/dra7xx_
Re: [U-Boot] commit 9a9d66f5ef break U-Boot Env
Hi Heiko,
The 01/18/2019 09:34, Heiko Schocher wrote:
> Hello Horatiu,
>
> just tried current mainline U-Boot on imx6ull based board with
> Env in SPI NOR. Your commit "9a9d66f5eff0"
>
> env: add spi_flash_read_env function
>
> breaks reading Env from SPI NOR in my case...
>
> If I interprete your patch correct, you only read until the 2 0x0
> in the env ... but for the env crc, the hole CONFIG_ENV_SIZE
> must be read ... else missing for crc calculation ...
>
> Hmm... following patch fixes for me the issue:
>
> hs@threadripper:git [master] $ git diff env/sf.c
> diff --git a/env/sf.c b/env/sf.c
> index b3dec82c35..dc4b56d4a4 100644
> --- a/env/sf.c
> +++ b/env/sf.c
> @@ -98,7 +104,7 @@ static int spi_flash_read_env(struct spi_flash *flash, u32
> offset, size_t len,
> u32 addr = 0;
> u32 page_size = flash->page_size;
>
> - memset(buf, 0x0, len);
> + memset(buf, 0xff, len);
> for (int i = 0; i < len / page_size; ++i) {
> int ret = spi_flash_read(flash, offset, page_size,
> &((char *)buf)[addr]);
>
> But if I make a bigger ENV_SIZE this may break again...
That's correct, the buf should be initialized to 0xff.
But I don't see why increasing the ENV_SIZE would break it again. Can
you explain it why? Thank you.
>
> bye,
> Heiko
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
--
/Horatiu
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[U-Boot] [PATCH v2 3/3] MSCC: Add board support for Servalt SoC family
Add board support, configuration and DTS for Servalt SoC
family. Currently there is one board in this family.
Reviewed-by: Daniel Schwierzeck
Signed-off-by: Horatiu Vultur
---
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mscc,servalt.dtsi | 149 +++
arch/mips/dts/servalt_pcb116.dts | 56 +++
board/mscc/servalt/Kconfig | 14
board/mscc/servalt/Makefile | 3 +
board/mscc/servalt/servalt.c | 52 ++
configs/mscc_servalt_defconfig | 60
7 files changed, 335 insertions(+)
create mode 100644 arch/mips/dts/mscc,servalt.dtsi
create mode 100644 arch/mips/dts/servalt_pcb116.dts
create mode 100644 board/mscc/servalt/Kconfig
create mode 100644 board/mscc/servalt/Makefile
create mode 100644 board/mscc/servalt/servalt.c
create mode 100644 configs/mscc_servalt_defconfig
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 1484db9..af264ff 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -20,6 +20,7 @@ dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
+dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/mscc,servalt.dtsi b/arch/mips/dts/mscc,servalt.dtsi
new file mode 100644
index 000..4beb7a3
--- /dev/null
+++ b/arch/mips/dts/mscc,servalt.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,servalt";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 =
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5>;
+ };
+
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x7000 0x200>;
+
+ interrupt-parent = <>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,servalt-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,servalt-icpu-intr";
+ reg = <0x70 0x74>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@10 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x10 0x20>;
+ interrupts = <6>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+
[U-Boot] [PATCH v2 2/3] MSCC: Add support for Servalt SoC family.
As Ocelot, Luton and Jaguar2, this family of SoCs are found
in Microsemi Switches solution.
Reviewed-by: Daniel Schwierzeck
Signed-off-by: Horatiu Vultur
---
arch/mips/mach-mscc/Kconfig| 8 +
arch/mips/mach-mscc/cpu.c | 2 +-
arch/mips/mach-mscc/dram.c | 3 +-
arch/mips/mach-mscc/include/mach/common.h | 5 +
arch/mips/mach-mscc/include/mach/ddr.h | 22 +-
arch/mips/mach-mscc/include/mach/servalt/servalt.h | 24 ++
.../include/mach/servalt/servalt_devcpu_gcb.h | 20 ++
.../mach/servalt/servalt_devcpu_gcb_miim_regs.h| 25 ++
.../include/mach/servalt/servalt_icpu_cfg.h| 319 +
arch/mips/mach-mscc/reset.c| 2 +-
10 files changed, 419 insertions(+), 11 deletions(-)
create mode 100644 arch/mips/mach-mscc/include/mach/servalt/servalt.h
create mode 100644
arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h
create mode 100644
arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h
create mode 100644 arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index fc6aa03..80e4b44 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -40,6 +40,13 @@ config SOC_JR2
help
This supports MSCC Jaguar2 family of SOCs.
+config SOC_SERVALT
+ bool "Servalt SOC Family"
+ select SOC_VCOREIII
+ select MSCC_BB_SPI
+ help
+ This supports MSCC Servalt family of SOCs.
+
endchoice
config SYS_CONFIG_NAME
@@ -74,4 +81,5 @@ source "board/mscc/luton/Kconfig"
source "board/mscc/jr2/Kconfig"
+source "board/mscc/servalt/Kconfig"
endmenu
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index 4729b7a..1bfd636 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -91,7 +91,7 @@ int mach_cpu_init(void)
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#endif
-#ifdef CONFIG_SOC_JR2
+#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG);
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index 8002e07..2073821 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -19,7 +19,8 @@ static inline int vcoreiii_train_bytelane(void)
ret = hal_vcoreiii_train_bytelane(0);
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT)
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index b9e0939..97b3f82 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -21,6 +21,11 @@
#include
#include
#include
+#elif defined(CONFIG_SOC_SERVALT)
+#include
+#include
+#include
+#include
#else
#error Unsupported platform
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h
b/arch/mips/mach-mscc/include/mach/ddr.h
index 7552acb..ff32f22 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -161,7 +161,8 @@
#endif
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT)
#define MIPS_VCOREIII_MEMORY_16BIT 1
#endif
@@ -239,7 +240,8 @@
ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) | \
ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT)
#define MSCC_MEMPARM_PERIOD\
ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
@@ -378,7 +380,8 @@ static inline void memphy_soft_reset(void)
PAUSE();
}
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+ defined(CONFIG_SOC_SERVALT)
static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
static inline void sleep_100ns(u32 val)
@@ -449,7 +452,7 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n");
}
-#else /* JR2 */
+#else /* JR2 || ServalT */
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
/* Ensure th
