[PATCH 2/4] imx: imxrt1050-evk: Fix missing clocks for mmc
Two of the clocks required by the usdhc1 controller are missing from the
clock controller node. A recent change enables all the clocks in the
esdhc node, which fails as they are not defined in the clock controller.
Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API")
Signed-off-by: Jesse Taube
Cc: Peng Fan
---
arch/arm/dts/imxrt1050.dtsi | 2 +-
drivers/clk/imx/clk-imxrt1050.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 03e6a858a7b..a25eae9bd38 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -87,7 +87,7 @@
reg = <0x402c 0x4000>;
interrupts = <110>;
clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
- <&clks IMXRT1050_CLK_OSC>,
+ <&clks IMXRT1050_CLK_AHB_PODF>,
<&clks IMXRT1050_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 788e0650a92..2c029ec5a6e 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -144,6 +144,9 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_dm(IMXRT1050_CLK_AHB_PODF,
imx_clk_divider("ahb_podf", "periph_sel",
base + 0x14, 10, 3));
+ clk_dm(IMXRT1050_CLK_IPG_PDOF,
+ imx_clk_divider("ipg_podf", "ahb_podf",
+ base + 0x14, 8, 2));
clk_dm(IMXRT1050_CLK_USDHC1_PODF,
imx_clk_divider("usdhc1_podf", "usdhc1_sel",
base + 0x24, 11, 3));
--
2.45.2
[PATCH 1/4] imx: imxrt*: Fix binman breaking boot
The init_r parsing of U-Boot device tree to search the binman
information errors. set CONFIG_BINMAN_FDT to no to fix this.
Fixes: 7079eeb72fc ("imx: imxrt1050-evk: Add support for SPI flash booting
s")
Signed-off-by: Jesse Taube
---
configs/imxrt1020-evk_defconfig | 1 +
configs/imxrt1050-evk_defconfig | 1 +
configs/imxrt1050-evk_fspi_defconfig | 1 +
configs/imxrt1170-evk_defconfig | 1 +
4 files changed, 4 insertions(+)
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 5865d41a741..58a3e92ce08 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -67,6 +67,7 @@ CONFIG_FSL_LPUART=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_IMX_GPT_TIMER=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_HEXDUMP=y
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index f8b85398b79..2653efac148 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -84,5 +84,6 @@ CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_SHA256=y
CONFIG_HEXDUMP=y
diff --git a/configs/imxrt1050-evk_fspi_defconfig
b/configs/imxrt1050-evk_fspi_defconfig
index 73001ffe161..95b5b56ece7 100644
--- a/configs/imxrt1050-evk_fspi_defconfig
+++ b/configs/imxrt1050-evk_fspi_defconfig
@@ -85,6 +85,7 @@ CONFIG_VIDEO_MXS=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_SHA256=y
CONFIG_HEXDUMP=y
CONFIG_FSPI_CONF_HEADER=y
diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig
index 5f28c22e66c..487da275c62 100644
--- a/configs/imxrt1170-evk_defconfig
+++ b/configs/imxrt1170-evk_defconfig
@@ -68,3 +68,4 @@ CONFIG_FSL_LPUART=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_IMX_GPT_TIMER=y
+# CONFIG_BINMAN_FDT is not set
--
2.45.2
[PATCH 4/4] ARM: dts: imxrt1170: Fix default cells value warnings
Add #address-cells and #size-cells to the memory node to fix warnings
Signed-off-by: Jesse Taube
---
arch/arm/dts/imxrt1170-evk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts
index c2fd0c0392c..0d8e7016860 100644
--- a/arch/arm/dts/imxrt1170-evk.dts
+++ b/arch/arm/dts/imxrt1170-evk.dts
@@ -20,6 +20,8 @@
};
memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
device_type = "memory";
reg = <0x2024 0xf 0x8000 0x400>;
--
2.45.2
[PATCH 3/4] configs: imxrt1050-evk: Enable standard boot
Enable standard boot support and add default environments for the imxrt1050-evk board. Signed-off-by: Jesse Taube --- board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env | 13 + board/freescale/imxrt1050-evk/imxrt1050-evk.env | 13 + configs/imxrt1050-evk_defconfig | 4 ++-- configs/imxrt1050-evk_fspi_defconfig| 5 +++-- include/configs/imxrt1050-evk.h | 7 --- 5 files changed, 31 insertions(+), 11 deletions(-) create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.env diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env b/board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env new file mode 100644 index 000..c61e9e3c00a --- /dev/null +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* environment for imxrt1050-evk */ + +#ifdef CONFIG_VIDEO +stdin=serial +stdout=serial,vidconsole +stderr=serial,vidconsole +#endif + +fdt_addr_r=0x8080 +kernel_addr_r=0x8000 +boot_targets=nor diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.env b/board/freescale/imxrt1050-evk/imxrt1050-evk.env new file mode 100644 index 000..1c5cbc29d53 --- /dev/null +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.env @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* environment for imxrt1050-evk */ + +#ifdef CONFIG_VIDEO +stdin=serial +stdout=serial,vidconsole +stderr=serial,vidconsole +#endif + +fdt_addr_r=0x8080 +kernel_addr_r=0x8000 +boot_targets=mmc diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 2653efac148..141303c5a29 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -23,10 +23,10 @@ CONFIG_SPL_SIZE_LIMIT=0x2 CONFIG_SPL=y CONFIG_HAVE_SYS_UBOOT_START=y CONFIG_SYS_UBOOT_START=0x800023FD -CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_SD_BOOT=y CONFIG_SPI_BOOT=y -# CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig index 95b5b56ece7..b77dbab7077 100644 --- a/configs/imxrt1050-evk_fspi_defconfig +++ b/configs/imxrt1050-evk_fspi_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="imxrt1050-evk-nor" CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2002 CONFIG_ENV_OFFSET=0x8 @@ -24,10 +25,10 @@ CONFIG_SPL_SIZE_LIMIT=0x2 CONFIG_SPL=y CONFIG_HAVE_SYS_UBOOT_START=y CONFIG_SYS_UBOOT_START=0x800023FD -CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_SD_BOOT=y CONFIG_SPI_BOOT=y -# CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index b370e25105a..c520c2fc203 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -18,13 +18,6 @@ #define DMAMEM_BASE(PHYS_SDRAM + PHYS_SDRAM_SIZE - \ DMAMEM_SZ_ALL) -#ifdef CONFIG_VIDEO -#define CFG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" -#endif - /* * Address of U-Boot for SPI NOR boot */ -- 2.45.2
[PATCH v4 1/2] imx: imxrt1050-evk: Add support for SPI flash booting
Add support for booting the imxrt1050-evk from spi.
Add imximage config and the ability for SPL to boot from NOR.
Enable binman in Kconfig and device tree for imxrt* as it is used to
prepend fspi_header.bin to SPL and u-boot.img.
Signed-off-by: Jesse Taube
---
V1 -> V2:
- Add defconfig to MAINTAINERS
- Change Copyright of imximage-nor.cfg to myself
- Fix spelling and grammar
- Use imperative mood
V2 -> V3:
- Enabled binman for imxrt*
V3 -> V4:
- Mention binman in commit description
- Squash enabled binman and this commit
---
arch/arm/dts/imxrt1020-evk-u-boot.dtsi| 4 +
arch/arm/dts/imxrt1050-evk-u-boot.dtsi| 31 ++
arch/arm/dts/imxrt1170-evk-u-boot.dtsi| 4 +
arch/arm/mach-imx/imxrt/Kconfig | 1 +
board/freescale/imxrt1050-evk/MAINTAINERS | 1 +
.../freescale/imxrt1050-evk/imximage-nor.cfg | 42
board/freescale/imxrt1050-evk/imximage.cfg| 10 +-
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 7 +-
configs/imxrt1050-evk_defconfig | 8 +-
configs/imxrt1050-evk_fspi_defconfig | 100 ++
include/configs/imxrt1050-evk.h | 6 ++
11 files changed, 208 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/imxrt1050-evk/imximage-nor.cfg
create mode 100644 configs/imxrt1050-evk_fspi_defconfig
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 46928c07e9..e246de0299 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -5,6 +5,10 @@
*/
/ {
+ binman: binman {
+ multiple-images;
+ };
+
chosen {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index a9095e736b..3f54411b7b 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -8,6 +8,10 @@
#include "imxrt1050-pinfunc.h"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
aliases {
display0 = &lcdif;
usbphy0 = &usbphy1;
@@ -113,6 +117,33 @@
};
};
+&binman {
+#ifdef CONFIG_FSPI_CONF_HEADER
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ fspi_conf_block {
+ filename = CONFIG_FSPI_CONF_FILE;
+ type = "blob-ext";
+ offset = <0x0>;
+ };
+
+ spl {
+ filename = "SPL";
+ offset = <0x1000>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.img";
+ offset = <0x1>;
+ type = "blob-ext";
+ };
+ };
+#endif
+};
+
&osc {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
index f923a14301..6e892c1af7 100644
--- a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
@@ -6,6 +6,10 @@
*/
/ {
+ binman: binman {
+ multiple-images;
+ };
+
chosen {
bootph-pre-ram;
};
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index c1d6b09e77..f702f6 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -2,6 +2,7 @@ if ARCH_IMXRT
config IMXRT
bool
+ select BINMAN
select SYS_FSL_ERRATUM_ESDHC135
config IMXRT1020
diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS
b/board/freescale/imxrt1050-evk/MAINTAINERS
index a872855452..890825b39a 100644
--- a/board/freescale/imxrt1050-evk/MAINTAINERS
+++ b/board/freescale/imxrt1050-evk/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/imxrt1050-evk
F: include/configs/imxrt1050-evk.h
F: configs/imxrt1050-evk_defconfig
+F: configs/imxrt1050-evk_fspi_defconfig
diff --git a/board/freescale/imxrt1050-evk/imximage-nor.cfg
b/board/freescale/imxrt1050-evk/imximage-nor.cfg
new file mode 100644
index 00..3b80e1f178
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imximage-nor.cfg
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024
+ * Author(s): Jesse Taube
+ */
+
+#include
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM nor
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to
[PATCH v4 2/2] imx: imxrt1050-evk: Add documentation for SPI boot
Add documentation for SPI boot. Signed-off-by: Jesse Taube --- V1 -> V2: - Change s/Adds/Add - Change imxrt1050-evk_spi to fspi - Fix spelling and grammar - Mention the SPI NOR flash part number V2 -> V3: - No changes V3 -> V4: - No changes --- doc/board/nxp/imxrt1050-evk.rst | 30 ++ 1 file changed, 30 insertions(+) diff --git a/doc/board/nxp/imxrt1050-evk.rst b/doc/board/nxp/imxrt1050-evk.rst index c1fb48f0cd..e0cafe1035 100644 --- a/doc/board/nxp/imxrt1050-evk.rst +++ b/doc/board/nxp/imxrt1050-evk.rst @@ -39,3 +39,33 @@ switch label numbers reference). The USB console connector is the one close the ethernet connector - Insert the micro SD card in the board, power it up and U-Boot messages should come up. + + +How to use U-Boot with SPI flash on NXP i.MXRT1050 EVK +-- + +- Build U-Boot for i.MXRT1050 EVK: + +.. code-block:: bash + + $ make mrproper + $ make imxrt1050-evk_fspi_defconfig + $ make + +This will generate SPL, uboot.img, fspi_header.bin, and the final image (flash.bin). + +To boot from SPI flash on other boards, you may need to change the flash header config, +which is specific to your flash chip, in Kconfig. +The flash config is 4K in size and is documented on page 217 of the imxrt1050 RM. +The default flash chip on the i.MXRT1050 EVK is the S26KS512SDPBHI02 HYPERFLASH. + +- Jumper settings:: + + SW7: 0 1 1 0 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Connect the USB cable between the EVK and the PC for the console. + +- Use either JTAG or SWD to write `flash.bin` to the NOR. I used Mcuexpresso IDE's GUI flash tool. -- 2.43.0
[PATCH v3 3/3] imx: imxrt1050-evk: Add documentation for SPI boot
Add documentation for SPI boot. Signed-off-by: Jesse Taube --- V1 -> V2: - Change s/Adds/Add - Change imxrt1050-evk_spi to fspi - Fix spelling and grammar - Mention the SPI NOR flash part number V2 -> V3: - No changes --- doc/board/nxp/imxrt1050-evk.rst | 30 ++ 1 file changed, 30 insertions(+) diff --git a/doc/board/nxp/imxrt1050-evk.rst b/doc/board/nxp/imxrt1050-evk.rst index c1fb48f0cd..e0cafe1035 100644 --- a/doc/board/nxp/imxrt1050-evk.rst +++ b/doc/board/nxp/imxrt1050-evk.rst @@ -39,3 +39,33 @@ switch label numbers reference). The USB console connector is the one close the ethernet connector - Insert the micro SD card in the board, power it up and U-Boot messages should come up. + + +How to use U-Boot with SPI flash on NXP i.MXRT1050 EVK +-- + +- Build U-Boot for i.MXRT1050 EVK: + +.. code-block:: bash + + $ make mrproper + $ make imxrt1050-evk_fspi_defconfig + $ make + +This will generate SPL, uboot.img, fspi_header.bin, and the final image (flash.bin). + +To boot from SPI flash on other boards, you may need to change the flash header config, +which is specific to your flash chip, in Kconfig. +The flash config is 4K in size and is documented on page 217 of the imxrt1050 RM. +The default flash chip on the i.MXRT1050 EVK is the S26KS512SDPBHI02 HYPERFLASH. + +- Jumper settings:: + + SW7: 0 1 1 0 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Connect the USB cable between the EVK and the PC for the console. + +- Use either JTAG or SWD to write `flash.bin` to the NOR. I used Mcuexpresso IDE's GUI flash tool. -- 2.43.0
[PATCH v3 1/3] arm: dts: imxrt: Add binman support
Enable binman in Kconfig and in device tree.
Signed-off-by: Jesse Taube
---
V2 -> V3:
- New commit
---
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4
arch/arm/dts/imxrt1170-evk-u-boot.dtsi | 4
arch/arm/mach-imx/imxrt/Kconfig| 1 +
4 files changed, 13 insertions(+)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 46928c07e9..e246de0299 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -5,6 +5,10 @@
*/
/ {
+ binman: binman {
+ multiple-images;
+ };
+
chosen {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index a9095e736b..8a9f6119b1 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -8,6 +8,10 @@
#include "imxrt1050-pinfunc.h"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
aliases {
display0 = &lcdif;
usbphy0 = &usbphy1;
diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
index f923a14301..6e892c1af7 100644
--- a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
@@ -6,6 +6,10 @@
*/
/ {
+ binman: binman {
+ multiple-images;
+ };
+
chosen {
bootph-pre-ram;
};
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index c1d6b09e77..f702f6 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -2,6 +2,7 @@ if ARCH_IMXRT
config IMXRT
bool
+ select BINMAN
select SYS_FSL_ERRATUM_ESDHC135
config IMXRT1020
--
2.43.0
[PATCH v3 2/3] imx: imxrt1050-evk: Add support for SPI flash booting
Add support for booting the imxrt1050-evk from spi.
Add imximage config and the ability for SPL to boot from NOR.
Signed-off-by: Jesse Taube
---
V1 -> V2:
- Add defconfig to MAINTAINERS
- Change Copyright of imximage-nor.cfg to myself
- Fix spelling and grammar
- Use imperative mood
V2 -> V3:
- Move enabling of binman to another commit
---
arch/arm/dts/imxrt1050-evk-u-boot.dtsi| 27 +
board/freescale/imxrt1050-evk/MAINTAINERS | 1 +
.../freescale/imxrt1050-evk/imximage-nor.cfg | 42
board/freescale/imxrt1050-evk/imximage.cfg| 10 +-
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 7 +-
configs/imxrt1050-evk_defconfig | 8 +-
configs/imxrt1050-evk_fspi_defconfig | 100 ++
include/configs/imxrt1050-evk.h | 6 ++
8 files changed, 195 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/imxrt1050-evk/imximage-nor.cfg
create mode 100644 configs/imxrt1050-evk_fspi_defconfig
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 8a9f6119b1..3f54411b7b 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -117,6 +117,33 @@
};
};
+&binman {
+#ifdef CONFIG_FSPI_CONF_HEADER
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ fspi_conf_block {
+ filename = CONFIG_FSPI_CONF_FILE;
+ type = "blob-ext";
+ offset = <0x0>;
+ };
+
+ spl {
+ filename = "SPL";
+ offset = <0x1000>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.img";
+ offset = <0x1>;
+ type = "blob-ext";
+ };
+ };
+#endif
+};
+
&osc {
bootph-pre-ram;
};
diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS
b/board/freescale/imxrt1050-evk/MAINTAINERS
index a872855452..890825b39a 100644
--- a/board/freescale/imxrt1050-evk/MAINTAINERS
+++ b/board/freescale/imxrt1050-evk/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/imxrt1050-evk
F: include/configs/imxrt1050-evk.h
F: configs/imxrt1050-evk_defconfig
+F: configs/imxrt1050-evk_fspi_defconfig
diff --git a/board/freescale/imxrt1050-evk/imximage-nor.cfg
b/board/freescale/imxrt1050-evk/imximage-nor.cfg
new file mode 100644
index 00..3b80e1f178
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imximage-nor.cfg
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024
+ * Author(s): Jesse Taube
+ */
+
+#include
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM nor
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunately setting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configuration fortunately works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aa
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
+
diff --git a/board/freescale/imxrt1050-evk/imximage.cfg
b/board/freescale/imxrt1050-evk/imximage.cfg
index f1f09fd7eb..b30d852194 100644
--- a/board/freescale/imxrt1050-evk/imximage.cfg
+++ b/board/freescale/imxrt1050-evk/imximage.cfg
@@ -29,7 +29,13 @@ BOOT_FROMsd
* value value to be stored in the register
*/
-/* Set all FlexRAM as OCRAM(01b) */
-DATA 4 0x400AC044 0x
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunately setting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configuration fortunately works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aa
/* Use FLEXRAM_BANK_CFG to config FlexRAM */
SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
index 4b82ee5e9c..4cc3defc88 100644
--- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
+++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
@@ -68,7 +68,12 @@ void spl_board_init(void)
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_MMC1;
+ /* There is no way to find the boot device so look if t
[PATCH v2 1/2] imx: imxrt1050-evk: Add support for SPI flash booting
Add support for booting the imxrt1050-evk from spi.
Add imximage config and the ability for SPL to boot from NOR.
Signed-off-by: Jesse Taube
---
V1 -> V2:
- Add defconfig to MAINTAINERS
- Change Copyright of imximage-nor.cfg to myself
- Fix spelling and grammar
- Use imperative mood
---
arch/arm/dts/imxrt1050-evk-u-boot.dtsi| 31 ++
arch/arm/mach-imx/imxrt/Kconfig | 1 +
board/freescale/imxrt1050-evk/MAINTAINERS | 1 +
.../freescale/imxrt1050-evk/imximage-nor.cfg | 42
board/freescale/imxrt1050-evk/imximage.cfg| 10 +-
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 7 +-
configs/imxrt1050-evk_defconfig | 8 +-
configs/imxrt1050-evk_fspi_defconfig | 100 ++
include/configs/imxrt1050-evk.h | 6 ++
9 files changed, 200 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/imxrt1050-evk/imximage-nor.cfg
create mode 100644 configs/imxrt1050-evk_fspi_defconfig
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index a9095e736b..3f54411b7b 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -8,6 +8,10 @@
#include "imxrt1050-pinfunc.h"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
aliases {
display0 = &lcdif;
usbphy0 = &usbphy1;
@@ -113,6 +117,33 @@
};
};
+&binman {
+#ifdef CONFIG_FSPI_CONF_HEADER
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ fspi_conf_block {
+ filename = CONFIG_FSPI_CONF_FILE;
+ type = "blob-ext";
+ offset = <0x0>;
+ };
+
+ spl {
+ filename = "SPL";
+ offset = <0x1000>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.img";
+ offset = <0x1>;
+ type = "blob-ext";
+ };
+ };
+#endif
+};
+
&osc {
bootph-pre-ram;
};
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index c1d6b09e77..f702f6 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -2,6 +2,7 @@ if ARCH_IMXRT
config IMXRT
bool
+ select BINMAN
select SYS_FSL_ERRATUM_ESDHC135
config IMXRT1020
diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS
b/board/freescale/imxrt1050-evk/MAINTAINERS
index a872855452..890825b39a 100644
--- a/board/freescale/imxrt1050-evk/MAINTAINERS
+++ b/board/freescale/imxrt1050-evk/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/imxrt1050-evk
F: include/configs/imxrt1050-evk.h
F: configs/imxrt1050-evk_defconfig
+F: configs/imxrt1050-evk_fspi_defconfig
diff --git a/board/freescale/imxrt1050-evk/imximage-nor.cfg
b/board/freescale/imxrt1050-evk/imximage-nor.cfg
new file mode 100644
index 00..3b80e1f178
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imximage-nor.cfg
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024
+ * Author(s): Jesse Taube
+ */
+
+#include
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM nor
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunately setting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configuration fortunately works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aa
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
+
diff --git a/board/freescale/imxrt1050-evk/imximage.cfg
b/board/freescale/imxrt1050-evk/imximage.cfg
index f1f09fd7eb..b30d852194 100644
--- a/board/freescale/imxrt1050-evk/imximage.cfg
+++ b/board/freescale/imxrt1050-evk/imximage.cfg
@@ -29,7 +29,13 @@ BOOT_FROMsd
* value value to be stored in the register
*/
-/* Set all FlexRAM as OCRAM(01b) */
-DATA 4 0x400AC044 0x
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunately setting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configuration fortunately works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) an
[PATCH v2 2/2] imx: imxrt1050-evk: Add documentation for SPI boot
Add documentation for SPI boot. Signed-off-by: Jesse Taube --- V1 -> V2: - Change s/Adds/Add - Change imxrt1050-evk_spi to fspi - Fix spelling and grammar - Mention the SPI NOR flash part number --- doc/board/nxp/imxrt1050-evk.rst | 30 ++ 1 file changed, 30 insertions(+) diff --git a/doc/board/nxp/imxrt1050-evk.rst b/doc/board/nxp/imxrt1050-evk.rst index c1fb48f0cd..e0cafe1035 100644 --- a/doc/board/nxp/imxrt1050-evk.rst +++ b/doc/board/nxp/imxrt1050-evk.rst @@ -39,3 +39,33 @@ switch label numbers reference). The USB console connector is the one close the ethernet connector - Insert the micro SD card in the board, power it up and U-Boot messages should come up. + + +How to use U-Boot with SPI flash on NXP i.MXRT1050 EVK +-- + +- Build U-Boot for i.MXRT1050 EVK: + +.. code-block:: bash + + $ make mrproper + $ make imxrt1050-evk_fspi_defconfig + $ make + +This will generate SPL, uboot.img, fspi_header.bin, and the final image (flash.bin). + +To boot from SPI flash on other boards, you may need to change the flash header config, +which is specific to your flash chip, in Kconfig. +The flash config is 4K in size and is documented on page 217 of the imxrt1050 RM. +The default flash chip on the i.MXRT1050 EVK is the S26KS512SDPBHI02 HYPERFLASH. + +- Jumper settings:: + + SW7: 0 1 1 0 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Connect the USB cable between the EVK and the PC for the console. + +- Use either JTAG or SWD to write `flash.bin` to the NOR. I used Mcuexpresso IDE's GUI flash tool. -- 2.43.0
[PATCH v1] doc: imx: imxrt1170: Document imxrt1170-evk board
Add documentation for imxrt1170-evk. Signed-off-by: Jesse Taube --- doc/board/nxp/imxrt1170-evk.rst | 42 + 1 file changed, 42 insertions(+) create mode 100644 doc/board/nxp/imxrt1170-evk.rst diff --git a/doc/board/nxp/imxrt1170-evk.rst b/doc/board/nxp/imxrt1170-evk.rst new file mode 100644 index 00..4acccdcc93 --- /dev/null +++ b/doc/board/nxp/imxrt1170-evk.rst @@ -0,0 +1,42 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imxrt1170-evk += + +How to use U-Boot on NXP i.MXRT1170 EVK +--- + +- Build U-Boot for i.MXRT1170 EVK: + +.. code-block:: bash + + $ make mrproper + $ make imxrt1170-evk_defconfig + $ make + +This will generate the SPL image called SPL and the u-boot.img. + +- Flash the SPL image into the micro SD card: + +.. code-block:: bash + + $sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=notrunc; sync + +- Flash the u-boot.img image into the micro SD card: + +.. code-block:: bash + + $sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128 conv=notrunc; sync + +- Jumper settings:: + + SW1: 1 0 1 0 + SW2: 0 0 0 0 0 0 0 0 1 0 0 0 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Connect the USB cable between the EVK and the PC for the console. + The USB console connector is the one close the ethernet connector + +- Insert the micro SD card in the board, power it up and U-Boot messages should come up. -- 2.43.0
[PATCH v1 2/2] imx: imxrt1050-evk: Add documentation for SPI boot
Adds documentation for SPI boot. Signed-off-by: Jesse Taube --- doc/board/nxp/imxrt1050-evk.rst | 29 + 1 file changed, 29 insertions(+) diff --git a/doc/board/nxp/imxrt1050-evk.rst b/doc/board/nxp/imxrt1050-evk.rst index c1fb48f0cd..aca5071181 100644 --- a/doc/board/nxp/imxrt1050-evk.rst +++ b/doc/board/nxp/imxrt1050-evk.rst @@ -39,3 +39,32 @@ switch label numbers reference). The USB console connector is the one close the ethernet connector - Insert the micro SD card in the board, power it up and U-Boot messages should come up. + + +How to use U-Boot with SPI flash on NXP i.MXRT1050 EVK +-- + +- Build U-Boot for i.MXRT1050 EVK: + +.. code-block:: bash + + $ make mrproper + $ make imxrt1050-evk_spi_defconfig + $ make + +This will generate SPL, uboot.img, fspi_header.bin, and the final image (flash.bin). + +To boot from SPI flash on other boards you may need to change the flash header config, +that is specific to your flash chip, in Kconfig. +The flash config is 4K in size and is documented on page 217 of the imxrt1050RM. + +- Jumper settings:: + + SW7: 0 1 1 0 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Connect the USB cable between the EVK and the PC for the console. + +- Use either JTAG or SWD to write `flash.bin` to the NOR. I used Mcuexpresso IDE's GUI flash tool. -- 2.43.0
[PATCH v1 1/2] imx: imxrt1050-evk: Add support for SPI flash booting
This add some macros to change addresses to use flexspi.
This commit adds support for booting the imxrt1050-evk from spi.
It adds imximage config and the ability for SPL to boot from NOR.
Signed-off-by: Jesse Taube
---
arch/arm/dts/imxrt1050-evk-u-boot.dtsi| 31 ++
arch/arm/mach-imx/imxrt/Kconfig | 1 +
.../freescale/imxrt1050-evk/imximage-nor.cfg | 41 +++
board/freescale/imxrt1050-evk/imximage.cfg| 10 +-
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 7 +-
configs/imxrt1050-evk_defconfig | 8 +-
configs/imxrt1050-evk_fspi_defconfig | 100 ++
include/configs/imxrt1050-evk.h | 6 ++
8 files changed, 198 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/imxrt1050-evk/imximage-nor.cfg
create mode 100644 configs/imxrt1050-evk_fspi_defconfig
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index a9095e736b..3f54411b7b 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -8,6 +8,10 @@
#include "imxrt1050-pinfunc.h"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
aliases {
display0 = &lcdif;
usbphy0 = &usbphy1;
@@ -113,6 +117,33 @@
};
};
+&binman {
+#ifdef CONFIG_FSPI_CONF_HEADER
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ fspi_conf_block {
+ filename = CONFIG_FSPI_CONF_FILE;
+ type = "blob-ext";
+ offset = <0x0>;
+ };
+
+ spl {
+ filename = "SPL";
+ offset = <0x1000>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.img";
+ offset = <0x1>;
+ type = "blob-ext";
+ };
+ };
+#endif
+};
+
&osc {
bootph-pre-ram;
};
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index c1d6b09e77..f702f6 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -2,6 +2,7 @@ if ARCH_IMXRT
config IMXRT
bool
+ select BINMAN
select SYS_FSL_ERRATUM_ESDHC135
config IMXRT1020
diff --git a/board/freescale/imxrt1050-evk/imximage-nor.cfg
b/board/freescale/imxrt1050-evk/imximage-nor.cfg
new file mode 100644
index 00..fb7b6489a3
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imximage-nor.cfg
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti
+ */
+
+#include
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM nor
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunatly seting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configureation fortunaly works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aa
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1050-evk/imximage.cfg
b/board/freescale/imxrt1050-evk/imximage.cfg
index f1f09fd7eb..dd5c231b39 100644
--- a/board/freescale/imxrt1050-evk/imximage.cfg
+++ b/board/freescale/imxrt1050-evk/imximage.cfg
@@ -29,7 +29,13 @@ BOOT_FROMsd
* value value to be stored in the register
*/
-/* Set all FlexRAM as OCRAM(01b) */
-DATA 4 0x400AC044 0x
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunatly seting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configureation fortunaly works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aa
/* Use FLEXRAM_BANK_CFG to config FlexRAM */
SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
index 4b82ee5e9c..d4e39fd914 100644
--- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
+++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
@@ -68,7 +68,12 @@ void spl_board_init(void)
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_MMC1;
+ /* There is no way to find boot device so look if there is v
[PATCH v1] tools: mkimage: Add support for i.MXRT FlexSPI Header
Modify imx8m Flex SPI Configuration Block to work with imxrt.
Add more Flex SPI configuration options to Kconfig.
Signed-off-by: Jesse Taube
---
include/imximage.h | 42 +
tools/Kconfig | 21 +
tools/imx8mimage.c | 41
tools/imximage.c | 77 ++
4 files changed, 143 insertions(+), 38 deletions(-)
diff --git a/include/imximage.h b/include/imximage.h
index c1ecc0b7cb..a951699d0a 100644
--- a/include/imximage.h
+++ b/include/imximage.h
@@ -210,33 +210,37 @@ typedef struct {
uint8_t datasetup;
uint8_t coladdrwidth;
uint8_t devcfgenable;
- uint8_t reserved_2[3];
+ uint8_t deviceModeType;
+ uint16_t waitTimeCfgCommands;
uint8_t devmodeseq[4];
- uint8_t devmodearg[4];
+ uint32_t devmodearg;
uint8_t cmd_enable;
- uint8_t reserved_3[3];
+ uint8_t configModeType[3];
uint8_t cmd_seq[16] ;
uint8_t cmd_arg[16];
- uint8_t controllermisc[4];
+ uint32_t controllermisc;
uint8_t dev_type;
uint8_t sflash_pad;
uint8_t serial_clk;
- uint8_t lut_custom ;
- uint8_t reserved_4[8];
- uint8_t sflashA1[4];
- uint8_t sflashA2[4];
- uint8_t sflashB1[4];
- uint8_t sflashB2[4];
- uint8_t cspadover[4];
- uint8_t sclkpadover[4];
- uint8_t datapadover[4];
- uint8_t dqspadover[4];
- uint8_t timeout[4];
- uint8_t commandInt[4];
- uint8_t datavalid[4];
- uint8_t busyoffset[2];
- uint8_t busybitpolarity[2];
+ uint8_t lut_custom;
+ uint8_t reserved_2[8];
+ uint32_t sflashA1;
+ uint32_t sflashA2;
+ uint32_t sflashB1;
+ uint32_t sflashB2;
+ uint32_t cspadover;
+ uint32_t sclkpadover;
+ uint32_t datapadover;
+ uint32_t dqspadover;
+ uint32_t timeout;
+ uint32_t commandInt;
+ uint16_t datavalid[2];
+ uint16_t busyoffset;
+ uint16_t busybitpolarity;
uint8_t lut[256];
+ uint8_t lutCustomSeq[48];
+ uint8_t reserved_3[16];
+
} __attribute__((packed)) fspi_conf;
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
diff --git a/tools/Kconfig b/tools/Kconfig
index f01ed783e6..667807b331 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -148,6 +148,27 @@ config SERIAL_CLK_FREQUENCY
Chip specific frequency: other value 30MHz
1-30MHz 2-50MHz 3-60MHz 4-75MHz 5-80MHz 6-100MHz 7-133MHz 8-166MHz
+config FSPI_COL_ADDR_W
+ hex "Column Address With"
+ default 0x00
+ depends on FSPI_CONF_HEADER
+ help
+ Default 0. For HyperBus protocol, it is fixed to 3
+
+config FSPI_CONTROLLER_MISC
+ hex "FSPI miscellaneous control"
+ default 0x
+ depends on FSPI_CONF_HEADER
+ help
+ Default 0. [0x40] Controller Misc Options
+
+config FSPI_FLASH_A1_SIZE
+ hex "Size in bytes of Flash A1"
+ default 0x1000
+ depends on FSPI_CONF_HEADER
+ help
+ Size of Flash connected to A1 in bytes
+
config LUT_CUSTOM_SEQUENCE
hex "Enable Custom Look Up Table(LUT) Sequence"
default 0x00
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index 21075c2379..939f829a9f 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -426,36 +426,39 @@ static int generate_fspi_header (int ifd)
.read_sample = CONFIG_READ_CLK_SOURCE,
.datahold = 0x03,
.datasetup = 0x03,
- .coladdrwidth = 0x00,
+ .coladdrwidth = CONFIG_FSPI_COL_ADDR_W,
.devcfgenable = 0x00,
- .reserved_2 = {0x00, 0x00, 0x00},
+ .deviceModeType = 0x00,
+ .waitTimeCfgCommands = 0x,
.devmodeseq = {0x00, 0x00, 0x00, 0x00},
- .devmodearg = {0x00, 0x00, 0x00, 0x00},
+ .devmodearg = 0x,
.cmd_enable = 0x00,
- .reserved_3 = {0x00},
+ .configModeType = {0x00},
.cmd_seq = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00},
.cmd_arg = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00},
- .controllermisc = {0x00, 0x00, 0x00, 0x00},
+ .controllermisc = cpu_to_le32(CONFIG_FSPI_CONTROLLER_MISC),
.dev_type = CONFIG_DEVICE_TYPE,
.sflash_pad = CONFIG_FLASH_PAD_TYPE,
.serial_clk = CONFIG_SERIAL_CLK_FREQUENCY,
.lut_custom = CONFIG_LUT_CUSTOM_SEQUENCE,
- .reserved_4 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .sflashA1 = {0x00, 0x00, 0x00, 0x10},
- .sflashA2 = {0x00, 0x00, 0x00, 0x00},
- .sflashB1 = {0x00, 0x00, 0x00, 0x00},
- .sflashB2 = {0x00, 0x00, 0x00, 0x00},
- .cspadover = {0x00, 0x00, 0x00, 0x00},
[PATCH v1] configs: imxrt1050-evk: enable distro bootcmd
Add support to boot from script.scr from mmc. imxrt1050-evk was not able to boot from script.scr because we did not include config_distro_bootcmd.h and set the device to mmc. Signed-off-by: Jesse Taube --- configs/imxrt1050-evk_defconfig | 2 +- include/configs/imxrt1050-evk.h | 15 ++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index cbf9469b24..35c0364e6b 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_SYS_UBOOT_START=y CONFIG_SYS_UBOOT_START=0x800023FD CONFIG_DISTRO_DEFAULTS=y CONFIG_SD_BOOT=y -# CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_NO_BSS_LIMIT=y @@ -40,6 +39,7 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_MII is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index 2af2dde2ae..4b78d61d3f 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -19,10 +19,23 @@ DMAMEM_SZ_ALL) #ifdef CONFIG_VIDEO -#define CFG_EXTRA_ENV_SETTINGS \ +#define ENV_DEVICE_SETTINGS \ "stdin=serial\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" #endif +/* Config distro_bootcmd */ +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) +#include +#endif + +#define CFG_EXTRA_ENV_SETTINGS \ + ENV_DEVICE_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(PHYS_SDRAM) "\0" \ + "kernel_addr_r" __stringify(PHYS_SDRAM) "\0" + #endif /* __IMXRT1050_EVK_H */ -- 2.40.1
[PATCH v2] Convert CFG_SYS_UBOOT_START to Kconfig
Commit 65cc0e2a65d2 ("global: Move remaining CONFIG_SYS_* to CFG_SYS_*")
renamed CONFIG_SYS_UBOOT_START to CFG_SYS_UBOOT_START. Unfortunately,
this meant that the value was no longer available to the Makefile. This
caused imxrt to fail to boot. All the other boards that used this
variable were unaffected because they were using the default value
which is CONFIG_TEXT_BASE.
This commit converts CFG_SYS_UBOOT_START to Kconfig and sets the default
value to CONFIG_TEXT_BASE.
Suggested-by: Marek Vasut
Suggested-by: Tom Rini
Signed-off-by: Jesse Taube
---
V1->V2:
- Add "and executed" to TEXT_BASE
- Reword SYS_UBOOT_START
- Reword HAVE_SYS_UBOOT_START
- Use bool as prompt
---
Makefile | 16
arch/arm/mach-k3/config_secure.mk | 2 +-
arch/arm/mach-omap2/config_secure.mk | 2 +-
boot/Kconfig | 19 ++-
common/spl/spl.c | 6 +-
common/spl/spl_fit.c | 2 +-
configs/imxrt1020-evk_defconfig | 2 ++
configs/imxrt1050-evk_defconfig | 2 ++
configs/imxrt1170-evk_defconfig | 2 ++
.../configs/gardena-smart-gateway-mt7688.h| 4
include/configs/imxrt1020-evk.h | 6 --
include/configs/imxrt1050-evk.h | 6 --
include/configs/imxrt1170-evk.h | 3 ---
include/configs/linkit-smart-7688.h | 4
include/configs/mt7620.h | 3 ---
include/configs/mt7628.h | 3 ---
include/configs/mt8512.h | 2 --
include/configs/vocore2.h | 4
include/spl.h | 2 +-
19 files changed, 33 insertions(+), 57 deletions(-)
diff --git a/Makefile b/Makefile
index 9b90204bfe..13d4c63439 100644
--- a/Makefile
+++ b/Makefile
@@ -1364,14 +1364,6 @@ OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
$(call if_changed,objcopy)
-#
-# U-Boot entry point, needed for booting of full-blown U-Boot
-# from the SPL U-Boot version.
-#
-ifndef CFG_SYS_UBOOT_START
-CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
-endif
-
# Boards with more complex image requirements can provide an .its source file
# or a generator script
# NOTE: Please do not use this. We are migrating away from Makefile rules to
use
@@ -1391,7 +1383,7 @@ endif
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
@@ -1399,10 +1391,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T
firmware -C none -O u-boot \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst
",,$(CONFIG_OF_OVERLAY_LIST)))
else
MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
endif
@@ -1433,7 +1425,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n
$(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
UBOOT_BIN := u-boot.bin
MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot.bin.lzma: u-boot.bin FORCE
diff --git a/arch/arm/mach-k3/config_secure.mk
b/arch/arm/mach-k3/config_secure.mk
index 7bc8af813a..9cc1f9eb24 100644
--- a/arch/arm/mach-k3/config_secure.mk
+++ b/arch/arm/mach-k3/config_secure.mk
@@ -30,7 +30,7 @@ tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst
%,$(obj)/dts/%.dtb_HS,$(
$(call if_changed,mkfitimage)
MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
diff --git a/arch/arm/mach-omap2/config_secure.mk
b/arch/arm/mach-omap2/config_secure.mk
index 24ddcdb961..f76262bb0c 100644
--- a/arc
[PATCH] Convert CFG_SYS_UBOOT_START to Kconfig
Commit 65cc0e2a65d2 ("global: Move remaining CONFIG_SYS_* to CFG_SYS_*")
renamed CONFIG_SYS_UBOOT_START to CFG_SYS_UBOOT_START. Unfortunately,
this meant that the value was no longer available to the Makefile. This
caused imxrt to fail to boot. All the other boards that used this
variable were unaffected because they were using the default value
which is CONFIG_TEXT_BASE.
This commit converts CFG_SYS_UBOOT_START to Kconfig and sets the default
value to CONFIG_TEXT_BASE.
Suggested-by: Marek Vasut
Suggested-by: Tom Rini
Signed-off-by: Jesse Taube
---
Makefile | 16
arch/arm/mach-k3/config_secure.mk | 2 +-
arch/arm/mach-omap2/config_secure.mk | 2 +-
boot/Kconfig | 16
common/spl/spl.c | 6 +-
common/spl/spl_fit.c | 2 +-
configs/imxrt1020-evk_defconfig| 2 ++
configs/imxrt1050-evk_defconfig| 2 ++
configs/imxrt1170-evk_defconfig| 2 ++
include/configs/gardena-smart-gateway-mt7688.h | 4
include/configs/imxrt1020-evk.h| 6 --
include/configs/imxrt1050-evk.h| 6 --
include/configs/imxrt1170-evk.h| 3 ---
include/configs/linkit-smart-7688.h| 4
include/configs/mt7620.h | 3 ---
include/configs/mt7628.h | 3 ---
include/configs/mt8512.h | 2 --
include/configs/vocore2.h | 4
include/spl.h | 2 +-
19 files changed, 31 insertions(+), 56 deletions(-)
diff --git a/Makefile b/Makefile
index 9b90204bfe..13d4c63439 100644
--- a/Makefile
+++ b/Makefile
@@ -1364,14 +1364,6 @@ OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
$(call if_changed,objcopy)
-#
-# U-Boot entry point, needed for booting of full-blown U-Boot
-# from the SPL U-Boot version.
-#
-ifndef CFG_SYS_UBOOT_START
-CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
-endif
-
# Boards with more complex image requirements can provide an .its source file
# or a generator script
# NOTE: Please do not use this. We are migrating away from Makefile rules to
use
@@ -1391,7 +1383,7 @@ endif
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
@@ -1399,10 +1391,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T
firmware -C none -O u-boot \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst
",,$(CONFIG_OF_OVERLAY_LIST)))
else
MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
endif
@@ -1433,7 +1425,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n
$(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
UBOOT_BIN := u-boot.bin
MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot.bin.lzma: u-boot.bin FORCE
diff --git a/arch/arm/mach-k3/config_secure.mk
b/arch/arm/mach-k3/config_secure.mk
index 7bc8af813a..9cc1f9eb24 100644
--- a/arch/arm/mach-k3/config_secure.mk
+++ b/arch/arm/mach-k3/config_secure.mk
@@ -30,7 +30,7 @@ tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst
%,$(obj)/dts/%.dtb_HS,$(
$(call if_changed,mkfitimage)
MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
diff --git a/arch/arm/mach-omap2/config_secure.mk
b/arch/arm/mach-omap2/config_secure.mk
index 24ddcdb961..f76262bb0c 100644
--- a/arch/arm/mach-omap2/config_secure.mk
+++ b/arch/arm/mach-omap2/config_secure.mk
@@ -102,7 +102,7 @@ u-boot_HS_XIP_X-LOADER: $(obj)/u
Re: [PATCH v2 3/4] sunxi: binman: Support FIT generation for 32-bit SoCs
On 1/22/23 16:15, Samuel Holland wrote:
Some 32-bit SoCs can use SCP firmware to implement additional PSCI
functionality, such as system suspend. In order to load this firmware
from SPL, we need to generate and use a FIT instead of a legacy image.
Adjust the binman FIT definition so it does not rely on TF-A BL31, as
this is not used on 32-bit SoCs. Instead, after loading the firmware,
U-Boot proper is executed directly.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Rely on binman min-size instead of using explicit offsets
- Use Kconfig for firmware addresses instead of an #ifdef staircase
arch/arm/dts/sunxi-u-boot.dtsi | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index f38359fd42..c7089b8619 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -1,5 +1,11 @@
#include
+#ifdef CONFIG_ARM64
+#define ARCH "arm64"
+#else
+#define ARCH "arm"
+#endif
+
There should be a better way to do this, but if not shouldn't the else
should be elseif because of the RISCV SOCs.
The rest looks fine to me.
Thanks,
Jesse T
/ {
aliases {
#ifndef CONFIG_MACH_SUNIV
@@ -29,30 +35,32 @@
filename = "spl/sunxi-spl.bin";
};
-#ifdef CONFIG_ARM64
+#ifdef CONFIG_SPL_LOAD_FIT
fit {
- description = "Configuration to load ATF before U-Boot";
+ description = "Configuration to load U-Boot and
firmware";
#address-cells = <1>;
fit,fdt-list = "of-list";
images {
uboot {
- description = "U-Boot (64-bit)";
+ description = "U-Boot";
type = "standalone";
os = "u-boot";
- arch = "arm64";
+ arch = ARCH;
compression = "none";
load = ;
+ entry = ;
u-boot-nodtb {
};
};
+#if CONFIG_SUNXI_BL31_BASE
atf {
description = "ARM Trusted Firmware";
type = "firmware";
os = "arm-trusted-firmware";
- arch = "arm64";
+ arch = ARCH;
compression = "none";
load = ;
entry = ;
@@ -62,6 +70,7 @@
missing-msg = "atf-bl31-sunxi";
};
};
+#endif
#if CONFIG_SUNXI_SCP_BASE
scp {
@@ -90,7 +99,11 @@
@config-SEQ {
description = "NAME";
+#if CONFIG_SUNXI_BL31_BASE
firmware = "atf";
+#else
+ firmware = "uboot";
+#endif
#if CONFIG_SUNXI_SCP_BASE
loadables = "scp", "uboot";
#else
Re: [PATCH v3 3/8] imxrt1050: synchronise device tree with linux
On 10/23/22 18:13, Marcel Ziswiler wrote:
Hi Giulio
On Sun, 2022-10-23 at 01:47 +0200, Giulio Benetti wrote:
Hi Marcel,
Il 22/10/2022 23:42, Marcel Ziswiler ha scritto:
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
Changes in v3:
- Incorporate feedback from Jesse.
Changes in v2:
- imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 162 ++--
arch/arm/dts/imxrt1050-evk.dts | 257 +++-
arch/arm/dts/imxrt1050-pinfunc.h | 2 +-
arch/arm/dts/imxrt1050.dtsi | 168 ++---
include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
5 files changed, 255 insertions(+), 343 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 617cece448..bf40ada234 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -4,8 +4,12 @@
* Author(s): Giulio Benetti
*/
+#include
+#include "imxrt1050-pinfunc.h"
+
/ {
chosen {
+ tick-timer = &gpt;
u-boot,dm-spl;
};
@@ -15,6 +19,52 @@
soc {
u-boot,dm-spl;
+
+ semc@402f {
semc: semc@402f {
+ compatible = "fsl,imxrt-semc";
move reg node here
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ reg = <0x402f 0x4000>;
reg node ^^^
+ status = "okay";
+ u-boot,dm-spl;
+
I think this needs to be moved to &semc but i may be wrong, reffer to
https://github.com/Mr-Bossman/u-boot/commit/42a7f430d761bb4d44f646a27649deda15352f2e#diff-743b975140312a7292a3aa36def69ff93b4d4571bb22166a5943f17935bc767dR33
+ /*
+ * Memory configuration from sdram datasheet
IS42S16160J-6BLI
+ */
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+ 0x2
+ 0x9
+ 0x1
+ 0x5
+ 0x6
+
+ 0x20
+ 0x09
+ 0x01
+ 0x00
+
+ 0x04
+ 0x0A
+ 0x21
+ 0x50>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x8000>;
+ fsl,memory-size = ;
+ u-boot,dm-spl;
+ };
+ };
};
};
@@ -50,41 +100,121 @@
u-boot,dm-spl;
};
-&gpt1 {
+&gpt {
+ clocks = <&osc>;
+ compatible = "fsl,imxrt-gpt";
+ status = "okay";
u-boot,dm-spl;
};
&lpuart1 { /* console */
+ compatible = "fsl,imxrt-lpuart";
+ clock-names = "per";
Forgot this last time sry.
u-boot,dm-spl;
};
-&semc {
- u-boot,dm-spl;
-
- bank1: bank@0 {
- u-boot,dm-spl;
- };
-};
-
&iomuxc {
u-boot,dm-spl;
compatible = "fsl,imxrt-iomuxc";
pinctrl-0 = <&pinctrl_lpuart1>;
imxrt1050-evk {
Must drop extra node to make compatible with linux.
Also add gpio compatibles.
&gpio1 {
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
u-boot,dm-spl;
};
Reffer to https://github.com/Mr-Bossman/u-boot/commits/sync for changes
which I tested.
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
- u-boot,dm-spl;
- };
-
- pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1/* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1 /* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1 /* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+
Re: [PATCH v2 3/8] imxrt1050: synchronise device tree with linux
On 10/22/22 08:57, Marcel Ziswiler wrote:
Hi Jesse
Sorry, I kinda missed your reply and imx maintainership was quiet for quite
some time. I am now preparing a v3
taking your feedback into account. Thanks!
On Sun, 2022-08-28 at 02:50 -0400, Jesse Taube wrote:
On 8/26/22 14:31, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
Changes in v2:
- imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 155 ++--
arch/arm/dts/imxrt1050-evk.dts | 257 +++-
arch/arm/dts/imxrt1050-pinfunc.h | 2 +-
arch/arm/dts/imxrt1050.dtsi | 168 ++---
include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
5 files changed, 248 insertions(+), 343 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 617cece448a..7db53b19c2f 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -4,6 +4,8 @@
* Author(s): Giulio Benetti
*/
+#include
+
#include "imxrt1050-pinfunc.h"
Okay.
/ {
chosen {
u-boot,dm-spl;
diff says `tick-timer = &gpt;` its important for boot
Okay.
@@ -15,6 +17,52 @@
soc {
u-boot,dm-spl;
+
+ semc@402f {
+ compatible = "fsl,imxrt-semc";
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ reg = <0x402f 0x4000>;
+ status = "okay";
+ u-boot,dm-spl;
I dont think this part under should go here tell me if im wrong. It
should be move outside as a reference.
Not sure what you mean as this is the U-Boot specific device tree include file
after all.
+ /*
+ * Memory configuration from sdram datasheet
IS42S16160J-6BLI
+ */
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+ 0x2
+ 0x9
+ 0x1
+ 0x5
+ 0x6
+
+ 0x20
+ 0x09
+ 0x01
+ 0x00
+
+ 0x04
+ 0x0A
+ 0x21
+ 0x50>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x8000>;
+ fsl,memory-size = ;
+ u-boot,dm-spl;
+ };
+ };
};
};
@@ -50,7 +98,7 @@
u-boot,dm-spl;
};
-&gpt1 {
+&gpt {
Add diff:
clocks = <&osc>;
compatible = "fsl,imxrt-gpt";
status = "okay";
Okay.
u-boot,dm-spl;
};
@@ -58,33 +106,108 @@
u-boot,dm-spl;
};
-&semc {
- u-boot,dm-spl;
-
- bank1: bank@0 {
- u-boot,dm-spl;
- };
-};
-
&iomuxc {
u-boot,dm-spl;
imxrt1050-evk {drop unneeded node ^^^
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
- u-boot,dm-spl;
- };
-
- pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1/* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1 /* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1 /* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+ 0xf1 /* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
+ 0xf1 /* SEMC_D4
Re: [PATCH 6/6] sunxi: add CherryPi-F1C200s support
On 10/13/22 05:53, Andre Przywara wrote:
On 13/10/2022 09:33, Clément Péron wrote:
Hi Clément,
On Wed, 12 Oct 2022 at 18:35, Andre Przywara wrote:
The CherryPi F1C200s board is a small development board, featuring the
F1C200s with 64MB of co-packaged DRAM. It comes with two USB-C sockets,
of which one is connected to a USB-UART chip, that provides easy access
to UART1.
A similar board is trying to been upstreamed by Icenowy:
see : https://lore.kernel.org/lkml/20221012055602.1544944-11-...@icenowy.me/
[PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1
Maybe we should take into account the remarks that Krzysztof Kozlowski
made to follow the same device-tree rules on U-boot.
Yeah, thanks for the heads up, I saw that. I just wanted to post this to
demonstrate what needs to be done. I will be sending a Linux DT patch
anyway, since DTs need to go via Linux anyway.
Thanks,
Andre
Regards,
Clement
Beside the usual micro-SD card slot, the board comes with a SPI NAND
flash chip, which is not yet supported.
Signed-off-by: Andre Przywara
---
.../dts/suniv-f1c100s-cherrypi-f1c200s.dts| 45 +++
configs/cherrypi_f1c200s_defconfig| 11 +
2 files changed, 56 insertions(+)
create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
create mode 100644 configs/cherrypi_f1c200s_defconfig
diff --git a/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
new file mode 100644
index 000..f0ebcb6d893
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2022 Arm Ltd.
+ * based on another DT, which is:
+ * Copyright 2018 Icenowy Zheng
Her email changed IDK if it is proper to change here.
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+/ {
+ model = "Cherry Pi F1C200s";
+ compatible = "lctech,cherrypi-f1c200s", "allwinner,suniv-f1c100s";
+
+ aliases {
+ mmc0 = &mmc0;
+ serial0 = &uart1;
+ spi0 = &spi0;
no need for spi.
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ status = "okay";
+ vmmc-supply = <®_vcc3v3>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pa_pins>;
+ status = "okay";
+};
diff --git a/configs/cherrypi_f1c200s_defconfig
b/configs/cherrypi_f1c200s_defconfig
new file mode 100644
index 000..306d363f485
--- /dev/null
+++ b/configs/cherrypi_f1c200s_defconfig
@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-cherrypi-f1c200s"
+CONFIG_SPL=y
+CONFIG_MACH_SUNIV=y
+CONFIG_DRAM_CLK=156
+CONFIG_DRAM_ZQ=0
You need
+CONFIG_SPL_STACK=0x8000
I will test this on both 100s and 200s.
Thanks,
Jesse Taube
+CONFIG_SUNXI_MINIMUM_DRAM_MB=64
+# CONFIG_VIDEO_SUNXI is not set
+CONFIG_CONS_INDEX=2
--
2.25.1
Re: [PATCH v3 6/8] RAM: Add changes for i.MXRT11xx series
On 7/27/22 13:19, sba...@denx.de wrote: The i.MXRT11 series has different offsets for IOCR_MUX, it also can address 64MiB of SDRAM so add a macro for that. Signed-off-by: Jesse Taube Applied to u-boot-imx, master, thanks ! Was this ever applied? Thanks, Jesse Best regards, Stefano Babic
Re: [PATCH v2 3/8] imxrt1050: synchronise device tree with linux
On 8/26/22 14:31, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
Changes in v2:
- imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 155 ++--
arch/arm/dts/imxrt1050-evk.dts | 257 +++-
arch/arm/dts/imxrt1050-pinfunc.h| 2 +-
arch/arm/dts/imxrt1050.dtsi | 168 ++---
include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
5 files changed, 248 insertions(+), 343 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 617cece448a..7db53b19c2f 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -4,6 +4,8 @@
* Author(s): Giulio Benetti
*/
+#include
+
#include "imxrt1050-pinfunc.h"
/ {
chosen {
u-boot,dm-spl;
diff says `tick-timer = &gpt;` its important for boot
@@ -15,6 +17,52 @@
soc {
u-boot,dm-spl;
+
+ semc@402f {
+ compatible = "fsl,imxrt-semc";
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ reg = <0x402f 0x4000>;
+ status = "okay";
+ u-boot,dm-spl;
I dont think this part under should go here tell me if im wrong. It
should be move outside as a reference.
+ /*
+* Memory configuration from sdram datasheet
IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0x9
+0x1
+0x5
+0x6
+
+0x20
+0x09
+0x01
+0x00
+
+0x04
+0x0A
+0x21
+0x50>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x8000>;
+ fsl,memory-size = ;
+ u-boot,dm-spl;
+ };
+ };
};
};
@@ -50,7 +98,7 @@
u-boot,dm-spl;
};
-&gpt1 {
+&gpt {
Add diff:
clocks = <&osc>;
compatible = "fsl,imxrt-gpt";
status = "okay";
u-boot,dm-spl;
};
@@ -58,33 +106,108 @@
u-boot,dm-spl;
};
-&semc {
- u-boot,dm-spl;
-
- bank1: bank@0 {
- u-boot,dm-spl;
- };
-};
-
&iomuxc {
u-boot,dm-spl;
imxrt1050-evk {drop unneeded node ^^^
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
- u-boot,dm-spl;
- };
-
- pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1/* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1/* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1/* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+ 0xf1/* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
+ 0xf1/* SEMC_D4 */
+ MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
+ 0xf1/* SEMC_D5 */
+ MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
+ 0xf1/* SEMC_D6 */
+ MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
+ 0xf1/* SEMC_D7 */
+ MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
+ 0xf1/* SEMC_DM0 */
+ MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+ 0xf1
Re: [PATCH v1 3/8] imxrt1050: synchronise device tree with linux
On 8/26/22 06:49, Fabio Estevam wrote:
Hi Marcel,
On Fri, Aug 26, 2022 at 6:55 AM Marcel Ziswiler wrote:
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Thanks for working on this.
-&semc {
- /*
-* Memory configuration from sdram datasheet IS42S16160J-6BLI
-*/
- fsl,sdram-mux = /bits/ 8 ;
Shouldn't this go to imxrt1050-evk-u-boot.dts?
This node is responsible for describing the DDR timings. Removing it
will cause boot regression.
Yes it will. Linux doesn't have LCD or dram yet,
it should be moved into imxrt1050-evk-u-boot.dtsi.
If needed I can sync it as well as test.
Thanks,
Jesse
I don't have access to this platform. Adding Jesse and Giulio.
[PATCH v3 7/8] ARM: dts: imx: add i.MXRT1170-EVK support
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and Cortex-M4 core.
The EVK provides 64 MB SDRAM, Micro SD card socket,
USB 2.0 OTG.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
SDRAM
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Remove unused constant clocks
V2 -> V3:
* Nothing done
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imxrt1170-evk-u-boot.dtsi | 94 +
arch/arm/dts/imxrt1170-evk.dts | 250
arch/arm/dts/imxrt1170.dtsi| 257 +
4 files changed, 603 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/dts/imxrt1170.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7fa275ea7c..ccdf643c86 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -974,7 +974,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
- imxrt1020-evk.dtb
+ imxrt1020-evk.dtb \
+ imxrt1170-evk.dtb \
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
new file mode 100644
index 00..88ff986ba0
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ clocks {
+ u-boot,dm-spl;
+ };
+
+ soc {
+ u-boot,dm-spl;
+ };
+};
+
+&osc {
+ u-boot,dm-spl;
+};
+
+&rcosc16M {
+ u-boot,dm-spl;
+};
+
+&osc32k {
+ u-boot,dm-spl;
+};
+
+&clks {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpt1 {
+ u-boot,dm-spl;
+};
+
+&lpuart1 { /* console */
+ u-boot,dm-spl;
+};
+
+&semc {
+ u-boot,dm-spl;
+
+ bank1: bank@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+
+ imxrt1170-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ u-boot,dm-spl;
+ };
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts
new file mode 100644
index 00..c2fd0c0392
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk.dts
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/dts-v1/;
+#include "imxrt1170.dtsi"
+#include "imxrt1170-evk-u-boot.dtsi"
+#include "imxrt1170-pinfunc.h"
+
+/ {
+ model = "NXP imxrt1170-evk board";
+ compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ tick-timer = &gpt1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x2024 0xf 0x8000 0x400>;
+
+ ocram: ocram@2024 {
+ device_type = "memory";
+ reg = <0x2024 0xf>;
+ };
+
+ sdram: sdram@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x400>;
+ };
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&semc {
+ /*
+* Memory configuration from sdram datasheet IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0xd
+0x0
+0x8
+0x7
+
+0x0d
+0x0b
+0x00
+0x00
+
+
[PATCH v3 8/8] ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig
Add a base defconfig for the i.MXRT1170 Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done V2 -> V3: * Rebase --- configs/imxrt1170-evk_defconfig | 70 + include/configs/imxrt1170-evk.h | 29 ++ 2 files changed, 99 insertions(+) create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 include/configs/imxrt1170-evk.h diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig new file mode 100644 index 00..870ca115d5 --- /dev/null +++ b/configs/imxrt1170-evk_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_ARCH_IMXRT=y +CONFIG_SYS_TEXT_BASE=0x2024 +CONFIG_SYS_MALLOC_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x8 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imxrt1170-evk" +CONFIG_SPL_TEXT_BASE=0x202C +CONFIG_TARGET_IMXRT1170_EVK=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SIZE_LIMIT=0x2 +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2034 +CONFIG_SYS_LOAD_ADDR=0x202C +CONFIG_SD_BOOT=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_NO_BSS_LIMIT=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 +# CONFIG_SPL_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_MII is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_OF_TRANSLATE is not set +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMXRT1170=y +CONFIG_CLK_IMXRT1170=y +# CONFIG_SPL_DM_GPIO is not set +CONFIG_MXC_GPIO=y +# CONFIG_INPUT is not set +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMXRT=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_IMXRT_SDRAM=y +CONFIG_FSL_LPUART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h new file mode 100644 index 00..2459fe24e2 --- /dev/null +++ b/include/configs/imxrt1170-evk.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#ifndef __IMXRT1170_EVK_H +#define __IMXRT1170_EVK_H + +#include + +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +/* + * Configuration of the external SDRAM memory + */ + +#define PHYS_SDRAM 0x8000 +#define PHYS_SDRAM_SIZE(64 * 1024 * 1024) + +#define DMAMEM_SZ_ALL (1 * 1024 * 1024) +#define DMAMEM_BASE(PHYS_SDRAM + PHYS_SDRAM_SIZE - \ +DMAMEM_SZ_ALL) +/* For SPL */ +#define CONFIG_SYS_UBOOT_START 0x202403FD +/* For SPL ends */ + +#endif /* __IMXRT1170_EVK_H */ -- 2.36.1
[PATCH v3 6/8] RAM: Add changes for i.MXRT11xx series
The i.MXRT11 series has different offsets for IOCR_MUX, it also can
address 64MiB of SDRAM so add a macro for that.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Nothing done
V2 -> V3:
* Nothing done
---
drivers/ram/imxrt_sdram.c| 9 +
include/dt-bindings/memory/imxrt-sdram.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
index ca2eec767d..d0a88845cf 100644
--- a/drivers/ram/imxrt_sdram.c
+++ b/drivers/ram/imxrt_sdram.c
@@ -87,12 +87,21 @@ struct imxrt_semc_regs {
u32 sts[16];
};
+#if !defined(TARGET_IMXRT1170_EVK)
#define SEMC_IOCR_MUX_A8_SHIFT 0
#define SEMC_IOCR_MUX_CSX0_SHIFT 3
#define SEMC_IOCR_MUX_CSX1_SHIFT 6
#define SEMC_IOCR_MUX_CSX2_SHIFT 9
#define SEMC_IOCR_MUX_CSX3_SHIFT 12
#define SEMC_IOCR_MUX_RDY_SHIFT15
+#else
+#define SEMC_IOCR_MUX_A8_SHIFT 0
+#define SEMC_IOCR_MUX_CSX0_SHIFT 4
+#define SEMC_IOCR_MUX_CSX1_SHIFT 8
+#define SEMC_IOCR_MUX_CSX2_SHIFT 12
+#define SEMC_IOCR_MUX_CSX3_SHIFT 16
+#define SEMC_IOCR_MUX_RDY_SHIFT20
+#endif
struct imxrt_sdram_mux {
u8 a8;
diff --git a/include/dt-bindings/memory/imxrt-sdram.h
b/include/dt-bindings/memory/imxrt-sdram.h
index acb35bce27..4b3b0c2f50 100644
--- a/include/dt-bindings/memory/imxrt-sdram.h
+++ b/include/dt-bindings/memory/imxrt-sdram.h
@@ -82,6 +82,7 @@
#define MEM_WIDTH_8BITS0x0
#define MEM_WIDTH_16BITS 0x1
+#define MEM_WIDTH_32BITS 0x2
#define BL_1 0x0
#define BL_2 0x1
--
2.36.1
[PATCH v3 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver
Add clock driver support for i.MXRT1170.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Use C file not dts for constant clock divider
V2 -> V3:
* Nothing done
---
drivers/clk/imx/Kconfig | 16 +++
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-imxrt1170.c | 221
3 files changed, 238 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 04d252a1e0..abcb19ce6d 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -124,3 +124,19 @@ config CLK_IMXRT1050
select CLK_COMPOSITE_CCF
help
This enables support clock driver for i.MXRT1050 platforms.
+
+config SPL_CLK_IMXRT1170
+ bool "SPL clock support for i.MXRT1170"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MXRT1170.
+
+config CLK_IMXRT1170
+ bool "Clock support for i.MXRT1170"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1170 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index c5766901f2..b9c197f952 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o
clk-pll14xx.o \
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) += clk-imxrt1170.o
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
new file mode 100644
index 00..077dd1bf02
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static ulong imxrt1170_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1170_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1170_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1170_clk_disable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 0);
+}
+
+static int imxrt1170_clk_enable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 1);
+}
+
+static int imxrt1170_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &cp);
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
+static struct clk_ops imxrt1170_clk_ops = {
+ .set_rate = imxrt1170_clk_set_rate,
+ .get_rate = imxrt1170_clk_get_rate,
+ .enable = imxrt1170_clk_enable,
+ .disable = imxrt1170_clk_disable,
+ .set_parent = imxrt1170_clk_set_parent,
+};
+
+static const char * const lpuart1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3"};
+static const char * const gpt1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3"};
+static const char * const usdhc1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
+static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"};
+
+static int imxrt11
[PATCH v3 4/8] clk: imx: Add i.MXRT11xx pllv3 variant
The i.MXRT11 series has two new pll types but are variants of existing.
This patch adds the ability to read one of the pll types' frequency
as it can't be changed unlike the generic pll it also has the
division factors swapped.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Change BM_PLL_POWER and BM_PLL_LOCK bit to variable
* Use different lock and power bit for new pll
V2 -> V3:
* Nothing done
---
drivers/clk/imx/clk-pllv3.c | 56 +++--
drivers/clk/imx/clk.h | 1 +
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 077757efcb..fad306aeed 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -21,19 +21,23 @@
#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
+#define UBOOT_DM_CLK_IMX_PLLV3_GENV2 "imx_clk_pllv3_genericv2"
#define PLL_NUM_OFFSET 0x10
#define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12)
+#define BM_PLL_POWER_V2(0x1 << 21)
#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_LOCK(0x1 << 31)
+#define BM_PLL_LOCK_V2 (0x1 << 29)
struct clk_pllv3 {
struct clk clk;
void __iomem*base;
u32 power_bit;
boolpowerup_set;
+ u32 lock_bit;
u32 enable_bit;
u32 div_mask;
u32 div_shift;
@@ -42,6 +46,30 @@ struct clk_pllv3 {
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
+static ulong clk_pllv3_genericv2_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+
+ return (div == 0) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static ulong clk_pllv3_genericv2_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+ u32 val = (div == 0) ? parent_rate * 22 : parent_rate * 20;
+
+ if (rate == val)
+ return 0;
+
+ return -EINVAL;
+}
+
static ulong clk_pllv3_generic_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
@@ -71,7 +99,7 @@ static ulong clk_pllv3_generic_set_rate(struct clk *clk,
ulong rate)
writel(val, pll->base);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -120,6 +148,13 @@ static const struct clk_ops clk_pllv3_generic_ops = {
.set_rate = clk_pllv3_generic_set_rate,
};
+static const struct clk_ops clk_pllv3_genericv2_ops = {
+ .get_rate = clk_pllv3_genericv2_get_rate,
+ .enable = clk_pllv3_generic_enable,
+ .disable= clk_pllv3_generic_disable,
+ .set_rate = clk_pllv3_genericv2_set_rate,
+};
+
static ulong clk_pllv3_sys_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(clk);
@@ -153,7 +188,7 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong
rate)
writel(val, pll->base);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -221,7 +256,7 @@ static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong
rate)
writel(mfd, pll->base + PLL_DENOM_OFFSET);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -262,6 +297,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->power_bit = BM_PLL_POWER;
pll->enable_bit = BM_PLL_ENABLE;
+ pll->lock_bit = BM_PLL_LOCK;
switch (type) {
case IMX_PLLV3_GENERIC:
@@ -269,6 +305,13 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->div_shift = 0;
pll->powerup_set = false;
break;
+ case IMX_PLLV3_GENERICV2:
+ pll->power_bit = BM_PLL_POWER_V2;
+ pll->lock_bit = BM_PLL_LOCK_V2;
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENV2;
+ pll->div_shift = 0;
+ pll->powerup_set = false;
+ b
[PATCH v3 3/8] dt-bindings: imx: Add clock binding for i.MXRT1170
Add the clock binding doc for i.MXRT1170. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done V2 -> V3: * Nothing done --- include/dt-bindings/clock/imxrt1170-clock.h | 48 + 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h diff --git a/include/dt-bindings/clock/imxrt1170-clock.h b/include/dt-bindings/clock/imxrt1170-clock.h new file mode 100644 index 00..8ab8018a15 --- /dev/null +++ b/include/dt-bindings/clock/imxrt1170-clock.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + */ + +#ifndef __DT_BINDINGS_CLOCK_IMXRT1170_H +#define __DT_BINDINGS_CLOCK_IMXRT1170_H + +#define IMXRT1170_CLK_DUMMY0 +#define IMXRT1170_CLK_OSC 1 +#define IMXRT1170_CLK_OSC_32K 2 +#define IMXRT1170_CLK_RCOSC_16M3 +#define IMXRT1170_CLK_RCOSC_48M4 +#define IMXRT1170_CLK_RCOSC_48M_DIV2 5 +#define IMXRT1170_CLK_RCOSC_400M 6 +#define IMXRT1170_CLK_PLL_ARM 7 +#define IMXRT1170_CLK_PLL_AUDIO8 +#define IMXRT1170_CLK_PLL_VIDEO9 +#define IMXRT1170_CLK_PLL1 10 +#define IMXRT1170_CLK_PLL1_DIV211 +#define IMXRT1170_CLK_PLL1_DIV512 +#define IMXRT1170_CLK_PLL2 13 +#define IMXRT1170_CLK_PLL2_PFD014 +#define IMXRT1170_CLK_PLL2_PFD115 +#define IMXRT1170_CLK_PLL2_PFD216 +#define IMXRT1170_CLK_PLL2_PFD317 +#define IMXRT1170_CLK_PLL3 18 +#define IMXRT1170_CLK_PLL3_DIV219 +#define IMXRT1170_CLK_PLL3_PFD020 +#define IMXRT1170_CLK_PLL3_PFD121 +#define IMXRT1170_CLK_PLL3_PFD222 +#define IMXRT1170_CLK_PLL3_PFD323 +#define IMXRT1170_CLK_M7 24 +#define IMXRT1170_CLK_M4 25 +#define IMXRT1170_CLK_BUS 26 +#define IMXRT1170_CLK_BUS_LPSR 27 +#define IMXRT1170_CLK_LPUART1_SEL 28 +#define IMXRT1170_CLK_LPUART1 29 +#define IMXRT1170_CLK_USDHC1_SEL 30 +#define IMXRT1170_CLK_USDHC1 31 +#define IMXRT1170_CLK_GPT1_SEL 32 +#define IMXRT1170_CLK_GPT1 33 +#define IMXRT1170_CLK_SEMC_SEL 34 +#define IMXRT1170_CLK_SEMC 35 +#define IMXRT1170_CLK_END 36 + +#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */ -- 2.36.1
[PATCH v3 2/8] ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header
Add binding header for i.MXRT1170 pinctrl device tree. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done V2 -> V3: * Nothing done --- arch/arm/dts/imxrt1170-pinfunc.h | 1561 ++ 1 file changed, 1561 insertions(+) create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h diff --git a/arch/arm/dts/imxrt1170-pinfunc.h b/arch/arm/dts/imxrt1170-pinfunc.h new file mode 100644 index 00..fba5483a08 --- /dev/null +++ b/arch/arm/dts/imxrt1170-pinfunc.h @@ -0,0 +1,1561 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * Author(s): Jesse Taube + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H + +#define IMX_PAD_SION 0x4000 + +/* + * The pin function ID is a tuple of + * + */ + +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX0x000 0x040 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_00_MIC_CLK0x000 0x040 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO000x000 0x040 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX0x004 0x044 0x080 0x0 0x0 +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO010x004 0x044 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO020x008 0x048 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE000x008 0x048 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE010x00C 0x04C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS00x00C 0x04C 0x094 0x1 0x0 +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO030x00C 0x04C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT0x010 0x050 0x0A0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO040x010 0x050 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO050x014 0x054 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 +#define IOMUXC_GPIO_LPSR_06_LPSPI
[PATCH v3 1/8] imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK
This commit adds board support for i.MXRT1170-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT117x processor family. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done V2 -> V3: * Rebase --- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/mach-imx/imxrt/Kconfig | 9 +++ arch/arm/mach-imx/imxrt/soc.c | 2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS | 7 ++ board/freescale/imxrt1170-evk/Makefile| 6 ++ board/freescale/imxrt1170-evk/imximage.cfg| 31 +++ board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 +++ 8 files changed, 158 insertions(+) create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 4f63803765..09767be1ca 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -56,6 +56,7 @@ #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ +#define MXC_CPU_IMXRT1170 0xBA /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index 8c89133965..c1d6b09e77 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -12,6 +12,10 @@ config IMXRT1050 bool select IMXRT +config IMXRT1170 + bool + select IMXRT + config SYS_SOC default "imxrt" @@ -27,9 +31,14 @@ config TARGET_IMXRT1050_EVK bool "Support imxrt1050 EVK board" select IMXRT1050 +config TARGET_IMXRT1170_EVK + bool "Support imxrt1170 EVK board" + select IMXRT1170 + endchoice source "board/freescale/imxrt1020-evk/Kconfig" source "board/freescale/imxrt1050-evk/Kconfig" +source "board/freescale/imxrt1170-evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index ba015992ee..34162a3976 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -43,6 +43,8 @@ u32 get_cpu_rev(void) return MXC_CPU_IMXRT1020 << 12; #elif defined(CONFIG_IMXRT1050) return MXC_CPU_IMXRT1050 << 12; +#elif defined(CONFIG_IMXRT1170) + return MXC_CPU_IMXRT1170 << 12; #else #error This IMXRT SoC is not supported #endif diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig new file mode 100644 index 00..c61fc57971 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Kconfig @@ -0,0 +1,22 @@ +if TARGET_IMXRT1170_EVK + +config SYS_BOARD + string + default "imxrt1170-evk" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "imxrt1170" + +config SYS_CONFIG_NAME + string + default "imxrt1170-evk" + +config IMX_CONFIG + default "board/freescale/imxrt1170-evk/imximage.cfg" + +endif diff --git a/board/freescale/imxrt1170-evk/MAINTAINERS b/board/freescale/imxrt1170-evk/MAINTAINERS new file mode 100644 index 00..1fc3179c00 --- /dev/null +++ b/board/freescale/imxrt1170-evk/MAINTAINERS @@ -0,0 +1,7 @@ +IMXRT1170 EVALUATION KIT +M: Giulio Benetti +M: Jesse Taube +S: Maintained +F: board/freescale/imxrt1170-evk +F: include/configs/imxrt1170-evk.h +F: configs/imxrt1170-evk_defconfig diff --git a/board/freescale/imxrt1170-evk/Makefile b/board/freescale/imxrt1170-evk/Makefile new file mode 100644 index 00..857a168b09 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# Author(s): Giulio Benetti + +obj-y := imxrt1170-evk.o diff --git a/board/freescale/imxrt1170-evk/imximage.cfg b/board/freescale/imxrt1170-evk/imximage.cfg new file mode 100644 index 00..57583d04ce --- /dev/null +++ b/board/freescale/imxrt1170-evk/imximage.cfg @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register +
[PATCH v3 0/8] Add support for the i.MXRT1170
This patchset contains: - i.MXRT1170 clock driver adaption - i.MXRT1170-evk basic support Jesse Taube (8): imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header dt-bindings: imx: Add clock binding for i.MXRT1170 clk: imx: Add i.MXRT11xx pllv3 variant clk: imx: Add initial support for i.MXRT1170 clock driver RAM: Add changes for i.MXRT11xx series ARM: dts: imx: add i.MXRT1170-EVK support ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig arch/arm/dts/Makefile |3 +- arch/arm/dts/imxrt1170-evk-u-boot.dtsi| 94 + arch/arm/dts/imxrt1170-evk.dts| 250 +++ arch/arm/dts/imxrt1170-pinfunc.h | 1561 + arch/arm/dts/imxrt1170.dtsi | 257 +++ arch/arm/include/asm/arch-imx/cpu.h |1 + arch/arm/mach-imx/imxrt/Kconfig |9 + arch/arm/mach-imx/imxrt/soc.c |2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS |7 + board/freescale/imxrt1170-evk/Makefile|6 + board/freescale/imxrt1170-evk/imximage.cfg| 31 + board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 + configs/imxrt1170-evk_defconfig | 70 + drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile |1 + drivers/clk/imx/clk-imxrt1170.c | 221 +++ drivers/clk/imx/clk-pllv3.c | 56 +- drivers/clk/imx/clk.h |1 + drivers/ram/imxrt_sdram.c |9 + include/configs/imxrt1170-evk.h | 29 + include/dt-bindings/clock/imxrt1170-clock.h | 48 + include/dt-bindings/memory/imxrt-sdram.h |1 + 23 files changed, 2771 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h create mode 100644 arch/arm/dts/imxrt1170.dtsi create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1170.c create mode 100644 include/configs/imxrt1170-evk.h create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h -- 2.36.1
Re: [PATCH v2 0/8] Add support for the i.MXRT1170
On 7/25/22 09:34, Stefano Babic wrote: Hi Jesse, I get errors as soon as I merge the series: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/471284 In fact, you add new CONFIG_ but not via Kbuild: CONFIG_SPL_STACK CONFIG_SYS_FSL_ERRATUM_ESDHC13 I'm sorry I need to rebase. Thanks, Jesse Check this job, too: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/471287 Best regards, Stefano On 17.06.22 18:42, Jesse Taube wrote: This patchset contains: - i.MXRT1170 clock driver adaption - i.MXRT1170-evk basic support Jesse Taube (8): imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header dt-bindings: imx: Add clock binding for i.MXRT1170 clk: imx: Add i.MXRT11xx pllv3 variant clk: imx: Add initial support for i.MXRT1170 clock driver RAM: Add changes for i.MXRT11xx series ARM: dts: imx: add i.MXRT1170-EVK support ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig arch/arm/dts/Makefile |3 +- arch/arm/dts/imxrt1170-evk-u-boot.dtsi| 94 + arch/arm/dts/imxrt1170-evk.dts| 250 +++ arch/arm/dts/imxrt1170-pinfunc.h | 1561 + arch/arm/dts/imxrt1170.dtsi | 257 +++ arch/arm/include/asm/arch-imx/cpu.h |1 + arch/arm/mach-imx/imxrt/Kconfig |9 + arch/arm/mach-imx/imxrt/soc.c |2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS |7 + board/freescale/imxrt1170-evk/Makefile|6 + board/freescale/imxrt1170-evk/imximage.cfg| 32 + board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 + configs/imxrt1170-evk_defconfig | 67 + drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile |1 + drivers/clk/imx/clk-imxrt1170.c | 221 +++ drivers/clk/imx/clk-pllv3.c | 56 +- drivers/clk/imx/clk.h |1 + drivers/ram/imxrt_sdram.c |9 + include/configs/imxrt1170-evk.h | 37 + include/dt-bindings/clock/imxrt1170-clock.h | 48 + include/dt-bindings/memory/imxrt-sdram.h |1 + 23 files changed, 2777 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h create mode 100644 arch/arm/dts/imxrt1170.dtsi create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1170.c create mode 100644 include/configs/imxrt1170-evk.h create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h
Re: [PATCH v1] arm: relocate: Replace ADR instruction with non-pseudo-instruction
On 7/11/22 10:19, Andre Przywara wrote: > On Mon, 11 Jul 2022 15:11:13 +0100 > Andre Przywara wrote: > >> On Mon, 11 Jul 2022 13:57:40 +0100 >> Andre Przywara wrote: >> >> Hi, >> >>> On Sun, 10 Jul 2022 03:09:53 -0400 >>> Jesse Taube wrote: >>> >>> Hi Jesse, >>> >>>> In Binutils 2.37 the ADR instruction has changed >>>> use alternate instructions. >>> >>> Can you elaborate on this? What has changed exactly, and why? Looking at >>> the commit you mention below I don't see an immediate problem that would >>> require code changes? Also it speaks of forward references, but this one >>> is not one? >>> And I didn't spot any difference between 2.38 and 2.35, at least not in my >>> isolated test (but I didn't bother to compile a whole stage 1 GCC with >>> newer binutils yet). >> >> OK, so digging a bit deeper I think I have an idea: >> With as 2.35 I get: >> 080007cc : >> 80007cc: f2af 0304 subwr3, pc, #4 >> >> whereas with 2.38 it's: >> 080007cc : >> 80007cc: f2af 0303 subwr3, pc, #3 >> >> the latter looks correct since we compile relocate.S with -mthumb >> -mthumb-interwork, so the lowest bit of the *function* address should be >> set, to indicate this is a Thumb function. And "ENTRY(relocate_code)" >> clearly tells the assembler that relocate_code is a function entry point, >> so should carry the instruction set flag in bit 0. >> However we don't use the result of "adr" as an argument for a bx call >> later, but to calculate some relocation offset, so the bit is getting in >> the way. >> Without thinking too much about this, wouldn't it help to just always >> clear bit 0 in r3? >> Or probably better: to have an additional label, which is not marked as a >> function entry point? > > Does that fix it? > > diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S > index 14b7f61c1a..5102bfabde 100644 > --- a/arch/arm/lib/relocate.S > +++ b/arch/arm/lib/relocate.S > @@ -78,7 +78,8 @@ ENDPROC(relocate_vectors) > */ > > ENTRY(relocate_code) > - adr r3, relocate_code > +relocate_base: > + adr r3, relocate_base > ldr r1, _image_copy_start_ofs > add r1, r3 /* r1 <- Run &__image_copy_start */ > subsr4, r0, r1 /* r4 <- Run to copy offset */ > > Seems to generate the same code with both gas 2.35 and gas 2.38. Works thanks. Do you want to submit it or. Sorry about me not knowing Assembly for arm very well... Thanks, Jesse > Cheers, > Andre > >> >> Cheers, >> Andre >> >>>> The change causes armv7-m to not boot. >>> >>> What does "causes armv7-m to not boot" mean? It compiles fine, but hangs >>> or crashes? >>> Can you show the relevant disassembly from both binutils versions? >>> >>> And from trying to reproduce this minimally, do we need a ".syntax unified" >>> in the .S file? >>> >>>> Signed-off-by: Jesse Taube >>>> --- >>>> arch/arm/lib/relocate.S | 8 +++- >>>> 1 file changed, 7 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S >>>> index 14b7f61c1a..22c419534f 100644 >>>> --- a/arch/arm/lib/relocate.S >>>> +++ b/arch/arm/lib/relocate.S >>>> @@ -78,7 +78,13 @@ ENDPROC(relocate_vectors) >>>> */ >>>> >>>> ENTRY(relocate_code) >>>> - adr r3, relocate_code >>>> +/* >>>> + * Binutils doesn't comply with the arm docs for adr in thumb2 >>>> + * from commit d3e52e120b68bf19552743fbc078e0a759f48cb7 onward >>>> + * to remove ambiguity explicitly define the pseudo-instruction >>>> + */ >>>> + mov r3, pc >>>> + subs r3, #4 >>> >>> But this will break ARM, won't it? Because it would require to subtract #8? >>> I mean there is a reason for this adr instruction, because this offset >>> calculation is best left to the assembler. Not to speak of the fragility >>> of assuming that the relocate_code label is pointing to the very first >>> instruction. The ENTRY macro could also insert instructions. >>> >>> Cheers, >>> Andre >>> >>>>ldr r1, _image_copy_start_ofs >>>>add r1, r3 /* r1 <- Run &__image_copy_start */ >>>>subsr4, r0, r1 /* r4 <- Run to copy offset */ >>> >> >
Re: [PATCH v1] arm: relocate: Replace ADR instruction with non-pseudo-instruction
On 7/11/22 08:57, Andre Przywara wrote: > On Sun, 10 Jul 2022 03:09:53 -0400 > Jesse Taube wrote: > > Hi Jesse, > >> In Binutils 2.37 the ADR instruction has changed >> use alternate instructions. > > Can you elaborate on this? What has changed exactly, and why? Looking at > the commit you mention below I don't see an immediate problem that would > require code changes? Also it speaks of forward references, but this one > is not one? > And I didn't spot any difference between 2.38 and 2.35, at least not in my > isolated test (but I didn't bother to compile a whole stage 1 GCC with > newer binutils yet). > >> The change causes armv7-m to not boot. > > What does "causes armv7-m to not boot" mean? It compiles fine, but hangs > or crashes? well when we reallocate it doesn't copy the whole instruction so its an invalid instruction and boot loops. > Can you show the relevant disassembly from both binutils versions? > > And from trying to reproduce this minimally, do we need a ".syntax unified" > in the .S file? Yes its required. sorry i didn't post the test code here... The test code is as follows ``` .syntax unified .global bug; .align 4 bug: adr r3, bug .size bug, .-bug .type bug 2; // This changes offset from 4 to 3 in include/linux/linkage.h:ENDPROC //arm-linux-gnueabi-as -march=armv7-m -c -o bug.o bug.S && arm-linux-gnueabi-objdump --disassemble=bug bug.o ``` > >> Signed-off-by: Jesse Taube >> --- >> arch/arm/lib/relocate.S | 8 +++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S >> index 14b7f61c1a..22c419534f 100644 >> --- a/arch/arm/lib/relocate.S >> +++ b/arch/arm/lib/relocate.S >> @@ -78,7 +78,13 @@ ENDPROC(relocate_vectors) >> */ >> >> ENTRY(relocate_code) >> -adr r3, relocate_code >> +/* >> + * Binutils doesn't comply with the arm docs for adr in thumb2 >> + * from commit d3e52e120b68bf19552743fbc078e0a759f48cb7 onward >> + * to remove ambiguity explicitly define the pseudo-instruction >> + */ >> +mov r3, pc >> +subs r3, #4 > > But this will break ARM, won't it? Because it would require to subtract #8? > I mean there is a reason for this adr instruction, because this offset > calculation is best left to the assembler. Not to speak of the fragility > of assuming that the relocate_code label is pointing to the very first > instruction. The ENTRY macro could also insert instructions. > > Cheers, > Andre > >> ldr r1, _image_copy_start_ofs >> add r1, r3 /* r1 <- Run &__image_copy_start */ >> subsr4, r0, r1 /* r4 <- Run to copy offset */ >
[PATCH v1] arm: relocate: Replace ADR instruction with non-pseudo-instruction
In Binutils 2.37 the ADR instruction has changed use alternate instructions. The change causes armv7-m to not boot. Signed-off-by: Jesse Taube --- arch/arm/lib/relocate.S | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 14b7f61c1a..22c419534f 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -78,7 +78,13 @@ ENDPROC(relocate_vectors) */ ENTRY(relocate_code) - adr r3, relocate_code +/* + * Binutils doesn't comply with the arm docs for adr in thumb2 + * from commit d3e52e120b68bf19552743fbc078e0a759f48cb7 onward + * to remove ambiguity explicitly define the pseudo-instruction + */ + mov r3, pc + subs r3, #4 ldr r1, _image_copy_start_ofs add r1, r3 /* r1 <- Run &__image_copy_start */ subsr4, r0, r1 /* r4 <- Run to copy offset */ -- 2.36.1
Re: [ANN] U-Boot v2022.01-rc3 released
On 7/6/22 10:47, Tom Rini wrote: On Wed, Jul 06, 2022 at 10:31:41AM -0400, Jesse Taube wrote: On 11/30/21 14:36, Tom Rini wrote: On Mon, Nov 29, 2021 at 09:35:52PM -0500, Jesse Taube wrote: On 11/29/21 11:28, Tom Rini wrote: Hey all, It's been two weeks since v2022.01-rc2, so here's -rc3. To repeat what I said with -rc2, we've enabled issue tracking on our gitlab instance. You can sign up and then be able to file issues at: https://source.denx.de/groups/u-boot/-/issues This is intended for everyone to be able to use, both custodians for their own needs (you can see for example Heinrich has filed something for UEFI and LMB) as well as users to just report bugs so they don't feel like they're lost in the mailing list. As noted with the last release, the -next branch is open and I'll sync in -rc3 shortly. Please feel free to get a PR ready now if you're able. In terms of a changelog, git log --merges v2022.01-rc2..v2022.01-rc3 contains what I've pulled but as always, better PR messages and tags will provide better results here. So we're now looking at regular releases every other Monday, and with final release on January 10th, 2022. Thanks all! Hey tom, Thank you for the update as always! I have a question about a recent commit, I hope its okay to ask here. In commit cd82f199852d88218e1f17f5ec07cdd9112a89c4 In arch/arm/lib/relocate.S:81 on my SBC it returns an invalid value. My soc is Thumb2 but the instruction `adr r3, relocate_code` assembles to `subw r3, pc, #3` which is not 32bit aligned. If i change the instruction to `adr.w r3, relocate_code` it evaluates to `subw r3, pc, #4`, which is. There is a slight problem as it seems to work fine on my laptop using Debian bullseye, but on my Desktop where I found this I'm running sid. They are both gcc-10. I have yet to find a way to consistently replicate it. What are your thoughts of this? It sounds like you have enough details here to file a bug with Debian and see where that leads. Sorry for replying to old messages but the bug has appeared again in a separate case the bug seems to be introduced in https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=d3e52e120b68bf19552743fbc078e0a759f48cb7 The test code is as follows ``` .syntax unified .global bug; .align 4 bug: adr r3, bug .size bug, .-bug .type bug 2; // This changes offset from 4 to 3 in include/linux/linkage.h:ENDPROC //arm-linux-gnueabi-as -march=armv7-m -c -o bug.o bug.S && arm-linux-gnueabi-objdump --disassemble=bug bug.o ``` Releases >2.37 have this issue and causes some arm platforms in u-boot at /arch/arm/lib/relocate.S:81 adr r3, relocate_code I'm wondering if there should be a mitigation for this till binutils is patched. Thanks for being persistent on this. What would a mitigation look like? Other people have suggested to use `subw r3, pc, #4` and ifdef for different variants. We could also do `adr.w`, what do you recommend. Unfortunately I'm not very familiar with arm asm so I was just putting it out there because many here know more. I'll continue to look into fixes for u-boot. And look into fixes for binutils as 2.37 is now in buildroot and other tool and distros. I'm not sure if line 81 is the only one that is affected but if it is then its a much easier fix than every adr instruction. Thanks, Jesse
Re: [ANN] U-Boot v2022.01-rc3 released
On 11/30/21 14:36, Tom Rini wrote: On Mon, Nov 29, 2021 at 09:35:52PM -0500, Jesse Taube wrote: On 11/29/21 11:28, Tom Rini wrote: Hey all, It's been two weeks since v2022.01-rc2, so here's -rc3. To repeat what I said with -rc2, we've enabled issue tracking on our gitlab instance. You can sign up and then be able to file issues at: https://source.denx.de/groups/u-boot/-/issues This is intended for everyone to be able to use, both custodians for their own needs (you can see for example Heinrich has filed something for UEFI and LMB) as well as users to just report bugs so they don't feel like they're lost in the mailing list. As noted with the last release, the -next branch is open and I'll sync in -rc3 shortly. Please feel free to get a PR ready now if you're able. In terms of a changelog, git log --merges v2022.01-rc2..v2022.01-rc3 contains what I've pulled but as always, better PR messages and tags will provide better results here. So we're now looking at regular releases every other Monday, and with final release on January 10th, 2022. Thanks all! Hey tom, Thank you for the update as always! I have a question about a recent commit, I hope its okay to ask here. In commit cd82f199852d88218e1f17f5ec07cdd9112a89c4 In arch/arm/lib/relocate.S:81 on my SBC it returns an invalid value. My soc is Thumb2 but the instruction `adr r3, relocate_code` assembles to `subw r3, pc, #3` which is not 32bit aligned. If i change the instruction to `adr.w r3, relocate_code` it evaluates to `subw r3, pc, #4`, which is. There is a slight problem as it seems to work fine on my laptop using Debian bullseye, but on my Desktop where I found this I'm running sid. They are both gcc-10. I have yet to find a way to consistently replicate it. What are your thoughts of this? It sounds like you have enough details here to file a bug with Debian and see where that leads. Sorry for replying to old messages but the bug has appeared again in a separate case the bug seems to be introduced in https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=d3e52e120b68bf19552743fbc078e0a759f48cb7 The test code is as follows ``` .syntax unified .global bug; .align 4 bug: adr r3, bug .size bug, .-bug .type bug 2; // This changes offset from 4 to 3 in include/linux/linkage.h:ENDPROC //arm-linux-gnueabi-as -march=armv7-m -c -o bug.o bug.S && arm-linux-gnueabi-objdump --disassemble=bug bug.o ``` Releases >2.37 have this issue and causes some arm platforms in u-boot at /arch/arm/lib/relocate.S:81 adr r3, relocate_code I'm wondering if there should be a mitigation for this till binutils is patched. Thanks, Jesse
Re: [PATCH 2/7] spi: sunxi: refactor SPI speed/mode programming
On 6/27/22 20:31, Andre Przywara wrote:
On Tue, 3 May 2022 22:20:35 +0100
Andre Przywara wrote:
Hi,
As George rightfully pointed out [1], the spi-sunxi driver programs the
speed and mode settings only when the respective functions are called,
but this gets lost over a call to release_bus(). That asserts the
reset line, thus forces each SPI register back to its default value.
Adding to that, trying to program SPI_CCR and SPI_TCR might be pointless
in the first place, when the reset line is still asserted (before
claim_bus()), so those setting won't apply most of the time. In reality
I see two nested claim_bus() calls for the first use, so settings between
the two would work (for instance for the initial "sf probe"). However
later on the speed setting is not programmed into the hardware anymore.
So this issue was addressed with patches by both George (earlier, in a
different way) and Qianfan (later, in a very similar way).
Can someone (Jagan?) please have a look at this change from the U-Boot
SPI perspective? And also the other changes in this series?
I pushed them to the sunxi/next branch:
https://source.denx.de/u-boot/custodians/u-boot-sunxi/-/commits/next/
Tested-by: Jesse Taube
I talked to Icenowy who also tested and said it worked with spi-nand.
There is one issue but not related to this set, the SPI max clock is 1Mhz.
Another note disabling the clock gates in `sun4i_spi_set_clock` will
stop you from dumping the memory of the peripheral.
It would also be nice if i was kept in CC for other SUNIV patches.
Thanks,
Jesse
So can people please test this and report whether this now works as
expected?
Thanks,
Andre
So far we get away with that default frequency, because that is a rather
tame 24 MHz, which most SPI flash chips can handle just fine.
Move the actual register programming into a separate function, and use
.set_speed and .set_mode just to set the variables in our priv structure.
Then we only call this new function in claim_bus(), when we are sure
that register accesses actually work and are preserved.
[1] https://lore.kernel.org/u-boot/20210725231636.879913-17...@yifangu.com/
Signed-off-by: Andre Przywara
Reported-by: George Hilliard
---
drivers/spi/spi-sunxi.c | 95 ++---
1 file changed, 52 insertions(+), 43 deletions(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index b6cd7ddafad..d6b2dd09514 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -221,6 +221,56 @@ err_ahb:
return ret;
}
+static void sun4i_spi_set_speed_mode(struct udevice *dev)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(dev);
+ unsigned int div;
+ u32 reg;
+
+ /*
+* Setup clock divider.
+*
+* We have two choices there. Either we can use the clock
+* divide rate 1, which is calculated thanks to this formula:
+* SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
+* Or we can use CDR2, which is calculated with the formula:
+* SPI_CLK = MOD_CLK / (2 * (cdr + 1))
+* Whether we use the former or the latter is set through the
+* DRS bit.
+*
+* First try CDR2, and if we can't reach the expected
+* frequency, fall back to CDR1.
+*/
+
+ div = SUN4I_SPI_MAX_RATE / (2 * priv->freq);
+ reg = readl(SPI_REG(priv, SPI_CCR));
+
+ if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
+ if (div > 0)
+ div--;
+
+ reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
+ } else {
+ div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(priv->freq);
+ reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR1(div);
+ }
+
+ writel(reg, SPI_REG(priv, SPI_CCR));
+
+ reg = readl(SPI_REG(priv, SPI_TCR));
+ reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
+
+ if (priv->mode & SPI_CPOL)
+ reg |= SPI_BIT(priv, SPI_TCR_CPOL);
+
+ if (priv->mode & SPI_CPHA)
+ reg |= SPI_BIT(priv, SPI_TCR_CPHA);
+
+ writel(reg, SPI_REG(priv, SPI_TCR));
+}
+
static int sun4i_spi_claim_bus(struct udevice *dev)
{
struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
@@ -240,6 +290,8 @@ static int sun4i_spi_claim_bus(struct udevice *dev)
setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
+ sun4i_spi_set_speed_mode(dev->parent);
+
return 0;
}
@@ -329,46 +381,14 @@ static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
{
struct sun4i_spi_plat *plat = dev_get_plat(dev);
struct sun4i_spi_priv *priv = dev_get_priv(dev);
- unsigned int div;
-
Re: [PATCH 2/7] spi: sunxi: refactor SPI speed/mode programming
On 6/27/22 20:31, Andre Przywara wrote:
On Tue, 3 May 2022 22:20:35 +0100
Andre Przywara wrote:
Hi,
As George rightfully pointed out [1], the spi-sunxi driver programs the
speed and mode settings only when the respective functions are called,
but this gets lost over a call to release_bus(). That asserts the
reset line, thus forces each SPI register back to its default value.
Adding to that, trying to program SPI_CCR and SPI_TCR might be pointless
in the first place, when the reset line is still asserted (before
claim_bus()), so those setting won't apply most of the time. In reality
I see two nested claim_bus() calls for the first use, so settings between
the two would work (for instance for the initial "sf probe"). However
later on the speed setting is not programmed into the hardware anymore.
So this issue was addressed with patches by both George (earlier, in a
different way) and Qianfan (later, in a very similar way).
Can someone (Jagan?) please have a look at this change from the U-Boot
SPI perspective? And also the other changes in this series?
I pushed them to the sunxi/next branch:
https://source.denx.de/u-boot/custodians/u-boot-sunxi/-/commits/next/
So can people please test this and report whether this now works as
expected?
I'm very confused I have forgotten much about this patch set.
I'm going to test it, but why has it only been merged now?
Thanks,
Jesse
Thanks,
Andre
So far we get away with that default frequency, because that is a rather
tame 24 MHz, which most SPI flash chips can handle just fine.
Move the actual register programming into a separate function, and use
.set_speed and .set_mode just to set the variables in our priv structure.
Then we only call this new function in claim_bus(), when we are sure
that register accesses actually work and are preserved.
[1] https://lore.kernel.org/u-boot/20210725231636.879913-17...@yifangu.com/
Signed-off-by: Andre Przywara
Reported-by: George Hilliard
---
drivers/spi/spi-sunxi.c | 95 ++---
1 file changed, 52 insertions(+), 43 deletions(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index b6cd7ddafad..d6b2dd09514 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -221,6 +221,56 @@ err_ahb:
return ret;
}
+static void sun4i_spi_set_speed_mode(struct udevice *dev)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(dev);
+ unsigned int div;
+ u32 reg;
+
+ /*
+* Setup clock divider.
+*
+* We have two choices there. Either we can use the clock
+* divide rate 1, which is calculated thanks to this formula:
+* SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
+* Or we can use CDR2, which is calculated with the formula:
+* SPI_CLK = MOD_CLK / (2 * (cdr + 1))
+* Whether we use the former or the latter is set through the
+* DRS bit.
+*
+* First try CDR2, and if we can't reach the expected
+* frequency, fall back to CDR1.
+*/
+
+ div = SUN4I_SPI_MAX_RATE / (2 * priv->freq);
+ reg = readl(SPI_REG(priv, SPI_CCR));
+
+ if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
+ if (div > 0)
+ div--;
+
+ reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
+ } else {
+ div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(priv->freq);
+ reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR1(div);
+ }
+
+ writel(reg, SPI_REG(priv, SPI_CCR));
+
+ reg = readl(SPI_REG(priv, SPI_TCR));
+ reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
+
+ if (priv->mode & SPI_CPOL)
+ reg |= SPI_BIT(priv, SPI_TCR_CPOL);
+
+ if (priv->mode & SPI_CPHA)
+ reg |= SPI_BIT(priv, SPI_TCR_CPHA);
+
+ writel(reg, SPI_REG(priv, SPI_TCR));
+}
+
static int sun4i_spi_claim_bus(struct udevice *dev)
{
struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
@@ -240,6 +290,8 @@ static int sun4i_spi_claim_bus(struct udevice *dev)
setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
+ sun4i_spi_set_speed_mode(dev->parent);
+
return 0;
}
@@ -329,46 +381,14 @@ static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
{
struct sun4i_spi_plat *plat = dev_get_plat(dev);
struct sun4i_spi_priv *priv = dev_get_priv(dev);
- unsigned int div;
- u32 reg;
if (speed > plat->max_hz)
speed = plat->max_hz;
if (speed < SUN4I_SPI_MIN_RATE)
speed = SUN4I_SPI_MIN_RATE;
- /*
-* Setup clock divider.
-*
-* We have two choices there. Either we can use the clock
-* divide rate 1, which is c
[PATCH v2 7/8] ARM: dts: imx: add i.MXRT1170-EVK support
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and Cortex-M4 core.
The EVK provides 64 MB SDRAM, Micro SD card socket,
USB 2.0 OTG.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
SDRAM
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Remove unused constant clocks
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imxrt1170-evk-u-boot.dtsi | 94 +
arch/arm/dts/imxrt1170-evk.dts | 250
arch/arm/dts/imxrt1170.dtsi| 257 +
4 files changed, 603 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/dts/imxrt1170.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0a2713c06a..85d166b292 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -967,7 +967,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
- imxrt1020-evk.dtb
+ imxrt1020-evk.dtb \
+ imxrt1170-evk.dtb \
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
new file mode 100644
index 00..88ff986ba0
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ clocks {
+ u-boot,dm-spl;
+ };
+
+ soc {
+ u-boot,dm-spl;
+ };
+};
+
+&osc {
+ u-boot,dm-spl;
+};
+
+&rcosc16M {
+ u-boot,dm-spl;
+};
+
+&osc32k {
+ u-boot,dm-spl;
+};
+
+&clks {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpt1 {
+ u-boot,dm-spl;
+};
+
+&lpuart1 { /* console */
+ u-boot,dm-spl;
+};
+
+&semc {
+ u-boot,dm-spl;
+
+ bank1: bank@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+
+ imxrt1170-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ u-boot,dm-spl;
+ };
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts
new file mode 100644
index 00..c2fd0c0392
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk.dts
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/dts-v1/;
+#include "imxrt1170.dtsi"
+#include "imxrt1170-evk-u-boot.dtsi"
+#include "imxrt1170-pinfunc.h"
+
+/ {
+ model = "NXP imxrt1170-evk board";
+ compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ tick-timer = &gpt1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x2024 0xf 0x8000 0x400>;
+
+ ocram: ocram@2024 {
+ device_type = "memory";
+ reg = <0x2024 0xf>;
+ };
+
+ sdram: sdram@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x400>;
+ };
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&semc {
+ /*
+* Memory configuration from sdram datasheet IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0xd
+0x0
+0x8
+0x7
+
+0x0d
+0x0b
+0x00
+0x00
+
+0x00
+
[PATCH v2 8/8] ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig
Add a base defconfig for the i.MXRT1170 Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done --- configs/imxrt1170-evk_defconfig | 67 + include/configs/imxrt1170-evk.h | 37 ++ 2 files changed, 104 insertions(+) create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 include/configs/imxrt1170-evk.h diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig new file mode 100644 index 00..a8de8ad18e --- /dev/null +++ b/configs/imxrt1170-evk_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_ARCH_IMXRT=y +CONFIG_SYS_TEXT_BASE=0x2024 +CONFIG_SYS_MALLOC_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x8 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imxrt1170-evk" +CONFIG_SPL_TEXT_BASE=0x202C +CONFIG_TARGET_IMXRT1170_EVK=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SIZE_LIMIT=0x2 +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x202C +CONFIG_SD_BOOT=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 +# CONFIG_SPL_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_MII is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_OF_TRANSLATE is not set +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMXRT1170=y +CONFIG_CLK_IMXRT1170=y +# CONFIG_SPL_DM_GPIO is not set +CONFIG_MXC_GPIO=y +# CONFIG_INPUT is not set +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMXRT=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_IMXRT_SDRAM=y +CONFIG_FSL_LPUART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h new file mode 100644 index 00..4ebeffd255 --- /dev/null +++ b/include/configs/imxrt1170-evk.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#ifndef __IMXRT1170_EVK_H +#define __IMXRT1170_EVK_H + +#include + +#define CONFIG_SYS_INIT_SP_ADDR0x2034 + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC1351 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +#define PHYS_SDRAM 0x8000 +#define PHYS_SDRAM_SIZE(64 * 1024 * 1024) + +#define DMAMEM_SZ_ALL (1 * 1024 * 1024) +#define DMAMEM_BASE(PHYS_SDRAM + PHYS_SDRAM_SIZE - \ +DMAMEM_SZ_ALL) + +/* + * Configuration of the external SDRAM memory + */ + +/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_LEN 0x8000 +#define CONFIG_SYS_UBOOT_START 0x202403FD +#endif +/* For SPL ends */ + +#endif /* __IMXRT1170_EVK_H */ -- 2.36.1
[PATCH v2 2/8] ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header
Add binding header for i.MXRT1170 pinctrl device tree. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done --- arch/arm/dts/imxrt1170-pinfunc.h | 1561 ++ 1 file changed, 1561 insertions(+) create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h diff --git a/arch/arm/dts/imxrt1170-pinfunc.h b/arch/arm/dts/imxrt1170-pinfunc.h new file mode 100644 index 00..fba5483a08 --- /dev/null +++ b/arch/arm/dts/imxrt1170-pinfunc.h @@ -0,0 +1,1561 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * Author(s): Jesse Taube + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H + +#define IMX_PAD_SION 0x4000 + +/* + * The pin function ID is a tuple of + * + */ + +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX0x000 0x040 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_00_MIC_CLK0x000 0x040 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO000x000 0x040 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX0x004 0x044 0x080 0x0 0x0 +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO010x004 0x044 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO020x008 0x048 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE000x008 0x048 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE010x00C 0x04C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS00x00C 0x04C 0x094 0x1 0x0 +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO030x00C 0x04C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT0x010 0x050 0x0A0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO040x010 0x050 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO050x014 0x054 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 +#define IOMUXC_GPIO_LPSR_06_LPSPI6_P
[PATCH v2 6/8] RAM: Add changes for i.MXRT11xx series
The i.MXRT11 series has different offsets for IOCR_MUX, it also can
address 64MiB of SDRAM so add a macro for that.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Nothing done
---
drivers/ram/imxrt_sdram.c| 9 +
include/dt-bindings/memory/imxrt-sdram.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
index ca2eec767d..d0a88845cf 100644
--- a/drivers/ram/imxrt_sdram.c
+++ b/drivers/ram/imxrt_sdram.c
@@ -87,12 +87,21 @@ struct imxrt_semc_regs {
u32 sts[16];
};
+#if !defined(TARGET_IMXRT1170_EVK)
#define SEMC_IOCR_MUX_A8_SHIFT 0
#define SEMC_IOCR_MUX_CSX0_SHIFT 3
#define SEMC_IOCR_MUX_CSX1_SHIFT 6
#define SEMC_IOCR_MUX_CSX2_SHIFT 9
#define SEMC_IOCR_MUX_CSX3_SHIFT 12
#define SEMC_IOCR_MUX_RDY_SHIFT15
+#else
+#define SEMC_IOCR_MUX_A8_SHIFT 0
+#define SEMC_IOCR_MUX_CSX0_SHIFT 4
+#define SEMC_IOCR_MUX_CSX1_SHIFT 8
+#define SEMC_IOCR_MUX_CSX2_SHIFT 12
+#define SEMC_IOCR_MUX_CSX3_SHIFT 16
+#define SEMC_IOCR_MUX_RDY_SHIFT20
+#endif
struct imxrt_sdram_mux {
u8 a8;
diff --git a/include/dt-bindings/memory/imxrt-sdram.h
b/include/dt-bindings/memory/imxrt-sdram.h
index acb35bce27..4b3b0c2f50 100644
--- a/include/dt-bindings/memory/imxrt-sdram.h
+++ b/include/dt-bindings/memory/imxrt-sdram.h
@@ -82,6 +82,7 @@
#define MEM_WIDTH_8BITS0x0
#define MEM_WIDTH_16BITS 0x1
+#define MEM_WIDTH_32BITS 0x2
#define BL_1 0x0
#define BL_2 0x1
--
2.36.1
[PATCH v2 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver
Add clock driver support for i.MXRT1170.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Use C file not dts for constant clock divider
---
drivers/clk/imx/Kconfig | 16 +++
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-imxrt1170.c | 221
3 files changed, 238 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 04d252a1e0..abcb19ce6d 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -124,3 +124,19 @@ config CLK_IMXRT1050
select CLK_COMPOSITE_CCF
help
This enables support clock driver for i.MXRT1050 platforms.
+
+config SPL_CLK_IMXRT1170
+ bool "SPL clock support for i.MXRT1170"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MXRT1170.
+
+config CLK_IMXRT1170
+ bool "Clock support for i.MXRT1170"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1170 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index c5766901f2..b9c197f952 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o
clk-pll14xx.o \
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) += clk-imxrt1170.o
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
new file mode 100644
index 00..077dd1bf02
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static ulong imxrt1170_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1170_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1170_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1170_clk_disable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 0);
+}
+
+static int imxrt1170_clk_enable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 1);
+}
+
+static int imxrt1170_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &cp);
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
+static struct clk_ops imxrt1170_clk_ops = {
+ .set_rate = imxrt1170_clk_set_rate,
+ .get_rate = imxrt1170_clk_get_rate,
+ .enable = imxrt1170_clk_enable,
+ .disable = imxrt1170_clk_disable,
+ .set_parent = imxrt1170_clk_set_parent,
+};
+
+static const char * const lpuart1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3"};
+static const char * const gpt1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3"};
+static const char * const usdhc1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
+static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"};
+
+static int imxrt1170_clk_probe(struct udevice *dev)
+{
+
[PATCH v2 4/8] clk: imx: Add i.MXRT11xx pllv3 variant
The i.MXRT11 series has two new pll types but are variants of existing.
This patch adds the ability to read one of the pll types' frequency
as it can't be changed unlike the generic pll it also has the
division factors swapped.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Change BM_PLL_POWER and BM_PLL_LOCK bit to variable
* Use different lock and power bit for new pll
---
drivers/clk/imx/clk-pllv3.c | 56 +++--
drivers/clk/imx/clk.h | 1 +
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 077757efcb..fad306aeed 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -21,19 +21,23 @@
#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
+#define UBOOT_DM_CLK_IMX_PLLV3_GENV2 "imx_clk_pllv3_genericv2"
#define PLL_NUM_OFFSET 0x10
#define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12)
+#define BM_PLL_POWER_V2(0x1 << 21)
#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_LOCK(0x1 << 31)
+#define BM_PLL_LOCK_V2 (0x1 << 29)
struct clk_pllv3 {
struct clk clk;
void __iomem*base;
u32 power_bit;
boolpowerup_set;
+ u32 lock_bit;
u32 enable_bit;
u32 div_mask;
u32 div_shift;
@@ -42,6 +46,30 @@ struct clk_pllv3 {
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
+static ulong clk_pllv3_genericv2_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+
+ return (div == 0) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static ulong clk_pllv3_genericv2_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+ u32 val = (div == 0) ? parent_rate * 22 : parent_rate * 20;
+
+ if (rate == val)
+ return 0;
+
+ return -EINVAL;
+}
+
static ulong clk_pllv3_generic_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
@@ -71,7 +99,7 @@ static ulong clk_pllv3_generic_set_rate(struct clk *clk,
ulong rate)
writel(val, pll->base);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -120,6 +148,13 @@ static const struct clk_ops clk_pllv3_generic_ops = {
.set_rate = clk_pllv3_generic_set_rate,
};
+static const struct clk_ops clk_pllv3_genericv2_ops = {
+ .get_rate = clk_pllv3_genericv2_get_rate,
+ .enable = clk_pllv3_generic_enable,
+ .disable= clk_pllv3_generic_disable,
+ .set_rate = clk_pllv3_genericv2_set_rate,
+};
+
static ulong clk_pllv3_sys_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(clk);
@@ -153,7 +188,7 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong
rate)
writel(val, pll->base);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -221,7 +256,7 @@ static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong
rate)
writel(mfd, pll->base + PLL_DENOM_OFFSET);
/* Wait for PLL to lock */
- while (!(readl(pll->base) & BM_PLL_LOCK))
+ while (!(readl(pll->base) & pll->lock_bit))
;
return 0;
@@ -262,6 +297,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->power_bit = BM_PLL_POWER;
pll->enable_bit = BM_PLL_ENABLE;
+ pll->lock_bit = BM_PLL_LOCK;
switch (type) {
case IMX_PLLV3_GENERIC:
@@ -269,6 +305,13 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->div_shift = 0;
pll->powerup_set = false;
break;
+ case IMX_PLLV3_GENERICV2:
+ pll->power_bit = BM_PLL_POWER_V2;
+ pll->lock_bit = BM_PLL_LOCK_V2;
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENV2;
+ pll->div_shift = 0;
+ pll->powerup_set = false;
+ break;
case IMX_PL
[PATCH v2 3/8] dt-bindings: imx: Add clock binding for i.MXRT1170
Add the clock binding doc for i.MXRT1170. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done --- include/dt-bindings/clock/imxrt1170-clock.h | 48 + 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h diff --git a/include/dt-bindings/clock/imxrt1170-clock.h b/include/dt-bindings/clock/imxrt1170-clock.h new file mode 100644 index 00..8ab8018a15 --- /dev/null +++ b/include/dt-bindings/clock/imxrt1170-clock.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + */ + +#ifndef __DT_BINDINGS_CLOCK_IMXRT1170_H +#define __DT_BINDINGS_CLOCK_IMXRT1170_H + +#define IMXRT1170_CLK_DUMMY0 +#define IMXRT1170_CLK_OSC 1 +#define IMXRT1170_CLK_OSC_32K 2 +#define IMXRT1170_CLK_RCOSC_16M3 +#define IMXRT1170_CLK_RCOSC_48M4 +#define IMXRT1170_CLK_RCOSC_48M_DIV2 5 +#define IMXRT1170_CLK_RCOSC_400M 6 +#define IMXRT1170_CLK_PLL_ARM 7 +#define IMXRT1170_CLK_PLL_AUDIO8 +#define IMXRT1170_CLK_PLL_VIDEO9 +#define IMXRT1170_CLK_PLL1 10 +#define IMXRT1170_CLK_PLL1_DIV211 +#define IMXRT1170_CLK_PLL1_DIV512 +#define IMXRT1170_CLK_PLL2 13 +#define IMXRT1170_CLK_PLL2_PFD014 +#define IMXRT1170_CLK_PLL2_PFD115 +#define IMXRT1170_CLK_PLL2_PFD216 +#define IMXRT1170_CLK_PLL2_PFD317 +#define IMXRT1170_CLK_PLL3 18 +#define IMXRT1170_CLK_PLL3_DIV219 +#define IMXRT1170_CLK_PLL3_PFD020 +#define IMXRT1170_CLK_PLL3_PFD121 +#define IMXRT1170_CLK_PLL3_PFD222 +#define IMXRT1170_CLK_PLL3_PFD323 +#define IMXRT1170_CLK_M7 24 +#define IMXRT1170_CLK_M4 25 +#define IMXRT1170_CLK_BUS 26 +#define IMXRT1170_CLK_BUS_LPSR 27 +#define IMXRT1170_CLK_LPUART1_SEL 28 +#define IMXRT1170_CLK_LPUART1 29 +#define IMXRT1170_CLK_USDHC1_SEL 30 +#define IMXRT1170_CLK_USDHC1 31 +#define IMXRT1170_CLK_GPT1_SEL 32 +#define IMXRT1170_CLK_GPT1 33 +#define IMXRT1170_CLK_SEMC_SEL 34 +#define IMXRT1170_CLK_SEMC 35 +#define IMXRT1170_CLK_END 36 + +#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */ -- 2.36.1
[PATCH v2 1/8] imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK
This commit adds board support for i.MXRT1170-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT117x processor family. Signed-off-by: Jesse Taube --- V1 -> V2: * Nothing done --- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/mach-imx/imxrt/Kconfig | 9 +++ arch/arm/mach-imx/imxrt/soc.c | 2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS | 7 ++ board/freescale/imxrt1170-evk/Makefile| 6 ++ board/freescale/imxrt1170-evk/imximage.cfg| 32 board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 +++ 8 files changed, 159 insertions(+) create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 4f63803765..09767be1ca 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -56,6 +56,7 @@ #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ +#define MXC_CPU_IMXRT1170 0xBA /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index 8c89133965..c1d6b09e77 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -12,6 +12,10 @@ config IMXRT1050 bool select IMXRT +config IMXRT1170 + bool + select IMXRT + config SYS_SOC default "imxrt" @@ -27,9 +31,14 @@ config TARGET_IMXRT1050_EVK bool "Support imxrt1050 EVK board" select IMXRT1050 +config TARGET_IMXRT1170_EVK + bool "Support imxrt1170 EVK board" + select IMXRT1170 + endchoice source "board/freescale/imxrt1020-evk/Kconfig" source "board/freescale/imxrt1050-evk/Kconfig" +source "board/freescale/imxrt1170-evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index ba015992ee..34162a3976 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -43,6 +43,8 @@ u32 get_cpu_rev(void) return MXC_CPU_IMXRT1020 << 12; #elif defined(CONFIG_IMXRT1050) return MXC_CPU_IMXRT1050 << 12; +#elif defined(CONFIG_IMXRT1170) + return MXC_CPU_IMXRT1170 << 12; #else #error This IMXRT SoC is not supported #endif diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig new file mode 100644 index 00..c61fc57971 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Kconfig @@ -0,0 +1,22 @@ +if TARGET_IMXRT1170_EVK + +config SYS_BOARD + string + default "imxrt1170-evk" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "imxrt1170" + +config SYS_CONFIG_NAME + string + default "imxrt1170-evk" + +config IMX_CONFIG + default "board/freescale/imxrt1170-evk/imximage.cfg" + +endif diff --git a/board/freescale/imxrt1170-evk/MAINTAINERS b/board/freescale/imxrt1170-evk/MAINTAINERS new file mode 100644 index 00..1fc3179c00 --- /dev/null +++ b/board/freescale/imxrt1170-evk/MAINTAINERS @@ -0,0 +1,7 @@ +IMXRT1170 EVALUATION KIT +M: Giulio Benetti +M: Jesse Taube +S: Maintained +F: board/freescale/imxrt1170-evk +F: include/configs/imxrt1170-evk.h +F: configs/imxrt1170-evk_defconfig diff --git a/board/freescale/imxrt1170-evk/Makefile b/board/freescale/imxrt1170-evk/Makefile new file mode 100644 index 00..857a168b09 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# Author(s): Giulio Benetti + +obj-y := imxrt1170-evk.o diff --git a/board/freescale/imxrt1170-evk/imximage.cfg b/board/freescale/imxrt1170-evk/imximage.cfg new file mode 100644 index 00..3354672825 --- /dev/null +++ b/board/freescale/imxrt1170-evk/imximage.cfg @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + *
[PATCH v2 0/8] Add support for the i.MXRT1170
This patchset contains: - i.MXRT1170 clock driver adaption - i.MXRT1170-evk basic support Jesse Taube (8): imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header dt-bindings: imx: Add clock binding for i.MXRT1170 clk: imx: Add i.MXRT11xx pllv3 variant clk: imx: Add initial support for i.MXRT1170 clock driver RAM: Add changes for i.MXRT11xx series ARM: dts: imx: add i.MXRT1170-EVK support ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig arch/arm/dts/Makefile |3 +- arch/arm/dts/imxrt1170-evk-u-boot.dtsi| 94 + arch/arm/dts/imxrt1170-evk.dts| 250 +++ arch/arm/dts/imxrt1170-pinfunc.h | 1561 + arch/arm/dts/imxrt1170.dtsi | 257 +++ arch/arm/include/asm/arch-imx/cpu.h |1 + arch/arm/mach-imx/imxrt/Kconfig |9 + arch/arm/mach-imx/imxrt/soc.c |2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS |7 + board/freescale/imxrt1170-evk/Makefile|6 + board/freescale/imxrt1170-evk/imximage.cfg| 32 + board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 + configs/imxrt1170-evk_defconfig | 67 + drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile |1 + drivers/clk/imx/clk-imxrt1170.c | 221 +++ drivers/clk/imx/clk-pllv3.c | 56 +- drivers/clk/imx/clk.h |1 + drivers/ram/imxrt_sdram.c |9 + include/configs/imxrt1170-evk.h | 37 + include/dt-bindings/clock/imxrt1170-clock.h | 48 + include/dt-bindings/memory/imxrt-sdram.h |1 + 23 files changed, 2777 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h create mode 100644 arch/arm/dts/imxrt1170.dtsi create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1170.c create mode 100644 include/configs/imxrt1170-evk.h create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h -- 2.36.1
Re: [PATCH 5/7] sunxi: F1C100s: update DT files from Linux
uot;,
+"allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+<&ccu CLK_MMC0>,
+<&ccu CLK_MMC0_OUTPUT>,
+<&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <23>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@1c1 {
+ compatible = "allwinner,suniv-f1c100s-mmc",
+"allwinner,sun7i-a20-mmc";
+ reg = <0x01c1 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+<&ccu CLK_MMC1>,
+<&ccu CLK_MMC1_OUTPUT>,
+<&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <24>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccu: clock@1c2 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c2 0x400>;
@@ -82,13 +153,24 @@
compatible = "allwinner,suniv-f1c100s-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <38>, <39>, <40>;
- clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ };
+
+ spi0_pc_pins: spi0-pc-pins {
+ pins = "PC0", "PC1", "PC2", "PC3";
+ function = "spi0";
+ };
+
uart0_pe_pins: uart0-pe-pins {
pins = "PE0", "PE1";
function = "uart0";
@@ -98,14 +180,16 @@
timer@1c20c00 {
compatible = "allwinner,suniv-f1c100s-timer";
reg = <0x01c20c00 0x90>;
- interrupts = <13>;
+ interrupts = <13>, <14>, <15>;
clocks = <&osc24M>;
};
wdt: watchdog@1c20ca0 {
compatible = "allwinner,suniv-f1c100s-wdt",
-"allwinner,sun4i-a10-wdt";
+"allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
+ interrupts = <16>;
+ clocks = <&osc32k>;
};
uart0: serial@1c25000 {
@@ -114,8 +198,8 @@
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 38>;
- resets = <&ccu 24>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -125,8 +209,8 @@
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 39>;
- resets = <&ccu 25>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -136,8 +220,8 @@
interrupts = <3>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 40>;
- resets = <&ccu 26>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
};
Acked-by: Jesse Taube
Re: [PATCH v1 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver
On 3/20/22 15:17, Sean Anderson wrote:
On 3/17/22 2:32 PM, Jesse Taube wrote:
Add clock driver support for i.MXRT1170.
Signed-off-by: Jesse Taube
---
drivers/clk/imx/Kconfig | 16 +++
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-imxrt1170.c | 215
3 files changed, 232 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 96721bcbf3..ae56603194 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -100,3 +100,19 @@ config CLK_IMXRT1050
select CLK_CCF
help
This enables support clock driver for i.MXRT1050 platforms.
+
+config SPL_CLK_IMXRT1170
+ bool "SPL clock support for i.MXRT1170"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MXRT1170.
+
+config CLK_IMXRT1170
+ bool "Clock support for i.MXRT1170"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1170 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3ae..3ed326739a 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o
clk-pll14xx.o \
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) += clk-imxrt1170.o
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
new file mode 100644
index 00..6ea46b6a52
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static ulong imxrt1170_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
Consider dev_dbg() if you do a v2.
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1170_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1170_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1170_clk_disable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 0);
+}
+
+static int imxrt1170_clk_enable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 1);
+}
+
+static int imxrt1170_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &cp);
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
+static struct clk_ops imxrt1170_clk_ops = {
+ .set_rate = imxrt1170_clk_set_rate,
+ .get_rate = imxrt1170_clk_get_rate,
+ .enable = imxrt1170_clk_enable,
+ .disable = imxrt1170_clk_disable,
+ .set_parent = imxrt1170_clk_set_parent,
+};
+
+static const char * const lpuart1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3"};
+static const char * const gpt1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3"};
+static const char * const usdhc1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
+static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"
[PATCH v2 3/4] ARM: dts: imxrt10..-evk: Linux moved pins-imxrt1020 to dts
The Linux kernel moved dt-bindings/pinctrl/pins-imxrt to the device tree
This patch move it in U-Boot as well.
Signed-off-by: Jesse Taube
---
arch/arm/dts/imxrt1020-evk.dts | 2 +-
.../pins-imxrt1020.h => arch/arm/dts/imxrt1020-pinfunc.h| 0
arch/arm/dts/imxrt1050-evk.dts | 2 +-
.../pins-imxrt1050.h => arch/arm/dts/imxrt1050-pinfunc.h| 0
4 files changed, 2 insertions(+), 2 deletions(-)
rename include/dt-bindings/pinctrl/pins-imxrt1020.h =>
arch/arm/dts/imxrt1020-pinfunc.h (100%)
rename include/dt-bindings/pinctrl/pins-imxrt1050.h =>
arch/arm/dts/imxrt1050-pinfunc.h (100%)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index 2da79e5c20..22ae5ed735 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -7,7 +7,7 @@
/dts-v1/;
#include "imxrt1020.dtsi"
#include "imxrt1020-evk-u-boot.dtsi"
-#include
+#include "imxrt1020-pinfunc.h"
/ {
model = "NXP IMXRT1020-evk board";
diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h
b/arch/arm/dts/imxrt1020-pinfunc.h
similarity index 100%
rename from include/dt-bindings/pinctrl/pins-imxrt1020.h
rename to arch/arm/dts/imxrt1020-pinfunc.h
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 324cf7af96..fb2da3adfc 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -7,7 +7,7 @@
/dts-v1/;
#include "imxrt1050.dtsi"
#include "imxrt1050-evk-u-boot.dtsi"
-#include
+#include "imxrt1050-pinfunc.h"
/ {
model = "NXP IMXRT1050-evk board";
diff --git a/include/dt-bindings/pinctrl/pins-imxrt1050.h
b/arch/arm/dts/imxrt1050-pinfunc.h
similarity index 100%
rename from include/dt-bindings/pinctrl/pins-imxrt1050.h
rename to arch/arm/dts/imxrt1050-pinfunc.h
--
2.34.1
[PATCH v2 2/4] configs/*imxrt10*: SYS_MALLOC_LEN is too large
1M of heap is more than internal ram making booting without SDRAM not possible now it is 256k Signed-off-by: Jesse Taube --- configs/imxrt1020-evk_defconfig | 2 +- configs/imxrt1050-evk_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig index dafa4a505a..362f2e3bb0 100644 --- a/configs/imxrt1020-evk_defconfig +++ b/configs/imxrt1020-evk_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_IMXRT=y CONFIG_SYS_TEXT_BASE=0x80002000 -CONFIG_SYS_MALLOC_LEN=0x10 +CONFIG_SYS_MALLOC_LEN=0x4 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 09dcc9e6e3..aa4faacca0 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -3,7 +3,7 @@ CONFIG_SYS_DCACHE_OFF=y # CONFIG_SPL_SYS_DCACHE_OFF is not set CONFIG_ARCH_IMXRT=y CONFIG_SYS_TEXT_BASE=0x80002000 -CONFIG_SYS_MALLOC_LEN=0x10 +CONFIG_SYS_MALLOC_LEN=0x4 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y -- 2.34.1
[PATCH v2 4/4] board: freescale: imxrt10..-evk: Fix missing include of serial.h
If FALCON mode is enabled we have a missing include in spl_start_uboot. Signed-off-by: Jesse Taube --- board/freescale/imxrt1020-evk/imxrt1020-evk.c | 1 + board/freescale/imxrt1050-evk/imxrt1050-evk.c | 1 + 2 files changed, 2 insertions(+) diff --git a/board/freescale/imxrt1020-evk/imxrt1020-evk.c b/board/freescale/imxrt1020-evk/imxrt1020-evk.c index 54a733b12c..785da604b9 100644 --- a/board/freescale/imxrt1020-evk/imxrt1020-evk.c +++ b/board/freescale/imxrt1020-evk/imxrt1020-evk.c @@ -13,6 +13,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c index 6132916578..4b82ee5e9c 100644 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c @@ -13,6 +13,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -- 2.34.1
[PATCH v2 1/4] clk: imxrt: Use dts for anatop base address
In Linux IMX and IMXRT use the device tree to hold the anatop address.
The anatop is used in clock drivers as it controls the internal PLLs
This will move the macro from asm/arch-imxrt to the device tree.
This presumably should also be done with the other IMX boards as well.
Signed-off-by: Jesse Taube
---
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4
arch/arm/dts/imxrt1020.dtsi| 5 +
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4
arch/arm/dts/imxrt1050.dtsi| 5 +
arch/arm/include/asm/arch-imxrt/imx-regs.h | 2 --
drivers/clk/imx/clk-imxrt1020.c| 2 +-
drivers/clk/imx/clk-imxrt1050.c| 2 +-
7 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 121665a2d2..9e1b074d2e 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -22,6 +22,10 @@
u-boot,dm-spl;
};
+&anatop {
+ u-boot,dm-spl;
+};
+
&clks {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 5ba314f995..13511ebb18 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -67,6 +67,11 @@
fsl,mux_mask = <0x7>;
};
+ anatop: anatop@400d8000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x400d8000 0x4000>;
+ };
+
clks: ccm@400fc000 {
compatible = "fsl,imxrt1020-ccm";
reg = <0x400fc000 0x4000>;
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 3168c2df2c..617cece448 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -22,6 +22,10 @@
u-boot,dm-spl;
};
+&anatop {
+ u-boot,dm-spl;
+};
+
&clks {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 6560a3827f..09f4712af6 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -59,6 +59,11 @@
fsl,mux_mask = <0x7>;
};
+ anatop: anatop@400d8000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x400d8000 0x4000>;
+ };
+
clks: ccm@400fc000 {
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h
b/arch/arm/include/asm/arch-imxrt/imx-regs.h
index d01e6ca2e0..ad739caae9 100644
--- a/arch/arm/include/asm/arch-imxrt/imx-regs.h
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -15,8 +15,6 @@
#define GPIO4_BASE_ADDR0x401C4000
#define GPIO5_BASE_ADDR0x400C
-#define ANATOP_BASE_ADDR 0x400d8000
-
#define MXS_LCDIF_BASE 0x402b8000
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
index 840f783940..14ba6b47c1 100644
--- a/drivers/clk/imx/clk-imxrt1020.c
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -93,7 +93,7 @@ static int imxrt1020_clk_probe(struct udevice *dev)
void *base;
/* Anatop clocks */
- base = (void *)ANATOP_BASE_ADDR;
+ base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
"fsl,imxrt-anatop"));
clk_dm(IMXRT1020_CLK_PLL2_SYS,
imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 3e17161002..514516a3a3 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -117,7 +117,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
void *base;
/* Anatop clocks */
- base = (void *)ANATOP_BASE_ADDR;
+ base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
"fsl,imxrt-anatop"));
clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
--
2.34.1
[PATCH v1 2/8] ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header
Add binding header for i.MXRT1170 pinctrl device tree. Signed-off-by: Jesse Taube --- arch/arm/dts/imxrt1170-pinfunc.h | 1561 ++ 1 file changed, 1561 insertions(+) create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h diff --git a/arch/arm/dts/imxrt1170-pinfunc.h b/arch/arm/dts/imxrt1170-pinfunc.h new file mode 100644 index 00..fba5483a08 --- /dev/null +++ b/arch/arm/dts/imxrt1170-pinfunc.h @@ -0,0 +1,1561 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * Author(s): Jesse Taube + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H + +#define IMX_PAD_SION 0x4000 + +/* + * The pin function ID is a tuple of + * + */ + +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX0x000 0x040 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_00_MIC_CLK0x000 0x040 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO000x000 0x040 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX0x004 0x044 0x080 0x0 0x0 +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO010x004 0x044 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO020x008 0x048 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE000x008 0x048 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE010x00C 0x04C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS00x00C 0x04C 0x094 0x1 0x0 +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO030x00C 0x04C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT0x010 0x050 0x0A0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO040x010 0x050 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO050x014 0x054 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 +#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS30x018 0x058 0x0 0x4 0x0
[PATCH v2 0/4] IMXRT: Maintnice updates
Updates to the imxrt family include: - Adding missing include in board - Moving pinctrl binding to dts - Reducing SYS_MALLOC_LEN - Using device tree for anatop base address Jesse Taube (4): clk: imxrt: Use dts for anatop base address configs/*imxrt10*: SYS_MALLOC_LEN is too large ARM: dts: imxrt10..-evk: Linux moved pins-imxrt1020 to dts board: freescale: imxrt10..-evk: Fix missing include of serial.h arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4 arch/arm/dts/imxrt1020-evk.dts | 2 +- .../pins-imxrt1020.h => arch/arm/dts/imxrt1020-pinfunc.h | 0 arch/arm/dts/imxrt1020.dtsi | 5 + arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4 arch/arm/dts/imxrt1050-evk.dts | 2 +- .../pins-imxrt1050.h => arch/arm/dts/imxrt1050-pinfunc.h | 0 arch/arm/dts/imxrt1050.dtsi | 5 + arch/arm/include/asm/arch-imxrt/imx-regs.h | 2 -- board/freescale/imxrt1020-evk/imxrt1020-evk.c| 1 + board/freescale/imxrt1050-evk/imxrt1050-evk.c| 1 + configs/imxrt1020-evk_defconfig | 2 +- configs/imxrt1050-evk_defconfig | 2 +- drivers/clk/imx/clk-imxrt1020.c | 2 +- drivers/clk/imx/clk-imxrt1050.c | 2 +- 15 files changed, 26 insertions(+), 8 deletions(-) rename include/dt-bindings/pinctrl/pins-imxrt1020.h => arch/arm/dts/imxrt1020-pinfunc.h (100%) rename include/dt-bindings/pinctrl/pins-imxrt1050.h => arch/arm/dts/imxrt1050-pinfunc.h (100%) -- 2.34.1
[PATCH v1 7/8] ARM: dts: imx: add i.MXRT1170-EVK support
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and Cortex-M4 core.
The EVK provides 64 MB SDRAM, Micro SD card socket,
USB 2.0 OTG.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
SDRAM
Signed-off-by: Jesse Taube
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imxrt1170-evk-u-boot.dtsi | 106 ++
arch/arm/dts/imxrt1170-evk.dts | 246 ++
arch/arm/dts/imxrt1170.dtsi| 274 +
4 files changed, 628 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/dts/imxrt1170.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cc34da7bd8..cf5f668b62 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -910,7 +910,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
- imxrt1020-evk.dtb
+ imxrt1020-evk.dtb \
+ imxrt1170-evk.dtb \
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
new file mode 100644
index 00..ebc3a5051c
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ clocks {
+ u-boot,dm-spl;
+ };
+
+ soc {
+ u-boot,dm-spl;
+ };
+};
+
+&osc {
+ u-boot,dm-spl;
+};
+
+&osc32k {
+ u-boot,dm-spl;
+};
+
+&rcosc48M_div2 {
+ u-boot,dm-spl;
+};
+
+&rcosc48M {
+ u-boot,dm-spl;
+};
+
+&rcosc400M {
+ u-boot,dm-spl;
+};
+
+&rcosc16M {
+ u-boot,dm-spl;
+};
+
+&clks {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpt1 {
+ u-boot,dm-spl;
+};
+
+&lpuart1 { /* console */
+ u-boot,dm-spl;
+};
+
+&semc {
+ u-boot,dm-spl;
+
+ bank1: bank@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+
+ imxrt1170-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ u-boot,dm-spl;
+ };
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts
new file mode 100644
index 00..e612eda5ca
--- /dev/null
+++ b/arch/arm/dts/imxrt1170-evk.dts
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ * Giulio Benetti
+ */
+
+/dts-v1/;
+#include "imxrt1170.dtsi"
+#include "imxrt1170-evk-u-boot.dtsi"
+#include "imxrt1170-pinfunc.h"
+
+/ {
+ model = "NXP imxrt1170-evk board";
+ compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ tick-timer = &gpt1;
+ };
+
+ memory@2024 {
+ device_type = "memory";
+ reg = <0x2024 0xf>;
+ };
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x400>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&semc {
+ /*
+* Memory configuration from sdram datasheet IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0xd
+0x0
+0x8
+0x7
+
+0x0d
+0x0b
+0x00
+0x00
+
+0x00
+0x0A
+0x08
+
[PATCH v1 8/8] ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig
Add a base defconfig for the i.MXRT1170 Signed-off-by: Jesse Taube --- configs/imxrt1170-evk_defconfig | 67 + include/configs/imxrt1170-evk.h | 37 ++ 2 files changed, 104 insertions(+) create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 include/configs/imxrt1170-evk.h diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig new file mode 100644 index 00..a8de8ad18e --- /dev/null +++ b/configs/imxrt1170-evk_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_ARCH_IMXRT=y +CONFIG_SYS_TEXT_BASE=0x2024 +CONFIG_SYS_MALLOC_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x8 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imxrt1170-evk" +CONFIG_SPL_TEXT_BASE=0x202C +CONFIG_TARGET_IMXRT1170_EVK=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SIZE_LIMIT=0x2 +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x202C +CONFIG_SD_BOOT=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 +# CONFIG_SPL_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_MII is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_OF_TRANSLATE is not set +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMXRT1170=y +CONFIG_CLK_IMXRT1170=y +# CONFIG_SPL_DM_GPIO is not set +CONFIG_MXC_GPIO=y +# CONFIG_INPUT is not set +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMXRT=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_IMXRT_SDRAM=y +CONFIG_FSL_LPUART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h new file mode 100644 index 00..4ebeffd255 --- /dev/null +++ b/include/configs/imxrt1170-evk.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#ifndef __IMXRT1170_EVK_H +#define __IMXRT1170_EVK_H + +#include + +#define CONFIG_SYS_INIT_SP_ADDR0x2034 + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC1351 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +#define PHYS_SDRAM 0x8000 +#define PHYS_SDRAM_SIZE(64 * 1024 * 1024) + +#define DMAMEM_SZ_ALL (1 * 1024 * 1024) +#define DMAMEM_BASE(PHYS_SDRAM + PHYS_SDRAM_SIZE - \ +DMAMEM_SZ_ALL) + +/* + * Configuration of the external SDRAM memory + */ + +/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_LEN 0x8000 +#define CONFIG_SYS_UBOOT_START 0x202403FD +#endif +/* For SPL ends */ + +#endif /* __IMXRT1170_EVK_H */ -- 2.34.1
[PATCH v1 6/8] RAM: Add changes for i.MXRT11xx series
The i.MXRT11 series has different offsets for IOCR_MUX, it also can
address 64MiB of SDRAM so add a macro for that.
Signed-off-by: Jesse Taube
---
drivers/ram/imxrt_sdram.c| 9 +
include/dt-bindings/memory/imxrt-sdram.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c
index ca2eec767d..d0a88845cf 100644
--- a/drivers/ram/imxrt_sdram.c
+++ b/drivers/ram/imxrt_sdram.c
@@ -87,12 +87,21 @@ struct imxrt_semc_regs {
u32 sts[16];
};
+#if !defined(TARGET_IMXRT1170_EVK)
#define SEMC_IOCR_MUX_A8_SHIFT 0
#define SEMC_IOCR_MUX_CSX0_SHIFT 3
#define SEMC_IOCR_MUX_CSX1_SHIFT 6
#define SEMC_IOCR_MUX_CSX2_SHIFT 9
#define SEMC_IOCR_MUX_CSX3_SHIFT 12
#define SEMC_IOCR_MUX_RDY_SHIFT15
+#else
+#define SEMC_IOCR_MUX_A8_SHIFT 0
+#define SEMC_IOCR_MUX_CSX0_SHIFT 4
+#define SEMC_IOCR_MUX_CSX1_SHIFT 8
+#define SEMC_IOCR_MUX_CSX2_SHIFT 12
+#define SEMC_IOCR_MUX_CSX3_SHIFT 16
+#define SEMC_IOCR_MUX_RDY_SHIFT20
+#endif
struct imxrt_sdram_mux {
u8 a8;
diff --git a/include/dt-bindings/memory/imxrt-sdram.h
b/include/dt-bindings/memory/imxrt-sdram.h
index acb35bce27..4b3b0c2f50 100644
--- a/include/dt-bindings/memory/imxrt-sdram.h
+++ b/include/dt-bindings/memory/imxrt-sdram.h
@@ -82,6 +82,7 @@
#define MEM_WIDTH_8BITS0x0
#define MEM_WIDTH_16BITS 0x1
+#define MEM_WIDTH_32BITS 0x2
#define BL_1 0x0
#define BL_2 0x1
--
2.34.1
[PATCH v1 4/8] clk: imx: Add i.MXRT11xx pllv3 variant
The i.MXRT11 series has two new pll types but are variants of existing.
This patch adds the ability to read one of the pll types' frequency
as it can't be changed unlike the generic pll it also has the
division factors swapped.
Signed-off-by: Jesse Taube
---
drivers/clk/imx/clk-pllv3.c | 44 +
drivers/clk/imx/clk.h | 1 +
2 files changed, 45 insertions(+)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 077757efcb..511c973e5c 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -21,6 +21,7 @@
#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
+#define UBOOT_DM_CLK_IMX_PLLV3_GENV2 "imx_clk_pllv3_genericv2"
#define PLL_NUM_OFFSET 0x10
#define PLL_DENOM_OFFSET 0x20
@@ -42,6 +43,30 @@ struct clk_pllv3 {
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
+static ulong clk_pllv3_genericv2_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+
+ return (div == 0) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static ulong clk_pllv3_genericv2_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+ u32 val = (div == 0) ? parent_rate * 22 : parent_rate * 20;
+
+ if (rate == val)
+ return 0;
+
+ return -EINVAL;
+}
+
static ulong clk_pllv3_generic_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
@@ -120,6 +145,13 @@ static const struct clk_ops clk_pllv3_generic_ops = {
.set_rate = clk_pllv3_generic_set_rate,
};
+static const struct clk_ops clk_pllv3_genericv2_ops = {
+ .get_rate = clk_pllv3_genericv2_get_rate,
+ .enable = clk_pllv3_generic_enable,
+ .disable= clk_pllv3_generic_disable,
+ .set_rate = clk_pllv3_genericv2_set_rate,
+};
+
static ulong clk_pllv3_sys_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(clk);
@@ -269,6 +301,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->div_shift = 0;
pll->powerup_set = false;
break;
+ case IMX_PLLV3_GENERICV2:
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENV2;
+ pll->div_shift = 0;
+ pll->powerup_set = false;
+ break;
case IMX_PLLV3_SYS:
drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
pll->div_shift = 0;
@@ -313,6 +350,13 @@ U_BOOT_DRIVER(clk_pllv3_generic) = {
.flags = DM_FLAG_PRE_RELOC,
};
+U_BOOT_DRIVER(clk_pllv3_genericv2) = {
+ .name = UBOOT_DM_CLK_IMX_PLLV3_GENV2,
+ .id = UCLASS_CLK,
+ .ops= &clk_pllv3_genericv2_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
U_BOOT_DRIVER(clk_pllv3_sys) = {
.name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
.id = UCLASS_CLK,
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 60f287046b..10670252b1 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -10,6 +10,7 @@
enum imx_pllv3_type {
IMX_PLLV3_GENERIC,
+ IMX_PLLV3_GENERICV2,
IMX_PLLV3_SYS,
IMX_PLLV3_USB,
IMX_PLLV3_USB_VF610,
--
2.34.1
[PATCH v1 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver
Add clock driver support for i.MXRT1170.
Signed-off-by: Jesse Taube
---
drivers/clk/imx/Kconfig | 16 +++
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-imxrt1170.c | 215
3 files changed, 232 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 96721bcbf3..ae56603194 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -100,3 +100,19 @@ config CLK_IMXRT1050
select CLK_CCF
help
This enables support clock driver for i.MXRT1050 platforms.
+
+config SPL_CLK_IMXRT1170
+ bool "SPL clock support for i.MXRT1170"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MXRT1170.
+
+config CLK_IMXRT1170
+ bool "Clock support for i.MXRT1170"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1170 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3ae..3ed326739a 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o
clk-pll14xx.o \
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) += clk-imxrt1170.o
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
new file mode 100644
index 00..6ea46b6a52
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static ulong imxrt1170_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1170_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1170_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1170_clk_disable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 0);
+}
+
+static int imxrt1170_clk_enable(struct clk *clk)
+{
+ return __imxrt1170_clk_enable(clk, 1);
+}
+
+static int imxrt1170_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &cp);
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
+static struct clk_ops imxrt1170_clk_ops = {
+ .set_rate = imxrt1170_clk_set_rate,
+ .get_rate = imxrt1170_clk_get_rate,
+ .enable = imxrt1170_clk_enable,
+ .disable = imxrt1170_clk_disable,
+ .set_parent = imxrt1170_clk_set_parent,
+};
+
+static const char * const lpuart1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3"};
+static const char * const gpt1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3"};
+static const char * const usdhc1_sels[] = {"rcosc48M_div2", "osc",
"rcosc400M", "rcosc16M",
+"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
+static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"rcosc16M",
+"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"};
+
+static int imxrt1170_clk_probe(struct udevice *dev)
+{
+ void *base;
+
+ /* Anatop clocks */
+ base = (vo
[PATCH v1 3/8] dt-bindings: imx: Add clock binding for i.MXRT1170
Add the clock binding doc for i.MXRT1170. Signed-off-by: Jesse Taube --- include/dt-bindings/clock/imxrt1170-clock.h | 48 + 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h diff --git a/include/dt-bindings/clock/imxrt1170-clock.h b/include/dt-bindings/clock/imxrt1170-clock.h new file mode 100644 index 00..8ab8018a15 --- /dev/null +++ b/include/dt-bindings/clock/imxrt1170-clock.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + */ + +#ifndef __DT_BINDINGS_CLOCK_IMXRT1170_H +#define __DT_BINDINGS_CLOCK_IMXRT1170_H + +#define IMXRT1170_CLK_DUMMY0 +#define IMXRT1170_CLK_OSC 1 +#define IMXRT1170_CLK_OSC_32K 2 +#define IMXRT1170_CLK_RCOSC_16M3 +#define IMXRT1170_CLK_RCOSC_48M4 +#define IMXRT1170_CLK_RCOSC_48M_DIV2 5 +#define IMXRT1170_CLK_RCOSC_400M 6 +#define IMXRT1170_CLK_PLL_ARM 7 +#define IMXRT1170_CLK_PLL_AUDIO8 +#define IMXRT1170_CLK_PLL_VIDEO9 +#define IMXRT1170_CLK_PLL1 10 +#define IMXRT1170_CLK_PLL1_DIV211 +#define IMXRT1170_CLK_PLL1_DIV512 +#define IMXRT1170_CLK_PLL2 13 +#define IMXRT1170_CLK_PLL2_PFD014 +#define IMXRT1170_CLK_PLL2_PFD115 +#define IMXRT1170_CLK_PLL2_PFD216 +#define IMXRT1170_CLK_PLL2_PFD317 +#define IMXRT1170_CLK_PLL3 18 +#define IMXRT1170_CLK_PLL3_DIV219 +#define IMXRT1170_CLK_PLL3_PFD020 +#define IMXRT1170_CLK_PLL3_PFD121 +#define IMXRT1170_CLK_PLL3_PFD222 +#define IMXRT1170_CLK_PLL3_PFD323 +#define IMXRT1170_CLK_M7 24 +#define IMXRT1170_CLK_M4 25 +#define IMXRT1170_CLK_BUS 26 +#define IMXRT1170_CLK_BUS_LPSR 27 +#define IMXRT1170_CLK_LPUART1_SEL 28 +#define IMXRT1170_CLK_LPUART1 29 +#define IMXRT1170_CLK_USDHC1_SEL 30 +#define IMXRT1170_CLK_USDHC1 31 +#define IMXRT1170_CLK_GPT1_SEL 32 +#define IMXRT1170_CLK_GPT1 33 +#define IMXRT1170_CLK_SEMC_SEL 34 +#define IMXRT1170_CLK_SEMC 35 +#define IMXRT1170_CLK_END 36 + +#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */ -- 2.34.1
[PATCH v1 1/8] imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK
This commit adds board support for i.MXRT1170-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT117x processor family. Signed-off-by: Jesse Taube --- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/mach-imx/imxrt/Kconfig | 9 +++ arch/arm/mach-imx/imxrt/soc.c | 2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS | 7 ++ board/freescale/imxrt1170-evk/Makefile| 6 ++ board/freescale/imxrt1170-evk/imximage.cfg| 32 board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 +++ 8 files changed, 159 insertions(+) create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index fe96378971..b896bdd2de 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -55,6 +55,7 @@ #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ +#define MXC_CPU_IMXRT1170 0xBA /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index d275fdf72e..86923c6c15 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -11,6 +11,10 @@ config IMXRT1050 bool select IMXRT +config IMXRT1170 + bool + select IMXRT + config SYS_SOC default "imxrt" @@ -26,9 +30,14 @@ config TARGET_IMXRT1050_EVK bool "Support imxrt1050 EVK board" select IMXRT1050 +config TARGET_IMXRT1170_EVK + bool "Support imxrt1170 EVK board" + select IMXRT1170 + endchoice source "board/freescale/imxrt1020-evk/Kconfig" source "board/freescale/imxrt1050-evk/Kconfig" +source "board/freescale/imxrt1170-evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index ba015992ee..34162a3976 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -43,6 +43,8 @@ u32 get_cpu_rev(void) return MXC_CPU_IMXRT1020 << 12; #elif defined(CONFIG_IMXRT1050) return MXC_CPU_IMXRT1050 << 12; +#elif defined(CONFIG_IMXRT1170) + return MXC_CPU_IMXRT1170 << 12; #else #error This IMXRT SoC is not supported #endif diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig new file mode 100644 index 00..c61fc57971 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Kconfig @@ -0,0 +1,22 @@ +if TARGET_IMXRT1170_EVK + +config SYS_BOARD + string + default "imxrt1170-evk" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "imxrt1170" + +config SYS_CONFIG_NAME + string + default "imxrt1170-evk" + +config IMX_CONFIG + default "board/freescale/imxrt1170-evk/imximage.cfg" + +endif diff --git a/board/freescale/imxrt1170-evk/MAINTAINERS b/board/freescale/imxrt1170-evk/MAINTAINERS new file mode 100644 index 00..1fc3179c00 --- /dev/null +++ b/board/freescale/imxrt1170-evk/MAINTAINERS @@ -0,0 +1,7 @@ +IMXRT1170 EVALUATION KIT +M: Giulio Benetti +M: Jesse Taube +S: Maintained +F: board/freescale/imxrt1170-evk +F: include/configs/imxrt1170-evk.h +F: configs/imxrt1170-evk_defconfig diff --git a/board/freescale/imxrt1170-evk/Makefile b/board/freescale/imxrt1170-evk/Makefile new file mode 100644 index 00..857a168b09 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# Author(s): Giulio Benetti + +obj-y := imxrt1170-evk.o diff --git a/board/freescale/imxrt1170-evk/imximage.cfg b/board/freescale/imxrt1170-evk/imximage.cfg new file mode 100644 index 00..3354672825 --- /dev/null +++ b/board/freescale/imxrt1170-evk/imximage.cfg @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type AddressValue + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored
[PATCH v1 0/8] Add support for the i.MXRT1170
This patchset contains: - i.MXRT1170 clock driver adaption - i.MXRT1170-evk basic support Jesse Taube (8): imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header dt-bindings: imx: Add clock binding for i.MXRT1170 clk: imx: Add i.MXRT11xx pllv3 variant clk: imx: Add initial support for i.MXRT1170 clock driver RAM: Add changes for i.MXRT11xx series ARM: dts: imx: add i.MXRT1170-EVK support ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig arch/arm/dts/Makefile |3 +- arch/arm/dts/imxrt1170-evk-u-boot.dtsi| 106 ++ arch/arm/dts/imxrt1170-evk.dts| 246 +++ arch/arm/dts/imxrt1170-pinfunc.h | 1561 + arch/arm/dts/imxrt1170.dtsi | 274 +++ arch/arm/include/asm/arch-imx/cpu.h |1 + arch/arm/mach-imx/imxrt/Kconfig |9 + arch/arm/mach-imx/imxrt/soc.c |2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS |7 + board/freescale/imxrt1170-evk/Makefile|6 + board/freescale/imxrt1170-evk/imximage.cfg| 32 + board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 + configs/imxrt1170-evk_defconfig | 67 + drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile |1 + drivers/clk/imx/clk-imxrt1170.c | 215 +++ drivers/clk/imx/clk-pllv3.c | 44 + drivers/clk/imx/clk.h |1 + drivers/ram/imxrt_sdram.c |9 + include/configs/imxrt1170-evk.h | 37 + include/dt-bindings/clock/imxrt1170-clock.h | 48 + include/dt-bindings/memory/imxrt-sdram.h |1 + 23 files changed, 2787 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h create mode 100644 arch/arm/dts/imxrt1170.dtsi create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1170.c create mode 100644 include/configs/imxrt1170-evk.h create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h -- 2.34.1
[PATCH v1 2/2] imx: imxrt1050-evk: Add documentation for SPI boot
Adds documentation for SPI boot. Signed-off-by: Jesse Taube --- doc/board/nxp/imxrt1050-evk.rst | 41 + 1 file changed, 41 insertions(+) diff --git a/doc/board/nxp/imxrt1050-evk.rst b/doc/board/nxp/imxrt1050-evk.rst index c1fb48f0cd..0838a04871 100644 --- a/doc/board/nxp/imxrt1050-evk.rst +++ b/doc/board/nxp/imxrt1050-evk.rst @@ -39,3 +39,44 @@ switch label numbers reference). The USB console connector is the one close the ethernet connector - Insert the micro SD card in the board, power it up and U-Boot messages should come up. + + +How to use U-Boot with SPI flash on NXP i.MXRT1050 EVK +-- + +- Build U-Boot for i.MXRT1050 EVK: + +First you will need to enable the following option: +CONFIG_IMX_CONFIG="board/freescale/imxrt1050-evk/imximage-nor.cfg" + +.. code-block:: bash + + $ make mrproper + $ make imxrt1050-evk_defconfig + $ make + +This will generate the SPL image called SPL and the u-boot.img. + +To boot from SPI flash you will need to provide a flash configuration block that is specific to your flash chip. +The flash config is 4K in size and is documented on page 217 of the imxrt1050RM. + +I took my FLASH config from a binary made from MCUexpresso IDE. +The truncate command should pad the spl with zeros till the value from CONFIG_SYS_UBOOT_BASE. + +.. code-block:: bash + + $ cp FLASH nor.bin + $ cat SPL >> nor.bin + $ truncate -s $((0x1)) nor.bin + $ cat u-boot.img >> nor.bin + +- Jumper settings:: + + SW7: 0 1 1 0 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Connect the USB cable between the EVK and the PC for the console. + +- Use either JTAG or SWD to flash the flash I used Mcuexpresso IDEs GUI flash tool -- 2.34.1
[PATCH v1 1/2] imx: imxrt1050-evk: Add support for SPI flash booting
This add some macros to change addresses to use flexspi.
This commit adds support for booting the imxrt1050-evk from spi.
It adds imximage config and the ability for SPL to boot from NOR.
Signed-off-by: Jesse Taube
---
.../freescale/imxrt1050-evk/imximage-nor.cfg | 42 +++
board/freescale/imxrt1050-evk/imximage.cfg| 11 -
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 8 +++-
configs/imxrt1050-evk_defconfig | 6 ++-
include/configs/imxrt1050-evk.h | 4 +-
5 files changed, 65 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/imxrt1050-evk/imximage-nor.cfg
diff --git a/board/freescale/imxrt1050-evk/imximage-nor.cfg
b/board/freescale/imxrt1050-evk/imximage-nor.cfg
new file mode 100644
index 00..3e1b059075
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imximage-nor.cfg
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti
+ */
+
+#define __ASSEMBLY__
+#include
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM nor
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunatly seting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configureation fortunaly works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aa
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
diff --git a/board/freescale/imxrt1050-evk/imximage.cfg
b/board/freescale/imxrt1050-evk/imximage.cfg
index cf1665be61..dffca91f0a 100644
--- a/board/freescale/imxrt1050-evk/imximage.cfg
+++ b/board/freescale/imxrt1050-evk/imximage.cfg
@@ -30,7 +30,14 @@ BOOT_FROMsd
* value value to be stored in the register
*/
-/* Set all FlexRAM as OCRAM(01b) */
-DATA 4 0x400AC044 0x
+/*
+ * 0x400AC044 is used to configure the flexram.
+ * Unfortunatly seting all to OCRAM only works for MMC
+ * and setting all to DTCM only works for FLEXSPI NOR.
+ * This configureation fortunaly works for both SPI and MMC.
+*/
+/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */
+DATA 4 0x400AC044 0x55aa
/* Use FLEXRAM_BANK_CFG to config FlexRAM */
SET_BIT 4 0x400AC040 0x4
+
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
index 6132916578..d4e39fd914 100644
--- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
+++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -67,7 +68,12 @@ void spl_board_init(void)
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_MMC1;
+ /* There is no way to find boot device so look if there is valid IVT in
RAM for MMC*/
+ u32 nor_ivt = *(u32 *)(CONFIG_SYS_LOAD_ADDR - 0xC00);
+
+ if (nor_ivt == 0x402000d1)
+ return BOOT_DEVICE_MMC1;
+ return BOOT_DEVICE_NOR;
}
#endif
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index ca3f810e02..eaf46bbeb6 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -12,15 +12,16 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x8
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
-CONFIG_SPL_TEXT_BASE=0x20209000
+CONFIG_SPL_TEXT_BASE=0x20002000
CONFIG_TARGET_IMXRT1050_EVK=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SIZE_LIMIT=0x2
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x20209000
+CONFIG_SYS_LOAD_ADDR=0x20002000
CONFIG_SD_BOOT=y
+CONFIG_SPI_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -30,6 +31,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
# CONFIG_SPL_CRC32 is not set
+CONFIG_SPL_NOR_SUPPORT=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
index 99d25c1e6e..f9b80e7b2b 100644
--- a/include/configs/imxrt1050-evk.h
+++ b/include/configs/imxrt1050-evk.h
@@ -9,7 +9,7 @@
#include
-#define CONFIG_SYS_INIT_SP_ADDR0x2028
+#define CONFIG_SYS_INIT_SP_ADDR0x2002
#define CONFIG_SYS_FSL_ERRATUM_ESDHC1351
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
@@ -40,6 +40,8 @@
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADD
[PATCH v1] clk: imxrt: Use dts for anatop base address
In Linux IMX and IMXRT use the device tree to hold the anatop address.
The anatop is used in clock drivers as it controls the internal PLLs
This will move the macro from asm/arch-imxrt to the device tree.
This presumably should also be done with the other IMX boards as well.
Signed-off-by: Jesse Taube
---
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4
arch/arm/dts/imxrt1020.dtsi| 5 +
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4
arch/arm/dts/imxrt1050.dtsi| 5 +
arch/arm/include/asm/arch-imxrt/imx-regs.h | 2 --
drivers/clk/imx/clk-imxrt1020.c| 2 +-
drivers/clk/imx/clk-imxrt1050.c| 2 +-
7 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 121665a2d2..9e1b074d2e 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -22,6 +22,10 @@
u-boot,dm-spl;
};
+&anatop {
+ u-boot,dm-spl;
+};
+
&clks {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 5ba314f995..13511ebb18 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -67,6 +67,11 @@
fsl,mux_mask = <0x7>;
};
+ anatop: anatop@400d8000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x400d8000 0x4000>;
+ };
+
clks: ccm@400fc000 {
compatible = "fsl,imxrt1020-ccm";
reg = <0x400fc000 0x4000>;
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 3168c2df2c..617cece448 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -22,6 +22,10 @@
u-boot,dm-spl;
};
+&anatop {
+ u-boot,dm-spl;
+};
+
&clks {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 6560a3827f..09f4712af6 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -59,6 +59,11 @@
fsl,mux_mask = <0x7>;
};
+ anatop: anatop@400d8000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x400d8000 0x4000>;
+ };
+
clks: ccm@400fc000 {
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h
b/arch/arm/include/asm/arch-imxrt/imx-regs.h
index d01e6ca2e0..ad739caae9 100644
--- a/arch/arm/include/asm/arch-imxrt/imx-regs.h
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -15,8 +15,6 @@
#define GPIO4_BASE_ADDR0x401C4000
#define GPIO5_BASE_ADDR0x400C
-#define ANATOP_BASE_ADDR 0x400d8000
-
#define MXS_LCDIF_BASE 0x402b8000
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
index 840f783940..5adc37ebfe 100644
--- a/drivers/clk/imx/clk-imxrt1020.c
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -93,7 +93,7 @@ static int imxrt1020_clk_probe(struct udevice *dev)
void *base;
/* Anatop clocks */
- base = (void *)ANATOP_BASE_ADDR;
+ base = ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
"fsl,imxrt-anatop"));
clk_dm(IMXRT1020_CLK_PLL2_SYS,
imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 3e17161002..cced32b758 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -117,7 +117,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
void *base;
/* Anatop clocks */
- base = (void *)ANATOP_BASE_ADDR;
+ base = ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
"fsl,imxrt-anatop"));
clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
--
2.34.1
Re: [PATCH v2 0/3] Add SPI boot to SPL on SUNIV/F1C100s
Hey just checking if you know about this set. This patch adds the ability to detect the BROM's boot source, as well as the ability to boot from SPI. Jesse Taube (3): mach-sunxi: Add boot device detection for SUNIV/F1C100s mach-sunxi: Add SPL SPI boot for SUNIV mach-sunxi: Enable SPI boot for SUNIV and licheepi nano arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/include/asm/arch-sunxi/spl.h | 10 + arch/arm/mach-sunxi/Kconfig| 2 +- arch/arm/mach-sunxi/board.c| 57 +- arch/arm/mach-sunxi/spl_spi_sunxi.c| 24 +++ configs/licheepi_nano_defconfig| 1 + 6 files changed, 58 insertions(+), 37 deletions(-)
Re: [PATCH v2 1/3] mach-sunxi: Add boot device detection for SUNIV/F1C100s
On 2/11/22 19:32, Jesse Taube wrote:
In contrast to other Allwinner SoCs the F1C100s BROM does not store a
boot source indicator in the eGON header in SRAM. This leaves the SPL
guessing where we were exactly booted from, and for instance trying
the SD card first, even though we booted from SPI flash.
By inspecting the BROM code and by experimentation, Samuel found that the
top of the BROM stack contains unique pointers for each of the boot
sources, which we can use as a boot source indicator.
This patch removes the existing board_boot_order bodge and replace it
with a proper boot source indication function.
Signed-off-by: Jesse Taube
Suggested-by: Samuel Holland
---
V1 -> V2:
* Bail on NAND
* Change commit description
* Change sunxi_get_boot_source to u32
* Fix FEL boot by next change
* Move suniv_get_boot_device call into sunxi_get_boot_source
* Rename suniv_get_boot_device
* Remove redundant comments
---
arch/arm/include/asm/arch-sunxi/spl.h | 10 +
arch/arm/mach-sunxi/board.c | 57 +--
2 files changed, 38 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h
b/arch/arm/include/asm/arch-sunxi/spl.h
index 58cdf806d9..9a6e8da8e1 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -19,6 +19,16 @@
#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10
#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12
+/*
+ * Values taken from the Bootrom's stack used
+ * to determine where we booted from.
+ */
+
+#define SUNIV_BOOTED_FROM_MMC0 0x40f8
+#define SUNIV_BOOTED_FROM_NAND 0x4114
+#define SUNIV_BOOTED_FROM_SPI 0x4130
+#define SUNIV_BOOTED_FROM_MMC1 0x4150
+
#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0)
uint32_t sunxi_get_boot_device(void);
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 57078f7a7b..27aee1e445 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -191,12 +191,37 @@ SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD,
spl_board_load_image);
#define SUNXI_INVALID_BOOT_SOURCE -1
-static int sunxi_get_boot_source(void)
Didn't like the implicit cast on the return statement.
+static uint32_t suniv_get_boot_source(void)
+{
+ /* Get the last function call from BootRom's stack. */
+ u32 brom_call = *(u32 *)(fel_stash.sp - 4);
+
+ /* translate SUNIV Bootrom stack to standard SUNXI boot sources */
+ switch (brom_call) {
+ case SUNIV_BOOTED_FROM_MMC0:
+ return SUNXI_BOOTED_FROM_MMC0;
+ case SUNIV_BOOTED_FROM_SPI:
+ return SUNXI_BOOTED_FROM_SPI;
+ case SUNIV_BOOTED_FROM_MMC1:
+ return SUNXI_BOOTED_FROM_MMC2;
+ /* SPI nand is invalid try to boot from FEL*/
+ case SUNIV_BOOTED_FROM_NAND:
+ return SUNXI_INVALID_BOOT_SOURCE;
+ }
+ /* If we get here something went wrong try to boot from FEL.*/
+ printf("Unknown boot source from BROM: 0x%x\n", brom_call);
+ return SUNXI_INVALID_BOOT_SOURCE;
This just trys to boot from FEL doesn't hang.
+}
+
+static uint32_t sunxi_get_boot_source(void)
{
if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
return SUNXI_INVALID_BOOT_SOURCE;
This will return when booting from FEL.
- return readb(SPL_ADDR + 0x28);
+ if (IS_ENABLED(CONFIG_MACH_SUNIV))
+ return suniv_get_boot_source();
+ else
+ return readb(SPL_ADDR + 0x28);
}
/* The sunxi internal brom will try to loader external bootloader
@@ -204,7 +229,7 @@ static int sunxi_get_boot_source(void)
*/
uint32_t sunxi_get_boot_device(void)
{
- int boot_source = sunxi_get_boot_source();
+ uint32_t boot_source = sunxi_get_boot_source();
/*
* When booting from the SD card or NAND memory, the "eGON.BT0"
@@ -276,36 +301,10 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc
*mmc,
return sector;
}
-#ifdef CONFIG_MACH_SUNIV
-/*
- * The suniv BROM does not pass the boot media type to SPL, so we try with the
- * boot sequence in BROM: mmc0->spinor->fail.
- * TODO: This has the slight chance of being wrong (invalid SPL signature,
- * but valid U-Boot legacy image on the SD card), but this should be rare.
- * It looks like we can deduce from some BROM state upon entering the SPL
- * (registers, SP, or stack itself) where the BROM was coming from and use
- * that here.
- */
-void board_boot_order(u32 *spl_boot_list)
-{
- /*
-* See the comments above in sunxi_get_boot_device() for information
-* about FEL boot.
-*/
- if (!is_boot0_magic(SPL_ADDR + 4)) {
- spl_boot_list[0] = BOOT_DEVICE_BOARD;
- return;
- }
-
- spl_boot_list[0] = BOOT_DEVICE_MMC1;
- spl_boot_list[1] = BOOT_DEVICE_SPI;
-}
-#else
u32 spl_boot_device(vo
[PATCH v2 3/3] mach-sunxi: Enable SPI boot for SUNIV and licheepi nano
Enable SPI boot in SPL on SUNIV architecture and use it in the licheepi nano that uses the F1C100s. Signed-off-by: Jesse Taube Reviewed-by: Andre Przywara --- V1 -> V2: * Change commit description --- arch/arm/mach-sunxi/Kconfig | 2 +- configs/licheepi_nano_defconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 205fe3c9d3..d1c60d2408 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1038,7 +1038,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 2ac0ef4285..9fd1dcc995 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -9,3 +9,4 @@ CONFIG_MACH_SUNIV=y CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set +CONFIG_SPL_SPI_SUNXI=y -- 2.34.1
[PATCH v2 2/3] mach-sunxi: Add SPL SPI boot for SUNIV
The SUNIV SoCs come with a sun6i-style SPI controller at the base address
of sun4i SPI controller. The module clock of the SPI controller is
missing which leaves us running directly from the AHB clock, which is
set to 200MHz.
Signed-off-by: Icenowy Zheng
[Icenowy: Original implementation]
Signed-off-by: Jesse Taube
[Jesse: adaptation to Upstream U-Boot]
---
V1 -> V2:
* Change commit description
* Remove redundant conditional statment
* Use else if for pin-function
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
arch/arm/mach-sunxi/spl_spi_sunxi.c| 24 +---
2 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 7f7eb0517c..edd0fbf49f 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -160,6 +160,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI04
+#define SUNIV_GPC_SPI0 2
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS03
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 910e805016..734c165e5d 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -90,6 +90,7 @@
#define SPI0_CLK_DIV_BY_2 0x1000
#define SPI0_CLK_DIV_BY_4 0x1001
+#define SPI0_CLK_DIV_BY_32 0x100f
/*/
@@ -132,7 +133,8 @@ static uintptr_t spi0_base_address(void)
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
return 0x0501;
- if (!is_sun6i_gen_spi())
+ if (!is_sun6i_gen_spi() ||
+ IS_ENABLED(CONFIG_MACH_SUNIV))
return 0x01C05000;
return 0x01C68000;
@@ -156,11 +158,16 @@ static void spi0_enable_clock(void)
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
- /* Divide by 4 */
- writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
- SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
- /* 24MHz from OSC24M */
- writel((1 << 31), CCM_SPI0_CLK);
+ if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
+ /* Divide by 32, clock source is AHB clock 200MHz */
+ writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL);
+ } else {
+ /* Divide by 4 */
+ writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
+ SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
+ /* 24MHz from OSC24M */
+ writel((1 << 31), CCM_SPI0_CLK);
+ }
if (is_sun6i_gen_spi()) {
/* Enable SPI in the master mode and do a soft reset */
@@ -191,7 +198,8 @@ static void spi0_disable_clock(void)
SUN4I_CTL_ENABLE);
/* Disable the SPI0 clock */
- writel(0, CCM_SPI0_CLK);
+ if (!IS_ENABLED(CONFIG_MACH_SUNIV))
+ writel(0, CCM_SPI0_CLK);
/* Close the SPI0 gate */
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
@@ -212,6 +220,8 @@ static void spi0_init(void)
if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6))
pin_function = SUN50I_GPC_SPI0;
+ else if (IS_ENABLED(CONFIG_MACH_SUNIV))
+ pin_function = SUNIV_GPC_SPI0;
spi0_pinmux_setup(pin_function);
spi0_enable_clock();
--
2.34.1
[PATCH v2 1/3] mach-sunxi: Add boot device detection for SUNIV/F1C100s
In contrast to other Allwinner SoCs the F1C100s BROM does not store a
boot source indicator in the eGON header in SRAM. This leaves the SPL
guessing where we were exactly booted from, and for instance trying
the SD card first, even though we booted from SPI flash.
By inspecting the BROM code and by experimentation, Samuel found that the
top of the BROM stack contains unique pointers for each of the boot
sources, which we can use as a boot source indicator.
This patch removes the existing board_boot_order bodge and replace it
with a proper boot source indication function.
Signed-off-by: Jesse Taube
Suggested-by: Samuel Holland
---
V1 -> V2:
* Bail on NAND
* Change commit description
* Change sunxi_get_boot_source to u32
* Fix FEL boot by next change
* Move suniv_get_boot_device call into sunxi_get_boot_source
* Rename suniv_get_boot_device
* Remove redundant comments
---
arch/arm/include/asm/arch-sunxi/spl.h | 10 +
arch/arm/mach-sunxi/board.c | 57 +--
2 files changed, 38 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h
b/arch/arm/include/asm/arch-sunxi/spl.h
index 58cdf806d9..9a6e8da8e1 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -19,6 +19,16 @@
#define SUNXI_BOOTED_FROM_MMC0_HIGH0x10
#define SUNXI_BOOTED_FROM_MMC2_HIGH0x12
+/*
+ * Values taken from the Bootrom's stack used
+ * to determine where we booted from.
+ */
+
+#define SUNIV_BOOTED_FROM_MMC0 0x40f8
+#define SUNIV_BOOTED_FROM_NAND 0x4114
+#define SUNIV_BOOTED_FROM_SPI 0x4130
+#define SUNIV_BOOTED_FROM_MMC1 0x4150
+
#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0)
uint32_t sunxi_get_boot_device(void);
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 57078f7a7b..27aee1e445 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -191,12 +191,37 @@ SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD,
spl_board_load_image);
#define SUNXI_INVALID_BOOT_SOURCE -1
-static int sunxi_get_boot_source(void)
+static uint32_t suniv_get_boot_source(void)
+{
+ /* Get the last function call from BootRom's stack. */
+ u32 brom_call = *(u32 *)(fel_stash.sp - 4);
+
+ /* translate SUNIV Bootrom stack to standard SUNXI boot sources */
+ switch (brom_call) {
+ case SUNIV_BOOTED_FROM_MMC0:
+ return SUNXI_BOOTED_FROM_MMC0;
+ case SUNIV_BOOTED_FROM_SPI:
+ return SUNXI_BOOTED_FROM_SPI;
+ case SUNIV_BOOTED_FROM_MMC1:
+ return SUNXI_BOOTED_FROM_MMC2;
+ /* SPI nand is invalid try to boot from FEL*/
+ case SUNIV_BOOTED_FROM_NAND:
+ return SUNXI_INVALID_BOOT_SOURCE;
+ }
+ /* If we get here something went wrong try to boot from FEL.*/
+ printf("Unknown boot source from BROM: 0x%x\n", brom_call);
+ return SUNXI_INVALID_BOOT_SOURCE;
+}
+
+static uint32_t sunxi_get_boot_source(void)
{
if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
return SUNXI_INVALID_BOOT_SOURCE;
- return readb(SPL_ADDR + 0x28);
+ if (IS_ENABLED(CONFIG_MACH_SUNIV))
+ return suniv_get_boot_source();
+ else
+ return readb(SPL_ADDR + 0x28);
}
/* The sunxi internal brom will try to loader external bootloader
@@ -204,7 +229,7 @@ static int sunxi_get_boot_source(void)
*/
uint32_t sunxi_get_boot_device(void)
{
- int boot_source = sunxi_get_boot_source();
+ uint32_t boot_source = sunxi_get_boot_source();
/*
* When booting from the SD card or NAND memory, the "eGON.BT0"
@@ -276,36 +301,10 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc
*mmc,
return sector;
}
-#ifdef CONFIG_MACH_SUNIV
-/*
- * The suniv BROM does not pass the boot media type to SPL, so we try with the
- * boot sequence in BROM: mmc0->spinor->fail.
- * TODO: This has the slight chance of being wrong (invalid SPL signature,
- * but valid U-Boot legacy image on the SD card), but this should be rare.
- * It looks like we can deduce from some BROM state upon entering the SPL
- * (registers, SP, or stack itself) where the BROM was coming from and use
- * that here.
- */
-void board_boot_order(u32 *spl_boot_list)
-{
- /*
-* See the comments above in sunxi_get_boot_device() for information
-* about FEL boot.
-*/
- if (!is_boot0_magic(SPL_ADDR + 4)) {
- spl_boot_list[0] = BOOT_DEVICE_BOARD;
- return;
- }
-
- spl_boot_list[0] = BOOT_DEVICE_MMC1;
- spl_boot_list[1] = BOOT_DEVICE_SPI;
-}
-#else
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
-#endif
__weak void sunxi_sram_init(void)
{
--
2.34.1
[PATCH v2 0/3] Add SPI boot to SPL on SUNIV/F1C100s
This patch adds the ability to detect the BROM's boot source, as well as the ability to boot from SPI. Jesse Taube (3): mach-sunxi: Add boot device detection for SUNIV/F1C100s mach-sunxi: Add SPL SPI boot for SUNIV mach-sunxi: Enable SPI boot for SUNIV and licheepi nano arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/include/asm/arch-sunxi/spl.h | 10 + arch/arm/mach-sunxi/Kconfig| 2 +- arch/arm/mach-sunxi/board.c| 57 +- arch/arm/mach-sunxi/spl_spi_sunxi.c| 24 +++ configs/licheepi_nano_defconfig| 1 + 6 files changed, 58 insertions(+), 37 deletions(-) -- 2.34.1
Re: [PATCH v1 1/3] mach-sunxi: Add boot device detection for SUNIV
On 2/10/22 14:38, Siarhei Siamashka wrote:
On Thu, Feb 10, 2022 at 6:35 AM Jesse Taube wrote:
[...]
+ case SUNIV_BOOTED_FROM_NAND:
+ case SUNIV_BOOTED_FROM_SPI:
+ return BOOT_DEVICE_SPI;
Is it really okay to lump SPI and NAND together and return
BOOT_DEVICE_SPI for both?
Booting from SPI NAND.
I can change it to BOOT_DEVICE_NAND.
What's the NAND support story on this device?
I thought BOOT_DEVICE_NAND was for parallel NAND but I may be wrong
could come one clarify please?
Thanks,
Jesse Taube
Re: [PATCH v1 1/3] mach-sunxi: Add boot device detection for SUNIV
On 2/10/22 05:57, Andre Przywara wrote:
On Wed, 9 Feb 2022 23:34:36 -0500
Jesse Taube wrote:
Hi Jesse,
many thanks for sending this, much appreciated!
Use Samuel's suggestion of looking at the BootRom's stack
to determine the boot device.
Can you please elaborate here what's going on, for future reference? Like:
=
In contrast to other Allwinner SoCs the F1C100s BROM does not store a boot
source indicator in the eGON header in SRAM. This leaves us guessing where
we were exactly booted from, and for instance trying the SD card first,
even though we booted from SPI flash.
By inspecting the BROM code and by experimentation, Samuel found that the
top of the BROM stack contains unique pointers for each of the boot
sources, which we can use as a boot source indicator.
Remove the existing board_boot_order kludge and replace it with a proper
boot source indication function.
=
Signed-off-by: Jesse Taube
Suggested-by: Samuel Holland
---
arch/arm/include/asm/arch-sunxi/spl.h | 15
arch/arm/mach-sunxi/board.c | 50 ---
2 files changed, 38 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h
b/arch/arm/include/asm/arch-sunxi/spl.h
index 58cdf806d9..d069091297 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -19,8 +19,23 @@
#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10
#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12
+/*
+ * Values taken from the Bootrom's stack used
+ * to determine where we booted from.
+ * 0x40f8: mmc0
+ * 0x4114: spi0 NAND
+ * 0x4130: spi0 NOR
+ * 0x4150: mmc1
Those last four lines are redundant, as you say exactly that, in code,
down here again. Comments are good, speaking code is better.
+ */
+
+#define SUNIV_BOOTED_FROM_MMC0 0x40f8
+#define SUNIV_BOOTED_FROM_NAND 0x4114
+#define SUNIV_BOOTED_FROM_SPI 0x4130
+#define SUNIV_BOOTED_FROM_MMC1 0x4150
+
#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0)
uint32_t sunxi_get_boot_device(void);
+uint32_t suniv_get_boot_device(void);
#endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 57078f7a7b..b0658d583e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -241,6 +241,25 @@ uint32_t sunxi_get_boot_device(void)
return -1; /* Never reached */
}
+uint32_t suniv_get_boot_device(void)
This can be static, right?
+{
+ /* Get the last function call from BootRom's stack. */
+ u32 brom_call = *(u32 *)(fel_stash.sp - 4);You are okay with this I was expecting you to explain a better way that
i don't know about.
+
+ switch (brom_call) {
+ case SUNIV_BOOTED_FROM_MMC0:
+ return BOOT_DEVICE_MMC1;
+ case SUNIV_BOOTED_FROM_NAND:
+ case SUNIV_BOOTED_FROM_SPI:
+ return BOOT_DEVICE_SPI;
+ case SUNIV_BOOTED_FROM_MMC1:
+ return BOOT_DEVICE_MMC2;
+ }
Don't you need to handle FEL boot here somehow?
Yes but I have no clue what the SP is also wouldn't we have it hang
anyway. The other changes requested i have fixed, I'm sorry about the
subpar commit descriptions.
Thanks,
Jesse
Cheers,
Andre
+
+ printf("Unknown boot source from BROM: 0x%x\n", brom_call);
+ return BOOT_DEVICE_MMC1;
+}
+
#ifdef CONFIG_SPL_BUILD
static u32 sunxi_get_spl_size(void)
{
@@ -276,36 +295,13 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc
*mmc,
return sector;
}
-#ifdef CONFIG_MACH_SUNIV
-/*
- * The suniv BROM does not pass the boot media type to SPL, so we try with the
- * boot sequence in BROM: mmc0->spinor->fail.
- * TODO: This has the slight chance of being wrong (invalid SPL signature,
- * but valid U-Boot legacy image on the SD card), but this should be rare.
- * It looks like we can deduce from some BROM state upon entering the SPL
- * (registers, SP, or stack itself) where the BROM was coming from and use
- * that here.
- */
-void board_boot_order(u32 *spl_boot_list)
-{
- /*
-* See the comments above in sunxi_get_boot_device() for information
-* about FEL boot.
-*/
- if (!is_boot0_magic(SPL_ADDR + 4)) {
- spl_boot_list[0] = BOOT_DEVICE_BOARD;
- return;
- }
-
- spl_boot_list[0] = BOOT_DEVICE_MMC1;
- spl_boot_list[1] = BOOT_DEVICE_SPI;
-}
-#else
u32 spl_boot_device(void)
{
- return sunxi_get_boot_device();
+ if (IS_ENABLED(CONFIG_MACH_SUNIV))
+ return suniv_get_boot_device();
+ else
+ return sunxi_get_boot_device();
}
-#endif
__weak void sunxi_sram_init(void)
{
Re: [PATCH v1 1/3] mach-sunxi: Add boot device detection for SUNIV
On 2/10/22 05:57, Andre Przywara wrote:
On Wed, 9 Feb 2022 23:34:36 -0500
Jesse Taube wrote:
Hi Jesse,
many thanks for sending this, much appreciated!
Use Samuel's suggestion of looking at the BootRom's stack
to determine the boot device.
Can you please elaborate here what's going on, for future reference? Like:
=
In contrast to other Allwinner SoCs the F1C100s BROM does not store a boot
source indicator in the eGON header in SRAM. This leaves us guessing where
we were exactly booted from, and for instance trying the SD card first,
even though we booted from SPI flash.
By inspecting the BROM code and by experimentation, Samuel found that the
top of the BROM stack contains unique pointers for each of the boot
sources, which we can use as a boot source indicator.
Remove the existing board_boot_order kludge and replace it with a proper
boot source indication function.
=
Signed-off-by: Jesse Taube
Suggested-by: Samuel Holland
---
arch/arm/include/asm/arch-sunxi/spl.h | 15
arch/arm/mach-sunxi/board.c | 50 ---
2 files changed, 38 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h
b/arch/arm/include/asm/arch-sunxi/spl.h
index 58cdf806d9..d069091297 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -19,8 +19,23 @@
#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10
#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12
+/*
+ * Values taken from the Bootrom's stack used
+ * to determine where we booted from.
+ * 0x40f8: mmc0
+ * 0x4114: spi0 NAND
+ * 0x4130: spi0 NOR
+ * 0x4150: mmc1
Those last four lines are redundant, as you say exactly that, in code,
down here again. Comments are good, speaking code is better.
+ */
+
+#define SUNIV_BOOTED_FROM_MMC0 0x40f8
+#define SUNIV_BOOTED_FROM_NAND 0x4114
+#define SUNIV_BOOTED_FROM_SPI 0x4130
+#define SUNIV_BOOTED_FROM_MMC1 0x4150
+
#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0)
uint32_t sunxi_get_boot_device(void);
+uint32_t suniv_get_boot_device(void);
#endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 57078f7a7b..b0658d583e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -241,6 +241,25 @@ uint32_t sunxi_get_boot_device(void)
return -1; /* Never reached */
}
+uint32_t suniv_get_boot_device(void)
This can be static, right?
Yes it can it is not because sunxi_get_boot_device isn'tm,
but that is only not static because board/sunxi/board.c:mmc_get_env_dev.
I will make it static.
+{
+ /* Get the last function call from BootRom's stack. */
+ u32 brom_call = *(u32 *)(fel_stash.sp - 4);
+
+ switch (brom_call) {
+ case SUNIV_BOOTED_FROM_MMC0:
+ return BOOT_DEVICE_MMC1;
+ case SUNIV_BOOTED_FROM_NAND:
+ case SUNIV_BOOTED_FROM_SPI:
+ return BOOT_DEVICE_SPI;
+ case SUNIV_BOOTED_FROM_MMC1:
+ return BOOT_DEVICE_MMC2;
+ }
Don't you need to handle FEL boot here somehow?
Cheers,
Andre
+
+ printf("Unknown boot source from BROM: 0x%x\n", brom_call);
+ return BOOT_DEVICE_MMC1;
+}
+
#ifdef CONFIG_SPL_BUILD
static u32 sunxi_get_spl_size(void)
{
@@ -276,36 +295,13 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc
*mmc,
return sector;
}
-#ifdef CONFIG_MACH_SUNIV
-/*
- * The suniv BROM does not pass the boot media type to SPL, so we try with the
- * boot sequence in BROM: mmc0->spinor->fail.
- * TODO: This has the slight chance of being wrong (invalid SPL signature,
- * but valid U-Boot legacy image on the SD card), but this should be rare.
- * It looks like we can deduce from some BROM state upon entering the SPL
- * (registers, SP, or stack itself) where the BROM was coming from and use
- * that here.
- */
-void board_boot_order(u32 *spl_boot_list)
-{
- /*
-* See the comments above in sunxi_get_boot_device() for information
-* about FEL boot.
-*/
- if (!is_boot0_magic(SPL_ADDR + 4)) {
- spl_boot_list[0] = BOOT_DEVICE_BOARD;
- return;
- }
-
- spl_boot_list[0] = BOOT_DEVICE_MMC1;
- spl_boot_list[1] = BOOT_DEVICE_SPI;
-}
-#else
u32 spl_boot_device(void)
{
- return sunxi_get_boot_device();
+ if (IS_ENABLED(CONFIG_MACH_SUNIV))
+ return suniv_get_boot_device();
+ else
+ return sunxi_get_boot_device();
}
-#endif
__weak void sunxi_sram_init(void)
{
[PATCH v1 3/3] mach-sunxi: Enable spi boot for SUNIV
Enable spi boot in spl on suniv architecture. Signed-off-by: Jesse Taube --- arch/arm/mach-sunxi/Kconfig | 2 +- configs/licheepi_nano_defconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 205fe3c9d3..d1c60d2408 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1038,7 +1038,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 2ac0ef4285..9fd1dcc995 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -9,3 +9,4 @@ CONFIG_MACH_SUNIV=y CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set +CONFIG_SPL_SPI_SUNXI=y -- 2.34.1
[PATCH v1 2/3] mach-sunxi: Add spi boot for SUNIV
Add support for the spi boot in spl on suniv architecture.
Signed-off-by: Jesse Taube
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
arch/arm/mach-sunxi/spl_spi_sunxi.c| 26 +++---
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 7f7eb0517c..edd0fbf49f 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -160,6 +160,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI04
+#define SUNIV_GPC_SPI0 2
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS03
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 910e805016..9a3666a2d7 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -90,6 +90,7 @@
#define SPI0_CLK_DIV_BY_2 0x1000
#define SPI0_CLK_DIV_BY_4 0x1001
+#define SPI0_CLK_DIV_BY_32 0x100f
/*/
@@ -132,7 +133,8 @@ static uintptr_t spi0_base_address(void)
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
return 0x0501;
- if (!is_sun6i_gen_spi())
+ if (!is_sun6i_gen_spi() ||
+ IS_ENABLED(CONFIG_MACH_SUNIV))
return 0x01C05000;
return 0x01C68000;
@@ -156,11 +158,17 @@ static void spi0_enable_clock(void)
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
- /* Divide by 4 */
- writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
- SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
- /* 24MHz from OSC24M */
- writel((1 << 31), CCM_SPI0_CLK);
+ if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
+ /* Divide by 32, clock source is AHB clock 200MHz */
+ writel(SPI0_CLK_DIV_BY_32, base +
(IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?
+ SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
+ } else {
+ /* Divide by 4 */
+ writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
+ SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
+ /* 24MHz from OSC24M */
+ writel((1 << 31), CCM_SPI0_CLK);
+ }
if (is_sun6i_gen_spi()) {
/* Enable SPI in the master mode and do a soft reset */
@@ -191,7 +199,8 @@ static void spi0_disable_clock(void)
SUN4I_CTL_ENABLE);
/* Disable the SPI0 clock */
- writel(0, CCM_SPI0_CLK);
+ if (!IS_ENABLED(CONFIG_MACH_SUNIV))
+ writel(0, CCM_SPI0_CLK);
/* Close the SPI0 gate */
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
@@ -213,6 +222,9 @@ static void spi0_init(void)
IS_ENABLED(CONFIG_MACH_SUN50I_H6))
pin_function = SUN50I_GPC_SPI0;
+ if (IS_ENABLED(CONFIG_MACH_SUNIV))
+ pin_function = SUNIV_GPC_SPI0;
+
spi0_pinmux_setup(pin_function);
spi0_enable_clock();
}
--
2.34.1
[PATCH v1 1/3] mach-sunxi: Add boot device detection for SUNIV
Use Samuel's suggestion of looking at the BootRom's stack
to determine the boot device.
Signed-off-by: Jesse Taube
Suggested-by: Samuel Holland
---
arch/arm/include/asm/arch-sunxi/spl.h | 15
arch/arm/mach-sunxi/board.c | 50 ---
2 files changed, 38 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h
b/arch/arm/include/asm/arch-sunxi/spl.h
index 58cdf806d9..d069091297 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -19,8 +19,23 @@
#define SUNXI_BOOTED_FROM_MMC0_HIGH0x10
#define SUNXI_BOOTED_FROM_MMC2_HIGH0x12
+/*
+ * Values taken from the Bootrom's stack used
+ * to determine where we booted from.
+ * 0x40f8: mmc0
+ * 0x4114: spi0 NAND
+ * 0x4130: spi0 NOR
+ * 0x4150: mmc1
+ */
+
+#define SUNIV_BOOTED_FROM_MMC0 0x40f8
+#define SUNIV_BOOTED_FROM_NAND 0x4114
+#define SUNIV_BOOTED_FROM_SPI 0x4130
+#define SUNIV_BOOTED_FROM_MMC1 0x4150
+
#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0)
uint32_t sunxi_get_boot_device(void);
+uint32_t suniv_get_boot_device(void);
#endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 57078f7a7b..b0658d583e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -241,6 +241,25 @@ uint32_t sunxi_get_boot_device(void)
return -1; /* Never reached */
}
+uint32_t suniv_get_boot_device(void)
+{
+ /* Get the last function call from BootRom's stack. */
+ u32 brom_call = *(u32 *)(fel_stash.sp - 4);
+
+ switch (brom_call) {
+ case SUNIV_BOOTED_FROM_MMC0:
+ return BOOT_DEVICE_MMC1;
+ case SUNIV_BOOTED_FROM_NAND:
+ case SUNIV_BOOTED_FROM_SPI:
+ return BOOT_DEVICE_SPI;
+ case SUNIV_BOOTED_FROM_MMC1:
+ return BOOT_DEVICE_MMC2;
+ }
+
+ printf("Unknown boot source from BROM: 0x%x\n", brom_call);
+ return BOOT_DEVICE_MMC1;
+}
+
#ifdef CONFIG_SPL_BUILD
static u32 sunxi_get_spl_size(void)
{
@@ -276,36 +295,13 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc
*mmc,
return sector;
}
-#ifdef CONFIG_MACH_SUNIV
-/*
- * The suniv BROM does not pass the boot media type to SPL, so we try with the
- * boot sequence in BROM: mmc0->spinor->fail.
- * TODO: This has the slight chance of being wrong (invalid SPL signature,
- * but valid U-Boot legacy image on the SD card), but this should be rare.
- * It looks like we can deduce from some BROM state upon entering the SPL
- * (registers, SP, or stack itself) where the BROM was coming from and use
- * that here.
- */
-void board_boot_order(u32 *spl_boot_list)
-{
- /*
-* See the comments above in sunxi_get_boot_device() for information
-* about FEL boot.
-*/
- if (!is_boot0_magic(SPL_ADDR + 4)) {
- spl_boot_list[0] = BOOT_DEVICE_BOARD;
- return;
- }
-
- spl_boot_list[0] = BOOT_DEVICE_MMC1;
- spl_boot_list[1] = BOOT_DEVICE_SPI;
-}
-#else
u32 spl_boot_device(void)
{
- return sunxi_get_boot_device();
+ if (IS_ENABLED(CONFIG_MACH_SUNIV))
+ return suniv_get_boot_device();
+ else
+ return sunxi_get_boot_device();
}
-#endif
__weak void sunxi_sram_init(void)
{
--
2.34.1
[PATCH v1 0/3] Add spi boot to SPL on SUNIV
This patch adds the ability to detect the BROM's boot source as well as the ability to boot from spi. Jesse Taube (3): mach-sunxi: Add boot device detection for SUNIV mach-sunxi: Add spi boot for SUNIV mach-sunxi: Enable spi boot for SUNIV arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/include/asm/arch-sunxi/spl.h | 15 arch/arm/mach-sunxi/Kconfig| 2 +- arch/arm/mach-sunxi/board.c| 50 -- arch/arm/mach-sunxi/spl_spi_sunxi.c| 26 ++ configs/licheepi_nano_defconfig| 1 + 6 files changed, 60 insertions(+), 35 deletions(-) -- 2.34.1
Re: [PATCH v2 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs
On 2/7/22 19:22, Stanley Chu wrote:
This driver enables a periodic timer on NPCM SoCs and
implements the get_count timer ops.
Signed-off-by: Stanley Chu
---
Changes in v2:
calculate the prescale value, not hardcode.I would have waited to see what maintainers say. They usually take
longer about 2 days. You also may want to find other people more
relevant to this patch. Do you have an online presence like linkedin,
github etc?
Thanks,
Jesse Taube
---
drivers/timer/Kconfig | 6 ++
drivers/timer/Makefile | 1 +
drivers/timer/npcm-timer.c | 110 +
3 files changed, 117 insertions(+)
create mode 100644 drivers/timer/npcm-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 8913142654..f22c46f44e 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -143,6 +143,12 @@ config NOMADIK_MTU_TIMER
The MTU provides 4 decrementing free-running timers.
At the moment, only the first timer is used by the driver.
+config NPCM_TIMER
+ bool "Nuvoton NPCM timer support"
+ depends on TIMER
+ help
+ Select this to enable a timer on Nuvoton NPCM SoCs.
+
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index e2bd530eb0..39bda1ea79 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER)+= dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o
+obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
new file mode 100644
index 00..65727e41a4
--- /dev/null
+++ b/drivers/timer/npcm-timer.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NPCM_TIMER_CLOCK_RATE 100UL /* 1MHz timer */
+#define NPCM_TIMER_INPUT_RATE 2500UL /* Rate of input clock
*/
+#define NPCM_TIMER_TDR_MASKGENMASK(23, 0)
+#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
+
+/* Register offsets */
+#define TCR0 0x0 /* Timer Control and Status Register */
+#define TICR0 0x8 /* Timer Initial Count Register */
+#define TDR0 0x10/* Timer Data Register */
+
+/* TCR fields */
+#define TCR_MODE_PERIODIC BIT(27)
+#define TCR_EN BIT(30)
+#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE
- 1)
+
+/*
+ * 24-bits down-counting hw timer.
+ * last_count: last hw counter value.
+ * counter: the value to be returned for get_count ops.
+ */
+struct npcm_timer_priv {
+ void __iomem *base;
+ u32 last_count;
+ u64 counter;
+};
+
+static u64 npcm_timer_get_count(struct udevice *dev)
+{
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ /* The timer is couting down */
+ val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
+ if (val <= priv->last_count)
+ priv->counter += priv->last_count - val;
+ else
+ priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 -
val);
+ priv->last_count = val;
+
+ return priv->counter;
+}
+
+static int npcm_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+ priv->counter = 0;
+ priv->last_count = 0;
+ uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
+
+ if (IS_ENABLED(CONFIG_ARCH_NPCM750)) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /*
+* Configure timer and start
+* periodic mode
+* input clock freq = 25Mhz
+* timer clock rate = input clock / prescale
+*/
+ writel(0, priv->base + TCR0);
+ writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
+ writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE,
+ priv->base + TCR0);
+
+ return 0;
+}
+
+static const struct timer_ops npcm_timer_ops = {
+ .get_count = npcm_timer_get_count,
+};
+
+static const struct udevice_id npcm_timer_ids[
Re: [PATCH v1 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs
On 2/7/22 01:02, Stanley Chu wrote:
This driver enables a periodic timer on NPCM SoCs and
implements the get_count timer ops.
Signed-off-by: Stanley Chu
---
drivers/timer/Kconfig | 6 ++
drivers/timer/Makefile | 1 +
drivers/timer/npcm-timer.c | 111 +
3 files changed, 118 insertions(+)
create mode 100644 drivers/timer/npcm-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 8913142654..f22c46f44e 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -143,6 +143,12 @@ config NOMADIK_MTU_TIMER
The MTU provides 4 decrementing free-running timers.
At the moment, only the first timer is used by the driver.
+config NPCM_TIMER
+ bool "Nuvoton NPCM timer support"
+ depends on TIMER
+ help
+ Select this to enable a timer on Nuvoton NPCM SoCs.
+
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index e2bd530eb0..39bda1ea79 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER)+= dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o
+obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
new file mode 100644
index 00..f7d95d4bfa
--- /dev/null
+++ b/drivers/timer/npcm-timer.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NPCM_TIMER_CLOCK_RATE 100UL /* 1MHz timer */
+#define NPCM_TIMER_INPUT_RATE 2500UL /* Rate of input clock
*/
+#define NPCM_TIMER_TDR_MASKGENMASK(23, 0)
+#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
+
+/* Register offsets */
+#define TCR0 0x0 /* Timer Control and Status Register */
+#define TICR0 0x8 /* Timer Initial Count Register */
+#define TDR0 0x10/* Timer Data Register */
+
+/* TCR fields */
+#define TCR_MODE_PERIODIC BIT(27)
+#define TCR_EN BIT(30)
+#define TCR_PRESCALE_25(25 - 1)
Should this be calculated by NPCM_TIMER_INPUT_RATE/NPCM_TIMER_CLOCK_RATE
Also thanks for including me I always love the attention, but I'm not
sure why I have been CCed in many of you recent patches is there a
reason for this?
Thank you,
Jesse Taube
+
+/*
+ * 24-bits down-counting hw timer.
+ * last_count: last hw counter value.
+ * counter: the value to be returned for get_count ops.
+ */
+struct npcm_timer_priv {
+ void __iomem *base;
+ u32 last_count;
+ u64 counter;
+};
+
+static u64 npcm_timer_get_count(struct udevice *dev)
+{
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ /* The timer is couting down */
+ val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
+ if (val <= priv->last_count)
+ priv->counter += priv->last_count - val;
+ else
+ priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 -
val);
+ priv->last_count = val;
+
+ return priv->counter;
+}
+
+static int npcm_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+ priv->counter = 0;
+ priv->last_count = 0;
+ uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
+
+ if (IS_ENABLED(CONFIG_ARCH_NPCM750)) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /*
+* Configure timer and start
+* periodic mode
+* input clock freq = 25Mhz
+* prescale = 25
+* timer clock rate = 25Mhz/25
+*/
+ writel(0, priv->base + TCR0);
+ writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
+ writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE_25,
+ priv->base + TCR0);
+
+ return 0;
+}
+
+static const struct timer_ops npcm_timer_ops = {
+ .get_count = npcm_timer_get_count,
+};
+
+static const struct udevice_id npcm_timer_ids[] = {
+ { .compatible = "nuvoton,npcm845-time
Re: Please test U-Boot Allwinner F1C100s support
On 1/31/22 08:07, Giulio Benetti wrote: Hi Andre, Il giorno 31 gen 2022, alle ore 13:57, Andre Przywara ha scritto: On Mon, 31 Jan 2022 13:17:52 +0100 Giulio Benetti wrote: Hi All, I've tried several times on both F1C100s and F1C200s, maybe I'm doing something wrong but it doesn't work :-/ I burn sd-card with: # sudo dd if=u-boot-sunxi-with-spl.bin of=/dev/sdb bs=1k seek=8 I've triple-checked that the file has been written there by dumping the sd-card and I see it's written at 0x2000, so 8K offset, like the mangoPI image for example. But no uart output. I haven't looked in detail what would be needed for the SPL part of the MMC driver to really work, I just checked that the base addresses are correct, the pinmux looked alright as well. The DT nodes are not needed for the SPL, and I don't see other changes related to MMC in the original series? Yes that’s true. Do you see UART output from the SPL, or nothing at all? Unfortunately nothing either with SPL And you are not using UART0 on the PortF pins, so multiplexed with the MMC, I guess? I use PE0 and PE1 Uart0 according to dts. Have you got such board to test it? Or we can wait for Jesse or George. I’ve used the git you’ve pointed. Anyway I think we’re very close to have it working. At least my work “behind the scenes” will be worth, right Jesse :-)? Yes, I'm sorry there wasn't much mention of you on this patch. I Just woke up, sorry i couldn't be here earlier, I'll take a look with Giulio. Best regards —- Giulio Benetti Benetti Engineering sas Cheers, Andre Am I doing something wrong? Best regards
Re: Please test U-Boot Allwinner F1C100s support
On 1/30/22 21:04, Andre Przywara wrote:
Hi,
thanks to the tireless work of Jesse, I think the basic Allwinner
F1C100s support for mainline U-Boot is now ready to be merged. Since I
don't have the hardware, can any of you who have boards please give it a
try on their hardware? I would really love to see some confirmations
before I merge it.
I really have to thank you for reviewing!
I put a branch here:
https://source.denx.de/u-boot/custodians/u-boot-sunxi/-/tree/f1c100s
This should probably work on any F1C100s board, using the LicheePi Nano
defconfig. Also curious about the F1C200s (looking at you, George ;-)
I have tested on both. Giulio has them aswell now.
This is very basic support at this point, there is no USB or SPI
support, and even the SD card is not usable from U-Boot proper.
Sd card will work if we add it to the dts.
I am hopeful we can add MMC and SPI support still in this cycle, but I don't
want to hold back this series any longer, and it should be relatively
simple support patches.
I have patches for both spi-boot and U-Boot proper spi suport.
I did manage to get it to find the boot device with:
`u32 brom_call = *(u32*)(fel_stash.sp-4);` in mach-sunxi/board.c with
the suggestion that Stephen said. Should I submit after it gets into
master or is tomorrow fine.
Many thanks,
Jesse Taube
What should work though is booting via FEL and from SD card (the SPL
MMC code is in place, if I am not mistaken). Just booting it to a U-Boot
prompt via both methods would be a great test already. Maybe you can
even upload a kernel and initrd via FEL and boot it from there, using
$fdtcontroladdr for the DT address, for instance.
Any replies would be highly appreciated!
Many thanks,
Andre
Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
On 1/29/22 16:21, Giulio Benetti wrote:
On 29/01/22 22:19, Jesse Taube wrote:
On 1/29/22 16:05, Jesse Taube wrote:
On 1/29/22 15:59, Samuel Holland wrote:
On 1/29/22 5:51 AM, Andre Przywara wrote:
On Fri, 28 Jan 2022 22:21:28 -0500
Jesse Taube wrote:
On 1/26/22 09:38, Jesse Taube wrote:
On 1/26/22 09:13, Andre Przywara wrote:
On Tue, 4 Jan 2022 19:35:06 -0500
Jesse Taube wrote:
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
+#else
+/*
+ * suniv BROM do not pass the boot media type to SPL, so we try with the
+ * boot sequence in BROM: mmc0->spinor->fail.
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+* See the comments above in sunxi_get_boot_device() for information
+* about FEL boot.
+*/
+ if (!is_boot0_magic(SPL_ADDR + 4)) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
So does that mean that it tries MMC first, even when booted via SPI? So if
there is a *non*-bootable microSD card in, it will read something from
sector 80, and will execute that if this is a FIT or legacy image?
yes
Uh sorry to bother you again but I cant seem to find a way to find where
the bootrom got the spl. I could check other periphirals like pinmux. I
could also just have it configured at build. Are both these options
okay? I will try to find a way to find the boot device at runtime first.
Don't bother for this version, it's fine as it is now, we can refine
this later. It's only a problem if there is a non-valid SPL, but a
valid U-Boot proper legacy image on the SD card.
I don't want to have a build time option, we try to keep a single image
for all boot sources.
So eventually I'd prefer the pinmux/clock check, since that's cheaper.
The alternative would be to read the SPL (again), check for a valid
header and verify the checksum. You can look at this for inspiration:
https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przyw...@arm.com/
I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
it loaded SPL from, or make any other changes to the loaded eGON image. The boot
ROM also completely cleans up its clock and pinctrl changes, regardless of the
success/failure of a specific boot device.
There's a function which loads some value to r2, but that gets called before the
"load eGON from storage" functions, so r2 will be clobbered.
So as far as I can tell, the only way to determine the boot device, other than
reimplementing the BROM in SPL, is to look at the return address on the top of
the BROM's stack. These are the possible values (in order of execution):
0x40f8: mmc0
0x4114: spi0 NAND
0x4130: spi0 NOR
0x4150: mmc1
If i save it in save_boot_params it does change when in a different boot
device. Ill look into it more.
the sp is also a good idea.
Sry Im just dumb. it does change but it is because it doesn't clean the
registers.
Thanks sam, looking at the stack is the best option.
I've been too late :-)
Im sorry only by a couple of seconds.
So happy assembly coding Jesse!
Its very difficult :( I'm not used to how it works yet.
Thanks,
Jesse Taube
Best regards
Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
On 1/29/22 16:05, Jesse Taube wrote:
On 1/29/22 15:59, Samuel Holland wrote:
On 1/29/22 5:51 AM, Andre Przywara wrote:
On Fri, 28 Jan 2022 22:21:28 -0500
Jesse Taube wrote:
On 1/26/22 09:38, Jesse Taube wrote:
On 1/26/22 09:13, Andre Przywara wrote:
On Tue, 4 Jan 2022 19:35:06 -0500
Jesse Taube wrote:
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
+#else
+/*
+ * suniv BROM do not pass the boot media type to SPL, so we try with the
+ * boot sequence in BROM: mmc0->spinor->fail.
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+* See the comments above in sunxi_get_boot_device() for information
+* about FEL boot.
+*/
+ if (!is_boot0_magic(SPL_ADDR + 4)) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
So does that mean that it tries MMC first, even when booted via SPI? So if
there is a *non*-bootable microSD card in, it will read something from
sector 80, and will execute that if this is a FIT or legacy image?
yes
Uh sorry to bother you again but I cant seem to find a way to find where
the bootrom got the spl. I could check other periphirals like pinmux. I
could also just have it configured at build. Are both these options
okay? I will try to find a way to find the boot device at runtime first.
Don't bother for this version, it's fine as it is now, we can refine
this later. It's only a problem if there is a non-valid SPL, but a
valid U-Boot proper legacy image on the SD card.
I don't want to have a build time option, we try to keep a single image
for all boot sources.
So eventually I'd prefer the pinmux/clock check, since that's cheaper.
The alternative would be to read the SPL (again), check for a valid
header and verify the checksum. You can look at this for inspiration:
https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przyw...@arm.com/
I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
it loaded SPL from, or make any other changes to the loaded eGON image. The boot
ROM also completely cleans up its clock and pinctrl changes, regardless of the
success/failure of a specific boot device.
There's a function which loads some value to r2, but that gets called before the
"load eGON from storage" functions, so r2 will be clobbered.
So as far as I can tell, the only way to determine the boot device, other than
reimplementing the BROM in SPL, is to look at the return address on the top of
the BROM's stack. These are the possible values (in order of execution):
0x40f8: mmc0
0x4114: spi0 NAND
0x4130: spi0 NOR
0x4150: mmc1
If i save it in save_boot_params it does change when in a different boot
device. Ill look into it more.
the sp is also a good idea.
Sry Im just dumb. it does change but it is because it doesn't clean the
registers.
Thanks sam, looking at the stack is the best option.
Sorry,
Jesse Taube
Regards,
Samuel
Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
On 1/29/22 15:59, Samuel Holland wrote:
On 1/29/22 5:51 AM, Andre Przywara wrote:
On Fri, 28 Jan 2022 22:21:28 -0500
Jesse Taube wrote:
On 1/26/22 09:38, Jesse Taube wrote:
On 1/26/22 09:13, Andre Przywara wrote:
On Tue, 4 Jan 2022 19:35:06 -0500
Jesse Taube wrote:
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
+#else
+/*
+ * suniv BROM do not pass the boot media type to SPL, so we try with the
+ * boot sequence in BROM: mmc0->spinor->fail.
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+* See the comments above in sunxi_get_boot_device() for information
+* about FEL boot.
+*/
+ if (!is_boot0_magic(SPL_ADDR + 4)) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
So does that mean that it tries MMC first, even when booted via SPI? So if
there is a *non*-bootable microSD card in, it will read something from
sector 80, and will execute that if this is a FIT or legacy image?
yes
Uh sorry to bother you again but I cant seem to find a way to find where
the bootrom got the spl. I could check other periphirals like pinmux. I
could also just have it configured at build. Are both these options
okay? I will try to find a way to find the boot device at runtime first.
Don't bother for this version, it's fine as it is now, we can refine
this later. It's only a problem if there is a non-valid SPL, but a
valid U-Boot proper legacy image on the SD card.
I don't want to have a build time option, we try to keep a single image
for all boot sources.
So eventually I'd prefer the pinmux/clock check, since that's cheaper.
The alternative would be to read the SPL (again), check for a valid
header and verify the checksum. You can look at this for inspiration:
https://patchwork.ozlabs.org/project/uboot/patch/20210712100651.6912-3-andre.przyw...@arm.com/
I checked the boot ROM code (thanks Jesse!), and indeed it does not report where
it loaded SPL from, or make any other changes to the loaded eGON image. The boot
ROM also completely cleans up its clock and pinctrl changes, regardless of the
success/failure of a specific boot device.
There's a function which loads some value to r2, but that gets called before the
"load eGON from storage" functions, so r2 will be clobbered.
So as far as I can tell, the only way to determine the boot device, other than
reimplementing the BROM in SPL, is to look at the return address on the top of
the BROM's stack. These are the possible values (in order of execution):
0x40f8: mmc0
0x4114: spi0 NAND
0x4130: spi0 NOR
0x4150: mmc1
If i save it in save_boot_params it does change when in a different boot
device. Ill look into it more.
the sp is also a good idea.
Regards,
Samuel
Re: [PATCH 09/11] sunxi: Add support for SUNIV architecture
On 1/29/22 06:51, Andre Przywara wrote: On Fri, 28 Jan 2022 22:21:28 -0500 Jesse Taube wrote: On 1/26/22 09:38, Jesse Taube wrote: On 1/26/22 09:13, Andre Przywara wrote: On Tue, 4 Jan 2022 19:35:06 -0500 Jesse Taube wrote: Hi Jesse, I was checking some bits and pieces here, so sorry for the delay. I saw your v2, and will review that ASAP, so that we get one step closer. Please don't send a v3 before that. If you have some time, can you also meanwhile check if this series is bisectable, meaning that every patch compiles? I have the feeling there is something off, but didn't check it. Pick an H3 and an A64 board, and compile it after each patch. I can do this as well, if you don't find the time for this. I didnt check for bisectability but i did order the patches to avoid it. In general I am tempted to merge this still in this cycle, since we don't have other big changes, but we would need to settle this by early next week then. See below for more work ;-) (Sorry!) Its okay. From: Icenowy Zheng Add support for the suniv architecture, which is newer ARM9 SoCs by Allwinner. The design of it seems to be a mixture of sun3i, sun4i and sun6i. Signed-off-by: Icenowy Zheng Signed-off-by: Jesse Taube --- arch/arm/mach-sunxi/Kconfig | 16 +-- arch/arm/mach-sunxi/board.c | 31 +++-- arch/arm/mach-sunxi/clock.c | 3 +- arch/arm/mach-sunxi/clock_sun6i.c | 46 ++- arch/arm/mach-sunxi/cpu_info.c| 2 ++ 5 files changed, 91 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 2c18cf02d1..9bb7717731 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,7 +1,8 @@ if ARCH_SUNXI config SPL_LDSCRIPT - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 + default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 && !MACH_SUNIV config IDENT_STRING default " Allwinner Technology" @@ -183,6 +184,12 @@ choice prompt "Sunxi SoC Variant" optional +config MACH_SUNIV + bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)" + select CPU_ARM926EJS + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A @@ -587,6 +594,7 @@ config DRAM_ODT_CORRECTION endif config SYS_CLK_FREQ + default 40800 if MACH_SUNIV default 100800 if MACH_SUN4I default 100800 if MACH_SUN5I default 100800 if MACH_SUN6I @@ -598,6 +606,7 @@ config SYS_CLK_FREQ default 100800 if MACH_SUN50I_H616 config SYS_CONFIG_NAME + default "suniv" if MACH_SUNIV default "sun4i" if MACH_SUN4I default "sun5i" if MACH_SUN5I default "sun6i" if MACH_SUN6I @@ -805,7 +814,7 @@ config VIDEO_SUNXI config VIDEO_HDMI bool "HDMI output support" - depends on VIDEO_SUNXI && !MACH_SUN8I + depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV default y ---help--- Say Y here to add support for outputting video over HDMI. @@ -1005,6 +1014,7 @@ config GMAC_TX_DELAY Set the GMAC Transmit Clock Delay Chain value. config SPL_STACK_R_ADDR + default 0x81e0 if MACH_SUNIV default 0x4fe0 if MACH_SUN4I default 0x4fe0 if MACH_SUN5I default 0x4fe0 if MACH_SUN6I @@ -1016,7 +1026,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV I think this is premature without the corresponding patch to spl_spi_sunxi.c. Ill look into this. help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 3ef179742c..2fee86b49b 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -86,7 +86,8 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); #endif -#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40) +#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \ +defined
[PATCH v3 10/10] configs: sunxi: Add support for Lichee Pi Nano
From: Icenowy Zheng The Lichee Pi Nano is a board based on the F1C100s. Add defconfigs for it. Signed-off-by: Icenowy Zheng Signed-off-by: Jesse Taube --- V1->V2: * Add SKIP_LOWLEVEL_INIT_ONLY * Remove spi defconfig V2->V3: * Move SYS_MALLOC_F_LEN to kconf and format it * Move SYS_LOAD_ADDR to kconf and format it * Move SYS_TEXT_BASE to kconf and format it --- Kconfig | 8 +--- boot/Kconfig| 7 --- configs/licheepi_nano_defconfig | 11 +++ 3 files changed, 20 insertions(+), 6 deletions(-) create mode 100644 configs/licheepi_nano_defconfig diff --git a/Kconfig b/Kconfig index c46f4fce86..ef4e350ea8 100644 --- a/Kconfig +++ b/Kconfig @@ -246,9 +246,10 @@ config SYS_MALLOC_F_LEN config SYS_MALLOC_LEN hex "Define memory for Dynamic allocation" default 0x200 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON - default 0x402 if ARCH_SUNXI && !MACH_SUN8I_V3S default 0x20 if ARCH_BMIPS || X86 - default 0x22 if ARCH_SUNXI && MACH_SUN8I_V3S + default 0x12 if MACH_SUNIV + default 0x22 if MACH_SUN8I_V3S + default 0x402 if ARCH_SUNXI default 0x40 help This defines memory to be allocated for Dynamic allocation @@ -391,8 +392,9 @@ config SYS_LOAD_ADDR hex "Address in memory to use by default" default 0x0100 if ARCH_SOCFPGA default 0x0200 if PPC || X86 + default 0x8100 if MACH_SUNIV default 0x2200 if MACH_SUN9I - default 0x4200 if ARCH_SUNXI && !MACH_SUN9I + default 0x4200 if ARCH_SUNXI default 0x8200 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3 default 0x8200 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL) default 0x1200 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL) diff --git a/boot/Kconfig b/boot/Kconfig index f1ce576ab2..d16acfe563 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -351,9 +351,10 @@ config SYS_TEXT_BASE depends on HAVE_SYS_TEXT_BASE default 0x0 if POSITION_INDEPENDENT default 0x8080 if ARCH_OMAP2PLUS || ARCH_K3 - default 0x4a00 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S - default 0x2a00 if ARCH_SUNXI && MACH_SUN9I - default 0x42e0 if ARCH_SUNXI && MACH_SUN8I_V3S + default 0x8170 if MACH_SUNIV + default 0x2a00 if MACH_SUN9I + default 0x42e0 if MACH_SUN8I_V3S + default 0x4a00 if ARCH_SUNXI hex "Text Base" help The address in memory that U-Boot will be running from, initially. diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig new file mode 100644 index 00..ecec869d18 --- /dev/null +++ b/configs/licheepi_nano_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUNIV=y +CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_DRAM_CLK=156 +CONFIG_SYS_DCACHE_OFF=y +CONFIG_DRAM_ZQ=0 +# CONFIG_VIDEO_SUNXI is not set +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano" +CONFIG_SPL=y -- 2.34.1
[PATCH v3 09/10] ARM: dts: suniv: Add device tree files and bindings for F1C100s
From: Icenowy Zheng
Add device tree files for suniv and
Lichee Pi Nano it is a board based on F1C100s.
dt-bindings/dts are synced with 5.16.0
Signed-off-by: Icenowy Zheng
Signed-off-by: Jesse Taube
---
V1->V2:
* Sync with Linux
* Re-add MMC node
V2->V3:
* Add ifndef for mmc in sunxi-u-boot.dtsi
* Direct copy of all files from linux
* Squash dt-bindings here
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 26
arch/arm/dts/suniv-f1c100s.dtsi | 144 ++
arch/arm/dts/sunxi-u-boot.dtsi| 2 +
include/dt-bindings/clock/suniv-ccu-f1c100s.h | 70 +
include/dt-bindings/reset/suniv-ccu-f1c100s.h | 38 +
6 files changed, 282 insertions(+)
create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi
create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h
create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 453e2fd1a9..07030deeca 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -497,6 +497,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
stm32h743i-eval.dtb \
stm32h750i-art-pi.dtb
+dtb-$(CONFIG_MACH_SUNIV) += \
+ suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
new file mode 100644
index 00..a1154e6c7c
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+/ {
+ model = "Lichee Pi Nano";
+ compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pe_pins>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
new file mode 100644
index 00..6100d3b75f
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s.dtsi
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng
+ * Copyright 2018 Mesih Kilinc
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ clocks {
+ osc24M: clk-24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk-32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ cpus {
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram-controller@1c0 {
+ compatible = "allwinner,suniv-f1c100s-system-control",
+"allwinner,sun4i-a10-system-control";
+ reg = <0x01c0 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_d: sram@1 {
+ compatible = "mmio-sram";
+ reg = <0x0001 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0001 0x1000>;
+
+ otg_sram: sram-section@0 {
+ compatible =
"allwinner,suniv-f1c100s-sram-d",
+
"allwinner,sun4i-a10-sram-d";
+ reg = <0x 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ccu
[PATCH v3 08/10] mach-sunxi: Add support for SUNIV architecture
From: Icenowy Zheng
Add support for the suniv architecture, which is newer ARM9 SoCs by
Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
sun6i.
Signed-off-by: Icenowy Zheng
Signed-off-by: Jesse Taube
---
V1->V2:
* Remove change in s_init (sunxi: remove lowlevel_init)
V2->V3:
* Covert to if(IS_ENABLED) from ifdef
* Remove busy loop
* Remove depends on for SPL_SPI_SUNXI
---
arch/arm/mach-sunxi/Kconfig | 14 -
arch/arm/mach-sunxi/board.c | 28 +-
arch/arm/mach-sunxi/clock.c | 3 +-
arch/arm/mach-sunxi/clock_sun6i.c | 89 +--
arch/arm/mach-sunxi/cpu_info.c| 2 +
5 files changed, 104 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 4e49ad4f0c..11f295033f 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,7 +1,8 @@
if ARCH_SUNXI
config SPL_LDSCRIPT
- default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
+ default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV
+ default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 &&
!MACH_SUNIV
config IDENT_STRING
default " Allwinner Technology"
@@ -183,6 +184,12 @@ choice
prompt "Sunxi SoC Variant"
optional
+config MACH_SUNIV
+ bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
+ select CPU_ARM926EJS
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
config MACH_SUN4I
bool "sun4i (Allwinner A10)"
select CPU_V7A
@@ -585,6 +592,7 @@ config DRAM_ODT_CORRECTION
endif
config SYS_CLK_FREQ
+ default 40800 if MACH_SUNIV
default 100800 if MACH_SUN4I
default 100800 if MACH_SUN5I
default 100800 if MACH_SUN6I
@@ -596,6 +604,7 @@ config SYS_CLK_FREQ
default 100800 if MACH_SUN50I_H616
config SYS_CONFIG_NAME
+ default "suniv" if MACH_SUNIV
default "sun4i" if MACH_SUN4I
default "sun5i" if MACH_SUN5I
default "sun6i" if MACH_SUN6I
@@ -803,7 +812,7 @@ config VIDEO_SUNXI
config VIDEO_HDMI
bool "HDMI output support"
- depends on VIDEO_SUNXI && !MACH_SUN8I
+ depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
default y
---help---
Say Y here to add support for outputting video over HDMI.
@@ -1003,6 +1012,7 @@ config GMAC_TX_DELAY
Set the GMAC Transmit Clock Delay Chain value.
config SPL_STACK_R_ADDR
+ default 0x81e0 if MACH_SUNIV
default 0x4fe0 if MACH_SUN4I
default 0x4fe0 if MACH_SUN5I
default 0x4fe0 if MACH_SUN6I
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index a60dc6b299..2aa30c62c5 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -87,7 +87,8 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
-#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
+#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \
+defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
@@ -95,6 +96,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40))
@@ -271,10 +276,31 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc
*mmc,
return sector;
}
+#ifndef CONFIG_MACH_SUNIV
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
+#else
+/*
+ * suniv BROM do not pass the boot media type to SPL, so we try with the
+ * boot sequence in BROM: mmc0->spinor->fail.
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+* See the comments above in sunxi_get_boot_device() for information
+* about FEL boot.
+*/
+ if (!is_boot0_magic(SPL_ADDR + 4)) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+}
+#endif
__weak void sunxi_sram_init(void)
{
diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
index de7e
[PATCH v3 07/10] configs: sunxi: Add common SUNIV header
From: Icenowy Zheng Adds support for SUNIV and the F1C100s. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara Signed-off-by: Jesse Taube --- V1->V2: * Combine ifdefs * Fix indentation * Fix negative logic * Fix rebase artifacts * Remove CONFIG_SYS_LOAD_ADDR * Remove CONFIG_ENV_SECT_SIZE V2->V3: * Fix comment --- include/configs/suniv.h| 14 + include/configs/sunxi-common.h | 57 +- 2 files changed, 56 insertions(+), 15 deletions(-) create mode 100644 include/configs/suniv.h diff --git a/include/configs/suniv.h b/include/configs/suniv.h new file mode 100644 index 00..6118cd5e1a --- /dev/null +++ b/include/configs/suniv.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for new Allwinner F-series (suniv) CPU + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 01c3cfced2..4bab917c0b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -22,7 +22,12 @@ /* Serial & console */ #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ +#ifdef CONFIG_MACH_SUNIV +/* suniv doesn't have apb2 and uart is connected to apb1 */ +#define CONFIG_SYS_NS16550_CLK 1 +#else #define CONFIG_SYS_NS16550_CLK 2400 +#endif #ifndef CONFIG_DM_SERIAL # define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE @@ -49,6 +54,15 @@ * since it needs to fit in with the other values. By also #defining it * we get warnings if the Kconfig value mismatches. */ #define CONFIG_SPL_BSS_START_ADDR 0x2ff8 +#elif defined(CONFIG_MACH_SUNIV) +#define SDRAM_OFFSET(x) 0x8##x +#define CONFIG_SYS_SDRAM_BASE 0x8000 +/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here + * since it needs to fit in with the other values. By also #defining it + * we get warnings if the Kconfig value mismatches. + */ +#define CONFIG_SPL_STACK_R_ADDR0x81e0 +#define CONFIG_SPL_BSS_START_ADDR 0x81f8 #else #define SDRAM_OFFSET(x) 0x4##x #define CONFIG_SYS_SDRAM_BASE 0x4000 @@ -179,13 +193,40 @@ #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE0)) #define RAMDISK_ADDR_R__stringify(SDRAM_OFFSET(FF0)) +#elif defined(CONFIG_MACH_SUN8I_V3S) +/* + * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. + * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, + * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. + */ +#define BOOTM_SIZE__stringify(0x2e0) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(100)) +#define FDT_ADDR_R__stringify(SDRAM_OFFSET(180)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(190)) +#define PXEFILE_ADDR_R__stringify(SDRAM_OFFSET(1A0)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B0)) +#define RAMDISK_ADDR_R__stringify(SDRAM_OFFSET(1C0)) + +#elif defined(CONFIG_MACH_SUNIV) +/* + * 32M RAM minus 1MB heap + 8MB for u-boot, stack, fb, etc. + * 8M uncompressed kernel, 4M compressed kernel, 512K fdt, + * 512K script, 512K pxe and the ramdisk at the end. + */ +#define BOOTM_SIZE__stringify(0x170) +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(050)) +#define FDT_ADDR_R__stringify(SDRAM_OFFSET(0C0)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(0C5)) +#define PXEFILE_ADDR_R__stringify(SDRAM_OFFSET(0D0)) +#define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(0D5)) +#define RAMDISK_ADDR_R__stringify(SDRAM_OFFSET(0D6)) + #else /* * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. */ -#ifndef CONFIG_MACH_SUN8I_V3S #define BOOTM_SIZE__stringify(0xa00) #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(200)) #define FDT_ADDR_R__stringify(SDRAM_OFFSET(300)) @@ -193,20 +234,6 @@ #define PXEFILE_ADDR_R__stringify(SDRAM_OFFSET(320)) #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(330)) #define RAMDISK_ADDR_R__stringify(SDRAM_OFFSET(340)) -#else -/* - * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. - * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, - * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. - */ -#define BOOTM_SIZE__stringify(0x2e0) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(100)) -#define FDT_ADDR_R__stringify(SDRAM_OFFSET(180)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(190)) -#define PXEFILE_ADDR_R__stringify(SDRAM_OFFSET(1A0)) -#define FDTOVERLAY_ADDR_R __stringify(SDRAM
[PATCH v3 05/10] sunxi: Add F1C100s DRAM initial support
From: Icenowy Zheng
Add support for F1C100s internal dram controller.
Signed-off-by: Icenowy Zheng
Signed-off-by: Jesse Taube
---
V1->V2:
* Nothing done
V2->V3:
* Nothing done
---
arch/arm/include/asm/arch-sunxi/dram.h | 2 +
arch/arm/include/asm/arch-sunxi/dram_suniv.h | 46 ++
arch/arm/mach-sunxi/Makefile | 2 +
arch/arm/mach-sunxi/dram_helpers.c | 4 +
arch/arm/mach-sunxi/dram_suniv.c | 420 +++
5 files changed, 474 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_suniv.h
create mode 100644 arch/arm/mach-sunxi/dram_suniv.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index c3b3e1f512..682daae6b1 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -31,6 +31,8 @@
#include
#elif defined(CONFIG_MACH_SUN50I_H616)
#include
+#elif defined(CONFIG_MACH_SUNIV)
+#include
#else
#include
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_suniv.h
b/arch/arm/include/asm/arch-sunxi/dram_suniv.h
new file mode 100644
index 00..6f4c0512d6
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_suniv.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * suniv DRAM controller register definition
+ *
+ * Copyright (C) 2018 Icenowy Zheng
+ *
+ * Based on xboot's arch/arm32/mach-f1c100s/sys-dram.c, which is:
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192...@qq.com>
+ */
+
+#define PIO_SDRAM_DRV (0x2c0)
+#define PIO_SDRAM_PULL (0x2c4)
+
+#define DRAM_SCONR (0x00)
+#define DRAM_STMG0R(0x04)
+#define DRAM_STMG1R(0x08)
+#define DRAM_SCTLR (0x0c)
+#define DRAM_SREFR (0x10)
+#define DRAM_SEXTMR(0x14)
+#define DRAM_DDLYR (0x24)
+#define DRAM_DADRR (0x28)
+#define DRAM_DVALR (0x2c)
+#define DRAM_DRPTR0(0x30)
+#define DRAM_DRPTR1(0x34)
+#define DRAM_DRPTR2(0x38)
+#define DRAM_DRPTR3(0x3c)
+#define DRAM_SEFR (0x40)
+#define DRAM_MAE (0x44)
+#define DRAM_ASPR (0x48)
+#define DRAM_SDLY0 (0x4C)
+#define DRAM_SDLY1 (0x50)
+#define DRAM_SDLY2 (0x54)
+#define DRAM_MCR0 (0x100)
+#define DRAM_MCR1 (0x104)
+#define DRAM_MCR2 (0x108)
+#define DRAM_MCR3 (0x10c)
+#define DRAM_MCR4 (0x110)
+#define DRAM_MCR5 (0x114)
+#define DRAM_MCR6 (0x118)
+#define DRAM_MCR7 (0x11c)
+#define DRAM_MCR8 (0x120)
+#define DRAM_MCR9 (0x124)
+#define DRAM_MCR10 (0x128)
+#define DRAM_MCR11 (0x12c)
+#define DRAM_BWCR (0x140)
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index b1adb75e17..58f807cb82 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y += dram_helpers.o
obj-y += pinmux.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
+obj-$(CONFIG_MACH_SUNIV) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
@@ -30,6 +31,7 @@ obj-y += timer.o
endif
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o
obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o
obj-$(CONFIG_DRAM_SUN8I_A23) += dram_sun8i_a23.o
diff --git a/arch/arm/mach-sunxi/dram_helpers.c
b/arch/arm/mach-sunxi/dram_helpers.c
index 520b597fcc..2c873192e6 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -26,7 +26,10 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val)
/*
* Test if memory at offset offset matches memory at begin of DRAM
+ *
+ * Note: dsb() is not available on ARMv5 in Thumb mode
*/
+#ifndef CONFIG_MACH_SUNIV
bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
@@ -37,3 +40,4 @@ bool mctl_mem_matches(u32 offset)
return readl(CONFIG_SYS_SDRAM_BASE) ==
readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
}
+#endif
diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c
new file mode 100644
index 00..56c2d557ff
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_suniv.c
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * suniv DRAM initialization
+ *
+ * Copyright (C) 2018 Icenowy Zheng
+ *
+ * Based on xboot&
[PATCH v3 06/10] sunxi: board: Add support for SUNIV
From: Icenowy Zheng
Generic Timer Extension is not available on SUNIV.
Signed-off-by: Icenowy Zheng
Reviewed-by: Andre Przywara
Signed-off-by: Jesse Taube
---
V1->V2:
* Nothing done
V2->V3:
* Nothing done
---
board/sunxi/board.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 2790a0f9e8..59eb195c26 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -197,7 +197,7 @@ int board_init(void)
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
-#ifndef CONFIG_ARM64
+#if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
debug("id_pfr1: 0x%08x\n", id_pfr1);
/* Generic Timer Extension available? */
@@ -224,7 +224,7 @@ int board_init(void)
#endif
}
}
-#endif /* !CONFIG_ARM64 */
+#endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
ret = axp_gpio_init();
if (ret)
--
2.34.1
[PATCH v3 04/10] ARM: sunxi: Add clock and uart to sunxi headers
From: Icenowy Zheng
This patch aims to add header files for the suniv.
The header files included add support for uart, and clocks.
Signed-off-by: Icenowy Zheng
Reviewed-by: Andre Przywara
Signed-off-by: Jesse Taube
---
V1->V2:
* Change commit description and topic
* Change PLL6_CFG_DEFAULT
* Combine APB1_GATE ifdefs
* Combine SUNXI_UART0_BASE ifdefs
* Fix negative logic
* Remove unused macros
V2->V3:
* Nothing done
---
arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 13 +
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 ++
arch/arm/include/asm/arch-sunxi/gpio.h| 1 +
4 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index cbbe5c7a1e..2cfd540742 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -19,7 +19,7 @@
#elif defined(CONFIG_SUN50I_GEN_H6)
#include
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
- defined(CONFIG_MACH_SUN50I)
+ defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
#include
#elif defined(CONFIG_MACH_SUN9I)
#include
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index ee387127f3..7fcf340db6 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -226,7 +226,12 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
+#ifdef CONFIG_MACH_SUNIV
+/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */
+#define PLL6_CFG_DEFAULT 0x90041801
+#else
#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
+#endif
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
@@ -488,6 +493,14 @@ struct sunxi_ccm_reg {
#define AHB_RESET_OFFSET_EPHY 2
#define AHB_RESET_OFFSET_LVDS 0
+/* apb1 reset */
+#ifdef CONFIG_MACH_SUNIV
+#define APB1_GATE_UART_SHIFT (20)
+#define APB1_GATE_TWI_SHIFT(16)
+#define APB1_RESET_UART_SHIFT (20)
+#define APB1_RESET_TWI_SHIFT (16)
+#endif
+
/* apb2 reset */
#define APB2_RESET_UART_SHIFT (16)
#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index d4c795d89c..b7b4564af3 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -129,9 +129,15 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_CPUCFG_BASE 0x01c25c00
#endif
+#ifndef CONFIG_MACH_SUNIV
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
#define SUNXI_UART2_BASE 0x01c28800
+#else
+#define SUNXI_UART0_BASE 0x01c25000
+#define SUNXI_UART1_BASE 0x01c25400
+#define SUNXI_UART2_BASE 0x01c25800
+#endif
#define SUNXI_UART3_BASE 0x01c28c00
#define SUNXI_UART4_BASE 0x01c29000
#define SUNXI_UART5_BASE 0x01c29400
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index f3ab1aea0e..ced69f7dd4 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -165,6 +165,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPD_LVDS03
#define SUNXI_GPD_PWM 2
+#define SUNIV_GPE_UART05
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI23
--
2.34.1
[PATCH v3 03/10] arm: arm926ej-s: Add sunxi code
From: Icenowy Zheng
Some Allwinner SoCs use ARM926EJ-S core.
Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.
Signed-off-by: Icenowy Zheng
Reviewed-by: Andre Przywara
Signed-off-by: Jesse Taube
---
V1->V2:
* Fix Copyright notice
* Remove lowlevel_init
* Remove replaced timer.c
* Remove Read CP15 Control Register
* Remove unused start.c
V2->V3:
* Add sdelay to arm926ejs/cpu.c
---
arch/arm/cpu/arm926ejs/Makefile | 1 +
arch/arm/cpu/arm926ejs/cpu.c| 13 ++
arch/arm/cpu/arm926ejs/sunxi/Makefile | 5 +++
arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 +++
arch/arm/cpu/arm926ejs/sunxi/fel_utils.S| 33 ++
arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 48 +
6 files changed, 106 insertions(+)
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index b901b7c5c9..7f1436d76e 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -15,6 +15,7 @@ endif
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
# some files can only build in ARM or THUMB2, not THUMB1
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index 93d7a02ed4..2ce413a7f8 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -21,6 +21,19 @@
static void cache_flush(void);
+/
+ * sdelay() - simple spin loop. Will be constant time as
+ * its generally used in bypass conditions only. This
+ * is necessary until timers are accessible.
+ *
+ * not inline to increase chances its in cache when called
+ */
+void sdelay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
int cleanup_before_linux (void)
{
/*
diff --git a/arch/arm/cpu/arm926ejs/sunxi/Makefile
b/arch/arm/cpu/arm926ejs/sunxi/Makefile
new file mode 100644
index 00..7d8b959dcd
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2012 Henrik Nordstrom
+
+obj-y += fel_utils.o
+CFLAGS_fel_utils.o := -marm
diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk
b/arch/arm/cpu/arm926ejs/sunxi/config.mk
new file mode 100644
index 00..76ffec9df6
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk
@@ -0,0 +1,6 @@
+# Build a combined spl + u-boot image
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+ALL-y += u-boot-sunxi-with-spl.bin
+endif
+endif
diff --git a/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
new file mode 100644
index 00..08be7ed11a
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Utility functions for FEL mode.
+ *
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#include
+#include
+#include
+#include
+
+ENTRY(save_boot_params)
+ ldr r0, =fel_stash
+ str sp, [r0, #0]
+ str lr, [r0, #4]
+ mrs lr, cpsr@ Read CPSR
+ str lr, [r0, #8]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
+ str lr, [r0, #12]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(return_to_fel)
+ mov sp, r0
+ mov lr, r1
+ ldr r0, =fel_stash
+ ldr r1, [r0, #16]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
+ ldr r1, [r0, #12]
+ msr cpsr, r1@ Write CPSR
+ bx lr
+ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
new file mode 100644
index 00..9a000ac5d3
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Icenowy Zheng
+ *
+ * Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds:
+ */
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ *(.text*)
+ } > .sram
+
+ . = AL
[PATCH v3 01/10] arm: arm926ej-s: start.S: port save_boot_params support from armv7 code
From: Icenowy Zheng The ARMv7 start code has support for saving some boot params at the entry point, which is used by some SoCs to return to BROM. Port this to ARM926EJ-S start code. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara Signed-off-by: Jesse Taube --- V1->V2: * Nothing done V2->V3: * Nothing done --- arch/arm/cpu/arm926ejs/start.S | 19 +++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 0afcc47aad..aca7793c57 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -17,6 +17,7 @@ #include #include #include +#include /* * @@ -32,8 +33,13 @@ */ .globl reset + .globl save_boot_params_ret + .type save_boot_params_ret,%function reset: + /* Allow the board to save important registers */ + b save_boot_params +save_boot_params_ret: /* * set the cpu to SVC32 mode */ @@ -110,3 +116,16 @@ flush_dcache: #endif mov pc, lr /* back to my caller */ #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ + +/* + * + * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) + * __attribute__((weak)); + * + * Stack pointer is not yet initialized at this moment + * Don't save anything to stack even if compiled with -O0 + * + */ +WEAK(save_boot_params) + b save_boot_params_ret/* back to my caller */ +ENDPROC(save_boot_params) -- 2.34.1
