Re: [U-Boot] [PATCH] eth: mtk-eth: fix incorrect read of phy-handle
On Sun, Apr 28, 2019 at 2:09 AM Weijie Gao wrote:
>
> In mt7629-rfb.dts, the phy-handle is a reference to the node phy0, not the
> node itself:
>
> phy-handle = <&phy0>;
>
> phy0: ethernet-phy@0 {
> reg = <0>;
> }
>
> However the driver used ofnode_find_subnode("phy-handle") to read the node.
> It will always fail.
>
> This patch replaces ofnode_find_subnode with dev_read_phandle_with_args to
> make sure the node can be read correctly.
>
> Cc: Joe Hershberger
> Signed-off-by: Weijie Gao
Acked-by: Joe Hershberger
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-net.git master
Hi Tom, This is the series with the AR8xxx phy series removed until we figure it out. Tested to work fine on your evm. The following changes since commit 8d7f06bbbef16f172cd5e9c4923cdcebe16b8980: Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-05-07 09:38:00 -0400) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to 6314d1c8c035d1c4d14ea1ffd133f25385edd067: net: phy: micrel: Find Micrel PHY node correctly (2019-05-08 17:27:01 -0500) Carlo Caione (4): net: phy: Add generic helpers to access MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Switch to generic helpers when accessing the registers net: phy: realtek: Introduce quirk to mark RXC not stoppable James Byrne (2): net: phy: micrel: Use correct skew values on KSZ9021 net: phy: micrel: Find Micrel PHY node correctly Murali Karicheri (2): ARM: k2g-gp-evm: update to rgmii pinmux configuration ARM: k2g-ice: Add pinmux support for rgmii interface Pankaj Bansal (1): drivers: net: ldpaa_eth: fix resource leak Siva Durga Prasad Paladugu (2): net: phy: Reloc next and prev pointers inside phy_drivers net: phy: Fix return value check phy_probe Valentin-catalin Neacsu (1): net: phy: aquantia: Set only autoneg on in register 4.c441 arch/arm/dts/sama5d3xcm.dtsi| 32 +++--- arch/arm/dts/sama5d3xcm_cmp.dtsi| 32 +++--- arch/arm/dts/socfpga_arria5_socdk.dts | 4 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 4 +- arch/arm/dts/socfpga_cyclone5_socdk.dts | 4 +- arch/arm/dts/socfpga_cyclone5_sockit.dts| 4 +- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 4 +- board/ti/ks2_evm/mux-k2g.h | 36 +++ cmd/mdio.c | 27 +++-- doc/device-tree-bindings/net/micrel-ksz90x1.txt | 27 + drivers/net/ldpaa_eth/ldpaa_eth.c | 1 + drivers/net/phy/Kconfig | 20 drivers/net/phy/aquantia.c | 7 +- drivers/net/phy/micrel_ksz90x1.c| 24 - drivers/net/phy/phy.c | 21 +++- drivers/net/phy/realtek.c | 19 drivers/net/phy/ti.c| 130 +--- include/phy.h | 70 + 18 files changed, 283 insertions(+), 183 deletions(-) Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-net.git master
On Tue, May 7, 2019 at 5:15 PM Joe Hershberger wrote: > > Hi Tom, > > The following changes since commit 8d7f06bbbef16f172cd5e9c4923cdcebe16b8980: > > I rebased on your master and built for BB Black. DHCP seems to work fine. > MLO also now fits again. > > Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-05-07 09:38:00 > -0400) > > are available in the git repository at: > > git://git.denx.de/u-boot-net.git master > > for you to fetch changes up to 8d0c6858455e89b089222a08d55ff711681ca011: > > net: phy: micrel: Find Micrel PHY node correctly (2019-05-07 14:51:55 -0500) > > > Carlo Caione (4): > net: phy: Add generic helpers to access MMD PHY registers > net: phy: ti: use generic helpers to access MMD registers > cmd: mdio: Switch to generic helpers when accessing the registers > net: phy: realtek: Introduce quirk to mark RXC not stoppable > > James Byrne (2): > net: phy: micrel: Use correct skew values on KSZ9021 > net: phy: micrel: Find Micrel PHY node correctly > > Murali Karicheri (2): > ARM: k2g-gp-evm: update to rgmii pinmux configuration > ARM: k2g-ice: Add pinmux support for rgmii interface > > Pankaj Bansal (1): > drivers: net: ldpaa_eth: fix resource leak > > Siva Durga Prasad Paladugu (2): > net: phy: Reloc next and prev pointers inside phy_drivers > net: phy: Fix return value check phy_probe > > Valentin-catalin Neacsu (1): > net: phy: aquantia: Set only autoneg on in register 4.c441 > > Vladimir Oltean (6): > net: phy: ar803x: Address packet drops at low traffic rate due to > SmartEEE feature > net: phy: ar803x: Make RGMII Tx delays actually configurable for AR8035 > net: phy: ar803x: Use common functions for RGMII internal delays > net: phy: ar803x: Clarify the configuration of the CLK_25M output pin > net: phy: ar803x: Explicitly disable RGMII delays Tom, this [1] is the patch that is breaking the evm. It doesn't affect BB Black because it uses an SMSC phy, where as this evm uses an AR8031/AR8033. Is it possible the device tree [2] is wrong for the board? It lists 'phy-mode = "rgmii-txid";', so that means that with this patch the RX delay is now being disabled. Any thoughts, Vladimir? Thanks, -Joe [1] b3224e0f7e - "net: phy: ar803x: Explicitly disable RGMII delays" [2] arch/arm/dts/am335x-evm.dts > net: phy: ar803x: Clarify the intention of ar8021_config > > arch/arm/dts/sama5d3xcm.dtsi| 32 +++--- > arch/arm/dts/sama5d3xcm_cmp.dtsi| 32 +++--- > arch/arm/dts/socfpga_arria5_socdk.dts | 4 +- > arch/arm/dts/socfpga_cyclone5_is1.dts | 4 +- > arch/arm/dts/socfpga_cyclone5_socdk.dts | 4 +- > arch/arm/dts/socfpga_cyclone5_sockit.dts| 4 +- > arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 4 +- > board/ti/ks2_evm/mux-k2g.h | 36 +++ > cmd/mdio.c | 27 +++-- > doc/device-tree-bindings/net/micrel-ksz90x1.txt | 27 + > drivers/net/ldpaa_eth/ldpaa_eth.c | 1 + > drivers/net/phy/Kconfig | 41 > drivers/net/phy/aquantia.c | 7 +- > drivers/net/phy/atheros.c | 128 --- > drivers/net/phy/micrel_ksz90x1.c| 24 - > drivers/net/phy/phy.c | 21 +++- > drivers/net/phy/realtek.c | 19 > drivers/net/phy/ti.c| 130 > +--- > include/phy.h | 70 + > 19 files changed, 394 insertions(+), 221 deletions(-) > > Thanks! > -Joe > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: mvpp2: support setting hardware addresses from ethernet core
On Wed, May 8, 2019 at 2:36 PM Matt Pelland wrote: > > mvpp2 already has support for setting MAC addresses but this > functionality was not exposed to the ethernet core. This commit exposes > this functionality so that MAC address assignments stored in U-Boot's > environment are correctly applied before Linux boots. > > Signed-off-by: Matt Pelland Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-net.git master
Hi Tom, The following changes since commit 8d7f06bbbef16f172cd5e9c4923cdcebe16b8980: I rebased on your master and built for BB Black. DHCP seems to work fine. MLO also now fits again. Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-05-07 09:38:00 -0400) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to 8d0c6858455e89b089222a08d55ff711681ca011: net: phy: micrel: Find Micrel PHY node correctly (2019-05-07 14:51:55 -0500) Carlo Caione (4): net: phy: Add generic helpers to access MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Switch to generic helpers when accessing the registers net: phy: realtek: Introduce quirk to mark RXC not stoppable James Byrne (2): net: phy: micrel: Use correct skew values on KSZ9021 net: phy: micrel: Find Micrel PHY node correctly Murali Karicheri (2): ARM: k2g-gp-evm: update to rgmii pinmux configuration ARM: k2g-ice: Add pinmux support for rgmii interface Pankaj Bansal (1): drivers: net: ldpaa_eth: fix resource leak Siva Durga Prasad Paladugu (2): net: phy: Reloc next and prev pointers inside phy_drivers net: phy: Fix return value check phy_probe Valentin-catalin Neacsu (1): net: phy: aquantia: Set only autoneg on in register 4.c441 Vladimir Oltean (6): net: phy: ar803x: Address packet drops at low traffic rate due to SmartEEE feature net: phy: ar803x: Make RGMII Tx delays actually configurable for AR8035 net: phy: ar803x: Use common functions for RGMII internal delays net: phy: ar803x: Clarify the configuration of the CLK_25M output pin net: phy: ar803x: Explicitly disable RGMII delays net: phy: ar803x: Clarify the intention of ar8021_config arch/arm/dts/sama5d3xcm.dtsi| 32 +++--- arch/arm/dts/sama5d3xcm_cmp.dtsi| 32 +++--- arch/arm/dts/socfpga_arria5_socdk.dts | 4 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 4 +- arch/arm/dts/socfpga_cyclone5_socdk.dts | 4 +- arch/arm/dts/socfpga_cyclone5_sockit.dts| 4 +- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 4 +- board/ti/ks2_evm/mux-k2g.h | 36 +++ cmd/mdio.c | 27 +++-- doc/device-tree-bindings/net/micrel-ksz90x1.txt | 27 + drivers/net/ldpaa_eth/ldpaa_eth.c | 1 + drivers/net/phy/Kconfig | 41 drivers/net/phy/aquantia.c | 7 +- drivers/net/phy/atheros.c | 128 --- drivers/net/phy/micrel_ksz90x1.c| 24 - drivers/net/phy/phy.c | 21 +++- drivers/net/phy/realtek.c | 19 drivers/net/phy/ti.c| 130 +--- include/phy.h | 70 + 19 files changed, 394 insertions(+), 221 deletions(-) Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-net.git master
On Tue, Apr 30, 2019 at 4:29 PM Tom Rini wrote: > > On Tue, Apr 30, 2019 at 09:15:33PM +0000, Joe Hershberger wrote: > > On Tue, Mar 19, 2019 at 5:41 PM Tom Rini wrote: > > > > > > On Tue, Mar 12, 2019 at 01:15:46PM -0500, Joe Hershberger wrote: > > > > > > > Hi Tom, > > > > > > > > These patches passed the CI build here: > > > > https://travis-ci.org/jhershbe/u-boot/builds/501807294 > > > > > > > > The following changes since commit > > > > 2e8092d94f40a5692baf3ec768ce3216a7bf032a: > > > > > > > > Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2019-03-11 > > > > 15:48:57 -0400) > > > > > > > > are available in the git repository at: > > > > > > > > > > > > git://git.denx.de/u-boot-net.git master > > > > > > > > for you to fetch changes up to 85f05f72bacc2d047731fc64801e4f6b34cf: > > > > > > > > net: phy: aquantia: Set only autoneg on in register 4.c441 > > > > (2019-03-12 13:13:37 -0500) > > > > > > > > > > NAK. One of: > > > The first bad commit could be any of: > > > 30b2ca2e0fa274b875bb56f541b7dd33ce93c1d1 > > > 8860e1563f38d16f7ae29053018cd445c0fa111d > > > ebb5027d69196dd83fd0fa5bd91fca07acfd77be > > > 09e0a36497c84273e5b22488d5af01bf0ba17469 > > > 841b9df209e37fe1bfefa5f44e837a0ad497443f > > > 15e67d1cdc7258c0c07ad1fd6c2818f7e9f52447 > > > 7aadf5134f2f5771689d0657b69875d0a464859d > > > d35488518f3c16d305092c816a5129f45a0b62d7 > > > Breaks am335x_evm ethernet: > > > 18:39:52 => => dhcp > > > 18:39:52 ethernet@4a10 Waiting for PHY auto negotiation to > > > complete... done > > > 18:39:52 link up on port 0, speed 1000, full duplex > > > 18:39:52 BOOTP broadcast 1 > > > 18:39:52 BOOTP broadcast 2 > > > 18:39:52 BOOTP broadcast 3 > > > 18:39:52 BOOTP broadcast 4 > > > 18:39:52 BOOTP broadcast 5 > > > 18:39:52 BOOTP broadcast 6 > > > 18:39:52 BOOTP broadcast 7 > > > 18:39:52 BOOTP broadcast 8 > > > 18:39:52 BOOTP broadcast 9 > > > 18:39:52 BOOTP broadcast 10 > > > 18:39:52 BOOTP broadcast 11 > > > 18:39:52 BOOTP broadcast 12 > > > 18:39:52 BOOTP broadcast 13 > > > 18:39:52 BOOTP broadcast 14 > > > 18:39:52 BOOTP broadcast 15 > > > 18:39:52 BOOTP broadcast 16 > > > 18:39:52 BOOTP broadcast 17 > > > > I rebased the series on the current master and I can't reproduce this > > dhcp issue. On the original series I saw broken DHCP only with "net: > > phy: micrel: Use correct skew values on KSZ9021" which doesn't make > > any sense because that phy is not used on BBB and isn't even compiled > > in. Also, the issue doesn't reproduce when the next patch is applied. > > Even that oddity doesn't happen after the rebase. > > > > Also the SPL for boneblack is too big to build with some of the > > patches in this series now, so I'm not sure how that should be > > handled. > > Drop those parts for now I guess and we'll have to look harder at them > stand-alone? And I assume you mean am335x_boneblack_vboot is too large? > Or am335x_evm itself? Thanks! Meaning the SPL part of am335x_evm target fails by a few hundred bytes. > -- > Tom > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-net.git master
On Tue, Mar 19, 2019 at 5:41 PM Tom Rini wrote: > > On Tue, Mar 12, 2019 at 01:15:46PM -0500, Joe Hershberger wrote: > > > Hi Tom, > > > > These patches passed the CI build here: > > https://travis-ci.org/jhershbe/u-boot/builds/501807294 > > > > The following changes since commit 2e8092d94f40a5692baf3ec768ce3216a7bf032a: > > > > Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2019-03-11 > > 15:48:57 -0400) > > > > are available in the git repository at: > > > > > > git://git.denx.de/u-boot-net.git master > > > > for you to fetch changes up to 85f05f72bacc2d047731fc64801e4f6b34cf: > > > > net: phy: aquantia: Set only autoneg on in register 4.c441 (2019-03-12 > > 13:13:37 -0500) > > > > NAK. One of: > The first bad commit could be any of: > 30b2ca2e0fa274b875bb56f541b7dd33ce93c1d1 > 8860e1563f38d16f7ae29053018cd445c0fa111d > ebb5027d69196dd83fd0fa5bd91fca07acfd77be > 09e0a36497c84273e5b22488d5af01bf0ba17469 > 841b9df209e37fe1bfefa5f44e837a0ad497443f > 15e67d1cdc7258c0c07ad1fd6c2818f7e9f52447 > 7aadf5134f2f5771689d0657b69875d0a464859d > d35488518f3c16d305092c816a5129f45a0b62d7 > Breaks am335x_evm ethernet: > 18:39:52 => => dhcp > 18:39:52 ethernet@4a10 Waiting for PHY auto negotiation to > complete... done > 18:39:52 link up on port 0, speed 1000, full duplex > 18:39:52 BOOTP broadcast 1 > 18:39:52 BOOTP broadcast 2 > 18:39:52 BOOTP broadcast 3 > 18:39:52 BOOTP broadcast 4 > 18:39:52 BOOTP broadcast 5 > 18:39:52 BOOTP broadcast 6 > 18:39:52 BOOTP broadcast 7 > 18:39:52 BOOTP broadcast 8 > 18:39:52 BOOTP broadcast 9 > 18:39:52 BOOTP broadcast 10 > 18:39:52 BOOTP broadcast 11 > 18:39:52 BOOTP broadcast 12 > 18:39:52 BOOTP broadcast 13 > 18:39:52 BOOTP broadcast 14 > 18:39:52 BOOTP broadcast 15 > 18:39:52 BOOTP broadcast 16 > 18:39:52 BOOTP broadcast 17 I rebased the series on the current master and I can't reproduce this dhcp issue. On the original series I saw broken DHCP only with "net: phy: micrel: Use correct skew values on KSZ9021" which doesn't make any sense because that phy is not used on BBB and isn't even compiled in. Also, the issue doesn't reproduce when the next patch is applied. Even that oddity doesn't happen after the rebase. Also the SPL for boneblack is too big to build with some of the patches in this series now, so I'm not sure how that should be handled. Thanks, -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [REGRESSION] [PATCH] imx: add lowlevel init for ARM64
> On Apr 28, 2019, at 12:52 PM, Stefano Babic wrote:
>
>
>
>> On 27/04/19 01:58, Peng Fan wrote:
>> Hi Marcel,
>>
>> Please apply this patch, Joe has not pick it up.
>> https://patchwork.ozlabs.org/patch/1085432/
>>
>> Stefano,
>>
>> Would you pick it up?
>
> It is acked by Joe, i assign the patch to me in patchwork and I pick it up.
>
> Regards,
> Stefano
>
>>
>>
>>> Subject: [REGRESSION] [PATCH] imx: add lowlevel init for ARM64
>>>
>>> Hi Peng and Stefano
>>>
>>> Unfortunately, this seems to break Ethernet on Colibri iMX8X:
Has this been addressed?
>>>
>>> => dhcp
>>> "Error" handler, esr 0xbf02
>>> elr: 80049664 lr : 8004964c (reloc)
>>> elr: ffef6664 lr : ffef664c
>>> x0 : 5b040288 x1 : 0001
>>> x2 : fd6c5ff4 x3 : 0020
>>> x4 : fd6c5ff0 x5 : 0020
>>> x6 : ffef079c x7 : fd6f1600
>>> x8 : 0044 x9 : 0008
>>> x10: fd6d1620 x11: fd6d3a10
>>> x12: x13: 0200
>>> x14: fd6c62cc x15: 0002
>>> x16: 2080 x17:
>>> x18: fd6cada8 x19: fd6d1160
>>> x20: 0200 x21: 5b040300
>>> x22: fd6f1000 x23: fd6cfdf0
>>> x24: 8000 x25:
>>> x26: x27:
>>> x28: fd6d15c0 x29: fd6c6030
>>>
>>> Resetting CPU ...
>>>
>>> resetting ...
>>>
>>> Reverting commit 5955c6eeb453 ("imx: add lowlevel init for ARM64") makes
>>> it work again.
>>>
>>> Unfortunately, I don't have a MEK in my home office but will check Ethernet
>>> operation there on Monday as well.
>>>
>>> Anyway, does anybody know what exactly is going on?
>>
>> Regards,
>> Peng.
>>
>>>
>>> Cheers
>>>
>>> Marcel
>>>
On Mon, 2019-04-15 at 05:20 +, Peng Fan wrote:
Sometimes we met SERROR, but only to catch it when Linux boots up.
Let's enable catching in U-Boot to catch it ealier and ease debug.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/lowlevel.S | 22 ++
2 files changed, 23 insertions(+), 1 deletion(-) create mode 100644
arch/arm/mach-imx/lowlevel.S
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c3ed62aed6..37675d0558 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -204,7 +204,7 @@ endif
targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-
dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
-obj-$(CONFIG_ARM64) += sip.o
+obj-$(CONFIG_ARM64) += lowlevel.o sip.o
obj-$(CONFIG_MX5) += mx5/
obj-$(CONFIG_MX6) += mx6/
diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-
imx/lowlevel.S new file mode 100644 index 00..158fdb7d87
--- /dev/null
+++ b/arch/arm/mach-imx/lowlevel.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+
+ENTRY(lowlevel_init)
+mrsx0, CurrentEL
+cmpx0, #8
+b.eq1f
+ret
+1:
+msr daifclr, #4
+
+/* set HCR_EL2.AMO to catch SERROR */
+mrsx0, hcr_el2
+orrx0, x0, #0x20
+msrhcr_el2, x0
+isb
+ret
+ENDPROC(lowlevel_init)
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>>> s.denx.de%2Flistinfo%2Fu-boot&data=02%7C01%7Cpeng.fan%40nxp.co
>>> m%7C
>>> d671eca9f1cc4d06a7d008d6ca7661b1%7C686ea1d3bc2b4c6fa92cd99c5c30
>>> 1635%7C
>>> 0%7C0%7C636919007134459412&sdata=R6xBpoVJHL7meQkRkBi1I8vg
>>> MgOTXlFEA
QfMePrDdSc%3D&reserved=0
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH 1/2] net: rtl8169: Implement ->hwaddr_write() callback
Hi Thierry, On Thu, Apr 25, 2019 at 8:32 AM Thierry Reding wrote: > > On Tue, Apr 16, 2019 at 04:36:16PM +0000, Joe Hershberger wrote: > > On Tue, Apr 16, 2019 at 11:21 AM Thierry Reding > > wrote: > > > > > > From: Thierry Reding > > > > > > Implement this callback that allows the MAC address to be set for the > > > Ethernet card. This is necessary in order for the device to be able to > > > receive packets for the MAC address that U-Boot advertises. > > > > > > Signed-off-by: Thierry Reding > > > > Acked-by: Joe Hershberger > > Hi Joe, > > it's not clear to me who you expect to pick this (and patch 2/2) up. I > didn't Cc anyone, so nobody else may consider themselves responsible for > these. > > Did you mean to pick these up yourself or should they go via Simon's DT > tree along with the two eth-uclass patches that I sent? Or perhaps TomR > handles these patches directly? MAINTAINERS clearly identifies you as a > maintainer for the u-boot-net tree, so I was expecting you to pick them > up. Let me know if I should resend these to someone else with your > Acked-by. Yes, I expect to pick these through my tree, but there are two circumstances slowing that. One is that the last series I pulled into my tree included a breaking change, and Tom asked me to identify that patch and reject it. That means I need to reproduce it. That leads to the next problem... I've been travelling most of this month and haven't reproduced the issue yet. When I get my tree unclogged, I'll be pulling these patches as well as all others Acked and delegated to me in patchwork. Cheers, -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] net: eth-uclass: Write MAC address to hardware after probe
On Tue, Apr 16, 2019 at 11:24 AM Thierry Reding wrote: > > From: Thierry Reding > > In order for the device to use the proper MAC address, which can have > been configured in the environment prior to the device being registered, > ensure that the MAC address is written after the device has been probed. > For devices that are registered before the network stack is initialized, > this is already done during eth_initialize(). If the Ethernet device is > on a bus that is not initialized on early boot, such as PCI, the device > is not available at the time eth_initialize() is called, so we need the > MAC address programming to also happen after probe. > > Signed-off-by: Thierry Reding Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH 2/2] net: rtl8169: Support RTL-8168h/8111h
On Tue, Apr 16, 2019 at 11:21 AM Thierry Reding wrote: > > From: Thierry Reding > > This version of the RTL-8168 is present on some development boards and > is compatible with this driver. Add support for identifying this version > of the chip so that U-Boot won't complain about it being unknown. > > Signed-off-by: Thierry Reding Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH 1/2] net: rtl8169: Implement ->hwaddr_write() callback
On Tue, Apr 16, 2019 at 11:21 AM Thierry Reding wrote: > > From: Thierry Reding > > Implement this callback that allows the MAC address to be set for the > Ethernet card. This is necessary in order for the device to be able to > receive packets for the MAC address that U-Boot advertises. > > Signed-off-by: Thierry Reding Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] net: eth-uclass: Support device tree MAC addresses
On Mon, Apr 15, 2019 at 4:11 AM Thierry Reding wrote: > > From: Thierry Reding > > Add the standard Ethernet device tree bindings (imported from v5.0 of > the Linux kernel) and implement support for reading the MAC address for > Ethernet devices in the Ethernet uclass. If the "mac-address" property > exists, the MAC address will be parsed from that. If that property does > not exist, the "local-mac-address" property will be tried as fallback. > > MAC addresses from device tree take precedence over the ones stored in > a network interface card's ROM. > > Signed-off-by: Thierry Reding Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] net: eth-uclass: Write MAC address to hardware after probe
On Mon, Apr 15, 2019 at 4:11 AM Thierry Reding wrote: > > From: Thierry Reding > > In order for the device to use the proper MAC address, which can have > been configured in the environment prior to the device being registered, > ensure that the MAC address is written after the device has been probed. > For devices that are registered before the network stack is initialized, > this is already done during eth_initialize(). If the Ethernet device is > on a bus that is not initialized on early boot, such as PCI, the device > is not available at the time eth_initialize() is called, so we need the > MAC address programming to also happen after probe. I would expect to also see a removal of the call in eth_initialize, right? Why do it both places? > Signed-off-by: Thierry Reding > --- > net/eth-uclass.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/net/eth-uclass.c b/net/eth-uclass.c > index 2ef20df19203..4225aabf1fa1 100644 > --- a/net/eth-uclass.c > +++ b/net/eth-uclass.c > @@ -524,6 +524,8 @@ static int eth_post_probe(struct udevice *dev) > #endif > } > > + eth_write_hwaddr(dev); > + > return 0; > } > > -- > 2.21.0 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] dm: core: Add dev_read_bytes()
On Mon, Apr 15, 2019 at 4:11 AM Thierry Reding wrote: > > From: Thierry Reding > > This function can be used to read a binary property into a buffer. One > example where this is needed is to read a MAC address from device tree. > > Signed-off-by: Thierry Reding Is there a reason dev_read_u8_array_ptr is insuffient? Thanks, -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: fec_mxc: not access reserved register on i.MX8
On Mon, Apr 15, 2019 at 12:18 AM Peng Fan wrote: > > We should not access reserved register on i.MX8, otherwise met SERROR > > Signed-off-by: Peng Fan Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] phy: ti: Init node before reading
Hi Michal, On Tue, Apr 9, 2019 at 5:51 AM Michal Simek wrote: > > On 17. 03. 19 0:06, Hannes Schmelzer wrote: > > "U-Boot" schrieb am 16.03.2019 12:43:17: > > > >> Von: Michal Simek > >> An: u-boot@lists.denx.de > >> Kopie: Janine Hagemann , Joe Hershberger > >> , Hannes Schmelzer > >> Datum: 16.03.2019 12:43 > >> Betreff: [U-Boot] [PATCH] phy: ti: Init node before reading > >> Gesendet von: "U-Boot" > >> > >> There is a need to fill node before clk_output_sel is setup. > >> > >> Signed-off-by: Michal Simek > >> Acked-by: Siva Durga Prasad Paladugu > >> --- > >> > >> drivers/net/phy/ti.c | 8 > >> 1 file changed, 4 insertions(+), 4 deletions(-) > > > > Reviewed-by: > > Joe: Do you want to take it via your net tree? Sure, I'll take it through my tree. I have to figure out which patch on my tree is breaking Tom's board, but once I get that figured out, I'll be pulling things in. I see it is already delegated to me in patchwork. Thanks, -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: macb: Add small delay after link establishment
On Wed, Mar 27, 2019 at 5:20 AM Stefan Roese wrote: > > I've noticed that the first ethernet packet after PHY link establishment > is not tranferred correctly most of the time on my AT91SAM9G25 board. > Here I usually see a timeout of a few seconds, which is quite > annoying. > > Adding a small delay (10ms in this case) after the link establishment > helps to solve this problem. With this patch applied, this timeout > on the first packet is not seen any more. > > Signed-off-by: Stefan Roese > Cc: Wenyou Yang > Cc: Eugen Hristev > Cc: Joe Hershberger Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/4] reset: add polarity field into struct reset_ctl
On Wed, Mar 20, 2019 at 2:34 AM Shawn Guo wrote: > > Some reset controllers support different polarities for reset operation, > so let's add a polarity field into struct reset_ctl. > > Signed-off-by: Shawn Guo Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/4] poplar: enable Ethernet driver support
On Wed, Mar 20, 2019 at 2:34 AM Shawn Guo wrote: > > The 'phy' reset of gmac device in kernel device tree is not generic > enough for u-boot to use, so we need to overwrite the 'resets' property > as needed. With this device tree fixup and poplar_defconfig changes, > Ethernet starts working on Poplar board. > > Signed-off-by: Shawn Guo Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/4] Add Ethernet support for Poplar board
On Tue, Mar 26, 2019 at 2:36 AM Shawn Guo wrote: > > Hi Joe, > > On Wed, Mar 20, 2019 at 03:32:37PM +0800, Shawn Guo wrote: > > The series adds Ethernet support for Poplar board. It firstly creates > > a reset driver for HiSilicon platform, then introduces higmacv300 > > Ethernet driver, and finally enables Ethernet support for Poplar board. > > > > Changes for v4: > > - Add a polarity field into struct reset_ctl. > > - Instead of defining custom macros for polarity, use generic ones > >in include/dt-bindings/reset/ti-syscon.h. > > - Use .data field as register offset and .id field as bit shift. > > How is this version? Any comments there? Looks great! Thanks! > > Shawn > > > Changes for v3: > > - Add polarity support into reset driver, so that we can drop the > >hacking on gmac reset sequence from higmacv300 driver. > > Changes for v2: > > - Rename driver symbol to HIGMACV300_ETH. > > - Remove the use of temp variable 'addr' in higmac_recv(). > > - Simplify the return of function higmac_ofdata_to_platdata() and > >higmac_probe(). > > - Combine delaration and initialization for phyintf in function > >higmac_ofdata_to_platdata(). > > - Eliminate the MDIO read/write macros. > > - Use wait_for_bit_le32() for MDIO command completion polling. > > - Set up RX packet buffers in RX_FQ descriptor at initialization time, > >so that we do not need to allocate/free packet buffers repeatedly. > > - Inform GMAC that the RX descriptor is no longer in use in function > >higmac_free_pkt(). > > - Define BITS_DESC_ENA instead of using magic number 0xf. > > > > Shawn Guo (4): > > reset: add polarity field into struct reset_ctl > > reset: add reset driver for HiSilicon platform > > net: add higmacv300 Ethernet driver for HiSilicon platform > > poplar: enable Ethernet driver support > > > > arch/arm/dts/hi3798cv200-u-boot.dtsi | 14 + > > configs/poplar_defconfig | 3 + > > drivers/net/Kconfig | 9 + > > drivers/net/Makefile | 1 + > > drivers/net/higmacv300.c | 597 +++ > > drivers/reset/Kconfig| 6 + > > drivers/reset/Makefile | 1 + > > drivers/reset/reset-hisilicon.c | 103 + > > include/reset.h | 3 + > > 9 files changed, 737 insertions(+) > > create mode 100644 drivers/net/higmacv300.c > > create mode 100644 drivers/reset/reset-hisilicon.c > > > > -- > > 2.18.0 > > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/4] reset: add reset driver for HiSilicon platform
On Wed, Mar 20, 2019 at 2:34 AM Shawn Guo wrote: > > It adds a Driver Model compatible reset driver for HiSlicon platform. > The driver implements a custom .of_xlate function, and uses .data field > as reset register offset and .id field as bit shift. > > Signed-off-by: Shawn Guo Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/3] poplar: enable Ethernet driver support
On Sun, Mar 10, 2019 at 3:53 AM Shawn Guo wrote:
>
> The 'phy' reset of gmac device in kernel device tree is not generic
> enough for u-boot to use, so we need to overwrite the 'resets' property
> as needed. With this device tree fixup and poplar_defconfig changes,
> Ethernet starts working on Poplar board.
>
> Signed-off-by: Shawn Guo
> Reviewed-by: Igor Opaniuk
> ---
> arch/arm/dts/hi3798cv200-u-boot.dtsi | 14 ++
> configs/poplar_defconfig | 3 +++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi
> b/arch/arm/dts/hi3798cv200-u-boot.dtsi
> index 7844c5208c5d..2ca943f64e59 100644
> --- a/arch/arm/dts/hi3798cv200-u-boot.dtsi
> +++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi
> @@ -8,7 +8,15 @@
> * (C) Copyright 2017 Jorge Ramirez-Ortiz
> */
>
> +#include
Where does this file come from?
> +
> &soc {
> + rst: reset-controller@8a22000 {
> + compatible = "hisilicon,hi3798cv200-reset";
> + reg = <0x8a22000 0x1000>;
Would it not be reasonable to include the "0xcc" from below in this
address instead of adding them at runtime?
> + #reset-cells = <3>;
> + };
> +
> usb2: ehci@989 {
> compatible = "generic-ehci";
> reg = <0x989 0x100>;
> @@ -16,6 +24,12 @@
> };
> };
>
> +&gmac1 {
> + resets = <&rst 0xcc 9 HISI_RESET_ACTIVE_HIGH>,
> +<&rst 0xcc 11 HISI_RESET_ACTIVE_HIGH>,
> +<&rst 0xcc 13 HISI_RESET_ACTIVE_LOW>;
> +};
> +
> &uart0 {
> clock = <7500>;
> status = "okay";
> diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig
> index 81bd3702e42a..76ab5eb70e7e 100644
> --- a/configs/poplar_defconfig
> +++ b/configs/poplar_defconfig
> @@ -19,6 +19,9 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> CONFIG_DM_MMC=y
> CONFIG_MMC_DW=y
> CONFIG_MMC_DW_K3=y
> +CONFIG_DM_ETH=y
> +CONFIG_HIGMACV300_ETH=y
> +CONFIG_RESET_HISILICON=y
> CONFIG_USB=y
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_EHCI_GENERIC=y
> --
> 2.18.0
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/3] reset: add reset driver for HiSilicon platform
Hi Shawn,
On Sun, Mar 10, 2019 at 3:53 AM Shawn Guo wrote:
>
> It adds a Driver Model compatible reset driver for HiSlicon platform.
> The driver implements a custom .of_xlate function, and uses .data field
> as reset register offset and .id field as bit shift.
>
> Signed-off-by: Shawn Guo
> Reviewed-by: Igor Opaniuk
> ---
> drivers/reset/Kconfig | 6 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-hisilicon.c | 111
> 3 files changed, 118 insertions(+)
> create mode 100644 drivers/reset/reset-hisilicon.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index a81e76769604..6ec6f39c85f0 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -121,4 +121,10 @@ config RESET_SUNXI
> This enables support for common reset driver for
> Allwinner SoCs.
>
> +config RESET_HISILICON
> + bool "Reset controller driver for HiSilicon SoCs"
> + depends on DM_RESET
> + help
> + Support for reset controller on HiSilicon SoCs.
> +
> endmenu
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 4fad7d412985..7fec75bb4923 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -19,3 +19,4 @@ obj-$(CONFIG_RESET_MESON) += reset-meson.o
> obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
> obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> +obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
> diff --git a/drivers/reset/reset-hisilicon.c b/drivers/reset/reset-hisilicon.c
> new file mode 100644
> index ..7b0c11fbc82e
> --- /dev/null
> +++ b/drivers/reset/reset-hisilicon.c
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019, Linaro Limited
> + */
> +
> +#include
> +#include
> +#include
> +#include
Where does this file come from?
> +#include
> +
> +struct hisi_reset_priv {
> + void __iomem *base;
> +};
> +
> +static int hisi_reset_deassert(struct reset_ctl *rst)
> +{
> + struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
> + u32 offset = rst->data & 0x;
> + u32 shift = rst->data >> 16;
> + int polarity = rst->id;
> + u32 val;
> +
> + val = readl(priv->base + offset);
> + if (polarity == HISI_RESET_ACTIVE_HIGH)
> + val &= ~BIT(shift);
> + else
> + val |= BIT(shift);
> + writel(val, priv->base + offset);
> +
> + return 0;
> +}
> +
> +static int hisi_reset_assert(struct reset_ctl *rst)
> +{
> + struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
> + u32 offset = rst->data & 0x;
> + u32 shift = rst->data >> 16;
> + int polarity = rst->id;
> + u32 val;
> +
> + val = readl(priv->base + offset);
> + if (polarity == HISI_RESET_ACTIVE_HIGH)
> + val |= BIT(shift);
> + else
> + val &= ~BIT(shift);
> + writel(val, priv->base + offset);
> +
> + return 0;
> +}
> +
> +static int hisi_reset_free(struct reset_ctl *rst)
> +{
> + return 0;
> +}
> +
> +static int hisi_reset_request(struct reset_ctl *rst)
> +{
> + return 0;
> +}
> +
> +static int hisi_reset_of_xlate(struct reset_ctl *rst,
> + struct ofnode_phandle_args *args)
> +{
> + if (args->args_count != 3) {
> + debug("Invalid args_count: %d\n", args->args_count);
> + return -EINVAL;
> + }
> +
> + /*
> +* Encode register offset in .data[15..0] and bit shift in
> +* .data[31..16], and use .id field as polarity.
> +*/
I don't like going through these contortions to avoid changing the
struct in reset.h
I think you should add a "polarity" field to that struct and instead
of defining a specific constant for HISI_RESET_ACTIVE_HIGH, instead
make a generic one that everyone can use, such as the ASSERT_CLEAR and
friends in Linux.
I also hope you can get rid of the register offset and either include
it in the DT base address if it is something that needs to be selected
or simply make a #define for the 0xCC for what the register is called
and go from there. If both are not acceptable, I think it makes sense
to use "data" as the register.
> + rst->data = (args->args[1] << 16) | (args->args[0] & 0x);
> + rst->id = args->args[2];
I think "id" should be used to hold the "shift" or bit number of the reset.
> +
> + return 0;
> +}
> +
> +static const struct reset_ops hisi_reset_reset_ops = {
> + .of_xlate = hisi_reset_of_xlate,
> + .request = hisi_reset_request,
> + .free = hisi_reset_free,
> + .rst_assert = hisi_reset_assert,
> + .rst_deassert = hisi_reset_deassert,
> +};
> +
> +static const struct udevice_id hisi_reset_ids[] = {
> + { .compatible = "hisilicon,hi3798cv200-reset" },
> + { }
> +};
> +
> +static int hisi_reset_probe(struct udevice *dev)
> +{
> +
Re: [U-Boot] [PATCH v3 2/3] net: add higmacv300 Ethernet driver for HiSilicon platform
On Sun, Mar 10, 2019 at 3:52 AM Shawn Guo wrote: > > It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon > SoCs like Hi3798CV200. It's based on a downstream U-Boot driver, but > quite a lot of code gets rewritten and cleaned up to adopt driver model > and PHY API. > > Signed-off-by: Shawn Guo > --- Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: dm: fec: Support phy-reset-post-delay property
Hi Anatolij, On Tue, Mar 12, 2019 at 4:10 AM Anatolij Gustschin wrote: > > Hi Joe, > > On Tue, 5 Mar 2019 12:05:38 -0600 > Joe Hershberger joe.hershber...@ni.com wrote: > > > Hi Andrejs, > > > > https://patchwork.ozlabs.org/patch/1050177/ was applied to > > http://git.denx.de/?p=u-boot/u-boot-net.git > > This patch is not in mainline tree yet, but it is marked as accepted > on patchwork. Could you please check? This is part of a bug-fix for > broken ethernet on the board and should go into v2019.04 release. Yes, it should go into this release. Hopefully Tom will pull it in shortly. Thanks, -Joe > Thanks, > Anatolij > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-net.git master
Hi Tom, These patches passed the CI build here: https://travis-ci.org/jhershbe/u-boot/builds/501807294 The following changes since commit 2e8092d94f40a5692baf3ec768ce3216a7bf032a: Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2019-03-11 15:48:57 -0400) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to 85f05f72bacc2d047731fc64801e4f6b34cf: net: phy: aquantia: Set only autoneg on in register 4.c441 (2019-03-12 13:13:37 -0500) Andrejs Cainikovs (2): net: dm: fec: Support phy-reset-post-delay property dts: imx8qxp-mek: Add PHY post reset delay Carlo Caione (4): net: phy: realtek: Introduce quirk to mark RXC not stoppable net: phy: Add generic helpers to access MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Switch to generic helpers when accessing the registers James Byrne (2): net: phy: micrel: Use correct skew values on KSZ9021 net: phy: micrel: Find Micrel PHY node correctly Meenakshi Aggarwal (1): mc : Reduce MC memory size to 128M Murali Karicheri (7): ARM: k2g-gp-evm: update to rgmii pinmux configuration ARM: k2g-ice: Add pinmux support for rgmii interface net: netcp: add support for phy with rgmii ids ARM: k2g: add a workaround to reset the phy ARM: dts: k2g-evm: remove unused phy-mode property from phy node k2g: config enable ti phy dp83867 for k2g ARM: dts: k2g-ice: add dt node for netcp Pankaj Bansal (1): drivers: net: ldpaa_eth: fix resource leak Siva Durga Prasad Paladugu (2): net: phy: Reloc next and prev pointers inside phy_drivers net: phy: Fix return value check phy_probe Valentin-catalin Neacsu (1): net: phy: aquantia: Set only autoneg on in register 4.c441 Vladimir Oltean (6): net: phy: ar803x: Address packet drops at low traffic rate due to SmartEEE feature net: phy: ar803x: Make RGMII Tx delays actually configurable for AR8035 net: phy: ar803x: Use common functions for RGMII internal delays net: phy: ar803x: Clarify the configuration of the CLK_25M output pin net: phy: ar803x: Explicitly disable RGMII delays net: phy: ar803x: Clarify the intention of ar8021_config arch/arm/dts/fsl-imx8qxp-mek.dts | 1 + arch/arm/dts/keystone-k2g-evm.dts | 1 - arch/arm/dts/keystone-k2g-ice.dts | 35 ++ arch/arm/dts/sama5d3xcm.dtsi | 32 ++--- arch/arm/dts/sama5d3xcm_cmp.dtsi | 32 ++--- arch/arm/dts/socfpga_arria5_socdk.dts | 4 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 4 +- arch/arm/dts/socfpga_cyclone5_socdk.dts| 4 +- arch/arm/dts/socfpga_cyclone5_sockit.dts | 4 +- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 4 +- arch/arm/mach-keystone/include/mach/hardware-k2g.h | 3 + arch/arm/mach-keystone/include/mach/mux-k2g.h | 5 + board/ti/ks2_evm/board_k2g.c | 15 +++ board/ti/ks2_evm/mux-k2g.h | 51 +--- cmd/mdio.c | 27 +++-- configs/k2g_evm_defconfig | 1 + doc/device-tree-bindings/net/micrel-ksz90x1.txt| 27 + drivers/net/fec_mxc.c | 11 ++ drivers/net/fec_mxc.h | 1 + drivers/net/fsl-mc/mc.c| 22 +++- drivers/net/ldpaa_eth/ldpaa_eth.c | 1 + drivers/net/phy/Kconfig| 41 +++ drivers/net/phy/aquantia.c | 7 +- drivers/net/phy/atheros.c | 128 ++-- drivers/net/phy/micrel_ksz90x1.c | 24 +++- drivers/net/phy/phy.c | 21 +++- drivers/net/phy/realtek.c | 19 +++ drivers/net/phy/ti.c | 130 - drivers/net/ti/keystone_net.c | 22 +++- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 2 +- include/phy.h | 70 +++ 33 files changed, 526 insertions(+), 227 deletions(-) Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 03/13] net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle
On Thu, Mar 7, 2019 at 10:22 AM Jagan Teki wrote:
>
> On Tue, Mar 5, 2019 at 10:55 PM Joe Hershberger
> wrote:
> >
> > On Tue, Mar 5, 2019 at 10:17 AM Jagan Teki
> > wrote:
> > >
> > > On Sat, Mar 2, 2019 at 12:29 AM Joe Hershberger
> > > wrote:
> > > >
> > > > On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki
> > > > wrote:
> > > > >
> > > > > Unlike other Allwinner SoC's R40 GMAC clock control register
> > > > > is locate in CCU, but rest located via syscon itself. Since
> > > > > the phandle property for current code look for 'syscon' and
> > > > > it will grab the respective ccu or syscon base address based
> > > > > on DT property defined in respective SoC dtsi.
> > > > >
> > > > > So, use the existing 'syscon' code even for R40 for retrieving
> > > > > GMAC clock via CCU and update the register directly in
> > > > > sun8i_emac_set_syscon instead of writing it separately using
> > > > > ccm base.
> > > > >
> > > > > Cc: Joe Hershberger
> > > > > Cc: Lothar Felten
> > > > > Signed-off-by: Jagan Teki
> > > > > ---
> > > > > drivers/net/sun8i_emac.c | 55
> > > > >
> > > > > 1 file changed, 27 insertions(+), 28 deletions(-)
> > > > >
> > > > > diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> > > > > index c9798445c7..a7fb7ac405 100644
> > > > > --- a/drivers/net/sun8i_emac.c
> > > > > +++ b/drivers/net/sun8i_emac.c
> > > > > @@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct
> > > > > sun8i_eth_pdata *pdata,
> > > > > int ret;
> > > > > u32 reg;
> > > > >
> > > > > - reg = readl(priv->sysctl_reg + 0x30);
> > > > > + if (priv->variant == R40_GMAC) {
> > > > > + /* Select RGMII for R40 */
> > > > > + reg = readl(priv->sysctl_reg + 0x164);
> > > >
> > > > Please don't add more magic numbers. #define with register name.
> > >
> > > I do prefer the same, but kept it as same as original. and there are
> > > other place do have similar reg magic numbers. Will clean it up all
> > > in separate patch. would that be okay?
> >
> > OK. This cam in after the merge window closed, right? If so, please
> > move the cleanup patch before this one in the next version.
>
> It's been in ML many releases, but I will send PR in next MW. mean
> while I'll push it on my sunxi/next and will send separate patch about
> the cleanup. will that be fine?
Sure, that's fine.
Thanks!
-Joe
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/3] net: add higmacv300 Ethernet driver for HiSilicon platform
On Tue, Mar 5, 2019 at 7:42 PM Shawn Guo wrote:
>
> On Tue, Mar 05, 2019 at 11:58:26PM +0000, Joe Hershberger wrote:
> > > +static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
> > > +{
> > > + struct higmac_priv *priv = dev_get_priv(dev);
> > > + struct higmac_desc *fqd = priv->rxfq;
> > > + struct higmac_desc *bqd = priv->rxbq;
> > > + int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
> > > + int timeout = 10;
> > > + int len = 0;
> > > + int space;
> > > + int i;
> > > +
> > > + fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
> > > + fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
> > > +
> > > + if (fqw_pos >= fqr_pos)
> > > + space = RX_DESC_NUM - (fqw_pos - fqr_pos);
> > > + else
> > > + space = fqr_pos - fqw_pos;
> > > +
> > > + /* Leave one free to distinguish full filled from empty buffer */
> > > + for (i = 0; i < space - 1; i++) {
> > > + fqd = priv->rxfq + fqw_pos;
> > > + invalidate_dcache_range(fqd->buf_addr,
> > > + fqd->buf_addr +
> > > MAC_MAX_FRAME_SIZE);
> > > +
> > > + if (++fqw_pos >= RX_DESC_NUM)
> > > + fqw_pos = 0;
> > > +
> > > + writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
> > > + }
> > > +
> > > + bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
> > > + bqd += bqr_pos;
> > > + /* BQ is only ever written by GMAC */
> > > + invalidate_desc(bqd);
> > > +
> > > + do {
> > > + bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
> > > + udelay(1);
> > > + } while (--timeout && bqw_pos == bqr_pos);
> >
> > Did you look into using wait bit macros?
>
> I may miss your point, but this is not a loop waiting for some bits set
> or clear. It's waiting for a given number.
OK, I see that, thanks. Should you make these "breakable" in the same
way that wait_for_bit_* does? The timeout seems quite long.
>
> >
> > > +
> > > + if (!timeout)
> > > + return -ETIMEDOUT;
> > > +
> > > + if (++bqr_pos >= RX_DESC_NUM)
> > > + bqr_pos = 0;
> > > +
> > > + len = bqd->data_len;
> > > +
> > > + /* CPU should not have touched this buffer since we added it to
> > > FQ */
> > > + invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
> > > + *packetp = (void *)(unsigned long)bqd->buf_addr;
> > > +
> > > + /* Record the RX_BQ descriptor that is holding RX data */
> > > + priv->rxdesc_in_use = bqr_pos;
> > > +
> > > + return len;
> > > +}
>
>
>
> > > +static int higmac_hw_init(struct higmac_priv *priv)
> > > +{
> > > + int ret;
> > > +
> > > + /* Initialize hardware queues */
> > > + ret = higmac_init_hw_queue(priv, RX_FQ);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + ret = higmac_init_hw_queue(priv, RX_BQ);
> > > + if (ret)
> > > + goto free_rx_fq;
> > > +
> > > + ret = higmac_init_hw_queue(priv, TX_BQ);
> > > + if (ret)
> > > + goto free_rx_bq;
> > > +
> > > + ret = higmac_init_hw_queue(priv, TX_RQ);
> > > + if (ret)
> > > + goto free_tx_bq;
> > > +
> > > + /* Reset phy */
> > > + reset_assert(&priv->rst_phy);
> > > + mdelay(10);
> >
> > I'm surprised the delay here is not a DT parameter.
>
> We do not see the necessity for now. We can make it a DT parameter when
> we see the real need in the future.
OK
>
> >
> > > + reset_deassert(&priv->rst_phy);
> > > + mdelay(30);
> >
> > I'm surprised the delay here is not a DT parameter.
> >
> > > + reset_assert(&priv->rst_phy);
> > > + mdelay(30);
> >
> > Why is this reasserted?
>
> I have to admit this is a bit hackish. Ideally, the reset sequence
> should be:
Re: [U-Boot] [PATCH] net: phy: micrel: Allow KSZ8xxx and KSZ90x1 to be used together
On Wed, Mar 6, 2019 at 6:48 AM James Byrne
wrote:
>
> Commit d397f7c45b0b ("net: phy: micrel: Separate KSZ9000 drivers from
> KSZ8000 drivers") separated the KSZ8xxx and KSZ90x1 drivers and warns
> that you shouldn't select both of them due to a device ID clash between
> the KSZ9021 and the KS8721, asserting that "it is highly unlikely for a
> system to contain both a KSZ8000 and a KSZ9000 PHY". Unfortunately
> boards like the SAMA5D3xEK do contain both types of PHY, but fortunately
> the Linux Micrel PHY driver provides a solution by using different PHY
> ID and mask values to distinguish these chips.
>
> This commit contains the following changes:
>
> - The PHY ID and mask values for the KSZ9021 and the KS8721 now match
> those used by the Linux driver.
> - The warnings about not enabling both drivers have been removed.
> - The description for PHY_MICREL_KSZ8XXX has been corrected (these are
> 10/100 PHYs, not GbE PHYs).
> - PHY_MICREL_KSZ9021 and PHY_MICREL_KSZ9031 no longer select PHY_GIGE
> since this is selected by PHY_MICREL_KSZ90X1.
> - All of the relevant defconfig files have been updated now that
> PHY_MICREL_KSZ8XXX does not default to 'Y'.
>
> Signed-off-by: James Byrne
Acked-by: Joe Hershberger
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/3] net: add higmacv300 Ethernet driver for HiSilicon platform
On Sun, Feb 17, 2019 at 9:39 PM Shawn Guo wrote: > > It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon > SoCs like Hi3798CV200. It's based on a downstream U-Boot driver, but > quite a lot of code gets rewritten and cleaned up to adopt driver model > and PHY API. > > Signed-off-by: Shawn Guo Looks pretty good. I have a few questions / comments below. > --- > drivers/net/Kconfig | 9 + > drivers/net/Makefile | 1 + > drivers/net/higmacv300.c | 597 +++ > 3 files changed, 607 insertions(+) > create mode 100644 drivers/net/higmacv300.c > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index 6a570285aac5..ad1e50c0e8ca 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -525,4 +525,13 @@ config MEDIATEK_ETH > This Driver support MediaTek Ethernet GMAC > Say Y to enable support for the MediaTek Ethernet GMAC. > > +config HIGMACV300_ETH > + bool "HiSilicon Gigabit Ethernet Controller" > + depends on DM_ETH > + select DM_RESET > + select PHYLIB > + help > + This driver supports HIGMACV300 Ethernet controller found on > + HiSilicon SoCs. > + > endif # NETDEVICES > diff --git a/drivers/net/Makefile b/drivers/net/Makefile > index 51be72b0aa86..8d02a378964b 100644 > --- a/drivers/net/Makefile > +++ b/drivers/net/Makefile > @@ -76,3 +76,4 @@ obj-$(CONFIG_SNI_AVE) += sni_ave.o > obj-y += ti/ > obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o > obj-y += mscc_eswitch/ > +obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o > diff --git a/drivers/net/higmacv300.c b/drivers/net/higmacv300.c > new file mode 100644 > index ..549c26b19b99 > --- /dev/null > +++ b/drivers/net/higmacv300.c > @@ -0,0 +1,597 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2019, Linaro Limited > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define STATION_ADDR_LOW 0x > +#define STATION_ADDR_HIGH 0x0004 > +#define MAC_DUPLEX_HALF_CTRL 0x0008 > +#define PORT_MODE 0x0040 > +#define PORT_EN0x0044 > +#define BIT_TX_EN BIT(2) > +#define BIT_RX_EN BIT(1) > +#define MODE_CHANGE_EN 0x01b4 > +#define BIT_MODE_CHANGE_EN BIT(0) > +#define MDIO_SINGLE_CMD0x03c0 > +#define BIT_MDIO_BUSY BIT(20) > +#define MDIO_READ (BIT(17) | BIT_MDIO_BUSY) > +#define MDIO_WRITE (BIT(16) | BIT_MDIO_BUSY) > +#define MDIO_SINGLE_DATA 0x03c4 > +#define MDIO_RDATA_STATUS 0x03d0 > +#define BIT_MDIO_RDATA_INVALID BIT(0) > +#define RX_FQ_START_ADDR 0x0500 > +#define RX_FQ_DEPTH0x0504 > +#define RX_FQ_WR_ADDR 0x0508 > +#define RX_FQ_RD_ADDR 0x050c > +#define RX_FQ_REG_EN 0x0518 > +#define RX_BQ_START_ADDR 0x0520 > +#define RX_BQ_DEPTH0x0524 > +#define RX_BQ_WR_ADDR 0x0528 > +#define RX_BQ_RD_ADDR 0x052c > +#define RX_BQ_REG_EN 0x0538 > +#define TX_BQ_START_ADDR 0x0580 > +#define TX_BQ_DEPTH0x0584 > +#define TX_BQ_WR_ADDR 0x0588 > +#define TX_BQ_RD_ADDR 0x058c > +#define TX_BQ_REG_EN 0x0598 > +#define TX_RQ_START_ADDR 0x05a0 > +#define TX_RQ_DEPTH0x05a4 > +#define TX_RQ_WR_ADDR 0x05a8 > +#define TX_RQ_RD_ADDR 0x05ac > +#define TX_RQ_REG_EN 0x05b8 > +#define BIT_START_ADDR_EN BIT(2) > +#define BIT_DEPTH_EN BIT(1) > +#define DESC_WR_RD_ENA 0x05cc > +#define BIT_RX_OUTCFF_WR BIT(3) > +#define BIT_RX_CFF_RD BIT(2) > +#define BIT_TX_OUTCFF_WR BIT(1) > +#define BIT_TX_CFF_RD BIT(0) > +#define BITS_DESC_ENA (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \ > +BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD) > + > +/* MACIF_CTRL */ > +#define RGMII_SPEED_1000 0x2c > +#define RGMII_SPEED_1000x2f > +#define RGMII_SPEED_10 0x2d > +#define MII_SPEED_100 0x0f > +#define MII_SPEED_10 0x0d > +#define GMAC_SPEED_10000x05 > +#define GMAC_SPEED_100 0x01 > +#define GMAC_SPEED_10 0x00 > +#define GMAC_FULL_DUPLEX BIT(4) > + > +#define RX_DESC_NUM64 > +#define TX_DESC_NUM2 > +#define DESC_SIZE 32 > +#define DESC_WORD_SHIFT3 > +#define DESC_BYTE_SH
Re: [U-Boot] [PATCH v3 03/13] net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle
On Tue, Mar 5, 2019 at 10:17 AM Jagan Teki wrote:
>
> On Sat, Mar 2, 2019 at 12:29 AM Joe Hershberger
> wrote:
> >
> > On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki
> > wrote:
> > >
> > > Unlike other Allwinner SoC's R40 GMAC clock control register
> > > is locate in CCU, but rest located via syscon itself. Since
> > > the phandle property for current code look for 'syscon' and
> > > it will grab the respective ccu or syscon base address based
> > > on DT property defined in respective SoC dtsi.
> > >
> > > So, use the existing 'syscon' code even for R40 for retrieving
> > > GMAC clock via CCU and update the register directly in
> > > sun8i_emac_set_syscon instead of writing it separately using
> > > ccm base.
> > >
> > > Cc: Joe Hershberger
> > > Cc: Lothar Felten
> > > Signed-off-by: Jagan Teki
> > > ---
> > > drivers/net/sun8i_emac.c | 55
> > > 1 file changed, 27 insertions(+), 28 deletions(-)
> > >
> > > diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> > > index c9798445c7..a7fb7ac405 100644
> > > --- a/drivers/net/sun8i_emac.c
> > > +++ b/drivers/net/sun8i_emac.c
> > > @@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct
> > > sun8i_eth_pdata *pdata,
> > > int ret;
> > > u32 reg;
> > >
> > > - reg = readl(priv->sysctl_reg + 0x30);
> > > + if (priv->variant == R40_GMAC) {
> > > + /* Select RGMII for R40 */
> > > + reg = readl(priv->sysctl_reg + 0x164);
> >
> > Please don't add more magic numbers. #define with register name.
>
> I do prefer the same, but kept it as same as original. and there are
> other place do have similar reg magic numbers. Will clean it up all
> in separate patch. would that be okay?
OK. This cam in after the merge window closed, right? If so, please
move the cleanup patch before this one in the next version.
Thanks.
-Joe
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: dm: fec: Support phy-reset-post-delay property
Hi Andrejs, https://patchwork.ozlabs.org/patch/1050177/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ARM: k2g-ice: Add pinmux support for rgmii interface
Hi Murali, https://patchwork.ozlabs.org/patch/1047978/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: ti: use generic helpers to access MMD registers
Hi Carlo, https://patchwork.ozlabs.org/patch/1038820/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] mc : Reduce MC memory size to 128M
Hi Meenakshi, https://patchwork.ozlabs.org/patch/1048656/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: micrel: Find Micrel PHY node correctly
Hi James, https://patchwork.ozlabs.org/patch/1051237/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ARM: dts: k2g-ice: add dt node for netcp
Hi Murali, https://patchwork.ozlabs.org/patch/1047980/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: Fix return value check phy_probe
Hi Michal, https://patchwork.ozlabs.org/patch/1051139/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] k2g: config enable ti phy dp83867 for k2g
Hi Murali, https://patchwork.ozlabs.org/patch/1047983/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] dts: imx8qxp-mek: Add PHY post reset delay
Hi Andrejs, https://patchwork.ozlabs.org/patch/1050178/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-net.git master
Hi Tom, These patches passed the CI build here: https://travis-ci.org/jhershbe/u-boot/builds/501807294 The following changes since commit aff66f22d6eeb27c6329c0a3c1ebc52914c8affa: Merge tag 'mips-pull-2019-01-23' of git://git.denx.de/u-boot-mips (2019-01-23 17:24:31 -0500) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to 91c9cbabf935b37ab6c0b9b622e7faf0b350acb6: net: phy: aquantia: Print information on config (2019-01-24 11:35:30 -0600) Aditya Prayoga (1): net: mvneta: Add GPIO configuration support Andreas Pretzsch (1): net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps Baruch Siach (2): net: mvpp2: fix lookup of mdio registers base address net: mvpp2: mdio device per port Carlo Caione (1): net: phy: realtek: Add functions to read PHY's extended registers Chris Packham (3): net: mvgbe: fallback phy-mode to GMII net: move ether_crc to tsec driver net: remove CONFIG_MCAST_TFTP Pankaj Bansal (1): net: phy: Add clause 45 identifier to phy_device Ramon Fried (1): net: macb: fix mapping of registers Simon Goldschmidt (4): net: designware: fix tx packet length net: designware: clear padding bytes net: remove duplicate definition of ETHADDR_WILDCARD net: fix env flags for eth10addr and above Thomas RIENOESSL (1): net: explicitly assign errno to return code in case of network failure Valentin-catalin Neacsu (2): net: phy: aquantia: Enable autoneg when on USXGMII net: phy: aquantia: Print information on config README | 9 -- drivers/net/designware.c | 18 ++-- drivers/net/macb.c | 4 +- drivers/net/mvgbe.c | 6 +- drivers/net/mvneta.c | 15 +++ drivers/net/mvpp2.c | 84 +++ drivers/net/phy/aquantia.c | 39 +++ drivers/net/phy/micrel_ksz90x1.c | 4 +- drivers/net/phy/phy.c| 15 ++- drivers/net/phy/realtek.c| 29 ++ drivers/net/rtl8139.c| 6 +- drivers/net/tsec.c | 37 +-- drivers/usb/gadget/ether.c | 3 - include/env_callback.h | 2 - include/env_flags.h | 2 +- include/net.h| 15 +-- include/phy.h| 1 + net/eth-uclass.c | 2 - net/eth_legacy.c | 28 - net/net.c| 8 +- net/tftp.c | 219 --- scripts/config_whitelist.txt | 1 - test/dm/eth.c| 2 +- 23 files changed, 184 insertions(+), 365 deletions(-) Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: netcp: add support for phy with rgmii ids
Hi Murali, https://patchwork.ozlabs.org/patch/1047982/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ARM: k2g: add a workaround to reset the phy
Hi Murali, https://patchwork.ozlabs.org/patch/1047979/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: Reloc next and prev pointers inside phy_drivers
Hi Michal, https://patchwork.ozlabs.org/patch/1051137/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: aquantia: Set only autoneg on in register 4.c441
Hi Valentin-catalin, https://patchwork.ozlabs.org/patch/1041087/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] drivers: net: ldpaa_eth: fix resource leak
Hi Pankaj, https://patchwork.ozlabs.org/patch/1038527/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: Add generic helpers to access MMD PHY registers
Hi Carlo, https://patchwork.ozlabs.org/patch/1038818/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: micrel: Use correct skew values on KSZ9021
Hi James, https://patchwork.ozlabs.org/patch/1051234/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ARM: dts: k2g-evm: remove unused phy-mode property from phy node
Hi Murali, https://patchwork.ozlabs.org/patch/1047977/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: ar803x: Explicitly disable RGMII delays
Hi Vladimir, https://patchwork.ozlabs.org/patch/1031365/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: ar803x: Clarify the intention of ar8021_config
Hi Vladimir, https://patchwork.ozlabs.org/patch/1031366/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] cmd: mdio: Switch to generic helpers when accessing the registers
Hi Carlo, https://patchwork.ozlabs.org/patch/1038821/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] ARM: k2g-gp-evm: update to rgmii pinmux configuration
Hi Murali, https://patchwork.ozlabs.org/patch/1047981/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: ar803x: Use common functions for RGMII internal delays
Hi Vladimir, https://patchwork.ozlabs.org/patch/1031363/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: ar803x: Clarify the configuration of the CLK_25M output pin
Hi Vladimir, https://patchwork.ozlabs.org/patch/1031364/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: ar803x: Make RGMII Tx delays actually configurable for AR8035
Hi Vladimir, https://patchwork.ozlabs.org/patch/1031362/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: ar803x: Address packet drops at low traffic rate due to SmartEEE feature
Hi Vladimir, https://patchwork.ozlabs.org/patch/1031361/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] net: phy: realtek: Introduce quirk to mark RXC not stoppable
Hi Carlo, https://patchwork.ozlabs.org/patch/1030370/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] board: stm32f746-disco: Get MII/RMII phy_mode from DT
On Fri, Feb 22, 2019 at 8:06 AM Patrice Chotard wrote: > > This is needed to make ethernet work on stm32f746-eval which > uses MII mode. > > Signed-off-by: Patrice Chotard Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] board: fsl: lx2160aqds: modify the phy fixup code
On Thu, Feb 28, 2019 at 2:13 AM Pankaj Bansal wrote: > > Now that we are representing the MDIO mux in LX2160AQDS board in > producer/consumer terms, the consumer nodes' has been changed. > > Therefore, modify the device tree fixups according to change in device > tree. > > Signed-off-by: Pankaj Bansal Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 22/22] pcm052: bk4: Add board_phy_config() for BK4 to setup ksz8081 phy
On Wed, Feb 13, 2019 at 3:51 PM Lukasz Majewski wrote:
>
> BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices.
>
> Signed-off-by: Lukasz Majewski
Acked-by: Joe Hershberger
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> board/phytec/pcm052/pcm052.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
> index 1e443a5850..c30df5df9d 100644
> --- a/board/phytec/pcm052/pcm052.c
> +++ b/board/phytec/pcm052/pcm052.c
> @@ -15,6 +15,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -382,6 +383,21 @@ int board_late_init(void)
>
> return 0;
> }
> +
> +/**
> + * KSZ8081
> + */
> +#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f
> +#define RMII_50MHz_CLOCK 0x8180
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + /* Set 50 MHz reference clock */
> + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
> + RMII_50MHz_CLOCK);
Is it reasonable to use the clock infrastructure? Not necessarily
instead of fixing this now, but would be a good direction.
> +
> + return genphy_config(phydev);
> +}
> #endif /* CONFIG_TARGET_BK4R1 */
>
> int checkboard(void)
> --
> 2.11.0
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers/net/fec: phy_init: remove redundant logic
On Fri, Feb 15, 2019 at 3:30 AM Hannes Schmelzer wrote: > > The phy_connect_dev(...) function from phy.c does all the handling > (inclusive catching fixed-link). > > So we drop here the single steps and call just phy_connect_dev(...). > > Signed-off-by: Hannes Schmelzer Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] net: phy: micrel: Find Micrel PHY node correctly
On Mon, Mar 4, 2019 at 11:47 AM James Byrne wrote: > > In some of the device trees that specify skew values for KSZ90x1 PHYs > the values are stored (incorrectly) in the MAC node, whereas in others > it is in an 'ethernet-phy' subnode. Previously the code would fail to > find and program these skew values, so this commit changes it to look > for an "ethernet-phy" subnode first, and revert to looking in the MAC > node if there isn't one. > > The device trees affected (where the skew values are in a subnode) are > imx6qdl-icore-rqs.dtsi, r8a77970-eagle.dts, r8a77990-ebisu.dts, > r8a77995-draak.dts, salvator-common.dtsi, sama5d3xcm.dtsi, > sama5d3xcm_cmp.dtsi, socfpga_cyclone5_vining_fpga.dts, > socfpga_stratix10_socdk.dts and ulcb.dtsi. Before this change the skew > values in these device trees would be ignored. > > The device trees where the skew values are in the MAC node are > socfpga_arria10_socdk.dtsi, socfpga_arria5_socdk.dts, > socfpga_cyclone5_de0_nano_soc.dts, socfpga_cyclone5_de10_nano.dts, > socfpga_cyclone5_de1_soc.dts, socfpga_cyclone5_is1.dts, > socfpga_cyclone5_socdk.dts, socfpga_cyclone5_sockit.dts. These should be > unaffected by this change. > > The changes were tested on a sama5d3xcm. > > Signed-off-by: James Byrne Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] net: phy: micrel: Use correct skew values on KSZ9021
On Mon, Mar 4, 2019 at 11:46 AM James Byrne
wrote:
>
> Commit ff7bd212cb8a ("net: phy: micrel: fix divisor value for KSZ9031
> phy skew") fixed the skew value divisor for the KSZ9031, but left the
> code using the same divisor for the KSZ9021, which is incorrect.
>
> The preceding commit c16e69f702b1 ("net: phy: micrel: add documentation
> for Micrel KSZ90x1 binding") added the DTS documentation for the
> KSZ90x1, changing it from the equivalent file in the Linux kernel to
> correctly state that for this part the skew value is set in 120ps steps,
> whereas the Linux documentation and driver continue to this day to use
> the incorrect value of 200 that came from the original KSZ9021 datasheet
> before it was corrected in revision 1.2 (Feb 2014).
>
> This commit sorts out the resulting confusion in a consistent way by
> making the following changes:
>
> - Update the documentation to be clear about what the skew values mean,
> in the same was as for the KSZ9031.
>
> - Update the Micrel PHY driver to select the appropriate divisor for
> both parts.
>
> - Adjust all the device trees that state skew values for KSZ9021 PHYs to
> use values based on 120ps steps instead of 200ps steps. This will result
> in the same values being programmed into the skew registers as the
> equivalent device trees in the Linux kernel do, where it incorrectly
> uses 200ps steps (since that's where all these device trees were copied
> from).
>
> Signed-off-by: James Byrne
Acked-by: Joe Hershberger
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: net: ls1088ardb: Fix EC1 and EC2 RCW offset
On Thu, Feb 28, 2019 at 3:06 AM Pramod Kumar wrote: > > Fix EC1 and EC2 read from correct offset 26, instead of 25 > > Signed-off-by: Pramod Kumar Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] driver: net: fsl-mc: Fix DPC MAC address fixup
On Tue, Feb 26, 2019 at 9:51 AM Ioana Ciocoi Radulescu
wrote:
>
> If node /board_info/ports does not exist in the DPC file,
> function mc_fixup_dpc() will skip not only MAC address fixup,
> but also the cache flush at the end. This may cause the other
> fixup changes (e.g. ICID relatd ones) to be ignored by MC.
Typo in commit log.
>
> Fixes: 1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL")
>
> Signed-off-by: Ioana Radulescu
Acked-by: Joe Hershberger
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH] net: phy: Reloc next and prev pointers inside phy_drivers
On Mon, Mar 4, 2019 at 9:01 AM Michal Simek wrote: > > From: Siva Durga Prasad Paladugu > > This patch relocates the pointers inside phy_drivers incase > of manual reloc. Without this reloc, these points to invalid > pre relocation address and hence causes exception or hang. > > Signed-off-by: Siva Durga Prasad Paladugu > Signed-off-by: Michal Simek Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH] net: phy: Fix return value check phy_probe
On Mon, Mar 4, 2019 at 9:02 AM Michal Simek wrote: > > From: Siva Durga Prasad Paladugu > > Don't ignore return value of phy_probe() call as > the probe may fail and it needs to be reported. > > Signed-off-by: Siva Durga Prasad Paladugu > Signed-off-by: Michal Simek Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net:phy:aquantia Set only autoneg on in register 4.c441
On Wed, Feb 13, 2019 at 3:15 AM Valentin-catalin Neacsu wrote: > > For AQR405 in register 4.c441 bit 15 was override with 0. This caused the > phy to not negotiate at 2.5GB rate with mac. To avoid > this override it needed first to know the previous value of reg 4.c441 > and set only bit 3. > Signed-off-by: Valentin Catalin Neacsu Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Convert CONFIG_IP_DEFRAG to Kconfig
On Tue, Feb 12, 2019 at 6:29 AM Christian Gmeiner wrote: > > This converts the following to Kconfig: >CONFIG_IP_DEFRAG > > Signed-off-by: Christian Gmeiner Thanks for doing this, but don't we also need to migrate the existing targets that define this? include/configs/apalis_imx6.h:72:#define CONFIG_IP_DEFRAG include/configs/colibri_imx6.h:60:#define CONFIG_IP_DEFRAG include/configs/xilinx_versal.h:44:#define CONFIG_IP_DEFRAG include/configs/apalis_t30.h:31:#define CONFIG_IP_DEFRAG include/configs/sandbox.h:74:#define CONFIG_IP_DEFRAG include/configs/colibri-imx6ull.h:26:#define CONFIG_IP_DEFRAG include/configs/apalis-tk1.h:37:#define CONFIG_IP_DEFRAG include/configs/colibri_t30.h:30:#define CONFIG_IP_DEFRAG include/configs/colibri_t20.h:21:#define CONFIG_IP_DEFRAG include/configs/colibri_imx7.h:25:#define CONFIG_IP_DEFRAG Thanks, -Joe > --- > net/Kconfig | 6 ++ > scripts/config_whitelist.txt | 1 - > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/net/Kconfig b/net/Kconfig > index f2363e5256..5f5f632469 100644 > --- a/net/Kconfig > +++ b/net/Kconfig > @@ -8,6 +8,12 @@ menuconfig NET > > if NET > > +config IP_DEFRAG > + bool "Support IP datagram reassembly" > + help > + Selecting this will enable IP datagram reassembly according > + to the algorithm in RFC815. > + > config NET_RANDOM_ETHADDR > bool "Random ethaddr if unset" > help > diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt > index 2b3572568b..6b746c5242 100644 > --- a/scripts/config_whitelist.txt > +++ b/scripts/config_whitelist.txt > @@ -972,7 +972,6 @@ CONFIG_IPAM390_GPIO_BOOTMODE > CONFIG_IPAM390_GPIO_LED_GREEN > CONFIG_IPAM390_GPIO_LED_RED > CONFIG_IPROC > -CONFIG_IP_DEFRAG > CONFIG_IRAM_BASE > CONFIG_IRAM_END > CONFIG_IRAM_SIZE > -- > 2.20.1 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: net: ldpaa_eth: check if the dpmac is enabled
On Fri, Feb 8, 2019 at 2:59 AM Pankaj Bansal wrote: > > some dpmacs in armv8a based freescale layerscape SOCs can be > configured via both serdes(sgmii, xfi, xlaui etc) bits and via > EC*_PMUX(rgmii) bits in RCW. > e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from > serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits > Now if a dpmac is enabled by serdes bits then it takes precedence > over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol > that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, > then the dpmac is SGMII and not RGMII. > > Therefore, in fsl_rgmii_init function of SOC, we will check if the > dpmac is enabled or not? if it is (fsl_serdes_init has already enabled > the dpmac), then don't enable it. > > Signed-off-by: Pankaj Bansal Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 12/13] net: sun8i_emac: Add EPHY CLK and RESET support
On Wed, Feb 27, 2019 at 1:03 PM Jagan Teki wrote: > > Add EPHY CLK and RESET support for sun8i_emac driver to > enable EPHY TX clock and EPHY reset pins via CLK and RESET > framework. > > Cc: Joe Hershberger > Cc: Lothar Felten > Signed-off-by: Jagan Teki Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] mc : Reduce MC memory size to 128M
On Tue, Feb 26, 2019 at 9:26 PM Meenakshi Aggarwal wrote: > > ls2088, ls1088 : minimum MC Memory size is 128 MB > lx2 : minimum MC memory size is 256 MB > > Signed-off-by: Meenakshi Aggarwal Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 10/13] net: sun8i_emac: Add CLK and RESET support
On Wed, Feb 27, 2019 at 1:03 PM Jagan Teki wrote: > > Add CLK and RESET support for sun8i_emac driver to > enable TX clock and reset pins via CLK and RESET > framework. > > Cc: Joe Hershberger > Cc: Lothar Felten > Signed-off-by: Jagan Teki Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 11/13] clk: sunxi: h3: Implement EPHY CLK and RESET
On Wed, Feb 27, 2019 at 1:02 PM Jagan Teki wrote: > > EPHY CLK and RESET is available in Allwinner H3 EMAC > via mdio-mux node of internal PHY. Add the respetive Please fix typo in log above. respetive -> respective > clock and reset reg and bits. > > Cc: Joe Hershberger > Signed-off-by: Jagan Teki Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] mc : Reduce MC memory size to 128M
On Fri, Mar 1, 2019 at 2:48 PM Heinrich Schuchardt wrote: > > On 2/27/19 10:11 AM, Meenakshi Aggarwal wrote: > > ls2088, ls1088 : minimum MC Memory size is 128 MB > > lx2 : minimum MC memory size is 256 MB > > > > Signed-off-by: Meenakshi Aggarwal > > Hello Joe, > > in patchwork I have reassigned the patch > https://patchwork.ozlabs.org/patch/1048656/ > to you. > > The first patch of the series received a comment by the author: "Please > ignore, it is sent by mistake." So I set it to superseeded. Thanks for the heads up! -Joe > Best regards > > Heinrich > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 09/13] clk: sunxi: Implement EMAC, GMAC clocks, resets
On Wed, Feb 27, 2019 at 1:00 PM Jagan Teki wrote: > > - Implement EMAC, GMAC clocks via ccu_clk_gate for > all supported Allwinner SoCs. > - Implement EMAC, GMAC resets via ccu_reset for all > supported Allwinner SoCs. > > Cc: Joe Hershberger > Signed-off-by: Jagan Teki Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 02/13] net: sunxi_emac: Add CLK support
On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki wrote: > > Add CLk support for sunxi_emac to enable AHB_EMAC clock > via CLK framework. > > Cc: Joe Hershberger > Signed-off-by: Jagan Teki Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 03/13] net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle
On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki wrote:
>
> Unlike other Allwinner SoC's R40 GMAC clock control register
> is locate in CCU, but rest located via syscon itself. Since
> the phandle property for current code look for 'syscon' and
> it will grab the respective ccu or syscon base address based
> on DT property defined in respective SoC dtsi.
>
> So, use the existing 'syscon' code even for R40 for retrieving
> GMAC clock via CCU and update the register directly in
> sun8i_emac_set_syscon instead of writing it separately using
> ccm base.
>
> Cc: Joe Hershberger
> Cc: Lothar Felten
> Signed-off-by: Jagan Teki
> ---
> drivers/net/sun8i_emac.c | 55
> 1 file changed, 27 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index c9798445c7..a7fb7ac405 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata
> *pdata,
> int ret;
> u32 reg;
>
> - reg = readl(priv->sysctl_reg + 0x30);
> + if (priv->variant == R40_GMAC) {
> + /* Select RGMII for R40 */
> + reg = readl(priv->sysctl_reg + 0x164);
Please don't add more magic numbers. #define with register name.
> + reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
> + CCM_GMAC_CTRL_GPIT_RGMII |
> + CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
>
> - if (priv->variant == R40_GMAC)
> + writel(reg, priv->sysctl_reg + 0x164);
Same.
> return 0;
> + }
> +
> + reg = readl(priv->sysctl_reg + 0x30);
>
> if (priv->variant == H3_EMAC) {
> ret = sun8i_emac_set_syscon_ephy(priv, ®);
> @@ -662,13 +670,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev
> *priv)
>
> /* De-assert EMAC */
> setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
> -
> - /* Select RGMII for R40 */
> - setbits_le32(&ccm->gmac_clk_cfg,
> -CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
> -CCM_GMAC_CTRL_GPIT_RGMII);
> - setbits_le32(&ccm->gmac_clk_cfg,
> -
> CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
> } else {
> /* Set clock gating for emac */
> setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
> @@ -850,25 +851,23 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct
> udevice *dev)
> return -EINVAL;
> }
>
> - if (priv->variant != R40_GMAC) {
> - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
> - if (offset < 0) {
> - debug("%s: cannot find syscon node\n", __func__);
> - return -EINVAL;
> - }
> - reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
> - if (!reg) {
> - debug("%s: cannot find reg property in syscon node\n",
> - __func__);
> - return -EINVAL;
> - }
> - priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
> -offset, reg);
> - if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
> - debug("%s: Cannot find syscon base address\n",
> - __func__);
> - return -EINVAL;
> - }
> + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
> + if (offset < 0) {
> + debug("%s: cannot find syscon node\n", __func__);
> + return -EINVAL;
> + }
> +
> + reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
> + if (!reg) {
> + debug("%s: cannot find reg property in syscon node\n",
> + __func__);
> + return -EINVAL;
> + }
> + priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
> +offset, reg);
> + if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
> + debug("%s: Cannot find syscon base address\n", __func__);
> + return -EINVAL;
> }
>
> pdata->phy_interface = -1;
> --
> 2.18.0.321.gffc6fa0e3
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] dts: imx8qxp-mek: Add PHY post reset delay
On Fri, Mar 1, 2019 at 7:28 AM Andrejs Cainikovs wrote: > > PHY cannot be detected unless we wait about 150 ms. > > Signed-off-by: Andrejs Cainikovs Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] net: dm: fec: Support phy-reset-post-delay property
On Fri, Mar 1, 2019 at 7:28 AM Andrejs Cainikovs wrote: > > As per Linux kernel DT binding doc: > - phy-reset-post-delay : Post reset delay in milliseconds. If present then > a delay of phy-reset-post-delay milliseconds will be observed after the > phy-reset-gpios has been toggled. Can be omitted thus no delay is > observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. > > Signed-off-by: Andrejs Cainikovs Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/7] Add netcp networking support on K2G ICE EVM
On Mon, Feb 25, 2019 at 3:45 PM Murali Karicheri wrote: > > Hello Maintainer, > > On 02/25/2019 03:27 PM, Murali Karicheri wrote: > > This patch series add networking capability to K2G ICE EVM > > based on netcp driver. Networking function has been tested > > using the latest master branch from u-boot repo. Following > > boot mode has been tested for networking. > > > > Net boot (tftp images over ethernet interface and boot kernel) > >log at https://pastebin.ubuntu.com/p/b3nyCXPhWc/ > > MMC boot: (load images from boot folder of rootfs and boot kernel) > >log at https://pastebin.ubuntu.com/p/FWycmKd9KB/ > > > > Used Linux upstream linux kernel version 4.19.9 for the tests. > > > > Please review and apply if this looks good. Will do, thanks, -Joe > > > > Thanks > > > > Revision history: > > > > v4: Sorted pins by pin number in patch 1 and 2 as per comment. > > Collected Acked-by and included in patch > > v3: Addressed comment to use KConfig for enable TI PHY driver and also > > netcp driver comment to use proper function as in cpsw driver. > > Rebased to latest on master branch. > > v2: Collected Reviewed-by for patch 1 and 2. Rebased to latest > > on master > > > > Murali Karicheri (7): > >ARM: k2g-gp-evm: update to rgmii pinmux configuration > >ARM: k2g-ice: Add pinmux support for rgmii interface > >net: netcp: add support for phy with rgmii ids > >ARM: k2g: add a workaround to reset the phy > >ARM: dts: k2g-evm: remove unused phy-mode property from phy node > >k2g: config enable ti phy dp83867 for k2g > >ARM: dts: k2g-ice: add dt node for netcp > > > > arch/arm/dts/keystone-k2g-evm.dts | 1 - > > arch/arm/dts/keystone-k2g-ice.dts | 35 + > > .../mach-keystone/include/mach/hardware-k2g.h | 3 ++ > > arch/arm/mach-keystone/include/mach/mux-k2g.h | 5 ++ > > board/ti/ks2_evm/board_k2g.c | 15 ++ > > board/ti/ks2_evm/mux-k2g.h| 51 +-- > > configs/k2g_evm_defconfig | 1 + > > drivers/net/ti/keystone_net.c | 22 +++- > > 8 files changed, 116 insertions(+), 17 deletions(-) > > > > Please merge this version if looks good. Have addressed all comments > received so far. > > Murali > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/7] ARM: k2g-gp-evm: update to rgmii pinmux configuration
On Mon, Feb 25, 2019 at 2:28 PM Murali Karicheri wrote: > > This patch updates pinmux configuration for K2G GP EVM based on > data generated by the pinmux tool at > https://dev.ti.com/pinmux/app.html#/default > > Signed-off-by: Murali Karicheri > Reviewed-by: Lokesh Vutla Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 5/7] ARM: dts: k2g-evm: remove unused phy-mode property from phy node
On Thu, Feb 21, 2019 at 11:01 AM Murali Karicheri wrote: > > This patch removes the unused phy-mode property from the phy dt node. On > K2G, currently link-interface determines if phy is used or not and is > already set to use rgmii. So this is not needed. Besides phy-mode should > be added to slave interface configuration of the cpsw driver, not in the > phy node. > > Signed-off-by: Murali Karicheri Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 6/7] k2g: config enable ti phy dp83867 for k2g
On Thu, Feb 21, 2019 at 11:03 AM Murali Karicheri wrote: > > Enable ti phy dp83867 for k2g > > Signed-off-by: Murali Karicheri Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 7/7] ARM: dts: k2g-ice: add dt node for netcp
On Thu, Feb 21, 2019 at 11:03 AM Murali Karicheri wrote: > > This patch adds dt node for DP83867 phy used on K2G ICE board and > also enable netcp device nodes for the board. > > EVM hardware spec recommends to add 0.25 nsec delay in the tx > direction and 2.25 nsec delay in the rx direction for internal > delay in the clock path to be on the safer side. > > The board straps RX_DV/RX_CTRL pin of on board DP83867 phy in mode > 1. Unfortunately, the phy data manual disallows this. Add > ti,dp83867-rxctrl-strap-quirk in the phy node to allow software to > enable workaround suggested for this incorrect strap setting. This > ensures proper operation of this PHY. > > The dts bindings are kept in sync with that from 4.14.y linux > kernel. This required the pinmux device related bindings to be > commented out to allow for compilation. > > Signed-off-by: Murali Karicheri Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/7] ARM: k2g-ice: Add pinmux support for rgmii interface
On Thu, Feb 21, 2019 at 11:03 AM Murali Karicheri wrote: > > This add pinmux configuration for rgmii interface so that network > driver can be supported on K2G ICE boards. The pinmux configurations > for this are generated using the pinmux tool at > https://dev.ti.com/pinmux/app.html#/default > > As this required some BUFFER_CLASS definitions, same is re-used > from the linux defnitions in include/dt-bindings/pinctrl/keystone.h > > Signed-off-by: Murali Karicheri > Reviewed-by: Lokesh Vutla Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/7] ARM: k2g: add a workaround to reset the phy
On Thu, Feb 21, 2019 at 11:02 AM Murali Karicheri wrote: > > This patch adds a workaround to reset the phy one time during boot > using GPIO0 pin 10 to make sure, the Phy latches the configuration > from the input pins correctly. > > Signed-off-by: Murali Karicheri Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/7] net: netcp: add support for phy with rgmii ids
On Thu, Feb 21, 2019 at 11:01 AM Murali Karicheri wrote: > > Enhance the netcp driver to support phys that can be configured > for internal delay (rgmii-id, rgmii-rxid, rgmii-txid) > > Signed-off-by: Murali Karicheri Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/7] ARM: k2g-ice: Add pinmux support for rgmii interface
On Thu, Feb 21, 2019 at 11:03 AM Murali Karicheri wrote:
>
> This add pinmux configuration for rgmii interface so that network
> driver can be supported on K2G ICE boards. The pinmux configurations
> for this are generated using the pinmux tool at
> https://dev.ti.com/pinmux/app.html#/default
>
> As this required some BUFFER_CLASS definitions, same is re-used
> from the linux defnitions in include/dt-bindings/pinctrl/keystone.h
>
> Signed-off-by: Murali Karicheri
> Reviewed-by: Lokesh Vutla
> ---
> arch/arm/mach-keystone/include/mach/mux-k2g.h | 5 +
> board/ti/ks2_evm/mux-k2g.h| 19 +++
> 2 files changed, 24 insertions(+)
>
> diff --git a/arch/arm/mach-keystone/include/mach/mux-k2g.h
> b/arch/arm/mach-keystone/include/mach/mux-k2g.h
> index 809b72d5bf..67d47f8172 100644
> --- a/arch/arm/mach-keystone/include/mach/mux-k2g.h
> +++ b/arch/arm/mach-keystone/include/mach/mux-k2g.h
> @@ -27,6 +27,11 @@
> #define PIN_PTU(1 << 17) /* pull up */
> #define PIN_PTD(0 << 17) /* pull down */
>
> +#define BUFFER_CLASS_B (0 << 19)
> +#define BUFFER_CLASS_C (1 << 19)
> +#define BUFFER_CLASS_D (2 << 19)
> +#define BUFFER_CLASS_E (3 << 19)
> +
> #define MODE(m)((m) & 0x7)
> #define MAX_PIN_N 260
>
> diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h
> index 706fb7e838..8c184a85ae 100644
> --- a/board/ti/ks2_evm/mux-k2g.h
> +++ b/board/ti/ks2_evm/mux-k2g.h
> @@ -346,6 +346,25 @@ struct pin_cfg k2g_ice_evm_pin_cfg[] = {
> { 133, MODE(0) }, /* SOC_QSPI_D2 */
> { 134, MODE(0) }, /* SOC_QSPI_D3 */
> { 135, MODE(0) }, /* SOC_QSPI_CSN0 */
> +
> + /* EMAC */
> + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
> + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
> + { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
> + { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
> + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
> + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
> + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
> + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
> + { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
> + { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
> + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
> + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
Actually... please sort these by pin number.
Thanks,
-Joe
> +
> + /* MDIO */
> + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
> + { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
> +
> { MAX_PIN_N, }
> };
>
> --
> 2.17.0
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/7] ARM: k2g-gp-evm: update to rgmii pinmux configuration
On Thu, Feb 21, 2019 at 11:00 AM Murali Karicheri wrote:
>
> This patch updates pinmux configuration for K2G GP EVM based on
> data generated by the pinmux tool at
> https://dev.ti.com/pinmux/app.html#/default
>
> Signed-off-by: Murali Karicheri
> Reviewed-by: Lokesh Vutla
> ---
> board/ti/ks2_evm/mux-k2g.h | 32 +---
> 1 file changed, 17 insertions(+), 15 deletions(-)
>
> diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h
> index 8c184a85ae..89c49f9e4f 100644
> --- a/board/ti/ks2_evm/mux-k2g.h
> +++ b/board/ti/ks2_evm/mux-k2g.h
> @@ -125,21 +125,23 @@ struct pin_cfg k2g_evm_pin_cfg[] = {
> { 70, MODE(0) }, /* SOC_MMC1_SDWP */
> { 71, MODE(0) }, /* MMC1POW TP124 */
>
> - /* RGMII */
> - { 72, MODE(1) | PIN_IEN },/* SOC_RGMII_RXCLK */
> - { 77, MODE(1) | PIN_IEN },/* SOC_RGMII_RXD3 */
> - { 78, MODE(1) | PIN_IEN },/* SOC_RGMII_RXD2 */
> - { 79, MODE(1) | PIN_IEN },/* SOC_RGMII_RXD1 */
> - { 80, MODE(1) | PIN_IEN },/* SOC_RGMII_RXD0 */
> - { 81, MODE(1) | PIN_IEN },/* SOC_RGMII_RXCTL */
> - { 85, MODE(1) }, /* SOC_RGMII_TXCLK */
> - { 91, MODE(1) }, /* SOC_RGMII_TXD3 */
> - { 92, MODE(1) }, /* SOC_RGMII_TXD2 */
> - { 93, MODE(1) }, /* SOC_RGMII_TXD1 */
> - { 94, MODE(1) }, /* SOC_RGMII_TXD0 */
> - { 95, MODE(1) }, /* SOC_RGMII_TXCTL */
> - { 98, MODE(0) }, /* SOC_MDIO_DATA */
> - { 99, MODE(0) }, /* SOC_MDIO_CLK */
> + /* EMAC */
> + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
> + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
> + { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
> + { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
> + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
> + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
> + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
> + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
> + { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
> + { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
> + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
Please sort by pin number.
> + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
> +
> + /* MDIO */
> + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
> + { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
>
> /* PWM */
> { 73, MODE(4) }, /* SOC_EHRPWM3A */
> --
> 2.17.0
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: eth-uclass: call stop only for active devices
On Wed, Feb 20, 2019 at 9:01 PM Bin Meng wrote: > > On Wed, Feb 20, 2019 at 8:33 PM Keerthy wrote: > > > > Currently stop is being called unconditionally without even > > checking if start is called. In case of multiple instances eth > > being present many devices might just be initialized without > > a start call in such cases stop might lead unpredictable behaviors > > including aborts and crashes. Hence add a check before calling stop. > > > > Signed-off-by: Keerthy > > --- > > net/eth-uclass.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > Could you please provide a test case? Presumably that test should live in test/dm/eth.c with some potential support needed by drivers/net/sandbox.c Thanks, -Joe > Regards, > Bin > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: eth-uclass: call stop only for active devices
On Wed, Feb 20, 2019 at 6:33 AM Keerthy wrote:
>
> Currently stop is being called unconditionally without even
> checking if start is called. In case of multiple instances eth
> being present many devices might just be initialized without
> a start call in such cases stop might lead unpredictable behaviors
> including aborts and crashes. Hence add a check before calling stop.
>
> Signed-off-by: Keerthy
> ---
> net/eth-uclass.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/net/eth-uclass.c b/net/eth-uclass.c
> index 2ef20df192..26f7e0b8cd 100644
> --- a/net/eth-uclass.c
> +++ b/net/eth-uclass.c
> @@ -531,7 +531,8 @@ static int eth_pre_remove(struct udevice *dev)
> {
> struct eth_pdata *pdata = dev->platdata;
>
> - eth_get_ops(dev)->stop(dev);
> + if (eth_is_active(dev))
> + eth_get_ops(dev)->stop(dev);
This seems reasonable... What was the case that provoked an issue?
Which driver was having trouble?
>
> /* clear the MAC address */
> memset(pdata->enetaddr, 0, ARP_HLEN);
> --
> 2.17.1
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 06/15] net: macb: Fix clk API usage for RISC-V systems
On Wed, Feb 20, 2019 at 10:36 PM Anup Patel wrote: > > Don't fail in macb_enable_clk() if clk_enable() returns > -ENOSYS because we get -ENOSYS for fixed-rate clocks. > > Signed-off-by: Anup Patel > Reviewed-by: Bin Meng Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/3] net: phy: Add generic helpers to access MMD PHY registers
On Fri, Feb 8, 2019 at 11:29 AM Carlo Caione wrote:
>
> Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
> to allow access to the MMD PHY registers.
>
> The MMD PHY registers can be accessed by several means:
>
> 1. Using two new MMD access function hooks in the PHY driver. These
> functions can be implemented when the PHY driver does not support the
> standard IEEE Compatible clause 45 access mechanism described in clause
> 22 or if the PHY uses its own non-standard access mechanism.
>
> 2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable
> DEVADs.
>
> 3. The standard clause 45 access extensions to the MMD registers through
> the indirection registers (clause 22) in all the other cases.
>
> Signed-off-by: Carlo Caione
Except for the off-by-ones below...
Acked-by: Joe Hershberger
> ---
> drivers/net/phy/phy.c | 4 +++
> include/phy.h | 70 +++
> 2 files changed, 74 insertions(+)
>
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index cda4caa803..6769047407 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -549,6 +549,10 @@ int phy_register(struct phy_driver *drv)
> drv->readext += gd->reloc_off;
> if (drv->writeext)
> drv->writeext += gd->reloc_off;
> + if (drv->read_mmd)
> + drv->read_mmd += gd->reloc_off;
> + if (drv->write_mmd)
> + drv->write_mmd += gd->reloc_off;
> #endif
> return 0;
> }
> diff --git a/include/phy.h b/include/phy.h
> index b86fdfb2ce..7ec2b4e86c 100644
> --- a/include/phy.h
> +++ b/include/phy.h
> @@ -101,6 +101,14 @@ struct phy_driver {
> int (*readext)(struct phy_device *phydev, int addr, int devad, int
> reg);
> int (*writeext)(struct phy_device *phydev, int addr, int devad, int
> reg,
> u16 val);
> +
> + /* Phy specific driver override for reading a MMD register */
> + int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
> +
> + /* Phy specific driver override for writing a MMD register */
> + int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
> +u16 val);
> +
> struct list_head list;
> };
>
> @@ -164,6 +172,68 @@ static inline int phy_write(struct phy_device *phydev,
> int devad, int regnum,
> return bus->write(bus, phydev->addr, devad, regnum, val);
> }
>
> +static inline void phy_mmd_start_indirect(struct phy_device *phydev, int
> devad,
> + int regnum)
> +{
> + /* Write the desired MMD Devad */
> + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
> +
> + /* Write the desired MMD register address */
> + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
> +
> + /* Select the Function : DATA with no post increment */
> + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
> + (devad | MII_MMD_CTRL_NOINCR));
> +}
> +
> +static inline int phy_read_mmd(struct phy_device *phydev, int devad,
> + int regnum)
> +{
> + struct phy_driver *drv = phydev->drv;
> +
> + if (regnum > (u16)~0 || devad > 32)
Shouldn't this be >= 32?
> + return -EINVAL;
> +
> + /* driver-specific access */
> + if (drv->read_mmd)
> + return drv->read_mmd(phydev, devad, regnum);
> +
> + /* direct C45 / C22 access */
> + if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
> + devad == MDIO_DEVAD_NONE || !devad)
> + return phy_read(phydev, devad, regnum);
> +
> + /* indirect C22 access */
> + phy_mmd_start_indirect(phydev, devad, regnum);
> +
> + /* Read the content of the MMD's selected register */
> + return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
> +}
> +
> +static inline int phy_write_mmd(struct phy_device *phydev, int devad,
> + int regnum, u16 val)
> +{
> + struct phy_driver *drv = phydev->drv;
> +
> + if (regnum > (u16)~0 || devad > 32)
Same here.
> + return -EINVAL;
> +
> + /* driver-specific access */
> + if (drv->write_mmd)
> + return drv->write_mmd(phydev, devad, regnum, val);
> +
> + /* direct C45 / C22 access */
> + if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
> + devad == MDIO_DEVAD_NONE || !devad)
> + retu
Re: [U-Boot] [PATCH v5 3/3] cmd: mdio: Switch to generic helpers when accessing the registers
On Fri, Feb 8, 2019 at 11:31 AM Carlo Caione wrote: > > Switch to use the generic helpers to access the MMD registers so that we > can used the same command also for C45 PHYs, C22 PHYs with direct and > indirect access and PHYs implementing a custom way to access the > registers. > > Signed-off-by: Carlo Caione Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: net: ldpaa_eth: fix resource leak
On Fri, Feb 8, 2019 at 2:46 AM Pankaj Bansal wrote: > > if an error occurs in ldpaa_eth_init, need to free all resources > before returning the error. > > Threfore, free net_dev before returning from ldpaa_eth_init. > > Signed-off-by: Pankaj Bansal > Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
On Tue, Feb 5, 2019 at 7:37 PM Vladimir Oltean wrote: > > On 2/6/19 12:10 AM, Joe Hershberger wrote: > > On Tue, Feb 5, 2019 at 9:20 AM Carlo Caione wrote: > >> > >> On 05/02/2019 00:15, Joe Hershberger wrote: > >>> On Mon, Feb 4, 2019 at 5:39 PM Vladimir Oltean > >>> wrote: > >> > >> /cut > >>>> Which brings me to my next point. > >>>> If we can't properly make the distinction between an indirect C22 MMD > >>>> access and a proper C45 MMD access, and hence not keeping proper API > >>>> compatibility with Linux kernel, aren't we better off going back to > >>>> square 1 and using phy_read_mmd_indirect and phy_write_mmd_indirect? > >>> > >>> I think we can and should make the new wrapper functions remain named > >>> phy_*_mmd_indirect and the names of the override functions in the phy > >>> driver ops should be *_mmd_indirect. The override is still for an > >>> indirect access of c45 registers, just an apparently non-standard one. > >>> It is this way in Linux as well. > > I guess it is just me who is still unclear on this? > Since Russell King's patch "3b85d8d net: phy: remove the indirect MMD > read/write methods", the Linux API is no longer like that (the > phy_driver pointers phy_read_mmd and phy_read_mmd_indirect were merged > into one). > Just want to make sure that everybody is on the same page and we agreed > on API compatibility with pre-3b85d8d Linux. Argh. I was looking at the patch that Carlo referenced and did not look to see that it further changed. But looking at 3b85d8d I don't see how the concerns that you and Carlo discussed about determining what to do if c45 is also supported. Do you know how Linux handles this or should I do some research? > >> > >> Alright then. I'll prepare a V5. > >> > >> A couple on notes: > >> > >> 1. I'd prefer the parameters of the "mdio" command to be name "rimmd" > >> and "wimmd" for "r/w indirect MMD" to keep the (twisted) logic of the > >> mdio command code of differentiating the parameters according to > >> argv[1][1] and r/w according to argv[1][0] > > > > Is there a reason you want to keep the mmd in there? It seems implied > > by doing any access using the mdio command. > > > > Maybe wi and ri or windirect and rindirect or wind and rind? > > > > What about exposing the indirect read as > "mii read[.]"? > > It should be clear to most people (and if it isn't, it should be > clarified) that the legacy "mii" command is clause 22 only, therefore > the "." syntactic sugar must logically mean that indirect > access is what's going on when applied to "mii". The implementation can > freely call phy_read_mmd_indirect if it parses such syntax. While it is clear, I would prefer to not encourage further use of the mii command. I would rather add the ability to explicitly specify the clause in the mdio command. Perhaps the default can be to attempt to auto select, but if it is ambiguous, require the explicit specification. It could follow a similar approach to the "md" command. We can add the ability to add ".22" and ".45" to the mdio command to explicitly select. > Just my 2c. Either way, exposing an explicit command for indirect access > means that U-boot commits long-term to not trying to implicitly know > about, and populate, phydev->is_c45. While using either mdio rindirect or mii / mdio.22 read they are effectively explicit commands to select "indirect", so I'm not sure what point you are making here. -Joe > > -Vladimir > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] cmd: mdio: Add new parameter to access MMD PHY registers
On Tue, Feb 5, 2019 at 9:20 AM Carlo Caione wrote: > > On 05/02/2019 00:15, Joe Hershberger wrote: > > On Mon, Feb 4, 2019 at 5:39 PM Vladimir Oltean > > wrote: > > /cut > >> Which brings me to my next point. > >> If we can't properly make the distinction between an indirect C22 MMD > >> access and a proper C45 MMD access, and hence not keeping proper API > >> compatibility with Linux kernel, aren't we better off going back to > >> square 1 and using phy_read_mmd_indirect and phy_write_mmd_indirect? > > > > I think we can and should make the new wrapper functions remain named > > phy_*_mmd_indirect and the names of the override functions in the phy > > driver ops should be *_mmd_indirect. The override is still for an > > indirect access of c45 registers, just an apparently non-standard one. > > It is this way in Linux as well. > > Alright then. I'll prepare a V5. > > A couple on notes: > > 1. I'd prefer the parameters of the "mdio" command to be name "rimmd" > and "wimmd" for "r/w indirect MMD" to keep the (twisted) logic of the > mdio command code of differentiating the parameters according to > argv[1][1] and r/w according to argv[1][0] Is there a reason you want to keep the mmd in there? It seems implied by doing any access using the mdio command. Maybe wi and ri or windirect and rindirect or wind and rind? > 2. Since [0] needs a respin as well after the requested changes, I'm > going to embedded that patch into this patchset. Sounds good. > > Cheers > > [0] https://lists.denx.de/pipermail/u-boot/2019-January/356019.html > > -- > Carlo Caione > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
