[U-Boot] [PATCH 2/2] GPIO: pca953x: fix error reporting
Use the standard CMD_RET_* constants to clearly report errors from the
pca953x command. In addition, print error messages when I2C communication
fails.
Signed-off-by: Laurence Withers
---
drivers/gpio/pca953x.c | 49 ++-
1 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index 64c7797..be13745 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c
@@ -221,7 +221,7 @@ cmd_tbl_t cmd_pca953x[] = {
int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
- int val;
+ int ret = CMD_RET_USAGE, val;
ulong ul_arg2 = 0;
ulong ul_arg3 = 0;
cmd_tbl_t *c;
@@ -232,7 +232,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
if (!c || !((argc == (c->maxargs)) ||
(((int)c->cmd == PCA953X_CMD_DEVICE) &&
(argc == (c->maxargs - 1) {
- return cmd_usage(cmdtp);
+ return CMD_RET_USAGE;
}
/* arg2 used as chip number or pin number */
@@ -246,32 +246,53 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
switch ((int)c->cmd) {
#ifdef CONFIG_CMD_PCA953X_INFO
case PCA953X_CMD_INFO:
- return pca953x_info(chip);
+ ret = pca953x_info(chip);
+ if (ret)
+ ret = CMD_RET_FAILURE;
+ break;
#endif
+
case PCA953X_CMD_DEVICE:
if (argc == 3)
chip = (uint8_t)ul_arg2;
printf("Current device address: 0x%x\n", chip);
- return 0;
+ ret = CMD_RET_SUCCESS;
+ break;
+
case PCA953X_CMD_INPUT:
- pca953x_set_dir(chip, (1 << ul_arg2),
+ ret = pca953x_set_dir(chip, (1 << ul_arg2),
PCA953X_DIR_IN << ul_arg2);
val = (pca953x_get_val(chip) & (1 << ul_arg2)) != 0;
- printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2, val);
- return val;
+ if (ret)
+ ret = CMD_RET_FAILURE;
+ else
+ printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2,
+ val);
+ break;
+
case PCA953X_CMD_OUTPUT:
- pca953x_set_dir(chip, (1 << ul_arg2),
+ ret = pca953x_set_dir(chip, (1 << ul_arg2),
(PCA953X_DIR_OUT << ul_arg2));
- return pca953x_set_val(chip, (1 << ul_arg2),
- (ul_arg3 << ul_arg2));
+ if (!ret)
+ ret = pca953x_set_val(chip, (1 << ul_arg2),
+ (ul_arg3 << ul_arg2));
+ if (ret)
+ ret = CMD_RET_FAILURE;
+ break;
+
case PCA953X_CMD_INVERT:
- return pca953x_set_pol(chip, (1 << ul_arg2),
+ ret = pca953x_set_pol(chip, (1 << ul_arg2),
(ul_arg3 << ul_arg2));
- default:
- /* We should never get here */
- return 1;
+ if (ret)
+ ret = CMD_RET_FAILURE;
+ break;
}
+
+ if (ret == CMD_RET_FAILURE)
+ eprintf("Error talking to chip at 0x%x\n", chip);
+
+ return ret;
}
U_BOOT_CMD(
--
1.7.2.5
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[U-Boot] [PATCH 1/2] GPIO: pca953x: fix spelling in help
Signed-off-by: Laurence Withers --- drivers/gpio/pca953x.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 359fdee..64c7797 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -287,7 +287,7 @@ U_BOOT_CMD( " - set pin as output and drive low or high\n" "pca953x invert pin 0|1\n" " - disable/enable polarity inversion for reads\n" - "pca953x intput pin\n" + "pca953x input pin\n" " - set pin as input and read value" ); -- 1.7.2.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] DaVinci DA8xx: fix set_cpu_clk_info()
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
initialising the DSP frequency, leading to 'bdinfo' command output such as:
[...snip...]
ARM frequency = 300 MHz
DSP frequency = -536870913 MHz
DDR frequency = 300 MHz
This commit provides a separate implementation of set_cpu_clk_info() for
the DA8xx SoCs that initialises the DSP frequency to zero (since
currently the DSP is not enabled by U-Boot on any DA8xx platform). The
separate implementation is justified because there is no common code
between DA8xx and the other SoC families. It is now much easier to
understand the flow of the two separate functions.
Signed-off-by: Laurence Withers
Cc: Tom Rini
Cc: Hadli, Manjunath
Cc: Heiko Schocher
---
arch/arm/cpu/arm926ejs/davinci/cpu.c | 21 +
1 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 6cb857a..4bdb08b 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -117,6 +117,16 @@ int clk_get(enum davinci_clk_ids id)
out:
return pll_out;
}
+
+int set_cpu_clk_info(void)
+{
+ gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
+ /* DDR PHY uses an x2 input clock */
+ gd->bd->bi_ddr_freq = clk_get(0x10001) / 100;
+ gd->bd->bi_dsp_freq = 0;
+ return 0;
+}
+
#else /* CONFIG_SOC_DA8XX */
static unsigned pll_div(volatile void *pllbase, unsigned offset)
@@ -187,16 +197,9 @@ unsigned int davinci_clk_get(unsigned int div)
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 100;
}
#endif
-#endif /* !CONFIG_SOC_DA8XX */
int set_cpu_clk_info(void)
{
-#ifdef CONFIG_SOC_DA8XX
- gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
- /* DDR PHY uses an x2 input clock */
- gd->bd->bi_ddr_freq = clk_get(0x10001) / 100;
-#else
-
unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
#if defined(CONFIG_SOC_DM365)
pllbase = DAVINCI_PLL_CNTRL1_BASE;
@@ -215,10 +218,12 @@ int set_cpu_clk_info(void)
pllbase = DAVINCI_PLL_CNTRL0_BASE;
#endif
gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
-#endif
+
return 0;
}
+#endif /* !CONFIG_SOC_DA8XX */
+
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
--
1.7.2.5
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Re: [U-Boot] [PATCH v3 1/8] da850: indicate cache usage disable in config file
On Thu, Aug 18, 2011 at 11:13:19AM -0400, Ben Gardiner wrote: > I understand that both Laurence and Stefan (cc'd) have confirmed that > there dcache issues with the EMA; I am assuming that the 'issue' > results in a delay in tftp'ing... No; the issue was that packets were being sent on to the wire with incorrect IP checksums. It twigged that the problem was cache coherency when I put a full hexdump of each outgoing packet in and suddenly the outbound packets started being valid. > Disabling the caches will slow down decompression which will slow down > boot overall when booting from flash. > > Rather than masking the issue by disabling caches and slowing down > u-boot for it's users perhaps TI should be fixing the EMAC drivers' > cache bugs instead? Indeed, the correct solution is to properly manage the net buffers with respect to the cache, although I have not attempted that change myself. I have seen some patches start to flow that make changes in drivers to work correctly with caches enabled, such as http://lists.denx.de/pipermail/u-boot/2011-August/098484.html . Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] davinci: add support for printing clock frequency
atch the rest of the file (even if the rest of the file
is wrong, and this patch has used tabs as it should have).
> diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
> index 3d78274..500e216 100644
> --- a/arch/arm/lib/board.c
> +++ b/arch/arm/lib/board.c
> @@ -463,7 +463,15 @@ void board_init_r(gd_t *id, ulong dest_addr)
>
> debug("monitor flash len: %08lX\n", monitor_flash_len);
> board_init(); /* Setup chipselects */
> -
> + /*
> + * TODO: printing of the clock inforamtion of the board is now
> + * implemented as part of bdinfo command. Currently only support for
> + * davinci SOC's is added. Remove this check once all the board
> + * implement this.
> + */
> +#ifdef CONFIG_CLOCKS
> + set_cpu_clk_info(); /* Setup clock information */
> +#endif
> #ifdef CONFIG_SERIAL_MULTI
> serial_initialize();
> #endif
> diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
> index 97f2945..5359a47 100644
> --- a/common/cmd_bdinfo.c
> +++ b/common/cmd_bdinfo.c
> @@ -370,6 +370,15 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char
> * const argv[])
> print_num("irq_sp", gd->irq_sp);/* irq stack pointer */
> print_num("sp start ", gd->start_addr_sp);
> print_num("FB base ", gd->fb_base);
> + /*
> + * TODO: Currently only support for davinci SOC's is added.
> + * Remove this check once all the board implement this.
> + */
> +#ifdef CONFIG_CLOCKS
> + printf("ARM frequency = %ld MHz\n", gd->bd->bi_arm_freq);
> + printf("DSP frequency = %ld MHz\n", gd->bd->bi_dsp_freq);
> + printf("DDR frequency = %ld MHz\n", gd->bd->bi_ddr_freq);
> +#endif
> return 0;
> }
>
Again, here it is implied that the only clocks we'll ever want to print are
ARM, DSP and DDR. Seems way too specific for such common code.
Bye for now,
--
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Direct tel:+447753988197 or tel:+44408643 Software Engineer
General support queries: CMG-DCM CMG-EAM CMG-NAM
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Re: [U-Boot] [WIP, PATCH] initcall: An outline of the idea
Hi Graeme,
On Fri, Mar 02, 2012 at 10:05:12PM +1100, Graeme Russ wrote:
> diff --git a/doc/README.INIT_FUNC b/doc/README.INIT_FUNC
> new file mode 100644
> index 000..b545390
> --- /dev/null
> +++ b/doc/README.INIT_FUNC
> @@ -0,0 +1,31 @@
> +The INIT_FUNC macro allows initialisation functions (i.e. functions which are
> +executed before the main loop) to be easily added to the init sequence
> +
> +The format of the INIT_FUNC macro is:
> +
> +INIT_FUNC({function_name}, {init_class}, {prerequisite init_class(es)})
> +
> +{function_name} is the name of the init function to call. This function must
> +have the following prototype:
> +
> +int foo(void);
> +
> +Each init function must return 0 to indicate success - any other return value
> +indicates failure and the init sequence will stop
> +
> +{init_class} is a simple test string to describe the basic purpose of the
> init
> +function. Multiple init functions may share the same init_class string
> +
> +{prerequisite init_class(es)} is a list of init_class strings (see above)
> which
> +defines what init functions are executed before and after the given init
> +function. Each prerequisite init_class is seperated by a space and preceeded
> by
> +either:
> + * - At least one function of this init class must exist (i.e. there must be
> at
> + least one INIT_FUNC entry with {init_class} set to the init class named
> + after the '*' - All init functions with an init class matching the class
> + named after the '*' will be executed before this function
> + + - All init functions with an init class matching the class named after the
> + '+' will be executed before this function, but there does not need to be
> + any functions with the named init class in the init sequence
> + - - This function will be called before any other functions with the init
> + class named after the '-'
What happens if there's a set of dependencies that cannot be resolved? From
reading the above, it seems I can do something like this:
INIT_FUNC(ifunc1, class1, *class2);
INIT_FUNC(ifunc2, class2, *class1);
It would also seem that if you want to change the prerequisites for a given
init_class, you need to find every instance of INIT_FUNC for that init_class
and change it.
Perhaps there's a better way of solving this, but it maybe there should be a
separate place which names the init classes and their prerequisites?
> diff --git a/include/initcall.h b/include/initcall.h
> new file mode 100644
> index 000..a81cf21
> --- /dev/null
> +++ b/include/initcall.h
> @@ -0,0 +1,19 @@
> +#ifndef __INIT_CALL_H__
> +#define __INIT_CALL_H__
> +#include
> +#define INIT_FUNC(fn, init_name, deps) \
> + static const char __init_func_ ## fn[] __used \
> + __attribute__((__section__(".initfuncs"))) = \
> + "(" #fn ":" #init_name ";" #deps ")\n";
> +
> +#define SKIP_INIT(init_name) \
> + static const char __skip_init_ ## req[] __used \
> + __attribute__((__section__(".initfuncs"))) = \
> + "{" #init_name "}\n";
> +
> +#define REPLACE_INIT(old_func, new_func) \
> + static const char __replace_init_ ## old_func[] __used \
> + __attribute__((__section__(".initfuncs"))) = \
> + "[" #old_func "," #new_func "]\n";
> +
> +#endif /* !__INIT_CALL_H__ */
What are SKIP_INIT() and REPLACE_INIT() used for?
Perhaps the macro could be expanded to include a prototype for the function,
so that gcc complains with a useful error message if there's a type mismatch.
Bye for now,
--
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General support queries: CMG-DCM CMG-EAM CMG-NAM
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Re: [U-Boot] [WIP, PATCH] initcall: An outline of the idea
On Sat, Mar 03, 2012 at 11:46:01PM +1100, Graeme Russ wrote:
> > Perhaps the macro could be expanded to include a prototype for the function,
>
> How so - Can you provide a code example?
Sure, since all the functions are int(*)(void), just something like this:
+#define INIT_FUNC(fn, init_name, deps) \
+static int ##fn (void); \
+static const char __init_func_ ## fn[] __used \
+__attribute__((__section__(".initfuncs"))) = \
+"(" #fn ":" #init_name ";" #deps ")\n";
(I'm guessing static is OK for this use case?).
The patch overall looks like it will make it a lot simpler to understand and
change the sequence initialisation functions are called, which is a very good
thing. I'm just mindful of getting easy-to-diagnose error messages back when
things go wrong.
An example:
static int f1(int x)
{
return x + 1;
}
#define INIT_FUNC(fn) \
static void fn(int)
INIT_FUNC(f1);
gcc immediately throws the following error:
t2.c:9: error: conflicting types for ‘f1’
t2.c:1: note: previous definition of ‘f1’ was here
which is pretty clear.
Bye for now,
--
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Re: [U-Boot] [WIP, PATCH] initcall: An outline of the idea
On Sun, Mar 04, 2012 at 11:58:27AM +, Laurence Withers wrote: > +#define INIT_FUNC(fn, init_name, deps) \ > +static int ##fn (void); \ ^^ Excuse the macro catenation operator; that shouldn't be there. Hopefully the example made it clear. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] spl: add ymodem support
On Wed, Mar 07, 2012 at 12:54:05AM +0400, Mikhail Kshevetskiy wrote: > We have an omap l138 based board without jtag and empty spi flash. > UART is an only way to load something on this board, so we are using > uart to load spl image u-boot and then we are using ymodem to load > the rest part of u-boot. Dear Mikhail, I am asking mainly out of curiousity, rather than giving feedback on the patch, but the OMAP-L138 boot ROM has the capability to load both SPL and U-Boot into empty SPI flash using the UART and sfh program or equivalent. (sfh is "serial flash host" for those following along, a program to talk to the boot ROM over the UART and download some code that the boot ROM can burn into SPI flash). What is the advantage in allowing the SPL to flash U-Boot also? Many thanks, and bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] miiphy: use strcpy() not sprintf()
In miiphy_register() the new device's name was initialised by passing a string parameter as the format string to sprintf(). As this would cause problems if it ever contained a '%' symbol, switch to using strcpy() instead. Signed-off-by: Laurence Withers Cc: Andy Fleming --- common/miiphyutil.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/miiphyutil.c b/common/miiphyutil.c index bcab74e..0ddf88e 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -141,7 +141,7 @@ void miiphy_register(const char *name, /* initalize mii_dev struct fields */ new_dev->read = legacy_miiphy_read; new_dev->write = legacy_miiphy_write; - sprintf(new_dev->name, name); + strcpy(new_dev->name, name); ldev->read = read; ldev->write = write; new_dev->priv = ldev; -- 1.7.2.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] miiphy: use strncpy() not sprintf()
In miiphy_register() the new device's name was initialised by passing a string parameter as the format string to sprintf(). As this would cause problems if it ever contained a '%' symbol, switch to using strncpy() instead. Signed-off-by: Laurence Withers Cc: Andy Fleming --- Changes for v2: - Use strncpy() rather than plain strcpy() for extra safety. --- common/miiphyutil.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/common/miiphyutil.c b/common/miiphyutil.c index bcab74e..bc9896e 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -141,7 +141,8 @@ void miiphy_register(const char *name, /* initalize mii_dev struct fields */ new_dev->read = legacy_miiphy_read; new_dev->write = legacy_miiphy_write; - sprintf(new_dev->name, name); + strncpy(new_dev->name, name, MDIO_NAME_LEN); + new_dev->name[MDIO_NAME_LEN - 1] = 0; ldev->read = read; ldev->write = write; new_dev->priv = ldev; -- 1.7.2.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] integratorap: disable dcache
On Fri, Jul 15, 2011 at 09:42:53AM +0200, Heiko Schocher wrote: > Hmm.. trying bootm with actual u-boot on a davinci (arm926ejs) based > board, there I couldn;t use the Davinci-EMAC (if I disable the dcache > it works ...) I can confirm there are some cache coherency problems with the DaVinci EMAC driver. I've done a port to a new board based on the DA850 and had problems with corrupt Ethernet packets until I disabled the dcache altogether. The clue was the packets started working when I added a hex dump just before eth_send()! While I haven't come across any explicit documentation I presume the EMAC controller's independent DMA engine is simply not aware of the ARM's cache. I haven't yet identified whether there's some mechanism already in U-Boot for marking particular bits of memory as uncacheable, which would seem to be the correct approach, but turning of dcache doesn't really have any side effects that cause problems for me. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] miiphy: use strcpy() not sprintf()
On Thu, Jul 14, 2011 at 02:02:42PM -0400, Mike Frysinger wrote: > On Thursday, July 14, 2011 09:49:23 Albert ARIBAUD wrote: > > Please use strncpy() which will also guard against overflows. > > or BUG_ON(strlen(name) >= MDIO_NAME_LEN) > -mike Patch v3 has both. The original code did have a check for the name overflowing but BUG_ON() is IMO clearer so I switched to using it instead. I kept strncpy() in v3, rather than just strcpy(), because it makes the code robust against future edits. Thanks for the feedback. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] miiphy: use strncpy() not sprintf()
In miiphy_register() the new device's name was initialised by passing a
string parameter as the format string to sprintf(). As this would cause
problems if it ever contained a '%' symbol, switch to using strncpy()
instead.
Signed-off-by: Laurence Withers
Cc: Andy Fleming
---
Changes for v2:
- Use strncpy() rather than plain strcpy() for extra safety.
Changes for v3:
- Use BUG_ON() as an additional safety measure to ensure the name never
exceeds the buffer size MDIO_NAME_LEN, simplifying the previous test.
---
common/miiphyutil.c | 14 --
1 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index bcab74e..35ad357 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -111,7 +111,8 @@ void miiphy_register(const char *name,
{
struct mii_dev *new_dev;
struct legacy_mii_dev *ldev;
- unsigned int name_len;
+
+ BUG_ON(strlen(name) >= MDIO_NAME_LEN);
/* check if we have unique name */
new_dev = miiphy_get_dev_by_name(name);
@@ -121,14 +122,6 @@ void miiphy_register(const char *name,
}
/* allocate memory */
- name_len = strlen(name);
- if (name_len > MDIO_NAME_LEN - 1) {
- /* Hopefully this won't happen, but if it does, we'll know */
- printf("miiphy_register: MDIO name was longer than %d\n",
- MDIO_NAME_LEN);
- return;
- }
-
new_dev = mdio_alloc();
ldev = malloc(sizeof(*ldev));
@@ -141,7 +134,8 @@ void miiphy_register(const char *name,
/* initalize mii_dev struct fields */
new_dev->read = legacy_miiphy_read;
new_dev->write = legacy_miiphy_write;
- sprintf(new_dev->name, name);
+ strncpy(new_dev->name, name, MDIO_NAME_LEN);
+ new_dev->name[MDIO_NAME_LEN - 1] = 0;
ldev->read = read;
ldev->write = write;
new_dev->priv = ldev;
--
1.7.2.5
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Re: [U-Boot] [PATCH] miiphy: use strncpy() not sprintf()
On Fri, Jul 15, 2011 at 09:21:45AM +, Laurence Withers wrote: > In miiphy_register() the new device's name was initialised by passing a > string parameter as the format string to sprintf(). As this would cause > problems if it ever contained a '%' symbol, switch to using strncpy() > instead. My apologies; I have missed the "v3" tag in the subject. I shall repost. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] miiphy: use strncpy() not sprintf()
In miiphy_register() the new device's name was initialised by passing a
string parameter as the format string to sprintf(). As this would cause
problems if it ever contained a '%' symbol, switch to using strncpy()
instead.
Signed-off-by: Laurence Withers
Cc: Andy Fleming
---
Changes for v2:
- Use strncpy() rather than plain strcpy() for extra safety.
Changes for v3:
- Use BUG_ON() as an additional safety measure to ensure the name never
exceeds the buffer size MDIO_NAME_LEN, simplifying the previous test.
---
common/miiphyutil.c | 14 --
1 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index bcab74e..35ad357 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -111,7 +111,8 @@ void miiphy_register(const char *name,
{
struct mii_dev *new_dev;
struct legacy_mii_dev *ldev;
- unsigned int name_len;
+
+ BUG_ON(strlen(name) >= MDIO_NAME_LEN);
/* check if we have unique name */
new_dev = miiphy_get_dev_by_name(name);
@@ -121,14 +122,6 @@ void miiphy_register(const char *name,
}
/* allocate memory */
- name_len = strlen(name);
- if (name_len > MDIO_NAME_LEN - 1) {
- /* Hopefully this won't happen, but if it does, we'll know */
- printf("miiphy_register: MDIO name was longer than %d\n",
- MDIO_NAME_LEN);
- return;
- }
-
new_dev = mdio_alloc();
ldev = malloc(sizeof(*ldev));
@@ -141,7 +134,8 @@ void miiphy_register(const char *name,
/* initalize mii_dev struct fields */
new_dev->read = legacy_miiphy_read;
new_dev->write = legacy_miiphy_write;
- sprintf(new_dev->name, name);
+ strncpy(new_dev->name, name, MDIO_NAME_LEN);
+ new_dev->name[MDIO_NAME_LEN - 1] = 0;
ldev->read = read;
ldev->write = write;
new_dev->priv = ldev;
--
1.7.2.5
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[U-Boot] [PATCH 0/4] DaVinci/DA8xx cleanups
Some general cleanup patches for the DaVinci/DA8xx CPUs made in preparation for porting to a new board based on the DA850. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] DA8xx: fix LPSC constants
Some of the LPSC constants were incorrect, and some were missing. This commit fixes the incorrect constants (which were not used anywhere in the tree) and adds all constants for both DA830 and DA850, as per the TI datasheets. Signed-off-by: Laurence Withers --- arch/arm/include/asm/arch-davinci/hardware.h | 43 ++--- 1 files changed, 31 insertions(+), 12 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 551b469..f537c4b 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -234,27 +234,46 @@ typedef volatile unsigned int * dv_reg_p; /* for LPSCs in PSC1, offset from 32 for differentiation */ #define DAVINCI_LPSC_PSC1_BASE 32 -#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 1) -#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 2) +#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1) +#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2) #define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3) #define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4) #define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5) #define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6) #define DAVINCI_LPSC_McASP0(DAVINCI_LPSC_PSC1_BASE + 7) -#define DAVINCI_LPSC_McASP1(DAVINCI_LPSC_PSC1_BASE + 8) -#define DAVINCI_LPSC_McASP2(DAVINCI_LPSC_PSC1_BASE + 9) #define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10) #define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11) #define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12) #define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13) -#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 14) -#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 15) -#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 16) -#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 17) -#define DAVINCI_LPSC_SCR_P0(DAVINCI_LPSC_PSC1_BASE + 18) -#define DAVINCI_LPSC_SCR_P1(DAVINCI_LPSC_PSC1_BASE + 19) -#define DAVINCI_LPSC_CR_P3 (DAVINCI_LPSC_PSC1_BASE + 20) -#define DAVINCI_LPSC_L3_CBA_RAM(DAVINCI_LPSC_PSC1_BASE + 21) +#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16) +#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17) +#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20) +#define DAVINCI_LPSC_L3_CBA_RAM(DAVINCI_LPSC_PSC1_BASE + 31) + +/* DA830-specific peripherals */ +#define DAVINCI_LPSC_McASP1(DAVINCI_LPSC_PSC1_BASE + 8) +#define DAVINCI_LPSC_McASP2(DAVINCI_LPSC_PSC1_BASE + 9) +#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21) +#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24) +#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25) +#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26) + +/* DA850-specific peripherals */ +#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0) +#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8) +#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9) +#define DAVINCI_LPSC_McBSP0(DAVINCI_LPSC_PSC1_BASE + 14) +#define DAVINCI_LPSC_McBSP1(DAVINCI_LPSC_PSC1_BASE + 15) +#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18) +#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19) +#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21) +#define DAVINCI_LPSC_SCR_F0(DAVINCI_LPSC_PSC1_BASE + 24) +#define DAVINCI_LPSC_SCR_F1(DAVINCI_LPSC_PSC1_BASE + 25) +#define DAVINCI_LPSC_SCR_F2(DAVINCI_LPSC_PSC1_BASE + 26) +#define DAVINCI_LPSC_SCR_F6(DAVINCI_LPSC_PSC1_BASE + 27) +#define DAVINCI_LPSC_SCR_F7(DAVINCI_LPSC_PSC1_BASE + 28) +#define DAVINCI_LPSC_SCR_F8(DAVINCI_LPSC_PSC1_BASE + 29) +#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30) #endif /* CONFIG_SOC_DA8XX */ -- 1.7.2.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] DaVinci EMAC: declare function for all DA8xx CPUs
The function davinci_emac_mii_mode_sel() is defined in board/davinci/common/misc.c for any DA8xx CPU which has CONFIG_DRIVER_TI_EMAC enabled. However, the prototype was only being declared in for the DA850 EVM board. This patch declares it for all DA8xx CPUs where CONFIG_DRIVER_TI_EMAC is enabled. Signed-off-by: Laurence Withers --- arch/arm/include/asm/arch-davinci/davinci_misc.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h index 347aa89..211b769 100644 --- a/arch/arm/include/asm/arch-davinci/davinci_misc.h +++ b/arch/arm/include/asm/arch-davinci/davinci_misc.h @@ -57,7 +57,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); int davinci_configure_pin_mux_items(const struct pinmux_resource *item, int n_items); -#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM) +#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX) void davinci_emac_mii_mode_sel(int mode_sel); #endif #if defined(CONFIG_SOC_DA8XX) -- 1.7.2.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] DA8xx: switch an enum to defines for consistency
There are two main sets of LPSC constants, depending on the processor
family. The DA8xx constants were given in an enum whereas the non-DA8xx
constants were preprocessor defines. This commit switches the DA8xx
constants to defines for consistency.
Signed-off-by: Laurence Withers
---
arch/arm/include/asm/arch-davinci/hardware.h | 81 +-
1 files changed, 40 insertions(+), 41 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index d5d4211..551b469 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -215,47 +215,46 @@ typedef volatile unsigned int * dv_reg_p;
#else /* CONFIG_SOC_DA8XX */
-enum davinci_lpsc_ids {
- DAVINCI_LPSC_TPCC = 0,
- DAVINCI_LPSC_TPTC0,
- DAVINCI_LPSC_TPTC1,
- DAVINCI_LPSC_AEMIF,
- DAVINCI_LPSC_SPI0,
- DAVINCI_LPSC_MMC_SD,
- DAVINCI_LPSC_AINTC,
- DAVINCI_LPSC_ARM_RAM_ROM,
- DAVINCI_LPSC_SECCTL_KEYMGR,
- DAVINCI_LPSC_UART0,
- DAVINCI_LPSC_SCR0,
- DAVINCI_LPSC_SCR1,
- DAVINCI_LPSC_SCR2,
- DAVINCI_LPSC_DMAX,
- DAVINCI_LPSC_ARM,
- DAVINCI_LPSC_GEM,
- /* for LPSCs in PSC1, offset from 32 for differentiation */
- DAVINCI_LPSC_PSC1_BASE = 32,
- DAVINCI_LPSC_USB11,
- DAVINCI_LPSC_USB20,
- DAVINCI_LPSC_GPIO,
- DAVINCI_LPSC_UHPI,
- DAVINCI_LPSC_EMAC,
- DAVINCI_LPSC_DDR_EMIF,
- DAVINCI_LPSC_McASP0,
- DAVINCI_LPSC_McASP1,
- DAVINCI_LPSC_McASP2,
- DAVINCI_LPSC_SPI1,
- DAVINCI_LPSC_I2C1,
- DAVINCI_LPSC_UART1,
- DAVINCI_LPSC_UART2,
- DAVINCI_LPSC_LCDC,
- DAVINCI_LPSC_ePWM,
- DAVINCI_LPSC_eCAP,
- DAVINCI_LPSC_eQEP,
- DAVINCI_LPSC_SCR_P0,
- DAVINCI_LPSC_SCR_P1,
- DAVINCI_LPSC_CR_P3,
- DAVINCI_LPSC_L3_CBA_RAM
-};
+#define DAVINCI_LPSC_TPCC 0
+#define DAVINCI_LPSC_TPTC0 1
+#define DAVINCI_LPSC_TPTC1 2
+#define DAVINCI_LPSC_AEMIF 3
+#define DAVINCI_LPSC_SPI0 4
+#define DAVINCI_LPSC_MMC_SD5
+#define DAVINCI_LPSC_AINTC 6
+#define DAVINCI_LPSC_ARM_RAM_ROM 7
+#define DAVINCI_LPSC_SECCTL_KEYMGR 8
+#define DAVINCI_LPSC_UART0 9
+#define DAVINCI_LPSC_SCR0 10
+#define DAVINCI_LPSC_SCR1 11
+#define DAVINCI_LPSC_SCR2 12
+#define DAVINCI_LPSC_DMAX 13
+#define DAVINCI_LPSC_ARM 14
+#define DAVINCI_LPSC_GEM 15
+
+/* for LPSCs in PSC1, offset from 32 for differentiation */
+#define DAVINCI_LPSC_PSC1_BASE 32
+#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 1)
+#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 2)
+#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
+#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
+#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
+#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
+#define DAVINCI_LPSC_McASP0(DAVINCI_LPSC_PSC1_BASE + 7)
+#define DAVINCI_LPSC_McASP1(DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_McASP2(DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
+#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
+#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
+#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
+#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 14)
+#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 15)
+#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 16)
+#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 17)
+#define DAVINCI_LPSC_SCR_P0(DAVINCI_LPSC_PSC1_BASE + 18)
+#define DAVINCI_LPSC_SCR_P1(DAVINCI_LPSC_PSC1_BASE + 19)
+#define DAVINCI_LPSC_CR_P3 (DAVINCI_LPSC_PSC1_BASE + 20)
+#define DAVINCI_LPSC_L3_CBA_RAM(DAVINCI_LPSC_PSC1_BASE + 21)
#endif /* CONFIG_SOC_DA8XX */
--
1.7.2.5
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[U-Boot] [PATCH 2/4] DA8xx: add MMC/SD controller addresses
Signed-off-by: Laurence Withers --- arch/arm/include/asm/arch-davinci/hardware.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index df3f549..d5d4211 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -140,6 +140,8 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e2 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 +#define DAVINCI_MMC_SD0_BASE 0x01c4 +#define DAVINCI_MMC_SD1_BASE 0x01e1b000 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x6800 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x4000 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x6000 -- 1.7.2.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] DA8xx: add generic GPIO driver
This adds a generic GPIO driver fulfilling the interface for the TI DaVinci DA8xx CPU. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] DaVinci: rename gpio_defs.h to gpio.h
In preparation for a generic GPIO driver for the DA8xx processors,
rename to and fix up all files
which include it.
Signed-off-by: Laurence Withers
---
arch/arm/include/asm/arch-davinci/gpio.h | 66 +
arch/arm/include/asm/arch-davinci/gpio_defs.h | 66 -
board/davinci/dm355leopard/dm355leopard.c |2 +-
board/davinci/dm365evm/dm365evm.c |2 +-
drivers/usb/musb/da8xx.h |2 +-
5 files changed, 69 insertions(+), 69 deletions(-)
create mode 100644 arch/arm/include/asm/arch-davinci/gpio.h
delete mode 100644 arch/arm/include/asm/arch-davinci/gpio_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/gpio.h
b/arch/arm/include/asm/arch-davinci/gpio.h
new file mode 100644
index 000..1be2ac2
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/gpio.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _GPIO_DEFS_H_
+#define _GPIO_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+#define DAVINCI_GPIO_BINTEN0x01C67008
+#define DAVINCI_GPIO_BANK010x01C67010
+#define DAVINCI_GPIO_BANK230x01C67038
+#define DAVINCI_GPIO_BANK450x01C67060
+#define DAVINCI_GPIO_BANK670x01C67088
+
+#else /* CONFIG_SOC_DA8XX */
+#define DAVINCI_GPIO_BINTEN0x01E26008
+#define DAVINCI_GPIO_BANK010x01E26010
+#define DAVINCI_GPIO_BANK230x01E26038
+#define DAVINCI_GPIO_BANK450x01E26060
+#define DAVINCI_GPIO_BANK670x01E26088
+#endif /* CONFIG_SOC_DA8XX */
+
+struct davinci_gpio {
+ unsigned int dir;
+ unsigned int out_data;
+ unsigned int set_data;
+ unsigned int clr_data;
+ unsigned int in_data;
+ unsigned int set_rising;
+ unsigned int clr_rising;
+ unsigned int set_falling;
+ unsigned int clr_falling;
+ unsigned int intstat;
+};
+
+struct davinci_gpio_bank {
+ int num_gpio;
+ unsigned int irq_num;
+ unsigned int irq_mask;
+ unsigned long *in_use;
+ unsigned long base;
+};
+
+#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
+#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
+#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
+#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
+
+#endif
diff --git a/arch/arm/include/asm/arch-davinci/gpio_defs.h
b/arch/arm/include/asm/arch-davinci/gpio_defs.h
deleted file mode 100644
index 1be2ac2..000
--- a/arch/arm/include/asm/arch-davinci/gpio_defs.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _GPIO_DEFS_H_
-#define _GPIO_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-#define DAVINCI_GPIO_BINTEN0x01C67008
-#define DAVINCI_GPIO_BANK010x01C67010
-#define DAVINCI_GPIO_BANK230x01C67038
-#define DAVINCI_GPIO_BANK450x01C67060
-#define DAVINCI_GPIO_BANK670x01C67088
-
-#else /* CONFIG_SOC_DA8XX */
-#define DAVINCI_GPIO_BINTEN0x01E26008
-#define DAVINCI_GPIO_BANK010x01E26010
-#define DAVINCI_GPIO_BANK230x01E26038
-#define DAVINCI_GPIO_BANK450x01E26060
-#define DAVINCI_GPIO_BANK670x01E26088
-#endif /* CONFIG_SOC_DA8XX */
-
-struct davinci_gpio {
- unsigned int dir;
- unsigned int out_data;
- unsigned int set_data;
- unsigned int clr_data;
- unsigned
[U-Boot] [PATCH 2/2] DA8xx: add generic GPIO driver
Add a generic GPIO driver for the DaVinci DA8xx processors. It is turned
on by defining CONFIG_DA8XX_GPIO and fulfills the generic GPIO interface
specified in . The driver has support for both manipulating
GPIO pins as well as automatically configuring the pin multiplexor
registers to set the pin function to GPIO.
Signed-off-by: Laurence Withers
---
arch/arm/include/asm/arch-davinci/gpio.h |8 +
drivers/gpio/Makefile|1 +
drivers/gpio/da8xx_gpio.c| 281 ++
3 files changed, 290 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/da8xx_gpio.c
diff --git a/arch/arm/include/asm/arch-davinci/gpio.h
b/arch/arm/include/asm/arch-davinci/gpio.h
index 1be2ac2..29dcccf 100644
--- a/arch/arm/include/asm/arch-davinci/gpio.h
+++ b/arch/arm/include/asm/arch-davinci/gpio.h
@@ -63,4 +63,12 @@ struct davinci_gpio_bank {
#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
+#define gpio_status() gpio_info()
+#define GPIO_NAME_SIZE 20
+#define MAX_NUM_GPIOS 144
+#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
+#define GPIO_BIT(gp) ((gp) & 0x1F)
+
+void gpio_info(void);
+
#endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1e3ae11..62ec97d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X)+= pca953x.o
COBJS-$(CONFIG_S5P)+= s5p_gpio.o
COBJS-$(CONFIG_TEGRA2_GPIO)+= tegra2_gpio.o
+COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c
new file mode 100644
index 000..0308223
--- /dev/null
+++ b/drivers/gpio/da8xx_gpio.c
@@ -0,0 +1,281 @@
+/*
+ * GPIO driver for TI DaVinci DA8xx SOCs.
+ *
+ * (C) Copyright 2011 Guralp Systems Ltd.
+ * Laurence Withers
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+static struct gpio_registry {
+ int is_registered;
+ char name[GPIO_NAME_SIZE];
+} gpio_registry[MAX_NUM_GPIOS];
+
+
+#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+
+static const struct pinmux_config gpio_pinmux[] = {
+ { pinmux(1), 8, 7 },/* GP0[0] */
+ { pinmux(1), 8, 6 },
+ { pinmux(1), 8, 5 },
+ { pinmux(1), 8, 4 },
+ { pinmux(1), 8, 3 },
+ { pinmux(1), 8, 2 },
+ { pinmux(1), 8, 1 },
+ { pinmux(1), 8, 0 },
+ { pinmux(0), 8, 7 },
+ { pinmux(0), 8, 6 },
+ { pinmux(0), 8, 5 },
+ { pinmux(0), 8, 4 },
+ { pinmux(0), 8, 3 },
+ { pinmux(0), 8, 2 },
+ { pinmux(0), 8, 1 },
+ { pinmux(0), 8, 0 },
+ { pinmux(4), 8, 7 },/* GP1[0] */
+ { pinmux(4), 8, 6 },
+ { pinmux(4), 8, 5 },
+ { pinmux(4), 8, 4 },
+ { pinmux(4), 8, 3 },
+ { pinmux(4), 8, 2 },
+ { pinmux(4), 4, 1 },
+ { pinmux(4), 4, 0 },
+ { pinmux(3), 4, 0 },
+ { pinmux(2), 4, 6 },
+ { pinmux(2), 4, 5 },
+ { pinmux(2), 4, 4 },
+ { pinmux(2), 4, 3 },
+ { pinmux(2), 4, 2 },
+ { pinmux(2), 4, 1 },
+ { pinmux(2), 8, 0 },
+ { pinmux(6), 8, 7 },/* GP2[0] */
+ { pinmux(6), 8, 6 },
+ { pinmux(6), 8, 5 },
+ { pinmux(6), 8, 4 },
+ { pinmux(6), 8, 3 },
+ { pinmux(6), 8, 2 },
+ { pinmux(6), 8, 1 },
+ { pinmux(6), 8, 0 },
+ { pinmux(5), 8, 7 },
+ { pinmux(5), 8, 6 },
+ { pinmux(5), 8, 5 },
+ { pinmux(5), 8, 4 },
+ { pinmux(5), 8, 3 },
+ { pinmux(5), 8, 2 },
+ { pinmux(5), 8, 1 },
+ { pinmux(5), 8, 0 },
+ { pinmux(8), 8, 7 },/* GP3[0] */
+ { pinmux(8), 8, 6 },
+ { pinmux(8), 8, 5 },
+ { pinmux(8), 8, 4 },
+ { pinmux(8), 8, 3 },
+ { pinmux(8), 8, 2 },
+ { pinmux(8), 8, 1 },
+ { pinmux(8), 8, 0 },
+ { pinmux(7), 8, 7 },
+ { pinmux(7), 8, 6 },
+ { pinmux(7), 8, 5 },
+ { pinmux(7), 8, 4 },
+ { pinmux(7), 8, 3 },
+ { pinmux(7), 8, 2 },
+
[U-Boot] [PATCH v2 0/2] DA8xx: add generic GPIO driver
This adds a generic GPIO driver fulfilling the interface for the
TI DaVinci DA8xx CPU.
Laurence Withers (2):
DaVinci: rename gpio_defs.h to gpio.h
DA8xx: add generic GPIO driver
.../asm/arch-davinci/{gpio_defs.h => gpio.h} |8 +
board/davinci/dm355leopard/dm355leopard.c |2 +-
board/davinci/dm365evm/dm365evm.c |2 +-
drivers/gpio/Makefile |1 +
drivers/gpio/da8xx_gpio.c | 281
drivers/usb/musb/da8xx.h |2 +-
6 files changed, 293 insertions(+), 3 deletions(-)
rename arch/arm/include/asm/arch-davinci/{gpio_defs.h => gpio.h} (90%)
create mode 100644 drivers/gpio/da8xx_gpio.c
--
Laurence Withers, http://www.guralp.com/
Direct tel:+447753988197 or tel:+44408643 Software Engineer
General support queries: CMG-DCM CMG-EAM CMG-NAM
___
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[U-Boot] [PATCH v2 2/2] DA8xx: add generic GPIO driver
Add a generic GPIO driver for the DaVinci DA8xx processors. It is turned
on by defining CONFIG_DA8XX_GPIO and fulfills the generic GPIO interface
specified in . The driver has support for both manipulating
GPIO pins as well as automatically configuring the pin multiplexor
registers to set the pin function to GPIO.
Signed-off-by: Laurence Withers
---
Changes for v2:
- None.
---
arch/arm/include/asm/arch-davinci/gpio.h |8 +
drivers/gpio/Makefile|1 +
drivers/gpio/da8xx_gpio.c| 281 ++
3 files changed, 290 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/da8xx_gpio.c
diff --git a/arch/arm/include/asm/arch-davinci/gpio.h
b/arch/arm/include/asm/arch-davinci/gpio.h
index 1be2ac2..29dcccf 100644
--- a/arch/arm/include/asm/arch-davinci/gpio.h
+++ b/arch/arm/include/asm/arch-davinci/gpio.h
@@ -63,4 +63,12 @@ struct davinci_gpio_bank {
#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
+#define gpio_status() gpio_info()
+#define GPIO_NAME_SIZE 20
+#define MAX_NUM_GPIOS 144
+#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
+#define GPIO_BIT(gp) ((gp) & 0x1F)
+
+void gpio_info(void);
+
#endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1e3ae11..62ec97d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X)+= pca953x.o
COBJS-$(CONFIG_S5P)+= s5p_gpio.o
COBJS-$(CONFIG_TEGRA2_GPIO)+= tegra2_gpio.o
+COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c
new file mode 100644
index 000..0308223
--- /dev/null
+++ b/drivers/gpio/da8xx_gpio.c
@@ -0,0 +1,281 @@
+/*
+ * GPIO driver for TI DaVinci DA8xx SOCs.
+ *
+ * (C) Copyright 2011 Guralp Systems Ltd.
+ * Laurence Withers
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+static struct gpio_registry {
+ int is_registered;
+ char name[GPIO_NAME_SIZE];
+} gpio_registry[MAX_NUM_GPIOS];
+
+
+#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+
+static const struct pinmux_config gpio_pinmux[] = {
+ { pinmux(1), 8, 7 },/* GP0[0] */
+ { pinmux(1), 8, 6 },
+ { pinmux(1), 8, 5 },
+ { pinmux(1), 8, 4 },
+ { pinmux(1), 8, 3 },
+ { pinmux(1), 8, 2 },
+ { pinmux(1), 8, 1 },
+ { pinmux(1), 8, 0 },
+ { pinmux(0), 8, 7 },
+ { pinmux(0), 8, 6 },
+ { pinmux(0), 8, 5 },
+ { pinmux(0), 8, 4 },
+ { pinmux(0), 8, 3 },
+ { pinmux(0), 8, 2 },
+ { pinmux(0), 8, 1 },
+ { pinmux(0), 8, 0 },
+ { pinmux(4), 8, 7 },/* GP1[0] */
+ { pinmux(4), 8, 6 },
+ { pinmux(4), 8, 5 },
+ { pinmux(4), 8, 4 },
+ { pinmux(4), 8, 3 },
+ { pinmux(4), 8, 2 },
+ { pinmux(4), 4, 1 },
+ { pinmux(4), 4, 0 },
+ { pinmux(3), 4, 0 },
+ { pinmux(2), 4, 6 },
+ { pinmux(2), 4, 5 },
+ { pinmux(2), 4, 4 },
+ { pinmux(2), 4, 3 },
+ { pinmux(2), 4, 2 },
+ { pinmux(2), 4, 1 },
+ { pinmux(2), 8, 0 },
+ { pinmux(6), 8, 7 },/* GP2[0] */
+ { pinmux(6), 8, 6 },
+ { pinmux(6), 8, 5 },
+ { pinmux(6), 8, 4 },
+ { pinmux(6), 8, 3 },
+ { pinmux(6), 8, 2 },
+ { pinmux(6), 8, 1 },
+ { pinmux(6), 8, 0 },
+ { pinmux(5), 8, 7 },
+ { pinmux(5), 8, 6 },
+ { pinmux(5), 8, 5 },
+ { pinmux(5), 8, 4 },
+ { pinmux(5), 8, 3 },
+ { pinmux(5), 8, 2 },
+ { pinmux(5), 8, 1 },
+ { pinmux(5), 8, 0 },
+ { pinmux(8), 8, 7 },/* GP3[0] */
+ { pinmux(8), 8, 6 },
+ { pinmux(8), 8, 5 },
+ { pinmux(8), 8, 4 },
+ { pinmux(8), 8, 3 },
+ { pinmux(8), 8, 2 },
+ { pinmux(8), 8, 1 },
+ { pinmux(8), 8, 0 },
+ { pinmux(7), 8, 7 },
+ { pinmux(7), 8, 6 },
+ { pinmux(7), 8, 5 },
+ { pinmux(7), 8, 4 },
+ { pinmux(7), 8, 3 },
+
[U-Boot] [PATCH v2 1/2] DaVinci: rename gpio_defs.h to gpio.h
In preparation for a generic GPIO driver for the DA8xx processors,
rename to and fix up all files
which include it.
Signed-off-by: Laurence Withers
---
Changes for v2:
- Use git format-patch -C to properly denote rename.
---
.../asm/arch-davinci/{gpio_defs.h => gpio.h} |0
board/davinci/dm355leopard/dm355leopard.c |2 +-
board/davinci/dm365evm/dm365evm.c |2 +-
drivers/usb/musb/da8xx.h |2 +-
4 files changed, 3 insertions(+), 3 deletions(-)
rename arch/arm/include/asm/arch-davinci/{gpio_defs.h => gpio.h} (100%)
diff --git a/arch/arm/include/asm/arch-davinci/gpio_defs.h
b/arch/arm/include/asm/arch-davinci/gpio.h
similarity index 100%
rename from arch/arm/include/asm/arch-davinci/gpio_defs.h
rename to arch/arm/include/asm/arch-davinci/gpio.h
diff --git a/board/davinci/dm355leopard/dm355leopard.c
b/board/davinci/dm355leopard/dm355leopard.c
index 0ee0d11..0ad5678 100644
--- a/board/davinci/dm355leopard/dm355leopard.c
+++ b/board/davinci/dm355leopard/dm355leopard.c
@@ -20,7 +20,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/board/davinci/dm365evm/dm365evm.c
b/board/davinci/dm365evm/dm365evm.c
index 5fb7611..ac54106 100644
--- a/board/davinci/dm365evm/dm365evm.c
+++ b/board/davinci/dm365evm/dm365evm.c
@@ -22,7 +22,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#ifdef CONFIG_DAVINCI_MMC
diff --git a/drivers/usb/musb/da8xx.h b/drivers/usb/musb/da8xx.h
index b9660ba..be1cdaf 100644
--- a/drivers/usb/musb/da8xx.h
+++ b/drivers/usb/musb/da8xx.h
@@ -25,7 +25,7 @@
#define __DA8XX_MUSB_H__
#include
-#include
+#include
#include "musb_core.h"
/* Base address of da8xx usb0 wrapper */
--
Laurence Withers, http://www.guralp.com/
Direct tel:+447753988197 or tel:+44408643 Software Engineer
General support queries: CMG-DCM CMG-EAM CMG-NAM
___
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[U-Boot] [PATCH 3/4] DA8xx: switch an enum to defines for consistency
There are two main sets of LPSC constants, depending on the processor
family. The DA8xx constants were given in an enum whereas the non-DA8xx
constants were preprocessor defines. This commit switches the DA8xx
constants to defines for consistency.
Signed-off-by: Laurence Withers
---
arch/arm/include/asm/arch-davinci/hardware.h | 81 +-
1 files changed, 40 insertions(+), 41 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index d5d4211..551b469 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -215,47 +215,46 @@ typedef volatile unsigned int * dv_reg_p;
#else /* CONFIG_SOC_DA8XX */
-enum davinci_lpsc_ids {
- DAVINCI_LPSC_TPCC = 0,
- DAVINCI_LPSC_TPTC0,
- DAVINCI_LPSC_TPTC1,
- DAVINCI_LPSC_AEMIF,
- DAVINCI_LPSC_SPI0,
- DAVINCI_LPSC_MMC_SD,
- DAVINCI_LPSC_AINTC,
- DAVINCI_LPSC_ARM_RAM_ROM,
- DAVINCI_LPSC_SECCTL_KEYMGR,
- DAVINCI_LPSC_UART0,
- DAVINCI_LPSC_SCR0,
- DAVINCI_LPSC_SCR1,
- DAVINCI_LPSC_SCR2,
- DAVINCI_LPSC_DMAX,
- DAVINCI_LPSC_ARM,
- DAVINCI_LPSC_GEM,
- /* for LPSCs in PSC1, offset from 32 for differentiation */
- DAVINCI_LPSC_PSC1_BASE = 32,
- DAVINCI_LPSC_USB11,
- DAVINCI_LPSC_USB20,
- DAVINCI_LPSC_GPIO,
- DAVINCI_LPSC_UHPI,
- DAVINCI_LPSC_EMAC,
- DAVINCI_LPSC_DDR_EMIF,
- DAVINCI_LPSC_McASP0,
- DAVINCI_LPSC_McASP1,
- DAVINCI_LPSC_McASP2,
- DAVINCI_LPSC_SPI1,
- DAVINCI_LPSC_I2C1,
- DAVINCI_LPSC_UART1,
- DAVINCI_LPSC_UART2,
- DAVINCI_LPSC_LCDC,
- DAVINCI_LPSC_ePWM,
- DAVINCI_LPSC_eCAP,
- DAVINCI_LPSC_eQEP,
- DAVINCI_LPSC_SCR_P0,
- DAVINCI_LPSC_SCR_P1,
- DAVINCI_LPSC_CR_P3,
- DAVINCI_LPSC_L3_CBA_RAM
-};
+#define DAVINCI_LPSC_TPCC 0
+#define DAVINCI_LPSC_TPTC0 1
+#define DAVINCI_LPSC_TPTC1 2
+#define DAVINCI_LPSC_AEMIF 3
+#define DAVINCI_LPSC_SPI0 4
+#define DAVINCI_LPSC_MMC_SD5
+#define DAVINCI_LPSC_AINTC 6
+#define DAVINCI_LPSC_ARM_RAM_ROM 7
+#define DAVINCI_LPSC_SECCTL_KEYMGR 8
+#define DAVINCI_LPSC_UART0 9
+#define DAVINCI_LPSC_SCR0 10
+#define DAVINCI_LPSC_SCR1 11
+#define DAVINCI_LPSC_SCR2 12
+#define DAVINCI_LPSC_DMAX 13
+#define DAVINCI_LPSC_ARM 14
+#define DAVINCI_LPSC_GEM 15
+
+/* for LPSCs in PSC1, offset from 32 for differentiation */
+#define DAVINCI_LPSC_PSC1_BASE 32
+#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 1)
+#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 2)
+#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
+#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
+#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
+#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
+#define DAVINCI_LPSC_McASP0(DAVINCI_LPSC_PSC1_BASE + 7)
+#define DAVINCI_LPSC_McASP1(DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_McASP2(DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
+#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
+#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
+#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
+#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 14)
+#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 15)
+#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 16)
+#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 17)
+#define DAVINCI_LPSC_SCR_P0(DAVINCI_LPSC_PSC1_BASE + 18)
+#define DAVINCI_LPSC_SCR_P1(DAVINCI_LPSC_PSC1_BASE + 19)
+#define DAVINCI_LPSC_CR_P3 (DAVINCI_LPSC_PSC1_BASE + 20)
+#define DAVINCI_LPSC_L3_CBA_RAM(DAVINCI_LPSC_PSC1_BASE + 21)
#endif /* CONFIG_SOC_DA8XX */
--
Laurence Withers, http://www.guralp.com/
Direct tel:+447753988197 or tel:+44408643 Software Engineer
General support queries: CMG-DCM CMG-EAM CMG-NAM
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[U-Boot] [PATCH 2/4] DA8xx: add MMC/SD controller addresses
Signed-off-by: Laurence Withers --- arch/arm/include/asm/arch-davinci/hardware.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index df3f549..d5d4211 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -140,6 +140,8 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e2 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 +#define DAVINCI_MMC_SD0_BASE 0x01c4 +#define DAVINCI_MMC_SD1_BASE 0x01e1b000 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x6800 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x4000 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x6000 -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] DaVinci EMAC: declare function for all DA8xx CPUs
The function davinci_emac_mii_mode_sel() is defined in board/davinci/common/misc.c for any DA8xx CPU which has CONFIG_DRIVER_TI_EMAC enabled. However, the prototype was only being declared in for the DA850 EVM board. This patch declares it for all DA8xx CPUs where CONFIG_DRIVER_TI_EMAC is enabled. Signed-off-by: Laurence Withers --- arch/arm/include/asm/arch-davinci/davinci_misc.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h index 347aa89..211b769 100644 --- a/arch/arm/include/asm/arch-davinci/davinci_misc.h +++ b/arch/arm/include/asm/arch-davinci/davinci_misc.h @@ -57,7 +57,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); int davinci_configure_pin_mux_items(const struct pinmux_resource *item, int n_items); -#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM) +#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX) void davinci_emac_mii_mode_sel(int mode_sel); #endif #if defined(CONFIG_SOC_DA8XX) -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] DA8xx: fix LPSC constants
Some of the LPSC constants were incorrect, and some were missing. This commit fixes the incorrect constants (which were not used anywhere in the tree) and adds all constants for both DA830 and DA850, as per the TI datasheets. Signed-off-by: Laurence Withers --- arch/arm/include/asm/arch-davinci/hardware.h | 43 ++--- 1 files changed, 31 insertions(+), 12 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 551b469..f537c4b 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -234,27 +234,46 @@ typedef volatile unsigned int * dv_reg_p; /* for LPSCs in PSC1, offset from 32 for differentiation */ #define DAVINCI_LPSC_PSC1_BASE 32 -#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 1) -#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 2) +#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1) +#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2) #define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3) #define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4) #define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5) #define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6) #define DAVINCI_LPSC_McASP0(DAVINCI_LPSC_PSC1_BASE + 7) -#define DAVINCI_LPSC_McASP1(DAVINCI_LPSC_PSC1_BASE + 8) -#define DAVINCI_LPSC_McASP2(DAVINCI_LPSC_PSC1_BASE + 9) #define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10) #define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11) #define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12) #define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13) -#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 14) -#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 15) -#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 16) -#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 17) -#define DAVINCI_LPSC_SCR_P0(DAVINCI_LPSC_PSC1_BASE + 18) -#define DAVINCI_LPSC_SCR_P1(DAVINCI_LPSC_PSC1_BASE + 19) -#define DAVINCI_LPSC_CR_P3 (DAVINCI_LPSC_PSC1_BASE + 20) -#define DAVINCI_LPSC_L3_CBA_RAM(DAVINCI_LPSC_PSC1_BASE + 21) +#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16) +#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17) +#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20) +#define DAVINCI_LPSC_L3_CBA_RAM(DAVINCI_LPSC_PSC1_BASE + 31) + +/* DA830-specific peripherals */ +#define DAVINCI_LPSC_McASP1(DAVINCI_LPSC_PSC1_BASE + 8) +#define DAVINCI_LPSC_McASP2(DAVINCI_LPSC_PSC1_BASE + 9) +#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21) +#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24) +#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25) +#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26) + +/* DA850-specific peripherals */ +#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0) +#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8) +#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9) +#define DAVINCI_LPSC_McBSP0(DAVINCI_LPSC_PSC1_BASE + 14) +#define DAVINCI_LPSC_McBSP1(DAVINCI_LPSC_PSC1_BASE + 15) +#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18) +#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19) +#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21) +#define DAVINCI_LPSC_SCR_F0(DAVINCI_LPSC_PSC1_BASE + 24) +#define DAVINCI_LPSC_SCR_F1(DAVINCI_LPSC_PSC1_BASE + 25) +#define DAVINCI_LPSC_SCR_F2(DAVINCI_LPSC_PSC1_BASE + 26) +#define DAVINCI_LPSC_SCR_F6(DAVINCI_LPSC_PSC1_BASE + 27) +#define DAVINCI_LPSC_SCR_F7(DAVINCI_LPSC_PSC1_BASE + 28) +#define DAVINCI_LPSC_SCR_F8(DAVINCI_LPSC_PSC1_BASE + 29) +#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30) #endif /* CONFIG_SOC_DA8XX */ -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] DaVinci/DA8xx cleanups
Some general cleanup patches for the DaVinci/DA8xx CPUs made in preparation for porting to a new board based on the DA850. This is an unchanged repost from my original, with DaVinci/DA8xx board maintainers CCed. Laurence Withers (4): DaVinci EMAC: declare function for all DA8xx CPUs DA8xx: add MMC/SD controller addresses DA8xx: switch an enum to defines for consistency DA8xx: fix LPSC constants arch/arm/include/asm/arch-davinci/davinci_misc.h |2 +- arch/arm/include/asm/arch-davinci/hardware.h | 102 +- 2 files changed, 62 insertions(+), 42 deletions(-) -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] DaVinci/DA8xx cleanups
On Sat, Jul 16, 2011 at 11:06:50AM +0200, Albert ARIBAUD wrote: > Maybe as it touches at least indirectly DA8x boards you could CC: the > board maintainers? Hi Albert, Thanks for the pointer, I have reposted with CCs in place. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] DaVinci: rename gpio_defs.h to gpio.h
On Sat, Jul 16, 2011 at 11:11:15AM +0200, Albert ARIBAUD wrote: > This is a rename, so use 'git mv...' and 'git format-patch -C' to let > git and readers know it is. Hi Albert, Thanks for the tip. I reposted a v2 with this. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] DA8xx: fix LPSC constants
On Mon, Jul 18, 2011 at 10:32:07AM +0530, Rajashekhara, Sudhakar wrote: > Why not remove the LPSC constants which are not used. They can be added > as and when required. Hi Sudhakar, This makes sense. I'll leave it a day or two in case there are any other comments, and then post an updated patch set. Many thanks, and bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/12] da850: indicate cache usage disable in config file
On Tue, Aug 02, 2011 at 06:06:42PM +0200, Wolfgang Denk wrote: > Dear nagabhushana.netagu...@ti.com, > > In message <1312299792-16415-2-git-send-email-nagabhushana.netagu...@ti.com> > you wrote: > > From: Nagabhushana Netagunte > > > > As per new cache management framework, if the caches are not used > > in u-boot, it needs to be explicitly indicated through macros in > > config file. da850 doesnt support I-CACHE, D-CACHE or L2-CACHE > > usage in u-boot which is indicated by the following macro definitions, > > What exactly does this mean? Does it mean that > > 1) the hardware does not have working caches, so there is no chance to >ever add such support in software? > > 2) the hardware does have working caches, but this current software >support is simple / incomplete, and cache support will be added >later? I am also working on a U-Boot port to a DA850-based board, and I can confirm that both I-cache and D-cache do work correctly. However, there are cache coherency issues when using the Ethernet driver (DaVinci EMAC). There may also be other drivers that fail similarly. If driver issues are the reason for disabling the caches then the commit message should reflect this. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg
In nand_davinci_readecc(), select the correct NANDFECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.
Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.
Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.
---
drivers/mtd/nand/davinci_nand.c | 26 +-
1 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d41579c..e8506dd 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -176,12 +176,22 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd,
int cmd,
#ifdef CONFIG_SYS_NAND_HW_ECC
+static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
+{
+ u_int32_t ecc = 0;
+
+ ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
+ CONFIG_SYS_NAND_CS - 2]));
+
+ return ecc;
+}
+
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
u_int32_t val;
- (void)__raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ /* reading the ECC result register resets the ECC calculation */
+ nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
@@ -189,22 +199,12 @@ static void nand_davinci_enable_hwecc(struct mtd_info
*mtd, int mode)
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
-{
- u_int32_t ecc = 0;
-
- ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
-
- return ecc;
-}
-
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
u_int32_t tmp;
- const int region = 1;
- tmp = nand_davinci_readecc(mtd, region);
+ tmp = nand_davinci_readecc(mtd);
/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
--
1.7.2.5
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Re: [U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg
On Wed, Sep 28, 2011 at 12:58:45PM +0400, Sergei Shtylyov wrote: >You need to sign off your patch. Add this line to the changelog: > > Signed-off-by: Laurence Withers Thanks, I have reposted v2. Please ignore the posting with the unaltered subject line; I only realised after sending that I had forgotten it. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] NAND: davinci: choose correct 1-bit h/w ECC reg
In nand_davinci_readecc(), select the correct NANDFECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.
Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.
Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.
Signed-off-by: Laurence Withers
---
Changes for v2:
Add Signed-off-by to commit message.
---
drivers/mtd/nand/davinci_nand.c | 26 +-
1 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d41579c..e8506dd 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -176,12 +176,22 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd,
int cmd,
#ifdef CONFIG_SYS_NAND_HW_ECC
+static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
+{
+ u_int32_t ecc = 0;
+
+ ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
+ CONFIG_SYS_NAND_CS - 2]));
+
+ return ecc;
+}
+
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
u_int32_t val;
- (void)__raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ /* reading the ECC result register resets the ECC calculation */
+ nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
@@ -189,22 +199,12 @@ static void nand_davinci_enable_hwecc(struct mtd_info
*mtd, int mode)
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
-{
- u_int32_t ecc = 0;
-
- ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
-
- return ecc;
-}
-
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
u_int32_t tmp;
- const int region = 1;
- tmp = nand_davinci_readecc(mtd, region);
+ tmp = nand_davinci_readecc(mtd);
/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
--
1.7.2.5
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[U-Boot] [PATCH] NAND: davinci: choose correct 1-bit h/w ECC reg
In nand_davinci_readecc(), select the correct NANDFECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.
Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.
Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.
Signed-off-by: Laurence Withers
---
Changes for v2:
Add Signed-off-by to commit message.
---
drivers/mtd/nand/davinci_nand.c | 26 +-
1 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d41579c..e8506dd 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -176,12 +176,22 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd,
int cmd,
#ifdef CONFIG_SYS_NAND_HW_ECC
+static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
+{
+ u_int32_t ecc = 0;
+
+ ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
+ CONFIG_SYS_NAND_CS - 2]));
+
+ return ecc;
+}
+
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
u_int32_t val;
- (void)__raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ /* reading the ECC result register resets the ECC calculation */
+ nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
@@ -189,22 +199,12 @@ static void nand_davinci_enable_hwecc(struct mtd_info
*mtd, int mode)
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
-{
- u_int32_t ecc = 0;
-
- ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
-
- return ecc;
-}
-
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
u_int32_t tmp;
- const int region = 1;
- tmp = nand_davinci_readecc(mtd, region);
+ tmp = nand_davinci_readecc(mtd);
/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
--
1.7.2.5
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Re: [U-Boot] [PATCH] arm, davinci: add missing LSPC define for MMC/SD1
On Wed, Sep 28, 2011 at 07:40:41AM +0200, Heiko Schocher wrote: > diff --git a/arch/arm/include/asm/arch-davinci/hardware.h > b/arch/arm/include/asm/arch-davinci/hardware.h > index 24ae49d..a6cb07c 100644 > --- a/arch/arm/include/asm/arch-davinci/hardware.h > +++ b/arch/arm/include/asm/arch-davinci/hardware.h > @@ -260,6 +260,7 @@ typedef volatile unsigned int * dv_reg_p; > #define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13) > #define DAVINCI_LPSC_LCDC(DAVINCI_LPSC_PSC1_BASE + 16) > #define DAVINCI_LPSC_ePWM(DAVINCI_LPSC_PSC1_BASE + 17) > +#define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18) > #define DAVINCI_LPSC_eCAP(DAVINCI_LPSC_PSC1_BASE + 20) > #define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31) Dear Heiko, DAVINCI_LPSC_MMC_SD1 already exists; look a few lines further down, under /* DA850-specific peripherals */ . This was added in commit 732590b3. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ignore soc asm-offsets.s
On Mon, Sep 12, 2011 at 12:47:24AM -0400, Mike Frysinger wrote: > Recent commit a4814a69d3bca6ee05f4bfc4 cleaned up generation of > asm-offsets.s for SoC dirs, but missed adding it to the ignore > list which makes it show up in `git status`. > > Signed-off-by: Mike Frysinger > --- > .gitignore |1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/.gitignore b/.gitignore > index dbf545f..2a82cd9 100644 > --- a/.gitignore > +++ b/.gitignore > @@ -46,6 +46,7 @@ > > /include/generated/ > /lib/asm-offsets.s > +/arch/*/cpu/asm-offsets.s > > # stgit generated dirs > patches-* Dear Mike, There appear to be some SoCs which have further subdirectories, e.g.: lwithers@rhodium u-boot $ git status # On branch lw-diamond # Untracked files: # (use "git add ..." to include in what will be committed) # # arch/arm/cpu/arm926ejs/davinci/asm-offsets.s nothing added to commit but untracked files present (use "git add" to track) We could ignore all files named asm-offsets.s , or perhaps all files under arch ? Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] davinci: emac: add support for more than 1 PHYs
On Fri, Sep 30, 2011 at 05:27:11PM +0530, nagabhushana.netagu...@ti.com wrote: > add support for more than 1 PHYs. Many of the davinci platforms have more > than 1 PHYs on thier board. This patch extends support in davinci emac > driver for upto 3 PHYs. As a nitpick, there is a typo in "thier", which should be "their". But a real question: where does the number 3 come from? It seems rather arbitrary, at least without any explanatory comments. The MDIO interface can support up to 31 devices, so perhaps you should allow for that many PHYs? (Or perhaps a limit configurable with a #define, as it would seem wasteful to allocate memory for 31 phy_t structures when I doubt there are any boards that could truly take advantage of that). Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] davinci: emac: add new features to autonegotiate for EMAC
On Fri, Sep 30, 2011 at 05:27:09PM +0530, nagabhushana.netagu...@ti.com wrote: > From: Nagabhushana Netagunte > > add more features like DUPLEX, 100MB link speed etc to auto negotiate > in EMAC driver. EMAC controller autonegotiates for these features with > PHYs which are on the board. > > Signed-off-by: Sudhakar Rajashekhara > Signed-off-by: Nagabhushana Netagunte I tried this on a board I am developing with an OMAP-L138. I have a managed switch and tried a few different port settings (auto negotiate enabled and disabled etc.) with no problems at all. If you like, please feel free to add: Tested-by: Laurence Withers Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] da850: revert cache disable patch
On Fri, Sep 30, 2011 at 04:54:25PM +0530, nagabhushana.netagu...@ti.com wrote: > From: Nagabhushana Netagunte > > revert commit bd65d006a6088bcb857e079447d7549e2cd7054d as cache > disabling is no more needed. Subsequent patches to new cache > management framework has fixed EMAC issue with cache coherency. > > Signed-off-by: Nagabhushana Netagunte > --- > include/configs/da850_l138evm.h |3 --- > 1 files changed, 0 insertions(+), 3 deletions(-) > > diff --git a/include/configs/da850_l138evm.h b/include/configs/da850_l138evm.h > index 347893c..0bd630f 100644 > --- a/include/configs/da850_l138evm.h > +++ b/include/configs/da850_l138evm.h > @@ -43,9 +43,6 @@ > #define CONFIG_SYS_HZ1000 > #define CONFIG_SKIP_LOWLEVEL_INIT > #define CONFIG_SYS_TEXT_BASE 0xc108 > -#define CONFIG_SYS_ICACHE_OFF > -#define CONFIG_SYS_DCACHE_OFF > -#define CONFIG_SYS_L2CACHE_OFF > > /* > * Memory Info Am I correct in thinking that what you mean is that caches are now disabled by default, and therefore you don't need to explicitly disable them? I guess so, since I couldn't find any posted patches to fix the EMAC driver (though I would be very glad if I was wrong about this!). If so, we haven't actually "fixed EMAC issue with cache coherency" - the driver is still broken if caches are enabled, and the commit message should reflect that. The same would apply to the dm644X and dm36x cache disable patches. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Tell git to ignore asm-offsets.s
The generated file asm-offsets.s may be found at various depths in the arch subdirectories, so simply ignore it throughout the tree. Signed-off-by: Laurence Withers --- .gitignore |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 2a82cd9..e85d461 100644 --- a/.gitignore +++ b/.gitignore @@ -45,8 +45,7 @@ /reloc_off /include/generated/ -/lib/asm-offsets.s -/arch/*/cpu/asm-offsets.s +asm-offsets.s # stgit generated dirs patches-* -- 1.7.2.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] da830: emac: add support for RMII
On Fri, Sep 30, 2011 at 11:48:13AM -0400, Mike Frysinger wrote:
> On Friday, September 30, 2011 07:57:10 nagabhushana.netagu...@ti.com wrote:
> > --- a/drivers/net/davinci_emac.c
> > +++ b/drivers/net/davinci_emac.c
> > @@ -246,7 +246,7 @@ static int gen_get_link_speed(int phy_addr)
> > if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
> > (tmp & 0x04)) {
> > #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
>
> there's a common CONFIG_RMII symbol already ...
>
> > - defined(CONFIG_MACH_DAVINCI_DA850_EVM)
> > + defined(CONFIG_MACH_DAVINCI_DA8XX_EVM)
>
> maybe it's just me, but board level defines in an emac driver make no sense
This led me to look a bit more closely at this code, and I think there is
something wrong with it. Under Linux, I am able to run in RMII mode at either
10BASE-T or 100BASE-TX, either by forcing it on the board with ethtool or by
forcing it on the managed switch.
However, the driver in U-Boot fails to work with 10BASE-T altogether. A
simple change to #if defined(CONFIG_SOC_DA8XX) doesn't seem to resolve the
situation so it would appear there are some bugs in the TI EMAC driver. I
also note it doesn't reset the PHY properly as if I reboot from Linux with
the PHY forced to 10BASE-T then U-Boot is no longer able to get the link up.
Bye for now,
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Re: [U-Boot] [PATCH] ubifs bad superblock bug
On Tue, Oct 04, 2011 at 06:41:52PM +0900, Kyungmin Park wrote:
> On Tue, Oct 4, 2011 at 6:08 PM, larsi
> wrote:
> > - free(ubifs_sb->s_fs_info);
> > - free(ubifs_sb);
> > + if (ubifs_sb != null) {
Should be NULL.
> > + free(ubifs_sb->s_fs_info);
> > + free(ubifs_sb);
> > + }
> Which statement is problem? Basically free() check the null address.
> so If ubifs_sb->s_fs_info doesn't have value its skipped. and ubifs_sb
> is similar.
The problem is the first call to free() above. If ubifs_sb is null, then
free(ubis_sb->...) will be a null pointer dereference.
Bye for now,
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Re: [U-Boot] [PATCH 02/12] Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
On Wed, Oct 05, 2011 at 11:43:29AM +0200, Stefano Babic wrote: > From: Bastian Ruppert > > Signed-off-by: Bastian Ruppert > Signed-off-by: Stefano Babic > CC: d...@denx.de > CC: Sandeep Paulraj > --- > arch/arm/include/asm/arch-davinci/hardware.h |4 +++ > board/davinci/ea20/ea20.c| 30 > +- > 2 files changed, 33 insertions(+), 1 deletions(-) There are generic GPIO functions (asm/gpio.h) for DaVinci; you should probably use those instead of directly programming the registers. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/13] Davinci: ea20: use gpio framework to access gpios
On Wed, Oct 05, 2011 at 03:08:24PM +0200, Stefano Babic wrote: > Drop direct access to SOC's registers and use > the function of the GPIO driver for da8xx. Dear Stefano, The da8xx GPIO driver also configures the pinmux for you. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 4/6] da850: revert cache disable patch
On Sat, Oct 08, 2011 at 02:58:36PM +0530, manjunath.ha...@ti.com wrote: > revert commit bd65d006a6088bcb857e079447d7549e2cd7054d as the > disabling of cache need not be done explicitly. Subsequent > patches to new cache management framework has fixed it. > EMAC issue with cache coherency still exists when cahces are > enabled. Hi Manjunath, A small thing, but I'd recommend you drop the sentence "Subsequent patches to new cache management framework has fixed it.", as it implies things were broken (true) and are now fixed (still not true). In fact, would it be better to simply drop this patch from the patch series altogether, leaving the caches explicitly disabled, until such a time as the EMAC driver is fixed (I guess we are mainly waiting to see if anyone wants to tackle cache ops for the ARM926EJS) and the code has been verified with caches enabled? Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/6] da850: add board specific functions
On Sat, Oct 08, 2011 at 02:58:32PM +0530, manjunath.ha...@ti.com wrote: > There are two boards AM18xx and L138 both of which are based > on da850 SOC. AM18xx boards have mac address stored in I2C > EEPROM and they have spi flash manufactured by WINBOND. L138 > boards store mac address in SPI flash and they have SPI flash > manufactured by ST Microelectronics.Due to these differences, > instead of one config file, two config files are introduced > to manage configs specific to board types. Hi Manjunath, Does this patchset touch SoC functionality, or just the board configs for the EVMs? If the latter, it might be better to change the patch subject. Otherwise it flags these patches as being relevant to anyone using the DA850 processor, which actually isn't the case from a quick read. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] davinci_emac: fix for running with dcache enabled
On Sun, Oct 09, 2011 at 02:41:47PM +0400, Ilya Yanok wrote:
> arm926ejs doesn't have {invalidate,flush}_dcache_range(), so we have to
> add this not to break the driver on DaVinci boards (maybe we need to add
> empty cache functions on arm926ejs instead?)
Even better would be working cache functions, so that DA8xx boards (and
presumably other DaVinci processors) can run with Ethernet and cache enabled.
There have been a few proposals floating around to do this, but I'm not sure
whether they've stalled or are continuing quietly along.
Bye for now,
--
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Re: [U-Boot] [PATCH v2] NAND: davinci: choose correct 1-bit h/w ECC reg
On Mon, Sep 26, 2011 at 04:02:30PM +, Laurence Withers wrote: > In nand_davinci_readecc(), select the correct NANDFECC register based > on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC. > This allows 1-bit hardware ECC to work with chip select other than CS2. > > Note this now matches the usage in nand_davinci_enable_hwecc(), which > already had the correct handling, and allows refactoring to a single > function encapsulating the register read. > > Without this fix, writing NAND pages to a chip not wired to CS2 would > result in in the ECC calculation always returning FF for each > 512-byte segment, and reading back a correctly written page (one with > ECC intact) would always fail. With this fix, the ECC is written and > verified correctly. > > Signed-off-by: Laurence Withers Does anybody have any comments on this bugfix? If not, can it be accepted? Many thanks, and bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 1/4] gpio: Move common gpio.h to include/asm-generic
On Tue, Oct 11, 2011 at 10:50:12PM -0500, Joe Hershberger wrote: > Common GPIO API used by cmd_gpio should be available to any arch > > Signed-off-by: Joe Hershberger > Cc: Joe Hershberger > Cc: Kim Phillips Tested-by: Laurence Withers Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 2/4] gpio: Modify common gpio.h to more closely match Linux
On Tue, Oct 11, 2011 at 10:50:13PM -0500, Joe Hershberger wrote: > Change "int gp" to "unsigned gpio" > Update the 2 existing arm implementations to match the new API > Remove the gpio_toggle() implementation (never used) > > Signed-off-by: Joe Hershberger > Cc: Joe Hershberger > Cc: Kim Phillips Tested-by: Laurence Withers Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/3] davinci: emac: add support for more than 1 PHYs
On Wed, Oct 12, 2011 at 06:58:00PM +0530, manjunath.ha...@ti.com wrote: > From: Manjunath Hadli > > add support for more than 1 PHYs. Many of the davinci platforms have more > than 1 PHYs on their board. This patch extends support in davinci emac > driver for upto 3 PHYs. > > Signed-off-by: Sudhakar Rajashekhara > Signed-off-by: Manjunath Hadli Dear Manjunath, I do not have multiple PHYs on my board, but I can confirm that this patch (and your following patch 3/3) do not introduce any regressions and correctly detect and operate my board's single PHY. I note this patch uses some constants introduced by your previous patch that Mike Frysinger has NAKed, so I guess it will require some rework once you have addressed his comments. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Syncing custodian tree (the new way) - What am I doing wrong?
On Tue, Oct 25, 2011 at 10:32:21PM +1100, Graeme Russ wrote:
> git checkout master
> git rebase ${upstream}/master
>
> But that is not right - I would normally rebase to uboot
>
> I think there is a missing link here somewhere
${upstream}/master needs to correspond to a remote tracking branch. Do you
have a remote named after ${upstream} ? ("git remote" prints them, "git
remote add " adds them). I think that might be the missing
link.
Quite often you'll have a remote called origin since that is created
automatically and points at the URL you cloned from. I guess a "normal"
workflow would be:
git checkout
git fetch
git rebase /master
Bye for now,
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[U-Boot] [PATCH 1/3] DaVinci DA8xx: tidy up clock ID definition
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.
Signed-off-by: Laurence Withers
Cc: Prabhakar Lad
---
arch/arm/include/asm/arch-davinci/hardware.h | 53 +++---
1 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..dac43bb 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -441,21 +441,46 @@ struct davinci_pllc_regs {
#define davinci_pllc1_regs ((struct davinci_pllc_regs
*)DAVINCI_PLL_CNTRL1_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
-#define ASYNC3 get_async3_src()
-#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
-#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
-/* Clock IDs */
+/*
+ * A clock ID is a 32-bit number where bit 16 represents the PLL controller
+ * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
+ * counting from 1. Clock IDs may be passed to clk_get().
+ */
+
+/* flags to select PLL controller */
+#define DAVINCI_PLLC0_FLAG (0)
+#define DAVINCI_PLLC1_FLAG (1 << 16)
+
enum davinci_clk_ids {
- DAVINCI_SPI0_CLKID = 2,
- DAVINCI_UART2_CLKID = 2,
- DAVINCI_MMC_CLKID = 2,
- DAVINCI_MDIO_CLKID = 4,
- DAVINCI_ARM_CLKID = 6,
- DAVINCI_PLLM_CLKID = 0xff,
- DAVINCI_PLLC_CLKID = 0x100,
- DAVINCI_AUXCLK_CLKID = 0x101
+ /*
+* Clock IDs for PLL outputs. Each may be switched on/off independently,
+* and each may map to one or more peripherals.
+*/
+ DAVINCI_PLL0_SYSCLK2= DAVINCI_PLLC0_FLAG | 2,
+ DAVINCI_PLL0_SYSCLK4= DAVINCI_PLLC0_FLAG | 4,
+ DAVINCI_PLL0_SYSCLK6= DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK2= DAVINCI_PLLC1_FLAG | 2,
+
+ /* map peripherals to clock IDs */
+ DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
+ DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2,
+
+ /* special clock ID - output of PLL multiplier */
+ DAVINCI_PLLM_CLKID = 0x0FF,
+
+ /* special clock ID - output of PLL post divisor */
+ DAVINCI_PLLC_CLKID = 0x100,
+
+ /* special clock ID - PLL bypass */
+ DAVINCI_AUXCLK_CLKID= 0x101,
};
+#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
int clk_get(enum davinci_clk_ids id);
/* Boot config */
@@ -570,10 +595,10 @@ static inline int cpu_is_da850(void)
return ((part_no == 0xb7d1) ? 1 : 0);
}
-static inline int get_async3_src(void)
+static inline enum davinci_clk_ids get_async3_src(void)
{
return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
- PLL1_SYSCLK2 : 2;
+ DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
}
#endif /* CONFIG_SOC_DA8XX */
--
1.7.2.5
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[U-Boot] [PATCH 3/3] DaVinci DA8xx: replace magic number for DDR speed
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers
Cc: Prabhakar Lad
---
arch/arm/cpu/arm926ejs/davinci/cpu.c |3 ++-
arch/arm/include/asm/arch-davinci/hardware.h |2 ++
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 4bdb08b..b31add8 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -122,7 +122,8 @@ int set_cpu_clk_info(void)
{
gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
/* DDR PHY uses an x2 input clock */
- gd->bd->bi_ddr_freq = clk_get(0x10001) / 100;
+ gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
+ (clk_get(DAVINCI_DDR_CLKID) / 100);
gd->bd->bi_dsp_freq = 0;
return 0;
}
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index 0fce940..7f3dcc2 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -459,10 +459,12 @@ enum davinci_clk_ids {
DAVINCI_PLL0_SYSCLK2= DAVINCI_PLLC0_FLAG | 2,
DAVINCI_PLL0_SYSCLK4= DAVINCI_PLLC0_FLAG | 4,
DAVINCI_PLL0_SYSCLK6= DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK1= DAVINCI_PLLC1_FLAG | 1,
DAVINCI_PLL1_SYSCLK2= DAVINCI_PLLC1_FLAG | 2,
/* map peripherals to clock IDs */
DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
--
1.7.2.5
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[U-Boot] [PATCH 2/3] DaVinci DA850: UART2 clock ID comes from ASYNC3
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.
Signed-off-by: Laurence Withers
Cc: Prabhakar Lad
---
arch/arm/include/asm/arch-davinci/hardware.h |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index dac43bb..0fce940 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -466,7 +466,6 @@ enum davinci_clk_ids {
DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
- DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2,
/* special clock ID - output of PLL multiplier */
DAVINCI_PLLM_CLKID = 0x0FF,
@@ -478,6 +477,9 @@ enum davinci_clk_ids {
DAVINCI_AUXCLK_CLKID= 0x101,
};
+#define DAVINCI_UART2_CLKID(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
: get_async3_src())
--
1.7.2.5
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Re: [U-Boot] [PATCH] DaVinci DA8xx: fix set_cpu_clk_info()
On Sat, Jul 28, 2012 at 12:49:55PM +0530, Prabhakar Lad wrote:
> Thanks for the patch. I have tested this patch, below are few comments.
[snip]
> > +int set_cpu_clk_info(void)
> > +{
> > + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
> > + /* DDR PHY uses an x2 input clock */
> > + gd->bd->bi_ddr_freq = clk_get(0x10001) / 100;
>
> Can you define a macro for this 0x10001 ?
>
> With that change you can add my ACK:
> Acked-by: Prabhakar Lad
Hi Prabhakar,
I have tidied up the clock IDs a little and added a constant for the DDR2
clock ID as you suggested. It made sense that this would be a separate set
of patches:
http://lists.denx.de/pipermail/u-boot/2012-July/129444.html
Bye for now,
--
Laurence Withers, http://www.guralp.com/
Direct tel:+447753988197 or tel:+44408643 Software Engineer
General support queries: CMG-DCM CMG-EAM CMG-NAM
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Re: [U-Boot] [PATCH 3/3] DaVinci DA8xx: replace magic number for DDR speed
On Mon, Jul 30, 2012 at 04:30:15PM +, Laurence Withers wrote:
> Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
> definition. In addition, don't request this clock ID on DA830 hardware,
> which does not have a DDR2/mDDR PHY (or associated PLL controller).
>
> Signed-off-by: Laurence Withers
> Cc: Prabhakar Lad
> ---
> arch/arm/cpu/arm926ejs/davinci/cpu.c |3 ++-
> arch/arm/include/asm/arch-davinci/hardware.h |2 ++
> 2 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
> b/arch/arm/cpu/arm926ejs/davinci/cpu.c
> index 4bdb08b..b31add8 100644
> --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
> +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
> @@ -122,7 +122,8 @@ int set_cpu_clk_info(void)
> {
> gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
> /* DDR PHY uses an x2 input clock */
> - gd->bd->bi_ddr_freq = clk_get(0x10001) / 100;
> + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
> + (clk_get(DAVINCI_DDR_CLKID) / 100);
> gd->bd->bi_dsp_freq = 0;
> return 0;
> }
> diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
> b/arch/arm/include/asm/arch-davinci/hardware.h
> index 0fce940..7f3dcc2 100644
> --- a/arch/arm/include/asm/arch-davinci/hardware.h
> +++ b/arch/arm/include/asm/arch-davinci/hardware.h
> @@ -459,10 +459,12 @@ enum davinci_clk_ids {
> DAVINCI_PLL0_SYSCLK2= DAVINCI_PLLC0_FLAG | 2,
> DAVINCI_PLL0_SYSCLK4= DAVINCI_PLLC0_FLAG | 4,
> DAVINCI_PLL0_SYSCLK6= DAVINCI_PLLC0_FLAG | 6,
> + DAVINCI_PLL1_SYSCLK1= DAVINCI_PLLC1_FLAG | 1,
> DAVINCI_PLL1_SYSCLK2= DAVINCI_PLLC1_FLAG | 2,
>
> /* map peripherals to clock IDs */
> DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
> + DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
> DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
> DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
> DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
> --
> 1.7.2.5
>
Hi,
This patch does depend on my earlier patch to tidy up the definition of
set_cpu_clk_info() :
http://lists.denx.de/pipermail/u-boot/2012-July/129205.html
Bye for now,
--
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Direct tel:+447753988197 or tel:+44408643 Software Engineer
General support queries: CMG-DCM CMG-EAM CMG-NAM
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[U-Boot] [PATCH v2 0/4] DaVinci DA8xx: tidy up clock IDs
This small series of patches tidies up the clock IDs that are used to interact with the PLL controllers on the DaVinci DA8xx processors. It more clearly defines the structure and meaning of the IDs and untangles some model-specific code that can't be shared among the family. This tidying allows three bugs to be identified and resolved: - on the DA850, UART2's clock may come from ASYNC3, unlike the DA830; - the DA830 doesn't have a DDR2/mDDR PHY, or a PLL controller for it; - the DSP speed reported by bdinfo was not being initialised on the DA8xx family. Laurence Withers (4): DaVinci DA8xx: tidy up clock ID definition DaVinci DA850: UART2 clock ID comes from ASYNC3 DaVinci DA8xx: replace magic number for DDR speed DaVinci DA8xx: fix set_cpu_clk_info() arch/arm/cpu/arm926ejs/davinci/cpu.c | 22 ++ arch/arm/include/asm/arch-davinci/hardware.h | 57 +++-- 2 files changed, 57 insertions(+), 22 deletions(-) -- 1.7.2.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/4] DaVinci DA850: UART2 clock ID comes from ASYNC3
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.
Signed-off-by: Laurence Withers
Cc: Tom Rini
Cc: Prabhakar Lad
---
Changes in v2:
- Re-ordered patch series to tidy up clock IDs before tidying up users
(set_cpu_clk_info()).
---
arch/arm/include/asm/arch-davinci/hardware.h |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index dac43bb..0fce940 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -466,7 +466,6 @@ enum davinci_clk_ids {
DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
- DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2,
/* special clock ID - output of PLL multiplier */
DAVINCI_PLLM_CLKID = 0x0FF,
@@ -478,6 +477,9 @@ enum davinci_clk_ids {
DAVINCI_AUXCLK_CLKID= 0x101,
};
+#define DAVINCI_UART2_CLKID(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
: get_async3_src())
--
1.7.2.5
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[U-Boot] [PATCH v2 1/4] DaVinci DA8xx: tidy up clock ID definition
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.
Signed-off-by: Laurence Withers
Cc: Tom Rini
Cc: Prabhakar Lad
---
Changes in v2:
- Re-ordered patch series to tidy up clock IDs before tidying up users
(set_cpu_clk_info()).
---
arch/arm/include/asm/arch-davinci/hardware.h | 53 +++---
1 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..dac43bb 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -441,21 +441,46 @@ struct davinci_pllc_regs {
#define davinci_pllc1_regs ((struct davinci_pllc_regs
*)DAVINCI_PLL_CNTRL1_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
-#define ASYNC3 get_async3_src()
-#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
-#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
-/* Clock IDs */
+/*
+ * A clock ID is a 32-bit number where bit 16 represents the PLL controller
+ * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
+ * counting from 1. Clock IDs may be passed to clk_get().
+ */
+
+/* flags to select PLL controller */
+#define DAVINCI_PLLC0_FLAG (0)
+#define DAVINCI_PLLC1_FLAG (1 << 16)
+
enum davinci_clk_ids {
- DAVINCI_SPI0_CLKID = 2,
- DAVINCI_UART2_CLKID = 2,
- DAVINCI_MMC_CLKID = 2,
- DAVINCI_MDIO_CLKID = 4,
- DAVINCI_ARM_CLKID = 6,
- DAVINCI_PLLM_CLKID = 0xff,
- DAVINCI_PLLC_CLKID = 0x100,
- DAVINCI_AUXCLK_CLKID = 0x101
+ /*
+* Clock IDs for PLL outputs. Each may be switched on/off independently,
+* and each may map to one or more peripherals.
+*/
+ DAVINCI_PLL0_SYSCLK2= DAVINCI_PLLC0_FLAG | 2,
+ DAVINCI_PLL0_SYSCLK4= DAVINCI_PLLC0_FLAG | 4,
+ DAVINCI_PLL0_SYSCLK6= DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK2= DAVINCI_PLLC1_FLAG | 2,
+
+ /* map peripherals to clock IDs */
+ DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
+ DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2,
+
+ /* special clock ID - output of PLL multiplier */
+ DAVINCI_PLLM_CLKID = 0x0FF,
+
+ /* special clock ID - output of PLL post divisor */
+ DAVINCI_PLLC_CLKID = 0x100,
+
+ /* special clock ID - PLL bypass */
+ DAVINCI_AUXCLK_CLKID= 0x101,
};
+#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
int clk_get(enum davinci_clk_ids id);
/* Boot config */
@@ -570,10 +595,10 @@ static inline int cpu_is_da850(void)
return ((part_no == 0xb7d1) ? 1 : 0);
}
-static inline int get_async3_src(void)
+static inline enum davinci_clk_ids get_async3_src(void)
{
return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
- PLL1_SYSCLK2 : 2;
+ DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
}
#endif /* CONFIG_SOC_DA8XX */
--
1.7.2.5
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[U-Boot] [PATCH v2 3/4] DaVinci DA8xx: replace magic number for DDR speed
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers
Cc: Tom Rini
Cc: Prabhakar Lad
---
Changes in v2:
- Re-ordered patch series to tidy up clock IDs before tidying up users
(set_cpu_clk_info()).
---
arch/arm/cpu/arm926ejs/davinci/cpu.c |3 ++-
arch/arm/include/asm/arch-davinci/hardware.h |2 ++
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 6cb857a..41201d0 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -194,7 +194,8 @@ int set_cpu_clk_info(void)
#ifdef CONFIG_SOC_DA8XX
gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
/* DDR PHY uses an x2 input clock */
- gd->bd->bi_ddr_freq = clk_get(0x10001) / 100;
+ gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
+ (clk_get(DAVINCI_DDR_CLKID) / 100);
#else
unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index 0fce940..7f3dcc2 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -459,10 +459,12 @@ enum davinci_clk_ids {
DAVINCI_PLL0_SYSCLK2= DAVINCI_PLLC0_FLAG | 2,
DAVINCI_PLL0_SYSCLK4= DAVINCI_PLLC0_FLAG | 4,
DAVINCI_PLL0_SYSCLK6= DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK1= DAVINCI_PLLC1_FLAG | 1,
DAVINCI_PLL1_SYSCLK2= DAVINCI_PLLC1_FLAG | 2,
/* map peripherals to clock IDs */
DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
--
1.7.2.5
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[U-Boot] [PATCH v2 4/4] DaVinci DA8xx: fix set_cpu_clk_info()
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
initialising the DSP frequency, leading to 'bdinfo' command output such as:
[...snip...]
ARM frequency = 300 MHz
DSP frequency = -536870913 MHz
DDR frequency = 300 MHz
This commit provides a separate implementation of set_cpu_clk_info() for
the DA8xx SoCs that initialises the DSP frequency to zero (since
currently the DSP is not enabled by U-Boot on any DA8xx platform). The
separate implementation is justified because there is no common code
between DA8xx and the other SoC families. It is now much easier to
understand the flow of the two separate functions.
Signed-off-by: Laurence Withers
Cc: Tom Rini
Cc: Hadli, Manjunath
Cc: Heiko Schocher
---
Changes in v2:
- Re-ordered patch series to tidy up clock IDs before tidying up users
(set_cpu_clk_info()).
---
arch/arm/cpu/arm926ejs/davinci/cpu.c | 23 ++-
1 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 41201d0..b31add8 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -117,6 +117,17 @@ int clk_get(enum davinci_clk_ids id)
out:
return pll_out;
}
+
+int set_cpu_clk_info(void)
+{
+ gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
+ /* DDR PHY uses an x2 input clock */
+ gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
+ (clk_get(DAVINCI_DDR_CLKID) / 100);
+ gd->bd->bi_dsp_freq = 0;
+ return 0;
+}
+
#else /* CONFIG_SOC_DA8XX */
static unsigned pll_div(volatile void *pllbase, unsigned offset)
@@ -187,17 +198,9 @@ unsigned int davinci_clk_get(unsigned int div)
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 100;
}
#endif
-#endif /* !CONFIG_SOC_DA8XX */
int set_cpu_clk_info(void)
{
-#ifdef CONFIG_SOC_DA8XX
- gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
- /* DDR PHY uses an x2 input clock */
- gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
- (clk_get(DAVINCI_DDR_CLKID) / 100);
-#else
-
unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
#if defined(CONFIG_SOC_DM365)
pllbase = DAVINCI_PLL_CNTRL1_BASE;
@@ -216,10 +219,12 @@ int set_cpu_clk_info(void)
pllbase = DAVINCI_PLL_CNTRL0_BASE;
#endif
gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
-#endif
+
return 0;
}
+#endif /* !CONFIG_SOC_DA8XX */
+
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
--
1.7.2.5
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[U-Boot] [PATCH] DA8xx: fix LPSC numbering
Hi, I'm in the process of porting u-boot to a new board we have developed using the OMAP-L138 (or DA850). While I'm a long way from finishing the port, I have noticed that the definitions of some of the local power and sleep controller (LPSC) register module numbers are incorrect. As a reply to this mail I've attached my first attempt at a patch for u-boot, which addresses this issue. Any feedback (esp. wrt formatting and use of the git tools etc.) is gratefully received. Laurence Withers (1): DA8xx: fix LPSC numbering arch/arm/include/asm/arch-davinci/hardware.h | 29 +- 1 files changed, 19 insertions(+), 10 deletions(-) -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] DA8xx: fix LPSC numbering
The DA8xx chips have two modules PSC0 and PSC1 for the local power and sleep
controllers (LPSC). Each LPSC has up to 32 submodules over which it has control,
which are enumerated by the DAVINCI_LPSC_* symbols.
This commit fixes the definitions of a number of symbols to be consistent with
both the OMAP-L137 and OMAP-L138 data sheets (TI documents SPRS563D and SPRS586A
respectively): some minor renaming to reflect actual functionality and some
reordering of modules in PSC1 to be correct.
None of the affected symbols were actually used anywhere in the code, so there
are no related code changes.
---
arch/arm/include/asm/arch-davinci/hardware.h | 29 +-
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index df3f549..d0a3036 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -214,12 +214,12 @@ typedef volatile unsigned int * dv_reg_p;
#else /* CONFIG_SOC_DA8XX */
enum davinci_lpsc_ids {
- DAVINCI_LPSC_TPCC = 0,
+ DAVINCI_LPSC_TPCC0 = 0,
DAVINCI_LPSC_TPTC0,
DAVINCI_LPSC_TPTC1,
DAVINCI_LPSC_AEMIF,
DAVINCI_LPSC_SPI0,
- DAVINCI_LPSC_MMC_SD,
+ DAVINCI_LPSC_MMC_SD0,
DAVINCI_LPSC_AINTC,
DAVINCI_LPSC_ARM_RAM_ROM,
DAVINCI_LPSC_SECCTL_KEYMGR,
@@ -227,31 +227,40 @@ enum davinci_lpsc_ids {
DAVINCI_LPSC_SCR0,
DAVINCI_LPSC_SCR1,
DAVINCI_LPSC_SCR2,
- DAVINCI_LPSC_DMAX,
+ DAVINCI_LPSC_PRUSS,
DAVINCI_LPSC_ARM,
DAVINCI_LPSC_GEM,
/* for LPSCs in PSC1, offset from 32 for differentiation */
DAVINCI_LPSC_PSC1_BASE = 32,
- DAVINCI_LPSC_USB11,
+ DAVINCI_LPSC_TPCC1 = 32,
DAVINCI_LPSC_USB20,
+ DAVINCI_LPSC_USB11,
DAVINCI_LPSC_GPIO,
DAVINCI_LPSC_UHPI,
DAVINCI_LPSC_EMAC,
DAVINCI_LPSC_DDR_EMIF,
DAVINCI_LPSC_McASP0,
- DAVINCI_LPSC_McASP1,
- DAVINCI_LPSC_McASP2,
+ DAVINCI_LPSC_McASP1_SATA,
+ DAVINCI_LPSC_McASP2_VPIF,
DAVINCI_LPSC_SPI1,
DAVINCI_LPSC_I2C1,
DAVINCI_LPSC_UART1,
DAVINCI_LPSC_UART2,
+ DAVINCI_LPSC_McBSP0,
+ DAVINCI_LPSC_McBSP1,
DAVINCI_LPSC_LCDC,
DAVINCI_LPSC_ePWM,
+ DAVINCI_LPSC_MMC_SD1,
+ DAVINCI_LPSC_uPP,
DAVINCI_LPSC_eCAP,
- DAVINCI_LPSC_eQEP,
- DAVINCI_LPSC_SCR_P0,
- DAVINCI_LPSC_SCR_P1,
- DAVINCI_LPSC_CR_P3,
+ DAVINCI_LPSC_eQEP_TPTC2,
+ DAVINCI_LPSC_SCR_F0 = 56,
+ DAVINCI_LPSC_SCR_F1,
+ DAVINCI_LPSC_SCR_F2,
+ DAVINCI_LPSC_SCR_F6,
+ DAVINCI_LPSC_SCR_F7,
+ DAVINCI_LPSC_SCR_F8,
+ DAVINCI_LPSC_BR_F7,
DAVINCI_LPSC_L3_CBA_RAM
};
--
1.7.2.5
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[U-Boot] [PATCH v2] DA8xx: fix LPSC numbering
The DA8xx chips have two modules PSC0 and PSC1 for the local power and
sleep controllers (LPSC). Each LPSC has up to 32 submodules over which
it has control, which are enumerated by the DAVINCI_LPSC_* symbols.
This commit fixes the definitions of a number of symbols to be
consistent with both the OMAP-L137 and OMAP-L138 data sheets (TI
documents SPRS563D and SPRS586A respectively): some minor renaming to
reflect actual functionality and some reordering of modules in PSC1 to
be correct.
None of the affected symbols were actually used anywhere in the code,
so there are no related code changes.
Signed-off-by: Laurence Withers
Cc: Sandeep Paulraj
---
Changes for v2:
- Fixed formatting of commit message.
---
arch/arm/include/asm/arch-davinci/hardware.h | 29 +-
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index df3f549..d0a3036 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -214,12 +214,12 @@ typedef volatile unsigned int * dv_reg_p;
#else /* CONFIG_SOC_DA8XX */
enum davinci_lpsc_ids {
- DAVINCI_LPSC_TPCC = 0,
+ DAVINCI_LPSC_TPCC0 = 0,
DAVINCI_LPSC_TPTC0,
DAVINCI_LPSC_TPTC1,
DAVINCI_LPSC_AEMIF,
DAVINCI_LPSC_SPI0,
- DAVINCI_LPSC_MMC_SD,
+ DAVINCI_LPSC_MMC_SD0,
DAVINCI_LPSC_AINTC,
DAVINCI_LPSC_ARM_RAM_ROM,
DAVINCI_LPSC_SECCTL_KEYMGR,
@@ -227,31 +227,40 @@ enum davinci_lpsc_ids {
DAVINCI_LPSC_SCR0,
DAVINCI_LPSC_SCR1,
DAVINCI_LPSC_SCR2,
- DAVINCI_LPSC_DMAX,
+ DAVINCI_LPSC_PRUSS,
DAVINCI_LPSC_ARM,
DAVINCI_LPSC_GEM,
/* for LPSCs in PSC1, offset from 32 for differentiation */
DAVINCI_LPSC_PSC1_BASE = 32,
- DAVINCI_LPSC_USB11,
+ DAVINCI_LPSC_TPCC1 = 32,
DAVINCI_LPSC_USB20,
+ DAVINCI_LPSC_USB11,
DAVINCI_LPSC_GPIO,
DAVINCI_LPSC_UHPI,
DAVINCI_LPSC_EMAC,
DAVINCI_LPSC_DDR_EMIF,
DAVINCI_LPSC_McASP0,
- DAVINCI_LPSC_McASP1,
- DAVINCI_LPSC_McASP2,
+ DAVINCI_LPSC_McASP1_SATA,
+ DAVINCI_LPSC_McASP2_VPIF,
DAVINCI_LPSC_SPI1,
DAVINCI_LPSC_I2C1,
DAVINCI_LPSC_UART1,
DAVINCI_LPSC_UART2,
+ DAVINCI_LPSC_McBSP0,
+ DAVINCI_LPSC_McBSP1,
DAVINCI_LPSC_LCDC,
DAVINCI_LPSC_ePWM,
+ DAVINCI_LPSC_MMC_SD1,
+ DAVINCI_LPSC_uPP,
DAVINCI_LPSC_eCAP,
- DAVINCI_LPSC_eQEP,
- DAVINCI_LPSC_SCR_P0,
- DAVINCI_LPSC_SCR_P1,
- DAVINCI_LPSC_CR_P3,
+ DAVINCI_LPSC_eQEP_TPTC2,
+ DAVINCI_LPSC_SCR_F0 = 56,
+ DAVINCI_LPSC_SCR_F1,
+ DAVINCI_LPSC_SCR_F2,
+ DAVINCI_LPSC_SCR_F6,
+ DAVINCI_LPSC_SCR_F7,
+ DAVINCI_LPSC_SCR_F8,
+ DAVINCI_LPSC_BR_F7,
DAVINCI_LPSC_L3_CBA_RAM
};
--
1.7.2.5
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Re: [U-Boot] [PATCH] DA8xx: fix LPSC numbering
On Mon, Mar 21, 2011 at 07:43:51PM +0100, Wolfgang Denk wrote: > SoB missing. > > Lines in commit message too long. Thanks; I have fixed and will resend. > Please fix also all other places where these identifiers are used in > the code. The identifiers changed in the patch were not used anywhere in the code. I also verified that a "./MAKEALL -s davinci" gave the same results before and after. Many thanks for the feedback, and bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] DA8xx: fix LPSC numbering
On Mon, Mar 21, 2011 at 10:14:18PM +0100, Wolfgang Denk wrote:
> -> grep -R DAVINCI_LPSC_TPCC *
> arch/arm/include/asm/arch-davinci/hardware.h:#define DAVINCI_LPSC_TPCC
> 2
> arch/arm/include/asm/arch-davinci/hardware.h: DAVINCI_LPSC_TPCC = 0,
> board/davinci/dm355evm/dm355evm.c: lpsc_on(DAVINCI_LPSC_TPCC);
>
> you change:
>
> - DAVINCI_LPSC_MMC_SD,
> + DAVINCI_LPSC_MMC_SD0,
>
> I see:
>
> -> grep -R DAVINCI_LPSC_MMC_SD *
> arch/arm/cpu/arm926ejs/davinci/psc.c: case DAVINCI_LPSC_MMC_SD:
> arch/arm/include/asm/arch-davinci/hardware.h:#define DAVINCI_LPSC_MMC_SD
> 15
> arch/arm/include/asm/arch-davinci/hardware.h: DAVINCI_LPSC_MMC_SD,
>
>
> Seems your change would break a few boards...
There are several chips in the Davinci family; my commit changes the LPSC
definitions for the DA8xx (the DA830/DA850) processors only, leaving the
other processors alone (they are quite different).
Looking at the hardware.h file that I changed, just above the enum { } block
where my changes reside are a set of #defines for the same symbols. The
#defines are used when CONFIG_SOC_DA8XX is not defined; the enum is used when
it is.
The existing uses in the code are special cases for the non-DA8xx processors;
DAVINCI_LPSC_TPCC is used in the DM355 EVM kit board code, and while
DAVINCI_LPSC_MMC_SD is used in the processor generic C code it is wrapped in
a #ifdef CONFIG_SOC_DM644X (another chip) with a comment about special
treatment.
So, I can change the non-DA8xx names to match. But that changes existing,
working code and the names would no longer match the datasheets.
Or, I can leave the old names be, and then have the new names with suffices,
e.g.:
DAVINCI_LPSC_MMC_SD,/* actually MMC_SD0 on DA8xx */
DAVINCI_LPSC_MMC_SD1,
It seems a little inconsistent to me, but I'm happy to do it if preferred.
Or, I can do what I have done, and change only the DA8xx names.
Which is the preferred option? Or something else entirely?
Many thanks, and bye for now,
--
Laurence Withers, http://www.guralp.com/
Direct tel:+447753988197 or tel:+44408643 Software Engineer
General support queries: CMG-DCM CMG-EAM CMG-NAM
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Re: [U-Boot] [PATCH] DA8xx: fix LPSC numbering
On Mon, Mar 21, 2011 at 10:44:11PM +0100, Wolfgang Denk wrote: > We should agree on a common way to implement this - either #define > _or_ enum, but not a mix of both. > > Having a closer look, it turns out that all these "indices" are > actually register names, and functions like lpsc_on() use horrible > code like this: > > mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); > > to perform address magic, even worse, perform device I/O without using > any I/O acessors (as in dsp_on()). So, as a rough way forward, does the following sound sane? - drop REG_P() and REG() macros, use readl()/writel()/etc. instead. - drop address magic, use structures/arrays instead. - choose either enum or #define (I'd say enum as it's mostly a set of incrementing integers, but it depends on what the result looks like). - try to unify the various Davinci LPSC modules as much as possible. I'm willing to give this a go, but I am unable to physically test the results on any of the Davinci family except the DA850. Bye for now, -- Laurence Withers, http://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
