[PATCH v2] ARM: am335x: Add phyBOARD REGOR support

2020-10-23 Thread Parthiban Nallathambi 
phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060).

CPU  : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-REGOR
DRAM:  512 MiB
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0
eth0: ethernet@4a10

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART
 - USB (host)

Device trees were taken from Linux mainline:
commit c4d6fe731176 ("Linux 5.9.0")

Signed-off-by: Parthiban Nallathambi 
---

Notes:
Changelog in v2:
- include regor files in MAINTAINERS

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/am335x-regor-rdk-u-boot.dtsi  |  31 
 arch/arm/dts/am335x-regor-rdk.dts  |  24 +++
 arch/arm/dts/am335x-regor.dtsi | 202 +
 board/phytec/phycore_am335x_r2/MAINTAINERS |   6 +-
 configs/phycore-am335x-r2-regor_defconfig  |  88 +
 6 files changed, 352 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
 create mode 100644 arch/arm/dts/am335x-regor-rdk.dts
 create mode 100644 arch/arm/dts/am335x-regor.dtsi
 create mode 100644 configs/phycore-am335x-r2-regor_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b195723f16..4f67108e7f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -347,7 +347,8 @@ dtb-$(CONFIG_AM33XX) += \
am335x-sl50.dtb \
am335x-base0033.dtb \
am335x-guardian.dtb \
-   am335x-wega-rdk.dtb
+   am335x-wega-rdk.dtb \
+   am335x-regor-rdk.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb\
am43x-epos-evm.dtb \
am437x-idk-evm.dtb \
diff --git a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi 
b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
new file mode 100644
index 00..1ddd715875
--- /dev/null
+++ b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ */
+
+/ {
+   chosen {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   bootargs = "console=ttyO0,115200 earlyprintk";
+   stdout-path = &uart0;
+   };
+
+   ocp {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+&i2c0 {
+   u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+   u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+   u-boot,dm-pre-reloc;
+   cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/am335x-regor-rdk.dts 
b/arch/arm/dts/am335x-regor-rdk.dts
new file mode 100644
index 00..66a1360b83
--- /dev/null
+++ b/arch/arm/dts/am335x-regor-rdk.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet 
+ *
+ */
+
+/dts-v1/;
+
+#include "am335x-phycore-som.dtsi"
+#include "am335x-regor.dtsi"
+
+/* SoM */
+&gpmc {
+   status = "okay";
+};
+
+&i2c_eeprom {
+   status = "okay";
+};
+
+&serial_flash {
+   status = "okay";
+};
diff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi
new file mode 100644
index 00..86b3f07429
--- /dev/null
+++ b/arch/arm/dts/am335x-regor.dtsi
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet 
+ *
+ */
+
+/ {
+   model = "Phytec AM335x phyBOARD-REGOR";
+   compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", 
"ti,am33xx";
+
+   vcc3v3: fixedregulator@1 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   };
+
+   /* User IO */
+   user_leds: user_leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&user_leds_pins>;
+
+   run_stop-led {
+   gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "gpio";
+   default-state = "off";
+   };
+
+   error-led {
+   gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "gpio";
+   default-state = "off";
+   };
+   };
+};
+
+/* User Leds */
+&am33xx_pinmux {
+   user_leds_pins: pinmux_user_leds {
+   pinctrl-single,pins = <
+   AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
/* lcd_hsync.gpio2_22 */
+   AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
/* mcasp0_fsx.gpio3_15 */
+   >;
+   };
+};
+
+/* CAN Busses */
+&am33xx_

[PATCH] ARM: am335x: Add phyBOARD REGOR support

2020-10-22 Thread Parthiban Nallathambi 
phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060).

CPU  : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-REGOR
DRAM:  512 MiB
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0
eth0: ethernet@4a10

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART
 - USB (host)

Device trees were taken from Linux mainline:
commit c4d6fe731176 ("Linux 5.9.0")

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/dts/Makefile |   3 +-
 arch/arm/dts/am335x-regor-rdk-u-boot.dtsi |  31 +
 arch/arm/dts/am335x-regor-rdk.dts |  24 
 arch/arm/dts/am335x-regor.dtsi| 202 ++
 configs/phycore-am335x-r2-regor_defconfig |  88 +
 5 files changed, 347 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
 create mode 100644 arch/arm/dts/am335x-regor-rdk.dts
 create mode 100644 arch/arm/dts/am335x-regor.dtsi
 create mode 100644 configs/phycore-am335x-r2-regor_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b195723f16..4f67108e7f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -347,7 +347,8 @@ dtb-$(CONFIG_AM33XX) += \
am335x-sl50.dtb \
am335x-base0033.dtb \
am335x-guardian.dtb \
-   am335x-wega-rdk.dtb
+   am335x-wega-rdk.dtb \
+   am335x-regor-rdk.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb\
am43x-epos-evm.dtb \
am437x-idk-evm.dtb \
diff --git a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi 
b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
new file mode 100644
index 00..1ddd715875
--- /dev/null
+++ b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ */
+
+/ {
+   chosen {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   bootargs = "console=ttyO0,115200 earlyprintk";
+   stdout-path = &uart0;
+   };
+
+   ocp {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+&i2c0 {
+   u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+   u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+   u-boot,dm-pre-reloc;
+   cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/am335x-regor-rdk.dts 
b/arch/arm/dts/am335x-regor-rdk.dts
new file mode 100644
index 00..66a1360b83
--- /dev/null
+++ b/arch/arm/dts/am335x-regor-rdk.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet 
+ *
+ */
+
+/dts-v1/;
+
+#include "am335x-phycore-som.dtsi"
+#include "am335x-regor.dtsi"
+
+/* SoM */
+&gpmc {
+   status = "okay";
+};
+
+&i2c_eeprom {
+   status = "okay";
+};
+
+&serial_flash {
+   status = "okay";
+};
diff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi
new file mode 100644
index 00..86b3f07429
--- /dev/null
+++ b/arch/arm/dts/am335x-regor.dtsi
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet 
+ *
+ */
+
+/ {
+   model = "Phytec AM335x phyBOARD-REGOR";
+   compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", 
"ti,am33xx";
+
+   vcc3v3: fixedregulator@1 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   };
+
+   /* User IO */
+   user_leds: user_leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&user_leds_pins>;
+
+   run_stop-led {
+   gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "gpio";
+   default-state = "off";
+   };
+
+   error-led {
+   gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "gpio";
+   default-state = "off";
+   };
+   };
+};
+
+/* User Leds */
+&am33xx_pinmux {
+   user_leds_pins: pinmux_user_leds {
+   pinctrl-single,pins = <
+   AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
/* lcd_hsync.gpio2_22 */
+   AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
/* mcasp0_fsx.gpio3_15 */
+   >;
+   };
+};
+
+/* CAN Busses */
+&am33xx_pinmux {
+   dcan1_pins: pinmux_dcan1 {
+   pinctrl-single,pins = <
+   AM33XX_IOPAD(0x968, PIN_OUTPUT_

[PATCH v2] imx: Add MYiR Tech MYS-6ULX support

2020-07-27 Thread Parthiban Nallathambi 
MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based
on imx6ULL SoC from NXP and provision for expansion board. This
commit adds support only for SBC with NAND.

CPU:   Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 45C
Reset cause: WDOG
Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND
Board: MYiR MYS-6ULX 6ULL Single Board Computer
DRAM:  256 MiB
NAND:  256 MiB
MMC:   FSL_SDHC: 0
In:serial@202
Out:   serial@202
Err:   serial@202
Net:   FEC0

Working:
 - Eth0
 - MMC/SD
 - NAND
 - UART 1
 - USB host

Signed-off-by: Parthiban Nallathambi 
---

Notes:
Changelog v2:
- remove iomux for FEC in favout of dts
- move SYS_MEMSET_* to defconfig
- sync devicetree with Linux Kernel accepted version
- rebased to master

 arch/arm/Kconfig|   1 +
 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts |  19 ++
 arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi | 238 
 arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi   |  24 ++
 arch/arm/mach-imx/mx6/Kconfig   |  12 +
 board/myir/mys_6ulx/Kconfig |  12 +
 board/myir/mys_6ulx/MAINTAINERS |   9 +
 board/myir/mys_6ulx/Makefile|   4 +
 board/myir/mys_6ulx/README  |  52 +
 board/myir/mys_6ulx/mys_6ulx.c  | 117 ++
 board/myir/mys_6ulx/spl.c   | 206 +
 configs/myir_mys_6ulx_defconfig |  69 ++
 include/configs/mys_6ulx.h  |  76 +++
 14 files changed, 840 insertions(+)
 create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts
 create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi
 create mode 100644 arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi
 create mode 100644 board/myir/mys_6ulx/Kconfig
 create mode 100644 board/myir/mys_6ulx/MAINTAINERS
 create mode 100644 board/myir/mys_6ulx/Makefile
 create mode 100644 board/myir/mys_6ulx/README
 create mode 100644 board/myir/mys_6ulx/mys_6ulx.c
 create mode 100644 board/myir/mys_6ulx/spl.c
 create mode 100644 configs/myir_mys_6ulx_defconfig
 create mode 100644 include/configs/mys_6ulx.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e16fe03887..cd5fb0d353 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1925,6 +1925,7 @@ source "board/hisilicon/hikey/Kconfig"
 source "board/hisilicon/hikey960/Kconfig"
 source "board/hisilicon/poplar/Kconfig"
 source "board/isee/igep003x/Kconfig"
+source "board/myir/mys_6ulx/Kconfig"
 source "board/spear/spear300/Kconfig"
 source "board/spear/spear310/Kconfig"
 source "board/spear/spear320/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5726156a2d..93a848eac5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -718,6 +718,7 @@ dtb-$(CONFIG_MX6UL) += \
 dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+   imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
imx6ull-somlabs-visionsom.dtb \
diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts 
b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts
new file mode 100644
index 00..2fd69da028
--- /dev/null
+++ b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ * Author: Parthiban Nallathambi 
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-myir-mys-6ulx.dtsi"
+#include "imx6ull-mys-6ulx-u-boot.dtsi"
+
+/ {
+   model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
+   compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull";
+};
+
+&gpmi {
+   status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi 
b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi
new file mode 100644
index 00..d03694feaf
--- /dev/null
+++ b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ * Author: Parthiban Nallathambi 
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "MYiR MYS-6ULX Single Board Computer";
+   compatible = "fsl,imx6ull";
+
+   chosen {
+   stdout-path = &uart1;
+   };
+
+   reg_vdd_5v: regulator-vdd-5v {
+   compatible = "regulator-fixed";
+   regulator-name = "VDD_5V";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_vdd_3v3: regulator-vdd-3v3 {
+   compatible = "regulator-fixed"

[PATCH] imx: Add MYiR Tech MYS-6ULX support

2020-07-05 Thread Parthiban Nallathambi 
MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based
on imx6ULL SoC from NXP and provision for expansion board. This
commit adds support only for SBC with NAND.

CPU:   Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 45C
Reset cause: WDOG
Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND
Board: MYiR MYS-6ULX 6ULL Single Board Computer
DRAM:  256 MiB
NAND:  256 MiB
MMC:   FSL_SDHC: 0
In:serial@202
Out:   serial@202
Err:   serial@202
Net:   FEC0

Working:
 - Eth0
 - MMC/SD
 - NAND
 - UART 1
 - USB host

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/Kconfig|   1 +
 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts |  20 ++
 arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi | 238 
 arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi   |  24 ++
 arch/arm/mach-imx/mx6/Kconfig   |  12 +
 board/myir/mys_6ulx/Kconfig |  12 +
 board/myir/mys_6ulx/MAINTAINERS |   9 +
 board/myir/mys_6ulx/Makefile|   4 +
 board/myir/mys_6ulx/README  |  52 +
 board/myir/mys_6ulx/mys_6ulx.c  | 146 
 board/myir/mys_6ulx/spl.c   | 206 +
 configs/myir_mys_6ulx_defconfig |  66 ++
 include/configs/mys_6ulx.h  |  80 +++
 14 files changed, 871 insertions(+)
 create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts
 create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi
 create mode 100644 arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi
 create mode 100644 board/myir/mys_6ulx/Kconfig
 create mode 100644 board/myir/mys_6ulx/MAINTAINERS
 create mode 100644 board/myir/mys_6ulx/Makefile
 create mode 100644 board/myir/mys_6ulx/README
 create mode 100644 board/myir/mys_6ulx/mys_6ulx.c
 create mode 100644 board/myir/mys_6ulx/spl.c
 create mode 100644 configs/myir_mys_6ulx_defconfig
 create mode 100644 include/configs/mys_6ulx.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 54d65f8488..24767198e8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1905,6 +1905,7 @@ source "board/hisilicon/hikey/Kconfig"
 source "board/hisilicon/hikey960/Kconfig"
 source "board/hisilicon/poplar/Kconfig"
 source "board/isee/igep003x/Kconfig"
+source "board/myir/mys_6ulx/Kconfig"
 source "board/silica/pengwyn/Kconfig"
 source "board/spear/spear300/Kconfig"
 source "board/spear/spear310/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9900b44274..4e06c83234 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -710,6 +710,7 @@ dtb-$(CONFIG_MX6UL) += \
 dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+   imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
imx6ull-somlabs-visionsom.dtb \
diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts 
b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts
new file mode 100644
index 00..6bc2d80837
--- /dev/null
+++ b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ * Author: Parthiban Nallathambi 
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-myir-mys-6ulx.dtsi"
+#include "imx6ull-mys-6ulx-u-boot.dtsi"
+
+/ {
+   model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
+   compatible = "myir,imx6ull-mys-6ulx-eval", "myir,imx6ull-mys-6ulx",
+"fsl,imx6ull";
+};
+
+&gpmi {
+   status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi 
b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi
new file mode 100644
index 00..03365a1ca8
--- /dev/null
+++ b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ * Author: Parthiban Nallathambi 
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "MYiR MYS-6ULX Single Board Computer";
+   compatible = "myir,imx6ull-mys-6ulx", "fsl,imx6ull";
+
+   chosen {
+   stdout-path = &uart1;
+   };
+
+   reg_vdd_5v: regulator-vdd-5v {
+   compatible = "regulator-fixed";
+   regulator-name = "VDD_5V";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   reg_vdd_3v3: regulator-vdd-3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "VDD_3V3";
+   regulator-min-

Re: [U-Boot] [PATCH] imx: sync with kernel device tree for Phycore SoM

2019-12-20 Thread Parthiban Nallathambi 

Hello Stefano,

Ping on this patch.

On 11/5/19 2:37 AM, Peng Fan wrote:

Subject: [PATCH] imx: sync with kernel device tree for Phycore SoM

Sync the Linux Kernel 5.4-rc6 device tree for Phytec Phycore SoM and Segin
board based on imx6UL and imx6ULL.

Changes includes Phytec naming convention for the devicetree files.

Signed-off-by: Parthiban Nallathambi 


Acked-by: Peng Fan 


---
  arch/arm/dts/Makefile |   4 +-
  arch/arm/dts/imx6ul-phycore-segin.dts |  81 
  ...on.dtsi => imx6ul-phytec-phycore-som.dtsi} | 130 +++
  .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts   |  93 +
  .../dts/imx6ul-phytec-segin-peb-eval-01.dtsi  |  57 +++
  arch/arm/dts/imx6ul-phytec-segin.dtsi | 346
++
  arch/arm/dts/imx6ull-phycore-segin.dts|  70 
  arch/arm/dts/imx6ull-phytec-phycore-som.dtsi  |  24
++  .../dts/imx6ull-phytec-segin-ff-rdk-emmc.dts  |  93
+  .../dts/imx6ull-phytec-segin-peb-eval-01.dtsi |  19 +
  arch/arm/dts/imx6ull-phytec-segin.dtsi|  38 ++
  board/phytec/pcl063/MAINTAINERS   |  12 +-
  configs/phycore_pcl063_defconfig  |   3 +-
  configs/phycore_pcl063_ull_defconfig  |   2 +-
  14 files changed, 732 insertions(+), 240 deletions(-)  delete mode 100644
arch/arm/dts/imx6ul-phycore-segin.dts
  rename arch/arm/dts/{pcl063-common.dtsi =>
imx6ul-phytec-phycore-som.dtsi} (56%)  create mode 100644
arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
  create mode 100644 arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
  create mode 100644 arch/arm/dts/imx6ul-phytec-segin.dtsi
  delete mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
  create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som.dtsi
  create mode 100644 arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
  create mode 100644 arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
  create mode 100644 arch/arm/dts/imx6ull-phytec-segin.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
47978e7685..935b661284 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -621,14 +621,14 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-9x9-evk.dtb \
imx6ul-9x9-evk.dtb \
imx6ul-liteboard.dtb \
-   imx6ul-phycore-segin.dtb \
+   imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb

  dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
-   imx6ull-phycore-segin.dtb \
+   imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
imx6ulz-14x14-evk.dtb

diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts
b/arch/arm/dts/imx6ul-phycore-segin.dts
deleted file mode 100644
index 7d68bf8430..00
--- a/arch/arm/dts/imx6ul-phycore-segin.dts
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Collabora Ltd.
- *
- * Based on dts[i] from Phytec barebox port:
- * Copyright (C) 2016 PHYTEC Messtechnik GmbH
- * Author: Christian Hemp 
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- *
https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.o
pensource.org%2Flicenses%2Fgpl-license.html&data=02%7C01%7Cpeng
.fan%40nxp.com%7Cb5436c55ac684a693cf308d76157d5a3%7C686ea1d3bc
2b4c6fa92cd99c5c301635%7C0%7C1%7C637084902183324601&sdata
=3jSUWElygGkm68v%2BnCz%2BoNJDlFgqGFQ5TtHXR3ZrkhE%3D&reser
ved=0
- *
https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.g
nu.org%2Fcopyleft%2Fgpl.html&data=02%7C01%7Cpeng.fan%40nxp.co
m%7Cb5436c55ac684a693cf308d76157d5a3%7C686ea1d3bc2b4c6fa92cd99
c5c301635%7C0%7C1%7C637084902183324601&sdata=iUmn4qiL0Oyl
PygYqMtZB2MNoToAhppXpwdHwFFBdyQ%3D&reserved=0
- */
-
-/dts-v1/;
-
-#include "imx6ul.dtsi"
-#include "pcl063-common.dtsi"
-
-/ {
-   model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
-   compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063",
-"fsl,imx6ul";
-};
-
-&gpmi {
-   status = "okay";
-};
-
-&i2c1 {
-   i2c_rtc: rtc@68 {
-   compatible = "microcrystal,rv4162";
-   reg = <0x68>;
-   status = "okay";
-   };
-};
-
-&uart5 {
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_uart5>;
-   uart-has-rtscts;
-   status = "okay";
-};
-
-&usbotg1 {
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_usb_otg1_id>;
-   dr_mode = "otg";
-   srp-disable;
-   hnp-disable;
-   adp-disable;
-   status = "okay";
-};
-
-&usbotg2 {
-   dr_mode = "host";
-   disable-o

[U-Boot] [PATCH] imx: sync with kernel device tree for Phycore SoM

2019-11-04 Thread Parthiban Nallathambi 
Sync the Linux Kernel 5.4-rc6 device tree for Phytec Phycore
SoM and Segin board based on imx6UL and imx6ULL.

Changes includes Phytec naming convention for the devicetree files.

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/dts/Makefile |   4 +-
 arch/arm/dts/imx6ul-phycore-segin.dts |  81 
 ...on.dtsi => imx6ul-phytec-phycore-som.dtsi} | 130 +++
 .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts   |  93 +
 .../dts/imx6ul-phytec-segin-peb-eval-01.dtsi  |  57 +++
 arch/arm/dts/imx6ul-phytec-segin.dtsi | 346 ++
 arch/arm/dts/imx6ull-phycore-segin.dts|  70 
 arch/arm/dts/imx6ull-phytec-phycore-som.dtsi  |  24 ++
 .../dts/imx6ull-phytec-segin-ff-rdk-emmc.dts  |  93 +
 .../dts/imx6ull-phytec-segin-peb-eval-01.dtsi |  19 +
 arch/arm/dts/imx6ull-phytec-segin.dtsi|  38 ++
 board/phytec/pcl063/MAINTAINERS   |  12 +-
 configs/phycore_pcl063_defconfig  |   3 +-
 configs/phycore_pcl063_ull_defconfig  |   2 +-
 14 files changed, 732 insertions(+), 240 deletions(-)
 delete mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts
 rename arch/arm/dts/{pcl063-common.dtsi => imx6ul-phytec-phycore-som.dtsi} 
(56%)
 create mode 100644 arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
 create mode 100644 arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
 create mode 100644 arch/arm/dts/imx6ul-phytec-segin.dtsi
 delete mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
 create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som.dtsi
 create mode 100644 arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
 create mode 100644 arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
 create mode 100644 arch/arm/dts/imx6ull-phytec-segin.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 47978e7685..935b661284 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -621,14 +621,14 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-9x9-evk.dtb \
imx6ul-9x9-evk.dtb \
imx6ul-liteboard.dtb \
-   imx6ul-phycore-segin.dtb \
+   imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb
 
 dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
-   imx6ull-phycore-segin.dtb \
+   imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
imx6ulz-14x14-evk.dtb
 
diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts 
b/arch/arm/dts/imx6ul-phycore-segin.dts
deleted file mode 100644
index 7d68bf8430..00
--- a/arch/arm/dts/imx6ul-phycore-segin.dts
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Collabora Ltd.
- *
- * Based on dts[i] from Phytec barebox port:
- * Copyright (C) 2016 PHYTEC Messtechnik GmbH
- * Author: Christian Hemp 
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-
-#include "imx6ul.dtsi"
-#include "pcl063-common.dtsi"
-
-/ {
-   model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
-   compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063",
-"fsl,imx6ul";
-};
-
-&gpmi {
-   status = "okay";
-};
-
-&i2c1 {
-   i2c_rtc: rtc@68 {
-   compatible = "microcrystal,rv4162";
-   reg = <0x68>;
-   status = "okay";
-   };
-};
-
-&uart5 {
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_uart5>;
-   uart-has-rtscts;
-   status = "okay";
-};
-
-&usbotg1 {
-   pinctrl-names = "default";
-   pinctrl-0 = <&pinctrl_usb_otg1_id>;
-   dr_mode = "otg";
-   srp-disable;
-   hnp-disable;
-   adp-disable;
-   status = "okay";
-};
-
-&usbotg2 {
-   dr_mode = "host";
-   disable-over-current;
-   status = "okay";
-};
-
-&iomuxc {
-   pinctrl-names = "default";
-
-   pinctrl_uart5: uart5grp {
-   fsl,pins = <
-   MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
-   MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
-   MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
-   MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
-   >;
-   };
-
-   pinctrl_usb_otg1_id: usbotg1idgrp {
-   fsl,pins = <
-   MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID0x17059
-   >;
-   };
-
-};
diff --git a/arch/arm/dts/pcl063-common.dtsi 
b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
simi

[U-Boot] [PATCH v3] i.MX6: nand: extend nandbcb command for imx6UL(L)

2019-10-18 Thread Parthiban Nallathambi 
Firmware Configuration Block(FCB) for imx6ul(l) needs to be
BCH encoded.

Signed-off-by: Parthiban Nallathambi 
Acked-by: Shyam Saini 
Acked-by: Peng Fan 
---

Notes:
Notes:
Changes in v3:
- Conditionally include BCH both in Kconfig and source
Changes in v2:
- use kfree instead of free

 arch/arm/mach-imx/Kconfig   |  1 +
 arch/arm/mach-imx/cmd_nandbcb.c | 69 +
 2 files changed, 70 insertions(+)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b0b9d2c070..4a2f39b110 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -81,6 +81,7 @@ config CMD_HDMIDETECT
 config CMD_NANDBCB
bool "i.MX6 NAND Boot Control Block(BCB) command"
depends on NAND && CMD_MTDPARTS
+   select BCH if MX6UL || MX6ULL
default y if ARCH_MX6 && NAND_MXS
help
  Unlike normal 'nand write/erase' commands, this command update
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index 7811c61d22..1a2e017aaf 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -14,6 +14,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -25,6 +26,68 @@
 #define BF_VAL(v, bf)  (((v) & bf##_MASK) >> bf##_OFFSET)
 #define GETBIT(v, n)   (((v) >> (n)) & 0x1)
 
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+static uint8_t reverse_bit(uint8_t b)
+{
+   b = (b & 0xf0) >> 4 | (b & 0x0f) << 4;
+   b = (b & 0xcc) >> 2 | (b & 0x33) << 2;
+   b = (b & 0xaa) >> 1 | (b & 0x55) << 1;
+
+   return b;
+}
+
+static void encode_bch_ecc(void *buf, struct fcb_block *fcb, int eccbits)
+{
+   int i, j, m = 13;
+   int blocksize = 128;
+   int numblocks = 8;
+   int ecc_buf_size = (m * eccbits + 7) / 8;
+   struct bch_control *bch = init_bch(m, eccbits, 0);
+   u8 *ecc_buf = kzalloc(ecc_buf_size, GFP_KERNEL);
+   u8 *tmp_buf = kzalloc(blocksize * numblocks, GFP_KERNEL);
+   u8 *psrc, *pdst;
+
+   /*
+* The blocks here are bit aligned. If eccbits is a multiple of 8,
+* we just can copy bytes. Otherwiese we must move the blocks to
+* the next free bit position.
+*/
+   WARN_ON(eccbits % 8);
+
+   memcpy(tmp_buf, fcb, sizeof(*fcb));
+
+   for (i = 0; i < numblocks; i++) {
+   memset(ecc_buf, 0, ecc_buf_size);
+   psrc = tmp_buf + i * blocksize;
+   pdst = buf + i * (blocksize + ecc_buf_size);
+
+   /* copy data byte aligned to destination buf */
+   memcpy(pdst, psrc, blocksize);
+
+   /*
+* imx-kobs use a modified encode_bch which reverse the
+* bit order of the data before calculating bch.
+* Do this in the buffer and use the bch lib here.
+*/
+   for (j = 0; j < blocksize; j++)
+   psrc[j] = reverse_bit(psrc[j]);
+
+   encode_bch(bch, psrc, blocksize, ecc_buf);
+
+   /* reverse ecc bit */
+   for (j = 0; j < ecc_buf_size; j++)
+   ecc_buf[j] = reverse_bit(ecc_buf[j]);
+
+   /* Here eccbuf is byte aligned and we can just copy it */
+   memcpy(pdst + blocksize, ecc_buf, ecc_buf_size);
+   }
+
+   kfree(ecc_buf);
+   kfree(tmp_buf);
+   free_bch(bch);
+}
+#else
+
 static u8 calculate_parity_13_8(u8 d)
 {
u8 p = 0;
@@ -50,6 +113,7 @@ static void encode_hamming_13_8(void *_src, void *_ecc, 
size_t size)
for (i = 0; i < size; i++)
ecc[i] = calculate_parity_13_8(src[i]);
 }
+#endif
 
 static u32 calc_chksum(void *buf, size_t size)
 {
@@ -231,8 +295,13 @@ static int nandbcb_update(struct mtd_info *mtd, loff_t 
off, size_t size,
goto dbbt_data_page_err;
}
 
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+   /* 40 bit BCH, for i.MX6UL(L) */
+   encode_bch_ecc(fcb_raw_page + 32, fcb, 40);
+#else
memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
encode_hamming_13_8(fcb_raw_page + 12, fcb_raw_page + 12 + 512, 512);
+#endif
/*
 * Set the first and second byte of OOB data to 0xFF, not 0x00. These
 * bytes are used as the Manufacturers Bad Block Marker (MBBM). Since
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] i.MX6: nand: extend nandbcb command for imx6UL(L)

2019-10-18 Thread Parthiban Nallathambi 

Hello Stefano,

On 10/8/19 10:23 AM, Stefano Babic wrote:

On 08/10/19 10:12, Parthiban Nallathambi wrote:

Hi Stefano,

On 10/7/19 6:06 PM, Stefano Babic wrote:

Hi Parthiban,

On 23/08/19 18:19, Parthiban Nallathambi wrote:

Firmware Configuration Block(FCB) for imx6ul(l) needs to be
BCH encoded. This patch depends on [1].

[1]: https://patchwork.ozlabs.org/project/uboot/list/?series=113810



Why does it depend on this if it is just defoconfig for a board ?


The patch series was nandbcb inclusion, but this is already merged in u-boot.
patchwork query shows only the pending merger now.

As the nandbcb is already in mainline, this patch should apply fine.


Please read the whole e-mail. Issue is not that patch cannot be applied,
issue is that it breaks several boards. All i.MX6 boards with NAND -
check again:


Building current source for 1 boards (1 thread, 8 jobs per thread)
arm:  +   pfla02
+arch/arm/mach-imx/built-in.o: In function `encode_bch_ecc':
+arch/arm/mach-imx/cmd_nandbcb.c:45: undefined reference to `init_bch'
+arch/arm/mach-imx/cmd_nandbcb.c:75: undefined reference to `encode_bch'
+arch/arm/mach-imx/cmd_nandbcb.c:87: undefined reference to `free_bch'
+arm-poky-linux-gnueabi-ld.bfd: BFD (GNU Binutils) 2.28.0.20170307
assertion fail ../../bfd/elf32-arm.c:9512
+make[1]: *** [u-boot] Error 1
+make: *** [sub-make] Error 2
 001 /1  pfla02


The same happens to other boards, too.


I missed this. Will send v3 with conditionally including BCH in source
as well.

Thanks,
Parthiban N



Best regards,
Stefano Babic



Thanks,
Parthiban N




Signed-off-by: Parthiban Nallathambi 
Acked-by: Shyam Saini 
---

Notes:
 Changes in v2:
 - use kfree instead of free

  arch/arm/mach-imx/Kconfig   |  1 +
  arch/arm/mach-imx/cmd_nandbcb.c | 72 -
  2 files changed, 71 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index aeb5493488..175bed601e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -74,6 +74,7 @@ config CMD_HDMIDETECT
  config CMD_NANDBCB
bool "i.MX6 NAND Boot Control Block(BCB) command"
depends on NAND && CMD_MTDPARTS
+   select BCH if MX6UL || MX6ULL


This eems to break all i.MX6 boards (not UL(L)) using NAND. In fact, I
get these errors:

Building current source for 1 boards (1 thread, 8 jobs per thread)
arm:  +   pfla02
+arch/arm/mach-imx/built-in.o: In function `encode_bch_ecc':
+arch/arm/mach-imx/cmd_nandbcb.c:45: undefined reference to `init_bch'
+arch/arm/mach-imx/cmd_nandbcb.c:75: undefined reference to `encode_bch'
+arch/arm/mach-imx/cmd_nandbcb.c:87: undefined reference to `free_bch'
+arm-poky-linux-gnueabi-ld.bfd: BFD (GNU Binutils) 2.28.0.20170307
assertion fail ../../bfd/elf32-arm.c:9512
+make[1]: *** [u-boot] Error 1
+make: *** [sub-make] Error 2
 001 /1  pfla02

Can you check this please ? I temporary remove the patch from -next branch.

Best regards,
Stefano Babic


default y if ARCH_MX6 && NAND_MXS
help
  Unlike normal 'nand write/erase' commands, this command update
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index 065b814b2e..e11df401e4 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -14,8 +14,10 @@
  
  #include 

  #include 
+#include 
  #include 
  
+#include 

  #include 
  #include 
  #include 
@@ -25,6 +27,66 @@
  #define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
  #define GETBIT(v, n)  (((v) >> (n)) & 0x1)
  
+static uint8_t reverse_bit(uint8_t b)

+{
+   b = (b & 0xf0) >> 4 | (b & 0x0f) << 4;
+   b = (b & 0xcc) >> 2 | (b & 0x33) << 2;
+   b = (b & 0xaa) >> 1 | (b & 0x55) << 1;
+
+   return b;
+}
+
+static void encode_bch_ecc(void *buf, struct fcb_block *fcb, int eccbits)
+{
+   int i, j, m = 13;
+   int blocksize = 128;
+   int numblocks = 8;
+   int ecc_buf_size = (m * eccbits + 7) / 8;
+   struct bch_control *bch = init_bch(m, eccbits, 0);
+   u8 *ecc_buf = kzalloc(ecc_buf_size, GFP_KERNEL);
+   u8 *tmp_buf = kzalloc(blocksize * numblocks, GFP_KERNEL);
+   u8 *psrc, *pdst;
+
+   /*
+* The blocks here are bit aligned. If eccbits is a multiple of 8,
+* we just can copy bytes. Otherwiese we must move the blocks to
+* the next free bit position.
+*/
+   WARN_ON(eccbits % 8);
+
+   memcpy(tmp_buf, fcb, sizeof(*fcb));
+
+   for (i = 0; i < numblocks; i++) {
+   memset(ecc_buf, 0, ecc_buf_size);
+   psrc = tmp_buf + i * blocksize;
+   pdst = buf + i * (blocksize + ecc_buf_size);
+
+   /* copy data byte aligned to destination buf */
+   memcpy(pdst, psrc, blocksize

Re: [U-Boot] [PATCH v2 1/2] i.MX6: nand: extend nandbcb command for imx6UL(L)

2019-10-08 Thread Parthiban Nallathambi 
Hi Stefano,

On 10/7/19 6:06 PM, Stefano Babic wrote:
> Hi Parthiban,
> 
> On 23/08/19 18:19, Parthiban Nallathambi wrote:
>> Firmware Configuration Block(FCB) for imx6ul(l) needs to be
>> BCH encoded. This patch depends on [1].
>>
>> [1]: https://patchwork.ozlabs.org/project/uboot/list/?series=113810
>>
> 
> Why does it depend on this if it is just defoconfig for a board ?

The patch series was nandbcb inclusion, but this is already merged in u-boot.
patchwork query shows only the pending merger now.

As the nandbcb is already in mainline, this patch should apply fine.

Thanks,
Parthiban N

> 
>> Signed-off-by: Parthiban Nallathambi 
>> Acked-by: Shyam Saini 
>> ---
>>
>> Notes:
>> Changes in v2:
>> - use kfree instead of free
>>
>>  arch/arm/mach-imx/Kconfig   |  1 +
>>  arch/arm/mach-imx/cmd_nandbcb.c | 72 -
>>  2 files changed, 71 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
>> index aeb5493488..175bed601e 100644
>> --- a/arch/arm/mach-imx/Kconfig
>> +++ b/arch/arm/mach-imx/Kconfig
>> @@ -74,6 +74,7 @@ config CMD_HDMIDETECT
>>  config CMD_NANDBCB
>>  bool "i.MX6 NAND Boot Control Block(BCB) command"
>>  depends on NAND && CMD_MTDPARTS
>> +select BCH if MX6UL || MX6ULL
> 
> This eems to break all i.MX6 boards (not UL(L)) using NAND. In fact, I
> get these errors:
> 
> Building current source for 1 boards (1 thread, 8 jobs per thread)
>arm:  +   pfla02
> +arch/arm/mach-imx/built-in.o: In function `encode_bch_ecc':
> +arch/arm/mach-imx/cmd_nandbcb.c:45: undefined reference to `init_bch'
> +arch/arm/mach-imx/cmd_nandbcb.c:75: undefined reference to `encode_bch'
> +arch/arm/mach-imx/cmd_nandbcb.c:87: undefined reference to `free_bch'
> +arm-poky-linux-gnueabi-ld.bfd: BFD (GNU Binutils) 2.28.0.20170307
> assertion fail ../../bfd/elf32-arm.c:9512
> +make[1]: *** [u-boot] Error 1
> +make: *** [sub-make] Error 2
> 001 /1  pfla02
> 
> Can you check this please ? I temporary remove the patch from -next branch.
> 
> Best regards,
> Stefano Babic
> 
>>  default y if ARCH_MX6 && NAND_MXS
>>  help
>>Unlike normal 'nand write/erase' commands, this command update
>> diff --git a/arch/arm/mach-imx/cmd_nandbcb.c 
>> b/arch/arm/mach-imx/cmd_nandbcb.c
>> index 065b814b2e..e11df401e4 100644
>> --- a/arch/arm/mach-imx/cmd_nandbcb.c
>> +++ b/arch/arm/mach-imx/cmd_nandbcb.c
>> @@ -14,8 +14,10 @@
>>  
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -25,6 +27,66 @@
>>  #define BF_VAL(v, bf)   (((v) & bf##_MASK) >> bf##_OFFSET)
>>  #define GETBIT(v, n)(((v) >> (n)) & 0x1)
>>  
>> +static uint8_t reverse_bit(uint8_t b)
>> +{
>> +b = (b & 0xf0) >> 4 | (b & 0x0f) << 4;
>> +b = (b & 0xcc) >> 2 | (b & 0x33) << 2;
>> +b = (b & 0xaa) >> 1 | (b & 0x55) << 1;
>> +
>> +return b;
>> +}
>> +
>> +static void encode_bch_ecc(void *buf, struct fcb_block *fcb, int eccbits)
>> +{
>> +int i, j, m = 13;
>> +int blocksize = 128;
>> +int numblocks = 8;
>> +int ecc_buf_size = (m * eccbits + 7) / 8;
>> +struct bch_control *bch = init_bch(m, eccbits, 0);
>> +u8 *ecc_buf = kzalloc(ecc_buf_size, GFP_KERNEL);
>> +u8 *tmp_buf = kzalloc(blocksize * numblocks, GFP_KERNEL);
>> +u8 *psrc, *pdst;
>> +
>> +/*
>> + * The blocks here are bit aligned. If eccbits is a multiple of 8,
>> + * we just can copy bytes. Otherwiese we must move the blocks to
>> + * the next free bit position.
>> + */
>> +WARN_ON(eccbits % 8);
>> +
>> +memcpy(tmp_buf, fcb, sizeof(*fcb));
>> +
>> +for (i = 0; i < numblocks; i++) {
>> +memset(ecc_buf, 0, ecc_buf_size);
>> +psrc = tmp_buf + i * blocksize;
>> +pdst = buf + i * (blocksize + ecc_buf_size);
>> +
>> +/* copy data byte aligned to destination buf */
>> +memcpy(pdst, psrc, blocksize);
>> +
>> +/*
>> + * imx-kobs use a modified encode_bch which reverse the
>> + * bit order of the data before calculating bch.
>> + * Do this in the buffer and use the bch

[U-Boot] [PATCH] ARM: dts: pcl063: add usdhc reset pin of eMMC

2019-09-26 Thread Parthiban Nallathambi 
pcl063 phycore SoM with eMMC also got usdhc reset pin,
add reset pin to pinmux.

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/dts/pcl063-common.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/pcl063-common.dtsi b/arch/arm/dts/pcl063-common.dtsi
index 2b14b2dc5f..b88dde2fb0 100644
--- a/arch/arm/dts/pcl063-common.dtsi
+++ b/arch/arm/dts/pcl063-common.dtsi
@@ -113,7 +113,7 @@
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO0x1b0b0
-   MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
+   MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN  0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER  0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
@@ -191,6 +191,7 @@
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+   MX6UL_PAD_NAND_ALE__USDHC2_RESET_B  0x170f9
>;
};
 };
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] configs: move CONFIG_SPL_TEXT_BASE to Kconfig

2019-09-16 Thread Parthiban Nallathambi 
CONFIG_SPL_TEXT_BASE is moved to common/spl/Kconfig, update
pcl063_ull defconfig.

Signed-off-by: Parthiban Nallathambi 
---
 configs/phycore_pcl063_ull_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/phycore_pcl063_ull_defconfig 
b/configs/phycore_pcl063_ull_defconfig
index 4b9bb36984..b516248a5f 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x908000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 3/3] imx: nandbcb: include long help only when enabled

2019-08-23 Thread Parthiban Nallathambi 
conditionally include long help text when enabled

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/mach-imx/cmd_nandbcb.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index 065b814b2e..7811c61d22 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -359,9 +359,11 @@ usage:
return CMD_RET_USAGE;
 }
 
+#ifdef CONFIG_SYS_LONGHELP
 static char nandbcb_help_text[] =
"update addr off|partition len  - update 'len' bytes starting at\n"
"   'off|part' to memory address 'addr', skipping  bad blocks";
+#endif
 
 U_BOOT_CMD(nandbcb, 5, 1, do_nandbcb,
   "i.MX6 Nand BCB",
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 2/3] imx: initialize fec only when enabled

2019-08-23 Thread Parthiban Nallathambi 
board early initialize fec ethernet controller pinmux
only when FEC is enabled

Signed-off-by: Parthiban Nallathambi 
---
 board/phytec/pcl063/pcl063.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c
index f8cbd1c11e..96dd9e38f3 100644
--- a/board/phytec/pcl063/pcl063.c
+++ b/board/phytec/pcl063/pcl063.c
@@ -178,7 +178,9 @@ int board_phy_config(struct phy_device *phydev)
 int board_early_init_f(void)
 {
setup_iomux_uart();
+#ifdef CONFIG_FEC_MXC
setup_iomux_fec();
+#endif
 
return 0;
 }
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 1/3] imx: remove board specific boot order from spl

2019-08-23 Thread Parthiban Nallathambi 
boot order was added to handle both SD and eMMC. But commit
14d319b1 introduced to handle both eMMC and SD globally.

Signed-off-by: Parthiban Nallathambi 
---
 board/phytec/pcl063/spl.c | 23 ---
 1 file changed, 23 deletions(-)

diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
index 6d4c827918..18fc251890 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -182,29 +182,6 @@ int board_mmc_init(bd_t *bis)
 
return 0;
 }
-
-void board_boot_order(u32 *spl_boot_list)
-{
-   u32 bmode = imx6_src_get_boot_mode();
-   u8 boot_dev = BOOT_DEVICE_MMC1;
-
-   switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
-   case IMX6_BMODE_SD:
-   case IMX6_BMODE_ESD:
-   boot_dev = BOOT_DEVICE_MMC1;
-   break;
-   case IMX6_BMODE_MMC:
-   case IMX6_BMODE_EMMC:
-   boot_dev = BOOT_DEVICE_MMC2;
-   break;
-   default:
-   /* Default - BOOT_DEVICE_MMC1 */
-   printf("Wrong board boot order\n");
-   break;
-   }
-
-   spl_boot_list[0] = boot_dev;
-}
 #endif /* CONFIG_FSL_ESDHC_IMX */
 
 void board_init_f(ulong dummy)
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 1/2] i.MX6: nand: extend nandbcb command for imx6UL(L)

2019-08-23 Thread Parthiban Nallathambi 
Firmware Configuration Block(FCB) for imx6ul(l) needs to be
BCH encoded. This patch depends on [1].

[1]: https://patchwork.ozlabs.org/project/uboot/list/?series=113810

Signed-off-by: Parthiban Nallathambi 
Acked-by: Shyam Saini 
---

Notes:
Changes in v2:
- use kfree instead of free

 arch/arm/mach-imx/Kconfig   |  1 +
 arch/arm/mach-imx/cmd_nandbcb.c | 72 -
 2 files changed, 71 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index aeb5493488..175bed601e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -74,6 +74,7 @@ config CMD_HDMIDETECT
 config CMD_NANDBCB
bool "i.MX6 NAND Boot Control Block(BCB) command"
depends on NAND && CMD_MTDPARTS
+   select BCH if MX6UL || MX6ULL
default y if ARCH_MX6 && NAND_MXS
help
  Unlike normal 'nand write/erase' commands, this command update
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index 065b814b2e..e11df401e4 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -14,8 +14,10 @@
 
 #include 
 #include 
+#include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
@@ -25,6 +27,66 @@
 #define BF_VAL(v, bf)  (((v) & bf##_MASK) >> bf##_OFFSET)
 #define GETBIT(v, n)   (((v) >> (n)) & 0x1)
 
+static uint8_t reverse_bit(uint8_t b)
+{
+   b = (b & 0xf0) >> 4 | (b & 0x0f) << 4;
+   b = (b & 0xcc) >> 2 | (b & 0x33) << 2;
+   b = (b & 0xaa) >> 1 | (b & 0x55) << 1;
+
+   return b;
+}
+
+static void encode_bch_ecc(void *buf, struct fcb_block *fcb, int eccbits)
+{
+   int i, j, m = 13;
+   int blocksize = 128;
+   int numblocks = 8;
+   int ecc_buf_size = (m * eccbits + 7) / 8;
+   struct bch_control *bch = init_bch(m, eccbits, 0);
+   u8 *ecc_buf = kzalloc(ecc_buf_size, GFP_KERNEL);
+   u8 *tmp_buf = kzalloc(blocksize * numblocks, GFP_KERNEL);
+   u8 *psrc, *pdst;
+
+   /*
+* The blocks here are bit aligned. If eccbits is a multiple of 8,
+* we just can copy bytes. Otherwiese we must move the blocks to
+* the next free bit position.
+*/
+   WARN_ON(eccbits % 8);
+
+   memcpy(tmp_buf, fcb, sizeof(*fcb));
+
+   for (i = 0; i < numblocks; i++) {
+   memset(ecc_buf, 0, ecc_buf_size);
+   psrc = tmp_buf + i * blocksize;
+   pdst = buf + i * (blocksize + ecc_buf_size);
+
+   /* copy data byte aligned to destination buf */
+   memcpy(pdst, psrc, blocksize);
+
+   /*
+* imx-kobs use a modified encode_bch which reverse the
+* bit order of the data before calculating bch.
+* Do this in the buffer and use the bch lib here.
+*/
+   for (j = 0; j < blocksize; j++)
+   psrc[j] = reverse_bit(psrc[j]);
+
+   encode_bch(bch, psrc, blocksize, ecc_buf);
+
+   /* reverse ecc bit */
+   for (j = 0; j < ecc_buf_size; j++)
+   ecc_buf[j] = reverse_bit(ecc_buf[j]);
+
+   /* Here eccbuf is byte aligned and we can just copy it */
+   memcpy(pdst + blocksize, ecc_buf, ecc_buf_size);
+   }
+
+   kfree(ecc_buf);
+   kfree(tmp_buf);
+   free_bch(bch);
+}
+
 static u8 calculate_parity_13_8(u8 d)
 {
u8 p = 0;
@@ -231,8 +293,14 @@ static int nandbcb_update(struct mtd_info *mtd, loff_t 
off, size_t size,
goto dbbt_data_page_err;
}
 
-   memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
-   encode_hamming_13_8(fcb_raw_page + 12, fcb_raw_page + 12 + 512, 512);
+   if (is_mx6ul() || is_mx6ull()) {
+   /* 40 bit BCH, for i.MX6UL(L) */
+   encode_bch_ecc(fcb_raw_page + 32, fcb, 40);
+   } else {
+   memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
+   encode_hamming_13_8(fcb_raw_page + 12,
+   fcb_raw_page + 12 + 512, 512);
+   }
/*
 * Set the first and second byte of OOB data to 0xFF, not 0x00. These
 * bytes are used as the Manufacturers Bad Block Marker (MBBM). Since
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 2/2] imx: pcl063: add nand boot support

2019-08-23 Thread Parthiban Nallathambi 
Booting from NAND needs nandbcb and nand boot device selection

Signed-off-by: Parthiban Nallathambi 
---

Notes:
Changes in v2:
- None

 board/phytec/pcl063/spl.c| 3 +++
 configs/phycore_pcl063_defconfig | 1 +
 2 files changed, 4 insertions(+)

diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
index 6d4c827918..358156bfbc 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -197,6 +197,9 @@ void board_boot_order(u32 *spl_boot_list)
case IMX6_BMODE_EMMC:
boot_dev = BOOT_DEVICE_MMC2;
break;
+   case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
+   boot_dev = BOOT_DEVICE_NAND;
+   break;
default:
/* Default - BOOT_DEVICE_MMC1 */
printf("Wrong board boot order\n");
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index cf43b43924..c55670a8ff 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_MTD=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_NANDBCB=y
 CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
 CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)"
 CONFIG_CMD_UBI=y
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] i.MX6: nand: extend nandbcb command for imx6UL(L)

2019-08-13 Thread Parthiban Nallathambi 

Hi Shyam,

On 8/13/19 3:40 PM, Shyam Saini wrote:

Hi Parthiban,

Thanks a lot for working on this.


Still enabling SECURE_BOOT fails to boot. Am yet to figure out this.
Do you have secure boot working from NAND?



Please see comments below.


Firmware Configuration Block(FCB) for imx6ul(l) needs to be
BCH encoded. This patch depends on [1].

[1]: https://patchwork.ozlabs.org/project/uboot/list/?series=113810

Signed-off-by: Parthiban Nallathambi 
---
  arch/arm/mach-imx/Kconfig   |  1 +
  arch/arm/mach-imx/cmd_nandbcb.c | 72 -
  2 files changed, 71 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index aeb5493488..175bed601e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -74,6 +74,7 @@ config CMD_HDMIDETECT
  config CMD_NANDBCB
 bool "i.MX6 NAND Boot Control Block(BCB) command"
 depends on NAND && CMD_MTDPARTS
+   select BCH if MX6UL || MX6ULL
 default y if ARCH_MX6 && NAND_MXS
 help
   Unlike normal 'nand write/erase' commands, this command update
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index 065b814b2e..34176ee6e4 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -14,8 +14,10 @@

  #include 
  #include 
+#include 
  #include 

+#include 
  #include 
  #include 
  #include 
@@ -25,6 +27,66 @@
  #define BF_VAL(v, bf)  (((v) & bf##_MASK) >> bf##_OFFSET)
  #define GETBIT(v, n)   (((v) >> (n)) & 0x1)

+static uint8_t reverse_bit(uint8_t b)
+{
+   b = (b & 0xf0) >> 4 | (b & 0x0f) << 4;
+   b = (b & 0xcc) >> 2 | (b & 0x33) << 2;
+   b = (b & 0xaa) >> 1 | (b & 0x55) << 1;
+
+   return b;
+}
+
+static void encode_bch_ecc(void *buf, struct fcb_block *fcb, int eccbits)
+{
+   int i, j, m = 13;
+   int blocksize = 128;
+   int numblocks = 8;
+   int ecc_buf_size = (m * eccbits + 7) / 8;
+   struct bch_control *bch = init_bch(m, eccbits, 0);
+   u8 *ecc_buf = kzalloc(ecc_buf_size, GFP_KERNEL);
+   u8 *tmp_buf = kzalloc(blocksize * numblocks, GFP_KERNEL);
+   u8 *psrc, *pdst;
+
+   /*
+* The blocks here are bit aligned. If eccbits is a multiple of 8,
+* we just can copy bytes. Otherwiese we must move the blocks to
+* the next free bit position.
+*/
+   WARN_ON(eccbits % 8);
+
+   memcpy(tmp_buf, fcb, sizeof(*fcb));
+
+   for (i = 0; i < numblocks; i++) {
+   memset(ecc_buf, 0, ecc_buf_size);
+   psrc = tmp_buf + i * blocksize;
+   pdst = buf + i * (blocksize + ecc_buf_size);
+
+   /* copy data byte aligned to destination buf */
+   memcpy(pdst, psrc, blocksize);
+
+   /*
+* imx-kobs use a modified encode_bch which reverse the
+* bit order of the data before calculating bch.
+* Do this in the buffer and use the bch lib here.
+*/
+   for (j = 0; j < blocksize; j++)
+   psrc[j] = reverse_bit(psrc[j]);
+
+   encode_bch(bch, psrc, blocksize, ecc_buf);
+
+   /* reverse ecc bit */
+   for (j = 0; j < ecc_buf_size; j++)
+   ecc_buf[j] = reverse_bit(ecc_buf[j]);
+
+   /* Here eccbuf is byte aligned and we can just copy it */
+   memcpy(pdst + blocksize, ecc_buf, ecc_buf_size);
+   }
+
+   free(ecc_buf);
+   free(tmp_buf);
+   free_bch(bch);


I have used kfree() instead of free() in entire nand bcb code
So, I think for consistency reason it should be kfree here.

Could you please resend this patch with above mentioned changes.
Other than this,


Thanks, will change it to kfree in v2.





  static u8 calculate_parity_13_8(u8 d)
  {
 u8 p = 0;
@@ -231,8 +293,14 @@ static int nandbcb_update(struct mtd_info *mtd, loff_t 
off, size_t size,
 goto dbbt_data_page_err;
 }

-   memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
-   encode_hamming_13_8(fcb_raw_page + 12, fcb_raw_page + 12 + 512, 512);
+   if (is_mx6ul() || is_mx6ull()) {
+   /* 40 bit BCH, for i.MX6UL(L) */
+   encode_bch_ecc(fcb_raw_page + 32, fcb, 40);
+   } else {
+   memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
+   encode_hamming_13_8(fcb_raw_page + 12,
+   fcb_raw_page + 12 + 512, 512);
+   }
 /*
  * Set the first and second byte of OOB data to 0xFF, not 0x00. These
  * bytes are used as the Manufacturers Bad Block Marker (MBBM). Since


Acked-by: Shyam Saini 



--
Thanks,
Parthiban N

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 1

[U-Boot] [PATCH 2/2] imx: pcl063: add nand boot support

2019-07-18 Thread Parthiban Nallathambi 
Booting from NAND needs nandbcb and nand boot device selection

Signed-off-by: Parthiban Nallathambi 
---
 board/phytec/pcl063/spl.c| 3 +++
 configs/phycore_pcl063_defconfig | 1 +
 2 files changed, 4 insertions(+)

diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
index 6d4c827918..358156bfbc 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -197,6 +197,9 @@ void board_boot_order(u32 *spl_boot_list)
case IMX6_BMODE_EMMC:
boot_dev = BOOT_DEVICE_MMC2;
break;
+   case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
+   boot_dev = BOOT_DEVICE_NAND;
+   break;
default:
/* Default - BOOT_DEVICE_MMC1 */
printf("Wrong board boot order\n");
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index cf43b43924..c55670a8ff 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_MTD=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_NANDBCB=y
 CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
 CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)"
 CONFIG_CMD_UBI=y
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 1/2] i.MX6: nand: extend nandbcb command for imx6UL(L)

2019-07-18 Thread Parthiban Nallathambi 
Firmware Configuration Block(FCB) for imx6ul(l) needs to be
BCH encoded. This patch depends on [1].

[1]: https://patchwork.ozlabs.org/project/uboot/list/?series=113810

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/mach-imx/Kconfig   |  1 +
 arch/arm/mach-imx/cmd_nandbcb.c | 72 -
 2 files changed, 71 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index aeb5493488..175bed601e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -74,6 +74,7 @@ config CMD_HDMIDETECT
 config CMD_NANDBCB
bool "i.MX6 NAND Boot Control Block(BCB) command"
depends on NAND && CMD_MTDPARTS
+   select BCH if MX6UL || MX6ULL
default y if ARCH_MX6 && NAND_MXS
help
  Unlike normal 'nand write/erase' commands, this command update
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index 065b814b2e..34176ee6e4 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -14,8 +14,10 @@
 
 #include 
 #include 
+#include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
@@ -25,6 +27,66 @@
 #define BF_VAL(v, bf)  (((v) & bf##_MASK) >> bf##_OFFSET)
 #define GETBIT(v, n)   (((v) >> (n)) & 0x1)
 
+static uint8_t reverse_bit(uint8_t b)
+{
+   b = (b & 0xf0) >> 4 | (b & 0x0f) << 4;
+   b = (b & 0xcc) >> 2 | (b & 0x33) << 2;
+   b = (b & 0xaa) >> 1 | (b & 0x55) << 1;
+
+   return b;
+}
+
+static void encode_bch_ecc(void *buf, struct fcb_block *fcb, int eccbits)
+{
+   int i, j, m = 13;
+   int blocksize = 128;
+   int numblocks = 8;
+   int ecc_buf_size = (m * eccbits + 7) / 8;
+   struct bch_control *bch = init_bch(m, eccbits, 0);
+   u8 *ecc_buf = kzalloc(ecc_buf_size, GFP_KERNEL);
+   u8 *tmp_buf = kzalloc(blocksize * numblocks, GFP_KERNEL);
+   u8 *psrc, *pdst;
+
+   /*
+* The blocks here are bit aligned. If eccbits is a multiple of 8,
+* we just can copy bytes. Otherwiese we must move the blocks to
+* the next free bit position.
+*/
+   WARN_ON(eccbits % 8);
+
+   memcpy(tmp_buf, fcb, sizeof(*fcb));
+
+   for (i = 0; i < numblocks; i++) {
+   memset(ecc_buf, 0, ecc_buf_size);
+   psrc = tmp_buf + i * blocksize;
+   pdst = buf + i * (blocksize + ecc_buf_size);
+
+   /* copy data byte aligned to destination buf */
+   memcpy(pdst, psrc, blocksize);
+
+   /*
+* imx-kobs use a modified encode_bch which reverse the
+* bit order of the data before calculating bch.
+* Do this in the buffer and use the bch lib here.
+*/
+   for (j = 0; j < blocksize; j++)
+   psrc[j] = reverse_bit(psrc[j]);
+
+   encode_bch(bch, psrc, blocksize, ecc_buf);
+
+   /* reverse ecc bit */
+   for (j = 0; j < ecc_buf_size; j++)
+   ecc_buf[j] = reverse_bit(ecc_buf[j]);
+
+   /* Here eccbuf is byte aligned and we can just copy it */
+   memcpy(pdst + blocksize, ecc_buf, ecc_buf_size);
+   }
+
+   free(ecc_buf);
+   free(tmp_buf);
+   free_bch(bch);
+}
+
 static u8 calculate_parity_13_8(u8 d)
 {
u8 p = 0;
@@ -231,8 +293,14 @@ static int nandbcb_update(struct mtd_info *mtd, loff_t 
off, size_t size,
goto dbbt_data_page_err;
}
 
-   memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
-   encode_hamming_13_8(fcb_raw_page + 12, fcb_raw_page + 12 + 512, 512);
+   if (is_mx6ul() || is_mx6ull()) {
+   /* 40 bit BCH, for i.MX6UL(L) */
+   encode_bch_ecc(fcb_raw_page + 32, fcb, 40);
+   } else {
+   memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
+   encode_hamming_13_8(fcb_raw_page + 12,
+   fcb_raw_page + 12 + 512, 512);
+   }
/*
 * Set the first and second byte of OOB data to 0xFF, not 0x00. These
 * bytes are used as the Manufacturers Bad Block Marker (MBBM). Since
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v6 1/3] i.MX6: nand: add nandbcb command for imx

2019-06-28 Thread Parthiban Nallathambi 
Hello Shyam,

On 6/18/19 9:54 AM, Shyam Saini wrote:
> Hi Igor,
> 
>> Hi Shyam,
>>
>> On Fri, Jun 14, 2019 at 10:37 AM Shyam Saini
>>  wrote:
>>>
>>> Writing/updating boot image in nand device is not
>>> straight forward in i.MX6 platform and it requires
>>> boot control block(BCB) to be configured.
>>>
>>> It becomes difficult to use uboot 'nand' command to
>>> write BCB since it requires platform specific attributes
>>> need to be taken care of.
>>>
>>> It is even difficult to use existing msx-nand.c driver by
>>> incorporating BCB attributes like mxs_dma_desc does
>>> because it requires change in mtd and nand command.
>>>
>>> So, cmd_nandbcb implemented in arch/arm/mach-imx
>>>
>>> BCB contains two data structures, Firmware Configuration Block(FCB)
>>> and Discovered Bad Block Table(DBBT). FCB has nand timings,
>>> DBBT search area, page address of firmware.
>>>
>>> On summary, nandbcb update will
>>> - erase the entire partition
>>> - create BCB by creating 2 FCB/DBBT block followed by
>>>   1 FW block based on partition size and erasesize.
>>> - fill FCB/DBBT structures
>>> - write FW/SPL on FW1
>>> - write FCB/DBBT in first 2 blocks
>>>
>>> for nand boot, up on reset bootrom look for FCB structure in
>>> first block's if FCB found the nand timings are loaded for
>>> further reads. once FCB read done, DTTB will load and finally
>>> firmware will be loaded which is boot image.
>>>
>>> Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage
>>> information.
>>>
>>> Reviewed-by: Stefano Babic 
>>> Signed-off-by: Jagan Teki 
>>> Signed-off-by: Sergey Kubushyn 
>>> Signed-off-by: Shyam Saini 
>>> ---
>>> Changes for v6:
>>> - Consolidate v5 patch 1 and patch 2 into one single patch
>>> - Make separate docs patch out of v5 patch 1
>>>
>>> Changes for v5:
>>> - Move mxs_nand.h file from drivers/mtd/nand/raw/ to include/ directory so
>>>   that it can be used by both drivers/ and arch/
>>> - Fix command steps output in docs
>>>
>>> Changes for v4:
>>> - Remove obselete apis and use bch_geometry structure for calculating
>>>   ecc level, bad block start bit and bad block byte
>>> - Write firmware only once
>>> - Shorten variable names
>>> - Update commit message
>>> - Update docs as per current patch
>>> - Fix checkpatch warnings
>>>
>>> Changes for v3:
>>> - Fixed multi-line comments
>>> - Better error handling for failed allocations
>>>
>>> Changes for v2:
>>> - Fixed commit message notes
>>> - Updated proper commit message
>>> - Update doc/README.imx6 with NAND boot details
>>> - Fixed long length variable names.
>>> - Fixed Gigantic variable name.
>>> - NULL checks for kzalloc
>>> - Move Kconfig option in separate patch
>>> - Fixed checkpatch warninigs
>>>
>>>  arch/arm/include/asm/mach-imx/imx-nandbcb.h  | 111 
>>>  arch/arm/mach-imx/Kconfig|  11 +
>>>  arch/arm/mach-imx/Makefile   |   1 +
>>>  arch/arm/mach-imx/cmd_nandbcb.c  | 369 
>>> +++
>>>  drivers/mtd/nand/raw/mxs_nand.c  |   2 +-
>>>  drivers/mtd/nand/raw/mxs_nand_dt.c   |   2 +-
>>>  drivers/mtd/nand/raw/mxs_nand_spl.c  |   2 +-
>>>  {drivers/mtd/nand/raw => include}/mxs_nand.h |   0
>>>  8 files changed, 495 insertions(+), 3 deletions(-)
>>>  create mode 100644 arch/arm/include/asm/mach-imx/imx-nandbcb.h
>>>  create mode 100644 arch/arm/mach-imx/cmd_nandbcb.c
>>>  rename {drivers/mtd/nand/raw => include}/mxs_nand.h (100%)
>>>
>>> diff --git a/arch/arm/include/asm/mach-imx/imx-nandbcb.h 
>>> b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
>>> new file mode 100644
>>> index 00..033659a038
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
>>> @@ -0,0 +1,111 @@
>>> +/*
>>> + * Copyright (C) 2017 Jagan Teki 
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +#ifndef _IMX_NAND_BCB_H_
>>> +#define _IMX_NAND_BCB_H_
>>> +
>>> +#define FCB_FINGERPRINT0x20424346  /* 'FCB' */
>>> +#define FCB_VERSION_1  0x0100
>>> +
>>> +#define DBBT_FINGERPRINT2  0x54424244  /* 'DBBT' */
>>> +#define DBBT_VERSION_1 0x0100
>>> +
>>> +struct dbbt_block {
>>> +   u32 checksum;   /* reserved on i.MX6 */
>>> +   u32 fingerprint;
>>> +   u32 version;
>>> +   u32 numberbb;   /* reserved on i.MX6 */
>>> +   u32 dbbtpages;
>>> +};
>>> +
>>> +struct fcb_block {
>>> +   u32 checksum;   /* First fingerprint in first byte */
>>> +   u32 fingerprint;/* 2nd fingerprint at byte 4 */
>>> +   u32 version;/* 3rd fingerprint at byte 8 */
>>> +   u8 datasetup;
>>> +   u8 datahold;
>>> +   u8 addr_setup;
>>> +   u8 dsample_time;
>>> +
>>> +   /* These are for application use only and not for ROM. */
>>> +   u8 nandtiming;
>>> +   u8 rea;
>>> +   u8 rloh;
>>> +   u8 rhoh;
>>> +   u32 pagesize;   /* 2048 for 2K pages, 4096 for 4K pages */
>>> +   u32 oob_pagesize;

[U-Boot] [PATCH v7] ARM: am335x: Add phyCORE AM335x R2 support

2019-06-03 Thread Parthiban Nallathambi 
From: Niel Fourie 

Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
phyBOARD-Wega AM335x.

CPU  : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-WEGA
DRAM:  256 MiB
NAND:  256 MiB
MMC:   OMAP SD/MMC: 0
eth0: ethernet@4a10

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART
 - USB (host)

Device trees were taken from Linux mainline:
commit 37624b58542f ("Linux 5.1-rc7")

Signed-off-by: Niel Fourie 
Signed-off-by: Parthiban Nallathambi 
Reviewed-by: Heiko Schocher 
Reviewed-by: Tom Rini 
Tested-by: Marek Vasut 
---

Notes:
Notes:
Changes for v7:
- commands dhcp, ping added by default
- dm-pre-reloc added for i2c0
- console changed to ttyO0 and other nit picks fix

Changes for v6:
- RAM initialisation reworked to detect available memory
- Remove memory section from am335x-wega-rdk-u-boot.dtsi

Changes for v5:
- Revert proposed moving of sections to am33xx-u-boot.dtsi
- Remove redundant/incorrect lines from am33xx-u-boot.dtsi
- Add missing changelog

Changes for v4:
- Propose abstracting common sections to am33xx-u-boot.dtsi
- Remove dead Falcon mode code
- Remove non-DM I2C support for TPS65910 I2C

Changes for v3:
- Added kernel revision of upstream Linux dtsi files
- Place TARGET_PHYCORE_AM335X_R2 alphabetically in Kconfig
- Rework TPS65910 I2C init code
- Remove non-DM USB board macros
- Minor tweaks

Changes for v2:
- Remove formatting changes to upstream Linux dtsi files
- Remove incorrectly added MACH_TYPE
- Rename board from phycore_pcl060 to phycore_am335x_r2
- Implement selecting memory size from device tree
- Remove non-DM Ethernet board code
- General clean-up

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/am335x-phycore-som.dtsi   | 322 +
 arch/arm/dts/am335x-wega-rdk-u-boot.dtsi   |  31 ++
 arch/arm/dts/am335x-wega-rdk.dts   |  23 ++
 arch/arm/dts/am335x-wega.dtsi  | 230 +++
 arch/arm/mach-omap2/Kconfig|   1 +
 arch/arm/mach-omap2/am33xx/Kconfig |   7 +
 board/phytec/phycore_am335x_r2/Kconfig |  15 +
 board/phytec/phycore_am335x_r2/MAINTAINERS |   7 +
 board/phytec/phycore_am335x_r2/Makefile|  11 +
 board/phytec/phycore_am335x_r2/board.c | 260 +
 board/phytec/phycore_am335x_r2/board.h |  24 ++
 board/phytec/phycore_am335x_r2/mux.c   | 117 
 configs/phycore-am335x-r2-wega_defconfig   |  81 ++
 include/configs/phycore_am335x_r2.h| 130 +
 15 files changed, 1261 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/am335x-phycore-som.dtsi
 create mode 100644 arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
 create mode 100644 arch/arm/dts/am335x-wega-rdk.dts
 create mode 100644 arch/arm/dts/am335x-wega.dtsi
 create mode 100644 board/phytec/phycore_am335x_r2/Kconfig
 create mode 100644 board/phytec/phycore_am335x_r2/MAINTAINERS
 create mode 100644 board/phytec/phycore_am335x_r2/Makefile
 create mode 100644 board/phytec/phycore_am335x_r2/board.c
 create mode 100644 board/phytec/phycore_am335x_r2/board.h
 create mode 100644 board/phytec/phycore_am335x_r2/mux.c
 create mode 100644 configs/phycore-am335x-r2-wega_defconfig
 create mode 100644 include/configs/phycore_am335x_r2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e0c54bfa76..ceb7a32cf6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -287,7 +287,8 @@ dtb-$(CONFIG_AM33XX) += \
am335x-chiliboard.dtb \
am335x-sl50.dtb \
am335x-base0033.dtb \
-   am335x-guardian.dtb
+   am335x-guardian.dtb \
+   am335x-wega-rdk.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb\
am43x-epos-evm.dtb \
am437x-idk-evm.dtb \
diff --git a/arch/arm/dts/am335x-phycore-som.dtsi 
b/arch/arm/dts/am335x-phycore-som.dtsi
new file mode 100644
index 00..8d7c19e5e1
--- /dev/null
+++ b/arch/arm/dts/am335x-phycore-som.dtsi
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am33xx.dtsi"
+#include 
+
+/ {
+   model = "Phytec AM335x phyCORE";
+   compatible = "phytec,am335x-phycore-som", "ti,am33xx";
+
+   aliases {
+   rtc0 = &i2c_rtc;
+   rtc1 = &rtc;
+   };
+
+   cpus {
+   cpu@0 {
+   cpu0-supply = <&vdd1_reg>;
+   };
+   };
+
+   memory@8000 {
+   device_type

Re: [U-Boot] [PATCH v2] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-26 Thread Parthiban Nallathambi 

Ping on this patch.

Thanks,
Parthiban N

On 4/10/19 4:35 PM, Parthiban Nallathambi wrote:

Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063)
with eMMC on SoM.

CPU:   Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 38C
Reset cause: POR
Model: Phytec phyBOARD-i.MX6ULL-Segin SBC
Board: PHYTEC phyCORE-i.MX6ULL
DRAM:  256 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:serial@0202
Out:   serial@0202
Err:   serial@0202
Net:   FEC0

Working:
  - Eth0
  - i2C
  - MMC/SD
  - eMMC
  - UART (1 & 5)
  - USB (host & otg)

Signed-off-by: Parthiban Nallathambi 
---

Notes:
 Changes in v2:
 - disabled gpmi and usdhc by default in pcl063-common.dtsi. Board
 dts enables it based on the flash storage which is present.
 - added CONFIG_SYS_FSL_USDHC_NUM in pcl063.h

  arch/arm/dts/Makefile |   1 +
  arch/arm/dts/imx6ul-phycore-segin.dts |   7 +-
  arch/arm/dts/imx6ull-phycore-segin.dts|  70 +++
  ...{imx6ul-pcl063.dtsi => pcl063-common.dtsi} |  33 -
  arch/arm/mach-imx/mx6/Kconfig |  12 ++
  board/phytec/pcl063/Kconfig   |  13 ++
  board/phytec/pcl063/MAINTAINERS   |   6 +-
  board/phytec/pcl063/pcl063.c  |   5 +-
  board/phytec/pcl063/spl.c |  76 +++-
  configs/phycore_pcl063_ull_defconfig  |  54 
  include/configs/pcl063.h  |   2 +
  include/configs/pcl063_ull.h  | 117 ++
  12 files changed, 384 insertions(+), 12 deletions(-)
  create mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
  rename arch/arm/dts/{imx6ul-pcl063.dtsi => pcl063-common.dtsi} (83%)
  create mode 100644 configs/phycore_pcl063_ull_defconfig
  create mode 100644 include/configs/pcl063_ull.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 930b7e03db..8459acb344 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -539,6 +539,7 @@ dtb-$(CONFIG_MX6UL) += \
  dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+   imx6ull-phycore-segin.dtb
  
  dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \

imx7d-sdb-qspi.dtb \
diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts 
b/arch/arm/dts/imx6ul-phycore-segin.dts
index a46012e2b4..7d68bf8430 100644
--- a/arch/arm/dts/imx6ul-phycore-segin.dts
+++ b/arch/arm/dts/imx6ul-phycore-segin.dts
@@ -16,7 +16,8 @@
  
  /dts-v1/;
  
-#include "imx6ul-pcl063.dtsi"

+#include "imx6ul.dtsi"
+#include "pcl063-common.dtsi"
  
  / {

model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
@@ -24,6 +25,10 @@
 "fsl,imx6ul";
  };
  
+&gpmi {

+   status = "okay";
+};
+
  &i2c1 {
i2c_rtc: rtc@68 {
compatible = "microcrystal,rv4162";
diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts 
b/arch/arm/dts/imx6ull-phycore-segin.dts
new file mode 100644
index 00..6df3ad2e4a
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phycore-segin.dts
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi 
+ */
+
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "pcl063-common.dtsi"
+
+/ {
+   model = "Phytec phyBOARD-i.MX6ULL-Segin SBC";
+   compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063",
+"fsl,imx6ull";
+};
+
+&i2c1 {
+   i2c_rtc: rtc@68 {
+   compatible = "microcrystal,rv4162";
+   reg = <0x68>;
+   status = "okay";
+   };
+};
+
+&uart5 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart5>;
+   uart-has-rtscts;
+   status = "okay";
+};
+
+&usdhc2 {
+   status = "okay";
+};
+
+&usbotg1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usb_otg1_id>;
+   dr_mode = "otg";
+   srp-disable;
+   hnp-disable;
+   adp-disable;
+   status = "okay";
+};
+
+&usbotg2 {
+   dr_mode = "host";
+   disable-over-current;
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl-names = "default";
+
+   pinctrl_uart5: uart5grp {
+   fsl,pins = <
+   MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
+   MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
+   MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
+   MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
+   >;
+   };
+
+   pinctrl_usb_otg1_id: usbotg1idgrp {
+   fsl,pins = <
+   MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID0x17059
+

Re: [U-Boot] [PATCH] phycore-pcl060: U-boot support for Phytec phyCORE PCL060

2019-04-19 Thread Parthiban Nallathambi 
Hello Marek,

On 4/19/19 3:35 PM, Marek Vasut wrote:
> On 4/19/19 3:18 PM, Parthiban Nallathambi wrote:
> 
> Hi,
> 
> [...]
> 
>>>> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
>>>> index d29f1ca0b5..9336439340 100644
>>>> --- a/arch/arm/mach-omap2/Kconfig
>>>> +++ b/arch/arm/mach-omap2/Kconfig
>>>> @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig"
>>>>  source "board/ti/am335x/Kconfig"
>>>>  source "board/compulab/cm_t335/Kconfig"
>>>>  source "board/compulab/cm_t43/Kconfig"
>>>> +source "board/phytec/phycore_pcl060/Kconfig"
>>>
>>> Here [1] it says the name of the SoM is PCM-060 , what is PCL-060 ?
>>>
>>> [1]
>>> https://www.phytec.eu/product-eu/system-on-modules/phycore-am335x-download/
>>>  [...]
>>
>> This differs only by the connector. PCM variants are pluggable and PCL 
>> variants
>> are direct soliderable to the carrier board.
>>
>> Copied from [1]:
>> The PCL-060 System On Module is a connector-less, BGA style variant of the
>> PCM-060/phyCORE-AM335x R2 SOM. Unlike traditional Phytec SOM products that 
>> support
>> high density connectors, the PCL-060 SOM is directly soldered down to the
>> phyBOARD-Wega AM335x using Phytec's Direct Solder Connect technology (DSC). 
>> This
>> solution offers an ultra-low cost Single Board Computer for the AM335x 
>> processor, while
>> maintaining most of the advantages of the SOM concept.
>>
>> [1] 
>> https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-845e_1.pdf
> 
> Ah damn, this looks like a consistency problem is coming up. We have
> multiple PCM* SoMs in U-Boot, one PCL* SoM and now another PCL/PCM SoM.
> But the PCL063 isn't even manufactured in variant with connectors, so I
> guess we can ignore that one.
> 
> I wonder whether we should stick to PCM* for all of the Phytec SoMs for
> consistency sake and document that PCL060 is also supported or maybe
> there's a better way ?

Does PCX/PCx makes sense? But we have the same problem with variscite [1] SoM's
(either SODIMM or solderable).

[1] https://lists.denx.de/pipermail/u-boot/2019-April/365667.html

> 
> [...]
> 

-- 
Thanks,
Parthiban N

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-22 Fax: (+49)-8142-66989-80 Email: p...@denx.de
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] phycore-pcl060: U-boot support for Phytec phyCORE PCL060

2019-04-19 Thread Parthiban Nallathambi 
Hello Marek,

On 4/19/19 11:47 AM, Marek Vasut wrote:
> On 4/18/19 5:01 PM, Niel Fourie wrote:
>> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
>> phyBOARD-Wega AM335x.
>>
>> CPU  : AM335X-GP rev 2.1
>> Model: Phytec AM335x phyBOARD-WEGA
>> DRAM:  256 MiB
>> NAND:  256 MiB
>> MMC:   OMAP SD/MMC: 0
>> eth0: ethernet@4a10
>>
>> Working:
>>  - Eth0
>>  - i2C
>>  - MMC/SD
>>  - NAND
>>  - UART
>>  - USB (host)
>>
>> Signed-off-by: Niel Fourie 
>> ---
>>  arch/arm/dts/Makefile|   3 +-
>>  arch/arm/dts/am335x-phycore-som.dtsi | 327 ++
>>  arch/arm/dts/am335x-wega-rdk-u-boot.dtsi |  35 +++
>>  arch/arm/dts/am335x-wega-rdk.dts |  23 ++
>>  arch/arm/dts/am335x-wega.dtsi| 231 +++
> 
> The DTs come from Linux kernel, but which version of Linux ?
> Which exact commit ? Did you modify them in any way ?
> 
> [...]
> 
>> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
>> index d29f1ca0b5..9336439340 100644
>> --- a/arch/arm/mach-omap2/Kconfig
>> +++ b/arch/arm/mach-omap2/Kconfig
>> @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig"
>>  source "board/ti/am335x/Kconfig"
>>  source "board/compulab/cm_t335/Kconfig"
>>  source "board/compulab/cm_t43/Kconfig"
>> +source "board/phytec/phycore_pcl060/Kconfig"
> 
> Here [1] it says the name of the SoM is PCM-060 , what is PCL-060 ?
> 
> [1]
> https://www.phytec.eu/product-eu/system-on-modules/phycore-am335x-download/
>  [...]

This differs only by the connector. PCM variants are pluggable and PCL variants
are direct soliderable to the carrier board.

Copied from [1]:
The PCL-060 System On Module is a connector-less, BGA style variant of the
PCM-060/phyCORE-AM335x R2 SOM. Unlike traditional Phytec SOM products that 
support
high density connectors, the PCL-060 SOM is directly soldered down to the
phyBOARD-Wega AM335x using Phytec's Direct Solder Connect technology (DSC). This
solution offers an ultra-low cost Single Board Computer for the AM335x 
processor, while
maintaining most of the advantages of the SOM concept.

[1] https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-845e_1.pdf

Thanks,
Parthiban N

> 
>> diff --git a/board/phytec/phycore_pcl060/Kconfig 
>> b/board/phytec/phycore_pcl060/Kconfig
>> new file mode 100644
>> index 00..bdd1a9b6e0
>> --- /dev/null
>> +++ b/board/phytec/phycore_pcl060/Kconfig
>> @@ -0,0 +1,19 @@
>> +if TARGET_PCL060
>> +
>> +config SYS_BOARD
>> +default "phycore_pcl060"
>> +
>> +config SYS_VENDOR
>> +default "phytec"
>> +
>> +config SYS_SOC
>> +default "am33xx"
>> +
>> +config SYS_CONFIG_NAME
>> +default "phycore_pcl060"
>> +
>> +config PCL060_DDR_SIZE
>> +int "DDR size (in MiB) of Phycore PCL060 module"
>> +default 256
> 
> DRAM size should come from DT, we don't need another custom config
> option. Look at fdtdec_setup_mem_size_base() and
> fdtdec_setup_memory_banksize().
> 
> [...]
> 
>> diff --git a/board/phytec/phycore_pcl060/board.c 
>> b/board/phytec/phycore_pcl060/board.c
>> new file mode 100644
>> index 00..01fe13e959
>> --- /dev/null
>> +++ b/board/phytec/phycore_pcl060/board.c
>> @@ -0,0 +1,340 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * board.c
>> + *
>> + * Board functions for Phytec phyCORE-AM335x R2 (pcl060) based boards
>> + *
>> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
>> + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
>> + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
>> + * Copyright (C) 2019 DENX Software Engineering GmbH
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include "board.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
>> +
>> +#ifdef CONFIG_SPL_BUILD
>> +
>> +#ifdef CONFIG_SPL_OS_BOOT
> 
> #if CONFIG_IS_ENABLED(OS_BOOT)
> 
>> +int spl_start_uboot(void)
>> +{
>> +return 1;
>> +}
>> +#endif
>> +/* DDR RAM defines */
>> +#define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */
>> +
>> +#define OSC (V_OSCK / 100)
>> +const struct dpll_params dpll_ddr = {
>> +DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
>> +
>> +const struct dpll_params *get_dpll_ddr_params(void)
>> +{
>> +return &dpll_ddr;
>> +}
>> +
>> +const struct ctrl_ioregs ioregs = {
>> +.cm0ioctl   = 0x18B,
>> +.cm1ioctl   = 0x18B,
>> +.cm2ioctl   = 0x18B,
>> +.dt0ioctl   = 0x18B,
>> +.dt1ioctl   = 0x18B,
>> +};
>> +
>> +static const struct cmd_control ddr3_cmd_ctrl_data = {
>> +.cmd0csratio = 0x80,
>> +.cmd0iclkout = 0x0,
>> +
>> +.cmd1csratio = 0x80,
>> +.cmd1i

Re: [U-Boot] [PATCH] imx: Add variscite DART-6UL Evaluation Kit

2019-04-18 Thread Parthiban Nallathambi 

Hello Peng,

On 4/18/19 2:50 AM, Peng Fan wrote:





Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL
iMX6ULL SoM.

CPU:   Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 43C
Reset cause: POR
Model: Variscite DART-6UL Evaluation Kit
Board: Variscite DART-6UL Evaluation Kit
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:serial@0202
Out:   serial@0202
Err:   serial@0202
Net:   FEC0

Working:
  - Eth0
  - i2c
  - MMC/SD
  - eMMC
  - USB host
  - UART 1

Note: LCDIF porting needs DM_VIDEO
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.d
enx.de%2Fpipermail%2Fu-boot%2F2019-April%2F365506.html&data=02
%7C01%7Cpeng.fan%40nxp.com%7Ced2e2a78aa28409c4c1c08d6c380a738
%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636911354661076
012&sdata=meF0d06pEsGDBXW83kDMr10Qu%2FafP76xBhdzFCzp8VY%
3D&reserved=0

Signed-off-by: Parthiban Nallathambi 
---
  arch/arm/Kconfig |   1 +
  arch/arm/dts/Makefile|   1 +
  arch/arm/dts/imx6ull-dart-6ul.dts|  39 
  arch/arm/dts/imx6ull-dart-6ul.dtsi   | 261
+++
  arch/arm/mach-imx/mx6/Kconfig|  12 ++
  board/variscite/dart_6ul/Kconfig |  12 ++
  board/variscite/dart_6ul/MAINTAINERS |   8 +
  board/variscite/dart_6ul/Makefile|   4 +
  board/variscite/dart_6ul/README  |  41 +
  board/variscite/dart_6ul/dart_6ul.c  | 228 +++
  board/variscite/dart_6ul/spl.c   | 215 ++
  configs/variscite_dart6ul_defconfig  |  55 ++
  include/configs/dart_6ul.h   | 131 ++
  13 files changed, 1008 insertions(+)
  create mode 100644 arch/arm/dts/imx6ull-dart-6ul.dts  create mode
100644 arch/arm/dts/imx6ull-dart-6ul.dtsi
  create mode 100644 board/variscite/dart_6ul/Kconfig  create mode
100644 board/variscite/dart_6ul/MAINTAINERS
  create mode 100644 board/variscite/dart_6ul/Makefile  create mode
100644 board/variscite/dart_6ul/README  create mode 100644
board/variscite/dart_6ul/dart_6ul.c
  create mode 100644 board/variscite/dart_6ul/spl.c  create mode 100644
configs/variscite_dart6ul_defconfig
  create mode 100644 include/configs/dart_6ul.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index
4640f3b3bd..c20866c86a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1635,6 +1635,7 @@ source "board/tcl/sl50/Kconfig"
  source "board/ucRobotics/bubblegum_96/Kconfig"
  source "board/birdland/bav335x/Kconfig"
  source "board/toradex/colibri_pxa270/Kconfig"
+source "board/variscite/dart_6ul/Kconfig"
  source "board/vscom/baltos/Kconfig"
  source "board/woodburn/Kconfig"
  source "board/xilinx/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
0aee8dfde0..6fb545dc9f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -549,6 +549,7 @@ dtb-$(CONFIG_MX6UL) += \
  dtb-$(CONFIG_MX6ULL) += \
 imx6ull-14x14-evk.dtb \
 imx6ull-colibri.dtb \
+   imx6ull-dart-6ul.dtb

  dtb-$(CONFIG_ARCH_MX6) += \
 imx6-colibri.dtb
diff --git a/arch/arm/dts/imx6ull-dart-6ul.dts
b/arch/arm/dts/imx6ull-dart-6ul.dts
new file mode 100644
index 00..4cab1a048b
--- /dev/null
+++ b/arch/arm/dts/imx6ull-dart-6ul.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi   */
+
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "imx6ull-dart-6ul.dtsi"
+
+/ {
+   model = "Variscite DART-6UL Evaluation Kit";
+   compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull"; };
+
+&usdhc2 {
+   status = "okay";
+};
+
+&usbotg1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usb_otg1_id>;
+   dr_mode = "otg";
+   srp-disable;
+   hnp-disable;
+   adp-disable;
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl-names = "default";
+
+   pinctrl_usb_otg1_id: usbotg1idgrp {
+   fsl,pins = <
+   MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID
0x17059
+   >;
+   };
+
+};
diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi
b/arch/arm/dts/imx6ull-dart-6ul.dtsi
new file mode 100644
index 00..e96669f493
--- /dev/null
+++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi   */
+
+/ {
+   model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
+   compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
+
+   memory {
+   reg = <0x8000 0x2000>;
+   };
+
+   chosen {
+   stdout-path = &uart1;
+   };
+};
+
+&fec1 {
+   pinctrl-names = "

[U-Boot] [PATCH] imx: Add variscite DART-6UL Evaluation Kit

2019-04-17 Thread Parthiban Nallathambi 
Port for the DART-6UL Evaluation Kit SBC. Based on the variscite
DART-6UL iMX6ULL SoM.

CPU:   Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 43C
Reset cause: POR
Model: Variscite DART-6UL Evaluation Kit
Board: Variscite DART-6UL Evaluation Kit
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:serial@0202
Out:   serial@0202
Err:   serial@0202
Net:   FEC0

Working:
 - Eth0
 - i2c
 - MMC/SD
 - eMMC
 - USB host
 - UART 1

Note: LCDIF porting needs DM_VIDEO
https://lists.denx.de/pipermail/u-boot/2019-April/365506.html

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/Kconfig |   1 +
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/imx6ull-dart-6ul.dts|  39 
 arch/arm/dts/imx6ull-dart-6ul.dtsi   | 261 +++
 arch/arm/mach-imx/mx6/Kconfig|  12 ++
 board/variscite/dart_6ul/Kconfig |  12 ++
 board/variscite/dart_6ul/MAINTAINERS |   8 +
 board/variscite/dart_6ul/Makefile|   4 +
 board/variscite/dart_6ul/README  |  41 +
 board/variscite/dart_6ul/dart_6ul.c  | 228 +++
 board/variscite/dart_6ul/spl.c   | 215 ++
 configs/variscite_dart6ul_defconfig  |  55 ++
 include/configs/dart_6ul.h   | 131 ++
 13 files changed, 1008 insertions(+)
 create mode 100644 arch/arm/dts/imx6ull-dart-6ul.dts
 create mode 100644 arch/arm/dts/imx6ull-dart-6ul.dtsi
 create mode 100644 board/variscite/dart_6ul/Kconfig
 create mode 100644 board/variscite/dart_6ul/MAINTAINERS
 create mode 100644 board/variscite/dart_6ul/Makefile
 create mode 100644 board/variscite/dart_6ul/README
 create mode 100644 board/variscite/dart_6ul/dart_6ul.c
 create mode 100644 board/variscite/dart_6ul/spl.c
 create mode 100644 configs/variscite_dart6ul_defconfig
 create mode 100644 include/configs/dart_6ul.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4640f3b3bd..c20866c86a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1635,6 +1635,7 @@ source "board/tcl/sl50/Kconfig"
 source "board/ucRobotics/bubblegum_96/Kconfig"
 source "board/birdland/bav335x/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
+source "board/variscite/dart_6ul/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/xilinx/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0aee8dfde0..6fb545dc9f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -549,6 +549,7 @@ dtb-$(CONFIG_MX6UL) += \
 dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+   imx6ull-dart-6ul.dtb
 
 dtb-$(CONFIG_ARCH_MX6) += \
imx6-colibri.dtb
diff --git a/arch/arm/dts/imx6ull-dart-6ul.dts 
b/arch/arm/dts/imx6ull-dart-6ul.dts
new file mode 100644
index 00..4cab1a048b
--- /dev/null
+++ b/arch/arm/dts/imx6ull-dart-6ul.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi 
+ */
+
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "imx6ull-dart-6ul.dtsi"
+
+/ {
+   model = "Variscite DART-6UL Evaluation Kit";
+   compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
+};
+
+&usdhc2 {
+   status = "okay";
+};
+
+&usbotg1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usb_otg1_id>;
+   dr_mode = "otg";
+   srp-disable;
+   hnp-disable;
+   adp-disable;
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl-names = "default";
+
+   pinctrl_usb_otg1_id: usbotg1idgrp {
+   fsl,pins = <
+   MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID0x17059
+   >;
+   };
+
+};
diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi 
b/arch/arm/dts/imx6ull-dart-6ul.dtsi
new file mode 100644
index 00..e96669f493
--- /dev/null
+++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi 
+ */
+
+/ {
+   model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
+   compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
+
+   memory {
+   reg = <0x8000 0x2000>;
+   };
+
+   chosen {
+   stdout-path = &uart1;
+   };
+};
+
+&fec1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_enet1>;
+   phy-mode = "rmii";
+   phy-handle = <ðphy0>;
+   status = "okay";
+
+   mdio1: mdio1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethphy0: ethernet-phy@1 {
+   reg = <1>;
+   mi

[U-Boot] [PATCH v2] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-10 Thread Parthiban Nallathambi 
Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063)
with eMMC on SoM.

CPU:   Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 38C
Reset cause: POR
Model: Phytec phyBOARD-i.MX6ULL-Segin SBC
Board: PHYTEC phyCORE-i.MX6ULL
DRAM:  256 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:serial@0202
Out:   serial@0202
Err:   serial@0202
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - eMMC
 - UART (1 & 5)
 - USB (host & otg)

Signed-off-by: Parthiban Nallathambi 
---

Notes:
Changes in v2:
- disabled gpmi and usdhc by default in pcl063-common.dtsi. Board
dts enables it based on the flash storage which is present.
- added CONFIG_SYS_FSL_USDHC_NUM in pcl063.h

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/imx6ul-phycore-segin.dts |   7 +-
 arch/arm/dts/imx6ull-phycore-segin.dts|  70 +++
 ...{imx6ul-pcl063.dtsi => pcl063-common.dtsi} |  33 -
 arch/arm/mach-imx/mx6/Kconfig |  12 ++
 board/phytec/pcl063/Kconfig   |  13 ++
 board/phytec/pcl063/MAINTAINERS   |   6 +-
 board/phytec/pcl063/pcl063.c  |   5 +-
 board/phytec/pcl063/spl.c |  76 +++-
 configs/phycore_pcl063_ull_defconfig  |  54 
 include/configs/pcl063.h  |   2 +
 include/configs/pcl063_ull.h  | 117 ++
 12 files changed, 384 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
 rename arch/arm/dts/{imx6ul-pcl063.dtsi => pcl063-common.dtsi} (83%)
 create mode 100644 configs/phycore_pcl063_ull_defconfig
 create mode 100644 include/configs/pcl063_ull.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 930b7e03db..8459acb344 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -539,6 +539,7 @@ dtb-$(CONFIG_MX6UL) += \
 dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+   imx6ull-phycore-segin.dtb
 
 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts 
b/arch/arm/dts/imx6ul-phycore-segin.dts
index a46012e2b4..7d68bf8430 100644
--- a/arch/arm/dts/imx6ul-phycore-segin.dts
+++ b/arch/arm/dts/imx6ul-phycore-segin.dts
@@ -16,7 +16,8 @@
 
 /dts-v1/;
 
-#include "imx6ul-pcl063.dtsi"
+#include "imx6ul.dtsi"
+#include "pcl063-common.dtsi"
 
 / {
model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
@@ -24,6 +25,10 @@
 "fsl,imx6ul";
 };
 
+&gpmi {
+   status = "okay";
+};
+
 &i2c1 {
i2c_rtc: rtc@68 {
compatible = "microcrystal,rv4162";
diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts 
b/arch/arm/dts/imx6ull-phycore-segin.dts
new file mode 100644
index 00..6df3ad2e4a
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phycore-segin.dts
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi 
+ */
+
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "pcl063-common.dtsi"
+
+/ {
+   model = "Phytec phyBOARD-i.MX6ULL-Segin SBC";
+   compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063",
+"fsl,imx6ull";
+};
+
+&i2c1 {
+   i2c_rtc: rtc@68 {
+   compatible = "microcrystal,rv4162";
+   reg = <0x68>;
+   status = "okay";
+   };
+};
+
+&uart5 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart5>;
+   uart-has-rtscts;
+   status = "okay";
+};
+
+&usdhc2 {
+   status = "okay";
+};
+
+&usbotg1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usb_otg1_id>;
+   dr_mode = "otg";
+   srp-disable;
+   hnp-disable;
+   adp-disable;
+   status = "okay";
+};
+
+&usbotg2 {
+   dr_mode = "host";
+   disable-over-current;
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl-names = "default";
+
+   pinctrl_uart5: uart5grp {
+   fsl,pins = <
+   MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
+   MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
+   MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
+   MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
+   >;
+   };
+
+   pinctrl_usb_otg1_id: usbotg1idgrp {
+   fsl,pins = <
+   MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID0x17059
+   >;
+   };
+
+};
diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/pcl063-common.dtsi
similarity index 83%
rename

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-10 Thread Parthiban Nallathambi 

Hello Wadim,

Thanks for sharing the details.

On 4/10/19 10:35 AM, Wadim Egorov wrote:

Martyn,

On 09.04.19 12:46, Martyn Welch wrote:

On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:

Hello Martyn,

On 4/9/19 10:49 AM, Martyn Welch wrote:

On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:

Hello Martyn,

On 4/8/19 7:45 PM, Martyn Welch wrote:

On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:

diff --git a/board/phytec/pcl063/spl.c
b/board/phytec/pcl063/spl.c
index b93cd493f2..73a774645d 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -13,6 +13,7 @@
   #include 
   #include 
   #include 
+#include 
   #include 
   
   /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x

16 x 8
->
256MiB */
@@ -117,11 +118,32 @@ static iomux_v3_cfg_t const
usdhc1_pads[] =
{
MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
   };
   
+#ifndef CONFIG_NAND_MXS

+static iomux_v3_cfg_t const usdhc2_pads[] = {
+   MX6_PAD_NAND_RE_B__USDHC2_CLK|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_WE_B__USDHC2_CMD|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+

Umm, these pins are already used a few lines up for the NAND,
via
gpmi:

I understand. But pcl063 can't co-exit with NAND and eMMC
together. I
comes
either with eMMC or NAND.

Opps, sorry, just realised that I added this comment in the wrong
place. This is in relation to the following being added to
pcl063-common.dtsi:

+
+   pinctrl_usdhc2: usdhc2grp {
+   fsl,pins = <
+   MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x1
70f9
+   MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x1
00f9
+   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x1
70f9
+   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x1
70f9
+   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x1
70f9
+   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x1
70f9
+   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x1
70f9
+   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x1
70f9
+   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x1
70f9
+   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x1
70f9
+   >;
+   };

If there exists pcl063 modules that have eMMC and others that have
NAND
using the same pins, then this configuration is not common and
therefore shouldn't be in pcl063-common.dtsi. Is it dependent on
the
flavour of i.MX used? If so I'd suggest the gpmi config needs to be
pulled out into imx6ul-phycore-segin.dts and the usdhc2 config
needs to
be in imx6ull-phycore-segin.dts.

  From phytec I understand that pcl063 SoM is a common platform for
imx6UL
and imx6ULL. This can either be shipped with eMMC or NAND, but not
both.


This is correct. There are PCL-063 SOMs with eMMC or NAND. And each
PCL-063 can be a 6UL or 6ULL.





Looking a bit deeper, this seems a little odd as the product
description suggests that NAND is provided onboard and 2 SD/SDIO/MMC
connections are provided to the edge connector of the pcl063 for
expansion.

The schematic suggests the only way they could achieve eMMC onboard
would be with an eMMC that is pin compatible with the NAND they use.


eMMC is connected via usdhc2. The usdhc2 pins conflict with the gpmi pins.




Additionally, looking at the DTBs for this board in Phytec's own kernel
tree, the only use of usdhc2 that I can see is for their WLAN expansion
board[1] and I would have expected their tree to have supported such an
option if it was available (they seem to have gone to some length to
support a lot of configurations there).

Are you sure that the eMMC is provided on the pcl063 and not off board?


eMMC is on the PCL-063 and not on a carrier board.




(CCing Wadim who might be able to shed some light on this)


So there exist a possibility that phytec can provide imx6UL with eMMC
as
well. IMO, both pinmux detailing for NAND and eMMC should still
reside
in common.dtsi.


Assuming Phytec do in fact sell a pcl0063 with eMMC on board, the DTB
describes the hardware. You've said Phytec provide the board
either with eMMC *or* NAND. The device tree, as used on a specific
board, should show either the existence of NAND or eMMC.


AFAIK, the idea was to put the muxing for both flash devices in the
pcl063-som

Re: [U-Boot] [PATCH] ARM: dts: i.MX6ULL: U-Boot specific dts for u-boot, dm-spl

2019-04-09 Thread Parthiban Nallathambi 

Hi Marcel,

On 4/8/19 3:53 PM, Marcel Ziswiler wrote:

Hi Parthiban

On Sun, 2019-04-07 at 20:32 +0200, Parthiban Nallathambi wrote:

u-boot,dm-spl property is specific to U-Boot, so created one
for i.MX6ULL platforms.


What exactly makes you so sure others do want your exact configuration
thereof as well? Shouldn't you make this board specific instead like
e.g. done elsewhere [1]?


Sure, thanks for pointing it. I will move them to my board specific
files.

Thanks,
Parthiban N



[1]
https://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/dts/am335x-chiliboard-u-boot.dtsi;h=4f9d3080394be001f79731b736c5eac934c07ebf;hb=HEAD

Cheers

Marcel


Signed-off-by: Parthiban Nallathambi 
---
  arch/arm/dts/imx6ull-u-boot.dtsi | 34

  board/phytec/pcl063/MAINTAINERS  |  1 +
  2 files changed, 35 insertions(+)
  create mode 100644 arch/arm/dts/imx6ull-u-boot.dtsi

diff --git a/arch/arm/dts/imx6ull-u-boot.dtsi b/arch/arm/dts/imx6ull-
u-boot.dtsi
new file mode 100644
index 00..74ca95fa2c
--- /dev/null
+++ b/arch/arm/dts/imx6ull-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi 
+ */
+
+/ {
+   soc {
+   u-boot,dm-spl;
+   };
+};
+
+&aips1 {
+   u-boot,dm-spl;
+};
+
+&aips2 {
+   u-boot,dm-spl;
+};
+
+&aips3 {
+   u-boot,dm-spl;
+};
+
+&gpio1 {
+   u-boot,dm-spl;
+};
+
+&gpio4 {
+   u-boot,dm-spl;
+};
+
+&iomuxc {
+   u-boot,dm-spl;
+};
diff --git a/board/phytec/pcl063/MAINTAINERS
b/board/phytec/pcl063/MAINTAINERS
index 70e03cfe71..7d9978c339 100644
--- a/board/phytec/pcl063/MAINTAINERS
+++ b/board/phytec/pcl063/MAINTAINERS
@@ -3,6 +3,7 @@ M:  Martyn Welch 
  M:Parthiban Nallathambi 
  S:Maintained
  F:arch/arm/dts/imx6ul-phycore-segin.dts
+F: arch/arm/dts/imx6ull-u-boot.dtsi
  F:arch/arm/dts/imx6ull-phycore-segin.dts
  F:arch/arm/dts/pcl063-common.dtsi
  F:board/phytec/pcl063/

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-09 Thread Parthiban Nallathambi 

Hello Martyn,

On 4/9/19 12:46 PM, Martyn Welch wrote:

On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:

Hello Martyn,

On 4/9/19 10:49 AM, Martyn Welch wrote:

On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:

Hello Martyn,

On 4/8/19 7:45 PM, Martyn Welch wrote:

On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:

diff --git a/board/phytec/pcl063/spl.c
b/board/phytec/pcl063/spl.c
index b93cd493f2..73a774645d 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -13,6 +13,7 @@
   #include 
   #include 
   #include 
+#include 
   #include 
   
   /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x

16 x 8
->
256MiB */
@@ -117,11 +118,32 @@ static iomux_v3_cfg_t const
usdhc1_pads[] =
{
MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
   };
   
+#ifndef CONFIG_NAND_MXS

+static iomux_v3_cfg_t const usdhc2_pads[] = {
+   MX6_PAD_NAND_RE_B__USDHC2_CLK|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_WE_B__USDHC2_CMD|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+


Umm, these pins are already used a few lines up for the NAND,
via
gpmi:


I understand. But pcl063 can't co-exit with NAND and eMMC
together. I
comes
either with eMMC or NAND.


Opps, sorry, just realised that I added this comment in the wrong
place. This is in relation to the following being added to
pcl063-common.dtsi:

+
+   pinctrl_usdhc2: usdhc2grp {
+   fsl,pins = <
+   MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x1
70f9
+   MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x1
00f9
+   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x1
70f9
+   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x1
70f9
+   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x1
70f9
+   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x1
70f9
+   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x1
70f9
+   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x1
70f9
+   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x1
70f9
+   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x1
70f9
+   >;
+   };

If there exists pcl063 modules that have eMMC and others that have
NAND
using the same pins, then this configuration is not common and
therefore shouldn't be in pcl063-common.dtsi. Is it dependent on
the
flavour of i.MX used? If so I'd suggest the gpmi config needs to be
pulled out into imx6ul-phycore-segin.dts and the usdhc2 config
needs to
be in imx6ull-phycore-segin.dts.


  From phytec I understand that pcl063 SoM is a common platform for
imx6UL
and imx6ULL. This can either be shipped with eMMC or NAND, but not
both.



Looking a bit deeper, this seems a little odd as the product
description suggests that NAND is provided onboard and 2 SD/SDIO/MMC
connections are provided to the edge connector of the pcl063 for
expansion.

The schematic suggests the only way they could achieve eMMC onboard
would be with an eMMC that is pin compatible with the NAND they use.

Additionally, looking at the DTBs for this board in Phytec's own kernel
tree, the only use of usdhc2 that I can see is for their WLAN expansion
board[1] and I would have expected their tree to have supported such an
option if it was available (they seem to have gone to some length to
support a lot of configurations there).

Are you sure that the eMMC is provided on the pcl063 and not off board?


Yes, I have this SoM with me and the changes are tested in it already.
Pinmuxing details are based on phytec's barebox which is yet to be in
mainline [1].

Phytec already published the booting from eMMC option and configurations
which are needed in the hardware level here [2].



(CCing Wadim who might be able to shed some light on this)


So there exist a possibility that phytec can provide imx6UL with eMMC
as
well. IMO, both pinmux detailing for NAND and eMMC should still
reside
in common.dtsi.



Assuming Phytec do in fact sell a pcl0063 with eMMC on board, the DTB
describes the hardware. You've said Phytec provide the board
either with eMMC *or* NAND. The device tree, as used on a specific
board, should show either the existence of NAND or eMMC.

I suspect having both options in the common file is going to lead to
issues with the pinmuxing for one or th

Re: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-09 Thread Parthiban Nallathambi 

Hello Martyn,

On 4/9/19 10:49 AM, Martyn Welch wrote:

On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:

Hello Martyn,

On 4/8/19 7:45 PM, Martyn Welch wrote:

On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:

diff --git a/board/phytec/pcl063/spl.c
b/board/phytec/pcl063/spl.c
index b93cd493f2..73a774645d 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -13,6 +13,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  
  /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8

->
256MiB */
@@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] =
{
MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
  };
  
+#ifndef CONFIG_NAND_MXS

+static iomux_v3_cfg_t const usdhc2_pads[] = {
+   MX6_PAD_NAND_RE_B__USDHC2_CLK|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_WE_B__USDHC2_CMD|
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+


Umm, these pins are already used a few lines up for the NAND, via
gpmi:


I understand. But pcl063 can't co-exit with NAND and eMMC together. I
comes
either with eMMC or NAND.


Opps, sorry, just realised that I added this comment in the wrong
place. This is in relation to the following being added to
pcl063-common.dtsi:

+
+   pinctrl_usdhc2: usdhc2grp {
+   fsl,pins = <
+   MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+   MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+   MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+   MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+   MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+   MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+   MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+   MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+   MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+   MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+   >;
+   };

If there exists pcl063 modules that have eMMC and others that have NAND
using the same pins, then this configuration is not common and
therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the
flavour of i.MX used? If so I'd suggest the gpmi config needs to be
pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to
be in imx6ull-phycore-segin.dts.


From phytec I understand that pcl063 SoM is a common platform for imx6UL
and imx6ULL. This can either be shipped with eMMC or NAND, but not both.

So there exist a possibility that phytec can provide imx6UL with eMMC as
well. IMO, both pinmux detailing for NAND and eMMC should still reside
in common.dtsi.

Creating multiple common.dtsi based on these variants is not friendly.
So I suggest to keep these changes in common.dtsi as such and decide in
board dts whether to enable or disable usdhc1, usdhc2 explicitly.






 pinctrl_gpmi_nand: gpminandgrp {
 fsl,pins = <
 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0
b0b1
 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0
b0b1
 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B   0x0
b0b1
 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B
0x0b000
 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0
b0b1
 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B   0x0
b0b1
 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B   0x0
b0b1
 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0
b0b1
 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0
b0b1
 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0
b0b1
 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0
b0b1
 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0
b0b1
 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0
b0b1
 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0
b0b1
 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0
b0b1
 >;
 };


  static struct fsl_esdhc_cfg usdhc_cfg[] = {
{
.esdhc_base = USDHC1_BASE_ADDR,
.max_bus_width = 4,

[U-Boot] [PATCH] ARM: dts: i.MX6ULL: U-Boot specific dts for u-boot, dm-spl

2019-04-07 Thread Parthiban Nallathambi 
u-boot,dm-spl property is specific to U-Boot, so created one
for i.MX6ULL platforms.

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/dts/imx6ull-u-boot.dtsi | 34 
 board/phytec/pcl063/MAINTAINERS  |  1 +
 2 files changed, 35 insertions(+)
 create mode 100644 arch/arm/dts/imx6ull-u-boot.dtsi

diff --git a/arch/arm/dts/imx6ull-u-boot.dtsi b/arch/arm/dts/imx6ull-u-boot.dtsi
new file mode 100644
index 00..74ca95fa2c
--- /dev/null
+++ b/arch/arm/dts/imx6ull-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi 
+ */
+
+/ {
+   soc {
+   u-boot,dm-spl;
+   };
+};
+
+&aips1 {
+   u-boot,dm-spl;
+};
+
+&aips2 {
+   u-boot,dm-spl;
+};
+
+&aips3 {
+   u-boot,dm-spl;
+};
+
+&gpio1 {
+   u-boot,dm-spl;
+};
+
+&gpio4 {
+   u-boot,dm-spl;
+};
+
+&iomuxc {
+   u-boot,dm-spl;
+};
diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS
index 70e03cfe71..7d9978c339 100644
--- a/board/phytec/pcl063/MAINTAINERS
+++ b/board/phytec/pcl063/MAINTAINERS
@@ -3,6 +3,7 @@ M:  Martyn Welch 
 M:     Parthiban Nallathambi 
 S: Maintained
 F: arch/arm/dts/imx6ul-phycore-segin.dts
+F: arch/arm/dts/imx6ull-u-boot.dtsi
 F: arch/arm/dts/imx6ull-phycore-segin.dts
 F: arch/arm/dts/pcl063-common.dtsi
 F: board/phytec/pcl063/
-- 
2.17.2

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM

2019-04-07 Thread Parthiban Nallathambi 
Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063)
with eMMC on SoM.

CPU:   Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 38C
Reset cause: POR
Model: Phytec phyBOARD-i.MX6ULL-Segin SBC
Board: PHYTEC phyCORE-i.MX6ULL
DRAM:  256 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:serial@0202
Out:   serial@0202
Err:   serial@0202
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - eMMC
 - UART (1 & 5)
 - USB (host & otg)

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/imx6ul-phycore-segin.dts |   3 +-
 arch/arm/dts/imx6ull-phycore-segin.dts|  81 
 ...{imx6ul-pcl063.dtsi => pcl063-common.dtsi} |  31 -
 arch/arm/mach-imx/mx6/Kconfig |  12 ++
 board/phytec/pcl063/Kconfig   |  13 ++
 board/phytec/pcl063/MAINTAINERS   |   6 +-
 board/phytec/pcl063/pcl063.c  |   5 +-
 board/phytec/pcl063/spl.c |  76 +++-
 configs/phycore_pcl063_ull_defconfig  |  54 
 include/configs/pcl063_ull.h  | 117 ++
 11 files changed, 388 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
 rename arch/arm/dts/{imx6ul-pcl063.dtsi => pcl063-common.dtsi} (84%)
 create mode 100644 configs/phycore_pcl063_ull_defconfig
 create mode 100644 include/configs/pcl063_ull.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0e2ffdb87f..431afb915f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -539,6 +539,7 @@ dtb-$(CONFIG_MX6UL) += \
 dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+   imx6ull-phycore-segin.dtb
 
 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts 
b/arch/arm/dts/imx6ul-phycore-segin.dts
index a46012e2b4..9e6984e137 100644
--- a/arch/arm/dts/imx6ul-phycore-segin.dts
+++ b/arch/arm/dts/imx6ul-phycore-segin.dts
@@ -16,7 +16,8 @@
 
 /dts-v1/;
 
-#include "imx6ul-pcl063.dtsi"
+#include "imx6ul.dtsi"
+#include "pcl063-common.dtsi"
 
 / {
model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts 
b/arch/arm/dts/imx6ull-phycore-segin.dts
new file mode 100644
index 00..c20a867c90
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phycore-segin.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi 
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "pcl063-common.dtsi"
+
+/ {
+   model = "Phytec phyBOARD-i.MX6ULL-Segin SBC";
+   compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063",
+"fsl,imx6ull";
+};
+
+&gpmi {
+   status = "disabled";
+};
+
+&i2c1 {
+   i2c_rtc: rtc@68 {
+   compatible = "microcrystal,rv4162";
+   reg = <0x68>;
+   status = "okay";
+   };
+};
+
+&uart5 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart5>;
+   uart-has-rtscts;
+   status = "okay";
+};
+
+&usdhc2 {
+   status = "okay";
+};
+
+&usbotg1 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_usb_otg1_id>;
+   dr_mode = "otg";
+   srp-disable;
+   hnp-disable;
+   adp-disable;
+   status = "okay";
+};
+
+&usbotg2 {
+   dr_mode = "host";
+   disable-over-current;
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl-names = "default";
+
+   pinctrl_uart5: uart5grp {
+   fsl,pins = <
+   MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
+   MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
+   MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
+   MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
+   >;
+   };
+
+   pinctrl_usb_otg1_id: usbotg1idgrp {
+   fsl,pins = <
+   MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID0x17059
+   >;
+   };
+
+};
diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/pcl063-common.dtsi
similarity index 84%
rename from arch/arm/dts/imx6ul-pcl063.dtsi
rename to arch/arm/dts/pcl063-common.dtsi
index 24a6a47983..f505f62230 100644
--- a/arch/arm/dts/

Re: [U-Boot] [PATCH] imx: hab: extend hab_auth_img to calculate ivt_offset

2018-11-28 Thread Parthiban Nallathambi 

Hi,

On 11/28/18 9:19 AM, Quentin Grembert wrote:

Hello,

I did not see I still could use the old parameters. So I guess I disturb
you for nothing.


You must still be able to use the previous method with ivt_offset as
last argument to hab_auth_img.


I did not not about FIT image. I will look into it.

Thank's !
Quentin Grembert

On Wed, 28 Nov 2018 at 05:43, Heiko Schocher  wrote:


Hello Quentin,

Am 27.11.2018 um 15:15 schrieb Parthiban Nallathambi:

Hi Quentin Grembert,

On 11/27/18 3:12 PM, Quentin Grembert wrote:

Hi,

I don't know how to publish on U-Boot mailing list, so i'm writing

directly

to you.

I am using hab_auth_img to authentificate other files than Linux image,
like *.dtb or others.


So you have dtb and other images signed without combining them into a
single image like fitimage?

You can still use the previous method of using hab_auth_img with ivt if
you are providing the ivt at fixed offset.


Yes, but I recommend to use FIT image. It is design for such tasks.

bye,
Heiko




The patch you submitted may broke the compatibility with our use :
https://lists.denx.de/pipermail/u-boot/2018-November/348563.html

Regards,
Quentin Grembert





--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de





--
Thanks,
Parthiban N

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-22 Fax: (+49)-8142-66989-80 Email: p...@denx.de
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] imx: hab: extend hab_auth_img to calculate ivt_offset

2018-11-27 Thread Parthiban Nallathambi 

Hi Quentin Grembert,

On 11/27/18 3:12 PM, Quentin Grembert wrote:

Hi,

I don't know how to publish on U-Boot mailing list, so i'm writing directly
to you.

I am using hab_auth_img to authentificate other files than Linux image,
like *.dtb or others.


So you have dtb and other images signed without combining them into a
single image like fitimage?

You can still use the previous method of using hab_auth_img with ivt if
you are providing the ivt at fixed offset.



The patch you submitted may broke the compatibility with our use :
https://lists.denx.de/pipermail/u-boot/2018-November/348563.html

Regards,
Quentin Grembert



--
Thanks,
Parthiban N

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-22 Fax: (+49)-8142-66989-80 Email: p...@denx.de
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2] imx: hab: extend hab_auth_img to calculate ivt_offset

2018-11-21 Thread Parthiban Nallathambi 
Hi Breno,

On 11/21/18 7:42 PM, Breno Matheus Lima wrote:
> Hi Parthiban,
> 
> Em qua, 21 de nov de 2018 às 15:52, Parthiban Nallathambi  
> escreveu:
>>
>> Hi Breno,
>>
>> On 11/21/18 5:45 PM, Breno Matheus Lima wrote:
>>> Hi Parthiban,
>>>
>>> Em qua, 21 de nov de 2018 às 11:50, Parthiban Nallathambi  
>>> escreveu:
>>>>
>>>> Current implementation of hab_auth_img command needs ivt_offset to
>>>> authenticate the image. But ivt header is placed at the end of image
>>>> date after padding.
>>>>
>>>> This leaves the usage of hab_auth_img command to fixed size or static
>>>> offset for ivt header. New function "get_image_ivt_offset" is introduced
>>>> to find the ivt offset during runtime. The case conditional check in this
>>>> function is same as boot_get_kernel in common/bootm.c
>>>>
>>>> With this variable length image e.g. FIT image with any random size can
>>>> have IVT at the end and ivt_offset option can be left optional
>>>>
>>>> Can be used as "hab_auth_img $loadaddr $filesize" from u-boot script
>>>>
>>>> Signed-off-by: Parthiban Nallathambi 
>>>> ---
>>>>
>>>> Notes:
>>>>  Changelog in v2:
>>>>  - Finding IVT offset doesn't need length. Removed the
>>>>  length argument from get_image_ivt_offset
>>>>
>>>>   arch/arm/mach-imx/hab.c | 29 +++--
>>>>   1 file changed, 27 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
>>>> index b88acd13da..dbfd692fa3 100644
>>>> --- a/arch/arm/mach-imx/hab.c
>>>> +++ b/arch/arm/mach-imx/hab.c
>>>> @@ -6,6 +6,8 @@
>>>>   #include 
>>>>   #include 
>>>>   #include 
>>>> +#include 
>>>> +#include 
>>>>   #include 
>>>>   #include 
>>>>   #include 
>>>> @@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, 
>>>> int argc,
>>>>  return 0;
>>>>   }
>>>>
>>>> +static ulong get_image_ivt_offset(ulong img_addr)
>>>> +{
>>>> +   const void *buf;
>>>> +
>>>> +   buf = map_sysmem(img_addr, 0);
>>>> +   switch (genimg_get_format(buf)) {
>>>> +#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
>>>> +   case IMAGE_FORMAT_LEGACY:
>>>> +   return (image_get_image_size((image_header_t *)img_addr)
>>>> +   + 0x1000 - 1)  & ~(0x1000 - 1);
>>>> +#endif
>>>> +#if IMAGE_ENABLE_FIT
>>>> +   case IMAGE_FORMAT_FIT:
>>>> +   return (fit_get_size(buf) + 0x1000 - 1)  & ~(0x1000 - 1);
>>>> +#endif
>>>> +   default:
>>>> +   return 0;
>>>> +   }
>>>> +}
>>>
>>>
>>> Do you have more details about the image header I should use here?
>>
>> Is the image signed using CST or similar tool? Is so, the signature data
>> (HAB data: CSF, Certs and signature) pads at the end of the kernel
>> image.
> 
> Yes, my Kernel image contains an IVT and is signed with CST. The image
> layout looks like link below:
> https://pastebin.com/5qEt7ETa
> 
>>
>>>
>>> I'm trying to get the IVT offset for my Kernel image based on NXP
>>> 4.9.11_2.0.0_GA Linux release loaded at 0x8080:
>>>
>>> => fatload mmc 0:1 0x8080 zImage
>>> => hab_auth_img 0x8080 
>>
>> Length for hab_auth_img is still mandatory. Length hear means the file
>> size or total length of the image, this is required for the HAB API to
>> authenticate (HAB_RVT_AUTHENTICATE_IMAGE).
> 
> Oh ok, I understood the scenario right now.
> 
>>From my first overview I thought we would add IVT_SIZE + CSF_PAD_SIZE
> in ivt_offset to calculate the image length, similar approach we have
> in spl.c:
> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-imx/spl.c;h=a20b30d154d788e4ebd4e22e9a6568a4f24c057e;hb=HEAD#l226
> 
> In this case only load addr would be necessary.
> 
>>
>>>
>>> The zImage size in Header looks correct (0x00726690), but
>>> get_image_ivt_offset() is returning 0x0
>>
>> Looks like IVT offset is not found in the image.
>>
>>>
>>> $ hexdump zImage | h

Re: [U-Boot] [PATCH v2] imx: hab: extend hab_auth_img to calculate ivt_offset

2018-11-21 Thread Parthiban Nallathambi 

Hi Breno,

On 11/21/18 5:45 PM, Breno Matheus Lima wrote:

Hi Parthiban,

Em qua, 21 de nov de 2018 às 11:50, Parthiban Nallathambi  
escreveu:


Current implementation of hab_auth_img command needs ivt_offset to
authenticate the image. But ivt header is placed at the end of image
date after padding.

This leaves the usage of hab_auth_img command to fixed size or static
offset for ivt header. New function "get_image_ivt_offset" is introduced
to find the ivt offset during runtime. The case conditional check in this
function is same as boot_get_kernel in common/bootm.c

With this variable length image e.g. FIT image with any random size can
have IVT at the end and ivt_offset option can be left optional

Can be used as "hab_auth_img $loadaddr $filesize" from u-boot script

Signed-off-by: Parthiban Nallathambi 
---

Notes:
 Changelog in v2:
 - Finding IVT offset doesn't need length. Removed the
 length argument from get_image_ivt_offset

  arch/arm/mach-imx/hab.c | 29 +++--
  1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index b88acd13da..dbfd692fa3 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -6,6 +6,8 @@
  #include 
  #include 
  #include 
+#include 
+#include 
  #include 
  #include 
  #include 
@@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int 
argc,
 return 0;
  }

+static ulong get_image_ivt_offset(ulong img_addr)
+{
+   const void *buf;
+
+   buf = map_sysmem(img_addr, 0);
+   switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+   case IMAGE_FORMAT_LEGACY:
+   return (image_get_image_size((image_header_t *)img_addr)
+   + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+#if IMAGE_ENABLE_FIT
+   case IMAGE_FORMAT_FIT:
+   return (fit_get_size(buf) + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+   default:
+   return 0;
+   }
+}



Do you have more details about the image header I should use here?


Is the image signed using CST or similar tool? Is so, the signature data
(HAB data: CSF, Certs and signature) pads at the end of the kernel
image.



I'm trying to get the IVT offset for my Kernel image based on NXP
4.9.11_2.0.0_GA Linux release loaded at 0x8080:

=> fatload mmc 0:1 0x8080 zImage
=> hab_auth_img 0x8080 


Length for hab_auth_img is still mandatory. Length hear means the file
size or total length of the image, this is required for the HAB API to
authenticate (HAB_RVT_AUTHENTICATE_IMAGE).



The zImage size in Header looks correct (0x00726690), but
get_image_ivt_offset() is returning 0x0


Looks like IVT offset is not found in the image.



$ hexdump zImage | head
000  e1a0  e1a0  e1a0  e1a0
*
020 0003 ea00 2818 016f   6690 0072
030 0201 0403 9000 e10f 04f8 eb00 7001 e1a0
040 8002 e1a0 2000 e10f 0003 e312 0001 1a00

Seems that genimg_get_format() is returning 0x0.


Image is not signed?



Any ideias if I'm missing something?


+
  static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
  char * const argv[])
  {
 ulong   addr, length, ivt_offset;
 int rcode = 0;

-   if (argc < 4)
+   if (argc < 3)


I think we can also change here to argc < 2, the function
get_image_ivt_offset() only requires the img addr now.


No, length is mandatory for authentication. To brief, this patch just
removes the ivt_offset as argument and make it optional. This is needed
because, in images like FIT, the location of the ivt header varies
dynamically depending on the total number of images clubbed.

In such cases, the existing hab_auth_img is hard to use as ivt header
offset needs to be pre-calculated everytime and fed into.




 return CMD_RET_USAGE;

 addr = simple_strtoul(argv[1], NULL, 16);
 length = simple_strtoul(argv[2], NULL, 16);
-   ivt_offset = simple_strtoul(argv[3], NULL, 16);
+   if (argc == 3)


argc ==2


No, length is needed as stated above.





--
Thanks,
Parthiban N

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-22 Fax: (+49)-8142-66989-80 Email: p...@denx.de
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2] imx: hab: extend hab_auth_img to calculate ivt_offset

2018-11-21 Thread Parthiban Nallathambi 
Current implementation of hab_auth_img command needs ivt_offset to
authenticate the image. But ivt header is placed at the end of image
date after padding.

This leaves the usage of hab_auth_img command to fixed size or static
offset for ivt header. New function "get_image_ivt_offset" is introduced
to find the ivt offset during runtime. The case conditional check in this
function is same as boot_get_kernel in common/bootm.c

With this variable length image e.g. FIT image with any random size can
have IVT at the end and ivt_offset option can be left optional

Can be used as "hab_auth_img $loadaddr $filesize" from u-boot script

Signed-off-by: Parthiban Nallathambi 
---

Notes:
Changelog in v2:
- Finding IVT offset doesn't need length. Removed the
length argument from get_image_ivt_offset

 arch/arm/mach-imx/hab.c | 29 +++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index b88acd13da..dbfd692fa3 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -6,6 +6,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int 
argc,
return 0;
 }
 
+static ulong get_image_ivt_offset(ulong img_addr)
+{
+   const void *buf;
+
+   buf = map_sysmem(img_addr, 0);
+   switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+   case IMAGE_FORMAT_LEGACY:
+   return (image_get_image_size((image_header_t *)img_addr)
+   + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+#if IMAGE_ENABLE_FIT
+   case IMAGE_FORMAT_FIT:
+   return (fit_get_size(buf) + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+   default:
+   return 0;
+   }
+}
+
 static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
 char * const argv[])
 {
ulong   addr, length, ivt_offset;
int rcode = 0;
 
-   if (argc < 4)
+   if (argc < 3)
return CMD_RET_USAGE;
 
addr = simple_strtoul(argv[1], NULL, 16);
length = simple_strtoul(argv[2], NULL, 16);
-   ivt_offset = simple_strtoul(argv[3], NULL, 16);
+   if (argc == 3)
+   ivt_offset = get_image_ivt_offset(addr);
+   else
+   ivt_offset = simple_strtoul(argv[3], NULL, 16);
 
rcode = imx_hab_authenticate_image(addr, length, ivt_offset);
if (rcode == 0)
-- 
2.17.2

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] imx: hab: extend hab_auth_img to calculate ivt_offset

2018-11-21 Thread Parthiban Nallathambi 

Hi Breno,

On 11/21/18 2:24 PM, Breno Matheus Lima wrote:

Hi Parthiban,

Em ter, 6 de nov de 2018 às 14:42, Parthiban Nallathambi  
escreveu:


Current implementation of hab_auth_img command needs ivt_offset to
authenticate the image. But ivt header is placed at the end of image
date after padding.

This leaves the usage of hab_auth_img command to fixed size or static
offset for ivt header. New function "get_image_ivt_offset" is introduced
to find the ivt offset during runtime. The case conditional check in this
function is same as boot_get_kernel in common/bootm.c

With this variable length image e.g. FIT image with any random size can
have IVT at the end and ivt_offset option can be left optional

Can be used as "hab_auth_img $loadaddr $filesize" from u-boot script

Signed-off-by: Parthiban Nallathambi 
---
  arch/arm/mach-imx/hab.c | 29 +++--
  1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index b88acd13da..060d0866b3 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -6,6 +6,8 @@
  #include 
  #include 
  #include 
+#include 
+#include 
  #include 
  #include 
  #include 
@@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int 
argc,
 return 0;
  }

+static ulong get_image_ivt_offset(ulong img_addr, ulong length)
+{


I'm seeing that function get_image_ivt_offset() requires a length but
we are not using it, there is any reason for that?


length is not required to find the ivt offset in the image. I will
remove this.



Thanks,
Breno Lima



--
Thanks,
Parthiban N

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-22 Fax: (+49)-8142-66989-80 Email: p...@denx.de
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] imx: hab: extend hab_auth_img to calculate ivt_offset

2018-11-19 Thread Parthiban Nallathambi 

Ping on this patch!

On 11/6/18 5:39 PM, Parthiban Nallathambi wrote:

Current implementation of hab_auth_img command needs ivt_offset to
authenticate the image. But ivt header is placed at the end of image
date after padding.

This leaves the usage of hab_auth_img command to fixed size or static
offset for ivt header. New function "get_image_ivt_offset" is introduced
to find the ivt offset during runtime. The case conditional check in this
function is same as boot_get_kernel in common/bootm.c

With this variable length image e.g. FIT image with any random size can
have IVT at the end and ivt_offset option can be left optional

Can be used as "hab_auth_img $loadaddr $filesize" from u-boot script

Signed-off-by: Parthiban Nallathambi 
---
  arch/arm/mach-imx/hab.c | 29 +++--
  1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index b88acd13da..060d0866b3 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -6,6 +6,8 @@
  #include 
  #include 
  #include 
+#include 
+#include 
  #include 
  #include 
  #include 
@@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int 
argc,
return 0;
  }
  
+static ulong get_image_ivt_offset(ulong img_addr, ulong length)

+{
+   const void *buf;
+
+   buf = map_sysmem(img_addr, 0);
+   switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+   case IMAGE_FORMAT_LEGACY:
+   return (image_get_image_size((image_header_t *)img_addr)
+   + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+#if IMAGE_ENABLE_FIT
+   case IMAGE_FORMAT_FIT:
+   return (fit_get_size(buf) + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+   default:
+   return 0;
+   }
+}
+
  static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
 char * const argv[])
  {
ulong   addr, length, ivt_offset;
int rcode = 0;
  
-	if (argc < 4)

+   if (argc < 3)
return CMD_RET_USAGE;
  
  	addr = simple_strtoul(argv[1], NULL, 16);

length = simple_strtoul(argv[2], NULL, 16);
-   ivt_offset = simple_strtoul(argv[3], NULL, 16);
+   if (argc == 3)
+   ivt_offset = get_image_ivt_offset(addr, length);
+   else
+   ivt_offset = simple_strtoul(argv[3], NULL, 16);
  
  	rcode = imx_hab_authenticate_image(addr, length, ivt_offset);

if (rcode == 0)



--
Thanks,
Parthiban N

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-22 Fax: (+49)-8142-66989-80 Email: p...@denx.de
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] imx: hab: extend hab_auth_img to calculate ivt_offset

2018-11-06 Thread Parthiban Nallathambi 
Current implementation of hab_auth_img command needs ivt_offset to
authenticate the image. But ivt header is placed at the end of image
date after padding.

This leaves the usage of hab_auth_img command to fixed size or static
offset for ivt header. New function "get_image_ivt_offset" is introduced
to find the ivt offset during runtime. The case conditional check in this
function is same as boot_get_kernel in common/bootm.c

With this variable length image e.g. FIT image with any random size can
have IVT at the end and ivt_offset option can be left optional

Can be used as "hab_auth_img $loadaddr $filesize" from u-boot script

Signed-off-by: Parthiban Nallathambi 
---
 arch/arm/mach-imx/hab.c | 29 +++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index b88acd13da..060d0866b3 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -6,6 +6,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int 
argc,
return 0;
 }
 
+static ulong get_image_ivt_offset(ulong img_addr, ulong length)
+{
+   const void *buf;
+
+   buf = map_sysmem(img_addr, 0);
+   switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+   case IMAGE_FORMAT_LEGACY:
+   return (image_get_image_size((image_header_t *)img_addr)
+   + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+#if IMAGE_ENABLE_FIT
+   case IMAGE_FORMAT_FIT:
+   return (fit_get_size(buf) + 0x1000 - 1)  & ~(0x1000 - 1);
+#endif
+   default:
+   return 0;
+   }
+}
+
 static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
 char * const argv[])
 {
ulong   addr, length, ivt_offset;
int rcode = 0;
 
-   if (argc < 4)
+   if (argc < 3)
return CMD_RET_USAGE;
 
addr = simple_strtoul(argv[1], NULL, 16);
length = simple_strtoul(argv[2], NULL, 16);
-   ivt_offset = simple_strtoul(argv[3], NULL, 16);
+   if (argc == 3)
+   ivt_offset = get_image_ivt_offset(addr, length);
+   else
+   ivt_offset = simple_strtoul(argv[3], NULL, 16);
 
rcode = imx_hab_authenticate_image(addr, length, ivt_offset);
if (rcode == 0)
-- 
2.17.2

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot