[PATCH] arm: renesas: Fix RZ/G2L GICR base address

[Paul Barker]

When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.

Fixes: 387d4275ab0e ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker 
---
 arch/arm/mach-renesas/include/mach/rzg2l.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-renesas/include/mach/rzg2l.h 
b/arch/arm/mach-renesas/include/mach/rzg2l.h
index 057df5cb9d46..c49a71a6dd41 100644
--- a/arch/arm/mach-renesas/include/mach/rzg2l.h
+++ b/arch/arm/mach-renesas/include/mach/rzg2l.h
@@ -8,6 +8,6 @@
 #define __ASM_ARCH_RZG2L_H
 
 #define GICD_BASE  0x1190
-#define GICR_BASE  0x1196
+#define GICR_BASE  0x1194
 
 #endif /* __ASM_ARCH_RZG2L_H */
-- 
2.43.0

[PATCH v2 1/2] ARM: dts: Drop unused RZ/G2L devicetrees

[Paul Barker]

We are now using the dts/upstream subtree for the RZ/G2L SoC family so
we can drop unused devicetree files from arch/arm/dts.

Signed-off-by: Paul Barker 
---
Changes v1->v2:
  - Improve commit message

 arch/arm/dts/Makefile |3 -
 arch/arm/dts/r9a07g044.dtsi   | 1273 -
 arch/arm/dts/r9a07g044l2-smarc.dts|   39 -
 arch/arm/dts/r9a07g044l2.dtsi |   13 -
 arch/arm/dts/rz-smarc-common.dtsi |  183 ---
 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi |  157 ---
 arch/arm/dts/rzg2l-smarc-som.dtsi |  371 --
 arch/arm/dts/rzg2l-smarc.dtsi |  181 ---
 8 files changed, 2220 deletions(-)
 delete mode 100644 arch/arm/dts/r9a07g044.dtsi
 delete mode 100644 arch/arm/dts/r9a07g044l2-smarc.dts
 delete mode 100644 arch/arm/dts/r9a07g044l2.dtsi
 delete mode 100644 arch/arm/dts/rz-smarc-common.dtsi
 delete mode 100644 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
 delete mode 100644 arch/arm/dts/rzg2l-smarc-som.dtsi
 delete mode 100644 arch/arm/dts/rzg2l-smarc.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aeccfa93fc53..e0cc9937acb4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -979,9 +979,6 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
 
-dtb-$(CONFIG_TARGET_RZG2L) += \
-   r9a07g044l2-smarc.dts
-
 ifdef CONFIG_RCAR_64
 DTC_FLAGS += -R 4 -p 0x1000
 endif
diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
deleted file mode 100644
index 66f68fc2b241..
--- a/arch/arm/dts/r9a07g044.dtsi
+++ /dev/null
@@ -1,1273 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include 
-#include 
-
-/ {
-   compatible = "renesas,r9a07g044";
-   #address-cells = <2>;
-   #size-cells = <2>;
-
-   audio_clk1: audio1-clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   /* This value must be overridden by boards that provide it */
-   clock-frequency = <0>;
-   };
-
-   audio_clk2: audio2-clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   /* This value must be overridden by boards that provide it */
-   clock-frequency = <0>;
-   };
-
-   /* External CAN clock - to be overridden by boards that provide it */
-   can_clk: can-clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
-   /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
-   extal_clk: extal-clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   /* This value must be overridden by the board */
-   clock-frequency = <0>;
-   };
-
-   cluster0_opp: opp-table-0 {
-   compatible = "operating-points-v2";
-   opp-shared;
-
-   opp-15000 {
-   opp-hz = /bits/ 64 <15000>;
-   opp-microvolt = <110>;
-   clock-latency-ns = <30>;
-   };
-   opp-3 {
-   opp-hz = /bits/ 64 <3>;
-   opp-microvolt = <110>;
-   clock-latency-ns = <30>;
-   };
-   opp-6 {
-   opp-hz = /bits/ 64 <6>;
-   opp-microvolt = <110>;
-   clock-latency-ns = <30>;
-   };
-   opp-12 {
-   opp-hz = /bits/ 64 <12>;
-   opp-microvolt = <110>;
-   clock-latency-ns = <30>;
-   opp-suspend;
-   };
-   };
-
-   cpus {
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   cpu-map {
-   cluster0 {
-   core0 {
-   cpu = <&cpu0>;
-   };
-   core1 {
-   cpu = <&cpu1>;
-   };
-   };
-   };
-
-   cpu0: cpu@0 {
-   compatible = "arm,cortex-a55";
-   reg = <0>;
-   device_type = "cpu";
-   #cooling-cells = <2>;
-  

[PATCH v2 2/2] dt-bindings: Drop unused RZ/G2L devicetree bindings

[Paul Barker]

We are now using the dts/upstream subtree for the RZ/G2L SoC family so
we can drop unused dt-bindings headers.

Signed-off-by: Paul Barker 
---
Changes v1->v2:
  - Improve commit message

 include/dt-bindings/clock/r9a07g044-cpg.h | 220 --
 .../interrupt-controller/irqc-rzg2l.h |  25 --
 include/dt-bindings/pinctrl/rzg2l-pinctrl.h   |  23 --
 3 files changed, 268 deletions(-)
 delete mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h
 delete mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h
 delete mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h

diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h 
b/include/dt-bindings/clock/r9a07g044-cpg.h
deleted file mode 100644
index 0bb17ff1a01a..
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
-#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
-
-#include 
-
-/* R9A07G044 CPG Core Clocks */
-#define R9A07G044_CLK_I0
-#define R9A07G044_CLK_I2   1
-#define R9A07G044_CLK_G2
-#define R9A07G044_CLK_S0   3
-#define R9A07G044_CLK_S1   4
-#define R9A07G044_CLK_SPI0 5
-#define R9A07G044_CLK_SPI1 6
-#define R9A07G044_CLK_SD0  7
-#define R9A07G044_CLK_SD1  8
-#define R9A07G044_CLK_M0   9
-#define R9A07G044_CLK_M1   10
-#define R9A07G044_CLK_M2   11
-#define R9A07G044_CLK_M3   12
-#define R9A07G044_CLK_M4   13
-#define R9A07G044_CLK_HP   14
-#define R9A07G044_CLK_TSU  15
-#define R9A07G044_CLK_ZT   16
-#define R9A07G044_CLK_P0   17
-#define R9A07G044_CLK_P1   18
-#define R9A07G044_CLK_P2   19
-#define R9A07G044_CLK_AT   20
-#define R9A07G044_OSCCLK   21
-#define R9A07G044_CLK_P0_DIV2  22
-
-/* R9A07G044 Module Clocks */
-#define R9A07G044_CA55_SCLK0
-#define R9A07G044_CA55_PCLK1
-#define R9A07G044_CA55_ATCLK   2
-#define R9A07G044_CA55_GICCLK  3
-#define R9A07G044_CA55_PERICLK 4
-#define R9A07G044_CA55_ACLK5
-#define R9A07G044_CA55_TSCLK   6
-#define R9A07G044_GIC600_GICCLK7
-#define R9A07G044_IA55_CLK 8
-#define R9A07G044_IA55_PCLK9
-#define R9A07G044_MHU_PCLK 10
-#define R9A07G044_SYC_CNT_CLK  11
-#define R9A07G044_DMAC_ACLK12
-#define R9A07G044_DMAC_PCLK13
-#define R9A07G044_OSTM0_PCLK   14
-#define R9A07G044_OSTM1_PCLK   15
-#define R9A07G044_OSTM2_PCLK   16
-#define R9A07G044_MTU_X_MCK_MTU3   17
-#define R9A07G044_POE3_CLKM_POE18
-#define R9A07G044_GPT_PCLK 19
-#define R9A07G044_POEG_A_CLKP  20
-#define R9A07G044_POEG_B_CLKP  21
-#define R9A07G044_POEG_C_CLKP  22
-#define R9A07G044_POEG_D_CLKP  23
-#define R9A07G044_WDT0_PCLK24
-#define R9A07G044_WDT0_CLK 25
-#define R9A07G044_WDT1_PCLK26
-#define R9A07G044_WDT1_CLK 27
-#define R9A07G044_WDT2_PCLK28
-#define R9A07G044_WDT2_CLK 29
-#define R9A07G044_SPI_CLK2 30
-#define R9A07G044_SPI_CLK  31
-#define R9A07G044_SDHI0_IMCLK  32
-#define R9A07G044_SDHI0_IMCLK2 33
-#define R9A07G044_SDHI0_CLK_HS 34
-#define R9A07G044_SDHI0_ACLK   35
-#define R9A07G044_SDHI1_IMCLK  36
-#define R9A07G044_SDHI1_IMCLK2 37
-#define R9A07G044_SDHI1_CLK_HS 38
-#define R9A07G044_SDHI1_ACLK   39
-#define R9A07G044_GPU_CLK  40
-#define R9A07G044_GPU_AXI_CLK  41
-#define R9A07G044_GPU_ACE_CLK  42
-#define R9A07G044_ISU_ACLK 43
-#define R9A07G044_ISU_PCLK 44
-#define R9A07G044_H264_CLK_A   45
-#define R9A07G044_H264_CLK_P   46
-#define R9A07G044_CRU_SYSCLK   47
-#define R9A07G044_CRU_VCLK 48
-#define R9A07G044_CRU_PCLK 49
-#define R9A07G044_CRU_ACLK 50
-#define R9A07G044_MIPI_DSI_PLLCLK  51
-#define R9A07G044_MIPI_DSI_SYSCLK  52
-#define R9A07G044_MIPI_DSI_ACLK53
-#define R9A07G044_MIPI_DSI_PCLK54
-#define R9A07G044_MIPI_DSI_VCLK55
-#define R9A07G044_MIPI_DSI_LPCLK   56
-#define R9A07G044_LCDC_CLK_A   57
-#define R9A07G044_LCDC_CLK_P   58
-#define R9A07G044_LCDC_CLK_D   59
-#define R9A07G044_SSI0_PCLK2   60
-#define R9A07G044_SSI0_PCLK_SFR61
-#define R9A07G044_SSI1_PCLK2   62
-#define R9A07G044_SSI1_PCLK_SFR63
-#define R9A07G044_SSI2_PCLK2   64
-#def

[PATCH 2/2] dt-bindings: Drop unused RZ/G2L devicetree bindings

[Paul Barker]

We are now using the dts/upstream subtree for the RZ/G2L SoC family.

Signed-off-by: Paul Barker 
---
 include/dt-bindings/clock/r9a07g044-cpg.h | 220 --
 .../interrupt-controller/irqc-rzg2l.h |  25 --
 include/dt-bindings/pinctrl/rzg2l-pinctrl.h   |  23 --
 3 files changed, 268 deletions(-)
 delete mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h
 delete mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h
 delete mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h

diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h 
b/include/dt-bindings/clock/r9a07g044-cpg.h
deleted file mode 100644
index 0bb17ff1a01a..
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
-#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
-
-#include 
-
-/* R9A07G044 CPG Core Clocks */
-#define R9A07G044_CLK_I0
-#define R9A07G044_CLK_I2   1
-#define R9A07G044_CLK_G2
-#define R9A07G044_CLK_S0   3
-#define R9A07G044_CLK_S1   4
-#define R9A07G044_CLK_SPI0 5
-#define R9A07G044_CLK_SPI1 6
-#define R9A07G044_CLK_SD0  7
-#define R9A07G044_CLK_SD1  8
-#define R9A07G044_CLK_M0   9
-#define R9A07G044_CLK_M1   10
-#define R9A07G044_CLK_M2   11
-#define R9A07G044_CLK_M3   12
-#define R9A07G044_CLK_M4   13
-#define R9A07G044_CLK_HP   14
-#define R9A07G044_CLK_TSU  15
-#define R9A07G044_CLK_ZT   16
-#define R9A07G044_CLK_P0   17
-#define R9A07G044_CLK_P1   18
-#define R9A07G044_CLK_P2   19
-#define R9A07G044_CLK_AT   20
-#define R9A07G044_OSCCLK   21
-#define R9A07G044_CLK_P0_DIV2  22
-
-/* R9A07G044 Module Clocks */
-#define R9A07G044_CA55_SCLK0
-#define R9A07G044_CA55_PCLK1
-#define R9A07G044_CA55_ATCLK   2
-#define R9A07G044_CA55_GICCLK  3
-#define R9A07G044_CA55_PERICLK 4
-#define R9A07G044_CA55_ACLK5
-#define R9A07G044_CA55_TSCLK   6
-#define R9A07G044_GIC600_GICCLK7
-#define R9A07G044_IA55_CLK 8
-#define R9A07G044_IA55_PCLK9
-#define R9A07G044_MHU_PCLK 10
-#define R9A07G044_SYC_CNT_CLK  11
-#define R9A07G044_DMAC_ACLK12
-#define R9A07G044_DMAC_PCLK13
-#define R9A07G044_OSTM0_PCLK   14
-#define R9A07G044_OSTM1_PCLK   15
-#define R9A07G044_OSTM2_PCLK   16
-#define R9A07G044_MTU_X_MCK_MTU3   17
-#define R9A07G044_POE3_CLKM_POE18
-#define R9A07G044_GPT_PCLK 19
-#define R9A07G044_POEG_A_CLKP  20
-#define R9A07G044_POEG_B_CLKP  21
-#define R9A07G044_POEG_C_CLKP  22
-#define R9A07G044_POEG_D_CLKP  23
-#define R9A07G044_WDT0_PCLK24
-#define R9A07G044_WDT0_CLK 25
-#define R9A07G044_WDT1_PCLK26
-#define R9A07G044_WDT1_CLK 27
-#define R9A07G044_WDT2_PCLK28
-#define R9A07G044_WDT2_CLK 29
-#define R9A07G044_SPI_CLK2 30
-#define R9A07G044_SPI_CLK  31
-#define R9A07G044_SDHI0_IMCLK  32
-#define R9A07G044_SDHI0_IMCLK2 33
-#define R9A07G044_SDHI0_CLK_HS 34
-#define R9A07G044_SDHI0_ACLK   35
-#define R9A07G044_SDHI1_IMCLK  36
-#define R9A07G044_SDHI1_IMCLK2 37
-#define R9A07G044_SDHI1_CLK_HS 38
-#define R9A07G044_SDHI1_ACLK   39
-#define R9A07G044_GPU_CLK  40
-#define R9A07G044_GPU_AXI_CLK  41
-#define R9A07G044_GPU_ACE_CLK  42
-#define R9A07G044_ISU_ACLK 43
-#define R9A07G044_ISU_PCLK 44
-#define R9A07G044_H264_CLK_A   45
-#define R9A07G044_H264_CLK_P   46
-#define R9A07G044_CRU_SYSCLK   47
-#define R9A07G044_CRU_VCLK 48
-#define R9A07G044_CRU_PCLK 49
-#define R9A07G044_CRU_ACLK 50
-#define R9A07G044_MIPI_DSI_PLLCLK  51
-#define R9A07G044_MIPI_DSI_SYSCLK  52
-#define R9A07G044_MIPI_DSI_ACLK53
-#define R9A07G044_MIPI_DSI_PCLK54
-#define R9A07G044_MIPI_DSI_VCLK55
-#define R9A07G044_MIPI_DSI_LPCLK   56
-#define R9A07G044_LCDC_CLK_A   57
-#define R9A07G044_LCDC_CLK_P   58
-#define R9A07G044_LCDC_CLK_D   59
-#define R9A07G044_SSI0_PCLK2   60
-#define R9A07G044_SSI0_PCLK_SFR61
-#define R9A07G044_SSI1_PCLK2   62
-#define R9A07G044_SSI1_PCLK_SFR63
-#define R9A07G044_SSI2_PCLK2   64
-#define R9A07G044_SSI2_PCLK_SFR65
-#define R9A07G044_SSI3_PCLK2   66
-#define

[PATCH 1/2] ARM: dts: Drop unused RZ/G2L devicetrees

[Paul Barker]

We are now using the dts/upstream subtree for the RZ/G2L SoC family.

Signed-off-by: Paul Barker 
---
 arch/arm/dts/Makefile |3 -
 arch/arm/dts/r9a07g044.dtsi   | 1273 -
 arch/arm/dts/r9a07g044l2-smarc.dts|   39 -
 arch/arm/dts/r9a07g044l2.dtsi |   13 -
 arch/arm/dts/rz-smarc-common.dtsi |  183 ---
 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi |  157 ---
 arch/arm/dts/rzg2l-smarc-som.dtsi |  371 --
 arch/arm/dts/rzg2l-smarc.dtsi |  181 ---
 8 files changed, 2220 deletions(-)
 delete mode 100644 arch/arm/dts/r9a07g044.dtsi
 delete mode 100644 arch/arm/dts/r9a07g044l2-smarc.dts
 delete mode 100644 arch/arm/dts/r9a07g044l2.dtsi
 delete mode 100644 arch/arm/dts/rz-smarc-common.dtsi
 delete mode 100644 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
 delete mode 100644 arch/arm/dts/rzg2l-smarc-som.dtsi
 delete mode 100644 arch/arm/dts/rzg2l-smarc.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aeccfa93fc53..e0cc9937acb4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -979,9 +979,6 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
 
-dtb-$(CONFIG_TARGET_RZG2L) += \
-   r9a07g044l2-smarc.dts
-
 ifdef CONFIG_RCAR_64
 DTC_FLAGS += -R 4 -p 0x1000
 endif
diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
deleted file mode 100644
index 66f68fc2b241..
--- a/arch/arm/dts/r9a07g044.dtsi
+++ /dev/null
@@ -1,1273 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include 
-#include 
-
-/ {
-   compatible = "renesas,r9a07g044";
-   #address-cells = <2>;
-   #size-cells = <2>;
-
-   audio_clk1: audio1-clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   /* This value must be overridden by boards that provide it */
-   clock-frequency = <0>;
-   };
-
-   audio_clk2: audio2-clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   /* This value must be overridden by boards that provide it */
-   clock-frequency = <0>;
-   };
-
-   /* External CAN clock - to be overridden by boards that provide it */
-   can_clk: can-clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
-   /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
-   extal_clk: extal-clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   /* This value must be overridden by the board */
-   clock-frequency = <0>;
-   };
-
-   cluster0_opp: opp-table-0 {
-   compatible = "operating-points-v2";
-   opp-shared;
-
-   opp-15000 {
-   opp-hz = /bits/ 64 <15000>;
-   opp-microvolt = <110>;
-   clock-latency-ns = <30>;
-   };
-   opp-3 {
-   opp-hz = /bits/ 64 <3>;
-   opp-microvolt = <110>;
-   clock-latency-ns = <30>;
-   };
-   opp-6 {
-   opp-hz = /bits/ 64 <6>;
-   opp-microvolt = <110>;
-   clock-latency-ns = <30>;
-   };
-   opp-12 {
-   opp-hz = /bits/ 64 <12>;
-   opp-microvolt = <110>;
-   clock-latency-ns = <30>;
-   opp-suspend;
-   };
-   };
-
-   cpus {
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   cpu-map {
-   cluster0 {
-   core0 {
-   cpu = <&cpu0>;
-   };
-   core1 {
-   cpu = <&cpu1>;
-   };
-   };
-   };
-
-   cpu0: cpu@0 {
-   compatible = "arm,cortex-a55";
-   reg = <0>;
-   device_type = "cpu";
-   #cooling-cells = <2>;
-   next-level-cache = <&L3_CA55>;
-   enable-method = "psci"

[PATCH] board: rzg2l: Update MAINTAINERS file to match dts/upstream paths

[Paul Barker]

We are now using the dts/upstream subtree for the RZ/G2L SoC family, so
update the board MAINTAINERS file to match rz-smarc dtsi files in this
subtree.

Signed-off-by: Paul Barker 
---
 board/renesas/rzg2l/MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/renesas/rzg2l/MAINTAINERS b/board/renesas/rzg2l/MAINTAINERS
index 0a51391c1fc9..0e656e2ef4f0 100644
--- a/board/renesas/rzg2l/MAINTAINERS
+++ b/board/renesas/rzg2l/MAINTAINERS
@@ -1,6 +1,6 @@
 RENESAS RZG2L BOARD FAMILY
 M: Paul Barker 
 S: Supported
-F: arch/arm/dts/rz-smarc-common.dtsi
+N: rz-smarc
 N: rzg2l
 N: r9a07g044
-- 
2.43.0

Re: [PATCH 06/14] net: phy: ksz90x1: Handle ksz9131 LED errata

[Paul Barker]

On 27/10/2024 16:18, Marek Vasut wrote:
> On 10/24/24 5:24 PM, Paul Barker wrote:
>> Micrel KSZ9131 PHY LED behavior is not correct when configured in
>> Individual Mode, LED1 (Activity LED) is in the ON state when there is
>> no-link.
>>
>> Workaround this by setting bit 9 of register 0x1e after verifying that
>> the LED configuration is Individual Mode.
>>
>> This issue is described in KSZ9131RNX Silicon Errata DS8693B [*]
>> and according to that it will not be corrected in a future silicon
>> revision.
>>
>> [*] 
>> https://ww1.microchip.com/downloads/en/DeviceDoc/KSZ9131RNX-Silicon-Errata-and-Data-Sheet-Clarification-8863B.pdf
>>
>> Based on commit 0316c7e66bbd in the Linux kernel.
>>
>> Signed-off-by: Paul Barker 
>> ---
>>   drivers/net/phy/micrel_ksz90x1.c | 24 
>>   1 file changed, 24 insertions(+)
>>
>> diff --git a/drivers/net/phy/micrel_ksz90x1.c 
>> b/drivers/net/phy/micrel_ksz90x1.c
>> index c48ae6e88f30..4f99b115a3c7 100644
>> --- a/drivers/net/phy/micrel_ksz90x1.c
>> +++ b/drivers/net/phy/micrel_ksz90x1.c
>> @@ -436,6 +436,26 @@ static int ksz9131_config_rgmii_delay(struct phy_device 
>> *phydev)
>>  return ret;
>>   }
>>   
>> +/* Silicon Errata DS8693B
>> + *
>> + * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
>> + * condition. Workaround is to set register 0x1e, bit 9, this way LED1 
>> behaves
>> + * according to the datasheet (off if there is no link).
>> + */
>> +static int ksz9131_led_errata(struct phy_device *phydev)
>> +{
>> +int reg;
>> +
>> +reg = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 0);
>> +if (reg < 0)
>> +return reg;
>> +
>> +if (!(reg & BIT(4)))
> It would be good to have symbolic names for these BIT()s , please add 
> some #define ... macros .

I can add symbolic names for the values used above
(KSZ9131RN_COMMON_CTRL=0 and KSZ9131RN_COMMON_CTRL_LED_MODE=BIT(4)).

The arguments used in the following phy_set_bits() call are a bit
trickier - all the errata document says is "Register 0x1E (30d), bit 9
must be set to 1". The Linux kernel commit adding this workaround
doesn't have any symbolic names either.

Thanks,

-- 
Paul Barker

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Re: [PATCH 11/14] net: ravb: Add RZ/G2L Support

[Paul Barker]

On 27/10/2024 16:29, Marek Vasut wrote:
> On 10/24/24 5:24 PM, Paul Barker wrote:
>> The Renesas R9A07G044L (RZ/G2L) SoC includes two Gigabit Ethernet
>> interfaces which can be supported using the ravb driver. Some RZ/G2L
>> specific steps need to be taken during initialization due to differences
>> between this SoC and previously supported SoCs. We also need to ensure
>> that the module reset is de-asserted after the module clock is enabled
>> but before any Ethernet register reads/writes take place.
>>
>> Signed-off-by: Paul Barker 
>> ---
>>   arch/arm/mach-renesas/Kconfig |   1 +
>>   drivers/net/Kconfig   |   2 +
>>   drivers/net/ravb.c| 183 --
>>   3 files changed, 176 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig
>> index aeb55da609bd..d373ab56ce91 100644
>> --- a/arch/arm/mach-renesas/Kconfig
>> +++ b/arch/arm/mach-renesas/Kconfig
>> @@ -76,6 +76,7 @@ config RZG2L
>>  imply MULTI_DTB_FIT
>>  imply MULTI_DTB_FIT_USER_DEFINED_AREA
>>  imply PINCTRL_RZG2L
>> +imply RENESAS_RAVB
>>  imply RENESAS_SDHI
>>  imply RZG2L_GPIO
>>  imply SCIF_CONSOLE
>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
>> index 89f7411bdf33..d009acdcd94f 100644
>> --- a/drivers/net/Kconfig
>> +++ b/drivers/net/Kconfig
>> @@ -822,6 +822,8 @@ config RENESAS_RAVB
>>  depends on RCAR_64
>>  select PHYLIB
>>  select PHY_ETHERNET_ID
>> +select BITBANGMII
>> +select BITBANGMII_MULTI
> 
> Keep the list sorted.

Will fix in v2.

> 
>>  help
>>This driver implements support for the Ethernet AVB block in
>>Renesas M3 and H3 SoCs.
>> diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
>> index fb869cd0872e..e2ab929858c8 100644
>> --- a/drivers/net/ravb.c
>> +++ b/drivers/net/ravb.c
> 
> [...]
> 
>> @@ -108,6 +122,16 @@
>>   
>>   #define RAVB_TX_TIMEOUT_MS 1000
>>   
>> +#define RAVB_RCV_BUFF_MAX   8192
>> +
>> +struct ravb_device_ops {
>> +int (*mac_init)(struct udevice *dev);
>> +int (*dmac_init)(struct udevice *dev);
>> +int (*config)(struct udevice *dev);
>> +int (*reset_deassert)(struct udevice *dev);
>> +void (*reset_assert)(struct udevice *dev);
>> +};
> 
> [...]
> 
>> +static int ravb_reset_deassert_rcar(struct udevice *dev)
>> +{
> 
> The callsites should check if a callback is assigned or NULL and only 
> call the callback if it is assigned. Then you won't need empty callbacks 
> like this.
> 
> Basically add if (ops->reset_deassert) ops->reset_deassert() and remove 
> this empty function.

Will fix in v2.

> 
>> +return 0;
>> +}
>> +
>> +static void ravb_reset_assert_rzg2l(struct udevice *dev)
>> +{
>> +struct ravb_priv *eth = dev_get_priv(dev);
>> +
>> +reset_assert(ð->rst);
>> +reset_free(ð->rst);
>> +}
> 
> A bit of a design question -- would it make sense to have ravb-rcar.c 
> and ravb-rzg2l.c to contain the differences between the ravb variants, 
> and keep common code only in ravb.c ?

That would probably be an improvement. I'll do that for v2.

Thanks,

-- 
Paul Barker


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Re: [PATCH 09/14] net: ravb: Support up to two instances

[Paul Barker]

On 27/10/2024 16:25, Marek Vasut wrote:
> On 10/24/24 5:24 PM, Paul Barker wrote:
>> Several Renesas SoCs in the RZ/G2L family have two Ethernet interfaces.
>> To support this second interface, we extend the bb_miiphy_buses[] array
>> and keep track of the current bus index in ravb_of_to_plat().
>>
>> Support for an arbitrary number of instances is not implemented - it is
>> expected that bb_miiphy_buses will be replaced with a proper device
>> model/uclass implementation before that is needed.
>>
>> Signed-off-by: Paul Barker 
>> ---
>>   drivers/net/ravb.c | 28 
>>   1 file changed, 24 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
>> index f1401d2f6ed2..9b33ce929618 100644
>> --- a/drivers/net/ravb.c
>> +++ b/drivers/net/ravb.c
>> @@ -11,6 +11,7 @@
>>   #include 
>>   #include 
>>   #include 
>> +#include 
>>   #include 
>>   #include 
>>   #include 
>> @@ -494,6 +495,7 @@ static int ravb_probe(struct udevice *dev)
>>   {
>>  struct eth_pdata *pdata = dev_get_plat(dev);
>>  struct ravb_priv *eth = dev_get_priv(dev);
>> +struct bb_miiphy_bus *phybus;
>>  struct mii_dev *mdiodev;
>>  void __iomem *iobase;
>>  int ret;
>> @@ -513,7 +515,8 @@ static int ravb_probe(struct udevice *dev)
>>   
>>  mdiodev->read = bb_miiphy_read;
>>  mdiodev->write = bb_miiphy_write;
>> -bb_miiphy_buses[0].priv = eth;
>> +phybus = (struct bb_miiphy_bus *)pdata->priv_pdata;
>> +phybus->priv = eth;
>>  snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
>>   
>>  ret = mdio_register(mdiodev);
>> @@ -625,7 +628,17 @@ int ravb_bb_delay(struct bb_miiphy_bus *bus)
>>   
>>   struct bb_miiphy_bus bb_miiphy_buses[] = {
>>  {
>> -.name   = "ravb",
>> +.name   = "ravb0",
>> +.init   = ravb_bb_init,
>> +.mdio_active= ravb_bb_mdio_active,
>> +.mdio_tristate  = ravb_bb_mdio_tristate,
>> +.set_mdio   = ravb_bb_set_mdio,
>> +.get_mdio   = ravb_bb_get_mdio,
>> +.set_mdc= ravb_bb_set_mdc,
>> +.delay  = ravb_bb_delay,
>> +},
>> +{
>> +.name   = "ravb1",
>>  .init   = ravb_bb_init,
>>  .mdio_active= ravb_bb_mdio_active,
>>  .mdio_tristate  = ravb_bb_mdio_tristate,
>> @@ -646,10 +659,16 @@ static const struct eth_ops ravb_ops = {
>>  .write_hwaddr   = ravb_write_hwaddr,
>>   };
>>   
>> +static int bb_miiphy_index;
>> +
>>   int ravb_of_to_plat(struct udevice *dev)
>>   {
>>  struct eth_pdata *pdata = dev_get_plat(dev);
>> -const fdt32_t *cell;
>> +
>> +if (bb_miiphy_index >= bb_miiphy_buses_num) {
>> +dev_err(dev, "ravb driver supports only 1 or 2 devices!\n");
> H, I really do not like this, can we make this dynamic ?
> 
> Unless you want to take a look at this yourself, I can add it into my todo ?

I think the real solution here would be to separate the bb_miiphy
operations from the bus instance, so we would have something like:

struct bb_miiphy_bus {
struct bb_miiphy_ops *ops;
void *priv;
};

struct bb_miiphy_ops {
int (*init)(struct bb_miiphy_bus *bus);
int (*mdio_active)(struct bb_miiphy_bus *bus);
int (*mdio_tristate)(struct bb_miiphy_bus *bus);
int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
int (*delay)(struct bb_miiphy_bus *bus);
};

int bb_miiphy_bus_register(const char *name,
   struct bb_miiphy_ops *ops,
   void *priv);

Where drivers will call `bb_miiphy_bus_register()` from the probe
function, it will create a `struct bb_miiphy_bus` instance and a
`struct mii_dev` instance then call `mdio_register()`. The driver can
then support an arbitrary number of MDIO busses from a single constant
`struct bb_miiphy_ops` instance.

The bb_miiphy_getbus() function should be dropped from miiphy.c.
Instead, the priv pointer in the `struct mii_dev` instance can point to
the appropriate `struct bb_miiphy_bus` instance.

It looks like all users of CONFIG_BITBANGMII also set
CONFIG_BITBANGMII_MULTI, and there don't seem to be any targets that
define the macros documented in README.bitbangMII (lines 15-22). So, we
can drop the non-BITBANGMII_MULTI code from miiphybb.c and simplify
things a lot.

That's non-trivial but it's not a huge set of changes, maybe something
we could target for v2024.04?

Thanks,

-- 
Paul Barker

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Re: [PATCH 08/14] net: phy: ksz90x1: Simplify ksz9131_config_rgmii_delay

[Paul Barker]

On 27/10/2024 16:20, Marek Vasut wrote:
> On 10/24/24 5:24 PM, Paul Barker wrote:
>> We can call phy_modify_mmd() instead of manually calling drv->readext()
>> and drv->writeext().
>>
>> Signed-off-by: Paul Barker 
>> ---
>>   drivers/net/phy/micrel_ksz90x1.c | 26 --
>>   1 file changed, 8 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/net/phy/micrel_ksz90x1.c 
>> b/drivers/net/phy/micrel_ksz90x1.c
>> index b64046e0bc72..6515d8feb9be 100644
>> --- a/drivers/net/phy/micrel_ksz90x1.c
>> +++ b/drivers/net/phy/micrel_ksz90x1.c
>> @@ -502,8 +502,7 @@ static int ksz9131_of_load_all_skew_values(struct 
>> phy_device *phydev)
>>   
>>   static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
>>   {
>> -struct phy_driver *drv = phydev->drv;
>> -u16 rxcdll_val, txcdll_val, val;
>> +u16 rxcdll_val, txcdll_val;
>>  int ret;
>>   
>>  switch (phydev->interface) {
>> @@ -527,24 +526,15 @@ static int ksz9131_config_rgmii_delay(struct 
>> phy_device *phydev)
>>  return 0;
>>  }
>>   
>> -val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
>> -   KSZ9131RN_RXC_DLL_CTRL);
>> -val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
>> -val |= rxcdll_val;
>> -ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
>> -KSZ9131RN_RXC_DLL_CTRL, val);
>> -if (ret)
>> +ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
>> + KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
>> + rxcdll_val);
>> +if (ret < 0)
>>  return ret;
>>   
>> -val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
>> -   KSZ9131RN_TXC_DLL_CTRL);
>> -
>> -val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
>> -val |= txcdll_val;
>> -ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
>> -KSZ9131RN_TXC_DLL_CTRL, val);
>> -
>> -return ret;
>> +return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
>> +  KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
>> +  txcdll_val);
>>   }
> Can't you set both bitfields at the same time ? They seem to be in the 
> same register.

These writes are to two different registers (KSZ9131RN_RXC_DLL_CTRL and
KSZ9131RN_TXC_DLL_CTRL), using the same bitmask in both cases
(KSZ9131RN_DLL_CTRL_BYPASS).

Thanks,

-- 
Paul Barker

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Re: [PATCH 04/14] pinctrl: rzg2l: Drop unnecessary scope

[Paul Barker]

On 27/10/2024 16:16, Marek Vasut wrote:
> On 10/24/24 5:24 PM, Paul Barker wrote:
>> In rzg2l_pinconf_set(), there are no new variables defined in the case
>> statement for PIN_CONFIG_INPUT_ENABLE so no additional scope is needed.
>>
>> Signed-off-by: Paul Barker 
> Reviewed-by: Marek Vasut 
> 
> btw. it might make sense to split the series per subsystem so it can go 
> in piece by piece.

I could split this into clk (patch 1), pinctrl (patch 2-4), Ethernet phy
(patch 5-8) and ravb prep patches (9-10), sent as independent series.
The support for RZ/G2L Ethernet (patches 11 & 12) would have to wait
until all those series are merged. The devicetree changes (patches 13 &
14) could be sent once the pinctrl patches are merged.

I think that this would delay things and prevent RZ/G2L Ethernet support
from landing in v2024.01, so I sent this as one series. I can break it
up if needed though. Let me know what you would prefer.

Thanks,

-- 
Paul Barker

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Re: [PATCH 03/14] pinctrl: rzg2l: Support Ethernet TXC output enable

[Paul Barker]

On 27/10/2024 16:15, Marek Vasut wrote:
> On 10/24/24 5:24 PM, Paul Barker wrote:
>> On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
>> signal is selectable to support an Ethernet PHY operating in either MII
>> or RGMII mode. By default, the signal is configured as an input and MII
>> mode is supported. The ETH_MODE register can be modified to configure
>> this signal as an output to support RGMII mode.
>>
>> As this signal is be default an input, and can optionally be switched to
>> an output, it maps neatly onto an `output-enable` property in the device
>> tree.
>>
>> Signed-off-by: Paul Barker 
> Same comment as on 2/14 regarding kernel commits.

This was re-implemented in U-Boot due to differences between the
existing RZ/G2L pinctrl code in Linux and U-Boot.

> 
> Is this something which should be configured in DT instead ?

This patch adds support for configuring it in the DT, using the
'output-enable' property. You can see this used later in this series in
the device tree patch to enable Ethernet TXC output [1].

[1]: https://msgid.link/20241024152448.102-14-paul.barker...@bp.renesas.com

Thanks,

-- 
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Re: [PATCH 02/14] pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces

[Paul Barker]

On 27/10/2024 16:14, Marek Vasut wrote:
> On 10/24/24 5:24 PM, Paul Barker wrote:
>> The Ethenet interfaces on the Renesas RZ/G2L SoC family can operate at
>> multiple power supply voltages: 3.3V (default value), 2.5V and 1.8V.
>>
>> rzg2l_pinconf_set() is extended to support the 2.5V setting, with a
>> check to ensure this is only used on Ethernet interfaces as it is not
>> supported on the SD & QSPI interfaces.
>>
>> While we're modifying rzg2l_pinconf_set(), drop the unnecessary default
>> value for pwr_reg as it is set in every branch of the following if
>> condition.
>>
>> Signed-off-by: Paul Barker 
> Is this ported from Linux ? If so, please include the Linux kernel 
> commit in the commit message, else ignore this comment.

This was re-implemented in U-Boot instead of porting Linux commits
(51996952b8b50 and cd27553b0dee6) due to differences between the
existing RZ/G2L pinctrl code in Linux and U-Boot.

Thanks,

-- 
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Re: [PATCH 2/2] ARM: renesas: Drop old unused power DT headers

[Paul Barker]

On 27/10/2024 02:04, Marek Vasut wrote:
> Renesas R-Car systems use mainline Linux DTs for U-Boot via OF_UPSTREAM,
> which also includes headers from dts/upstream/include/dt-bindings/power .
> Remove unused legacy DT header files from include/dt-bindings/power .
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: "Cogent Embedded, Inc." 
> Cc: Adam Ford 
> Cc: Biju Das 
> Cc: Hai Pham 
> Cc: Heinrich Schuchardt 
> Cc: Lad Prabhakar 
> Cc: Masakazu Mochizuki 
> Cc: Nobuhiro Iwamatsu 
> Cc: Paul Barker 
> Cc: Sumit Garg 
> Cc: Tom Rini 
> Cc: u-boot@lists.denx.de

Reviewed-by: Paul Barker 

Thanks!

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Re: [PATCH 1/2] ARM: renesas: Drop old unused clock DT headers

[Paul Barker]

On 27/10/2024 02:04, Marek Vasut wrote:
> Renesas R-Car systems use mainline Linux DTs for U-Boot via OF_UPSTREAM,
> which also includes headers from dts/upstream/include/dt-bindings/clock .
> Remove unused legacy DT header files from include/dt-bindings/clock .
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: "Cogent Embedded, Inc." 
> Cc: Adam Ford 
> Cc: Biju Das 
> Cc: Hai Pham 
> Cc: Heinrich Schuchardt 
> Cc: Lad Prabhakar 
> Cc: Masakazu Mochizuki 
> Cc: Nobuhiro Iwamatsu 
> Cc: Paul Barker 
> Cc: Sumit Garg 
> Cc: Tom Rini 
> Cc: u-boot@lists.denx.de

Reviewed-by: Paul Barker 

Thanks!

-- 
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Re: [PATCH v2] ARM: renesas: Add top level board/renesas/ MAINTAINERS file

[Paul Barker]

On 27/10/2024 02:10, Marek Vasut wrote:
> Add top level board/renesas/ MAINTAINERS file to catch all the common
> Renesas file patterns and put people on CC via get_maintainer.pl script.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Nobuhiro Iwamatsu 
> Cc: Tom Rini 
> Cc: u-boot@lists.denx.de
> ---
> V2: - Replace boards with board in commit message
> - Add rzg2l and r9a0

Reviewed-by: Paul Barker 

Thanks!

-- 
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[PATCH 05/14] net: phy: Port set/clear bits from Linux

[Paul Barker]

To simply porting phy drivers from Linux to U-Boot, define
phy_set_bits() and phy_clear_bits() functions with a similar API to
those used in Linux.

The U-Boot versions of these functions include the `devad` argument
which is not present in the Linux versions, to keep them aligned with
the other phy functions in U-Boot.

Signed-off-by: Paul Barker 
---
 include/phy.h | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/include/phy.h b/include/phy.h
index 36785031eeb0..510b0a21831b 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -333,6 +333,28 @@ int gen10g_startup(struct phy_device *phydev);
 int gen10g_shutdown(struct phy_device *phydev);
 int gen10g_discover_mmds(struct phy_device *phydev);
 
+/**
+ * phy_set_bits - Convenience function for setting bits in a PHY register
+ * @phydev: the phy_device struct
+ * @regnum: register number to write
+ * @val: bits to set
+ */
+static inline int phy_set_bits(struct phy_device *phydev, int devad, u32 
regnum, u16 val)
+{
+   return phy_modify(phydev, devad, regnum, 0, val);
+}
+
+/**
+ * phy_clear_bits - Convenience function for clearing bits in a PHY register
+ * @phydev: the phy_device struct
+ * @regnum: register number to write
+ * @val: bits to clear
+ */
+static inline int phy_clear_bits(struct phy_device *phydev, int devad, u32 
regnum, u16 val)
+{
+   return phy_modify(phydev, devad, regnum, val, 0);
+}
+
 /**
  * U_BOOT_PHY_DRIVER() - Declare a new U-Boot driver
  * @__name: name of the driver
-- 
2.43.0

[PATCH 06/14] net: phy: ksz90x1: Handle ksz9131 LED errata

[Paul Barker]

Micrel KSZ9131 PHY LED behavior is not correct when configured in
Individual Mode, LED1 (Activity LED) is in the ON state when there is
no-link.

Workaround this by setting bit 9 of register 0x1e after verifying that
the LED configuration is Individual Mode.

This issue is described in KSZ9131RNX Silicon Errata DS8693B [*]
and according to that it will not be corrected in a future silicon
revision.

[*] 
https://ww1.microchip.com/downloads/en/DeviceDoc/KSZ9131RNX-Silicon-Errata-and-Data-Sheet-Clarification-8863B.pdf

Based on commit 0316c7e66bbd in the Linux kernel.

Signed-off-by: Paul Barker 
---
 drivers/net/phy/micrel_ksz90x1.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index c48ae6e88f30..4f99b115a3c7 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -436,6 +436,26 @@ static int ksz9131_config_rgmii_delay(struct phy_device 
*phydev)
return ret;
 }
 
+/* Silicon Errata DS8693B
+ *
+ * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
+ * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
+ * according to the datasheet (off if there is no link).
+ */
+static int ksz9131_led_errata(struct phy_device *phydev)
+{
+   int reg;
+
+   reg = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 0);
+   if (reg < 0)
+   return reg;
+
+   if (!(reg & BIT(4)))
+   return 0;
+
+   return phy_set_bits(phydev, MDIO_DEVAD_NONE, 0x1e, BIT(9));
+}
+
 static int ksz9131_config(struct phy_device *phydev)
 {
int ret;
@@ -446,6 +466,10 @@ static int ksz9131_config(struct phy_device *phydev)
return ret;
}
 
+   ret = ksz9131_led_errata(phydev);
+   if (ret < 0)
+   return ret;
+
/* add an option to disable the gigabit feature of this PHY */
if (env_get("disable_giga")) {
unsigned features;
-- 
2.43.0

[PATCH 04/14] pinctrl: rzg2l: Drop unnecessary scope

[Paul Barker]

In rzg2l_pinconf_set(), there are no new variables defined in the case
statement for PIN_CONFIG_INPUT_ENABLE so no additional scope is needed.

Signed-off-by: Paul Barker 
---
 drivers/pinctrl/renesas/rzg2l-pfc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c 
b/drivers/pinctrl/renesas/rzg2l-pfc.c
index af371bd0ff1e..3c751e9473a5 100644
--- a/drivers/pinctrl/renesas/rzg2l-pfc.c
+++ b/drivers/pinctrl/renesas/rzg2l-pfc.c
@@ -381,7 +381,7 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned 
int pin_selector,
}
 
switch (param) {
-   case PIN_CONFIG_INPUT_ENABLE: {
+   case PIN_CONFIG_INPUT_ENABLE:
if (!(cfg & PIN_CFG_IEN)) {
dev_err(dev, "pin does not support IEN\n");
return -EINVAL;
@@ -391,7 +391,6 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned 
int pin_selector,
port_offset, pin, argument);
rzg2l_rmw_pin_config(data, IEN(port_offset), pin, IEN_MASK, 
!!argument);
break;
-   }
 
case PIN_CONFIG_POWER_SOURCE: {
bool support_2500 = false;
-- 
2.43.0

[PATCH 03/14] pinctrl: rzg2l: Support Ethernet TXC output enable

[Paul Barker]

On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
signal is selectable to support an Ethernet PHY operating in either MII
or RGMII mode. By default, the signal is configured as an input and MII
mode is supported. The ETH_MODE register can be modified to configure
this signal as an output to support RGMII mode.

As this signal is be default an input, and can optionally be switched to
an output, it maps neatly onto an `output-enable` property in the device
tree.

Signed-off-by: Paul Barker 
---
 drivers/pinctrl/renesas/rzg2l-pfc.c | 31 +++--
 include/renesas/rzg2l-pfc.h |  2 ++
 2 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c 
b/drivers/pinctrl/renesas/rzg2l-pfc.c
index 0098e2d52d57..af371bd0ff1e 100644
--- a/drivers/pinctrl/renesas/rzg2l-pfc.c
+++ b/drivers/pinctrl/renesas/rzg2l-pfc.c
@@ -180,7 +180,7 @@ static const u32 r9a07g044_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
-   RZG2L_GPIO_PORT_PACK(3, 0x24, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+   RZG2L_GPIO_PORT_PACK(3, 0x24, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
RZG2L_GPIO_PORT_PACK(2, 0x25, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x26, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x27, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
@@ -189,7 +189,7 @@ static const u32 r9a07g044_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(2, 0x2a, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x2b, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x2c, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
-   RZG2L_GPIO_PORT_PACK(2, 0x2d, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+   RZG2L_GPIO_PORT_PACK(2, 0x2d, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
RZG2L_GPIO_PORT_PACK(2, 0x2e, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
RZG2L_GPIO_PORT_PACK(2, 0x2f, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
RZG2L_GPIO_PORT_PACK(2, 0x30, 
RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -449,6 +449,32 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned 
int pin_selector,
break;
}
 
+   case PIN_CONFIG_OUTPUT_ENABLE: {
+   u8 ch;
+
+   if (!(cfg & PIN_CFG_OEN)) {
+   dev_err(dev, "pin does not support OEN\n");
+   return -EINVAL;
+   }
+
+   /*
+* We can determine which Ethernet interface we're dealing with 
from
+* the caps.
+*/
+   if (cfg & PIN_CFG_IO_VMC_ETH0)
+   ch = 0;
+   else /* PIN_CFG_IO_VMC_ETH1 */
+   ch = 1;
+
+   dev_dbg(dev, "set ETH%u TXC OEN=%u\n", ch, argument);
+   if (argument)
+   clrbits_8(data->base + ETH_MODE, BIT(ch));
+   else
+   setbits_8(data->base + ETH_MODE, BIT(ch));
+
+   break;
+   }
+
default:
dev_err(dev, "Invalid pinconf parameter\n");
return -EOPNOTSUPP;
@@ -542,6 +568,7 @@ static int rzg2l_get_pin_muxing(struct udevice *dev, 
unsigned int selector,
 
 static const struct pinconf_param rzg2l_pinconf_params[] = {
{ "input-enable",   PIN_CONFIG_INPUT_ENABLE,1 },
+   { "output-enable",  PIN_CONFIG_OUTPUT_ENABLE,   1 },
{ "power-source",   PIN_CONFIG_POWER_SOURCE,3300 /* mV */ },
 };
 
diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h
index d1015b1d2ac1..36fa8da8e2e4 100644
--- a/include/renesas/rzg2l-pfc.h
+++ b/include/renesas/rzg2l-pfc.h
@@ -22,6 +22,7 @@
 #define PIN_CFG_FILONOFF   BIT(10)
 #define PIN_CFG_FILNUM BIT(11)
 #define PIN_CFG_FILCLKSEL  BIT(12)
+#define PIN_CFG_OENBIT(13)
 
 #define RZG2L_MPXED_PIN_FUNCS  (PIN_CFG_IOLH_A | \
 PIN_CFG_SR | \
@@ -79,6 +80,7 @@
 #define SD_CH(n)   (0x3000 + (n) * 4)
 #define ETH_POC(ch)(0x300c + (ch) * 4)
 #define QSPI   0x3008
+#define ETH_MODE   (0x3018)
 
 #define PVDD_1800  1   /* I/O domain voltage <= 1.8V */
 #define PVDD_2500  2   /* I/O domain voltage 2.5V */
-- 
2.43.0

[PATCH 02/14] pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces

[Paul Barker]

The Ethenet interfaces on the Renesas RZ/G2L SoC family can operate at
multiple power supply voltages: 3.3V (default value), 2.5V and 1.8V.

rzg2l_pinconf_set() is extended to support the 2.5V setting, with a
check to ensure this is only used on Ethernet interfaces as it is not
supported on the SD & QSPI interfaces.

While we're modifying rzg2l_pinconf_set(), drop the unnecessary default
value for pwr_reg as it is set in every branch of the following if
condition.

Signed-off-by: Paul Barker 
---
 drivers/pinctrl/renesas/rzg2l-pfc.c | 49 -
 include/renesas/rzg2l-pfc.h |  2 ++
 2 files changed, 37 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c 
b/drivers/pinctrl/renesas/rzg2l-pfc.c
index e88ec1c18373..0098e2d52d57 100644
--- a/drivers/pinctrl/renesas/rzg2l-pfc.c
+++ b/drivers/pinctrl/renesas/rzg2l-pfc.c
@@ -394,18 +394,10 @@ static int rzg2l_pinconf_set(struct udevice *dev, 
unsigned int pin_selector,
}
 
case PIN_CONFIG_POWER_SOURCE: {
-   u32 pwr_reg = 0x0;
+   bool support_2500 = false;
+   u32 pwr_reg;
+   u32 value;
 
-   /* argument is in mV */
-   if (argument != 1800 && argument != 3300) {
-   dev_err(dev, "Invalid mV %u\n", argument);
-   return -EINVAL;
-   }
-
-   /*
-* TODO: PIN_CFG_IO_VMC_ETH0 & PIN_CFG_IO_VMC_ETH1 will be
-* handled when the RZ/G2L Ethernet driver is added.
-*/
if (cfg & PIN_CFG_IO_VMC_SD0) {
dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n",
port_offset, pin, argument);
@@ -418,13 +410,42 @@ static int rzg2l_pinconf_set(struct udevice *dev, 
unsigned int pin_selector,
dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n",
port_offset, pin, argument);
pwr_reg = QSPI;
+   } else if (cfg & PIN_CFG_IO_VMC_ETH0) {
+   dev_dbg(dev, "port off %u:%u set ETH0 PVDD=%u\n",
+   port_offset, pin, argument);
+   pwr_reg = ETH_POC(0);
+   support_2500 = true;
+   } else if (cfg & PIN_CFG_IO_VMC_ETH1) {
+   dev_dbg(dev, "port off %u:%u set ETH1 PVDD=%u\n",
+   port_offset, pin, argument);
+   pwr_reg = ETH_POC(1);
+   support_2500 = true;
} else {
-   dev_dbg(dev, "pin power source is not selectable\n");
+   dev_dbg(dev, "port off %u:%u PVDD is not selectable\n",
+   port_offset, pin);
+   return -EINVAL;
+   }
+
+   /* argument is in mV */
+   switch (argument) {
+   case 1800:
+   value = PVDD_1800;
+   break;
+   case 3300:
+   value = PVDD_3300;
+   break;
+   case 2500:
+   if (support_2500) {
+   value = PVDD_2500;
+   break;
+   }
+   fallthrough;
+   default:
+   dev_err(dev, "Invalid mV %u\n", argument);
return -EINVAL;
}
 
-   writel((argument == 1800) ? PVDD_1800 : PVDD_3300,
-  data->base + pwr_reg);
+   writel(value, data->base + pwr_reg);
break;
}
 
diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h
index 2df17ece2a31..d1015b1d2ac1 100644
--- a/include/renesas/rzg2l-pfc.h
+++ b/include/renesas/rzg2l-pfc.h
@@ -77,9 +77,11 @@
 #define IEN(n) (0x1800 + (n) * 8)
 #define PWPR   0x3014
 #define SD_CH(n)   (0x3000 + (n) * 4)
+#define ETH_POC(ch)(0x300c + (ch) * 4)
 #define QSPI   0x3008
 
 #define PVDD_1800  1   /* I/O domain voltage <= 1.8V */
+#define PVDD_2500  2   /* I/O domain voltage 2.5V */
 #define PVDD_3300  0   /* I/O domain voltage >= 3.3V */
 
 #define PWPR_B0WI  BIT(7)  /* Bit Write Disable */
-- 
2.43.0

[PATCH 09/14] net: ravb: Support up to two instances

[Paul Barker]

Several Renesas SoCs in the RZ/G2L family have two Ethernet interfaces.
To support this second interface, we extend the bb_miiphy_buses[] array
and keep track of the current bus index in ravb_of_to_plat().

Support for an arbitrary number of instances is not implemented - it is
expected that bb_miiphy_buses will be replaced with a proper device
model/uclass implementation before that is needed.

Signed-off-by: Paul Barker 
---
 drivers/net/ravb.c | 28 
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index f1401d2f6ed2..9b33ce929618 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -494,6 +495,7 @@ static int ravb_probe(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_plat(dev);
struct ravb_priv *eth = dev_get_priv(dev);
+   struct bb_miiphy_bus *phybus;
struct mii_dev *mdiodev;
void __iomem *iobase;
int ret;
@@ -513,7 +515,8 @@ static int ravb_probe(struct udevice *dev)
 
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
-   bb_miiphy_buses[0].priv = eth;
+   phybus = (struct bb_miiphy_bus *)pdata->priv_pdata;
+   phybus->priv = eth;
snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
 
ret = mdio_register(mdiodev);
@@ -625,7 +628,17 @@ int ravb_bb_delay(struct bb_miiphy_bus *bus)
 
 struct bb_miiphy_bus bb_miiphy_buses[] = {
{
-   .name   = "ravb",
+   .name   = "ravb0",
+   .init   = ravb_bb_init,
+   .mdio_active= ravb_bb_mdio_active,
+   .mdio_tristate  = ravb_bb_mdio_tristate,
+   .set_mdio   = ravb_bb_set_mdio,
+   .get_mdio   = ravb_bb_get_mdio,
+   .set_mdc= ravb_bb_set_mdc,
+   .delay  = ravb_bb_delay,
+   },
+   {
+   .name   = "ravb1",
.init   = ravb_bb_init,
.mdio_active= ravb_bb_mdio_active,
.mdio_tristate  = ravb_bb_mdio_tristate,
@@ -646,10 +659,16 @@ static const struct eth_ops ravb_ops = {
.write_hwaddr   = ravb_write_hwaddr,
 };
 
+static int bb_miiphy_index;
+
 int ravb_of_to_plat(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_plat(dev);
-   const fdt32_t *cell;
+
+   if (bb_miiphy_index >= bb_miiphy_buses_num) {
+   dev_err(dev, "ravb driver supports only 1 or 2 devices!\n");
+   return -EOVERFLOW;
+   }
 
pdata->iobase = dev_read_addr(dev);
 
@@ -662,7 +681,8 @@ int ravb_of_to_plat(struct udevice *dev)
if (cell)
pdata->max_speed = fdt32_to_cpu(*cell);
 
-   sprintf(bb_miiphy_buses[0].name, dev->name);
+   pdata->priv_pdata = &bb_miiphy_buses[bb_miiphy_index];
+   sprintf(bb_miiphy_buses[bb_miiphy_index++].name, dev->name);
 
return 0;
 }
-- 
2.43.0

[PATCH 07/14] net: phy: ksz90x1: Load skew values from device tree

[Paul Barker]

Various signal skew values may be set in the device tree for the ksz9131
Ethernet PHY. For example, the RZ/G2L board requires non-default values
for rxc-skew-psec & txc-skew-psec.

This is based on the ksz9131 phy driver in Linux v6.11.

Signed-off-by: Paul Barker 
---
 drivers/net/phy/micrel_ksz90x1.c | 115 +++
 1 file changed, 115 insertions(+)

diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index 4f99b115a3c7..b64046e0bc72 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -389,6 +389,117 @@ U_BOOT_PHY_DRIVER(ksz9031) = {
 #define KSZ9131RN_DLL_ENABLE_DELAY 0
 #define KSZ9131RN_DLL_DISABLE_DELAYBIT(12)
 
+#define KSZ9131RN_CONTROL_PAD_SKEW 4
+#define KSZ9131RN_RX_DATA_PAD_SKEW 5
+#define KSZ9131RN_TX_DATA_PAD_SKEW 6
+#define KSZ9131RN_CLK_PAD_SKEW 8
+
+#define KSZ9131RN_SKEW_5BIT_MAX2400
+#define KSZ9131RN_SKEW_4BIT_MAX800
+#define KSZ9131RN_OFFSET   700
+#define KSZ9131RN_STEP 100
+
+static int ksz9131_of_load_skew_values(struct phy_device *phydev,
+  ofnode of_node,
+  u16 reg, size_t field_sz,
+  const char *field[], u8 numfields)
+{
+   int val[4] = {-(1 + KSZ9131RN_OFFSET), -(2 + KSZ9131RN_OFFSET),
+ -(3 + KSZ9131RN_OFFSET), -(4 + KSZ9131RN_OFFSET)};
+   int skewval, skewmax = 0;
+   int matches = 0;
+   u16 maxval;
+   u16 newval;
+   u16 mask;
+   int i;
+
+   /* psec properties in dts should mean x pico seconds */
+   if (field_sz == 5)
+   skewmax = KSZ9131RN_SKEW_5BIT_MAX;
+   else
+   skewmax = KSZ9131RN_SKEW_4BIT_MAX;
+
+   for (i = 0; i < numfields; i++)
+   if (!ofnode_read_s32(of_node, field[i], &skewval)) {
+   if (skewval < -KSZ9131RN_OFFSET)
+   skewval = -KSZ9131RN_OFFSET;
+   else if (skewval > skewmax)
+   skewval = skewmax;
+
+   val[i] = skewval + KSZ9131RN_OFFSET;
+   matches++;
+   }
+
+   if (!matches)
+   return 0;
+
+   if (matches < numfields)
+   newval = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, 
reg);
+   else
+   newval = 0;
+
+   maxval = (field_sz == 4) ? 0xf : 0x1f;
+   for (i = 0; i < numfields; i++)
+   if (val[i] != -(i + 1 + KSZ9131RN_OFFSET)) {
+   mask = 0x;
+   mask ^= maxval << (field_sz * i);
+   newval = (newval & mask) |
+   (((val[i] / KSZ9131RN_STEP) & maxval)
+   << (field_sz * i));
+   }
+
+   return phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg, 
newval);
+}
+
+static int ksz9131_of_load_all_skew_values(struct phy_device *phydev)
+{
+   const char *control_skews[2] = { "txen-skew-psec", "rxdv-skew-psec" };
+   const char *clk_skews[2] = { "rxc-skew-psec", "txc-skew-psec" };
+   const char *rx_data_skews[4] = {
+   "rxd0-skew-psec", "rxd1-skew-psec",
+   "rxd2-skew-psec", "rxd3-skew-psec"
+   };
+   const char *tx_data_skews[4] = {
+   "txd0-skew-psec", "txd1-skew-psec",
+   "txd2-skew-psec", "txd3-skew-psec"
+   };
+   struct ofnode_phandle_args phandle_args;
+   int ret;
+
+   /*
+* Silently ignore failure here as the device tree is not required to
+* contain a phy node.
+*/
+   if (dev_read_phandle_with_args(phydev->dev, "phy-handle", NULL, 0, 0,
+  &phandle_args))
+   return 0;
+
+   if (!ofnode_valid(phandle_args.node))
+   return 0;
+
+   ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_CLK_PAD_SKEW, 5,
+ clk_skews, 2);
+   if (ret < 0)
+   return ret;
+
+   ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_CONTROL_PAD_SKEW, 4,
+ control_skews, 2);
+   if (ret < 0)
+   return ret;
+
+   ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_RX_DATA_PAD_SKEW, 4,
+ rx_data_skews, 4);
+   if (ret < 0)
+   return ret;
+
+   return ksz9131_of_load_sk

[PATCH 01/14] clk: rzg2l: Ignore enable for core clocks

[Paul Barker]

In the RZ/G2L family, core clocks are always on and can't be disabled.
However, drivers which are shared with other SoCs may call clk_enable()
or clk_enable_bulk() for a clock referenced in the device tree which
happens to be a core clock on the RZ/G2L. To avoid the need for
conditionals in these drivers, simply ignore attempts to enable a core
clock.

Signed-off-by: Paul Barker 
---
 drivers/clk/renesas/rzg2l-cpg.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index c8735d869cf9..3c5340df8eed 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -69,7 +69,15 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
 
dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable",
is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id);
+
if (!is_mod_clk(clk->id)) {
+   /*
+* Non-module clocks are always on. Ignore attempts to enable
+* them and reject attempts to disable them.
+*/
+   if (enable)
+   return 0;
+
dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id);
return -EINVAL;
}
-- 
2.43.0

Re: [PATCH 13/14] arm64: dts: renesas: rzg2l: Enable Ethernet TXC output

[Paul Barker]

On 24/10/2024 16:24, Paul Barker wrote:
> Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/[GV]2L SMARC
> SoMs, as per RGMII specification.
> 
> Signed-off-by: Paul Barker 
> Reviewed-by: Geert Uytterhoeven 
> Acked-by: Linus Walleij 
> Link: 
> https://lore.kernel.org/20240625200316.4282-5-paul.barker...@bp.renesas.com
> Signed-off-by: Geert Uytterhoeven 
> 
> [ upstream commit: 41c934da488d3a5a79148ead3b5c5eecac1b1d5d ]
> 
> (cherry picked from commit 11cbf7bc3124f3d5267ea6aef8e4ba6d6b4f589e)

Apologies Geert and Linus W, this and the following patch are for
U-Boot. `git send-email` Cc'd you based on the Reviewed-by & Acked-by
tags. You can safely ignore these :)

I'll see if I can add some notes to the relevant U-Boot docs [1] [2] to
use the `--no-signed-off-cc` argument to `git send-email` for such
patches, so that myself and others hopefully don't make the same mistake
in the future.

[1]: 
https://docs.u-boot.org/en/latest/develop/process.html#resyncing-of-the-device-tree-subtree
[2]: 
https://docs.u-boot.org/en/latest/develop/devicetree/control.html#resyncing-with-devicetree-rebasing

Thanks,

-- 
Paul Barker

OpenPGP_0x27F4B3459F002257.asc
Description: OpenPGP public key


OpenPGP_signature.asc
Description: OpenPGP digital signature

[PATCH 14/14] arm64: dts: renesas: rzg2l: Set Ethernet PVDD to 1.8V

[Paul Barker]

On the RZ/G2L & RZ/V2L SMARC SOMs, the RGMII interface between the SoC
and the Ethernet PHY operates at 1.8V.

The power supply for this interface may be correctly configured in
u-boot, but the kernel should not be relying on this. Now that the
RZ/G2L pinctrl driver supports configuring the Ethernet power supply
voltage, we can simply specify the desired voltage in the device tree.

Signed-off-by: Paul Barker 
Reviewed-by: Geert Uytterhoeven 
Acked-by: Linus Walleij 
Link: 
https://lore.kernel.org/20240625200316.4282-8-paul.barker...@bp.renesas.com
Signed-off-by: Geert Uytterhoeven 

[ upstream commit: 96a3f525708120379013d9d3265663c07ceb38d5 ]

(cherry picked from commit c535103b52a1edf50309dcbd1948d56520e84a1e)
---
 .../src/arm64/renesas/rzg2l-smarc-som.dtsi | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi 
b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi
index 2b5e037ea9fa..83f5642d0d35 100644
--- a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi
@@ -182,6 +182,7 @@
eth0_pins: eth0 {
txc {
pinmux = ; /* ET0_TXC */
+   power-source = <1800>;
output-enable;
};
 
@@ -199,14 +200,19 @@
 , /* ET0_RXD0 */
 , /* ET0_RXD1 */
 , /* ET0_RXD2 */
-, /* ET0_RXD3 */
-;  /* IRQ2 */
+; /* ET0_RXD3 */
+   power-source = <1800>;
+   };
+
+   irq {
+   pinmux = ;  /* IRQ2 */
};
};
 
eth1_pins: eth1 {
txc {
pinmux = ; /* ET1_TXC */
+   power-source = <1800>;
output-enable;
};
 
@@ -224,8 +230,12 @@
 , /* ET1_RXD0 */
 , /* ET1_RXD1 */
 , /* ET1_RXD2 */
-, /* ET1_RXD3 */
-;  /* IRQ3 */
+; /* ET1_RXD3 */
+   power-source = <1800>;
+   };
+
+   irq {
+   pinmux = ;  /* IRQ3 */
};
};
 
-- 
2.43.0

[PATCH 12/14] renesas_rzg2l_smarc_defconfig: Enable networking support

[Paul Barker]

For Ethernet to work on the RZ/G2L board, we need to enable support for
the ksz9131 PHY and enable random MAC address generation (as no MAC
address is programmed into the board).

We also enable the `dhcp`, `mii` and `ping` commands so that Ethernet
functionality can be tested and used to boot Linux.

Signed-off-by: Paul Barker 
---
 configs/renesas_rzg2l_smarc_defconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index 7a1224b3f07a..991818e797ea 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -26,6 +26,9 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -40,6 +43,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=2
 CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
@@ -49,6 +53,8 @@ CONFIG_DM_I2C=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RAA215300=y
 CONFIG_DM_REGULATOR=y
-- 
2.43.0

[PATCH 11/14] net: ravb: Add RZ/G2L Support

[Paul Barker]

The Renesas R9A07G044L (RZ/G2L) SoC includes two Gigabit Ethernet
interfaces which can be supported using the ravb driver. Some RZ/G2L
specific steps need to be taken during initialization due to differences
between this SoC and previously supported SoCs. We also need to ensure
that the module reset is de-asserted after the module clock is enabled
but before any Ethernet register reads/writes take place.

Signed-off-by: Paul Barker 
---
 arch/arm/mach-renesas/Kconfig |   1 +
 drivers/net/Kconfig   |   2 +
 drivers/net/ravb.c| 183 --
 3 files changed, 176 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig
index aeb55da609bd..d373ab56ce91 100644
--- a/arch/arm/mach-renesas/Kconfig
+++ b/arch/arm/mach-renesas/Kconfig
@@ -76,6 +76,7 @@ config RZG2L
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
imply PINCTRL_RZG2L
+   imply RENESAS_RAVB
imply RENESAS_SDHI
imply RZG2L_GPIO
imply SCIF_CONSOLE
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 89f7411bdf33..d009acdcd94f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -822,6 +822,8 @@ config RENESAS_RAVB
depends on RCAR_64
select PHYLIB
select PHY_ETHERNET_ID
+   select BITBANGMII
+   select BITBANGMII_MULTI
help
  This driver implements support for the Ethernet AVB block in
  Renesas M3 and H3 SoCs.
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index fb869cd0872e..e2ab929858c8 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* Registers */
 #define RAVB_REG_CCC   0x000
@@ -31,12 +32,14 @@
 #define RAVB_REG_CSR   0x00C
 #define RAVB_REG_APSR  0x08C
 #define RAVB_REG_RCR   0x090
+#define RAVB_REG_RTC   0x0B4
 #define RAVB_REG_TGC   0x300
 #define RAVB_REG_TCCR  0x304
 #define RAVB_REG_RIC0  0x360
 #define RAVB_REG_RIC1  0x368
 #define RAVB_REG_RIC2  0x370
 #define RAVB_REG_TIC   0x378
+#define RAVB_REG_RIC3  0x388
 #define RAVB_REG_ECMR  0x500
 #define RAVB_REG_RFLR  0x508
 #define RAVB_REG_ECSIPR0x518
@@ -44,6 +47,7 @@
 #define RAVB_REG_GECMR 0x5b0
 #define RAVB_REG_MAHR  0x5c0
 #define RAVB_REG_MALR  0x5c8
+#define RAVB_REG_CSR0  0x800
 
 #define CCC_OPC_CONFIG BIT(0)
 #define CCC_OPC_OPERATION  BIT(1)
@@ -65,14 +69,24 @@
 #define PIR_MDCBIT(0)
 
 #define ECMR_TRCCM BIT(26)
+#define ECMR_RCPT  BIT(25)
 #define ECMR_RZPF  BIT(20)
 #define ECMR_PFR   BIT(18)
 #define ECMR_RXF   BIT(17)
+#define ECMR_TXF   BIT(16)
 #define ECMR_REBIT(6)
 #define ECMR_TEBIT(5)
 #define ECMR_DMBIT(1)
+#define ECMR_PRM   BIT(0)
 #define ECMR_CHG_DM(ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
 
+#define CSR0_RPE   BIT(5)
+#define CSR0_TPE   BIT(4)
+
+#define GECMR_SPEED_10M(0 << 4)
+#define GECMR_SPEED_100M   (1 << 4)
+#define GECMR_SPEED_1G (2 << 4)
+
 /* DMA Descriptors */
 #define RAVB_NUM_BASE_DESC 16
 #define RAVB_NUM_TX_DESC   8
@@ -108,6 +122,16 @@
 
 #define RAVB_TX_TIMEOUT_MS 1000
 
+#define RAVB_RCV_BUFF_MAX  8192
+
+struct ravb_device_ops {
+   int (*mac_init)(struct udevice *dev);
+   int (*dmac_init)(struct udevice *dev);
+   int (*config)(struct udevice *dev);
+   int (*reset_deassert)(struct udevice *dev);
+   void (*reset_assert)(struct udevice *dev);
+};
+
 struct ravb_desc {
u32 ctrl;
u32 dptr;
@@ -131,6 +155,7 @@ struct ravb_priv {
struct mii_dev  *bus;
void __iomem*iobase;
struct clk_bulk clks;
+   struct reset_ctlrst;
 };
 
 static inline void ravb_flush_dcache(u32 addr, u32 len)
@@ -350,8 +375,25 @@ static int ravb_write_hwaddr(struct udevice *dev)
 }
 
 /* E-MAC init function */
-static int ravb_mac_init(struct ravb_priv *eth)
+static int ravb_mac_init_rzg2l(struct udevice *dev)
 {
+   struct ravb_priv *eth = dev_get_priv(dev);
+
+   setbits_32(eth->iobase + RAVB_REG_ECMR,
+  ECMR_PRM | ECMR_RXF | ECMR_TXF | ECMR_RCPT |
+  ECMR_TE | ECMR_RE | ECMR_RZPF |
+  (eth->phydev->duplex ? ECMR_DM : 0));
+
+   /* Recv frame limit set register */
+   writel(RAVB_RCV_BUFF_MAX + ETH_FCS_LEN, eth->iobase + RAVB_REG_RFLR);
+
+   return 0;
+}
+
+static int ravb_mac_init_rcar(struct udevice *dev)
+{
+   struct ravb_priv *eth = dev_get_priv(dev);
+
/* Disable MAC Interrupt */

[PATCH 10/14] net: ravb: Simplify max-speed handling in ravb_of_to_plat

[Paul Barker]

We can call dev_read_u32_default() instead of calling fdt_getprop() then
fdt32_to_cpu().

Signed-off-by: Paul Barker 
---
 drivers/net/ravb.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 9b33ce929618..fb869cd0872e 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -676,10 +676,7 @@ int ravb_of_to_plat(struct udevice *dev)
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
 
-   pdata->max_speed = 1000;
-   cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
-   if (cell)
-   pdata->max_speed = fdt32_to_cpu(*cell);
+   pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000);
 
pdata->priv_pdata = &bb_miiphy_buses[bb_miiphy_index];
sprintf(bb_miiphy_buses[bb_miiphy_index++].name, dev->name);
-- 
2.43.0

[PATCH 08/14] net: phy: ksz90x1: Simplify ksz9131_config_rgmii_delay

[Paul Barker]

We can call phy_modify_mmd() instead of manually calling drv->readext()
and drv->writeext().

Signed-off-by: Paul Barker 
---
 drivers/net/phy/micrel_ksz90x1.c | 26 --
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index b64046e0bc72..6515d8feb9be 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -502,8 +502,7 @@ static int ksz9131_of_load_all_skew_values(struct 
phy_device *phydev)
 
 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
 {
-   struct phy_driver *drv = phydev->drv;
-   u16 rxcdll_val, txcdll_val, val;
+   u16 rxcdll_val, txcdll_val;
int ret;
 
switch (phydev->interface) {
@@ -527,24 +526,15 @@ static int ksz9131_config_rgmii_delay(struct phy_device 
*phydev)
return 0;
}
 
-   val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-  KSZ9131RN_RXC_DLL_CTRL);
-   val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
-   val |= rxcdll_val;
-   ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-   KSZ9131RN_RXC_DLL_CTRL, val);
-   if (ret)
+   ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+rxcdll_val);
+   if (ret < 0)
return ret;
 
-   val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-  KSZ9131RN_TXC_DLL_CTRL);
-
-   val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
-   val |= txcdll_val;
-   ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-   KSZ9131RN_TXC_DLL_CTRL, val);
-
-   return ret;
+   return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+ txcdll_val);
 }
 
 /* Silicon Errata DS8693B
-- 
2.43.0

[PATCH 13/14] arm64: dts: renesas: rzg2l: Enable Ethernet TXC output

[Paul Barker]

Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/[GV]2L SMARC
SoMs, as per RGMII specification.

Signed-off-by: Paul Barker 
Reviewed-by: Geert Uytterhoeven 
Acked-by: Linus Walleij 
Link: 
https://lore.kernel.org/20240625200316.4282-5-paul.barker...@bp.renesas.com
Signed-off-by: Geert Uytterhoeven 

[ upstream commit: 41c934da488d3a5a79148ead3b5c5eecac1b1d5d ]

(cherry picked from commit 11cbf7bc3124f3d5267ea6aef8e4ba6d6b4f589e)
---
 .../src/arm64/renesas/rzg2l-smarc-som.dtsi| 76 +++
 1 file changed, 44 insertions(+), 32 deletions(-)

diff --git a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi 
b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi
index 4409c47239b9..2b5e037ea9fa 100644
--- a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi
@@ -180,41 +180,53 @@
};
 
eth0_pins: eth0 {
-   pinmux = , /* ET0_LINKSTA */
-, /* ET0_MDC */
-, /* ET0_MDIO */
-, /* ET0_TXC */
-, /* ET0_TX_CTL */
-, /* ET0_TXD0 */
-, /* ET0_TXD1 */
-, /* ET0_TXD2 */
-, /* ET0_TXD3 */
-, /* ET0_RXC */
-, /* ET0_RX_CTL */
-, /* ET0_RXD0 */
-, /* ET0_RXD1 */
-, /* ET0_RXD2 */
-, /* ET0_RXD3 */
-;  /* IRQ2 */
+   txc {
+   pinmux = ; /* ET0_TXC */
+   output-enable;
+   };
+
+   mux {
+   pinmux = , /* ET0_LINKSTA 
*/
+, /* ET0_MDC */
+, /* ET0_MDIO */
+, /* ET0_TX_CTL */
+, /* ET0_TXD0 */
+, /* ET0_TXD1 */
+, /* ET0_TXD2 */
+, /* ET0_TXD3 */
+, /* ET0_RXC */
+, /* ET0_RX_CTL */
+, /* ET0_RXD0 */
+, /* ET0_RXD1 */
+, /* ET0_RXD2 */
+, /* ET0_RXD3 */
+;  /* IRQ2 */
+   };
};
 
eth1_pins: eth1 {
-   pinmux = , /* ET1_LINKSTA */
-, /* ET1_MDC */
-, /* ET1_MDIO */
-, /* ET1_TXC */
-, /* ET1_TX_CTL */
-, /* ET1_TXD0 */
-, /* ET1_TXD1 */
-, /* ET1_TXD2 */
-, /* ET1_TXD3 */
-, /* ET1_RXC */
-, /* ET1_RX_CTL */
-, /* ET1_RXD0 */
-, /* ET1_RXD1 */
-, /* ET1_RXD2 */
-, /* ET1_RXD3 */
-;  /* IRQ3 */
+   txc {
+   pinmux = ; /* ET1_TXC */
+   output-enable;
+   };
+
+   mux {
+   pinmux = , /* ET1_LINKSTA 
*/
+, /* ET1_MDC */
+, /* ET1_MDIO */
+, /* ET1_TX_CTL */
+, /* ET1_TXD0 */
+, /* ET1_TXD1 */
+, /* ET1_TXD2 */
+, /* ET1_TXD3 */
+, /* ET1_RXC */
+, /* ET1_RX_CTL */
+, /* ET1_RXD0 */
+, /* ET1_RXD1 */
+, /* ET1_RXD2 */
+, /* ET1_RXD3 */
+;  /* IRQ3 */
+   };
};
 
gpio-sd0-pwr-en-hog {
-- 
2.43.0

[PATCH 00/14] Add support for Ethernet interfaces on RZ/G2L

[Paul Barker]

This patch series enables the usage of both Ethernet interfaces on the
Renesas RZ/G2L SMARC EVK board. This requires changes to the RZ/G2L
clock driver, RZ/G2L pinctrl driver, ksz9131 phy driver and ravb network
driver. Once all drivers have the required support, we enable the
relevant options in the RZ/G2L defconfig and cherry-pick required
devicetree changes from Linux v6.12-rc4.

Paul Barker (14):
  clk: rzg2l: Ignore enable for core clocks
  pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces
  pinctrl: rzg2l: Support Ethernet TXC output enable
  pinctrl: rzg2l: Drop unnecessary scope
  net: phy: Port set/clear bits from Linux
  net: phy: ksz90x1: Handle ksz9131 LED errata
  net: phy: ksz90x1: Load skew values from device tree
  net: phy: ksz90x1: Simplify ksz9131_config_rgmii_delay
  net: ravb: Support up to two instances
  net: ravb: Simplify max-speed handling in ravb_of_to_plat
  net: ravb: Add RZ/G2L Support
  renesas_rzg2l_smarc_defconfig: Enable networking support
  arm64: dts: renesas: rzg2l: Enable Ethernet TXC output
  arm64: dts: renesas: rzg2l: Set Ethernet PVDD to 1.8V

 arch/arm/mach-renesas/Kconfig |   1 +
 configs/renesas_rzg2l_smarc_defconfig |   6 +
 drivers/clk/renesas/rzg2l-cpg.c   |   8 +
 drivers/net/Kconfig   |   2 +
 drivers/net/phy/micrel_ksz90x1.c  | 161 +++--
 drivers/net/ravb.c| 216 --
 drivers/pinctrl/renesas/rzg2l-pfc.c   |  83 +--
 .../src/arm64/renesas/rzg2l-smarc-som.dtsi|  86 ---
 include/phy.h |  22 ++
 include/renesas/rzg2l-pfc.h   |   4 +
 10 files changed, 505 insertions(+), 84 deletions(-)

-- 
2.43.0

[PATCH v2] mmc: renesas-sdhi: Add compatible string for rzg2l-sdhi

[Paul Barker]

After the recent dts/upstream subtree merge, the sdhi compatible string
used in the device tree for RZ/G2L family SoCs is "renesas,rzg2l-sdhi"
not "renesas,rcar-gen3-sdhi". This broke the ability to access the eMMC
and SD card devices on RZ/G2L boards.

Fix this by adding the new compatible string to the sdhi driver.

Fixes: 136b7b6d2e98 ("Subtree merge tag 'v6.11-dts' of dts repo [1] into 
dts/upstream")
Reviewed-by: Jaehoon Chung 
Reviewed-by: Marek Vasut 
Signed-off-by: Paul Barker 
---
Changes v1->v2:
  - Moved new entry after "renesas,rcar-gen4-sdhi".
  - Added Reviewed-by tags.

 drivers/mmc/renesas-sdhi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 23db2a75c444..92afa6adcdac 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -864,6 +864,7 @@ static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
+   { .compatible = "renesas,rzg2l-sdhi", .data = RENESAS_GEN3_QUIRKS },
{ /* sentinel */ }
 };
 
-- 
2.43.0

Re: [PATCH] ARM: renesas: Add top level boards/renesas/ MAINTAINERS file

[Paul Barker]

On 22/10/2024 01:55, Marek Vasut wrote:
> Add top level boards/renesas/ MAINTAINERS file to catch all the common
> Renesas file patterns and put people on CC via get_maintainer.pl script.

s/boards/board/, here and in the commit title.

> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Nobuhiro Iwamatsu 
> Cc: Tom Rini 
> Cc: u-boot@lists.denx.de
> ---
>  board/renesas/MAINTAINERS | 15 +++
>  1 file changed, 15 insertions(+)
>  create mode 100644 board/renesas/MAINTAINERS
> 
> diff --git a/board/renesas/MAINTAINERS b/board/renesas/MAINTAINERS
> new file mode 100644
> index 000..d96be7d8520
> --- /dev/null
> +++ b/board/renesas/MAINTAINERS
> @@ -0,0 +1,15 @@
> +RENESAS BOARDS
> +M:   Marek Vasut 
> +M:   Nobuhiro Iwamatsu 
> +S:   Maintained
> +N:   grpeach
> +N:   r2dplus
> +N:   r7s72100
> +N:   r8a66597
> +N:   r8a77
> +N:   rcar
> +N:   renesas
> +N:   rza1
> +N:   serial_sh
> +N:   sh77
> +N:   sh_eth

Should we also add 'rzg2l' and 'r9a07g' to this list?

Thanks,

-- 
Paul Barker


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[PATCH] mmc: renesas-sdhi: Add compatible string for rzg2l-sdhi

[Paul Barker]

After the recent dts/upstream subtree merge, the sdhi compatible string
used in the device tree for RZ/G2L family SoCs is "renesas,rzg2l-sdhi"
not "renesas,rcar-gen3-sdhi". This broke the ability to access the eMMC
and SD card devices on RZ/G2L boards.

Fix this by adding the new compatible string to the sdhi driver.

Fixes: 136b7b6d2e98 ("Subtree merge tag 'v6.11-dts' of dts repo [1] into 
dts/upstream")
Signed-off-by: Paul Barker 
---
 drivers/mmc/renesas-sdhi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 23db2a75c444..916182cdadea 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -863,6 +863,7 @@ static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
+   { .compatible = "renesas,rzg2l-sdhi", .data = RENESAS_GEN3_QUIRKS },
{ .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
{ /* sentinel */ }
 };
-- 
2.43.0

Re: [PATCH 2/2] ARM: dts: renesas: Switch to using upstream DT on 64bit Renesas SoCs

[Paul Barker]

On 18/03/2024 14:59, Marek Vasut wrote:
> Enable OF_UPSTREAM to use upstream DT and add renesas/ prefix to the
> DEFAULT_DEVICE_TREE and OF_LIST. And thereby directly build DTB from
> dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/
> directory.
> 
> The configuration update has been done using the following script:
> ```
> sed -i '/^CONFIG_DEFAULT_DEVICE_TREE/ s@="@&renesas/@' `git grep -li renesas 
> configs`
> sed -i '/^CONFIG_OF_LIST/ s@r8a@renesas/&@g' `git grep -li renesas configs`
> ```
> 
> There are SoCs which are not included in this patch. The 32bit SoCs
> require further infrastructure work. R8A779H0 is coming during the
> next upstream DT synchronization cycle as it is not included in
> current upstream DTs yet.
> 
> Signed-off-by: Marek Vasut 

Reviewed-by: Paul Barker 
(for RZ/G2L only)

Do we also plan to drop the corresponding .dts & .dtsi files from
arch/arm/dts?

Thanks,

-- 
Paul Barker


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Re: [PATCH] doc: devicetree: Lets avoid short reference link names

[Paul Barker]

On 02/03/2024 07:39, Paul Barker wrote:
> On 01/03/2024 13:24, Sumit Garg wrote:
>> Short reference link names like "dtspec", "dtrepo", "dttweaks" etc.
>> interrupt the flow of the document text. Lets avoid them and instead
>> expand in place for better readability.
>>
>> Suggested-by: Paul Barker 
>> Signed-off-by: Sumit Garg 
>> ---
>>  doc/develop/devicetree/control.rst | 24 
>>  1 file changed, 12 insertions(+), 12 deletions(-)
>>
>> diff --git a/doc/develop/devicetree/control.rst 
>> b/doc/develop/devicetree/control.rst
>> index c94d84192b71..4cc1457d4ea8 100644
>> --- a/doc/develop/devicetree/control.rst
>> +++ b/doc/develop/devicetree/control.rst
>> @@ -36,10 +36,10 @@ What is a Flattened Devicetree?
>>  ---
>>  
>>  An fdt can be specified in source format as a text file. To read about
>> -the fdt syntax, take a look at the specification (dtspec_).
>> +the fdt syntax, take a look at `the devicetree specification`_.
>>  
>> -There is also a mailing list (dtlist_) for the compiler and associated
>> -tools.
>> +There is also a `devicetree compiler mailing list`_ for the compiler and
>> +associated tools.
>>  
>>  In case you are wondering, OF stands for Open Firmware. This follows the
>>  convention used in Linux.
>> @@ -89,7 +89,7 @@ Failing that, you could write one from scratch yourself!
>>  Resyncing with devicetree-rebasing
>>  --
>>  
>> -The devicetee-rebasing repository (dtrepo_) maintains a fork cum mirror 
>> copy of
>> +The `devicetree-rebasing repository`_ maintains a fork cum mirror copy of
>>  devicetree files along with the bindings synced at every Linux kernel major
>>  release or intermediate release candidates. The U-Boot maintainers regularly
>>  sync the `dts/upstream/` subtree from the devicetree-rebasing repo whenever
>> @@ -118,7 +118,7 @@ as `arch//dts/.dts`. To select that add `# 
>> CONFIG_OF_UPSTREAM is not
>>  set` and set `DEFAULT_DEVICE_TREE=` when prompted by Kconfig.
>>  
>>  This should include your CPU or SoC's devicetree file. On top of that any 
>> U-Boot
>> -specific tweaks (see: dttweaks_) can be made for your board.
>> +specific tweaks (see: :ref:`dttweaks`) can be made for your board.
>>  
>>  If `OF_EMBED` is selected by Kconfig, then it will be picked up and built 
>> into
>>  the U-Boot image (including u-boot.bin). This is suitable for debugging
>> @@ -243,7 +243,7 @@ Dependencies
>>  
>>  The DT schema project must be installed in order to validate the DT schema
>>  binding documents and validate DTS files using the DT schema. For 
>> installation
>> -instructions, refer to the DT schema project page (dtschema_).
>> +instructions, refer to the `DT schema project page`_.
>>  
>>  Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be
>>  installed. Ensure they are in your PATH (~/.local/bin by default).
>> @@ -333,10 +333,10 @@ used it before Linux (e.g. snow). The two projects 
>> developed in parallel
>>  and there are still some differences in the bindings for certain boards.
>>  While there has been discussion of having a separate repository for 
>> devicetree
>>  files, in practice the Linux kernel Git repository has become the place 
>> where
>> -these are stored, with U-Boot taking copies via devicetree-rebasing repo
>> -(see: dtrepo_) and adding tweaks with u-boot.dtsi files.
>> +these are stored, with U-Boot taking copies via
>> +`devicetree-rebasing repository`_ and adding tweaks with u-boot.dtsi files.
>>  
>> -.. _dtspec: https://www.devicetree.org/specifications/
>> -.. _dtlist: https://www.spinics.net/lists/devicetree-compiler/
>> -.. _dtrepo: 
>> https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
>> -.. _dtschema: https://github.com/devicetree-org/dt-schema/tree/main
>> +.. _the devicetree specification: https://www.devicetree.org/specifications/
>> +.. _devicetree compiler mailing list: 
>> https://www.spinics.net/lists/devicetree-compiler/
>> +.. _devicetree-rebasing repository: 
>> https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
>> +.. _DT schema project page: 
>> https://github.com/devicetree-org/dt-schema/tree/main
> 
> Reviewed-by: Paul Barker 
> 

There are no comments from anyone else, but this hasn't hit the next
branch yet so I'm sending a gentle ping.

-- 
Paul Barker

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Re: [PATCH 00/19] ARM: renesas: Rename R-Mobile to Renesas

[Paul Barker]

On 27/02/2024 16:05, Marek Vasut wrote:
> Rename R-Mobile to Renesas all over the place because the chips are
> made by Renesas, while only a subset of them is from the R-Mobile line.
> 
> Marek Vasut (19):
>   ARM: renesas: Drop remnants of R8A7740 support
>   ARM: renesas: Drop unused sh_sdhi.h
>   ARM: renesas: Drop unused mmc.h
>   ARM: renesas: Drop unused pfc-r8a7790.h
>   ARM: renesas: Rename rmobile_get_cpu_type() to renesas_get_cpu_type()
>   ARM: renesas: Rename rmobile_get_cpu_rev_*() to
> renesas_get_cpu_rev_*()
>   ARM: renesas: Rename RMOBILE_CPU_TYPE_* to RENESAS_CPU_TYPE_*
>   ARM: renesas: Rename rmobile_cpuinfo_idx() to renesas_cpuinfo_idx()
>   ARM: renesas: Rename rmobile_cpuinfo[] to renesas_cpuinfo[]
>   ARM: renesas: Simplify weak symbols
>   ARM: renesas: Rename rmobile_get_prr() to renesas_get_prr()
>   ARM: renesas: Rename ARCH_RMOBILE_BOARD_STRING to
> ARCH_RENESAS_BOARD_STRING
>   ARM: renesas: Rename CONFIG_ARCH_RMOBILE_EXTRAM_BOOT to
> CONFIG_RENESAS_EXTRAM_BOOT
>   ARM: renesas: Rename rmobile.h to renesas.h
>   ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESAS
>   ARM: renesas: Rename arch-/mach-rmobile to arch-/mach-renesas
>   ARM: renesas: Post rename fix ups
>   mmc: renesas-sdhi: Rename rmobile_is_gen3_mmc0() to
> rcar_is_gen3_mmc0()
>   git-mailrc: Add renesas entry and update rmobile entry
> 

For every patch in the series:

Reviewed-by: Paul Barker 

-- 
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Re: [PATCH] doc: devicetree: Lets avoid short reference link names

[Paul Barker]

On 01/03/2024 13:24, Sumit Garg wrote:
> Short reference link names like "dtspec", "dtrepo", "dttweaks" etc.
> interrupt the flow of the document text. Lets avoid them and instead
> expand in place for better readability.
> 
> Suggested-by: Paul Barker 
> Signed-off-by: Sumit Garg 
> ---
>  doc/develop/devicetree/control.rst | 24 
>  1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/doc/develop/devicetree/control.rst 
> b/doc/develop/devicetree/control.rst
> index c94d84192b71..4cc1457d4ea8 100644
> --- a/doc/develop/devicetree/control.rst
> +++ b/doc/develop/devicetree/control.rst
> @@ -36,10 +36,10 @@ What is a Flattened Devicetree?
>  ---
>  
>  An fdt can be specified in source format as a text file. To read about
> -the fdt syntax, take a look at the specification (dtspec_).
> +the fdt syntax, take a look at `the devicetree specification`_.
>  
> -There is also a mailing list (dtlist_) for the compiler and associated
> -tools.
> +There is also a `devicetree compiler mailing list`_ for the compiler and
> +associated tools.
>  
>  In case you are wondering, OF stands for Open Firmware. This follows the
>  convention used in Linux.
> @@ -89,7 +89,7 @@ Failing that, you could write one from scratch yourself!
>  Resyncing with devicetree-rebasing
>  --
>  
> -The devicetee-rebasing repository (dtrepo_) maintains a fork cum mirror copy 
> of
> +The `devicetree-rebasing repository`_ maintains a fork cum mirror copy of
>  devicetree files along with the bindings synced at every Linux kernel major
>  release or intermediate release candidates. The U-Boot maintainers regularly
>  sync the `dts/upstream/` subtree from the devicetree-rebasing repo whenever
> @@ -118,7 +118,7 @@ as `arch//dts/.dts`. To select that add `# 
> CONFIG_OF_UPSTREAM is not
>  set` and set `DEFAULT_DEVICE_TREE=` when prompted by Kconfig.
>  
>  This should include your CPU or SoC's devicetree file. On top of that any 
> U-Boot
> -specific tweaks (see: dttweaks_) can be made for your board.
> +specific tweaks (see: :ref:`dttweaks`) can be made for your board.
>  
>  If `OF_EMBED` is selected by Kconfig, then it will be picked up and built 
> into
>  the U-Boot image (including u-boot.bin). This is suitable for debugging
> @@ -243,7 +243,7 @@ Dependencies
>  
>  The DT schema project must be installed in order to validate the DT schema
>  binding documents and validate DTS files using the DT schema. For 
> installation
> -instructions, refer to the DT schema project page (dtschema_).
> +instructions, refer to the `DT schema project page`_.
>  
>  Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be
>  installed. Ensure they are in your PATH (~/.local/bin by default).
> @@ -333,10 +333,10 @@ used it before Linux (e.g. snow). The two projects 
> developed in parallel
>  and there are still some differences in the bindings for certain boards.
>  While there has been discussion of having a separate repository for 
> devicetree
>  files, in practice the Linux kernel Git repository has become the place where
> -these are stored, with U-Boot taking copies via devicetree-rebasing repo
> -(see: dtrepo_) and adding tweaks with u-boot.dtsi files.
> +these are stored, with U-Boot taking copies via
> +`devicetree-rebasing repository`_ and adding tweaks with u-boot.dtsi files.
>  
> -.. _dtspec: https://www.devicetree.org/specifications/
> -.. _dtlist: https://www.spinics.net/lists/devicetree-compiler/
> -.. _dtrepo: 
> https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
> -.. _dtschema: https://github.com/devicetree-org/dt-schema/tree/main
> +.. _the devicetree specification: https://www.devicetree.org/specifications/
> +.. _devicetree compiler mailing list: 
> https://www.spinics.net/lists/devicetree-compiler/
> +.. _devicetree-rebasing repository: 
> https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
> +.. _DT schema project page: 
> https://github.com/devicetree-org/dt-schema/tree/main

Reviewed-by: Paul Barker 

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Re: [PATCH v6 08/11] doc: devicetree: Updates for devicetree-rebasing subtree

[Paul Barker]

On 28/02/2024 09:20, Sumit Garg wrote:
> Hi Paul,
> 
> On Wed, 28 Feb 2024 at 03:08, Paul Barker  
> wrote:
>>
>> Hi Sumit,
>>
>> On 22/02/2024 09:36, Sumit Garg wrote:
>>> Encourage SoC/board maintainers to migrate to using devicetree-rebasing
>>> subtree and maintain a regular sync with Linux kernel devicetree files
>>> and bindings.
>>>
>>> Along with that add documentation regarding how to run DT bindings
>>> schema checks.
>>>
>>> Signed-off-by: Sumit Garg 
>>> ---
>>>
>>> Changes in v6:
>>> - Incorporate documentation review comments from Paul.
>>>
>>
>> I have just a couple of tidy up suggestions for the links in this
>> document - these let us avoid short reference names like `dtrepo` or
>> `dttweaks` appearing in the document itself where they interrupt the
>> flow of the text.
> 
> Although these are following the same pattern as `dtspec` and `dtlist`
> , your suggestion sounds reasonable. However, I would just like to
> avoid sending a newer version just for these since this patch-set is
> already a dependency for others [1] [2].
> 
> If you agree then I can send a follow up patch to get rid of all the
> short reference names in this document.
> 
> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=396399
> [2] https://patchwork.ozlabs.org/project/uboot/list/?series=396742

Please go ahead and fix this as a follow up patch. I don't see any
reason to hold up this series.

-- 
Paul Barker

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Re: [PATCH v6 08/11] doc: devicetree: Updates for devicetree-rebasing subtree

[Paul Barker]

S files using the DT schema. For 
> installation
> +instructions, refer to the DT schema project page (dtschema_).

instructions, refer to the `DT schema project page`_.

> +
> +Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be
> +installed. Ensure they are in your PATH (~/.local/bin by default).
> +
> +You should also install yamllint (used by dtschema when present). On Debian/
> +Ubuntu systems::
> +
> +apt install yamllint
> +
> +Running checks
> +~~
> +
> +In order to perform validation of DTB files, use the ``dtbs_check`` target::
> +
> +make dtbs_check
> +
> +It is also possible to run checks with a subset of matching schema files by
> +setting the ``DT_SCHEMA_FILES`` variable to 1 or more specific schema files 
> or
> +patterns (partial match of a fixed string). Each file or pattern should be
> +separated by ':'.
> +
> +::
> +
> +make dtbs_check DT_SCHEMA_FILES=trivial-devices.yaml:rtc.yaml
> +make dtbs_check DT_SCHEMA_FILES=/gpio/
> +make dtbs_check DT_SCHEMA_FILES=trivial-devices.yaml
> +
> +
>  Relocation, SPL and TPL
>  ---
>  
> @@ -260,8 +333,10 @@ used it before Linux (e.g. snow). The two projects 
> developed in parallel
>  and there are still some differences in the bindings for certain boards.
>  While there has been discussion of having a separate repository for 
> devicetree
>  files, in practice the Linux kernel Git repository has become the place where
> -these are stored, with U-Boot taking copies and adding tweaks with 
> u-boot.dtsi
> -files.
> +these are stored, with U-Boot taking copies via devicetree-rebasing repo

these are stored, with U-Boot taking copies via the `devicetree-rebasing 
repository`_

> +(see: dtrepo_) and adding tweaks with u-boot.dtsi files.

and adding tweaks with u-boot.dtsi files.

>  
>  .. _dtspec: https://www.devicetree.org/specifications/
>  .. _dtlist: https://www.spinics.net/lists/devicetree-compiler/
> +.. _dtrepo: 
> https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

.. _devicetree-rebasing repository: 
https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

> +.. _dtschema: https://github.com/devicetree-org/dt-schema/tree/main

.. _DT schema project page: 
https://github.com/devicetree-org/dt-schema/tree/main

Thanks,

-- 
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[PATCH v3 7/8] pmic: raa215300: Bind sysreset driver

[Paul Barker]

If SYSRESET support is enabled for the RAA215300 PMIC, we need to bind
the raa215300_sysreset driver as a child device of the PMIC.

Signed-off-by: Paul Barker 
Reviewed-by: Marek Vasut 
---
 drivers/power/pmic/raa215300.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
index b93a0d3a084a..a581a1f6dc15 100644
--- a/drivers/power/pmic/raa215300.c
+++ b/drivers/power/pmic/raa215300.c
@@ -29,6 +29,15 @@ static const struct udevice_id raa215300_ids[] = {
 
 static int raa215300_bind(struct udevice *dev)
 {
+   if (IS_ENABLED(CONFIG_SYSRESET_RAA215300)) {
+   struct driver *drv = 
lists_driver_lookup_name("raa215300_sysreset");
+   if (!drv)
+   return -ENOENT;
+
+   return device_bind(dev, drv, dev->name, NULL, dev_ofnode(dev),
+  NULL);
+   }
+
return 0;
 }
 
-- 
2.44.0

[PATCH v3 8/8] board: rzg2l: Support reset via Renesas RAA215300 PMIC

[Paul Barker]

With the SYSRESET subsystem enabled we do not need to implement
reset_cpu() in the board directory.

Signed-off-by: Paul Barker 
Reviewed-by: Marek Vasut 
---
 board/renesas/rzg2l/rzg2l.c   | 8 
 configs/renesas_rzg2l_smarc_defconfig | 2 ++
 2 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
index 73201a8c69e5..0f6d6e7f514f 100644
--- a/board/renesas/rzg2l/rzg2l.c
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -56,11 +56,3 @@ int board_init(void)
 {
return 0;
 }
-
-void reset_cpu(void)
-{
-   /*
-* TODO: Implement reset support once TrustedFirmware supports
-* the appropriate call.
-*/
-}
diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index 2cab79329db4..21365a21fe8c 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -55,3 +55,5 @@ CONFIG_PMIC_RAA215300=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_RAA215300=y
-- 
2.44.0

[PATCH v3 6/8] sysreset: Support reset via Renesas RAA215300 PMIC

[Paul Barker]

This patch adds support for resetting a board via the RAA215300 PMIC.

Note that the RAA215300 documentation names the available reset types
differently to u-boot:

  * A "warm" reset via the RAA215300 PMIC will fully reset the SoC
(CPU & GPIOs), so this corresponds to SYSRESET_COLD.

  * A "cold" reset via the RAA215300 PMIC will cycle all power supply
rails, so this corresponds to SYSRESET_POWER.

Signed-off-by: Paul Barker 
Reviewed-by: Marek Vasut 
---
 drivers/sysreset/Kconfig  |  6 +++
 drivers/sysreset/Makefile |  1 +
 drivers/sysreset/sysreset_raa215300.c | 58 +++
 3 files changed, 65 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_raa215300.c

diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 0e52f996283c..49c0787b26d8 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -229,6 +229,12 @@ config SYSRESET_MPC83XX
help
  Reboot support for NXP MPC83xx SoCs.
 
+config SYSRESET_RAA215300
+   bool "Support sysreset via Renesas RAA215300 PMIC"
+   depends on PMIC_RAA215300
+   help
+ Add support for the system reboot via the Renesas RAA215300 PMIC.
+
 endif
 
 endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index c9f1c625aebb..e0e732205df3 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
 obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
+obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_raa215300.c 
b/drivers/sysreset/sysreset_raa215300.c
new file mode 100644
index ..32dfcb0aec84
--- /dev/null
+++ b/drivers/sysreset/sysreset_raa215300.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+
+#define RAA215300_REG_SWRESET  0x6D
+#define RAA215300_COLD_RESET   BIT(0)
+#define RAA215300_WARM_RESET   BIT(1)
+
+static int raa215300_sysreset_request(struct udevice *dev, enum sysreset_t 
type)
+{
+   struct udevice *pmic = dev_get_parent(dev);
+   int ret;
+   u8 val;
+
+   /*
+* The RAA215300 documentation names the available reset types
+* differently to u-boot:
+*
+*   - A "warm" reset via the RAA215300 PMIC will fully reset the SoC
+* (CPU & GPIOs), so this corresponds to SYSRESET_COLD.
+*
+*   - A "cold" reset via the RAA215300 PMIC will cycle all power supply
+* rails, so this corresponds to SYSRESET_POWER.
+*/
+   switch (type) {
+   case SYSRESET_COLD:
+   val = RAA215300_WARM_RESET;
+   break;
+
+   case SYSRESET_POWER:
+   val = RAA215300_COLD_RESET;
+   break;
+
+   default:
+   return -EPROTONOSUPPORT;
+   }
+
+   ret = pmic_reg_write(pmic, RAA215300_REG_SWRESET, val);
+   if (ret)
+   return ret;
+
+   return -EINPROGRESS;
+}
+
+static struct sysreset_ops raa215300_sysreset_ops = {
+   .request = raa215300_sysreset_request,
+};
+
+U_BOOT_DRIVER(raa215300_sysreset) = {
+   .name = "raa215300_sysreset",
+   .id = UCLASS_SYSRESET,
+   .ops = &raa215300_sysreset_ops,
+};
-- 
2.44.0

[PATCH v3 5/8] board: rzg2l: Enable access to Renesas RAA215300 PMIC

[Paul Barker]

Enable the appropriate PMIC driver as well as the `pmic` command.

Signed-off-by: Paul Barker 
---
 configs/renesas_rzg2l_smarc_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index ad46297c6619..2cab79329db4 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
+CONFIG_CMD_PMIC=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -49,6 +50,8 @@ CONFIG_DM_I2C=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RAA215300=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-- 
2.44.0

[PATCH v3 4/8] pmic: Add Renesas RAA215300 PMIC driver

[Paul Barker]

The RZ/G2L SMARC module is powered via a Renesas RAA215300 PMIC which
provides several voltage converters, a real time clock (RTC) and reset
control. A basic driver is implemented for this device so that we can
read, write and dump the PMIC registers.

The raa215300_bind() function is added as a stub, binding of the
sysreset driver will be added in a later patch.

Additional features of this PMIC (such as reset control) may be
supported by future patches.

Signed-off-by: Paul Barker 
---
 drivers/power/pmic/Kconfig |  9 
 drivers/power/pmic/Makefile|  1 +
 drivers/power/pmic/raa215300.c | 41 ++
 3 files changed, 51 insertions(+)
 create mode 100644 drivers/power/pmic/raa215300.c

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 454a6e0cf87a..9b61b18e11fd 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -404,6 +404,15 @@ config PMIC_TPS65219
help
The TPS65219 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
+
+config PMIC_RAA215300
+   bool "Renesas RAA215300 PMIC driver"
+   depends on DM_PMIC
+   help
+ The Renesas RAA215300 PMIC driver includes RTC support, system reset
+ support and several voltage regulators. For now, this driver simply
+ allows register access and will bind the sysreset driver
+ (CONFIG_SYSRESET_RAA215300) if it is enabled.
 endif
 
 config PMIC_TPS65217
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 55ee614364be..a2d59deeed8b 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
 obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
 obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
 obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
+obj-$(CONFIG_PMIC_RAA215300) += raa215300.o
 obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
 
 ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
new file mode 100644
index ..b93a0d3a084a
--- /dev/null
+++ b/drivers/power/pmic/raa215300.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RAA215300_REG_COUNT 0x80
+
+static int raa215300_reg_count(struct udevice *dev)
+{
+   return RAA215300_REG_COUNT;
+}
+
+static struct dm_pmic_ops raa215300_ops = {
+   .reg_count = raa215300_reg_count,
+   .read = dm_i2c_read,
+   .write = dm_i2c_write,
+};
+
+static const struct udevice_id raa215300_ids[] = {
+   { .compatible = "renesas,raa215300" },
+   { /* sentinel */ }
+};
+
+static int raa215300_bind(struct udevice *dev)
+{
+   return 0;
+}
+
+U_BOOT_DRIVER(raa215300_pmic) = {
+   .name = "raa215300_pmic",
+   .id = UCLASS_PMIC,
+   .of_match = raa215300_ids,
+   .bind = raa215300_bind,
+   .ops = &raa215300_ops,
+};
-- 
2.44.0

[PATCH v3 3/8] i2c: rzg2l: Add I2C driver for RZ/G2L family

[Paul Barker]

This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044)
SoC, also known as the RIIC module.

This patch is based on both the u-boot driver in the Renesas RZ BSP
3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver
(commit 0dd3ee311255).

Support for deblocking the I2C bus is included as this may be needed
after triggering a reset via the Power Management IC (PMIC) over I2C
(the PMIC asserts the reset line before the SoC completes the I2C write
transaction with obvious bus locking effects). If the SDA line is
observed to be low during initialisation, we automatically attempt to
deblock.

[1]: https://github.com/renesas-rz/renesas-u-boot-cip

Signed-off-by: Paul Barker 
Reviewed-by: Marek Vasut 
---
 arch/arm/mach-rmobile/Kconfig |   1 +
 configs/renesas_rzg2l_smarc_defconfig |   2 +
 drivers/i2c/Kconfig   |   7 +
 drivers/i2c/Makefile  |   1 +
 drivers/i2c/rz_riic.c | 624 ++
 5 files changed, 635 insertions(+)
 create mode 100644 drivers/i2c/rz_riic.c

diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 2bb96749fc0d..38ede6e0b5b5 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -78,6 +78,7 @@ config RZG2L
imply RENESAS_SDHI
imply RZG2L_GPIO
imply SCIF_CONSOLE
+   imply SYS_I2C_RZ_RIIC
imply SYS_MALLOC_F
help
  Enable support for the Renesas RZ/G2L family of SoCs. Currently
diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index e45579ae6b98..ad46297c6619 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -24,6 +24,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_EXT2=y
@@ -44,6 +45,7 @@ CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 # CONFIG_CLK_RCAR_GEN3 is not set
 CONFIG_GPIO_HOG=y
+CONFIG_DM_I2C=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 4f42200f3923..d2a3a13493aa 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -524,6 +524,13 @@ config SYS_I2C_ROCKCHIP
  have several I2C ports and all are provided, controlled by the
  device tree.
 
+config SYS_I2C_RZ_RIIC
+   bool "Renesas RZ/G2L RIIC driver"
+   depends on RZG2L && DM_I2C
+   help
+ Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC
+ family.
+
 config SYS_I2C_SANDBOX
bool "Sandbox I2C driver"
depends on SANDBOX && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index a96a8c7e955e..692f63bafd02 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
 obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
+obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o
 obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
 obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c
new file mode 100644
index ..5f3f8d1b24b7
--- /dev/null
+++ b/drivers/i2c/rz_riic.c
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RZ/G2L I2C (RIIC) driver
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RIIC_ICCR1 0x00
+#define RIIC_ICCR2 0x04
+#define RIIC_ICMR1 0x08
+#define RIIC_ICMR2 0x0c
+#define RIIC_ICMR3 0x10
+#define RIIC_ICFER 0x14
+#define RIIC_ICSER 0x18
+#define RIIC_ICIER 0x1c
+#define RIIC_ICSR1 0x20
+#define RIIC_ICSR2 0x24
+#define RIIC_ICSAR00x28
+#define RIIC_ICBRL 0x34
+#define RIIC_ICBRH 0x38
+#define RIIC_ICDRT 0x3c
+#define RIIC_ICDRR 0x40
+
+/* ICCR1 */
+#define ICCR1_ICE  BIT(7)
+#define ICCR1_IICRST   BIT(6)
+#define ICCR1_CLO  BIT(5)
+#define ICCR1_SOWP BIT(4)
+#define ICCR1_SCLO BIT(3)
+#define ICCR1_SDAO BIT(2)
+#define ICCR1_SCLI BIT(1)
+#define ICCR1_SDAI BIT(0)
+
+/* ICCR2 */
+#define ICCR2_BBSY BIT(7)
+#define ICCR2_MST  BIT(6)
+#define ICCR2_TRS  BIT(5)
+#define ICCR2_SP   BIT(3)
+#define ICCR2_RS   BIT(2)
+#define ICCR2_ST   BIT(1)
+
+/* ICMR1 */
+#define ICMR1_MTWP BIT(7)
+#define ICMR1_CKS_MASK GENMASK(6, 4)
+#define ICMR1_BCWP BIT(3)
+#define ICMR1_BC_MASK  GENMASK(2, 0)
+
+#define ICMR1_CKS(x)   (((x) << 4) & ICMR1_CKS_MASK)
+#define ICMR1_BC(x)((x) & ICMR1_BC_MASK)
+
+/* ICMR2 */
+#define ICMR2_DLCS BIT(7)
+#define ICMR2_SDDL_MASKGENMASK(6, 4)
+#define ICMR2_TMOH 

[PATCH v3 2/8] arm: dts: rzg2l: Sync with Linux v6.7

[Paul Barker]

Pull in the recent changes to the RZ/G2L device tree and related dtsi
files so that we're aligned with Linux v6.7 (commit 0dd3ee311255).

Signed-off-by: Paul Barker 
Reviewed-by: Marek Vasut 
---
 arch/arm/dts/r9a07g044.dtsi   | 16 -
 arch/arm/dts/r9a07g044l2-smarc.dts| 21 +++
 arch/arm/dts/rz-smarc-common.dtsi | 18 +-
 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20 +++
 arch/arm/dts/rzg2l-smarc-som.dtsi | 22 ++--
 arch/arm/dts/rzg2l-smarc.dtsi | 43 +--
 6 files changed, 118 insertions(+), 22 deletions(-)

diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
index 232910e07444..66f68fc2b241 100644
--- a/arch/arm/dts/r9a07g044.dtsi
+++ b/arch/arm/dts/r9a07g044.dtsi
@@ -223,20 +223,20 @@
 ,
 ;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
- "tgiv0", "tgie0", "tgif0",
- "tgia1", "tgib1", "tgiv1", "tgiu1",
- "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
  "tgia3", "tgib3", "tgic3", "tgid3",
- "tgiv3",
+ "tciv3",
  "tgia4", "tgib4", "tgic4", "tgid4",
- "tgiv4",
+ "tciv4",
  "tgiu5", "tgiv5", "tgiw5",
  "tgia6", "tgib6", "tgic6", "tgid6",
- "tgiv6",
+ "tciv6",
  "tgia7", "tgib7", "tgic7", "tgid7",
- "tgiv7",
+ "tciv7",
  "tgia8", "tgib8", "tgic8", "tgid8",
- "tgiv8", "tgiu8";
+ "tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
diff --git a/arch/arm/dts/r9a07g044l2-smarc.dts 
b/arch/arm/dts/r9a07g044l2-smarc.dts
index bc2af6c92ccd..568d49cfe44a 100644
--- a/arch/arm/dts/r9a07g044l2-smarc.dts
+++ b/arch/arm/dts/r9a07g044l2-smarc.dts
@@ -6,6 +6,27 @@
  */
 
 /dts-v1/;
+
+/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * Disable PMOD1_SER0 by setting "#define PMOD1_SER0   0" above and
+ * enable PMOD_MTU3 by setting "#define PMOD_MTU3  1" below.
+ */
+#define PMOD_MTU3  0
+
+#if (PMOD_MTU3 && PMOD1_SER0)
+#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
+#endif
+
+#define MTU3_COUNTER_Z_PHASE_SIGNAL0
+
+#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
+#endif
+
 #include "r9a07g044l2.dtsi"
 #include "rzg2l-smarc-som.dtsi"
 #include "rzg2l-smarc-pinfunction.dtsi"
diff --git a/arch/arm/dts/rz-smarc-common.dtsi 
b/arch/arm/dts/rz-smarc-common.dtsi
index 3962d47b3e59..b7a3e6caa386 100644
--- a/arch/arm/dts/rz-smarc-common.dtsi
+++ b/arch/arm/dts/rz-smarc-common.dtsi
@@ -32,12 +32,6 @@
stdout-path = "serial0:115200n8";
};
 
-   audio_mclock: audio_mclock {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <11289600>;
-   };
-
snd_rzg2l: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -55,7 +49,7 @@
};
 
codec_dai: simple-audio-card,codec {
-  

[PATCH v3 1/8] clk: renesas: Confirm all clock & reset changes on RZ/G2L

[Paul Barker]

When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.

Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().

This change is needed for reliable initialization of the I2C driver
which is added in a following patch.

Signed-off-by: Paul Barker 
Reviewed-by: Marek Vasut 
---
 drivers/clk/renesas/rzg2l-cpg.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index e54508c35ce2..dba009997a81 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -23,10 +23,18 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "rzg2l-cpg.h"
 
+/*
+ * Monitor registers for both clock and reset signals are offset by 0x180 from
+ * the corresponding control registers.
+ */
 #define CLK_MON_R(reg) (0x180 + (reg))
+#define RST_MON_R(reg) (0x180 + (reg))
+
+#define CPG_TIMEOUT_MSEC   100
 
 static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int 
id);
 static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char 
*name);
@@ -83,9 +91,9 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
value |= BIT(mod_clk->bit);
writel(value, data->base + mod_clk->off);
 
-   if (enable && readl_poll_timeout(data->base + CLK_MON_R(mod_clk->off),
-value, (value & BIT(mod_clk->bit)),
-10)) {
+   if (enable && wait_for_bit_32(data->base + CLK_MON_R(mod_clk->off),
+ BIT(mod_clk->bit), enable,
+ CPG_TIMEOUT_MSEC, false)) {
dev_err(clk->dev, "Timeout\n");
return -ETIMEDOUT;
}
@@ -420,7 +428,8 @@ static int rzg2l_cpg_rst_set(struct reset_ctl *reset_ctl, 
bool asserted)
value |= BIT(rst->bit);
writel(value, data->base + rst->off);
 
-   return 0;
+   return wait_for_bit_32(data->base + RST_MON_R(rst->off), BIT(rst->bit),
+  asserted, CPG_TIMEOUT_MSEC, false);
 }
 
 static int rzg2l_cpg_rst_assert(struct reset_ctl *reset_ctl)
-- 
2.44.0

[PATCH v3 0/8] Add i2c and reset support for Renesas RZ/G2L

[Paul Barker]

This patch series extends the support for the Renesas RZ/G2L SMARC EVK
board (based on the R9A07G044L2 SoC) to include the following new
features:

  * I2C bus support, including automatic deblocking if SDA is stuck low
due to another device on the board.

  * Basic PMIC support, with the ability to read, write & dump PMIC
registers.

  * Support for requesting system reset (SYSRESET_COLD or
SYSRESET_POWER) via the PMIC.

Along the way we fix the CPG driver to confirm all clock & reset changes
before returning, and update the device tree to align with Linux 6.7.

This series has been tested on RZ/G2L hardware, and the full u-boot
GitLab CI pipeline has been executed in our internal GitLab instance.

Changes from v2:
  * Split the addition of RZ/G2L PMIC support into two patches: one to
add the PMIC driver and one to modify the defconfig.
  * Collected Marek's Reviewed-by tags.

Changes from v1:
  * Rebased on U-Boot v2024.04-rc2 and re-tested.
  * Sync with Linux v6.7 instead of v6.6.
  * Add raa215300_bind() as a stub in patch 4.
  * Split up the addition of sysreset support into 3 patches: patch 5
adds the driver, patch 6 binds it with the pmic driver and patch 7
enables sysreset for the RZ/G2L.

Paul Barker (8):
  clk: renesas: Confirm all clock & reset changes on RZ/G2L
  arm: dts: rzg2l: Sync with Linux v6.7
  i2c: rzg2l: Add I2C driver for RZ/G2L family
  pmic: Add Renesas RAA215300 PMIC driver
  board: rzg2l: Enable access to Renesas RAA215300 PMIC
  sysreset: Support reset via Renesas RAA215300 PMIC
  pmic: raa215300: Bind sysreset driver
  board: rzg2l: Support reset via Renesas RAA215300 PMIC

 arch/arm/dts/r9a07g044.dtsi   |  16 +-
 arch/arm/dts/r9a07g044l2-smarc.dts|  21 +
 arch/arm/dts/rz-smarc-common.dtsi |  18 +-
 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi |  20 +
 arch/arm/dts/rzg2l-smarc-som.dtsi |  22 +-
 arch/arm/dts/rzg2l-smarc.dtsi |  43 +-
 arch/arm/mach-rmobile/Kconfig |   1 +
 board/renesas/rzg2l/rzg2l.c   |   8 -
 configs/renesas_rzg2l_smarc_defconfig |   7 +
 drivers/clk/renesas/rzg2l-cpg.c   |  17 +-
 drivers/i2c/Kconfig   |   7 +
 drivers/i2c/Makefile  |   1 +
 drivers/i2c/rz_riic.c | 624 ++
 drivers/power/pmic/Kconfig|   9 +
 drivers/power/pmic/Makefile   |   1 +
 drivers/power/pmic/raa215300.c|  50 ++
 drivers/sysreset/Kconfig  |   6 +
 drivers/sysreset/Makefile |   1 +
 drivers/sysreset/sysreset_raa215300.c |  58 ++
 19 files changed, 896 insertions(+), 34 deletions(-)
 create mode 100644 drivers/i2c/rz_riic.c
 create mode 100644 drivers/power/pmic/raa215300.c
 create mode 100644 drivers/sysreset/sysreset_raa215300.c


base-commit: d49fa3defa50c6d3f04acbb52fd486c13c14ab6a
-- 
2.44.0

Re: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family

[Paul Barker]

On 26/02/2024 17:43, Biju Das wrote:
> 
> 
>> -Original Message-
>> From: U-Boot  On Behalf Of Paul Barker
>> Sent: Monday, February 26, 2024 3:06 PM
>> To: Marek Vasut ; Nobuhiro Iwamatsu
>> 
>> Cc: Paul Barker ; u-boot@lists.denx.de
>> Subject: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family
>>
>> This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) SoC,
>> also known as the RIIC module.
>>
>> This patch is based on both the u-boot driver in the Renesas RZ BSP
>> 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver (commit
>> 0dd3ee311255).
>>
>> Support for deblocking the I2C bus is included as this may be needed after
>> triggering a reset via the Power Management IC (PMIC) over I2C (the PMIC
>> asserts the reset line before the SoC completes the I2C write transaction
>> with obvious bus locking effects). If the SDA line is observed to be low
>> during initialisation, we automatically attempt to deblock.
>>
>> [1]:
>>
>> Signed-off-by: Paul Barker 
>> eviewed-by: Marek Vasut 
> 
> Typo. R is missing in the Rb tag.

Good catch - I pasted it right in the first patch but messed it up here
somehow. Hopefully Marek can fix this when applying if there's nothing
else that needs changing.

> 
> Also change log is missing.

The changelog is in the cover letter [1].

[1]: 
https://lore.kernel.org/u-boot/20240226150536.1690-1-paul.barker...@bp.renesas.com/

Thanks,

-- 
Paul Barker

OpenPGP_0x27F4B3459F002257.asc
Description: OpenPGP public key


OpenPGP_signature.asc
Description: OpenPGP digital signature

[PATCH v2 7/7] board: rzg2l: Support reset via Renesas RAA215300 PMIC

[Paul Barker]

With the SYSRESET subsystem enabled we do not need to implement
reset_cpu() in the board directory.

Signed-off-by: Paul Barker 
---
 board/renesas/rzg2l/rzg2l.c   | 8 
 configs/renesas_rzg2l_smarc_defconfig | 2 ++
 2 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
index 73201a8c69e5..0f6d6e7f514f 100644
--- a/board/renesas/rzg2l/rzg2l.c
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -56,11 +56,3 @@ int board_init(void)
 {
return 0;
 }
-
-void reset_cpu(void)
-{
-   /*
-* TODO: Implement reset support once TrustedFirmware supports
-* the appropriate call.
-*/
-}
diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index 2cab79329db4..21365a21fe8c 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -55,3 +55,5 @@ CONFIG_PMIC_RAA215300=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_RAA215300=y
-- 
2.43.2

[PATCH v2 6/7] pmic: raa215300: Bind sysreset driver

[Paul Barker]

If SYSRESET support is enabled for the RAA215300 PMIC, we need to bind
the raa215300_sysreset driver as a child device of the PMIC.

Signed-off-by: Paul Barker 
---
 drivers/power/pmic/raa215300.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
index b93a0d3a084a..a581a1f6dc15 100644
--- a/drivers/power/pmic/raa215300.c
+++ b/drivers/power/pmic/raa215300.c
@@ -29,6 +29,15 @@ static const struct udevice_id raa215300_ids[] = {
 
 static int raa215300_bind(struct udevice *dev)
 {
+   if (IS_ENABLED(CONFIG_SYSRESET_RAA215300)) {
+   struct driver *drv = 
lists_driver_lookup_name("raa215300_sysreset");
+   if (!drv)
+   return -ENOENT;
+
+   return device_bind(dev, drv, dev->name, NULL, dev_ofnode(dev),
+  NULL);
+   }
+
return 0;
 }
 
-- 
2.43.2

[PATCH v2 4/7] pmic: Add Renesas RAA215300 PMIC driver

[Paul Barker]

The RZ/G2L SMARC module is powered via a Renesas RAA215300 PMIC which
provides several voltage converters, a real time clock (RTC) and reset
control. A basic driver is implemented for this device so that we can
read, write and dump the PMIC registers.

The raa215300_bind() function is added as a stub, binding of the
sysreset driver will be added in a later patch.

Additional features of this PMIC (such as reset control) may be
supported by future patches.

Signed-off-by: Paul Barker 
---
 configs/renesas_rzg2l_smarc_defconfig |  3 ++
 drivers/power/pmic/Kconfig|  9 ++
 drivers/power/pmic/Makefile   |  1 +
 drivers/power/pmic/raa215300.c| 41 +++
 4 files changed, 54 insertions(+)
 create mode 100644 drivers/power/pmic/raa215300.c

diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index ad46297c6619..2cab79329db4 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
+CONFIG_CMD_PMIC=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -49,6 +50,8 @@ CONFIG_DM_I2C=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RAA215300=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 454a6e0cf87a..9b61b18e11fd 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -404,6 +404,15 @@ config PMIC_TPS65219
help
The TPS65219 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
+
+config PMIC_RAA215300
+   bool "Renesas RAA215300 PMIC driver"
+   depends on DM_PMIC
+   help
+ The Renesas RAA215300 PMIC driver includes RTC support, system reset
+ support and several voltage regulators. For now, this driver simply
+ allows register access and will bind the sysreset driver
+ (CONFIG_SYSRESET_RAA215300) if it is enabled.
 endif
 
 config PMIC_TPS65217
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 55ee614364be..a2d59deeed8b 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
 obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
 obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
 obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
+obj-$(CONFIG_PMIC_RAA215300) += raa215300.o
 obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
 
 ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
new file mode 100644
index ..b93a0d3a084a
--- /dev/null
+++ b/drivers/power/pmic/raa215300.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RAA215300_REG_COUNT 0x80
+
+static int raa215300_reg_count(struct udevice *dev)
+{
+   return RAA215300_REG_COUNT;
+}
+
+static struct dm_pmic_ops raa215300_ops = {
+   .reg_count = raa215300_reg_count,
+   .read = dm_i2c_read,
+   .write = dm_i2c_write,
+};
+
+static const struct udevice_id raa215300_ids[] = {
+   { .compatible = "renesas,raa215300" },
+   { /* sentinel */ }
+};
+
+static int raa215300_bind(struct udevice *dev)
+{
+   return 0;
+}
+
+U_BOOT_DRIVER(raa215300_pmic) = {
+   .name = "raa215300_pmic",
+   .id = UCLASS_PMIC,
+   .of_match = raa215300_ids,
+   .bind = raa215300_bind,
+   .ops = &raa215300_ops,
+};
-- 
2.43.2

[PATCH v2 5/7] sysreset: Support reset via Renesas RAA215300 PMIC

[Paul Barker]

This patch adds support for resetting a board via the RAA215300 PMIC.

Note that the RAA215300 documentation names the available reset types
differently to u-boot:

  * A "warm" reset via the RAA215300 PMIC will fully reset the SoC
(CPU & GPIOs), so this corresponds to SYSRESET_COLD.
  
  * A "cold" reset via the RAA215300 PMIC will cycle all power supply
rails, so this corresponds to SYSRESET_POWER.

Signed-off-by: Paul Barker 
---
 drivers/sysreset/Kconfig  |  6 +++
 drivers/sysreset/Makefile |  1 +
 drivers/sysreset/sysreset_raa215300.c | 58 +++
 3 files changed, 65 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_raa215300.c

diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 0e52f996283c..49c0787b26d8 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -229,6 +229,12 @@ config SYSRESET_MPC83XX
help
  Reboot support for NXP MPC83xx SoCs.
 
+config SYSRESET_RAA215300
+   bool "Support sysreset via Renesas RAA215300 PMIC"
+   depends on PMIC_RAA215300
+   help
+ Add support for the system reboot via the Renesas RAA215300 PMIC.
+
 endif
 
 endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index c9f1c625aebb..e0e732205df3 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
 obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
+obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_raa215300.c 
b/drivers/sysreset/sysreset_raa215300.c
new file mode 100644
index ..32dfcb0aec84
--- /dev/null
+++ b/drivers/sysreset/sysreset_raa215300.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+
+#define RAA215300_REG_SWRESET  0x6D
+#define RAA215300_COLD_RESET   BIT(0)
+#define RAA215300_WARM_RESET   BIT(1)
+
+static int raa215300_sysreset_request(struct udevice *dev, enum sysreset_t 
type)
+{
+   struct udevice *pmic = dev_get_parent(dev);
+   int ret;
+   u8 val;
+
+   /*
+* The RAA215300 documentation names the available reset types
+* differently to u-boot:
+*
+*   - A "warm" reset via the RAA215300 PMIC will fully reset the SoC
+* (CPU & GPIOs), so this corresponds to SYSRESET_COLD.
+*
+*   - A "cold" reset via the RAA215300 PMIC will cycle all power supply
+* rails, so this corresponds to SYSRESET_POWER.
+*/
+   switch (type) {
+   case SYSRESET_COLD:
+   val = RAA215300_WARM_RESET;
+   break;
+
+   case SYSRESET_POWER:
+   val = RAA215300_COLD_RESET;
+   break;
+
+   default:
+   return -EPROTONOSUPPORT;
+   }
+
+   ret = pmic_reg_write(pmic, RAA215300_REG_SWRESET, val);
+   if (ret)
+   return ret;
+
+   return -EINPROGRESS;
+}
+
+static struct sysreset_ops raa215300_sysreset_ops = {
+   .request = raa215300_sysreset_request,
+};
+
+U_BOOT_DRIVER(raa215300_sysreset) = {
+   .name = "raa215300_sysreset",
+   .id = UCLASS_SYSRESET,
+   .ops = &raa215300_sysreset_ops,
+};
-- 
2.43.2

[PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family

[Paul Barker]

This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044)
SoC, also known as the RIIC module.

This patch is based on both the u-boot driver in the Renesas RZ BSP
3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver
(commit 0dd3ee311255).

Support for deblocking the I2C bus is included as this may be needed
after triggering a reset via the Power Management IC (PMIC) over I2C
(the PMIC asserts the reset line before the SoC completes the I2C write
transaction with obvious bus locking effects). If the SDA line is
observed to be low during initialisation, we automatically attempt to
deblock.

[1]: https://github.com/renesas-rz/renesas-u-boot-cip

Signed-off-by: Paul Barker 
eviewed-by: Marek Vasut 
---
 arch/arm/mach-rmobile/Kconfig |   1 +
 configs/renesas_rzg2l_smarc_defconfig |   2 +
 drivers/i2c/Kconfig   |   7 +
 drivers/i2c/Makefile  |   1 +
 drivers/i2c/rz_riic.c | 624 ++
 5 files changed, 635 insertions(+)
 create mode 100644 drivers/i2c/rz_riic.c

diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 2bb96749fc0d..38ede6e0b5b5 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -78,6 +78,7 @@ config RZG2L
imply RENESAS_SDHI
imply RZG2L_GPIO
imply SCIF_CONSOLE
+   imply SYS_I2C_RZ_RIIC
imply SYS_MALLOC_F
help
  Enable support for the Renesas RZ/G2L family of SoCs. Currently
diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index e45579ae6b98..ad46297c6619 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -24,6 +24,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_EXT2=y
@@ -44,6 +45,7 @@ CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 # CONFIG_CLK_RCAR_GEN3 is not set
 CONFIG_GPIO_HOG=y
+CONFIG_DM_I2C=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 4f42200f3923..d2a3a13493aa 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -524,6 +524,13 @@ config SYS_I2C_ROCKCHIP
  have several I2C ports and all are provided, controlled by the
  device tree.
 
+config SYS_I2C_RZ_RIIC
+   bool "Renesas RZ/G2L RIIC driver"
+   depends on RZG2L && DM_I2C
+   help
+ Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC
+ family.
+
 config SYS_I2C_SANDBOX
bool "Sandbox I2C driver"
depends on SANDBOX && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index a96a8c7e955e..692f63bafd02 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
 obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
+obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o
 obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
 obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c
new file mode 100644
index ..5f3f8d1b24b7
--- /dev/null
+++ b/drivers/i2c/rz_riic.c
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RZ/G2L I2C (RIIC) driver
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RIIC_ICCR1 0x00
+#define RIIC_ICCR2 0x04
+#define RIIC_ICMR1 0x08
+#define RIIC_ICMR2 0x0c
+#define RIIC_ICMR3 0x10
+#define RIIC_ICFER 0x14
+#define RIIC_ICSER 0x18
+#define RIIC_ICIER 0x1c
+#define RIIC_ICSR1 0x20
+#define RIIC_ICSR2 0x24
+#define RIIC_ICSAR00x28
+#define RIIC_ICBRL 0x34
+#define RIIC_ICBRH 0x38
+#define RIIC_ICDRT 0x3c
+#define RIIC_ICDRR 0x40
+
+/* ICCR1 */
+#define ICCR1_ICE  BIT(7)
+#define ICCR1_IICRST   BIT(6)
+#define ICCR1_CLO  BIT(5)
+#define ICCR1_SOWP BIT(4)
+#define ICCR1_SCLO BIT(3)
+#define ICCR1_SDAO BIT(2)
+#define ICCR1_SCLI BIT(1)
+#define ICCR1_SDAI BIT(0)
+
+/* ICCR2 */
+#define ICCR2_BBSY BIT(7)
+#define ICCR2_MST  BIT(6)
+#define ICCR2_TRS  BIT(5)
+#define ICCR2_SP   BIT(3)
+#define ICCR2_RS   BIT(2)
+#define ICCR2_ST   BIT(1)
+
+/* ICMR1 */
+#define ICMR1_MTWP BIT(7)
+#define ICMR1_CKS_MASK GENMASK(6, 4)
+#define ICMR1_BCWP BIT(3)
+#define ICMR1_BC_MASK  GENMASK(2, 0)
+
+#define ICMR1_CKS(x)   (((x) << 4) & ICMR1_CKS_MASK)
+#define ICMR1_BC(x)((x) & ICMR1_BC_MASK)
+
+/* ICMR2 */
+#define ICMR2_DLCS BIT(7)
+#define ICMR2_SDDL_MASKGENMASK(6, 4)
+#define ICMR2_TMOH 

[PATCH v2 2/7] arm: dts: rzg2l: Sync with Linux v6.7

[Paul Barker]

Pull in the recent changes to the RZ/G2L device tree and related dtsi
files so that we're aligned with Linux v6.7 (commit 0dd3ee311255).

Signed-off-by: Paul Barker 
Reviewed-by: Marek Vasut 
---
 arch/arm/dts/r9a07g044.dtsi   | 16 -
 arch/arm/dts/r9a07g044l2-smarc.dts| 21 +++
 arch/arm/dts/rz-smarc-common.dtsi | 18 +-
 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20 +++
 arch/arm/dts/rzg2l-smarc-som.dtsi | 22 ++--
 arch/arm/dts/rzg2l-smarc.dtsi | 43 +--
 6 files changed, 118 insertions(+), 22 deletions(-)

diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
index 232910e07444..66f68fc2b241 100644
--- a/arch/arm/dts/r9a07g044.dtsi
+++ b/arch/arm/dts/r9a07g044.dtsi
@@ -223,20 +223,20 @@
 ,
 ;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
- "tgiv0", "tgie0", "tgif0",
- "tgia1", "tgib1", "tgiv1", "tgiu1",
- "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
  "tgia3", "tgib3", "tgic3", "tgid3",
- "tgiv3",
+ "tciv3",
  "tgia4", "tgib4", "tgic4", "tgid4",
- "tgiv4",
+ "tciv4",
  "tgiu5", "tgiv5", "tgiw5",
  "tgia6", "tgib6", "tgic6", "tgid6",
- "tgiv6",
+ "tciv6",
  "tgia7", "tgib7", "tgic7", "tgid7",
- "tgiv7",
+ "tciv7",
  "tgia8", "tgib8", "tgic8", "tgid8",
- "tgiv8", "tgiu8";
+ "tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
diff --git a/arch/arm/dts/r9a07g044l2-smarc.dts 
b/arch/arm/dts/r9a07g044l2-smarc.dts
index bc2af6c92ccd..568d49cfe44a 100644
--- a/arch/arm/dts/r9a07g044l2-smarc.dts
+++ b/arch/arm/dts/r9a07g044l2-smarc.dts
@@ -6,6 +6,27 @@
  */
 
 /dts-v1/;
+
+/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * Disable PMOD1_SER0 by setting "#define PMOD1_SER0   0" above and
+ * enable PMOD_MTU3 by setting "#define PMOD_MTU3  1" below.
+ */
+#define PMOD_MTU3  0
+
+#if (PMOD_MTU3 && PMOD1_SER0)
+#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
+#endif
+
+#define MTU3_COUNTER_Z_PHASE_SIGNAL0
+
+#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
+#endif
+
 #include "r9a07g044l2.dtsi"
 #include "rzg2l-smarc-som.dtsi"
 #include "rzg2l-smarc-pinfunction.dtsi"
diff --git a/arch/arm/dts/rz-smarc-common.dtsi 
b/arch/arm/dts/rz-smarc-common.dtsi
index 3962d47b3e59..b7a3e6caa386 100644
--- a/arch/arm/dts/rz-smarc-common.dtsi
+++ b/arch/arm/dts/rz-smarc-common.dtsi
@@ -32,12 +32,6 @@
stdout-path = "serial0:115200n8";
};
 
-   audio_mclock: audio_mclock {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <11289600>;
-   };
-
snd_rzg2l: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -55,7 +49,7 @@
};
 
codec_dai: simple-audio-card,codec {
-  

[PATCH v2 1/7] clk: renesas: Confirm all clock & reset changes on RZ/G2L

[Paul Barker]

When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.

Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().

This change is needed for reliable initialization of the I2C driver
which is added in a following patch.

Signed-off-by: Paul Barker 
Reviewed-by: Marek Vasut 
---
 drivers/clk/renesas/rzg2l-cpg.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index e54508c35ce2..dba009997a81 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -23,10 +23,18 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "rzg2l-cpg.h"
 
+/*
+ * Monitor registers for both clock and reset signals are offset by 0x180 from
+ * the corresponding control registers.
+ */
 #define CLK_MON_R(reg) (0x180 + (reg))
+#define RST_MON_R(reg) (0x180 + (reg))
+
+#define CPG_TIMEOUT_MSEC   100
 
 static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int 
id);
 static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char 
*name);
@@ -83,9 +91,9 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
value |= BIT(mod_clk->bit);
writel(value, data->base + mod_clk->off);
 
-   if (enable && readl_poll_timeout(data->base + CLK_MON_R(mod_clk->off),
-value, (value & BIT(mod_clk->bit)),
-10)) {
+   if (enable && wait_for_bit_32(data->base + CLK_MON_R(mod_clk->off),
+ BIT(mod_clk->bit), enable,
+ CPG_TIMEOUT_MSEC, false)) {
dev_err(clk->dev, "Timeout\n");
return -ETIMEDOUT;
}
@@ -420,7 +428,8 @@ static int rzg2l_cpg_rst_set(struct reset_ctl *reset_ctl, 
bool asserted)
value |= BIT(rst->bit);
writel(value, data->base + rst->off);
 
-   return 0;
+   return wait_for_bit_32(data->base + RST_MON_R(rst->off), BIT(rst->bit),
+  asserted, CPG_TIMEOUT_MSEC, false);
 }
 
 static int rzg2l_cpg_rst_assert(struct reset_ctl *reset_ctl)
-- 
2.43.2

[PATCH v2 0/7] Add i2c and reset support for Renesas RZ/G2L

[Paul Barker]

This patch series extends the support for the Renesas RZ/G2L SMARC EVK
board (based on the R9A07G044L2 SoC) to include the following new
features:

  * I2C bus support, including automatic deblocking if SDA is stuck low
due to another device on the board.

  * Basic PMIC support, with the ability to read, write & dump PMIC
registers.

  * Support for requesting system reset (SYSRESET_COLD or
SYSRESET_POWER) via the PMIC.

Along the way we fix the CPG driver to confirm all clock & reset changes
before returning, and update the device tree to align with Linux 6.7.

This series has been tested on RZ/G2L hardware, and the full u-boot
GitLab CI pipeline has been executed in our internal GitLab instance.

Changes from v1:
  * Rebased on U-Boot v2024.04-rc2 and re-tested.
  * Sync with Linux v6.7 instead of v6.6.
  * Add raa215300_bind() as a stub in patch 4.
  * Split up the addition of sysreset support into 3 patches: patch 5
adds the driver, patch 6 binds it with the pmic driver and patch 7
enables sysreset for the RZ/G2L.

Paul Barker (7):
  clk: renesas: Confirm all clock & reset changes on RZ/G2L
  arm: dts: rzg2l: Sync with Linux v6.7
  i2c: rzg2l: Add I2C driver for RZ/G2L family
  pmic: Add Renesas RAA215300 PMIC driver
  sysreset: Support reset via Renesas RAA215300 PMIC
  pmic: raa215300: Bind sysreset driver
  board: rzg2l: Support reset via Renesas RAA215300 PMIC

 arch/arm/dts/r9a07g044.dtsi   |  16 +-
 arch/arm/dts/r9a07g044l2-smarc.dts|  21 +
 arch/arm/dts/rz-smarc-common.dtsi |  18 +-
 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi |  20 +
 arch/arm/dts/rzg2l-smarc-som.dtsi |  22 +-
 arch/arm/dts/rzg2l-smarc.dtsi |  43 +-
 arch/arm/mach-rmobile/Kconfig |   1 +
 board/renesas/rzg2l/rzg2l.c   |   8 -
 configs/renesas_rzg2l_smarc_defconfig |   7 +
 drivers/clk/renesas/rzg2l-cpg.c   |  17 +-
 drivers/i2c/Kconfig   |   7 +
 drivers/i2c/Makefile  |   1 +
 drivers/i2c/rz_riic.c | 624 ++
 drivers/power/pmic/Kconfig|   9 +
 drivers/power/pmic/Makefile   |   1 +
 drivers/power/pmic/raa215300.c|  50 ++
 drivers/sysreset/Kconfig  |   6 +
 drivers/sysreset/Makefile |   1 +
 drivers/sysreset/sysreset_raa215300.c |  58 ++
 19 files changed, 896 insertions(+), 34 deletions(-)
 create mode 100644 drivers/i2c/rz_riic.c
 create mode 100644 drivers/power/pmic/raa215300.c
 create mode 100644 drivers/sysreset/sysreset_raa215300.c


base-commit: 37345abb97ef0dd9c50a03b2a72617612dcae585
-- 
2.43.2

Re: [PATCH 1/3] mmc: Convert hs400_tuning flag from u8 to bool

[Paul Barker]

On 20/02/2024 11:27, Marek Vasut wrote:
> On 2/20/24 11:57, Paul Barker wrote:
>> On 20/02/2024 08:37, Marek Vasut wrote:
>>> This hs400_tuning is a flag, make it bool. No functional change.
>>> This will be useful in the following patch, which adds another
>>> more generic flag, where the compiler can better use the space
>>> now reserved for the u8 to store more flags in it.
>>
>> The minimum size for a bool is one byte so there likely won't be any
>> improvement in struct size from using bool instead of u8 for
>> `hs400_tuning` here and `tuning` added in the next patch. I still think
>> it's a good change to make though, bool is the right type for an on/off
>> flag.
> 
> The compiler does not do boolean packing in structures ?

The compiler will only pack booleans if you explicitly say that only
one bit of memory is needed, e.g.:

bool tuning:1;
bool hs400_tuning:1;

Otherwise the assumption is that you may wish to take the address of
each field and so each one must have a distinct address in memory.

Thanks,

-- 
Paul Barker


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Re: [PATCH] mmc: Drop unused mmc_send_tuning() cmd_error parameter

[Paul Barker]

On 20/02/2024 11:26, Marek Vasut wrote:
> On 2/20/24 11:50, Paul Barker wrote:
>> On 20/02/2024 08:36, Marek Vasut wrote:
>>> The cmd_error parameter is not used, remove it.
>>>   [snip]
>>>
>>> diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
>>> index 5a0c61daed5..296aaee7331 100644
>>> --- a/drivers/mmc/mtk-sd.c
>>> +++ b/drivers/mmc/mtk-sd.c
>>> @@ -1131,7 +1131,7 @@ static int hs400_tune_response(struct udevice *dev, 
>>> u32 opcode)
>>> i << PAD_CMD_TUNE_RX_DLY3_S);
>>>   
>>> for (j = 0; j < 3; j++) {
>>> -   mmc_send_tuning(mmc, opcode, &cmd_err);
>>> +   cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err) {
>>> cmd_delay |= (1 << i);
>>> } else {
>>> @@ -1181,7 +1181,7 @@ static int msdc_tune_response(struct udevice *dev, 
>>> u32 opcode)
>>> i << MSDC_PAD_TUNE_CMDRDLY_S);
>>>   
>>> for (j = 0; j < 3; j++) {
>>> -   mmc_send_tuning(mmc, opcode, &cmd_err);
>>> +   cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err) {
>>> rise_delay |= (1 << i);
>>> } else {
>>> @@ -1203,7 +1203,7 @@ static int msdc_tune_response(struct udevice *dev, 
>>> u32 opcode)
>>> i << MSDC_PAD_TUNE_CMDRDLY_S);
>>>   
>>> for (j = 0; j < 3; j++) {
>>> -   mmc_send_tuning(mmc, opcode, &cmd_err);
>>> +   cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err) {
>>> fall_delay |= (1 << i);
>>> } else {
>>> @@ -1238,7 +1238,7 @@ skip_fall:
>>> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
>>> i << MSDC_PAD_TUNE_CMDRRDLY_S);
>>>   
>>> -   mmc_send_tuning(mmc, opcode, &cmd_err);
>>> +   cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err)
>>> internal_delay |= (1 << i);
>>> }
>>> @@ -1264,7 +1264,6 @@ static int msdc_tune_data(struct udevice *dev, u32 
>>> opcode)
>>> struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
>>> u8 final_delay, final_maxlen;
>>> void __iomem *tune_reg = &host->base->pad_tune;
>>> -   int cmd_err;
>>> int i, ret;
>>>   
>>> if (host->dev_comp->pad_tune0)
>>> @@ -1277,10 +1276,10 @@ static int msdc_tune_data(struct udevice *dev, u32 
>>> opcode)
>>> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
>>> i << MSDC_PAD_TUNE_DATRRDLY_S);
>>>   
>>> -   ret = mmc_send_tuning(mmc, opcode, &cmd_err);
>>> +   ret = mmc_send_tuning(mmc, opcode);
>>> if (!ret) {
>>> rise_delay |= (1 << i);
>>> -   } else if (cmd_err) {
>>> +   } else {
>>> /* in this case, retune response is needed */
>>> ret = msdc_tune_response(dev, opcode);
>>> if (ret)
>>> @@ -1300,10 +1299,10 @@ static int msdc_tune_data(struct udevice *dev, u32 
>>> opcode)
>>> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
>>> i << MSDC_PAD_TUNE_DATRRDLY_S);
>>>   
>>> -   ret = mmc_send_tuning(mmc, opcode, &cmd_err);
>>> +   ret = mmc_send_tuning(mmc, opcode);
>>> if (!ret) {
>>> fall_delay |= (1 << i);
>>> -   } else if (cmd_err) {
>>> +   } else {
>>> /* in this case, retune response is needed */
>>> ret = msdc_tune_response(dev, opcode);
>>> if (ret)
>>
>> This driver (mtk-sd.c) seems to be the only one that really uses the
>> `cmd_error` parameter.
>>
>> Looking at the implementation of mmc_send_tuning() in Linux, this
>> parameter is used so that a caller can differentiate between a command
>> error and a data error. I don't know enough details about MMC to
>> understand the distinction, but I assume there is some reason for this.
>> So I wonder if the mtk-sd driver will still work if those error paths
>> are taken for data errors and not just command errors. Has this change
>> been tested on some board which uses this driver?
> 
> Not by me, so far this driver used uninitialized error value and assumed 
> it was initialized as far as I can tell, so it is likely already broken.

+To: Ryder Lee, Weijie Gao, Chunfeng Yun
+Cc: gss_mtk_uboot_upstr...@mediatek.com

Do you have any input as ARM MEDIATEK maintainers?

-- 
Paul Barker


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Re: [PATCH] mmc: renesas-sdhi: Stop transmission in case tuning block transfer fails

[Paul Barker]

On 20/02/2024 08:38, Marek Vasut wrote:
> The current code uses the state of tuning block received by SCC to
> determine whether or not to send transmission stop command. This is
> not correct. Use the state of tuning block transfer to determine
> whether or not to send transmission stop command instead, because
> the transmission stop command has to be sent in case the tuning
> block transfer failed.
> 
> This requires two changes, separate variable to store and check the
> state of tuning block received by SCC, and another separate variable
> to store and check return value from transmission stop command.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Hai Pham 
> Cc: Jaehoon Chung 
> Cc: Nobuhiro Iwamatsu 
> Cc: Paul Barker 
> Cc: Peng Fan 
> Cc: Sean Anderson 
> Cc: Tom Rini 
> Cc: Yoshihiro Shimoda 
> ---
>  drivers/mmc/renesas-sdhi.c | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> index 316b75b35fe..c4d0733b621 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -568,8 +568,8 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint 
> opcode)
>   struct mmc *mmc = upriv->mmc;
>   unsigned int tap_num;
>   unsigned int taps = 0;
> - int i, ret = 0;
> - u32 caps;
> + int i, ret = 0, sret;
> + u32 caps, reg;
>  
>   /* Only supported on Renesas RCar */
>   if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
> @@ -612,8 +612,8 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint 
> opcode)
>   if (ret == 0)
>   taps |= BIT(i);
>  
> - ret = renesas_sdhi_compare_scc_data(priv);
> - if (ret == 0)
> + reg = renesas_sdhi_compare_scc_data(priv);
> + if (reg == 0)
>   priv->smpcmp |= BIT(i);
>  
>   mdelay(1);
> @@ -624,9 +624,9 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint 
> opcode)
>* eMMC.
>*/
>   if (ret && (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
> - ret = mmc_send_stop_transmission(mmc, false);
> - if (ret < 0)
> - dev_dbg(dev, "Tuning abort fail (%d)\n", ret);
> + sret = mmc_send_stop_transmission(mmc, false);
> + if (sret < 0)
> + dev_dbg(dev, "Tuning abort fail (%d)\n", sret);
>   }
>   }
>  

Reviewed-by: Paul Barker 
Tested-by: Paul Barker 
  (tested on RZ/G2L with commit ad50a8151387 from
  https://source.denx.de/u-boot/custodians/u-boot-sh)

-- 
Paul Barker


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Re: [PATCH] mmc: tmio: Check INFO1 for completion during DMA transfer

[Paul Barker]

On 20/02/2024 08:38, Marek Vasut wrote:
> In case a CRC error occurs during DMA transfer, the transfer completion
> flag is not set in TMIO_SD_DMA_INFO1 and the transfer would eventually
> time out. The timeout could be very long in case the transfer consists
> of a large amount of blocks, the base timeout is 10 seconds and every
> block adds 100 us more.
> 
> In case a CRC error does occur, a completion flag is set in a different
> register, TMIO_SD_INFO1. Use this other completion flag to detect DMA
> transfer ended and stop waiting for TMIO_SD_DMA_INFO1 completion flag.
> This reduces the lengthy timeout in case of an error. The unconditional
> check of TMIO_SD_DMA_INFO2 register for DMA related errors must not be
> skipped in any case to actually recognize the DMA error and report it.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Hai Pham 
> Cc: Jaehoon Chung 
> Cc: Nobuhiro Iwamatsu 
> Cc: Paul Barker 
> Cc: Peng Fan 
> Cc: Sean Anderson 
> Cc: Tom Rini 
> Cc: Yoshihiro Shimoda 
> ---
>  drivers/mmc/tmio-common.c | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
> index 890c496b535..719c4830bc3 100644
> --- a/drivers/mmc/tmio-common.c
> +++ b/drivers/mmc/tmio-common.c
> @@ -299,7 +299,13 @@ static int tmio_sd_dma_wait_for_irq(struct udevice *dev, 
> u32 flag,
>   struct tmio_sd_priv *priv = dev_get_priv(dev);
>   long wait = 100 + 10 * blocks;
>  
> - while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
> + for (;;) {
> + if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)
> + break;
> +
> + if (tmio_sd_readl(priv, TMIO_SD_INFO1) & TMIO_SD_INFO1_CMP)
> + break;
> +
>   if (wait-- < 0) {
>   dev_err(dev, "timeout during DMA\n");
>   return -ETIMEDOUT;

Reviewed-by: Paul Barker 
Tested-by: Paul Barker 
  (tested on RZ/G2L with commit ad50a8151387 from
  https://source.denx.de/u-boot/custodians/u-boot-sh)

-- 
Paul Barker


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Re: [PATCH 3/3] mmc: renesas-sdhi: Do not access SCC during tuning in send_cmd callback

[Paul Barker]

On 20/02/2024 08:37, Marek Vasut wrote:
> Do not access SCC when sending commands during tuning operation as that
> will disrupt the tuning operation. The tuning operation is adjusting the
> SCC settings itself in execute_tuning callback.
> 
> When renesas_sdhi_execute_tuning() is called by the MMC core code, a loop
> which consists of renesas_sdhi_prepare_tuning(), mmc_send_tuning() and
> renesas_sdhi_compare_scc_data() iterates over each SCC tuning tap.
> 
> The renesas_sdhi_prepare_tuning() configures the SCC tuning tap number into
> hardware, mmc_send_tuning() triggers transfer of tuning block which depends
> on the bus mode for which the bus is currently being tuned, this information
> is supplied by the MMC core code, and finally renesas_sdhi_compare_scc_data()
> tests the received tuning block for validity.
> 
> Because renesas_sdhi_prepare_tuning() configures the SCC tuning tap into
> the hardware to fit the tuning operation, mmc_send_tuning() which triggers
> command transfer using renesas_sdhi_send_cmd() must not manipulate with
> the SCC in any way. Currently renesas_sdhi_send_cmd() does unconditionally
> call renesas_sdhi_check_scc_error(), which may adjust the SCC tuning tap
> position by writing RENESAS_SDHI_SCC_TAPSET, which would overwrite the
> required tuning configuration set by renesas_sdhi_prepare_tuning() and
> disrupt the tuning operation.
> 
> Fix this by skipping the renesas_sdhi_check_scc_error() call in case the
> MMC subsystem is in tuning state. This way, the SCC settings are left
> unmodified by command transfer during tuning operation.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Hai Pham 
> Cc: Jaehoon Chung 
> Cc: Nobuhiro Iwamatsu 
> Cc: Paul Barker 
> Cc: Peng Fan 
> Cc: Sean Anderson 
> Cc: Tom Rini 
> Cc: Yoshihiro Shimoda 
> ---
>  drivers/mmc/renesas-sdhi.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> index 9770b6bb5e1..316b75b35fe 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -798,9 +798,12 @@ static int renesas_sdhi_send_cmd(struct udevice *dev, 
> struct mmc_cmd *cmd,
>  #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
>  CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
>  CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
> + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
>   struct tmio_sd_priv *priv = dev_get_priv(dev);
> + struct mmc *mmc = upriv->mmc;
>  
> - renesas_sdhi_check_scc_error(dev);
> + if (!mmc->tuning)
> +     renesas_sdhi_check_scc_error(dev);
>  
>   if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
>   renesas_sdhi_adjust_hs400_mode_enable(priv);

Reviewed-by: Paul Barker 
Tested-by: Paul Barker 
  (tested on RZ/G2L with commit ad50a8151387 from
  https://source.denx.de/u-boot/custodians/u-boot-sh)

-- 
Paul Barker


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Re: [PATCH 2/3] mmc: Add generic tuning flag

[Paul Barker]

On 20/02/2024 08:37, Marek Vasut wrote:
> Set generic mmc->tuning flag when performing tuning to indicate
> this condition to drivers. Drivers may use this to bypass various
> checks during tuning.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Hai Pham 
> Cc: Jaehoon Chung 
> Cc: Nobuhiro Iwamatsu 
> Cc: Paul Barker 
> Cc: Peng Fan 
> Cc: Sean Anderson 
> Cc: Tom Rini 
> Cc: Yoshihiro Shimoda 
> ---
>  drivers/mmc/mmc-uclass.c | 8 +++-
>  include/mmc.h| 1 +
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
> index 328456831dd..304bd5eaee2 100644
> --- a/drivers/mmc/mmc-uclass.c
> +++ b/drivers/mmc/mmc-uclass.c
> @@ -124,7 +124,13 @@ static int dm_mmc_execute_tuning(struct udevice *dev, 
> uint opcode)
>  
>  int mmc_execute_tuning(struct mmc *mmc, uint opcode)
>  {
> - return dm_mmc_execute_tuning(mmc->dev, opcode);
> + int ret;
> +
> + mmc->tuning = true;
> + ret = dm_mmc_execute_tuning(mmc->dev, opcode);
> + mmc->tuning = false;
> +
> + return ret;
>  }
>  #endif
>  
> diff --git a/include/mmc.h b/include/mmc.h
> index 92cffc6a19a..47ccf5f45a1 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -736,6 +736,7 @@ struct mmc {
> * accessing the boot partitions
> */
>   u32 quirks;
> + bool tuning;
>   bool hs400_tuning;
>  
>   enum bus_mode user_speed_mode; /* input speed mode from user */

Reviewed-by: Paul Barker 
Tested-by: Paul Barker 
  (tested on RZ/G2L with commit ad50a8151387 from
  https://source.denx.de/u-boot/custodians/u-boot-sh)

-- 
Paul Barker


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Re: [PATCH 1/3] mmc: Convert hs400_tuning flag from u8 to bool

[Paul Barker]

On 20/02/2024 08:37, Marek Vasut wrote:
> This hs400_tuning is a flag, make it bool. No functional change.
> This will be useful in the following patch, which adds another
> more generic flag, where the compiler can better use the space
> now reserved for the u8 to store more flags in it.

The minimum size for a bool is one byte so there likely won't be any
improvement in struct size from using bool instead of u8 for
`hs400_tuning` here and `tuning` added in the next patch. I still think
it's a good change to make though, bool is the right type for an on/off
flag.

So I think the commit message needs a little clarification. Other than
that,

Reviewed-by: Paul Barker 
Tested-by: Paul Barker 
  (tested on RZ/G2L with commit ad50a8151387 from
  https://source.denx.de/u-boot/custodians/u-boot-sh)

Thanks,

-- 
Paul Barker

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Re: [PATCH] mmc: Drop unused mmc_send_tuning() cmd_error parameter

[Paul Barker]

On 20/02/2024 08:36, Marek Vasut wrote:
> The cmd_error parameter is not used, remove it.
>  [snip]
> 
> diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
> index 5a0c61daed5..296aaee7331 100644
> --- a/drivers/mmc/mtk-sd.c
> +++ b/drivers/mmc/mtk-sd.c
> @@ -1131,7 +1131,7 @@ static int hs400_tune_response(struct udevice *dev, u32 
> opcode)
>   i << PAD_CMD_TUNE_RX_DLY3_S);
>  
>   for (j = 0; j < 3; j++) {
> - mmc_send_tuning(mmc, opcode, &cmd_err);
> + cmd_err = mmc_send_tuning(mmc, opcode);
>   if (!cmd_err) {
>   cmd_delay |= (1 << i);
>   } else {
> @@ -1181,7 +1181,7 @@ static int msdc_tune_response(struct udevice *dev, u32 
> opcode)
>   i << MSDC_PAD_TUNE_CMDRDLY_S);
>  
>   for (j = 0; j < 3; j++) {
> - mmc_send_tuning(mmc, opcode, &cmd_err);
> + cmd_err = mmc_send_tuning(mmc, opcode);
>   if (!cmd_err) {
>   rise_delay |= (1 << i);
>   } else {
> @@ -1203,7 +1203,7 @@ static int msdc_tune_response(struct udevice *dev, u32 
> opcode)
>   i << MSDC_PAD_TUNE_CMDRDLY_S);
>  
>   for (j = 0; j < 3; j++) {
> - mmc_send_tuning(mmc, opcode, &cmd_err);
> + cmd_err = mmc_send_tuning(mmc, opcode);
>   if (!cmd_err) {
>   fall_delay |= (1 << i);
>   } else {
> @@ -1238,7 +1238,7 @@ skip_fall:
>   clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
>   i << MSDC_PAD_TUNE_CMDRRDLY_S);
>  
> - mmc_send_tuning(mmc, opcode, &cmd_err);
> + cmd_err = mmc_send_tuning(mmc, opcode);
>   if (!cmd_err)
>   internal_delay |= (1 << i);
>   }
> @@ -1264,7 +1264,6 @@ static int msdc_tune_data(struct udevice *dev, u32 
> opcode)
>   struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
>   u8 final_delay, final_maxlen;
>   void __iomem *tune_reg = &host->base->pad_tune;
> - int cmd_err;
>   int i, ret;
>  
>   if (host->dev_comp->pad_tune0)
> @@ -1277,10 +1276,10 @@ static int msdc_tune_data(struct udevice *dev, u32 
> opcode)
>   clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
>   i << MSDC_PAD_TUNE_DATRRDLY_S);
>  
> - ret = mmc_send_tuning(mmc, opcode, &cmd_err);
> + ret = mmc_send_tuning(mmc, opcode);
>   if (!ret) {
>   rise_delay |= (1 << i);
> - } else if (cmd_err) {
> + } else {
>   /* in this case, retune response is needed */
>   ret = msdc_tune_response(dev, opcode);
>   if (ret)
> @@ -1300,10 +1299,10 @@ static int msdc_tune_data(struct udevice *dev, u32 
> opcode)
>   clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
>   i << MSDC_PAD_TUNE_DATRRDLY_S);
>  
> - ret = mmc_send_tuning(mmc, opcode, &cmd_err);
> + ret = mmc_send_tuning(mmc, opcode);
>   if (!ret) {
>   fall_delay |= (1 << i);
> - } else if (cmd_err) {
> + } else {
>   /* in this case, retune response is needed */
>   ret = msdc_tune_response(dev, opcode);
>   if (ret)

This driver (mtk-sd.c) seems to be the only one that really uses the
`cmd_error` parameter.

Looking at the implementation of mmc_send_tuning() in Linux, this
parameter is used so that a caller can differentiate between a command
error and a data error. I don't know enough details about MMC to
understand the distinction, but I assume there is some reason for this.
So I wonder if the mtk-sd driver will still work if those error paths
are taken for data errors and not just command errors. Has this change
been tested on some board which uses this driver?

Thanks,

-- 
Paul Barker

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Re: [PATCH 3/5] i2c: rzg2l: Add I2C driver for RZ/G2L family

[Paul Barker]

On 02/12/2023 18:18, Marek Vasut wrote:
> On 11/19/23 21:48, Paul Barker wrote:
>> On Sun, Nov 19, 2023 at 09:15:36PM +0100, Marek Vasut wrote:
>>> On 11/15/23 18:40, Paul Barker wrote:
>>>> This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044)
>>>> SoC, also known as the RIIC module.
>>>>
>>>> This patch is based on both the u-boot driver in the Renesas RZ BSP
>>>> 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.6 driver
>>>> (commit ffc253263a13).
>>>>
>>>> Support for deblocking the I2C bus is included as this may be needed
>>>> after triggering a reset via the Power Management IC (PMIC) over I2C
>>>> (the PMIC asserts the reset line before the SoC completes the I2C write
>>>> transaction with obvious bus locking effects). If the SDA line is
>>>> observed to be low during initialisation, we automatically attempt to
>>>> deblock.
>>>>
>>>> [1]: https://github.com/renesas-rz/renesas-u-boot-cip
>>>>
>>>> Signed-off-by: Paul Barker 
>>>
>>> The driver seems very similar to drivers/i2c/rcar_iic.c , can there be some
>>> code reuse ?
>>
>> My initial idea was to extend the R-Car iic driver but I quickly saw
>> that would be very messy. All the registers and bits are in different
>> places, the calculations are different (particularly in regard to
>> setting bus speed) and the read/write process has more edge cases for
>> the RZ/G2L. The bus recovery mechanism we use also doesn't exist on
>> previous R-Car SoCs.
>>
>> The Linux drivers for these modules are also separate, see
>> drivers/i2c/busses/i2c-sh_mobile.c (for R-Car and earlier SoCs) and
>> drivers/i2c/busses/i2c-riic.c (for RZ/G2L) in the Linux kernel.
> 
> Ah, I thought some of the registers were the same, but indeed the RZG 
> core is much more extensive.
> 
> You should either use devm_clk_*() in probe() or implement .remove 
> callback. With that fixed:
> 
> Reviewed-by: Marek Vasut 
> 
> And sorry for the delayed reply.

Here's an even more delayed reply from me! I've been busy on other work
but getting back to u-boot now.

Using devm_clk_get() in the probe function for this driver doesn't seem
to be needed. The `struct clk` is stored in a `struct riic_priv`, this
is allocated and freed automatically for each device as we set
`priv_auto` in the driver definition.

Thanks,

-- 
Paul Barker

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Re: [PATCH v5 08/11] doc: devicetree: Updates for devicetree-rebasing subtree

[Paul Barker]

On 14/02/2024 13:32, Sumit Garg wrote:
> On Wed, 14 Feb 2024 at 03:01, Paul Barker  
> wrote:
>> On 02/02/2024 13:05, Sumit Garg wrote:
>>> +Dependencies
>>> +
>>> +
>>> +The DT schema project must be installed in order to validate the DT schema
>>> +binding documents and validate DTS files using the DT schema. The DT schema
>>> +project can be installed with pip::
>>> +
>>> +pip3 install dtschema
>>
>> Unfortunately this won't work on recent distro versions, e.g. on Debian
>> 12 I get:
>>
>> error: externally-managed-environment
>>
>> × This environment is externally managed
>> ╰─> To install Python packages system-wide, try apt install
>> python3-xyz, where xyz is the package you are trying to
>> install.
>>
>> If you wish to install a non-Debian-packaged Python package,
>> create a virtual environment using python3 -m venv path/to/venv.
>> Then use path/to/venv/bin/python and path/to/venv/bin/pip. Make
>> sure you have python3-full installed.
>>
>> If you wish to install a non-Debian packaged Python application,
>> it may be easiest to use pipx install xyz, which will manage a
>> virtual environment for you. Make sure you have pipx installed.
>>
>> See /usr/share/doc/python3.11/README.venv for more information.
>>
>> note: If you believe this is a mistake, please contact your Python
>> installation or OS distribution provider. You can override this, at the
>> risk of breaking your Python installation or OS, by passing
>> --break-system-packages.
>> hint: See PEP 668 for the detailed specification.
>>
>> I don't have a good solution to recommend here - there's no consensus on
>> how to install Python tools for use in development. You could use
>> `pipx`, you could create a virtualenv, and I'm sure there are other
>> options as well. Perhaps we just need to leave it up to the reader to
>> find out how to install dtschema on their system.
> 
> I suppose you haven't installed python3-pip package [1] on your Debian
> 12. BTW, `pip3` is being used as the common way to install dtschema
> [2]. Also, every user may not be aware about python virtual
> environments. So it's better to provide the commonly used pip3 option
> for installation.

The python3-pip package is installed, it's the pip3 program that is
printing the error message I saw. This is the new behaviour in Debian
12, also seen in rolling distributions like Arch Linux and OpenSuSE
Tumbleweed since the middle of last year. There is a good guide to this
from Python=>Speed [1] and more detail in the Python packaging spec [2].
Sadly it's something we now have to live with in recent Linux distro
releases, and I expect all distros will enable this in upcoming
releases.

[1]: https://pythonspeed.com/articles/externally-managed-environment-pep-668/
[2]: 
https://packaging.python.org/en/latest/specifications/externally-managed-environments/#externally-managed-environments

Thanks,

-- 
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Re: [PATCH 2/2] doc: Rework the gcc section to reflect general build instructions

[Paul Barker]

On 15/02/2024 21:10, Tom Rini wrote:
> The first big issue is that the "gcc" file talked a lot about the
> general build requirements as well, but was titled in a gcc-centric
> manner. Solve this by renaming the file to compile.rst and more fully
> reflecting that it is general build instructions. Next, add a section
> about the prebuilt toolchains that are recommended (as they are the ones
> we use in CI), and update a few places to reference these vendor-neutral
> tools.
> 
> Next, we can include the reproducible builds section directly in the
> compile instructions rather than as a small standalone file.
> 
> Finally, we update the sandbox document to reflect both the name change
> as well as what is specifically required to build sandbox.
> 
> Signed-off-by: Tom Rini 
> ---
> Cc: Heinrich Schuchardt 
> ---
>  doc/arch/sandbox/sandbox.rst   |  5 ++-
>  doc/build/{gcc.rst => compile.rst} | 64 ++
>  doc/build/index.rst|  3 +-
>  doc/build/reproducible.rst | 27 -
>  4 files changed, 61 insertions(+), 38 deletions(-)
>  rename doc/build/{gcc.rst => compile.rst} (73%)
>  delete mode 100644 doc/build/reproducible.rst
> 
> diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
> index 5f8db126657f..f2ed5a25c115 100644
> --- a/doc/arch/sandbox/sandbox.rst
> +++ b/doc/arch/sandbox/sandbox.rst
> @@ -39,11 +39,12 @@ integers can only be built on 64-bit hosts.
>  
>  Note that standalone/API support is not available at present.
>  
> -
>  Prerequisites
>  -
>  
> -Install the dependencies noted in :doc:`../../build/gcc`.
> +In addition to the normal dependencies shows in the :doc:`general build
> +instructions <../../build/compile>` to enable display support SDL2 libraries
> +need to be available.

I find this a little unclear. Perhaps:

To enable display support, SDL2 libraries need to be available in
addition to the normal dependencies shown in the :doc:`general build
instructions <../../build/compile>`.

>  
>  
>  Basic Operation
> diff --git a/doc/build/gcc.rst b/doc/build/compile.rst
> similarity index 73%
> rename from doc/build/gcc.rst
> rename to doc/build/compile.rst
> index 3c6465772729..ef9c8545835a 100644
> --- a/doc/build/gcc.rst
> +++ b/doc/build/compile.rst
> @@ -1,11 +1,19 @@
> -Building with GCC
> -=
> +Building U-Boot
> +===
>  
>  Dependencies
>  
>  
> -For building U-Boot you need a GCC compiler for your host platform. If you
> -are not building on the target platform you further need  a GCC cross 
> compiler.
> +For building U-Boot you need the general build tools such as `make` and a C
> +compiler for your host platform. Next, if you are not building on the same
> +architecture as the target platform you further need a C cross compiler.
> +Furthermore, some target platforms require additional host tools to be 
> present
> +and their package names may vary slightly dependinng on the naming scheme 
> used

s/dependinng/depending/

Thanks,

-- 
Paul Barker

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Re: [PATCH 1/2] doc: Update our clang documentation to reflect current status

[Paul Barker]

On 15/02/2024 21:10, Tom Rini wrote:
> First, since this document was written the biggest challenges at the
> time are simply not applicable anymore. Second, we need to list the
> challenges which are preventing more platforms from being able to be
> built with Clang today.  Next, we update the general wording to be host
> distribution agnostic. Finally, the section about xenguest_arm64 issues
> is not present anymore.
> 
> Signed-off-by: Tom Rini 
> ---
> Cc: Mark Kettenis 
> This does leave the FreeBSD section unchanged and should likely be
> looked at again by someone with a BSD build machine available.
> ---
>  doc/build/clang.rst | 85 +++--
>  1 file changed, 21 insertions(+), 64 deletions(-)
> 
> diff --git a/doc/build/clang.rst b/doc/build/clang.rst
> index 09bb988e9236..d8c554982567 100644
> --- a/doc/build/clang.rst
> +++ b/doc/build/clang.rst
> @@ -1,34 +1,27 @@
>  Building with Clang
>  ===
>  
> -The biggest problem when trying to compile U-Boot with Clang is that almost 
> all
> -archs rely on storing gd in a global register and the Clang 3.5 user manual
> -states: "Clang does not support global register variables; this is unlikely 
> to
> -be implemented soon because it requires additional LLVM backend support."
> -
> -The ARM backend can be instructed not to use the r9 and x18 registers using
> --ffixed-r9 or -ffixed-x18 respectively. As global registers themselves are 
> not
> -supported inline assembly is needed to get and set the r9 or x18 value. This
> -leads to larger code then strictly necessary, but at least works.
> -
> -Debian based
> -
> -
> -Required packages can be installed via apt, e.g.
> -
> -.. code-block:: bash
> -
> -sudo apt-get install clang
> -
> -We make use of the CROSS_COMPILE variable to derive the build target which is
> -passed as the --target parameter to clang.
> -
> -The CROSS_COMPILE variable further determines the paths to other build
> -tools. As assembler we use the binary pointed to by '$(CROSS_COMPILE)as'
> -instead of the LLVM integrated assembler (IAS).
> -
> -Here is an example demonstrating building U-Boot for the Raspberry Pi 2
> -using clang:
> +In general terms, U-Boot support building with Clang as the C compiler and

s/support/supports/

> +building and booting our "sandbox" target is part of CI.

Are you saying that building the sandbox target with Clang then booting
it is part of CI? I think this sentence needs re-wording to make it a
little clearer.

Thanks,

-- 
Paul Barker

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Re: [PATCH v5 08/11] doc: devicetree: Updates for devicetree-rebasing subtree

[Paul Barker]

nstalled in order to validate the DT schema
> +binding documents and validate DTS files using the DT schema. The DT schema
> +project can be installed with pip::
> +
> +pip3 install dtschema

Unfortunately this won't work on recent distro versions, e.g. on Debian
12 I get:

error: externally-managed-environment

× This environment is externally managed
╰─> To install Python packages system-wide, try apt install
python3-xyz, where xyz is the package you are trying to
install.

If you wish to install a non-Debian-packaged Python package,
create a virtual environment using python3 -m venv path/to/venv.
Then use path/to/venv/bin/python and path/to/venv/bin/pip. Make
sure you have python3-full installed.

If you wish to install a non-Debian packaged Python application,
it may be easiest to use pipx install xyz, which will manage a
virtual environment for you. Make sure you have pipx installed.

See /usr/share/doc/python3.11/README.venv for more information.

note: If you believe this is a mistake, please contact your Python
installation or OS distribution provider. You can override this, at the
risk of breaking your Python installation or OS, by passing
--break-system-packages.
hint: See PEP 668 for the detailed specification.

I don't have a good solution to recommend here - there's no consensus on
how to install Python tools for use in development. You could use
`pipx`, you could create a virtualenv, and I'm sure there are other
options as well. Perhaps we just need to leave it up to the reader to
find out how to install dtschema on their system.

> +
> +Note that 'dtschema' installation requires 'swig' and Python development 
> files
> +installed first. Please, refer to the GCC build documentation for 
> installation
> +instructions :doc:`../../build/gcc`.
> +
> +Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be
> +installed. Ensure they are in your PATH (~/.local/bin by default).
> +
> +Recommended is also to install yamllint (used by dtschema when present). On

"You should also install yamllint"

> +Debian/Ubuntu systems::
> +
> +apt install yamllint
> +
> +Running checks
> +~~
> +
> +In order to perform validation of DTB files, use the ``dtbs_check`` target::
> +
> +make dtbs_check
> +
> +It is also possible to run checks with a subset of matching schema files by
> +setting the ``DT_SCHEMA_FILES`` variable to 1 or more specific schema files 
> or
> +patterns (partial match of a fixed string). Each file or pattern should be
> +separated by ':'.
> +
> +::
> +
> +make dtbs_check DT_SCHEMA_FILES=trivial-devices.yaml:rtc.yaml
> +make dtbs_check DT_SCHEMA_FILES=/gpio/
> +make dtbs_check DT_SCHEMA_FILES=trivial-devices.yaml
> +
> +
>  Relocation, SPL and TPL
>  ---
>  
> @@ -260,8 +336,9 @@ used it before Linux (e.g. snow). The two projects 
> developed in parallel
>  and there are still some differences in the bindings for certain boards.
>  While there has been discussion of having a separate repository for 
> devicetree
>  files, in practice the Linux kernel Git repository has become the place where
> -these are stored, with U-Boot taking copies and adding tweaks with 
> u-boot.dtsi
> -files.
> +these are stored, with U-Boot taking copies via devicetree-rebasing repo
> +(see: dtrepo_) and adding tweaks with u-boot.dtsi files.
>  
>  .. _dtspec: https://www.devicetree.org/specifications/
>  .. _dtlist: https://www.spinics.net/lists/devicetree-compiler/
> +.. _dtrepo: 
> https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

Thanks,

-- 
Paul Barker

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Re: [PATCH 3/3] ARM: renesas: Enable LTO on R-Car

[Paul Barker]

On 11/02/2024 17:34, Marek Vasut wrote:
> Enable LTO globally on Renesas R-Car platforms. This has been enabled
> on a subset of boards already, but at this point it is safe to enable
> it globally. This saves units or tens of kiB from the resulting build.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Niklas Söderlund 
> Cc: Paul Barker 
> ---
>  arch/arm/Kconfig | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Paul Barker 


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Re: [PATCH 2/3] ARM: renesas: Set R-Car Gen2 board size limit to 512 kiB

[Paul Barker]

On 11/02/2024 17:34, Marek Vasut wrote:
> The maximum size of u-boot.img on R-Car Gen2 is 0x8 or 512 kiB,
> set the limit to avoid overflows as new functionality gets pulled in.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Niklas Söderlund 
> Cc: Paul Barker 
> ---
>  Kconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Paul Barker 


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Re: [PATCH 1/3] ARM: renesas: Disable EFI on R-Car Gen2

[Paul Barker]

On 11/02/2024 17:34, Marek Vasut wrote:
> These systems are unlikely to use EFI as this functionality has not been
> enabled until it got pulled in by Kconfig default. This functionality
> does add some 60-70 kiB to the u-boot.img size, which overflows the size
> limit. Disable it.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Niklas Söderlund 
> Cc: Paul Barker 
> ---
>  configs/alt_defconfig | 2 ++
>  configs/blanche_defconfig | 2 ++
>  configs/gose_defconfig| 2 ++
>  configs/koelsch_defconfig | 2 ++
>  configs/lager_defconfig   | 2 ++
>  configs/porter_defconfig  | 2 ++
>  configs/silk_defconfig| 2 ++
>  configs/stout_defconfig   | 2 ++
>  8 files changed, 16 insertions(+)

Reviewed-by: Paul Barker 

OpenPGP_0x27F4B3459F002257.asc
Description: OpenPGP public key


OpenPGP_signature.asc
Description: OpenPGP digital signature

Re: [PATCH v2] net: phy: Use PHY MDIO address from DT if available

[Paul Barker]

On 28/01/2024 01:19, Marek Vasut wrote:
> In case the PHY is fully described in DT, use PHY MDIO address
> from DT directly instead of always using auto-detection. This
> also fixes the behavior of 'mdio list' in such DT setup, which
> now prints the PHY connected to the MAC correctly.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Joe Hershberger 
> Cc: Paul Barker 
> Cc: Ramon Fried 
> ---
> V2: This patch is generic replacement for
> - net: ravb: Use PHY MDIO address from DT if available
> - net: sh_eth: Use PHY MDIO address from DT if available
> ---
>  drivers/net/phy/ethernet_id.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c
> index 877a51c3d00..6cb1fd4453e 100644
> --- a/drivers/net/phy/ethernet_id.c
> +++ b/drivers/net/phy/ethernet_id.c
> @@ -71,6 +71,9 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, 
> struct udevice *dev,
>   }
>   }
>  
> + if (phyaddr == -1)
> + phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1);
> +
>   id =  vendor << 16 | device;
>   phydev = phy_device_create(bus, phyaddr, id, false);
>   if (phydev)

Reviewed-by: Paul Barker 

OpenPGP_0x27F4B3459F002257.asc
Description: OpenPGP public key


OpenPGP_signature.asc
Description: OpenPGP digital signature

Re: [PATCH 3/3] ARM: renesas: Drop include common.h

[Paul Barker]

On 21/01/2024 17:31, Marek Vasut wrote:
> The header file is not necessary in either of those files,
> remove it as common.h is going away.
> 
> Include missing asm/arch/rmobile.h in board/renesas/rcar-common/v3-common.c
> to prevent build failure of r8a77970_eagle r8a779a0_falcon r8a77980_v3hsk
> and r8a77970_v3msk .
> 
> Include missing asm/u-boot.h in falcon.c and grpeach.c to fix build failure
> due to missing definition of struct bd_info . Include errno.h in grpeach.c
> to fix build error due to missing definition of EINVAL.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Adam Ford 
> Cc: Paul Barker 
> ---
>  board/renesas/alt/alt.c   | 1 -
>  board/renesas/alt/alt_spl.c   | 1 -
>  board/renesas/alt/qos.c   | 1 -
>  board/renesas/blanche/blanche.c   | 1 -
>  board/renesas/blanche/qos.c   | 1 -
>  board/renesas/draak/draak.c   | 1 -
>  board/renesas/falcon/falcon.c | 2 +-
>  board/renesas/gose/gose.c | 1 -
>  board/renesas/gose/gose_spl.c | 1 -
>  board/renesas/gose/qos.c  | 1 -
>  board/renesas/grpeach/grpeach.c   | 3 ++-
>  board/renesas/koelsch/koelsch.c   | 1 -
>  board/renesas/koelsch/koelsch_spl.c   | 1 -
>  board/renesas/koelsch/qos.c   | 1 -
>  board/renesas/lager/lager.c   | 1 -
>  board/renesas/lager/lager_spl.c   | 1 -
>  board/renesas/lager/qos.c | 1 -
>  board/renesas/porter/porter.c | 1 -
>  board/renesas/porter/porter_spl.c | 1 -
>  board/renesas/porter/qos.c| 1 -
>  board/renesas/r2dplus/r2dplus.c   | 1 -
>  board/renesas/rcar-common/common.c| 1 -
>  board/renesas/rcar-common/gen3-spl.c  | 1 -
>  board/renesas/rcar-common/v3-common.c | 2 +-
>  board/renesas/salvator-x/salvator-x.c | 1 -
>  board/renesas/silk/qos.c  | 1 -
>  board/renesas/silk/silk.c | 1 -
>  board/renesas/silk/silk_spl.c | 1 -
>  board/renesas/spider/spider.c | 1 -
>  board/renesas/stout/cpld.c| 1 -
>  board/renesas/stout/qos.c | 1 -
>  board/renesas/stout/stout.c   | 1 -
>  board/renesas/stout/stout_spl.c   | 1 -
>  board/renesas/ulcb/cpld.c | 1 -
>  board/renesas/ulcb/ulcb.c | 1 -
>  board/renesas/v3hsk/cpld.c| 1 -
>  board/renesas/v3msk/cpld.c| 1 -
>  board/renesas/whitehawk/whitehawk.c   | 1 -
>  38 files changed, 4 insertions(+), 38 deletions(-)
> 
> diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
> index 85fbaf0b28b..be77cade01b 100644
> --- a/board/renesas/alt/alt.c
> +++ b/board/renesas/alt/alt.c
> @@ -5,7 +5,6 @@
>   * Copyright (C) 2014, 2015 Renesas Electronics Corporation
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/board/renesas/alt/alt_spl.c b/board/renesas/alt/alt_spl.c
> index cdaa04e4f4c..fc9dac55e6a 100644
> --- a/board/renesas/alt/alt_spl.c
> +++ b/board/renesas/alt/alt_spl.c
> @@ -5,7 +5,6 @@
>   * Copyright (C) 2018 Marek Vasut 
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c
> index 2f657505ceb..38dfa647e81 100644
> --- a/board/renesas/alt/qos.c
> +++ b/board/renesas/alt/qos.c
> @@ -6,7 +6,6 @@
>   *
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
> index 8e1ae29e221..c6ecea2afcf 100644
> --- a/board/renesas/blanche/blanche.c
> +++ b/board/renesas/blanche/blanche.c
> @@ -6,7 +6,6 @@
>   * Copyright (C) 2016 Renesas Electronics Corporation
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/board/renesas/blanche/qos.c b/board/renesas/blanche/qos.c
> index e3ad83ee0c2..3134b36a443 100644
> --- a/board/renesas/blanche/qos.c
> +++ b/board/renesas/blanche/qos.c
> @@ -5,7 +5,6 @@
>   * Copyright (C) 2016 Renesas Electronics Corporation
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
> index 1ed72d34a74..06a3a832984 100644
> --- a/board/renesas/draak/draak.c
> +++ b/board/renesas/draak/draak.c
> @@ -6,7 +6,6 @@
>   * Copyright (C) 2017 Marek Vasut 
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
> index 0aa0f1afcbf..cd86bb3108c 100644
> --- a/board/renesas/falcon/falcon.c
> +++ b/board/renesas/falcon/falcon.c
> @@ -6,7 +6,6 @@
>   * Copyright (C) 2020 Renesas Electronics Corp.
>   */
>  
>

Re: [PATCH 2/3] pinctrl: renesas: Drop include common.h

[Paul Barker]

On 21/01/2024 17:31, Marek Vasut wrote:
> The header file is not necessary in either of those files,
> remove it as common.h is going away.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Paul Barker 
> ---
>  drivers/pinctrl/renesas/pfc-r8a7790.c  | 1 -
>  drivers/pinctrl/renesas/pfc-r8a7791.c  | 1 -
>  drivers/pinctrl/renesas/pfc-r8a7792.c  | 1 -
>  drivers/pinctrl/renesas/pfc-r8a7794.c  | 1 -
>  drivers/pinctrl/renesas/pfc-r8a77951.c | 1 -
>  drivers/pinctrl/renesas/pfc-r8a7796.c  | 1 -
>  drivers/pinctrl/renesas/pfc-r8a77965.c | 1 -
>  drivers/pinctrl/renesas/pfc-r8a77970.c | 1 -
>  drivers/pinctrl/renesas/pfc-r8a77980.c | 1 -
>  drivers/pinctrl/renesas/pfc-r8a77990.c | 1 -
>  drivers/pinctrl/renesas/pfc-r8a77995.c | 1 -
>  drivers/pinctrl/renesas/pfc-r8a779a0.c | 1 -
>  drivers/pinctrl/renesas/pfc-r8a779f0.c | 1 -
>  drivers/pinctrl/renesas/pfc-r8a779g0.c | 1 -
>  drivers/pinctrl/renesas/pfc.c  | 1 -
>  drivers/pinctrl/renesas/pinctrl-rza1.c | 1 -
>  16 files changed, 16 deletions(-)
> 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c 
> b/drivers/pinctrl/renesas/pfc-r8a7790.c
> index 7203648bbc8..e1811c4c908 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a7790.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
> @@ -8,7 +8,6 @@
>   * Copyright (C) 2012  Kuninori Morimoto 
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c 
> b/drivers/pinctrl/renesas/pfc-r8a7791.c
> index b25453ed285..fa94a51e5e7 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a7791.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
> @@ -6,7 +6,6 @@
>   * Copyright (C) 2014-2017 Cogent Embedded, Inc.
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c 
> b/drivers/pinctrl/renesas/pfc-r8a7792.c
> index 08f1f97af6e..7c1e6d40749 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a7792.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c
> @@ -6,7 +6,6 @@
>   * Copyright (C) 2016 Cogent Embedded, Inc., 
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c 
> b/drivers/pinctrl/renesas/pfc-r8a7794.c
> index e5d125ceca0..29eab2610c1 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a7794.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c
> @@ -7,7 +7,6 @@
>   * Copyright (C) 2015-2017 Cogent Embedded, Inc. 
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c 
> b/drivers/pinctrl/renesas/pfc-r8a77951.c
> index 5d1c81c3eae..81568ae4a5e 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a77951.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
> @@ -5,7 +5,6 @@
>   * Copyright (C) 2015-2019 Renesas Electronics Corporation
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c 
> b/drivers/pinctrl/renesas/pfc-r8a7796.c
> index 163d1805dfb..3de43febbd3 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a7796.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
> @@ -11,7 +11,6 @@
>   * Copyright (C) 2015  Renesas Electronics Corporation
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c 
> b/drivers/pinctrl/renesas/pfc-r8a77965.c
> index 377143d3918..3a6813cee61 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a77965.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
> @@ -12,7 +12,6 @@
>   * Copyright (C) 2015  Renesas Electronics Corporation
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c 
> b/drivers/pinctrl/renesas/pfc-r8a77970.c
> index 1cc6fa4f3fc..3c9c060d245 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a77970.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
> @@ -12,7 +12,6 @@
>   * Copyright (C) 2015  Renesas Electronics Corporation
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c 
> b/drivers/pinctrl/renesas/pfc-r8a77980.c
> index 523faa0ac8f..14a4b4dc731 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a77980.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
> @@ -12,7 +12,6 @@
>   * Copyright (C) 2015 Renesas Electronics Corporation
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c 
> b/drivers/pinctrl/renesas/pfc-r8a77990.c
> index 215a19ef9cd..e3a9c5e053d 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a77990.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
> @@

Re: [PATCH 1/3] clk: renesas: Drop include common.h

[Paul Barker]

On 21/01/2024 17:31, Marek Vasut wrote:
> The header file is not necessary in either of those files,
> remove it as common.h is going away.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Lukasz Majewski 
> Cc: Paul Barker 
> Cc: Sean Anderson 
> ---
>  drivers/clk/renesas/clk-rcar-gen2.c | 1 -
>  drivers/clk/renesas/clk-rcar-gen3.c | 1 -
>  drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a774b1-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a774e1-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a7790-cpg-mssr.c  | 1 -
>  drivers/clk/renesas/r8a7791-cpg-mssr.c  | 1 -
>  drivers/clk/renesas/r8a7792-cpg-mssr.c  | 1 -
>  drivers/clk/renesas/r8a7794-cpg-mssr.c  | 1 -
>  drivers/clk/renesas/r8a7795-cpg-mssr.c  | 1 -
>  drivers/clk/renesas/r8a7796-cpg-mssr.c  | 1 -
>  drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r8a779g0-cpg-mssr.c | 1 -
>  drivers/clk/renesas/r9a06g032-clocks.c  | 1 -
>  drivers/clk/renesas/rcar-cpg-lib.c  | 1 -
>  drivers/clk/renesas/renesas-cpg-mssr.c  | 1 -
>  23 files changed, 23 deletions(-)
> 
> diff --git a/drivers/clk/renesas/clk-rcar-gen2.c 
> b/drivers/clk/renesas/clk-rcar-gen2.c
> index 850d6411190..66ffef96b69 100644
> --- a/drivers/clk/renesas/clk-rcar-gen2.c
> +++ b/drivers/clk/renesas/clk-rcar-gen2.c
> @@ -10,7 +10,6 @@
>   * Copyright (C) 2016 Glider bvba
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/clk/renesas/clk-rcar-gen3.c 
> b/drivers/clk/renesas/clk-rcar-gen3.c
> index 0d274bb986e..196903e406c 100644
> --- a/drivers/clk/renesas/clk-rcar-gen3.c
> +++ b/drivers/clk/renesas/clk-rcar-gen3.c
> @@ -10,7 +10,6 @@
>   * Copyright (C) 2016 Glider bvba
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c 
> b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> index 6f94906cc99..d23041a8026 100644
> --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> @@ -9,7 +9,6 @@
>   * Copyright (C) 2016 Glider bvba
>   */
>  
> -#include 
>  #include 
>  #include 
>  
> diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c 
> b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> index 1a794980319..81d7dfe5421 100644
> --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
> @@ -9,7 +9,6 @@
>   * Copyright (C) 2016 Glider bvba
>   */
>  
> -#include 
>  #include 
>  #include 
>  
> diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c 
> b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> index ec8ce6ad7d6..f92fd25c0f7 100644
> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> @@ -10,7 +10,6 @@
>   * Copyright (C) 2015 Renesas Electronics Corp.
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c 
> b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
> index 6a8fe92b975..7c7cb7b6a05 100644
> --- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
> @@ -9,7 +9,6 @@
>   * Copyright (C) 2015 Glider bvba
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c 
> b/drivers/clk/renesas/r8a7790-cpg-mssr.c
> index 686f2af0052..190b68ee7d3 100644
> --- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
> @@ -9,7 +9,6 @@
>   * Copyright (C) 2013 Ideas On Board SPRL
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c 
> b/drivers/clk/renesas/r8a7791-cpg-mssr.c
> index dcb0fd85c52..30711bf8921 100644
> --- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
> @@ -9,7 +9,6 @@
>   * Copyright (C) 2013 Ideas On Board SPRL
>   */
>  
> -#include 
>  #include 
>  #include 
>  #include 
> diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c 
> b/drivers/clk/renesas/r8a7792-cpg-mssr.c
> index 496e51aa73f..623981e9c38 100644
> --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
> @@ -9,7 +9,6 @@
>   * Copyright (C) 2013 Ideas On Board SPRL
>   */
>  
> -#include 
>  

Re: [PATCH 3/3] net: ravb: Use PHY MDIO address from DT if available

[Paul Barker]

On 21/01/2024 17:29, Marek Vasut wrote:
> In case the PHY is fully described in DT, use PHY MDIO address
> from DT directly instead of always using auto-detection. This
> also fixes the behavior of 'mdio list' in such DT setup, which
> now prints the PHY connected to the MAC correctly.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Joe Hershberger 
> Cc: Paul Barker 
> Cc: Ramon Fried 
> ---
>  drivers/net/sh_eth.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)

I think the commit summaries are mixed up here - this patch says 'ravb'
but changes 'sh_eth.c' and vice-versa with the other patch.

> 
> diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
> index 7b1f59dc498..5e2e3054ecf 100644
> --- a/drivers/net/sh_eth.c
> +++ b/drivers/net/sh_eth.c
> @@ -12,6 +12,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -597,11 +598,16 @@ static int sh_eth_phy_config(struct udevice *dev)
>   struct sh_ether_priv *priv = dev_get_priv(dev);
>   struct eth_pdata *pdata = dev_get_plat(dev);
>   struct sh_eth_dev *eth = &priv->shdev;
> - int ret = 0;
>   struct sh_eth_info *port_info = ð->port_info[eth->port];
>   struct phy_device *phydev;
> + int phy_addr;
> + int ret = 0;
> +
> + phy_addr = eth_phy_get_addr(dev);
> + if (phy_addr < 0)
> + phy_addr = -1;
>  
> - phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface);
> + phydev = phy_connect(priv->bus, phy_addr, dev, pdata->phy_interface);
>   if (!phydev)
>   return -ENODEV;
>  

I have a local patch to handle (phy_addr < 0) in phy_connect_phy_id()
and lookup the address there. I think that's the better place to handle
this as it's a universal fix for all users of CONFIG_PHY_ETHERNET_ID.
Unfortunately I've been distracted by some higher priority work but I'm
hoping to get back to this soon.

I can do some quick testing with that patch and send it this week if
that's helpful.

Thanks,
Paul

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Re: [PATCH] ARM: renesas: whitehawk: Drop extra leading space

[Paul Barker]

On 21/01/2024 17:33, Marek Vasut wrote:
> Drop leading space in front of a comment. No functional change.
> 
> Signed-off-by: Marek Vasut 
> ---
> Cc: Paul Barker 
> ---
>  board/renesas/whitehawk/whitehawk.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/board/renesas/whitehawk/whitehawk.c 
> b/board/renesas/whitehawk/whitehawk.c
> index 3423ebd2995..a72f5e0a7a5 100644
> --- a/board/renesas/whitehawk/whitehawk.c
> +++ b/board/renesas/whitehawk/whitehawk.c
> @@ -31,7 +31,7 @@ static void init_generic_timer(void)
>  
>  static void init_gic_v3(void)
>  {
> -  /* GIC v3 power on */
> + /* GIC v3 power on */
>   writel(BIT(1), GICR_LPI_PWRR);
>  
>   /* Wait till the WAKER_CA_BIT changes to 0 */

Simple enough.

Reviewed-by: Paul Barker 

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Re: [PATCH 01/11] dt-bindings: power: Add R8A779H0 V4M SYSC power domain definitions

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Duy Nguyen 
> 
> Add power domain indices for R-Car V4M (R8A779H0).
> 
> Signed-off-by: Duy Nguyen 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  include/dt-bindings/power/r8a779h0-sysc.h | 49 +++
>  1 file changed, 49 insertions(+)
>  create mode 100644 include/dt-bindings/power/r8a779h0-sysc.h

We should reference the corresponding Linux kernel patch via
lore.kernel.org if this isn't in the mainline kernel yet.

Also, as a general series comment: I'd prefer to see a cover letter to
say which interfaces and key features are supported on the V4M by this
series. Is this enough to boot Linux from at least one interface (SDHI,
Ethernet, etc)?

Thanks,
Paul

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Re: [PATCH 02/11] dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Duy Nguyen 
> 
> Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
> V4M (R8A779H0) SoC.
> 
> Signed-off-by: Duy Nguyen 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  include/dt-bindings/clock/r8a779h0-cpg-mssr.h | 100 ++
>  1 file changed, 100 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r8a779h0-cpg-mssr.h

We should reference the corresponding Linux kernel patch via
lore.kernel.org if this isn't in the mainline kernel yet.

Thanks,
Paul

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Re: [PATCH 03/11] clk: renesas: Add R8A779H0 V4M clock tables

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Add clock tables for R8A779H0 V4M SoC.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Lukasz Majewski 
> Cc: Paul Barker 
> Cc: Sean Anderson 
> ---
>  drivers/clk/renesas/Kconfig |   6 +
>  drivers/clk/renesas/Makefile|   1 +
>  drivers/clk/renesas/r8a779h0-cpg-mssr.c | 294 
>  drivers/clk/renesas/rcar-gen3-cpg.h |   1 +
>  4 files changed, 302 insertions(+)
>  create mode 100644 drivers/clk/renesas/r8a779h0-cpg-mssr.c

How does this relate to the Linux kernel clk patch sent by Geert [1]? If
this patch is based on that, then we should have a link to that patch in
the commit message (since it hasn't appeared in a mainline kernel
release yet).

[1]: 
https://lore.kernel.org/all/0eb04b570d65d67de72069167e16d49e189dec54.1704726960.git.geert+rene...@glider.be/

Thanks,
Paul

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Re: [PATCH 06/11] mtd: spi: renesas: Add R8A779H0 V4M support

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Support RPC SPI on R8A779H0 V4M SoC.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Jagan Teki 
> Cc: Paul Barker 
> ---
>  drivers/spi/renesas_rpc_spi.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
> index 51c37d72eb6..3eb14061c81 100644
> --- a/drivers/spi/renesas_rpc_spi.c
> +++ b/drivers/spi/renesas_rpc_spi.c
> @@ -215,7 +215,8 @@ static u32 rpc_spi_get_strobe_delay(void)
>   if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && 
> rmobile_get_cpu_rev_integer() == 1)
>   return RPC_PHYCNT_STRTIM(6);
>   else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 ||
> -  cpu_type == RMOBILE_CPU_TYPE_R8A779G0)
> +  cpu_type == RMOBILE_CPU_TYPE_R8A779G0 ||
> +  cpu_type == RMOBILE_CPU_TYPE_R8A779H0)
>   return RPC_PHYCNT_STRTIM2(15);
>   else
>  #endif

Reviewed-by: Paul Barker 

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Re: [PATCH 07/11] ARM: renesas: Add R8A779H0 V4M Kconfig entry and PRR ID

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Add Kconfig entry and PRR ID to support R8A779H0 V4M SoC.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  arch/arm/mach-rmobile/Kconfig.rcar4  | 6 ++
>  arch/arm/mach-rmobile/cpu_info.c | 1 +
>  arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
>  3 files changed, 8 insertions(+)
> 
> diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 
> b/arch/arm/mach-rmobile/Kconfig.rcar4
> index d4f93c89cac..3c8d683974c 100644
> --- a/arch/arm/mach-rmobile/Kconfig.rcar4
> +++ b/arch/arm/mach-rmobile/Kconfig.rcar4
> @@ -20,6 +20,12 @@ config R8A779G0
>   imply CLK_R8A779G0
>   imply PINCTRL_PFC_R8A779G0
>  
> +config R8A779H0
> + bool "Renesas SoC R8A779H0"
> + select GICV3
> + imply CLK_R8A779H0
> + imply PINCTRL_PFC_R8A779H0
> +
>  endmenu
>  
>  choice
> diff --git a/arch/arm/mach-rmobile/cpu_info.c 
> b/arch/arm/mach-rmobile/cpu_info.c
> index 895c0f5336b..3d5d5ba79a9 100644
> --- a/arch/arm/mach-rmobile/cpu_info.c
> +++ b/arch/arm/mach-rmobile/cpu_info.c
> @@ -78,6 +78,7 @@ static const struct {
>   { RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
>   { RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
>   { RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
> + { RMOBILE_CPU_TYPE_R8A779H0, "R8A779H0" },
>   { 0x0, "CPU" },
>  };
>  
> diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h 
> b/arch/arm/mach-rmobile/include/mach/rmobile.h
> index 88b8b78671b..f0216210ba9 100644
> --- a/arch/arm/mach-rmobile/include/mach/rmobile.h
> +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
> @@ -43,6 +43,7 @@
>  #define RMOBILE_CPU_TYPE_R8A779A00x59
>  #define RMOBILE_CPU_TYPE_R8A779F00x5A
>  #define RMOBILE_CPU_TYPE_R8A779G00x5C
> +#define RMOBILE_CPU_TYPE_R8A779H00x5D
>  #define RMOBILE_CPU_TYPE_R9A07G044L  0x9A070440
>  
>  #ifndef __ASSEMBLY__

Reviewed-by: Paul Barker 

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Re: [PATCH 09/11] ARM: dts: renesas: Add Renesas R8A779H0 V4M DT extras

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Add Renesas R8A779H0 V4M DT extras for U-Boot.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  arch/arm/dts/r8a779h0-u-boot.dtsi | 27 +++
>  1 file changed, 27 insertions(+)
>  create mode 100644 arch/arm/dts/r8a779h0-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi 
> b/arch/arm/dts/r8a779h0-u-boot.dtsi
> new file mode 100644
> index 000..b2f7e054eef
> --- /dev/null
> +++ b/arch/arm/dts/r8a779h0-u-boot.dtsi
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
> + *
> + * Copyright (C) 2023 Renesas Electronics Corp.
> + */
> +
> +#include "r8a779x-u-boot.dtsi"
> +/ {
> + soc {
> + rpc: spi@ee20 {
> + compatible = "renesas,r8a779h0-rpc-if", 
> "renesas,rcar-gen4-rpc-if";
> + reg = <0 0xee20 0 0x200>, <0 0x0800 0 
> 0x0400>;
> + interrupts = ;
> + clocks = <&cpg CPG_MOD 629>;
> + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
> + resets = <&cpg 629>;
> + bank-width = <2>;
> + num-cs = <1>;
> + status = "disabled";
> + };

Either the commit message or a comment should give some idea why this
node is in a -u-boot.dtsi file instead of the r8a779h0.dtsi file itself.

Thanks,
Paul

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Re: [PATCH 08/11] ARM: dts: renesas: Add Renesas R8A779H0 V4M SoC support

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Add initial support for the Renesas R8A779H0 (R-Car V4M) SoC.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  arch/arm/dts/r8a779h0.dtsi | 461 +
>  1 file changed, 461 insertions(+)
>  create mode 100644 arch/arm/dts/r8a779h0.dtsi

Is this a sync from the Linux kernel? If so we should say which commit
the dtsi file is taken from.

Thanks,
Paul


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Re: [PATCH 10/11] ARM: dts: renesas: Add Renesas Gray Hawk boards support

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham 
> 
> Initial support for the Renesas Gray Hawk CPU and BreakOut boards.
> 
> Signed-off-by: Hai Pham 
> ---
> Cc: Paul Barker 
> ---
>  arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi  | 165 ++
>  arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi  |  15 ++
>  arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi |  15 ++
>  arch/arm/dts/r8a779h0-gray-hawk.dts   |  25 +++
>  4 files changed, 220 insertions(+)
>  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi
>  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi
>  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi
>  create mode 100644 arch/arm/dts/r8a779h0-gray-hawk.dts

Is this a sync from the Linux kernel? If so we should say which commit
the dts/dtsi files are taken from.

Thanks,
Paul

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Re: [PATCH 11/11] ARM: renesas: Add Renesas R8A779H0 V4M Gray Hawk board code

[Paul Barker]

On 21/01/2024 17:41, Marek Vasut wrote:
> diff --git a/board/renesas/grayhawk/MAINTAINERS 
> b/board/renesas/grayhawk/MAINTAINERS
> new file mode 100644
> index 000..b3532141ce7
> --- /dev/null
> +++ b/board/renesas/grayhawk/MAINTAINERS
> @@ -0,0 +1,7 @@
> +GRAYHAWK BOARD
> +M:   Marek Vasut 
> +S:   Maintained
> +F:   arch/arm/dts/r8a779h0*
> +F:   board/renesas/grayhawk/
> +F:   configs/r8a779h0_grayhawk_defconfig
> +F:   include/configs/grayhawk.h

You could use the following here to catch everything with 'r8a779h0' or
'grayhawk' in the filename:

  N:  r8a779h0
  N:  grayhawk

Otherwise, LGTM.

Reviewed-by: Paul Barker 

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Re: [PATCH 5/5] sysreset: Support reset via Renesas RAA215300 PMIC

[Paul Barker]

On Sun, Nov 19, 2023 at 09:17:40PM +0100, Marek Vasut wrote:
> On 11/15/23 18:40, Paul Barker wrote:
> > This patch allows us to reset the RZ/G2L board via the RAA215300 PMIC.
> > 
> > Note that the RAA215300 documentation names the available reset types
> > differently to u-boot:
> > 
> >- A "warm" reset via the RAA215300 PMIC will fully reset the SoC
> >  (CPU & GPIOs), so this corresponds to SYSRESET_COLD.
> > 
> >- A "cold" reset via the RAA215300 PMIC will cycle all power supply
> >  rails, so this corresponds to SYSRESET_POWER.
> > 
> > Signed-off-by: Paul Barker 
> > ---
> >   board/renesas/rzg2l/rzg2l.c   |  8 
> >   configs/renesas_rzg2l_smarc_defconfig |  2 +
> >   drivers/power/pmic/raa215300.c| 17 
> >   drivers/sysreset/Kconfig  |  6 +++
> >   drivers/sysreset/Makefile |  1 +
> >   drivers/sysreset/sysreset_raa215300.c | 58 +++
> >   6 files changed, 84 insertions(+), 8 deletions(-)
> >   create mode 100644 drivers/sysreset/sysreset_raa215300.c
> > 
> > diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
> > index 73201a8c69e5..0f6d6e7f514f 100644
> > --- a/board/renesas/rzg2l/rzg2l.c
> > +++ b/board/renesas/rzg2l/rzg2l.c
> > @@ -56,11 +56,3 @@ int board_init(void)
> >   {
> > return 0;
> >   }
> > -
> > -void reset_cpu(void)
> > -{
> > -   /*
> > -* TODO: Implement reset support once TrustedFirmware supports
> > -* the appropriate call.
> > -*/
> > -}
> 
> Board change -- separate patch please.

Ok, this makes sense. I'll move this and the defconfig change into a
separate patch.

> 
> > diff --git a/configs/renesas_rzg2l_smarc_defconfig 
> > b/configs/renesas_rzg2l_smarc_defconfig
> > index b62eae4ee0a4..ba96e746df9e 100644
> > --- a/configs/renesas_rzg2l_smarc_defconfig
> > +++ b/configs/renesas_rzg2l_smarc_defconfig
> > @@ -55,3 +55,5 @@ CONFIG_PMIC_RAA215300=y
> >   CONFIG_DM_REGULATOR=y
> >   CONFIG_DM_REGULATOR_FIXED=y
> >   CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_SYSRESET=y
> > +CONFIG_SYSRESET_RAA215300=y
> > diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
> > index 9c0b720994b2..7f68f95f25cf 100644
> > --- a/drivers/power/pmic/raa215300.c
> > +++ b/drivers/power/pmic/raa215300.c
> > @@ -27,9 +27,26 @@ static const struct udevice_id raa215300_ids[] = {
> > { /* sentinel */ }
> >   };
> > +static int raa215300_bind(struct udevice *dev)
> > +{
> > +   struct driver *drv;
> > +
> > +   if (IS_ENABLED(CONFIG_SYSRESET_RAA215300)) {
> > +   drv = lists_driver_lookup_name("raa215300_sysreset");
> > +   if (!drv)
> > +   return -ENOENT;
> > +
> > +   return device_bind(dev, drv, dev->name, NULL, dev_ofnode(dev),
> > +  NULL);
> > +   }
> > +
> > +   return 0;
> > +}
> 
> Driver change should be squashed in 4/5.

Moving this to the previous patch doesn't make sense to me - the
sysreset driver needs to exist for this check to be meaningful.
Conversely, adding the sysreset driver first then the pmic driver
wouldn't make sense since the sysreset driver depends on the pmic
driver. This seemed the neatest way to do things to me.

Thanks,
Paul


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Re: [PATCH 3/5] i2c: rzg2l: Add I2C driver for RZ/G2L family

[Paul Barker]

On Sun, Nov 19, 2023 at 09:15:36PM +0100, Marek Vasut wrote:
> On 11/15/23 18:40, Paul Barker wrote:
> > This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044)
> > SoC, also known as the RIIC module.
> > 
> > This patch is based on both the u-boot driver in the Renesas RZ BSP
> > 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.6 driver
> > (commit ffc253263a13).
> > 
> > Support for deblocking the I2C bus is included as this may be needed
> > after triggering a reset via the Power Management IC (PMIC) over I2C
> > (the PMIC asserts the reset line before the SoC completes the I2C write
> > transaction with obvious bus locking effects). If the SDA line is
> > observed to be low during initialisation, we automatically attempt to
> > deblock.
> > 
> > [1]: https://github.com/renesas-rz/renesas-u-boot-cip
> > 
> > Signed-off-by: Paul Barker 
> 
> The driver seems very similar to drivers/i2c/rcar_iic.c , can there be some
> code reuse ?

My initial idea was to extend the R-Car iic driver but I quickly saw
that would be very messy. All the registers and bits are in different
places, the calculations are different (particularly in regard to
setting bus speed) and the read/write process has more edge cases for
the RZ/G2L. The bus recovery mechanism we use also doesn't exist on
previous R-Car SoCs.

The Linux drivers for these modules are also separate, see
drivers/i2c/busses/i2c-sh_mobile.c (for R-Car and earlier SoCs) and
drivers/i2c/busses/i2c-riic.c (for RZ/G2L) in the Linux kernel.

Thanks,
Paul


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Re: [PATCH v2] net: designware: Add bitbang feature for designware driver

[Paul Barker]

On Fri, Nov 17, 2023 at 10:04:53AM +0800, Jim Liu wrote:
> Add bb_miiphy_bus function for designware bitbang feature.
> 
> Signed-off-by: Jim Liu 
> ---
> Changes for v2:
>- add bitbang delay dts read
>- modify printf to debug
> ---
>  drivers/net/designware.c | 105 +++
>  drivers/net/designware.h |   5 ++
>  2 files changed, 110 insertions(+)
> 
> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
> index a174344b3e..e86f96fc1a 100644
> --- a/drivers/net/designware.c
> +++ b/drivers/net/designware.c
> @@ -767,6 +767,31 @@ int designware_eth_probe(struct udevice *dev)
>   priv->bus = miiphy_get_dev_by_name(dev->name);
>   priv->dev = dev;
>  
> +#if defined(CONFIG_BITBANGMII) && CONFIG_IS_ENABLED(DM_GPIO)
> + if (dev_read_bool(dev, "snps,bitbang-mii")) {
> + debug("\n%s: use bitbang mii..\n", dev->name);
> + ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,
> +&priv->mdc_gpio, GPIOD_IS_OUT | 
> GPIOD_IS_OUT_ACTIVE);
> + if (ret) {
> + printf("no mdc-gpio\n");
> + return ret;
> + }
> + ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,
> +&priv->mdio_gpio, GPIOD_IS_OUT | 
> GPIOD_IS_OUT_ACTIVE);
> + if (ret) {
> + printf("no mdio-gpio\n");
> + return ret;
> + }
> +
> + priv->bb_delay = dev_read_u32_default(dev, 
> "snps,bitbang-delay", 1);
> +
> + bb_miiphy_buses[0].priv = priv;
> + sprintf(bb_miiphy_buses[0].name, dev->name);

If designware_eth_probe() is called for multiple Ethernet interfaces
then only the last interface to be probed will have a working MDIO bus.

We should either support multiple buses here or raise an error if there
is an attempt to probe a second interface.

(I spotted the same issue in the ravb driver while extending it to
support a board with two Ethernet interfaces)

Thanks,
Paul


signature.asc
Description: PGP signature

[PATCH 5/5] sysreset: Support reset via Renesas RAA215300 PMIC

[Paul Barker]

This patch allows us to reset the RZ/G2L board via the RAA215300 PMIC.

Note that the RAA215300 documentation names the available reset types
differently to u-boot:

  - A "warm" reset via the RAA215300 PMIC will fully reset the SoC
(CPU & GPIOs), so this corresponds to SYSRESET_COLD.

  - A "cold" reset via the RAA215300 PMIC will cycle all power supply
rails, so this corresponds to SYSRESET_POWER.

Signed-off-by: Paul Barker 
---
 board/renesas/rzg2l/rzg2l.c   |  8 
 configs/renesas_rzg2l_smarc_defconfig |  2 +
 drivers/power/pmic/raa215300.c| 17 
 drivers/sysreset/Kconfig  |  6 +++
 drivers/sysreset/Makefile |  1 +
 drivers/sysreset/sysreset_raa215300.c | 58 +++
 6 files changed, 84 insertions(+), 8 deletions(-)
 create mode 100644 drivers/sysreset/sysreset_raa215300.c

diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
index 73201a8c69e5..0f6d6e7f514f 100644
--- a/board/renesas/rzg2l/rzg2l.c
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -56,11 +56,3 @@ int board_init(void)
 {
return 0;
 }
-
-void reset_cpu(void)
-{
-   /*
-* TODO: Implement reset support once TrustedFirmware supports
-* the appropriate call.
-*/
-}
diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index b62eae4ee0a4..ba96e746df9e 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -55,3 +55,5 @@ CONFIG_PMIC_RAA215300=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_RAA215300=y
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
index 9c0b720994b2..7f68f95f25cf 100644
--- a/drivers/power/pmic/raa215300.c
+++ b/drivers/power/pmic/raa215300.c
@@ -27,9 +27,26 @@ static const struct udevice_id raa215300_ids[] = {
{ /* sentinel */ }
 };
 
+static int raa215300_bind(struct udevice *dev)
+{
+   struct driver *drv;
+
+   if (IS_ENABLED(CONFIG_SYSRESET_RAA215300)) {
+   drv = lists_driver_lookup_name("raa215300_sysreset");
+   if (!drv)
+   return -ENOENT;
+
+   return device_bind(dev, drv, dev->name, NULL, dev_ofnode(dev),
+  NULL);
+   }
+
+   return 0;
+}
+
 U_BOOT_DRIVER(raa215300_pmic) = {
.name = "raa215300_pmic",
.id = UCLASS_PMIC,
.of_match = raa215300_ids,
+   .bind = raa215300_bind,
.ops = &raa215300_ops,
 };
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 0e52f996283c..49c0787b26d8 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -229,6 +229,12 @@ config SYSRESET_MPC83XX
help
  Reboot support for NXP MPC83xx SoCs.
 
+config SYSRESET_RAA215300
+   bool "Support sysreset via Renesas RAA215300 PMIC"
+   depends on PMIC_RAA215300
+   help
+ Add support for the system reboot via the Renesas RAA215300 PMIC.
+
 endif
 
 endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index c9f1c625aebb..e0e732205df3 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
 obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
+obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_raa215300.c 
b/drivers/sysreset/sysreset_raa215300.c
new file mode 100644
index ..32dfcb0aec84
--- /dev/null
+++ b/drivers/sysreset/sysreset_raa215300.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+
+#define RAA215300_REG_SWRESET  0x6D
+#define RAA215300_COLD_RESET   BIT(0)
+#define RAA215300_WARM_RESET   BIT(1)
+
+static int raa215300_sysreset_request(struct udevice *dev, enum sysreset_t 
type)
+{
+   struct udevice *pmic = dev_get_parent(dev);
+   int ret;
+   u8 val;
+
+   /*
+* The RAA215300 documentation names the available reset types
+* differently to u-boot:
+*
+*   - A "warm" reset via the RAA215300 PMIC will fully reset the SoC
+* (CPU & GPIOs), so this corresponds to SYSRESET_COLD.
+*
+*   - A "cold" reset via the RAA215300 PMIC will cycle all power supply
+* rails, so this corresponds to SYSRESET_POWER.
+*/
+   switch (type) {
+   case SYSRESET_COLD:
+   val = RAA215300_WARM_RESET;
+   break;
+
+   case SYSRESET_POWER:
+   val = RAA215300_COLD_RESET;
+   break

[PATCH 4/5] pmic: Add Renesas RAA215300 PMIC driver

[Paul Barker]

The RZ/G2L SMARC module is powered via a Renesas RAA215300 PMIC which
provides several voltage converters, a real time clock (RTC) and reset
control. A basic driver is implemented for this device so that we can
read, write and dump the PMIC registers.

Additional features of this PMIC (such as reset control) may be
supported by future patches.

Signed-off-by: Paul Barker 
---
 configs/renesas_rzg2l_smarc_defconfig |  3 +++
 drivers/power/pmic/Kconfig|  9 +++
 drivers/power/pmic/Makefile   |  1 +
 drivers/power/pmic/raa215300.c| 35 +++
 4 files changed, 48 insertions(+)
 create mode 100644 drivers/power/pmic/raa215300.c

diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index acf9e6a9f4f5..b62eae4ee0a4 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
+CONFIG_CMD_PMIC=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -49,6 +50,8 @@ CONFIG_DM_I2C=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RAA215300=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 454a6e0cf87a..9b61b18e11fd 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -404,6 +404,15 @@ config PMIC_TPS65219
help
The TPS65219 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
+
+config PMIC_RAA215300
+   bool "Renesas RAA215300 PMIC driver"
+   depends on DM_PMIC
+   help
+ The Renesas RAA215300 PMIC driver includes RTC support, system reset
+ support and several voltage regulators. For now, this driver simply
+ allows register access and will bind the sysreset driver
+ (CONFIG_SYSRESET_RAA215300) if it is enabled.
 endif
 
 config PMIC_TPS65217
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 55ee614364be..a2d59deeed8b 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
 obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
 obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
 obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
+obj-$(CONFIG_PMIC_RAA215300) += raa215300.o
 obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
 
 ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
new file mode 100644
index ..9c0b720994b2
--- /dev/null
+++ b/drivers/power/pmic/raa215300.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RAA215300_REG_COUNT 0x80
+
+static int raa215300_reg_count(struct udevice *dev)
+{
+   return RAA215300_REG_COUNT;
+}
+
+static struct dm_pmic_ops raa215300_ops = {
+   .reg_count = raa215300_reg_count,
+   .read = dm_i2c_read,
+   .write = dm_i2c_write,
+};
+
+static const struct udevice_id raa215300_ids[] = {
+   { .compatible = "renesas,raa215300" },
+   { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(raa215300_pmic) = {
+   .name = "raa215300_pmic",
+   .id = UCLASS_PMIC,
+   .of_match = raa215300_ids,
+   .ops = &raa215300_ops,
+};
-- 
2.39.2

[PATCH 3/5] i2c: rzg2l: Add I2C driver for RZ/G2L family

[Paul Barker]

This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044)
SoC, also known as the RIIC module.

This patch is based on both the u-boot driver in the Renesas RZ BSP
3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.6 driver
(commit ffc253263a13).

Support for deblocking the I2C bus is included as this may be needed
after triggering a reset via the Power Management IC (PMIC) over I2C
(the PMIC asserts the reset line before the SoC completes the I2C write
transaction with obvious bus locking effects). If the SDA line is
observed to be low during initialisation, we automatically attempt to
deblock.

[1]: https://github.com/renesas-rz/renesas-u-boot-cip

Signed-off-by: Paul Barker 
---
 arch/arm/mach-rmobile/Kconfig |   1 +
 configs/renesas_rzg2l_smarc_defconfig |   2 +
 drivers/i2c/Kconfig   |   7 +
 drivers/i2c/Makefile  |   1 +
 drivers/i2c/rz_riic.c | 626 ++
 5 files changed, 637 insertions(+)
 create mode 100644 drivers/i2c/rz_riic.c

diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 2bb96749fc0d..38ede6e0b5b5 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -78,6 +78,7 @@ config RZG2L
imply RENESAS_SDHI
imply RZG2L_GPIO
imply SCIF_CONSOLE
+   imply SYS_I2C_RZ_RIIC
imply SYS_MALLOC_F
help
  Enable support for the Renesas RZ/G2L family of SoCs. Currently
diff --git a/configs/renesas_rzg2l_smarc_defconfig 
b/configs/renesas_rzg2l_smarc_defconfig
index e17d22695787..acf9e6a9f4f5 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -24,6 +24,7 @@ CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_PBSIZE=2068
 CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_EXT2=y
@@ -44,6 +45,7 @@ CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 # CONFIG_CLK_RCAR_GEN3 is not set
 CONFIG_GPIO_HOG=y
+CONFIG_DM_I2C=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 4f42200f3923..d2a3a13493aa 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -524,6 +524,13 @@ config SYS_I2C_ROCKCHIP
  have several I2C ports and all are provided, controlled by the
  device tree.
 
+config SYS_I2C_RZ_RIIC
+   bool "Renesas RZ/G2L RIIC driver"
+   depends on RZG2L && DM_I2C
+   help
+ Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC
+ family.
+
 config SYS_I2C_SANDBOX
bool "Sandbox I2C driver"
depends on SANDBOX && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index a96a8c7e955e..692f63bafd02 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
 obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
+obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o
 obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
 obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c
new file mode 100644
index ..734ed084f666
--- /dev/null
+++ b/drivers/i2c/rz_riic.c
@@ -0,0 +1,626 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RZ/G2L I2C (RIIC) driver
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RIIC_ICCR1 0x00
+#define RIIC_ICCR2 0x04
+#define RIIC_ICMR1 0x08
+#define RIIC_ICMR2 0x0c
+#define RIIC_ICMR3 0x10
+#define RIIC_ICFER 0x14
+#define RIIC_ICSER 0x18
+#define RIIC_ICIER 0x1c
+#define RIIC_ICSR1 0x20
+#define RIIC_ICSR2 0x24
+#define RIIC_ICSAR00x28
+#define RIIC_ICBRL 0x34
+#define RIIC_ICBRH 0x38
+#define RIIC_ICDRT 0x3c
+#define RIIC_ICDRR 0x40
+
+/* ICCR1 */
+#define ICCR1_ICE  BIT(7)
+#define ICCR1_IICRST   BIT(6)
+#define ICCR1_CLO  BIT(5)
+#define ICCR1_SOWP BIT(4)
+#define ICCR1_SCLO BIT(3)
+#define ICCR1_SDAO BIT(2)
+#define ICCR1_SCLI BIT(1)
+#define ICCR1_SDAI BIT(0)
+
+/* ICCR2 */
+#define ICCR2_BBSY BIT(7)
+#define ICCR2_MST  BIT(6)
+#define ICCR2_TRS  BIT(5)
+#define ICCR2_SP   BIT(3)
+#define ICCR2_RS   BIT(2)
+#define ICCR2_ST   BIT(1)
+
+/* ICMR1 */
+#define ICMR1_MTWP BIT(7)
+#define ICMR1_CKS_MASK GENMASK(6, 4)
+#define ICMR1_BCWP BIT(3)
+#define ICMR1_BC_MASK  GENMASK(2, 0)
+
+#define ICMR1_CKS(x)   (((x) << 4) & ICMR1_CKS_MASK)
+#define ICMR1_BC(x)((x) & ICMR1_BC_MASK)
+
+/* ICMR2 */
+#define ICMR2_DLCS BIT(7)
+#define ICMR2_SDDL_MASKGENMASK(6, 4)
+#define ICMR2_TMOH BIT(2)
+#define I

[PATCH 2/5] arm: dts: rzg2l: Sync with Linux v6.6

[Paul Barker]

Pull in the recent changes to the RZ/G2L device tree and related dtsi
files so that we're aligned with Linux v6.6 (commit ffc253263a13).

Signed-off-by: Paul Barker 
---
 arch/arm/dts/r9a07g044.dtsi   | 16 
 arch/arm/dts/r9a07g044l2-smarc.dts| 21 +
 arch/arm/dts/rz-smarc-common.dtsi |  4 ++--
 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20 
 arch/arm/dts/rzg2l-smarc-som.dtsi | 22 --
 arch/arm/dts/rzg2l-smarc.dtsi | 23 ---
 6 files changed, 91 insertions(+), 15 deletions(-)

diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
index 232910e07444..66f68fc2b241 100644
--- a/arch/arm/dts/r9a07g044.dtsi
+++ b/arch/arm/dts/r9a07g044.dtsi
@@ -223,20 +223,20 @@
 ,
 ;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
- "tgiv0", "tgie0", "tgif0",
- "tgia1", "tgib1", "tgiv1", "tgiu1",
- "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
  "tgia3", "tgib3", "tgic3", "tgid3",
- "tgiv3",
+ "tciv3",
  "tgia4", "tgib4", "tgic4", "tgid4",
- "tgiv4",
+ "tciv4",
  "tgiu5", "tgiv5", "tgiw5",
  "tgia6", "tgib6", "tgic6", "tgid6",
- "tgiv6",
+ "tciv6",
  "tgia7", "tgib7", "tgic7", "tgid7",
- "tgiv7",
+ "tciv7",
  "tgia8", "tgib8", "tgic8", "tgid8",
- "tgiv8", "tgiu8";
+ "tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
diff --git a/arch/arm/dts/r9a07g044l2-smarc.dts 
b/arch/arm/dts/r9a07g044l2-smarc.dts
index bc2af6c92ccd..568d49cfe44a 100644
--- a/arch/arm/dts/r9a07g044l2-smarc.dts
+++ b/arch/arm/dts/r9a07g044l2-smarc.dts
@@ -6,6 +6,27 @@
  */
 
 /dts-v1/;
+
+/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * Disable PMOD1_SER0 by setting "#define PMOD1_SER0   0" above and
+ * enable PMOD_MTU3 by setting "#define PMOD_MTU3  1" below.
+ */
+#define PMOD_MTU3  0
+
+#if (PMOD_MTU3 && PMOD1_SER0)
+#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
+#endif
+
+#define MTU3_COUNTER_Z_PHASE_SIGNAL0
+
+#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
+#endif
+
 #include "r9a07g044l2.dtsi"
 #include "rzg2l-smarc-som.dtsi"
 #include "rzg2l-smarc-pinfunction.dtsi"
diff --git a/arch/arm/dts/rz-smarc-common.dtsi 
b/arch/arm/dts/rz-smarc-common.dtsi
index 3962d47b3e59..a7594ba3a998 100644
--- a/arch/arm/dts/rz-smarc-common.dtsi
+++ b/arch/arm/dts/rz-smarc-common.dtsi
@@ -78,11 +78,11 @@
};
 };
 
-&audio_clk1{
+&audio_clk1 {
clock-frequency = <11289600>;
 };
 
-&audio_clk2{
+&audio_clk2 {
clock-frequency = <12288000>;
 };
 
diff --git a/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi 
b/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
index 9085d8c76ce1..18c526c7a4cf 100644
--- a/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
@@ -53,6 +53,26 @@
 ; /* SCL */
};
 
+   mtu3_pins: mtu3 {
+  

[PATCH 1/5] clk: renesas: Confirm all clock & reset changes on RZ/G2L

[Paul Barker]

When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.

Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().

This change is needed for reliable initialization of the I2C driver
which is added in a following patch.

Fixes: 1918ff5c95be ("clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver")
Signed-off-by: Paul Barker 
---
 drivers/clk/renesas/rzg2l-cpg.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index e54508c35ce2..dba009997a81 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -23,10 +23,18 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "rzg2l-cpg.h"
 
+/*
+ * Monitor registers for both clock and reset signals are offset by 0x180 from
+ * the corresponding control registers.
+ */
 #define CLK_MON_R(reg) (0x180 + (reg))
+#define RST_MON_R(reg) (0x180 + (reg))
+
+#define CPG_TIMEOUT_MSEC   100
 
 static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int 
id);
 static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char 
*name);
@@ -83,9 +91,9 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
value |= BIT(mod_clk->bit);
writel(value, data->base + mod_clk->off);
 
-   if (enable && readl_poll_timeout(data->base + CLK_MON_R(mod_clk->off),
-value, (value & BIT(mod_clk->bit)),
-10)) {
+   if (enable && wait_for_bit_32(data->base + CLK_MON_R(mod_clk->off),
+ BIT(mod_clk->bit), enable,
+ CPG_TIMEOUT_MSEC, false)) {
dev_err(clk->dev, "Timeout\n");
return -ETIMEDOUT;
}
@@ -420,7 +428,8 @@ static int rzg2l_cpg_rst_set(struct reset_ctl *reset_ctl, 
bool asserted)
value |= BIT(rst->bit);
writel(value, data->base + rst->off);
 
-   return 0;
+   return wait_for_bit_32(data->base + RST_MON_R(rst->off), BIT(rst->bit),
+  asserted, CPG_TIMEOUT_MSEC, false);
 }
 
 static int rzg2l_cpg_rst_assert(struct reset_ctl *reset_ctl)
-- 
2.39.2

[PATCH 0/5] Add i2c and reset support for Renesas RZ/G2L

[Paul Barker]

This patch series extends the support for the Renesas RZ/G2L SMARC EVK
board (based on the R9A07G044L2 SoC) to include the following new
features:

  * I2C bus support, including automatic deblocking if SDA is stuck low
due to another device on the board.

  * Basic PMIC support, with the ability to read, write & dump PMIC
registers.

  * Support for requesting system reset (SYSRESET_COLD or
SYSRESET_POWER) via the PMIC.

Along the way we fix the CPG driver to confirm all clock & reset changes
before returning, and update the device tree to align with Linux 6.6.

This series has been tested on RZ/G2L hardware, and the full u-boot
GitLab CI pipeline has been executed in our internal GitLab instance.

Paul Barker (5):
  clk: renesas: Confirm all clock & reset changes on RZ/G2L
  arm: dts: rzg2l: Sync with Linux v6.6
  i2c: rzg2l: Add I2C driver for RZ/G2L family
  pmic: Add Renesas RAA215300 PMIC driver
  sysreset: Support reset via Renesas RAA215300 PMIC

 arch/arm/dts/r9a07g044.dtsi   |  16 +-
 arch/arm/dts/r9a07g044l2-smarc.dts|  21 +
 arch/arm/dts/rz-smarc-common.dtsi |   4 +-
 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi |  20 +
 arch/arm/dts/rzg2l-smarc-som.dtsi |  22 +-
 arch/arm/dts/rzg2l-smarc.dtsi |  23 +-
 arch/arm/mach-rmobile/Kconfig |   1 +
 board/renesas/rzg2l/rzg2l.c   |   8 -
 configs/renesas_rzg2l_smarc_defconfig |   7 +
 drivers/clk/renesas/rzg2l-cpg.c   |  17 +-
 drivers/i2c/Kconfig   |   7 +
 drivers/i2c/Makefile  |   1 +
 drivers/i2c/rz_riic.c | 626 ++
 drivers/power/pmic/Kconfig|   9 +
 drivers/power/pmic/Makefile   |   1 +
 drivers/power/pmic/raa215300.c|  52 ++
 drivers/sysreset/Kconfig  |   6 +
 drivers/sysreset/Makefile |   1 +
 drivers/sysreset/sysreset_raa215300.c |  58 ++
 19 files changed, 873 insertions(+), 27 deletions(-)
 create mode 100644 drivers/i2c/rz_riic.c
 create mode 100644 drivers/power/pmic/raa215300.c
 create mode 100644 drivers/sysreset/sysreset_raa215300.c


base-commit: 92b27528d777ce85362af45e7d2974a6c856219b
-- 
2.39.2

[PATCH] sysreset: Fix unsupported request return values

[Paul Barker]

The description of the sysreset request method in  says that
the return value should be -EPROTONOSUPPORT if the requested reset type
is not supported by this device.

Signed-off-by: Paul Barker 
---
 drivers/sysreset/poweroff_gpio.c | 2 +-
 drivers/sysreset/sysreset_psci.c | 2 +-
 drivers/sysreset/sysreset_sandbox.c  | 4 ++--
 drivers/sysreset/sysreset_watchdog.c | 2 +-
 drivers/sysreset/sysreset_x86.c  | 2 +-
 test/dm/sysreset.c   | 6 +++---
 6 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/sysreset/poweroff_gpio.c b/drivers/sysreset/poweroff_gpio.c
index a5c24fd85bca..ad04e4b1a85e 100644
--- a/drivers/sysreset/poweroff_gpio.c
+++ b/drivers/sysreset/poweroff_gpio.c
@@ -33,7 +33,7 @@ static int poweroff_gpio_request(struct udevice *dev, enum 
sysreset_t type)
int r;
 
if (type != SYSRESET_POWER_OFF)
-   return -ENOSYS;
+   return -EPROTONOSUPPORT;
 
debug("GPIO poweroff\n");
 
diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c
index a8a41528a849..aa09d0b88271 100644
--- a/drivers/sysreset/sysreset_psci.c
+++ b/drivers/sysreset/sysreset_psci.c
@@ -25,7 +25,7 @@ static int psci_sysreset_request(struct udevice *dev, enum 
sysreset_t type)
psci_sys_poweroff();
break;
default:
-   return -ENOSYS;
+   return -EPROTONOSUPPORT;
}
 
return -EINPROGRESS;
diff --git a/drivers/sysreset/sysreset_sandbox.c 
b/drivers/sysreset/sysreset_sandbox.c
index f485a1352993..c12eda81d03e 100644
--- a/drivers/sysreset/sysreset_sandbox.c
+++ b/drivers/sysreset/sysreset_sandbox.c
@@ -21,7 +21,7 @@ static int sandbox_warm_sysreset_request(struct udevice *dev,
state->last_sysreset = type;
break;
default:
-   return -ENOSYS;
+   return -EPROTONOSUPPORT;
}
if (!state->sysreset_allowed[type])
return -EACCES;
@@ -70,7 +70,7 @@ static int sandbox_sysreset_request(struct udevice *dev, enum 
sysreset_t type)
return -EACCES;
sandbox_exit();
default:
-   return -ENOSYS;
+   return -EPROTONOSUPPORT;
}
if (!state->sysreset_allowed[type])
return -EACCES;
diff --git a/drivers/sysreset/sysreset_watchdog.c 
b/drivers/sysreset/sysreset_watchdog.c
index ceada2e47b54..6db5aa75b541 100644
--- a/drivers/sysreset/sysreset_watchdog.c
+++ b/drivers/sysreset/sysreset_watchdog.c
@@ -29,7 +29,7 @@ static int wdt_reboot_request(struct udevice *dev, enum 
sysreset_t type)
return ret;
break;
default:
-   return -ENOSYS;
+   return -EPROTONOSUPPORT;
}
 
return -EINPROGRESS;
diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index 4936fdb76c72..dc772b5ff9e3 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -87,7 +87,7 @@ static int x86_sysreset_request(struct udevice *dev, enum 
sysreset_t type)
return ret;
return -EINPROGRESS;
default:
-   return -ENOSYS;
+   return -EPROTONOSUPPORT;
}
 
outb(value, IO_PORT_RESET);
diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c
index 691683c56740..5aa69e046186 100644
--- a/test/dm/sysreset.c
+++ b/test/dm/sysreset.c
@@ -27,8 +27,8 @@ static int dm_test_sysreset_base(struct unit_test_state *uts)
/* Device 1 is the warm sysreset device */
ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev));
ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM));
-   ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD));
-   ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER));
+   ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_COLD));
+   ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_POWER));
 
state->sysreset_allowed[SYSRESET_WARM] = true;
ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM));
@@ -36,7 +36,7 @@ static int dm_test_sysreset_base(struct unit_test_state *uts)
 
/* Device 2 is the cold sysreset device */
ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev));
-   ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM));
+   ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_WARM));
state->sysreset_allowed[SYSRESET_COLD] = false;
ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD));
state->sysreset_allowed[SYSRESET_COLD] = true;

base-commit: e17d174773e9ba9447596708e702b7382e47a6cf
-- 
2.39.2