Re: [PATCH 13/27] ppc: Remove sbc8548 boards
[[PATCH 13/27] ppc: Remove sbc8548 boards] On 14/05/2021 (Fri 21:34) Tom Rini wrote: > These boards have not been converted to CONFIG_DM_PCI by the deadline and are > also missing conversion to CONFIG_DM. Remove them. > > Cc: Paul Gortmaker Ack - kernel removal was queued several months ago, but has yet to be merged to mainline or linux-next https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20210111082823.99562-2-paul.gortma...@windriver.com/ Thanks, Paul. -- > Signed-off-by: Tom Rini > --- > arch/powerpc/cpu/mpc85xx/Kconfig | 5 - > board/sbc8548/Kconfig | 9 - > board/sbc8548/MAINTAINERS | 10 - > board/sbc8548/Makefile| 12 - > board/sbc8548/README | 269 - > board/sbc8548/ddr.c | 132 --- > board/sbc8548/law.c | 54 --- > board/sbc8548/sbc8548.c | 315 --- > board/sbc8548/tlb.c | 121 -- > configs/sbc8548_PCI_33_PCIE_defconfig | 42 -- > configs/sbc8548_PCI_33_defconfig | 42 -- > configs/sbc8548_PCI_66_PCIE_defconfig | 42 -- > configs/sbc8548_PCI_66_defconfig | 42 -- > configs/sbc8548_defconfig | 41 -- > include/configs/sbc8548.h | 540 -- > 15 files changed, 1676 deletions(-) > delete mode 100644 board/sbc8548/Kconfig > delete mode 100644 board/sbc8548/MAINTAINERS > delete mode 100644 board/sbc8548/Makefile > delete mode 100644 board/sbc8548/README > delete mode 100644 board/sbc8548/ddr.c > delete mode 100644 board/sbc8548/law.c > delete mode 100644 board/sbc8548/sbc8548.c > delete mode 100644 board/sbc8548/tlb.c > delete mode 100644 configs/sbc8548_PCI_33_PCIE_defconfig > delete mode 100644 configs/sbc8548_PCI_33_defconfig > delete mode 100644 configs/sbc8548_PCI_66_PCIE_defconfig > delete mode 100644 configs/sbc8548_PCI_66_defconfig > delete mode 100644 configs/sbc8548_defconfig > delete mode 100644 include/configs/sbc8548.h > > diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig > b/arch/powerpc/cpu/mpc85xx/Kconfig > index 676aaf1d2ca6..22cfa4dc3499 100644 > --- a/arch/powerpc/cpu/mpc85xx/Kconfig > +++ b/arch/powerpc/cpu/mpc85xx/Kconfig > @@ -16,10 +16,6 @@ choice > prompt "Target select" > optional > > -config TARGET_SBC8548 > - bool "Support sbc8548" > - select ARCH_MPC8548 > - > config TARGET_SOCRATES > bool "Support socrates" > select ARCH_MPC8544 > @@ -1303,7 +1299,6 @@ source "board/freescale/t208xqds/Kconfig" > source "board/freescale/t208xrdb/Kconfig" > source "board/freescale/t4rdb/Kconfig" > source "board/keymile/Kconfig" > -source "board/sbc8548/Kconfig" > source "board/socrates/Kconfig" > source "board/xes/xpedite520x/Kconfig" > source "board/xes/xpedite537x/Kconfig" > diff --git a/board/sbc8548/Kconfig b/board/sbc8548/Kconfig > deleted file mode 100644 > index 626cbdf2ab27.. > --- a/board/sbc8548/Kconfig > +++ /dev/null > @@ -1,9 +0,0 @@ > -if TARGET_SBC8548 > - > -config SYS_BOARD > - default "sbc8548" > - > -config SYS_CONFIG_NAME > - default "sbc8548" > - > -endif > diff --git a/board/sbc8548/MAINTAINERS b/board/sbc8548/MAINTAINERS > deleted file mode 100644 > index ba1f2475eabf.. > --- a/board/sbc8548/MAINTAINERS > +++ /dev/null > @@ -1,10 +0,0 @@ > -SBC8548 BOARD > -M: Paul Gortmaker > -S: Maintained > -F: board/sbc8548/ > -F: include/configs/sbc8548.h > -F: configs/sbc8548_defconfig > -F: configs/sbc8548_PCI_33_defconfig > -F: configs/sbc8548_PCI_33_PCIE_defconfig > -F: configs/sbc8548_PCI_66_defconfig > -F: configs/sbc8548_PCI_66_PCIE_defconfig > diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile > deleted file mode 100644 > index 83d208cf1fe9.. > --- a/board/sbc8548/Makefile > +++ /dev/null > @@ -1,12 +0,0 @@ > -# SPDX-License-Identifier: GPL-2.0+ > -# > -# (C) Copyright 2004-2006 > -# Wolfgang Denk, DENX Software Engineering, w...@denx.de. > -# > -# (C) Copyright 2007 Wind River Systems Inc . > -# Added support for Wind River SBC8548 board > - > -obj-y+= sbc8548.o > -obj-y+= law.o > -obj-y+= tlb.o > -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o > diff --git a/board/sbc8548/README b/board/sbc8548/README > deleted file mode 100644 > index 0def245bd9ce.. > --- a/board/sbc8548/README > +++ /dev/null > @@ -1,269 +0,0 @@ > -Intro: > -== > - > -The SBC8548 is a stand alone single board com
Re: [PATCH 07/27] ppc: Remove sbc8349 board
[[PATCH 07/27] ppc: Remove sbc8349 board] On 14/05/2021 (Fri 21:34) Tom Rini wrote: > This board has not been converted to CONFIG_DM_MMC by the deadline. > Remove it. > > Cc: Paul Gortmaker Ack - this was removed in the linux-kernel already. Thanks, Paul. -- > Signed-off-by: Tom Rini > --- > arch/powerpc/cpu/mpc83xx/Kconfig | 5 - > board/sbc8349/Kconfig| 9 - > board/sbc8349/MAINTAINERS| 8 - > board/sbc8349/Makefile | 6 - > board/sbc8349/README | 127 > board/sbc8349/pci.c | 70 --- > board/sbc8349/sbc8349.c | 243 --- > configs/sbc8349_PCI_33_defconfig | 123 > configs/sbc8349_PCI_66_defconfig | 123 > configs/sbc8349_defconfig| 101 -- > include/configs/sbc8349.h| 322 --- > 11 files changed, 1137 deletions(-) > delete mode 100644 board/sbc8349/Kconfig > delete mode 100644 board/sbc8349/MAINTAINERS > delete mode 100644 board/sbc8349/Makefile > delete mode 100644 board/sbc8349/README > delete mode 100644 board/sbc8349/pci.c > delete mode 100644 board/sbc8349/sbc8349.c > delete mode 100644 configs/sbc8349_PCI_33_defconfig > delete mode 100644 configs/sbc8349_PCI_66_defconfig > delete mode 100644 configs/sbc8349_defconfig > delete mode 100644 include/configs/sbc8349.h > > diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig > b/arch/powerpc/cpu/mpc83xx/Kconfig > index ff85834c460c..e0bdfc4b9716 100644 > --- a/arch/powerpc/cpu/mpc83xx/Kconfig > +++ b/arch/powerpc/cpu/mpc83xx/Kconfig > @@ -12,10 +12,6 @@ config TARGET_MPC8308_P1M > bool "Support mpc8308_p1m" > select ARCH_MPC8308 > > -config TARGET_SBC8349 > - bool "Support sbc8349" > - select ARCH_MPC8349 > - > config TARGET_VE8313 > bool "Support ve8313" > select ARCH_MPC8313 > @@ -312,7 +308,6 @@ source "board/freescale/mpc837xerdb/Kconfig" > source "board/ids/ids8313/Kconfig" > source "board/keymile/Kconfig" > source "board/mpc8308_p1m/Kconfig" > -source "board/sbc8349/Kconfig" > source "board/tqc/tqm834x/Kconfig" > source "board/ve8313/Kconfig" > source "board/gdsys/mpc8308/Kconfig" > diff --git a/board/sbc8349/Kconfig b/board/sbc8349/Kconfig > deleted file mode 100644 > index 129d6b92ec57.. > --- a/board/sbc8349/Kconfig > +++ /dev/null > @@ -1,9 +0,0 @@ > -if TARGET_SBC8349 > - > -config SYS_BOARD > - default "sbc8349" > - > -config SYS_CONFIG_NAME > - default "sbc8349" > - > -endif > diff --git a/board/sbc8349/MAINTAINERS b/board/sbc8349/MAINTAINERS > deleted file mode 100644 > index af95c1dd0d23.. > --- a/board/sbc8349/MAINTAINERS > +++ /dev/null > @@ -1,8 +0,0 @@ > -SBC8349 BOARD > -M: Paul Gortmaker > -S: Maintained > -F: board/sbc8349/ > -F: include/configs/sbc8349.h > -F: configs/sbc8349_defconfig > -F: configs/sbc8349_PCI_33_defconfig > -F: configs/sbc8349_PCI_66_defconfig > diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile > deleted file mode 100644 > index c469174085d9.. > --- a/board/sbc8349/Makefile > +++ /dev/null > @@ -1,6 +0,0 @@ > -# SPDX-License-Identifier: GPL-2.0+ > -# > -# Copyright (c) 2006 Wind River Systems, Inc. > - > -obj-y += sbc8349.o > -obj-$(CONFIG_PCI) += pci.o > diff --git a/board/sbc8349/README b/board/sbc8349/README > deleted file mode 100644 > index 3c142e040762.. > --- a/board/sbc8349/README > +++ /dev/null > @@ -1,127 +0,0 @@ > - > - > - U-Boot for Wind River SBC834x Boards > - > - > - > -The Wind River SBC834x board is a 6U form factor (not CPCI) reference > -design that uses the MPC8347E or MPC8349E processor. U-Boot support > -for this board is heavily based on the existing U-Boot support for > -Freescale MPC8349 reference boards. > - > -Support has been primarily tested on the SBC8349 version of the board, > -although earlier versions were also tested on the SBC8347. The primary > -difference in the two is the level of PCI functionality. > - > - http://www.windriver.com/products/OCD/SBC8347E_49E/ > - > - > -Flash Details: > -== > - > -The flash type is intel 28F640Jx (4096x16) [one device]. Base address > -is 0xFF80_ which is also where the Hardware Reset Configuration > -Word (HRCW) is stored. Caution should be used to not reset the > -board without having a valid HRCW in place (i.e. erased flash) as > -then a Wind Rive
Re: [U-Boot] [PATCH] powerpc/85xx: Increase fdt address
[[PATCH] powerpc/85xx: Increase fdt address] On 19/07/2016 (Tue 17:52) Scott Wood wrote: > Loading the fdt at 0xc0 fails if the uncompressed kernel image is > greater than 12 MiB, which is quite common with modern kernels and > multiplatform defconfigs. Move fdtaddr to 0x1e0 which is just under > the ramdiskaddr on most targets. > > Signed-off-by: Scott Wood <o...@buserror.net> > Cc: Peter Tyser <pty...@xes-inc.com> > Cc: Dirk Eibach <eib...@gdsys.de> > Cc: Andy Fleming <aflem...@gmail.com> > Cc: Paul Gortmaker <paul.gortma...@windriver.com> > --- [...] diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h > index bbd1a63..74f219f 100644 > --- a/include/configs/sbc8548.h > +++ b/include/configs/sbc8548.h > @@ -596,7 +596,7 @@ > "consoledev=ttyS0\0" \ > "ramdiskaddr=200\0" \ > "ramdiskfile=uRamdisk\0" \ > -"fdtaddr=c0\0" \ > +"fdtaddr=1e0\0" \ Pretty sure it was common to have to bump the "c" to an "e" now and again, so "1e" sounds like a better long term solution. For sbc, Acked-by: Paul Gortmaker <paul.gortma...@windriver.com> Thanks, Paul. -- > "fdtfile=sbc8548.dtb\0" > > #define CONFIG_NFSBOOTCOMMAND > \ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 5/6] sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD
On 2015-10-19 08:07 PM, Tom Rini wrote: > On Sat, Oct 17, 2015 at 04:40:30PM -0400, Paul Gortmaker wrote: > > [nuked most of the commit message as it's now not true] Ah crap, I forgot to get rid of that; thanks for tossing it. P. -- > > Applied to u-boot/master, thanks! > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/6] sbc8641d: misc fixes and generic board enablement
[Re: [PATCH 0/6] sbc8641d: misc fixes and generic board enablement] On 17/10/2015 (Sat 17:50) Tom Rini wrote: > On Sat, Oct 17, 2015 at 04:40:25PM -0400, Paul Gortmaker wrote: > > > The sbc8641d is not really a state of the art board anymore, but it > > does have the distinctive feature of being one of the relatively few > > SMP powerpc boards around. Combined with its small form factor, it > > remains a useful testing platform. So here we enable the generic > > board support so that it can remain in tree. > > > > It turns out that in bringing the board forward, we've run into the > > size limit for the image, due to inevitable expansion, which led > > to some odd testing behaviour, depending on .config settings etc. > > Here we increase the image space from two 128k sectors to three, > > so we should be good for as long as the board remains relevant now. > > Thanks for finding this. I am going to grab this for the release and I > might re-word a commit or two. I have one ask tho, can you look at > using CONFIG_BOARD_SIZE_LIMIT, perhaps in a generic way so that we catch > more "oops, the board grew too big, run-time now will fail!" issues? Yeah, I'll have a look -- I was kind of surprised that it didn't scream at me when this happened during the build, since I'd think we have all the information at our fingertips to do a build bug on or similar, and I can't be the 1st one bitten by this. P. -- > > -- > Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/6] sbc8641d: misc fixes and generic board enablement
[Re: [PATCH 0/6] sbc8641d: misc fixes and generic board enablement] On 17/10/2015 (Sat 18:50) Paul Gortmaker wrote: > [Re: [PATCH 0/6] sbc8641d: misc fixes and generic board enablement] On > 17/10/2015 (Sat 17:50) Tom Rini wrote: > > > On Sat, Oct 17, 2015 at 04:40:25PM -0400, Paul Gortmaker wrote: > > > > > The sbc8641d is not really a state of the art board anymore, but it > > > does have the distinctive feature of being one of the relatively few > > > SMP powerpc boards around. Combined with its small form factor, it > > > remains a useful testing platform. So here we enable the generic > > > board support so that it can remain in tree. > > > > > > It turns out that in bringing the board forward, we've run into the > > > size limit for the image, due to inevitable expansion, which led > > > to some odd testing behaviour, depending on .config settings etc. > > > Here we increase the image space from two 128k sectors to three, > > > so we should be good for as long as the board remains relevant now. > > > > Thanks for finding this. I am going to grab this for the release and I > > might re-word a commit or two. I have one ask tho, can you look at > > using CONFIG_BOARD_SIZE_LIMIT, perhaps in a generic way so that we catch > > more "oops, the board grew too big, run-time now will fail!" issues? > > Yeah, I'll have a look -- I was kind of surprised that it didn't scream at > me when this happened during the build, since I'd think we have all the > information at our fingertips to do a build bug on or similar, and I > can't be the 1st one bitten by this. So, it seems we already have this in a "generic" way via BOARD_SIZE_LIMIT but hardly anyone sets that for their board. u-boot$git grep -l CONFIG_BOARD_SIZE_LIMIT include/ include/configs/bf548-ezkit.h include/configs/bf609-ezkit.h include/configs/bfin_adi_common.h include/configs/cm-bf537e.h include/configs/cm-bf537u.h include/configs/colibri_pxa270.h include/configs/colibri_vf.h include/configs/pcm052.h include/configs/tcm-bf537.h include/configs/vf610twr.h u-boot$ Can we just assign CONFIG_SYS_MONITOR_LEN to CONFIG_BOARD_SIZE_LIMIT if the latter isn't explicitly set? Or will that not be valid in some cases? Paul. -- > > P. > -- > > > > > -- > > Tom > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/6] sbc8641d: set proper environment sector size.
When debugging an env fail due to too small a malloc pool, it was noted that the env write was 256k. But the device sector size is 1/2 that, as can be seen from "fli" output: Bank # 1: CFI conformant flash (16 x 16) Size: 16 MB in 131 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1888 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 2 ms, buffer size: 64 bytes Sector Start Addresses: FF00 E RO FF02 E RO FF04 E RO FF06 E RO FF08 E RO FF0A E RO FF0C E RO FF0E E RO FF10 E RO FF12 E RO [...] FFF0 RO FFF2 RO FFF4 RO FFF6 RO FFF8 RO FFFA RO FFFC RO FFFE E RO FFFE8000 RO E RO 8000 RO => The desired env sector is FFF4->FFF6, or 0x2 in length, just after the 256k u-boot image which starts @ FFF0. Signed-off-by: Paul Gortmaker <paul.gortma...@windriver.com> --- include/configs/sbc8641d.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index d248eff42005..9fe90f00ff2a 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -473,7 +473,7 @@ */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE + 0x4) -#define CONFIG_ENV_SECT_SIZE 0x4 /* 256K(one sector) for env */ +#define CONFIG_ENV_SECT_SIZE 0x2 /* 128k(one sector) for env */ #define CONFIG_ENV_SIZE0x2000 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/6] sbc8641d: enable command line editing
It is just too painful to use interactively without it. Signed-off-by: Paul Gortmaker <paul.gortma...@windriver.com> --- include/configs/sbc8641d.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 00aab6b3d51d..b4466bc3b4c8 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -494,6 +494,7 @@ */ #define CONFIG_SYS_LONGHELP/* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x200 /* default load address */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 6/6] sbc8641d: increase monitor size from 256k to 384k
Between 2015.07-rc1 and 2015.07-rc2 this board started
silent boot failure. A bisect led to commit 6eed3786c68c8a49d
("net: Move the CMD_NET config to defconfigs"). This commit
looks harmless in itself, but it did implicitly add a feature
to the image which led to this:
u-boot$git describe 6eed3786c68c8a49d
v2015.07-rc1-412-g6eed3786c68c
^^^
u-boot$ls -l ../41*/u-boot.bin
-rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin
-rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin
u-boot$bc
bc 1.06.95
Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation,
Inc.
This is free software with ABSOLUTELY NO WARRANTY.
For details type `warranty'.
256*1024
262144
i.e. we finally broke through the 256k monitor size. Jump it
up to 384k and fix the hard coded value used in the env offset
at the same time.
We were probably flirting with the 256k size issue without
knowing it when testing on different baselines in earlier
commits, but since this is all board specific, a rebase or
reorder to put this commit 1st is of little value.
Signed-off-by: Paul Gortmaker <paul.gortma...@windriver.com>
---
board/sbc8641d/README | 6 +++---
include/configs/sbc8641d.h | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/board/sbc8641d/README b/board/sbc8641d/README
index af180888182d..d07f1ccf7c33 100644
--- a/board/sbc8641d/README
+++ b/board/sbc8641d/README
@@ -3,7 +3,7 @@ Wind River SBC8641D reference board
Created 06/14/2007 Joe Hamman
Copyright 2007, Embedded Specialties, Inc.
-Copyright 2007 Wind River Systemes, Inc.
+Copyright 2007 Wind River Systems, Inc.
-
1. Building U-Boot
@@ -43,7 +43,7 @@ c) while on, using static precautions, move JP10 back to the
failed image.
d) use "md fff0" to confirm you are looking at the failed image
e) turn off write protect with "prot off all"
f) get new image, i.e. "tftp 20 /somepath/u-boot.bin"
-g) erase failed image: "erase FFF0 FFF3"
-h) copy in new image: "cp.b 20 FFF0 4"
+g) erase failed image: "erase FFF0 FFF5"
+h) copy in new image: "cp.b 20 FFF0 6"
i) ensure new image is written: "md fff0"
k) power cycle the board and confirm new image works.
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 2f3ec2e20088..eed0f4975164 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -243,7 +243,7 @@
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for
Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024)/* Reserve 384 kB for
Mon */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc
*/
/* Serial Port */
@@ -474,7 +474,7 @@
* Environment
*/
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE + 0x4)
+#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE +
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x2 /* 128k(one sector) for env */
#define CONFIG_ENV_SIZE0x2000
--
2.1.0
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/6] sbc8641d: increase malloc pool size to a sane default
Currently the board fails to save its env, since the env size is much smaller than the sector size, and the malloc fails for the pad buffer, giving the user visible symptom of: Unable to save the rest of sector (253952) Allow for 1M malloc pool, the same as used on the sbc8548 board. Signed-off-by: Paul Gortmaker <paul.gortma...@windriver.com> --- include/configs/sbc8641d.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index b4466bc3b4c8..d248eff42005 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -242,7 +242,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024)/* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/6] sbc8641d: misc fixes and generic board enablement
The sbc8641d is not really a state of the art board anymore, but it does have the distinctive feature of being one of the relatively few SMP powerpc boards around. Combined with its small form factor, it remains a useful testing platform. So here we enable the generic board support so that it can remain in tree. It turns out that in bringing the board forward, we've run into the size limit for the image, due to inevitable expansion, which led to some odd testing behaviour, depending on .config settings etc. Here we increase the image space from two 128k sectors to three, so we should be good for as long as the board remains relevant now. --- [v2: add patch for extra sector for image ; retest on master] Paul Gortmaker (6): sbc8641d: enable command line editing sbc8641d: increase malloc pool size to a sane default sbc8641d: set proper environment sector size. sbc8641d: add basic flash setup instructions to README file sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD sbc8641d: increase monitor size from 256k to 384k board/sbc8641d/README | 23 ++- include/configs/sbc8641d.h | 11 +++ 2 files changed, 29 insertions(+), 5 deletions(-) -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/6] sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD
Tested on commit 3ea0953d36023d7e50fb00b2e258d8fb2828aeac
("dm: Move pre-reloc init earlier to cope with board_early_init_f()")
since the commit after that ("Set up stdio earlier when using driver
model") hangs this board at "Net:" init, just like it hangs the
sbc8548 board[1]. So, until that is resolved, this will be the
newest functional baseline for both boards.
Boot up looks as follows:
---
U-Boot 2014.10-rc2-00061-gb5e69635dc20 (Aug 24 2015 - 12:20:40)
CPU: 8641D, Version: 2.0, (0x80900120)
Core: e600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
CPU:1000 MHz, MPX:400 MHz
DDR:200 MHz (400 MT/s data rate), LBC:25 MHz
L1:D-cache 32 KiB enabled
I-cache 32 KiB enabled
L2:512 KiB enabled
I2C: ready
DRAM: 512 MiB
Flash: 16 MiB
SRIO1: disabled
PCIe1: Root Complex, no link, regs @ 0xf8008000
PCIe1: Bus 00 - 00
PCIe2: Root Complex, no link, regs @ 0xf8009000
PCIe2: Bus 01 - 01
In:serial
Out: serial
Err: serial
Net: eTSEC1, eTSEC2, eTSEC3, eTSEC4
Hit any key to stop autoboot: 0
=> ver
U-Boot 2014.10-rc2-00061-gb5e69635dc20 (Aug 24 2015 - 12:20:40)
powerpc-linux-gcc (GCC) 4.5.2
GNU ld (GNU Binutils) 2.21
=>
---
As can be seen, the "generic" banner warning message is now gone.
[1] sbc8548 hang: https://www.marc.info/?l=u-boot=142655649417364=3
Signed-off-by: Paul Gortmaker <paul.gortma...@windriver.com>
---
include/configs/sbc8641d.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 9fe90f00ff2a..2f3ec2e20088 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -20,6 +20,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/* High Level Configuration Options */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_SBC8641D1 /* SBC8641D board specific */
--
2.1.0
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[U-Boot] [PATCH v2 4/6] sbc8641d: add basic flash setup instructions to README file
...so that I don't have to go work them out from scratch again by peering at the manual. Signed-off-by: Paul Gortmaker <paul.gortma...@windriver.com> --- board/sbc8641d/README | 21 + 1 file changed, 21 insertions(+) diff --git a/board/sbc8641d/README b/board/sbc8641d/README index a051466a11b0..af180888182d 100644 --- a/board/sbc8641d/README +++ b/board/sbc8641d/README @@ -26,3 +26,24 @@ and settings may change with board revisions. PCI: The PCI command may hang if no boards are present in either slot. + +4. Reflashing U-Boot + +The board has two independent flash devices which can be used for dual +booting, or for u-boot backup and recovery. A two pin jumper on the +three pin JP10 determines which device is attached to /CS0 line. + +Assuming one device has a functional u-boot, and the other device has +a recently installed non-functional image, to perform a recovery from +that non-functional image goes essentially as follows: + +a) power down the board and jumper JP10 to select the functional image. +b) power on the board and let it get to u-boot prompt. +c) while on, using static precautions, move JP10 back to the failed image. +d) use "md fff0" to confirm you are looking at the failed image +e) turn off write protect with "prot off all" +f) get new image, i.e. "tftp 20 /somepath/u-boot.bin" +g) erase failed image: "erase FFF0 FFF3" +h) copy in new image: "cp.b 20 FFF0 4" +i) ensure new image is written: "md fff0" +k) power cycle the board and confirm new image works. -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD
On 2015-10-06 11:27 AM, Paul Gortmaker wrote: > On 2015-10-05 08:53 PM, Paul Gortmaker wrote: >> [Re: [U-Boot] [PATCH 5/5] sbc8641d: enable and test >> CONFIG_SYS_GENERIC_BOARD] On 04/10/2015 (Sun 01:45) Masahiro Yamada wrote: >> > > [...] > >> >>> >>> Any plan about this patch? >>> >>> I think this is the last non-generic board for PowerPC architecture. >>> >>> This board is still keeping us from removing arch/powerpc/lib/board.c >> >> Let me see if I can identify the exact line of change that breaks >> booting tomorrow, and maybe then Simon or someone can suggest next steps >> from there. > > So I broke down the suspect patch into three chunks, testing each > chunk as I went and it booted each time. A git diff of my split > by 3 vs a cherry pick of what I thought was the offending commit > shows nothing. > > So at this point, it seems the bisect returned the wrong result, > which is odd, since it seemed the same for sbc8548 and sbc8641. > Maybe a makefile bug let an object file get re-used that should > not have been? I'll do distclean in each bisect step in the > future. > > I'll have another chance to work on this Thurs AM, and I'm curious > to get to the bottom of this, so I'll follow up then with what I > find out. OK. So I finally got to the bottom of this and now it makes more sense. The monitor len was set to 256k and we were flirting with breaking that threshold based on .config settings and where we were in the tree ; my 2nd bisect led me to 2015.07-ish stuff and there I saw this when comparing the passing build with the fail: u-boot$git describe 6eed3786c68c8a49d v2015.07-rc1-412-g6eed3786c68c ^^^ u-boot$ls -l ../41*/u-boot.bin -rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin -rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin u-boot$bc bc 1.06.95 Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc. This is free software with ABSOLUTELY NO WARRANTY. For details type `warranty'. 256*1024 262144 The 412 commit added CONFIG_NET to the board and added 5k to the image which broke the 256k limit. Not sure why the earlier bisect that led to Simon's commit was breaking initially, but then not reproducible; I'm guessing that I wasn't re-running the defconfig step for each bisect step perhaps? I'll send a v2 of the series with 384k mon len shortly ; I have it booting on today's master commit now. Paul. -- U-Boot 2015.10-rc5-00024-gefbcba5eb4a0 (Oct 16 2015 - 17:34:32 -0400) CPU: 8641D, Version: 2.0, (0x80900120) Core: e600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1000 MHz, MPX:400 MHz DDR:200 MHz (400 MT/s data rate), LBC:25 MHz L1:D-cache 32 KiB enabled I-cache 32 KiB enabled L2:512 KiB enabled I2C: ready DRAM: 512 MiB Flash: 16 MiB SRIO1: disabled *** Warning - bad CRC, using default environment PCIe1: Root Complex, no link, regs @ 0xf8008000 PCIe1: Bus 00 - 00 PCIe2: Root Complex, no link, regs @ 0xf8009000 PCIe2: Bus 01 - 01 In:serial Out: serial Err: serial Net: eTSEC1 [PRIME] Error: eTSEC1 address not set. , eTSEC2 Error: eTSEC2 address not set. , eTSEC3 Error: eTSEC3 address not set. , eTSEC4 Error: eTSEC4 address not set. Hit any key to stop autoboot: 0 => ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD
On 2015-10-05 08:53 PM, Paul Gortmaker wrote: > [Re: [U-Boot] [PATCH 5/5] sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD] > On 04/10/2015 (Sun 01:45) Masahiro Yamada wrote: > [...] > >> >> Any plan about this patch? >> >> I think this is the last non-generic board for PowerPC architecture. >> >> This board is still keeping us from removing arch/powerpc/lib/board.c > > Let me see if I can identify the exact line of change that breaks > booting tomorrow, and maybe then Simon or someone can suggest next steps > from there. So I broke down the suspect patch into three chunks, testing each chunk as I went and it booted each time. A git diff of my split by 3 vs a cherry pick of what I thought was the offending commit shows nothing. So at this point, it seems the bisect returned the wrong result, which is odd, since it seemed the same for sbc8548 and sbc8641. Maybe a makefile bug let an object file get re-used that should not have been? I'll do distclean in each bisect step in the future. I'll have another chance to work on this Thurs AM, and I'm curious to get to the bottom of this, so I'll follow up then with what I find out. Paul. -- > > P. > -- > >> >> >> >> -- >> Best Regards >> Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD
[Re: [U-Boot] [PATCH 5/5] sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD]
On 04/10/2015 (Sun 01:45) Masahiro Yamada wrote:
> Hi.
>
>
> 2015-09-02 23:05 GMT+09:00 Simon Glass <s...@chromium.org>:
> > Hi Paul,
> >
> > On 2 September 2015 at 07:37, Paul Gortmaker
> > <paul.gortma...@windriver.com> wrote:
> >> On 2015-09-01 10:08 PM, York Sun wrote:
> >>>
> >>>
> >>> On 08/24/2015 12:26 PM, Paul Gortmaker wrote:
> >>>> Tested on commit 3ea0953d36023d7e50fb00b2e258d8fb2828aeac
> >>>> ("dm: Move pre-reloc init earlier to cope with board_early_init_f()")
> >>>> since the commit after that ("Set up stdio earlier when using driver
> >>>> model") hangs this board at "Net:" init, just like it hangs the
> >>>> sbc8548 board[1]. So, until that is resolved, this will be the
> >>>> newest functional baseline for both boards.
> >>>>
> >>> Paul,
> >>>
> >>> I can't test this patch. As the commit message said, it only works on an
> >>> ancient
> >>> point. Even this patch is merged, you can use the top of tree anyway. Is
> >>> there
> >>> any effort to find out why it is broken?
> >>
> >> Well, I was hoping to get more detailed suggestions from folks here,
> >> now that we know it is not board specific and probably breaks a lot
> >> of the older freescale boards - both the sbc8548 and sbc8641d were
> >> close derivatives of their MPC8548CDS and HPCNET/8641D cousins, but
> >> just targeting a smaller form factor. I'm betting they are dead too.
> >>
> >> Maybe now that we know that, Simon [added to CC] can offer some more
> >> detailed suggestions on what is going on, since I bisected it back
> >> to his commit relating to uart init.
> >>
> >> http://marc.info/?l=u-boot=142715170512534
> >>
> >> I can test incremental changes on top of that last working baseline
> >> easily enough, since the board has redundant flash (which let me
> >> get that far). But currently I've no clue where to start, since
> >> the uart init breaking net init, or leaving a booby-trap such that
> >> touching the net device hangs - doesn't really point to an obvious
> >> starting point to test. :(
> >
> > I don't have any good ideas, you could try these (with reference to my
> > commit 294b91a5):
> >
> > 1. Move the initr_barrier()...initr_dm() code sequence back to its
> > original place below initr_w83c553f(), and see if that fixes it. Then
> > progressively move it earlier until you see a breakage.
> >
> > 2. Add another initr_barrier() in the original place
> >
> > 3. Comment out initr_dm()
> >
> > Since you are presumably not using driver model for serial yet you
> > should be able to fiddling things around quite a bit without breaking
> > anything. Once you narrow it down a fix may be obvious, or may need a
> > bit of thought.
> >
>
>
> Any plan about this patch?
>
> I think this is the last non-generic board for PowerPC architecture.
>
> This board is still keeping us from removing arch/powerpc/lib/board.c
Let me see if I can identify the exact line of change that breaks
booting tomorrow, and maybe then Simon or someone can suggest next steps
from there.
P.
--
>
>
>
> --
> Best Regards
> Masahiro Yamada
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Re: [U-Boot] [PATCH 5/5] sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD
On 2015-09-01 10:08 PM, York Sun wrote:
>
>
> On 08/24/2015 12:26 PM, Paul Gortmaker wrote:
>> Tested on commit 3ea0953d36023d7e50fb00b2e258d8fb2828aeac
>> ("dm: Move pre-reloc init earlier to cope with board_early_init_f()")
>> since the commit after that ("Set up stdio earlier when using driver
>> model") hangs this board at "Net:" init, just like it hangs the
>> sbc8548 board[1]. So, until that is resolved, this will be the
>> newest functional baseline for both boards.
>>
> Paul,
>
> I can't test this patch. As the commit message said, it only works on an
> ancient
> point. Even this patch is merged, you can use the top of tree anyway. Is there
> any effort to find out why it is broken?
Well, I was hoping to get more detailed suggestions from folks here,
now that we know it is not board specific and probably breaks a lot
of the older freescale boards - both the sbc8548 and sbc8641d were
close derivatives of their MPC8548CDS and HPCNET/8641D cousins, but
just targeting a smaller form factor. I'm betting they are dead too.
Maybe now that we know that, Simon [added to CC] can offer some more
detailed suggestions on what is going on, since I bisected it back
to his commit relating to uart init.
http://marc.info/?l=u-boot=142715170512534
I can test incremental changes on top of that last working baseline
easily enough, since the board has redundant flash (which let me
get that far). But currently I've no clue where to start, since
the uart init breaking net init, or leaving a booby-trap such that
touching the net device hangs - doesn't really point to an obvious
starting point to test. :(
Paul.
--
>
> York
>
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Re: [U-Boot] [PATCH 19/19] powerpc: mpc86xx: remove sbc8641d support
On 2015-09-01 09:28 AM, Masahiro Yamada wrote: > This has not been converted to Generic Board, so should be removed. > (See doc/README.generic-board for details.) > > Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com> > Cc: Paul Gortmaker <paul.gortma...@windriver.com> NACK. I've sent the conversion patches a week ago or so. https://www.mail-archive.com/u-boot@lists.denx.de/msg183343.html Paul. -- > --- > > arch/powerpc/cpu/mpc86xx/Kconfig | 4 - > board/sbc8641d/Kconfig | 9 - > board/sbc8641d/MAINTAINERS | 6 - > board/sbc8641d/Makefile | 10 - > board/sbc8641d/README| 28 -- > board/sbc8641d/ddr.c | 56 > board/sbc8641d/law.c | 40 --- > board/sbc8641d/sbc8641d.c| 261 - > configs/sbc8641d_defconfig | 4 - > doc/README.scrapyard | 1 + > include/configs/sbc8641d.h | 590 > --- > 11 files changed, 1 insertion(+), 1008 deletions(-) > delete mode 100644 board/sbc8641d/Kconfig > delete mode 100644 board/sbc8641d/MAINTAINERS > delete mode 100644 board/sbc8641d/Makefile > delete mode 100644 board/sbc8641d/README > delete mode 100644 board/sbc8641d/ddr.c > delete mode 100644 board/sbc8641d/law.c > delete mode 100644 board/sbc8641d/sbc8641d.c > delete mode 100644 configs/sbc8641d_defconfig > delete mode 100644 include/configs/sbc8641d.h > > diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig > b/arch/powerpc/cpu/mpc86xx/Kconfig > index 46d15e2..0dcee70 100644 > --- a/arch/powerpc/cpu/mpc86xx/Kconfig > +++ b/arch/powerpc/cpu/mpc86xx/Kconfig > @@ -8,9 +8,6 @@ choice > prompt "Target select" > optional > > -config TARGET_SBC8641D > - bool "Support sbc8641d" > - > config TARGET_MPC8641HPCN > bool "Support MPC8641HPCN" > > @@ -20,7 +17,6 @@ config TARGET_XPEDITE517X > endchoice > > source "board/freescale/mpc8641hpcn/Kconfig" > -source "board/sbc8641d/Kconfig" > source "board/xes/xpedite517x/Kconfig" > > endmenu > diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig > deleted file mode 100644 > index 8dfc90c..000 > diff --git a/board/sbc8641d/MAINTAINERS b/board/sbc8641d/MAINTAINERS > deleted file mode 100644 > index a50b541..000 > diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile > deleted file mode 100644 > index a9b2026..000 > diff --git a/board/sbc8641d/README b/board/sbc8641d/README > deleted file mode 100644 > index a051466..000 > diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c > deleted file mode 100644 > index b31ea34..000 > diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c > deleted file mode 100644 > index c4e736b..000 > diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c > deleted file mode 100644 > index 6bdf1a2..000 > diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig > deleted file mode 100644 > index b67c7c0..000 > diff --git a/doc/README.scrapyard b/doc/README.scrapyard > index 2a3ba4c..81fbc97 100644 > --- a/doc/README.scrapyard > +++ b/doc/README.scrapyard > @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. > > BoardArchCPUCommit Removed Last > known maintainer/contact > > = > +sbc8641d powerpc mpc86xx- - Paul > Gortmaker <paul.gortma...@windriver.com> > MPC8610HPCD powerpc mpc86xx- - > MPC8569MDS powerpc mpc85xx- - > MPC8568MDS powerpc mpc85xx- - > diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h > deleted file mode 100644 > index 00aab6b..000 > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] sbc8641d: set proper environment sector size.
When debugging an env fail due to too small a malloc pool, it was noted that the env write was 256k. But the device sector size is 1/2 that, as can be seen from fli output: Bank # 1: CFI conformant flash (16 x 16) Size: 16 MB in 131 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1888 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 2 ms, buffer size: 64 bytes Sector Start Addresses: FF00 E RO FF02 E RO FF04 E RO FF06 E RO FF08 E RO FF0A E RO FF0C E RO FF0E E RO FF10 E RO FF12 E RO [...] FFF0 RO FFF2 RO FFF4 RO FFF6 RO FFF8 RO FFFA RO FFFC RO FFFE E RO FFFE8000 RO E RO 8000 RO = The desired env sector is FFF4-FFF6, or 0x2 in length, just after the 256k u-boot image which starts @ FFF0. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- include/configs/sbc8641d.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 77a7e5a799b8..20e7152b0952 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -473,7 +473,7 @@ */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE + 0x4) -#define CONFIG_ENV_SECT_SIZE 0x4 /* 256K(one sector) for env */ +#define CONFIG_ENV_SECT_SIZE 0x2 /* 128k(one sector) for env */ #define CONFIG_ENV_SIZE0x2000 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] sbc8641d: enable command line editing
It is just too painful to use interactively without it. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- include/configs/sbc8641d.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 8eb7276618b0..354b673845cf 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -495,6 +495,7 @@ */ #define CONFIG_SYS_LONGHELP/* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x200 /* default load address */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD
Tested on commit 3ea0953d36023d7e50fb00b2e258d8fb2828aeac (dm: Move pre-reloc init earlier to cope with board_early_init_f()) since the commit after that (Set up stdio earlier when using driver model) hangs this board at Net: init, just like it hangs the sbc8548 board[1]. So, until that is resolved, this will be the newest functional baseline for both boards. Boot up looks as follows: --- U-Boot 2014.10-rc2-00061-gb5e69635dc20 (Aug 24 2015 - 12:20:40) CPU: 8641D, Version: 2.0, (0x80900120) Core: e600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1000 MHz, MPX:400 MHz DDR:200 MHz (400 MT/s data rate), LBC:25 MHz L1:D-cache 32 KiB enabled I-cache 32 KiB enabled L2:512 KiB enabled I2C: ready DRAM: 512 MiB Flash: 16 MiB SRIO1: disabled PCIe1: Root Complex, no link, regs @ 0xf8008000 PCIe1: Bus 00 - 00 PCIe2: Root Complex, no link, regs @ 0xf8009000 PCIe2: Bus 01 - 01 In:serial Out: serial Err: serial Net: eTSEC1, eTSEC2, eTSEC3, eTSEC4 Hit any key to stop autoboot: 0 = ver U-Boot 2014.10-rc2-00061-gb5e69635dc20 (Aug 24 2015 - 12:20:40) powerpc-linux-gcc (GCC) 4.5.2 GNU ld (GNU Binutils) 2.21 = --- As can be seen, the generic banner warning message is now gone. [1] sbc8548 hang: https://www.marc.info/?l=u-bootm=142655649417364w=3 Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- include/configs/sbc8641d.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 20e7152b0952..32468453f524 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -20,6 +20,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD + /* High Level Configuration Options */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_SBC8641D1 /* SBC8641D board specific */ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/5] sbc8641d: increase malloc pool size to a sane default
Currently the board fails to save its env, since the env size is much smaller than the sector size, and the malloc fails for the pad buffer, giving the user visible symptom of: Unable to save the rest of sector (253952) Allow for 1M malloc pool, the same as used on the sbc8548 board. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- include/configs/sbc8641d.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 354b673845cf..77a7e5a799b8 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -242,7 +242,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024)/* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/5] sbc8641d: misc fixes and generic board enablement
The sbc8641d is not really a state of the art board anymore, but it does have the distinctive feature of being one of the relatively few SMP powerpc boards around. Combined with its small form factor, it remains a useful testing platform. So here we enable the generic board support so that it can remain in tree. One note worthy of mention is that the same commit that breaks[1] the sbc8548 board [commit 294b91a58171 (Set up stdio earlier when using driver model)] also breaks this board in the identical way (hangs at Net: line during bootup). So the baseline for run time testing was one commit prior to that commit that introduced the regressions. The fixes are all board specific and a branch off 294b91a58171~ will merge seamlessly to master, or they can be applied to master; whenever the regressions of 294b91a58171 are resolved then things will work again on the tip of tree. [1] https://www.marc.info/?l=u-bootm=142655649417364w=3 Paul Gortmaker (5): sbc8641d: enable command line editing sbc8641d: increase malloc pool size to a sane default sbc8641d: set proper environment sector size. sbc8641d: add basic flash setup instructions to README file sbc8641d: enable and test CONFIG_SYS_GENERIC_BOARD board/sbc8641d/README | 21 + include/configs/sbc8641d.h | 7 +-- 2 files changed, 26 insertions(+), 2 deletions(-) -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/5] sbc8641d: add basic flash setup instructions to README file
...so that I don't have to go work them out from scratch again by peering at the manual. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- board/sbc8641d/README | 21 + 1 file changed, 21 insertions(+) diff --git a/board/sbc8641d/README b/board/sbc8641d/README index a051466a11b0..af180888182d 100644 --- a/board/sbc8641d/README +++ b/board/sbc8641d/README @@ -26,3 +26,24 @@ and settings may change with board revisions. PCI: The PCI command may hang if no boards are present in either slot. + +4. Reflashing U-Boot + +The board has two independent flash devices which can be used for dual +booting, or for u-boot backup and recovery. A two pin jumper on the +three pin JP10 determines which device is attached to /CS0 line. + +Assuming one device has a functional u-boot, and the other device has +a recently installed non-functional image, to perform a recovery from +that non-functional image goes essentially as follows: + +a) power down the board and jumper JP10 to select the functional image. +b) power on the board and let it get to u-boot prompt. +c) while on, using static precautions, move JP10 back to the failed image. +d) use md fff0 to confirm you are looking at the failed image +e) turn off write protect with prot off all +f) get new image, i.e. tftp 20 /somepath/u-boot.bin +g) erase failed image: erase FFF0 FFF3 +h) copy in new image: cp.b 20 FFF0 4 +i) ensure new image is written: md fff0 +k) power cycle the board and confirm new image works. -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 28/28] powerpc: remove sbc8641d support
[Re: [RFC PATCH 28/28] powerpc: remove sbc8641d support] On 13/08/2015 (Thu 23:17) Anatolij Gustschin wrote: CCing Paul. On Thu, 13 Aug 2015 19:15:46 +0900 Masahiro Yamada yamada.masah...@socionext.com wrote: This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Thanks for the CC: -- let me have a look next week as to how complex the conversion is, since it is one of the few PowerPC platforms that is actually SMP, it makes a useful test platform. When I converted the sbc8548, I recall testing the 8641d but there was breakage in the DDR init caused by other (unknown) changes that prevented me from doing the conversion then and there. Mabye I'll get lucky and that issue will be resolved now. So please hold on this for a short while longer. Paul. -- Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com --- arch/powerpc/cpu/mpc86xx/Kconfig | 4 - board/sbc8641d/Kconfig | 9 - board/sbc8641d/MAINTAINERS | 6 - board/sbc8641d/Makefile | 10 - board/sbc8641d/README| 28 -- board/sbc8641d/ddr.c | 56 board/sbc8641d/law.c | 40 --- board/sbc8641d/sbc8641d.c| 261 - configs/sbc8641d_defconfig | 4 - include/configs/sbc8641d.h | 590 --- 10 files changed, 1008 deletions(-) delete mode 100644 board/sbc8641d/Kconfig delete mode 100644 board/sbc8641d/MAINTAINERS delete mode 100644 board/sbc8641d/Makefile delete mode 100644 board/sbc8641d/README delete mode 100644 board/sbc8641d/ddr.c delete mode 100644 board/sbc8641d/law.c delete mode 100644 board/sbc8641d/sbc8641d.c delete mode 100644 configs/sbc8641d_defconfig delete mode 100644 include/configs/sbc8641d.h diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index 46d15e2..0dcee70 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -8,9 +8,6 @@ choice prompt Target select optional -config TARGET_SBC8641D - bool Support sbc8641d - config TARGET_MPC8641HPCN bool Support MPC8641HPCN @@ -20,7 +17,6 @@ config TARGET_XPEDITE517X endchoice source board/freescale/mpc8641hpcn/Kconfig -source board/sbc8641d/Kconfig source board/xes/xpedite517x/Kconfig endmenu diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig deleted file mode 100644 index 8dfc90c..000 --- a/board/sbc8641d/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_SBC8641D - -config SYS_BOARD - default sbc8641d - -config SYS_CONFIG_NAME - default sbc8641d - -endif diff --git a/board/sbc8641d/MAINTAINERS b/board/sbc8641d/MAINTAINERS deleted file mode 100644 index a50b541..000 --- a/board/sbc8641d/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SBC8641D BOARD -M: Paul Gortmaker paul.gortma...@windriver.com -S: Maintained -F: board/sbc8641d/ -F: include/configs/sbc8641d.h -F: configs/sbc8641d_defconfig diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile deleted file mode 100644 index a9b2026..000 --- a/board/sbc8641d/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, w...@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += sbc8641d.o -obj-y += law.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/sbc8641d/README b/board/sbc8641d/README deleted file mode 100644 index a051466..000 --- a/board/sbc8641d/README +++ /dev/null @@ -1,28 +0,0 @@ -Wind River SBC8641D reference board -=== - -Created 06/14/2007 Joe Hamman -Copyright 2007, Embedded Specialties, Inc. -Copyright 2007 Wind River Systemes, Inc. -- - -1. Building U-Boot --- -The SBC8641D code is known to build using ELDK 4.1. - -$ make sbc8641d_config -Configuring for sbc8641d board... - -$ make - - -2. Switch and Jumper Settings -- -All Jumpers Switches are in their default positions. Please refer to -the board documentation for details. Some settings control CPU voltages -and settings may change with board revisions. - -3. Known limitations - -PCI: - The PCI command may hang if no boards are present in either slot. diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c deleted file mode 100644 index b31ea34..000 --- a/board/sbc8641d/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software
Re: [U-Boot] Set up stdio earlier when using driver model --- breaks sbc8548 booting.
[Re: Set up stdio earlier when using driver model --- breaks sbc8548 booting.] On 23/03/2015 (Mon 17:01) Simon Glass wrote: Hi Paul, On 16 March 2015 at 19:41, Paul Gortmaker paul.gortma...@windriver.com wrote: Testing latest master on sbc8548 (ppc e500v2 single core) and it hangs at the Net: line; a working boot shows the full Net: line as: - PCI: Host, 64 bit, 66 MHz, sync, arbiter 00:01.0 - 8086:1026 - Network controller PCI1: Bus 00 - 00 PCIe1: disabled In:serial Out: serial Err: serial Net: eTSEC0 [PRIME], eTSEC1 Hit any key to stop autoboot: 0 - So we never see the eTSEC0 or any other output after Net: . My 1st bisect led to my own commit: - commit 2bf4207b8a452476a591d733c6b8f09b337acc08 Author: Paul Gortmaker paul.gortma...@windriver.com AuthorDate: Thu Aug 14 10:42:52 2014 -0400 Commit: York Sun york...@freescale.com CommitDate: Fri Nov 14 11:12:13 2014 -0800 sbc8548: enable and test CONFIG_SYS_GENERIC_BOARD - ...but that is a red herring, since I'd tested it on master at Aug14, but it wasn't committed to master until three months later. So the breakage is in that 3 month window. Since I recorded the original baseline I'd tested on, I restarted the bisect with that baseline as good and the above 2bf42 as bad, and just added the oneline change for CONFIG_SYS_GENERIC_BOARD manually at each bisect point. Doing that led me unequivocally to: - commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 Author: Simon Glass s...@chromium.org Date: Wed Sep 3 17:37:00 2014 -0600 Set up stdio earlier when using driver model - Based on a part of that commit log, it says Should there be any problems with this approach they can be dealt with as boards are converted over to use driver model for serial. So maybe the sbc8548 is just missing some additional conversion? Oddly it seems it is dying at network device probing and not in/out/err that use serial as stdio. Any hints on what to look at next to solve this would be appreciated. I had a look at this link: http://www.denx.de/wiki/U-Boot/DriverModel ..but wasn't sure where to go from there, since I'm still unsure what the real root of the breakage is. Yes it is certainly odd. The driver init for serial is over by then, so I don't see why it would hang. Also the code has changed further since that commit. So there is no board wide conversion to some new API needed from this change, i.e. things should have stayed working as is? My suggestion would be to dig into the network init and see if you figure out where it hangs. Do you have an ICE? Ugh. I could probably find an ICE and the associated software, but I've never really liked using the things, which is why I bisected my way here to identify the commit that caused the regression, hoping that once it was identified, that the author of the changeset would know what happened... :-( P. -- Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Set up stdio earlier when using driver model --- breaks sbc8548 booting.
Testing latest master on sbc8548 (ppc e500v2 single core) and it hangs at the Net: line; a working boot shows the full Net: line as: - PCI: Host, 64 bit, 66 MHz, sync, arbiter 00:01.0 - 8086:1026 - Network controller PCI1: Bus 00 - 00 PCIe1: disabled In:serial Out: serial Err: serial Net: eTSEC0 [PRIME], eTSEC1 Hit any key to stop autoboot: 0 - So we never see the eTSEC0 or any other output after Net: . My 1st bisect led to my own commit: - commit 2bf4207b8a452476a591d733c6b8f09b337acc08 Author: Paul Gortmaker paul.gortma...@windriver.com AuthorDate: Thu Aug 14 10:42:52 2014 -0400 Commit: York Sun york...@freescale.com CommitDate: Fri Nov 14 11:12:13 2014 -0800 sbc8548: enable and test CONFIG_SYS_GENERIC_BOARD - ...but that is a red herring, since I'd tested it on master at Aug14, but it wasn't committed to master until three months later. So the breakage is in that 3 month window. Since I recorded the original baseline I'd tested on, I restarted the bisect with that baseline as good and the above 2bf42 as bad, and just added the oneline change for CONFIG_SYS_GENERIC_BOARD manually at each bisect point. Doing that led me unequivocally to: - commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 Author: Simon Glass s...@chromium.org Date: Wed Sep 3 17:37:00 2014 -0600 Set up stdio earlier when using driver model - Based on a part of that commit log, it says Should there be any problems with this approach they can be dealt with as boards are converted over to use driver model for serial. So maybe the sbc8548 is just missing some additional conversion? Oddly it seems it is dying at network device probing and not in/out/err that use serial as stdio. Any hints on what to look at next to solve this would be appreciated. I had a look at this link: http://www.denx.de/wiki/U-Boot/DriverModel ..but wasn't sure where to go from there, since I'm still unsure what the real root of the breakage is. Thanks, Paul. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] sbc8548: document how to write main flash from alternate flash
On 15-03-16 04:01 PM, York Sun wrote: On 03/16/2015 12:53 PM, Paul Gortmaker wrote: If you are running on the alternate flash in order to fix a corrupted main flash image, it might be good to have the steps for that documented as well. Also delete any protect commands from non-active flash banks; they are only required for the instances where you are writing to the currently in use flash image. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- [v2: drop protect commands from instances where we flash the non active flash bank ; it wasn't protected anyway.] board/sbc8548/README | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/board/sbc8548/README b/board/sbc8548/README index feac5e3e63e5..92731645f266 100644 --- a/board/sbc8548/README +++ b/board/sbc8548/README @@ -132,11 +132,19 @@ image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, tftp u-boot.bin md 20 10 -protect off all era eff0 efff cp.b 20 eff0 10 md eff0 10 -protect on all + +If you are running the alternate 64MB /CS0 settings and want to update +the normal default 8MB u-boot image, then (built with CONFIG_SYS_ALT_BOOT +disabled) the steps will become: + +tftp u-boot.bin +md 20 10 +erase effa efff +cp.b 20 effa 6 +md effa 10 Finally, if you are running the alternate 64MB /CS0 settings and want to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT Paul, Sorry I didn't catch this in previous version. In your instruction, you presume the tftp location is 0x20, which may not be the case. I suggest you add specific location in tftp command so it is clear. Sure, I can do that. I also noticed the file size seems different in your README, comparing with the section above. It may be worth to double check. I think the reason for that was that the alternate flash has a large sector size, and we can't get the exact number of 0x6 alignment on 0x8 sized sectors. From fli output: FF98 E FFA0 E FFA8 E FFB0 E FFB8 E FFC0 E FFC8 E FFD0 E FFD8 E FFE0 E FFE8 E FFF0 RO FFF8 RO I guess it could be 0x8 for write instead of 0x10, but for some reason I recall it being useful to invalidate the environment sector at the same time on the alt bank ; I can't recall why anymore... The eTSEC aren't detected when I build v2015.04-rc3 ; if I solve that then I'll try a 8 write for alt flash and see if it comes up OK. (if you have a hint about the eTSEC, let me know ; will save me a bisect) P. -- York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sbc8548: document how to write main flash from alternate flash
If you are running on the alternate flash in order to fix a corrupted main flash image, it might be good to have the steps for that documented as well. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- board/sbc8548/README | 12 1 file changed, 12 insertions(+) diff --git a/board/sbc8548/README b/board/sbc8548/README index feac5e3e63e5..493ea837ba3b 100644 --- a/board/sbc8548/README +++ b/board/sbc8548/README @@ -138,6 +138,18 @@ image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, md eff0 10 protect on all +If you are running the alternate 64MB /CS0 settings and want to update +the normal default 8MB u-boot image, then (built with CONFIG_SYS_ALT_BOOT +disabled) the steps will become: + + tftp u-boot.bin + md 20 10 + protect off all + erase effa efff + cp.b 20 effa 6 + md effa 10 + protect on all + Finally, if you are running the alternate 64MB /CS0 settings and want to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT enabled) the steps will become: -- 2.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] sbc8548: document how to write main flash from alternate flash
If you are running on the alternate flash in order to fix a corrupted main flash image, it might be good to have the steps for that documented as well. Also delete any protect commands from non-active flash banks; they are only required for the instances where you are writing to the currently in use flash image. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- [v2: drop protect commands from instances where we flash the non active flash bank ; it wasn't protected anyway.] board/sbc8548/README | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/board/sbc8548/README b/board/sbc8548/README index feac5e3e63e5..92731645f266 100644 --- a/board/sbc8548/README +++ b/board/sbc8548/README @@ -132,11 +132,19 @@ image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, tftp u-boot.bin md 20 10 - protect off all era eff0 efff cp.b 20 eff0 10 md eff0 10 - protect on all + +If you are running the alternate 64MB /CS0 settings and want to update +the normal default 8MB u-boot image, then (built with CONFIG_SYS_ALT_BOOT +disabled) the steps will become: + + tftp u-boot.bin + md 20 10 + erase effa efff + cp.b 20 effa 6 + md effa 10 Finally, if you are running the alternate 64MB /CS0 settings and want to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT -- 2.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sbc8548: enable and test CONFIG_SYS_GENERIC_BOARD
Tested on the following baseline (note dirty since I enabled ALT_BOOT in the config in order to use the alternate boot bank.) Everything seems to work fine with no additional changes. The banner warning message is now gone. --- U-Boot 2014.10-rc1-00075-ge49f14af1349-dirty (Aug 14 2014 - 10:26:15) CPU: 8548E, Version: 2.1, (0x80390021) Core: e500, Version: 2.2, (0x80210022) Clock Configuration: CPU0:990 MHz, CCB:396 MHz, DDR:198 MHz (396 MT/s data rate), LBC:99 MHz L1:D-cache 32 KiB enabled I-cache 32 KiB enabled I2C: ready DRAM: Detected UDIMM SDRAM: 128 MiB 256 MiB (DDR2, 64-bit, CL=3, ECC off) Flash: 72 MiB L2:512 KiB enabled *** Warning - bad CRC, using default environment PCI: Host, 64 bit, 66 MHz, sync, arbiter 00:01.0 - 8086:1026 - Network controller PCI1: Bus 00 - 00 PCIe1: Root Complex, x1 gen1, regs @ 0xe000a000 02:00.0 - 1148:9e00 - Network controller PCIe1: Bus 01 - 02 In:serial Out: serial Err: serial Net: eTSEC0 [PRIME], eTSEC1 Hit any key to stop autoboot: 0 = ver U-Boot 2014.10-rc1-00075-ge49f14af1349-dirty (Aug 14 2014 - 10:26:15) powerpc-linux-gcc (GCC) 4.5.2 GNU ld (GNU Binutils) 2.21 = --- Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- include/configs/sbc8548.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index f28f350fcc86..aee0d9e27309 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -13,6 +13,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Top level Makefile configuration choices */ -- 1.9.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/1] Delete sbc8650 / sbc8540 support.
This old board has already been deleted from the linux kernel. Sending this 0/1 so that I can include a pull request. The following patch has been formatted with --irreversible-delete so that it does not contain all the meaningless deleted lines in the mailout to the list. However git-am does not (yet) know how to apply such a patch[1]. So I also have a pull req. below. Thanks, Paul. [1] http://marc.info/?l=gitm=134394003916648w=2 -- The following changes since commit ee1f4caaa2a3f79d692155eec8a4c7289d60e106: Prepare v2012.10-rc1 (2012-09-21 17:18:28 -0700) are available in the git repository at: git://openlinux.windriver.com/people/paulg/u-boot.git delete-sbc8560 for you to fetch changes up to 48d1357355588946a1b2bda337dc0fd7b3b48256: powerpc: delete Wind River SBC8560/8540 support (2012-09-24 13:30:53 -0400) Paul Gortmaker (1): powerpc: delete Wind River SBC8560/8540 support MAINTAINERS | 2 - board/sbc8560/Makefile| 50 - board/sbc8560/README | 57 -- board/sbc8560/ddr.c | 43 - board/sbc8560/law.c | 60 -- board/sbc8560/sbc8560.c | 369 - board/sbc8560/tlb.c | 65 --- boards.cfg| 6 - include/configs/SBC8540.h | 428 -- include/configs/sbc8560.h | 459 -- 10 files changed, 1539 deletions(-) delete mode 100644 board/sbc8560/Makefile delete mode 100644 board/sbc8560/README delete mode 100644 board/sbc8560/ddr.c delete mode 100644 board/sbc8560/law.c delete mode 100644 board/sbc8560/sbc8560.c delete mode 100644 board/sbc8560/tlb.c delete mode 100644 include/configs/SBC8540.h delete mode 100644 include/configs/sbc8560.h -- 1.7.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc: delete Wind River SBC8560/8540 support
The sbc8548/60 (both similar, just variations in UART hardware) support has been removed from the linux kernel as of v3.6-rc1~132 so lets also now remove it from the u-boot tree as well. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- MAINTAINERS | 2 - board/sbc8560/Makefile| 50 - board/sbc8560/README | 57 -- board/sbc8560/ddr.c | 43 - board/sbc8560/law.c | 60 -- board/sbc8560/sbc8560.c | 369 - board/sbc8560/tlb.c | 65 --- boards.cfg| 6 - include/configs/SBC8540.h | 428 -- include/configs/sbc8560.h | 459 -- 10 files changed, 1539 deletions(-) delete mode 100644 board/sbc8560/Makefile delete mode 100644 board/sbc8560/README delete mode 100644 board/sbc8560/ddr.c delete mode 100644 board/sbc8560/law.c delete mode 100644 board/sbc8560/sbc8560.c delete mode 100644 board/sbc8560/tlb.c delete mode 100644 include/configs/SBC8540.h delete mode 100644 include/configs/sbc8560.h diff --git a/MAINTAINERS b/MAINTAINERS index aa54fe1..b8cbd63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -220,9 +220,7 @@ Siddarth Gore go...@marvell.com Paul Gortmaker paul.gortma...@windriver.com sbc8349 MPC8349 - sbc8540 MPC8540 sbc8548 MPC8548 - sbc8560 MPC8560 sbc8641dMPC8641D Frank Gottschling fgottschl...@eltec.de diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile deleted file mode 100644 index ce01560..000 diff --git a/board/sbc8560/README b/board/sbc8560/README deleted file mode 100644 index c4b6422..000 diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c deleted file mode 100644 index e9babc6..000 diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c deleted file mode 100644 index 4e6baed..000 diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c deleted file mode 100644 index 98bc7df..000 diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c deleted file mode 100644 index fe0ac76..000 diff --git a/boards.cfg b/boards.cfg index 091c79f..1f8934c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -670,17 +670,11 @@ suvd3powerpc mpc83xx km83xx keymile tuge1powerpc mpc83xx km83xx keymile- tuxx1:KM_DISABLE_APP2,TUGE1 tuxx1powerpc mpc83xx km83xx keymile kmsupx5 powerpc mpc83xx km83xx keymile- tuxx1:KM_DISABLE_APP2,KMSUPX5 -sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 -sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 -sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540 sbc8548 powerpc mpc85xx sbc8548 - - sbc8548 sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33 sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE sbc8548_PCI_66 powerpc mpc85xx sbc8548 - - sbc8548:PCI,66 sbc8548_PCI_66_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,66,PCIE -sbc8560 powerpc mpc85xx sbc8560 - - sbc8560 -sbc8560_33 powerpc mpc85xx sbc8560 - - sbc8560 -sbc8560_66 powerpc mpc85xx sbc8560 - - sbc8560 socrates powerpc mpc85xx socrates HWW1U1A powerpc mpc85xx hww1u1a exmeritus MPC8536DSpowerpc mpc85xx mpc8536ds freescale - MPC8536DS diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h deleted file mode 100644 index d448bf6..000 diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h deleted file mode 100644 index 46d6098..000 -- 1.7.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mpc85xx: use LCRR_DBYP define instead of raw constant
Using the raw value of 0x8000 directly in the code can
lead to count the zeros bugs like that fixed in commit
718e9d13b98 (MPC85xxCDS: Fix missing LCRR_DBYP bits for
66-133MHz LBC)
Change all existing raw values to use the symbolic value of
LCRR_DBYP instead.
Cc: Kumar Gala ga...@kernel.crashing.org
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c
b/board/freescale/mpc8540ads/mpc8540ads.c
index c75585e..a275d3a 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -87,10 +87,10 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 100 / clkdiv;
if (lbc_hz 66) {
- lbc-lcrr = CONFIG_SYS_LBC_LCRR | 0x8000; /* DLL Bypass */
+ lbc-lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;/* DLL Bypass */
} else if (lbc_hz = 133) {
- lbc-lcrr = CONFIG_SYS_LBC_LCRR (~0x8000); /* DLL Enabled
*/
+ lbc-lcrr = CONFIG_SYS_LBC_LCRR (~LCRR_DBYP); /* DLL Enabled
*/
} else {
/*
@@ -105,7 +105,7 @@ local_bus_init(void)
lbc-lcrr = 0x1004;
}
- lbc-lcrr = CONFIG_SYS_LBC_LCRR (~0x8000); /* DLL Enabled
*/
+ lbc-lcrr = CONFIG_SYS_LBC_LCRR (~LCRR_DBYP); /* DLL Enabled
*/
udelay(200);
/*
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c
b/board/freescale/mpc8541cds/mpc8541cds.c
index 532d32a..13ca84b 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -269,13 +269,13 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 100 / clkdiv;
if (lbc_hz 66) {
- lbc-lcrr |= 0x8000;/* DLL Bypass */
+ lbc-lcrr |= LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz = 133) {
- lbc-lcrr = (~0x8000); /* DLL Enabled */
+ lbc-lcrr = (~LCRR_DBYP); /* DLL Enabled */
} else {
- lbc-lcrr = (~0x8000); /* DLL Enabled */
+ lbc-lcrr = (~LCRR_DBYP); /* DLL Enabled */
udelay(200);
/*
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c
b/board/freescale/mpc8555cds/mpc8555cds.c
index 3361614..4cfd61c 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -267,13 +267,13 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 100 / clkdiv;
if (lbc_hz 66) {
- lbc-lcrr |= 0x8000;/* DLL Bypass */
+ lbc-lcrr |= LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz = 133) {
- lbc-lcrr = (~0x8000); /* DLL Enabled */
+ lbc-lcrr = (~LCRR_DBYP); /* DLL Enabled */
} else {
- lbc-lcrr = (~0x8000); /* DLL Enabled */
+ lbc-lcrr = (~LCRR_DBYP); /* DLL Enabled */
udelay(200);
/*
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c
b/board/freescale/mpc8560ads/mpc8560ads.c
index 1a165bf..285edbc 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -292,10 +292,10 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 100 / clkdiv;
if (lbc_hz 66) {
- lbc-lcrr = CONFIG_SYS_LBC_LCRR | 0x8000; /* DLL Bypass */
+ lbc-lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;/* DLL Bypass */
} else if (lbc_hz = 133) {
- lbc-lcrr = CONFIG_SYS_LBC_LCRR (~0x8000); /* DLL Enabled
*/
+ lbc-lcrr = CONFIG_SYS_LBC_LCRR (~LCRR_DBYP); /* DLL Enabled
*/
} else {
/*
@@ -310,7 +310,7 @@ local_bus_init(void)
lbc-lcrr = 0x1004;
}
- lbc-lcrr = CONFIG_SYS_LBC_LCRR (~0x8000);/* DLL Enabled
*/
+ lbc-lcrr = CONFIG_SYS_LBC_LCRR (~LCRR_DBYP);/* DLL Enabled */
udelay(200);
/*
--
1.7.12.rc1.1.ga9c166e
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Re: [U-Boot] [PATCH] AVR32 removal due to lack of custodian.
Adding linux maintainers to CC, since if it dies here, it should probably also die in the linux kernel as well... P. --- On Sat, Feb 25, 2012 at 5:13 PM, Wolfgang Denk w...@denx.de wrote: AVR32 appaers to be unmaintained, and nobody appears to care about that.  Let's get rid fof it. Signed-off-by: Wolfgang Denk w...@denx.de ---  doc/feature-removal-schedule.txt |   7 ++  1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt index e04ba2d..f0b828e 100644 --- a/doc/feature-removal-schedule.txt +++ b/doc/feature-removal-schedule.txt @@ -7,6 +7,20 @@ file.  --- +What:  ARV32 Support +When:  v2012.06 +Why:  Lack of a custodian and of interest, and lack of time and/or sponsors. +Who:  Wolfgang Denk w...@denx.de + +--- +  What:  Users of the legacy miiphy_* code  When:  undetermined -- 1.7.7.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] MPC8313 DDR2 configuration
On Tue, Feb 7, 2012 at 11:52 AM, Scott Larson slar...@a2etech.com wrote: Hi, Looking for help on DDR2 configuration in u-boot. I have the MPC8313ERDB from Freescale. It has 128Mbytes of DDR2 ram. The existing 128MByte that uses only CS0. I have a new board design to bring up. The timing parameters are all ok but I need some guidance on changing the settings to suit my memory configuration. My board has 512Mbytes on CS0 and 512Mbytes on CS1. Changes need to be made to files MPC8313ERDB.h and sdram.c SODIMM with SPD? Autoconfig with CONFIG_SPD_EEPROM is nice compared to hard coding values, if you can use it. I'm pretty sure it works fine on sbc8349 board. I have made all the row and column size and block address pin settings ok. I have set DDR size to 512Mbytes (per Chip Select). I need some guidance on the setting for CS1 bank of ram. Have you created the CONFIG_SYS_BR1_PRELIM and the CONFIG_SYS_OR1_PRELIM defines in your board header? If you copied these from a reference platform, they may still be populated with settings appropriate for flash up at the top of memory instead of DDR2 settings for your 2nd bank... P. thanks Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 85xx-next 2/8] sbc8548: relocate 64MB user flash to sane boundary
The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_ by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM. But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_.
This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_ to 0xff7f_, you would have to program a u-boot image
into the two sectors from 0xfbf0_ -- 0xfbff_ so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_)
We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.
In the end, there is address space from 0xec00_ to 0xefff_
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec -- 0xfc mapping. Plus we
can toss out a TLB entry.
Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/law.c |3 ++-
board/sbc8548/tlb.c | 23 ---
doc/README.sbc8548|8 +++-
include/configs/sbc8548.h | 10 +-
4 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index 5fa9db0..febb682 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -36,9 +36,9 @@
* 0xe000_ 0xe000_ CCSR1M
* 0xe200_ 0xe27f_ PCI1 IO 8M
* 0xe280_ 0xe2ff_ PCIe IO 8M
+ * 0xec00_ 0xefff_ FLASH (2nd bank)64M
* 0xf000_ 0xf7ff_ SDRAM 128M
* 0xf8b0_ 0xf80f_ EEPROM 1M
- * 0xfb80_ 0xff7f_ FLASH (2nd bank)64M
* 0xff80_ 0x_ FLASH (boot bank) 8M
*
* Notes:
@@ -47,6 +47,7 @@
*/
struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index bb4c052..e9cedc7 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -46,12 +46,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 0: 64M Non-cacheable, guarded
-* 0xfc00 56M 8MB - 64MB of user flash
+* 0xfc00 56M unused
* 0xff80 8M boot FLASH
+* or
+* 0xfc00 64M user flash
+*
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x80,
- CONFIG_SYS_ALT_FLASH + 0x80,
+ SET_TLB_ENTRY(1, 0xfc00, 0xfc00,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
@@ -103,21 +105,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 5, BOOKE_PAGESZ_16M, 1),
/*
-* TLB 6: 4M Non-cacheable, guarded
-* 0xfb80 4M 1st 4MB block of 64MB user FLASH
+* TLB 6: 64M Non-cacheable, guarded
+* 0xec00 64M 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_4M, 1),
-
- /*
-* TLB 7: 4M Non-cacheable, guarded
-* 0xfbc0 4M 2nd 4MB block of 64MB user FLASH
-*/
- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x40,
- CONFIG_SYS_ALT_FLASH + 0x40,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4M, 1),
+ 0, 6, BOOKE_PAGESZ_64M, 1),
};
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index 6cbe12f..5fa9c93 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -100,6 +100,9 @@ Boot flash:
Sodimm flash:
intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_
+ Note that this address reflects the default setting for
+ the JTAG debugging tools, but since the alignment is
+ rather inconvenient, u-boot puts it at 0xec00_.
Jumpers:
@@ -187,9 +190,12 @@ start end CSn width Desc.
_ 0fff_ MCS0,1 64 DDR2 (256MB)
f000_ f7ff_ CS3,4 32 LB SDRAM (128MB)
f800_ f8b0_1fff CS5 - EPLD
-fb80_ ff7f_ CS6 32 SODIMM flash (64MB)
+fb80_
[U-Boot] [PATCH 85xx-next 1/8] Revert SBC8548: fix address mask to allow 64M flash
This reverts commit ccf1ad535ae1c0dc2d466235c668adbdfe3a55b7.
The commit SBC8548: fix address mask to allow 64M flash
essentially made this change:
* OR6:
- *Addr Mask = 64M = OR6[0:16] = 1100 0
+ *Addr Mask = 64M = OR6[0:16] = 1000 0
But this makes no sense, as section 13.3.1.2.1 in the
MPC8548ERM v2 clearly indicates the masks:
__1000__0 8 Mbytes
_1100___0 64 Mbytes
_1000___0 128 Mbytes
So the original value was correct, and the commit was invalid,
causing a 128MB mapping for a 64MB flash device. The problem
rears its head when trying to configure u-boot to have access
to both flash, since the default memory map is:
FB80_ – FF7F_ 32-bits 64MB FLASH SODIMM
FF80_ – _ 8-bits 8MB FLASH
By extending the mapping of the 64MB flash to 128MB, it now
conflicts with the normal 8MB boot flash, causing issues.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
include/configs/sbc8548.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index ba7612c..7c26207 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -173,7 +173,7 @@
* 1000 0110 1110 0110 0101 = ff806e65OR0
*
* OR6:
- *Addr Mask = 64M = OR6[0:16] = 1000 0
+ *Addr Mask = 64M = OR6[0:16] = 1100 0
*XAM = OR6[17:18] = 11
*CSNT = OR6[20] = 1
*ACS = half cycle delay = OR6[21:22] = 11
@@ -182,7 +182,7 @@
*EAD = use external address latch delay = OR6[31] = 1
*
* 04812 16 20 24 28
- * 1000 0110 1110 0110 0101 = f8006e65OR6
+ * 1100 0110 1110 0110 0101 = fc006e65OR6
*/
#define CONFIG_SYS_BOOT_BLOCK 0xff80 /* start of 8MB Flash */
@@ -193,7 +193,7 @@
#define CONFIG_SYS_BR6_PRELIM 0xfb801801
#defineCONFIG_SYS_OR0_PRELIM 0xff806e65
-#defineCONFIG_SYS_OR6_PRELIM 0xf8006e65
+#defineCONFIG_SYS_OR6_PRELIM 0xfc006e65
#define CONFIG_SYS_FLASH_BANKS_LIST{CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_ALT_FLASH}
--
1.7.4.4
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[U-Boot] [PATCH 85xx-next 0/8] Updates for Wind River sbc8548 board
This updates the sbc8548 board support with several improvements for the end users. -ability to use SPD DDR config for easy RAM upgrades -ability to use alternate SODIMM flash for backup u-boot image -localbus config settings fixed so 128MB LBC SDRAM works reliably The discovery of a hardware errata (overlapping I2C SPD addresses) is at the core of what now allows the use of SPD configuration. The relocation of the 64MB user flash is to align it on a 64MB boundary, which simplifies a whole lot of things, both in the code and for the end user. (The previous mapping meant the last sector on the chip wasn't consistently the last sector in the address space assigned to the chip for all jumper configurations.) Reverting a bogus commit from the past that incorrectly set the windows for the 64MB flash to 128MB was the starting point for getting this all working. Paul. --- The following changes since commit cba9a894fdb1cb49b60fcd1d1d6919cbd7995dd5: Prepare v2011.12 (2011-12-23 20:25:35 +0100) are available in the git repository at: git://openlinux.windriver.com/people/paulg/u-boot sbc8548-Dec30_2011 Paul Gortmaker (8): Revert SBC8548: fix address mask to allow 64M flash sbc8548: relocate 64MB user flash to sane boundary sbc8548: enable ability to boot from alternate flash sbc8548: Fix LBC SDRAM initialization settings sbc8548: Make enabling SPD RAM configuration work sbc8548: relocate fixed ddr init code to ddr.c file sbc8548: enable support for hardware SPD errata workaround sbc8548: Fix up local bus init to be frequency aware board/sbc8548/ddr.c | 77 +++ board/sbc8548/law.c | 16 +- board/sbc8548/sbc8548.c | 111 +++-- board/sbc8548/tlb.c | 24 ++-- doc/README.sbc8548| 79 ++-- include/configs/sbc8548.h | 151 +++-- 6 files changed, 355 insertions(+), 103 deletions(-) -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 85xx-next 4/8] sbc8548: Fix LBC SDRAM initialization settings
These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size). Set the values
by comparing to the register file for the board used during
JTAG init sequence:
LSDMR1 0x2863B727 /* PCHALL */
LSDMR2 0x0863B727 /* NORMAL */
LSDMR3 0x1863B727 /* MRW*/
LSDMR4 0x4063B727 /* RFEN */
This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.
The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_ _and_ to 0xf400_.
We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/sbc8548.c | 29 -
include/configs/sbc8548.h | 21 ++---
2 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 63d504d..96554b2 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -107,13 +107,14 @@ void lbc_sdram_init(void)
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
+ const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- uint lsdmr_common;
+ uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
puts(SDRAM: );
- print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, \n);
+ print_size(size, \n);
/*
* Setup SDRAM Base and Option Registers
@@ -131,47 +132,49 @@ void lbc_sdram_init(void)
asm(msync);
/*
-* MPC8548 uses new 15-16 style addressing.
-*/
- lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= LSDMR_BSMA1516;
-
- /*
* Issue PRECHARGE ALL command.
*/
- out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
+ out_be32(lbc-lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
/*
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx 8; idx++) {
- out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
+ out_be32(lbc-lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
}
/*
* Issue 8 MODE-set command.
*/
- out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_MRW);
+ out_be32(lbc-lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(100);
/*
-* Issue NORMAL OP command.
+* Issue RFEN command.
*/
- out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
+ out_be32(lbc-lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
udelay(200);/* Overkill. Must wait 200 bus cycles */
#endif /* enable SDRAM init */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index fb07d09..1df2225 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -362,19 +362,26 @@
/*
* Common settings for all Local Bus SDRAM commands.
- * At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
- * is OR'ed in too.
*/
#define CONFIG_SYS_LBC_LSDMR_COMMON( LSDMR_RFCR16 \
- | LSDMR_PRETOACT7 \
- | LSDMR_ACTTORW7\
+ | LSDMR_BSMA1516\
+ | LSDMR_PRETOACT3 \
+ | LSDMR_ACTTORW3\
+ | LSDMR_BUFCMD \
| LSDMR_BL8 \
- | LSDMR_WRC4\
+ | LSDMR_WRC2\
| LSDMR_CL3 \
- | LSDMR_RFEN\
)
+#define CONFIG_SYS_LBC_LSDMR_PCHALL
[U-Boot] [PATCH 85xx-next 3/8] sbc8548: enable ability to boot from alternate flash
This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module. Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6. This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.
To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.
We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.
The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/law.c |8 +++
board/sbc8548/sbc8548.c |2 +-
board/sbc8548/tlb.c | 19
doc/README.sbc8548| 34 +--
include/configs/sbc8548.h | 106 +++-
5 files changed, 142 insertions(+), 27 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index febb682..c263191 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -41,13 +41,21 @@
* 0xf8b0_ 0xf80f_ EEPROM 1M
* 0xff80_ 0x_ FLASH (boot bank) 8M
*
+ * If swapped CS0/CS6 via JP12+SW2.8:
+ * 0xef80_ 0xefff_ FLASH (2nd bank)8M
+ * 0xfc00_ 0x_ FLASH (boot bank) 64M
+ *
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_ALT_BOOT
+ SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+#else
SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#endif
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 26095a5..63d504d 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -113,7 +113,7 @@ void lbc_sdram_init(void)
puts(SDRAM: );
- print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, \n);
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, \n);
/*
* Setup SDRAM Base and Option Registers
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index e9cedc7..4bf7214 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -104,6 +104,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_16M, 1),
+#ifndef CONFIG_SYS_ALT_BOOT
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xec00 64M 64MB user FLASH
@@ -111,6 +112,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
+#else
+ /*
+* TLB 6: 4M Non-cacheable, guarded
+* 0xef80 4M 1st 1/2 8MB soldered FLASH
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_4M, 1),
+
+ /*
+* TLB 7: 4M Non-cacheable, guarded
+* 0xefc0 4M 2nd half 8MB soldered FLASH
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x40,
+ CONFIG_SYS_ALT_FLASH + 0x40,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_4M, 1),
+#endif
};
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index 5fa9c93..e6b8abe 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -86,6 +86,33 @@ The md steps in the above are just a precautionary step
that allow
you to confirm the u-boot version that was downloaded, and then confirm
that it was copied to flash.
+The above assumes that you are using the default board settings which
+have u-boot in the 8MB flash, tied to /CS0.
+
+If you are running the default 8MB /CS0 settings but want to store an
+image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
+(as a backup, etc) then the steps will become:
+
+ tftp u-boot.bin
+ md 20 10
+ protect off all
+ era eff0 efff
+ cp.b 20 eff0 10
+ md eff0 10
+ protect on all
+
+Finally, if you are running the alternate 64MB /CS0 settings and want
+to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT
+enabled) the steps will become:
+
+ tftp u-boot.bin
[U-Boot] [PATCH 85xx-next 8/8] sbc8548: Fix up local bus init to be frequency aware
The code here was copied from the mpc8548cds support, and it
wasn't using the CONFIG_SYS_LBC_LCRR define, and was just
unconditionally setting the LCRR_EADC bit. Snooping with a
hardware debugger also showed we had LCRR_DBYP set, since we were
setting it based on a read of an uninitialized lcrr read via
clkdiv. Borrow from the code in the tqm85xx.c support to add
LBC frequency aware masking of these bits.
This change will correct reliability issues associated with trying
to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to
Keith Savage for assistance in diagnosing the root cause of this.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/sbc8548.c | 38 +++---
1 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index d1ef3be..371d076 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -76,11 +76,15 @@ local_bus_init(void)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint clkdiv;
+ uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
sys_info_t sysinfo;
get_sys_info(sysinfo);
- clkdiv = (in_be32(lbc-lcrr) LCRR_CLKDIV) * 2;
+
+ lbc_mhz = sysinfo.freqLocalBus / 100;
+ clkdiv = sysinfo.freqSystemBus / sysinfo.freqLocalBus;
+
+ debug(LCRR=0x%x, CD=%d, MHz=%d\n, lcrr, clkdiv, lbc_mhz);
out_be32(gur-lbiuiplldcr1, 0x00078080);
if (clkdiv == 16) {
@@ -91,10 +95,38 @@ local_bus_init(void)
out_be32(gur-lbiuiplldcr0, 0x5c0f1bf0);
}
- setbits_be32(lbc-lcrr, 0x0003);
+ /*
+* Local Bus Clock 83.3 MHz. According to timing
+* specifications set LCRR[EADC] to 2 delay cycles.
+*/
+ if (lbc_mhz 83) {
+ lcrr = ~LCRR_EADC;
+ lcrr |= LCRR_EADC_2;
+ }
+
+ /*
+* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
+* disable PLL bypass for Local Bus Clock 83 MHz.
+*/
+ if (lbc_mhz = 66)
+ lcrr = (~LCRR_DBYP); /* DLL Enabled */
+
+ else
+ lcrr |= LCRR_DBYP; /* DLL Bypass */
+ out_be32(lbc-lcrr, lcrr);
asm(sync;isync;msync);
+/*
+* According to MPC8548ERMAD Rev.1.3 read back LCRR
+* and terminate with isync
+*/
+ lcrr = in_be32(lbc-lcrr);
+ asm (isync;);
+
+ /* let DLL stabilize */
+ udelay(500);
+
out_be32(lbc-ltesr, 0x); /* Clear LBC error IRQs */
out_be32(lbc-lteir, 0x); /* Enable LBC error IRQs */
}
--
1.7.4.4
___
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[U-Boot] [PATCH 85xx-next 6/8] sbc8548: relocate fixed ddr init code to ddr.c file
Nothing to see here, just a relocation of the fixed ddr init
sequence to live in the actual ddr.c file itself.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/ddr.c | 48 +
board/sbc8548/sbc8548.c | 44 -
include/configs/sbc8548.h |1 +
3 files changed, 49 insertions(+), 44 deletions(-)
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 996ffe2..0d9a1ba 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -54,3 +54,51 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts-half_strength_driver_enable = 0;
}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * fixed_sdram init -- doesn't use serial presence detect.
+ * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
+ */
+phys_size_t fixed_sdram(void)
+{
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+ out_be32(ddr-cs0_bnds,0x007f);
+ out_be32(ddr-cs1_bnds,0x008000ff);
+ out_be32(ddr-cs2_bnds,0x);
+ out_be32(ddr-cs3_bnds,0x);
+
+ out_be32(ddr-cs0_config, 0x80010101);
+ out_be32(ddr-cs1_config, 0x80010101);
+ out_be32(ddr-cs2_config, 0x);
+ out_be32(ddr-cs3_config, 0x);
+
+ out_be32(ddr-timing_cfg_3,0x);
+ out_be32(ddr-timing_cfg_0,0x00220802);
+ out_be32(ddr-timing_cfg_1,0x38377322);
+ out_be32(ddr-timing_cfg_2,0x0fa044C7);
+
+ out_be32(ddr-sdram_cfg, 0x4300C000);
+ out_be32(ddr-sdram_cfg_2, 0x24401000);
+
+ out_be32(ddr-sdram_mode, 0x23C00542);
+ out_be32(ddr-sdram_mode_2,0x);
+
+ out_be32(ddr-sdram_interval, 0x05080100);
+ out_be32(ddr-sdram_md_cntl, 0x);
+ out_be32(ddr-sdram_data_init, 0x);
+ out_be32(ddr-sdram_clk_cntl, 0x0380);
+ asm(sync;isync;msync);
+ udelay(500);
+
+ #ifdef CONFIG_DDR_ECC
+ /* Enable ECC checking */
+ out_be32(ddr-sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x2000);
+ #else
+ out_be32(ddr-sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+ #endif
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 96554b2..d1ef3be 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -219,50 +219,6 @@ testdram(void)
}
#endif
-#if !defined(CONFIG_SPD_EEPROM)
-#define CONFIG_SYS_DDR_CONTROL 0xc300c000
-/*
- * fixed_sdram init -- doesn't use serial presence detect.
- * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
- /
-phys_size_t fixed_sdram(void)
-{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
- out_be32(ddr-cs0_bnds, 0x007f);
- out_be32(ddr-cs1_bnds, 0x008000ff);
- out_be32(ddr-cs2_bnds, 0x);
- out_be32(ddr-cs3_bnds, 0x);
- out_be32(ddr-cs0_config, 0x80010101);
- out_be32(ddr-cs1_config, 0x80010101);
- out_be32(ddr-cs2_config, 0x);
- out_be32(ddr-cs3_config, 0x);
- out_be32(ddr-timing_cfg_3, 0x);
- out_be32(ddr-timing_cfg_0, 0x00220802);
- out_be32(ddr-timing_cfg_1, 0x38377322);
- out_be32(ddr-timing_cfg_2, 0x0fa044C7);
- out_be32(ddr-sdram_cfg, 0x4300C000);
- out_be32(ddr-sdram_cfg_2, 0x24401000);
- out_be32(ddr-sdram_mode, 0x23C00542);
- out_be32(ddr-sdram_mode_2, 0x);
- out_be32(ddr-sdram_interval, 0x05080100);
- out_be32(ddr-sdram_md_cntl, 0x);
- out_be32(ddr-sdram_data_init, 0x);
- out_be32(ddr-sdram_clk_cntl, 0x0380);
- asm(sync;isync;msync);
- udelay(500);
-
- #if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- out_be32(ddr-sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x2000);
- #else
- out_be32(ddr-sdram_cfg, CONFIG_SYS_DDR_CONTROL);
- #endif
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif
-
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI1 */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 44c7526..09245b5 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -148,6 +148,7 @@
*/
#ifndef CONFIG_SPD_EEPROM
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
+ #define CONFIG_SYS_DDR_CONTROL 0xc300c000
#endif
#undef CONFIG_CLOCKS_IN_MHZ
--
1.7.4.4
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[U-Boot] [PATCH 85xx-next 7/8] sbc8548: enable support for hardware SPD errata workaround
Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.
After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53. So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.
Since the old dependency issue of SPD implies no LBC SDRAM
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/ddr.c | 31 ++-
doc/README.sbc8548| 20 ++--
include/configs/sbc8548.h | 14 ++
3 files changed, 58 insertions(+), 7 deletions(-)
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 0d9a1ba..45ec485 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -7,6 +7,7 @@
*/
#include common.h
+#include i2c.h
#include asm/fsl_ddr_sdram.h
#include asm/fsl_ddr_dimm_params.h
@@ -55,7 +56,35 @@ void fsl_ddr_board_options(memctl_options_t *popts,
popts-half_strength_driver_enable = 0;
}
-#if !defined(CONFIG_SPD_EEPROM)
+#ifdef CONFIG_SPD_EEPROM
+/*
+ * Workaround for hardware errata. An i2c address conflict
+ * existed on earlier boards; the workaround moved the DDR
+ * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
+ * if that fails, then fall back to reading at 0x51.
+ */
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret;
+
+#ifdef ALT_SPD_EEPROM_ADDRESS
+ if (i2c_address == SPD_EEPROM_ADDRESS) {
+ ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+ if (ret == 0)
+ return; /* Good data at 0x53 */
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+#endif
+ ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+ if (ret) {
+ printf(DDR: failed to read SPD from addr %u\n, i2c_address);
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+}
+
+#else
/*
* fixed_sdram init -- doesn't use serial presence detect.
* Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index f9e2dea..0f3f543 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -71,7 +71,22 @@ EEPROM data to read what memory is installed.
There is a hardware errata, which causes the older local bus SDRAM
SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
-that the SPD data can not be read reliably.
+that the SPD data can not be read reliably. You can test if your
+board has the errata fix by running i2c probe. If you see 0x53
+as a valid device, it has been fixed. If you only see 0x50, 0x51
+then your board does not have the fix.
+
+You can also visually inspect the board to see if this hardware
+fix has been applied:
+
+ 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
+ the back of the PCB behind the DDR SDRAM SODIMM connector.
+ 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
+ to R313 pin 2. Pin 2 for each resistor is the end of the
+ resistor closest to the CPU.
+
+Boards without the mod will have R314 and R313 in parallel, like ||.
+After the mod, they will be touching and form an L shape.
If you want to upgrade to larger RAM size, you can simply enable
#define CONFIG_SPD_EEPROM
@@ -79,7 +94,8 @@ If you want to upgrade to larger RAM size, you can simply
enable
in include/configs/sbc8548.h file. (The lines are already there
but listed as #undef).
-Note that you will have to physically remove the LBC 128MB DIMM
+If you did the i2c test, and your board does not have the errata
+fix, then you will have to physically remove the LBC 128MB DIMM
from the board's socket to resolve the above i2c address overlap
issue and allow SPD autodetection of RAM to work.
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 09245b5..d87394c 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -124,7 +124,9 @@
* A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
* to collide, meaning you couldn't reliably read either. So
* physically remove the LBC PC100 SDRAM module from the board
- * before enabling the two SPD options below.
+ * before enabling the two SPD options below, or check that you
+ * have the hardware fix on your board via i2c probe and looking
+ * for a device at 0x53.
*/
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_SPD
@@ -140,8 +142,13 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define
[U-Boot] [PATCH 85xx-next 5/8] sbc8548: Make enabling SPD RAM configuration work
Previously, SPD configuration of RAM was non functional on
this board. Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.
We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled. We can revisit this dependency as the
hardware workaround becomes available.
Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.
This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.
The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs. But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/law.c |5 +
board/sbc8548/tlb.c |2 ++
doc/README.sbc8548| 21 +
include/configs/sbc8548.h | 13 -
4 files changed, 40 insertions(+), 1 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index c263191..322af76 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -59,8 +59,13 @@ struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/* LBC window - maps 256M 0xf000 - 0x */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#else
+ /* LBC window - maps 128M 0xf800 - 0x */
+ SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 4bf7214..af927f1 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -76,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
/*
* TLB 3: 64M Cacheable, non-guarded
* 0xf000 64M LBC SDRAM First half
@@ -92,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_LBC_SDRAM_BASE + 0x400,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
+#endif
/*
* TLB 5: 16M Cacheable, non-guarded
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index e6b8abe..f9e2dea 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -62,6 +62,27 @@ a 33MHz PCI configuration is currently untested.)
02.00.00 0x1148 0x9e00 Network controller 0x00
=
+Memory Size and using SPD:
+==
+
+The default configuration uses hard coded memory configuration settings
+for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
+EEPROM data to read what memory is installed.
+
+There is a hardware errata, which causes the older local bus SDRAM
+SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
+that the SPD data can not be read reliably.
+
+If you want to upgrade to larger RAM size, you can simply enable
+ #define CONFIG_SPD_EEPROM
+ #define CONFIG_DDR_SPD
+in include/configs/sbc8548.h file. (The lines are already there
+but listed as #undef).
+
+Note that you will have to physically remove the LBC 128MB DIMM
+from the board's socket to resolve the above i2c address overlap
+issue and allow SPD autodetection of RAM to work.
+
Updating U-boot with U-boot:
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 1df2225..44c7526 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -119,9 +119,15 @@
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+/*
+ * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
+ * to collide, meaning you couldn't reliably read either. So
+ * physically remove the LBC PC100 SDRAM module from the board
+ * before enabling the two SPD options below.
+ */
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_SPD
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -283,9 +289,14 @@
/*
* SDRAM on the Local Bus (CS3 and CS4)
+ * Note that most boards have a hardware errata where both the
+ * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
Re: [U-Boot] New Oxford Semiconductor board with assertion fail in linker
On Mon, Dec 19, 2011 at 5:26 PM, Michael Kebe michael.k...@gmail.com wrote: Here is the output from a bootup of the old U-Boot: [...] U-Boot 1.1.2 (Jun 24 2011 - 09:41:57) [...] However even if I try to build with these addresses, the linking crashes with even more assertion fails: Everyone always feels that they need to do a big uprev in one giant step. That is not an insult in any way -- I've also done the same thing. But even if you get it compiled, are you ready to debug silent-boot-death where you don't get a single byte out the UART? The probability of this happening is relatively high, since your origin tree is so old and predates the config.mk removal stuff. I think in a case like this, you would be well served to start with smaller steps, since your origin is so old. Try moving it just to U-Boot-1_1_4 and see if you can make that work. THat will ensure your process, and your toolchain and your install are OK. Then maybe U-Boot-1_2_0 and then next to v1.3.0, then v1.3.4, then v2008.10 and so on. In doing so, you'll have a chance to test your images along the way, and you'll eventually find the region in which the assertion failures appear for the 1st time. Sometimes you simply can't see the problems by staring at the code; you really need to know at what point they 1st appeared. Your patches should be largely portable, since they mostly create new files, and should only make small changes to existing Makefiles, etc. So the task is not too hard to attack incrementally. Using git rebase and enabling git rerere in your .gitconfig will be something you'll want to make use of. Once you've got a definitive good version, and a definitive bad version, you can even make use of git bisect, as long as you remember to layer on your patches at each bisection point before building. It isn't an answer to your specific problem, but it is a process that will get you there by yourself, at your own pace. And once you have a more concrete focus on what change caused your problem, then when you do ask for help, you will most likely get better help. Good luck! Paul. /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12241 /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld: BFD (crosstool-NG 1.13.2) 2.21.1 assertion fail /home/michael/tmp/x/.build/src/binutils-2.21.1a/bfd/elf32-arm.c:12478 /bin/bash: line 1: Â 5198 Segmentation fault /home/michael/x-tools/arm-unknown-eabi/bin/arm-unknown-eabi-ld -pie -T u-boot.lds -Bstatic -Ttext 0x60d0 $UNDEF_SYM arch/arm/cpu/arm1176/start.o --start-group api/libapi.o arch/arm/cpu/arm1176/libarm1176.o
Re: [U-Boot] New Oxford Semiconductor board with assertion fail in linker
On Mon, Dec 19, 2011 at 10:14 PM, Marek Vasut marek.va...@gmail.com wrote: On Mon, Dec 19, 2011 at 5:26 PM, Michael Kebe michael.k...@gmail.com wrote: Here is the output from a bootup of the old U-Boot: [...] It isn't an answer to your specific problem, but it is a process that will get you there by yourself, at your own pace. Â And once you have a more concrete focus on what change caused your problem, then when you do ask for help, you will most likely get better help. ... or you can just snap in a JTAG debugger, connect GDB and throw some break/watch points here and there ;-) And how exactly is a JTAG going to help him resolve compile time issues he's currently having? Sure, JTAG is nice for things, and some are lucky enough to have access to one. But $ means it is not something everyone has, and it is not a substitute for thinking your way through a problem. I'm more apt to use one to restore a bad flash image than anything else more complicated. P. M ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
These boards were meaning to deploy this value:
#define LCRR_DBYP0x8000
but were missing a zero, and hence toggling a bit that
lands in an area marked as reserved in the 8548 reference
manual.
According to the documentation, LCRR_DBYP should be used as:
PLL bypass. This bit should be set when using low bus
clock frequencies if the PLL is unable to lock. When in
PLL bypass mode, incoming data is captured in the middle
of the bus clock cycle. It is recommended that PLL bypass
mode be used at frequencies of 83 MHz or less.
So the impact would most likely be undefined behaviour for
LBC peripherals on boards that were running below 83MHz LBC.
Looking at the actual u-boot code, the missing DBYP bit was
meant to be deployed as follows:
Between 66 and 133, the DLL is enabled with an
override workaround.
In the future, we'll convert all boards to use the symbolic
DBYP constant to avoid these count the zeros problems, but
for now, just fix the impacted boards.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c
b/board/freescale/mpc8541cds/mpc8541cds.c
index d127137..532d32a 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -275,7 +275,7 @@ local_bus_init(void)
lbc-lcrr = (~0x8000); /* DLL Enabled */
} else {
- lbc-lcrr = (~0x800); /* DLL Enabled */
+ lbc-lcrr = (~0x8000); /* DLL Enabled */
udelay(200);
/*
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c
b/board/freescale/mpc8555cds/mpc8555cds.c
index 48ede98..3361614 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -273,7 +273,7 @@ local_bus_init(void)
lbc-lcrr = (~0x8000); /* DLL Enabled */
} else {
- lbc-lcrr = (~0x800); /* DLL Enabled */
+ lbc-lcrr = (~0x8000); /* DLL Enabled */
udelay(200);
/*
--
1.7.4.4
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[U-Boot] [PATCH] fsl_lbc: add printout of LCRR and LBCR to local bus regs
It can be handy to have these in the output when trying to debug odd behaviour. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 587576b..023ac9a 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -28,6 +28,8 @@ void print_lbc_regs(void) printf(BR%d\t0x%08X\tOR%d\t0x%08X\n, i, get_lbc_br(i), i, get_lbc_or(i)); } + printf(LBCR\t0x%08X\tLCRR\t0x%08X\n, + get_lbc_lbcr(), get_lbc_lcrr()); } void init_early_memctl_regs(void) diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index bf572b7..2a23d84 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -475,6 +475,8 @@ extern void init_early_memctl_regs(void); extern void upmconfig(uint upm, uint *table, uint size); #define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR) +#define get_lbc_lcrr() (in_be32((LBC_BASE_ADDR)-lcrr)) +#define get_lbc_lbcr() (in_be32((LBC_BASE_ADDR)-lbcr)) #define get_lbc_br(i) (in_be32((LBC_BASE_ADDR)-bank[i].br)) #define get_lbc_or(i) (in_be32((LBC_BASE_ADDR)-bank[i].or)) #define set_lbc_br(i, v) (out_be32((LBC_BASE_ADDR)-bank[i].br, v)) -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MAINTAINERS: delete stale entry for EOL Wind River boards
This e-mail address is no longer valid, and the boards are long since EOL. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com diff --git a/MAINTAINERS b/MAINTAINERS index 2f60a60..12fe091 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -355,11 +355,6 @@ Kim Phillips kim.phill...@freescale.com MPC8349EMDS MPC8349 -Daniel Poirot dan.poi...@windriver.com - - sbc8240 MPC8240 - sbc405 PPC405GP - Sergei Poselenov sposele...@emcraft.com a4m072 MPC5200 -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl_pci: Update PCIe boot ouput
On Tue, Dec 28, 2010 at 6:47 PM, Peter Tyser pty...@xes-inc.com wrote: This change does the following: - Adds printing of negotiated link width.  This information can be  useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name().  Previously boards that did not implement it would print unsightly  output such as PCIE1: Connected to NULL... - Rewords the PCIe boot output to reduce line length and to make it  clear that the base address XYZ value refers to the base address of  the internal processor PCIe registers and not a standard PCI BAR  value. - Changes PCIE output to the standard PCIe Before change: PCIE1: connected to NULL as Root Complex (base addr ef008000)  01:00.0   - 10b5:8518 - Bridge device  02:01.0   - 10b5:8518 - Bridge device  02:02.0   - 10b5:8518 - Bridge device  02:03.0   - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to NULL as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000  01:00.0   - 10b5:8518 - Bridge device  02:01.0   - 10b5:8518 - Bridge device  02:02.0   - 10b5:8518 - Bridge device  02:03.0   - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser pty...@xes-inc.com Tested-by: Paul Gortmaker paul.gortma...@windriver.com The sbc8641d had the same NULL issue; I've put the before and after below for reference. Paul. --- Board: Wind River SBC8641D I2C: ready DRAM: DDR: 512 MiB FLASH: 16 MiB PCIE1: connected to NULL as Root Complex (base addr f8008000) 01:00.0 - 1148:9e00 - Network controller PCIE1: Bus 00 - 01 PCIE2: connected to NULL as Root Complex (base addr f8009000) PCIE2: Bus 02 - 02 In:serial Out: serial Err: serial Net: eTSEC1, eTSEC2, eTSEC3, eTSEC4 - Board: Wind River SBC8641D I2C: ready DRAM: DDR: 512 MiB FLASH: 16 MiB PCIe1: Root Complex, x1, regs @ 0xf8008000 01:00.0 - 1148:9e00 - Network controller PCIe1: Bus 00 - 01 PCIe2: Root Complex, no link, regs @ 0xf8009000 PCIe2: Bus 02 - 02 In:serial Out: serial Err: serial Net: eTSEC1, eTSEC2, eTSEC3, eTSEC4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7] powerpc/86xx: Convert SBC8641 to use common SRIO init code
[[PATCH 7/7] powerpc/86xx: Convert SBC8641 to use common SRIO init code] On
06/01/2011 (Thu 10:58) Kumar Gala wrote:
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
CC: Paul Gortmaker paul.gortma...@windriver.com
Tested in conjuntion with the mpc85xx dev branch and Peter's patch.
For some reason flash erase doesn't work, but I'm guessing that is a
completely unrelated regression that I'll need to track down.
Tested-by: Paul Gortmaker paul.gortma...@windriver.com
P.
---
board/sbc8641d/law.c |1 -
include/configs/sbc8641d.h | 15 +--
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
index a6f60ee..14259d6 100644
--- a/board/sbc8641d/law.c
+++ b/board/sbc8641d/law.c
@@ -51,7 +51,6 @@ struct law_entry law_table[] = {
#endif
SET_LAW(0xf800, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(0xfe00, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 90d84eb..f425150 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -57,6 +57,9 @@
*/
#define CONFIG_SYS_SCRATCH_VA0xe800
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+
#define CONFIG_PCI 1 /* Enable PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
@@ -297,9 +300,9 @@
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_BASE 0xc000 /* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
-#define CONFIG_SYS_RIO_MEM_SIZE 0x2000 /* 128M */
+#define CONFIG_SYS_SRIO1_MEM_BASE0xc000 /* base address */
+#define CONFIG_SYS_SRIO1_MEM_PHYSCONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_SIZE0x2000 /* 128M */
/*
* General PCI
@@ -417,10 +420,10 @@
* BAT2 512M Cache-inhibited, guarded
* 0xc000_ 512M RapidIO Memory
*/
-#define CONFIG_SYS_DBAT2L(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M |
BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW |
BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M |
BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW |
BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2UCONFIG_SYS_DBAT2U
/*
--
1.7.2.3
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Re: [U-Boot] [PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code
[[PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code] On 17/12/2010 (Fri 17:50) Kumar Gala wrote: Remove duplicated code in SBC8548 board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala ga...@kernel.crashing.org CC: Paul Gortmaker paul.gortma...@windriver.com Tested-by: Paul Gortmaker paul.gortma...@windriver.com Tested with Peter's anti-NULL patch on top of the mpc85xx dev branch. Board has both PCI-X and PCI-e slots, with e1000 and skge respectively. P. --- U-Boot 2010.12-00426-ged7ea8f (Jan 06 2011 - 15:43:08) CPU: 8548E, Version: 2.0, (0x80390020) Core: E500, Version: 2.0, (0x80210020) Clock Configuration: CPU0:990 MHz, CCB:396 MHz, DDR:198 MHz (396 MT/s data rate), LBC:99 MHz L1:D-cache 32 kB enabled I-cache 32 kB enabled Board: Wind River SBC8548 Rev. 0x2 I2C: ready DRAM: SDRAM: 128 MiB DDR: 256 MiB (DDR2, 64-bit, CL=4, ECC off) DDR Chip-Select Interleaving Mode: CS0+CS1 FLASH: 72 MiB L2:512 KB already enabled *** Warning - bad CRC, using default environment PCI: Host, 64 bit, 66 MHz, sync, arbiter 00:01.0 - 8086:1026 - Network controller PCI1: Bus 00 - 00 PCIe1: Root Complex, x1, regs @ 0xe000a000 02:00.0 - 1148:9e00 - Network controller PCIe1: Bus 01 - 02 In:serial Out: serial Err: serial Net: eTSEC0, eTSEC1 Hit any key to stop autoboot: 0 = pci 0 Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _ 00.00.00 0x1057 0x0012 Processor 0x20 00.01.00 0x8086 0x1026 Network controller 0x00 = pci 1 Scanning PCI devices on bus 1 BusDevFun VendorId DeviceId Device Class Sub-Class _ 01.00.00 0x1957 0x0012 Processor 0x20 = pci 2 Scanning PCI devices on bus 2 BusDevFun VendorId DeviceId Device Class Sub-Class _ 02.00.00 0x1148 0x9e00 Network controller 0x00 = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 85xx board maintainership / anyone care?
On Tue, Dec 14, 2010 at 11:59 AM, Paul Gortmaker paul.gortma...@windriver.com wrote: On Tue, Dec 14, 2010 at 10:12 AM, Kumar Gala ga...@kernel.crashing.org wrote: On Dec 14, 2010, at 1:34 AM, Paul Gortmaker wrote: On Mon, Dec 13, 2010 at 11:10 PM, Kumar Gala ga...@kernel.crashing.org wrote: On Dec 10, 2010, at 12:21 PM, Kumar Gala wrote: MPC8540EVAL There might have been one of these relics kicking around somewhere, but I won't be able to check until I'm back in Ottawa on Wed. If it is just a hardware/validation issue to offset the inevitable bitrot, and if I do actually have a working board, I could probably build test it. Let me know if you have one. Â I'd like more than compile testing on the platform. Â We've been build testing it for years now. Â I'm more concerned if it actually boots and if anyone cares. Yeah, I meant to say boot not build. Â If I start requiring a physical board in order to just build test, I'll voluntarily surrender my keyboard. I'll let you know tomorrow when I get back. It turns out the board I have is an MPC8540ADS and not the MPC8540EVAL -- close but not quite the same. P. Paul. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 09/12] mpc85xx boards: initdram() cleanup/bugfix
On Mon, Dec 13, 2010 at 9:12 PM, Paul Gortmaker paul.gortma...@windriver.com wrote: I'm not anywhere near the office at the moment, but later in the week I'll see if I can find a board (or two?) to test on. Paul. Seems OK for POST test on an old MPC8540ADS. The info printed for SDRAM kind of interjects itself into the DRAM info, but that is largely cosmetic. Testing details of the base commit I used to am your patches to are below. Feel free to add a Tested-by: from me if you want. P. -- = reset U-Boot 2010.12-rc1-00038-g04af960 (Dec 15 2010 - 18:09:59) CPU: 8540, Version: 2.0, (0x80300020) Core: Unknown, Version: 2.0, (0x80200020) Clock Configuration: CPU0:825 MHz, CCB:330 MHz, DDR:165 MHz (330 MT/s data rate), LBC:82.500 MHz L1:D-cache 32 kB enabled I-cache 32 kB enabled Board: ADS PCI1: 32 bit, 33 MHz (compiled) I2C: ready DRAM: SDRAM: 64 MiB 256 MiB (DDR1, 64-bit, CL=2.5, ECC off) FLASH: 16 MiB L2:256 KB already enabled *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: TSEC0, TSEC1, FEC Hit any key to stop autoboot: 0 = u-boot$git merge-base master HEAD 0c0892be0d93a5a892b93739c5eb3bf692fed4ff u-boot$git describe v2010.12-rc1-38-g04af960 u-boot$git request-pull master . The following changes since commit 0c0892be0d93a5a892b93739c5eb3bf692fed4ff: Merge branch 'master' of git://git.denx.de/u-boot-marvell (2010-10-29 22:03:00 +0200) are available in the git repository at: . bb-dram Becky Bruce (12): mpc8540eval: Split initdram() into initdram() and sdram_init() tqm85xx: create fixed_sdram() to do sdram setup mpc85xx/tlb.c: Allow platforms to specify wimge bits socrates: rename sdram_setup fixed_sdram() mpc8569mds: Remove unnecessary CONFIG_SYS_LBC_SDRAM_BASE definition PM854: rename CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_BASE PM856: Rename CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_BASE MPC8568/MPC8569: Remove CONFIG_DDR_DLL define mpc85xx boards: initdram() cleanup/bugfix 85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN mpc85xx: rename sdram_init() lbc_sdram_init() MPC8xxx DDR: align informational prints ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 85xx board maintainership / anyone care?
On Tue, Dec 14, 2010 at 10:12 AM, Kumar Gala ga...@kernel.crashing.org wrote: On Dec 14, 2010, at 1:34 AM, Paul Gortmaker wrote: On Mon, Dec 13, 2010 at 11:10 PM, Kumar Gala ga...@kernel.crashing.org wrote: On Dec 10, 2010, at 12:21 PM, Kumar Gala wrote: MPC8540EVAL There might have been one of these relics kicking around somewhere, but I won't be able to check until I'm back in Ottawa on Wed. If it is just a hardware/validation issue to offset the inevitable bitrot, and if I do actually have a working board, I could probably build test it. Let me know if you have one. Â I'd like more than compile testing on the platform. Â We've been build testing it for years now. Â I'm more concerned if it actually boots and if anyone cares. Yeah, I meant to say boot not build. If I start requiring a physical board in order to just build test, I'll voluntarily surrender my keyboard. I'll let you know tomorrow when I get back. Paul. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 85xx board maintainership / anyone care?
[Re: [U-Boot] 85xx board maintainership / anyone care?] On 14/12/2010 (Tue 11:10) Becky Bruce wrote: On Dec 14, 2010, at 10:59 AM, Paul Gortmaker wrote: On Tue, Dec 14, 2010 at 10:12 AM, Kumar Gala ga...@kernel.crashing.org wrote: On Dec 14, 2010, at 1:34 AM, Paul Gortmaker wrote: On Mon, Dec 13, 2010 at 11:10 PM, Kumar Gala ga...@kernel.crashing.org wrote: On Dec 10, 2010, at 12:21 PM, Kumar Gala wrote: MPC8540EVAL There might have been one of these relics kicking around somewhere, but I won't be able to check until I'm back in Ottawa on Wed. If it is just a hardware/validation issue to offset the inevitable bitrot, and if I do actually have a working board, I could probably build test it. Let me know if you have one. I'd like more than compile testing on the platform. We've been build testing it for years now. I'm more concerned if it actually boots and if anyone cares. Yeah, I meant to say boot not build. If I start requiring a physical board in order to just build test, I'll voluntarily surrender my keyboard. I'll let you know tomorrow when I get back. So are we keeping 8540EVAL? Let me know and I'll look at fixing the problem Paul pointed out with RAMBOOT. I can test it actually boots (assuming I have the board). I'm not sure how to test for Kumar's 2nd question -- i.e. if anyone actually cares. :) I'm not sure what the board specs are -- if it is hideously crippled in terms of tiny amount of RAM and an ancient CPU, then maybe the best thing is to shoot it in the head and be done with it. In which case, I can think of other suitable victims for cull, like the original EST8260 that had all of a whopping 16MB RAM, etc. Does u-boot have an equivalent to feature-removal-schedule.txt like the kernel has? It might not be a bad idea to have something similar vs. having boards disappear with relatively short notice. Things like e-mail bounces and people on vacation might mean that someone who cares simply hadn't seen the notice yet. Paul. -b Paul. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 85xx board maintainership / anyone care?
[Re: [U-Boot] 85xx board maintainership / anyone care?] On 13/12/2010 (Mon 12:46) Kumar Gala wrote: On Dec 12, 2010, at 9:23 AM, Paul Gortmaker wrote: On Fri, Dec 10, 2010 at 1:21 PM, Kumar Gala ga...@kernel.crashing.org wrote: There are a few 85xx boards that I'm wondering if anyone cares about or is acting as a maintainer: ATUM8548(Robert Lazarski) MPC8540EVAL PM854 PM856 socrates(Sergei Poselenov) sbc8540 sbc8560 I think the sbc8560 has a year or so left in it based on what I've seen around here, and the sbc8540 uses the same code base. These are definitely in maintenance-only mode, though. sbc8548 (Joe Hamman) This board is definitely still in quite active use, and I've got some patches for booting off the alternate DIMM flash to submit someday (once I get them actually working, that is). Feel free to put me down as maintainer for the sbc85xx, and also for the sbc8641d (for consistency) if that helps. Paul. Paul, thanks I'll keep the SBC85xx boards around. Are you ok being listed as maintainer for them? Yep, as per above. I don't think Joe's around anymore as his email address bounced. Yeah, I saw that, so I went ahead and adopted the sbc8641d as well. The WR sbc p4080 will be the next to join the clan, once I get a better handle on DDR config/SPD magic and get it working on master. Paul. From f1aa146a4fd94b69affb4569b4b4393b54e0dbf8 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker paul.gortma...@windriver.com Date: Mon, 13 Dec 2010 14:35:21 -0500 Subject: [PATCH] MPC8xxx: Update maintainer entry for Wind River sbc8xxx boards I've probably got the best chance of getting access to these boards in order to test things, and since Joe's e-mail is bouncing, update the MAINTAINERS entry to reflect this. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- MAINTAINERS | 13 - 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 9258cb1..ddbe5d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -198,6 +198,14 @@ Siddarth Gore go...@marvell.com guruplugARM926EJS (Kirkwood SoC) +Paul Gortmaker paul.gortma...@windriver.com + + sbc8349 MPC8349 + sbc8540 MPC8540 + sbc8548 MPC8548 + sbc8560 MPC8560 + sbc8641dMPC8641D + Frank Gottschling fgottschl...@eltec.de MHPCMPC8xx @@ -212,11 +220,6 @@ Wolfgang Grandegger w...@denx.de IPHASE4539 MPC8260 SCM MPC8260 -Joe Hamman joe.ham...@embeddedspecialties.com - - sbc8548 MPC8548 - sbc8641dMPC8641D - Klaus Heydeck heyd...@kieback-peter.de KUP4K MPC855 -- 1.7.3.2.146.g2d444 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 85xx board maintainership / anyone care?
On Mon, Dec 13, 2010 at 11:10 PM, Kumar Gala ga...@kernel.crashing.org wrote: On Dec 10, 2010, at 12:21 PM, Kumar Gala wrote: MPC8540EVAL There might have been one of these relics kicking around somewhere, but I won't be able to check until I'm back in Ottawa on Wed. If it is just a hardware/validation issue to offset the inevitable bitrot, and if I do actually have a working board, I could probably build test it. P. PM854 PM856 Looks like these 3 boards don't have anyone speaking up for them so I intend to remove them. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] powerpc/sbc8xxx: Update MAINTAINERS
On Mon, Dec 13, 2010 at 11:12 PM, Kumar Gala ga...@kernel.crashing.org wrote: List Paul Gortmaker as maintainer for SBC85xx and SBC86xx boards Signed-off-by: Kumar Gala ga...@kernel.crashing.org ---  MAINTAINERS |   4 +++-  1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4cf7c77..8da6018 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -212,8 +212,10 @@ Wolfgang Grandegger w...@denx.de     IPHASE4539    MPC8260     SCM       MPC8260 -Joe Hamman joe.ham...@embeddedspecialties.com +Paul Gortmaker paul.gortma...@windriver.com +    sbc8540     MPC8540 +    sbc8546     MPC8560 Can you just grab the commit I sent you in the maintainers thread, since it also lists the sbc8349 which I'd added the support for, and it puts the listing in the desired alphabetical order? Thanks, Paul.     sbc8548     MPC8548     sbc8641d     MPC8641D -- 1.7.2.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 85xx board maintainership / anyone care?
On Fri, Dec 10, 2010 at 1:21 PM, Kumar Gala ga...@kernel.crashing.org wrote: There are a few 85xx boards that I'm wondering if anyone cares about or is acting as a maintainer: ATUM8548     (Robert Lazarski) MPC8540EVAL PM854 PM856 socrates     (Sergei Poselenov) sbc8540 sbc8560 I think the sbc8560 has a year or so left in it based on what I've seen around here, and the sbc8540 uses the same code base. These are definitely in maintenance-only mode, though. sbc8548 (Joe Hamman) This board is definitely still in quite active use, and I've got some patches for booting off the alternate DIMM flash to submit someday (once I get them actually working, that is). Feel free to put me down as maintainer for the sbc85xx, and also for the sbc8641d (for consistency) if that helps. Paul. stxgp3  (Dan Malek) stxssa  (Dan Malek) I'd like to remove support for any of these unmaintained or uncared for boards for post v2010.12. thanks - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: e1000: Add initialized eth_device e1000_hw structure
On Fri, Nov 12, 2010 at 5:13 AM, Kumar Gala ga...@kernel.crashing.org wrote:
nic and hw structures are allocated via malloc i.e. return memory
is not zero initialized. Because of this few structure member like
function pointers are initialized with garbage values.
It may cause problem. for eg. during eth_initialize, dev-write_hwaddr
is used.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
 drivers/net/e1000.c |  14 ++
 1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 2825342..911eb2c 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -5177,7 +5177,21 @@ e1000_initialize(bd_t * bis)
        }
        nic = (struct eth_device *) malloc(sizeof (*nic));
+ Â Â Â Â Â Â Â if (!nic) {
+ Â Â Â Â Â Â Â Â Â Â Â printf(Error: e1000 - Can not alloc memory\n);
+ Â Â Â Â Â Â Â Â Â Â Â return 0;
+ Â Â Â Â Â Â Â }
+
        hw = (struct e1000_hw *) malloc(sizeof (*hw));
+ Â Â Â Â Â Â Â if (!nic) {
Copy and paste error, I think you want if (!hw)
Paul.
+ Â Â Â Â Â Â Â Â Â Â Â free(nic);
+ Â Â Â Â Â Â Â Â Â Â Â printf(Error: e1000 - Can not alloc memory\n);
+ Â Â Â Â Â Â Â Â Â Â Â return 0;
+ Â Â Â Â Â Â Â }
+
+ Â Â Â Â Â Â Â memset(nic, 0, sizeof(*dev));
+ Â Â Â Â Â Â Â memset(hw, 0, sizeof(*hw));
+
        hw-pdev = devno;
        nic-priv = hw;
--
1.7.2.3
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Re: [U-Boot] [PATCH] mpc8xxx: improve LAW error messages when setting up DDR
Peter Tyser wrote:
Hi Paul,
diff --git a/cpu/mpc8xxx/ddr/util.c b/cpu/mpc8xxx/ddr/util.c
index 4451989..d0f61a8 100644
--- a/cpu/mpc8xxx/ddr/util.c
+++ b/cpu/mpc8xxx/ddr/util.c
@@ -89,16 +89,16 @@ __fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params,
? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(base, size, lawbar1_target_id) 0) {
-printf(ERROR\n);
+printf(set_lawbar: ERROR (%d)\n, memctl_interleaved);
return ;
}
} else if (ctrl_num == 1) {
if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) 0) {
-printf(ERROR\n);
+printf(set_lawbar: ERROR (ctrl #2)\n);
This error would print out #2 for the 2nd controller...
I was thinking 1 based counting for the messages presented to the
end user instead of the internal zero based, but...
return ;
}
} else {
-printf(unexpected controller number %u in %s\n,
+printf(set_lawbar: unexpected controller number %u in %s\n,
ctrl_num, __FUNCTION__);
But this error would print out 2 for the 3rd controller. Either
...as you point out, it then is inconsistent. I'll fix that.
convention is going to be confusing, but it'd be nice if they were at
least consistent.
__func__ is preferred over __FUNCTION__, maybe you could update it also?
Wouldn't this message look at bit funny with the title being
set_lawbar: but then also including the full __fsl_ddr_set_lawbar in
the same message? And neither of the other errors include the printing
of __func__? Hopefully I'll never see the errors, so proceed as you see
fit:)
I never got to see this last one either, just the ERROR ones,
fortunately (?) but you make a good point - while in there, they
might as well all be standardized on func. I'll do that too.
Thanks,
Paul.
Best,
Peter
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[U-Boot] [PATCH v2] mpc8xxx: improve LAW error messages when setting up DDR
When setting up the LAWs for the DDR, if there was an error,
you got the not-so-helpful error text ERROR and nothing
else. Not only is it non-informative, but it is also
pretty frustrating trying to grep for ERROR in the source.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
v2: sync ctrl #'s; use __func__ as per Peter's comments.
cpu/mpc8xxx/ddr/util.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/util.c b/cpu/mpc8xxx/ddr/util.c
index 4451989..1e2d921 100644
--- a/cpu/mpc8xxx/ddr/util.c
+++ b/cpu/mpc8xxx/ddr/util.c
@@ -89,17 +89,18 @@ __fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params,
? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(base, size, lawbar1_target_id) 0) {
- printf(ERROR\n);
+ printf(%s: ERROR (ctrl #0, intrlv=%d)\n, __func__,
+ memctl_interleaved);
return ;
}
} else if (ctrl_num == 1) {
if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) 0) {
- printf(ERROR\n);
+ printf(%s: ERROR (ctrl #1)\n, __func__);
return ;
}
} else {
- printf(unexpected controller number %u in %s\n,
- ctrl_num, __FUNCTION__);
+ printf(%s: unexpected DDR controller number (%u)\n, __func__,
+ ctrl_num);
}
}
--
1.6.5.rc1
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[U-Boot] [PATCH] mpc8xxx: improve LAW error messages when setting up DDR
When setting up the LAWs for the DDR, if there was an error,
you got the not-so-helpful error text ERROR and nothing
else. Not only is it non-informative, but it is also
pretty frustrating trying to grep for ERROR in the source.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
cpu/mpc8xxx/ddr/util.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/util.c b/cpu/mpc8xxx/ddr/util.c
index 4451989..d0f61a8 100644
--- a/cpu/mpc8xxx/ddr/util.c
+++ b/cpu/mpc8xxx/ddr/util.c
@@ -89,16 +89,16 @@ __fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params,
? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(base, size, lawbar1_target_id) 0) {
- printf(ERROR\n);
+ printf(set_lawbar: ERROR (%d)\n, memctl_interleaved);
return ;
}
} else if (ctrl_num == 1) {
if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) 0) {
- printf(ERROR\n);
+ printf(set_lawbar: ERROR (ctrl #2)\n);
return ;
}
} else {
- printf(unexpected controller number %u in %s\n,
+ printf(set_lawbar: unexpected controller number %u in %s\n,
ctrl_num, __FUNCTION__);
}
}
--
1.6.5.rc1
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[U-Boot] [PATCH] mem_mtest: fix error reporting, allow escape with ^C
The basic memtest function tries to watch for ^C after each
pattern pass as an escape mechanism, but if things are horribly
wrong, we'll be stuck in an inner loop flooding the console with
error messages and never check for ^C. To make matters worse,
if the user waits for all the error messages to complete, we
then incorrectly report the test passed without errors.
Adding a check for ^C after any error is printed will give
the end user an escape mechanism from a console flood without
slowing down the overall test speed on a slow processor.
Also, the more extensive memtest quit after just a single error,
which is inconsistent with the normal memtest, and not useful if
if you are doing dynamic environmental impact testing, such as
heating/cooling etc.
Both tests now track the error count and report it properly
at test completion.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
Changes: fixed return values since prev. version.
common/cmd_mem.c | 58 -
1 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 9850800..a34b342 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -631,7 +631,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
vu_long *addr, *start, *end;
ulong val;
ulong readback;
- int rcode = 0;
+ ulong errs = 0;
int iterations = 1;
int iteration_limit;
@@ -698,9 +698,9 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
if (iteration_limit iterations iteration_limit) {
- printf(Tested %d iteration(s) without errors.\n,
- iterations-1);
- return 0;
+ printf(Tested %d iteration(s) with %lu errors.\n,
+ iterations-1, errs);
+ return errs != 0;
}
printf(Iteration: %6d\r, iterations);
@@ -732,9 +732,14 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
*dummy = ~val; /* clear the test data off of the bus */
readback = *addr;
if(readback != val) {
-printf (FAILURE (data line):
+ printf (FAILURE (data line):
expected %08lx, actual %08lx\n,
val, readback);
+ errs++;
+ if (ctrlc()) {
+ putc ('\n');
+ return 1;
+ }
}
*addr = ~val;
*dummy = val;
@@ -743,6 +748,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
printf (FAILURE (data line):
Is %08lx, should be %08lx\n,
readback, ~val);
+ errs++;
+ if (ctrlc()) {
+ putc ('\n');
+ return 1;
+ }
}
}
}
@@ -808,7 +818,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
printf (\nFAILURE: Address bit stuck high @ 0x%.8lx:
expected 0x%.8lx, actual 0x%.8lx\n,
(ulong)start[offset], pattern, temp);
- return 1;
+ errs++;
+ if (ctrlc()) {
+ putc ('\n');
+ return 1;
+ }
}
}
start[test_offset] = pattern;
@@ -826,7 +840,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
printf (\nFAILURE: Address bit stuck low or
shorted @
0x%.8lx: expected 0x%.8lx, actual 0x%.8lx\n,
(ulong)start[offset], pattern, temp);
- return 1;
+ errs++;
+ if (ctrlc()) {
+ putc ('\n');
+ return 1;
+ }
}
}
start[test_offset] = pattern;
@@ -864,7 +882,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
printf (\nFAILURE (read/write) @ 0x%.8lx:
expected 0x%.8lx, actual 0x%.8lx)\n,
(ulong)start[offset], pattern, temp);
- return 1
[U-Boot] [PATCH] mpc86xx: delete unused MPC86xx_DDR_SDRAM_CLK_CNTL define
This is an orphaned legacy leftover that is just polluting the config file namespace. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- include/configs/MPC8610HPCD.h |2 -- include/configs/MPC8641HPCN.h |2 -- include/configs/sbc8641d.h|2 -- 3 files changed, 0 insertions(+), 6 deletions(-) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 7619328..7cb4ccd 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -102,8 +102,6 @@ #define CONFIG_SYS_MAX_DDR_BAT_SIZE0x8000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index b0ae25c..a46f7c8 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -141,8 +141,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MAX_DDR_BAT_SIZE0x8000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 2865df5..682d241 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -121,8 +121,6 @@ #define CONFIG_SYS_MAX_DDR_BAT_SIZE0x8000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -- 1.6.5.rc1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mpc83xx: cosmetic comment update relating to SPD EEPROM
commit 6d0f6bcf337c5261c08fabe12982178c2c489d76 did the big rename of CFG_ macros to CONFIG_SYS macros. But it missed a couple of instances within comments. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- include/configs/sbc8349.h |2 +- include/configs/vme8349.h |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index bf7cf82..4dea27d 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -304,7 +304,7 @@ #define CONFIG_SYS_I2C1_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ /* TSEC */ #define CONFIG_SYS_TSEC1_OFFSET 0x24000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index d0690fe..f9db73b 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -224,7 +224,7 @@ #define CONFIG_SYS_I2C1_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ #define CONFIG_SYS_I2C_8574_ADDR2 0x20/* I2C1, PCF8574 */ -- 1.6.5.rc1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mem_mtest: bail out after finding 1st memory error.
Wolfgang Denk wrote: Dear Paul Gortmaker, In message 4ac3c540.9050...@windriver.com you wrote: If you still think it is best to maintain current behaviour and not stop after the 1st error, that is fine, I can do that, but I just wanted to be sure it was clear why I did it this way. I have used the code many times (well, to be honest, not sooo many times, but several times) exactly that way: letting it run forever (or, for a long time), while manipulating the hardware (like using a hair dryer resp. cooling spray on it). In such a situation it is very useful when the code does _not_ terminate after the first error (even is this might have been the intention in earlier versions). Definitely a valid use case. Hopefully one I never have to use personally, mind you. So beause (1) it is the behaviour users might be used to, (2) I see use cases for this and (3) adding a new option will allow to have both beheaviours so anybody can chose what he wants, I think we should do as I suggested. OK. I can do that. What about the CONFIG_ALT_MEMTEST then? Should it be changed to run continuously as well, so at least the two tests are consistent in their default behaviours? Paul. Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mem_mtest: fix error reporting, allow escape with ^C
Mike Frysinger wrote:
On Thursday 01 October 2009 19:52:27 Paul Gortmaker wrote:
if (iteration_limit iterations iteration_limit) {
-printf(Tested %d iteration(s) without errors.\n,
-iterations-1);
+printf(Tested %d iteration(s) with %lu errors.\n,
+iterations-1, errs);
return 0;
if you're showing the errs variable, then presumably it could possibly be non-
zero, so you wouldnt want to return 0 right ?
return !!errs;
char *argv[]) incr = -incr;
}
#endif
-return rcode;
+return 0;
i dont think you want to return 0 all the time here right ?
return !!errs;
Doh! I had it in my mind to return errs!=0; and then forgot.
Thanks, I'll respin and resend tomorrow.
Paul.
otherwise, the basic ^C handling is something that has annoyed me in the
past,
so acked-by for that :)
-mike
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[U-Boot] [PATCH] mem_mtest: bail out after finding 1st memory error.
The basic memtest function tries to watch for ^C after each pattern pass as an escape mechanism, but if things are horribly wrong, we'll be stuck in an inner loop flooding the console with error messages and never check for ^C. To make matters worse, if the user waits for all the error messages to complete, we then incorrectly report the test passed without errors. By inspecting the code, it is clear that the test was originally written with returning after the 1st error in mind (which is what the optional more extensive test does). Making it do this also solves the endless console flood problem if a person tests really bad RAM. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- common/cmd_mem.c |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 9850800..abcd8fd 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -631,7 +631,6 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) vu_long *addr, *start, *end; ulong val; ulong readback; - int rcode = 0; int iterations = 1; int iteration_limit; @@ -923,7 +922,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf (\nMem error @ 0x%08X: found %08lX, expected %08lX\n, (uint)addr, readback, val); - rcode = 1; + return 1; } val += incr; } @@ -943,7 +942,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) incr = -incr; } #endif - return rcode; + return 0; } -- 1.6.5.rc1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sbc8641d: fix LAW so board doesn't hang on DDR init
All versions between now and since this commit:
commit bd76729bcbfd64b5d016a9b936f058931fc06eaf
MPC86xx: set CONFIG_MAX_MEM_MAPPED to 2G by default
will fail to allow the SBC8641D to get past DDR init, because the
LAW config was overlapping. Eventually this board will do SPD
EEPROM config, but for now this gets the board working again.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8641d/law.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
index 760c693..d20fa51 100644
--- a/board/sbc8641d/law.c
+++ b/board/sbc8641d/law.c
@@ -44,14 +44,17 @@
struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x1000,
+LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+#endif
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xf800, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xfe00, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
--
1.6.5.rc1
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Re: [U-Boot] [PATCH] mem_mtest: bail out after finding 1st memory error.
Wolfgang Denk wrote:
Dear Paul Gortmaker,
In message 1254338488-15332-1-git-send-email-paul.gortma...@windriver.com
you wrote:
The basic memtest function tries to watch for ^C after each
pattern pass as an escape mechanism, but if things are horribly
wrong, we'll be stuck in an inner loop flooding the console with
error messages and never check for ^C. To make matters worse,
if the user waits for all the error messages to complete, we
then incorrectly report the test passed without errors.
By inspecting the code, it is clear that the test was originally
written with returning after the 1st error in mind (which is what
the optional more extensive test does). Making it do this also
solves the endless console flood problem if a person tests really
bad RAM.
Please don't change the behaviour, rather fix the problems with it.
If you like, please feel free to add code to bail out after a number
of errors, but that should be optional (for example using an
additional argument on the command line).
I agree in principle, and I'd actually 1st created a patch
that watched for ^C in the inner loop. But the more I looked
at the code, the more I felt that the original intention of
the code was in fact the new behaviour.
For example, the CONFIG_SYS_ALT_MEMTEST contains:
printf (\nFAILURE: );
return 1;
in several places throughout the test. And in the
default test, the code has:
if (iteration_limit iterations iteration_limit) {
printf(Tested %d iteration(s) without errors.\n,
iterations-1);
return 0;
}
i.e. there was never any provision for checking the rcode
variable or counting the errors -- it assumed that if it
ran the full iteration count, then there were no errors.
If you still think it is best to maintain current behaviour
and not stop after the 1st error, that is fine, I can do that,
but I just wanted to be sure it was clear why I did it this
way.
Thanks,
Paul.
Best regards,
Wolfgang Denk
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[U-Boot] [PATCH] sbc8548: reclaim wasted sector in boot flash
By nature of being based off the MPC8548CDS board, this board inherited an ENV_SIZE setting of 256k. But since it has a smaller flash device (8MB soldered on), it has a native sector size of 128k, and hence the ENV_SIZE was causing 2 sectors to be used for the environment. By removing the unused sector, we can push TEXT_BASE up closer to the end of address space and reclaim that sector for any other application. This also fixes the mismatch between TEXT_BASE and MONITOR_LEN reported by Kumar earlier. Since this board also supports the ability to boot off the 64MB SODIMM flash, this change is forward looking with that in mind; i.e. the settings for MONITOR_LEN and ENV_SIZE will work when the 512k sectors of the SODIMM flash are used for alternate boot in the future. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- board/sbc8548/config.mk |2 +- doc/README.sbc8548| 24 include/configs/sbc8548.h | 20 +--- 3 files changed, 42 insertions(+), 4 deletions(-) diff --git a/board/sbc8548/config.mk b/board/sbc8548/config.mk index 440d650..b2013d6 100644 --- a/board/sbc8548/config.mk +++ b/board/sbc8548/config.mk @@ -24,5 +24,5 @@ # sbc8548 board # ifndef TEXT_BASE -TEXT_BASE = 0xfff8 +TEXT_BASE = 0xfffa endif diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index d72d97d..6cbe12f 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -63,6 +63,30 @@ a 33MHz PCI configuration is currently untested.) = +Updating U-boot with U-boot: + + +Note that versions of u-boot up to and including 2009.08 had u-boot stored +at 0xfff8_ - 0x_ (512k). Currently it is being stored from +0xfffa_ - 0x_ (384k). If you use an old macro/script to +update u-boot with u-boot and it uses the old address, you will render +your board inoperable, and you will require JTAG recovery. + +The following steps list how to update with the current address: + + tftp u-boot.bin + md 20 10 + protect off all + erase fffa + cp.b 20 fffa 6 + md fffa 10 + protect on all + +The md steps in the above are just a precautionary step that allow +you to confirm the u-boot version that was downloaded, and then confirm +that it was copied to flash. + + Hardware Reference: === diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index d10792a..aeac2de 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -330,7 +330,14 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +/* + * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and + * one for env+bootpg (TEXT_BASE=0xfffa_, 384kB total). For SODIMM + * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg + * (TEXT_BASE=0xfff0_, 1MB total). This dynamically sets the right + * thing for MONITOR_LEN in both cases. + */ +#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1) #define CONFIG_SYS_MALLOC_LEN (128 * 1024)/* Reserved for malloc */ /* Serial Port */ @@ -448,9 +455,16 @@ * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE + 0x4) -#define CONFIG_ENV_SECT_SIZE 0x4 /* 256K(one sector) for env */ #define CONFIG_ENV_SIZE0x2000 +#if TEXT_BASE == 0xfff0/* Boot from 64MB SODIMM */ +#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE + 0x8) +#define CONFIG_ENV_SECT_SIZE 0x8 /* 512K(one sector) for env */ +#elif TEXT_BASE == 0xfffa /* Boot from 8MB soldered flash */ +#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE + 0x4) +#define CONFIG_ENV_SECT_SIZE 0x2 /* 128K(one sector) for env */ +#else +#warning undefined environment size/location. +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- 1.6.5.rc1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-mpc85xx (updated)
On Thu, Sep 24, 2009 at 5:40 PM, Wolfgang Denk w...@denx.de wrote: Dear Kumar Gala, In message pine.lnx.4.64.0909241206140.30...@localhost.localdomain you wrote: This includes Paul's updates for sbc85xx and p4080 updates.  I have not fixed the immap line issue, but will do that as a follow on patch. - k [...] Paul Gortmaker (13):    sbc8548: replace README with completely new document    sbc8548: enable use of PCI network cards    sbc8548: delete unused MPC8548CDS info carried over from port    sbc8548: get_clock_freq is not valid for this board    sbc8548: cosmetic line re-wrap    sbc8548: enable access to second bank of flash    sbc8548: remove eTSEC3/4 voltage hack    sbc8548: use I/O accessors    sbc8548: correct local bus SDRAM size from 64M to 128M Ummm... I rejected this patch!! I believe that if you check, you will find that the patch that you have got from this pull request from Kumar has the long line issue that you wanted fixed already in it. If there is something else that I should have fixed, but missed then let me know. Thanks, Paul.    fsl_pci: create a SET_STD_PCI_INFO() helper wrapper    sbc8548: update PCI/PCI-e support code    sbc8548: allow enabling PCI via a make config option    sbc85x0: tidy up Makefile to use new configuration script. Peter Tyser (1):    mpc8610hpcd: Use common 86xx fdt fixup code Poonam Aggrwal (1):    ppc/85xx: 32bit DDR changes for P1020/P1011 Vivek Mahajan (1):    85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ  MAKEALL                  |   4 +  Makefile                  |  66 ++-  board/atum8548/law.c            |   2 +-  board/freescale/mpc8536ds/law.c      |   6 +-  board/freescale/mpc8540ads/law.c      |   2 +-  board/freescale/mpc8544ds/law.c      |   6 +-  board/freescale/mpc8560ads/law.c      |   2 +-  board/freescale/mpc8572ds/law.c      |   6 +-  board/freescale/mpc8572ds/mpc8572ds.c   |  230 +++---  board/freescale/mpc8610hpcd/mpc8610hpcd.c |  14 +--  board/freescale/p1_p2_rdb/ddr.c      |  29 +++-  board/freescale/p1_p2_rdb/law.c      |   4 +-  board/freescale/p1_p2_rdb/pci.c      |  42 ++--  board/freescale/p2020ds/law.c       |   6 +-  board/freescale/p2020ds/p2020ds.c     |  150 +++---  board/pm854/law.c             |   2 +-  board/pm856/law.c             |   2 +-  board/sbc8548/Makefile           |   4 +-  board/sbc8548/law.c            |  12 +-  board/sbc8548/sbc8548.c          |  305 ++---  board/sbc8548/tlb.c            |  80 +---  board/socrates/law.c            |   4 +-  board/stx/stxgp3/law.c           |   2 +-  board/stx/stxssa/law.c           |   2 +-  board/xes/xpedite5200/law.c        |   2 +-  cpu/mpc85xx/Makefile            |   1 +  cpu/mpc85xx/cpu.c             |  49 +-  cpu/mpc85xx/cpu_init.c           |  21 ++-  cpu/mpc85xx/cpu_init_early.c        |  72 +--  cpu/mpc85xx/cpu_init_nand.c        |  63 ++  cpu/mpc85xx/fdt.c             |  15 +-  cpu/mpc85xx/mp.c              |  68 ++-  cpu/mpc85xx/release.S           |   3 +-  cpu/mpc85xx/speed.c            |  86  cpu/mpc85xx/u-boot-nand_spl.lds      |  67 +++  cpu/mpc8xxx/cpu.c             |   4 +  doc/README.sbc8548             |  189 --  drivers/misc/fsl_law.c           |  128 +++-  drivers/pci/fsl_pci_init.c         |   2 +-  include/asm-ppc/config.h          |   6 +-  include/asm-ppc/fsl_law.h         |  31 +++  include/asm-ppc/fsl_lbc.h         |  12 ++  include/asm-ppc/fsl_pci.h         |  12 ++  include/asm-ppc/immap_85xx.h        |  289 +--  include/asm-ppc/mmu.h           |   9 +-  include/asm-ppc/processor.h        |   4 +  include/configs/MPC8536DS.h        |   2 +-  include/configs/MPC8572DS.h        |   4 +  include/configs/P1_P2_RDB.h        |  13 ++  include/configs/P2020DS.h         |   4 +  include/configs/SBC8540.h         |  19 +-  include/configs/XPEDITE5170.h       |   2 +-  include/configs/XPEDITE5200.h       |   2 +-  include/configs/XPEDITE5370.h       |   2 +-  include/configs/sbc8548.h         |  147 ++-  include/configs/sbc8560.h         |  17 ++-  include/e500.h               |   6 +  57 files changed, 1559 insertions(+), 774 deletions(-)  create mode 100644 cpu/mpc85xx/cpu_init_nand.c  create mode 100644 cpu/mpc85xx/u-boot-nand_spl.lds Applied
Re: [U-Boot] [PATCH 3/8] sbc8548: enable access to second bank of flash
Wolfgang Denk wrote: Dear Kumar Gala, In message 47177dab-3638-4978-bd72-78629adcd...@kernel.crashing.org you wrote: On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote: ... applied to 85xx. Argh... So how much time do you allow for code reviews? I ask you to wait at least 3...5 working days, please. Please undo, this needs fixing. I'd considered the line length, but there were many lines in tlb.c that were already way past 80 char (see directly under the comment/* TLB 0 - for temp stack in cache */ ) so I decided to be consistent with existing code. If you prefer, I can create an add-on patch that re-wraps both the old/existing code, and the updated line(s). Let me know what you would prefer. Paul. Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/8] sbc8548: update PCI/PCI-e support code
Wolfgang Denk wrote: Dear Paul Gortmaker, In message 7d1e5723fdd2d2e1cf51559f876edf17ae8e7a46.1253315004.git.paul.gortma...@windriver.com you wrote: The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match current MPC85xxCDS/MDS PCI-e support. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_ (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) ... diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 1db32ec..0387140 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c ... @@ -400,6 +400,7 @@ pci_init_board(void) struct pci_controller *hose = pcie1_hose; struct pci_region *r = hose-regions; +uint io_sel = (gur-pordevsr MPC85xx_PORDEVSR_IO_SEL) 19; Please use I/O accessors. Check globally, please. Already done - commit 48539e37c38c4f6ff78aba6134de2ae3cc3b5dab in the 85xx tree does a global sweep of the board file, and commit ac2cb674bd5dd1405ea0413adb71c253481d9a00 (also in 85xx) is an updated version of this commit that uses the I/O accessors, and also the new PCI helper functions that Kumar requested. Thanks, Paul. Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/8] sbc8548: enable access to second bank of flash
[Re: [U-Boot] [PATCH 3/8] sbc8548: enable access to second bank of flash] On 23/09/2009 (Wed 22:48) Wolfgang Denk wrote: Dear Paul Gortmaker, In message 4aba81da.8020...@windriver.com you wrote: I'd considered the line length, but there were many lines in tlb.c that were already way past 80 char (see directly under the comment/* TLB 0 - for temp stack in cache */ ) so I decided to be consistent with existing code. I see. If you prefer, I can create an add-on patch that re-wraps both the old/existing code, and the updated line(s). It would be better to fix the existing code in an initial patch, and then apply an update patch. To do this, I've rewound my copy of the 85xx repo to just before the 1st offending patch, inserted the cosmetic line wrap patch, and then re-applied all the remaining 85xx updates that I was responsible for. The patches are all unchanged, with the exception of re-wrapping any long lines in tlb.c -- which impacted the patches marked with a * I hope this what you had in mind. If not, or if you want patches in e-mail then let me know. Thanks, Paul. --- The following changes since commit 80f0cc6009a7bfdbb1458fcd50c4592badd33f83: Paul Gortmaker (1): sbc8548: get_clock_freq is not valid for this board are available in the git repository at: git://openlinux.windriver.com/people/paulg/u-boot wd-sbc8548 Paul Gortmaker (9): sbc8548: cosmetic line re-wrap * sbc8548: enable access to second bank of flash sbc8548: remove eTSEC3/4 voltage hack sbc8548: use I/O accessors * sbc8548: correct local bus SDRAM size from 64M to 128M fsl_pci: create a SET_STD_PCI_INFO() helper wrapper * sbc8548: update PCI/PCI-e support code sbc8548: allow enabling PCI via a make config option sbc85x0: tidy up Makefile to use new configuration script. MAKEALL |4 + Makefile | 26 ++ board/sbc8548/law.c | 12 ++- board/sbc8548/sbc8548.c | 234 +--- board/sbc8548/tlb.c | 80 ++- include/asm-ppc/fsl_pci.h | 12 +++ include/configs/SBC8540.h | 19 ++-- include/configs/sbc8548.h | 137 +++--- include/configs/sbc8560.h | 17 +++- 9 files changed, 300 insertions(+), 241 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/13] ppc: Remove pci config table pointer relocation fixups
On Mon, Sep 21, 2009 at 12:20 PM, Peter Tyser pty...@xes-inc.com wrote:
Signed-off-by: Peter Tyser pty...@xes-inc.com
It looks like something happened during the send of your patches;
it seems the long log of what you are trying to fix and how the patch
fixes it is missing here and from several of the other patches
as well.
---
 board/freescale/mpc8548cds/mpc8548cds.c |   7 ---
 board/mpl/common/pci.c          |  18 --
 board/sbc8548/sbc8548.c         |   6 --
 3 files changed, 0 insertions(+), 31 deletions(-)
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c
b/board/freescale/mpc8548cds/mpc8548cds.c
index 80de6f8..73e7c21 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -276,7 +276,6 @@ pci_init_board(void)
 {
    volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
    struct pci_controller *hose = pci1_hose;
- Â Â Â struct pci_config_table *table;
    struct pci_region *r = hose-regions;
    uint pci_32 = gur-pordevsr MPC85xx_PORDEVSR_PCI1_PCI32;    /*
PORDEVSR[15] */
@@ -312,12 +311,6 @@ pci_init_board(void)
               PCI_REGION_IO);
        hose-region_count = r - hose-regions;
- Â Â Â Â Â Â Â /* relocate config table pointers */
- Â Â Â Â Â Â Â hose-config_table = \
- Â Â Â Â Â Â Â Â Â Â Â (struct pci_config_table *)((uint)hose-config_table
+ gd-reloc_off);
- Â Â Â Â Â Â Â for (table = hose-config_table; table table-vendor;
table++)
- Â Â Â Â Â Â Â Â Â Â Â table-config_device += gd-reloc_off;
For the mpc8548cds, if this removal was somehow the right thing to do,
it would still be incomplete; I am sure that there is a dummy function
related to a PCI bridge quirk associated with the above change that
would now be orphaned in the code.
-
        hose-first_busno=first_free_busno;
        fsl_pci_init(hose, (u32)pci-cfg_addr, (u32)pci-cfg_data);
[...]
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index e5b21b5..5cdfef4 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -392,12 +392,6 @@ pci_init_board(void)
               PCI_REGION_IO);
        hose-region_count = r - hose-regions;
- Â Â Â Â Â Â Â /* relocate config table pointers */
- Â Â Â Â Â Â Â hose-config_table = \
- Â Â Â Â Â Â Â Â Â Â Â (struct pci_config_table *)((uint)hose-config_table
+ gd-reloc_off);
- Â Â Â Â Â Â Â for (table = hose-config_table; table table-vendor;
table++)
- Â Â Â Â Â Â Â Â Â Â Â table-config_device += gd-reloc_off;
This code is already gone from the sbc8548 in the 85xx branch;
the sbc8548 didn't need the bridge quirk fixup.
Paul.
-
        hose-first_busno=first_free_busno;
        fsl_pci_init(hose, (u32)pci-cfg_addr, (u32)pci-cfg_data);
--
1.6.2.1
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Re: [U-Boot] [PATCH 04/13] ppc: Remove pci config table pointer relocation fixups
Peter Tyser wrote:
On Mon, 2009-09-21 at 12:49 -0400, Paul Gortmaker wrote:
On Mon, Sep 21, 2009 at 12:20 PM, Peter Tyser pty...@xes-inc.com wrote:
Signed-off-by: Peter Tyser pty...@xes-inc.com
It looks like something happened during the send of your patches;
it seems the long log of what you are trying to fix and how the patch
fixes it is missing here and from several of the other patches
as well.
I didn't put long log messages in patches which I thought would be clear
what was changing. All the Remove XYZ relocation fixups are intended
to only remove no longer needed fixups. They shouldn't (hopefully) have
any functional change. I can add log messages, but they will all be the
same don't fixup xyz as relocation now works.
I guess even something as basic as that would be better than
nothing in my opinion. Folks rummaging through history won't
have the benefit of your [0/13] description when they are
looking through the change history with git.
---
board/freescale/mpc8548cds/mpc8548cds.c |7 ---
board/mpl/common/pci.c | 18 --
board/sbc8548/sbc8548.c |6 --
3 files changed, 0 insertions(+), 31 deletions(-)
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c
b/board/freescale/mpc8548cds/mpc8548cds.c
index 80de6f8..73e7c21 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -276,7 +276,6 @@ pci_init_board(void)
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)
CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = pci1_hose;
- struct pci_config_table *table;
struct pci_region *r = hose-regions;
uint pci_32 = gur-pordevsr MPC85xx_PORDEVSR_PCI1_PCI32; /*
PORDEVSR[15] */
@@ -312,12 +311,6 @@ pci_init_board(void)
PCI_REGION_IO);
hose-region_count = r - hose-regions;
- /* relocate config table pointers */
- hose-config_table = \
- (struct pci_config_table
*)((uint)hose-config_table + gd-reloc_off);
- for (table = hose-config_table; table table-vendor;
table++)
- table-config_device += gd-reloc_off;
For the mpc8548cds, if this removal was somehow the right thing to do,
it would still be incomplete; I am sure that there is a dummy function
related to a PCI bridge quirk associated with the above change that
would now be orphaned in the code.
I didn't intend to make any functional change as I know nothing about
this board:) I only intended to remove the references to gd-reloc_off.
I looked over this code quickly and came to the conclusion I wasn't
changing any functionality, let me know if I'm missing something.
OK, I just went and looked, and I think that you are correct.
The config_table with the dummy function is still hooked in via
the static pci1_hose initialization; sorry for the noise.
-
hose-first_busno=first_free_busno;
fsl_pci_init(hose, (u32)pci-cfg_addr, (u32)pci-cfg_data);
[...]
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index e5b21b5..5cdfef4 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -392,12 +392,6 @@ pci_init_board(void)
PCI_REGION_IO);
hose-region_count = r - hose-regions;
- /* relocate config table pointers */
- hose-config_table = \
- (struct pci_config_table
*)((uint)hose-config_table + gd-reloc_off);
- for (table = hose-config_table; table table-vendor;
table++)
- table-config_device += gd-reloc_off;
This code is already gone from the sbc8548 in the 85xx branch;
the sbc8548 didn't need the bridge quirk fixup.
Thanks for the heads up. Maybe git will gracefully handle this change?
Depends on your definition of gracefully, I guess. :-)
If not, I'd prefer to wait till Wolfgang attempts to merge this patch as
other things may be merged between now and then and I'd rather just send
1 cleanup patch series.
Makes sense.
Paul.
Best,
Peter
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[U-Boot] [PATCH] sbc85x0: tidy up Makefile to use new configuration script.
Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the boards config header. This takes advantage of that for the sbc8540/sbc8560 boards. There were a couple of cheezy comments pointing at incorrect files, or files that don't exist, so I've cleaned those up too. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- For 85xx tree; since it contains sbc8548 commits which this diff has context of one of those commit changes to Makefile Makefile | 18 ++ include/configs/SBC8540.h | 19 +++ include/configs/sbc8560.h | 17 - 3 files changed, 25 insertions(+), 29 deletions(-) diff --git a/Makefile b/Makefile index 55ee25d..9c5b2a5 100644 --- a/Makefile +++ b/Makefile @@ -2535,14 +2535,7 @@ PM856_config:unconfig sbc8540_config \ sbc8540_33_config \ sbc8540_66_config: unconfig - @mkdir -p $(obj)include - @if [ $(findstring _66_,$@) ] ; then \ - echo #define CONFIG_PCI_66$(obj)include/config.h ; \ - $(XECHO) ... 66 MHz PCI ; \ - else \ - $(XECHO) ... 33 MHz PCI ; \ - fi - @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 + @$(MKCONFIG) -t $(@:_config=) SBC8540 ppc mpc85xx sbc8560 sbc8548_config \ sbc8548_PCI_33_config \ @@ -2554,14 +2547,7 @@ sbc8548_PCI_66_PCIE_config: unconfig sbc8560_config \ sbc8560_33_config \ sbc8560_66_config: unconfig - @mkdir -p $(obj)include - @if [ $(findstring _66_,$@) ] ; then \ - echo #define CONFIG_PCI_66$(obj)include/config.h ; \ - $(XECHO) ... 66 MHz PCI ; \ - else \ - $(XECHO) ... 33 MHz PCI ; \ - fi - @$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560 + @$(MKCONFIG) -t $(@:_config=) sbc8560 ppc mpc85xx sbc8560 socrates_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 7239f84..198dece 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -24,22 +24,25 @@ * MA 02111-1307 USA */ -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * sbc8540 board configuration file. */ #ifndef __CONFIG_H #define __CONFIG_H -#if XXX -#define DEBUG/* General debug */ -#define ET_DEBUG +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_66 +#define CONFIG_PCI_66 #endif + #define TSEC_DEBUG -/* High Level Configuration Options */ +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE*/ #define CONFIG_E5001 /* BOOKE e500 family*/ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 4fa501d..7c1d7a6 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -24,16 +24,23 @@ * MA 02111-1307 USA */ -/* sbc8560 board configuration file */ -/* please refer to doc/README.sbc8560 for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * sbc8560 board configuration file. */ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_66 +#define CONFIG_PCI_66 +#endif + +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE*/ #define CONFIG_E5001 /* BOOKE e500 family*/ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -- 1.6.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sbc8349: tidy up Makefile to use new configuration script.
Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the board config header. This takes advantage of that for the sbc8349 board. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- Makefile | 15 +-- include/configs/sbc8349.h | 15 +++ 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/Makefile b/Makefile index 0b61d05..b90be69 100644 --- a/Makefile +++ b/Makefile @@ -2403,20 +2403,7 @@ MVBLM7_config: unconfig sbc8349_config \ sbc8349_PCI_33_config \ sbc8349_PCI_66_config: unconfig - @mkdir -p $(obj)include - @if [ $(findstring _PCI_,$@) ] ; then \ - $(XECHO) -n ... PCI HOST at ; \ - echo #define CONFIG_PCI $(obj)include/config.h ; \ - fi ; \ - if [ $(findstring _33_,$@) ] ; then \ - $(XECHO) -n 33MHz... ; \ - echo #define PCI_33M $(obj)include/config.h ; \ - fi ; \ - if [ $(findstring _66_,$@) ] ; then \ - $(XECHO) -n 66MHz... ; \ - echo #define PCI_66M $(obj)include/config.h ; \ - fi ; - @$(MKCONFIG) -a sbc8349 ppc mpc83xx sbc8349 + @$(MKCONFIG) -t $(@:_config=) sbc8349 ppc mpc83xx sbc8349 SIMPC8313_LP_config \ SIMPC8313_SP_config: unconfig diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e961bb3..6f574ca 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -32,6 +32,21 @@ #define __CONFIG_H /* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_PCI +#define CONFIG_PCI +#endif + +#ifdef CONFIG_MK_66 +#define PCI_66M +#endif + +#ifdef CONFIG_MK_33 +#define PCI_33M +#endif + +/* * High Level Configuration Options */ #define CONFIG_E3001 /* E300 Family */ -- 1.6.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] fsl_pci: create a SET_STD_PCI_INFO() helper wrapper
Recycle the recently added PCI-e wrapper used to reduce board
duplication of code by creating a similar version for plain PCI.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
include/asm-ppc/fsl_pci.h | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h
index b9972da..2790da7 100644
--- a/include/asm-ppc/fsl_pci.h
+++ b/include/asm-ppc/fsl_pci.h
@@ -173,6 +173,18 @@ struct fsl_pci_info {
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno);
+#define SET_STD_PCI_INFO(x, num) \
+{ \
+ x.regs = CONFIG_SYS_PCI##num##_ADDR;\
+ x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
+ x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
+ x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
+ x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
+ x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
+ x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+ x.pci_num = num; \
+}
+
#define SET_STD_PCIE_INFO(x, num) \
{ \
x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
--
1.6.4.1
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[U-Boot] [PATCH 5/6] sbc8548: update PCI/PCI-e support code
The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile. This re-syncs it to match
the latest codebase and makes use of the new shared PCI functions
to reduce board duplication.
It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_ (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.
Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/law.c | 12 -
board/sbc8548/sbc8548.c | 129 ++---
board/sbc8548/tlb.c | 48 +++-
include/configs/sbc8548.h | 45 ---
4 files changed, 94 insertions(+), 140 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index e8c7ae2..6d1efc0 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -32,8 +32,10 @@
*
* 0x_ 0x0fff_ DDR 256M
* 0x8000_ 0x9fff_ PCI1 MEM512M
+ * 0xa000_ 0xbfff_ PCIe MEM512M
* 0xe000_ 0xe000_ CCSR1M
- * 0xe200_ 0xe2ff_ PCI1 IO 16M
+ * 0xe200_ 0xe27f_ PCI1 IO 8M
+ * 0xe280_ 0xe2ff_ PCIe IO 8M
* 0xf000_ 0xf7ff_ SDRAM 128M
* 0xf8b0_ 0xf80f_ EEPROM 1M
* 0xfb80_ 0xff7f_ FLASH (2nd bank)64M
@@ -48,8 +50,14 @@ struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
+#endif
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
/* LBC window - maps 256M 0xf000 - 0x */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index f4bfd92..194f6ab 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -321,125 +321,74 @@ static struct pci_controller pci1_hose;
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
-int first_free_busno=0;
+#ifdef CONFIG_PCI
void
pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info[2];
+ u32 devdisr, pordevsr, porpllsr, io_sel;
+ int first_free_busno = 0;
+ int num = 0;
-#ifdef CONFIG_PCI1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = pci1_hose;
- struct pci_region *r = hose-regions;
+#ifdef CONFIG_PCIE1
+ int pcie_configured;
+#endif
- uint pci_32 = gur-pordevsr MPC85xx_PORDEVSR_PCI1_PCI32; /*
PORDEVSR[15] */
- uint pci_arb = gur-pordevsr MPC85xx_PORDEVSR_PCI1_ARB; /*
PORDEVSR[14] */
- uint pci_clk_sel = gur-porpllsr MPC85xx_PORDEVSR_PCI1_SPD; /*
PORPLLSR[16] */
+ devdisr = in_be32(gur-devdisr);
+ pordevsr = in_be32(gur-pordevsr);
+ porpllsr = in_be32(gur-porpllsr);
+ io_sel = (pordevsr MPC85xx_PORDEVSR_IO_SEL) 19;
- uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
+ debug( pci_init_board: devdisr=%x, io_sel=%x\n, devdisr, io_sel);
+
+#ifdef CONFIG_PCI1
+ if (!(devdisr MPC85xx_DEVDISR_PCI1)) {
+ uint pci_32 = pordevsr MPC85xx_PORDEVSR_PCI1_PCI32;
+ uint pci_arb = pordevsr MPC85xx_PORDEVSR_PCI1_ARB;
+ uint pci_clk_sel = porpllsr MPC85xx_PORDEVSR_PCI1_SPD;
+ uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
- if (!(gur-devdisr MPC85xx_DEVDISR_PCI1)) {
printf (PCI host: %d bit, %s MHz, %s, %s\n,
(pci_32) ? 32 : 64,
(pci_speed == 3300) ? 33 :
(pci_speed == 6600) ? 66 : unknown,
pci_clk_sel ? sync : async,
- pci_arb ? arbiter : external-arbiter
- );
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound
[U-Boot] [PATCH 6/6] sbc8548: allow enabling PCI via a make config option
Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CONFIG_SYS_NS16550_CLK too, which was
not real user friendly,
This adds the typical PCI and clock speed make targets to the
toplevel Makefile in accordance with what is being done with
other boards (i.e. using the -t to mkconfig).
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
MAKEALL |4
Makefile |8 ++--
include/configs/sbc8548.h | 43 +--
3 files changed, 43 insertions(+), 12 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 1d50c34..b394adb 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -399,6 +399,10 @@ LIST_85xx=\
PM856 \
sbc8540 \
sbc8548 \
+ sbc8548_PCI_33 \
+ sbc8548_PCI_66 \
+ sbc8548_PCI_33_PCIE \
+ sbc8548_PCI_66_PCIE \
sbc8560 \
socrates\
stxgp3 \
diff --git a/Makefile b/Makefile
index d8daa89..55ee25d 100644
--- a/Makefile
+++ b/Makefile
@@ -2544,8 +2544,12 @@ sbc8540_66_config: unconfig
fi
@$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
-sbc8548_config:unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548
+sbc8548_config \
+sbc8548_PCI_33_config \
+sbc8548_PCI_66_config \
+sbc8548_PCI_33_PCIE_config \
+sbc8548_PCI_66_PCIE_config: unconfig
+ @$(MKCONFIG) -t $(@:_config=) sbc8548 ppc mpc85xx sbc8548
sbc8560_config \
sbc8560_33_config \
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 4ef3028..cfb743f 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007 Wind River Systems www.windriver.com
+ * Copyright 2007,2009 Wind River Systems www.windriver.com
* Copyright 2007 Embedded Specialties, Inc.
* Copyright 2004, 2007 Freescale Semiconductor.
*
@@ -24,23 +24,40 @@
/*
* sbc8548 board configuration file
- *
- * Please refer to doc/README.sbc85xx for more info.
- *
+ * Please refer to doc/README.sbc8548 for more info.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_MK_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI1
+#endif
+
+#ifdef CONFIG_MK_66
+#define CONFIG_SYS_CLK_DIV 1
+#endif
+
+#ifdef CONFIG_MK_33
+#define CONFIG_SYS_CLK_DIV 2
+#endif
+
+#ifdef CONFIG_MK_PCIE
+#define CONFIG_PCIE1
+#endif
+
+/*
+ * High Level Configuration Options
+ */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E5001 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
-#undef CONFIG_PCI /* enable any pci type devices */
-#undef CONFIG_PCI1 /* PCI controller 1 */
-#undef CONFIG_PCIE1/* PCIE controler 1 (slot 1) */
#undef CONFIG_RIO
#ifdef CONFIG_PCI
@@ -58,7 +75,13 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_SYS_CLK_FREQ6600 /* SBC8548 default SYSCLK */
+/*
+ * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
+ */
+#ifndef CONFIG_SYS_CLK_DIV
+#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
+#endif
+#define CONFIG_SYS_CLK_FREQ(6600 / CONFIG_SYS_CLK_DIV)
/*
* These can be toggled for performance analysis, otherwise use default.
@@ -315,7 +338,7 @@
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE1
-#define CONFIG_SYS_NS16550_CLK 4 /* get_bus_freq(0) */
+#define CONFIG_SYS_NS16550_CLK (4 / CONFIG_SYS_CLK_DIV)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
--
1.6.4.1
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[U-Boot] [PATCH 3/6] sbc8548: use I/O accessors
Sweep throught the board specific file and replace the various
register proddings with the equivalent I/O accessors.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/sbc8548.c | 91 +++
1 files changed, 45 insertions(+), 46 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 96a5f42..ce998e1 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -56,15 +56,15 @@ int checkboard (void)
volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
printf (Board: Wind River SBC8548 Rev. 0x%01x\n,
- (*rev) 4);
+ in_8(rev) 4);
/*
* Initialize local bus.
*/
local_bus_init ();
- ecm-eedr = 0x; /* clear ecm errors */
- ecm-eeer = 0x; /* enable ecm errors */
+ out_be32(ecm-eedr, 0x); /* clear ecm errors */
+ out_be32(ecm-eeer, 0x); /* enable ecm errors */
return 0;
}
@@ -86,7 +86,7 @@ initdram(int board_type)
volatile ccsr_gur_t *gur = (void
*)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gur-ddrdllcr = 0x8100;
+ out_be32(gur-ddrdllcr, 0x8100);
asm(sync;isync;msync);
udelay(200);
}
@@ -123,24 +123,24 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(sysinfo);
- clkdiv = (lbc-lcrr LCRR_CLKDIV) * 2;
+ clkdiv = (in_be32(lbc-lcrr) LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 100 / clkdiv;
- gur-lbiuiplldcr1 = 0x00078080;
+ out_be32(gur-lbiuiplldcr1, 0x00078080);
if (clkdiv == 16) {
- gur-lbiuiplldcr0 = 0x7c0f1bf0;
+ out_be32(gur-lbiuiplldcr0, 0x7c0f1bf0);
} else if (clkdiv == 8) {
- gur-lbiuiplldcr0 = 0x6c0f1bf0;
+ out_be32(gur-lbiuiplldcr0, 0x6c0f1bf0);
} else if (clkdiv == 4) {
- gur-lbiuiplldcr0 = 0x5c0f1bf0;
+ out_be32(gur-lbiuiplldcr0, 0x5c0f1bf0);
}
- lbc-lcrr |= 0x0003;
+ setbits_be32(lbc-lcrr, 0x0003);
asm(sync;isync;msync);
- lbc-ltesr = 0x;/* Clear LBC error interrupts */
- lbc-lteir = 0x;/* Enable LBC error interrupts */
+ out_be32(lbc-ltesr, 0x); /* Clear LBC error IRQs */
+ out_be32(lbc-lteir, 0x); /* Enable LBC error IRQs */
}
/*
@@ -163,18 +163,18 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
- lbc-or3 = CONFIG_SYS_OR3_PRELIM;
+ out_be32(lbc-or3, CONFIG_SYS_OR3_PRELIM);
asm(msync);
- lbc-br3 = CONFIG_SYS_BR3_PRELIM;
+ out_be32(lbc-br3, CONFIG_SYS_BR3_PRELIM);
asm(msync);
- lbc-lbcr = CONFIG_SYS_LBC_LBCR;
+ out_be32(lbc-lbcr, CONFIG_SYS_LBC_LBCR);
asm(msync);
- lbc-lsrt = CONFIG_SYS_LBC_LSRT;
- lbc-mrtpr = CONFIG_SYS_LBC_MRTPR;
+ out_be32(lbc-lsrt, CONFIG_SYS_LBC_LSRT);
+ out_be32(lbc-mrtpr, CONFIG_SYS_LBC_MRTPR);
asm(msync);
/*
@@ -186,7 +186,7 @@ sdram_init(void)
/*
* Issue PRECHARGE ALL command.
*/
- lbc-lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+ out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -196,7 +196,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx 8; idx++) {
- lbc-lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+ out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -206,7 +206,7 @@ sdram_init(void)
/*
* Issue 8 MODE-set command.
*/
- lbc-lsdmr = lsdmr_common | LSDMR_OP_MRW;
+ out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_MRW);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -215,7 +215,7 @@ sdram_init(void)
/*
* Issue NORMAL OP command.
*/
- lbc-lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+ out_be32(lbc-lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
asm(sync;msync);
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -263,45 +263,44 @@ testdram(void)
}
#endif
-#if!defined(CONFIG_SPD_EEPROM)
+#if !defined(CONFIG_SPD_EEPROM)
+#define CONFIG_SYS_DDR_CONTROL 0xc300c000
/*
* fixed_sdram init -- doesn't use serial presence detect.
* assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
/
long int
[U-Boot] [PATCH 4/6] sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/sbc8548.c |8 +++-
board/sbc8548/tlb.c | 22 +++---
include/configs/sbc8548.h | 42 ++
3 files changed, 60 insertions(+), 12 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index ce998e1..f4bfd92 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -149,7 +149,7 @@ local_bus_init(void)
void
sdram_init(void)
{
-#if defined(CONFIG_SYS_OR3_PRELIM) defined(CONFIG_SYS_BR3_PRELIM)
+#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@@ -169,6 +169,12 @@ sdram_init(void)
out_be32(lbc-br3, CONFIG_SYS_BR3_PRELIM);
asm(msync);
+ out_be32(lbc-or4, CONFIG_SYS_OR4_PRELIM);
+ asm(msync);
+
+ out_be32(lbc-br4, CONFIG_SYS_BR4_PRELIM);
+ asm(msync);
+
out_be32(lbc-lbcr, CONFIG_SYS_LBC_LBCR);
asm(msync);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index dbb9ba8..e173245 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -88,14 +88,22 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 5: 64M Cacheable, non-guarded
-* 0xf000 64M LBC SDRAM
+* 0xf000 64M LBC SDRAM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_64M, 1),
/*
-* TLB 6: 16M Cacheable, non-guarded
+* TLB 6: 64M Cacheable, non-guarded
+* 0xf400 64M LBC SDRAM Second half
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x400,
CONFIG_SYS_LBC_SDRAM_BASE + 0x400,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+
+ /*
+* TLB 7: 16M Cacheable, non-guarded
* 0xf800 1M 7-segment LED display
* 0xf810 1M User switches
* 0xf830 1M Board revision
@@ -103,23 +111,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
+ 0, 7, BOOKE_PAGESZ_16M, 1),
/*
-* TLB 7: 4M Non-cacheable, guarded
+* TLB 8: 4M Non-cacheable, guarded
* 0xfb80 4M 1st 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4M, 1),
+ 0, 8, BOOKE_PAGESZ_4M, 1),
/*
-* TLB 8: 4M Non-cacheable, guarded
+* TLB 9: 4M Non-cacheable, guarded
* 0xfbc0 4M 2nd 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x40, CONFIG_SYS_ALT_FLASH
+ 0x40,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4M, 1),
+ 0, 9, BOOKE_PAGESZ_4M, 1),
};
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 8edba20..4751013 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -196,13 +196,13 @@
#define CONFIG_SYS_EEPROM_BASE 0xf8b0
/*
- * SDRAM on the Local Bus
+ * SDRAM on the Local Bus (CS3 and CS4)
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
/*
- * Base Register 3 and Option Register 3 configure SDRAM.
+ * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf000.
*
* For BR3, need:
@@ -220,7 +220,7 @@
#define CONFIG_SYS_BR3_PRELIM 0xf0001861
/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR3, need:
*64MB mask for AM, OR3[0:7] = 1100
@@ -235,6 +235,40 @@
#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
+/*
+ * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
+ * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf400.
+ *
+ * For BR4, need:
+ *Base address
[U-Boot] [PATCH 0/6] sbc8548 update; remaining bits for 85xx tree.
This is the remaining bits that weren't merged to 85xx, with the the requested fixes of course. Those being: sbc8548: correct local bus SDRAM size from 64M to 128M -now uses I/O accesors on BR4/OR4 sbc8548: update PCI/PCI-e support code -redone to make use of the code de-duplification effort. sbc8548: allow enabling PCI via a make config option -uses the -t to de-clutter the toplevel Makefile New patches are as follows: fsl_pci: create a SET_STD_PCI_INFO() helper wrapper -I believe this was meant to be created, but wasn't. sbc8548: use I/O accessors -uses the I/O accessors through the whole board file. sbc8548: remove eTSEC3/4 voltage hack -noticed this while doing above; sbc doesn't need it. Board still seems happy; I only noticed one cosmetic thing, that the new fsl_pci_init_port() prints PCIE always; even when the port is PCI and not PCI-e (see below). Thanks, Paul. U-Boot 2009.08-06732-g70c5c3d (Sep 20 2009 - 20:11:42) CPU: 8548E, Version: 2.0, (0x80390020) Core: E500, Version: 2.0, (0x80210020) Clock Configuration: CPU0:990 MHz, CCB:396 MHz, DDR:198 MHz (396 MT/s data rate), LBC:99 MHz L1:D-cache 32 kB enabled I-cache 32 kB enabled Board: Wind River SBC8548 Rev. 0x2 I2C: ready DRAM: Initializing SDRAM: 128 MB DDR: 256 MB FLASH: 72 MB L2:512 KB enabled PCI host: 64 bit, 66 MHz, sync, arbiter Scanning PCI bus 00 00 01 8086 1026 0200 00 PCIE1 on bus 00 - 00 PCIE at base address e000a000 Scanning PCI bus 02 02 00 1148 9e00 0200 00 PCIE1 on bus 01 - 02 In:serial Out: serial Err: serial Net: eTSEC0, eTSEC1 = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8] sbc8548: get_clock_freq is not valid for this board
The get_clock_freq() comes from freescale/common/cadmus.c and is
only valid for the CDS based 85xx reference platforms. It would
be nice if we could read the 33 vs. 66MHz status somehow, but in
the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other
non-CDS boards do.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/sbc8548.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index f4fd204..3104d37 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -336,13 +336,13 @@ pci_init_board(void)
uint pci_arb = gur-pordevsr MPC85xx_PORDEVSR_PCI1_ARB; /*
PORDEVSR[14] */
uint pci_clk_sel = gur-porpllsr MPC85xx_PORDEVSR_PCI1_SPD; /*
PORPLLSR[16] */
- uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+ uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
if (!(gur-devdisr MPC85xx_DEVDISR_PCI1)) {
printf (PCI host: %d bit, %s MHz, %s, %s\n,
(pci_32) ? 32 : 64,
- (pci_speed == 3000) ? 33 :
- (pci_speed == 6000) ? 66 : unknown,
+ (pci_speed == 3300) ? 33 :
+ (pci_speed == 6600) ? 66 : unknown,
pci_clk_sel ? sync : async,
pci_arb ? arbiter : external-arbiter
);
--
1.6.4.1
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[U-Boot] [PATCH 0/8] Update/enhance sbc8548 support
This series represents a significant usability improvement to the sbc8548 board, by delivering: -64MB SODIMM flash now usable from u-boot -PCI and PCI-e properly configured and functional -twice the size of LBC SDRAM available -easy selection of configuration via Makefile target rules -a README file that sucks less. I've also cleaned up a bunch of stuff that was left over from when this board support was cloned off of the MPC8548CDS. There are still a couple things I'd like to get working on this board, like DDR config via SPD, and booting from the alternate flash bank (for ease of recovery), but what is here now is validated and complete, so no point in me sitting on these bits. Patches are in e-mail for review, or can be pulled as per below. Thanks, Paul. The following changes since commit 15fba3279b56333bdb65ead366f82c945ed320d1: Kumar Gala (1): ppc/85xx: Disable all async interrupt sources when we boot are available in the git repository at: git://openlinux.windriver.com/people/paulg/u-boot sbc8548 Paul Gortmaker (8): sbc8548: delete unused MPC8548CDS info carried over from port sbc8548: get_clock_freq is not valid for this board sbc8548: enable access to second bank of flash sbc8548: correct local bus SDRAM size from 64M to 128M sbc8548: update PCI/PCI-e support code sbc8548: enable use of PCI network cards sbc8548: allow enabling PCI via a make config option sbc8548: replace README with completely new document MAKEALL |4 + Makefile | 26 ++- board/sbc8548/Makefile|4 +- board/sbc8548/law.c | 12 +++- board/sbc8548/sbc8548.c | 98 board/sbc8548/tlb.c | 64 ++- doc/README.sbc8548| 189 - include/configs/sbc8548.h | 114 +-- 8 files changed, 356 insertions(+), 155 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 7/8] sbc8548: allow enabling PCI via a make config option
Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CONFIG_SYS_NS16550_CLK too, which was
not real user friendly,
This adds the typical PCI and clock speed make targets to the
toplevel Makefile in accordance with what is being done with
other boards.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
MAKEALL |4
Makefile | 26 --
include/configs/sbc8548.h | 13 -
3 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 1d50c34..b394adb 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -399,6 +399,10 @@ LIST_85xx=\
PM856 \
sbc8540 \
sbc8548 \
+ sbc8548_PCI_33 \
+ sbc8548_PCI_66 \
+ sbc8548_PCI_33_PCIE \
+ sbc8548_PCI_66_PCIE \
sbc8560 \
socrates\
stxgp3 \
diff --git a/Makefile b/Makefile
index 0b61d05..28b20af 100644
--- a/Makefile
+++ b/Makefile
@@ -2570,8 +2570,30 @@ sbc8540_66_config: unconfig
fi
@$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
-sbc8548_config:unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548
+sbc8548_config \
+sbc8548_PCI_33_config \
+sbc8548_PCI_66_config \
+sbc8548_PCI_33_PCIE_config \
+sbc8548_PCI_66_PCIE_config: unconfig
+ @mkdir -p $(obj)include
+ @if [ $(findstring _PCI_,$@) ] ; then \
+ $(XECHO) -n ... PCI HOST at ; \
+ echo #define CONFIG_PCI $(obj)include/config.h ; \
+ echo #define CONFIG_PCI1 $(obj)include/config.h ; \
+ fi ; \
+ if [ $(findstring _33_,$@) ] ; then \
+ $(XECHO) -n 33MHz ... ; \
+ echo #define CONFIG_SYS_CLK_DIV 2 $(obj)include/config.h ; \
+ fi ; \
+ if [ $(findstring _66_,$@) ] ; then \
+ $(XECHO) -n 66MHz ; \
+ echo #define CONFIG_SYS_CLK_DIV 1 $(obj)include/config.h ; \
+ fi ; \
+ if [ $(findstring _PCIE_,$@) ] ; then \
+ $(XECHO) -n with PCI-e ... ; \
+ echo #define CONFIG_PCIE1 $(obj)include/config.h ; \
+ fi
+ @$(MKCONFIG) -a sbc8548 ppc mpc85xx sbc8548
sbc8560_config \
sbc8560_33_config \
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index e77e9e9..8eb5b4c 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -38,9 +38,6 @@
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
-#undef CONFIG_PCI /* enable any pci type devices */
-#undef CONFIG_PCI1 /* PCI controller 1 */
-#undef CONFIG_PCIE1/* PCIE controler 1 (slot 1) */
#undef CONFIG_RIO
#ifdef CONFIG_PCI
@@ -58,7 +55,13 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_SYS_CLK_FREQ6600 /* SBC8548 default SYSCLK */
+/*
+ * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
+ */
+#ifndef CONFIG_SYS_CLK_DIV
+#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
+#endif
+#define CONFIG_SYS_CLK_FREQ(6600 / CONFIG_SYS_CLK_DIV)
/*
* These can be toggled for performance analysis, otherwise use default.
@@ -315,7 +318,7 @@
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE1
-#define CONFIG_SYS_NS16550_CLK 4 /* get_bus_freq(0) */
+#define CONFIG_SYS_NS16550_CLK (4 / CONFIG_SYS_CLK_DIV)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
--
1.6.4.1
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[U-Boot] [PATCH 1/8] sbc8548: delete unused MPC8548CDS info carried over from port
There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
the port to the sbc8548 board, so delete them.
Also, the form factor of the sbc8548 is a standalone board with a
single PCI-X and a single PCI-e slot. That pretty much guarantees
that it will never be a PCI agent itself, so the host/agent and root
complex/end node distinctions have been removed.
Similarly, since there is no physical connector mapping to PCI2, so
all references of PCI2 in the board support files have been removed
as well.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/sbc8548.c | 63
include/configs/sbc8548.h |9 --
2 files changed, 6 insertions(+), 66 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index e5b21b5..f4fd204 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -311,35 +311,9 @@ long int fixed_sdram (void)
}
#endif
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device. Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct
pci_config_table *tab) { }
-
-static struct pci_config_table pci_sbc8548_config_table[] = {
- {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
- mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
- mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
- mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
- mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
- mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-static struct pci_controller pci1_hose = {
- config_table: pci_sbc8548_config_table};
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif /* CONFIG_PCI2 */
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif /* CONFIG_PCI1 */
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
@@ -356,24 +330,20 @@ pci_init_board(void)
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = pci1_hose;
- struct pci_config_table *table;
struct pci_region *r = hose-regions;
uint pci_32 = gur-pordevsr MPC85xx_PORDEVSR_PCI1_PCI32; /*
PORDEVSR[15] */
uint pci_arb = gur-pordevsr MPC85xx_PORDEVSR_PCI1_ARB; /*
PORDEVSR[14] */
uint pci_clk_sel = gur-porpllsr MPC85xx_PORDEVSR_PCI1_SPD; /*
PORPLLSR[16] */
- uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
-
uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
if (!(gur-devdisr MPC85xx_DEVDISR_PCI1)) {
- printf (PCI: %d bit, %s MHz, %s, %s, %s\n,
+ printf (PCI host: %d bit, %s MHz, %s, %s\n,
(pci_32) ? 32 : 64,
(pci_speed == 3000) ? 33 :
(pci_speed == 6000) ? 66 : unknown,
pci_clk_sel ? sync : async,
- pci_agent ? agent : host,
pci_arb ? arbiter : external-arbiter
);
@@ -392,12 +362,6 @@ pci_init_board(void)
PCI_REGION_IO);
hose-region_count = r - hose-regions;
- /* relocate config table pointers */
- hose-config_table = \
- (struct pci_config_table *)((uint)hose-config_table +
gd-reloc_off);
- for (table = hose-config_table; table table-vendor;
table++)
- table-config_device += gd-reloc_off;
-
hose-first_busno=first_free_busno;
fsl_pci_init(hose, (u32)pci-cfg_addr, (u32)pci-cfg_data);
@@ -422,33 +386,18 @@ pci_init_board(void)
gur-devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif
-#ifdef CONFIG_PCI2
-{
- uint pci2_clk_sel = gur-porpllsr 0x4000; /* PORPLLSR[17] */
- uint pci_dual = get_pci_dual ();/* PCI DUAL in CM_PCI[3] */
- if (pci_dual) {
- printf (PCI2: 32 bit, 66 MHz, %s\n,
- pci2_clk_sel ? sync : async);
- } else {
- printf (PCI2: disabled\n);
- }
-}
-#else
- gur-devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
-#endif /* CONFIG_PCI2 */
+ gur-devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t
[U-Boot] [PATCH 8/8] sbc8548: replace README with completely new document
The previous README.sbc8548 was pretty much content-free. Replace it with something that actually gives the end user some relevant hardware details, and also lists the u-boot configuration choices. Also in the cosmetic department, fix the bogus line in the Makefile that was carried over from the SBC8560 Makefile, and the typo in the sbc8548.c copyright. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- board/sbc8548/Makefile |4 +- board/sbc8548/sbc8548.c |3 +- doc/README.sbc8548 | 189 ++- 3 files changed, 173 insertions(+), 23 deletions(-) diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index 9919a6e..09e5c2e 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -2,8 +2,8 @@ # (C) Copyright 2004-2006 # Wolfgang Denk, DENX Software Engineering, w...@denx.de. # -# (C) Copyright 2004 Wind River Systems Inc www.windriver.com. -# Added support for Wind River SBC8560 board +# (C) Copyright 2007 Wind River Systems Inc www.windriver.com. +# Added support for Wind River SBC8548 board # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index c4dc5c5..2978884 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -1,5 +1,6 @@ /* - * Copyright 2007 Wind River Systemes, Inc. www.windriver.com + * Copyright 2007,2009 Wind River Systems, Inc. www.windriver.com + * * Copyright 2007 Embedded Specialties, Inc. * * Copyright 2004, 2007 Freescale Semiconductor. diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index b34d040..d72d97d 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -1,27 +1,176 @@ -Wind River SBC8548 reference board -=== +Intro: +== -Copyright 2007, Embedded Specialties, Inc. -Copyright 2007 Wind River Systemes, Inc. -- +The SBC8548 is a stand alone single board computer with a 1GHz +MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz +memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e, +and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC +ethernet connections. -1. Building U-Boot --- -The SBC8548 code is known to build using ELDK 4.1. +U-boot Configuration: += -$ make sbc8548_config -Configuring for sbc8548 board... +The following possible u-boot configuration targets are available: -$ make + 1) sbc8548_config + 2) sbc8548_PCI_33_config + 3) sbc8548_PCI_66_config + 4) sbc8548_PCI_33_PCIE_config + 5) sbc8548_PCI_66_PCIE_config +Generally speaking, most people should choose to use #5. Details +of each choice are listed below. -2. Switch and Jumper Settings -- -All Jumpers Switches are in their default positions. Please refer to -the board documentation for details. Some settings control CPU voltages -and settings may change with board revisions. +Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot +will be left empty (M66EN high), and so the board will operate with +a base clock of 66MHz. Note that you need both PCI enabled in u-boot +and linux in order to have functional PCI under linux. -3. Known limitations - -PCI: - The code to support PCI is currently disabled and has not been verified. +The second enables PCI support and builds for a 33MHz clock rate. Note +that if a 33MHz 32bit card is inserted in the slot, then the whole board +will clock down to a 33MHz base clock instead of the default 66MHz. This +will change the baud clocks and mess up your serial console output if you +were previously running at 66MHz. If you want to use a 33MHz PCI card, +then you should build a U-Boot with a _PCI_33_ config and store this +to flash prior to powering down the board and inserting the 33MHz PCI +card. [The above discussion assumes that the SW2[1-4] has not been changed +to reflect a different CCB:SYSCLK ratio] + +The third option builds PCI support in, and leaves the clocking at the +default 66MHz. Options four and five are just repeats of option two +and three, but with PCI-e support enabled as well. + +PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx +is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with +a 33MHz PCI configuration is currently untested.) + += pci 0 +Scanning PCI devices on bus 0 +BusDevFun VendorId DeviceId Device Class Sub-Class +_ +00.00.00 0x1057 0x0012 Processor 0x20 +00.01.00 0x8086 0x1026 Network controller 0x00 += pci 1 +Scanning PCI devices on bus 1 +BusDevFun VendorId DeviceId Device Class Sub-Class +_ +01.00.00 0x1957
[U-Boot] [PATCH 5/8] sbc8548: update PCI/PCI-e support code
The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile. This re-syncs it to match
current MPC85xxCDS/MDS PCI-e support.
It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_ (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.
Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8548/law.c | 12 +-
board/sbc8548/sbc8548.c |9 ---
board/sbc8548/tlb.c | 48 +++-
include/configs/sbc8548.h | 43 +--
4 files changed, 59 insertions(+), 53 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index e8c7ae2..6d1efc0 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -32,8 +32,10 @@
*
* 0x_ 0x0fff_ DDR 256M
* 0x8000_ 0x9fff_ PCI1 MEM512M
+ * 0xa000_ 0xbfff_ PCIe MEM512M
* 0xe000_ 0xe000_ CCSR1M
- * 0xe200_ 0xe2ff_ PCI1 IO 16M
+ * 0xe200_ 0xe27f_ PCI1 IO 8M
+ * 0xe280_ 0xe2ff_ PCIe IO 8M
* 0xf000_ 0xf7ff_ SDRAM 128M
* 0xf8b0_ 0xf80f_ EEPROM 1M
* 0xfb80_ 0xff7f_ FLASH (2nd bank)64M
@@ -48,8 +50,14 @@ struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
+#endif
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
/* LBC window - maps 256M 0xf000 - 0x */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 1db32ec..0387140 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -355,14 +355,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
@@ -400,6 +400,7 @@ pci_init_board(void)
struct pci_controller *hose = pcie1_hose;
struct pci_region *r = hose-regions;
+ uint io_sel = (gur-pordevsr MPC85xx_PORDEVSR_IO_SEL) 19;
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured !(gur-devdisr MPC85xx_DEVDISR_PCIE)){
@@ -414,14 +415,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index e173245..dab0eb1 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -52,58 +52,52 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 0, BOOKE_PAGESZ_64M, 1),
/*
-* TLB 1: 256MNon-cacheable, guarded
-* 0x8000 256MPCI1 MEM First half
+* TLB 1: 1G Non-cacheable, guarded
+* 0x8000 512MPCI1 MEM
+* 0xa000 512MPCIe MEM
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS
[U-Boot] [PATCH 2/2] mpc8349: delete unused SYS_MID_FLASH_JUMP
This was introduced with the MPC8349EMDS board, and then copied to a couple other boards by nature of being the reference implementation. u-boot$git grep CONFIG_SYS_MID_FLASH_JUMP include/configs/MPC8349EMDS.h:#define CONFIG_SYS_MID_FLASH_JUMP 0x7F00 include/configs/sbc8349.h:#define CONFIG_SYS_MID_FLASH_JUMP 0x7F00 include/configs/vme8349.h:#define CONFIG_SYS_MID_FLASH_JUMP 0x7F00 u-boot$ It currently isn't used, so delete it before it spreads further. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- include/configs/MPC8349EMDS.h |1 - include/configs/sbc8349.h |1 - include/configs/vme8349.h |1 - 3 files changed, 0 insertions(+), 3 deletions(-) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 3cf59ef..a8c8a79 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -172,7 +172,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MID_FLASH_JUMP 0x7F00 #define CONFIG_SYS_MONITOR_BASETEXT_BASE /* start of monitor */ #if (CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE) diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 088b283..4f2aef0 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -157,7 +157,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MID_FLASH_JUMP 0x7F00 #define CONFIG_SYS_MONITOR_BASETEXT_BASE /* start of monitor */ #if (CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE) diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 1477552..35d367d 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -152,7 +152,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase TO (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write TO (ms) */ -#define CONFIG_SYS_MID_FLASH_JUMP 0x7F00 #define CONFIG_SYS_MONITOR_BASETEXT_BASE /* start of monitor */ #if (CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE) -- 1.6.3.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] sbc8349: make enabling PCI more user friendly.
Prior to this commit, to enable PCI, you had to go manually edit the board config header, which isn't really user friendly. This adds the typical PCI make targets to the toplevel Makefile in accordance with what is being done with other boards. Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- Makefile | 19 +++- doc/README.sbc8349| 50 ++-- include/configs/sbc8349.h | 22 +++ 3 files changed, 64 insertions(+), 27 deletions(-) diff --git a/Makefile b/Makefile index 329e0f5..da98900 100644 --- a/Makefile +++ b/Makefile @@ -2375,8 +2375,23 @@ MPC837XERDB_config: unconfig MVBLM7_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 matrix_vision -sbc8349_config:unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 +sbc8349_config \ +sbc8349_PCI_33_config \ +sbc8349_PCI_66_config: unconfig + @mkdir -p $(obj)include + @if [ $(findstring _PCI_,$@) ] ; then \ + $(XECHO) -n ... PCI HOST at ; \ + echo #define CONFIG_PCI $(obj)include/config.h ; \ + fi ; \ + if [ $(findstring _33_,$@) ] ; then \ + $(XECHO) -n 33MHz... ; \ + echo #define PCI_33M $(obj)include/config.h ; \ + fi ; \ + if [ $(findstring _66_,$@) ] ; then \ + $(XECHO) -n 66MHz... ; \ + echo #define PCI_66M $(obj)include/config.h ; \ + fi ; + @$(MKCONFIG) -a sbc8349 ppc mpc83xx sbc8349 SIMPC8313_LP_config \ SIMPC8313_SP_config: unconfig diff --git a/doc/README.sbc8349 b/doc/README.sbc8349 index 908e768..2c35919 100644 --- a/doc/README.sbc8349 +++ b/doc/README.sbc8349 @@ -91,19 +91,37 @@ safety check before resetting the board upon completion of the reflash. PCI: -This board and U-Boot have been tested with PCI built in, on a SBC8349 -and confirmed that the pci command showed the intel e1000 that was -present in the PCI slot. Note that if a 33MHz 32bit card is inserted -in the slot, then the whole board will clock down to a 33MHz base -clock instead of the default 66MHz. This will change the baud clocks -and mess up your serial console output. If you want to use a 33MHz PCI -card, then you should build a U-Boot with #undef PCI_66M in the -include/configs/sbc8349.h and store this to flash prior to powering down -the board and inserting the 33MHz PCI card. - -By default PCI support is disabled to better support very early -revision MPC834x chips with possible PCI issues. Also PCI support is -untested on the sbc8347 variants at this point in time. - - - Paul Gortmaker, 01/2007 +There are three configuration choices: + sbc8349_config + sbc8349_PCI_33_config + sbc8349_PCI_66_config + +The 1st does not enable CONFIG_PCI, and assumes that the PCI slot +will be left empty (M66EN high), and so the board will operate with +a base clock of 66MHz. Note that you need both PCI enabled in u-boot +and linux in order to have functional PCI under linux. The only +reason for choosing to not enable PCI would be if you had a very +early (rev 1.0) CPU with possible PCI issues. + +The second enables PCI support and builds for a 33MHz clock rate. Note +that if a 33MHz 32bit card is inserted in the slot, then the whole board +will clock down to a 33MHz base clock instead of the default 66MHz. This +will change the baud clocks and mess up your serial console output if you +were previously running at 66MHz. If you want to use a 33MHz PCI card, +then you should build a U-Boot with sbc8349_PCI_33_config and store this +to flash prior to powering down the board and inserting the 33MHz PCI +card. + +The third option builds PCI support in, and leaves the clocking at the +default 66MHz. This has been tested with an intel PCI-X e1000 card. +This is also the appropriate choice for people with a recent (non 1.0) +CPU who currently have the PCI slot physically empty, but intend to +possibly add a PCI-X card at a later date. + + = pci + Scanning PCI devices on bus 0 + BusDevFun VendorId DeviceId Device Class Sub-Class + _ + 00.00.00 0x1957 0x0080 Processor 0x20 + 00.11.00 0x8086 0x1026 Network controller 0x00 + = diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 868bd54..088b283 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -40,24 +40,28 @@ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ -#undef CONFIG_PCI /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 6600/* in Hz */ -#else
[U-Boot] [PATCH] sbc8349: combine HRCW flash and u-boot image flash
Up to this point in time, the sbc8349 board was storing the u-boot
image in flash 2x. One for the HRCW value at the beginning of
flash (0xff80_), and once close to the end of flash (0xfff8_)
for the actual image that got executed.
This moves the TEXT_BASE to be the beginning of flash, which makes
the second copy of the image redundant, and frees up the flash
from the end of the environment storage to the end of the flash
device itself.
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
board/sbc8349/config.mk |2 +-
doc/README.sbc8349| 30 --
include/configs/sbc8349.h |4 ++--
3 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/board/sbc8349/config.mk b/board/sbc8349/config.mk
index 05fa5a0..eacb27e 100644
--- a/board/sbc8349/config.mk
+++ b/board/sbc8349/config.mk
@@ -24,4 +24,4 @@
# SBC8349E
#
-TEXT_BASE = 0xFFF0
+TEXT_BASE = 0xFF80
diff --git a/doc/README.sbc8349 b/doc/README.sbc8349
index a0ac638..908e768 100644
--- a/doc/README.sbc8349
+++ b/doc/README.sbc8349
@@ -21,15 +21,22 @@ Flash Details:
The flash type is intel 28F640Jx (4096x16) [one device]. Base address
is 0xFF80_ which is also where the Hardware Reset Configuration
-Word (HRCW) is stored. Caution should be used to not overwrite the
-HRCW, or CF RCW with a Wind River ICE will be required to restore
-the HRCW and allow the board to enter background mode for further
-steps in the flash process.
+Word (HRCW) is stored. Caution should be used to not reset the
+board without having a valid HRCW in place (i.e. erased flash) as
+then a Wind River ICE will be required to restore the HRCW and flash
+image.
Restoring a corrupted or missing flash image:
=
+Note that U-boot versions up to and including 2009.06 had essentially
+two copies of u-boot in flash; one at the very beginning, which set
+the HRCW, and one at the very end, which was the image that was run.
+As of this point in time, the two have been combined into just one
+at the beginning of flash, which provides both the HRCW, and the image
+that is executed. This frees up the remainder of flash for other uses.
+Use of the u-boot command fli will indicate what parts are in use.
Details for storing U-boot to flash using a Wind River ICE can be found
on page 19 of the board manual (request ERG-00328-001). The following
is a summary of that information:
@@ -39,9 +46,9 @@ is a summary of that information:
- Select the appropriate flash type (listed above)
- Prepare a u-boot image by using the Wind River Convert utility;
by using Convert and Add file on the ELF file from your build.
-Convert from FFF0_ to _ (or to FFF3_ if you are
-trying to preserve your old environment settings).
- - Set the start address of the erase/flash process to FFF0_
+Convert from FF80_ to _ (or to FF83_ if you are
+trying to preserve your old environment settings and user flash).
+ - Set the start address of the erase/flash process to FF80_
- Set the target RAM required to 64kB.
- Select sectors for erasing (see note on enviroment below)
- Select Erase and Reprogram.
@@ -59,7 +66,7 @@ beginning with SCGA TSEC1 and SCGA TSEC2. This allows
you to
use all the remaining register file content.
If you wish to preserve your prior U-Boot environment settings,
-then convert (and erase to) 0xFFF3 instead of 0x.
+then convert (and erase to) 0xFF83 instead of 0x.
The size for converting (and erasing) must be at least as large
as u-boot.bin.
@@ -73,10 +80,13 @@ has been copied to the TFTP server, the commands are:
tftp 20 u-boot.bin
protect off all
- erase fff0 fff3
- cp.b 20 fff0 3
+ erase ff80 ff83
+ cp.b 20 ff80 4
protect on all
+You may wish to do a md ff80 20 operation as a prefix and postfix
+to the above steps to inspect/compare the HRCW before/after as an extra
+safety check before resetting the board upon completion of the reflash.
PCI:
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 20dcd1c..1f13c36 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -652,8 +652,8 @@
net_nfs=tftp 20 ${bootfile};run nfsargs addip addtty; \
bootm\0 \
load=tftp 10 /tftpboot/sbc8349/u-boot.bin\0 \
- update=protect off fff0 fff3; \
- era fff0 fff3; cp.b 10 fff0 ${filesize}\0
\
+ update=protect off ff80 ff83; \
+ era ff80 ff83; cp.b 10 ff80 ${filesize}\0
\
upd=run load update\0 \
fdtaddr=40\0
Re: [U-Boot] TSEC ethernet controller problems (crc errors/ corruption)
Paul Gortmaker wrote: Kim Phillips wrote: On Wed, 3 Jun 2009 10:50:25 -0700 Ira Snyder i...@ovro.caltech.edu wrote: ... In practice, this doesn't seem to make a difference on the MPC8349EMDS eval board. Both settings work without any errors. For people like me, who are copying an existing board port to a similar board, it would be nice if it was correct. granted. I'm betting the sbc8349 and tqm834x just copied the setting You would be correct (at least for the sbc). from the MDS code, so those should get 0 too. Board maintainers, please test: I won't be able to test this on an sbc until later this week, but don't let that stop you from queueing it up; I suspect it will just be a formality. I applied the chunk below onto a checkout of v2009.06-rc2 and it works fine on sbc8349; tested both TSEC and at both 100 and 1GB. Tested-by: Paul Gortmaker paul.gortma...@windriver.com --- U-Boot 2009.06-rc2-dirty (Jun 05 2009 - 14:11:18) MPC83XX Reset Status: Software Hard, External/Internal Soft, External/Internal Hard CPU: e300c1, MPC8349E, Rev: 1.1 at 396 MHz, CSB: 264 MHz Board: Wind River SBC834x I2C: ready DRAM: SDRAM on Local Bus: Disabled in config 256 MB (DDR1, 64-bit, ECC off, 264 MHz) FLASH: 8 MB In:serial Out: serial Err: serial Net: TSEC0, TSEC1 = --- Thanks, Paul. diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index d0338f1..edd928d 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -519,7 +519,7 @@ #endif /* System IO Config */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 +#define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x0 Thanks, Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] TSEC ethernet controller problems (crc errors/ corruption)
Kim Phillips wrote: On Wed, 3 Jun 2009 10:50:25 -0700 Ira Snyder i...@ovro.caltech.edu wrote: ... In practice, this doesn't seem to make a difference on the MPC8349EMDS eval board. Both settings work without any errors. For people like me, who are copying an existing board port to a similar board, it would be nice if it was correct. granted. I'm betting the sbc8349 and tqm834x just copied the setting You would be correct (at least for the sbc). from the MDS code, so those should get 0 too. Board maintainers, please test: I won't be able to test this on an sbc until later this week, but don't let that stop you from queueing it up; I suspect it will just be a formality. Thanks, Paul. diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index d0338f1..edd928d 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -519,7 +519,7 @@ #endif /* System IO Config */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 +#define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x0 Thanks, Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/3] sbc8548 PHY fix, cmdline editing.
Hi Andy,
Would you please merge these three sbc8548 patches via the mpc85xx tree?
This fixes an incorrect PHY address issue that was masked by the tsec
driver inadvertently doing an if (0) {...} Rather than put in bogus
PHY address for the eTSEC3 and eTSEC4, I just purged them from the
board config file altogether.
I also got sick of not having command line editing, and so enabled that.
Thanks,
Paul.
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