Re: [PATCH v6] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Hi Sean, Thanks for the review, it will be revised in the next version. -- Stanley On Fri, May 27, 2022 at 12:06 PM Sean Anderson wrote: > > On 5/3/22 1:33 AM, Stanley Chu wrote: > > Add Nuvoton BMC NPCM845 Pinmux and Pinconf support. > > > > Signed-off-by: Stanley Chu > > --- > > v6: > > - sync pin name with Linux driver > > - add support for gpi35/gpi36/gpio183~189 > > v5: > > - lower-case hex consistently > > - use uint type for pin list in the group_config struct > > v4: > > - correct the pin flags, add slew rate control suuport for rgmii pins > > v3: > > - separate group names and function names in different tables > > to allow for adding additional functions > > v2: > > - drop the WDnRCRB/CORSTCB register access, it is not for > > GPIO modules reset control > > --- > > drivers/pinctrl/Kconfig |1 + > > drivers/pinctrl/Makefile |1 + > > drivers/pinctrl/nuvoton/Kconfig | 12 + > > drivers/pinctrl/nuvoton/Makefile |1 + > > drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1225 + > > 5 files changed, 1240 insertions(+) > > create mode 100644 drivers/pinctrl/nuvoton/Kconfig > > create mode 100644 drivers/pinctrl/nuvoton/Makefile > > create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c > > > > diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig > > index 13033198f9..e14e885c3e 100644 > > --- a/drivers/pinctrl/Kconfig > > +++ b/drivers/pinctrl/Kconfig > > @@ -339,6 +339,7 @@ source "drivers/pinctrl/mscc/Kconfig" > > source "drivers/pinctrl/mtmips/Kconfig" > > source "drivers/pinctrl/mvebu/Kconfig" > > source "drivers/pinctrl/nexell/Kconfig" > > +source "drivers/pinctrl/nuvoton/Kconfig" > > source "drivers/pinctrl/nxp/Kconfig" > > source "drivers/pinctrl/renesas/Kconfig" > > source "drivers/pinctrl/rockchip/Kconfig" > > diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile > > index 9b4978253b..aa31f31c16 100644 > > --- a/drivers/pinctrl/Makefile > > +++ b/drivers/pinctrl/Makefile > > @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ > > obj-$(CONFIG_ARCH_ATH79) += ath79/ > > obj-$(CONFIG_PINCTRL_INTEL) += intel/ > > obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ > > +obj-$(CONFIG_ARCH_NPCM) += nuvoton/ > > obj-$(CONFIG_ARCH_RMOBILE) += renesas/ > > obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o > > obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ > > diff --git a/drivers/pinctrl/nuvoton/Kconfig > > b/drivers/pinctrl/nuvoton/Kconfig > > new file mode 100644 > > index 00..519539d6ae > > --- /dev/null > > +++ b/drivers/pinctrl/nuvoton/Kconfig > > @@ -0,0 +1,12 @@ > > +config PINCTRL_NPCM8XX > > + bool "Pinctrl driver for Nuvoton NPCM8XX" > > + depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX > > + help > > + Support pin muxing and pin configuration on > > + Nuvoton NPCM8XX SoC. > > + > > + The NPCM8XX contains 256 GPIO pins. Most of them are > > + multiplexed with other system functions. These pins can > > + be configured as either GPIO pin or alternate function. > > + It also supports basic configurations such as pull up/down, > > + drive-strength, and slew rate control for some of the pins. > > diff --git a/drivers/pinctrl/nuvoton/Makefile > > b/drivers/pinctrl/nuvoton/Makefile > > new file mode 100644 > > index 00..a6dfdf3672 > > --- /dev/null > > +++ b/drivers/pinctrl/nuvoton/Makefile > > @@ -0,0 +1 @@ > > +obj-$(CONFIG_PINCTRL_NPCM8XX)+= pinctrl-npcm8xx.o > > diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c > > b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c > > new file mode 100644 > > index 00..cc49310506 > > --- /dev/null > > +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c > > @@ -0,0 +1,1225 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (c) 2022 Nuvoton Technology Corp. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* GCR register offsets */ > > +#define WD0RCR 0x38 > > +#define WD1RCR 0x3c > > +#define WD2RCR 0x40 > > +#
[PATCH v6] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support. Signed-off-by: Stanley Chu --- v6: - sync pin name with Linux driver - add support for gpi35/gpi36/gpio183~189 v5: - lower-case hex consistently - use uint type for pin list in the group_config struct v4: - correct the pin flags, add slew rate control suuport for rgmii pins v3: - separate group names and function names in different tables to allow for adding additional functions v2: - drop the WDnRCRB/CORSTCB register access, it is not for GPIO modules reset control --- drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig | 12 + drivers/pinctrl/nuvoton/Makefile |1 + drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1225 + 5 files changed, 1240 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 13033198f9..e14e885c3e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -339,6 +339,7 @@ source "drivers/pinctrl/mscc/Kconfig" source "drivers/pinctrl/mtmips/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nexell/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 9b4978253b..aa31f31c16 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ obj-$(CONFIG_PINCTRL_INTEL) += intel/ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ +obj-$(CONFIG_ARCH_NPCM) += nuvoton/ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI)+= sunxi/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index 00..519539d6ae --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,12 @@ +config PINCTRL_NPCM8XX + bool "Pinctrl driver for Nuvoton NPCM8XX" + depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX + help + Support pin muxing and pin configuration on + Nuvoton NPCM8XX SoC. + + The NPCM8XX contains 256 GPIO pins. Most of them are + multiplexed with other system functions. These pins can + be configured as either GPIO pin or alternate function. + It also supports basic configurations such as pull up/down, + drive-strength, and slew rate control for some of the pins. diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index 00..a6dfdf3672 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c new file mode 100644 index 00..cc49310506 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -0,0 +1,1225 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR register offsets */ +#define WD0RCR 0x38 +#define WD1RCR 0x3c +#define WD2RCR 0x40 +#define SWRSTC10x44 +#define SWRSTC20x48 +#define SWRSTC30x4c +#define SWRSTC40x50 +#define CORSTC 0x5c +#define FLOCKR10x74 +#define INTCR4 0xc0 +#define I2CSEGSEL 0xe0 +#define MFSEL1 0x260 +#define MFSEL2 0x264 +#define MFSEL3 0x268 +#define MFSEL4 0x26c +#define MFSEL5 0x270 +#define MFSEL6 0x274 +#define MFSEL7 0x278 + +/* GPIO register offsets */ +#define GPIO_POL 0x08 /* Polarity */ +#define GPIO_DOUT 0x0c /* Data OUT */ +#define GPIO_OTYP 0x14 /* Output Type */ +#define GPIO_PU0x1c /* Pull-up */ +#define GPIO_PD0x20 /* Pull-down */ +#define GPIO_DBNC 0x24 /* Debounce */ +#define GPIO_EVEN 0x40 /* Event Enable */ +#define GPIO_EVST 0x4c /* Event Status */ +#define GPIO_IEM 0x58 /* Input Enable */ +#define GPIO_OSRC 0x5c /* Output Slew-Rate Control */ +#define GPIO_ODSC 0x60 /* Output Drive Strength Control */ +#define GPIO_OES 0x70 /* Output Enable Set */ +#define GPIO_OEC 0x74 /* Output Enable Clear */ + +#define NPCM8XX_GPIO_PER_BANK 32 +#define GPIOX_OFFSET 16 + +/* The lists contain alternate GPIO pins of the functi
[PATCH v5] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
Signed-off-by: Stanley Chu
---
v5:
- lower-case hex consistently
- use uint type for pin list in the group_config struct
v4:
- correct the pin flags, add slew rate control suuport for rgmii pins
v3:
- separate group names and function names in different tables
to allow for adding additional functions
v2:
- drop the WDnRCRB/CORSTCB register access, it is not for
GPIO modules reset control
---
drivers/pinctrl/Kconfig |1 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/nuvoton/Kconfig | 12 +
drivers/pinctrl/nuvoton/Makefile |1 +
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1185 +
5 files changed, 1200 insertions(+)
create mode 100644 drivers/pinctrl/nuvoton/Kconfig
create mode 100644 drivers/pinctrl/nuvoton/Makefile
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 03946245c7..076aff1a8d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -329,6 +329,7 @@ source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mtmips/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nexell/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index df37c32033..de84f8912b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
new file mode 100644
index 00..519539d6ae
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -0,0 +1,12 @@
+config PINCTRL_NPCM8XX
+ bool "Pinctrl driver for Nuvoton NPCM8XX"
+ depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX
+ help
+ Support pin muxing and pin configuration on
+ Nuvoton NPCM8XX SoC.
+
+ The NPCM8XX contains 256 GPIO pins. Most of them are
+ multiplexed with other system functions. These pins can
+ be configured as either GPIO pin or alternate function.
+ It also supports basic configurations such as pull up/down,
+ drive-strength, and slew rate control for some of the pins.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
new file mode 100644
index 00..a6dfdf3672
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
new file mode 100644
index 00..ca6c5b9aa9
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -0,0 +1,1185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* GCR register offsets */
+#define WD0RCR 0x38
+#define WD1RCR 0x3c
+#define WD2RCR 0x40
+#define SWRSTC10x44
+#define SWRSTC20x48
+#define SWRSTC30x4c
+#define SWRSTC40x50
+#define CORSTC 0x5c
+#define FLOCKR10x74
+#define INTCR4 0xc0
+#define I2CSEGSEL 0xe0
+#define MFSEL1 0x260
+#define MFSEL2 0x264
+#define MFSEL3 0x268
+#define MFSEL4 0x26c
+#define MFSEL5 0x270
+#define MFSEL6 0x274
+#define MFSEL7 0x278
+
+/* GPIO register offsets */
+#define GPIO_POL 0x08 /* Polarity */
+#define GPIO_DOUT 0x0c /* Data OUT */
+#define GPIO_OTYP 0x14 /* Output Type */
+#define GPIO_PU0x1c /* Pull-up */
+#define GPIO_PD0x20 /* Pull-down */
+#define GPIO_DBNC 0x24 /* Debounce */
+#define GPIO_EVEN 0x40 /* Event Enable */
+#define GPIO_EVST 0x4c /* Event Status */
+#define GPIO_IEM 0x58 /* Input Enable */
+#define GPIO_OSRC 0x5c /* Output Slew-Rate Control */
+#define GPIO_ODSC 0x60 /* Output Drive Strength Control */
+#define GPIO_OES 0x70 /* Output Enable Set */
+#define GPIO_OEC 0x74 /* Output Enable Clear */
+
+#define NPCM8XX_GPIO_PER_BANK 32
+#define GPIOX_OFFSET 16
+
+/* The lists contain alternate GPIO pins of the function */
+/* Serial Interfaces */
+static const uint hsi1a_pins[] = { 43, 63 };
+static const uint hsi1b_pins[] = { 44, 62 };
+
[PATCH v4] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
Signed-off-by: Stanley Chu
---
v4:
- correct the pin flags, add slew rate control suuport for rgmii pins
v3:
- separate group names and function names in different tables
to allow for adding additional functions
v2:
- drop the WDnRCRB/CORSTCB register access, it is not for
GPIO modules reset control
---
drivers/pinctrl/Kconfig |1 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/nuvoton/Kconfig |6 +
drivers/pinctrl/nuvoton/Makefile |1 +
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1185 +
5 files changed, 1194 insertions(+)
create mode 100644 drivers/pinctrl/nuvoton/Kconfig
create mode 100644 drivers/pinctrl/nuvoton/Makefile
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 03946245c7..076aff1a8d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -329,6 +329,7 @@ source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mtmips/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nexell/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index df37c32033..de84f8912b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
new file mode 100644
index 00..b490b41a60
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -0,0 +1,6 @@
+config PINCTRL_NPCM8XX
+ bool "Pinctrl driver for Nuvoton NPCM8XX"
+ depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX
+ help
+ Support pin muxing and pin configuration on
+ Nuvoton NPCM8XX SoC.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
new file mode 100644
index 00..a6dfdf3672
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
new file mode 100644
index 00..9a21e990e8
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -0,0 +1,1185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* GCR register offsets */
+#define WD0RCR 0x38
+#define WD1RCR 0x3C
+#define WD2RCR 0x40
+#define SWRSTC10x44
+#define SWRSTC20x48
+#define SWRSTC30x4C
+#define SWRSTC40x50
+#define CORSTC 0x5C
+#define FLOCKR10x74
+#define INTCR4 0xC0
+#define I2CSEGSEL 0xE0
+#define MFSEL1 0x260
+#define MFSEL2 0x264
+#define MFSEL3 0x268
+#define MFSEL4 0x26C
+#define MFSEL5 0x270
+#define MFSEL6 0x274
+#define MFSEL7 0x278
+
+/* GPIO register offsets */
+#define GPIO_POL 0x08 /* Polarity */
+#define GPIO_DOUT 0x0c /* Data OUT */
+#define GPIO_OTYP 0x14 /* Output Type */
+#define GPIO_PU0x1c /* Pull-up */
+#define GPIO_PD0x20 /* Pull-down */
+#define GPIO_DBNC 0x24 /* Debounce */
+#define GPIO_EVEN 0x40 /* Event Enable */
+#define GPIO_EVST 0x4c /* Event Status */
+#define GPIO_IEM 0x58 /* Input Enable */
+#define GPIO_OSRC 0x5c /* Output Slew-Rate Control */
+#define GPIO_ODSC 0x60 /* Output Drive Strength Control */
+#define GPIO_OES 0x70 /* Output Enable Set */
+#define GPIO_OEC 0x74 /* Output Enable Clear */
+
+#define NPCM8XX_GPIO_PER_BANK 32
+#define GPIOX_OFFSET 16
+
+/* The lists contain alternate GPIO pins of the function */
+/* Serial Interfaces */
+static const unsigned int hsi1a_pins[] = { 43, 63 };
+static const unsigned int hsi1b_pins[] = { 44, 62 };
+static const unsigned int hsi1c_pins[] = { 45, 46, 47, 61 };
+static const unsigned int hsi2a_pins[] = { 48, 49 };
+static const unsigned int hsi2b_pins[] = { 50, 51 };
+static const unsigned int hsi2c_pins[] = { 52, 53, 54, 55 };
+static const unsigned int bmcuart0a_pins[] = { 41, 42 };
+static const unsigned int bmcuart0b_pins[] = { 48, 49 };
+static const unsigned int bmcuart1_pins[] = { 43, 63 };
+static c
[PATCH v3] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
Signed-off-by: Stanley Chu
---
v3:
- separate group names and function names in different tables
to allow for adding additional functions
v2:
- drop the WDnRCRB/CORSTCB register access, it is not for
GPIO modules reset control
---
drivers/pinctrl/Kconfig |1 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/nuvoton/Kconfig |6 +
drivers/pinctrl/nuvoton/Makefile |1 +
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1185 +
5 files changed, 1194 insertions(+)
create mode 100644 drivers/pinctrl/nuvoton/Kconfig
create mode 100644 drivers/pinctrl/nuvoton/Makefile
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 03946245c7..076aff1a8d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -329,6 +329,7 @@ source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mtmips/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nexell/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index df37c32033..de84f8912b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
new file mode 100644
index 00..b490b41a60
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -0,0 +1,6 @@
+config PINCTRL_NPCM8XX
+ bool "Pinctrl driver for Nuvoton NPCM8XX"
+ depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX
+ help
+ Support pin muxing and pin configuration on
+ Nuvoton NPCM8XX SoC.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
new file mode 100644
index 00..a6dfdf3672
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
new file mode 100644
index 00..c36174350b
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -0,0 +1,1185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* GCR register offsets */
+#define WD0RCR 0x38
+#define WD1RCR 0x3C
+#define WD2RCR 0x40
+#define SWRSTC10x44
+#define SWRSTC20x48
+#define SWRSTC30x4C
+#define SWRSTC40x50
+#define CORSTC 0x5C
+#define FLOCKR10x74
+#define INTCR4 0xC0
+#define I2CSEGSEL 0xE0
+#define MFSEL1 0x260
+#define MFSEL2 0x264
+#define MFSEL3 0x268
+#define MFSEL4 0x26C
+#define MFSEL5 0x270
+#define MFSEL6 0x274
+#define MFSEL7 0x278
+
+/* GPIO register offsets */
+#define GPIO_POL 0x08 /* Polarity */
+#define GPIO_DOUT 0x0c /* Data OUT */
+#define GPIO_OTYP 0x14 /* Output Type */
+#define GPIO_PU0x1c /* Pull-up */
+#define GPIO_PD0x20 /* Pull-down */
+#define GPIO_DBNC 0x24 /* Debounce */
+#define GPIO_EVEN 0x40 /* Event Enable */
+#define GPIO_EVST 0x4c /* Event Status */
+#define GPIO_IEM 0x58 /* Input Enable */
+#define GPIO_OSRC 0x5c /* Output Slew-Rate Control */
+#define GPIO_ODSC 0x60 /* Output Drive Strength Control */
+#define GPIO_OES 0x70 /* Output Enable Set */
+#define GPIO_OEC 0x74 /* Output Enable Clear */
+
+#define NPCM8XX_GPIO_PER_BANK 32
+#define GPIOX_OFFSET 16
+
+/* The lists contain alternate GPIO pins of the function */
+/* Serial Interfaces */
+static const unsigned int hsi1a_pins[] = { 43, 63 };
+static const unsigned int hsi1b_pins[] = { 44, 62 };
+static const unsigned int hsi1c_pins[] = { 45, 46, 47, 61 };
+static const unsigned int hsi2a_pins[] = { 48, 49 };
+static const unsigned int hsi2b_pins[] = { 50, 51 };
+static const unsigned int hsi2c_pins[] = { 52, 53, 54, 55 };
+static const unsigned int bmcuart0a_pins[] = { 41, 42 };
+static const unsigned int bmcuart0b_pins[] = { 48, 49 };
+static const unsigned int bmcuart1_pins[] = { 43, 63 };
+static const unsigned int nbu1crts_pins[] = { 44, 62 };
+static const unsigned
[PATCH v2] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
Signed-off-by: Stanley Chu
---
v2:
- drop the WDnRCRB/CORSTCB register access, it is not for
GPIO modules reset control
---
drivers/pinctrl/Kconfig |1 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/nuvoton/Kconfig |6 +
drivers/pinctrl/nuvoton/Makefile |1 +
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1163 +
5 files changed, 1172 insertions(+)
create mode 100644 drivers/pinctrl/nuvoton/Kconfig
create mode 100644 drivers/pinctrl/nuvoton/Makefile
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 03946245c7..076aff1a8d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -329,6 +329,7 @@ source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mtmips/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nexell/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index df37c32033..de84f8912b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
new file mode 100644
index 00..b490b41a60
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -0,0 +1,6 @@
+config PINCTRL_NPCM8XX
+ bool "Pinctrl driver for Nuvoton NPCM8XX"
+ depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX
+ help
+ Support pin muxing and pin configuration on
+ Nuvoton NPCM8XX SoC.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
new file mode 100644
index 00..a6dfdf3672
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
new file mode 100644
index 00..4531923cff
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -0,0 +1,1163 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* GCR register offsets */
+#define WD0RCR 0x38
+#define WD1RCR 0x3C
+#define WD2RCR 0x40
+#define SWRSTC10x44
+#define SWRSTC20x48
+#define SWRSTC30x4C
+#define SWRSTC40x50
+#define CORSTC 0x5C
+#define FLOCKR10x74
+#define INTCR4 0xC0
+#define I2CSEGSEL 0xE0
+#define MFSEL1 0x260
+#define MFSEL2 0x264
+#define MFSEL3 0x268
+#define MFSEL4 0x26C
+#define MFSEL5 0x270
+#define MFSEL6 0x274
+#define MFSEL7 0x278
+
+/* GPIO register offsets */
+#define GPIO_POL 0x08 /* Polarity */
+#define GPIO_DOUT 0x0c /* Data OUT */
+#define GPIO_OTYP 0x14 /* Output Type */
+#define GPIO_PU0x1c /* Pull-up */
+#define GPIO_PD0x20 /* Pull-down */
+#define GPIO_DBNC 0x24 /* Debounce */
+#define GPIO_EVEN 0x40 /* Event Enable */
+#define GPIO_EVST 0x4c /* Event Status */
+#define GPIO_IEM 0x58 /* Input Enable */
+#define GPIO_OSRC 0x5c /* Output Slew-Rate Control */
+#define GPIO_ODSC 0x60 /* Output Drive Strength Control */
+#define GPIO_OES 0x70 /* Output Enable Set */
+#define GPIO_OEC 0x74 /* Output Enable Clear */
+
+#define NPCM8XX_GPIO_PER_BANK 32
+#define GPIOX_OFFSET 16
+
+/* The lists contain alternate GPIO pins of the function */
+/* Serial Interfaces */
+static const unsigned int hsi1a_pins[] = { 43, 63 };
+static const unsigned int hsi1b_pins[] = { 44, 62 };
+static const unsigned int hsi1c_pins[] = { 45, 46, 47, 61 };
+static const unsigned int hsi2a_pins[] = { 48, 49 };
+static const unsigned int hsi2b_pins[] = { 50, 51 };
+static const unsigned int hsi2c_pins[] = { 52, 53, 54, 55 };
+static const unsigned int bmcuart0a_pins[] = { 41, 42 };
+static const unsigned int bmcuart0b_pins[] = { 48, 49 };
+static const unsigned int bmcuart1_pins[] = { 43, 63 };
+static const unsigned int nbu1crts_pins[] = { 44, 62 };
+static const unsigned int bu2_pins[] = { 96, 97};
+static const unsigned int bu4_pins[] = { 54, 55 };
+static const unsigned int bu4b_pin
[PATCH v1] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
Signed-off-by: Stanley Chu
---
drivers/pinctrl/Kconfig |1 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/nuvoton/Kconfig |6 +
drivers/pinctrl/nuvoton/Makefile |1 +
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1182 +
5 files changed, 1191 insertions(+)
create mode 100644 drivers/pinctrl/nuvoton/Kconfig
create mode 100644 drivers/pinctrl/nuvoton/Makefile
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 03946245c7..076aff1a8d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -329,6 +329,7 @@ source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mtmips/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nexell/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index df37c32033..de84f8912b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
new file mode 100644
index 00..b490b41a60
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -0,0 +1,6 @@
+config PINCTRL_NPCM8XX
+ bool "Pinctrl driver for Nuvoton NPCM8XX"
+ depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX
+ help
+ Support pin muxing and pin configuration on
+ Nuvoton NPCM8XX SoC.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
new file mode 100644
index 00..a6dfdf3672
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
new file mode 100644
index 00..476f441851
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -0,0 +1,1182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* GCR register offsets */
+#define WD0RCR 0x38
+#define WD1RCR 0x3C
+#define WD2RCR 0x40
+#define SWRSTC10x44
+#define SWRSTC20x48
+#define SWRSTC30x4C
+#define SWRSTC40x50
+#define CORSTC 0x5C
+#define FLOCKR10x74
+#define WD0RCRB0x80
+#define WD1RCRB0x84
+#define WD2RCRB0x88
+#define CORSTCB0x9C
+#define INTCR4 0xC0
+#define I2CSEGSEL 0xE0
+#define MFSEL1 0x260
+#define MFSEL2 0x264
+#define MFSEL3 0x268
+#define MFSEL4 0x26C
+#define MFSEL5 0x270
+#define MFSEL6 0x274
+#define MFSEL7 0x278
+
+/* GPIO register offsets */
+#define GPIO_POL 0x08 /* Polarity */
+#define GPIO_DOUT 0x0c /* Data OUT */
+#define GPIO_OTYP 0x14 /* Output Type */
+#define GPIO_PU0x1c /* Pull-up */
+#define GPIO_PD0x20 /* Pull-down */
+#define GPIO_DBNC 0x24 /* Debounce */
+#define GPIO_EVEN 0x40 /* Event Enable */
+#define GPIO_EVST 0x4c /* Event Status */
+#define GPIO_IEM 0x58 /* Input Enable */
+#define GPIO_OSRC 0x5c /* Output Slew-Rate Control */
+#define GPIO_ODSC 0x60 /* Output Drive Strength Control */
+#define GPIO_OES 0x70 /* Output Enable Set */
+#define GPIO_OEC 0x74 /* Output Enable Clear */
+
+#define NPCM8XX_GPIO_PER_BANK 32
+#define GPIOX_OFFSET 16
+
+/* The lists contain alternate GPIO pins of the function */
+/* Serial Interfaces */
+static const unsigned int hsi1a_pins[] = { 43, 63 };
+static const unsigned int hsi1b_pins[] = { 44, 62 };
+static const unsigned int hsi1c_pins[] = { 45, 46, 47, 61 };
+static const unsigned int hsi2a_pins[] = { 48, 49 };
+static const unsigned int hsi2b_pins[] = { 50, 51 };
+static const unsigned int hsi2c_pins[] = { 52, 53, 54, 55 };
+static const unsigned int bmcuart0a_pins[] = { 41, 42 };
+static const unsigned int bmcuart0b_pins[] = { 48, 49 };
+static const unsigned int bmcuart1_pins[] = { 43, 63 };
+static const unsigned int nbu1crts_pins[] = { 44, 62 };
+static const unsigned int bu2_pins[] = { 96, 97};
+static const unsigned int bu4_pin
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
On Fri, Mar 11, 2022 at 10:53 AM Giulio Benetti wrote: > > Hi Stanley, > > > Il giorno 11 mar 2022, alle ore 03:13, Stanley Chu > > ha scritto: > > > > Hi Tom, > > We need time to prepare linux dts, can I send the rest of the drivers > > first or need to wait until the linux dts is submitted? > > Because I want to remove some unused nodes/properties away from linux > > dts to reduce dtb size, can we use different dts for uboot? > > You can add a specific -uboot.dtsi file where you tag every node to be or not > to be part of final uboot .dtb > This way the original .dts file will be synced with Linux, except the > -uboot.dtsi inclusion. > Take a look at upstreamed .dts files and look for uboot.dtsi suffix files. Hi Giulio, Thanks a lot. It will be done in v2. -- Stanley > > Best regards > —- > Giulio Benetti > Benetti Engineering sas > > > Thanks a lot for your comments. > > > > -- > > Stanley > > > >> On Fri, Mar 11, 2022 at 2:49 AM Tom Rini wrote: > >> > >>> On Wed, Dec 15, 2021 at 10:57:52AM +0800, Stanley Chu wrote: > >>> > >>> Add basic support for the Nuvoton NPCM845 BMC. > >>> > >>> Signed-off-by: Stanley Chu > >> > >> I see there's a number of outstanding questions to this first part of > >> the port. Can you please address them? Furthermore, the defconfig and > >> dts patches should be part of this first patch and the dts needs to be > >> in linux-next at least, if not a full linux kernel release. Thanks and > >> sorry for the delay here. > >> > >> -- > >> Tom >
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Hi Tom, We need time to prepare linux dts, can I send the rest of the drivers first or need to wait until the linux dts is submitted? Because I want to remove some unused nodes/properties away from linux dts to reduce dtb size, can we use different dts for uboot? Thanks a lot for your comments. -- Stanley On Fri, Mar 11, 2022 at 2:49 AM Tom Rini wrote: > > On Wed, Dec 15, 2021 at 10:57:52AM +0800, Stanley Chu wrote: > > > Add basic support for the Nuvoton NPCM845 BMC. > > > > Signed-off-by: Stanley Chu > > I see there's a number of outstanding questions to this first part of > the port. Can you please address them? Furthermore, the defconfig and > dts patches should be part of this first patch and the dts needs to be > in linux-next at least, if not a full linux kernel release. Thanks and > sorry for the delay here. > > -- > Tom
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Hi Jesse, Thanks for the comment, this will be addressed in the next patches. -- Stanley On Thu, Dec 16, 2021 at 6:16 AM Jesse Taube wrote: > > > > On 12/15/21 13:32, Sean Anderson wrote: > > On 12/14/21 9:57 PM, Stanley Chu wrote: > >> Add basic support for the Nuvoton NPCM845 BMC. > >> > >> Signed-off-by: Stanley Chu > >> --- > >>arch/arm/Kconfig | 9 + > >>arch/arm/Makefile | 1 + > >>arch/arm/include/asm/arch-npcm8xx/clock.h | 164 > >>arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++ > >>arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++ > >>arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 + > >>arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++ > >>arch/arm/mach-nuvoton/Kconfig | 24 ++ > >>arch/arm/mach-nuvoton/Makefile| 1 + > >>arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++ > >>arch/arm/mach-nuvoton/npcm8xx/Makefile| 1 + > >>arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 > >>arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 > >>board/nuvoton/arbel/Kconfig | 18 ++ > >>board/nuvoton/arbel/Makefile | 1 + > >>board/nuvoton/arbel/arbel.c | 33 +++ > >>include/configs/arbel.h | 54 > >>17 files changed, 924 insertions(+) > Hello World! > > Because I was CC'ed I guess I will keep myself up-to date. > This commit has 17 files changed and almost 1k insertions, > That is a relatively large commit. Would it be better to split > /arch/arm/include/asm > /arch/arm/mach-nuvoton > /board > /include/configs > into different commits. > I ask this because I split them for a patch I'm working on
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Hi Sean, Thank you for your comment, I've submitted a clk driver patch to address this. https://patchwork.ozlabs.org/project/uboot/patch/20220225075954.3965-1-ys...@nuvoton.com/ As for the reset controller, I will take reset-syscon driver for that. -- Stanley On Thu, Dec 16, 2021 at 2:32 AM Sean Anderson wrote: > > On 12/14/21 9:57 PM, Stanley Chu wrote: > > Add basic support for the Nuvoton NPCM845 BMC. > > > > Signed-off-by: Stanley Chu > > --- > > arch/arm/Kconfig | 9 + > > arch/arm/Makefile | 1 + > > arch/arm/include/asm/arch-npcm8xx/clock.h | 164 > > arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++ > > arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++ > > arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 + > > arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++ > > arch/arm/mach-nuvoton/Kconfig | 24 ++ > > arch/arm/mach-nuvoton/Makefile| 1 + > > arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++ > > arch/arm/mach-nuvoton/npcm8xx/Makefile| 1 + > > arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 > > arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 > > board/nuvoton/arbel/Kconfig | 18 ++ > > board/nuvoton/arbel/Makefile | 1 + > > board/nuvoton/arbel/arbel.c | 33 +++ > > include/configs/arbel.h | 54 > > 17 files changed, 924 insertions(+) > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h > > create mode 100644 arch/arm/mach-nuvoton/Kconfig > > create mode 100644 arch/arm/mach-nuvoton/Makefile > > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig > > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile > > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c > > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c > > create mode 100644 board/nuvoton/arbel/Kconfig > > create mode 100644 board/nuvoton/arbel/Makefile > > create mode 100644 board/nuvoton/arbel/arbel.c > > create mode 100644 include/configs/arbel.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index f7f03837fe..80ec42f6be 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64 > > select LINUX_KERNEL_IMAGE_HEADER > > select XEN_SERIAL > > select SSCANF > > + > > +config ARCH_NPCM > > + bool "Support Nuvoton SoCs" > > + select DM > > + select OF_CONTROL > > + imply CMD_DM > > + > > endchoice > > > > config SUPPORT_PASSING_ATAGS > > @@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig" > > > > source "arch/arm/mach-nexell/Kconfig" > > > > +source "arch/arm/mach-nuvoton/Kconfig" > > + > > source "board/armltd/total_compute/Kconfig" > > > > source "board/bosch/shc/Kconfig" > > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > > index ad757e982e..29a0250ab6 100644 > > --- a/arch/arm/Makefile > > +++ b/arch/arm/Makefile > > @@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal > > machine-$(CONFIG_ARCH_ZYNQ) += zynq > > machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp > > machine-$(CONFIG_ARCH_ZYNQMP_R5)+= zynqmp-r5 > > +machine-$(CONFIG_ARCH_NPCM) += nuvoton > > > > machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) > > > > diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h > > b/arch/arm/include/asm/arch-npcm8xx/clock.h > > new file mode 100644 > > index 00..088b536b7b > > --- /dev/null > > +++ b/arch/arm/include/asm/arch-npcm8xx/clock.h > > Please add this (and all the other includes) in the patches adding the > drivers which use them. This makes it much easier to review. > > Additionally, if these defines are not used elsewhere, they can be > included at the beginning of the clock driver itself. > > > @@ -0,0 +1,164 @@ > > +/* SPDX-License-Identifier: GPL-2.0+ */ > > +/* > > + * Copyright (c) 2021 Nuvoton Technology Corp. > > + */ > > + > > +#ifndef _NPCM_CLOCK_H_ > &
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Hi Giulio, Thank you for your comment, I've submitted a clk driver patch to address this. https://patchwork.ozlabs.org/project/uboot/patch/20220225075954.3965-1-ys...@nuvoton.com/ -- Stanley On Wed, Dec 15, 2021 at 8:12 PM Giulio Benetti wrote: > > Hi Stanley, > > On 15/12/21 03:57, Stanley Chu wrote: > > Add basic support for the Nuvoton NPCM845 BMC. > > > > Signed-off-by: Stanley Chu > > --- > > arch/arm/Kconfig | 9 + > > arch/arm/Makefile | 1 + > > arch/arm/include/asm/arch-npcm8xx/clock.h | 164 > > arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++ > > arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++ > > arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 + > > arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++ > > arch/arm/mach-nuvoton/Kconfig | 24 ++ > > arch/arm/mach-nuvoton/Makefile| 1 + > > arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++ > > arch/arm/mach-nuvoton/npcm8xx/Makefile| 1 + > > arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 > > Here ^^^ you setup timer, but it should be a separate driver IMHO. At > least this is what I've done for imxrt. > Same goes for clock, there is no clock driver and you setup spi clock > directly inside the same file with npcm_sysintf_init() while that should > be part of the clock driver. > > Also all defines regarding to clocks and peripherals should go into > their driver. > > > arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 > > Here you've mixed up the architecture(above) and the board(below) in a > single patch. > > > board/nuvoton/arbel/Kconfig | 18 ++ > > board/nuvoton/arbel/Makefile | 1 + > > board/nuvoton/arbel/arbel.c | 33 +++ > > include/configs/arbel.h | 54 > > arbel should be arbel-evk > > I stop here, because there could be big changes if others agree. > > Best regards > -- > Giulio Benetti > Benetti Engineering sas > > > 17 files changed, 924 insertions(+) > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h > > create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h > > create mode 100644 arch/arm/mach-nuvoton/Kconfig > > create mode 100644 arch/arm/mach-nuvoton/Makefile > > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig > > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile > > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c > > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c > > create mode 100644 board/nuvoton/arbel/Kconfig > > create mode 100644 board/nuvoton/arbel/Makefile > > create mode 100644 board/nuvoton/arbel/arbel.c > > create mode 100644 include/configs/arbel.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index f7f03837fe..80ec42f6be 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64 > > select LINUX_KERNEL_IMAGE_HEADER > > select XEN_SERIAL > > select SSCANF > > + > > +config ARCH_NPCM > > + bool "Support Nuvoton SoCs" > > + select DM > > + select OF_CONTROL > > + imply CMD_DM > > + > > endchoice > > > > config SUPPORT_PASSING_ATAGS > > @@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig" > > > > source "arch/arm/mach-nexell/Kconfig" > > > > +source "arch/arm/mach-nuvoton/Kconfig" > > + > > source "board/armltd/total_compute/Kconfig" > > > > source "board/bosch/shc/Kconfig" > > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > > index ad757e982e..29a0250ab6 100644 > > --- a/arch/arm/Makefile > > +++ b/arch/arm/Makefile > > @@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal > > machine-$(CONFIG_ARCH_ZYNQ) += zynq > > machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp > > machine-$(CONFIG_ARCH_ZYNQMP_R5)+= zynqmp-r5 > > +machine-$(CONFIG_ARCH_NPCM) += nuvoton > > > > machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) > > > > diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h > > b/arch/arm/include/asm/arch
Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Hi Sean, Thanks for the review. It is addressed in the gpio driver patch as below. https://patchwork.ozlabs.org/project/uboot/patch/20220225021450.18690-1-ys...@nuvoton.com/ -- Stanley On Thu, Dec 16, 2021 at 6:30 AM Sean Anderson wrote: > > On 12/15/21 5:16 PM, Jesse Taube wrote: > > > > > > On 12/15/21 13:32, Sean Anderson wrote: > >> On 12/14/21 9:57 PM, Stanley Chu wrote: > >>> Add basic support for the Nuvoton NPCM845 BMC. > >>> > >>> Signed-off-by: Stanley Chu > >>> --- > >>>arch/arm/Kconfig | 9 + > >>>arch/arm/Makefile | 1 + > >>>arch/arm/include/asm/arch-npcm8xx/clock.h | 164 > >>>arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++ > >>>arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++ > >>>arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 + > >>>arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++ > >>>arch/arm/mach-nuvoton/Kconfig | 24 ++ > >>>arch/arm/mach-nuvoton/Makefile| 1 + > >>>arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++ > >>>arch/arm/mach-nuvoton/npcm8xx/Makefile| 1 + > >>>arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 > >>>arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 > >>>board/nuvoton/arbel/Kconfig | 18 ++ > >>>board/nuvoton/arbel/Makefile | 1 + > >>>board/nuvoton/arbel/arbel.c | 33 +++ > >>>include/configs/arbel.h | 54 > >>>17 files changed, 924 insertions(+) > > Hello World! > > > > Because I was CC'ed I guess I will keep myself up-to date. > > This commit has 17 files changed and almost 1k insertions, > > That is a relatively large commit. Would it be better to split > > /arch/arm/include/asm > > /arch/arm/mach-nuvoton > > /board > > /include/configs > > into different commits. > > I ask this because I split them for a patch I'm working on > > Please submit the relevant headers with their drivers. > > For example, arch/arm/include/asm/arch-npcm8xx/gpio.h should go > in "[PATCH v1 5/9] gpio: npcm: Add support for Nuvoton NPCM SoCs" > > --Sean >
[PATCH v2] clk: nuvoton: Add support for NPCM845
Add clock controller driver for NPCM845
Signed-off-by: Stanley Chu
Reviewed-by: Sean Anderson
---
v2:
- simplify function arguments as comment by Sean Anderson
---
drivers/clk/Makefile | 1 +
drivers/clk/nuvoton/Makefile | 1 +
drivers/clk/nuvoton/clk_npcm8xx.c | 469 ++
.../dt-bindings/clock/nuvoton,npcm8xx-clock.h | 27 +
4 files changed, 498 insertions(+)
create mode 100644 drivers/clk/nuvoton/Makefile
create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c
create mode 100644 include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 711ae5bc29..21e60bae0c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_MESON) += meson/
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile
new file mode 100644
index 00..998e5329bb
--- /dev/null
+++ b/drivers/clk/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_NPCM8XX) += clk_npcm8xx.o
diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c
b/drivers/clk/nuvoton/clk_npcm8xx.c
new file mode 100644
index 00..6b8c54bb62
--- /dev/null
+++ b/drivers/clk/nuvoton/clk_npcm8xx.c
@@ -0,0 +1,469 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register offsets */
+#define CLKSEL 0x04/* clock source selection */
+#define CLKDIV10x08/* clock divider 1 */
+#define CLKDIV20x2C/* clock divider 2 */
+#define CLKDIV30x58/* clock divider 3 */
+#define PLLCON00x0C/* pll0 control */
+#define PLLCON10x10/* pll1 control */
+#define PLLCON20x54/* pll2 control */
+
+/* PLLCON bit filed */
+#define PLLCON_INDVGENMASK(5, 0)
+#define PLLCON_OTDV1 GENMASK(10, 8)
+#define PLLCON_OTDV2 GENMASK(15, 13)
+#define PLLCON_FBDVGENMASK(27, 16)
+
+/* CLKSEL bit filed */
+#define CPUCKSEL GENMASK(2, 0)
+#define SDCKSELGENMASK(7, 6)
+#define UARTCKSEL GENMASK(9, 8)
+
+/* CLKDIV1 bit filed */
+#define SPI3CKDIV GENMASK(10, 6)
+#define MMCCKDIV GENMASK(15, 11)
+#define UARTDIV1 GENMASK(20, 16)
+#define CLK4DIVGENMASK(27, 26)
+
+/* CLKDIV2 bit filed */
+#define APB5CKDIV GENMASK(23, 22)
+#define APB2CKDIV GENMASK(27, 26)
+
+/* CLKDIV3 bit filed */
+#define SPIXCKDIV GENMASK(5, 1)
+#define SPI0CKDIV GENMASK(10, 6)
+#define UARTDIV2 GENMASK(15, 11)
+#define SPI1CKDIV GENMASK(23, 16)
+
+/* Flags */
+#define DIV_TYPE1 BIT(0) /* div = clkdiv + 1 */
+#define DIV_TYPE2 BIT(1) /* div = 1 << clkdiv */
+#define PRE_DIV2 BIT(2) /* Pre divisor = 2 */
+#define POST_DIV2 BIT(3) /* Post divisor = 2 */
+#define FIXED_PARENT BIT(4) /* clock source is fixed */
+
+struct npcm_clk_priv {
+ void __iomem *base;
+};
+
+/* Parameters of PLL configuration */
+struct npcm_clk_pll {
+ const int id;
+ const int parent_id;
+ u32 reg;
+ u32 flags;
+};
+
+/* Parent clock id to clksel mapping */
+struct parent_data {
+ int id;
+ int clksel;
+};
+
+/* Parameters of parent selection */
+struct npcm_clk_select {
+ const int id;
+ const struct parent_data *parents;
+ u32 reg;
+ u32 mask;
+ u8 num_parents;
+ u32 flags;
+};
+
+/* Parameters of clock divider */
+struct npcm_clk_div {
+ const int id;
+ u32 reg;
+ u32 mask;
+ u32 flags;
+};
+
+/* Parent clock map */
+static const struct parent_data pll_parents[] = {
+ {NPCM8XX_CLK_PLL0, 0},
+ {NPCM8XX_CLK_PLL1, 1},
+ {NPCM8XX_CLK_REFCLK, 2},
+ {NPCM8XX_CLK_PLL2DIV2, 3}
+};
+
+static const struct parent_data cpuck_parents[] = {
+ {NPCM8XX_CLK_PLL0, 0},
+ {NPCM8XX_CLK_PLL1, 1},
+ {NPCM8XX_CLK_REFCLK, 2},
+ {NPCM8XX_CLK_PLL2, 7}
+};
+
+static const struct parent_data apb_parent[] = {{NPCM8XX_CLK_AHB, 0}};
+
+static struct npcm_clk_pll npcm8xx_clk_plls[] = {
+ {NPCM8XX_CLK_PLL0, NPCM8XX_CLK_REFCLK, PLLCON0, 0},
+ {NPCM8XX_CLK_PLL1, NPCM8XX_CLK_REFCLK, PLLCON1, 0},
+ {NPCM8XX_CLK_PLL2, NPCM8XX_CLK_REFCLK, PLLCON2, 0},
+ {NPCM8XX_CLK_PLL2DIV2, NPCM8XX_CLK_REFCLK, PLLCON2, POST_DIV2}
+};
+
+static struct npcm_clk_select npcm8xx_clk_selectors[] = {
+ {NPCM8XX_CLK_AHB, cpuck_parents, CLKSEL, CPUCKSEL, 4, 0},
+ {NPCM8XX_CLK_APB2, apb_parent, 0, 0, 1, FIXED_PARENT},
+ {NPCM8XX_CLK_APB5, apb_parent, 0, 0, 1, FIXED_PARENT},
+ {NPCM8XX_CL
[PATCH v1 1/1] gpio: npcm: Add support for Nuvoton NPCM SoCs
Add Nuvoton BMC NPCM7xx/NPCM8xx gpio driver
Signed-off-by: Stanley Chu
---
drivers/gpio/Kconfig | 7 +++
drivers/gpio/Makefile| 1 +
drivers/gpio/npcm_gpio.c | 123 +++
3 files changed, 131 insertions(+)
create mode 100644 drivers/gpio/npcm_gpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 8d0e47c67d..e1a1f1c4db 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -247,6 +247,13 @@ config MXS_GPIO
help
Support GPIO controllers on i.MX23 and i.MX28 platforms
+config NPCM_GPIO
+ bool "Nuvoton NPCM GPIO driver"
+ depends on DM_GPIO
+ help
+ Support GPIO controllers on Nuvovon NPCM SoCs.
+ NPCM7xx/NPCM8xx contain 8 GPIO banks, each bank contains 32 pins.
+
config OMAP_GPIO
bool "TI OMAP GPIO driver"
depends on ARCH_OMAP2PLUS
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 63e9be6034..a42ae77285 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_MARVELL_GPIO)+= mvgpio.o
obj-$(CONFIG_MCP230XX_GPIO)+= mcp230xx_gpio.o
obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
+obj-$(CONFIG_NPCM_GPIO)+= npcm_gpio.o
obj-$(CONFIG_PCA953X) += pca953x.o
obj-$(CONFIG_PCA9698) += pca9698.o
obj-$(CONFIG_ROCKCHIP_GPIO)+= rk_gpio.o
diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c
new file mode 100644
index 00..8afd57fa8e
--- /dev/null
+++ b/drivers/gpio/npcm_gpio.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+#define NPCM_GPIOS_PER_BANK32
+
+/* Register offsets */
+#define GPIO_DIN 0x4 /* RO - Data In */
+#define GPIO_DOUT 0xC /* RW - Data Out */
+#define GPIO_OE0x10/* RW - Output Enable */
+#define GPIO_IEM 0x58/* RW - Input Enable Mask */
+#define GPIO_OES 0x70/* WO - Output Enable Register Set */
+#define GPIO_OEC 0x74/* WO - Output Enable Register Clear */
+
+struct npcm_gpio_priv {
+ void __iomem *base;
+};
+
+static int npcm_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+
+ writel(BIT(offset), priv->base + GPIO_OEC);
+ setbits_le32(priv->base + GPIO_IEM, BIT(offset));
+
+ return 0;
+}
+
+static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+
+ clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
+ writel(BIT(offset), priv->base + GPIO_OES);
+
+ if (value)
+ setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
+ else
+ clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
+
+ return 0;
+}
+
+static int npcm_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+
+ if (readl(priv->base + GPIO_IEM) & BIT(offset))
+ return !!(readl(priv->base + GPIO_DIN) & BIT(offset));
+
+ if (readl(priv->base + GPIO_OE) & BIT(offset))
+ return !!(readl(priv->base + GPIO_DOUT) & BIT(offset));
+
+ return -EINVAL;
+}
+
+static int npcm_gpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+
+ if (value)
+ setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
+ else
+ clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
+
+ return 0;
+}
+
+static int npcm_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+
+ if (readl(priv->base + GPIO_IEM) & BIT(offset))
+ return GPIOF_INPUT;
+
+ if (readl(priv->base + GPIO_OE) & BIT(offset))
+ return GPIOF_OUTPUT;
+
+ return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops npcm_gpio_ops = {
+ .direction_input= npcm_gpio_direction_input,
+ .direction_output = npcm_gpio_direction_output,
+ .get_value = npcm_gpio_get_value,
+ .set_value = npcm_gpio_set_value,
+ .get_function = npcm_gpio_get_function,
+};
+
+static int npcm_gpio_probe(struct udevice *dev)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ uc_priv->gpio_count = NPCM_GPIOS_PER_BANK;
+ uc_priv->bank_name = dev->name;
+
+ return 0;
+}
+
+
[PATCH v1 1/1] clk: nuvoton: Add support for NPCM845
Add clock controller driver for NPCM845
Signed-off-by: Stanley Chu
---
drivers/clk/Makefile | 1 +
drivers/clk/nuvoton/Makefile | 1 +
drivers/clk/nuvoton/clk_npcm8xx.c | 470 ++
.../dt-bindings/clock/nuvoton,npcm8xx-clock.h | 27 +
4 files changed, 499 insertions(+)
create mode 100644 drivers/clk/nuvoton/Makefile
create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c
create mode 100644 include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 711ae5bc29..21e60bae0c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_MESON) += meson/
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile
new file mode 100644
index 00..998e5329bb
--- /dev/null
+++ b/drivers/clk/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_NPCM8XX) += clk_npcm8xx.o
diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c
b/drivers/clk/nuvoton/clk_npcm8xx.c
new file mode 100644
index 00..cdb5af5d9f
--- /dev/null
+++ b/drivers/clk/nuvoton/clk_npcm8xx.c
@@ -0,0 +1,470 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register offsets */
+#define CLKSEL 0x04/* clock source selection */
+#define CLKDIV10x08/* clock divider 1 */
+#define CLKDIV20x2C/* clock divider 2 */
+#define CLKDIV30x58/* clock divider 3 */
+#define PLLCON00x0C/* pll0 control */
+#define PLLCON10x10/* pll1 control */
+#define PLLCON20x54/* pll2 control */
+
+/* PLLCON bit filed */
+#define PLLCON_INDVGENMASK(5, 0)
+#define PLLCON_OTDV1 GENMASK(10, 8)
+#define PLLCON_OTDV2 GENMASK(15, 13)
+#define PLLCON_FBDVGENMASK(27, 16)
+
+/* CLKSEL bit filed */
+#define CPUCKSEL GENMASK(2, 0)
+#define SDCKSELGENMASK(7, 6)
+#define UARTCKSEL GENMASK(9, 8)
+
+/* CLKDIV1 bit filed */
+#define SPI3CKDIV GENMASK(10, 6)
+#define MMCCKDIV GENMASK(15, 11)
+#define UARTDIV1 GENMASK(20, 16)
+#define CLK4DIVGENMASK(27, 26)
+
+/* CLKDIV2 bit filed */
+#define APB5CKDIV GENMASK(23, 22)
+#define APB2CKDIV GENMASK(27, 26)
+
+/* CLKDIV3 bit filed */
+#define SPIXCKDIV GENMASK(5, 1)
+#define SPI0CKDIV GENMASK(10, 6)
+#define UARTDIV2 GENMASK(15, 11)
+#define SPI1CKDIV GENMASK(23, 16)
+
+/* Flags */
+#define DIV_TYPE1 BIT(0) /* div = clkdiv + 1 */
+#define DIV_TYPE2 BIT(1) /* div = 1 << clkdiv */
+#define PRE_DIV2 BIT(2) /* Pre divisor = 2 */
+#define POST_DIV2 BIT(3) /* Post divisor = 2 */
+#define FIXED_PARENT BIT(4) /* clock source is fixed */
+
+struct npcm_clk_priv {
+ struct udevice *dev;
+ void __iomem *base;
+};
+
+/* Parameters of PLL configuration */
+struct npcm_clk_pll {
+ const int id;
+ const int parent_id;
+ u32 reg;
+ u32 flags;
+};
+
+/* Parent clock id to clksel mapping */
+struct parent_data {
+ int id;
+ int clksel;
+};
+
+/* Parameters of parent selection */
+struct npcm_clk_select {
+ const int id;
+ const struct parent_data *parents;
+ u32 reg;
+ u32 mask;
+ u8 num_parents;
+ u32 flags;
+};
+
+/* Parameters of clock divider */
+struct npcm_clk_div {
+ const int id;
+ u32 reg;
+ u32 mask;
+ u32 flags;
+};
+
+/* Parent clock map */
+static const struct parent_data pll_parents[] = {
+ {NPCM8XX_CLK_PLL0, 0},
+ {NPCM8XX_CLK_PLL1, 1},
+ {NPCM8XX_CLK_REFCLK, 2},
+ {NPCM8XX_CLK_PLL2DIV2, 3}
+};
+
+static const struct parent_data cpuck_parents[] = {
+ {NPCM8XX_CLK_PLL0, 0},
+ {NPCM8XX_CLK_PLL1, 1},
+ {NPCM8XX_CLK_REFCLK, 2},
+ {NPCM8XX_CLK_PLL2, 7}
+};
+
+static const struct parent_data apb_parent[] = {{NPCM8XX_CLK_AHB, 0}};
+
+static struct npcm_clk_pll npcm8xx_clk_plls[] = {
+ {NPCM8XX_CLK_PLL0, NPCM8XX_CLK_REFCLK, PLLCON0, 0},
+ {NPCM8XX_CLK_PLL1, NPCM8XX_CLK_REFCLK, PLLCON1, 0},
+ {NPCM8XX_CLK_PLL2, NPCM8XX_CLK_REFCLK, PLLCON2, 0},
+ {NPCM8XX_CLK_PLL2DIV2, NPCM8XX_CLK_REFCLK, PLLCON2, POST_DIV2}
+};
+
+static struct npcm_clk_select npcm8xx_clk_selectors[] = {
+ {NPCM8XX_CLK_AHB, cpuck_parents, CLKSEL, CPUCKSEL, 4, 0},
+ {NPCM8XX_CLK_APB2, apb_parent, 0, 0, 1, FIXED_PARENT},
+ {NPCM8XX_CLK_APB5, apb_parent, 0, 0, 1, FIXED_PARENT},
+ {NPCM8XX_CLK_SPI0, apb_parent, 0, 0, 1, FIXED_PARENT},
+ {NPCM8XX_CL
[PATCH v3 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs
Enable a periodic timer on NPCM SoCs and implement
the get_count timer ops.
Signed-off-by: Stanley Chu
---
v3:
- use driver data for clock setting on different chips
- remove unnecessary code of zeroing priv variables
- more help description in Kconfig
v2:
- calculate the prescale value, not hardcode
---
drivers/timer/Kconfig | 9 +++
drivers/timer/Makefile | 1 +
drivers/timer/npcm-timer.c | 115 +
3 files changed, 125 insertions(+)
create mode 100644 drivers/timer/npcm-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 8913142654..abcc736492 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -143,6 +143,15 @@ config NOMADIK_MTU_TIMER
The MTU provides 4 decrementing free-running timers.
At the moment, only the first timer is used by the driver.
+config NPCM_TIMER
+ bool "Nuvoton NPCM timer support"
+ depends on TIMER
+ help
+ Select this to enable a timer on Nuvoton NPCM SoCs.
+ NPCM timer module has 5 down-counting timers, only the first timer
+ is used to implement timer ops. No support for early timer and
+ boot timer.
+
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index e2bd530eb0..39bda1ea79 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER)+= nomadik-mtu-timer.o
+obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
new file mode 100644
index 00..4562a6f231
--- /dev/null
+++ b/drivers/timer/npcm-timer.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NPCM_TIMER_CLOCK_RATE 100UL /* 1MHz timer */
+#define NPCM_TIMER_INPUT_RATE 2500UL /* Rate of input clock
*/
+#define NPCM_TIMER_TDR_MASKGENMASK(23, 0)
+#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
+
+/* Register offsets */
+#define TCR0 0x0 /* Timer Control and Status Register */
+#define TICR0 0x8 /* Timer Initial Count Register */
+#define TDR0 0x10/* Timer Data Register */
+
+/* TCR fields */
+#define TCR_MODE_PERIODIC BIT(27)
+#define TCR_EN BIT(30)
+#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE
- 1)
+
+enum input_clock_type {
+ INPUT_CLOCK_FIXED, /* input clock rate is fixed */
+ INPUT_CLOCK_NON_FIXED
+};
+
+/**
+ * struct npcm_timer_priv - private data for npcm timer driver
+ * npcm timer is a 24-bits down-counting timer.
+ *
+ * @last_count: last hw counter value
+ * @counter: the value to be returned for get_count ops
+ */
+struct npcm_timer_priv {
+ void __iomem *base;
+ u32 last_count;
+ u64 counter;
+};
+
+static u64 npcm_timer_get_count(struct udevice *dev)
+{
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ /* The timer is counting down */
+ val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
+ if (val <= priv->last_count)
+ priv->counter += priv->last_count - val;
+ else
+ priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 -
val);
+ priv->last_count = val;
+
+ return priv->counter;
+}
+
+static int npcm_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ enum input_clock_type type = dev_get_driver_data(dev);
+ struct clk clk;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+ uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
+
+ if (type == INPUT_CLOCK_NON_FIXED) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /*
+* Configure timer and start
+* periodic mode
+* timer clock rate = input clock / prescale
+*/
+ writel(0, priv->base + TCR0);
+ writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
+ writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE,
+ priv->b
[PATCH v2 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs
This driver enables a periodic timer on NPCM SoCs and
implements the get_count timer ops.
Signed-off-by: Stanley Chu
---
Changes in v2:
calculate the prescale value, not hardcode.
---
drivers/timer/Kconfig | 6 ++
drivers/timer/Makefile | 1 +
drivers/timer/npcm-timer.c | 110 +
3 files changed, 117 insertions(+)
create mode 100644 drivers/timer/npcm-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 8913142654..f22c46f44e 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -143,6 +143,12 @@ config NOMADIK_MTU_TIMER
The MTU provides 4 decrementing free-running timers.
At the moment, only the first timer is used by the driver.
+config NPCM_TIMER
+ bool "Nuvoton NPCM timer support"
+ depends on TIMER
+ help
+ Select this to enable a timer on Nuvoton NPCM SoCs.
+
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index e2bd530eb0..39bda1ea79 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER)+= nomadik-mtu-timer.o
+obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
new file mode 100644
index 00..65727e41a4
--- /dev/null
+++ b/drivers/timer/npcm-timer.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NPCM_TIMER_CLOCK_RATE 100UL /* 1MHz timer */
+#define NPCM_TIMER_INPUT_RATE 2500UL /* Rate of input clock
*/
+#define NPCM_TIMER_TDR_MASKGENMASK(23, 0)
+#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
+
+/* Register offsets */
+#define TCR0 0x0 /* Timer Control and Status Register */
+#define TICR0 0x8 /* Timer Initial Count Register */
+#define TDR0 0x10/* Timer Data Register */
+
+/* TCR fields */
+#define TCR_MODE_PERIODIC BIT(27)
+#define TCR_EN BIT(30)
+#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE
- 1)
+
+/*
+ * 24-bits down-counting hw timer.
+ * last_count: last hw counter value.
+ * counter: the value to be returned for get_count ops.
+ */
+struct npcm_timer_priv {
+ void __iomem *base;
+ u32 last_count;
+ u64 counter;
+};
+
+static u64 npcm_timer_get_count(struct udevice *dev)
+{
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ /* The timer is couting down */
+ val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
+ if (val <= priv->last_count)
+ priv->counter += priv->last_count - val;
+ else
+ priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 -
val);
+ priv->last_count = val;
+
+ return priv->counter;
+}
+
+static int npcm_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+ priv->counter = 0;
+ priv->last_count = 0;
+ uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
+
+ if (IS_ENABLED(CONFIG_ARCH_NPCM750)) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /*
+* Configure timer and start
+* periodic mode
+* input clock freq = 25Mhz
+* timer clock rate = input clock / prescale
+*/
+ writel(0, priv->base + TCR0);
+ writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
+ writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE,
+ priv->base + TCR0);
+
+ return 0;
+}
+
+static const struct timer_ops npcm_timer_ops = {
+ .get_count = npcm_timer_get_count,
+};
+
+static const struct udevice_id npcm_timer_ids[] = {
+ { .compatible = "nuvoton,npcm845-timer" },
+ { .compatible = "nuvoton,npcm750-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(npcm_timer) = {
+ .name = "npcm_timer",
+ .id = UCLASS_TIMER,
+ .of_match = npcm_timer_ids,
+ .priv_auto
[PATCH v1 1/1] timer: npcm: Add driver for Nuvoton NPCM SoCs
This driver enables a periodic timer on NPCM SoCs and
implements the get_count timer ops.
Signed-off-by: Stanley Chu
---
drivers/timer/Kconfig | 6 ++
drivers/timer/Makefile | 1 +
drivers/timer/npcm-timer.c | 111 +
3 files changed, 118 insertions(+)
create mode 100644 drivers/timer/npcm-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 8913142654..f22c46f44e 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -143,6 +143,12 @@ config NOMADIK_MTU_TIMER
The MTU provides 4 decrementing free-running timers.
At the moment, only the first timer is used by the driver.
+config NPCM_TIMER
+ bool "Nuvoton NPCM timer support"
+ depends on TIMER
+ help
+ Select this to enable a timer on Nuvoton NPCM SoCs.
+
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index e2bd530eb0..39bda1ea79 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER)+= nomadik-mtu-timer.o
+obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
new file mode 100644
index 00..f7d95d4bfa
--- /dev/null
+++ b/drivers/timer/npcm-timer.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NPCM_TIMER_CLOCK_RATE 100UL /* 1MHz timer */
+#define NPCM_TIMER_INPUT_RATE 2500UL /* Rate of input clock
*/
+#define NPCM_TIMER_TDR_MASKGENMASK(23, 0)
+#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
+
+/* Register offsets */
+#define TCR0 0x0 /* Timer Control and Status Register */
+#define TICR0 0x8 /* Timer Initial Count Register */
+#define TDR0 0x10/* Timer Data Register */
+
+/* TCR fields */
+#define TCR_MODE_PERIODIC BIT(27)
+#define TCR_EN BIT(30)
+#define TCR_PRESCALE_25(25 - 1)
+
+/*
+ * 24-bits down-counting hw timer.
+ * last_count: last hw counter value.
+ * counter: the value to be returned for get_count ops.
+ */
+struct npcm_timer_priv {
+ void __iomem *base;
+ u32 last_count;
+ u64 counter;
+};
+
+static u64 npcm_timer_get_count(struct udevice *dev)
+{
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ /* The timer is couting down */
+ val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
+ if (val <= priv->last_count)
+ priv->counter += priv->last_count - val;
+ else
+ priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 -
val);
+ priv->last_count = val;
+
+ return priv->counter;
+}
+
+static int npcm_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+ priv->counter = 0;
+ priv->last_count = 0;
+ uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
+
+ if (IS_ENABLED(CONFIG_ARCH_NPCM750)) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /*
+* Configure timer and start
+* periodic mode
+* input clock freq = 25Mhz
+* prescale = 25
+* timer clock rate = 25Mhz/25
+*/
+ writel(0, priv->base + TCR0);
+ writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
+ writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE_25,
+ priv->base + TCR0);
+
+ return 0;
+}
+
+static const struct timer_ops npcm_timer_ops = {
+ .get_count = npcm_timer_get_count,
+};
+
+static const struct udevice_id npcm_timer_ids[] = {
+ { .compatible = "nuvoton,npcm845-timer" },
+ { .compatible = "nuvoton,npcm750-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(npcm_timer) = {
+ .name = "npcm_timer",
+ .id = UCLASS_TIMER,
+ .of_match = npcm_timer_ids,
+ .priv_auto = sizeof(struct npcm_timer_priv),
+ .probe = npcm_timer_probe,
+ .ops= &npcm_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.17.1
[PATCH v2 1/1] serial: npcm: Add support for Nuvoton NPCM SoCs
Add Nuvoton BMC NPCM7xx/NPCM8xx uart driver
Signed-off-by: Stanley Chu
---
Changes in v2:
Drop unnecessary outer brackets.
Return -EAGAIN if not ready for tx/rx.
Add comments.
---
drivers/serial/Kconfig | 9 +++
drivers/serial/Makefile | 1 +
drivers/serial/serial_npcm.c | 150 +++
3 files changed, 160 insertions(+)
create mode 100644 drivers/serial/serial_npcm.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 6c8fdda9a0..e67a76a424 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -920,6 +920,15 @@ config MPC8XX_CONS
depends on MPC8xx
default y
+config NPCM_SERIAL
+ bool "UART driver for Nuvoton NPCM BMC"
+ depends on DM_SERIAL
+ help
+ Select this to enable UART support for Nuvoton BMCs
+ (NPCM7xx and NPCM8xx).
+ The driver enables the onboard serial port with 8-N-1
+ configuration.
+
config XEN_SERIAL
bool "XEN serial support"
depends on XEN
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8168af640f..866495e416 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o
+obj-$(CONFIG_NPCM_SERIAL) += serial_npcm.o
obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
obj-$(CONFIG_XEN_SERIAL) += serial_xen.o
diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c
new file mode 100644
index 00..0c6f0410cf
--- /dev/null
+++ b/drivers/serial/serial_npcm.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+struct npcm_uart {
+ union {
+ u32 rbr;/* Receive Buffer Register */
+ u32 thr;/* Transmit Holding Register */
+ u32 dll;/* Divisor Latch (Low Byte) Register */
+ };
+ union {
+ u32 ier;/* Interrupt Enable Register */
+ u32 dlm;/* Divisor Latch (Low Byte) Register */
+ };
+ union {
+ u32 iir;/* Interrupt Identification Register */
+ u32 fcr;/* FIFO Control Register */
+ };
+ u32 lcr;/* Line Control Register */
+ u32 mcr;/* Modem Control Register */
+ u32 lsr;/* Line Status Control Register */
+ u32 msr;/* Modem Status Register */
+ u32 tor;/* Timeout Register */
+};
+
+#defineLCR_WLS_8BITS 3 /* 8-bit word length select */
+#defineFCR_TFR BIT(2) /* TxFIFO reset */
+#defineFCR_RFR BIT(1) /* RxFIFO reset */
+#defineFCR_FME BIT(0) /* FIFO mode enable */
+#defineLSR_THREBIT(5) /* Status of TxFIFO empty */
+#defineLSR_RFDRBIT(0) /* Status of RxFIFO data ready */
+#defineLCR_DLABBIT(7) /* Divisor latch access bit */
+
+struct npcm_serial_plat {
+ struct npcm_uart *reg;
+ u32 uart_clk; /* frequency of uart clock source */
+};
+
+static int npcm_serial_pending(struct udevice *dev, bool input)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *uart = plat->reg;
+
+ if (input)
+ return readb(&uart->lsr) & LSR_RFDR ? 1 : 0;
+ else
+ return readb(&uart->lsr) & LSR_THRE ? 0 : 1;
+}
+
+static int npcm_serial_putc(struct udevice *dev, const char ch)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *uart = plat->reg;
+
+ if (!(readb(&uart->lsr) & LSR_THRE))
+ return -EAGAIN;
+
+ writeb(ch, &uart->thr);
+
+ return 0;
+}
+
+static int npcm_serial_getc(struct udevice *dev)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *uart = plat->reg;
+
+ if (!(readb(&uart->lsr) & LSR_RFDR))
+ return -EAGAIN;
+
+ return readb(&uart->rbr);
+}
+
+static int npcm_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *uart = plat->reg;
+ u16 divisor;
+
+ /* BaudOut = UART Clock / (16 * [Divisor + 2]) */
+ divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2;
+
+ setbits_8(&uart->lcr, LCR_DLAB);
+ writeb(divisor & 0xff, &uart->dll);
+ writeb(divisor >> 8, &uart->dlm);
+ clrbits_8(&uart->lcr, LCR_DLAB);
+
+ return 0;
+}
+
+static int npcm_serial_probe(struct udevice *dev)
+{
+ struct npcm_serial_pl
[PATCH v1] serial: npcm: Add support for Nuvoton NPCM SoCs
Add Nuvoton BMC NPCM7xx/NPCM8xx uart driver
Signed-off-by: Stanley Chu
---
drivers/serial/Kconfig | 7 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_npcm.c | 151 +++
3 files changed, 159 insertions(+)
create mode 100644 drivers/serial/serial_npcm.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 6c8fdda9a0..8daaef61b3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -920,6 +920,13 @@ config MPC8XX_CONS
depends on MPC8xx
default y
+config NPCM_SERIAL
+ bool "UART driver for Nuvoton NPCM BMC"
+ depends on DM_SERIAL
+ help
+ Select this to enable UART support for Nuvoton BMCs
+ (NPCM7xx and NPCM8xx)
+
config XEN_SERIAL
bool "XEN serial support"
depends on XEN
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8168af640f..866495e416 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o
+obj-$(CONFIG_NPCM_SERIAL) += serial_npcm.o
obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
obj-$(CONFIG_XEN_SERIAL) += serial_xen.o
diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c
new file mode 100644
index 00..67343e5805
--- /dev/null
+++ b/drivers/serial/serial_npcm.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+struct npcm_uart {
+ union {
+ u32 rbr;
+ u32 thr;
+ u32 dll;
+ };
+ union {
+ u32 ier;
+ u32 dlm;
+ };
+ union {
+ u32 iir;
+ u32 fcr;
+ };
+ u32 lcr;
+ u32 mcr;
+ u32 lsr;
+ u32 msr;
+ u32 tor;
+};
+
+#define LCR_WLS_8BITS 3
+#defineFCR_TFR BIT(2)
+#defineFCR_RFR BIT(1)
+#defineFCR_FME BIT(0)
+#defineLSR_THREBIT(5)
+#defineLSR_RFDRBIT(0)
+#defineLCR_DLABBIT(7)
+
+struct npcm_serial_plat {
+ struct npcm_uart *reg;
+ u32 uart_clk;
+};
+
+static int npcm_serial_pending(struct udevice *dev, bool input)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *uart = plat->reg;
+
+ if (input)
+ return (readb(&uart->lsr) & LSR_RFDR);
+ else
+ return !(readb(&uart->lsr) & LSR_THRE);
+}
+
+static int npcm_serial_putc(struct udevice *dev, const char ch)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *uart = plat->reg;
+
+ while (!(readb(&uart->lsr) & LSR_THRE))
+ ;
+
+ writeb(ch, &uart->thr);
+
+ return 0;
+}
+
+static int npcm_serial_getc(struct udevice *dev)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *uart = plat->reg;
+
+ while (!(readb(&uart->lsr) & LSR_RFDR))
+ ;
+
+ return readb(&uart->rbr);
+}
+
+static int npcm_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *uart = plat->reg;
+ u16 divisor;
+
+ /* BaudOut = UART Clock / (16 * [Divisor + 2]) */
+ divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2;
+
+ setbits_8(&uart->lcr, LCR_DLAB);
+ writeb(divisor & 0xff, &uart->dll);
+ writeb(divisor >> 8, &uart->dlm);
+ clrbits_8(&uart->lcr, LCR_DLAB);
+
+ return 0;
+}
+
+static int npcm_serial_probe(struct udevice *dev)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *uart = plat->reg;
+ struct clk clk;
+ u32 freq;
+ int ret;
+
+ plat->reg = dev_read_addr_ptr(dev);
+ freq = dev_read_u32_default(dev, "clock-frequency", 0);
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ printf("Cannot get clk for uart\n");
+ return ret;
+ }
+ ret = clk_set_rate(&clk, freq);
+ if (ret < 0)
+ return ret;
+ plat->uart_clk = ret;
+
+ /* Disable all interrupt */
+ writeb(0, &uart->ier);
+
+ /* Set 8 bit, 1 stop, no parity */
+ writeb(LCR_WLS_8BITS, &uart->lcr);
+
+ /* Reset RX/TX FIFO */
+ writeb(FCR_FME | FCR_RFR | FCR_TFR, &uart->fcr);
+
+ return 0;
+}
+
+static const struct dm_serial_ops npcm_serial_ops = {
+ .getc = npcm_serial_getc
[PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree
Add a common device tree for all Nuvoton NPCM8xx BMCs and a board
specific device tree for the NPCM845(Arbel) evaluation board.
Signed-off-by: Stanley Chu
---
arch/arm/dts/Makefile |2 +
arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 598 ++
arch/arm/dts/nuvoton-npcm845-evb.dts | 264 +++
arch/arm/dts/nuvoton-npcm845-pincfg.dtsi | 2007 +
arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi | 623 +++
5 files changed, 3494 insertions(+)
create mode 100644 arch/arm/dts/nuvoton-common-npcm8xx.dtsi
create mode 100644 arch/arm/dts/nuvoton-npcm845-evb.dts
create mode 100644 arch/arm/dts/nuvoton-npcm845-pincfg.dtsi
create mode 100644 arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7f622fedbd..b866d488c5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1162,6 +1162,8 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) +=
imx8mm-cl-iot-gate-optee.dtb
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
+dtb-$(CONFIG_TARGET_ARBEL_EVB) += nuvoton-npcm845-evb.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
new file mode 100644
index 00..175c8af878
--- /dev/null
+++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
@@ -0,0 +1,598 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+#include "nuvoton-npcm8xx-pinctrl.dtsi"
+
+/ {
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clks: clock-control@f0801000 {
+ compatible = "nuvoton,npcm845-clock";
+ #clock-cells = <1>;
+ reg = <0x0 0xf0801000 0x0 0x70>;
+ u-boot,dm-pre-reloc;
+ };
+
+ serial0: serial0@f000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <2400>;
+ status = "disabled";
+ };
+
+ serial1: serial1@f0001000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0001000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <2400>;
+ status = "disabled";
+ };
+
+ serial2: serial2@f0002000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0002000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <2400>;
+ status = "disabled";
+ };
+
+ serial3: serial3@f0003000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0003000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <2400>;
+ status = "disabled";
+ };
+
+ serial4: serial4@f0004000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0004000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <2400>;
+ status = "disabled";
+ };
+
+ serial5: serial5@f0005000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0005000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <2400>;
+ status = "disabled";
+ };
+
+ serial6: serial6@f0006000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0006000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <2400>;
+ status = "disabled";
+ };
+
+ timer0: timer@f0008000 {
+ compatible = "nuvoton,npcm845-timer";
+ reg = <0x0 0xF0008000 0x0 0x100>;
+ clock-frequency = <2500>;
+ };
+
+ fiu0: fiu0@fb00 {
+ compatible = "nuvoton,npcm845-fiu";
+ reg = <0x0 0xfb00 0x0 0x1000>;
+ spi-max-frequency = <6600>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0cs1_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ fiu1: fiu1@fb002000 {
+ compatible = "nuvoton,npcm845-fiu";
+ reg = <0x0 0xfb002000 0x0 0x1000>;
+ spi-max-frequency = <5000>;
+ pinctrl-names = "default";
+ pin
[PATCH v1 9/9] ARM: configs: Add defconfig for Nuvoton NPCM845
Add defconfig for NPCM845 EVB (Arbel). Signed-off-by: Stanley Chu --- board/nuvoton/arbel/MAINTAINERS | 7 +++ configs/arbel_evb_defconfig | 77 + 2 files changed, 84 insertions(+) create mode 100644 board/nuvoton/arbel/MAINTAINERS create mode 100644 configs/arbel_evb_defconfig diff --git a/board/nuvoton/arbel/MAINTAINERS b/board/nuvoton/arbel/MAINTAINERS new file mode 100644 index 00..1086401f7d --- /dev/null +++ b/board/nuvoton/arbel/MAINTAINERS @@ -0,0 +1,7 @@ +Arbel EVB +M: Stanley Chu +M: Medad Cchien +S: Maintained +F: board/nuvoton/arbel/ +F: include/configs/arbel.h +F: configs/arbel_evb_defconfig diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig new file mode 100644 index 00..6efb72391a --- /dev/null +++ b/configs/arbel_evb_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_NPCM=y +CONFIG_ARCH_NPCM8XX=y +CONFIG_TARGET_ARBEL_EVB=y +CONFIG_SYS_TEXT_BASE=0x8000 +CONFIG_SYS_LOAD_ADDR=0x1000 +CONFIG_SYS_PROMPT="U-Boot>" +CONFIG_SYS_MALLOC_LEN=0x24 +CONFIG_SYS_MEMTEST_END=0x0800 +CONFIG_SYS_MEMTEST_START=0 +CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm845-evb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_OFFSET=0x10 +CONFIG_ENV_SIZE=0x4 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_ENV_ADDR=0x8010 +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_PARTITIONS=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_NPCM_SERIAL=y +CONFIG_TIMER=y +CONFIG_NPCM_TIMER=y +CONFIG_CLK=y +CONFIG_CMD_UUID=y +CONFIG_CMD_SAVEENV=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_NPCM8XX=y +CONFIG_PINCONF=y +CONFIG_DM_GPIO=y +CONFIG_NPCM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CMD_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_NEW=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_CMD_FAT=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NPCM_FIU_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_CMD_SF=y +CONFIG_CMD_MEMORY=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_SPI=y +CONFIG_CMD_PING=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_RGMII=y +CONFIG_MII=y +# CONFIG_EFI is not set +# CONFIG_EFI_LOADER is not set +# CONFIG_ENV_IS_IN_FLASH is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_PSCI_RESET is not set +# CONFIG_INPUT is not set -- 2.17.1
[PATCH v1 6/9] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support. Signed-off-by: Stanley Chu --- drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig |6 + drivers/pinctrl/nuvoton/Makefile |1 + drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2042 + 5 files changed, 2051 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 30eaa376c8..276b7aaa56 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -313,5 +313,6 @@ source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" endmenu diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 05b71f2f13..2c19eb00f5 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -29,3 +29,4 @@ obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o obj-$(CONFIG_PINCTRL_STM32)+= pinctrl_stm32.o obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-y += broadcom/ +obj-$(CONFIG_PINCTRL_NPCM8XX) += nuvoton/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index 00..e7063f13ab --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,6 @@ +config PINCTRL_NPCM8XX + bool "Pinctrl and GPIO driver for Nuvoton NPCM8XX" + depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX + help + Say Y here to enable pin controller and GPIO support + for Nuvoton NPCM8xx SoCs. diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index 00..b05aa62d33 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1 @@ + obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c new file mode 100644 index 00..0252e80312 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -0,0 +1,2042 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Nuvoton Technology Corp. + * Author: Joseph Liu + * Author: Tomer Maimon + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR registers */ +#define NPCM8XX_GCR_PDID 0x00 +#define NPCM8XX_GCR_SRCNT 0x68 +#define NPCM8XX_GCR_FLOCKR10x74 +#define NPCM8XX_GCR_DSCNT 0x78 +#define NPCM8XX_GCR_INTCR4 0xC0 +#define NPCM8XX_GCR_I2CSEGCTL 0xE4 +#define NPCM8XX_GCR_I2CSEGSEL 0xE0 +#define NPCM8XX_GCR_MFSEL1 0x260 +#define NPCM8XX_GCR_MFSEL2 0x264 +#define NPCM8XX_GCR_MFSEL3 0x268 +#define NPCM8XX_GCR_MFSEL4 0x26C +#define NPCM8XX_GCR_MFSEL5 0x270 +#define NPCM8XX_GCR_MFSEL6 0x274 +#define NPCM8XX_GCR_MFSEL7 0x278 +#define NPCM8XX_GCR_MFSEL7 0x278 + +#define SRCNT_ESPI BIT(3) + +/* reset registers */ +#define NPCM8XX_RST_WD0RCR 0x38 +#define NPCM8XX_RST_WD1RCR 0x3C +#define NPCM8XX_RST_WD2RCR 0x40 +#define NPCM8XX_RST_SWRSTC10x44 +#define NPCM8XX_RST_SWRSTC20x48 +#define NPCM8XX_RST_SWRSTC30x4C +#define NPCM8XX_RST_SWRSTC40x50 +#define NPCM8XX_RST_CORSTC 0x5C + +#define GPIOX_MODULE_RESET 16 +#define CA9C_MODULE_RESET BIT(0) + +/* GPIO registers */ +#define NPCM8XX_GP_N_TLOCK10x00 +#define NPCM8XX_GP_N_DIN 0x04 /* Data IN */ +#define NPCM8XX_GP_N_POL 0x08 /* Polarity */ +#define NPCM8XX_GP_N_DOUT 0x0c /* Data OUT */ +#define NPCM8XX_GP_N_OE0x10 /* Output Enable */ +#define NPCM8XX_GP_N_OTYP 0x14 +#define NPCM8XX_GP_N_MP0x18 +#define NPCM8XX_GP_N_PU0x1c /* Pull-up */ +#define NPCM8XX_GP_N_PD0x20 /* Pull-down */ +#define NPCM8XX_GP_N_DBNC 0x24 /* Debounce */ +#define NPCM8XX_GP_N_EVTYP 0x28 /* Event Type */ +#define NPCM8XX_GP_N_EVBE 0x2c /* Event Both Edge */ +#define NPCM8XX_GP_N_OBL0 0x30 +#define NPCM8XX_GP_N_OBL1 0x34 +#define NPCM8XX_GP_N_OBL2 0x38 +#define NPCM8XX_GP_N_OBL3 0x3c +#define NPCM8XX_GP_N_EVEN 0x40 /* Event Enable */ +#define NPCM8XX_GP_N_EVENS 0x44 /* Event Set (enable) */ +#define NPCM8XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ +#define NPCM8XX_GP_N_EVST 0x4c /* Event Status */ +#define NPCM8XX_GP_N_SPLCK 0x50 +#define NPCM8XX_GP_N_MPLCK 0x54 +#define NPCM8XX_GP_N_IEM 0x58 /* Input Enable */ +#define NPCM8XX_GP_N_OSRC 0x5c +#define NPCM8XX_GP_N_ODSC 0x60 +#define NPCM8XX_GP_N_DOS 0x68 /* Data OUT Set */ +#define NPCM8XX_G
[PATCH v1 7/9] spi: npcm-fiu: add NPCM8xx FIU controller driver
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master
controller driver using SPI-MEM interface.
The FIU supports single, dual or quad communication interface.
The FIU controller driver provides flash access in UMA(User
Mode Access) mode by using an indirect address/data mechanism.
Signed-off-by: Stanley Chu
---
arch/arm/include/asm/arch-npcm8xx/fiu.h | 61 +
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile| 1 +
drivers/spi/npcm_fiu_spi.c | 311
4 files changed, 379 insertions(+)
create mode 100644 arch/arm/include/asm/arch-npcm8xx/fiu.h
create mode 100644 drivers/spi/npcm_fiu_spi.c
diff --git a/arch/arm/include/asm/arch-npcm8xx/fiu.h
b/arch/arm/include/asm/arch-npcm8xx/fiu.h
new file mode 100644
index 00..22fc66dd9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/fiu.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#ifndef _NPCM_FIU_H_
+#define _NPCM_FIU_H_
+
+#define CHUNK_SIZE 16
+
+/* FIU UMA Configuration Register (FIU_UMA_CFG) */
+#define FIU_UMA_CFG_LCK 31
+#define FIU_UMA_CFG_CMMLCK 30
+#define FIU_UMA_CFG_RDATSIZ 24
+#define FIU_UMA_CFG_DBSIZ 21
+#define FIU_UMA_CFG_WDATSIZ 16
+#define FIU_UMA_CFG_ADDSIZ 11
+#define FIU_UMA_CFG_CMDSIZ 10
+#define FIU_UMA_CFG_RDBPCK 8
+#define FIU_UMA_CFG_DBPCK 6
+#define FIU_UMA_CFG_WDBPCK 4
+#define FIU_UMA_CFG_ADBPCK 2
+#define FIU_UMA_CFG_CMBPCK 0
+
+/* FIU UMA Control and Status Register (FIU_UMA_CTS) */
+#define FIU_UMA_CTS_SW_CS 16
+#define FIU_UMA_CTS_DEV_NUM8
+#define FIU_UMA_CTS_EXEC_DONE 0
+
+struct npcm_fiu_regs {
+ unsigned intdrd_cfg;
+ unsigned intdwr_cfg;
+ unsigned intuma_cfg;
+ unsigned intuma_cts;
+ unsigned intuma_cmd;
+ unsigned intuma_addr;
+ unsigned intprt_cfg;
+ unsigned char res1[4];
+ unsigned intuma_dw0;
+ unsigned intuma_dw1;
+ unsigned intuma_dw2;
+ unsigned intuma_dw3;
+ unsigned intuma_dr0;
+ unsigned intuma_dr1;
+ unsigned intuma_dr2;
+ unsigned intuma_dr3;
+ unsigned intprt_cmd0;
+ unsigned intprt_cmd1;
+ unsigned intprt_cmd2;
+ unsigned intprt_cmd3;
+ unsigned intprt_cmd4;
+ unsigned intprt_cmd5;
+ unsigned intprt_cmd6;
+ unsigned intprt_cmd7;
+ unsigned intprt_cmd8;
+ unsigned intprt_cmd9;
+ unsigned intstuff[4];
+ unsigned intfiu_cfg;
+};
+
+#endif
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d07e9a28af..a7b8f2fa1b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -474,6 +474,12 @@ config ZYNQMP_GQSPI
This option is used to enable ZynqMP QSPI controller driver which
is used to communicate with qspi flash devices.
+config NPCM_FIU_SPI
+ bool "FIU driver for Nuvoton NPCM SoC"
+ help
+ This enables support for the Flash Interface Unit SPI controller
+ in master mode.
+
endif # if DM_SPI
config FSL_ESPI
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d2f24bccef..4d1be1bb67 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o
+obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o
diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c
new file mode 100644
index 00..38b87cc4ac
--- /dev/null
+++ b/drivers/spi/npcm_fiu_spi.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct npcm_fiu_priv {
+ struct npcm_fiu_regs *regs;
+};
+
+static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed)
+{
+ return 0;
+}
+
+static int npcm_fiu_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static inline void activate_cs(struct npcm_fiu_regs *regs, int cs)
+{
+ writel((cs & 0x3) << FIU_UMA_CTS_DEV_NUM, ®s->uma_cts);
+}
+
+static inline void deactivate_cs(struct npcm_fiu_regs *regs)
+{
+ writel((1 << FIU_UMA_CTS_SW_CS), ®s->uma_cts);
+}
+
+static int fiu_uma_read(struct udevice *bus, u8 *buf, u32 data_size)
+{
+ struct npcm_fiu_priv *priv = dev_get_priv(bus);
+ struct npcm_fiu_regs *regs = priv->regs;
+ u32 data_reg[4];
+ u32 val;
+ int ret;
+
+ /* Set data size */
+ writel((data_size << FIU_UMA_CFG_RDATSIZ), ®s-
[PATCH v1 5/9] gpio: npcm: Add support for Nuvoton NPCM SoCs
Add Nuvoton BMC NPCM7xx/NPCM8xx gpio driver
Signed-off-by: Stanley Chu
---
drivers/gpio/Kconfig | 7 +++
drivers/gpio/Makefile| 1 +
drivers/gpio/npcm_gpio.c | 133 +++
3 files changed, 141 insertions(+)
create mode 100644 drivers/gpio/npcm_gpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 40abc33772..2aed8fdae3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -523,4 +523,11 @@ config NOMADIK_GPIO
into a number of banks each with 32 GPIOs. The GPIOs for a device are
defined in the device tree with one node for each bank.
+config NPCM_GPIO
+ bool "NuvoTon NPCM GPIO driver"
+ depends on DM_GPIO
+ help
+ Support GPIO controllers on NuvoTon NPCM SoCs.
+ It contains eight GPIO modules with total 256 pins.
+
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3c851b38c7..d0206580c4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -69,3 +69,4 @@ obj-$(CONFIG_NX_GPIO) += nx_gpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o
obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
+obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o
diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c
new file mode 100644
index 00..703d2e4815
--- /dev/null
+++ b/drivers/gpio/npcm_gpio.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define NPCM_GPIO_PORTS_PER_BANK32
+
+#define NPCM_GPIO_REG_DIN 0x04/* RO - Data In */
+#define NPCM_GPIO_REG_DOUT 0x0C/* RW - Data Out */
+#define NPCM_GPIO_REG_IEM 0x58/* RW - Input Enable Mask */
+#define NPCM_GPIO_REG_OE 0x10/* RW - Output Enable */
+#define NPCM_GPIO_REG_OES 0x70/* WO - Output Enable Register
Set */
+#define NPCM_GPIO_REG_OEC 0x74/* WO - Output Enable Register
Clear */
+
+struct npcm_gpio_priv {
+ void __iomem *base;
+};
+
+static void npcm_gpio_offset_write(struct udevice *dev, unsigned int offset,
+ unsigned int reg, int value)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+ u32 tmp;
+
+ tmp = readl(priv->base + reg);
+
+ if (value)
+ tmp |= BIT(offset);
+ else
+ tmp &= ~BIT(offset);
+
+ writel(tmp, priv->base + reg);
+}
+
+static int npcm_gpio_offset_read(struct udevice *dev, unsigned int offset,
+unsigned int reg)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+
+ return !!(readl(priv->base + reg) & BIT(offset));
+}
+
+static int npcm_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_OEC, 1);
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_IEM, 1);
+
+ return 0;
+}
+
+static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_IEM, 0);
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_OES, 1);
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_DOUT, value);
+
+ return 0;
+}
+
+static int npcm_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ if (npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_IEM))
+ return npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_DIN);
+
+ if (npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_OE))
+ return npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_DOUT);
+
+ return -EINVAL;
+}
+
+static int npcm_gpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_DOUT, value);
+
+ return 0;
+}
+
+static int npcm_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ if (npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_IEM))
+ return GPIOF_INPUT;
+
+ if (npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_OE))
+ return GPIOF_OUTPUT;
+
+ return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops npcm_gpio_ops = {
+ .direction_input= npcm_gpio_direction_input,
+ .direction_output = npcm_gpio_direction_output,
+ .get_value = npcm_gpio_get_value,
+ .set_value = npcm_gpio_set_value,
+ .get_function = npcm_gpio_get_function,
+};
+
+static int npcm_gpio_probe(struct udevice *dev)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev
[PATCH v1 4/9] serial: npcm: Add support for Nuvoton NPCM SoCs
Add Nuvoton BMC NPCM7xx/NPCM8xx uart driver
Signed-off-by: Stanley Chu
---
arch/arm/include/asm/arch-npcm8xx/uart.h | 82 ++
drivers/serial/Kconfig | 7 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_npcm.c | 137 +++
4 files changed, 227 insertions(+)
create mode 100644 arch/arm/include/asm/arch-npcm8xx/uart.h
create mode 100644 drivers/serial/serial_npcm.c
diff --git a/arch/arm/include/asm/arch-npcm8xx/uart.h
b/arch/arm/include/asm/arch-npcm8xx/uart.h
new file mode 100644
index 00..e3c86849f3
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/uart.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_UART_H_
+#define _NPCM_UART_H_
+
+struct npcm_uart {
+ union {
+ unsigned intrbr;
+ unsigned intthr;
+ unsigned intdll;
+ };
+ union {
+ unsigned intier;
+ unsigned intdlm;
+ };
+ union {
+ unsigned intiir;
+ unsigned intfcr;
+ };
+ unsigned intlcr;
+ unsigned intmcr;
+ unsigned intlsr;
+ unsigned intmsr;
+ unsigned inttor;
+};
+
+#defineIER_DBGACK BIT(4)
+#defineIER_MSIEBIT(3)
+#defineIER_RLSEBIT(2)
+#defineIER_THREIE BIT(1)
+#defineIER_RDAIE BIT(0)
+
+#defineIIR_FMESBIT(7)
+#defineIIR_RFTLS BIT(5)
+#defineIIR_DMS BIT(4)
+#defineIIR_IID BIT(1)
+#defineIIR_NIP BIT(0)
+
+#defineFCR_RFITL_1B(0 << 4)
+#defineFCR_RFITL_4B(4 << 4)
+#defineFCR_RFITL_8B(8 << 4)
+#defineFCR_RFITL_14B (12 << 4)
+#defineFCR_DMS BIT(3)
+#defineFCR_TFR BIT(2)
+#defineFCR_RFR BIT(1)
+#defineFCR_FME BIT(0)
+
+#defineLCR_DLABBIT(7)
+#defineLCR_BCB BIT(6)
+#defineLCR_SPE BIT(5)
+#defineLCR_EPS BIT(4)
+#defineLCR_PBE BIT(3)
+#defineLCR_NSB BIT(2)
+#defineLCR_WLS_8b 3
+#defineLCR_WLS_7b 2
+#defineLCR_WLS_6b 1
+#defineLCR_WLS_5b 0
+
+#defineMCR_LBMEBIT(4)
+#defineMCR_OUT2BIT(3)
+#defineMCR_RTS BIT(1)
+#defineMCR_DTR BIT(0)
+
+#defineLSR_ERR_RX BIT(7)
+#defineLSR_TE BIT(6)
+#defineLSR_THREBIT(5)
+#defineLSR_BII BIT(4)
+#defineLSR_FEI BIT(3)
+#defineLSR_PEI BIT(2)
+#defineLSR_OEI BIT(1)
+#defineLSR_RFDRBIT(0)
+
+#defineMSR_DCD BIT(7)
+#defineMSR_RI BIT(6)
+#defineMSR_DSR BIT(5)
+#defineMSR_CTS BIT(4)
+#defineMSR_DDCDBIT(3)
+#defineMSR_DRI BIT(2)
+#defineMSR_DDSRBIT(1)
+#defineMSR_DCTSBIT(0)
+
+#endif
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 6c8fdda9a0..3982bc9426 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -975,4 +975,11 @@ config SYS_SDMR
depends on MPC8XX_CONS
default 0
+config NPCM_SERIAL
+ bool "Nuvoton NPCM UART driver"
+ depends on DM_SERIAL
+ help
+ Select this to enable UART support for Nuvoton BMCs
+ (NPCM7xx and NPCM8xx)
+
endif
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8168af640f..1b86acf5cf 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o
obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
obj-$(CONFIG_XEN_SERIAL) += serial_xen.o
+obj-$(CONFIG_NPCM_SERIAL) += serial_npcm.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c
new file mode 100644
index 00..330c544e5a
--- /dev/null
+++ b/drivers/serial/serial_npcm.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct npcm_serial_plat {
+ struct npcm_uart *reg;
+ u32 uart_clk;
+};
+
+static int npcm_serial_init(struct npcm_uart *uart)
+{
+ u8 val;
+
+ /* Disable all UART interrupt */
+ writeb(0, &uart->ier);
+
+ /* Set port for 8 bit, 1 stop, no parity */
+ val = LCR_WLS_8b;
+ writeb(val, &uart->lcr);
+
+ /* Set the RX FIFO trigger level, reset RX, TX FIFO */
+ val = FCR_FME | FCR_RFR | FCR_TFR | FCR_RFITL_4B;
+ writeb(val, &uart->fcr);
+
+ return
[PATCH v1 3/9] timer: npcm: Add NPCM timer support
Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver.
Signed-off-by: Stanley Chu
---
drivers/timer/Kconfig | 7
drivers/timer/Makefile | 1 +
drivers/timer/npcm_timer.c | 82 ++
3 files changed, 90 insertions(+)
create mode 100644 drivers/timer/npcm_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 8913142654..c17bc5b8b9 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -234,4 +234,11 @@ config IMX_GPT_TIMER
Select this to enable support for the timer found on
NXP i.MX devices.
+config NPCM_TIMER
+ bool "Nuvoton NPCM timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ Nuvoton NPCM devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index e2bd530eb0..d6f04f1cf4 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
obj-$(CONFIG_MCHP_PIT64B_TIMER)+= mchp-pit64b-timer.o
obj-$(CONFIG_IMX_GPT_TIMER)+= imx-gpt-timer.o
+obj-$(CONFIG_NPCM_TIMER) += npcm_timer.o
diff --git a/drivers/timer/npcm_timer.c b/drivers/timer/npcm_timer.c
new file mode 100644
index 00..499c1003ff
--- /dev/null
+++ b/drivers/timer/npcm_timer.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology.
+ */
+
+#include
+#include
+#include
+#include
+
+#define NPCM_CLOCK_RATE100
+#define NPCM_TIMER_INIT_VAL0x
+
+/* Register offsets */
+#define TCR0 0x0
+#define TICR0 0x8
+#define TDR0 0x10
+
+/* TCR fields */
+#define TCR_MODE_PERIODIC BIT(27)
+#define TCR_EN BIT(30)
+#define TCR_PRESCALE_25(25 - 1)
+
+struct npcm_timer_priv {
+ void __iomem *base;
+};
+
+static u64 npcm_timer_get_count(struct udevice *dev)
+{
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = NPCM_TIMER_INIT_VAL - readl(priv->base + TDR0);
+
+ return timer_conv_64(val);
+}
+
+static int npcm_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+ uc_priv->clock_rate = NPCM_CLOCK_RATE;
+
+ writel(0, priv->base + TCR0);
+ writel(NPCM_TIMER_INIT_VAL, priv->base + TICR0);
+
+ /*
+* Configure timer and start
+* periodic mode
+* input clock freq = 25Mhz
+* prescale = 25
+* clock rate = 25Mhz/25 = 1Mhz
+*/
+ writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE_25,
+ priv->base + TCR0);
+
+ return 0;
+}
+
+static const struct timer_ops npcm_timer_ops = {
+ .get_count = npcm_timer_get_count,
+};
+
+static const struct udevice_id npcm_timer_ids[] = {
+ { .compatible = "nuvoton,npcm845-timer" },
+ { .compatible = "nuvoton,npcm750-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(npcm_timer) = {
+ .name = "npcm_timer",
+ .id = UCLASS_TIMER,
+ .of_match = npcm_timer_ids,
+ .priv_auto = sizeof(struct npcm_timer_priv),
+ .probe = npcm_timer_probe,
+ .ops= &npcm_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.17.1
[PATCH v1 2/9] clk: nuvoton: Add support for NPCM845
Add clock controller driver for NPCM845
Signed-off-by: Stanley Chu
---
drivers/clk/Makefile | 1 +
drivers/clk/nuvoton/Makefile | 1 +
drivers/clk/nuvoton/clk_npcm8xx.c | 213 ++
include/dt-bindings/clock/npcm845-clock.h | 17 ++
4 files changed, 232 insertions(+)
create mode 100644 drivers/clk/nuvoton/Makefile
create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c
create mode 100644 include/dt-bindings/clock/npcm845-clock.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 711ae5bc29..a3b64b73c2 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_STM32H7) += clk_stm32h7.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile
new file mode 100644
index 00..998e5329bb
--- /dev/null
+++ b/drivers/clk/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_NPCM8XX) += clk_npcm8xx.o
diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c
b/drivers/clk/nuvoton/clk_npcm8xx.c
new file mode 100644
index 00..c547c47e82
--- /dev/null
+++ b/drivers/clk/nuvoton/clk_npcm8xx.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct npcm_clk_priv {
+ struct clk_ctl *regs;
+};
+
+enum regss {
+ PLL_0,
+ PLL_1,
+ PLL_2,
+ PLL_CLKREF,
+};
+
+static u32 clk_get_pll_freq(struct clk_ctl *regs, enum regss pll)
+{
+ u32 pllval;
+ u32 fin = EXT_CLOCK_FREQUENCY_KHZ; /* 25KHz */
+ u32 fout, nr, nf, no;
+
+ switch (pll) {
+ case PLL_0:
+ pllval = readl(®s->pllcon0);
+ break;
+ case PLL_1:
+ pllval = readl(®s->pllcon1);
+ break;
+ case PLL_2:
+ pllval = readl(®s->pllcon2);
+ break;
+ case PLL_CLKREF:
+ default:
+ return 0;
+ }
+
+ /* PLL Input Clock Divider */
+ nr = (pllval >> PLLCON_INDV) & 0x1f;
+ /* PLL VCO Output Clock Feedback Divider */
+ nf = (pllval >> PLLCON_FBDV) & 0xfff;
+ /* PLL Output Clock Divider 1 */
+ no = ((pllval >> PLLCON_OTDV1) & 0x7) *
+ ((pllval >> PLLCON_OTDV2) & 0x7);
+
+ fout = ((10 * fin * nf) / (no * nr));
+
+ return fout * 100;
+}
+
+static u32 npcm_mmc_set_rate(struct clk_ctl *regs, ulong rate)
+{
+ u32 pll0_freq, div, sdhci_clk;
+
+ /* To acquire PLL0 frequency. */
+ pll0_freq = clk_get_pll_freq(regs, PLL_0);
+
+ /* Calculate rounded up div to produce closest to
+* target output clock
+*/
+ div = (pll0_freq % rate == 0) ? (pll0_freq / rate) :
+ (pll0_freq / rate) + 1;
+
+ writel((readl(®s->clkdiv1) & ~(0x1f << CLKDIV1_MMCCKDIV))
+ | (div - 1) << CLKDIV1_MMCCKDIV, ®s->clkdiv1);
+
+ /* Wait to the div to stabilize */
+ udelay(100);
+
+ /* Select PLL0 as source */
+ writel((readl(®s->clksel) & ~(0x3 << CLKSEL_SDCKSEL))
+ | (CLKSEL_SDCKSEL_PLL0 << CLKSEL_SDCKSEL),
+ ®s->clksel);
+
+ sdhci_clk = pll0_freq / div;
+
+ return sdhci_clk;
+}
+
+static u32 npcm_uart_set_rate(struct clk_ctl *regs, ulong rate)
+{
+ u32 src_freq, div;
+
+ src_freq = clk_get_pll_freq(regs, PLL_2) / 2;
+ div = (src_freq % rate == 0) ? (src_freq / rate) :
+ (src_freq / rate) + 1;
+ writel((readl(®s->clkdiv1) & ~(0x1f << CLKDIV1_UARTDIV))
+ | (div - 1) << CLKDIV1_UARTDIV, ®s->clkdiv1);
+ writel((readl(®s->clksel) & ~(3 << CLKSEL_UARTCKSEL))
+ | (CLKSEL_UARTCKSEL_PLL2 << CLKSEL_UARTCKSEL),
+ ®s->clksel);
+
+ return (src_freq / div);
+}
+
+static ulong npcm_get_cpu_freq(struct clk_ctl *regs)
+{
+ ulong fout = 0;
+ u32 clksel = readl(®s->clksel) & (0x3 << CLKSEL_CPUCKSEL);
+
+ if (clksel == CLKSEL_CPUCKSEL_PLL0)
+ fout = (ulong)clk_get_pll_freq(regs, PLL_0);
+ else if (clksel == CLKSEL_CPUCKSEL_PLL1)
+ fout = (ulong)clk_get_pll_freq(regs, PLL_1);
+ else if (clksel == CLKSEL_CPUCKSEL_CLKREF)
+ fout = EXT_CLOCK_FREQUENCY_MHZ; /* FOUT is specified in MHz */
+ else
+ fout = EXT_CLOCK_FREQUENCY_MHZ; /* FOUT is specified in MHz */
+
+ return fout;
+}
+
+static u32 npcm_get_apb_divisor(struct clk_ctl *regs, u32 apb)
+{
+ u32 apb_divisor = 2;
+
+ /* AHBn div */
+ apb_divisor = apb_divisor * (1 &
[PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Add basic support for the Nuvoton NPCM845 BMC.
Signed-off-by: Stanley Chu
---
arch/arm/Kconfig | 9 +
arch/arm/Makefile | 1 +
arch/arm/include/asm/arch-npcm8xx/clock.h | 164
arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++
arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
arch/arm/mach-nuvoton/Kconfig | 24 ++
arch/arm/mach-nuvoton/Makefile| 1 +
arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
arch/arm/mach-nuvoton/npcm8xx/Makefile| 1 +
arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170
arch/arm/mach-nuvoton/npcm8xx/reset.c | 51
board/nuvoton/arbel/Kconfig | 18 ++
board/nuvoton/arbel/Makefile | 1 +
board/nuvoton/arbel/arbel.c | 33 +++
include/configs/arbel.h | 54
17 files changed, 924 insertions(+)
create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h
create mode 100644 arch/arm/mach-nuvoton/Kconfig
create mode 100644 arch/arm/mach-nuvoton/Makefile
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c
create mode 100644 board/nuvoton/arbel/Kconfig
create mode 100644 board/nuvoton/arbel/Makefile
create mode 100644 board/nuvoton/arbel/arbel.c
create mode 100644 include/configs/arbel.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f7f03837fe..80ec42f6be 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64
select LINUX_KERNEL_IMAGE_HEADER
select XEN_SERIAL
select SSCANF
+
+config ARCH_NPCM
+ bool "Support Nuvoton SoCs"
+ select DM
+ select OF_CONTROL
+ imply CMD_DM
+
endchoice
config SUPPORT_PASSING_ATAGS
@@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-nexell/Kconfig"
+source "arch/arm/mach-nuvoton/Kconfig"
+
source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ad757e982e..29a0250ab6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQ)+= zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
+machine-$(CONFIG_ARCH_NPCM)+= nuvoton
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h
b/arch/arm/include/asm/arch-npcm8xx/clock.h
new file mode 100644
index 00..088b536b7b
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/clock.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#ifndef _NPCM_CLOCK_H_
+#define _NPCM_CLOCK_H_
+
+#define NPCM_CLK_BA0xF0801000
+enum {
+ APB1 = 1,
+ APB2 = 2,
+ APB3 = 3,
+ APB4 = 4,
+ APB5 = 5,
+ SPI0 = 10,
+ SPI1 = 11,
+ SPI3 = 13,
+ SPIX = 14,
+};
+
+/* Clock Select Register (CLKSEL) */
+#define CLKSEL_RCPCKSEL 27
+#define CLKSEL_RGSEL25
+#define CLKSEL_GFXMSEL 21
+#define CLKSEL_CLKOUTSEL18
+#define CLKSEL_PCICKSEL 16
+#define CLKSEL_ADCCKSEL 14
+#define CLKSEL_MCCKSEL 12
+#define CLKSEL_SUCKSEL 10
+#define CLKSEL_UARTCKSEL8
+#define CLKSEL_SDCKSEL 6
+#define CLKSEL_PIXCKSEL 4
+#define CLKSEL_CPUCKSEL 0
+
+/* Clock Divider Control Register 1 (CLKDIV1) */
+#define CLKDIV1_ADCCKDIV28
+#define CLKDIV1_CLK4DIV 26
+#define CLKDIV1_PRE_ADCCKDIV21
+#define CLKDIV1_UARTDIV 16
+#define CLKDIV1_MMCCKDIV11
+#define CLKDIV1_SPI3CKDIV 6
+#define CLKDIV1_PCICKDIV2
+
+/* Clock Divider Control Register 2 (CLKDIV2) */
+#define CLKDIV2_APB4CKDIV 30
+#define CLKDIV2_APB3CKDIV 28
+#define CLKDIV2_APB2CKDIV 26
+#define CLKDIV2_APB1CKDIV 24
+#define CLKDIV2_APB5CKDIV 22
+#define CLKDIV2_CLKOUTDIV 16
+#define CLKDIV2_GFXCKDIV13
+#define CLKDIV2_SUCKDIV 8
+#define CLKDIV2_SU48CKDIV 4
+
+/* PLL Control Register 2 (PLLCON2) */
+#define PLLCON_LOKI31
[PATCH v1 0/9] Add Nuvoton NPCM845 support
The patch series add basic supoorts for NPCM845, which is Nuvoton's 4th-generation BMC (Baseboard Management Controller). Add drivers to support Clock,Timer,Uart,GPIO, Pinctrl, SPI Flash Access for NPCM8xx SoC. Stanley Chu (9): arm: nuvoton: Add support for Nuvoton NPCM845 BMC clk: nuvoton: Add support for NPCM845 timer: npcm: Add NPCM timer support serial: npcm: Add support for Nuvoton NPCM SoCs gpio: npcm: Add support for Nuvoton NPCM SoCs pinctrl: nuvoton: Add NPCM8xx pinctrl driver spi: npcm-fiu: add NPCM8xx FIU controller driver ARM: dts: Add Nuvoton NPCM845 device tree ARM: configs: Add defconfig for Nuvoton NPCM845 arch/arm/Kconfig |9 + arch/arm/Makefile |1 + arch/arm/dts/Makefile |2 + arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 598 ++ arch/arm/dts/nuvoton-npcm845-evb.dts | 264 +++ arch/arm/dts/nuvoton-npcm845-pincfg.dtsi | 2007 arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi | 623 +++ arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++ arch/arm/include/asm/arch-npcm8xx/espi.h | 23 + arch/arm/include/asm/arch-npcm8xx/fiu.h | 61 + arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 + arch/arm/include/asm/arch-npcm8xx/rst.h | 32 + arch/arm/include/asm/arch-npcm8xx/uart.h | 82 + arch/arm/mach-nuvoton/Kconfig | 24 + arch/arm/mach-nuvoton/Makefile|1 + arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 + arch/arm/mach-nuvoton/npcm8xx/Makefile|1 + arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++ arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 + board/nuvoton/arbel/Kconfig | 18 + board/nuvoton/arbel/MAINTAINERS |7 + board/nuvoton/arbel/Makefile |1 + board/nuvoton/arbel/arbel.c | 33 + configs/arbel_evb_defconfig | 77 + drivers/clk/Makefile |1 + drivers/clk/nuvoton/Makefile |1 + drivers/clk/nuvoton/clk_npcm8xx.c | 213 +++ drivers/gpio/Kconfig |7 + drivers/gpio/Makefile |1 + drivers/gpio/npcm_gpio.c | 133 ++ drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig |6 + drivers/pinctrl/nuvoton/Makefile |1 + drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2042 + drivers/serial/Kconfig|7 + drivers/serial/Makefile |1 + drivers/serial/serial_npcm.c | 137 ++ drivers/spi/Kconfig |6 + drivers/spi/Makefile |1 + drivers/spi/npcm_fiu_spi.c| 311 drivers/timer/Kconfig |7 + drivers/timer/Makefile|1 + drivers/timer/npcm_timer.c| 82 + include/configs/arbel.h | 54 + include/dt-bindings/clock/npcm845-clock.h | 17 + 47 files changed, 7622 insertions(+) create mode 100644 arch/arm/dts/nuvoton-common-npcm8xx.dtsi create mode 100644 arch/arm/dts/nuvoton-npcm845-evb.dts create mode 100644 arch/arm/dts/nuvoton-npcm845-pincfg.dtsi create mode 100644 arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/fiu.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/uart.h create mode 100644 arch/arm/mach-nuvoton/Kconfig create mode 100644 arch/arm/mach-nuvoton/Makefile create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c create mode 100644 board/nuvoton/arbel/Kconfig create mode 100644 board/nuvoton/arbel/MAINTAINERS create mode 100644 board/nuvoton/arbel/Makefile create mode 100644 board/nuvoton/arbel/arbel.c create mode 100644 configs/arbel_evb_defconfig create mode 100644 drivers/clk/nuvoton/Makefile create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c create mode 100644 drivers/gpio/npcm_gpio.c create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c create mode 100644 drivers/serial/serial_npcm.c create mode 100644 drivers/spi/npcm_fiu_spi.c create mode 100644 drivers/timer/npcm_timer.c create mode 100644 include/configs/arbel.h create mode 100644 include/dt-bindings/clock/np
